732 lines
27 KiB
C
732 lines
27 KiB
C
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/////////////////////////////////////////////////////////////////////////////
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//
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// r3000 - Emulates R3000 CPU
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//
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/////////////////////////////////////////////////////////////////////////////
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#ifndef EMU_COMPILE
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#error "Hi I forgot to set EMU_COMPILE"
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#endif
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#include "r3000.h"
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/////////////////////////////////////////////////////////////////////////////
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/*
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** integer overflow exceptions are not taken!
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** divide by zero exceptions are not taken!
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*/
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/////////////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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/*
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** Divider is now hardcoded
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*/
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#define DIVIDER (1)
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/////////////////////////////////////////////////////////////////////////////
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/*
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** Static information
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*/
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/* (none) */
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sint32 EMU_CALL r3000_init(void) {
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return 0;
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}
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/////////////////////////////////////////////////////////////////////////////
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/*
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** State information
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*/
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#define STATE ((struct R3000_STATE*)(state))
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#define C0_status (12)
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#define C0_cause (13)
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#define C0_epc (14)
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#define C0_prid (15)
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struct R3000_STATE {
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uint32 regs[32];
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uint32 c0_status;
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uint32 c0_cause;
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uint32 c0_epc;
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uint32 c0_prid;
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uint32 pc;
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uint32 hi,lo;
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uint32 intpending;
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sint32 slot;
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uint32 slot_target;
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sint32 cycles_remaining;
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sint32 cycles_remaining_last_checkpoint;
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sint32 cycles_deferred_from_break;
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/* usage statistics */
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sint32 usage_total_cycles;
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sint32 usage_idle_cycles;
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sint32 usage_cycles_max;
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uint32 usage_last_fraction;
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uint32 cache_ctrl;
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uint32 cache_isolate;
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//
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// These are REGISTERED EXTERNAL POINTERS.
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//
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r3000_advance_callback_t advance;
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void *hwstate;
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struct R3000_MEMORY_MAP *map_load;
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struct R3000_MEMORY_MAP *map_store;
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//
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// The following are TEMPORARY.
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// There are no location invariance issues.
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//
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uint32 maxpc;
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void *fetchbase;
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uint32 fetchbox;
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};
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uint32 EMU_CALL r3000_get_state_size(void) {
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return sizeof(struct R3000_STATE);
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}
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void EMU_CALL r3000_clear_state(void *state) {
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memset(state, 0, sizeof(struct R3000_STATE));
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STATE->c0_prid = 0x02;
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STATE->pc = 0xBFC00000;
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/* update statistics every 20 million cycles (may overshoot a little) */
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STATE->usage_cycles_max = 20000000;
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}
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/////////////////////////////////////////////////////////////////////////////
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/*
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** Registration of external pointers within the state
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*/
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void EMU_CALL r3000_set_memory_maps(
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void *state,
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struct R3000_MEMORY_MAP *map_load,
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struct R3000_MEMORY_MAP *map_store
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) {
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STATE->map_load = map_load;
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STATE->map_store = map_store;
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}
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void EMU_CALL r3000_set_advance_callback(
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void *state,
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r3000_advance_callback_t advance,
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void *hwstate
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) {
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STATE->advance = advance;
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STATE->hwstate = hwstate;
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}
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/////////////////////////////////////////////////////////////////////////////
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/*
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** Set the processor revision ID
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*/
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void EMU_CALL r3000_set_prid(void *state, uint32 prid) {
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STATE->c0_prid = prid;
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}
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/////////////////////////////////////////////////////////////////////////////
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static EMU_INLINE uint32 EMU_CALL getc0(struct R3000_STATE *state, uint32 regnum) {
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switch(regnum) {
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case 12: return state->c0_status;
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case 13: return state->c0_cause;
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case 14: return state->c0_epc;
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case 15: return state->c0_prid;
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}
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return 0;
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}
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static EMU_INLINE void EMU_CALL setc0(struct R3000_STATE *state, uint32 regnum, uint32 value) {
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switch(regnum) {
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case 12: state->c0_status = value; break;
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case 13: state->c0_cause = value; break;
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case 14: state->c0_epc = value; break;
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case 15: break;
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}
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}
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/////////////////////////////////////////////////////////////////////////////
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uint32 EMU_CALL r3000_getreg(void *state, sint32 regnum) {
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if(regnum >= R3000_REG_GEN && regnum < (R3000_REG_GEN+32)) { return STATE->regs[regnum - R3000_REG_GEN]; }
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if(regnum >= R3000_REG_C0 && regnum < (R3000_REG_C0+32)) { return getc0(STATE, regnum - R3000_REG_C0); }
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switch(regnum) {
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case R3000_REG_PC: return STATE->pc;
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case R3000_REG_HI: return STATE->hi;
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case R3000_REG_LO: return STATE->lo;
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case R3000_REG_CI: return STATE->cache_isolate;
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}
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return 0;
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}
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void EMU_CALL r3000_setreg(void *state, sint32 regnum, uint32 value) {
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if(regnum >= R3000_REG_GEN && regnum < (R3000_REG_GEN+32)) { STATE->regs[regnum - R3000_REG_GEN] = value; return; }
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if(regnum >= R3000_REG_C0 && regnum < (R3000_REG_C0+32)) { setc0(STATE, regnum - R3000_REG_C0, value); return; }
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switch(regnum) {
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case R3000_REG_PC: STATE->pc = value; return;
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case R3000_REG_HI: STATE->hi = value; return;
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case R3000_REG_LO: STATE->lo = value; return;
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case R3000_REG_CI: STATE->cache_isolate = value; return;
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}
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}
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/////////////////////////////////////////////////////////////////////////////
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void EMU_CALL r3000_break(void *state) {
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if(STATE->cycles_remaining <= 0) return;
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STATE->cycles_deferred_from_break += STATE->cycles_remaining;
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STATE->cycles_remaining_last_checkpoint -= STATE->cycles_remaining;
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STATE->cycles_remaining = 0;
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}
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void EMU_CALL r3000_setinterrupt(void *state, uint32 intpending) {
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STATE->intpending = intpending;
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r3000_break(state);
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}
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/////////////////////////////////////////////////////////////////////////////
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/*
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** Memory map walker
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*/
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static EMU_INLINE struct R3000_MEMORY_TYPE* EMU_CALL mmwalk(struct R3000_MEMORY_MAP *map, uint32 a) {
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a &= 0x1FFFFFFF;
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for(;; map++) {
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uint32 x = map->x;
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uint32 y = map->y;
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if(a < x || a > y) continue;
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return &(map->type);
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}
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}
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/////////////////////////////////////////////////////////////////////////////
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static EMU_INLINE void EMU_CALL exception(struct R3000_STATE *state, uint32 cause, uint32 IP) {
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/* Step out of the delay slot, if we were in one */
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if(state->slot) {
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// state->pc = state->slot_target & (~3);
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state->pc -= 4;
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state->slot = 0;
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}
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/* Shift mode/interrupt bits */
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state->c0_status =
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(state->c0_status & 0xFFFFFFC0) |
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((state->c0_status & 0x0F) << 2);
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state->c0_epc = state->pc;
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state->c0_cause = ((cause & 0xF) << 2) | ((IP & 0x3F) << 10);
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/* ignore BEV for now */
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state->pc = 0x80000080;
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/* Force a recheck of the memory map */
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state->maxpc = 0;
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//printf("exception %08X %08X\n",cause,IP);
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}
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/////////////////////////////////////////////////////////////////////////////
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static EMU_INLINE void EMU_CALL update_usage(void *state) {
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/*
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** Update usage statistics
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*/
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if(STATE->usage_total_cycles >= STATE->usage_cycles_max) {
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sint64 fraction;
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/*
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** Bounds checking
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*/
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if(STATE->usage_total_cycles <= 0) { STATE->usage_total_cycles = 1; }
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if(STATE->usage_idle_cycles > STATE->usage_total_cycles) {
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STATE->usage_idle_cycles = STATE->usage_total_cycles;
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} else if(STATE->usage_idle_cycles < 0) {
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STATE->usage_idle_cycles = 0;
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}
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fraction = STATE->usage_total_cycles - STATE->usage_idle_cycles;
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fraction *= ((sint64)(0x20000));
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fraction /= ((sint64)(STATE->usage_total_cycles));
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fraction++;
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fraction /= 2;
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if(fraction < 0x00000) fraction = 0x00000;
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if(fraction > 0x10000) fraction = 0x10000;
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STATE->usage_last_fraction = (uint32)fraction;
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STATE->usage_total_cycles = 0;
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STATE->usage_idle_cycles = 0;
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}
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}
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/////////////////////////////////////////////////////////////////////////////
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#define INS_S ((uint32)((instruction>>21)&0x1F))
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#define INS_T ((uint32)((instruction>>16)&0x1F))
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#define INS_D ((uint32)((instruction>>11)&0x1F))
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#define INS_H ((uint32)((instruction>>6)&0x1F))
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#define INS_I ((uint32)(instruction&0xFFFF))
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#define SIGNED16(x) ((sint32)(((sint16)(x))))
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#define UNSIGNED16(x) ((uint32)(((uint16)(x))))
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#define REL_I (PC+4+(((sint32)(SIGNED16(INS_I)))<<2))
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#define ABS_I ((PC&0xF0000000)|((instruction<<2)&0x0FFFFFFC))
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#define J_REL_I {STATE->slot=2;STATE->slot_target=REL_I;}
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#define J_ABS_I {STATE->slot=2;STATE->slot_target=ABS_I;}
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#define REGS (STATE->regs)
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#define HI (STATE->hi)
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#define LO (STATE->lo)
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#define PC (STATE->pc)
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static EMU_INLINE void EMU_CALL cold_interrupt_check(struct R3000_STATE *state) {
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uint32 hotint = ((STATE->intpending) & (STATE->c0_status >> 8)) & 0x3F;
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if(!(STATE->c0_status & 1)) hotint = 0;
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if(hotint) { exception(STATE, 0, hotint); state->cycles_remaining -= DIVIDER; }
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}
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static EMU_INLINE void EMU_CALL hw_sync(struct R3000_STATE *state) {
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sint32 d = state->cycles_remaining_last_checkpoint - state->cycles_remaining;
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if(d > 0) {
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state->advance(state->hwstate, d);
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state->cycles_remaining_last_checkpoint = state->cycles_remaining;
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}
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}
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static EMU_INLINE void EMU_CALL renew_fetch_region(struct R3000_STATE *state) {
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struct R3000_MEMORY_TYPE *t = mmwalk(state->map_load, state->pc);
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if(t->n == R3000_MAP_TYPE_POINTER) {
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uint32 astart = (state->pc) & (~(t->mask));
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state->maxpc = astart + ((t->mask) + 1);
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state->fetchbase = ((uint8*)(t->p)) - astart;
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} else {
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state->maxpc = state->pc + 4;
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state->fetchbase = ((uint8*)(&(state->fetchbox)))-(state->pc);
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state->fetchbox = ((r3000_load_callback_t)(t->p))(state->hwstate, state->pc, 0xFFFFFFFF);
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}
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}
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static EMU_INLINE uint32 EMU_CALL lb(struct R3000_STATE *state, uint32 a) {
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struct R3000_MEMORY_TYPE *t = mmwalk(state->map_load, a);
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a &= t->mask;
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if(t->n == R3000_MAP_TYPE_POINTER) {
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a ^= EMU_ENDIAN_XOR(3);
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return *((uint8*)(((uint8*)(t->p))+a));
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} else {
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uint32 sh = (a & 3) * 8;
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hw_sync(state);
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a = ((r3000_load_callback_t)(t->p))(state->hwstate, a & (~3), 0xFF << sh);
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a >>= sh;
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return a & 0xFF;
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}
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}
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static EMU_INLINE uint32 EMU_CALL lh(struct R3000_STATE *state, uint32 a) {
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struct R3000_MEMORY_TYPE *t = mmwalk(state->map_load, a);
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a &= t->mask;
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if(t->n == R3000_MAP_TYPE_POINTER) {
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a ^= EMU_ENDIAN_XOR(2);
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a &= (~1);
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return *((uint16*)(((uint8*)(t->p))+a));
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} else {
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uint32 sh = (a & 2) * 8;
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hw_sync(state);
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a = ((r3000_load_callback_t)(t->p))(state->hwstate, a & (~3), 0xFFFF << sh);
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a >>= sh;
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return a & 0xFFFF;
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}
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}
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static EMU_INLINE uint32 EMU_CALL lw(struct R3000_STATE *state, uint32 a) {
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struct R3000_MEMORY_TYPE *t;
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/*
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** HACK HACK HACK TODO fix later
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*/
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if(a == 0xFFFE0130) {
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return state->cache_ctrl;
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}
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t = mmwalk(state->map_load, a);
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a &= t->mask;
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if(t->n == R3000_MAP_TYPE_POINTER) {
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a &= (~3);
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return *((uint32*)(((uint8*)(t->p))+a));
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} else {
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hw_sync(state);
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|
|
a = ((r3000_load_callback_t)(t->p))(state->hwstate, a & (~3), 0xFFFFFFFF);
|
||
|
|
return a;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
//
|
||
|
|
// Performs no callbacks; suitable for prediction
|
||
|
|
//
|
||
|
|
static EMU_INLINE uint32 EMU_CALL lw_noeffects(struct R3000_STATE *state, uint32 a) {
|
||
|
|
struct R3000_MEMORY_TYPE *t;
|
||
|
|
t = mmwalk(state->map_load, a);
|
||
|
|
a &= t->mask;
|
||
|
|
if(t->n == R3000_MAP_TYPE_POINTER) {
|
||
|
|
a &= (~3);
|
||
|
|
return *((uint32*)(((uint8*)(t->p))+a));
|
||
|
|
} else {
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static EMU_INLINE void EMU_CALL sb(struct R3000_STATE *state, uint32 a, uint32 d) {
|
||
|
|
struct R3000_MEMORY_TYPE *t = mmwalk(state->map_store, a);
|
||
|
|
a &= t->mask;
|
||
|
|
if(t->n == R3000_MAP_TYPE_POINTER) {
|
||
|
|
a ^= EMU_ENDIAN_XOR(3);
|
||
|
|
*((uint8*)(((uint8*)(t->p))+a)) = d;
|
||
|
|
} else {
|
||
|
|
uint32 sh = (a & 3) * 8;
|
||
|
|
hw_sync(state);
|
||
|
|
d &= 0xFF;
|
||
|
|
((r3000_store_callback_t)(t->p))(state->hwstate, a & (~3), d << sh, 0xFF << sh);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static EMU_INLINE void EMU_CALL sh(struct R3000_STATE *state, uint32 a, uint32 d) {
|
||
|
|
struct R3000_MEMORY_TYPE *t = mmwalk(state->map_store, a);
|
||
|
|
a &= t->mask;
|
||
|
|
if(t->n == R3000_MAP_TYPE_POINTER) {
|
||
|
|
a ^= EMU_ENDIAN_XOR(2);
|
||
|
|
a &= (~1);
|
||
|
|
*((uint16*)(((uint8*)(t->p))+a)) = d;
|
||
|
|
} else {
|
||
|
|
uint32 sh = (a & 2) * 8;
|
||
|
|
hw_sync(state);
|
||
|
|
d &= 0xFFFF;
|
||
|
|
((r3000_store_callback_t)(t->p))(state->hwstate, a & (~3), d << sh, 0xFFFF << sh);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static EMU_INLINE void EMU_CALL sw(struct R3000_STATE *state, uint32 a, uint32 d) {
|
||
|
|
struct R3000_MEMORY_TYPE *t;
|
||
|
|
/*
|
||
|
|
** HACK HACK HACK TODO fix later
|
||
|
|
*/
|
||
|
|
if(a == 0xFFFE0130) {
|
||
|
|
state->cache_ctrl = d;
|
||
|
|
if(d >= 0x10000) {
|
||
|
|
state->cache_isolate = 0;
|
||
|
|
} else {
|
||
|
|
state->cache_isolate = 1;
|
||
|
|
}
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
if(state->cache_isolate) return;
|
||
|
|
|
||
|
|
t = mmwalk(state->map_store, a);
|
||
|
|
a &= t->mask;
|
||
|
|
a &= (~3);
|
||
|
|
if(t->n == R3000_MAP_TYPE_POINTER) {
|
||
|
|
*((uint32*)(((uint8*)(t->p))+a)) = d;
|
||
|
|
} else {
|
||
|
|
hw_sync(state);
|
||
|
|
((r3000_store_callback_t)(t->p))(state->hwstate, a & (~3), d, 0xFFFFFFFF);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static EMU_INLINE uint32 EMU_CALL fetch(struct R3000_STATE *state) {
|
||
|
|
if(state->pc >= state->maxpc) renew_fetch_region(state);
|
||
|
|
return *((uint32*)(((uint8*)(state->fetchbase))+(state->pc)));
|
||
|
|
}
|
||
|
|
|
||
|
|
#define caseMINOR(a) case(a):
|
||
|
|
#define caseMAJOR(a) case(a):
|
||
|
|
|
||
|
|
//
|
||
|
|
// Returns 0 or positive on success
|
||
|
|
// Returns negative on error
|
||
|
|
// (value is otherwise meaningless for now)
|
||
|
|
//
|
||
|
|
sint32 EMU_CALL r3000_execute(void *state, sint32 cycles) {
|
||
|
|
uint32 a, d;
|
||
|
|
uint32 instruction;
|
||
|
|
|
||
|
|
STATE->cycles_remaining_last_checkpoint = cycles;
|
||
|
|
STATE->cycles_remaining = cycles;
|
||
|
|
STATE->cycles_deferred_from_break = 0;
|
||
|
|
|
||
|
|
STATE->usage_total_cycles += cycles;
|
||
|
|
|
||
|
|
PC &= (~3);
|
||
|
|
|
||
|
|
cold_interrupt_check(STATE);
|
||
|
|
|
||
|
|
//
|
||
|
|
// This guarantees location invariance on fetchbox/fetchbase
|
||
|
|
//
|
||
|
|
STATE->maxpc = 0;
|
||
|
|
|
||
|
|
while(STATE->slot || STATE->cycles_remaining > 0) {
|
||
|
|
instruction = fetch(state);
|
||
|
|
if(instruction < 0x04000000) {
|
||
|
|
switch(instruction & 0x3F) {
|
||
|
|
/* MINOR */
|
||
|
|
caseMINOR(0x00) /* sll */ if(INS_D) { REGS[INS_D] = ((uint32)(REGS[INS_T])) << INS_H;
|
||
|
|
} else {
|
||
|
|
/* idle detect */
|
||
|
|
/* if this is a nop in a branch delay slot, and the target is the
|
||
|
|
** previous instruction, then we are officially idle */
|
||
|
|
if((STATE->slot) && (STATE->slot_target == (PC - 4))) {
|
||
|
|
/* steal off cycles under cycidle */
|
||
|
|
sint32 cycidle = STATE->cycles_remaining;
|
||
|
|
if(cycidle < 0) { cycidle = 0; }
|
||
|
|
STATE->cycles_remaining -= cycidle;
|
||
|
|
STATE->usage_idle_cycles += cycidle;
|
||
|
|
|
||
|
|
STATE->slot = 0;
|
||
|
|
PC -= 4;
|
||
|
|
STATE->maxpc = 0;
|
||
|
|
goto finishing_sync;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
caseMINOR(0x02) /* srl */ if(INS_D) { REGS[INS_D] = ((uint32)(REGS[INS_T])) >> INS_H; } break;
|
||
|
|
caseMINOR(0x03) /* sra */ if(INS_D) { REGS[INS_D] = ((sint32)(REGS[INS_T])) >> INS_H; } break;
|
||
|
|
caseMINOR(0x04) /* sllv */ if(INS_D) { uint32 sc=REGS[INS_S]; if(sc>=32){REGS[INS_D]=0;}else{REGS[INS_D]=REGS[INS_T]<<sc;} } break;
|
||
|
|
caseMINOR(0x06) /* srlv */ if(INS_D) { uint32 sc=REGS[INS_S]; if(sc>=32){REGS[INS_D]=0;}else{REGS[INS_D]=REGS[INS_T]>>sc;} } break;
|
||
|
|
caseMINOR(0x07) /* srav */ if(INS_D) { uint32 sc=REGS[INS_S]; if(sc>=32){sc=31;} {REGS[INS_D]=(((sint32)(REGS[INS_T]))>>sc);} } break;
|
||
|
|
caseMINOR(0x08) /* jr */ if(!STATE->slot) { {STATE->slot=2;STATE->slot_target=REGS[INS_S];} } break;
|
||
|
|
caseMINOR(0x09) /* jalr */ if(!STATE->slot) { REGS[INS_D] = PC + 8;{STATE->slot=2;STATE->slot_target=REGS[INS_S];} } break;
|
||
|
|
caseMINOR(0x0C) /*syscall*/ if(!STATE->slot) { exception(STATE, 8, 0); PC -= 4; } break;
|
||
|
|
caseMINOR(0x10) /* mfhi */ if(INS_D) { REGS[INS_D] = HI; } break;
|
||
|
|
caseMINOR(0x11) /* mthi */ { HI = REGS[INS_S]; } break;
|
||
|
|
caseMINOR(0x12) /* mflo */ if(INS_D) { REGS[INS_D] = LO; } break;
|
||
|
|
caseMINOR(0x13) /* mtlo */ { LO = REGS[INS_S]; } break;
|
||
|
|
caseMINOR(0x18) /* mult */ { sint64 t = ((sint64)(((sint32)(REGS[INS_S])))) * ((sint64)(((sint32)(REGS[INS_T])))); LO = (uint32)(t); HI = (uint32)(t >> 32); } break;
|
||
|
|
caseMINOR(0x19) /* multu */ { uint64 t = ((uint64)(((uint32)(REGS[INS_S])))) * ((uint64)(((uint32)(REGS[INS_T])))); LO = (uint32)(t); HI = (uint32)(t >> 32); } break;
|
||
|
|
caseMINOR(0x1A) /* div */ if(REGS[INS_T]) { LO = ((sint32)(REGS[INS_S])) / ((sint32)(REGS[INS_T])); HI = ((sint32)(REGS[INS_S])) % ((sint32)(REGS[INS_T])); } break;
|
||
|
|
caseMINOR(0x1B) /* divu */ if(REGS[INS_T]) { LO = ((uint32)(REGS[INS_S])) / ((uint32)(REGS[INS_T])); HI = ((uint32)(REGS[INS_S])) % ((uint32)(REGS[INS_T])); } break;
|
||
|
|
caseMINOR(0x20) /* add */ if(INS_D) { REGS[INS_D] = (((uint32)(REGS[INS_S])) + ((uint32)(REGS[INS_T]))); } break;
|
||
|
|
caseMINOR(0x21) /* addu */ if(INS_D) { REGS[INS_D] = (((uint32)(REGS[INS_S])) + ((uint32)(REGS[INS_T]))); } break;
|
||
|
|
caseMINOR(0x22) /* sub */ if(INS_D) { REGS[INS_D] = (((uint32)(REGS[INS_S])) - ((uint32)(REGS[INS_T]))); } break;
|
||
|
|
caseMINOR(0x23) /* subu */ if(INS_D) { REGS[INS_D] = (((uint32)(REGS[INS_S])) - ((uint32)(REGS[INS_T]))); } break;
|
||
|
|
caseMINOR(0x24) /* and */ if(INS_D) { REGS[INS_D] = (((uint32)(REGS[INS_S])) & ((uint32)(REGS[INS_T]))); } break;
|
||
|
|
caseMINOR(0x25) /* or */ if(INS_D) { REGS[INS_D] = (((uint32)(REGS[INS_S])) | ((uint32)(REGS[INS_T]))); } break;
|
||
|
|
caseMINOR(0x26) /* xor */ if(INS_D) { REGS[INS_D] = (((uint32)(REGS[INS_S])) ^ ((uint32)(REGS[INS_T]))); } break;
|
||
|
|
caseMINOR(0x27) /* nor */ if(INS_D) { REGS[INS_D] = ~(((uint32)(REGS[INS_S])) | ((uint32)(REGS[INS_T]))); } break;
|
||
|
|
caseMINOR(0x2A) /* slt */ if(INS_D) { REGS[INS_D] = (((sint32)(REGS[INS_S])) < ((sint32)(REGS[INS_T]))); } break;
|
||
|
|
caseMINOR(0x2B) /* sltu */ if(INS_D) { REGS[INS_D] = (((uint32)(REGS[INS_S])) < ((uint32)(REGS[INS_T]))); } break;
|
||
|
|
default: goto badins;
|
||
|
|
}
|
||
|
|
} else {
|
||
|
|
switch(instruction >> 26) {
|
||
|
|
/* MAJOR */
|
||
|
|
caseMAJOR(0x01)
|
||
|
|
switch(INS_T) {
|
||
|
|
case 0x00: /* bltz */ if(!STATE->slot) { if( ((sint32)(REGS[INS_S])) < 0) { J_REL_I; } } break;
|
||
|
|
case 0x01: /* bgez */ if(!STATE->slot) { if( ((sint32)(REGS[INS_S])) >= 0) { J_REL_I; } } break;
|
||
|
|
case 0x10: /* bltzal*/ if(!STATE->slot) { if( ((sint32)(REGS[INS_S])) < 0) { REGS[31]=PC+8; J_REL_I; } } break;
|
||
|
|
case 0x11: /* bgezal*/ if(!STATE->slot) { if( ((sint32)(REGS[INS_S])) >= 0) { REGS[31]=PC+8; J_REL_I; } } break;
|
||
|
|
default: goto badins;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
caseMAJOR(0x02) /* j */ if(!STATE->slot) { J_ABS_I; } break;
|
||
|
|
caseMAJOR(0x03) /* jal */ if(!STATE->slot) { REGS[31]=PC+8; J_ABS_I; } break;
|
||
|
|
caseMAJOR(0x04) /* beq */ if(!STATE->slot) { if(REGS[INS_S] == REGS[INS_T]) { J_REL_I; } } break;
|
||
|
|
caseMAJOR(0x05) /* bne */ if(!STATE->slot) { if(REGS[INS_S] != REGS[INS_T]) { J_REL_I; } } break;
|
||
|
|
caseMAJOR(0x06) /* blez */ if(!STATE->slot) { if( ((sint32)(REGS[INS_S])) <= 0) { J_REL_I; } } break;
|
||
|
|
caseMAJOR(0x07) /* bgtz */ if(!STATE->slot) { if( ((sint32)(REGS[INS_S])) > 0) { J_REL_I; } } break;
|
||
|
|
caseMAJOR(0x08) /* addi */ if(INS_T) { REGS[INS_T] = REGS[INS_S] + SIGNED16(INS_I); } break;
|
||
|
|
caseMAJOR(0x09) /* addiu */ if(INS_T) { REGS[INS_T] = REGS[INS_S] + SIGNED16(INS_I); } break;
|
||
|
|
caseMAJOR(0x0A) /* slti */ if(INS_T) { REGS[INS_T] = ( ((sint32)(REGS[INS_S])) < ((sint32)( ((sint32)( SIGNED16(INS_I) )) )) ); } break;
|
||
|
|
caseMAJOR(0x0B) /* sltiu */ if(INS_T) { REGS[INS_T] = ( ((uint32)(REGS[INS_S])) < ((uint32)( ((sint32)( SIGNED16(INS_I) )) )) ); } break;
|
||
|
|
caseMAJOR(0x0C) /* andi */ if(INS_T) { REGS[INS_T] = REGS[INS_S] & UNSIGNED16(INS_I); } break;
|
||
|
|
caseMAJOR(0x0D) /* ori */ if(INS_T) { REGS[INS_T] = REGS[INS_S] | UNSIGNED16(INS_I); } break;
|
||
|
|
caseMAJOR(0x0E) /* xori */ if(INS_T) { REGS[INS_T] = REGS[INS_S] ^ UNSIGNED16(INS_I); } break;
|
||
|
|
caseMAJOR(0x0F) /* lui */ if(INS_T) { REGS[INS_T] = INS_I << 16; } break;
|
||
|
|
caseMAJOR(0x10) /* cop0 */
|
||
|
|
switch(INS_S) {
|
||
|
|
case 0x00: /* mfc0 */ if(INS_T) { REGS[INS_T] = getc0(STATE, INS_D); } break;
|
||
|
|
case 0x04: /* mtc0 */ { setc0(STATE, INS_D, REGS[INS_T]); r3000_break(state); } break;
|
||
|
|
case 0x10: /* rfe */ {
|
||
|
|
STATE->c0_status =
|
||
|
|
(STATE->c0_status & 0xFFFFFFC0) |
|
||
|
|
((STATE->c0_status & 0x3C) >> 2) |
|
||
|
|
((STATE->c0_status & 0x03) << 4);
|
||
|
|
r3000_break(state); } break;
|
||
|
|
default: goto badins;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
caseMAJOR(0x20) /* lb */ { a = REGS[INS_S] + SIGNED16(INS_I); d = lb(state, a); if(INS_T) { REGS[INS_T] = ((sint32)((sint8)(d))); } } break;
|
||
|
|
caseMAJOR(0x21) /* lh */ { a = REGS[INS_S] + SIGNED16(INS_I); d = lh(state, a); if(INS_T) { REGS[INS_T] = ((sint32)((sint16)(d))); } } break;
|
||
|
|
caseMAJOR(0x23) /* lw */ { a = REGS[INS_S] + SIGNED16(INS_I); d = lw(state, a); if(INS_T) { REGS[INS_T] = d; } } break;
|
||
|
|
caseMAJOR(0x24) /* lbu */ { a = REGS[INS_S] + SIGNED16(INS_I); d = lb(state, a); if(INS_T) { REGS[INS_T] = d & 0x000000FF; } } break;
|
||
|
|
caseMAJOR(0x25) /* lhu */ { a = REGS[INS_S] + SIGNED16(INS_I); d = lh(state, a); if(INS_T) { REGS[INS_T] = d & 0x0000FFFF; } } break;
|
||
|
|
caseMAJOR(0x28) /* sb */ { a = REGS[INS_S] + SIGNED16(INS_I); sb(state, a, REGS[INS_T] & 0x000000FF); } break;
|
||
|
|
caseMAJOR(0x29) /* sh */ { a = REGS[INS_S] + SIGNED16(INS_I); sh(state, a, REGS[INS_T] & 0x0000FFFF); } break;
|
||
|
|
caseMAJOR(0x2B) /* sw */ { a = REGS[INS_S] + SIGNED16(INS_I); sw(state, a, REGS[INS_T] ); } break;
|
||
|
|
|
||
|
|
caseMAJOR(0x22) /* lwl */
|
||
|
|
a = REGS[INS_S] + SIGNED16(INS_I);
|
||
|
|
{ int bitshift;
|
||
|
|
for(bitshift = 24;; bitshift -= 8) {
|
||
|
|
REGS[INS_T] &= ~(0xFF << bitshift);
|
||
|
|
REGS[INS_T] |= (((uint32)(lb(state, a))) & 0xFF) << bitshift;
|
||
|
|
if(!(a&3))break;
|
||
|
|
a--;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
REGS[0] = 0;
|
||
|
|
break;
|
||
|
|
caseMAJOR(0x26) /* lwr */
|
||
|
|
a = REGS[INS_S] + SIGNED16(INS_I);
|
||
|
|
{ int bitshift;
|
||
|
|
for(bitshift = 0;; bitshift += 8) {
|
||
|
|
REGS[INS_T] &= ~(0xFF << bitshift);
|
||
|
|
REGS[INS_T] |= (((uint32)(lb(state, a))) & 0xFF) << bitshift;
|
||
|
|
if((a&3) == 3)break;
|
||
|
|
a++;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
REGS[0] = 0;
|
||
|
|
break;
|
||
|
|
caseMAJOR(0x2A) /* swl */
|
||
|
|
a = REGS[INS_S] + SIGNED16(INS_I);
|
||
|
|
{ int bitshift;
|
||
|
|
for(bitshift = 24;; bitshift -= 8) {
|
||
|
|
sb(state, a, REGS[INS_T]>>bitshift);
|
||
|
|
if(!(a&3))break;
|
||
|
|
a--;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
caseMAJOR(0x2E) /* swr */
|
||
|
|
a = REGS[INS_S] + SIGNED16(INS_I);
|
||
|
|
{ int bitshift;
|
||
|
|
for(bitshift = 0;; bitshift += 8) {
|
||
|
|
sb(state, a, REGS[INS_T]>>bitshift);
|
||
|
|
if((a&3) == 3)break;
|
||
|
|
a++;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
|
||
|
|
default: goto badins;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
PC += 4;
|
||
|
|
|
||
|
|
STATE->cycles_remaining -= DIVIDER;
|
||
|
|
if(STATE->slot) {
|
||
|
|
STATE->slot--;
|
||
|
|
if(!(STATE->slot)) {
|
||
|
|
PC = STATE->slot_target & (~3);
|
||
|
|
STATE->maxpc = 0;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
finishing_sync:
|
||
|
|
|
||
|
|
STATE->cycles_remaining_last_checkpoint += STATE->cycles_deferred_from_break;
|
||
|
|
STATE->cycles_remaining += STATE->cycles_deferred_from_break;
|
||
|
|
STATE->cycles_deferred_from_break = 0;
|
||
|
|
STATE->usage_total_cycles -= STATE->cycles_remaining;
|
||
|
|
update_usage(state);
|
||
|
|
|
||
|
|
hw_sync(state);
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
badins:
|
||
|
|
|
||
|
|
STATE->cycles_remaining_last_checkpoint += STATE->cycles_deferred_from_break;
|
||
|
|
STATE->cycles_remaining += STATE->cycles_deferred_from_break;
|
||
|
|
STATE->cycles_deferred_from_break = 0;
|
||
|
|
STATE->usage_total_cycles -= STATE->cycles_remaining;
|
||
|
|
update_usage(state);
|
||
|
|
|
||
|
|
hw_sync(state);
|
||
|
|
return -1;
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
/////////////////////////////////////////////////////////////////////////////
|
||
|
|
//
|
||
|
|
// Get usage statistics
|
||
|
|
//
|
||
|
|
uint32 EMU_CALL r3000_get_usage_fraction(void *state) {
|
||
|
|
return STATE->usage_last_fraction;
|
||
|
|
}
|
||
|
|
|
||
|
|
/////////////////////////////////////////////////////////////////////////////
|
||
|
|
//
|
||
|
|
// Perform prediction of what next instruction will do
|
||
|
|
//
|
||
|
|
// first word: address of next instruction
|
||
|
|
// following words describe possible activity
|
||
|
|
// 0xxxxxxx yyyyyyyy means "read x bytes from address y"
|
||
|
|
// 1xxxxxxx yyyyyyyy means "write x bytes from address y"
|
||
|
|
// 20000000 yyyyyyyy means "jump to y"
|
||
|
|
// 30000000 yyyyyyyy means "call to y"
|
||
|
|
// 00000000 terminates the list
|
||
|
|
// max 256 bytes in prediction profile
|
||
|
|
//
|
||
|
|
#define PROFILE_READ 0x00000000
|
||
|
|
#define PROFILE_WRITE 0x10000000
|
||
|
|
#define PROFILE_JUMP 0x20000000
|
||
|
|
#define PROFILE_CALL 0x30000000
|
||
|
|
|
||
|
|
void EMU_CALL r3000_predict(void *state, uint32 *profile) {
|
||
|
|
uint32 instruction = lw_noeffects(STATE, PC);
|
||
|
|
*profile++ = PC + 4;
|
||
|
|
if(instruction < 0x04000000) {
|
||
|
|
switch(instruction & 0x3F) {
|
||
|
|
caseMINOR(0x08) /* jr */ *profile++ = PROFILE_JUMP; *profile++ = REGS[INS_S]; break;
|
||
|
|
caseMINOR(0x09) /* jalr */ *profile++ = PROFILE_CALL; *profile++ = REGS[INS_S]; break;
|
||
|
|
}
|
||
|
|
} else {
|
||
|
|
switch(instruction >> 26) {
|
||
|
|
caseMAJOR(0x01)
|
||
|
|
switch(INS_T) {
|
||
|
|
case 0x00: /* bltz */ *profile++ = PROFILE_JUMP; *profile++ = REL_I; break;
|
||
|
|
case 0x01: /* bgez */ *profile++ = PROFILE_JUMP; *profile++ = REL_I; break;
|
||
|
|
case 0x10: /* bltzal*/ *profile++ = PROFILE_CALL; *profile++ = REL_I; break;
|
||
|
|
case 0x11: /* bgezal*/ *profile++ = PROFILE_CALL; *profile++ = REL_I; break;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
caseMAJOR(0x02) /* j */ *profile++ = PROFILE_JUMP; *profile++ = ABS_I; break;
|
||
|
|
caseMAJOR(0x03) /* jal */ *profile++ = PROFILE_CALL; *profile++ = ABS_I; break;
|
||
|
|
caseMAJOR(0x04) /* beq */ *profile++ = PROFILE_JUMP; *profile++ = REL_I; break;
|
||
|
|
caseMAJOR(0x05) /* bne */ *profile++ = PROFILE_JUMP; *profile++ = REL_I; break;
|
||
|
|
caseMAJOR(0x06) /* blez */ *profile++ = PROFILE_JUMP; *profile++ = REL_I; break;
|
||
|
|
caseMAJOR(0x07) /* bgtz */ *profile++ = PROFILE_JUMP; *profile++ = REL_I; break;
|
||
|
|
|
||
|
|
caseMAJOR(0x20) /* lb */ *profile++ = PROFILE_READ +1; *profile++ = REGS[INS_S] + SIGNED16(INS_I); break;
|
||
|
|
caseMAJOR(0x21) /* lh */ *profile++ = PROFILE_READ +2; *profile++ = REGS[INS_S] + SIGNED16(INS_I); break;
|
||
|
|
caseMAJOR(0x23) /* lw */ *profile++ = PROFILE_READ +4; *profile++ = REGS[INS_S] + SIGNED16(INS_I); break;
|
||
|
|
caseMAJOR(0x24) /* lbu */ *profile++ = PROFILE_READ +1; *profile++ = REGS[INS_S] + SIGNED16(INS_I); break;
|
||
|
|
caseMAJOR(0x25) /* lhu */ *profile++ = PROFILE_READ +2; *profile++ = REGS[INS_S] + SIGNED16(INS_I); break;
|
||
|
|
caseMAJOR(0x28) /* sb */ *profile++ = PROFILE_WRITE+1; *profile++ = REGS[INS_S] + SIGNED16(INS_I); break;
|
||
|
|
caseMAJOR(0x29) /* sh */ *profile++ = PROFILE_WRITE+2; *profile++ = REGS[INS_S] + SIGNED16(INS_I); break;
|
||
|
|
caseMAJOR(0x2B) /* sw */ *profile++ = PROFILE_WRITE+4; *profile++ = REGS[INS_S] + SIGNED16(INS_I); break;
|
||
|
|
|
||
|
|
// these could be done better, but this is good enough for now
|
||
|
|
caseMAJOR(0x22) /* lwl */ *profile++ = PROFILE_READ +4; *profile++ = REGS[INS_S] + SIGNED16(INS_I); break;
|
||
|
|
caseMAJOR(0x26) /* lwr */ *profile++ = PROFILE_READ +4; *profile++ = REGS[INS_S] + SIGNED16(INS_I); break;
|
||
|
|
caseMAJOR(0x2A) /* swl */ *profile++ = PROFILE_WRITE+4; *profile++ = REGS[INS_S] + SIGNED16(INS_I); break;
|
||
|
|
caseMAJOR(0x2E) /* swr */ *profile++ = PROFILE_WRITE+4; *profile++ = REGS[INS_S] + SIGNED16(INS_I); break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
*profile = 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/////////////////////////////////////////////////////////////////////////////
|