From 2b40e87fee685abd178fc06fe4a0ac69c8ee6503 Mon Sep 17 00:00:00 2001
From: Chris Moeller <kode54@gmail.com>
Date: Sat, 26 Oct 2013 15:25:06 -0700
Subject: [PATCH] Yes, the SPC control register is supposed to clear its read
 ports, but SPC files aren't supposed to trigger that with their initial
 control register

---
 Frameworks/GME/gme/Spc_Emu.cpp          | 2 +-
 Frameworks/GME/gme/higan/smp/memory.cpp | 9 +++++++++
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/Frameworks/GME/gme/Spc_Emu.cpp b/Frameworks/GME/gme/Spc_Emu.cpp
index f323b15b5..abe59015f 100644
--- a/Frameworks/GME/gme/Spc_Emu.cpp
+++ b/Frameworks/GME/gme/Spc_Emu.cpp
@@ -376,10 +376,10 @@ blargg_err_t Spc_Emu::start_track_( int track )
     smp.regs.s = header.sp;
     
     memcpy( smp.apuram, ptr, 0x10000 );
-    memcpy( smp.sfm_last, ptr + 0xF4, 4 );
     
     static const uint8_t regs_to_copy[] = { 0xF1, 0xF2, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC };
     for (auto n : regs_to_copy) smp.op_buswrite( n, ptr[ n ] );
+    memcpy( smp.sfm_last, ptr + 0xF4, 4 );
     ptr += 0x10000;
     
     smp.dsp.spc_dsp.load( ptr );
diff --git a/Frameworks/GME/gme/higan/smp/memory.cpp b/Frameworks/GME/gme/higan/smp/memory.cpp
index 951b719d0..d3836b543 100755
--- a/Frameworks/GME/gme/higan/smp/memory.cpp
+++ b/Frameworks/GME/gme/higan/smp/memory.cpp
@@ -97,6 +97,15 @@ void SMP::op_buswrite(uint16_t addr, uint8_t data) {
 
   case 0xf1:  //CONTROL
     status.iplrom_enable = data & 0x80;
+          
+    if (data & 0x10) {
+      sfm_last[ 0 ] = 0;
+      sfm_last[ 1 ] = 0;
+    }
+    if (data & 0x20) {
+      sfm_last[ 2 ] = 0;
+      sfm_last[ 3 ] = 0;
+    }
 
     //0->1 transistion resets timers
     if(timer2.enable == false && (data & 0x04)) {