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containerPortal = 17C808710C3BD167005707C4 /* FileSource.xcodeproj */; @@ -422,6 +408,13 @@ remoteGlobalIDString = 99B989F40CC7E10400C256E9; remoteInfo = "APL Plugin"; }; + 8360EF0417F92B24005208A4 /* PBXContainerItemProxy */ = { + isa = PBXContainerItemProxy; + containerPortal = 8360EF0017F92B23005208A4 /* HighlyComplete.xcodeproj */; + proxyType = 2; + remoteGlobalIDString = 8360EEE417F92AC8005208A4; + remoteInfo = HighlyComplete; + }; 8E8D40860CBB036600135C1B /* PBXContainerItemProxy */ = { isa = PBXContainerItemProxy; containerPortal = 8E8D40820CBB036600135C1B /* M3u.xcodeproj */; @@ -475,7 +468,7 @@ dstPath = ""; dstSubfolderSpec = 13; files = ( - 17B7CF970F5A0A4D00A47027 /* AudioOverload.bundle in CopyFiles */, + 8360EF6D17F92E56005208A4 /* HighlyComplete.bundle in CopyFiles */, 99EAACA80DD1BB7A00423C38 /* APL.bundle in CopyFiles */, 17C8F7D80CBEF3EF008D969D /* Dumb.bundle in CopyFiles */, 17C8F3CF0CBED66C008D969D /* GME.bundle in CopyFiles */, @@ -638,7 +631,6 @@ 17B7CF590F5A05EE00A47027 /* pauseBadge.png */ = {isa = PBXFileReference; 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Belmont and Richard Bannister. -# -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: -# -# * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. -# * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. -# * Neither the names of R. Belmont and Richard Bannister nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR -# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# - -# NOTE: this makefile will auto-detect Linux and MinGW and work appropriately. Other OSes will likely -# need some help. - -CC = gcc -LD = gcc -CPP = g++ -CFLAGS = -c -O3 -DPATH_MAX=1024 -DHAS_PSXCPU=1 -I. -I.. -Ieng_ssf -Ieng_qsf -Ieng_dsf -Izlib -# set for Linux 64-bit -# CFLAGS += -DLONG_IS_64BIT=1 -# set for little-endian, make "0" for big-endian -CFLAGS += -DLSB_FIRST=1 - -LDFLAGS = - -EXE = aosdk -LIBS = -lm -lz - -# main objects -OBJS = corlett.o main_original.o - -# port objects -#ifeq ($(OSTYPE),linux) -#OBJS += oss.o -#else -#OBJS += dsnd.o -#LIBS += -ldsound -ldxguid -#endif -OBJS += file.o - -# DSF engine -OBJS += eng_dsf/eng_dsf.o eng_dsf/dc_hw.o eng_dsf/aica.o eng_dsf/aicadsp.o eng_dsf/arm7.o eng_dsf/arm7i.o - -# SSF engine -OBJS += eng_ssf/m68kcpu.o eng_ssf/m68kopac.o eng_ssf/m68kopdm.o eng_ssf/m68kopnz.o eng_ssf/m68kops.o -OBJS += eng_ssf/scsp.o eng_ssf/scspdsp.o eng_ssf/sat_hw.o eng_ssf/eng_ssf.o - -# QSF engine -OBJS += eng_qsf/eng_qsf.o eng_qsf/kabuki.o eng_qsf/qsound.o eng_qsf/z80.o eng_qsf/z80dasm.o - -# PSF engine -OBJS += eng_psf/eng_psf.o eng_psf/psx.o eng_psf/psx_hw.o eng_psf/peops/spu.o - -# PSF2 extentions -OBJS += eng_psf/eng_psf2.o eng_psf/peops2/spu.o eng_psf/peops2/dma.o eng_psf/peops2/registers.o - -# SPU engine (requires PSF engine) -OBJS += eng_psf/eng_spu.o - -# zlib (included for max portability) -#OBJS += zlib/adler32.o zlib/compress.o zlib/crc32.o zlib/gzio.o zlib/uncompr.o zlib/deflate.o zlib/trees.o -#OBJS += zlib/zutil.o zlib/inflate.o zlib/infback.o zlib/inftrees.o zlib/inffast.o - -SRCS=$(OBJS:.o=.c) - -%.o: %.c - @echo $(CC) $(CFLAGS) $< -o $@ - @$(CC) $(CFLAGS) $< -o $@ - -%.o: %.cpp - @echo $(CPP) $(CFLAGS) $< -o $@ - @$(CPP) $(CFLAGS) $< -o $@ - -all: $(EXE) - -$(EXE): $(OBJS) - @echo $(LD) $(LDFLAGS) -g -o $(EXE) $(OBJS) $(LIBS) - @$(LD) $(LDFLAGS) -g -o $(EXE) $(OBJS) $(LIBS) - -clean: - rm -f $(OBJS) $(EXE) - diff --git a/Frameworks/AudioOverload/aosdk/ao.h b/Frameworks/AudioOverload/aosdk/ao.h deleted file mode 100755 index 36aec497d..000000000 --- a/Frameworks/AudioOverload/aosdk/ao.h +++ /dev/null @@ -1,185 +0,0 @@ -// -// Audio Overload SDK -// -// Fake ao.h to set up the general Audio Overload style environment -// - -#ifndef __AO_H -#define __AO_H - -#define AO_SUCCESS 1 -#define AO_FAIL 0 -#define AO_FAIL_DECOMPRESSION -1 - -#define MAX_DISP_INFO_LENGTH 256 -#define AUDIO_RATE (44100) - -enum -{ - COMMAND_NONE = 0, - COMMAND_PREV, - COMMAND_NEXT, - COMMAND_RESTART, - COMMAND_HAS_PREV, - COMMAND_HAS_NEXT, - COMMAND_GET_MIN, - COMMAND_GET_MAX, - COMMAND_JUMP -}; - -/* Compiler defines for Xcode */ -#ifdef __BIG_ENDIAN__ - #undef LSB_FIRST -#endif - -#ifdef __LITTLE_ENDIAN__ - #define LSB_FIRST 1 -#endif - -typedef unsigned char ao_bool; - -#ifdef __GNUC__ -#include // get NULL -#include - -#ifndef nil -#define nil NULL -#endif - -#ifndef TRUE -#define TRUE (1) -#endif -#ifndef FALSE -#define FALSE (0) -#endif - -#define xmalloc(a) malloc(a) - -#endif - -#ifdef _MSC_VER -#include // get NULL -#include // for off_t - -#ifndef nil -#define nil NULL -#endif - -#ifndef TRUE -#define TRUE (1) -#endif -#ifndef FALSE -#define FALSE (0) -#endif - -#define true (1) -#define false (0) - -#define xmalloc(a) malloc(a) - -#define strcasecmp _strcmpi - -#endif - -#ifndef PATH_MAX -#define PATH_MAX 2048 -#endif - -typedef struct -{ - char title[9][MAX_DISP_INFO_LENGTH]; - char info[9][MAX_DISP_INFO_LENGTH]; -} ao_display_info; - -typedef unsigned char uint8; -typedef unsigned char UINT8; -typedef signed char int8; -typedef signed char INT8; -typedef unsigned short uint16; -typedef unsigned short UINT16; -typedef signed short int16; -typedef signed short INT16; -typedef signed int int32; -typedef unsigned int uint32; -#ifdef LONG_IS_64BIT -typedef signed long int64; -typedef unsigned long uint64; -#else -typedef signed long long int64; -typedef unsigned long long uint64; -#endif - -#ifdef WIN32 -#ifndef _BASETSD_H -typedef signed int INT32; -typedef unsigned int UINT32; -typedef signed long long INT64; -typedef unsigned long long UINT64; -#endif -#else -typedef signed int INT32; -typedef unsigned int UINT32; -#ifdef LONG_IS_64BIT -typedef signed long INT64; -typedef unsigned long UINT64; -#else -typedef signed long long INT64; -typedef unsigned long long UINT64; -#endif -#endif - -#ifndef INLINE -#if defined(_MSC_VER) -#define INLINE __forceinline -#elif defined(__GNUC__) -#define INLINE __inline__ -#elif defined(_MWERKS_) -#define INLINE inline -#elif defined(__powerc) -#define INLINE inline -#else -#define INLINE -#endif -#endif - -#if LSB_FIRST -#define LE16(x) (x) -#define LE32(x) (x) - -#ifndef __ENDIAN__ /* Mac OS X Endian header has this function in it */ -static unsigned long INLINE Endian32_Swap(unsigned long addr) -{ - unsigned long res = (((addr&0xff000000)>>24) | - ((addr&0x00ff0000)>>8) | - ((addr&0x0000ff00)<<8) | - ((addr&0x000000ff)<<24)); - - return res; -} -#endif - -#else - -static unsigned short INLINE LE16(unsigned short x) -{ - unsigned short res = (((x & 0xFF00) >> 8) | ((x & 0xFF) << 8)); - return res; -} - -static unsigned long INLINE LE32(unsigned long addr) -{ - unsigned long res = (((addr&0xff000000)>>24) | - ((addr&0x00ff0000)>>8) | - ((addr&0x0000ff00)<<8) | - ((addr&0x000000ff)<<24)); - - return res; -} - -#endif - -int ao_get_lib(char *filename, uint8 **buffer, uint64 *length); - -void ao_set_get_lib_callback(int (*callback)(char *, uint8 **, uint64 *)); - -#endif // AO_H diff --git a/Frameworks/AudioOverload/aosdk/corlett.c b/Frameworks/AudioOverload/aosdk/corlett.c deleted file mode 100644 index b7a68b68a..000000000 --- a/Frameworks/AudioOverload/aosdk/corlett.c +++ /dev/null @@ -1,380 +0,0 @@ -/* - - Audio Overload SDK - - Copyright (c) 2007-2008, R. Belmont and Richard Bannister. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - * Neither the names of R. Belmont and Richard Bannister nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -// corlett.c - -// Decodes file format designed by Neill Corlett (PSF, QSF, ...) - -/* - - First 3 bytes: ASCII signature: "PSF" (case sensitive) - -- Next 1 byte: Version byte - The version byte is used to determine the type of PSF file. It does NOT - affect the basic structure of the file in any way. - - Currently accepted version bytes are: - 0x01: Playstation (PSF1) - 0x02: Playstation 2 (PSF2) - 0x11: Saturn (SSF) [TENTATIVE] - 0x12: Dreamcast (DSF) [TENTATIVE] - 0x21: Nintendo 64 (USF) [RESERVED] - 0x41: Capcom QSound (QSF) - -- Next 4 bytes: Size of reserved area (R), little-endian unsigned long - -- Next 4 bytes: Compressed program length (N), little-endian unsigned long - This is the length of the program data _after_ compression. - -- Next 4 bytes: Compressed program CRC-32, little-endian unsigned long - This is the CRC-32 of the program data _after_ compression. Filling in - this value is mandatory, as a PSF file may be regarded as corrupt if it - does not match. - -- Next R bytes: Reserved area. - May be empty if R is 0 bytes. - -- Next N bytes: Compressed program, in zlib compress() format. - May be empty if N is 0 bytes. - -The following data is optional and may be omitted: - -- Next 5 bytes: ASCII signature: "[TAG]" (case sensitive) - If these 5 bytes do not match, then the remainder of the file may be - regarded as invalid and discarded. - -- Remainder of file: Uncompressed ASCII tag data. -*/ - -#include -#include -#include - -#include "ao.h" -#include "corlett.h" - -#include -#include - -#define DECOMP_MAX_SIZE ((32 * 1024 * 1024) + 12) - -int corlett_decode(uint8 *input, uint32 input_len, uint8 **output, uint64 *size, corlett_t **c) -{ - uint32 *buf; - uint32 res_area, comp_crc, actual_crc; - uint8 *decomp_dat, *tag_dec; - uLongf decomp_length, comp_length; - - // 32-bit pointer to data - buf = (uint32 *)input; - - // Check we have a PSF format file. - if ((input[0] != 'P') || (input[1] != 'S') || (input[2] != 'F')) - { - return AO_FAIL; - } - - // Get our values - res_area = LE32(buf[1]); - comp_length = LE32(buf[2]); - comp_crc = LE32(buf[3]); - - if (comp_length > 0) - { - // Check length - if (input_len < comp_length + 16) - return AO_FAIL; - - // Check CRC is correct - actual_crc = crc32(0, (unsigned char *)&buf[4+(res_area/4)], comp_length); - if (actual_crc != comp_crc) - return AO_FAIL; - - // Decompress data if any - decomp_dat = malloc(DECOMP_MAX_SIZE); - if (NULL == decomp_dat) { - return AO_FAIL; - } - - decomp_length = DECOMP_MAX_SIZE; - if (uncompress(decomp_dat, &decomp_length, (unsigned char *)&buf[4+(res_area/4)], comp_length) != Z_OK) - { - free(decomp_dat); - return AO_FAIL; - } - - // Resize memory buffer to what we actually need - decomp_dat = realloc(decomp_dat, (size_t)decomp_length + 1); - } - else - { - decomp_dat = NULL; - decomp_length = 0; - } - - // Make structure - *c = malloc(sizeof(corlett_t)); - if (!(*c)) - { - free(decomp_dat); - return AO_FAIL; - } - memset(*c, 0, sizeof(corlett_t)); - strcpy((*c)->inf_title, "n/a"); - strcpy((*c)->inf_copy, "n/a"); - strcpy((*c)->inf_artist, "n/a"); - strcpy((*c)->inf_game, "n/a"); - strcpy((*c)->inf_year, "n/a"); - strcpy((*c)->inf_length, "n/a"); - strcpy((*c)->inf_fade, "n/a"); - - // set reserved section pointer - (*c)->res_section = &buf[4]; - (*c)->res_size = res_area; - - // Return it - *output = decomp_dat; - *size = decomp_length; - - // Next check for tags - input_len -= (comp_length + 16 + res_area); - if (input_len < 5) - return AO_SUCCESS; - -// printf("\n\nNew corlett: input len %d\n", input_len); - - tag_dec = input + (comp_length + res_area + 16); - if ((tag_dec[0] == '[') && (tag_dec[1] == 'T') && (tag_dec[2] == 'A') && (tag_dec[3] == 'G') && (tag_dec[4] == ']')) - { - int tag, l, num_tags, data; - - // Tags found! - tag_dec += 5; - input_len -= 5; - - tag = 0; - data = false; - num_tags = 0; - l = 0; - while (input_len && (num_tags < MAX_UNKNOWN_TAGS)) - { - if (data) - { - if ((*tag_dec == 0xA) || (*tag_dec == 0x00)) - { - (*c)->tag_data[num_tags][l] = 0; - data = false; - num_tags++; - l = 0; - } - else - { - (*c)->tag_data[num_tags][l++] = *tag_dec; - } - } - else - { - if (*tag_dec == '=') - { - (*c)->tag_name[num_tags][l] = 0; - l = 0; - data = true; - } - else - { - (*c)->tag_name[num_tags][l++] = *tag_dec; - } - } - - tag_dec++; - input_len--; - } - - - // Now, process that tag array into what we expect - for (num_tags = 0; num_tags < MAX_UNKNOWN_TAGS; num_tags++) - { - // See if tag belongs in one of the special fields we have - if (!strcasecmp((*c)->tag_name[num_tags], "_lib")) - { - strcpy((*c)->lib, (*c)->tag_data[num_tags]); - (*c)->tag_data[num_tags][0] = 0; - (*c)->tag_name[num_tags][0] = 0; - } - else if (!strncmp((*c)->tag_name[num_tags], "_lib2", 5)) - { - strcpy((*c)->libaux[0], (*c)->tag_data[num_tags]); - (*c)->tag_data[num_tags][0] = 0; - (*c)->tag_name[num_tags][0] = 0; - } - else if (!strncmp((*c)->tag_name[num_tags], "_lib3", 5)) - { - strcpy((*c)->libaux[1], (*c)->tag_data[num_tags]); - (*c)->tag_data[num_tags][0] = 0; - (*c)->tag_name[num_tags][0] = 0; - } - else if (!strncmp((*c)->tag_name[num_tags], "_lib4", 5)) - { - strcpy((*c)->libaux[2], (*c)->tag_data[num_tags]); - (*c)->tag_data[num_tags][0] = 0; - (*c)->tag_name[num_tags][0] = 0; - } - else if (!strncmp((*c)->tag_name[num_tags], "_lib5", 5)) - { - strcpy((*c)->libaux[3], (*c)->tag_data[num_tags]); - (*c)->tag_data[num_tags][0] = 0; - (*c)->tag_name[num_tags][0] = 0; - } - else if (!strncmp((*c)->tag_name[num_tags], "_lib6", 5)) - { - strcpy((*c)->libaux[4], (*c)->tag_data[num_tags]); - (*c)->tag_data[num_tags][0] = 0; - (*c)->tag_name[num_tags][0] = 0; - } - else if (!strncmp((*c)->tag_name[num_tags], "_lib7", 5)) - { - strcpy((*c)->libaux[5], (*c)->tag_data[num_tags]); - (*c)->tag_data[num_tags][0] = 0; - (*c)->tag_name[num_tags][0] = 0; - } - else if (!strncmp((*c)->tag_name[num_tags], "_lib8", 5)) - { - strcpy((*c)->libaux[6], (*c)->tag_data[num_tags]); - (*c)->tag_data[num_tags][0] = 0; - (*c)->tag_name[num_tags][0] = 0; - } - else if (!strncmp((*c)->tag_name[num_tags], "_lib9", 5)) - { - strcpy((*c)->libaux[7], (*c)->tag_data[num_tags]); - (*c)->tag_data[num_tags][0] = 0; - (*c)->tag_name[num_tags][0] = 0; - } - else if (!strncmp((*c)->tag_name[num_tags], "_refresh", 8)) - { - strcpy((*c)->inf_refresh, (*c)->tag_data[num_tags]); - (*c)->tag_data[num_tags][0] = 0; - (*c)->tag_name[num_tags][0] = 0; - } - else if (!strncmp((*c)->tag_name[num_tags], "title", 5)) - { - strcpy((*c)->inf_title, (*c)->tag_data[num_tags]); - (*c)->tag_data[num_tags][0] = 0; - (*c)->tag_name[num_tags][0] = 0; - } - else if (!strncmp((*c)->tag_name[num_tags], "copyright", 9)) - { - strcpy((*c)->inf_copy, (*c)->tag_data[num_tags]); - (*c)->tag_data[num_tags][0] = 0; - (*c)->tag_name[num_tags][0] = 0; - } - else if (!strncmp((*c)->tag_name[num_tags], "artist", 6)) - { - strcpy((*c)->inf_artist, (*c)->tag_data[num_tags]); - (*c)->tag_data[num_tags][0] = 0; - (*c)->tag_name[num_tags][0] = 0; - } - else if (!strncmp((*c)->tag_name[num_tags], "game", 4)) - { - strcpy((*c)->inf_game, (*c)->tag_data[num_tags]); - (*c)->tag_data[num_tags][0] = 0; - (*c)->tag_name[num_tags][0] = 0; - } - else if (!strncmp((*c)->tag_name[num_tags], "year", 4)) - { - strcpy((*c)->inf_year, (*c)->tag_data[num_tags]); - (*c)->tag_data[num_tags][0] = 0; - (*c)->tag_name[num_tags][0] = 0; - } - else if (!strncmp((*c)->tag_name[num_tags], "length", 6)) - { - strcpy((*c)->inf_length, (*c)->tag_data[num_tags]); - (*c)->tag_data[num_tags][0] = 0; - (*c)->tag_name[num_tags][0] = 0; - } - else if (!strncmp((*c)->tag_name[num_tags], "fade", 4)) - { - strcpy((*c)->inf_fade, (*c)->tag_data[num_tags]); - (*c)->tag_data[num_tags][0] = 0; - (*c)->tag_name[num_tags][0] = 0; - } - } - } - - // Bingo - return AO_SUCCESS; -} - -uint32 psfTimeToMS(char *str) -{ - int x, c=0; - uint32 acc=0; - char s[100]; - - strncpy(s,str,100); - s[99]=0; - - for (x=strlen(s); x>=0; x--) - { - if (s[x]=='.' || s[x]==',') - { - acc=atoi(s+x+1); - s[x]=0; - } - else if (s[x]==':') - { - if(c==0) - { - acc+=atoi(s+x+1)*10; - } - else if(c==1) - { - acc+=atoi(s+x+(x?1:0))*10*60; - } - - c++; - s[x]=0; - } - else if (x==0) - { - if(c==0) - { - acc+=atoi(s+x)*10; - } - else if(c==1) - { - acc+=atoi(s+x)*10*60; - } - else if(c==2) - { - acc+=atoi(s+x)*10*60*60; - } - } - } - - acc*=100; - return(acc); -} - diff --git a/Frameworks/AudioOverload/aosdk/corlett.h b/Frameworks/AudioOverload/aosdk/corlett.h deleted file mode 100644 index a9b1ed16d..000000000 --- a/Frameworks/AudioOverload/aosdk/corlett.h +++ /dev/null @@ -1,35 +0,0 @@ -// -// Audio Overload -// Emulated music player -// -// (C) 2000-2008 Richard F. Bannister -// - -// corlett.h - -#define MAX_UNKNOWN_TAGS 32 - -typedef struct { - char lib[256]; - char libaux[8][256]; - - char inf_title[256]; - char inf_copy[256]; - char inf_artist[256]; - char inf_game[256]; - char inf_year[256]; - char inf_length[256]; - char inf_fade[256]; - - char inf_refresh[256]; - - char tag_name[MAX_UNKNOWN_TAGS][256]; - char tag_data[MAX_UNKNOWN_TAGS][256]; - - uint32 *res_section; - uint32 res_size; -} corlett_t; - -int corlett_decode(uint8 *input, uint32 input_len, uint8 **output, uint64 *size, corlett_t **c); -uint32 psfTimeToMS(char *str); - diff --git a/Frameworks/AudioOverload/aosdk/cpuintrf.h b/Frameworks/AudioOverload/aosdk/cpuintrf.h deleted file mode 100644 index 1317f4189..000000000 --- a/Frameworks/AudioOverload/aosdk/cpuintrf.h +++ /dev/null @@ -1,668 +0,0 @@ -#ifndef CPUINTRF_H -#define CPUINTRF_H - -#include "osd_cpu.h" - -/* The old system is obsolete and no longer supported by the core */ -#define NEW_INTERRUPT_SYSTEM 1 - -#define MAX_IRQ_LINES 8 /* maximum number of IRQ lines per CPU */ - -#define CLEAR_LINE 0 /* clear (a fired, held or pulsed) line */ -#define ASSERT_LINE 1 /* assert an interrupt immediately */ -#define HOLD_LINE 2 /* hold interrupt line until enable is true */ -#define PULSE_LINE 3 /* pulse interrupt line for one instruction */ - -#define MAX_REGS 64 /* maximum number of register of any CPU */ - -#define IRQ_LINE_NMI 10 -/* Values passed to the cpu_info function of a core to retrieve information */ -enum { - CPU_INFO_REG, - CPU_INFO_FLAGS=MAX_REGS, - CPU_INFO_NAME, - CPU_INFO_FAMILY, - CPU_INFO_VERSION, - CPU_INFO_FILE, - CPU_INFO_CREDITS, - CPU_INFO_REG_LAYOUT, - CPU_INFO_WIN_LAYOUT -}; - -#define CPU_IS_LE 0 /* emulated CPU is little endian */ -#define CPU_IS_BE 1 /* emulated CPU is big endian */ - -/* - * This value is passed to cpu_get_reg to retrieve the previous - * program counter value, ie. before a CPU emulation started - * to fetch opcodes and arguments for the current instrution. - */ -#define REG_PREVIOUSPC -1 - -/* - * This value is passed to cpu_get_reg/cpu_set_reg, instead of one of - * the names from the enum a CPU core defines for it's registers, - * to get or set the contents of the memory pointed to by a stack pointer. - * You can specify the n'th element on the stack by (REG_SP_CONTENTS-n), - * ie. lower negative values. The actual element size (UINT16 or UINT32) - * depends on the CPU core. - * This is also used to replace the cpu_geturnpc() function. - */ -#define REG_SP_CONTENTS -2 - -/* - * These flags can be defined in the makefile (or project) to - * exclude (zero) or include (non zero) specific CPU cores - */ -#ifndef HAS_GENSYNC -#define HAS_GENSYNC 0 -#endif -#ifndef HAS_Z80 -#define HAS_Z80 0 -#endif -#ifndef HAS_Z80_VM -#define HAS_Z80_VM 0 -#endif -#ifndef HAS_8080 -#define HAS_8080 0 -#endif -#ifndef HAS_8085A -#define HAS_8085A 0 -#endif -#ifndef HAS_M6502 -#define HAS_M6502 0 -#endif -#ifndef HAS_M65C02 -#define HAS_M65C02 0 -#endif -#ifndef HAS_M65SC02 -#define HAS_M65SC02 0 -#endif -#ifndef HAS_M65CE02 -#define HAS_M65CE02 0 -#endif -#ifndef HAS_M6509 -#define HAS_M6509 0 -#endif -#ifndef HAS_M6510 -#define HAS_M6510 0 -#endif -#ifndef HAS_N2A03 -#define HAS_N2A03 0 -#endif -#ifndef HAS_H6280 -#define HAS_H6280 0 -#endif -#ifndef HAS_I86 -#define HAS_I86 0 -#endif -#ifndef HAS_V20 -#define HAS_V20 0 -#endif -#ifndef HAS_V30 -#define HAS_V30 0 -#endif -#ifndef HAS_V33 -#define HAS_V33 0 -#endif -#ifndef HAS_I8035 -#define HAS_I8035 0 -#endif -#ifndef HAS_I8039 -#define HAS_I8039 0 -#endif -#ifndef HAS_I8048 -#define HAS_I8048 0 -#endif -#ifndef HAS_N7751 -#define HAS_N7751 0 -#endif -#ifndef HAS_M6800 -#define HAS_M6800 0 -#endif -#ifndef HAS_M6801 -#define HAS_M6801 0 -#endif -#ifndef HAS_M6802 -#define HAS_M6802 0 -#endif -#ifndef HAS_M6803 -#define HAS_M6803 0 -#endif -#ifndef HAS_M6808 -#define HAS_M6808 0 -#endif -#ifndef HAS_HD63701 -#define HAS_HD63701 0 -#endif -#ifndef HAS_M6805 -#define HAS_M6805 0 -#endif -#ifndef HAS_M68705 -#define HAS_M68705 0 -#endif -#ifndef HAS_HD63705 -#define HAS_HD63705 0 -#endif -#ifndef HAS_HD6309 -#define HAS_HD6309 0 -#endif -#ifndef HAS_M6809 -#define HAS_M6809 0 -#endif -#ifndef HAS_KONAMI -#define HAS_KONAMI 0 -#endif -#ifndef HAS_M68000 -#define HAS_M68000 0 -#endif -#ifndef HAS_M68010 -#define HAS_M68010 0 -#endif -#ifndef HAS_M68020 -#define HAS_M68020 0 -#endif -#ifndef HAS_T11 -#define HAS_T11 0 -#endif -#ifndef HAS_S2650 -#define HAS_S2650 0 -#endif -#ifndef HAS_TMS34010 -#define HAS_TMS34010 0 -#endif -#ifndef HAS_TMS9900 -#define HAS_TMS9900 0 -#endif -#ifndef HAS_TMS9940 -#define HAS_TMS9940 0 -#endif -#ifndef HAS_TMS9980 -#define HAS_TMS9980 0 -#endif -#ifndef HAS_TMS9985 -#define HAS_TMS9985 0 -#endif -#ifndef HAS_TMS9989 -#define HAS_TMS9989 0 -#endif -#ifndef HAS_TMS9995 -#define HAS_TMS9995 0 -#endif -#ifndef HAS_TMS99105A -#define HAS_TMS99105A 0 -#endif -#ifndef HAS_TMS99110A -#define HAS_TMS99110A 0 -#endif -#ifndef HAS_Z8000 -#define HAS_Z8000 0 -#endif -#ifndef HAS_TMS320C10 -#define HAS_TMS320C10 0 -#endif -#ifndef HAS_CCPU -#define HAS_CCPU 0 -#endif -#ifndef HAS_PDP1 -#define HAS_PDP1 0 -#endif -#ifndef HAS_ADSP2100 -#define HAS_ADSP2100 0 -#endif - -/* ASG 971222 -- added this generic structure */ -struct cpu_interface -{ - unsigned cpu_num; - void (*reset)(void *param); - void (*exit)(void); - int (*execute)(int cycles); - void (*burn)(int cycles); - unsigned (*get_context)(void *reg); - void (*set_context)(void *reg); - unsigned (*get_pc)(void); - void (*set_pc)(unsigned val); - unsigned (*get_sp)(void); - void (*set_sp)(unsigned val); - unsigned (*get_reg)(int regnum); - void (*set_reg)(int regnum, unsigned val); - void (*set_nmi_line)(int linestate); - void (*set_irq_line)(int irqline, int linestate); - void (*set_irq_callback)(int(*callback)(int irqline)); - void (*internal_interrupt)(int type); - void (*cpu_state_save)(void *file); - void (*cpu_state_load)(void *file); - const char* (*cpu_info)(void *context,int regnum); - unsigned (*cpu_dasm)(char *buffer,unsigned pc); - unsigned num_irqs; - int default_vector; - int *icount; - double overclock; - int no_int, irq_int, nmi_int; - int (*memory_read)(int offset); - void (*memory_write)(int offset, int data); - void (*set_op_base)(int pc); - int address_shift; - unsigned address_bits, endianess, align_unit, max_inst_len; - unsigned abits1, abits2, abitsmin; -}; - -extern struct cpu_interface cpuintf[]; - -void cpu_init(void); -void cpu_run(void); - -/* optional watchdog */ -void watchdog_reset_w(int offset,int data); -int watchdog_reset_r(int offset); -/* Use this function to reset the machine */ -void machine_reset(void); -/* Use this function to reset a single CPU */ -void cpu_set_reset_line(int cpu,int state); -/* Use this function to halt a single CPU */ -void cpu_set_halt_line(int cpu,int state); - -/* This function returns CPUNUM current status (running or halted) */ -int cpu_getstatus(int cpunum); -int cpu_gettotalcpu(void); -int cpu_getactivecpu(void); -void cpu_setactivecpu(int cpunum); - -/* Returns the current program counter */ -unsigned cpu_get_pc(void); -/* Set the current program counter */ -void cpu_set_pc(unsigned val); - -/* Returns the current stack pointer */ -unsigned cpu_get_sp(void); -/* Set the current stack pointer */ -void cpu_set_sp(unsigned val); - -/* Get the active CPUs context and return it's size */ -unsigned cpu_get_context(void *context); -/* Set the active CPUs context */ -void cpu_set_context(void *context); - -/* Returns a specific register value (mamedbg) */ -unsigned cpu_get_reg(int regnum); -/* Sets a specific register value (mamedbg) */ -void cpu_set_reg(int regnum, unsigned val); - -/* Returns previous pc (start of opcode causing read/write) */ -/* int cpu_getpreviouspc(void); */ -#define cpu_getpreviouspc() cpu_get_reg(REG_PREVIOUSPC) - -/* Returns the return address from the top of the stack (Z80 only) */ -/* int cpu_getreturnpc(void); */ -/* This can now be handled with a generic function */ -#define cpu_geturnpc() cpu_get_reg(REG_SP_CONTENTS) - -int cycles_currently_ran(void); -int cycles_left_to_run(void); - -/* Returns the number of CPU cycles which take place in one video frame */ -int cpu_gettotalcycles(void); -/* Returns the number of CPU cycles before the next interrupt handler call */ -int cpu_geticount(void); -/* Returns the number of CPU cycles before the end of the current video frame */ -int cpu_getfcount(void); -/* Returns the number of CPU cycles in one video frame */ -int cpu_getfperiod(void); -/* Scales a given value by the ratio of fcount / fperiod */ -int cpu_scalebyfcount(int value); -/* Returns the current scanline number */ -int cpu_getscanline(void); -/* Returns the amount of time until a given scanline */ -double cpu_getscanlinetime(int scanline); -/* Returns the duration of a single scanline */ -double cpu_getscanlineperiod(void); -/* Returns the duration of a single scanline in cycles */ -int cpu_getscanlinecycles(void); -/* Returns the number of cycles since the beginning of this frame */ -int cpu_getcurrentcycles(void); -/* Returns the current horizontal beam position in pixels */ -int cpu_gethorzbeampos(void); -/* - Returns the number of times the interrupt handler will be called before - the end of the current video frame. This is can be useful to interrupt - handlers to synchronize their operation. If you call this from outside - an interrupt handler, add 1 to the result, i.e. if it returns 0, it means - that the interrupt handler will be called once. -*/ -int cpu_getiloops(void); - -/* Returns the current VBLANK state */ -int cpu_getvblank(void); - -/* Returns the number of the video frame we are currently playing */ -int cpu_getcurrentframe(void); - - -/* generate a trigger after a specific period of time */ -void cpu_triggertime (double duration, int trigger); -/* generate a trigger now */ -void cpu_trigger (int trigger); - -/* burn CPU cycles until a timer trigger */ -void cpu_spinuntil_trigger (int trigger); -/* burn CPU cycles until the next interrupt */ -void cpu_spinuntil_int (void); -/* burn CPU cycles until our timeslice is up */ -void cpu_spin (void); -/* burn CPU cycles for a specific period of time */ -void cpu_spinuntil_time (double duration); - -/* yield our timeslice for a specific period of time */ -void cpu_yielduntil_trigger (int trigger); -/* yield our timeslice until the next interrupt */ -void cpu_yielduntil_int (void); -/* yield our current timeslice */ -void cpu_yield (void); -/* yield our timeslice for a specific period of time */ -void cpu_yielduntil_time (double duration); - -/* set the NMI line state for a CPU, normally use PULSE_LINE */ -void cpu_set_nmi_line(int cpunum, int state); -/* set the IRQ line state for a specific irq line of a CPU */ -/* normally use state HOLD_LINE, irqline 0 for first IRQ type of a cpu */ -void cpu_set_irq_line(int cpunum, int irqline, int state); -/* this is to be called by CPU cores only! */ -void cpu_generate_internal_interrupt(int cpunum, int type); -/* set the vector to be returned during a CPU's interrupt acknowledge cycle */ -void cpu_irq_line_vector_w(int cpunum, int irqline, int vector); - -/* use these in your write memory/port handles to set an IRQ vector */ -/* offset corresponds to the irq line number here */ -void cpu_0_irq_line_vector_w(int offset, int data); -void cpu_1_irq_line_vector_w(int offset, int data); -void cpu_2_irq_line_vector_w(int offset, int data); -void cpu_3_irq_line_vector_w(int offset, int data); -void cpu_4_irq_line_vector_w(int offset, int data); -void cpu_5_irq_line_vector_w(int offset, int data); -void cpu_6_irq_line_vector_w(int offset, int data); -void cpu_7_irq_line_vector_w(int offset, int data); - -/* Obsolete functions: avoid to use them in new drivers if possible. */ - -/* cause an interrupt on a CPU */ -void cpu_cause_interrupt(int cpu,int type); -void cpu_clear_pending_interrupts(int cpu); -void interrupt_enable_w(int offset,int data); -void interrupt_vector_w(int offset,int data); -int interrupt(void); -int nmi_interrupt(void); -int m68_level1_irq(void); -int m68_level2_irq(void); -int m68_level3_irq(void); -int m68_level4_irq(void); -int m68_level5_irq(void); -int m68_level6_irq(void); -int m68_level7_irq(void); -int ignore_interrupt(void); - -/* CPU context access */ -void* cpu_getcontext (int _activecpu); -int cpu_is_saving_context(int _activecpu); - -/*************************************************************************** - * Get information for the currently active CPU - * cputype is a value from the CPU enum in driver.h - ***************************************************************************/ -/* Return number of address bits */ -unsigned cpu_address_bits(void); -/* Return address mask */ -unsigned cpu_address_mask(void); -/* Return address shift factor (TMS34010 bit addressing mode) */ -int cpu_address_shift(void); -/* Return endianess of the emulated CPU (CPU_IS_LE or CPU_IS_BE) */ -unsigned cpu_endianess(void); -/* Return opcode align unit (1 byte, 2 word, 4 dword) */ -unsigned cpu_align_unit(void); -/* Return maximum instruction length */ -unsigned cpu_max_inst_len(void); - -/* Return name of the active CPU */ -const char *cpu_name(void); -/* Return family name of the active CPU */ -const char *cpu_core_family(void); -/* Return core version of the active CPU */ -const char *cpu_core_version(void); -/* Return core filename of the active CPU */ -const char *cpu_core_file(void); -/* Return credits info for of the active CPU */ -const char *cpu_core_credits(void); -/* Return register layout definition for the active CPU */ -const char *cpu_reg_layout(void); -/* Return (debugger) window layout definition for the active CPU */ -const char *cpu_win_layout(void); - -/* Disassemble an instruction at PC into the given buffer */ -unsigned cpu_dasm(char *buffer, unsigned pc); -/* Return a string describing the currently set flag (status) bits of the active CPU */ -const char *cpu_flags(void); -/* Return a string with a register name and hex value for the active CPU */ -/* regnum is a value defined in the CPU cores header files */ -const char *cpu_dump_reg(int regnum); -/* Return a string describing the active CPUs current state */ -const char *cpu_dump_state(void); - -/*************************************************************************** - * Get information for a specific CPU type - * cputype is a value from the CPU enum in driver.h - ***************************************************************************/ -/* Return address shift factor */ -/* TMS320C10 -1: word addressing mode, TMS34010 3: bit addressing mode */ -int cputype_address_shift(int cputype); -/* Return number of address bits */ -unsigned cputype_address_bits(int cputype); -/* Return address mask */ -unsigned cputype_address_mask(int cputype); -/* Return endianess of the emulated CPU (CPU_IS_LE or CPU_IS_BE) */ -unsigned cputype_endianess(int cputype); -/* Return opcode align unit (1 byte, 2 word, 4 dword) */ -unsigned cputype_align_unit(int cputype); -/* Return maximum instruction length */ -unsigned cputype_max_inst_len(int cputype); - -/* Return name of the CPU */ -const char *cputype_name(int cputype); -/* Return family name of the CPU */ -const char *cputype_core_family(int cputype); -/* Return core version number of the CPU */ -const char *cputype_core_version(int cputype); -/* Return core filename of the CPU */ -const char *cputype_core_file(int cputype); -/* Return credits for the CPU core */ -const char *cputype_core_credits(int cputype); -/* Return register layout definition for the CPU core */ -const char *cputype_reg_layout(int cputype); -/* Return (debugger) window layout definition for the CPU core */ -const char *cputype_win_layout(int cputype); - -/*************************************************************************** - * Get (or set) information for a numbered CPU of the running machine - * cpunum is a value between 0 and cpu_gettotalcpu() - 1 - ***************************************************************************/ -/* Return number of address bits */ -unsigned cpunum_address_bits(int cputype); -/* Return address mask */ -unsigned cpunum_address_mask(int cputype); -/* Return endianess of the emulated CPU (CPU_LSB_FIRST or CPU_MSB_FIRST) */ -unsigned cpunum_endianess(int cputype); -/* Return opcode align unit (1 byte, 2 word, 4 dword) */ -unsigned cpunum_align_unit(int cputype); -/* Return maximum instruction length */ -unsigned cpunum_max_inst_len(int cputype); - -/* Get a register value for the specified CPU number of the running machine */ -unsigned cpunum_get_reg(int cpunum, int regnum); -/* Set a register value for the specified CPU number of the running machine */ -void cpunum_set_reg(int cpunum, int regnum, unsigned val); - -/* Return (debugger) register layout definition for the CPU core */ -const char *cpunum_reg_layout(int cpunum); -/* Return (debugger) window layout definition for the CPU core */ -const char *cpunum_win_layout(int cpunum); - -unsigned cpunum_dasm(int cpunum,char *buffer,unsigned pc); -/* Return a string describing the currently set flag (status) bits of the CPU */ -const char *cpunum_flags(int cpunum); -/* Return a string with a register name and value */ -/* regnum is a value defined in the CPU cores header files */ -const char *cpunum_dump_reg(int cpunum, int regnum); -/* Return a string describing the CPUs current state */ -const char *cpunum_dump_state(int cpunum); -/* Return a name for the specified cpu number */ -const char *cpunum_name(int cpunum); -/* Return a family name for the specified cpu number */ -const char *cpunum_core_family(int cpunum); -/* Return a version for the specified cpu number */ -const char *cpunum_core_version(int cpunum); -/* Return a the source filename for the specified cpu number */ -const char *cpunum_core_file(int cpunum); -/* Return a the credits for the specified cpu number */ -const char *cpunum_core_credits(int cpunum); - -/* Dump all of the running machines CPUs state to stderr */ -void cpu_dump_states(void); - -/* daisy-chain link */ -typedef struct { - void (*reset)(int); /* reset callback */ - int (*interrupt_entry)(int); /* entry callback */ - void (*interrupt_reti)(int); /* reti callback */ - int irq_param; /* callback paramater */ -} Z80_DaisyChain; - -#define Z80_MAXDAISY 4 /* maximum of daisy chan device */ - -#define Z80_INT_REQ 0x01 /* interrupt request mask */ -#define Z80_INT_IEO 0x02 /* interrupt disable mask(IEO) */ - -#define Z80_VECTOR(device,state) (((device)<<8)|(state)) - -#ifndef INLINE -#define INLINE inline -#endif - -#include -#include -#include - -#define cpu_readmem16 memory_read -#define cpu_readport16 memory_readport -#define cpu_writeport16 memory_writeport -#define cpu_writemem16 memory_write -#define cpu_readop memory_readop -#define cpu_readop_arg memory_read -#define logerror(x, ...) -#define change_pc16(x) -#define CALL_MAME_DEBUG - -#define ADDRESS_SPACES 3 /* maximum number of address spaces */ -#define ADDRESS_SPACE_PROGRAM 0 /* program address space */ -#define ADDRESS_SPACE_DATA 1 /* data address space */ -#define ADDRESS_SPACE_IO 2 /* I/O address space */ - -enum -{ - /* internal flags (not for use by drivers!) */ - INTERNAL_CLEAR_LINE = 100 + CLEAR_LINE, - INTERNAL_ASSERT_LINE = 100 + ASSERT_LINE, - - /* input lines */ - MAX_INPUT_LINES = 32+3, - INPUT_LINE_IRQ0 = 0, - INPUT_LINE_IRQ1 = 1, - INPUT_LINE_IRQ2 = 2, - INPUT_LINE_IRQ3 = 3, - INPUT_LINE_IRQ4 = 4, - INPUT_LINE_IRQ5 = 5, - INPUT_LINE_IRQ6 = 6, - INPUT_LINE_IRQ7 = 7, - INPUT_LINE_IRQ8 = 8, - INPUT_LINE_IRQ9 = 9, - INPUT_LINE_NMI = MAX_INPUT_LINES - 3, - - /* special input lines that are implemented in the core */ - INPUT_LINE_RESET = MAX_INPUT_LINES - 2, - INPUT_LINE_HALT = MAX_INPUT_LINES - 1, - - /* output lines */ - MAX_OUTPUT_LINES = 32 -}; - -enum -{ - /* --- the following bits of info are returned as 64-bit signed integers --- */ - CPUINFO_INT_FIRST = 0x00000, - - CPUINFO_INT_CONTEXT_SIZE = CPUINFO_INT_FIRST, /* R/O: size of CPU context in bytes */ - CPUINFO_INT_INPUT_LINES, /* R/O: number of input lines */ - CPUINFO_INT_OUTPUT_LINES, /* R/O: number of output lines */ - CPUINFO_INT_DEFAULT_IRQ_VECTOR, /* R/O: default IRQ vector */ - CPUINFO_INT_ENDIANNESS, /* R/O: either CPU_IS_BE or CPU_IS_LE */ - CPUINFO_INT_CLOCK_DIVIDER, /* R/O: internal clock divider */ - CPUINFO_INT_MIN_INSTRUCTION_BYTES, /* R/O: minimum bytes per instruction */ - CPUINFO_INT_MAX_INSTRUCTION_BYTES, /* R/O: maximum bytes per instruction */ - CPUINFO_INT_MIN_CYCLES, /* R/O: minimum cycles for a single instruction */ - CPUINFO_INT_MAX_CYCLES, /* R/O: maximum cycles for a single instruction */ - - CPUINFO_INT_DATABUS_WIDTH, /* R/O: data bus size for each address space (8,16,32,64) */ - CPUINFO_INT_DATABUS_WIDTH_LAST = CPUINFO_INT_DATABUS_WIDTH + ADDRESS_SPACES - 1, - CPUINFO_INT_ADDRBUS_WIDTH, /* R/O: address bus size for each address space (12-32) */ - CPUINFO_INT_ADDRBUS_WIDTH_LAST = CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACES - 1, - CPUINFO_INT_ADDRBUS_SHIFT, /* R/O: shift applied to addresses each address space (+3 means >>3, -1 means <<1) */ - CPUINFO_INT_ADDRBUS_SHIFT_LAST = CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACES - 1, - - CPUINFO_INT_SP, /* R/W: the current stack pointer value */ - CPUINFO_INT_PC, /* R/W: the current PC value */ - CPUINFO_INT_PREVIOUSPC, /* R/W: the previous PC value */ - CPUINFO_INT_INPUT_STATE, /* R/W: states for each input line */ - CPUINFO_INT_INPUT_STATE_LAST = CPUINFO_INT_INPUT_STATE + MAX_INPUT_LINES - 1, - CPUINFO_INT_OUTPUT_STATE, /* R/W: states for each output line */ - CPUINFO_INT_OUTPUT_STATE_LAST = CPUINFO_INT_OUTPUT_STATE + MAX_OUTPUT_LINES - 1, - CPUINFO_INT_REGISTER, /* R/W: values of up to MAX_REGs registers */ - CPUINFO_INT_REGISTER_LAST = CPUINFO_INT_REGISTER + MAX_REGS - 1, - - CPUINFO_INT_CPU_SPECIFIC = 0x08000, /* R/W: CPU-specific values start here */ - - /* --- the following bits of info are returned as pointers to data or functions --- */ - CPUINFO_PTR_FIRST = 0x10000, - - CPUINFO_PTR_SET_INFO = CPUINFO_PTR_FIRST, /* R/O: void (*set_info)(UINT32 state, INT64 data, void *ptr) */ - CPUINFO_PTR_GET_CONTEXT, /* R/O: void (*get_context)(void *buffer) */ - CPUINFO_PTR_SET_CONTEXT, /* R/O: void (*set_context)(void *buffer) */ - CPUINFO_PTR_INIT, /* R/O: void (*init)(void) */ - CPUINFO_PTR_RESET, /* R/O: void (*reset)(void *param) */ - CPUINFO_PTR_EXIT, /* R/O: void (*exit)(void) */ - CPUINFO_PTR_EXECUTE, /* R/O: int (*execute)(int cycles) */ - CPUINFO_PTR_BURN, /* R/O: void (*burn)(int cycles) */ - CPUINFO_PTR_DISASSEMBLE, /* R/O: void (*disassemble)(char *buffer, offs_t pc) */ - CPUINFO_PTR_IRQ_CALLBACK, /* R/W: int (*irqcallback)(int state) */ - CPUINFO_PTR_INSTRUCTION_COUNTER, /* R/O: int *icount */ - CPUINFO_PTR_REGISTER_LAYOUT, /* R/O: struct debug_register_layout *layout */ - CPUINFO_PTR_WINDOW_LAYOUT, /* R/O: struct debug_window_layout *layout */ - CPUINFO_PTR_INTERNAL_MEMORY_MAP, /* R/O: construct_map_t map */ - CPUINFO_PTR_INTERNAL_MEMORY_MAP_LAST = CPUINFO_PTR_INTERNAL_MEMORY_MAP + ADDRESS_SPACES - 1, - CPUINFO_PTR_DEBUG_REGISTER_LIST, /* R/O: int *list: list of registers for NEW_DEBUGGER */ - - CPUINFO_PTR_CPU_SPECIFIC = 0x18000, /* R/W: CPU-specific values start here */ - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - CPUINFO_STR_FIRST = 0x20000, - - CPUINFO_STR_NAME = CPUINFO_STR_FIRST, /* R/O: name of the CPU */ - CPUINFO_STR_CORE_FAMILY, /* R/O: family of the CPU */ - CPUINFO_STR_CORE_VERSION, /* R/O: version of the CPU core */ - CPUINFO_STR_CORE_FILE, /* R/O: file containing the CPU core */ - CPUINFO_STR_CORE_CREDITS, /* R/O: credits for the CPU core */ - CPUINFO_STR_FLAGS, /* R/O: string representation of the main flags value */ - CPUINFO_STR_REGISTER, /* R/O: string representation of up to MAX_REGs registers */ - CPUINFO_STR_REGISTER_LAST = CPUINFO_STR_REGISTER + MAX_REGS - 1, - - CPUINFO_STR_CPU_SPECIFIC = 0x28000 /* R/W: CPU-specific values start here */ -}; - -#endif /* CPUINTRF_H */ diff --git a/Frameworks/AudioOverload/aosdk/dsnd.c b/Frameworks/AudioOverload/aosdk/dsnd.c deleted file mode 100644 index 96971e7cf..000000000 --- a/Frameworks/AudioOverload/aosdk/dsnd.c +++ /dev/null @@ -1,365 +0,0 @@ -/* - - Audio Overload SDK - - Copyright (c) 2007, R. Belmont and Richard Bannister. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - * Neither the names of R. Belmont and Richard Bannister nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#include -#include -#include - -#include "cpuintrf.h" -#include "oss.h" -#include "ao.h" - -static INT16 samples[44100*4]; // make sure we reserve enough for worst-case scenario - -void (*m1sdr_Callback)(unsigned long dwSamples, short *samples); -unsigned long cbUserData; - -static int hw_present, playtime; - -LPDIRECTSOUND lpDS; // DirectSound COM object -LPDIRECTSOUNDBUFFER lpPDSB; // Primary DirectSound buffer -LPDIRECTSOUNDBUFFER lpSecB; // Secondary DirectSound buffer - -int nDSoundSamRate=44100; // sample rate -int nDSoundSegCount=16; // Segs in the pdsbLoop buffer -static int cbLoopLen=0; // Loop length (in bytes) calculated - -int nDSoundFps=600; // Application fps * 10 -int nDSoundSegLen=0; // Seg length in samples (calculated from Rate/Fps) -short *DSoundNextSound=NULL; // The next sound seg we will add to the sample loop -unsigned char bDSoundOkay=0; // True if DSound was initted okay -unsigned char bDSoundPlaying=0; // True if the Loop buffer is playing - -#define WRAP_INC(x) { x++; if (x>=nDSoundSegCount) x=0; } - -static int nDSoundNextSeg=0; // We have filled the sound in the loop up to the beginning of 'nNextSeg' - -void m1sdr_SetSamplesPerTick(UINT32 spf) -{ - if (spf != (nDSoundFps/10)) - { - m1sdr_Exit(); - nDSoundFps = spf * 10; - m1sdr_Init(nDSoundSamRate); - } -} - -void m1sdr_TimeCheck(void) -{ - int nPlaySeg=0, nFollowingSeg=0; - DWORD nPlay=0, nWrite=0; - int nRet=0; - - if (!lpDS) return; - - // We should do nothing until nPlay has left nDSoundNextSeg - IDirectSoundBuffer_GetCurrentPosition(lpSecB, &nPlay, &nWrite); - - nPlaySeg=nPlay/(nDSoundSegLen<<2); - - if (nPlaySeg>nDSoundSegCount-1) nPlaySeg=nDSoundSegCount-1; - if (nPlaySeg<0) nPlaySeg=0; // important to ensure nPlaySeg clipped for below - - if (nDSoundNextSeg == nPlaySeg) - { - Sleep(200); // Don't need to do anything for a bit - goto End; - } - - // work out which seg we will fill next - nFollowingSeg = nDSoundNextSeg; - WRAP_INC(nFollowingSeg) - - while (nDSoundNextSeg != nPlaySeg) - { - void *pData=NULL,*pData2=NULL; DWORD cbLen=0,cbLen2=0; - - // fill nNextSeg - // Lock the relevant seg of the loop buffer - nRet = IDirectSoundBuffer_Lock(lpSecB, nDSoundNextSeg*(nDSoundSegLen<<2), nDSoundSegLen<<2, &pData, &cbLen, &pData2, &cbLen2, 0); - - if (nRet>=0 && pData!=NULL) - { - // Locked the seg okay - write the sound we calculated last time - memcpy(pData, samples, nDSoundSegLen<<2); - } - // Unlock (2nd 0 is because we wrote nothing to second part) - if (nRet>=0) IDirectSoundBuffer_Unlock(lpSecB, pData, cbLen, pData2, 0); - - // generate more samples - if (m1sdr_Callback) - { - m1sdr_Callback(nDSoundSegLen, samples); - playtime++; - } - else - { - memset(samples, 0, nDSoundSegLen*4); - } - - nDSoundNextSeg = nFollowingSeg; - WRAP_INC(nFollowingSeg) - } - -End: - return; -} - -INT16 m1sdr_Init(int sample_rate) -{ - DSBUFFERDESC dsbuf; - WAVEFORMATEX format; - - nDSoundSamRate = sample_rate; - - lpDS = NULL; - lpPDSB = NULL; - lpSecB = NULL; - - // Calculate the Seg Length and Loop length - // (round to nearest sample) - nDSoundSegLen=(nDSoundSamRate*10+(nDSoundFps>>1))/nDSoundFps; - cbLoopLen=(nDSoundSegLen*nDSoundSegCount)<<2; - - // create an IDirectSound COM object - - if (DS_OK != DirectSoundCreate(NULL, &lpDS, NULL)) - { - printf("Unable to create DirectSound object!\n"); - return(0); - } - - // set cooperative level where we need it - - if (DS_OK != IDirectSound_SetCooperativeLevel(lpDS, GetForegroundWindow(), DSSCL_PRIORITY)) - { - printf("Unable to set cooperative level!\n"); - return(0); - } - - // now create a primary sound buffer - memset(&format, 0, sizeof(format)); - format.wFormatTag = WAVE_FORMAT_PCM; - format.nChannels = 2; - format.wBitsPerSample = 16; - format.nSamplesPerSec = nDSoundSamRate; - format.nBlockAlign = 4; // stereo 16-bit - format.cbSize = 0; - format.nAvgBytesPerSec=format.nSamplesPerSec*format.nBlockAlign; - - memset(&dsbuf, 0, sizeof(dsbuf)); - dsbuf.dwSize = sizeof(DSBUFFERDESC); - dsbuf.dwFlags = DSBCAPS_PRIMARYBUFFER; - dsbuf.dwBufferBytes = 0; - dsbuf.lpwfxFormat = NULL; - - if (DS_OK != IDirectSound_CreateSoundBuffer(lpDS, &dsbuf, &lpPDSB, NULL)) - { - printf("Unable to create primary buffer!"); - return(0); - } - - // and set it's format how we want - - if (DS_OK != IDirectSoundBuffer_SetFormat(lpPDSB, &format)) - { - printf("Unable to set primary buffer format!\n"); - return(0); - } - - // start the primary buffer playing now so we get - // minimal lag when we trigger our secondary buffer - - IDirectSoundBuffer_Play(lpPDSB, 0, 0, DSBPLAY_LOOPING); - - // that's done, now let's create our secondary buffer - - memset(&dsbuf, 0, sizeof(DSBUFFERDESC)); - dsbuf.dwSize = sizeof(DSBUFFERDESC); - - // we'll take default controls for this one - dsbuf.dwFlags = DSBCAPS_GLOBALFOCUS | DSBCAPS_GETCURRENTPOSITION2 | DSBCAPS_CTRLPOSITIONNOTIFY; - dsbuf.dwBufferBytes = cbLoopLen; - dsbuf.lpwfxFormat = (LPWAVEFORMATEX)&format; - - if (DS_OK != IDirectSound_CreateSoundBuffer(lpDS, &dsbuf, &lpSecB, NULL)) - { - printf("Unable to create secondary buffer\n"); - return(0); - } - - // ok, cool, we're ready to go! - // blank out the entire sound buffer - { - LPVOID ptr; DWORD len; - - IDirectSoundBuffer_Lock(lpSecB, 0, 0, &ptr, &len, NULL, NULL, DSBLOCK_ENTIREBUFFER); - ZeroMemory(ptr, len); - IDirectSoundBuffer_Unlock(lpSecB, ptr, len, 0, 0); - } - - ZeroMemory(samples, nDSoundSegLen<<2); - - bDSoundOkay=1; // This module was initted okay - - return(1); -} - -void m1sdr_Exit(void) -{ - if (lpSecB) - { - IDirectSoundBuffer_Stop(lpSecB); - IDirectSoundBuffer_Release(lpSecB); - lpSecB = NULL; - } - if (lpPDSB) - { - IDirectSoundBuffer_Stop(lpPDSB); - IDirectSoundBuffer_Release(lpPDSB); - lpPDSB = NULL; - } - if (lpDS) - { - IDirectSound_Release(lpDS); - lpDS = NULL; - } -} - - - -void m1sdr_PlayStart(void) -{ - IDirectSound_SetCooperativeLevel(lpDS, GetForegroundWindow(), DSSCL_PRIORITY); - - IDirectSoundBuffer_SetCurrentPosition(lpSecB, 0); - IDirectSoundBuffer_Play(lpSecB, 0, 0, DSBPLAY_LOOPING); - - playtime = 0; -} - -void m1sdr_PlayStop(void) -{ - DSBUFFERDESC dsbuf; - WAVEFORMATEX format; - - IDirectSoundBuffer_Stop(lpSecB); - // this is a bit cheezity-hacky - IDirectSoundBuffer_Release(lpSecB); - - memset(&format, 0, sizeof(format)); - format.wFormatTag = WAVE_FORMAT_PCM; - format.nChannels = 2; - format.wBitsPerSample = 16; - format.nSamplesPerSec = nDSoundSamRate; - format.nBlockAlign = 4; // stereo 16-bit - format.cbSize = 0; - format.nAvgBytesPerSec=format.nSamplesPerSec*format.nBlockAlign; - - memset(&dsbuf, 0, sizeof(DSBUFFERDESC)); - dsbuf.dwSize = sizeof(DSBUFFERDESC); - // we'll take default controls for this one - dsbuf.dwFlags = DSBCAPS_GLOBALFOCUS | DSBCAPS_GETCURRENTPOSITION2 | DSBCAPS_CTRLPOSITIONNOTIFY; - dsbuf.dwBufferBytes = cbLoopLen; - dsbuf.lpwfxFormat = (LPWAVEFORMATEX)&format; - - if (DS_OK != IDirectSound_CreateSoundBuffer(lpDS, &dsbuf, &lpSecB, NULL)) - { - printf("Unable to create secondary buffer\n"); - return; - } - - // zero out the buffer - { - LPVOID ptr; DWORD len; - - IDirectSoundBuffer_Lock(lpSecB, 0, 0, &ptr, &len, NULL, NULL, DSBLOCK_ENTIREBUFFER); - ZeroMemory(ptr, len); - IDirectSoundBuffer_Unlock(lpSecB, ptr, len, 0, 0); - } -} - - -INT32 m1sdr_HwPresent(void) -{ - return hw_present; -} - -INT16 m1sdr_IsThere(void) -{ - if(DS_OK == DirectSoundCreate(NULL, &lpDS, NULL)) - { - IDirectSound_Release(lpDS); - hw_present = 1; - return(1); - } - else - { - hw_present = 0; - return(0); - } -} - -void m1sdr_SetCallback(void *fn) -{ - if (fn == (void *)NULL) - { - printf("ERROR: NULL CALLBACK!\n"); - } - - m1sdr_Callback = (void (*)(unsigned long, signed short *))fn; -} - -void m1sdr_FlushAudio(void) -{ - memset(samples, 0, nDSoundSegLen * 4); - m1sdr_TimeCheck(); - m1sdr_TimeCheck(); - m1sdr_TimeCheck(); - m1sdr_TimeCheck(); - m1sdr_TimeCheck(); -} - -short *m1sdr_GetSamples(void) -{ - return samples; -} - -int m1sdr_GetPlayTime(void) -{ - int rv; - int fps = nDSoundFps / 10; - - rv = playtime / fps; - - return rv; // total seconds -} - -int m1sdr_GetPlayTimeTicks(void) -{ - return playtime; -} diff --git a/Frameworks/AudioOverload/aosdk/eng_dsf/aica.c b/Frameworks/AudioOverload/aosdk/eng_dsf/aica.c deleted file mode 100644 index a9b5e37c9..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_dsf/aica.c +++ /dev/null @@ -1,1282 +0,0 @@ -/* - Sega/Yamaha AICA emulation - By ElSemi, kingshriek, and R. Belmont - - This is effectively a 64-voice SCSP, with the following differences: - - No FM mode - - A third sample format (ADPCM) has been added - - Some minor other tweeks -*/ - -#include -#include -#include "ao.h" -#include "cpuintrf.h" -#include "aica.h" -#include "aicadsp.h" -#include "dc_hw.h" - -#define ICLIP16(x) (x<-32768)?-32768:((x>32767)?32767:x) - -#define SHIFT 12 -#define FIX(v) ((UINT32) ((float) (1<udata.data[0x0]>>0x0)&0x8000) -#define KEYONB(slot) ((slot->udata.data[0x0]>>0x0)&0x4000) -#define SSCTL(slot) ((slot->udata.data[0x0]>>0xA)&0x0001) -#define LPCTL(slot) ((slot->udata.data[0x0]>>0x9)&0x0001) -#define PCMS(slot) ((slot->udata.data[0x0]>>0x7)&0x0003) - -#define SA(slot) (((slot->udata.data[0x0]&0x7F)<<16)|(slot->udata.data[0x4/2])) - -#define LSA(slot) (slot->udata.data[0x8/2]) - -#define LEA(slot) (slot->udata.data[0xc/2]) - -#define D2R(slot) ((slot->udata.data[0x10/2]>>0xB)&0x001F) -#define D1R(slot) ((slot->udata.data[0x10/2]>>0x6)&0x001F) -#define AR(slot) ((slot->udata.data[0x10/2]>>0x0)&0x001F) - -#define LPSLNK(slot) ((slot->udata.data[0x14/2]>>0x0)&0x4000) -#define KRS(slot) ((slot->udata.data[0x14/2]>>0xA)&0x000F) -#define DL(slot) ((slot->udata.data[0x14/2]>>0x5)&0x001F) -#define RR(slot) ((slot->udata.data[0x14/2]>>0x0)&0x001F) - -#define TL(slot) ((slot->udata.data[0x28/2]>>0x8)&0x00FF) - -#define OCT(slot) ((slot->udata.data[0x18/2]>>0xB)&0x000F) -#define FNS(slot) ((slot->udata.data[0x18/2]>>0x0)&0x03FF) - -#define LFORE(slot) ((slot->udata.data[0x1c/2]>>0x0)&0x8000) -#define LFOF(slot) ((slot->udata.data[0x1c/2]>>0xA)&0x001F) -#define PLFOWS(slot) ((slot->udata.data[0x1c/2]>>0x8)&0x0003) -#define PLFOS(slot) ((slot->udata.data[0x1c/2]>>0x5)&0x0007) -#define ALFOWS(slot) ((slot->udata.data[0x1c/2]>>0x3)&0x0003) -#define ALFOS(slot) ((slot->udata.data[0x1c/2]>>0x0)&0x0007) - -#define ISEL(slot) ((slot->udata.data[0x20/2]>>0x0)&0x000F) -#define IMXL(slot) ((slot->udata.data[0x20/2]>>0x4)&0x000F) - -#define DISDL(slot) ((slot->udata.data[0x24/2]>>0x8)&0x000F) -#define DIPAN(slot) ((slot->udata.data[0x24/2]>>0x0)&0x001F) - -#define EFSDL(slot) ((AICA->EFSPAN[slot*4]>>8)&0x000f) -#define EFPAN(slot) ((AICA->EFSPAN[slot*4]>>0)&0x001f) - -//Envelope times in ms -static const double ARTimes[64]={100000/*infinity*/,100000/*infinity*/,8100.0,6900.0,6000.0,4800.0,4000.0,3400.0,3000.0,2400.0,2000.0,1700.0,1500.0, - 1200.0,1000.0,860.0,760.0,600.0,500.0,430.0,380.0,300.0,250.0,220.0,190.0,150.0,130.0,110.0,95.0, - 76.0,63.0,55.0,47.0,38.0,31.0,27.0,24.0,19.0,15.0,13.0,12.0,9.4,7.9,6.8,6.0,4.7,3.8,3.4,3.0,2.4, - 2.0,1.8,1.6,1.3,1.1,0.93,0.85,0.65,0.53,0.44,0.40,0.35,0.0,0.0}; -static const double DRTimes[64]={100000/*infinity*/,100000/*infinity*/,118200.0,101300.0,88600.0,70900.0,59100.0,50700.0,44300.0,35500.0,29600.0,25300.0,22200.0,17700.0, - 14800.0,12700.0,11100.0,8900.0,7400.0,6300.0,5500.0,4400.0,3700.0,3200.0,2800.0,2200.0,1800.0,1600.0,1400.0,1100.0, - 920.0,790.0,690.0,550.0,460.0,390.0,340.0,270.0,230.0,200.0,170.0,140.0,110.0,98.0,85.0,68.0,57.0,49.0,43.0,34.0, - 28.0,25.0,22.0,18.0,14.0,12.0,11.0,8.5,7.1,6.1,5.4,4.3,3.6,3.1}; -static UINT32 FNS_Table[0x400]; -static INT32 EG_TABLE[0x400]; - -typedef enum {ATTACK,DECAY1,DECAY2,RELEASE} _STATE; -struct _EG -{ - int volume; // - _STATE state; - int step; - //step vals - int AR; //Attack - int D1R; //Decay1 - int D2R; //Decay2 - int RR; //Release - - int DL; //Decay level - UINT8 LPLINK; -}; - -struct _SLOT -{ - union - { - UINT16 data[0x40]; //only 0x1a bytes used - UINT8 datab[0x80]; - } udata; - UINT8 active; //this slot is currently playing - UINT8 *base; //samples base address - UINT32 prv_addr; // previous play address (for ADPCM) - UINT32 cur_addr; //current play address (24.8) - UINT32 nxt_addr; //next play address - UINT32 step; //pitch step (24.8) - UINT8 Backwards; //the wave is playing backwards - struct _EG EG; //Envelope - struct _EG FEG; //filter envelope - struct _LFO PLFO; //Phase LFO - struct _LFO ALFO; //Amplitude LFO - int slot; - int cur_sample; //current ADPCM sample - int cur_quant; //current ADPCM step - int curstep; - int cur_lpquant, cur_lpsample, cur_lpstep; - UINT8 *adbase, *adlpbase; - UINT8 mslc; // monitored? -}; - - -#define MEM4B(aica) ((aica->udata.data[0]>>0x0)&0x0200) -#define DAC18B(aica) ((aica->udata.data[0]>>0x0)&0x0100) -#define MVOL(aica) ((aica->udata.data[0]>>0x0)&0x000F) -#define RBL(aica) ((aica->udata.data[2]>>0xD)&0x0003) -#define RBP(aica) ((aica->udata.data[2]>>0x0)&0x0fff) -#define MOFULL(aica) ((aica->udata.data[4]>>0x0)&0x1000) -#define MOEMPTY(aica) ((aica->udata.data[4]>>0x0)&0x0800) -#define MIOVF(aica) ((aica->udata.data[4]>>0x0)&0x0400) -#define MIFULL(aica) ((aica->udata.data[4]>>0x0)&0x0200) -#define MIEMPTY(aica) ((aica->udata.data[4]>>0x0)&0x0100) - -#define AFSEL(aica) ((aica->udata.data[6]>>0x0)&0x4000) -#define MSLC(aica) ((aica->udata.data[6]>>0x8)&0x3F) - -#define SCILV0(aica) ((aica->udata.data[0xa8/2]>>0x0)&0xff) -#define SCILV1(aica) ((aica->udata.data[0xac/2]>>0x0)&0xff) -#define SCILV2(aica) ((aica->udata.data[0xb0/2]>>0x0)&0xff) - -#define SCIEX0 0 -#define SCIEX1 1 -#define SCIEX2 2 -#define SCIMID 3 -#define SCIDMA 4 -#define SCIIRQ 5 -#define SCITMA 6 -#define SCITMB 7 - -struct _AICA -{ - union - { - UINT16 data[0xc0/2]; - UINT8 datab[0xc0]; - } udata; - UINT16 IRQL, IRQR; - UINT16 EFSPAN[0x48]; - struct _SLOT Slots[64]; - signed short RINGBUF[64]; - unsigned char BUFPTR; - unsigned char *AICARAM; - UINT32 AICARAM_LENGTH; - char Master; - void (*IntARMCB)(int irq); - - INT32 *buffertmpl, *buffertmpr; - - UINT32 IrqTimA; - UINT32 IrqTimBC; - UINT32 IrqMidi; - - UINT8 MidiOutW,MidiOutR; - UINT8 MidiStack[16]; - UINT8 MidiW,MidiR; - - int LPANTABLE[0x20000]; - int RPANTABLE[0x20000]; - - int TimPris[3]; - int TimCnt[3]; - - // DMA stuff - UINT32 aica_dmea; - UINT16 aica_drga; - UINT16 aica_dtlg; - - int ARTABLE[64], DRTABLE[64]; - - struct _AICADSP DSP; -}; - -static struct _AICA *AllocedAICA; - -static const float SDLT[16]={-1000000.0,-42.0,-39.0,-36.0,-33.0,-30.0,-27.0,-24.0,-21.0,-18.0,-15.0,-12.0,-9.0,-6.0,-3.0,0.0}; - -static INT16 *bufferl; -static INT16 *bufferr; - -static int length; - -static signed short *RBUFDST; //this points to where the sample will be stored in the RingBuf - -static unsigned char DecodeSCI(struct _AICA *AICA, unsigned char irq) -{ - unsigned char SCI=0; - unsigned char v; - v=(SCILV0((AICA))&(1<udata.data[0xa4/2]; - if (reset & 0x40) - AICA->IntARMCB(-AICA->IrqTimA); - if (reset & 0x180) - AICA->IntARMCB(-AICA->IrqTimBC); -#endif -} - -static void CheckPendingIRQ(struct _AICA *AICA) -{ - UINT32 pend=AICA->udata.data[0xa0/2]; - UINT32 en=AICA->udata.data[0x9c/2]; - if(AICA->MidiW!=AICA->MidiR) - { - AICA->IRQL = AICA->IrqMidi; - AICA->IntARMCB(1); - return; - } - if(!pend) - return; - if(pend&0x40) - if(en&0x40) - { - AICA->IRQL = AICA->IrqTimA; - AICA->IntARMCB(1); - return; - } - if(pend&0x80) - if(en&0x80) - { - AICA->IRQL = AICA->IrqTimBC; - AICA->IntARMCB(1); - return; - } - if(pend&0x100) - if(en&0x100) - { - AICA->IRQL = AICA->IrqTimBC; - AICA->IntARMCB(1); - return; - } -} - -static int Get_AR(struct _AICA *AICA,int base,int R) -{ - int Rate=base+(R<<1); - if(Rate>63) Rate=63; - if(Rate<0) Rate=0; - return AICA->ARTABLE[Rate]; -} - -static int Get_DR(struct _AICA *AICA,int base,int R) -{ - int Rate=base+(R<<1); - if(Rate>63) Rate=63; - if(Rate<0) Rate=0; - return AICA->DRTABLE[Rate]; -} - -static int Get_RR(struct _AICA *AICA,int base,int R) -{ - int Rate=base+(R<<1); - if(Rate>63) Rate=63; - if(Rate<0) Rate=0; - return AICA->DRTABLE[Rate]; -} - -static void Compute_EG(struct _AICA *AICA,struct _SLOT *slot) -{ - int octave=OCT(slot); - int rate; - if(octave&8) octave=octave-16; - if(KRS(slot)!=0xf) - rate=octave+2*KRS(slot)+((FNS(slot)>>9)&1); - else - rate=0; //rate=((FNS(slot)>>9)&1); - - slot->EG.volume=0x17f<EG.AR=Get_AR(AICA,rate,AR(slot)); - slot->EG.D1R=Get_DR(AICA,rate,D1R(slot)); - slot->EG.D2R=Get_DR(AICA,rate,D2R(slot)); - slot->EG.RR=Get_RR(AICA,rate,RR(slot)); - slot->EG.DL=0x1f-DL(slot); -} - -static void AICA_StopSlot(struct _SLOT *slot,int keyoff); - -static int EG_Update(struct _SLOT *slot) -{ - switch(slot->EG.state) - { - case ATTACK: - slot->EG.volume+=slot->EG.AR; - if(slot->EG.volume>=(0x3ff<EG.state=DECAY1; - if(slot->EG.D1R>=(1024<EG.state=DECAY2; - } - slot->EG.volume=0x3ff<EG.volume-=slot->EG.D1R; - if(slot->EG.volume<=0) - slot->EG.volume=0; - if(slot->EG.volume>>(EG_SHIFT+5)EG.DL) - slot->EG.state=DECAY2; - break; - case DECAY2: - if(D2R(slot)==0) - return (slot->EG.volume>>EG_SHIFT)<<(SHIFT-10); - slot->EG.volume-=slot->EG.D2R; - if(slot->EG.volume<=0) - slot->EG.volume=0; - - break; - case RELEASE: - slot->EG.volume-=slot->EG.RR; - if(slot->EG.volume<=0) - { - slot->EG.volume=0; - AICA_StopSlot(slot,0); -// slot->EG.volume=0x17f<EG.state=ATTACK; - } - break; - default: - return 1<EG.volume>>EG_SHIFT)<<(SHIFT-10); -} - -static UINT32 AICA_Step(struct _SLOT *slot) -{ - int octave=OCT(slot); - UINT32 Fn; - - Fn=(FNS_Table[FNS(slot)]); //24.8 - if(octave&8) - Fn>>=(16-octave); - else - Fn<<=octave; - - return Fn/(44100); -} - - -static void Compute_LFO(struct _SLOT *slot) -{ - if(PLFOS(slot)!=0) - AICALFO_ComputeStep(&(slot->PLFO),LFOF(slot),PLFOWS(slot),PLFOS(slot),0); - if(ALFOS(slot)!=0) - AICALFO_ComputeStep(&(slot->ALFO),LFOF(slot),ALFOWS(slot),ALFOS(slot),1); -} - -#define ADPCMSHIFT 8 -#define ADFIX(f) (int) ((float) f*(float) (1<> 29)) >> 3); - *PrevSignal=ICLIP16(x); - *PrevQuant=(*PrevQuant*TableQuant[Delta&7])>>ADPCMSHIFT; - *PrevQuant=(*PrevQuant<0x7f)?0x7f:((*PrevQuant>0x6000)?0x6000:*PrevQuant); - return *PrevSignal; -} - -static void AICA_StartSlot(struct _AICA *AICA, struct _SLOT *slot) -{ - UINT64 start_offset; - - slot->active=1; - slot->Backwards=0; - slot->cur_addr=0; slot->nxt_addr=1<prv_addr=-1; - start_offset = SA(slot); // AICA can play 16-bit samples from any boundry - slot->base=&AICA->AICARAM[start_offset]; - slot->step=AICA_Step(slot); - Compute_EG(AICA,slot); - slot->EG.state=ATTACK; - slot->EG.volume=0x17f<= 2) - { - UINT8 *base; - UINT32 curstep, steps_to_go; - - slot->curstep = 0; - slot->adbase = (unsigned char *) (AICA->AICARAM+((SA(slot))&0x7fffff)); - InitADPCM(&(slot->cur_sample), &(slot->cur_quant)); - InitADPCM(&(slot->cur_lpsample), &(slot->cur_lpquant)); - - // walk to the ADPCM state at LSA - curstep = 0; - base = slot->adbase; - steps_to_go = LSA(slot); - - while (curstep < steps_to_go) - { - int shift1, delta1; - shift1 = 4*((curstep&1)); - delta1 = (*base>>shift1)&0xf; - DecodeADPCM(&(slot->cur_lpsample),delta1,&(slot->cur_lpquant)); - curstep++; - if (!(curstep & 1)) - { - base++; - } - } - - slot->cur_lpstep = curstep; - slot->adlpbase = base; - - // on real hardware this creates undefined behavior. - if (LSA(slot) > LEA(slot)) - { - slot->udata.data[0xc/2] = 0xffff; - } - } -} - -static void AICA_StopSlot(struct _SLOT *slot,int keyoff) -{ - if(keyoff /*&& slot->EG.state!=RELEASE*/) - { - slot->EG.state=RELEASE; - } - else - { - slot->active=0; - } - slot->udata.data[0]&=~0x4000; - -} - -#define log_base_2(n) (log((float) n)/log((float) 2)) - -static void AICA_Init(struct _AICA *AICA, const struct AICAinterface *intf) -{ - int i=0; - - AICA->IrqTimA = AICA->IrqTimBC = AICA->IrqMidi = 0; - AICA->MidiR=AICA->MidiW=0; - AICA->MidiOutR=AICA->MidiOutW=0; - - // get AICA RAM - { - memset(AICA,0,sizeof(*AICA)); - - if (!i) - { - AICA->Master=1; - } - else - { - AICA->Master=0; - } - - if (intf->region) - { - AICA->AICARAM = &dc_ram[0]; - AICA->AICARAM_LENGTH = 2*1024*1024; - AICA->DSP.AICARAM = (UINT16 *)AICA->AICARAM; - AICA->DSP.AICARAM_LENGTH = (2*1024*1024)/2; - } - } - - for(i=0;i<0x400;++i) - { - float fcent=(double) 1200.0*log_base_2((double)(((double) 1024.0+(double)i)/(double)1024.0)); - fcent=(double) 44100.0*pow(2.0,fcent/1200.0); - FNS_Table[i]=(float) (1<>0x0)&0xff; - int iPAN=(i>>0x8)&0x1f; - int iSDL=(i>>0xD)&0x0F; - float TL=1.0; - float SegaDB=0; - float fSDL=1.0; - float PAN=1.0; - float LPAN,RPAN; - - if(iTL&0x01) SegaDB-=0.4; - if(iTL&0x02) SegaDB-=0.8; - if(iTL&0x04) SegaDB-=1.5; - if(iTL&0x08) SegaDB-=3; - if(iTL&0x10) SegaDB-=6; - if(iTL&0x20) SegaDB-=12; - if(iTL&0x40) SegaDB-=24; - if(iTL&0x80) SegaDB-=48; - - TL=pow(10.0,SegaDB/20.0); - - SegaDB=0; - if(iPAN&0x1) SegaDB-=3; - if(iPAN&0x2) SegaDB-=6; - if(iPAN&0x4) SegaDB-=12; - if(iPAN&0x8) SegaDB-=24; - - if((iPAN&0xf)==0xf) PAN=0.0; - else PAN=pow(10.0,SegaDB/20.0); - - if(iPAN<0x10) - { - LPAN=PAN; - RPAN=1.0; - } - else - { - RPAN=PAN; - LPAN=1.0; - } - - if(iSDL) - fSDL=pow(10.0,(SDLT[iSDL])/20.0); - else - fSDL=0.0; - - AICA->LPANTABLE[i]=FIX((4.0*LPAN*TL*fSDL)); - AICA->RPANTABLE[i]=FIX((4.0*RPAN*TL*fSDL)); - } - - AICA->ARTABLE[0]=AICA->DRTABLE[0]=0; //Infinite time - AICA->ARTABLE[1]=AICA->DRTABLE[1]=0; //Infinite time - for(i=2;i<64;++i) - { - double t,step,scale; - t=ARTimes[i]; //In ms - if(t!=0.0) - { - step=(1023*1000.0)/((float) 44100.0f*t); - scale=(double) (1<ARTABLE[i]=(int) (step*scale); - } - else - AICA->ARTABLE[i]=1024<DRTABLE[i]=(int) (step*scale); - } - - // make sure all the slots are off - for(i=0;i<64;++i) - { - AICA->Slots[i].slot=i; - AICA->Slots[i].active=0; - AICA->Slots[i].base=NULL; - AICA->Slots[i].EG.state=RELEASE; - AICA->Slots[i].mslc=0; - } - - AICALFO_Init(); - AICA->buffertmpl=(signed int*) malloc(44100*sizeof(signed int)); - AICA->buffertmpr=(signed int*) malloc(44100*sizeof(signed int)); - memset(AICA->buffertmpl,0,44100*sizeof(signed int)); - memset(AICA->buffertmpr,0,44100*sizeof(signed int)); - - // no "pend" - AICA[0].udata.data[0xa0/2] = 0; - //AICA[1].udata.data[0x20/2] = 0; - AICA->TimCnt[0] = 0xffff; - AICA->TimCnt[1] = 0xffff; - AICA->TimCnt[2] = 0xffff; -} - -static void AICA_UpdateSlotReg(struct _AICA *AICA,int s,int r) -{ - struct _SLOT *slot=AICA->Slots+s; - int sl; - switch(r&0x7f) - { - case 0: - case 1: - if(KEYONEX(slot)) - { - for(sl=0;sl<64;++sl) - { - struct _SLOT *s2=AICA->Slots+sl; - { - if(KEYONB(s2) && s2->EG.state==RELEASE/*&& !s2->active*/) - { - if(s2->mslc) AICA->udata.data[0x10] &= 0x7FFF; // reset LP at KEY_ON - AICA_StartSlot(AICA, s2); - - #if 0 - printf("StartSlot[%02X]: SSCTL %01X SA %06X LSA %04X LEA %04X PCMS %01X LPCTL %01X\n",sl,SSCTL(s2),SA(s2),LSA(s2),LEA(s2),PCMS(s2),LPCTL(s2)); - printf(" AR %02X D1R %02X D2R %02X RR %02X DL %02X KRS %01X LPSLNK %01X\n",AR(s2),D1R(s2),D2R(s2),RR(s2),DL(s2),KRS(s2),LPSLNK(s2)>>14); - printf(" TL %02X OCT %01X FNS %03X\n",TL(s2),OCT(s2),FNS(s2)); - printf(" LFORE %01X LFOF %02X ALFOWS %01X ALFOS %01X PLFOWS %01X PLFOS %01X\n",LFORE(s2),LFOF(s2),ALFOWS(s2),ALFOS(s2),PLFOWS(s2),PLFOS(s2)); - printf(" IMXL %01X ISEL %01X DISDL %01X DIPAN %02X\n",IMXL(s2),ISEL(s2),DISDL(s2),DIPAN(s2)); - printf("\n"); - fflush(stdout); - #endif - } - if(!KEYONB(s2) /*&& s2->active*/) - { - AICA_StopSlot(s2,1); - } - } - } - slot->udata.data[0]&=~0x8000; - } - break; - case 0x18: - case 0x19: - slot->step=AICA_Step(slot); - break; - case 0x14: - case 0x15: - slot->EG.RR=Get_RR(AICA,0,RR(slot)); - slot->EG.DL=0x1f-DL(slot); - break; - case 0x1c: - case 0x1d: - Compute_LFO(slot); - break; - case 0x24: -// printf("[%02d]: %x to DISDL/DIPAN (PC=%x)\n", s, slot->udata.data[0x24/2], arm7_get_register(15)); - break; - } -} - -static void AICA_UpdateReg(struct _AICA *AICA, int reg) -{ - switch(reg&0xff) - { - case 0x4: - case 0x5: - { - unsigned int v=RBL(AICA); - AICA->DSP.RBP=RBP(AICA); - if(v==0) - AICA->DSP.RBL=8*1024; - else if(v==1) - AICA->DSP.RBL=16*1024; - else if(v==2) - AICA->DSP.RBL=32*1024; - else if(v==3) - AICA->DSP.RBL=64*1024; - } - break; - case 0x8: - case 0x9: - AICA_MidiIn(0, AICA->udata.data[0x8/2]&0xff, 0); - break; - case 0x12: - case 0x13: - case 0x14: - case 0x15: - case 0x16: - case 0x17: - break; - case 0x90: - case 0x91: - if(AICA->Master) - { - AICA->TimPris[0]=1<<((AICA->udata.data[0x90/2]>>8)&0x7); - AICA->TimCnt[0]=(AICA->udata.data[0x90/2]&0xff)<<8; - } - break; - case 0x94: - case 0x95: - if(AICA->Master) - { - AICA->TimPris[1]=1<<((AICA->udata.data[0x94/2]>>8)&0x7); - AICA->TimCnt[1]=(AICA->udata.data[0x94/2]&0xff)<<8; - } - break; - case 0x98: - case 0x99: - if(AICA->Master) - { - AICA->TimPris[2]=1<<((AICA->udata.data[0x98/2]>>8)&0x7); - AICA->TimCnt[2]=(AICA->udata.data[0x98/2]&0xff)<<8; - } - break; - case 0xa4: //SCIRE - case 0xa5: - - if(AICA->Master) - { - AICA->udata.data[0xa0/2] &= ~AICA->udata.data[0xa4/2]; - ResetInterrupts(AICA); - - // behavior from real hardware (SCSP, assumed to carry over): if you SCIRE a timer that's expired, - // it'll immediately pop up again - if (AICA->TimCnt[0] >= 0xff00) - { - AICA->udata.data[0xa0/2] |= 0x40; - } - if (AICA->TimCnt[1] >= 0xff00) - { - AICA->udata.data[0xa0/2] |= 0x80; - } - if (AICA->TimCnt[2] >= 0xff00) - { - AICA->udata.data[0xa0/2] |= 0x100; - } - } - break; - case 0xa8: - case 0xa9: - case 0xac: - case 0xad: - case 0xb0: - case 0xb1: - if(AICA->Master) - { - AICA->IrqTimA=DecodeSCI(AICA,SCITMA); - AICA->IrqTimBC=DecodeSCI(AICA,SCITMB); - AICA->IrqMidi=DecodeSCI(AICA,SCIMID); - } - break; - } -} - -static void AICA_UpdateSlotRegR(struct _AICA *AICA, int slot,int reg) -{ - -} - -static void AICA_UpdateRegR(struct _AICA *AICA, int reg) -{ - switch(reg&0xff) - { - case 8: - case 9: - { - unsigned short v=AICA->udata.data[0x8/2]; - v&=0xff00; - v|=AICA->MidiStack[AICA->MidiR]; - AICA->IntARMCB(0); // cancel the IRQ - if(AICA->MidiR!=AICA->MidiW) - { - ++AICA->MidiR; - AICA->MidiR&=15; - } - AICA->udata.data[0x8/2]=v; - } - break; - - case 0x10: // LP check - case 0x11: - { - //int MSLC = (AICA->udata.data[0xc/2]>>8) & 0x3f; // which slot are we monitoring? - } - break; - - case 0x14: // CA (slot address) - case 0x15: - { - int MSLC = (AICA->udata.data[0xc/2]>>8) & 0x3f; // which slot are we monitoring? - unsigned int CA = AICA->Slots[MSLC].cur_addr>>(SHIFT+12); - - AICA->udata.data[0x14/2] = CA; - } - break; - } -} - -static void AICA_w16(struct _AICA *AICA,unsigned int addr,unsigned short val) -{ - addr&=0xffff; - if(addr<0x2000) - { - int slot=addr/0x80; - addr&=0x7f; -// printf("%x to slot %d offset %x\n", val, slot, addr); - *((unsigned short *) (AICA->Slots[slot].udata.datab+(addr))) = val; - AICA_UpdateSlotReg(AICA,slot,addr&0x7f); - } - else if (addr < 0x2800) - { - if (addr <= 0x2044) - { -// printf("%x to EFSxx slot %d (addr %x)\n", val, (addr-0x2000)/4, addr&0x7f); - AICA->EFSPAN[addr&0x7f] = val; - } - } - else if(addr<0x3000) - { - if (addr < 0x28be) - { -// printf("%x to AICA global @ %x\n", val, addr & 0xff); - *((unsigned short *) (AICA->udata.datab+((addr&0xff)))) = val; - AICA_UpdateReg(AICA, addr&0xff); - } - else if (addr == 0x2d00) - { - AICA->IRQL = val; - } - else if (addr == 0x2d04) - { - AICA->IRQR = val; - - if (val) - { - AICA->IntARMCB(0); - } - } - } - else - { - //DSP - if(addr<0x3200) //COEF - *((unsigned short *) (AICA->DSP.COEF+(addr-0x3000)/2))=val; - else if(addr<0x3400) - *((unsigned short *) (AICA->DSP.MADRS+(addr-0x3200)/2))=val; - else if(addr<0x3c00) - { - *((unsigned short *) (AICA->DSP.MPRO+(addr-0x3400)/2))=val; - - if (addr == 0x3bfe) - { - AICADSP_Start(&AICA->DSP); - } - } - } -} - -static unsigned short AICA_r16(struct _AICA *AICA, unsigned int addr) -{ - unsigned short v=0; - addr&=0xffff; - if(addr<0x2000) - { - int slot=addr/0x80; - addr&=0x7f; - AICA_UpdateSlotRegR(AICA, slot,addr&0x7f); - v=*((unsigned short *) (AICA->Slots[slot].udata.datab+(addr))); - } - else if(addr<0x3000) - { - if (addr <= 0x2044) - { - v = AICA->EFSPAN[addr&0x7f]; - } - else if (addr < 0x28be) - { - AICA_UpdateRegR(AICA, addr&0xff); - v= *((unsigned short *) (AICA->udata.datab+((addr&0xff)))); - if((addr&0xfe)==0x10) AICA->udata.data[0x10/2] &= 0x7FFF; // reset LP on read - } - else if (addr == 0x2d00) - { - return AICA->IRQL; - } - else if (addr == 0x2d04) - { - return AICA->IRQR; - } - } -// else if (addr<0x700) -// v=AICA->RINGBUF[(addr-0x600)/2]; - return v; -} - - -#define REVSIGN(v) ((~v)+1) - -void AICA_TimersAddTicks(struct _AICA *AICA, int ticks) -{ - if(AICA->TimCnt[0]<=0xff00) - { - AICA->TimCnt[0] += ticks << (8-((AICA->udata.data[0x90/2]>>8)&0x7)); - if (AICA->TimCnt[0] >= 0xFF00) - { - AICA->TimCnt[0] = 0xFFFF; - AICA->udata.data[0xa0/2]|=0x40; - } - AICA->udata.data[0x90/2]&=0xff00; - AICA->udata.data[0x90/2]|=AICA->TimCnt[0]>>8; - } - - if(AICA->TimCnt[1]<=0xff00) - { - AICA->TimCnt[1] += ticks << (8-((AICA->udata.data[0x94/2]>>8)&0x7)); - if (AICA->TimCnt[1] >= 0xFF00) - { - AICA->TimCnt[1] = 0xFFFF; - AICA->udata.data[0xa0/2]|=0x80; - } - AICA->udata.data[0x94/2]&=0xff00; - AICA->udata.data[0x94/2]|=AICA->TimCnt[1]>>8; - } - - if(AICA->TimCnt[2]<=0xff00) - { - AICA->TimCnt[2] += ticks << (8-((AICA->udata.data[0x98/2]>>8)&0x7)); - if (AICA->TimCnt[2] >= 0xFF00) - { - AICA->TimCnt[2] = 0xFFFF; - AICA->udata.data[0xa0/2]|=0x100; - } - AICA->udata.data[0x98/2]&=0xff00; - AICA->udata.data[0x98/2]|=AICA->TimCnt[2]>>8; - } -} - -static INLINE INT32 AICA_UpdateSlot(struct _AICA *AICA, struct _SLOT *slot) -{ - INT32 sample, fpart; - int cur_sample; //current sample - int nxt_sample; //next sample - int step=slot->step; - UINT32 addr1,addr2; // current and next sample addresses - - if(SSCTL(slot)!=0) //no FM or noise yet - return 0; - - if(PLFOS(slot)!=0) - { - step=step*AICAPLFO_Step(&(slot->PLFO)); - step>>=SHIFT; - } - - if(PCMS(slot) == 0) - { - addr1=(slot->cur_addr>>(SHIFT-1))&0x7ffffe; - addr2=(slot->nxt_addr>>(SHIFT-1))&0x7ffffe; - } - else - { - addr1=slot->cur_addr>>SHIFT; - addr2=slot->nxt_addr>>SHIFT; - } - - if(PCMS(slot) == 1) // 8-bit signed - { - INT8 *p1=(signed char *) (AICA->AICARAM+(((SA(slot)+addr1))&0x7fffff)); - INT8 *p2=(signed char *) (AICA->AICARAM+(((SA(slot)+addr2))&0x7fffff)); - cur_sample = p1[0] << 8; - nxt_sample = p2[0] << 8; - } - else if (PCMS(slot) == 0) //16 bit signed - { - INT16 *p1=(signed short *) (AICA->AICARAM+((SA(slot)+addr1)&0x7fffff)); - INT16 *p2=(signed short *) (AICA->AICARAM+((SA(slot)+addr2)&0x7fffff)); - cur_sample = LE16(p1[0]); - nxt_sample = LE16(p2[0]); - } - else // 4-bit ADPCM - { - UINT8 *base= slot->adbase; - UINT32 steps_to_go = addr2, curstep = slot->curstep; - - if (base) - { - cur_sample = slot->cur_sample; // may already contains current decoded sample - - // seek to the interpolation sample - while (curstep < steps_to_go) - { - int shift1, delta1; - shift1 = 4*((curstep&1)); - delta1 = (*base>>shift1)&0xf; - DecodeADPCM(&(slot->cur_sample),delta1,&(slot->cur_quant)); - curstep++; - if (!(curstep & 1)) - { - base++; - } - if (curstep == addr1) - cur_sample = slot->cur_sample; - } - nxt_sample = slot->cur_sample; - - slot->adbase = base; - slot->curstep = curstep; - } - else - { - cur_sample = nxt_sample = 0; - } - } - fpart = slot->cur_addr & ((1<>=SHIFT; - - slot->prv_addr=slot->cur_addr; - slot->cur_addr+=step; - slot->nxt_addr=slot->cur_addr+(1<cur_addr>>SHIFT; - addr2=slot->nxt_addr>>SHIFT; - - if(addr1>=LSA(slot)) - { - if(LPSLNK(slot) && slot->EG.state==ATTACK) - slot->EG.state = DECAY1; - } - - switch(LPCTL(slot)) - { - case 0: //no loop - if(addr2>=LSA(slot) && addr2>=LEA(slot)) // if next sample exceed then current must exceed too - { - //slot->active=0; - if(slot->mslc) AICA->udata.data[8] |= 0x8000; - AICA_StopSlot(slot,0); - } - break; - case 1: //normal loop - if(addr2>=LEA(slot)) - { - INT32 rem_addr; - if(slot->mslc) AICA->udata.data[8] |= 0x8000; - rem_addr = slot->nxt_addr - (LEA(slot)<nxt_addr = (LSA(slot)<=LEA(slot)) - { - rem_addr = slot->cur_addr - (LEA(slot)<cur_addr = (LSA(slot)<=2) - { - // restore the state @ LSA - the sampler will naturally walk to (LSA + remainder) - slot->adbase = &AICA->AICARAM[SA(slot)+(LSA(slot)/2)]; - slot->curstep = LSA(slot); - if (PCMS(slot) == 2) - { - slot->cur_sample = slot->cur_lpsample; - slot->cur_quant = slot->cur_lpquant; - } -//printf("Looping: slot_addr %x LSA %x LEA %x step %x base %x\n", slot->cur_addr>>SHIFT, LSA(slot), LEA(slot), slot->curstep, slot->adbase); - } - } - break; - } - - if(ALFOS(slot)!=0) - { - sample=sample*AICAALFO_Step(&(slot->ALFO)); - sample>>=SHIFT; - } - - if(slot->EG.state==ATTACK) - sample=(sample*EG_Update(slot))>>SHIFT; - else - sample=(sample*EG_TABLE[EG_Update(slot)>>(SHIFT-10)])>>SHIFT; - - if(slot->mslc) - { - AICA->udata.data[0x14/2] = addr1; - if (!(AFSEL(AICA))) - { - UINT16 res; - - AICA->udata.data[0x10/2] |= slot->EG.state<<13; - - res = 0x3FF - (slot->EG.volume>>EG_SHIFT); - - res *= 959; - res /= 1024; - - if (res > 959) res = 959; - - AICA->udata.data[0x10/2] = res; - - //AICA->udata.data[0x10/2] |= 0x3FF - (slot->EG.volume>>EG_SHIFT); - } - } - - return sample; -} - -static void AICA_DoMasterSamples(struct _AICA *AICA, int nsamples) -{ - INT16 *bufr,*bufl; - int sl, s, i; - - bufr=bufferr; - bufl=bufferl; - - for(s=0;sSlots+sl; - slot->mslc = (MSLC(AICA)==sl); - RBUFDST=AICA->RINGBUF+AICA->BUFPTR; - if(AICA->Slots[sl].active) - { - unsigned int Enc; - signed int sample; - - sample=AICA_UpdateSlot(AICA, slot); - - Enc=((TL(slot))<<0x0)|((IMXL(slot))<<0xd); - AICADSP_SetSample(&AICA->DSP,(sample*AICA->LPANTABLE[Enc])>>(SHIFT-2),ISEL(slot),IMXL(slot)); - Enc=((TL(slot))<<0x0)|((DIPAN(slot))<<0x8)|((DISDL(slot))<<0xd); - { - smpl+=(sample*AICA->LPANTABLE[Enc])>>SHIFT; - smpr+=(sample*AICA->RPANTABLE[Enc])>>SHIFT; - } - } - - AICA->BUFPTR&=63; - } - - // process the DSP - AICADSP_Step(&AICA->DSP); - - // mix DSP output - for(i=0;i<16;++i) - { - if(EFSDL(i)) - { - unsigned int Enc=((EFPAN(i))<<0x8)|((EFSDL(i))<<0xd); - smpl+=(AICA->DSP.EFREG[i]*AICA->LPANTABLE[Enc])>>SHIFT; - smpr+=(AICA->DSP.EFREG[i]*AICA->RPANTABLE[Enc])>>SHIFT; - } - } - - *bufl++ = ICLIP16(smpl>>3); - *bufr++ = ICLIP16(smpr>>3); - - AICA_TimersAddTicks(AICA, 1); - CheckPendingIRQ(AICA); - } -} - -int AICA_IRQCB(void *param) -{ - CheckPendingIRQ(param); - return -1; -} - -void AICA_Update(void *param, INT16 **inputs, INT16 **buf, int samples) -{ - struct _AICA *AICA = AllocedAICA; - bufferl = buf[0]; - bufferr = buf[1]; - length = samples; - AICA_DoMasterSamples(AICA, samples); -} - -void *aica_start(const void *config) -{ - const struct AICAinterface *intf; - - struct _AICA *AICA; - - AICA = malloc(sizeof(*AICA)); - memset(AICA, 0, sizeof(*AICA)); - - intf = config; - - // init the emulation - AICA_Init(AICA, intf); - - // set up the IRQ callbacks - { - AICA->IntARMCB = intf->irq_callback[0]; - -// AICA->stream = stream_create(0, 2, 44100, AICA, AICA_Update); - } - - AllocedAICA = AICA; - - return AICA; -} - -void aica_stop(void) -{ - free(AllocedAICA->buffertmpl); - free(AllocedAICA->buffertmpr); - free(AllocedAICA); -} - -void AICA_set_ram_base(int which, void *base) -{ - struct _AICA *AICA = AllocedAICA; - if (AICA) - { - AICA->AICARAM = base; - AICA->DSP.AICARAM = base; - } -} - -READ16_HANDLER( AICA_0_r ) -{ - struct _AICA *AICA = AllocedAICA; - UINT16 res = AICA_r16(AICA, offset*2); - -// printf("Read AICA @ %x => %x (PC=%x, R5=%x)\n", offset*2, res, arm7_get_register(15), arm7_get_register(5)); - - return res; -} - -extern UINT32* stv_scu; - -WRITE16_HANDLER( AICA_0_w ) -{ - struct _AICA *AICA = AllocedAICA; - UINT16 tmp; - - tmp = AICA_r16(AICA, offset*2); - COMBINE_DATA(&tmp); - AICA_w16(AICA,offset*2, tmp); -} - -WRITE16_HANDLER( AICA_MidiIn ) -{ - struct _AICA *AICA = AllocedAICA; - AICA->MidiStack[AICA->MidiW++]=data; - AICA->MidiW &= 15; -} - -READ16_HANDLER( AICA_MidiOutR ) -{ - struct _AICA *AICA = AllocedAICA; - unsigned char val; - - val=AICA->MidiStack[AICA->MidiR++]; - AICA->MidiR&=7; - return val; -} - diff --git a/Frameworks/AudioOverload/aosdk/eng_dsf/aica.h b/Frameworks/AudioOverload/aosdk/eng_dsf/aica.h deleted file mode 100644 index f01468f3d..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_dsf/aica.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - - Sega/Yamaha AICA emulation -*/ - -#ifndef _AICA_H_ -#define _AICA_H_ - -#define MAX_AICA (2) - -#define COMBINE_DATA(varptr) (*(varptr) = (*(varptr) & mem_mask) | (data & ~mem_mask)) - -// convert AO types -typedef int8 data8_t; -typedef int16 data16_t; -typedef int32 data32_t; -typedef int offs_t; - -struct AICAinterface -{ - int num; - void *region[MAX_AICA]; - int mixing_level[MAX_AICA]; /* volume */ - void (*irq_callback[MAX_AICA])(int state); /* irq callback */ -}; - -int AICA_sh_start(struct AICAinterface *intf); -void AICA_sh_stop(void); -void scsp_stop(void); - -#define READ16_HANDLER(name) data16_t name(offs_t offset, data16_t mem_mask) -#define WRITE16_HANDLER(name) void name(offs_t offset, data16_t data, data16_t mem_mask) - -// AICA register access -READ16_HANDLER( AICA_0_r ); -WRITE16_HANDLER( AICA_0_w ); -READ16_HANDLER( AICA_1_r ); -WRITE16_HANDLER( AICA_1_w ); - -// MIDI I/O access (used for comms on Model 2/3) -WRITE16_HANDLER( AICA_MidiIn ); -READ16_HANDLER( AICA_MidiOutR ); - -#endif diff --git a/Frameworks/AudioOverload/aosdk/eng_dsf/aicadsp.c b/Frameworks/AudioOverload/aosdk/eng_dsf/aicadsp.c deleted file mode 100644 index b2fb5223b..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_dsf/aicadsp.c +++ /dev/null @@ -1,349 +0,0 @@ -#include -#include -#include "ao.h" -#include "cpuintrf.h" -#include "aica.h" -#include "aicadsp.h" - -static UINT16 PACK(INT32 val) -{ - UINT32 temp; - int sign,exponent,k; - - sign = (val >> 23) & 0x1; - temp = (val ^ (val << 1)) & 0xFFFFFF; - exponent = 0; - for (k=0; k<12; k++) - { - if (temp & 0x800000) - break; - temp <<= 1; - exponent += 1; - } - if (exponent < 12) - val = (val << exponent) & 0x3FFFFF; - else - val <<= 11; - val >>= 11; - val |= sign << 15; - val |= exponent << 11; - - return (UINT16)val; -} - -static INT32 UNPACK(UINT16 val) -{ - int sign,exponent,mantissa; - INT32 uval; - - sign = (val >> 15) & 0x1; - exponent = (val >> 11) & 0xF; - mantissa = val & 0x7FF; - uval = mantissa << 11; - if (exponent > 11) - exponent = 11; - else - uval |= (sign ^ 1) << 22; - uval |= sign << 23; - uval <<= 8; - uval >>= 8; - uval >>= exponent; - - return uval; -} - -void AICADSP_Init(struct _AICADSP *DSP) -{ - memset(DSP,0,sizeof(struct _AICADSP)); - DSP->RBL=0x8000; - DSP->Stopped=1; -} - -void AICADSP_Step(struct _AICADSP *DSP) -{ - INT32 ACC=0; //26 bit - INT32 SHIFTED=0; //24 bit - INT32 X=0; //24 bit - INT32 Y=0; //13 bit - INT32 B=0; //26 bit - INT32 INPUTS=0; //24 bit - INT32 MEMVAL=0; - INT32 FRC_REG=0; //13 bit - INT32 Y_REG=0; //24 bit - UINT32 ADDR=0; - UINT32 ADRS_REG=0; //13 bit - int step; - - if(DSP->Stopped) - return; - - memset(DSP->EFREG,0,2*16); -#if 0 - int dump=0; - FILE *f=NULL; - if(dump) - f=fopen("dsp.txt","wt"); -#endif - for(step=0;stepLastStep;++step) - { - UINT16 *IPtr=DSP->MPRO+step*8; - -// if(IPtr[0]==0 && IPtr[1]==0 && IPtr[2]==0 && IPtr[3]==0) -// break; - - UINT32 TRA=(IPtr[0]>>9)&0x7F; - UINT32 TWT=(IPtr[0]>>8)&0x01; - UINT32 TWA=(IPtr[0]>>1)&0x7F; - - UINT32 XSEL=(IPtr[2]>>15)&0x01; - UINT32 YSEL=(IPtr[2]>>13)&0x03; - UINT32 IRA=(IPtr[2]>>7)&0x3F; - UINT32 IWT=(IPtr[2]>>6)&0x01; - UINT32 IWA=(IPtr[2]>>1)&0x1F; - - UINT32 TABLE=(IPtr[4]>>15)&0x01; - UINT32 MWT=(IPtr[4]>>14)&0x01; - UINT32 MRD=(IPtr[4]>>13)&0x01; - UINT32 EWT=(IPtr[4]>>12)&0x01; - UINT32 EWA=(IPtr[4]>>8)&0x0F; - UINT32 ADRL=(IPtr[4]>>7)&0x01; - UINT32 FRCL=(IPtr[4]>>6)&0x01; - UINT32 SHIFT=(IPtr[4]>>4)&0x03; - UINT32 YRL=(IPtr[4]>>3)&0x01; - UINT32 NEGB=(IPtr[4]>>2)&0x01; - UINT32 ZERO=(IPtr[4]>>1)&0x01; - UINT32 BSEL=(IPtr[4]>>0)&0x01; - - UINT32 NOFL=(IPtr[6]>>15)&1; //???? - UINT32 COEF=step; - - UINT32 MASA=(IPtr[6]>>9)&0x3f; //??? - UINT32 ADREB=(IPtr[6]>>8)&0x1; - UINT32 NXADR=(IPtr[6]>>7)&0x1; - - INT64 v; - - //operations are done at 24 bit precision -#if 0 - if(MASA) - int a=1; - if(NOFL) - int a=1; - -// int dump=0; - - if(f) - { -#define DUMP(v) fprintf(f," " #v ": %04X",v); - - fprintf(f,"%d: ",step); - DUMP(ACC); - DUMP(SHIFTED); - DUMP(X); - DUMP(Y); - DUMP(B); - DUMP(INPUTS); - DUMP(MEMVAL); - DUMP(FRC_REG); - DUMP(Y_REG); - DUMP(ADDR); - DUMP(ADRS_REG); - fprintf(f,"\n"); - } -#endif - //INPUTS RW - assert(IRA<0x32); - if(IRA<=0x1f) - INPUTS=DSP->MEMS[IRA]; - else if(IRA<=0x2F) - INPUTS=DSP->MIXS[IRA-0x20]<<4; //MIXS is 20 bit - else if(IRA<=0x31) - INPUTS=0; - - INPUTS<<=8; - INPUTS>>=8; - //if(INPUTS&0x00800000) - // INPUTS|=0xFF000000; - - if(IWT) - { - DSP->MEMS[IWA]=MEMVAL; //MEMVAL was selected in previous MRD - if(IRA==IWA) - INPUTS=MEMVAL; - } - - //Operand sel - //B - if(!ZERO) - { - if(BSEL) - B=ACC; - else - { - B=DSP->TEMP[(TRA+DSP->DEC)&0x7F]; - B<<=8; - B>>=8; - //if(B&0x00800000) - // B|=0xFF000000; //Sign extend - } - if(NEGB) - B=0-B; - } - else - B=0; - - //X - if(XSEL) - X=INPUTS; - else - { - X=DSP->TEMP[(TRA+DSP->DEC)&0x7F]; - X<<=8; - X>>=8; - //if(X&0x00800000) - // X|=0xFF000000; - } - - //Y - if(YSEL==0) - Y=FRC_REG; - else if(YSEL==1) - Y=DSP->COEF[COEF<<1]>>3; //COEF is 16 bits - else if(YSEL==2) - Y=(Y_REG>>11)&0x1FFF; - else if(YSEL==3) - Y=(Y_REG>>4)&0x0FFF; - - if(YRL) - Y_REG=INPUTS; - - //Shifter - if(SHIFT==0) - { - SHIFTED=ACC; - if(SHIFTED>0x007FFFFF) - SHIFTED=0x007FFFFF; - if(SHIFTED<(-0x00800000)) - SHIFTED=-0x00800000; - } - else if(SHIFT==1) - { - SHIFTED=ACC*2; - if(SHIFTED>0x007FFFFF) - SHIFTED=0x007FFFFF; - if(SHIFTED<(-0x00800000)) - SHIFTED=-0x00800000; - } - else if(SHIFT==2) - { - SHIFTED=ACC*2; - SHIFTED<<=8; - SHIFTED>>=8; - //SHIFTED&=0x00FFFFFF; - //if(SHIFTED&0x00800000) - // SHIFTED|=0xFF000000; - } - else if(SHIFT==3) - { - SHIFTED=ACC; - SHIFTED<<=8; - SHIFTED>>=8; - //SHIFTED&=0x00FFFFFF; - //if(SHIFTED&0x00800000) - // SHIFTED|=0xFF000000; - } - - //ACCUM - Y<<=19; - Y>>=19; - //if(Y&0x1000) - // Y|=0xFFFFF000; - - v=(((INT64) X*(INT64) Y)>>12); - ACC=(int) v+B; - - if(TWT) - DSP->TEMP[(TWA+DSP->DEC)&0x7F]=SHIFTED; - - if(FRCL) - { - if(SHIFT==3) - FRC_REG=SHIFTED&0x0FFF; - else - FRC_REG=(SHIFTED>>11)&0x1FFF; - } - - if(MRD || MWT) - //if(0) - { - ADDR=DSP->MADRS[MASA<<1]; - if(!TABLE) - ADDR+=DSP->DEC; - if(ADREB) - ADDR+=ADRS_REG&0x0FFF; - if(NXADR) - ADDR++; - if(!TABLE) - ADDR&=DSP->RBL-1; - else - ADDR&=0xFFFF; - //ADDR<<=1; - //ADDR+=DSP->RBP<<13; - //MEMVAL=DSP->AICARAM[ADDR>>1]; - ADDR+=DSP->RBP<<10; - if(MRD && (step&1)) //memory only allowed on odd? DoA inserts NOPs on even - { - if(NOFL) - MEMVAL=DSP->AICARAM[ADDR]<<8; - else - MEMVAL=UNPACK(DSP->AICARAM[ADDR]); - } - if(MWT && (step&1)) - { - if(NOFL) - DSP->AICARAM[ADDR]=SHIFTED>>8; - else - DSP->AICARAM[ADDR]=PACK(SHIFTED); - } - } - - if(ADRL) - { - if(SHIFT==3) - ADRS_REG=(SHIFTED>>12)&0xFFF; - else - ADRS_REG=(INPUTS>>16); - } - - if(EWT) - DSP->EFREG[EWA]+=SHIFTED>>8; - - } - --DSP->DEC; - memset(DSP->MIXS,0,4*16); -// if(f) -// fclose(f); -} - -void AICADSP_SetSample(struct _AICADSP *DSP,INT32 sample,int SEL,int MXL) -{ - //DSP->MIXS[SEL]+=sample<<(MXL+1)/*7*/; - DSP->MIXS[SEL]+=sample; -// if(MXL) -// int a=1; -} - -void AICADSP_Start(struct _AICADSP *DSP) -{ - int i; - DSP->Stopped=0; - for(i=127;i>=0;--i) - { - UINT16 *IPtr=DSP->MPRO+i*8; - - if(IPtr[0]!=0 || IPtr[2]!=0 || IPtr[4]!=0 || IPtr[6]!=0) - break; - } - DSP->LastStep=i+1; - -} diff --git a/Frameworks/AudioOverload/aosdk/eng_dsf/aicadsp.h b/Frameworks/AudioOverload/aosdk/eng_dsf/aicadsp.h deleted file mode 100644 index b10accff5..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_dsf/aicadsp.h +++ /dev/null @@ -1,37 +0,0 @@ -#ifndef AICADSP_H -#define AICADSP_H - -//the DSP Context -struct _AICADSP -{ -//Config - UINT16 *AICARAM; - UINT32 AICARAM_LENGTH; - UINT32 RBP; //Ring buf pointer - UINT32 RBL; //Delay ram (Ring buffer) size in words - -//context - - INT16 COEF[128*2]; //16 bit signed - UINT16 MADRS[64*2]; //offsets (in words), 16 bit - UINT16 MPRO[128*4*2*2]; //128 steps 64 bit - INT32 TEMP[128]; //TEMP regs,24 bit signed - INT32 MEMS[32]; //MEMS regs,24 bit signed - UINT32 DEC; - -//input - INT32 MIXS[16]; //MIXS, 24 bit signed - INT16 EXTS[2]; //External inputs (CDDA) 16 bit signed - -//output - INT16 EFREG[16]; //EFREG, 16 bit signed - - int Stopped; - int LastStep; -}; - -void AICADSP_Init(struct _AICADSP *DSP); -void AICADSP_SetSample(struct _AICADSP *DSP, INT32 sample, INT32 SEL, INT32 MXL); -void AICADSP_Step(struct _AICADSP *DSP); -void AICADSP_Start(struct _AICADSP *DSP); -#endif diff --git a/Frameworks/AudioOverload/aosdk/eng_dsf/aicalfo.c b/Frameworks/AudioOverload/aosdk/eng_dsf/aicalfo.c deleted file mode 100644 index cc1ea1ccb..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_dsf/aicalfo.c +++ /dev/null @@ -1,159 +0,0 @@ -/* - AICA LFO handling - - Part of the AICA emulator package. - (not compiled directly, #included from aica.c) - - By ElSemi, kingshriek, and R. Belmont -*/ - -#define LFO_SHIFT 8 - -struct _LFO -{ - unsigned short phase; - UINT32 phase_step; - int *table; - int *scale; -}; - -#define LFIX(v) ((unsigned int) ((float) (1<phase+=LFO->phase_step; -#if LFO_SHIFT!=8 - LFO->phase&=(1<<(LFO_SHIFT+8))-1; -#endif - p=LFO->table[LFO->phase>>LFO_SHIFT]; - p=LFO->scale[p+128]; - return p<<(SHIFT-LFO_SHIFT); -} - -static signed int INLINE AICAALFO_Step(struct _LFO *LFO) -{ - int p; - LFO->phase+=LFO->phase_step; -#if LFO_SHIFT!=8 - LFO->phase&=(1<<(LFO_SHIFT+8))-1; -#endif - p=LFO->table[LFO->phase>>LFO_SHIFT]; - p=LFO->scale[p]; - return p<<(SHIFT-LFO_SHIFT); -} - -void AICALFO_ComputeStep(struct _LFO *LFO,UINT32 LFOF,UINT32 LFOWS,UINT32 LFOS,int ALFO) -{ - float step=(float) LFOFreq[LFOF]*256.0/(float)44100.0; - LFO->phase_step=(unsigned int) ((float) (1<table=ALFO_SAW; break; - case 1: LFO->table=ALFO_SQR; break; - case 2: LFO->table=ALFO_TRI; break; - case 3: LFO->table=ALFO_NOI; break; - default: printf("Unknown ALFO %d\n", LFOWS); - } - LFO->scale=ASCALES[LFOS]; - } - else - { - switch(LFOWS) - { - case 0: LFO->table=PLFO_SAW; break; - case 1: LFO->table=PLFO_SQR; break; - case 2: LFO->table=PLFO_TRI; break; - case 3: LFO->table=PLFO_NOI; break; - default: printf("Unknown PLFO %d\n", LFOWS); - } - LFO->scale=PSCALES[LFOS]; - } -} diff --git a/Frameworks/AudioOverload/aosdk/eng_dsf/arm7.c b/Frameworks/AudioOverload/aosdk/eng_dsf/arm7.c deleted file mode 100644 index 980c306fa..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_dsf/arm7.c +++ /dev/null @@ -1,274 +0,0 @@ -// -// ARM7 processor emulator -// version 1.6 / 2008-02-16 -// (c) Radoslaw Balcewicz -// - -#include "arm7.h" -#include "arm7i.h" - -#ifdef ARM7_THUMB -#include "arm7thumb.h" -#endif - - //-------------------------------------------------------------------------- - // definitions and macros - - /** Macro for accessing banked registers. */ -#define RX_BANK(t,r) (ARM7.Rx_bank [t][r - 8]) - //-------------------------------------------------------------------------- - - //-------------------------------------------------------------------------- - // private functions - - /** CPU Reset. */ -static void Reset (void); - //-------------------------------------------------------------------------- - - //-------------------------------------------------------------------------- - // public variables - - /** ARM7 state. */ -struct sARM7 ARM7; - - // private variables - - /** Table for decoding bit-coded mode to zero based index. */ -static const int s_tabTryb [32] = {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, - -1, -1, -1, -1, -1, -1, ARM7_MODE_usr, ARM7_MODE_fiq, ARM7_MODE_irq, - ARM7_MODE_svc, -1, -1, -1, ARM7_MODE_abt, -1, -1, -1, ARM7_MODE_und, - -1, -1, -1, ARM7_MODE_sys}; - //-------------------------------------------------------------------------- - - - // public functions - - - //-------------------------------------------------------------------------- - /** ARM7 emulator init. */ -void ARM7_Init () - { - // sane startup values - ARM7.fiq = 0; - ARM7.irq = 0; - ARM7.carry = 0; - ARM7.overflow = 0; - ARM7.flagi = FALSE; - ARM7.cykle = 0; - - // reset will do the rest - ARM7_HardReset (); - } - //-------------------------------------------------------------------------- - - //-------------------------------------------------------------------------- - /** Power-ON reset. */ -void ARM7_HardReset () - { - // CPSR that makes sense - ARM7.Rx [ARM7_CPSR] = ARM7_CPSR_I | ARM7_CPSR_F | ARM7_CPSR_M_svc; - Reset (); - } - //-------------------------------------------------------------------------- - - //-------------------------------------------------------------------------- - /** Hardware reset via /RESET line. */ -void ARM7_SoftReset () - { - Reset (); - } - //-------------------------------------------------------------------------- - - //-------------------------------------------------------------------------- - /** CPSR update, possibly changing operating mode. */ -void ARM7_SetCPSR (ARM7_REG sr) - { - int stary, nowy; - - stary = s_tabTryb [ARM7_CPSR_M (ARM7.Rx [ARM7_CPSR])]; - nowy = s_tabTryb [ARM7_CPSR_M (sr)]; - // do we have to change modes? - if (nowy != stary) - { - // save this mode registers - RX_BANK (stary, ARM7_SP) = ARM7.Rx [ARM7_SP], - RX_BANK (stary, ARM7_LR) = ARM7.Rx [ARM7_LR], - RX_BANK (stary, ARM7_SPSR) = ARM7.Rx [ARM7_SPSR]; - if (stary == ARM7_MODE_fiq) - { - // copy R8-R12 - RX_BANK (ARM7_MODE_fiq, 8) = ARM7.Rx [8], - RX_BANK (ARM7_MODE_fiq, 9) = ARM7.Rx [9], - RX_BANK (ARM7_MODE_fiq, 10) = ARM7.Rx [10], - RX_BANK (ARM7_MODE_fiq, 11) = ARM7.Rx [11], - RX_BANK (ARM7_MODE_fiq, 12) = ARM7.Rx [12]; - ARM7.Rx [8] = RX_BANK (ARM7_MODE_usr, 8), - ARM7.Rx [9] = RX_BANK (ARM7_MODE_usr, 9), - ARM7.Rx [10] = RX_BANK (ARM7_MODE_usr, 10), - ARM7.Rx [11] = RX_BANK (ARM7_MODE_usr, 11), - ARM7.Rx [12] = RX_BANK (ARM7_MODE_usr, 12); - } - - // fetch new mode registers - ARM7.Rx [ARM7_SP] = RX_BANK (nowy, ARM7_SP), - ARM7.Rx [ARM7_LR] = RX_BANK (nowy, ARM7_LR), - ARM7.Rx [ARM7_SPSR] = RX_BANK (nowy, ARM7_SPSR); - if (nowy == ARM7_MODE_fiq) - { - // copy R8-R12 - RX_BANK (ARM7_MODE_usr, 8) = ARM7.Rx [8], - RX_BANK (ARM7_MODE_usr, 9) = ARM7.Rx [9], - RX_BANK (ARM7_MODE_usr, 10) = ARM7.Rx [10], - RX_BANK (ARM7_MODE_usr, 11) = ARM7.Rx [11], - RX_BANK (ARM7_MODE_usr, 12) = ARM7.Rx [12]; - ARM7.Rx [8] = RX_BANK (ARM7_MODE_fiq, 8), - ARM7.Rx [9] = RX_BANK (ARM7_MODE_fiq, 9), - ARM7.Rx [10] = RX_BANK (ARM7_MODE_fiq, 10), - ARM7.Rx [11] = RX_BANK (ARM7_MODE_fiq, 11), - ARM7.Rx [12] = RX_BANK (ARM7_MODE_fiq, 12); - } - } - - // new CPSR value - ARM7.Rx [ARM7_CPSR] = sr; - - // mode change could've enabled interrups, so we test for those and set - // appropriate flag for the instruction loop to catch - if (ARM7.fiq) - ARM7.flagi |= ARM7_FL_FIQ; -#ifndef ARM7_DREAMCAST - if (ARM7.irq) - ARM7.flagi |= ARM7_FL_IRQ; -#endif - } - //-------------------------------------------------------------------------- - - //-------------------------------------------------------------------------- - /** Sets FIQ line state. */ -void ARM7_SetFIQ (int stan) - { - stan = stan ? TRUE : FALSE; - // we catch changes only - if (stan ^ ARM7.fiq) - { - ARM7.fiq = stan; - if (ARM7.fiq) - ARM7.flagi |= ARM7_FL_FIQ; - } - } - //-------------------------------------------------------------------------- - - //-------------------------------------------------------------------------- - /** Sets IRQ line state. */ -void ARM7_SetIRQ (int stan) - { - stan = stan ? TRUE : FALSE; - // we catch changes only - if (stan ^ ARM7.irq) - { - ARM7.irq = stan; - if (ARM7.irq) - ARM7.flagi |= ARM7_FL_IRQ; - } - } - //-------------------------------------------------------------------------- - - //-------------------------------------------------------------------------- - /** Tests for pending interrupts, switches to one if possible. */ -void ARM7_CheckIRQ () - { - UINT32 sr = ARM7.Rx [ARM7_CPSR]; - - // clear all interrupt flags - ARM7.flagi &= ~(ARM7_FL_FIQ | ARM7_FL_IRQ); - - // check for pending interrupts we can switch to - // (FIQ can interrupt IRQ, but not the other way around) - if (ARM7.fiq) - { - if (!(sr & ARM7_CPSR_F)) - { - // FIQ - ARM7_SetCPSR (ARM7_CPSR_MX (sr, ARM7_CPSR_M_fiq) | ARM7_CPSR_F | ARM7_CPSR_I); - ARM7.Rx [ARM7_SPSR] = sr; - // set new PC (return from interrupt will subtract 4) - ARM7.Rx [ARM7_LR] = ARM7.Rx [ARM7_PC] + 4; - ARM7.Rx [ARM7_PC] = 0x0000001c; - } - } -#ifndef ARM7_DREAMCAST - if (ARM7.irq) - { - if (!(sr & ARM7_CPSR_I)) - { - // IRQ - ARM7_SetCPSR (ARM7_CPSR_MX (sr, ARM7_CPSR_M_irq) | ARM7_CPSR_I); - ARM7.Rx [ARM7_SPSR] = sr; - // set new PC (return from interrupt will subtract 4) - ARM7.Rx [ARM7_LR] = ARM7.Rx [ARM7_PC] + 4; - ARM7.Rx [ARM7_PC] = 0x00000018; - ARM7.irq = 0; - } - } -#endif - } - //-------------------------------------------------------------------------- - - //-------------------------------------------------------------------------- - /** Single step. */ -void ARM7_Step () -{ - // make a step -#ifdef ARM7_THUMB - if (ARM7.Rx[ARM7_CPSR] & ARM7_CPSR_T) - { - ARM7i_Thumb_Step(); - } - else -#endif - { - ARM7i_Step (); - } - // and test interrupts - ARM7_CheckIRQ (); -} - //-------------------------------------------------------------------------- - - //-------------------------------------------------------------------------- - /** Runs emulation for at least n cycles, returns actual amount of cycles - burned - normal interpreter. */ -int ARM7_Execute (int n) - { - ARM7.cykle = 0; - while (ARM7.cykle < n) - { - ARM7_CheckIRQ (); - while (!ARM7.flagi && ARM7.cykle < n) - // make one step, sum up cycles - ARM7.cykle += ARM7i_Step (); - } - return ARM7.cykle; - } - //-------------------------------------------------------------------------- - - - // private functions - - - //-------------------------------------------------------------------------- - /** CPU Reset. */ -void Reset (void) - { - // clear ALU flags - ARM7.carry = 0; - ARM7.overflow = 0; - // test CPSR mode and pick a valid one if necessary - if (s_tabTryb [ARM7_CPSR_M (ARM7.Rx [ARM7_CPSR])] < 0) - ARM7.Rx [ARM7_CPSR] = ARM7_CPSR_I | ARM7_CPSR_F | ARM7_CPSR_M_svc; - // set up registers according to manual - RX_BANK (ARM7_MODE_svc, ARM7_LR) = ARM7.Rx [ARM7_PC]; - RX_BANK (ARM7_MODE_svc, ARM7_SPSR) = ARM7.Rx [ARM7_CPSR]; - ARM7_SetCPSR (ARM7_CPSR_I | ARM7_CPSR_F | ARM7_CPSR_M_svc); - ARM7.Rx [ARM7_PC] = 0x00000000; - } - //-------------------------------------------------------------------------- diff --git a/Frameworks/AudioOverload/aosdk/eng_dsf/arm7.h b/Frameworks/AudioOverload/aosdk/eng_dsf/arm7.h deleted file mode 100644 index 41cb9b563..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_dsf/arm7.h +++ /dev/null @@ -1,165 +0,0 @@ -// -// ARM7 processor emulator -// version 1.6 / 2008-02-16 -// (c) Radoslaw Balcewicz -// - -#ifndef _ARM7_h_ -#define _ARM7_h_ - -#include "cpuintrf.h" - - //-------------------------------------------------------------------------- - // definitions and macros - - /** If defined, will turn on specific behavior emulation, as well as some - optimizations that are valid only for Dreamcast AICA. */ -#define ARM7_DREAMCAST - - /** Define to enable Thumb support for ARM7. */ -//#define ARM7_THUMB - - // sanity tests -#ifdef ARM7_DREAMCAST - #ifdef ARM7_THUMB - #warning "Dreamcast ARM7 is a -DI type, it doesn't support Thumb mode." - #endif -#else -// #warning "Instructions cycle counts might not be correct." -#endif - - //-------------------------------------------------------------------------- - - //-------------------------------------------------------------------------- - // CPU definitions - - /** Status flags in CPSR register. */ -#define ARM7_CPSR_N (1 << 31) -#define ARM7_CPSR_Z (1 << 30) -#define ARM7_CPSR_C (1 << 29) -#define ARM7_CPSR_V (1 << 28) -#define ARM7_CPSR_I (1 << 7) -#define ARM7_CPSR_F (1 << 6) -#define ARM7_CPSR_T (1 << 5) - /** CPSR bit mask for current operating mode. */ -#define ARM7_CPSR_M(x) ((x) & 0x1f) -#define ARM7_CPSR_MX(sr,x) (((sr) & ~0x1f) | ((x) & 0x1f)) - /** Bit combinations for each operating mode. */ -#define ARM7_CPSR_M_usr 0x10 -#define ARM7_CPSR_M_fiq 0x11 -#define ARM7_CPSR_M_irq 0x12 -#define ARM7_CPSR_M_svc 0x13 -#define ARM7_CPSR_M_abt 0x17 -#define ARM7_CPSR_M_und 0x11 -#define ARM7_CPSR_M_sys 0x1f - - /** Control flags for ARM7 core. */ -#define ARM7_FL_FIQ (1 << 0) -#define ARM7_FL_IRQ (1 << 1) - - /** Operating modes. */ -#define ARM7_MODE_usr 0 -#define ARM7_MODE_fiq 1 -#define ARM7_MODE_irq 2 -#define ARM7_MODE_svc 3 -#define ARM7_MODE_abt 4 -#define ARM7_MODE_und 5 -#define ARM7_MODE_sys 0 - //-------------------------------------------------------------------------- - - //-------------------------------------------------------------------------- - // register definitions - - /** ARM7 register type (all are 32-bit). */ -typedef INT32 ARM7_REG; - -enum -{ - ARM7_R0 = 0, ARM7_R1, ARM7_R2, ARM7_R3, ARM7_R4, ARM7_R5, ARM7_R6, ARM7_R7, - ARM7_R8, ARM7_R9, ARM7_R10, ARM7_R11, ARM7_R12, ARM7_R13, ARM7_R14, ARM7_R15 -}; - - /** R13 is stack pointer. */ -#define ARM7_SP 13 - /** R14 is link/return address. */ -#define ARM7_LR 14 - /** R15 is program counter. */ -#define ARM7_PC 15 - /** CPSR control register. */ -#define ARM7_CPSR 16 - /** SPSR control register. */ -#define ARM7_SPSR 17 - //-------------------------------------------------------------------------- - - //-------------------------------------------------------------------------- - /** ARM7 CPU state structure. */ -struct sARM7 - { - /** All-purpose and control registers (for current mode). */ - ARM7_REG Rx [18]; - /** Banked registers for all operating modes. */ - ARM7_REG Rx_bank [6][10]; - - /** FIQ and IRQ interrupt requests. */ - int fiq, irq; - - /** Carry flag for barrel shifter and ALU operations. */ - int carry; - /** Overflow flag for arithmetic instructions. */ - int overflow; - - /** Emulation control flags. */ - int flagi; - - /** Instruction code. */ - UINT32 kod; - /** Cycle counter. */ - int cykle; - }; - //-------------------------------------------------------------------------- - - //-------------------------------------------------------------------------- - /** ARM7 state. */ -extern struct sARM7 ARM7; - //-------------------------------------------------------------------------- - - //-------------------------------------------------------------------------- - // public procedures - - /** ARM7 emulator init. */ -void ARM7_Init (void); - - /** Power-ON reset. */ -void ARM7_HardReset (void); - /** Hardware reset via /RESET line. */ -void ARM7_SoftReset (void); - - /** CPSR update, possibly changing operating mode. */ -void ARM7_SetCPSR (ARM7_REG sr); - - /** Sets FIQ line state. */ -void ARM7_SetFIQ (int stan); - /** Sets IRQ line state. */ -void ARM7_SetIRQ (int stan); - - /** Tests for pending interrupts, switches to one if possible. */ -void ARM7_CheckIRQ (void); - - /** Single step. */ -void ARM7_Step (void); - /** Runs emulation for at least n cycles, returns actual amount of cycles - burned - normal interpreter. */ -int ARM7_Execute (int n); - //-------------------------------------------------------------------------- - -enum -{ - ARM7_IRQ_LINE=0, ARM7_FIRQ_LINE, - ARM7_NUM_LINES -}; - -#ifdef ENABLE_DEBUGGER -extern UINT32 arm7_disasm( char *pBuf, UINT32 pc, UINT32 opcode ); -extern UINT32 thumb_disasm( char *pBuf, UINT32 pc, UINT16 opcode ); -#endif -#endif diff --git a/Frameworks/AudioOverload/aosdk/eng_dsf/arm7i.c b/Frameworks/AudioOverload/aosdk/eng_dsf/arm7i.c deleted file mode 100644 index cb6c7106a..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_dsf/arm7i.c +++ /dev/null @@ -1,1339 +0,0 @@ -// -// ARM7 processor emulator - interpreter core -// version 1.6 / 2008-02-16 -// (c) Radoslaw Balcewicz -// - -#include "arm7.h" -#include "arm7i.h" - - //-------------------------------------------------------------------------- - // definitions and macros - - /** PC is being incremented after every instruction fetch, so we adjust for - that on all stores and jumps. */ -#define PC_ADJUSTMENT (-4) - - /** Memory access routines. */ -#include "arm7memil.c" - - /** Bit shifts compatible with IA32. */ -#define SHL(w, k) (((UINT32)(w)) << (k)) -#define SHR(w, k) (((UINT32)(w)) >> (k)) -#define SAR(w, k) (((INT32)(w)) >> (k)) -#define ROR(w, k) (SHR (w, k) | SHL (w, 32 - (k))) - - /** Byte rotation for unaligned 32-bit read. */ -#define RBOD(w, i) (ROR (w, (i) * 8)) - - /** Data processing macros. */ -#define NEG(i) ((i) & (1 << 31)) -#define POS(i) (~(i) & (1 << 31)) -#define ADDCARRY(a, b, c) \ - ((NEG (a) & NEG (b)) |\ - (NEG (a) & POS (c)) |\ - (NEG (b) & POS (c))) ? 1 : 0; -#define ADDOVERFLOW(a, b, c) \ - ((NEG (a) & NEG (b) & POS (c)) |\ - (POS (a) & POS (b) & NEG (c))) ? 1 : 0; -#define SUBCARRY(a, b, c) \ - ((NEG (a) & POS (b)) |\ - (NEG (a) & POS (c)) |\ - (POS (b) & POS (c))) ? 1 : 0; -#define SUBOVERFLOW(a, b, c)\ - ((NEG (a) & POS (b) & POS (c)) |\ - (POS (a) & NEG (b) & NEG (c))) ? 1 : 0; - //-------------------------------------------------------------------------- - - //-------------------------------------------------------------------------- - // private functions - - /** Condition EQ. */ -static int R_WEQ (void); - /** Condition NE. */ -static int R_WNE (void); - /** Condition CS. */ -static int R_WCS (void); - /** Condition CC. */ -static int R_WCC (void); - /** Condition MI. */ -static int R_WMI (void); - /** Condition PL. */ -static int R_WPL (void); - /** Condition VS. */ -static int R_WVS (void); - /** Condition VC. */ -static int R_WVC (void); - /** Condition HI. */ -static int R_WHI (void); - /** Condition LS. */ -static int R_WLS (void); - /** Condition GE. */ -static int R_WGE (void); - /** Condition LT. */ -static int R_WLT (void); - /** Condition GT. */ -static int R_WGT (void); - /** Condition LE. */ -static int R_WLE (void); - /** Condition AL. */ -static int R_WAL (void); - /** Undefined condition. */ -static int R_Wxx (void); - - /** Calculates barrel shifter output. */ -static UINT32 WyliczPrzes (void); - /** Logical shift left. */ -static UINT32 LSL_x (UINT32 w, int i); - /** Logical shift right. */ -static UINT32 LSR_x (UINT32 w, int i); - /** Arithmetic shift right. */ -static UINT32 ASR_x (UINT32 w, int i); - /** Rotate right. */ -static UINT32 ROR_x (UINT32 w, int i); - /** Rotate right extended. */ -static UINT32 RRX_1 (UINT32 w); - - /** Group 00x opcodes. */ -static void R_G00x (void); - /** Multiply instructions. */ -static void R_MUL_MLA (void); - /** Single data swap. */ -static void R_SWP (void); - /** PSR Transfer. */ -static void R_PSR (void); - /** Data processing instructions. */ -static void R_DP (void); - /** Data processing result writeback. */ -static void R_WynikDP (ARM7_REG w); - /** Data processing flags writeback. */ -static void R_FlagiDP (ARM7_REG w); - /** Single data transfer. */ -static void R_SDT (void); - /** Rozkaz "Undefined". */ -static void R_Und (); - /** Block Data Transfer. */ -static void R_BDT (); - /** Block load instructions. */ -static void R_LDM (int Rn, UINT32 adres); - /** Block store instructions. */ -static void R_STM (int Rn, UINT32 adres); - /** Branch/Branch with link. */ -static void R_B_BL (void); - /** Group 110 opcodes. */ -static void R_G110 (void); - /** Group 111 opcodes. */ -static void R_G111 (void); - -#ifdef ARM7_THUMB - /** Halfword and Signed Data Transfer. */ -static void R_HSDT (); -#endif - //-------------------------------------------------------------------------- - - //-------------------------------------------------------------------------- - // private data - - /** Flag testing functions for conditional execution. */ -static int (*s_tabWar [16]) (void) = {R_WEQ, R_WNE, R_WCS, R_WCC, R_WMI, R_WPL, - R_WVS, R_WVC, R_WHI, R_WLS, R_WGE, R_WLT, R_WGT, R_WLE, R_WAL, R_Wxx}; - /** Handler table for instruction groups. */ -static void (*s_tabGrup [8]) (void) = {R_G00x, R_G00x, R_SDT, R_SDT, R_BDT, - R_B_BL, R_G110, R_G111}; - /** Data processing instructions split to arithmetic and logical. */ -static int s_tabAL [16] = {FALSE, FALSE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, - FALSE, FALSE, TRUE, TRUE, FALSE, FALSE, FALSE, FALSE}; - - /** Cycles it took for current instruction to complete. */ -static int s_cykle; - //-------------------------------------------------------------------------- - - - // public functions - - - //-------------------------------------------------------------------------- - /** Single step, returns number of burned cycles. */ -int ARM7i_Step () - { - ARM7.kod = arm7_read_32 (ARM7.Rx [ARM7_PC] & ~3); - - // we increment PC here, and if there's a load from memory it will simply - // overwrite it (all PC modyfing code should be aware of this) - ARM7.Rx [ARM7_PC] += 4; - s_cykle = 2; - // condition test and group selection - if (s_tabWar [(ARM7.kod >> 28) & 15] ()) - s_tabGrup [(ARM7.kod >> 25) & 7] (); - return s_cykle; - } - //-------------------------------------------------------------------------- - - - // private functions - - - //-------------------------------------------------------------------------- - /** Condition EQ. */ -int R_WEQ () - { - // "Z set" - return ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_Z; - } - //-------------------------------------------------------------------------- - - //-------------------------------------------------------------------------- - /** Condition NE. */ -int R_WNE () - { - // "Z clear" - return !(ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_Z); - } - //-------------------------------------------------------------------------- - - //-------------------------------------------------------------------------- - /** Condition CS. */ -int R_WCS () - { - // "C set" - return ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_C; - } - //-------------------------------------------------------------------------- - - //-------------------------------------------------------------------------- - /** Condition CC. */ -int R_WCC () - { - // "C clear" - return !(ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_C); - } - //-------------------------------------------------------------------------- - - //-------------------------------------------------------------------------- - /** Condition MI. */ -int R_WMI () - { - // "N set" - return ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_N; - } - //-------------------------------------------------------------------------- - - //-------------------------------------------------------------------------- - /** Condition PL. */ -int R_WPL () - { - // "N clear" - return !(ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_N); - } - //-------------------------------------------------------------------------- - - //-------------------------------------------------------------------------- - /** Condition VS. */ -int R_WVS () - { - // "V set" - return ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_V; - } - //-------------------------------------------------------------------------- - - //-------------------------------------------------------------------------- - /** Condition VC. */ -int R_WVC () - { - // "V clear" - return !(ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_V); - } - //-------------------------------------------------------------------------- - - //-------------------------------------------------------------------------- - /** Condition HI. */ -int R_WHI () - { - // "C set and Z clear" - return (ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_C) &&\ - !(ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_Z); - } - //-------------------------------------------------------------------------- - - //-------------------------------------------------------------------------- - /** Condition LS. */ -int R_WLS () - { - // "C clear or Z set" - return !(ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_C) ||\ - (ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_Z); - } - //-------------------------------------------------------------------------- - - //-------------------------------------------------------------------------- - /** Condition GE. */ -int R_WGE () - { - // "N equals V" - return (ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_N) &&\ - (ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_V) || !(ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_N) &&\ - !(ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_V); - } - //-------------------------------------------------------------------------- - - //-------------------------------------------------------------------------- - /** Condition LT. */ -int R_WLT () - { - // "N not equal to V" - return !(ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_N) &&\ - (ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_V) || (ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_N) &&\ - !(ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_V); - } - //-------------------------------------------------------------------------- - - //-------------------------------------------------------------------------- - /** Condition GT. */ -int R_WGT () - { - // "Z clear AND (N equals V)" - return !(ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_Z) && R_WGE (); - } - //-------------------------------------------------------------------------- - - //-------------------------------------------------------------------------- - /** Condition LE. */ -int R_WLE () - { - // "Z set OR (N not equal to V)" - return (ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_Z) || R_WLT (); - } - //-------------------------------------------------------------------------- - - //-------------------------------------------------------------------------- - /** Condition AL. */ -int R_WAL () - { - // "(ignored)" - return TRUE; - } - //-------------------------------------------------------------------------- - - //-------------------------------------------------------------------------- - /** Undefined condition. */ -int R_Wxx () - { - // behaviour undefined - return FALSE; - } - //-------------------------------------------------------------------------- - - //-------------------------------------------------------------------------- - /** Calculates barrel shifter output. */ -UINT32 WyliczPrzes () - { - int Rm, Rs, i; - UINT32 w; - - // Rm is source for the shift operation - Rm = ARM7.kod & 15; - - if (ARM7.kod & (1 << 4)) - { - s_cykle++; - // shift count in Rs (8 lowest bits) - if (Rm != ARM7_PC) - w = ARM7.Rx [Rm]; - else - w = (ARM7.Rx [ARM7_PC] & ~3) + 12 + PC_ADJUSTMENT; - // Rs can't be PC - Rs = (ARM7.kod >> 8) & 15; - i = (UINT8)ARM7.Rx [Rs]; - if (i == 0) - { - // special case - ARM7.carry = (ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_C) ? 1 : 0; - return w; - } - - switch ((ARM7.kod >> 5) & 3) - { - case 0: - w = LSL_x (w, i); - break; - case 1: - w = LSR_x (w, i); - break; - case 2: - w = ASR_x (w, i); - break; - case 3: - w = ROR_x (w, i); - break; - } - } - else - { - // shift count as immediate in opcode - if (Rm != ARM7_PC) - w = ARM7.Rx [Rm]; - else - w = (ARM7.Rx [ARM7_PC] & ~3) + 8 + PC_ADJUSTMENT; - i = (ARM7.kod >> 7) & 31; - - switch ((ARM7.kod >> 5) & 3) - { - case 0: - w = LSL_x (w, i); - break; - case 1: - if (i > 0) - w = LSR_x (w, i); - else - w = LSR_x (w, 32); - break; - case 2: - if (i > 0) - w = ASR_x (w, i); - else - w = ASR_x (w, 32); - break; - case 3: - if (i > 0) - w = ROR_x (w, i); - else - w = RRX_1 (w); - break; - } - } - return w; - } - //-------------------------------------------------------------------------- - - //-------------------------------------------------------------------------- - /** Logical shift left. */ -UINT32 LSL_x (UINT32 w, int i) -{ - // LSL #0 copies C into carry out and returns unmodified value - if (i == 0) - { - ARM7.carry = (ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_C) ? 1 : 0; - return w; - } - // LSL #32 copies LSB to carry out and returns zero - if (i == 32) - { - ARM7.carry = w & 1; - return 0; - } - // LSL > #32 returns zero for both carry and output - if (i > 32) - { - ARM7.carry = 0; - return 0; - } - // normal shift - ARM7.carry = (w & (1 << (32 - i))) ? 1 : 0; - w = SHL (w, i); - return w; -} - //-------------------------------------------------------------------------- - - //-------------------------------------------------------------------------- - /** Logical shift right. */ -UINT32 LSR_x (UINT32 w, int i) -{ - // LSR #32 copies MSB to carry out and returns zero - if (i == 32) - { - ARM7.carry = (w & (1 << 31)) ? 1 : 0; - return 0; - } - // LSR > #32 returns zero for both carry and output - if (i > 32) - { - ARM7.carry = 0; - return 0; - } - // normal shift - ARM7.carry = (w & (1 << (i - 1))) ? 1 : 0; - w = SHR (w, i); - return w; -} - //-------------------------------------------------------------------------- - - //-------------------------------------------------------------------------- - /** Arithmetic shift right. */ -UINT32 ASR_x (UINT32 w, int i) -{ - // ASR >= #32 carry out and output value depends on the minus sign - if (i >= 32) - { - if (w & (1 << 31)) - { - ARM7.carry = 1; - return ~0; - } - - ARM7.carry = 0; - return 0; - } - // normal shift - ARM7.carry = (w & (1 << (i - 1))) ? 1 : 0; - w = SAR (w, i); - return w; -} - //-------------------------------------------------------------------------- - - //-------------------------------------------------------------------------- - /** Rotate right. */ -UINT32 ROR_x (UINT32 w, int i) -{ - // mask count to [0; 31] - i &= 0x1f; - // ROR #32,#64,etc. copies MSB into carry out and returns unmodified value - if (i == 0) - { - ARM7.carry = (w & (1 << 31)) ? 1 : 0; - return w; - } - // normal shift - ARM7.carry = (w & (1 << (i-1))) ? 1 : 0; - w = ROR (w, i); - return w; -} - //-------------------------------------------------------------------------- - - //-------------------------------------------------------------------------- - /** Rotate right extended. */ -UINT32 RRX_1 (UINT32 w) - { - // same as RCR by 1 in IA32 - ARM7.carry = w & 1; - return (w >> 1) | ((ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_C) << 2); - } - //-------------------------------------------------------------------------- - - //-------------------------------------------------------------------------- - /** Group 00x opcodes. */ -void R_G00x () - { -#ifdef ARM7_THUMB - // 24 constant bits - if ((ARM7.kod & 0x0ffffff0) == 0x012fff10) // BX - branch with possible mode transfer - { - #ifdef ARM7_THUMB - int Rn = ARM7.Rx[ARM7.kod & 0xf]; - - // switching to Thumb mode? - if (Rn & 1) - { - ARM7_SetCPSR(ARM7.Rx[ARM7_CPSR] | ARM7_CPSR_T); - } - - ARM7.Rx[ARM7_PC] = Rn & ~1; - #endif - } - // 15 constant bits - else if ((ARM7.kod & 0x0fb00ff0) == 0x01000090) - R_SWP (); - // 10 constant bits - else if ((ARM7.kod & 0x0fc000f0) == 0x00000090) - R_MUL_MLA (); - // 10 constant bits - else if ((ARM7.kod & 0x0e400f90) == 0x00000090) - R_HSDT (); - // 9 constant bits - else if ((ARM7.kod & 0x0f8000f0) == 0x00800090) - { -// logerror("G00x / Multiply long\n"); - } - // 6 constant bits - else if ((ARM7.kod & 0x0e400090) == 0x00400090) - R_HSDT (); - // 2 constant bits - else - { - if ((ARM7.kod & 0x01900000) == 0x01000000) - // TST, TEQ, CMP & CMN without S bit are "PSR Transfer" - R_PSR (); - else - // the rest is "Data processing" - R_DP (); - } -#else - if ((ARM7.kod & 0x03b00090) == 0x01000090) - R_SWP (); - else if ((ARM7.kod & 0x03c00090) == 0x00000090) - R_MUL_MLA (); - else - { - if ((ARM7.kod & 0x01900000) == 0x01000000) - // TST, TEQ, CMP & CMN without S bit are "PSR Transfer" - R_PSR (); - else - // the rest is "Data processing" - R_DP (); - } -#endif - } - //-------------------------------------------------------------------------- - - //-------------------------------------------------------------------------- - /** Single data swap. */ -void R_SWP () - { - int Rn, Rd, Rm; - UINT32 adres, w; - -#define BIT_B (ARM7.kod & (1 << 21)) - - s_cykle += 4; - // none of these can be PC - Rn = (ARM7.kod >> 16) & 15; - Rd = (ARM7.kod >> 12) & 15; - Rm = ARM7.kod & 15; - adres = ARM7.Rx [Rn]; - - if (BIT_B) - { - // "byte" - w = arm7_read_8 (adres); - arm7_write_8 (adres, (UINT8)ARM7.Rx [Rm]); - } - else - { - // "word" - w = RBOD (arm7_read_32 (adres & ~3), adres & 3); - arm7_write_32 (adres & ~3, ARM7.Rx [Rm]); - } - ARM7.Rx [Rd] = w; - -#undef BIT_B - } - //-------------------------------------------------------------------------- - - //-------------------------------------------------------------------------- - /** Multiply instructions. */ -void R_MUL_MLA () - { - int Rm, Rs, Rn, Rd; - UINT32 wynik; - -#define BIT_A (ARM7.kod & (1 << 21)) -#define BIT_S (ARM7.kod & (1 << 20)) - - s_cykle += 2; - // none of these can be PC, also Rd != Rm - Rd = (ARM7.kod >> 16) & 15, - Rs = (ARM7.kod >> 8) & 15, - Rm = ARM7.kod & 15; - - // MUL - wynik = ARM7.Rx [Rm] * ARM7.Rx [Rs]; - if (BIT_A) - { - // MLA - Rn = (ARM7.kod >> 12) & 15; - wynik += ARM7.Rx [Rn]; - } - ARM7.Rx [Rd] = wynik; - - if (BIT_S) - { - // V remains unchanged, C is undefined - ARM7.Rx [ARM7_CPSR] &= ~(ARM7_CPSR_N | ARM7_CPSR_Z); - if (wynik == 0) - ARM7.Rx [ARM7_CPSR] |= ARM7_CPSR_Z; - ARM7.Rx [ARM7_CPSR] |= wynik & 0x80000000; - } - -#undef BIT_S -#undef BIT_A - } - //-------------------------------------------------------------------------- - - //-------------------------------------------------------------------------- - /** PSR Transfer. */ -void R_PSR () - { - int Rd, Rm; - UINT32 w, arg; - -#define BIT_I (ARM7.kod & (1 << 25)) -#define BIT_P (ARM7.kod & (1 << 22)) - - // none of the registers involved can be PC - - if (ARM7.kod & (1 << 21)) - { - // MSR - Rm = ARM7.kod & 15; - if (BIT_I) - // immediate (lower 12 bits) - arg = ROR (ARM7.kod & 0xff, ((ARM7.kod >> 8) & 0xf) * 2); - else - // register - arg = ARM7.Rx [Rm]; - - // decode mask bits - if (BIT_P) - { - w = ARM7.Rx [ARM7_SPSR]; - if (ARM7_CPSR_M (ARM7.Rx [ARM7_CPSR]) > ARM7_CPSR_M_usr &&\ - ARM7_CPSR_M (ARM7.Rx [ARM7_CPSR]) < ARM7_CPSR_M_sys) - { - if (ARM7.kod & (1 << 16)) - w = (w & 0xffffff00) | (arg & 0x000000ff); - if (ARM7.kod & (1 << 17)) - w = (w & 0xffff00ff) | (arg & 0x0000ff00); - if (ARM7.kod & (1 << 18)) - w = (w & 0xff00ffff) | (arg & 0x00ff0000); - if (ARM7.kod & (1 << 19)) - // ARMv5E should have 0xf8000000 argument mask - w = (w & 0x00ffffff) | (arg & 0xf0000000); - } - // force valid mode - w |= 0x10; - ARM7.Rx [ARM7_SPSR] = w; - } - else - { - w = ARM7.Rx [ARM7_CPSR]; - // only flags can be changed in User mode - if (ARM7_CPSR_M (ARM7.Rx [ARM7_CPSR]) != ARM7_CPSR_M_usr) - { - if (ARM7.kod & (1 << 16)) - w = (w & 0xffffff00) | (arg & 0x000000ff); - if (ARM7.kod & (1 << 17)) - w = (w & 0xffff00ff) | (arg & 0x0000ff00); - if (ARM7.kod & (1 << 18)) - w = (w & 0xff00ffff) | (arg & 0x00ff0000); - } - if (ARM7.kod & (1 << 19)) - // ARMv5E should have 0xf8000000 argument mask - w = (w & 0x00ffffff) | (arg & 0xf0000000); - // force valid mode - w |= 0x10; - ARM7_SetCPSR (w); - } - } - else - { - // MRS - Rd = (ARM7.kod >> 12) & 15; - if (BIT_P) - ARM7.Rx [Rd] = ARM7.Rx [ARM7_SPSR]; - else - ARM7.Rx [Rd] = ARM7.Rx [ARM7_CPSR]; - } - -#undef BIT_P -#undef BIT_I - } - //-------------------------------------------------------------------------- - - //-------------------------------------------------------------------------- - /** Data processing instructions. */ -void R_DP () - { - int Rn; - ARM7_REG arg1, arg2, w; - -#define BIT_I (ARM7.kod & (1 << 25)) - - // Rn can be PC, so we need to account for that - Rn = (ARM7.kod >> 16) & 15; - - if (BIT_I) - { - if (Rn != ARM7_PC) - arg1 = ARM7.Rx [Rn]; - else - arg1 = (ARM7.Rx [ARM7_PC] & ~3) + 8 + PC_ADJUSTMENT; - // immediate in lowest 12 bits - arg2 = ROR (ARM7.kod & 0xff, ((ARM7.kod >> 8) & 0xf) * 2); - // preload carry out from C - ARM7.carry = (ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_C) ? 1 : 0; - } - else - { - if (Rn != ARM7_PC) - arg1 = ARM7.Rx [Rn]; - else - // register or immediate shift? - if (ARM7.kod & (1 << 4)) - arg1 = (ARM7.Rx [ARM7_PC] & ~3) + 12 + PC_ADJUSTMENT; - else - arg1 = (ARM7.Rx [ARM7_PC] & ~3) + 8 + PC_ADJUSTMENT; - // calculate in barrel shifter - arg2 = WyliczPrzes (); - } - - // decode instruction type - switch ((ARM7.kod >> 21) & 15) - { - case 0: - // AND - R_WynikDP (arg1 & arg2); - break; - - case 1: - // EOR - R_WynikDP (arg1 ^ arg2); - break; - - case 2: - // SUB - w = arg1 - arg2; - ARM7.carry = SUBCARRY (arg1, arg2, w); - ARM7.overflow = SUBOVERFLOW (arg1, arg2, w); - R_WynikDP (w); - break; - - case 3: - // RSB - w = arg2 - arg1; - ARM7.carry = SUBCARRY (arg2, arg1, w); - ARM7.overflow = SUBOVERFLOW (arg2, arg1, w); - R_WynikDP (w); - break; - - case 4: - // ADD - w = arg1 + arg2; - ARM7.carry = ADDCARRY (arg1, arg2, w); - ARM7.overflow = ADDOVERFLOW (arg1, arg2, w); - R_WynikDP (w); - break; - - case 5: - // ADC - w = arg1 + arg2 + ((ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_C) ? 1 : 0); - ARM7.carry = ADDCARRY (arg1, arg2, w); - ARM7.overflow = ADDOVERFLOW (arg1, arg2, w); - R_WynikDP (w); - break; - - case 6: - // SBC - w = arg1 - arg2 - ((ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_C) ? 0 : 1); - ARM7.carry = SUBCARRY (arg1, arg2, w); - ARM7.overflow = SUBOVERFLOW (arg1, arg2, w); - R_WynikDP (w); - break; - - case 7: - // RSC - w = arg2 - arg1 - ((ARM7.Rx [ARM7_CPSR] & ARM7_CPSR_C) ? 0 : 1); - ARM7.carry = SUBCARRY (arg2, arg1, w); - ARM7.overflow = SUBOVERFLOW (arg2, arg1, w); - R_WynikDP (w); - break; - - case 8: - // TST - R_FlagiDP (arg1 & arg2); - break; - - case 9: - // TEQ - R_FlagiDP (arg1 ^ arg2); - break; - - case 10: - // CMP - w = arg1 - arg2; - ARM7.carry = SUBCARRY (arg1, arg2, w); - ARM7.overflow = SUBOVERFLOW (arg1, arg2, w); - R_FlagiDP (w); - break; - - case 11: - // CMN - w = arg1 + arg2; - ARM7.carry = ADDCARRY (arg1, arg2, w); - ARM7.overflow = ADDOVERFLOW (arg1, arg2, w); - R_FlagiDP (w); - break; - - case 12: - // ORR - R_WynikDP (arg1 | arg2); - break; - - case 13: - // MOV - R_WynikDP (arg2); - break; - - case 14: - // BIC - R_WynikDP (arg1 & ~arg2); - break; - - case 15: - // MVN - R_WynikDP (~arg2); - break; - } - -#undef BIT_I - } - //-------------------------------------------------------------------------- - - //-------------------------------------------------------------------------- - /** Data processing result writeback. */ -void R_WynikDP (ARM7_REG w) - { - int Rd; - -#define BIT_S (ARM7.kod & (1 << 20)) - - Rd = (ARM7.kod >> 12) & 15; - ARM7.Rx [Rd] = w; - if (BIT_S) - { - if (Rd == ARM7_PC) - { - s_cykle += 4; - // copy current SPSR to CPSR - ARM7_SetCPSR (ARM7.Rx [ARM7_SPSR]); - } - else - // save new flags - R_FlagiDP (w); - } - -#undef BIT_S - } - //-------------------------------------------------------------------------- - - //-------------------------------------------------------------------------- - /** Data processing flags writeback. */ -void R_FlagiDP (ARM7_REG w) - { - // arithmetic or logical instruction? - if (s_tabAL [(ARM7.kod >> 21) & 15]) - { - ARM7.Rx [ARM7_CPSR] &= ~(ARM7_CPSR_N | ARM7_CPSR_Z | ARM7_CPSR_C |\ - ARM7_CPSR_V); - ARM7.Rx [ARM7_CPSR] |= ARM7.overflow << 28; - } - else - ARM7.Rx [ARM7_CPSR] &= ~(ARM7_CPSR_N | ARM7_CPSR_Z | ARM7_CPSR_C); - ARM7.Rx [ARM7_CPSR] |= ARM7.carry << 29; - if (w == 0) - ARM7.Rx [ARM7_CPSR] |= ARM7_CPSR_Z; - ARM7.Rx [ARM7_CPSR] |= w & 0x80000000; - } - //-------------------------------------------------------------------------- - - //-------------------------------------------------------------------------- - /** Single data transfer. */ -void R_SDT (void) - { - int Rn, Rd, offset; - UINT32 adres, w = 0; - -#define BIT_I (ARM7.kod & (1 << 25)) -#define BIT_P (ARM7.kod & (1 << 24)) -#define BIT_U (ARM7.kod & (1 << 23)) -#define BIT_B (ARM7.kod & (1 << 22)) -#define BIT_W (ARM7.kod & (1 << 21)) -#define BIT_L (ARM7.kod & (1 << 20)) - - if (BIT_I && (ARM7.kod & (1 << 4))) - { - R_Und (); - return; - } - - Rn = (ARM7.kod >> 16) & 15, - Rd = (ARM7.kod >> 12) & 15; - if (Rn != ARM7_PC) - adres = ARM7.Rx [Rn]; - else - adres = ARM7.Rx [ARM7_PC] & ~3; - if (!BIT_L) - if (Rd != ARM7_PC) - w = ARM7.Rx [Rd]; - else - w = (ARM7.Rx [ARM7_PC] & ~3) + 12 + PC_ADJUSTMENT; - - if (BIT_I) - // calculate value in barrel shifter - offset = WyliczPrzes (); - else - // immediate in lowest 12 bits - offset = ARM7.kod & 0xfff; - - if (!BIT_U) - offset = -offset; - if (BIT_P) - { - // "pre-index" - adres += offset; - if (BIT_W) - // "write-back" - ARM7.Rx [Rn] = adres; - } - else - // "post-index" - ARM7.Rx [Rn] += offset; - if (Rn == ARM7_PC) - adres += 8 + PC_ADJUSTMENT; - - if (BIT_L) - { - s_cykle += 3; - // "load" - if (BIT_B) - // "byte" - ARM7.Rx [Rd] = arm7_read_8 (adres); - else - // "word" - ARM7.Rx [Rd] = RBOD (arm7_read_32 (adres & ~3), adres & 3); - } - else - { - s_cykle += 2; - // "store" - if (BIT_B) - // "byte" - arm7_write_8 (adres, (UINT8)w); - else - // "word" - arm7_write_32 (adres & ~3, w); - } - -#undef BIT_L -#undef BIT_W -#undef BIT_B -#undef BIT_U -#undef BIT_P -#undef BIT_I - } - //-------------------------------------------------------------------------- - - //-------------------------------------------------------------------------- - /** Undefined. */ -void R_Und () - { - UINT32 sr = ARM7.Rx [ARM7_CPSR]; - ARM7_SetCPSR (ARM7_CPSR_MX (sr, ARM7_CPSR_M_und) | ARM7_CPSR_I); - ARM7.Rx [ARM7_SPSR] = sr; - ARM7.Rx [ARM7_LR] = ARM7.Rx [ARM7_PC] + 4; - ARM7.Rx [ARM7_PC] = 0x00000004; - } - //-------------------------------------------------------------------------- - -#define BIT_U (ARM7.kod & (1 << 23)) -#define BIT_S (ARM7.kod & (1 << 22)) - //-------------------------------------------------------------------------- - /** Block Data Transfer. */ -void R_BDT () - { - int Rn, usr = FALSE; - UINT32 adres; - ARM7_REG cpsr = 0; - -#define BIT_L (ARM7.kod & (1 << 20)) - - // Rn can't be PC - Rn = (ARM7.kod >> 16) & 15; - adres = ARM7.Rx [Rn]; - - // transfer in User mode - if (BIT_S) - if (!BIT_L || !(ARM7.kod & (1 << ARM7_PC))) - usr = TRUE; - - if (usr) - { -//EMU_BLAD (BLAD_WEWNETRZNY, "BDT: user transfer"); - cpsr = ARM7.Rx [ARM7_CPSR]; - ARM7_SetCPSR (ARM7_CPSR_MX (cpsr, ARM7_CPSR_M_usr)); - } - - if (BIT_L) - // "load" - R_LDM (Rn, adres); - else - // "store" - R_STM (Rn, adres); - - if (usr) - ARM7_SetCPSR (cpsr); - -#undef BIT_L - } - //-------------------------------------------------------------------------- - -#define BIT_P (ARM7.kod & (1 << 24)) -#define BIT_W (ARM7.kod & (1 << 21)) - //-------------------------------------------------------------------------- - /** Block load instructions. */ -void R_LDM (int Rn, UINT32 adres) - { - int i, n, sp; - - // count registers on the list - for (i = 0, n = 0; i < 16; i++) - if (ARM7.kod & (1 << i)) - n++; - s_cykle += n * 2 + 1; - - n <<= 2; - // transfer type - sp = BIT_P; - if (!BIT_U) - { - // "down" - n = -n; - adres += n; - sp = !sp; - } - if (BIT_W) - // "write-back" - ARM7.Rx [Rn] += n; - - // for all registers in mask - if (sp) - for (i = 0; i < 16; i++) - { - if (!(ARM7.kod & (1 << i))) - continue; - adres += 4; - ARM7.Rx [i] = arm7_read_32 (adres); - } - else - for (i = 0; i < 16; i++) - { - if (!(ARM7.kod & (1 << i))) - continue; - ARM7.Rx [i] = arm7_read_32 (adres); - adres += 4; - } - - // special case - mode change when PC is written - if ((ARM7.kod & (1 << ARM7_PC)) && BIT_S) - ARM7_SetCPSR (ARM7.Rx [ARM7_SPSR]); - } - //-------------------------------------------------------------------------- - - //-------------------------------------------------------------------------- - /** Block store instructions. */ -void R_STM (int Rn, UINT32 adres) - { - int i, n, p, sp; - - // count registers on the list and remember the first one - for (i = 0, n = 0, p = -1; i < 16; i++) - if (ARM7.kod & (1 << i)) - { - n++; - if (p < 0) - p = i; - } - s_cykle += n * 2; - - n <<= 2; - // transfer type - sp = BIT_P; - if (!BIT_U) - { - // "down" - n = -n; - adres += n; - sp = !sp; - } - // if base register is not the first one to transfer, writeback happens here - if (BIT_W && Rn != p) - // "write-back" - ARM7.Rx [Rn] += n; - - // registers R0-R14 - if (sp) - for (i = 0; i < 15; i++) - { - if (!(ARM7.kod & (1 << i))) - continue; - adres += 4; - arm7_write_32 (adres, ARM7.Rx [i]); - } - else - for (i = 0; i < 15; i++) - { - if (!(ARM7.kod & (1 << i))) - continue; - arm7_write_32 (adres, ARM7.Rx [i]); - adres += 4; - } - - // PC is a special case - if (ARM7.kod & (1 << ARM7_PC)) - { - if (sp) - { - adres += 4; - arm7_write_32 (adres, (ARM7.Rx [ARM7_PC] & ~3) + 12 + PC_ADJUSTMENT); - } - else - { - arm7_write_32 (adres, (ARM7.Rx [ARM7_PC] & ~3) + 12 + PC_ADJUSTMENT); - adres += 4; - } - } - - // if base register is the first one to transfer, writeback happens here - if (BIT_W && Rn == p) - // "write-back" - ARM7.Rx [Rn] += n; - } - //-------------------------------------------------------------------------- -#undef BIT_W -#undef BIT_P -#undef BIT_S -#undef BIT_U - - //-------------------------------------------------------------------------- - /** Branch/Branch with link. */ -void R_B_BL () - { - INT32 offset; - -#define BIT_L (ARM7.kod & (1 << 24)) - - s_cykle += 4; - offset = (ARM7.kod & 0x00ffffff) << 2; - if (offset & 0x02000000) - offset |= 0xfc000000; - offset += 8 + PC_ADJUSTMENT; - if (BIT_L) - // "Branch with link" - ARM7.Rx [ARM7_LR] = (ARM7.Rx [ARM7_PC] & ~3) + 4 + PC_ADJUSTMENT; - // "Branch" - ARM7.Rx [ARM7_PC] += offset; - -#undef BIT_L - } - //-------------------------------------------------------------------------- - - //-------------------------------------------------------------------------- - /** Group 110 opcodes. */ -void R_G110 () - { -// logerror("ARM7: G110 / Coprocessor data transfer\n"); - } - //-------------------------------------------------------------------------- - - //-------------------------------------------------------------------------- - /** Group 111 opcodes. */ -void R_G111 () - { - if ((ARM7.kod & 0xf0000000) == 0xe0000000) - { -/* if (ARM7.kod & (1 << 4)) - logerror("ARM7: G111 / Coprocessor register transfer\n"); - else - logerror("ARM7: G111 / Coprocessor data operation\n"); */ - } - else - { - UINT32 sr = ARM7.Rx [ARM7_CPSR]; - ARM7_SetCPSR (ARM7_CPSR_MX (sr, ARM7_CPSR_M_svc) | ARM7_CPSR_I); - ARM7.Rx [ARM7_SPSR] = sr; - ARM7.Rx [ARM7_LR] = ARM7.Rx [ARM7_PC]; - ARM7.Rx [ARM7_PC] = 0x00000008; - } - } - //-------------------------------------------------------------------------- - -#ifdef ARM7_THUMB - //-------------------------------------------------------------------------- - /** Halfword and Signed Data Transfer. */ -void R_HSDT () - { - int Rm, Rd, Rn, offset; - uint32_t adres, w; - -#define BIT_P (ARM7.kod & (1 << 24)) -#define BIT_U (ARM7.kod & (1 << 23)) -#define BIT_W (ARM7.kod & (1 << 21)) -#define BIT_L (ARM7.kod & (1 << 20)) -#define BIT_S (ARM7.kod & (1 << 6)) -#define BIT_H (ARM7.kod & (1 << 5)) - - // Rm can't be PC - Rn = (ARM7.kod >> 16) & 15; - Rd = (ARM7.kod >> 12) & 15; - if (Rn != ARM7_PC) - adres = ARM7.Rx [Rn]; - else - adres = ARM7.Rx [ARM7_PC] & ~3; - if (!BIT_L) - if (Rd != ARM7_PC) - w = ARM7.Rx [Rd]; - else - w = (ARM7.Rx [ARM7_PC] & ~3) + 12 + POPRAWKA_PC; - - if (1 << 22) - // immediate - offset = ((ARM7.kod >> 4) & 0xf0) | (ARM7.kod & 15); - else - { - // register - Rm = ARM7.kod & 15; - offset = ARM7.Rx [Rm]; - } - - if (!BIT_U) - offset = -offset; - if (BIT_P) - { - // "pre-index" - adres += offset; - if (BIT_W) - // "write-back" - ARM7.Rx [Rn] = adres; - } - else - // "post-index" - ARM7.Rx [Rn] += offset; - if (Rn == ARM7_PC) - adres += 8 + POPRAWKA_PC; - - if (BIT_L) - { - // "load" - s_cykle += 3; - if (BIT_S) - { - if (BIT_H) - // "signed halfword" - ARM7.Rx [Rd] = (INT32)(INT16)arm7_read_16 (adres); - else - // "signed byte" - ARM7.Rx [Rd] = (INT32)(INT8)arm7_read_8 (adres); - } - else - // "unsigned halfword" - ARM7.Rx [Rd] = arm7_read_16 (adres); - } - else - { - // store - s_cykle += 2; - if (BIT_H) - // "halfword" - arm7_write_16 (adres, (UINT16)w); - else - // "byte" - arm7_write_8 (adres, (UINT8)w); - } - -#undef BIT_H -#undef BIT_S -#undef BIT_L -#undef BIT_W -#undef BIT_U -#undef BIT_P - } - //-------------------------------------------------------------------------- -#endif diff --git a/Frameworks/AudioOverload/aosdk/eng_dsf/arm7i.h b/Frameworks/AudioOverload/aosdk/eng_dsf/arm7i.h deleted file mode 100644 index 5a2e611ba..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_dsf/arm7i.h +++ /dev/null @@ -1,19 +0,0 @@ -// -// ARM7 processor emulator - interpreter core -// version 1.6 / 2008-02-16 -// (c) Radoslaw Balcewicz -// - -#ifndef _ARM7i_h_ -#define _ARM7i_h_ - -#include "arm7.h" - - //-------------------------------------------------------------------------- - // public functions - - /** Single step, returns number of burned cycles. */ -int ARM7i_Step(void); - //-------------------------------------------------------------------------- - -#endif diff --git a/Frameworks/AudioOverload/aosdk/eng_dsf/arm7memil.c b/Frameworks/AudioOverload/aosdk/eng_dsf/arm7memil.c deleted file mode 100644 index b9daed837..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_dsf/arm7memil.c +++ /dev/null @@ -1,56 +0,0 @@ -// memory inline functions shared by ARM and THUMB modes - -static INLINE void arm7_write_32(UINT32 addr, UINT32 data ) -{ - addr &= ~3; - dc_write32(addr,data); -} - - -static INLINE void arm7_write_16(UINT32 addr, UINT16 data) -{ - addr &= ~1; - dc_write16(addr,data); -} - -static INLINE void arm7_write_8(UINT32 addr, UINT8 data) -{ - dc_write8(addr,data); -} - -static INLINE UINT32 arm7_read_32(UINT32 addr) -{ - UINT32 result; - int k = (addr & 3) << 3; - - if (k) - { - result = dc_read32 (addr & ~3); - result = (result >> k) | (result << (32 - k)); - } - else - { - result = dc_read32(addr); - } - return result; -} - -static INLINE UINT16 arm7_read_16(UINT32 addr) -{ - UINT16 result; - - result = dc_read16(addr & ~1); - - if (addr & 1) - { - result = ((result>>8) & 0xff) | ((result&0xff)<<8); - } - - return result; -} - -static INLINE UINT8 arm7_read_8(UINT32 addr) -{ - return dc_read8(addr); -} - diff --git a/Frameworks/AudioOverload/aosdk/eng_dsf/arm7thumb.c b/Frameworks/AudioOverload/aosdk/eng_dsf/arm7thumb.c deleted file mode 100644 index f9780cab0..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_dsf/arm7thumb.c +++ /dev/null @@ -1,1176 +0,0 @@ -// -// ARM7 processor emulator - THUMB support -// version 2.0 / 2008-02-08 -// By R. Belmont and SGINut -// - -#include "arm7.h" -#include "arm7i.h" -#include "arm7thumb.h" - -// base cycle counts for Thumb instructions -static const int thumbCycles[256] = -{ -// 0 1 2 3 4 5 6 7 8 9 a b c d e f - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 0 - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 1 - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 2 - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 3 - 1, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, // 4 - 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, // 5 - 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, // 6 - 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, // 7 - 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, // 8 - 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, // 9 - 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, // a - 1, 1, 1, 1, 2, 2, 1, 1, 1, 1, 1, 1, 2, 4, 1, 1, // b - 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, // c - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3, // d - 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, // e - 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2 // f -}; - -// utility macros - -#define IsNeg(i) ((i) >> 31) -#define IsPos(i) ((~(i)) >> 31) - -#define N_BIT 31 -#define Z_BIT 30 -#define C_BIT 29 -#define V_BIT 28 -#define SIGN_BIT ((UINT32)(1<<31)) - -#define HandleThumbALUAddFlags(rd, rn, op2) \ - ARM7_SetCPSR( \ - ((GET_CPSR &~ (ARM7_CPSR_N | ARM7_CPSR_Z | ARM7_CPSR_V | ARM7_CPSR_C)) \ - | (((!THUMB_SIGN_BITS_DIFFER(rn, op2)) && THUMB_SIGN_BITS_DIFFER(rn, rd)) \ - << V_BIT) \ - | (((~(rn)) < (op2)) << C_BIT) \ - | HandleALUNZFlags(rd))); \ - R15 += 2; - -#define HandleThumbALUSubFlags(rd, rn, op2) \ - ARM7_SetCPSR( \ - ((GET_CPSR &~ (ARM7_CPSR_N | ARM7_CPSR_Z | ARM7_CPSR_V | ARM7_CPSR_C)) \ - | ((THUMB_SIGN_BITS_DIFFER(rn, op2) && THUMB_SIGN_BITS_DIFFER(rn, rd)) \ - << V_BIT) \ - | (((IsNeg(rn) & IsPos(op2)) | (IsNeg(rn) & IsPos(rd)) | (IsPos(op2) & IsPos(rd))) ? ARM7_CPSR_C : 0) \ - | HandleALUNZFlags(rd))); \ - R15 += 2; - -#define HandleALUNZFlags(rd) \ - (((rd) & SIGN_BIT) | ((!(rd)) << Z_BIT)) - -// memory accessors -#include "arm7memil.c" - -// public functions -int ARM7i_Thumb_Step() -{ - UINT32 readword; - UINT32 addr, insn; - UINT32 rm, rn, rs, rd, op2, imm, rrs, rrd; - INT32 offs; - UINT32 pc = ARM7.Rx[ARM7_PC]; - int cycles; - - insn = arm7_read_16(pc & (~1)); - - cycles = (3 - thumbCycles[insn >> 8]); - - switch( ( insn & THUMB_INSN_TYPE ) >> THUMB_INSN_TYPE_SHIFT ) - { - case 0x0: /* Logical shifting */ - ARM7_SetCPSR(GET_CPSR &~ (ARM7_CPSR_N | ARM7_CPSR_Z)); - if( insn & THUMB_SHIFT_R ) /* Shift right */ - { - rs = ( insn & THUMB_ADDSUB_RS ) >> THUMB_ADDSUB_RS_SHIFT; - rd = ( insn & THUMB_ADDSUB_RD ) >> THUMB_ADDSUB_RD_SHIFT; - rrs = GET_REGISTER(rs); - offs = ( insn & THUMB_SHIFT_AMT ) >> THUMB_SHIFT_AMT_SHIFT; - if( offs != 0 ) - { - SET_REGISTER( rd, rrs >> offs ); - if( rrs & ( 1 << (offs-1) ) ) - { - ARM7_SetCPSR(GET_CPSR | ARM7_CPSR_C); - } - else - { - ARM7_SetCPSR(GET_CPSR &~ ARM7_CPSR_C); - } - } - else - { - SET_REGISTER( rd, 0 ); - if( rrs & 0x80000000 ) - { - ARM7_SetCPSR( GET_CPSR | ARM7_CPSR_C ); - } - else - { - ARM7_SetCPSR( GET_CPSR &~ ARM7_CPSR_C ); - } - } - ARM7_SetCPSR(GET_CPSR &~ ( ARM7_CPSR_Z | ARM7_CPSR_N ) ); - ARM7_SetCPSR( GET_CPSR | HandleALUNZFlags( GET_REGISTER(rd) ) ); - R15 += 2; - } - else /* Shift left */ - { - rs = ( insn & THUMB_ADDSUB_RS ) >> THUMB_ADDSUB_RS_SHIFT; - rd = ( insn & THUMB_ADDSUB_RD ) >> THUMB_ADDSUB_RD_SHIFT; - rrs = GET_REGISTER(rs); - offs = ( insn & THUMB_SHIFT_AMT ) >> THUMB_SHIFT_AMT_SHIFT; - if( offs != 0 ) - { - SET_REGISTER( rd, rrs << offs ); - if( rrs & ( 1 << ( 31 - ( offs - 1 ) ) ) ) - { - ARM7_SetCPSR(GET_CPSR | ARM7_CPSR_C); - } - else - { - ARM7_SetCPSR(GET_CPSR &~ ARM7_CPSR_C); - } - } - else - { - SET_REGISTER( rd, rrs ); - } - ARM7_SetCPSR( GET_CPSR &~ ( ARM7_CPSR_Z | ARM7_CPSR_N ) ); - ARM7_SetCPSR( GET_CPSR | HandleALUNZFlags( GET_REGISTER(rd) ) ); - R15 += 2; - } - break; - case 0x1: /* Arithmetic */ - if( insn & THUMB_INSN_ADDSUB ) - { - switch( ( insn & THUMB_ADDSUB_TYPE ) >> THUMB_ADDSUB_TYPE_SHIFT ) - { - case 0x0: /* ADD Rd, Rs, Rn */ - rn = GET_REGISTER( ( insn & THUMB_ADDSUB_RNIMM ) >> THUMB_ADDSUB_RNIMM_SHIFT ); - rs = GET_REGISTER( ( insn & THUMB_ADDSUB_RS ) >> THUMB_ADDSUB_RS_SHIFT ); - rd = ( insn & THUMB_ADDSUB_RD ) >> THUMB_ADDSUB_RD_SHIFT; - SET_REGISTER( rd, rs + rn ); - HandleThumbALUAddFlags( GET_REGISTER(rd), rs, rn ); - break; - case 0x1: /* SUB Rd, Rs, Rn */ - rn = GET_REGISTER( ( insn & THUMB_ADDSUB_RNIMM ) >> THUMB_ADDSUB_RNIMM_SHIFT ); - rs = GET_REGISTER( ( insn & THUMB_ADDSUB_RS ) >> THUMB_ADDSUB_RS_SHIFT ); - rd = ( insn & THUMB_ADDSUB_RD ) >> THUMB_ADDSUB_RD_SHIFT; - SET_REGISTER( rd, rs - rn ); - HandleThumbALUSubFlags( GET_REGISTER(rd), rs, rn ); - break; - case 0x2: /* ADD Rd, Rs, #imm */ - imm = ( insn & THUMB_ADDSUB_RNIMM ) >> THUMB_ADDSUB_RNIMM_SHIFT; - rs = GET_REGISTER( ( insn & THUMB_ADDSUB_RS ) >> THUMB_ADDSUB_RS_SHIFT ); - rd = ( insn & THUMB_ADDSUB_RD ) >> THUMB_ADDSUB_RD_SHIFT; - SET_REGISTER( rd, rs + imm ); - HandleThumbALUAddFlags( GET_REGISTER(rd), rs, imm ); - break; - case 0x3: /* SUB Rd, Rs, #imm */ - imm = ( insn & THUMB_ADDSUB_RNIMM ) >> THUMB_ADDSUB_RNIMM_SHIFT; - rs = GET_REGISTER( ( insn & THUMB_ADDSUB_RS ) >> THUMB_ADDSUB_RS_SHIFT ); - rd = ( insn & THUMB_ADDSUB_RD ) >> THUMB_ADDSUB_RD_SHIFT; - SET_REGISTER( rd, rs - imm ); - HandleThumbALUSubFlags( GET_REGISTER(rd), rs,imm ); - break; - default: - printf("%08x: G1 Undefined Thumb instruction: %04x\n", pc, insn); - R15 += 2; - break; - } - } - else - { - /* ASR.. */ - //if( insn & THUMB_SHIFT_R ) /* Shift right */ - { - rs = ( insn & THUMB_ADDSUB_RS ) >> THUMB_ADDSUB_RS_SHIFT; - rd = ( insn & THUMB_ADDSUB_RD ) >> THUMB_ADDSUB_RD_SHIFT; - rrs = GET_REGISTER(rs); - offs = ( insn & THUMB_SHIFT_AMT ) >> THUMB_SHIFT_AMT_SHIFT; - if( offs == 0 ) - { - offs = 32; - } - - if( offs >= 32 ) - { - if( rrs >> 31 ) - { - ARM7_SetCPSR(GET_CPSR | ARM7_CPSR_C); - } - else - { - ARM7_SetCPSR(GET_CPSR &~ ARM7_CPSR_C); - } - SET_REGISTER( rd, ( rrs & 0x80000000 ) ? 0xFFFFFFFF : 0x00000000 ); - } - else - { - if( ( rrs >> ( offs - 1 ) ) & 1 ) - { - ARM7_SetCPSR( GET_CPSR | ARM7_CPSR_C ); - } - else - { - ARM7_SetCPSR( GET_CPSR &~ ARM7_CPSR_C ); - } - SET_REGISTER( rd, ( rrs & 0x80000000 ) ? ( ( 0xFFFFFFFF << ( 32 - offs ) ) | ( rrs >> offs ) ) : ( rrs >> offs ) ); - } - ARM7_SetCPSR(GET_CPSR &~ (ARM7_CPSR_N | ARM7_CPSR_Z)); - ARM7_SetCPSR( GET_CPSR | HandleALUNZFlags( GET_REGISTER(rd) ) ); - R15 += 2; - } - - } - break; - case 0x2: /* CMP / MOV */ - if( insn & THUMB_INSN_CMP ) - { - rn = GET_REGISTER( ( insn & THUMB_INSN_IMM_RD ) >> THUMB_INSN_IMM_RD_SHIFT ); - op2 = ( insn & THUMB_INSN_IMM ); - rd = rn - op2; - HandleThumbALUSubFlags( rd, rn, op2 ); - //mame_printf_debug("%08x: xxx Thumb instruction: CMP R%d (%08x), %02x (N=%d, Z=%d, C=%d, V=%d)\n", pc, ( insn & THUMB_INSN_IMM_RD ) >> THUMB_INSN_IMM_RD_SHIFT, GET_REGISTER( ( insn & THUMB_INSN_IMM_RD ) >> THUMB_INSN_IMM_RD_SHIFT ), op2, N_IS_SET(GET_CPSR) ? 1 : 0, Z_IS_SET(GET_CPSR) ? 1 : 0, C_IS_SET(GET_CPSR) ? 1 : 0, V_IS_SET(GET_CPSR) ? 1 : 0); - } - else - { - rd = ( insn & THUMB_INSN_IMM_RD ) >> THUMB_INSN_IMM_RD_SHIFT; - op2 = ( insn & THUMB_INSN_IMM ); - SET_REGISTER( rd, op2 ); - ARM7_SetCPSR( GET_CPSR &~ ( ARM7_CPSR_Z | ARM7_CPSR_N ) ); - ARM7_SetCPSR( GET_CPSR | HandleALUNZFlags( GET_REGISTER(rd) ) ); - R15 += 2; - } - break; - case 0x3: /* ADD/SUB immediate */ - if( insn & THUMB_INSN_SUB ) /* SUB Rd, #Offset8 */ - { - rn = GET_REGISTER( ( insn & THUMB_INSN_IMM_RD ) >> THUMB_INSN_IMM_RD_SHIFT ); - op2 = ( insn & THUMB_INSN_IMM ); - //mame_printf_debug("%08x: Thumb instruction: SUB R%d, %02x\n", pc, ( insn & THUMB_INSN_IMM_RD ) >> THUMB_INSN_IMM_RD_SHIFT, op2); - rd = rn - op2; - SET_REGISTER( ( insn & THUMB_INSN_IMM_RD ) >> THUMB_INSN_IMM_RD_SHIFT, rd ); - HandleThumbALUSubFlags( rd, rn, op2 ); - } - else /* ADD Rd, #Offset8 */ - { - rn = GET_REGISTER( ( insn & THUMB_INSN_IMM_RD ) >> THUMB_INSN_IMM_RD_SHIFT ); - op2 = insn & THUMB_INSN_IMM; - rd = rn + op2; - //mame_printf_debug("%08x: Thumb instruction: ADD R%d, %02x\n", pc, ( insn & THUMB_INSN_IMM_RD ) >> THUMB_INSN_IMM_RD_SHIFT, op2); - SET_REGISTER( ( insn & THUMB_INSN_IMM_RD ) >> THUMB_INSN_IMM_RD_SHIFT, rd ); - HandleThumbALUAddFlags( rd, rn, op2 ); - } - break; - case 0x4: /* Rd & Rm instructions */ - switch( ( insn & THUMB_GROUP4_TYPE ) >> THUMB_GROUP4_TYPE_SHIFT ) - { - case 0x0: - switch( ( insn & THUMB_ALUOP_TYPE ) >> THUMB_ALUOP_TYPE_SHIFT ) - { - case 0x0: /* AND Rd, Rs */ - rs = ( insn & THUMB_ADDSUB_RS ) >> THUMB_ADDSUB_RS_SHIFT; - rd = ( insn & THUMB_ADDSUB_RD ) >> THUMB_ADDSUB_RD_SHIFT; - SET_REGISTER( rd, GET_REGISTER(rd) & GET_REGISTER(rs) ); - ARM7_SetCPSR( GET_CPSR &~ ( ARM7_CPSR_Z | ARM7_CPSR_N ) ); - ARM7_SetCPSR( GET_CPSR | HandleALUNZFlags( GET_REGISTER(rd) ) ); - R15 += 2; - break; - case 0x1: /* EOR Rd, Rs */ - rs = ( insn & THUMB_ADDSUB_RS ) >> THUMB_ADDSUB_RS_SHIFT; - rd = ( insn & THUMB_ADDSUB_RD ) >> THUMB_ADDSUB_RD_SHIFT; - SET_REGISTER( rd, GET_REGISTER(rd) ^ GET_REGISTER(rs) ); - ARM7_SetCPSR( GET_CPSR &~ ( ARM7_CPSR_Z | ARM7_CPSR_N ) ); - ARM7_SetCPSR( GET_CPSR | HandleALUNZFlags( GET_REGISTER(rd) ) ); - R15 += 2; - break; - case 0x2: /* LSL Rd, Rs */ - rs = ( insn & THUMB_ADDSUB_RS ) >> THUMB_ADDSUB_RS_SHIFT; - rd = ( insn & THUMB_ADDSUB_RD ) >> THUMB_ADDSUB_RD_SHIFT; - rrd = GET_REGISTER(rd); - offs = GET_REGISTER(rs) & 0x000000ff; - if (offs > 0) - { - if ( offs < 32 ) - { - SET_REGISTER( rd, rrd << offs ); - if( rrd & ( 1 << ( 31 - ( offs - 1 ) ) ) ) - { - ARM7_SetCPSR( GET_CPSR | ARM7_CPSR_C ); - } - else - { - ARM7_SetCPSR( GET_CPSR &~ ARM7_CPSR_C ); - } - } - else if( offs == 32 ) - { - SET_REGISTER( rd, 0 ); - if( rrd & 1 ) - { - ARM7_SetCPSR( GET_CPSR | ARM7_CPSR_C ); - } - else - { - ARM7_SetCPSR( GET_CPSR &~ ARM7_CPSR_C ); - } - } - else - { - SET_REGISTER( rd, 0 ); - ARM7_SetCPSR( GET_CPSR &~ ARM7_CPSR_C ); - } - } - ARM7_SetCPSR( GET_CPSR &~ ( ARM7_CPSR_Z | ARM7_CPSR_N ) ); - ARM7_SetCPSR( GET_CPSR | HandleALUNZFlags( GET_REGISTER(rd) ) ); - R15 += 2; - break; - case 0x3: /* LSR Rd, Rs */ - rs = ( insn & THUMB_ADDSUB_RS ) >> THUMB_ADDSUB_RS_SHIFT; - rd = ( insn & THUMB_ADDSUB_RD ) >> THUMB_ADDSUB_RD_SHIFT; - rrd = GET_REGISTER(rd); - offs = GET_REGISTER(rs) & 0x000000ff; - if (offs > 0) - { - if( offs < 32 ) - { - SET_REGISTER( rd, rrd >> offs ); - if( rrd & ( 1 << ( offs - 1 ) ) ) - { - ARM7_SetCPSR( GET_CPSR | ARM7_CPSR_C ); - } - else - { - ARM7_SetCPSR( GET_CPSR &~ ARM7_CPSR_C ); - } - } - else if( offs == 32 ) - { - SET_REGISTER( rd, 0 ); - if( rrd & 0x80000000 ) - { - ARM7_SetCPSR( GET_CPSR | ARM7_CPSR_C ); - } - else - { - ARM7_SetCPSR( GET_CPSR &~ ARM7_CPSR_C ); - } - } - else - { - SET_REGISTER( rd, 0 ); - ARM7_SetCPSR( GET_CPSR &~ ARM7_CPSR_C ); - } - } - ARM7_SetCPSR( GET_CPSR &~ ( ARM7_CPSR_Z | ARM7_CPSR_N ) ); - ARM7_SetCPSR( GET_CPSR | HandleALUNZFlags( GET_REGISTER(rd) ) ); - R15 += 2; - break; - case 0x4: /* ASR Rd, Rs */ - { - rs = ( insn & THUMB_ADDSUB_RS ) >> THUMB_ADDSUB_RS_SHIFT; - rd = ( insn & THUMB_ADDSUB_RD ) >> THUMB_ADDSUB_RD_SHIFT; - rrs = GET_REGISTER(rs)&0xff; - rrd = GET_REGISTER(rd); - if (rrs != 0) - { - if (rrs >= 32) - { - if (rrd>>31) - { - ARM7_SetCPSR(GET_CPSR | ARM7_CPSR_C); - } - else - { - ARM7_SetCPSR(GET_CPSR &~ ARM7_CPSR_C); - } - SET_REGISTER( rd, (GET_REGISTER(rd) & 0x80000000) ? 0xFFFFFFFF : 0x00000000 ); - } - else - { - if ((rrd>>(rs-1))&1) - { - ARM7_SetCPSR(GET_CPSR | ARM7_CPSR_C); - } - else - { - ARM7_SetCPSR(GET_CPSR &~ ARM7_CPSR_C); - } - SET_REGISTER( rd, (rrd & 0x80000000) ? ((0xFFFFFFFF<<(32-rrs)) | (rrd>>rrs)) : (rrd>>rrs)); - } - } - ARM7_SetCPSR(GET_CPSR &~ (ARM7_CPSR_N | ARM7_CPSR_Z)); - ARM7_SetCPSR( GET_CPSR | HandleALUNZFlags( GET_REGISTER(rd) ) ); - R15 += 2; - } - break; - case 0x5: /* ADC Rd, Rs */ - rs = ( insn & THUMB_ADDSUB_RS ) >> THUMB_ADDSUB_RS_SHIFT; - rd = ( insn & THUMB_ADDSUB_RD ) >> THUMB_ADDSUB_RD_SHIFT; - op2=(GET_CPSR & ARM7_CPSR_C) ? 1 : 0; - rn=GET_REGISTER(rd) + GET_REGISTER(rs) + op2; - HandleThumbALUAddFlags( rn, GET_REGISTER(rd), ( GET_REGISTER(rs) ) ); //? - SET_REGISTER( rd, rn); - break; - case 0x6: /* SBC Rd, Rs */ - rs = ( insn & THUMB_ADDSUB_RS ) >> THUMB_ADDSUB_RS_SHIFT; - rd = ( insn & THUMB_ADDSUB_RD ) >> THUMB_ADDSUB_RD_SHIFT; - op2=(GET_CPSR & ARM7_CPSR_C) ? 0 : 1; - rn=GET_REGISTER(rd) - GET_REGISTER(rs) - op2; - HandleThumbALUSubFlags( rn, GET_REGISTER(rd), ( GET_REGISTER(rs) ) ); //? - SET_REGISTER( rd, rn); - break; - case 0x7: /* ROR Rd, Rs */ - rs = ( insn & THUMB_ADDSUB_RS ) >> THUMB_ADDSUB_RS_SHIFT; - rd = ( insn & THUMB_ADDSUB_RD ) >> THUMB_ADDSUB_RD_SHIFT; - rrd = GET_REGISTER(rd); - imm = GET_REGISTER(rs) & 0x0000001f; - SET_REGISTER( rd, ( rrd >> imm ) | ( rrd << ( 32 - imm ) ) ); - if( rrd & ( 1 << ( imm - 1 ) ) ) - { - ARM7_SetCPSR( GET_CPSR | ARM7_CPSR_C ); - } - else - { - ARM7_SetCPSR( GET_CPSR &~ ARM7_CPSR_C ); - } - ARM7_SetCPSR( GET_CPSR &~ ( ARM7_CPSR_Z | ARM7_CPSR_N ) ); - ARM7_SetCPSR( GET_CPSR | HandleALUNZFlags( GET_REGISTER(rd) ) ); - R15 += 2; - break; - case 0x8: /* TST Rd, Rs */ - rs = ( insn & THUMB_ADDSUB_RS ) >> THUMB_ADDSUB_RS_SHIFT; - rd = ( insn & THUMB_ADDSUB_RD ) >> THUMB_ADDSUB_RD_SHIFT; - ARM7_SetCPSR( GET_CPSR &~ ( ARM7_CPSR_Z | ARM7_CPSR_N ) ); - ARM7_SetCPSR( GET_CPSR | HandleALUNZFlags( GET_REGISTER(rd) & GET_REGISTER(rs) ) ); - R15 += 2; - break; - case 0x9: /* NEG Rd, Rs - todo: check me */ - rs = ( insn & THUMB_ADDSUB_RS ) >> THUMB_ADDSUB_RS_SHIFT; - rd = ( insn & THUMB_ADDSUB_RD ) >> THUMB_ADDSUB_RD_SHIFT; - rrs = GET_REGISTER(rs); - rn = 0 - rrs; - SET_REGISTER( rd, rn ); - HandleThumbALUSubFlags( GET_REGISTER(rd), 0, rrs ); - break; - case 0xa: /* CMP Rd, Rs */ - rs = ( insn & THUMB_ADDSUB_RS ) >> THUMB_ADDSUB_RS_SHIFT; - rd = ( insn & THUMB_ADDSUB_RD ) >> THUMB_ADDSUB_RD_SHIFT; - rn = GET_REGISTER(rd) - GET_REGISTER(rs); - HandleThumbALUSubFlags( rn, GET_REGISTER(rd), GET_REGISTER(rs) ); - break; - case 0xb: /* CMN Rd, Rs - check flags, add dasm */ - rs = ( insn & THUMB_ADDSUB_RS ) >> THUMB_ADDSUB_RS_SHIFT; - rd = ( insn & THUMB_ADDSUB_RD ) >> THUMB_ADDSUB_RD_SHIFT; - rn = GET_REGISTER(rd) + GET_REGISTER(rs); - HandleThumbALUAddFlags( rn, GET_REGISTER(rd), GET_REGISTER(rs) ); - break; - case 0xc: /* ORR Rd, Rs */ - rs = ( insn & THUMB_ADDSUB_RS ) >> THUMB_ADDSUB_RS_SHIFT; - rd = ( insn & THUMB_ADDSUB_RD ) >> THUMB_ADDSUB_RD_SHIFT; - SET_REGISTER( rd, GET_REGISTER(rd) | GET_REGISTER(rs) ); - ARM7_SetCPSR( GET_CPSR &~ ( ARM7_CPSR_Z | ARM7_CPSR_N ) ); - ARM7_SetCPSR( GET_CPSR | HandleALUNZFlags( GET_REGISTER(rd) ) ); - R15 += 2; - break; - case 0xd: /* MUL Rd, Rs */ - rs = ( insn & THUMB_ADDSUB_RS ) >> THUMB_ADDSUB_RS_SHIFT; - rd = ( insn & THUMB_ADDSUB_RD ) >> THUMB_ADDSUB_RD_SHIFT; - rn = GET_REGISTER(rd) * GET_REGISTER(rs); - ARM7_SetCPSR( GET_CPSR &~ ( ARM7_CPSR_Z | ARM7_CPSR_N ) ); - SET_REGISTER( rd, rn ); - ARM7_SetCPSR( GET_CPSR | HandleALUNZFlags( rn ) ); - R15 += 2; - break; - case 0xe: /* BIC Rd, Rs */ - rs = ( insn & THUMB_ADDSUB_RS ) >> THUMB_ADDSUB_RS_SHIFT; - rd = ( insn & THUMB_ADDSUB_RD ) >> THUMB_ADDSUB_RD_SHIFT; - SET_REGISTER( rd, GET_REGISTER(rd) & (~GET_REGISTER(rs)) ); - ARM7_SetCPSR( GET_CPSR &~ ( ARM7_CPSR_Z | ARM7_CPSR_N ) ); - ARM7_SetCPSR( GET_CPSR | HandleALUNZFlags( GET_REGISTER(rd) ) ); - R15 += 2; - break; - case 0xf: /* MVN Rd, Rs */ - rs = ( insn & THUMB_ADDSUB_RS ) >> THUMB_ADDSUB_RS_SHIFT; - rd = ( insn & THUMB_ADDSUB_RD ) >> THUMB_ADDSUB_RD_SHIFT; - op2 = GET_REGISTER(rs); - SET_REGISTER( rd, ~op2 ); - ARM7_SetCPSR( GET_CPSR &~ ( ARM7_CPSR_Z | ARM7_CPSR_N ) ); - ARM7_SetCPSR( GET_CPSR | HandleALUNZFlags( GET_REGISTER(rd) ) ); - R15 += 2; - break; - default: - printf("%08x: G4-0 Undefined Thumb instruction: %04x %x\n", pc, insn, ( insn & THUMB_ALUOP_TYPE ) >> THUMB_ALUOP_TYPE_SHIFT); - R15 += 2; - break; - } - break; - case 0x1: - switch( ( insn & THUMB_HIREG_OP ) >> THUMB_HIREG_OP_SHIFT ) - { - case 0x0: /* ADD Rd, Rs */ - rs = ( insn & THUMB_HIREG_RS ) >> THUMB_HIREG_RS_SHIFT; - rd = insn & THUMB_HIREG_RD; - switch( ( insn & THUMB_HIREG_H ) >> THUMB_HIREG_H_SHIFT ) - { - case 0x1: /* ADD Rd, HRs */ - SET_REGISTER( rd, GET_REGISTER(rd) + GET_REGISTER(rs+8) ); - // emulate the effects of pre-fetch - if (rs == 7) - { - SET_REGISTER(rd, GET_REGISTER(rd) + 4); - } - break; - case 0x2: /* ADD HRd, Rs */ - SET_REGISTER( rd+8, GET_REGISTER(rd+8) + GET_REGISTER(rs) ); - if (rd == 7) - { - R15 += 2; - change_pc(R15); - } - break; - case 0x3: /* Add HRd, HRs */ - SET_REGISTER( rd+8, GET_REGISTER(rd+8) + GET_REGISTER(rs+8) ); - // emulate the effects of pre-fetch - if (rs == 7) - { - SET_REGISTER(rd+8, GET_REGISTER(rd+8) + 4); - } - if (rd == 7) - { - R15 += 2; - change_pc(R15); - } - break; - default: - printf("%08x: G4-1-0 Undefined Thumb instruction: %04x %x\n", pc, insn, ( insn & THUMB_HIREG_H ) >> THUMB_HIREG_H_SHIFT ); - break; - } - R15 += 2; - break; - case 0x1: /* CMP */ - switch( ( insn & THUMB_HIREG_H ) >> THUMB_HIREG_H_SHIFT ) - { - case 0x0: /* CMP Rd, Rs */ - rs = GET_REGISTER( ( ( insn & THUMB_HIREG_RS ) >> THUMB_HIREG_RS_SHIFT ) ); - rd = GET_REGISTER( insn & THUMB_HIREG_RD ); - rn = rd - rs; - HandleThumbALUSubFlags( rn, rd, rs ); - break; - case 0x1: /* CMP Rd, Hs */ - rs = GET_REGISTER( ( ( insn & THUMB_HIREG_RS ) >> THUMB_HIREG_RS_SHIFT ) + 8 ); - rd = GET_REGISTER( insn & THUMB_HIREG_RD ); - rn = rd - rs; - HandleThumbALUSubFlags( rn, rd, rs ); - break; - case 0x2: /* CMP Hd, Rs */ - rs = GET_REGISTER( ( ( insn & THUMB_HIREG_RS ) >> THUMB_HIREG_RS_SHIFT ) ); - rd = GET_REGISTER( (insn & THUMB_HIREG_RD) + 8 ); - rn = rd - rs; - HandleThumbALUSubFlags( rn, rd, rs ); - break; - case 0x3: /* CMP Hd, Hs */ - rs = GET_REGISTER( ( ( insn & THUMB_HIREG_RS ) >> THUMB_HIREG_RS_SHIFT ) + 8 ); - rd = GET_REGISTER( (insn & THUMB_HIREG_RD) + 8 ); - rn = rd - rs; - HandleThumbALUSubFlags( rn, rd, rs ); - break; - default: - printf("%08x: G4-1 Undefined Thumb instruction: %04x %x\n", pc, insn, ( insn & THUMB_HIREG_H ) >> THUMB_HIREG_H_SHIFT); - R15 += 2; - break; - } - break; - case 0x2: /* MOV */ - switch( ( insn & THUMB_HIREG_H ) >> THUMB_HIREG_H_SHIFT ) - { - case 0x1: // MOV Rd, Hs - rs = ( insn & THUMB_HIREG_RS ) >> THUMB_HIREG_RS_SHIFT; - rd = insn & THUMB_HIREG_RD; - if( rs == 7 ) - { - SET_REGISTER( rd, GET_REGISTER(rs + 8) + 4 ); - } - else - { - SET_REGISTER( rd, GET_REGISTER(rs + 8) ); - } - R15 += 2; - break; - case 0x2: // MOV Hd, Rs - rs = ( insn & THUMB_HIREG_RS ) >> THUMB_HIREG_RS_SHIFT; - rd = insn & THUMB_HIREG_RD; - SET_REGISTER( rd + 8, GET_REGISTER(rs) ); - if( rd != 7 ) - { - R15 += 2; - } - else - { - R15 &= ~1; - change_pc(R15); - } - break; - case 0x3: // MOV Hd, Hs - rs = ( insn & THUMB_HIREG_RS ) >> THUMB_HIREG_RS_SHIFT; - rd = insn & THUMB_HIREG_RD; - if (rs == 7) - { - SET_REGISTER( rd + 8, GET_REGISTER(rs+8)+4 ); - } - else - { - SET_REGISTER( rd + 8, GET_REGISTER(rs+8) ); - } - if( rd != 7 ) - { - R15 += 2; - } - - if( rd == 7 ) - { - R15 &= ~1; - change_pc(R15); - } - break; - default: - printf("%08x: G4-2 Undefined Thumb instruction: %04x (%x)\n", pc, insn, ( insn & THUMB_HIREG_H ) >> THUMB_HIREG_H_SHIFT); - R15 += 2; - break; - } - break; - case 0x3: - switch( ( insn & THUMB_HIREG_H ) >> THUMB_HIREG_H_SHIFT ) - { - case 0x0: - rd = ( insn & THUMB_HIREG_RS ) >> THUMB_HIREG_RS_SHIFT; - addr = GET_REGISTER(rd); - if( addr & 1 ) - { - addr &= ~1; - } - else - { - ARM7_SetCPSR(GET_CPSR &~ ARM7_CPSR_T); - if( addr & 2 ) - { - addr += 2; - } - } - R15 = addr; - break; - case 0x1: - addr = GET_REGISTER( ( ( insn & THUMB_HIREG_RS ) >> THUMB_HIREG_RS_SHIFT ) + 8 ); - if( ( ( ( insn & THUMB_HIREG_RS ) >> THUMB_HIREG_RS_SHIFT ) + 8 ) == 15 ) - { - addr += 2; - } - if( addr & 1 ) - { - addr &= ~1; - } - else - { - ARM7_SetCPSR(GET_CPSR &~ ARM7_CPSR_T); - if( addr & 2 ) - { - addr += 2; - } - } - R15 = addr; - break; - default: - printf("%08x: G4-3 Undefined Thumb instruction: %04x\n", pc, insn); - R15 += 2; - break; - } - break; - default: - printf("%08x: G4-x Undefined Thumb instruction: %04x\n", pc, insn); - R15 += 2; - break; - } - break; - case 0x2: - case 0x3: - readword = arm7_read_32( ( R15 & ~2 ) + 4 + ( ( insn & THUMB_INSN_IMM ) << 2 ) ); - SET_REGISTER( ( insn & THUMB_INSN_IMM_RD ) >> THUMB_INSN_IMM_RD_SHIFT, readword ); - R15 += 2; - break; - default: - printf("%08x: G4-y Undefined Thumb instruction: %04x\n", pc, insn); - R15 += 2; - break; - } - break; - case 0x5: /* LDR* STR* */ - switch( ( insn & THUMB_GROUP5_TYPE ) >> THUMB_GROUP5_TYPE_SHIFT ) - { - case 0x0: /* STR Rd, [Rn, Rm] */ - rm = ( insn & THUMB_GROUP5_RM ) >> THUMB_GROUP5_RM_SHIFT; - rn = ( insn & THUMB_GROUP5_RN ) >> THUMB_GROUP5_RN_SHIFT; - rd = ( insn & THUMB_GROUP5_RD ) >> THUMB_GROUP5_RD_SHIFT; - addr = GET_REGISTER(rn) + GET_REGISTER(rm); - arm7_write_32( addr, GET_REGISTER(rd) ); - R15 += 2; - break; - case 0x1: /* STRH Rd, [Rn, Rm] */ - rm = ( insn & THUMB_GROUP5_RM ) >> THUMB_GROUP5_RM_SHIFT; - rn = ( insn & THUMB_GROUP5_RN ) >> THUMB_GROUP5_RN_SHIFT; - rd = ( insn & THUMB_GROUP5_RD ) >> THUMB_GROUP5_RD_SHIFT; - addr = GET_REGISTER(rn) + GET_REGISTER(rm); - arm7_write_16( addr, GET_REGISTER(rd) ); - R15 += 2; - break; - case 0x2: /* STRB Rd, [Rn, Rm] */ - rm = ( insn & THUMB_GROUP5_RM ) >> THUMB_GROUP5_RM_SHIFT; - rn = ( insn & THUMB_GROUP5_RN ) >> THUMB_GROUP5_RN_SHIFT; - rd = ( insn & THUMB_GROUP5_RD ) >> THUMB_GROUP5_RD_SHIFT; - addr = GET_REGISTER(rn) + GET_REGISTER(rm); - arm7_write_8( addr, GET_REGISTER(rd) ); - R15 += 2; - break; - case 0x3: /* LDSB Rd, [Rn, Rm] todo, add dasm */ - rm = ( insn & THUMB_GROUP5_RM ) >> THUMB_GROUP5_RM_SHIFT; - rn = ( insn & THUMB_GROUP5_RN ) >> THUMB_GROUP5_RN_SHIFT; - rd = ( insn & THUMB_GROUP5_RD ) >> THUMB_GROUP5_RD_SHIFT; - addr = GET_REGISTER(rn) + GET_REGISTER(rm); - op2 = arm7_read_8( addr ); - if( op2 & 0x00000080 ) - { - op2 |= 0xffffff00; - } - SET_REGISTER( rd, op2 ); - R15 += 2; - break; - case 0x4: /* LDR Rd, [Rn, Rm] */ - rm = ( insn & THUMB_GROUP5_RM ) >> THUMB_GROUP5_RM_SHIFT; - rn = ( insn & THUMB_GROUP5_RN ) >> THUMB_GROUP5_RN_SHIFT; - rd = ( insn & THUMB_GROUP5_RD ) >> THUMB_GROUP5_RD_SHIFT; - addr = GET_REGISTER(rn) + GET_REGISTER(rm); - op2 = arm7_read_32( addr ); - SET_REGISTER( rd, op2 ); - R15 += 2; - break; - case 0x5: /* LDRH Rd, [Rn, Rm] */ - rm = ( insn & THUMB_GROUP5_RM ) >> THUMB_GROUP5_RM_SHIFT; - rn = ( insn & THUMB_GROUP5_RN ) >> THUMB_GROUP5_RN_SHIFT; - rd = ( insn & THUMB_GROUP5_RD ) >> THUMB_GROUP5_RD_SHIFT; - addr = GET_REGISTER(rn) + GET_REGISTER(rm); - op2 = arm7_read_16( addr ); - SET_REGISTER( rd, op2 ); - R15 += 2; - break; - - case 0x6: /* LDRB Rd, [Rn, Rm] */ - rm = ( insn & THUMB_GROUP5_RM ) >> THUMB_GROUP5_RM_SHIFT; - rn = ( insn & THUMB_GROUP5_RN ) >> THUMB_GROUP5_RN_SHIFT; - rd = ( insn & THUMB_GROUP5_RD ) >> THUMB_GROUP5_RD_SHIFT; - addr = GET_REGISTER(rn) + GET_REGISTER(rm); - op2 = arm7_read_8( addr ); - SET_REGISTER( rd, op2 ); - R15 += 2; - break; - case 0x7: /* LDSH Rd, [Rn, Rm] */ - rm = ( insn & THUMB_GROUP5_RM ) >> THUMB_GROUP5_RM_SHIFT; - rn = ( insn & THUMB_GROUP5_RN ) >> THUMB_GROUP5_RN_SHIFT; - rd = ( insn & THUMB_GROUP5_RD ) >> THUMB_GROUP5_RD_SHIFT; - addr = GET_REGISTER(rn) + GET_REGISTER(rm); - op2 = arm7_read_16( addr ); - if( op2 & 0x00008000 ) - { - op2 |= 0xffff0000; - } - SET_REGISTER( rd, op2 ); - R15 += 2; - break; - default: - printf("%08x: G5 Undefined Thumb instruction: %04x\n", pc, insn); - R15 += 2; - break; - } - break; - case 0x6: /* Word Store w/ Immediate Offset */ - if( insn & THUMB_LSOP_L ) /* Load */ - { - rn = ( insn & THUMB_ADDSUB_RS ) >> THUMB_ADDSUB_RS_SHIFT; - rd = insn & THUMB_ADDSUB_RD; - offs = ( ( insn & THUMB_LSOP_OFFS ) >> THUMB_LSOP_OFFS_SHIFT ) << 2; - SET_REGISTER( rd, arm7_read_32(GET_REGISTER(rn) + offs) ); // fix - R15 += 2; - } - else /* Store */ - { - rn = ( insn & THUMB_ADDSUB_RS ) >> THUMB_ADDSUB_RS_SHIFT; - rd = insn & THUMB_ADDSUB_RD; - offs = ( ( insn & THUMB_LSOP_OFFS ) >> THUMB_LSOP_OFFS_SHIFT ) << 2; - arm7_write_32( GET_REGISTER(rn) + offs, GET_REGISTER(rd) ); - R15 += 2; - } - break; - case 0x7: /* Byte Store w/ Immeidate Offset */ - if( insn & THUMB_LSOP_L ) /* Load */ - { - rn = ( insn & THUMB_ADDSUB_RS ) >> THUMB_ADDSUB_RS_SHIFT; - rd = insn & THUMB_ADDSUB_RD; - offs = ( insn & THUMB_LSOP_OFFS ) >> THUMB_LSOP_OFFS_SHIFT; - SET_REGISTER( rd, arm7_read_8( GET_REGISTER(rn) + offs ) ); - R15 += 2; - } - else /* Store */ - { - rn = ( insn & THUMB_ADDSUB_RS ) >> THUMB_ADDSUB_RS_SHIFT; - rd = insn & THUMB_ADDSUB_RD; - offs = ( insn & THUMB_LSOP_OFFS ) >> THUMB_LSOP_OFFS_SHIFT; - arm7_write_8( GET_REGISTER(rn) + offs, GET_REGISTER(rd) ); - R15 += 2; - } - break; - case 0x8: /* Load/Store Halfword */ - if( insn & THUMB_HALFOP_L ) /* Load */ - { - imm = ( insn & THUMB_HALFOP_OFFS ) >> THUMB_HALFOP_OFFS_SHIFT; - rs = ( insn & THUMB_ADDSUB_RS ) >> THUMB_ADDSUB_RS_SHIFT; - rd = ( insn & THUMB_ADDSUB_RD ) >> THUMB_ADDSUB_RD_SHIFT; - SET_REGISTER( rd, arm7_read_16( GET_REGISTER(rs) + ( imm << 1 ) ) ); - R15 += 2; - } - else /* Store */ - { - imm = ( insn & THUMB_HALFOP_OFFS ) >> THUMB_HALFOP_OFFS_SHIFT; - rs = ( insn & THUMB_ADDSUB_RS ) >> THUMB_ADDSUB_RS_SHIFT; - rd = ( insn & THUMB_ADDSUB_RD ) >> THUMB_ADDSUB_RD_SHIFT; - arm7_write_16( GET_REGISTER(rs) + ( imm << 1 ), GET_REGISTER(rd) ); - R15 += 2; - } - break; - case 0x9: /* Stack-Relative Load/Store */ - if( insn & THUMB_STACKOP_L ) - { - rd = ( insn & THUMB_STACKOP_RD ) >> THUMB_STACKOP_RD_SHIFT; - offs = (UINT8)( insn & THUMB_INSN_IMM ); - readword = arm7_read_32( GET_REGISTER(13) + ( (UINT32)offs << 2 ) ); - SET_REGISTER( rd, readword ); - R15 += 2; - } - else - { - rd = ( insn & THUMB_STACKOP_RD ) >> THUMB_STACKOP_RD_SHIFT; - offs = (UINT8)( insn & THUMB_INSN_IMM ); - arm7_write_32( GET_REGISTER(13) + ( (UINT32)offs << 2 ), GET_REGISTER(rd) ); - R15 += 2; - } - break; - case 0xa: /* Get relative address */ - if( insn & THUMB_RELADDR_SP ) /* ADD Rd, SP, #nn */ - { - rd = ( insn & THUMB_RELADDR_RD ) >> THUMB_RELADDR_RD_SHIFT; - offs = (UINT8)( insn & THUMB_INSN_IMM ) << 2; - SET_REGISTER( rd, GET_REGISTER(13) + offs ); - R15 += 2; - } - else /* ADD Rd, PC, #nn */ - { - rd = ( insn & THUMB_RELADDR_RD ) >> THUMB_RELADDR_RD_SHIFT; - offs = (UINT8)( insn & THUMB_INSN_IMM ) << 2; - SET_REGISTER( rd, ( ( R15 + 4 ) & ~2 ) + offs ); - R15 += 2; - } - break; - case 0xb: /* Stack-Related Opcodes */ - switch( ( insn & THUMB_STACKOP_TYPE ) >> THUMB_STACKOP_TYPE_SHIFT ) - { - case 0x0: /* ADD SP, #imm */ - addr = ( insn & THUMB_INSN_IMM ); - addr &= ~THUMB_INSN_IMM_S; - SET_REGISTER( 13, GET_REGISTER(13) + ( ( insn & THUMB_INSN_IMM_S ) ? -( addr << 2 ) : ( addr << 2 ) ) ); - R15 += 2; - break; - case 0x4: /* PUSH {Rlist} */ - for( offs = 7; offs >= 0; offs-- ) - { - if( insn & ( 1 << offs ) ) - { - SET_REGISTER( 13, GET_REGISTER(13) - 4 ); - arm7_write_32( GET_REGISTER(13), GET_REGISTER(offs) ); - } - } - R15 += 2; - break; - case 0x5: /* PUSH {Rlist}{LR} */ - SET_REGISTER( 13, GET_REGISTER(13) - 4 ); - arm7_write_32( GET_REGISTER(13), GET_REGISTER(14) ); - for( offs = 7; offs >= 0; offs-- ) - { - if( insn & ( 1 << offs ) ) - { - SET_REGISTER( 13, GET_REGISTER(13) - 4 ); - arm7_write_32( GET_REGISTER(13), GET_REGISTER(offs) ); - } - } - R15 += 2; - break; - case 0xc: /* POP {Rlist} */ - for( offs = 0; offs < 8; offs++ ) - { - if( insn & ( 1 << offs ) ) - { - SET_REGISTER( offs, arm7_read_32( GET_REGISTER(13) ) ); - SET_REGISTER( 13, GET_REGISTER(13) + 4 ); - } - } - R15 += 2; - break; - case 0xd: /* POP {Rlist}{PC} */ - for( offs = 0; offs < 8; offs++ ) - { - if( insn & ( 1 << offs ) ) - { - SET_REGISTER( offs, arm7_read_32( GET_REGISTER(13) ) ); - SET_REGISTER( 13, GET_REGISTER(13) + 4 ); - } - } - R15 = arm7_read_32( GET_REGISTER(13) ) & ~1; - SET_REGISTER( 13, GET_REGISTER(13) + 4 ); - break; - default: - printf("%08x: Gb Undefined Thumb instruction: %04x\n", pc, insn); - R15 += 2; - break; - } - break; - case 0xc: /* Multiple Load/Store */ - if( insn & THUMB_MULTLS ) /* Load */ - { - rd = ( insn & THUMB_MULTLS_BASE ) >> THUMB_MULTLS_BASE_SHIFT; - for( offs = 0; offs < 8; offs++ ) - { - if( insn & ( 1 << offs ) ) - { - SET_REGISTER( offs, arm7_read_32( (GET_REGISTER(rd)&0xfffffffc) ) ); - SET_REGISTER( rd, GET_REGISTER(rd) + 4 ); - } - } - R15 += 2; - } - else /* Store */ - { - rd = ( insn & THUMB_MULTLS_BASE ) >> THUMB_MULTLS_BASE_SHIFT; - for( offs = 0; offs < 8; offs++ ) - { - if( insn & ( 1 << offs ) ) - { - arm7_write_32( (GET_REGISTER(rd)&0xfffffffc), GET_REGISTER(offs) ); - SET_REGISTER( rd, GET_REGISTER(rd) + 4 ); - } - } - R15 += 2; - } - break; - case 0xd: /* Conditional Branch */ - offs = (INT8)( insn & THUMB_INSN_IMM ); - switch( ( insn & THUMB_COND_TYPE ) >> THUMB_COND_TYPE_SHIFT ) - { - case COND_EQ: - if( Z_IS_SET(GET_CPSR) ) - { - R15 += 4 + (offs << 1); - } - else - { - R15 += 2; - } - break; - case COND_NE: - if( Z_IS_CLEAR(GET_CPSR) ) - { - R15 += 4 + (offs << 1); - } - else - { - R15 += 2; - } - break; - case COND_CS: - if( C_IS_SET(GET_CPSR) ) - { - R15 += 4 + (offs << 1); - } - else - { - R15 += 2; - } - break; - case COND_CC: - if( C_IS_CLEAR(GET_CPSR) ) - { - R15 += 4 + (offs << 1); - } - else - { - R15 += 2; - } - break; - case COND_MI: - if( N_IS_SET(GET_CPSR) ) - { - R15 += 4 + (offs << 1); - } - else - { - R15 += 2; - } - break; - case COND_PL: - if( N_IS_CLEAR(GET_CPSR) ) - { - R15 += 4 + (offs << 1); - } - else - { - R15 += 2; - } - break; - case COND_VS: - if( V_IS_SET(GET_CPSR) ) - { - R15 += 4 + (offs << 1); - } - else - { - R15 += 2; - } - break; - case COND_VC: - if( V_IS_CLEAR(GET_CPSR) ) - { - R15 += 4 + (offs << 1); - } - else - { - R15 += 2; - } - break; - case COND_HI: - if( C_IS_SET(GET_CPSR) && Z_IS_CLEAR(GET_CPSR) ) - { - R15 += 4 + (offs << 1); - } - else - { - R15 += 2; - } - break; - case COND_LS: - if( C_IS_CLEAR(GET_CPSR) || Z_IS_SET(GET_CPSR) ) - { - R15 += 4 + (offs << 1); - } - else - { - R15 += 2; - } - break; - case COND_GE: - if( !(GET_CPSR & ARM7_CPSR_N) == !(GET_CPSR & ARM7_CPSR_V) ) - { - R15 += 4 + (offs << 1); - } - else - { - R15 += 2; - } - break; - case COND_LT: - if( !(GET_CPSR & ARM7_CPSR_N) != !(GET_CPSR & ARM7_CPSR_V) ) - { - R15 += 4 + (offs << 1); - } - else - { - R15 += 2; - } - break; - case COND_GT: - if( Z_IS_CLEAR(GET_CPSR) && ( !(GET_CPSR & ARM7_CPSR_N) == !(GET_CPSR & ARM7_CPSR_V) ) ) - { - R15 += 4 + (offs << 1); - } - else - { - R15 += 2; - } - break; - case COND_LE: - if( Z_IS_SET(GET_CPSR) || ( !(GET_CPSR & ARM7_CPSR_N) != !(GET_CPSR & ARM7_CPSR_V) ) ) - { - R15 += 4 + (offs << 1); - } - else - { - R15 += 2; - } - break; - case COND_AL: - printf("%08x: Undefined Thumb instruction: %04x (ARM9 reserved)\n", pc, insn); - R15 += 2; - break; - - case COND_NV: // SWI (this is sort of a "hole" in the opcode encoding) - ARM7_SetSWI(); -// R15 -= 4; - break; - } - break; - case 0xe: /* B #offs */ - if( insn & THUMB_BLOP_LO ) - { - addr = GET_REGISTER(14); - addr += ( insn & THUMB_BLOP_OFFS ) << 1; - addr &= 0xfffffffc; - SET_REGISTER( 14, ( R15 + 4 ) | 1 ); - R15 = addr; - } - else - { - offs = ( insn & THUMB_BRANCH_OFFS ) << 1; - if( offs & 0x00000800 ) - { - offs |= 0xfffff800; - } - R15 += 4 + offs; - } - break; - case 0xf: /* BL */ - if( insn & THUMB_BLOP_LO ) - { - addr = GET_REGISTER(14); - addr += ( insn & THUMB_BLOP_OFFS ) << 1; - SET_REGISTER( 14, ( R15 + 2 ) | 1 ); - R15 = addr; - } - else - { - addr = ( insn & THUMB_BLOP_OFFS ) << 12; - if( addr & ( 1 << 22 ) ) - { - addr |= 0xff800000; - } - addr += R15 + 4; - SET_REGISTER( 14, addr ); - R15 += 2; - } - break; - default: - printf("%08x: Undefined Thumb instruction: %04x\n", pc, insn); - R15 += 2; - break; - } - - return cycles; -} diff --git a/Frameworks/AudioOverload/aosdk/eng_dsf/arm7thumb.h b/Frameworks/AudioOverload/aosdk/eng_dsf/arm7thumb.h deleted file mode 100644 index dabcd8acc..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_dsf/arm7thumb.h +++ /dev/null @@ -1,117 +0,0 @@ -#ifndef _ARM7_THUMB_ -#define _ARM7_THUMB_ - -#define THUMB_INSN_TYPE ((UINT16) 0xf000) -#define THUMB_COND_TYPE ((UINT16) 0x0f00) -#define THUMB_GROUP4_TYPE ((UINT16) 0x0c00) -#define THUMB_GROUP5_TYPE ((UINT16) 0x0e00) -#define THUMB_GROUP5_RM ((UINT16) 0x01c0) -#define THUMB_GROUP5_RN ((UINT16) 0x0038) -#define THUMB_GROUP5_RD ((UINT16) 0x0007) -#define THUMB_ADDSUB_RNIMM ((UINT16) 0x01c0) -#define THUMB_ADDSUB_RS ((UINT16) 0x0038) -#define THUMB_ADDSUB_RD ((UINT16) 0x0007) -#define THUMB_INSN_ADDSUB ((UINT16) 0x0800) -#define THUMB_INSN_CMP ((UINT16) 0x0800) -#define THUMB_INSN_SUB ((UINT16) 0x0800) -#define THUMB_INSN_IMM_RD ((UINT16) 0x0700) -#define THUMB_INSN_IMM_S ((UINT16) 0x0080) -#define THUMB_INSN_IMM ((UINT16) 0x00ff) -#define THUMB_ADDSUB_TYPE ((UINT16) 0x0600) -#define THUMB_HIREG_OP ((UINT16) 0x0300) -#define THUMB_HIREG_H ((UINT16) 0x00c0) -#define THUMB_HIREG_RS ((UINT16) 0x0038) -#define THUMB_HIREG_RD ((UINT16) 0x0007) -#define THUMB_STACKOP_TYPE ((UINT16) 0x0f00) -#define THUMB_STACKOP_L ((UINT16) 0x0800) -#define THUMB_STACKOP_RD ((UINT16) 0x0700) -#define THUMB_ALUOP_TYPE ((UINT16) 0x03c0) -#define THUMB_BLOP_LO ((UINT16) 0x0800) -#define THUMB_BLOP_OFFS ((UINT16) 0x07ff) -#define THUMB_SHIFT_R ((UINT16) 0x0800) -#define THUMB_SHIFT_AMT ((UINT16) 0x07c0) -#define THUMB_HALFOP_L ((UINT16) 0x0800) -#define THUMB_HALFOP_OFFS ((UINT16) 0x07c0) -#define THUMB_BRANCH_OFFS ((UINT16) 0x07ff) -#define THUMB_LSOP_L ((UINT16) 0x0800) -#define THUMB_LSOP_OFFS ((UINT16) 0x07c0) -#define THUMB_MULTLS ((UINT16) 0x0800) -#define THUMB_MULTLS_BASE ((UINT16) 0x0700) -#define THUMB_RELADDR_SP ((UINT16) 0x0800) -#define THUMB_RELADDR_RD ((UINT16) 0x0700) -#define THUMB_INSN_TYPE_SHIFT 12 -#define THUMB_COND_TYPE_SHIFT 8 -#define THUMB_GROUP4_TYPE_SHIFT 10 -#define THUMB_GROUP5_TYPE_SHIFT 9 -#define THUMB_ADDSUB_TYPE_SHIFT 9 -#define THUMB_INSN_IMM_RD_SHIFT 8 -#define THUMB_STACKOP_TYPE_SHIFT 8 -#define THUMB_HIREG_OP_SHIFT 8 -#define THUMB_STACKOP_RD_SHIFT 8 -#define THUMB_MULTLS_BASE_SHIFT 8 -#define THUMB_RELADDR_RD_SHIFT 8 -#define THUMB_HIREG_H_SHIFT 6 -#define THUMB_HIREG_RS_SHIFT 3 -#define THUMB_ALUOP_TYPE_SHIFT 6 -#define THUMB_SHIFT_AMT_SHIFT 6 -#define THUMB_HALFOP_OFFS_SHIFT 6 -#define THUMB_LSOP_OFFS_SHIFT 6 -#define THUMB_GROUP5_RM_SHIFT 6 -#define THUMB_GROUP5_RN_SHIFT 3 -#define THUMB_GROUP5_RD_SHIFT 0 -#define THUMB_ADDSUB_RNIMM_SHIFT 6 -#define THUMB_ADDSUB_RS_SHIFT 3 -#define THUMB_ADDSUB_RD_SHIFT 0 - -#define THUMB_SIGN_BIT ((UINT32)(1<<31)) -#define THUMB_SIGN_BITS_DIFFER(a,b) (((a)^(b)) >> 31) - -#define N_IS_SET(pc) ((pc) & ARM7_CPSR_N) -#define Z_IS_SET(pc) ((pc) & ARM7_CPSR_Z) -#define C_IS_SET(pc) ((pc) & ARM7_CPSR_C) -#define V_IS_SET(pc) ((pc) & ARM7_CPSR_V) -#define I_IS_SET(pc) ((pc) & ARM7_CPSR_I) -#define F_IS_SET(pc) ((pc) & ARM7_CPSR_F) -#define T_IS_SET(pc) ((pc) & ARM7_CPSR_T) - -#define N_IS_CLEAR(pc) (!N_IS_SET(pc)) -#define Z_IS_CLEAR(pc) (!Z_IS_SET(pc)) -#define C_IS_CLEAR(pc) (!C_IS_SET(pc)) -#define V_IS_CLEAR(pc) (!V_IS_SET(pc)) -#define I_IS_CLEAR(pc) (!I_IS_SET(pc)) -#define F_IS_CLEAR(pc) (!F_IS_SET(pc)) -#define T_IS_CLEAR(pc) (!T_IS_SET(pc)) - -enum -{ - COND_EQ = 0, /* Z: equal */ - COND_NE, /* ~Z: not equal */ - COND_CS, COND_HS = 2, /* C: unsigned higher or same */ - COND_CC, COND_LO = 3, /* ~C: unsigned lower */ - COND_MI, /* N: negative */ - COND_PL, /* ~N: positive or zero */ - COND_VS, /* V: overflow */ - COND_VC, /* ~V: no overflow */ - COND_HI, /* C && ~Z: unsigned higher */ - COND_LS, /* ~C || Z: unsigned lower or same */ - COND_GE, /* N == V: greater or equal */ - COND_LT, /* N != V: less than */ - COND_GT, /* ~Z && (N == V): greater than */ - COND_LE, /* Z || (N != V): less than or equal */ - COND_AL, /* always */ - COND_NV /* never */ -}; - -#define GET_CPSR ARM7.Rx [ARM7_CPSR] - -#define GET_REGISTER(r) ARM7.Rx[(r)] -#define SET_REGISTER(r, v) ARM7.Rx[(r)] = (v) - -#define R15 ARM7.Rx[ARM7_PC] - - -// public function -int ARM7i_Thumb_Step(void); - -#endif - diff --git a/Frameworks/AudioOverload/aosdk/eng_dsf/dc_hw.c b/Frameworks/AudioOverload/aosdk/eng_dsf/dc_hw.c deleted file mode 100644 index a82df3931..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_dsf/dc_hw.c +++ /dev/null @@ -1,175 +0,0 @@ -// dc_hw.c - Hardware found on the ARM7/AICA side of the Dreamcast - -#include "ao.h" -#include "dc_hw.h" -#include "aica.h" - -#define DK_CORE (1) - -#if DK_CORE -#include "arm7.h" -#else -#include "arm7core.h" -#endif - -uint8 dc_ram[8*1024*1024]; - -static void aica_irq(int irq) -{ - if (irq > 0) - { - #if DK_CORE - ARM7_SetFIQ(TRUE); - #else - set_irq_line(ARM7_FIRQ_LINE, 1); - #endif - } - else - { - #if DK_CORE - ARM7_SetFIQ(FALSE); - #else - set_irq_line(ARM7_FIRQ_LINE, 0); - #endif - } -} - -#define MIXER_PAN_LEFT 1 -#define MIXER_PAN_RIGHT 2 -#define MIXER(level,pan) ((level & 0xff) | ((pan & 0x03) << 8)) -#define YM3012_VOL(LVol,LPan,RVol,RPan) (MIXER(LVol,LPan)|(MIXER(RVol,RPan) << 16)) - -static struct AICAinterface aica_interface = -{ - 1, - { dc_ram, }, - { YM3012_VOL(100, MIXER_PAN_LEFT, 100, MIXER_PAN_RIGHT) }, - { aica_irq, }, -}; - -uint8 dc_read8(int addr) -{ - if (addr < 0x800000) - { - return dc_ram[addr]; - } - - if ((addr >= 0x800000) && (addr <= 0x807fff)) - { - int foo = AICA_0_r((addr-0x800000)/2, 0); - - if (addr & 1) - { - return foo>>8; - } - else - { - return foo & 0xff; - } - } - - printf("R8 @ %x\n", addr); - return -1; -} - -uint16 dc_read16(int addr) -{ - if (addr < 0x800000) - { - return dc_ram[addr] | (dc_ram[addr+1]<<8); - } - - if ((addr >= 0x800000) && (addr <= 0x807fff)) - { - return AICA_0_r((addr-0x800000)/2, 0); - } - - printf("R16 @ %x\n", addr); - return -1; -} - -uint32 dc_read32(int addr) -{ - if (addr < 0x800000) - { - return dc_ram[addr] | (dc_ram[addr+1]<<8) | (dc_ram[addr+2]<<16) | (dc_ram[addr+3]<<24); - } - - if ((addr >= 0x800000) && (addr <= 0x807fff)) - { - addr &= 0x7fff; - return AICA_0_r(addr/2, 0) & 0xffff; - } - -// printf("R32 @ %x\n", addr); - return 0; -} - -void dc_write8(int addr, uint8 data) -{ - if (addr < 0x800000) - { - dc_ram[addr] = data; - return; - } - - if ((addr >= 0x800000) && (addr <= 0x807fff)) - { - addr -= 0x800000; - if ((addr & 1)) - AICA_0_w(addr>>1, data<<8, 0x00ff); - else - AICA_0_w(addr>>1, data, 0xff00); - return; - } - - printf("W8 %x @ %x\n", data, addr); -} - -void dc_write16(int addr, uint16 data) -{ - if (addr < 0x800000) - { - dc_ram[addr] = data&0xff; - dc_ram[addr+1] = (data>>8) & 0xff; - return; - } - - if ((addr >= 0x800000) && (addr <= 0x807fff)) - { - AICA_0_w((addr-0x800000)/2, data, 0); - return; - } - - printf("W16 %x @ %x\n", data, addr); -} - -void dc_write32(int addr, uint32 data) -{ - if (addr < 0x800000) - { - dc_ram[addr] = data&0xff; - dc_ram[addr+1] = (data>>8) & 0xff; - dc_ram[addr+2] = (data>>16) & 0xff; - dc_ram[addr+3] = (data>>24) & 0xff; - return; - } - - if ((addr >= 0x800000) && (addr <= 0x807fff)) - { - addr -= 0x800000; - AICA_0_w((addr>>1), data&0xffff, 0x0000); - AICA_0_w((addr>>1)+1, data>>16, 0x0000); - return; - } - - printf("W32 %x @ %x\n", data, addr); -} - -void dc_hw_init(void) -{ - aica_interface.region[0] = dc_ram; - aica_start(&aica_interface); -} - - diff --git a/Frameworks/AudioOverload/aosdk/eng_dsf/dc_hw.h b/Frameworks/AudioOverload/aosdk/eng_dsf/dc_hw.h deleted file mode 100644 index b17de9e16..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_dsf/dc_hw.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef _DC_HW_H_ -#define _DC_HW_H_ - -extern uint8 dc_ram[8*1024*1024]; - -void dc_hw_init(void); - -#endif - diff --git a/Frameworks/AudioOverload/aosdk/eng_dsf/eng_dsf.c b/Frameworks/AudioOverload/aosdk/eng_dsf/eng_dsf.c deleted file mode 100644 index 2138f4708..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_dsf/eng_dsf.c +++ /dev/null @@ -1,261 +0,0 @@ -// -// Audio Overload -// Emulated music player -// -// (C) 2000-2008 Richard F. Bannister -// - -// -// eng_dsf.c -// - -#include -#include -#include - -#include "ao.h" -#include "eng_protos.h" -#include "corlett.h" -#include "dc_hw.h" -#include "aica.h" - -#define DEBUG_LOADER (0) -#define DK_CORE (1) - -#if DK_CORE -#include "arm7.h" -#else -#include "arm7core.h" -#endif - -static corlett_t *c = NULL; -static char psfby[256]; -static uint32 decaybegin, decayend, total_samples; - -void *aica_start(const void *config); -void aica_stop(void); -void AICA_Update(void *param, INT16 **inputs, INT16 **buf, int samples); - -int32 dsf_start(uint8 *buffer, uint32 length) -{ - uint8 *file, *lib_decoded, *lib_raw_file; - uint32 offset, plength, lengthMS, fadeMS; - uint64 file_len, lib_len, lib_raw_length; - corlett_t *lib; - char *libfile; - int i; - - // clear Dreamcast work RAM before we start scribbling in it - memset(dc_ram, 0, 8*1024*1024); - - // Decode the current SSF - if (corlett_decode(buffer, length, &file, &file_len, &c) != AO_SUCCESS) - { - return AO_FAIL; - } - - #if DEBUG_LOADER - printf("%d bytes decoded\n", file_len); - #endif - - // Get the library file, if any - for (i=0; i<9; i++) { - libfile = i ? c->libaux[i-1] : c->lib; - if (libfile[0] != 0) - { - uint64 tmp_length; - - #if DEBUG_LOADER - printf("Loading library: %s\n", c->lib); - #endif - if (ao_get_lib(libfile, &lib_raw_file, &tmp_length) != AO_SUCCESS) - { - return AO_FAIL; - } - lib_raw_length = tmp_length; - - if (corlett_decode(lib_raw_file, lib_raw_length, &lib_decoded, &lib_len, &lib) != AO_SUCCESS) - { - free(lib_raw_file); - return AO_FAIL; - } - - // Free up raw file - free(lib_raw_file); - - // patch the file into ram - offset = lib_decoded[0] | lib_decoded[1]<<8 | lib_decoded[2]<<16 | lib_decoded[3]<<24; - memcpy(&dc_ram[offset], lib_decoded+4, lib_len-4); - - // Dispose the corlett structure for the lib - we don't use it - free(lib); - free(lib_decoded); - } - } - - // now patch the file into RAM over the libraries - offset = file[3]<<24 | file[2]<<16 | file[1]<<8 | file[0]; - memcpy(&dc_ram[offset], file+4, file_len-4); - - free(file); - - // Finally, set psfby/ssfby tag - strcpy(psfby, "n/a"); - if (c) - { - for (i = 0; i < MAX_UNKNOWN_TAGS; i++) - { - if ((!strcasecmp(c->tag_name[i], "psfby")) || (!strcasecmp(c->tag_name[i], "ssfby"))) - strcpy(psfby, c->tag_data[i]); - } - } - - #if DEBUG_LOADER && 1 - { - FILE *f; - - f = fopen("dcram.bin", "wb"); - fwrite(dc_ram, 2*1024*1024, 1, f); - fclose(f); - } - #endif - - #if DK_CORE - ARM7_Init(); - #else - arm7_init(0, 45000000, NULL, NULL); - arm7_reset(); - #endif - dc_hw_init(); - - // now figure out the time in samples for the length/fade - lengthMS = psfTimeToMS(c->inf_length); - fadeMS = psfTimeToMS(c->inf_fade); - total_samples = 0; - - if (lengthMS == 0) - { - lengthMS = ~0; - } - - if (lengthMS == ~0) - { - decaybegin = lengthMS; - } - else - { - lengthMS = (lengthMS * 441) / 10; - fadeMS = (fadeMS * 441) / 10; - - decaybegin = lengthMS; - decayend = lengthMS + fadeMS; - } - - return AO_SUCCESS; -} - -int32 dsf_gen(int16 *buffer, uint32 samples) -{ - int i; - int16 output[44100/30], output2[44100/30]; - int16 *stereo[2]; - int16 *outp = buffer; - int opos; - - opos = 0; - for (i = 0; i < samples; i++) - { - #if DK_CORE - ARM7_Execute((33000000 / 60 / 4) / 735); - #else - arm7_execute((33000000 / 60 / 4) / 735); - #endif - stereo[0] = &output[opos]; - stereo[1] = &output2[opos]; - AICA_Update(NULL, NULL, stereo, 1); - opos++; - } - - for (i = 0; i < samples; i++) - { - // process the fade tags - if (total_samples >= decaybegin) - { - if (total_samples >= decayend) - { - // song is done here, signal your player appropriately! -// ao_song_done = 1; - output[i] = 0; - output2[i] = 0; - } - else - { - int32 fader = 256 - (256*(total_samples - decaybegin)/(decayend-decaybegin)); - output[i] = (output[i] * fader)>>8; - output2[i] = (output2[i] * fader)>>8; - - total_samples++; - } - } - else - { - total_samples++; - } - - *outp++ = output[i]; - *outp++ = output2[i]; - } - - return AO_SUCCESS; -} - -int32 dsf_stop(void) -{ - aica_stop(); - free(c); - - return AO_SUCCESS; -} - -int32 dsf_command(int32 command, int32 parameter) -{ - switch (command) - { - case COMMAND_RESTART: - return AO_SUCCESS; - - } - return AO_FAIL; -} - -int32 dsf_fill_info(ao_display_info *info) -{ - if (c == NULL) - return AO_FAIL; - - strcpy(info->title[1], "Name: "); - sprintf(info->info[1], "%s", c->inf_title); - - strcpy(info->title[2], "Game: "); - sprintf(info->info[2], "%s", c->inf_game); - - strcpy(info->title[3], "Artist: "); - sprintf(info->info[3], "%s", c->inf_artist); - - strcpy(info->title[4], "Copyright: "); - sprintf(info->info[4], "%s", c->inf_copy); - - strcpy(info->title[5], "Year: "); - sprintf(info->info[5], "%s", c->inf_year); - - strcpy(info->title[6], "Length: "); - sprintf(info->info[6], "%s", c->inf_length); - - strcpy(info->title[7], "Fade: "); - sprintf(info->info[7], "%s", c->inf_fade); - - strcpy(info->title[8], "Ripper: "); - sprintf(info->info[8], "%s", psfby); - - return AO_SUCCESS; -} diff --git a/Frameworks/AudioOverload/aosdk/eng_protos.h b/Frameworks/AudioOverload/aosdk/eng_protos.h deleted file mode 100644 index 335d13c03..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_protos.h +++ /dev/null @@ -1,53 +0,0 @@ -// -// Audio Overload -// Emulated music player -// -// (C) 2000-2007 Richard F. Bannister -// - -// -// eng_protos.h -// - -int32 psf_start(uint8 *, uint32 length); -int32 psf_gen(int16 *, uint32); -int32 psf_stop(void); -int32 psf_command(int32, int32); -int32 psf_fill_info(ao_display_info *); - -int32 psf2_start(uint8 *, uint32 length); -int32 psf2_gen(int16 *, uint32); -int32 psf2_stop(void); -int32 psf2_command(int32, int32); -int32 psf2_fill_info(ao_display_info *); - -int32 qsf_start(uint8 *, uint32 length); -int32 qsf_gen(int16 *, uint32); -int32 qsf_stop(void); -int32 qsf_command(int32, int32); -int32 qsf_fill_info(ao_display_info *); - -int32 ssf_start(uint8 *, uint32 length); -int32 ssf_gen(int16 *, uint32); -int32 ssf_stop(void); -int32 ssf_command(int32, int32); -int32 ssf_fill_info(ao_display_info *); - -int32 spu_start(uint8 *, uint32 length); -int32 spu_gen(int16 *, uint32); -int32 spu_stop(void); -int32 spu_command(int32, int32); -int32 spu_fill_info(ao_display_info *); - -uint8 qsf_memory_read(uint16 addr); -uint8 qsf_memory_readop(uint16 addr); -uint8 qsf_memory_readport(uint16 addr); -void qsf_memory_write(uint16 addr, uint8 byte); -void qsf_memory_writeport(uint16 addr, uint8 byte); - -int32 dsf_start(uint8 *, uint32 length); -int32 dsf_gen(int16 *, uint32); -int32 dsf_stop(void); -int32 dsf_command(int32, int32); -int32 dsf_fill_info(ao_display_info *); - diff --git a/Frameworks/AudioOverload/aosdk/eng_psf/cpuintrf.h b/Frameworks/AudioOverload/aosdk/eng_psf/cpuintrf.h deleted file mode 100644 index 1317f4189..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_psf/cpuintrf.h +++ /dev/null @@ -1,668 +0,0 @@ -#ifndef CPUINTRF_H -#define CPUINTRF_H - -#include "osd_cpu.h" - -/* The old system is obsolete and no longer supported by the core */ -#define NEW_INTERRUPT_SYSTEM 1 - -#define MAX_IRQ_LINES 8 /* maximum number of IRQ lines per CPU */ - -#define CLEAR_LINE 0 /* clear (a fired, held or pulsed) line */ -#define ASSERT_LINE 1 /* assert an interrupt immediately */ -#define HOLD_LINE 2 /* hold interrupt line until enable is true */ -#define PULSE_LINE 3 /* pulse interrupt line for one instruction */ - -#define MAX_REGS 64 /* maximum number of register of any CPU */ - -#define IRQ_LINE_NMI 10 -/* Values passed to the cpu_info function of a core to retrieve information */ -enum { - CPU_INFO_REG, - CPU_INFO_FLAGS=MAX_REGS, - CPU_INFO_NAME, - CPU_INFO_FAMILY, - CPU_INFO_VERSION, - CPU_INFO_FILE, - CPU_INFO_CREDITS, - CPU_INFO_REG_LAYOUT, - CPU_INFO_WIN_LAYOUT -}; - -#define CPU_IS_LE 0 /* emulated CPU is little endian */ -#define CPU_IS_BE 1 /* emulated CPU is big endian */ - -/* - * This value is passed to cpu_get_reg to retrieve the previous - * program counter value, ie. before a CPU emulation started - * to fetch opcodes and arguments for the current instrution. - */ -#define REG_PREVIOUSPC -1 - -/* - * This value is passed to cpu_get_reg/cpu_set_reg, instead of one of - * the names from the enum a CPU core defines for it's registers, - * to get or set the contents of the memory pointed to by a stack pointer. - * You can specify the n'th element on the stack by (REG_SP_CONTENTS-n), - * ie. lower negative values. The actual element size (UINT16 or UINT32) - * depends on the CPU core. - * This is also used to replace the cpu_geturnpc() function. - */ -#define REG_SP_CONTENTS -2 - -/* - * These flags can be defined in the makefile (or project) to - * exclude (zero) or include (non zero) specific CPU cores - */ -#ifndef HAS_GENSYNC -#define HAS_GENSYNC 0 -#endif -#ifndef HAS_Z80 -#define HAS_Z80 0 -#endif -#ifndef HAS_Z80_VM -#define HAS_Z80_VM 0 -#endif -#ifndef HAS_8080 -#define HAS_8080 0 -#endif -#ifndef HAS_8085A -#define HAS_8085A 0 -#endif -#ifndef HAS_M6502 -#define HAS_M6502 0 -#endif -#ifndef HAS_M65C02 -#define HAS_M65C02 0 -#endif -#ifndef HAS_M65SC02 -#define HAS_M65SC02 0 -#endif -#ifndef HAS_M65CE02 -#define HAS_M65CE02 0 -#endif -#ifndef HAS_M6509 -#define HAS_M6509 0 -#endif -#ifndef HAS_M6510 -#define HAS_M6510 0 -#endif -#ifndef HAS_N2A03 -#define HAS_N2A03 0 -#endif -#ifndef HAS_H6280 -#define HAS_H6280 0 -#endif -#ifndef HAS_I86 -#define HAS_I86 0 -#endif -#ifndef HAS_V20 -#define HAS_V20 0 -#endif -#ifndef HAS_V30 -#define HAS_V30 0 -#endif -#ifndef HAS_V33 -#define HAS_V33 0 -#endif -#ifndef HAS_I8035 -#define HAS_I8035 0 -#endif -#ifndef HAS_I8039 -#define HAS_I8039 0 -#endif -#ifndef HAS_I8048 -#define HAS_I8048 0 -#endif -#ifndef HAS_N7751 -#define HAS_N7751 0 -#endif -#ifndef HAS_M6800 -#define HAS_M6800 0 -#endif -#ifndef HAS_M6801 -#define HAS_M6801 0 -#endif -#ifndef HAS_M6802 -#define HAS_M6802 0 -#endif -#ifndef HAS_M6803 -#define HAS_M6803 0 -#endif -#ifndef HAS_M6808 -#define HAS_M6808 0 -#endif -#ifndef HAS_HD63701 -#define HAS_HD63701 0 -#endif -#ifndef HAS_M6805 -#define HAS_M6805 0 -#endif -#ifndef HAS_M68705 -#define HAS_M68705 0 -#endif -#ifndef HAS_HD63705 -#define HAS_HD63705 0 -#endif -#ifndef HAS_HD6309 -#define HAS_HD6309 0 -#endif -#ifndef HAS_M6809 -#define HAS_M6809 0 -#endif -#ifndef HAS_KONAMI -#define HAS_KONAMI 0 -#endif -#ifndef HAS_M68000 -#define HAS_M68000 0 -#endif -#ifndef HAS_M68010 -#define HAS_M68010 0 -#endif -#ifndef HAS_M68020 -#define HAS_M68020 0 -#endif -#ifndef HAS_T11 -#define HAS_T11 0 -#endif -#ifndef HAS_S2650 -#define HAS_S2650 0 -#endif -#ifndef HAS_TMS34010 -#define HAS_TMS34010 0 -#endif -#ifndef HAS_TMS9900 -#define HAS_TMS9900 0 -#endif -#ifndef HAS_TMS9940 -#define HAS_TMS9940 0 -#endif -#ifndef HAS_TMS9980 -#define HAS_TMS9980 0 -#endif -#ifndef HAS_TMS9985 -#define HAS_TMS9985 0 -#endif -#ifndef HAS_TMS9989 -#define HAS_TMS9989 0 -#endif -#ifndef HAS_TMS9995 -#define HAS_TMS9995 0 -#endif -#ifndef HAS_TMS99105A -#define HAS_TMS99105A 0 -#endif -#ifndef HAS_TMS99110A -#define HAS_TMS99110A 0 -#endif -#ifndef HAS_Z8000 -#define HAS_Z8000 0 -#endif -#ifndef HAS_TMS320C10 -#define HAS_TMS320C10 0 -#endif -#ifndef HAS_CCPU -#define HAS_CCPU 0 -#endif -#ifndef HAS_PDP1 -#define HAS_PDP1 0 -#endif -#ifndef HAS_ADSP2100 -#define HAS_ADSP2100 0 -#endif - -/* ASG 971222 -- added this generic structure */ -struct cpu_interface -{ - unsigned cpu_num; - void (*reset)(void *param); - void (*exit)(void); - int (*execute)(int cycles); - void (*burn)(int cycles); - unsigned (*get_context)(void *reg); - void (*set_context)(void *reg); - unsigned (*get_pc)(void); - void (*set_pc)(unsigned val); - unsigned (*get_sp)(void); - void (*set_sp)(unsigned val); - unsigned (*get_reg)(int regnum); - void (*set_reg)(int regnum, unsigned val); - void (*set_nmi_line)(int linestate); - void (*set_irq_line)(int irqline, int linestate); - void (*set_irq_callback)(int(*callback)(int irqline)); - void (*internal_interrupt)(int type); - void (*cpu_state_save)(void *file); - void (*cpu_state_load)(void *file); - const char* (*cpu_info)(void *context,int regnum); - unsigned (*cpu_dasm)(char *buffer,unsigned pc); - unsigned num_irqs; - int default_vector; - int *icount; - double overclock; - int no_int, irq_int, nmi_int; - int (*memory_read)(int offset); - void (*memory_write)(int offset, int data); - void (*set_op_base)(int pc); - int address_shift; - unsigned address_bits, endianess, align_unit, max_inst_len; - unsigned abits1, abits2, abitsmin; -}; - -extern struct cpu_interface cpuintf[]; - -void cpu_init(void); -void cpu_run(void); - -/* optional watchdog */ -void watchdog_reset_w(int offset,int data); -int watchdog_reset_r(int offset); -/* Use this function to reset the machine */ -void machine_reset(void); -/* Use this function to reset a single CPU */ -void cpu_set_reset_line(int cpu,int state); -/* Use this function to halt a single CPU */ -void cpu_set_halt_line(int cpu,int state); - -/* This function returns CPUNUM current status (running or halted) */ -int cpu_getstatus(int cpunum); -int cpu_gettotalcpu(void); -int cpu_getactivecpu(void); -void cpu_setactivecpu(int cpunum); - -/* Returns the current program counter */ -unsigned cpu_get_pc(void); -/* Set the current program counter */ -void cpu_set_pc(unsigned val); - -/* Returns the current stack pointer */ -unsigned cpu_get_sp(void); -/* Set the current stack pointer */ -void cpu_set_sp(unsigned val); - -/* Get the active CPUs context and return it's size */ -unsigned cpu_get_context(void *context); -/* Set the active CPUs context */ -void cpu_set_context(void *context); - -/* Returns a specific register value (mamedbg) */ -unsigned cpu_get_reg(int regnum); -/* Sets a specific register value (mamedbg) */ -void cpu_set_reg(int regnum, unsigned val); - -/* Returns previous pc (start of opcode causing read/write) */ -/* int cpu_getpreviouspc(void); */ -#define cpu_getpreviouspc() cpu_get_reg(REG_PREVIOUSPC) - -/* Returns the return address from the top of the stack (Z80 only) */ -/* int cpu_getreturnpc(void); */ -/* This can now be handled with a generic function */ -#define cpu_geturnpc() cpu_get_reg(REG_SP_CONTENTS) - -int cycles_currently_ran(void); -int cycles_left_to_run(void); - -/* Returns the number of CPU cycles which take place in one video frame */ -int cpu_gettotalcycles(void); -/* Returns the number of CPU cycles before the next interrupt handler call */ -int cpu_geticount(void); -/* Returns the number of CPU cycles before the end of the current video frame */ -int cpu_getfcount(void); -/* Returns the number of CPU cycles in one video frame */ -int cpu_getfperiod(void); -/* Scales a given value by the ratio of fcount / fperiod */ -int cpu_scalebyfcount(int value); -/* Returns the current scanline number */ -int cpu_getscanline(void); -/* Returns the amount of time until a given scanline */ -double cpu_getscanlinetime(int scanline); -/* Returns the duration of a single scanline */ -double cpu_getscanlineperiod(void); -/* Returns the duration of a single scanline in cycles */ -int cpu_getscanlinecycles(void); -/* Returns the number of cycles since the beginning of this frame */ -int cpu_getcurrentcycles(void); -/* Returns the current horizontal beam position in pixels */ -int cpu_gethorzbeampos(void); -/* - Returns the number of times the interrupt handler will be called before - the end of the current video frame. This is can be useful to interrupt - handlers to synchronize their operation. If you call this from outside - an interrupt handler, add 1 to the result, i.e. if it returns 0, it means - that the interrupt handler will be called once. -*/ -int cpu_getiloops(void); - -/* Returns the current VBLANK state */ -int cpu_getvblank(void); - -/* Returns the number of the video frame we are currently playing */ -int cpu_getcurrentframe(void); - - -/* generate a trigger after a specific period of time */ -void cpu_triggertime (double duration, int trigger); -/* generate a trigger now */ -void cpu_trigger (int trigger); - -/* burn CPU cycles until a timer trigger */ -void cpu_spinuntil_trigger (int trigger); -/* burn CPU cycles until the next interrupt */ -void cpu_spinuntil_int (void); -/* burn CPU cycles until our timeslice is up */ -void cpu_spin (void); -/* burn CPU cycles for a specific period of time */ -void cpu_spinuntil_time (double duration); - -/* yield our timeslice for a specific period of time */ -void cpu_yielduntil_trigger (int trigger); -/* yield our timeslice until the next interrupt */ -void cpu_yielduntil_int (void); -/* yield our current timeslice */ -void cpu_yield (void); -/* yield our timeslice for a specific period of time */ -void cpu_yielduntil_time (double duration); - -/* set the NMI line state for a CPU, normally use PULSE_LINE */ -void cpu_set_nmi_line(int cpunum, int state); -/* set the IRQ line state for a specific irq line of a CPU */ -/* normally use state HOLD_LINE, irqline 0 for first IRQ type of a cpu */ -void cpu_set_irq_line(int cpunum, int irqline, int state); -/* this is to be called by CPU cores only! */ -void cpu_generate_internal_interrupt(int cpunum, int type); -/* set the vector to be returned during a CPU's interrupt acknowledge cycle */ -void cpu_irq_line_vector_w(int cpunum, int irqline, int vector); - -/* use these in your write memory/port handles to set an IRQ vector */ -/* offset corresponds to the irq line number here */ -void cpu_0_irq_line_vector_w(int offset, int data); -void cpu_1_irq_line_vector_w(int offset, int data); -void cpu_2_irq_line_vector_w(int offset, int data); -void cpu_3_irq_line_vector_w(int offset, int data); -void cpu_4_irq_line_vector_w(int offset, int data); -void cpu_5_irq_line_vector_w(int offset, int data); -void cpu_6_irq_line_vector_w(int offset, int data); -void cpu_7_irq_line_vector_w(int offset, int data); - -/* Obsolete functions: avoid to use them in new drivers if possible. */ - -/* cause an interrupt on a CPU */ -void cpu_cause_interrupt(int cpu,int type); -void cpu_clear_pending_interrupts(int cpu); -void interrupt_enable_w(int offset,int data); -void interrupt_vector_w(int offset,int data); -int interrupt(void); -int nmi_interrupt(void); -int m68_level1_irq(void); -int m68_level2_irq(void); -int m68_level3_irq(void); -int m68_level4_irq(void); -int m68_level5_irq(void); -int m68_level6_irq(void); -int m68_level7_irq(void); -int ignore_interrupt(void); - -/* CPU context access */ -void* cpu_getcontext (int _activecpu); -int cpu_is_saving_context(int _activecpu); - -/*************************************************************************** - * Get information for the currently active CPU - * cputype is a value from the CPU enum in driver.h - ***************************************************************************/ -/* Return number of address bits */ -unsigned cpu_address_bits(void); -/* Return address mask */ -unsigned cpu_address_mask(void); -/* Return address shift factor (TMS34010 bit addressing mode) */ -int cpu_address_shift(void); -/* Return endianess of the emulated CPU (CPU_IS_LE or CPU_IS_BE) */ -unsigned cpu_endianess(void); -/* Return opcode align unit (1 byte, 2 word, 4 dword) */ -unsigned cpu_align_unit(void); -/* Return maximum instruction length */ -unsigned cpu_max_inst_len(void); - -/* Return name of the active CPU */ -const char *cpu_name(void); -/* Return family name of the active CPU */ -const char *cpu_core_family(void); -/* Return core version of the active CPU */ -const char *cpu_core_version(void); -/* Return core filename of the active CPU */ -const char *cpu_core_file(void); -/* Return credits info for of the active CPU */ -const char *cpu_core_credits(void); -/* Return register layout definition for the active CPU */ -const char *cpu_reg_layout(void); -/* Return (debugger) window layout definition for the active CPU */ -const char *cpu_win_layout(void); - -/* Disassemble an instruction at PC into the given buffer */ -unsigned cpu_dasm(char *buffer, unsigned pc); -/* Return a string describing the currently set flag (status) bits of the active CPU */ -const char *cpu_flags(void); -/* Return a string with a register name and hex value for the active CPU */ -/* regnum is a value defined in the CPU cores header files */ -const char *cpu_dump_reg(int regnum); -/* Return a string describing the active CPUs current state */ -const char *cpu_dump_state(void); - -/*************************************************************************** - * Get information for a specific CPU type - * cputype is a value from the CPU enum in driver.h - ***************************************************************************/ -/* Return address shift factor */ -/* TMS320C10 -1: word addressing mode, TMS34010 3: bit addressing mode */ -int cputype_address_shift(int cputype); -/* Return number of address bits */ -unsigned cputype_address_bits(int cputype); -/* Return address mask */ -unsigned cputype_address_mask(int cputype); -/* Return endianess of the emulated CPU (CPU_IS_LE or CPU_IS_BE) */ -unsigned cputype_endianess(int cputype); -/* Return opcode align unit (1 byte, 2 word, 4 dword) */ -unsigned cputype_align_unit(int cputype); -/* Return maximum instruction length */ -unsigned cputype_max_inst_len(int cputype); - -/* Return name of the CPU */ -const char *cputype_name(int cputype); -/* Return family name of the CPU */ -const char *cputype_core_family(int cputype); -/* Return core version number of the CPU */ -const char *cputype_core_version(int cputype); -/* Return core filename of the CPU */ -const char *cputype_core_file(int cputype); -/* Return credits for the CPU core */ -const char *cputype_core_credits(int cputype); -/* Return register layout definition for the CPU core */ -const char *cputype_reg_layout(int cputype); -/* Return (debugger) window layout definition for the CPU core */ -const char *cputype_win_layout(int cputype); - -/*************************************************************************** - * Get (or set) information for a numbered CPU of the running machine - * cpunum is a value between 0 and cpu_gettotalcpu() - 1 - ***************************************************************************/ -/* Return number of address bits */ -unsigned cpunum_address_bits(int cputype); -/* Return address mask */ -unsigned cpunum_address_mask(int cputype); -/* Return endianess of the emulated CPU (CPU_LSB_FIRST or CPU_MSB_FIRST) */ -unsigned cpunum_endianess(int cputype); -/* Return opcode align unit (1 byte, 2 word, 4 dword) */ -unsigned cpunum_align_unit(int cputype); -/* Return maximum instruction length */ -unsigned cpunum_max_inst_len(int cputype); - -/* Get a register value for the specified CPU number of the running machine */ -unsigned cpunum_get_reg(int cpunum, int regnum); -/* Set a register value for the specified CPU number of the running machine */ -void cpunum_set_reg(int cpunum, int regnum, unsigned val); - -/* Return (debugger) register layout definition for the CPU core */ -const char *cpunum_reg_layout(int cpunum); -/* Return (debugger) window layout definition for the CPU core */ -const char *cpunum_win_layout(int cpunum); - -unsigned cpunum_dasm(int cpunum,char *buffer,unsigned pc); -/* Return a string describing the currently set flag (status) bits of the CPU */ -const char *cpunum_flags(int cpunum); -/* Return a string with a register name and value */ -/* regnum is a value defined in the CPU cores header files */ -const char *cpunum_dump_reg(int cpunum, int regnum); -/* Return a string describing the CPUs current state */ -const char *cpunum_dump_state(int cpunum); -/* Return a name for the specified cpu number */ -const char *cpunum_name(int cpunum); -/* Return a family name for the specified cpu number */ -const char *cpunum_core_family(int cpunum); -/* Return a version for the specified cpu number */ -const char *cpunum_core_version(int cpunum); -/* Return a the source filename for the specified cpu number */ -const char *cpunum_core_file(int cpunum); -/* Return a the credits for the specified cpu number */ -const char *cpunum_core_credits(int cpunum); - -/* Dump all of the running machines CPUs state to stderr */ -void cpu_dump_states(void); - -/* daisy-chain link */ -typedef struct { - void (*reset)(int); /* reset callback */ - int (*interrupt_entry)(int); /* entry callback */ - void (*interrupt_reti)(int); /* reti callback */ - int irq_param; /* callback paramater */ -} Z80_DaisyChain; - -#define Z80_MAXDAISY 4 /* maximum of daisy chan device */ - -#define Z80_INT_REQ 0x01 /* interrupt request mask */ -#define Z80_INT_IEO 0x02 /* interrupt disable mask(IEO) */ - -#define Z80_VECTOR(device,state) (((device)<<8)|(state)) - -#ifndef INLINE -#define INLINE inline -#endif - -#include -#include -#include - -#define cpu_readmem16 memory_read -#define cpu_readport16 memory_readport -#define cpu_writeport16 memory_writeport -#define cpu_writemem16 memory_write -#define cpu_readop memory_readop -#define cpu_readop_arg memory_read -#define logerror(x, ...) -#define change_pc16(x) -#define CALL_MAME_DEBUG - -#define ADDRESS_SPACES 3 /* maximum number of address spaces */ -#define ADDRESS_SPACE_PROGRAM 0 /* program address space */ -#define ADDRESS_SPACE_DATA 1 /* data address space */ -#define ADDRESS_SPACE_IO 2 /* I/O address space */ - -enum -{ - /* internal flags (not for use by drivers!) */ - INTERNAL_CLEAR_LINE = 100 + CLEAR_LINE, - INTERNAL_ASSERT_LINE = 100 + ASSERT_LINE, - - /* input lines */ - MAX_INPUT_LINES = 32+3, - INPUT_LINE_IRQ0 = 0, - INPUT_LINE_IRQ1 = 1, - INPUT_LINE_IRQ2 = 2, - INPUT_LINE_IRQ3 = 3, - INPUT_LINE_IRQ4 = 4, - INPUT_LINE_IRQ5 = 5, - INPUT_LINE_IRQ6 = 6, - INPUT_LINE_IRQ7 = 7, - INPUT_LINE_IRQ8 = 8, - INPUT_LINE_IRQ9 = 9, - INPUT_LINE_NMI = MAX_INPUT_LINES - 3, - - /* special input lines that are implemented in the core */ - INPUT_LINE_RESET = MAX_INPUT_LINES - 2, - INPUT_LINE_HALT = MAX_INPUT_LINES - 1, - - /* output lines */ - MAX_OUTPUT_LINES = 32 -}; - -enum -{ - /* --- the following bits of info are returned as 64-bit signed integers --- */ - CPUINFO_INT_FIRST = 0x00000, - - CPUINFO_INT_CONTEXT_SIZE = CPUINFO_INT_FIRST, /* R/O: size of CPU context in bytes */ - CPUINFO_INT_INPUT_LINES, /* R/O: number of input lines */ - CPUINFO_INT_OUTPUT_LINES, /* R/O: number of output lines */ - CPUINFO_INT_DEFAULT_IRQ_VECTOR, /* R/O: default IRQ vector */ - CPUINFO_INT_ENDIANNESS, /* R/O: either CPU_IS_BE or CPU_IS_LE */ - CPUINFO_INT_CLOCK_DIVIDER, /* R/O: internal clock divider */ - CPUINFO_INT_MIN_INSTRUCTION_BYTES, /* R/O: minimum bytes per instruction */ - CPUINFO_INT_MAX_INSTRUCTION_BYTES, /* R/O: maximum bytes per instruction */ - CPUINFO_INT_MIN_CYCLES, /* R/O: minimum cycles for a single instruction */ - CPUINFO_INT_MAX_CYCLES, /* R/O: maximum cycles for a single instruction */ - - CPUINFO_INT_DATABUS_WIDTH, /* R/O: data bus size for each address space (8,16,32,64) */ - CPUINFO_INT_DATABUS_WIDTH_LAST = CPUINFO_INT_DATABUS_WIDTH + ADDRESS_SPACES - 1, - CPUINFO_INT_ADDRBUS_WIDTH, /* R/O: address bus size for each address space (12-32) */ - CPUINFO_INT_ADDRBUS_WIDTH_LAST = CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACES - 1, - CPUINFO_INT_ADDRBUS_SHIFT, /* R/O: shift applied to addresses each address space (+3 means >>3, -1 means <<1) */ - CPUINFO_INT_ADDRBUS_SHIFT_LAST = CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACES - 1, - - CPUINFO_INT_SP, /* R/W: the current stack pointer value */ - CPUINFO_INT_PC, /* R/W: the current PC value */ - CPUINFO_INT_PREVIOUSPC, /* R/W: the previous PC value */ - CPUINFO_INT_INPUT_STATE, /* R/W: states for each input line */ - CPUINFO_INT_INPUT_STATE_LAST = CPUINFO_INT_INPUT_STATE + MAX_INPUT_LINES - 1, - CPUINFO_INT_OUTPUT_STATE, /* R/W: states for each output line */ - CPUINFO_INT_OUTPUT_STATE_LAST = CPUINFO_INT_OUTPUT_STATE + MAX_OUTPUT_LINES - 1, - CPUINFO_INT_REGISTER, /* R/W: values of up to MAX_REGs registers */ - CPUINFO_INT_REGISTER_LAST = CPUINFO_INT_REGISTER + MAX_REGS - 1, - - CPUINFO_INT_CPU_SPECIFIC = 0x08000, /* R/W: CPU-specific values start here */ - - /* --- the following bits of info are returned as pointers to data or functions --- */ - CPUINFO_PTR_FIRST = 0x10000, - - CPUINFO_PTR_SET_INFO = CPUINFO_PTR_FIRST, /* R/O: void (*set_info)(UINT32 state, INT64 data, void *ptr) */ - CPUINFO_PTR_GET_CONTEXT, /* R/O: void (*get_context)(void *buffer) */ - CPUINFO_PTR_SET_CONTEXT, /* R/O: void (*set_context)(void *buffer) */ - CPUINFO_PTR_INIT, /* R/O: void (*init)(void) */ - CPUINFO_PTR_RESET, /* R/O: void (*reset)(void *param) */ - CPUINFO_PTR_EXIT, /* R/O: void (*exit)(void) */ - CPUINFO_PTR_EXECUTE, /* R/O: int (*execute)(int cycles) */ - CPUINFO_PTR_BURN, /* R/O: void (*burn)(int cycles) */ - CPUINFO_PTR_DISASSEMBLE, /* R/O: void (*disassemble)(char *buffer, offs_t pc) */ - CPUINFO_PTR_IRQ_CALLBACK, /* R/W: int (*irqcallback)(int state) */ - CPUINFO_PTR_INSTRUCTION_COUNTER, /* R/O: int *icount */ - CPUINFO_PTR_REGISTER_LAYOUT, /* R/O: struct debug_register_layout *layout */ - CPUINFO_PTR_WINDOW_LAYOUT, /* R/O: struct debug_window_layout *layout */ - CPUINFO_PTR_INTERNAL_MEMORY_MAP, /* R/O: construct_map_t map */ - CPUINFO_PTR_INTERNAL_MEMORY_MAP_LAST = CPUINFO_PTR_INTERNAL_MEMORY_MAP + ADDRESS_SPACES - 1, - CPUINFO_PTR_DEBUG_REGISTER_LIST, /* R/O: int *list: list of registers for NEW_DEBUGGER */ - - CPUINFO_PTR_CPU_SPECIFIC = 0x18000, /* R/W: CPU-specific values start here */ - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - CPUINFO_STR_FIRST = 0x20000, - - CPUINFO_STR_NAME = CPUINFO_STR_FIRST, /* R/O: name of the CPU */ - CPUINFO_STR_CORE_FAMILY, /* R/O: family of the CPU */ - CPUINFO_STR_CORE_VERSION, /* R/O: version of the CPU core */ - CPUINFO_STR_CORE_FILE, /* R/O: file containing the CPU core */ - CPUINFO_STR_CORE_CREDITS, /* R/O: credits for the CPU core */ - CPUINFO_STR_FLAGS, /* R/O: string representation of the main flags value */ - CPUINFO_STR_REGISTER, /* R/O: string representation of up to MAX_REGs registers */ - CPUINFO_STR_REGISTER_LAST = CPUINFO_STR_REGISTER + MAX_REGS - 1, - - CPUINFO_STR_CPU_SPECIFIC = 0x28000 /* R/W: CPU-specific values start here */ -}; - -#endif /* CPUINTRF_H */ diff --git a/Frameworks/AudioOverload/aosdk/eng_psf/eng_psf.c b/Frameworks/AudioOverload/aosdk/eng_psf/eng_psf.c deleted file mode 100644 index e8bf34400..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_psf/eng_psf.c +++ /dev/null @@ -1,463 +0,0 @@ -/* - Audio Overload SDK - PSF file format engine - - Copyright (c) 2007 R. Belmont and Richard Bannister. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - * Neither the names of R. Belmont and Richard Bannister nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#include -#include -#include - -#include "ao.h" -#include "eng_protos.h" -#include "cpuintrf.h" -#include "psx.h" - -#include "peops/stdafx.h" -#include "peops/externals.h" -#include "peops/regs.h" -#include "peops/registers.h" -#include "peops/spu.h" - - -#include "corlett.h" - -#define DEBUG_LOADER (0) - -static corlett_t *c = NULL; -static char psfby[256]; -char *spu_pOutput; -int psf_refresh = -1; - - -// main RAM -extern uint32 psx_ram[((2*1024*1024)/4)+4]; -extern uint32 psx_scratch[0x400]; -extern uint32 initial_ram[((2*1024*1024)/4)+4]; -extern uint32 initial_scratch[0x400]; -static uint32 initialPC, initialGP, initialSP; - -extern void mips_init( void ); -extern void mips_reset( void *param ); -extern int mips_execute( int cycles ); -extern void mips_set_info(UINT32 state, union cpuinfo *info); -extern void psx_hw_init(void); -extern void psx_hw_slice(void); -extern void psx_hw_frame(void); -extern void setlength(int32 stop, int32 fade); - -int32 psf_start(uint8 *buffer, uint32 length) -{ - uint8 *file, *lib_decoded, *lib_raw_file, *alib_decoded; - uint32 offset, plength, PC, SP, GP, lengthMS, fadeMS; - uint64 file_len, lib_len, lib_raw_length, alib_len; - corlett_t *lib; - int i; - union cpuinfo mipsinfo; - - // clear PSX work RAM before we start scribbling in it - memset(psx_ram, 0, 2*1024*1024); - -// printf("Length = %d\n", length); - - // Decode the current GSF - if (corlett_decode(buffer, length, &file, &file_len, &c) != AO_SUCCESS) - { - return AO_FAIL; - } - -// printf("file_len %d reserve %d\n", file_len, c->res_size); - - // check for PSX EXE signature - if (strncmp((char *)file, "PS-X EXE", 8)) - { - return AO_FAIL; - } - - #if DEBUG_LOADER - offset = file[0x18] | file[0x19]<<8 | file[0x1a]<<16 | file[0x1b]<<24; - printf("Text section start: %x\n", offset); - offset = file[0x1c] | file[0x1d]<<8 | file[0x1e]<<16 | file[0x1f]<<24; - printf("Text section size: %x\n", offset); - printf("Region: [%s]\n", &file[0x4c]); - printf("refresh: [%s]\n", c->inf_refresh); - #endif - - if (c->inf_refresh[0] == '5') - { - psf_refresh = 50; - } - if (c->inf_refresh[0] == '6') - { - psf_refresh = 60; - } - - PC = file[0x10] | file[0x11]<<8 | file[0x12]<<16 | file[0x13]<<24; - GP = file[0x14] | file[0x15]<<8 | file[0x16]<<16 | file[0x17]<<24; - SP = file[0x30] | file[0x31]<<8 | file[0x32]<<16 | file[0x33]<<24; - - #if DEBUG_LOADER - printf("Top level: PC %x GP %x SP %x\n", PC, GP, SP); - #endif - - // Get the library file, if any - if (c->lib[0] != 0) - { - uint64 tmp_length; - - #if DEBUG_LOADER - printf("Loading library: %s\n", c->lib); - #endif - if (ao_get_lib(c->lib, &lib_raw_file, &tmp_length) != AO_SUCCESS) - { - return AO_FAIL; - } - lib_raw_length = tmp_length; - - if (corlett_decode(lib_raw_file, lib_raw_length, &lib_decoded, &lib_len, &lib) != AO_SUCCESS) - { - free(lib_raw_file); - return AO_FAIL; - } - - // Free up raw file - free(lib_raw_file); - - if (strncmp((char *)lib_decoded, "PS-X EXE", 8)) - { - printf("Major error! PSF was OK, but referenced library is not!\n"); - free(lib); - return AO_FAIL; - } - - #if DEBUG_LOADER - offset = lib_decoded[0x18] | lib_decoded[0x19]<<8 | lib_decoded[0x1a]<<16 | lib_decoded[0x1b]<<24; - printf("Text section start: %x\n", offset); - offset = lib_decoded[0x1c] | lib_decoded[0x1d]<<8 | lib_decoded[0x1e]<<16 | lib_decoded[0x1f]<<24; - printf("Text section size: %x\n", offset); - printf("Region: [%s]\n", &lib_decoded[0x4c]); - printf("refresh: [%s]\n", lib->inf_refresh); - #endif - - // if the original file had no refresh tag, give the lib a shot - if (psf_refresh == -1) - { - if (lib->inf_refresh[0] == '5') - { - psf_refresh = 50; - } - if (lib->inf_refresh[0] == '6') - { - psf_refresh = 60; - } - } - - PC = lib_decoded[0x10] | lib_decoded[0x11]<<8 | lib_decoded[0x12]<<16 | lib_decoded[0x13]<<24; - GP = lib_decoded[0x14] | lib_decoded[0x15]<<8 | lib_decoded[0x16]<<16 | lib_decoded[0x17]<<24; - SP = lib_decoded[0x30] | lib_decoded[0x31]<<8 | lib_decoded[0x32]<<16 | lib_decoded[0x33]<<24; - - #if DEBUG_LOADER - printf("Library: PC %x GP %x SP %x\n", PC, GP, SP); - #endif - - // now patch the file into RAM - offset = lib_decoded[0x18] | lib_decoded[0x19]<<8 | lib_decoded[0x1a]<<16 | lib_decoded[0x1b]<<24; - offset &= 0x3fffffff; // kill any MIPS cache segment indicators - plength = lib_decoded[0x1c] | lib_decoded[0x1d]<<8 | lib_decoded[0x1e]<<16 | lib_decoded[0x1f]<<24; - #if DEBUG_LOADER - printf("library offset: %x plength: %d\n", offset, plength); - #endif - memcpy(&psx_ram[offset/4], lib_decoded+2048, plength); - - // Dispose the corlett structure for the lib - we don't use it - free(lib); - free(lib_decoded); - } - - // now patch the main file into RAM OVER the libraries (but not the aux lib) - offset = file[0x18] | file[0x19]<<8 | file[0x1a]<<16 | file[0x1b]<<24; - offset &= 0x3fffffff; // kill any MIPS cache segment indicators - plength = file[0x1c] | file[0x1d]<<8 | file[0x1e]<<16 | file[0x1f]<<24; - - // Philosoma has an illegal "plength". *sigh* - if (plength > (file_len-2048)) - { - plength = file_len-2048; - } - memcpy(&psx_ram[offset/4], file+2048, plength); - - // load any auxiliary libraries now - for (i = 0; i < 8; i++) - { - if (c->libaux[i][0] != 0) - { - uint64 tmp_length; - - #if DEBUG_LOADER - printf("Loading aux library: %s\n", c->libaux[i]); - #endif - - if (ao_get_lib(c->libaux[i], &lib_raw_file, &tmp_length) != AO_SUCCESS) - { - return AO_FAIL; - } - lib_raw_length = tmp_length; - - if (corlett_decode(lib_raw_file, lib_raw_length, &alib_decoded, &alib_len, &lib) != AO_SUCCESS) - { - free(lib_raw_file); - return AO_FAIL; - } - - // Free up raw file - free(lib_raw_file); - - if (strncmp((char *)alib_decoded, "PS-X EXE", 8)) - { - printf("Major error! PSF was OK, but referenced library is not!\n"); - free(lib); - return AO_FAIL; - } - - #if DEBUG_LOADER - offset = alib_decoded[0x18] | alib_decoded[0x19]<<8 | alib_decoded[0x1a]<<16 | alib_decoded[0x1b]<<24; - printf("Text section start: %x\n", offset); - offset = alib_decoded[0x1c] | alib_decoded[0x1d]<<8 | alib_decoded[0x1e]<<16 | alib_decoded[0x1f]<<24; - printf("Text section size: %x\n", offset); - printf("Region: [%s]\n", &alib_decoded[0x4c]); - #endif - - // now patch the file into RAM - offset = alib_decoded[0x18] | alib_decoded[0x19]<<8 | alib_decoded[0x1a]<<16 | alib_decoded[0x1b]<<24; - offset &= 0x3fffffff; // kill any MIPS cache segment indicators - plength = alib_decoded[0x1c] | alib_decoded[0x1d]<<8 | alib_decoded[0x1e]<<16 | alib_decoded[0x1f]<<24; - memcpy(&psx_ram[offset/4], alib_decoded+2048, plength); - - // Dispose the corlett structure for the lib - we don't use it - free(lib); - free(alib_decoded); - } - } - - free(file); - - // Finally, set psfby tag - strcpy(psfby, "n/a"); - if (c) - { - int i; - for (i = 0; i < MAX_UNKNOWN_TAGS; i++) - { - if (!strcasecmp(c->tag_name[i], "psfby")) - strcpy(psfby, c->tag_data[i]); - } - } - - mips_init(); - mips_reset(NULL); - - // set the initial PC, SP, GP - #if DEBUG_LOADER - printf("Initial PC %x, GP %x, SP %x\n", PC, GP, SP); - printf("Refresh = %d\n", psf_refresh); - #endif - mipsinfo.i = PC; - mips_set_info(CPUINFO_INT_PC, &mipsinfo); - - // set some reasonable default for the stack - if (SP == 0) - { - SP = 0x801fff00; - } - - mipsinfo.i = SP; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R29, &mipsinfo); - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R30, &mipsinfo); - - mipsinfo.i = GP; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R28, &mipsinfo); - - #if DEBUG_LOADER && 1 - { - FILE *f; - - f = fopen("psxram.bin", "wb"); - fwrite(psx_ram, 2*1024*1024, 1, f); - fclose(f); - } - #endif - - psx_hw_init(); - SPUinit(); - SPUopen(); - - lengthMS = psfTimeToMS(c->inf_length); - fadeMS = psfTimeToMS(c->inf_fade); - - #if DEBUG_LOADER - printf("length %d fade %d\n", lengthMS, fadeMS); - #endif - - if (lengthMS == 0) - { - lengthMS = ~0; - } - - setlength(lengthMS, fadeMS); - - // patch illegal Chocobo Dungeon 2 code - CaitSith2 put a jump in the delay slot from a BNE - // and rely on Highly Experimental's buggy-ass CPU to rescue them. Verified on real hardware - // that the initial code is wrong. - if (c->inf_game) - { - if (!strcmp(c->inf_game, "Chocobo Dungeon 2")) - { - if (psx_ram[0xbc090/4] == LE32(0x0802f040)) - { - psx_ram[0xbc090/4] = LE32(0); - psx_ram[0xbc094/4] = LE32(0x0802f040); - psx_ram[0xbc098/4] = LE32(0); - } - } - } - -// psx_ram[0x118b8/4] = LE32(0); // crash 2 hack - - // backup the initial state for restart - memcpy(initial_ram, psx_ram, 2*1024*1024); - memcpy(initial_scratch, psx_scratch, 0x400); - initialPC = PC; - initialGP = GP; - initialSP = SP; - - mips_execute(5000); - - return AO_SUCCESS; -} - -void spu_update(unsigned char* pSound,long lBytes) -{ - memcpy(spu_pOutput, pSound, lBytes); -} - -int32 psf_gen(int16 *buffer, uint32 samples) -{ - int i; - - for (i = 0; i < samples; i++) - { - psx_hw_slice(); - SPUasync(384); - } - - spu_pOutput = (char *)buffer; - SPU_flushboot(); - - psx_hw_frame(); - - return AO_SUCCESS; -} - -int32 psf_stop(void) -{ - SPUclose(); - free(c); - - return AO_SUCCESS; -} - -int32 psf_command(int32 command, int32 parameter) -{ - union cpuinfo mipsinfo; - uint32 lengthMS, fadeMS; - - switch (command) - { - case COMMAND_RESTART: - SPUclose(); - - memcpy(psx_ram, initial_ram, 2*1024*1024); - memcpy(psx_scratch, initial_scratch, 0x400); - - mips_init(); - mips_reset(NULL); - psx_hw_init(); - SPUinit(); - SPUopen(); - - lengthMS = psfTimeToMS(c->inf_length); - fadeMS = psfTimeToMS(c->inf_fade); - - if (lengthMS == 0) - { - lengthMS = ~0; - } - setlength(lengthMS, fadeMS); - - mipsinfo.i = initialPC; - mips_set_info(CPUINFO_INT_PC, &mipsinfo); - mipsinfo.i = initialSP; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R29, &mipsinfo); - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R30, &mipsinfo); - mipsinfo.i = initialGP; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R28, &mipsinfo); - - mips_execute(5000); - - return AO_SUCCESS; - - } - return AO_FAIL; -} - -int32 psf_fill_info(ao_display_info *info) -{ - if (c == NULL) - return AO_FAIL; - - strcpy(info->title[1], "Name: "); - sprintf(info->info[1], "%s", c->inf_title); - - strcpy(info->title[2], "Game: "); - sprintf(info->info[2], "%s", c->inf_game); - - strcpy(info->title[3], "Artist: "); - sprintf(info->info[3], "%s", c->inf_artist); - - strcpy(info->title[4], "Copyright: "); - sprintf(info->info[4], "%s", c->inf_copy); - - strcpy(info->title[5], "Year: "); - sprintf(info->info[5], "%s", c->inf_year); - - strcpy(info->title[6], "Length: "); - sprintf(info->info[6], "%s", c->inf_length); - - strcpy(info->title[7], "Fade: "); - sprintf(info->info[7], "%s", c->inf_fade); - - strcpy(info->title[8], "Ripper: "); - sprintf(info->info[8], "%s", psfby); - - return AO_SUCCESS; -} diff --git a/Frameworks/AudioOverload/aosdk/eng_psf/eng_psf2.c b/Frameworks/AudioOverload/aosdk/eng_psf/eng_psf2.c deleted file mode 100644 index d7c136009..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_psf/eng_psf2.c +++ /dev/null @@ -1,717 +0,0 @@ -/* - Audio Overload SDK - PSF2 file format engine - - Copyright (c) 2007-2008 R. Belmont and Richard Bannister. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - * Neither the names of R. Belmont and Richard Bannister nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -// -// Audio Overload -// Emulated music player -// -// (C) 2000-2008 Richard F. Bannister -// - -// -// eng_psf2.c -// -// References: -// psf_format.txt v1.6 by Neill Corlett (filesystem and decompression info) -// Intel ELF format specs ELF.PS (general ELF parsing info) -// http://ps2dev.org/kb.x?T=457 (IRX relocation and inter-module call info) -// http://ps2dev.org/ (the whole site - lots of IOP info) -// spu2regs.txt (comes with SexyPSF source: IOP hardware info) -// 64-bit ELF Object File Specification: http://techpubs.sgi.com/library/manuals/4000/007-4658-001/pdf/007-4658-001.pdf (MIPS ELF relocation types) - -#include -#include -#include -#include - -#include "ao.h" -#include "eng_protos.h" -#include "cpuintrf.h" -#include "psx.h" - -#include "peops2/stdafx.h" -#include "peops2/externals.h" -#include "peops2/regs.h" -#include "peops2/registers.h" -#include "peops2/spu.h" - -#include "corlett.h" - -#define DEBUG_LOADER (0) -#define MAX_FS (32) // maximum # of filesystems (libs and subdirectories) - -// ELF relocation helpers -#define ELF32_R_SYM(val) ((val) >> 8) -#define ELF32_R_TYPE(val) ((val) & 0xff) - -static corlett_t *c = NULL; -static char psfby[256]; -static char *spu_pOutput; - -// main RAM -extern uint32 psx_ram[(2*1024*1024)/4]; -extern uint32 initial_ram[(2*1024*1024)/4]; -static uint32 initialPC, initialSP; -static uint32 loadAddr, lengthMS, fadeMS; - -static uint8 *filesys[MAX_FS]; -static uint8 *lib_raw_file; -static uint32 fssize[MAX_FS]; -static int num_fs; - -extern void mips_init( void ); -extern void mips_reset( void *param ); -extern int mips_execute( int cycles ); -extern void mips_set_info(UINT32 state, union cpuinfo *info); -extern void psx_hw_init(void); -extern void ps2_hw_slice(void); -extern void ps2_hw_frame(void); -extern void setlength2(int32 stop, int32 fade); - -static uint32 secname(uint8 *start, uint32 strndx, uint32 shoff, uint32 shentsize, uint32 name) -{ - uint32 offset, shent; - - // get string table section - shent = shoff + (shentsize * strndx); - - // find the offset to the section - offset = start[shent+16] | start[shent+17]<<8 | start[shent+18]<<16 | start[shent+19]<<24; - - offset += name; - - return offset; -} - -static void do_iopmod(uint8 *start, uint32 offset) -{ - uint32 nameoffs, saddr, heap, tsize, dsize, bsize, vers2; - - nameoffs = start[offset] | start[offset+1]<<8 | start[offset+2]<<16 | start[offset+3]<<24; - - saddr = start[offset+4] | start[offset+5]<<8 | start[offset+6]<<16 | start[offset+7]<<24; - heap = start[offset+8] | start[offset+9]<<8 | start[offset+10]<<16 | start[offset+11]<<24; - tsize = start[offset+12] | start[offset+13]<<8 | start[offset+14]<<16 | start[offset+15]<<24; - dsize = start[offset+16] | start[offset+17]<<8 | start[offset+18]<<16 | start[offset+19]<<24; - bsize = start[offset+20] | start[offset+21]<<8 | start[offset+22]<<16 | start[offset+23]<<24; - vers2 = start[offset+24] | start[offset+25]<<8; - -// printf("nameoffs %08x saddr %08x heap %08x tsize %08x dsize %08x bsize %08x\n", nameoffs, saddr, heap, tsize, dsize, bsize); - #if DEBUG_LOADER - printf("vers: %04x name [%s]\n", vers2, &start[offset+26]); - #endif -} - -uint32 psf2_load_elf(uint8 *start, uint32 len) -{ - uint32 entry, phoff, shoff, phentsize, shentsize, phnum, shnum, shstrndx; - uint32 name, type, flags, addr, offset, size, shent; - uint32 totallen; - int i, rec; -// FILE *f; - - if (loadAddr & 3) - { - loadAddr &= ~3; - loadAddr += 4; - } - - #if DEBUG_LOADER - printf("psf2_load_elf: starting at %08x\n", loadAddr | 0x80000000); - #endif - - if ((start[0] != 0x7f) || (start[1] != 'E') || (start[2] != 'L') || (start[3] != 'F')) - { - printf("Not an ELF file\n"); - return 0xffffffff; - } - - entry = start[24] | start[25]<<8 | start[26]<<16 | start[27]<<24; // 0x18 - phoff = start[28] | start[29]<<8 | start[30]<<16 | start[31]<<24; // 0x1c - shoff = start[32] | start[33]<<8 | start[34]<<16 | start[35]<<24; // 0x20 - -// printf("Entry: %08x phoff %08x shoff %08x\n", entry, phoff, shoff); - - phentsize = start[42] | start[43]<<8; // 0x2a - phnum = start[44] | start[45]<<8; // 0x2c - shentsize = start[46] | start[47]<<8; // 0x2e - shnum = start[48] | start[49]<<8; // 0x30 - shstrndx = start[50] | start[51]<<8; // 0x32 - -// printf("phentsize %08x phnum %d shentsize %08x shnum %d shstrndx %d\n", phentsize, phnum, shentsize, shnum, shstrndx); - - // process ELF sections - shent = shoff; - totallen = 0; - for (i = 0; i < shnum; i++) - { - name = start[shent] | start[shent+1]<<8 | start[shent+2]<<16 | start[shent+3]<<24; - type = start[shent+4] | start[shent+5]<<8 | start[shent+6]<<16 | start[shent+7]<<24; - flags = start[shent+8] | start[shent+9]<<8 | start[shent+10]<<16 | start[shent+11]<<24; - addr = start[shent+12] | start[shent+13]<<8 | start[shent+14]<<16 | start[shent+15]<<24; - offset = start[shent+16] | start[shent+17]<<8 | start[shent+18]<<16 | start[shent+19]<<24; - size = start[shent+20] | start[shent+21]<<8 | start[shent+22]<<16 | start[shent+23]<<24; - -// printf("Section %02d: name %08x [%s] type %08x flags %08x addr %08x offset %08x size %08x\n", i, name, &start[secname(start, shstrndx, shoff, shentsize, name)], type, flags, addr, offset, size); - - switch (type) - { - case 0: // section table header - do nothing - break; - - case 1: // PROGBITS: copy data to destination - memcpy(&psx_ram[(loadAddr + addr)/4], &start[offset], size); - totallen += size; - break; - - case 2: // SYMTAB: ignore - break; - - case 3: // STRTAB: ignore - break; - - case 8: // NOBITS: BSS region, zero out destination - memset(&psx_ram[(loadAddr + addr)/4], 0, size); - totallen += size; - break; - - case 9: // REL: short relocation data - for (rec = 0; rec < (size/8); rec++) - { - uint32 offs, info, target, temp, val, vallo; - static uint32 hi16offs = 0, hi16target = 0; - - offs = start[offset+(rec*8)] | start[offset+1+(rec*8)]<<8 | start[offset+2+(rec*8)]<<16 | start[offset+3+(rec*8)]<<24; - info = start[offset+4+(rec*8)] | start[offset+5+(rec*8)]<<8 | start[offset+6+(rec*8)]<<16 | start[offset+7+(rec*8)]<<24; - target = LE32(psx_ram[(loadAddr+offs)/4]); - -// printf("[%04d] offs %08x type %02x info %08x => %08x\n", rec, offs, ELF32_R_TYPE(info), ELF32_R_SYM(info), target); - - switch (ELF32_R_TYPE(info)) - { - case 2: // R_MIPS_32 - target += loadAddr; -// target |= 0x80000000; - break; - - case 4: // R_MIPS_26 - temp = (target & 0x03ffffff); - target &= 0xfc000000; - temp += (loadAddr>>2); - target |= temp; - break; - - case 5: // R_MIPS_HI16 - hi16offs = offs; - hi16target = target; - break; - - case 6: // R_MIPS_LO16 - vallo = ((target & 0xffff) ^ 0x8000) - 0x8000; - - val = ((hi16target & 0xffff) << 16) + vallo; - val += loadAddr; -// val |= 0x80000000; - - /* Account for the sign extension that will happen in the low bits. */ - val = ((val >> 16) + ((val & 0x8000) != 0)) & 0xffff; - - hi16target = (hi16target & ~0xffff) | val; - - /* Ok, we're done with the HI16 relocs. Now deal with the LO16. */ - val = loadAddr + vallo; - target = (target & ~0xffff) | (val & 0xffff); - - psx_ram[(loadAddr+hi16offs)/4] = LE32(hi16target); - break; - - default: - printf("FATAL: Unknown MIPS ELF relocation!\n"); - return 0xffffffff; - break; - } - - psx_ram[(loadAddr+offs)/4] = LE32(target); - } - break; - - case 0x70000080: // .iopmod - do_iopmod(start, offset); - break; - - default: - #if DEBUG_LOADER - printf("Unhandled ELF section type %d\n", type); - #endif - break; - } - - shent += shentsize; - } - - entry += loadAddr; - entry |= 0x80000000; - loadAddr += totallen; - - #if DEBUG_LOADER - printf("psf2_load_elf: entry PC %08x\n", entry); - #endif - return entry; -} - -static uint32 load_file_ex(uint8 *top, uint8 *start, uint32 len, char *file, uint8 *buf, uint32 buflen) -{ - int32 numfiles, i, j; - uint8 *cptr; - uint32 offs, uncomp, bsize, cofs, uofs; - uint32 X; - uLongf dlength; - int uerr; - char matchname[512], *remainder; - - // strip out to only the directory name - i = 0; - while ((file[i] != '/') && (file[i] != '\\') && (file[i] != '\0')) - { - matchname[i] = file[i]; - i++; - } - matchname[i] = '\0'; - remainder = &file[i+1]; - - cptr = start + 4; - - numfiles = start[0] | start[1]<<8 | start[2]<<16 | start[3]<<24; - - for (i = 0; i < numfiles; i++) - { - offs = cptr[36] | cptr[37]<<8 | cptr[38]<<16 | cptr[39]<<24; - uncomp = cptr[40] | cptr[41]<<8 | cptr[42]<<16 | cptr[43]<<24; - bsize = cptr[44] | cptr[45]<<8 | cptr[46]<<16 | cptr[47]<<24; - - #if DEBUG_LOADER - printf("[%s vs %s]: ofs %08x uncomp %08x bsize %08x\n", cptr, matchname, offs, uncomp, bsize); - #endif - - if (!strcasecmp((char *)cptr, matchname)) - { - if ((uncomp == 0) && (bsize == 0)) - { - #if DEBUG_LOADER - printf("Drilling into subdirectory [%s] with [%s] at offset %x\n", matchname, remainder, offs); - #endif - return load_file_ex(top, &top[offs], len-offs, remainder, buf, buflen); - } - - X = (uncomp + bsize - 1) / bsize; - - cofs = offs + (X*4); - uofs = 0; - for (j = 0; j < X; j++) - { - uint32 usize; - - usize = top[offs+(j*4)] | top[offs+1+(j*4)]<<8 | top[offs+2+(j*4)]<<16 | top[offs+3+(j*4)]<<24; - - dlength = buflen - uofs; - - uerr = uncompress(&buf[uofs], &dlength, &top[cofs], usize); - if (uerr != Z_OK) - { - printf("Decompress fail: %x %d!\n", dlength, uerr); - return 0xffffffff; - } - - cofs += usize; - uofs += dlength; - } - - return uncomp; - } - else - { - cptr += 48; - } - } - - return 0xffffffff; -} - -static uint32 load_file(int fs, char *file, uint8 *buf, uint32 buflen) -{ - return load_file_ex(filesys[fs], filesys[fs], fssize[fs], file, buf, buflen); -} - -#if 0 -static dump_files(int fs, uint8 *buf, uint32 buflen) -{ - int32 numfiles, i, j; - uint8 *cptr; - uint32 offs, uncomp, bsize, cofs, uofs; - uint32 X; - uLongf dlength; - int uerr; - uint8 *start; - uint32 len; - FILE *f; - char tfn[128]; - - printf("Dumping FS %d\n", fs); - - start = filesys[fs]; - len = fssize[fs]; - - cptr = start + 4; - - numfiles = start[0] | start[1]<<8 | start[2]<<16 | start[3]<<24; - - for (i = 0; i < numfiles; i++) - { - offs = cptr[36] | cptr[37]<<8 | cptr[38]<<16 | cptr[39]<<24; - uncomp = cptr[40] | cptr[41]<<8 | cptr[42]<<16 | cptr[43]<<24; - bsize = cptr[44] | cptr[45]<<8 | cptr[46]<<16 | cptr[47]<<24; - - if (bsize > 0) - { - X = (uncomp + bsize - 1) / bsize; - - printf("[dump %s]: ofs %08x uncomp %08x bsize %08x\n", cptr, offs, uncomp, bsize); - - cofs = offs + (X*4); - uofs = 0; - for (j = 0; j < X; j++) - { - uint32 usize; - - usize = start[offs+(j*4)] | start[offs+1+(j*4)]<<8 | start[offs+2+(j*4)]<<16 | start[offs+3+(j*4)]<<24; - - dlength = buflen - uofs; - - uerr = uncompress(&buf[uofs], &dlength, &start[cofs], usize); - if (uerr != Z_OK) - { - printf("Decompress fail: %x %d!\n", dlength, uerr); - return 0xffffffff; - } - - cofs += usize; - uofs += dlength; - } - - sprintf(tfn, "iopfiles/%s", cptr); - f = fopen(tfn, "wb"); - fwrite(buf, uncomp, 1, f); - fclose(f); - } - else - { - printf("[subdir %s]: ofs %08x uncomp %08x bsize %08x\n", cptr, offs, uncomp, bsize); - } - - cptr += 48; - } - - return 0xffffffff; -} -#endif - -// find a file on our filesystems -uint32 psf2_load_file(char *file, uint8 *buf, uint32 buflen) -{ - int i; - uint32 flen; - - for (i = 0; i < num_fs; i++) - { - flen = load_file(i, file, buf, buflen); - if (flen != 0xffffffff) - { - return flen; - } - } - - return 0xffffffff; -} - -int32 psf2_start(uint8 *buffer, uint32 length) -{ - uint8 *file, *lib_decoded; - uint32 irx_len; - uint64 file_len, lib_raw_length, lib_len; - uint8 *buf; - union cpuinfo mipsinfo; - corlett_t *lib; - - loadAddr = 0x23f00; // this value makes allocations work out similarly to how they would - // in Highly Experimental (as per Shadow Hearts' hard-coded assumptions) - - // clear IOP work RAM before we start scribbling in it - memset(psx_ram, 0, 2*1024*1024); - - // Decode the current PSF2 - if (corlett_decode(buffer, length, &file, &file_len, &c) != AO_SUCCESS) - { - return AO_FAIL; - } - - if (file_len > 0) printf("ERROR: PSF2 can't have a program section! ps %08x\n", file_len); - - #if DEBUG_LOADER - printf("FS section: size %x\n", c->res_size); - #endif - - num_fs = 1; - filesys[0] = (uint8 *)c->res_section; - fssize[0] = c->res_size; - - // Get the library file, if any - if (c->lib[0] != 0) - { - uint64 tmp_length; - - #if DEBUG_LOADER - printf("Loading library: %s\n", c->lib); - #endif - if (ao_get_lib(c->lib, &lib_raw_file, &tmp_length) != AO_SUCCESS) - { - return AO_FAIL; - } - lib_raw_length = tmp_length; - - if (corlett_decode(lib_raw_file, lib_raw_length, &lib_decoded, &lib_len, &lib) != AO_SUCCESS) - { - free(lib_raw_file); - return AO_FAIL; - } - - free(lib_raw_file); - - #if DEBUG_LOADER - printf("Lib FS section: size %x bytes\n", lib->res_size); - #endif - - num_fs++; - filesys[1] = (uint8 *)lib->res_section; - fssize[1] = lib->res_size; - } - - // dump all files - #if 0 - buf = (uint8 *)malloc(16*1024*1024); - dump_files(0, buf, 16*1024*1024); - if (c->lib[0] != 0) - dump_files(1, buf, 16*1024*1024); - free(buf); - #endif - - // load psf2.irx, which kicks everything off - buf = (uint8 *)malloc(512*1024); - irx_len = psf2_load_file("psf2.irx", buf, 512*1024); - - if (irx_len != 0xffffffff) - { - initialPC = psf2_load_elf(buf, irx_len); - initialSP = 0x801ffff0; - } - free(buf); - - if (initialPC == 0xffffffff) - { - return AO_FAIL; - } - - lengthMS = psfTimeToMS(c->inf_length); - fadeMS = psfTimeToMS(c->inf_fade); - if (lengthMS == 0) - { - lengthMS = ~0; - } - setlength2(lengthMS, fadeMS); - - mips_init(); - mips_reset(NULL); - - mipsinfo.i = initialPC; - mips_set_info(CPUINFO_INT_PC, &mipsinfo); - - mipsinfo.i = initialSP; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R29, &mipsinfo); - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R30, &mipsinfo); - - // set RA - mipsinfo.i = 0x80000000; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R31, &mipsinfo); - - // set A0 & A1 to point to "aofile:/" - mipsinfo.i = 2; // argc - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R4, &mipsinfo); - - mipsinfo.i = 0x80000004; // argv - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R5, &mipsinfo); - psx_ram[1] = LE32(0x80000008); - - buf = (uint8 *)&psx_ram[2]; - strcpy((char *)buf, "aofile:/"); - - psx_ram[0] = LE32(FUNCT_HLECALL); - - // back up initial RAM image to quickly restart songs - memcpy(initial_ram, psx_ram, 2*1024*1024); - - psx_hw_init(); - SPU2init(); - SPU2open(NULL); - - return AO_SUCCESS; -} - -void ps2_update(unsigned char *pSound, long lBytes) -{ - memcpy(spu_pOutput, pSound, lBytes); // (for direct 44.1kHz output) -} - -int32 psf2_gen(int16 *buffer, uint32 samples) -{ - int i; - - spu_pOutput = (char *)buffer; - - for (i = 0; i < samples; i++) - { - SPU2async(1); - ps2_hw_slice(); - } - - ps2_hw_frame(); - - return AO_SUCCESS; -} - -int32 psf2_stop(void) -{ - SPU2close(); - if (c->lib[0] != 0) - { - free(lib_raw_file); - } - free(c); - - return AO_SUCCESS; -} - -int32 psf2_command(int32 command, int32 parameter) -{ - union cpuinfo mipsinfo; - uint32 lengthMS, fadeMS; - - switch (command) - { - case COMMAND_RESTART: - SPU2close(); - - memcpy(psx_ram, initial_ram, 2*1024*1024); - - mips_init(); - mips_reset(NULL); - psx_hw_init(); - SPU2init(); - SPU2open(NULL); - - mipsinfo.i = initialPC; - mips_set_info(CPUINFO_INT_PC, &mipsinfo); - - mipsinfo.i = initialSP; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R29, &mipsinfo); - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R30, &mipsinfo); - - // set RA - mipsinfo.i = 0x80000000; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R31, &mipsinfo); - - // set A0 & A1 to point to "aofile:/" - mipsinfo.i = 2; // argc - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R4, &mipsinfo); - - mipsinfo.i = 0x80000004; // argv - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R5, &mipsinfo); - - psx_hw_init(); - - lengthMS = psfTimeToMS(c->inf_length); - fadeMS = psfTimeToMS(c->inf_fade); - if (lengthMS == 0) - { - lengthMS = ~0; - } - setlength2(lengthMS, fadeMS); - - return AO_SUCCESS; - - } - return AO_FAIL; -} - -int32 psf2_fill_info(ao_display_info *info) -{ - if (c == NULL) - return AO_FAIL; - - strcpy(info->title[1], "Name: "); - sprintf(info->info[1], "%s", c->inf_title); - - strcpy(info->title[2], "Game: "); - sprintf(info->info[2], "%s", c->inf_game); - - strcpy(info->title[3], "Artist: "); - sprintf(info->info[3], "%s", c->inf_artist); - - strcpy(info->title[4], "Copyright: "); - sprintf(info->info[4], "%s", c->inf_copy); - - strcpy(info->title[5], "Year: "); - sprintf(info->info[5], "%s", c->inf_year); - - strcpy(info->title[6], "Length: "); - sprintf(info->info[6], "%s", c->inf_length); - - strcpy(info->title[7], "Fade: "); - sprintf(info->info[7], "%s", c->inf_fade); - - strcpy(info->title[8], "Ripper: "); - sprintf(info->info[8], "%s", psfby); - - return AO_SUCCESS; -} - -uint32 psf2_get_loadaddr(void) -{ - return loadAddr; -} - -void psf2_set_loadaddr(uint32 new) -{ - loadAddr = new; -} diff --git a/Frameworks/AudioOverload/aosdk/eng_psf/eng_spu.c b/Frameworks/AudioOverload/aosdk/eng_psf/eng_spu.c deleted file mode 100644 index 8bbda8799..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_psf/eng_spu.c +++ /dev/null @@ -1,319 +0,0 @@ -/* - Audio Overload SDK - SPU file format engine - - Copyright (c) 2007 R. Belmont and Richard Bannister. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - * Neither the names of R. Belmont and Richard Bannister nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -// -// eng_spu.c -// -// Note: support for old-format files is not tested and may not work. All the rips I could find -// are in the newer format. Also, CDDA and XA commands do not work - I've not found a rip using them. -// - -#include -#include -#include - -#include "ao.h" -#include "eng_protos.h" -#include "cpuintrf.h" -#include "psx.h" - -extern int SPUinit(void); -extern int SPUopen(void); -extern int SPUclose(void); -extern void SPUinjectRAMImage(unsigned short *source); - -static uint8 *start_of_file, *song_ptr; -static uint32 cur_tick, cur_event, num_events, next_tick, end_tick; -static int old_fmt; -static char name[128], song[128], company[128]; - -int32 spu_start(uint8 *buffer, uint32 length) -{ - int i; - uint16 reg; - - if (strncmp((char *)buffer, "SPU", 3)) - { - return AO_FAIL; - } - - start_of_file = buffer; - - SPUinit(); - SPUopen(); - setlength(~0, 0); - - // upload the SPU RAM image - SPUinjectRAMImage((unsigned short *)&buffer[0]); - - // apply the register image - for (i = 0; i < 512; i += 2) - { - reg = buffer[0x80000+i] | buffer[0x80000+i+1]<<8; - - SPUwriteRegister((i/2)+0x1f801c00, reg); - } - - old_fmt = 1; - - if ((buffer[0x80200] != 0x44) || (buffer[0x80201] != 0xac) || (buffer[0x80202] != 0x00) || (buffer[0x80203] != 0x00)) - { - old_fmt = 0; - } - - if (old_fmt) - { - num_events = buffer[0x80204] | buffer[0x80205]<<8 | buffer[0x80206]<<16 | buffer[0x80207]<<24; - - if (((num_events * 12) + 0x80208) > length) - { - old_fmt = 0; - } - else - { - cur_tick = 0; - } - } - - if (!old_fmt) - { - end_tick = buffer[0x80200] | buffer[0x80201]<<8 | buffer[0x80202]<<16 | buffer[0x80203]<<24; - cur_tick = buffer[0x80204] | buffer[0x80205]<<8 | buffer[0x80206]<<16 | buffer[0x80207]<<24; - next_tick = cur_tick; - } - - song_ptr = &buffer[0x80208]; - cur_event = 0; - - strncpy((char *)&buffer[4], name, 128); - strncpy((char *)&buffer[0x44], song, 128); - strncpy((char *)&buffer[0x84], company, 128); - - return AO_SUCCESS; -} - -extern int SPUasync(uint32 cycles); -extern void SPU_flushboot(void); - -extern char *spu_pOutput; // this is a bit lame, but we'll deal - -static void spu_tick(void) -{ - uint32 time, reg, size; - uint16 rdata; - uint8 opcode; - - if (old_fmt) - { - time = song_ptr[0] | song_ptr[1]<<8 | song_ptr[2]<<16 | song_ptr[3]<<24; - - while ((time == cur_tick) && (cur_event < num_events)) - { - reg = song_ptr[4] | song_ptr[5]<<8 | song_ptr[6]<<16 | song_ptr[7]<<24; - rdata = song_ptr[8] | song_ptr[9]<<8; - - SPUwriteRegister(reg, rdata); - - cur_event++; - song_ptr += 12; - - time = song_ptr[0] | song_ptr[1]<<8 | song_ptr[2]<<16 | song_ptr[3]<<24; - } - } - else - { - if (cur_tick < end_tick) - { - while (cur_tick == next_tick) - { - opcode = song_ptr[0]; - song_ptr++; - - switch (opcode) - { - case 0: // write register - reg = song_ptr[0] | song_ptr[1]<<8 | song_ptr[2]<<16 | song_ptr[3]<<24; - rdata = song_ptr[4] | song_ptr[5]<<8; - - SPUwriteRegister(reg, rdata); - - next_tick = song_ptr[6] | song_ptr[7]<<8 | song_ptr[8]<<16 | song_ptr[9]<<24; - song_ptr += 10; - break; - - case 1: // read register - reg = song_ptr[0] | song_ptr[1]<<8 | song_ptr[2]<<16 | song_ptr[3]<<24; - SPUreadRegister(reg); - next_tick = song_ptr[4] | song_ptr[5]<<8 | song_ptr[6]<<16 | song_ptr[7]<<24; - song_ptr += 8; - break; - - case 2: // dma write - size = song_ptr[0] | song_ptr[1]<<8 | song_ptr[2]<<16 | song_ptr[3]<<24; - song_ptr += (4 + size); - next_tick = song_ptr[0] | song_ptr[1]<<8 | song_ptr[2]<<16 | song_ptr[3]<<24; - song_ptr += 4; - break; - - case 3: // dma read - next_tick = song_ptr[4] | song_ptr[5]<<8 | song_ptr[6]<<16 | song_ptr[7]<<24; - song_ptr += 8; - break; - - case 4: // xa play - song_ptr += (32 + 16384); - next_tick = song_ptr[0] | song_ptr[1]<<8 | song_ptr[2]<<16 | song_ptr[3]<<24; - song_ptr += 4; - break; - - case 5: // cdda play - size = song_ptr[0] | song_ptr[1]<<8 | song_ptr[2]<<16 | song_ptr[3]<<24; - song_ptr += (4 + size); - next_tick = song_ptr[0] | song_ptr[1]<<8 | song_ptr[2]<<16 | song_ptr[3]<<24; - song_ptr += 4; - break; - - default: - printf("Unknown opcode %d\n", opcode); - exit(-1); - break; - } - } - } - else - { -// ao_song_done = 1; - } - } - - cur_tick++; -} - -int32 spu_gen(int16 *buffer, uint32 samples) -{ - int i, run = 1; - - if (old_fmt) - { - if (cur_event >= num_events) - { - run = 0; - } - } - else - { - if (cur_tick >= end_tick) - { - run = 0; - } - } - - if (run) - { - for (i = 0; i < samples; i++) - { - spu_tick(); - SPUasync(384); - } - - spu_pOutput = (char *)buffer; - SPU_flushboot(); - } - else - { - memset(buffer, 0, samples*2*sizeof(int16)); - } - - return AO_SUCCESS; -} - -int32 spu_stop(void) -{ - return AO_SUCCESS; -} - -int32 spu_command(int32 command, int32 parameter) -{ - switch (command) - { - case COMMAND_GET_MIN: - case COMMAND_GET_MAX: - { - return 0; - } - break; - - case COMMAND_HAS_PREV: - case COMMAND_HAS_NEXT: - case COMMAND_PREV: - case COMMAND_NEXT: - case COMMAND_JUMP: - { - return AO_FAIL; - } - break; - - case COMMAND_RESTART: - { - song_ptr = &start_of_file[0x80200]; - - if (old_fmt) - { - num_events = song_ptr[4] | song_ptr[5]<<8 | song_ptr[6]<<16 | song_ptr[7]<<24; - } - else - { - end_tick = song_ptr[0] | song_ptr[1]<<8 | song_ptr[2]<<16 | song_ptr[3]<<24; - cur_tick = song_ptr[4] | song_ptr[5]<<8 | song_ptr[6]<<16 | song_ptr[7]<<24; - } - - song_ptr += 8; - cur_event = 0; - return AO_SUCCESS; - } - break; - -#if VERBOSE - default: - printf("Unknown command executed!\n"); - break; -#endif - } - - return AO_FAIL; -} - -int32 spu_fill_info(ao_display_info *info) -{ - strcpy(info->title[1], "Game: "); - sprintf(info->info[1], "%.128s", name); - strcpy(info->title[2], "Song: "); - sprintf(info->info[2], "%.128s", song); - strcpy(info->title[3], "Company: "); - sprintf(info->info[3], "%.128s", company); - - return AO_SUCCESS; -} diff --git a/Frameworks/AudioOverload/aosdk/eng_psf/mamemem.h b/Frameworks/AudioOverload/aosdk/eng_psf/mamemem.h deleted file mode 100644 index a28deca82..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_psf/mamemem.h +++ /dev/null @@ -1,662 +0,0 @@ -#ifndef _MEMORY_H -#define _MEMORY_H - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __GNU__ -#define UNUSEDARG __attribute__((__unused__)) -#else -#define UNUSEDARG -#endif - -#define MAX_BANKS 20 - - -/* obsolete, to be removed */ -#define READ_WORD(a) (*(UINT16 *)(a)) -#define WRITE_WORD(a,d) (*(UINT16 *)(a) = (d)) -#define COMBINE_WORD(w,d) (((w) & ((d) >> 16)) | ((d) & 0xffff)) -#define COMBINE_WORD_MEM(a,d) (WRITE_WORD((a), (READ_WORD(a) & ((d) >> 16)) | (d))) - -#define ASSERT_LINE (1) -#define CLEAR_LINE (0) -#define TIME_NEVER (0) - -#define TIME_IN_HZ(hz) (1.0 / (double)(hz)) -#define TIME_IN_MSEC(ms) ((double)(ms) * (1.0 / 1000.0)) -#define TIME_IN_USEC(us) ((double)(us) * (1.0 / 1000000.0)) - -/*************************************************************************** - -Note that the memory hooks are not passed the actual memory address where -the operation takes place, but the offset from the beginning of the block -they are assigned to. This makes handling of mirror addresses easier, and -makes the handlers a bit more "object oriented". If you handler needs to -read/write the main memory area, provide a "base" pointer: it will be -initialized by the main engine to point to the beginning of the memory block -assigned to the handler. You may also provided a pointer to "size": it -will be set to the length of the memory area processed by the handler. - -***************************************************************************/ - -#define MEMORY_WIDTH_MASK 0x00000003 -#define MEMORY_WIDTH_8 0x00000001 -#define MEMORY_WIDTH_16 0x00000002 -#define MEMORY_WIDTH_32 0x00000003 - -#define MEMORY_TYPE_MASK 0x30000000 -#define MEMORY_TYPE_MEM 0x10000000 -#define MEMORY_TYPE_IO 0x20000000 - -#define MEMORY_DIRECTION_MASK 0xc0000000 -#define MEMORY_DIRECTION_READ 0x40000000 -#define MEMORY_DIRECTION_WRITE 0x80000000 - -typedef unsigned int offs_t; -typedef offs_t (*opbase_handler)(UNUSEDARG offs_t address); - -/*************************************************************************** - 8-BIT Core memory read/write/opbase handler types -***************************************************************************/ - -typedef unsigned char data8_t; -typedef unsigned short data16_t; - -typedef data8_t (*mem_read_handler)(UNUSEDARG offs_t offset); -typedef void (*mem_write_handler)(UNUSEDARG offs_t offset, UNUSEDARG data8_t data); - -#define READ_HANDLER(name) data8_t name(UNUSEDARG offs_t offset) -#define WRITE_HANDLER(name) void name(UNUSEDARG offs_t offset, UNUSEDARG data8_t data) -#define OPBASE_HANDLER(name) offs_t name(UNUSEDARG offs_t address) - -#define READ16_HANDLER(name) data16_t name(UNUSEDARG offs_t offset, UNUSEDARG UINT32 mem_mask) -#define WRITE16_HANDLER(name) void name(UNUSEDARG offs_t offset, UNUSEDARG data16_t data, UNUSEDARG UINT32 mem_mask) -#define OPBASE16_HANDLER(name) offs_t name(UNUSEDARG offs_t address) - -#define MRA_NOP 0 /* don't care, return 0 */ -#define MWA_NOP 0 /* do nothing */ -#define MRA_RAM ((mem_read_handler)-1) /* plain RAM location (return its contents) */ -#define MWA_RAM ((mem_write_handler)-1) /* plain RAM location (store the value) */ -#define MRA_ROM ((mem_read_handler)-2) /* plain ROM location (return its contents) */ -#define MWA_ROM ((mem_write_handler)-2) /* plain ROM location (do nothing) */ -/************************************************************************** - * If the CPU opcodes are encrypted, they are fetched from a different - * memory space. In such a case, if the program dynamically creates code - * in RAM and executes it, it won't work unless you use MWA_RAMROM - * to affect both memory spaces. - **************************************************************************/ -#define MWA_RAMROM ((mem_write_handler)-3) - -/* bank memory */ -#define MRA_BANK1 ((mem_read_handler)-10) -#define MWA_BANK1 ((mem_write_handler)-10) -#define MRA_BANK2 ((mem_read_handler)-11) -#define MWA_BANK2 ((mem_write_handler)-11) -#define MRA_BANK3 ((mem_read_handler)-12) -#define MWA_BANK3 ((mem_write_handler)-12) -#define MRA_BANK4 ((mem_read_handler)-13) -#define MWA_BANK4 ((mem_write_handler)-13) -#define MRA_BANK5 ((mem_read_handler)-14) -#define MWA_BANK5 ((mem_write_handler)-14) -#define MRA_BANK6 ((mem_read_handler)-15) -#define MWA_BANK6 ((mem_write_handler)-15) -#define MRA_BANK7 ((mem_read_handler)-16) -#define MWA_BANK7 ((mem_write_handler)-16) -#define MRA_BANK8 ((mem_read_handler)-17) -#define MWA_BANK8 ((mem_write_handler)-17) -#define MRA_BANK9 ((mem_read_handler)-18) -#define MWA_BANK9 ((mem_write_handler)-18) -#define MRA_BANK10 ((mem_read_handler)-19) -#define MWA_BANK10 ((mem_write_handler)-19) -#define MRA_BANK11 ((mem_read_handler)-20) -#define MWA_BANK11 ((mem_write_handler)-20) -#define MRA_BANK12 ((mem_read_handler)-21) -#define MWA_BANK12 ((mem_write_handler)-21) -#define MRA_BANK13 ((mem_read_handler)-22) -#define MWA_BANK13 ((mem_write_handler)-22) -#define MRA_BANK14 ((mem_read_handler)-23) -#define MWA_BANK14 ((mem_write_handler)-23) -#define MRA_BANK15 ((mem_read_handler)-24) -#define MWA_BANK15 ((mem_write_handler)-24) -#define MRA_BANK16 ((mem_read_handler)-25) -#define MWA_BANK16 ((mem_write_handler)-25) -#define MRA_BANK17 ((mem_read_handler)-26) -#define MWA_BANK17 ((mem_write_handler)-26) -#define MRA_BANK18 ((mem_read_handler)-27) -#define MWA_BANK18 ((mem_write_handler)-27) -#define MRA_BANK19 ((mem_read_handler)-28) -#define MWA_BANK19 ((mem_write_handler)-28) -#define MRA_BANK20 ((mem_read_handler)-29) -#define MWA_BANK20 ((mem_write_handler)-29) - -struct Memory_ReadAddress -{ - offs_t start, end; - mem_read_handler handler; /* see special values above */ -}; - -struct Memory_WriteAddress -{ - offs_t start, end; - mem_write_handler handler; /* see special values above */ - data8_t **base; /* optional (see explanation above) */ - size_t *size; /* optional (see explanation above) */ -}; - -#define MEMORY_MARKER ((offs_t)~0) - -#define MEMORY_END { MEMORY_MARKER, 0 } }; - -#define IS_MEMORY_MARKER( ma ) ((ma)->start == MEMORY_MARKER && (ma)->end < MEMORY_MARKER) -#define IS_MEMORY_END( ma ) ((ma)->start == MEMORY_MARKER && (ma)->end == 0) - -#define MEMORY_READ_START(name) const struct Memory_ReadAddress name[] = { \ - { MEMORY_MARKER, MEMORY_DIRECTION_READ | MEMORY_TYPE_MEM | MEMORY_WIDTH_8 }, -#define MEMORY_WRITE_START(name) const struct Memory_WriteAddress name[] = { \ - { MEMORY_MARKER, MEMORY_DIRECTION_WRITE | MEMORY_TYPE_MEM | MEMORY_WIDTH_8 }, - -/*************************************************************************** - 16-BIT Core memory read/write/opbase handler types -***************************************************************************/ - -typedef data16_t (*mem_read16_handler)(UNUSEDARG offs_t offset); -typedef void (*mem_write16_handler)(UNUSEDARG offs_t offset, UNUSEDARG data16_t data, UNUSEDARG UINT32 mem_mask); - -#define READ16_HANDLER(name) data16_t name(UNUSEDARG offs_t offset, UNUSEDARG UINT32 mem_mask) -#define WRITE16_HANDLER(name) void name(UNUSEDARG offs_t offset, UNUSEDARG data16_t data, UNUSEDARG UINT32 mem_mask) -#define OPBASE16_HANDLER(name) offs_t name(UNUSEDARG offs_t address) - -#define MRA16_NOP 0 /* don't care, return 0 */ -#define MWA16_NOP 0 /* do nothing */ -#define MRA16_RAM ((mem_read16_handler)-1) /* plain RAM location (return its contents) */ -#define MWA16_RAM ((mem_write16_handler)-1) /* plqain RAM location (store the value) */ -#define MRA16_ROM ((mem_read16_handler)-2) /* plain ROM location (return its contents) */ -#define MWA16_ROM ((mem_write16_handler)-2) /* plain ROM location (do nothing) */ -/************************************************************************** - * If the CPU opcodes are encrypted, they are fetched from a different - * memory space. In such a case, if the program dynamically creates code - * in RAM and executes it, it won't work unless you use MWA_RAMROM - * to affect both memory spaces. - **************************************************************************/ -#define MWA16_RAMROM ((mem_write16_handler)-3) - -/* bank memory */ -#define MRA16_BANK1 ((mem_read16_handler)-10) -#define MWA16_BANK1 ((mem_write16_handler)-10) -#define MRA16_BANK2 ((mem_read16_handler)-11) -#define MWA16_BANK2 ((mem_write16_handler)-11) -#define MRA16_BANK3 ((mem_read16_handler)-12) -#define MWA16_BANK3 ((mem_write16_handler)-12) -#define MRA16_BANK4 ((mem_read16_handler)-13) -#define MWA16_BANK4 ((mem_write16_handler)-13) -#define MRA16_BANK5 ((mem_read16_handler)-14) -#define MWA16_BANK5 ((mem_write16_handler)-14) -#define MRA16_BANK6 ((mem_read16_handler)-15) -#define MWA16_BANK6 ((mem_write16_handler)-15) -#define MRA16_BANK7 ((mem_read16_handler)-16) -#define MWA16_BANK7 ((mem_write16_handler)-16) -#define MRA16_BANK8 ((mem_read16_handler)-17) -#define MWA16_BANK8 ((mem_write16_handler)-17) -#define MRA16_BANK9 ((mem_read16_handler)-18) -#define MWA16_BANK9 ((mem_write16_handler)-18) -#define MRA16_BANK10 ((mem_read16_handler)-19) -#define MWA16_BANK10 ((mem_write16_handler)-19) -#define MRA16_BANK11 ((mem_read16_handler)-20) -#define MWA16_BANK11 ((mem_write16_handler)-20) -#define MRA16_BANK12 ((mem_read16_handler)-21) -#define MWA16_BANK12 ((mem_write16_handler)-21) -#define MRA16_BANK13 ((mem_read16_handler)-22) -#define MWA16_BANK13 ((mem_write16_handler)-22) -#define MRA16_BANK14 ((mem_read16_handler)-23) -#define MWA16_BANK14 ((mem_write16_handler)-23) -#define MRA16_BANK15 ((mem_read16_handler)-24) -#define MWA16_BANK15 ((mem_write16_handler)-24) -#define MRA16_BANK16 ((mem_read16_handler)-25) -#define MWA16_BANK16 ((mem_write16_handler)-25) -#define MRA16_BANK17 ((mem_read16_handler)-26) -#define MWA16_BANK17 ((mem_write16_handler)-26) -#define MRA16_BANK18 ((mem_read16_handler)-27) -#define MWA16_BANK18 ((mem_write16_handler)-27) -#define MRA16_BANK19 ((mem_read16_handler)-28) -#define MWA16_BANK19 ((mem_write16_handler)-28) -#define MRA16_BANK20 ((mem_read16_handler)-29) -#define MWA16_BANK20 ((mem_write16_handler)-29) - -struct Memory_ReadAddress16 -{ - offs_t start, end; - mem_read16_handler handler; /* see special values above */ -}; - -struct Memory_WriteAddress16 -{ - offs_t start, end; - mem_write16_handler handler; /* see special values above */ - data16_t **base; /* optional (see explanation above) */ - size_t *size; /* optional (see explanation above) */ -}; - -#define MEMORY_READ16_START(name) const struct Memory_ReadAddress16 name[] = { \ - { MEMORY_MARKER, MEMORY_DIRECTION_READ | MEMORY_TYPE_MEM | MEMORY_WIDTH_16 }, -#define MEMORY_WRITE16_START(name) const struct Memory_WriteAddress16 name[] = { \ - { MEMORY_MARKER, MEMORY_DIRECTION_WRITE | MEMORY_TYPE_MEM | MEMORY_WIDTH_16 }, - -/*************************************************************************** - 32-BIT Core memory read/write/opbase handler types -***************************************************************************/ - -typedef UINT32 data32_t; - -typedef data32_t (*mem_read32_handler)(UNUSEDARG offs_t offset); -typedef void (*mem_write32_handler)(UNUSEDARG offs_t offset, UNUSEDARG data32_t data, UNUSEDARG UINT32 mem_mask); - -#define READ32_HANDLER(name) data32_t name(UNUSEDARG offs_t offset, UNUSEDARG UINT32 mem_mask) -#define WRITE32_HANDLER(name) void name(UNUSEDARG offs_t offset, UNUSEDARG data32_t data, UNUSEDARG UINT32 mem_mask) -#define OPBASE32_HANDLER(name) offs_t name(UNUSEDARG offs_t address) - -#define MRA32_NOP 0 /* don't care, return 0 */ -#define MWA32_NOP 0 /* do nothing */ -#define MRA32_RAM ((mem_read32_handler)-1) /* plain RAM location (return its contents) */ -#define MWA32_RAM ((mem_write32_handler)-1) /* plain RAM location (store the value) */ -#define MRA32_ROM ((mem_read32_handler)-2) /* plain ROM location (return its contents) */ -#define MWA32_ROM ((mem_write32_handler)-2) /* plain ROM location (do nothing) */ -/************************************************************************** - * If the CPU opcodes are encrypted, they are fetched from a different - * memory space. In such a case, if the program dynamically creates code - * in RAM and executes it, it won't work unless you use MWA_RAMROM - * to affect both memory spaces. - **************************************************************************/ -#define MWA32_RAMROM ((mem_write32_handler)-3) - -/* bank memory */ -#define MRA32_BANK1 ((mem_read32_handler)-10) -#define MWA32_BANK1 ((mem_write32_handler)-10) -#define MRA32_BANK2 ((mem_read32_handler)-11) -#define MWA32_BANK2 ((mem_write32_handler)-11) -#define MRA32_BANK3 ((mem_read32_handler)-12) -#define MWA32_BANK3 ((mem_write32_handler)-12) -#define MRA32_BANK4 ((mem_read32_handler)-13) -#define MWA32_BANK4 ((mem_write32_handler)-13) -#define MRA32_BANK5 ((mem_read32_handler)-14) -#define MWA32_BANK5 ((mem_write32_handler)-14) -#define MRA32_BANK6 ((mem_read32_handler)-15) -#define MWA32_BANK6 ((mem_write32_handler)-15) -#define MRA32_BANK7 ((mem_read32_handler)-16) -#define MWA32_BANK7 ((mem_write32_handler)-16) -#define MRA32_BANK8 ((mem_read32_handler)-17) -#define MWA32_BANK8 ((mem_write32_handler)-17) -#define MRA32_BANK9 ((mem_read32_handler)-18) -#define MWA32_BANK9 ((mem_write32_handler)-18) -#define MRA32_BANK10 ((mem_read32_handler)-19) -#define MWA32_BANK10 ((mem_write32_handler)-19) -#define MRA32_BANK11 ((mem_read32_handler)-20) -#define MWA32_BANK11 ((mem_write32_handler)-20) -#define MRA32_BANK12 ((mem_read32_handler)-21) -#define MWA32_BANK12 ((mem_write32_handler)-21) -#define MRA32_BANK13 ((mem_read32_handler)-22) -#define MWA32_BANK13 ((mem_write32_handler)-22) -#define MRA32_BANK14 ((mem_read32_handler)-23) -#define MWA32_BANK14 ((mem_write32_handler)-23) -#define MRA32_BANK15 ((mem_read32_handler)-24) -#define MWA32_BANK15 ((mem_write32_handler)-24) -#define MRA32_BANK32 ((mem_read32_handler)-25) -#define MWA32_BANK32 ((mem_write32_handler)-25) -#define MRA32_BANK17 ((mem_read32_handler)-26) -#define MWA32_BANK17 ((mem_write32_handler)-26) -#define MRA32_BANK18 ((mem_read32_handler)-27) -#define MWA32_BANK18 ((mem_write32_handler)-27) -#define MRA32_BANK19 ((mem_read32_handler)-28) -#define MWA32_BANK19 ((mem_write32_handler)-28) -#define MRA32_BANK20 ((mem_read32_handler)-29) -#define MWA32_BANK20 ((mem_write32_handler)-29) - -struct Memory_ReadAddress32 -{ - offs_t start, end; - mem_read32_handler handler; /* see special values above */ -}; - -struct Memory_WriteAddress32 -{ - offs_t start, end; - mem_write32_handler handler; /* see special values above */ - data32_t **base; /* optional (see explanation above) */ - size_t *size; /* optional (see explanation above) */ -}; - -#define MEMORY_READ32_START(name) const struct Memory_ReadAddress32 name[] = { \ - { MEMORY_MARKER, MEMORY_DIRECTION_READ | MEMORY_TYPE_MEM | MEMORY_WIDTH_32 }, -#define MEMORY_WRITE32_START(name) const struct Memory_WriteAddress32 name[] = { \ - { MEMORY_MARKER, MEMORY_DIRECTION_WRITE | MEMORY_TYPE_MEM | MEMORY_WIDTH_32 }, - -/*************************************************************************** - -IN and OUT ports are handled like memory accesses, the hook template is the -same so you can interchange them. Of course there is no 'base' pointer for -IO ports. - -***************************************************************************/ - -struct IO_ReadPort -{ - offs_t start,end; - mem_read_handler handler; /* see special values below */ -}; - -#define IORP_NOP 0 /* don't care, return 0 */ - - -struct IO_WritePort -{ - offs_t start,end; - mem_write_handler handler; /* see special values below */ -}; - -#define IOWP_NOP 0 /* do nothing */ - -#define PORT_READ_START(name) const struct IO_ReadPort name[] = { \ - { MEMORY_MARKER, MEMORY_DIRECTION_READ | MEMORY_TYPE_IO | MEMORY_WIDTH_8 }, -#define PORT_WRITE_START(name) const struct IO_WritePort name[] = { \ - { MEMORY_MARKER, MEMORY_DIRECTION_WRITE | MEMORY_TYPE_IO | MEMORY_WIDTH_8 }, -#define PORT_END MEMORY_END - -/*************************************************************************** - -If a memory region contains areas that are outside of the ROM region for -an address space, the memory system will allocate an array of structures -to track the external areas. - -***************************************************************************/ - -#define MAX_EXT_MEMORY 64 - -struct ExtMemory -{ - offs_t start,end,region; - UINT8 *data; -}; - -extern struct ExtMemory ext_memory[MAX_EXT_MEMORY]; - - - -/*************************************************************************** - -For a given number of address bits, we need to determine how many elements -there are in the first and second-order lookup tables. We also need to know -how many low-order bits to ignore. The ABITS* values represent these -constants for each address space type we support. - -***************************************************************************/ - -/* memory element block size */ -#define MH_SBITS 8 /* sub element bank size */ -#define MH_PBITS 8 /* port current element size */ -#define MH_ELEMAX 64 /* sub elements limit */ -#define MH_HARDMAX 64 /* hardware functions limit */ - -/* 16 bits address */ -#define ABITS1_16 12 -#define ABITS2_16 4 -#define ABITS_MIN_16 0 /* minimum memory block is 1 byte */ -/* 16 bits address (word access) */ -#define ABITS1_16W 12 -#define ABITS2_16W 3 -#define ABITS_MIN_16W 1 /* minimum memory block is 2 bytes */ -/* 20 bits address */ -#define ABITS1_20 12 -#define ABITS2_20 8 -#define ABITS_MIN_20 0 /* minimum memory block is 1 byte */ -/* 21 bits address */ -#define ABITS1_21 13 -#define ABITS2_21 8 -#define ABITS_MIN_21 0 /* minimum memory block is 1 byte */ -/* 24 bits address */ -#define ABITS1_24 16 -#define ABITS2_24 8 -#define ABITS_MIN_24 0 /* minimum memory block is 1 byte */ -/* 24 bits address (word access) */ -#define ABITS1_24W 15 -#define ABITS2_24W 8 -#define ABITS_MIN_24W 1 /* minimum memory block is 2 bytes */ -/* 24 bits address (dword access) */ -#define ABITS1_24DW 14 -#define ABITS2_24DW 8 -#define ABITS_MIN_24DW 2 /* minimum memory block is 4 bytes */ -/* 26 bits address (dword access) */ -#define ABITS1_26DW 16 -#define ABITS2_26DW 8 -#define ABITS_MIN_26DW 2 /* minimum memory block is 4 bytes */ -/* 29 bits address (word access) */ -#define ABITS1_29W 20 -#define ABITS2_29W 8 -#define ABITS_MIN_29W 1 /* minimum memory block is 2 bytes */ -/* 32 bits address (word access) */ -#define ABITS1_32W 23 -#define ABITS2_32W 8 -#define ABITS_MIN_32W 1 /* minimum memory block is 2 bytes */ -/* 32 bits address (dword access) */ -#define ABITS1_32DW 22 -#define ABITS2_32DW 8 -#define ABITS_MIN_32DW 2 /* minimum memory block is 4 bytes */ -/* mask bits */ -#define MHMASK(abits) (0xffffffff >> (32 - abits)) - - -/*************************************************************************** - - Global variables - -***************************************************************************/ - -typedef unsigned char MHELE; - -extern MHELE ophw; /* opcode handler */ -extern MHELE *cur_mrhard; /* current set of read handlers */ -extern MHELE *cur_mwhard; /* current set of write handlers */ - -extern UINT8 *OP_RAM; /* opcode RAM base */ -extern UINT8 *OP_ROM; /* opcode ROM base */ -extern UINT8 *cpu_bankbase[]; /* array of bank bases */ - - -/* global memory access width and mask (16-bit and 32-bit under-size accesses) */ -//extern UINT32 mem_width; -//extern UINT32 mem_mask; -//extern UINT32 mem_offs; - -/*************************************************************************** - - Macros - -***************************************************************************/ - -/* ----- 16-bit memory accessing ----- */ -#define COMBINE_DATA(varptr) (*(varptr) = (*(varptr) & mem_mask) | (data & ~mem_mask)) -#define ACCESSING_LSB ((mem_mask & 0x00ff) == 0) -#define ACCESSING_MSB ((mem_mask & 0xff00) == 0) - -//extern unsigned char prgrom[128*1024]; - -/* ----- opcode reading ----- */ -#define cpu_readop cpu_readmem16 -//#define cpu_readop16(A) READ_WORD(&prgrom[A&0x3fff]) -//#define cpu_readop32(A) READ_DWORD(&prgrom[A&0x3fff]) - -/* ----- opcode argument reading ----- */ -#define cpu_readop_arg cpu_readmem16 -//#define cpu_readop_arg16(A) READ_WORD(&prgrom[A&0x3fff]) -//#define cpu_readop_arg32(A) READ_DWORD(&prgrom[A&0x3fff]) - -/* ----- bank switching for CPU cores ----- */ -#define change_pc_generic(pc,abits2,abitsmin,shift,setop) \ -{ \ - if (cur_mrhard[(pc)>>(abits2+abitsmin+shift)] != ophw) \ - setop(pc); \ -} -#define change_pc16(pc) -//change_pc_generic(pc, ABITS2_16, ABITS_MIN_16, 0, cpu_setOPbase16) -#define change_pc20(pc) change_pc_generic(pc, ABITS2_20, ABITS_MIN_20, 0, cpu_setOPbase20) -#define change_pc21(pc) change_pc_generic(pc, ABITS2_21, ABITS_MIN_21, 0, cpu_setOPbase21) -#define change_pc24(pc) change_pc_generic(pc, ABITS2_24, ABITS_MIN_24, 0, cpu_setOPbase24) -#define change_pc16bew(pc) change_pc_generic(pc, ABITS2_16W, ABITS_MIN_16W, 0, cpu_setOPbase16bew) -#define change_pc16lew(pc) change_pc_generic(pc, ABITS2_16W, ABITS_MIN_16W, 0, cpu_setOPbase16lew) -#define change_pc24bew(pc) change_pc_generic(pc, ABITS2_24W, ABITS_MIN_24W, 0, cpu_setOPbase24bew) -#define change_pc29lew(pc) change_pc_generic(pc, ABITS2_29W, ABITS_MIN_29W, 3, cpu_setOPbase29lew) -#define change_pc32bew(pc) change_pc_generic(pc, ABITS2_32W, ABITS_MIN_32W, 0, cpu_setOPbase32bew) -#define change_pc32lew(pc) change_pc_generic(pc, ABITS2_32W, ABITS_MIN_32W, 0, cpu_setOPbase32lew) -#define change_pc24bedw(pc) change_pc_generic(pc, ABITS2_24DW, ABITS_MIN_24DW, 0, cpu_setOPbase24bedw) -#define change_pc26ledw(pc) change_pc_generic(pc, ABITS2_26DW, ABITS_MIN_26DW, 0, cpu_setOPbase26ledw) -#define change_pc32bedw(pc) change_pc_generic(pc, ABITS2_32DW, ABITS_MIN_32DW, 0, cpu_setOPbase32bedw) - -/* backward compatibility */ -#define change_pc(pc) -// change_pc16(pc) - -/* ----- for use OPbaseOverride driver, request override callback to next cpu_setOPbase ----- */ -#define catch_nextBranch() (ophw = 0xff) - -/* ----- bank switching macro ----- */ -#define cpu_setbank(bank, base) \ -{ \ - if (bank >= 1 && bank <= MAX_BANKS) \ - { \ - cpu_bankbase[bank] = (UINT8 *)(base); \ - if (ophw == bank) \ - { \ - ophw = 0xff; \ - cpu_set_op_base(cpu_get_pc()); \ - } \ - } \ -} - - -/*************************************************************************** - - Function prototypes - -***************************************************************************/ - -/* ----- memory setup function ----- */ - -/* ----- memory read functions ----- */ -data8_t cpu_readmem16(offs_t address); -data8_t cpu_readmem20(offs_t address); -data8_t cpu_readmem21(offs_t address); -data8_t cpu_readmem24(offs_t address); - -data16_t cpu_readmem16bew(offs_t address); -data16_t cpu_readmem16bew_word(offs_t address); -data16_t cpu_readmem16lew(offs_t address); -data16_t cpu_readmem16lew_word(offs_t address); -data16_t cpu_readmem24bew(offs_t address); -data16_t cpu_readmem24bew_word(offs_t address); -data16_t cpu_readmem29lew(offs_t address); -data16_t cpu_readmem29lew_word(offs_t address); -data16_t cpu_readmem32bew(offs_t address); -data16_t cpu_readmem32bew_word(offs_t address); -data16_t cpu_readmem32lew(offs_t address); -data16_t cpu_readmem32lew_word(offs_t address); - -data32_t cpu_readmem24bedw(offs_t address); -data32_t cpu_readmem24bedw_word(offs_t address); -data32_t cpu_readmem24bedw_dword(offs_t address); -data32_t cpu_readmem26ledw(offs_t address); -data32_t cpu_readmem26ledw_word(offs_t address); -data32_t cpu_readmem26ledw_dword(offs_t address); -data32_t cpu_readmem27bedw(offs_t address); -data32_t cpu_readmem27bedw_word(offs_t address); -data32_t cpu_readmem27bedw_dword(offs_t address); -data32_t cpu_readmem32bedw(offs_t address); -data32_t cpu_readmem32bedw_word(offs_t address); -data32_t cpu_readmem32bedw_dword(offs_t address); - -/* ----- memory write functions ----- */ -void cpu_writemem16(offs_t address,data8_t data); -void cpu_writemem20(offs_t address,data8_t data); -void cpu_writemem21(offs_t address,data8_t data); -void cpu_writemem24(offs_t address,data8_t data); - -void cpu_writemem16bew(offs_t address,data16_t data); -void cpu_writemem16bew_word(offs_t address,data16_t data); -void cpu_writemem16lew(offs_t address,data16_t data); -void cpu_writemem16lew_word(offs_t address,data16_t data); -void cpu_writemem24bew(offs_t address,data16_t data); -void cpu_writemem24bew_word(offs_t address,data16_t data); -void cpu_writemem29lew(offs_t address,data16_t data); -void cpu_writemem29lew_word(offs_t address,data16_t data); -void cpu_writemem32bew(offs_t address,data16_t data); -void cpu_writemem32bew_word(offs_t address,data16_t data); -void cpu_writemem32lew(offs_t address,data16_t data); -void cpu_writemem32lew_word(offs_t address,data16_t data); - -void cpu_writemem24bedw(offs_t address,data32_t data); -void cpu_writemem24bedw_word(offs_t address,data32_t data); -void cpu_writemem24bedw_dword(offs_t address,data32_t data); -void cpu_writemem26ledw(offs_t address,data32_t data); -void cpu_writemem26ledw_word(offs_t address,data32_t data); -void cpu_writemem26ledw_dword(offs_t address,data32_t data); -void cpu_writemem27bedw(offs_t address,data32_t data); -void cpu_writemem27bedw_word(offs_t address,data32_t data); -void cpu_writemem27bedw_dword(offs_t address,data32_t data); -void cpu_writemem32bedw(offs_t address,data32_t data); -void cpu_writemem32bedw_word(offs_t address,data32_t data); -void cpu_writemem32bedw_dword(offs_t address,data32_t data); - -/* ----- port I/O functions ----- */ -int cpu_readport(int port); -void cpu_writeport(int port, int value); - -/* ----- dynamic memory/port mapping ----- */ -void *install_mem_read_handler(int cpu, int start, int end, mem_read_handler handler); -void *install_mem_read16_handler(int cpu, int start, int end, mem_read16_handler handler); -void *install_mem_read32_handler(int cpu, int start, int end, mem_read32_handler handler); -void *install_mem_write_handler(int cpu, int start, int end, mem_write_handler handler); -void *install_mem_write16_handler(int cpu, int start, int end, mem_write16_handler handler); -void *install_mem_write32_handler(int cpu, int start, int end, mem_write32_handler handler); -void *install_port_read_handler(int cpu, int start, int end, mem_read_handler handler); -void *install_port_write_handler(int cpu, int start, int end, mem_write_handler handler); - -/* ----- dynamic bank handlers ----- */ -void cpu_setbankhandler_r(int bank, mem_read_handler handler); -void cpu_setbankhandler_w(int bank, mem_write_handler handler); - -/* ----- opcode base control ---- */ -void cpu_setOPbase16(offs_t pc); -void cpu_setOPbase20(offs_t pc); -void cpu_setOPbase21(offs_t pc); -void cpu_setOPbase24(offs_t pc); -void cpu_setOPbase16bew(offs_t pc); -void cpu_setOPbase16lew(offs_t pc); -void cpu_setOPbase24bew(offs_t pc); -void cpu_setOPbase24bedw(offs_t pc); -void cpu_setOPbase26ledw(offs_t pc); -void cpu_setOPbase29lew(offs_t pc); -void cpu_setOPbase32bew(offs_t pc); -void cpu_setOPbase32lew(offs_t pc); -void cpu_setOPbaseoverride(int cpu, opbase_handler function); - -/* ----- harder-to-explain functions ---- */ - -/* use this to set the a different opcode base address when using a CPU with - opcodes and data encrypted separately */ -void memory_set_opcode_base(int cpu, void *base); - -/* look up a chunk of memory and get its start/end addresses, and its base. -Pass in the cpu number and the offset. It will find the chunk containing -that offset and return the start and end addresses, along with a pointer to -the base of the memory. -This can be used (carefully!) by drivers that wish to access memory directly -without going through the readmem/writemem accessors (e.g., blitters). */ -void *findmemorychunk(int cpu, int offset, int *chunkstart, int *chunkend); - -#ifdef __cplusplus -} -#endif - -#endif /* !_MEMORY_H */ - diff --git a/Frameworks/AudioOverload/aosdk/eng_psf/peops/License.txt b/Frameworks/AudioOverload/aosdk/eng_psf/peops/License.txt deleted file mode 100644 index e51338c2c..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_psf/peops/License.txt +++ /dev/null @@ -1,282 +0,0 @@ -######################################################################### - - GNU GENERAL PUBLIC LICENSE - Version 2, June 1991 - - Copyright (C) 1989, 1991 Free Software Foundation, Inc. - 675 Mass Ave, Cambridge, MA 02139, USA - Everyone is permitted to copy and distribute verbatim copies - of this license document, but changing it is not allowed. - - Preamble - - The licenses for most software are designed to take away your -freedom to share and change it. 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See also the license.txt file for * - * additional informations. * - * * - ***************************************************************************/ - -//*************************************************************************// -// History of changes: -// -// 2003/01/06 - Pete -// - added Neill's ADSR timings -// -// 2002/05/15 - Pete -// - generic cleanup for the Peops release -// -//*************************************************************************// - -#define _IN_ADSR - -// will be included from spu.c -#ifdef _IN_SPU - -//////////////////////////////////////////////////////////////////////// -// ADSR func -//////////////////////////////////////////////////////////////////////// - -static u32 RateTable[160]; - -static void InitADSR(void) // INIT ADSR -{ - u32 r,rs,rd;int i; - - memset(RateTable,0,sizeof(u32)*160); // build the rate table according to Neill's rules (see at bottom of file) - - r=3;rs=1;rd=0; - - for(i=32;i<160;i++) // we start at pos 32 with the real values... everything before is 0 - { - if(r<0x3FFFFFFF) - { - r+=rs; - rd++;if(rd==5) {rd=1;rs*=2;} - } - if(r>0x3FFFFFFF) r=0x3FFFFFFF; - - RateTable[i]=r; - } -} - -//////////////////////////////////////////////////////////////////////// - -static INLINE void StartADSR(int ch) // MIX ADSR -{ - s_chan[ch].ADSRX.lVolume=1; // and init some adsr vars - s_chan[ch].ADSRX.State=0; - s_chan[ch].ADSRX.EnvelopeVol=0; -} - -//////////////////////////////////////////////////////////////////////// - -static INLINE int MixADSR(int ch) // MIX ADSR -{ - static const int sexytable[8]= - {0,4,6,8,9,10,11,12}; - - if(s_chan[ch].bStop) // should be stopped: - { // do release - if(s_chan[ch].ADSRX.ReleaseModeExp) - { - s_chan[ch].ADSRX.EnvelopeVol-=RateTable[(4*(s_chan[ch].ADSRX.ReleaseRate^0x1F))-0x18+32+sexytable[(s_chan[ch].ADSRX.EnvelopeVol>>28)&0x7]]; - } - else - { - s_chan[ch].ADSRX.EnvelopeVol-=RateTable[(4*(s_chan[ch].ADSRX.ReleaseRate^0x1F))-0x0C + 32]; - } - - if(s_chan[ch].ADSRX.EnvelopeVol<0) - { - s_chan[ch].ADSRX.EnvelopeVol=0; - s_chan[ch].bOn=0; - s_chan[ch].bNoise=0; - } - - s_chan[ch].ADSRX.lVolume=s_chan[ch].ADSRX.EnvelopeVol>>21; - return s_chan[ch].ADSRX.lVolume; - } - else // not stopped yet? - { - if(s_chan[ch].ADSRX.State==0) // -> attack - { - if(s_chan[ch].ADSRX.AttackModeExp) - { - if(s_chan[ch].ADSRX.EnvelopeVol<0x60000000) - s_chan[ch].ADSRX.EnvelopeVol+=RateTable[(s_chan[ch].ADSRX.AttackRate^0x7F)-0x10 + 32]; - else - s_chan[ch].ADSRX.EnvelopeVol+=RateTable[(s_chan[ch].ADSRX.AttackRate^0x7F)-0x18 + 32]; - } - else - { - s_chan[ch].ADSRX.EnvelopeVol+=RateTable[(s_chan[ch].ADSRX.AttackRate^0x7F)-0x10 + 32]; - } - - if(s_chan[ch].ADSRX.EnvelopeVol<0) - { - s_chan[ch].ADSRX.EnvelopeVol=0x7FFFFFFF; - s_chan[ch].ADSRX.State=1; - } - - s_chan[ch].ADSRX.lVolume=s_chan[ch].ADSRX.EnvelopeVol>>21; - return s_chan[ch].ADSRX.lVolume; - } - //--------------------------------------------------// - if(s_chan[ch].ADSRX.State==1) // -> decay - { - s_chan[ch].ADSRX.EnvelopeVol-=RateTable[(4*(s_chan[ch].ADSRX.DecayRate^0x1F))-0x18+32+sexytable[(s_chan[ch].ADSRX.EnvelopeVol>>28)&0x7]]; - - if(s_chan[ch].ADSRX.EnvelopeVol<0) s_chan[ch].ADSRX.EnvelopeVol=0; - if(((s_chan[ch].ADSRX.EnvelopeVol>>27)&0xF) <= s_chan[ch].ADSRX.SustainLevel) - { - s_chan[ch].ADSRX.State=2; - } - - s_chan[ch].ADSRX.lVolume=s_chan[ch].ADSRX.EnvelopeVol>>21; - return s_chan[ch].ADSRX.lVolume; - } - //--------------------------------------------------// - if(s_chan[ch].ADSRX.State==2) // -> sustain - { - if(s_chan[ch].ADSRX.SustainIncrease) - { - if(s_chan[ch].ADSRX.SustainModeExp) - { - if(s_chan[ch].ADSRX.EnvelopeVol<0x60000000) - s_chan[ch].ADSRX.EnvelopeVol+=RateTable[(s_chan[ch].ADSRX.SustainRate^0x7F)-0x10 + 32]; - else - s_chan[ch].ADSRX.EnvelopeVol+=RateTable[(s_chan[ch].ADSRX.SustainRate^0x7F)-0x18 + 32]; - } - else - { - s_chan[ch].ADSRX.EnvelopeVol+=RateTable[(s_chan[ch].ADSRX.SustainRate^0x7F)-0x10 + 32]; - } - - if(s_chan[ch].ADSRX.EnvelopeVol<0) - { - s_chan[ch].ADSRX.EnvelopeVol=0x7FFFFFFF; - } - } - else - { - if(s_chan[ch].ADSRX.SustainModeExp) - s_chan[ch].ADSRX.EnvelopeVol-=RateTable[((s_chan[ch].ADSRX.SustainRate^0x7F))-0x1B+32+sexytable[(s_chan[ch].ADSRX.EnvelopeVol>>28)&0x7]]; - else - s_chan[ch].ADSRX.EnvelopeVol-=RateTable[((s_chan[ch].ADSRX.SustainRate^0x7F))-0x0F + 32]; - - if(s_chan[ch].ADSRX.EnvelopeVol<0) - { - s_chan[ch].ADSRX.EnvelopeVol=0; - } - } - s_chan[ch].ADSRX.lVolume=s_chan[ch].ADSRX.EnvelopeVol>>21; - return s_chan[ch].ADSRX.lVolume; - } - } - return 0; -} - -#endif - -/* -James Higgs ADSR investigations: - -PSX SPU Envelope Timings -~~~~~~~~~~~~~~~~~~~~~~~~ - -First, here is an extract from doomed's SPU doc, which explains the basics -of the SPU "volume envelope": - -*** doomed doc extract start *** - --------------------------------------------------------------------------- -Voices. --------------------------------------------------------------------------- -The SPU has 24 hardware voices. These voices can be used to reproduce sample -data, noise or can be used as frequency modulator on the next voice. -Each voice has it's own programmable ADSR envelope filter. The main volume -can be programmed independently for left and right output. - -The ADSR envelope filter works as follows: -Ar = Attack rate, which specifies the speed at which the volume increases - from zero to it's maximum value, as soon as the note on is given. The - slope can be set to lineair or exponential. -Dr = Decay rate specifies the speed at which the volume decreases to the - sustain level. Decay is always decreasing exponentially. -Sl = Sustain level, base level from which sustain starts. -Sr = Sustain rate is the rate at which the volume of the sustained note - increases or decreases. This can be either lineair or exponential. -Rr = Release rate is the rate at which the volume of the note decreases - as soon as the note off is given. - - lvl | - ^ | /\Dr __ - Sl _| _ / _ \__--- \ - | / ---__ \ Rr - | /Ar Sr \ \ - | / \\ - |/___________________\________ - ->time - -The overal volume can also be set to sweep up or down lineairly or -exponentially from it's current value. This can be done seperately -for left and right. - -Relevant SPU registers: -------------------------------------------------------------- -$1f801xx8 Attack/Decay/Sustain level -bit |0f|0e 0d 0c 0b 0a 09 08|07 06 05 04|03 02 01 00| -desc.|Am| Ar |Dr |Sl | - -Am 0 Attack mode Linear - 1 Exponential - -Ar 0-7f attack rate -Dr 0-f decay rate -Sl 0-f sustain level -------------------------------------------------------------- -$1f801xxa Sustain rate, Release Rate. -bit |0f|0e|0d|0c 0b 0a 09 08 07 06|05|04 03 02 01 00| -desc.|Sm|Sd| 0| Sr |Rm|Rr | - -Sm 0 sustain rate mode linear - 1 exponential -Sd 0 sustain rate mode increase - 1 decrease -Sr 0-7f Sustain Rate -Rm 0 Linear decrease - 1 Exponential decrease -Rr 0-1f Release Rate - -Note: decay mode is always Expontial decrease, and thus cannot -be set. -------------------------------------------------------------- -$1f801xxc Current ADSR volume -bit |0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00| -desc.|ADSRvol | - -ADSRvol Returns the current envelope volume when - read. --- James' Note: return range: 0 -> 32767 - -*** doomed doc extract end *** - -By using a small PSX proggie to visualise the envelope as it was played, -the following results for envelope timing were obtained: - -1. Attack rate value (linear mode) - - Attack value range: 0 -> 127 - - Value | 48 | 52 | 56 | 60 | 64 | 68 | 72 | | 80 | - ----------------------------------------------------------------- - Frames | 11 | 21 | 42 | 84 | 169| 338| 676| |2890| - - Note: frames is no. of PAL frames to reach full volume (100% - amplitude) - - Hmm, noticing that the time taken to reach full volume doubles - every time we add 4 to our attack value, we know the equation is - of form: - frames = k * 2 ^ (value / 4) - - (You may ponder about envelope generator hardware at this point, - or maybe not... :) - - By substituting some stuff and running some checks, we get: - - k = 0.00257 (close enuf) - - therefore, - frames = 0.00257 * 2 ^ (value / 4) - If you just happen to be writing an emulator, then you can probably - use an equation like: - - %volume_increase_per_tick = 1 / frames - - - ------------------------------------ - Pete: - ms=((1<<(value>>2))*514)/10000 - ------------------------------------ - -2. Decay rate value (only has log mode) - - Decay value range: 0 -> 15 - - Value | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | - ------------------------------------------------ - frames | | | | | 6 | 12 | 24 | 47 | - - Note: frames here is no. of PAL frames to decay to 50% volume. - - formula: frames = k * 2 ^ (value) - - Substituting, we get: k = 0.00146 - - Further info on logarithmic nature: - frames to decay to sustain level 3 = 3 * frames to decay to - sustain level 9 - - Also no. of frames to 25% volume = roughly 1.85 * no. of frames to - 50% volume. - - Frag it - just use linear approx. - - ------------------------------------ - Pete: - ms=((1< 127 - - Value | 48 | 52 | 56 | 60 | 64 | 68 | 72 | - ------------------------------------------- - frames | 9 | 19 | 37 | 74 | 147| 293| 587| - - Here, frames = no. of PAL frames for volume amplitude to go from 100% - to 0% (or vice-versa). - - Same formula as for attack value, just a different value for k: - - k = 0.00225 - - ie: frames = 0.00225 * 2 ^ (value / 4) - - For emulation purposes: - - %volume_increase_or_decrease_per_tick = 1 / frames - - ------------------------------------ - Pete: - ms=((1<<(value>>2))*450)/10000 - ------------------------------------ - - -4. Release rate (linear mode) - - Release rate range: 0 -> 31 - - Value | 13 | 14 | 15 | 16 | 17 | - --------------------------------------------------------------- - frames | 18 | 36 | 73 | 146| 292| - - Here, frames = no. of PAL frames to decay from 100% vol to 0% vol - after "note-off" is triggered. - - Formula: frames = k * 2 ^ (value) - - And so: k = 0.00223 - - ------------------------------------ - Pete: - ms=((1< release phase - { - if(s_chan[ch].ADSR.ReleaseVal!=0) // -> release not 0: do release (if 0: stop right now) - { - if(!s_chan[ch].ADSR.ReleaseVol) // --> release just started? set up the release stuff - { - s_chan[ch].ADSR.ReleaseStartTime=s_chan[ch].ADSR.lTime; - s_chan[ch].ADSR.ReleaseVol=s_chan[ch].ADSR.lVolume; - s_chan[ch].ADSR.ReleaseTime = // --> calc how long does it take to reach the wanted sus level - (s_chan[ch].ADSR.ReleaseTime* - s_chan[ch].ADSR.ReleaseVol)/1024; - } - // -> NO release exp mode used (yet) - v=s_chan[ch].ADSR.ReleaseVol; // -> get last volume - lT=s_chan[ch].ADSR.lTime- // -> how much time is past? - s_chan[ch].ADSR.ReleaseStartTime; - l1=s_chan[ch].ADSR.ReleaseTime; - - if(lT we still have to release - { - v=v-((v*lT)/l1); // --> calc new volume - } - else // -> release is over: now really stop that sample - {v=0;s_chan[ch].bOn=0;s_chan[ch].ADSR.ReleaseVol=0;s_chan[ch].bNoise=0;} - } - else // -> release IS 0: release at once - { - v=0;s_chan[ch].bOn=0;s_chan[ch].ADSR.ReleaseVol=0;s_chan[ch].bNoise=0; - } - } - else - {//--------------------------------------------------// not in release phase: - v=1024; - lT=s_chan[ch].ADSR.lTime; - l1=s_chan[ch].ADSR.AttackTime; - - if(lT0) - { - if(l3!=0) v2+=((v-v2)*lT)/l3; - else v2=v; - } - else - { - if(l3!=0) v2-=(v2*lT)/l3; - else v2=v; - } - - if(v2>v) v2=v; - if(v2<=0) {v2=0;s_chan[ch].bOn=0;s_chan[ch].ADSR.ReleaseVol=0;s_chan[ch].bNoise=0;} - - v=v2; - } - } - } - - //----------------------------------------------------// - // ok, done for this channel, so increase time - - s_chan[ch].ADSR.lTime+=1; // 1 = 1.020408f ms; - - if(v>1024) v=1024; // adjust volume - if(v<0) v=0; - s_chan[ch].ADSR.lVolume=v; // store act volume - - return v; // return the volume factor -*/ - - -//----------------------------------------------------------------------------- -//----------------------------------------------------------------------------- -//----------------------------------------------------------------------------- - - -/* ------------------------------------------------------------------------------ -Neill Corlett -Playstation SPU envelope timing notes ------------------------------------------------------------------------------ - -This is preliminary. This may be wrong. But the model described herein fits -all of my experimental data, and it's just simple enough to sound right. - -ADSR envelope level ranges from 0x00000000 to 0x7FFFFFFF internally. -The value returned by channel reg 0xC is (envelope_level>>16). - -Each sample, an increment or decrement value will be added to or -subtracted from this envelope level. - -Create the rate log table. The values double every 4 entries. - entry #0 = 4 - - 4, 5, 6, 7, - 8,10,12,14, - 16,20,24,28, ... - - entry #40 = 4096... - entry #44 = 8192... - entry #48 = 16384... - entry #52 = 32768... - entry #56 = 65536... - -increments and decrements are in terms of ratelogtable[n] -n may exceed the table bounds (plan on n being between -32 and 127). -table values are all clipped between 0x00000000 and 0x3FFFFFFF - -when you "voice on", the envelope is always fully reset. -(yes, it may click. the real thing does this too.) - -envelope level begins at zero. - -each state happens for at least 1 cycle -(transitions are not instantaneous) -this may result in some oddness: if the decay rate is uberfast, it will cut -the envelope from full down to half in one sample, potentially skipping over -the sustain level - -ATTACK ------- -- if the envelope level has overflowed past the max, clip to 0x7FFFFFFF and - proceed to DECAY. - -Linear attack mode: -- line extends upward to 0x7FFFFFFF -- increment per sample is ratelogtable[(Ar^0x7F)-0x10] - -Logarithmic attack mode: -if envelope_level < 0x60000000: - - line extends upward to 0x60000000 - - increment per sample is ratelogtable[(Ar^0x7F)-0x10] -else: - - line extends upward to 0x7FFFFFFF - - increment per sample is ratelogtable[(Ar^0x7F)-0x18] - -DECAY ------ -- if ((envelope_level>>27)&0xF) <= Sl, proceed to SUSTAIN. - Do not clip to the sustain level. -- current line ends at (envelope_level & 0x07FFFFFF) -- decrement per sample depends on (envelope_level>>28)&0x7 - 0: ratelogtable[(4*(Dr^0x1F))-0x18+0] - 1: ratelogtable[(4*(Dr^0x1F))-0x18+4] - 2: ratelogtable[(4*(Dr^0x1F))-0x18+6] - 3: ratelogtable[(4*(Dr^0x1F))-0x18+8] - 4: ratelogtable[(4*(Dr^0x1F))-0x18+9] - 5: ratelogtable[(4*(Dr^0x1F))-0x18+10] - 6: ratelogtable[(4*(Dr^0x1F))-0x18+11] - 7: ratelogtable[(4*(Dr^0x1F))-0x18+12] - (note that this is the same as the release rate formula, except that - decay rates 10-1F aren't possible... those would be slower in theory) - -SUSTAIN -------- -- no terminating condition except for voice off -- Sd=0 (increase) behavior is identical to ATTACK for both log and linear. -- Sd=1 (decrease) behavior: -Linear sustain decrease: -- line extends to 0x00000000 -- decrement per sample is ratelogtable[(Sr^0x7F)-0x0F] -Logarithmic sustain decrease: -- current line ends at (envelope_level & 0x07FFFFFF) -- decrement per sample depends on (envelope_level>>28)&0x7 - 0: ratelogtable[(Sr^0x7F)-0x1B+0] - 1: ratelogtable[(Sr^0x7F)-0x1B+4] - 2: ratelogtable[(Sr^0x7F)-0x1B+6] - 3: ratelogtable[(Sr^0x7F)-0x1B+8] - 4: ratelogtable[(Sr^0x7F)-0x1B+9] - 5: ratelogtable[(Sr^0x7F)-0x1B+10] - 6: ratelogtable[(Sr^0x7F)-0x1B+11] - 7: ratelogtable[(Sr^0x7F)-0x1B+12] - -RELEASE -------- -- if the envelope level has overflowed to negative, clip to 0 and QUIT. - -Linear release mode: -- line extends to 0x00000000 -- decrement per sample is ratelogtable[(4*(Rr^0x1F))-0x0C] - -Logarithmic release mode: -- line extends to (envelope_level & 0x0FFFFFFF) -- decrement per sample depends on (envelope_level>>28)&0x7 - 0: ratelogtable[(4*(Rr^0x1F))-0x18+0] - 1: ratelogtable[(4*(Rr^0x1F))-0x18+4] - 2: ratelogtable[(4*(Rr^0x1F))-0x18+6] - 3: ratelogtable[(4*(Rr^0x1F))-0x18+8] - 4: ratelogtable[(4*(Rr^0x1F))-0x18+9] - 5: ratelogtable[(4*(Rr^0x1F))-0x18+10] - 6: ratelogtable[(4*(Rr^0x1F))-0x18+11] - 7: ratelogtable[(4*(Rr^0x1F))-0x18+12] - ------------------------------------------------------------------------------ -*/ diff --git a/Frameworks/AudioOverload/aosdk/eng_psf/peops/adsr.h b/Frameworks/AudioOverload/aosdk/eng_psf/peops/adsr.h deleted file mode 100644 index 868d57a9e..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_psf/peops/adsr.h +++ /dev/null @@ -1,28 +0,0 @@ -/*************************************************************************** - adsr.h - description - ------------------- - begin : Wed May 15 2002 - copyright : (C) 2002 by Pete Bernert - email : BlackDove@addcom.de - ***************************************************************************/ - -/*************************************************************************** - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. See also the license.txt file for * - * additional informations. * - * * - ***************************************************************************/ - -//*************************************************************************// -// History of changes: -// -// 2002/05/15 - Pete -// - generic cleanup for the Peops release -// -//*************************************************************************// - -static INLINE void StartADSR(int ch); -static INLINE int MixADSR(int ch); diff --git a/Frameworks/AudioOverload/aosdk/eng_psf/peops/dma.c b/Frameworks/AudioOverload/aosdk/eng_psf/peops/dma.c deleted file mode 100644 index 9aab30907..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_psf/peops/dma.c +++ /dev/null @@ -1,80 +0,0 @@ -/*************************************************************************** - dma.c - description - ------------------- - begin : Wed May 15 2002 - copyright : (C) 2002 by Pete Bernert - email : BlackDove@addcom.de - ***************************************************************************/ - -/*************************************************************************** - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. See also the license.txt file for * - * additional informations. * - * * - ***************************************************************************/ - -//*************************************************************************// -// History of changes: -// -// 2002/05/15 - Pete -// - generic cleanup for the Peops release -// -//*************************************************************************// - -#include "../peops/stdafx.h" - -#define _IN_DMA - -extern uint32 psx_ram[(2*1024*1024)/4]; - -//#include "externals.h" -//////////////////////////////////////////////////////////////////////// -// READ DMA (many values) -//////////////////////////////////////////////////////////////////////// - -void SPUreadDMAMem(u32 usPSXMem,int iSize) -{ - int i; - u16 *ram16 = (u16 *)&psx_ram[0]; - - for(i=0;i>1]=spuMem[spuAddr>>1]; // spu addr got by writeregister - usPSXMem+=2; - spuAddr+=2; // inc spu addr - if(spuAddr>0x7ffff) spuAddr=0; // wrap - } -} - -//////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////// - -// to investigate: do sound data updates by writedma affect spu -// irqs? Will an irq be triggered, if new data is written to -// the memory irq address? - -//////////////////////////////////////////////////////////////////////// -// WRITE DMA (many values) -//////////////////////////////////////////////////////////////////////// - -void SPUwriteDMAMem(u32 usPSXMem,int iSize) -{ - int i; - u16 *ram16 = (u16 *)&psx_ram[0]; - - for(i=0;i SPU %x\n", usPSXMem, spuAddr); - spuMem[spuAddr>>1] = ram16[usPSXMem>>1]; - usPSXMem+=2; // spu addr got by writeregister - spuAddr+=2; // inc spu addr - if(spuAddr>0x7ffff) spuAddr=0; // wrap - } -} - -//////////////////////////////////////////////////////////////////////// - diff --git a/Frameworks/AudioOverload/aosdk/eng_psf/peops/dma.h b/Frameworks/AudioOverload/aosdk/eng_psf/peops/dma.h deleted file mode 100644 index 8c1a7e19c..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_psf/peops/dma.h +++ /dev/null @@ -1,31 +0,0 @@ -/*************************************************************************** - dma.h - description - ------------------- - begin : Wed May 15 2002 - copyright : (C) 2002 by Pete Bernert - email : BlackDove@addcom.de - ***************************************************************************/ - -/*************************************************************************** - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. See also the license.txt file for * - * additional informations. * - * * - ***************************************************************************/ - -//*************************************************************************// -// History of changes: -// -// 2002/05/15 - Pete -// - generic cleanup for the Peops release -// -//*************************************************************************// - - -u16 CALLBACK SPUreadDMA(void); -void CALLBACK SPUreadDMAMem(u16 * pusPSXMem,int iSize); -void CALLBACK SPUwriteDMA(u16 val); -void CALLBACK SPUwriteDMAMem(u16 * pusPSXMem,int iSize); diff --git a/Frameworks/AudioOverload/aosdk/eng_psf/peops/externals.h b/Frameworks/AudioOverload/aosdk/eng_psf/peops/externals.h deleted file mode 100644 index f27abc078..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_psf/peops/externals.h +++ /dev/null @@ -1,203 +0,0 @@ -/*************************************************************************** - externals.h - description - ------------------- - begin : Wed May 15 2002 - copyright : (C) 2002 by Pete Bernert - email : BlackDove@addcom.de - ***************************************************************************/ - -/*************************************************************************** - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. See also the license.txt file for * - * additional informations. * - * * - ***************************************************************************/ - -#include "ao.h" - -#ifndef PEOPS_EXTERNALS -#define PEOPS_EXTERNALS - -typedef int8 s8; -typedef int16 s16; -typedef int32 s32; -typedef int64 s64; - -typedef uint8 u8; -typedef uint16 u16; -typedef uint32 u32; -typedef uint64 u64; - -#if LSB_FIRST -static INLINE u16 BFLIP16(u16 x) -{ - return x; -} -#else -static INLINE u16 BFLIP16(u16 x) -{ - return( ((x>>8)&0xFF)| ((x&0xFF)<<8) ); -} -#endif - -//*************************************************************************// -// History of changes: -// -// 2002/05/15 - Pete -// - generic cleanup for the Peops release -// -//*************************************************************************// - -#define max(a,b) (((a) > (b)) ? (a) : (b)) -#define min(a,b) (((a) < (b)) ? (a) : (b)) - -//////////////////////////////////////////////////////////////////////// -// spu defines -//////////////////////////////////////////////////////////////////////// - -// num of channels -#define MAXCHAN 24 - -/////////////////////////////////////////////////////////// -// struct defines -/////////////////////////////////////////////////////////// - -// ADSR INFOS PER CHANNEL -typedef struct -{ - int AttackModeExp; - s32 AttackTime; - s32 DecayTime; - s32 SustainLevel; - int SustainModeExp; - s32 SustainModeDec; - s32 SustainTime; - int ReleaseModeExp; - u32 ReleaseVal; - s32 ReleaseTime; - s32 ReleaseStartTime; - s32 ReleaseVol; - s32 lTime; - s32 lVolume; -} ADSRInfo; - -typedef struct -{ - int State; - int AttackModeExp; - int AttackRate; - int DecayRate; - int SustainLevel; - int SustainModeExp; - int SustainIncrease; - int SustainRate; - int ReleaseModeExp; - int ReleaseRate; - int EnvelopeVol; - s32 lVolume; - s32 lDummy1; - s32 lDummy2; -} ADSRInfoEx; - -/////////////////////////////////////////////////////////// - -// Tmp Flags - -// used for debug channel muting -#define FLAG_MUTE 1 - -/////////////////////////////////////////////////////////// - -// MAIN CHANNEL STRUCT -typedef struct -{ - int bNew; // start flag - - int iSBPos; // mixing stuff - int spos; - int sinc; - int SB[32+1]; - int sval; - - u8 * pStart; // start ptr into sound mem - u8 * pCurr; // current pos in sound mem - u8 * pLoop; // loop ptr in sound mem - - int bOn; // is channel active (sample playing?) - int bStop; // is channel stopped (sample _can_ still be playing, ADSR Release phase) - int iActFreq; // current psx pitch - int iUsedFreq; // current pc pitch - int iLeftVolume; // left volume - int iLeftVolRaw; // left psx volume value - int bIgnoreLoop; // ignore loop bit, if an external loop address is used - int iRightVolume; // right volume - int iRightVolRaw; // right psx volume value - int iRawPitch; // raw pitch (0...3fff) - int iIrqDone; // debug irq done flag - int s_1; // last decoding infos - int s_2; - int bRVBActive; // reverb active flag - int iRVBOffset; // reverb offset - int iRVBRepeat; // reverb repeat - int bNoise; // noise active flag - int bFMod; // freq mod (0=off, 1=sound channel, 2=freq channel) - int iOldNoise; // old noise val for this channel - ADSRInfo ADSR; // active ADSR settings - ADSRInfoEx ADSRX; // next ADSR settings (will be moved to active on sample start) - -} SPUCHAN; - -/////////////////////////////////////////////////////////// - -typedef struct -{ - int StartAddr; // reverb area start addr in samples - int CurrAddr; // reverb area curr addr in samples - - int Enabled; - int VolLeft; - int VolRight; - int iLastRVBLeft; - int iLastRVBRight; - int iRVBLeft; - int iRVBRight; - - - int FB_SRC_A; // (offset) - int FB_SRC_B; // (offset) - int IIR_ALPHA; // (coef.) - int ACC_COEF_A; // (coef.) - int ACC_COEF_B; // (coef.) - int ACC_COEF_C; // (coef.) - int ACC_COEF_D; // (coef.) - int IIR_COEF; // (coef.) - int FB_ALPHA; // (coef.) - int FB_X; // (coef.) - int IIR_DEST_A0; // (offset) - int IIR_DEST_A1; // (offset) - int ACC_SRC_A0; // (offset) - int ACC_SRC_A1; // (offset) - int ACC_SRC_B0; // (offset) - int ACC_SRC_B1; // (offset) - int IIR_SRC_A0; // (offset) - int IIR_SRC_A1; // (offset) - int IIR_DEST_B0; // (offset) - int IIR_DEST_B1; // (offset) - int ACC_SRC_C0; // (offset) - int ACC_SRC_C1; // (offset) - int ACC_SRC_D0; // (offset) - int ACC_SRC_D1; // (offset) - int IIR_SRC_B1; // (offset) - int IIR_SRC_B0; // (offset) - int MIX_DEST_A0; // (offset) - int MIX_DEST_A1; // (offset) - int MIX_DEST_B0; // (offset) - int MIX_DEST_B1; // (offset) - int IN_COEF_L; // (coef.) - int IN_COEF_R; // (coef.) -} REVERBInfo; - -#endif // PEOPS_EXTERNALS diff --git a/Frameworks/AudioOverload/aosdk/eng_psf/peops/gauss_i.h b/Frameworks/AudioOverload/aosdk/eng_psf/peops/gauss_i.h deleted file mode 100644 index 37f952455..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_psf/peops/gauss_i.h +++ /dev/null @@ -1,163 +0,0 @@ -/*************************************************************************** - gauss_i.h - description - ----------------------- - begin : Sun Feb 08 2003 - copyright : (C) 2003 by Chris Moeller, eh, whatever - email : chris@kode54.tk - ***************************************************************************/ - -/*************************************************************************** - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. See also the license.txt file for * - * additional informations. * - * * - ***************************************************************************/ - -//*************************************************************************// -// History of changes: -// -// 2003/02/08 - kode54 -// - generated by interleaving table from gauss.h from the libopenspc -// project; a gaussian bell curve table logged from the SPC-700, -// though Neill says he logged the same curve from a PSX SPU. Also -// says that interleaving the coefficients together runs faster. Meh. -// -//*************************************************************************// - -#ifndef GAUSS_H -#define GAUSS_H - -// 1024 entries -const int gauss[]={ - 0x172, 0x519, 0x176, 0x000, 0x16E, 0x519, 0x17A, 0x000, - 0x16A, 0x518, 0x17D, 0x000, 0x166, 0x518, 0x181, 0x000, - 0x162, 0x518, 0x185, 0x000, 0x15F, 0x518, 0x189, 0x000, - 0x15B, 0x518, 0x18D, 0x000, 0x157, 0x517, 0x191, 0x000, - 0x153, 0x517, 0x195, 0x000, 0x150, 0x517, 0x19A, 0x000, - 0x14C, 0x516, 0x19E, 0x000, 0x148, 0x516, 0x1A2, 0x000, - 0x145, 0x515, 0x1A6, 0x000, 0x141, 0x514, 0x1AA, 0x000, - 0x13E, 0x514, 0x1AE, 0x000, 0x13A, 0x513, 0x1B2, 0x000, - 0x137, 0x512, 0x1B7, 0x001, 0x133, 0x511, 0x1BB, 0x001, - 0x130, 0x511, 0x1BF, 0x001, 0x12C, 0x510, 0x1C3, 0x001, - 0x129, 0x50F, 0x1C8, 0x001, 0x125, 0x50E, 0x1CC, 0x001, - 0x122, 0x50D, 0x1D0, 0x001, 0x11E, 0x50C, 0x1D5, 0x001, - 0x11B, 0x50B, 0x1D9, 0x001, 0x118, 0x50A, 0x1DD, 0x001, - 0x114, 0x508, 0x1E2, 0x001, 0x111, 0x507, 0x1E6, 0x002, - 0x10E, 0x506, 0x1EB, 0x002, 0x10B, 0x504, 0x1EF, 0x002, - 0x107, 0x503, 0x1F3, 0x002, 0x104, 0x502, 0x1F8, 0x002, - 0x101, 0x500, 0x1FC, 0x002, 0x0FE, 0x4FF, 0x201, 0x002, - 0x0FB, 0x4FD, 0x205, 0x003, 0x0F8, 0x4FB, 0x20A, 0x003, - 0x0F5, 0x4FA, 0x20F, 0x003, 0x0F2, 0x4F8, 0x213, 0x003, - 0x0EF, 0x4F6, 0x218, 0x003, 0x0EC, 0x4F5, 0x21C, 0x004, - 0x0E9, 0x4F3, 0x221, 0x004, 0x0E6, 0x4F1, 0x226, 0x004, - 0x0E3, 0x4EF, 0x22A, 0x004, 0x0E0, 0x4ED, 0x22F, 0x004, - 0x0DD, 0x4EB, 0x233, 0x005, 0x0DA, 0x4E9, 0x238, 0x005, - 0x0D7, 0x4E7, 0x23D, 0x005, 0x0D4, 0x4E5, 0x241, 0x005, - 0x0D2, 0x4E3, 0x246, 0x006, 0x0CF, 0x4E0, 0x24B, 0x006, - 0x0CC, 0x4DE, 0x250, 0x006, 0x0C9, 0x4DC, 0x254, 0x006, - 0x0C7, 0x4D9, 0x259, 0x007, 0x0C4, 0x4D7, 0x25E, 0x007, - 0x0C1, 0x4D5, 0x263, 0x007, 0x0BF, 0x4D2, 0x267, 0x008, - 0x0BC, 0x4D0, 0x26C, 0x008, 0x0BA, 0x4CD, 0x271, 0x008, - 0x0B7, 0x4CB, 0x276, 0x009, 0x0B4, 0x4C8, 0x27B, 0x009, - 0x0B2, 0x4C5, 0x280, 0x009, 0x0AF, 0x4C3, 0x284, 0x00A, - 0x0AD, 0x4C0, 0x289, 0x00A, 0x0AB, 0x4BD, 0x28E, 0x00A, - 0x0A8, 0x4BA, 0x293, 0x00B, 0x0A6, 0x4B7, 0x298, 0x00B, - 0x0A3, 0x4B5, 0x29D, 0x00B, 0x0A1, 0x4B2, 0x2A2, 0x00C, - 0x09F, 0x4AF, 0x2A6, 0x00C, 0x09C, 0x4AC, 0x2AB, 0x00D, - 0x09A, 0x4A9, 0x2B0, 0x00D, 0x098, 0x4A6, 0x2B5, 0x00E, - 0x096, 0x4A2, 0x2BA, 0x00E, 0x093, 0x49F, 0x2BF, 0x00F, - 0x091, 0x49C, 0x2C4, 0x00F, 0x08F, 0x499, 0x2C9, 0x00F, - 0x08D, 0x496, 0x2CE, 0x010, 0x08B, 0x492, 0x2D3, 0x010, - 0x089, 0x48F, 0x2D8, 0x011, 0x086, 0x48C, 0x2DC, 0x011, - 0x084, 0x488, 0x2E1, 0x012, 0x082, 0x485, 0x2E6, 0x013, - 0x080, 0x481, 0x2EB, 0x013, 0x07E, 0x47E, 0x2F0, 0x014, - 0x07C, 0x47A, 0x2F5, 0x014, 0x07A, 0x477, 0x2FA, 0x015, - 0x078, 0x473, 0x2FF, 0x015, 0x076, 0x470, 0x304, 0x016, - 0x075, 0x46C, 0x309, 0x017, 0x073, 0x468, 0x30E, 0x017, - 0x071, 0x465, 0x313, 0x018, 0x06F, 0x461, 0x318, 0x018, - 0x06D, 0x45D, 0x31D, 0x019, 0x06B, 0x459, 0x322, 0x01A, - 0x06A, 0x455, 0x326, 0x01B, 0x068, 0x452, 0x32B, 0x01B, - 0x066, 0x44E, 0x330, 0x01C, 0x064, 0x44A, 0x335, 0x01D, - 0x063, 0x446, 0x33A, 0x01D, 0x061, 0x442, 0x33F, 0x01E, - 0x05F, 0x43E, 0x344, 0x01F, 0x05E, 0x43A, 0x349, 0x020, - 0x05C, 0x436, 0x34E, 0x020, 0x05A, 0x432, 0x353, 0x021, - 0x059, 0x42E, 0x357, 0x022, 0x057, 0x42A, 0x35C, 0x023, - 0x056, 0x425, 0x361, 0x024, 0x054, 0x421, 0x366, 0x024, - 0x053, 0x41D, 0x36B, 0x025, 0x051, 0x419, 0x370, 0x026, - 0x050, 0x415, 0x374, 0x027, 0x04E, 0x410, 0x379, 0x028, - 0x04D, 0x40C, 0x37E, 0x029, 0x04C, 0x408, 0x383, 0x02A, - 0x04A, 0x403, 0x388, 0x02B, 0x049, 0x3FF, 0x38C, 0x02C, - 0x047, 0x3FB, 0x391, 0x02D, 0x046, 0x3F6, 0x396, 0x02E, - 0x045, 0x3F2, 0x39B, 0x02F, 0x043, 0x3ED, 0x39F, 0x030, - 0x042, 0x3E9, 0x3A4, 0x031, 0x041, 0x3E5, 0x3A9, 0x032, - 0x040, 0x3E0, 0x3AD, 0x033, 0x03E, 0x3DC, 0x3B2, 0x034, - 0x03D, 0x3D7, 0x3B7, 0x035, 0x03C, 0x3D2, 0x3BB, 0x036, - 0x03B, 0x3CE, 0x3C0, 0x037, 0x03A, 0x3C9, 0x3C5, 0x038, - 0x038, 0x3C5, 0x3C9, 0x03A, 0x037, 0x3C0, 0x3CE, 0x03B, - 0x036, 0x3BB, 0x3D2, 0x03C, 0x035, 0x3B7, 0x3D7, 0x03D, - 0x034, 0x3B2, 0x3DC, 0x03E, 0x033, 0x3AD, 0x3E0, 0x040, - 0x032, 0x3A9, 0x3E5, 0x041, 0x031, 0x3A4, 0x3E9, 0x042, - 0x030, 0x39F, 0x3ED, 0x043, 0x02F, 0x39B, 0x3F2, 0x045, - 0x02E, 0x396, 0x3F6, 0x046, 0x02D, 0x391, 0x3FB, 0x047, - 0x02C, 0x38C, 0x3FF, 0x049, 0x02B, 0x388, 0x403, 0x04A, - 0x02A, 0x383, 0x408, 0x04C, 0x029, 0x37E, 0x40C, 0x04D, - 0x028, 0x379, 0x410, 0x04E, 0x027, 0x374, 0x415, 0x050, - 0x026, 0x370, 0x419, 0x051, 0x025, 0x36B, 0x41D, 0x053, - 0x024, 0x366, 0x421, 0x054, 0x024, 0x361, 0x425, 0x056, - 0x023, 0x35C, 0x42A, 0x057, 0x022, 0x357, 0x42E, 0x059, - 0x021, 0x353, 0x432, 0x05A, 0x020, 0x34E, 0x436, 0x05C, - 0x020, 0x349, 0x43A, 0x05E, 0x01F, 0x344, 0x43E, 0x05F, - 0x01E, 0x33F, 0x442, 0x061, 0x01D, 0x33A, 0x446, 0x063, - 0x01D, 0x335, 0x44A, 0x064, 0x01C, 0x330, 0x44E, 0x066, - 0x01B, 0x32B, 0x452, 0x068, 0x01B, 0x326, 0x455, 0x06A, - 0x01A, 0x322, 0x459, 0x06B, 0x019, 0x31D, 0x45D, 0x06D, - 0x018, 0x318, 0x461, 0x06F, 0x018, 0x313, 0x465, 0x071, - 0x017, 0x30E, 0x468, 0x073, 0x017, 0x309, 0x46C, 0x075, - 0x016, 0x304, 0x470, 0x076, 0x015, 0x2FF, 0x473, 0x078, - 0x015, 0x2FA, 0x477, 0x07A, 0x014, 0x2F5, 0x47A, 0x07C, - 0x014, 0x2F0, 0x47E, 0x07E, 0x013, 0x2EB, 0x481, 0x080, - 0x013, 0x2E6, 0x485, 0x082, 0x012, 0x2E1, 0x488, 0x084, - 0x011, 0x2DC, 0x48C, 0x086, 0x011, 0x2D8, 0x48F, 0x089, - 0x010, 0x2D3, 0x492, 0x08B, 0x010, 0x2CE, 0x496, 0x08D, - 0x00F, 0x2C9, 0x499, 0x08F, 0x00F, 0x2C4, 0x49C, 0x091, - 0x00F, 0x2BF, 0x49F, 0x093, 0x00E, 0x2BA, 0x4A2, 0x096, - 0x00E, 0x2B5, 0x4A6, 0x098, 0x00D, 0x2B0, 0x4A9, 0x09A, - 0x00D, 0x2AB, 0x4AC, 0x09C, 0x00C, 0x2A6, 0x4AF, 0x09F, - 0x00C, 0x2A2, 0x4B2, 0x0A1, 0x00B, 0x29D, 0x4B5, 0x0A3, - 0x00B, 0x298, 0x4B7, 0x0A6, 0x00B, 0x293, 0x4BA, 0x0A8, - 0x00A, 0x28E, 0x4BD, 0x0AB, 0x00A, 0x289, 0x4C0, 0x0AD, - 0x00A, 0x284, 0x4C3, 0x0AF, 0x009, 0x280, 0x4C5, 0x0B2, - 0x009, 0x27B, 0x4C8, 0x0B4, 0x009, 0x276, 0x4CB, 0x0B7, - 0x008, 0x271, 0x4CD, 0x0BA, 0x008, 0x26C, 0x4D0, 0x0BC, - 0x008, 0x267, 0x4D2, 0x0BF, 0x007, 0x263, 0x4D5, 0x0C1, - 0x007, 0x25E, 0x4D7, 0x0C4, 0x007, 0x259, 0x4D9, 0x0C7, - 0x006, 0x254, 0x4DC, 0x0C9, 0x006, 0x250, 0x4DE, 0x0CC, - 0x006, 0x24B, 0x4E0, 0x0CF, 0x006, 0x246, 0x4E3, 0x0D2, - 0x005, 0x241, 0x4E5, 0x0D4, 0x005, 0x23D, 0x4E7, 0x0D7, - 0x005, 0x238, 0x4E9, 0x0DA, 0x005, 0x233, 0x4EB, 0x0DD, - 0x004, 0x22F, 0x4ED, 0x0E0, 0x004, 0x22A, 0x4EF, 0x0E3, - 0x004, 0x226, 0x4F1, 0x0E6, 0x004, 0x221, 0x4F3, 0x0E9, - 0x004, 0x21C, 0x4F5, 0x0EC, 0x003, 0x218, 0x4F6, 0x0EF, - 0x003, 0x213, 0x4F8, 0x0F2, 0x003, 0x20F, 0x4FA, 0x0F5, - 0x003, 0x20A, 0x4FB, 0x0F8, 0x003, 0x205, 0x4FD, 0x0FB, - 0x002, 0x201, 0x4FF, 0x0FE, 0x002, 0x1FC, 0x500, 0x101, - 0x002, 0x1F8, 0x502, 0x104, 0x002, 0x1F3, 0x503, 0x107, - 0x002, 0x1EF, 0x504, 0x10B, 0x002, 0x1EB, 0x506, 0x10E, - 0x002, 0x1E6, 0x507, 0x111, 0x001, 0x1E2, 0x508, 0x114, - 0x001, 0x1DD, 0x50A, 0x118, 0x001, 0x1D9, 0x50B, 0x11B, - 0x001, 0x1D5, 0x50C, 0x11E, 0x001, 0x1D0, 0x50D, 0x122, - 0x001, 0x1CC, 0x50E, 0x125, 0x001, 0x1C8, 0x50F, 0x129, - 0x001, 0x1C3, 0x510, 0x12C, 0x001, 0x1BF, 0x511, 0x130, - 0x001, 0x1BB, 0x511, 0x133, 0x001, 0x1B7, 0x512, 0x137, - 0x000, 0x1B2, 0x513, 0x13A, 0x000, 0x1AE, 0x514, 0x13E, - 0x000, 0x1AA, 0x514, 0x141, 0x000, 0x1A6, 0x515, 0x145, - 0x000, 0x1A2, 0x516, 0x148, 0x000, 0x19E, 0x516, 0x14C, - 0x000, 0x19A, 0x517, 0x150, 0x000, 0x195, 0x517, 0x153, - 0x000, 0x191, 0x517, 0x157, 0x000, 0x18D, 0x518, 0x15B, - 0x000, 0x189, 0x518, 0x15F, 0x000, 0x185, 0x518, 0x162, - 0x000, 0x181, 0x518, 0x166, 0x000, 0x17D, 0x518, 0x16A, - 0x000, 0x17A, 0x519, 0x16E, 0x000, 0x176, 0x519, 0x172}; -#endif diff --git a/Frameworks/AudioOverload/aosdk/eng_psf/peops/registers.c b/Frameworks/AudioOverload/aosdk/eng_psf/peops/registers.c deleted file mode 100644 index 0ad1540bc..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_psf/peops/registers.c +++ /dev/null @@ -1,492 +0,0 @@ -/*************************************************************************** - registers.c - description - ------------------- - begin : Wed May 15 2002 - copyright : (C) 2002 by Pete Bernert - email : BlackDove@addcom.de - ***************************************************************************/ - -/*************************************************************************** - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. See also the license.txt file for * - * additional informations. * - * * - ***************************************************************************/ - -/* ChangeLog - - February 8, 2004 - xodnizel - - Fixed setting of reverb volume. Just typecast val("u16") to s16. - Also adjusted the normal channel volume to be one less than what it was before when the - "phase invert" bit is set. I'm assuming it's just in two's complement. - - 2003/02/09 - kode54 - - removed &0x3fff from reverb volume registers, fixes a few games, - hopefully won't be breaking anything - - 2003/01/19 - Pete - - added Neill's reverb - - 2003/01/06 - Pete - - added Neill's ADSR timings - - 2002/05/15 - Pete - - generic cleanup for the Peops release - -*/ - -#include "stdafx.h" - -#define _IN_REGISTERS - -#include "../peops/externals.h" -#include "../peops/registers.h" -#include "../peops/regs.h" - -//////////////////////////////////////////////////////////////////////// -// WRITE REGISTERS: called by main emu -//////////////////////////////////////////////////////////////////////// - -void SPUwriteRegister(u32 reg, u16 val) -{ - const u32 r=reg&0xfff; - regArea[(r-0xc00)>>1] = val; - -// printf("SPUwrite: r %x val %x\n", r, val); - - if(r>=0x0c00 && r<0x0d80) // some channel info? - { - int ch=(r>>4)-0xc0; // calc channel - - //if(ch==20) printf("%08x: %04x\n",reg,val); - - switch(r&0x0f) - { - //------------------------------------------------// r volume - case 0: - SetVolumeLR(0,(u8)ch,val); - break; - //------------------------------------------------// l volume - case 2: - SetVolumeLR(1,(u8)ch,val); - break; - //------------------------------------------------// pitch - case 4: - SetPitch(ch,val); - break; - //------------------------------------------------// start - case 6: - s_chan[ch].pStart=spuMemC+((u32) val<<3); - break; - //------------------------------------------------// level with pre-calcs - case 8: - { - const u32 lval=val; // DEBUG CHECK - //---------------------------------------------// - s_chan[ch].ADSRX.AttackModeExp=(lval&0x8000)?1:0; - s_chan[ch].ADSRX.AttackRate=(lval>>8) & 0x007f; - s_chan[ch].ADSRX.DecayRate=(lval>>4) & 0x000f; - s_chan[ch].ADSRX.SustainLevel=lval & 0x000f; - //---------------------------------------------// - } - break; - //------------------------------------------------// adsr times with pre-calcs - case 10: - { - const u32 lval=val; // DEBUG CHECK - - //----------------------------------------------// - s_chan[ch].ADSRX.SustainModeExp = (lval&0x8000)?1:0; - s_chan[ch].ADSRX.SustainIncrease= (lval&0x4000)?0:1; - s_chan[ch].ADSRX.SustainRate = (lval>>6) & 0x007f; - s_chan[ch].ADSRX.ReleaseModeExp = (lval&0x0020)?1:0; - s_chan[ch].ADSRX.ReleaseRate = lval & 0x001f; - //----------------------------------------------// - } - break; - //------------------------------------------------// adsr volume... mmm have to investigate this - //case 0xC: - // break; - //------------------------------------------------// - case 0xE: // loop? - s_chan[ch].pLoop=spuMemC+((u32) val<<3); - s_chan[ch].bIgnoreLoop=1; - break; - //------------------------------------------------// - } - return; - } - - switch(r) - { - //-------------------------------------------------// - case H_SPUaddr: - spuAddr = (u32) val<<3; - break; - //-------------------------------------------------// - case H_SPUdata: - spuMem[spuAddr>>1] = BFLIP16(val); - spuAddr+=2; - if(spuAddr>0x7ffff) spuAddr=0; - break; - //-------------------------------------------------// - case H_SPUctrl: - spuCtrl=val; - break; - //-------------------------------------------------// - case H_SPUstat: - spuStat=val & 0xf800; - break; - //-------------------------------------------------// - case H_SPUReverbAddr: - if(val==0xFFFF || val<=0x200) - {rvb.StartAddr=rvb.CurrAddr=0;} - else - { - const s32 iv=(u32)val<<2; - if(rvb.StartAddr!=iv) - { - rvb.StartAddr=(u32)val<<2; - rvb.CurrAddr=rvb.StartAddr; - } - } - break; - //-------------------------------------------------// - case H_SPUirqAddr: - spuIrq = val; - pSpuIrq=spuMemC+((u32) val<<3); - break; - //-------------------------------------------------// - /* Volume settings appear to be at least 15-bit unsigned in this case. - Definitely NOT 15-bit signed. Probably 16-bit signed, so s16 type cast. - Check out "Chrono Cross: Shadow's End Forest" - */ - case H_SPUrvolL: - rvb.VolLeft=(s16)val; - //printf("%d\n",val); - break; - //-------------------------------------------------// - case H_SPUrvolR: - rvb.VolRight=(s16)val; - //printf("%d\n",val); - break; - //-------------------------------------------------// - -/* - case H_ExtLeft: - //auxprintf("EL %d\n",val); - break; - //-------------------------------------------------// - case H_ExtRight: - //auxprintf("ER %d\n",val); - break; - //-------------------------------------------------// - case H_SPUmvolL: - //auxprintf("ML %d\n",val); - break; - //-------------------------------------------------// - case H_SPUmvolR: - //auxprintf("MR %d\n",val); - break; - //-------------------------------------------------// - case H_SPUMute1: - //printf("M0 %04x\n",val); - break; - //-------------------------------------------------// - case H_SPUMute2: - // printf("M1 %04x\n",val); - break; -*/ - //-------------------------------------------------// - case H_SPUon1: - SoundOn(0,16,val); - break; - //-------------------------------------------------// - case H_SPUon2: - // printf("Boop: %08x: %04x\n",reg,val); - SoundOn(16,24,val); - break; - //-------------------------------------------------// - case H_SPUoff1: - SoundOff(0,16,val); - break; - //-------------------------------------------------// - case H_SPUoff2: - SoundOff(16,24,val); - // printf("Boop: %08x: %04x\n",reg,val); - break; - //-------------------------------------------------// - case H_FMod1: - FModOn(0,16,val); - break; - //-------------------------------------------------// - case H_FMod2: - FModOn(16,24,val); - break; - //-------------------------------------------------// - case H_Noise1: - NoiseOn(0,16,val); - break; - //-------------------------------------------------// - case H_Noise2: - NoiseOn(16,24,val); - break; - //-------------------------------------------------// - case H_RVBon1: - rvb.Enabled&=~0xFFFF; - rvb.Enabled|=val; - break; - - //-------------------------------------------------// - case H_RVBon2: - rvb.Enabled&=0xFFFF; - rvb.Enabled|=val<<16; - break; - - //-------------------------------------------------// - case H_Reverb+0: - rvb.FB_SRC_A=val; - break; - - case H_Reverb+2 : rvb.FB_SRC_B=(s16)val; break; - case H_Reverb+4 : rvb.IIR_ALPHA=(s16)val; break; - case H_Reverb+6 : rvb.ACC_COEF_A=(s16)val; break; - case H_Reverb+8 : rvb.ACC_COEF_B=(s16)val; break; - case H_Reverb+10 : rvb.ACC_COEF_C=(s16)val; break; - case H_Reverb+12 : rvb.ACC_COEF_D=(s16)val; break; - case H_Reverb+14 : rvb.IIR_COEF=(s16)val; break; - case H_Reverb+16 : rvb.FB_ALPHA=(s16)val; break; - case H_Reverb+18 : rvb.FB_X=(s16)val; break; - case H_Reverb+20 : rvb.IIR_DEST_A0=(s16)val; break; - case H_Reverb+22 : rvb.IIR_DEST_A1=(s16)val; break; - case H_Reverb+24 : rvb.ACC_SRC_A0=(s16)val; break; - case H_Reverb+26 : rvb.ACC_SRC_A1=(s16)val; break; - case H_Reverb+28 : rvb.ACC_SRC_B0=(s16)val; break; - case H_Reverb+30 : rvb.ACC_SRC_B1=(s16)val; break; - case H_Reverb+32 : rvb.IIR_SRC_A0=(s16)val; break; - case H_Reverb+34 : rvb.IIR_SRC_A1=(s16)val; break; - case H_Reverb+36 : rvb.IIR_DEST_B0=(s16)val; break; - case H_Reverb+38 : rvb.IIR_DEST_B1=(s16)val; break; - case H_Reverb+40 : rvb.ACC_SRC_C0=(s16)val; break; - case H_Reverb+42 : rvb.ACC_SRC_C1=(s16)val; break; - case H_Reverb+44 : rvb.ACC_SRC_D0=(s16)val; break; - case H_Reverb+46 : rvb.ACC_SRC_D1=(s16)val; break; - case H_Reverb+48 : rvb.IIR_SRC_B1=(s16)val; break; - case H_Reverb+50 : rvb.IIR_SRC_B0=(s16)val; break; - case H_Reverb+52 : rvb.MIX_DEST_A0=(s16)val; break; - case H_Reverb+54 : rvb.MIX_DEST_A1=(s16)val; break; - case H_Reverb+56 : rvb.MIX_DEST_B0=(s16)val; break; - case H_Reverb+58 : rvb.MIX_DEST_B1=(s16)val; break; - case H_Reverb+60 : rvb.IN_COEF_L=(s16)val; break; - case H_Reverb+62 : rvb.IN_COEF_R=(s16)val; break; - } - -} - -//////////////////////////////////////////////////////////////////////// -// READ REGISTER: called by main emu -//////////////////////////////////////////////////////////////////////// - -u16 SPUreadRegister(u32 reg) -{ - const u32 r=reg&0xfff; - - if(r>=0x0c00 && r<0x0d80) - { - switch(r&0x0f) - { - case 0xC: // get adsr vol - { - const int ch=(r>>4)-0xc0; - if(s_chan[ch].bNew) return 1; // we are started, but not processed? return 1 - if(s_chan[ch].ADSRX.lVolume && // same here... we haven't decoded one sample yet, so no envelope yet. return 1 as well - !s_chan[ch].ADSRX.EnvelopeVol) - return 1; - return (u16)(s_chan[ch].ADSRX.EnvelopeVol>>16); - } - - case 0xE: // get loop address - { - const int ch=(r>>4)-0xc0; - if(s_chan[ch].pLoop==NULL) return 0; - return (u16)((s_chan[ch].pLoop-spuMemC)>>3); - } - } - } - - switch(r) - { - case H_SPUctrl: - return spuCtrl; - - case H_SPUstat: - return spuStat; - - case H_SPUaddr: - return (u16)(spuAddr>>3); - - case H_SPUdata: - { - u16 s=BFLIP16(spuMem[spuAddr>>1]); - spuAddr+=2; - if(spuAddr>0x7ffff) spuAddr=0; - return s; - } - - case H_SPUirqAddr: - return spuIrq; - - //case H_SPUIsOn1: - // return IsSoundOn(0,16); - - //case H_SPUIsOn2: - // return IsSoundOn(16,24); - - } - - return regArea[(r-0xc00)>>1]; -} - -//////////////////////////////////////////////////////////////////////// -// SOUND ON register write -//////////////////////////////////////////////////////////////////////// - -static void SoundOn(int start,int end,u16 val) // SOUND ON PSX COMAND -{ - int ch; - - for(ch=start;ch>=1) // loop channels - { - if((val&1) && s_chan[ch].pStart) // mmm... start has to be set before key on !?! - { - s_chan[ch].bIgnoreLoop=0; - s_chan[ch].bNew=1; - } - } -} - -//////////////////////////////////////////////////////////////////////// -// SOUND OFF register write -//////////////////////////////////////////////////////////////////////// - -static void SoundOff(int start,int end,u16 val) // SOUND OFF PSX COMMAND -{ - int ch; - for(ch=start;ch>=1) // loop channels - { - if(val&1) // && s_chan[i].bOn) mmm... - { - s_chan[ch].bStop=1; - } - } -} - -//////////////////////////////////////////////////////////////////////// -// FMOD register write -//////////////////////////////////////////////////////////////////////// - -static void FModOn(int start,int end,u16 val) // FMOD ON PSX COMMAND -{ - int ch; - - for(ch=start;ch>=1) // loop channels - { - if(val&1) // -> fmod on/off - { - if(ch>0) - { - s_chan[ch].bFMod=1; // --> sound channel - s_chan[ch-1].bFMod=2; // --> freq channel - } - } - else - { - s_chan[ch].bFMod=0; // --> turn off fmod - } - } -} - -//////////////////////////////////////////////////////////////////////// -// NOISE register write -//////////////////////////////////////////////////////////////////////// - -static void NoiseOn(int start,int end,u16 val) // NOISE ON PSX COMMAND -{ - int ch; - - for(ch=start;ch>=1) // loop channels - { - if(val&1) // -> noise on/off - { - s_chan[ch].bNoise=1; - } - else - { - s_chan[ch].bNoise=0; - } - } -} - -//////////////////////////////////////////////////////////////////////// -// LEFT VOLUME register write -//////////////////////////////////////////////////////////////////////// - -// please note: sweep is wrong. - -static void SetVolumeLR(int right, u8 ch,s16 vol) // LEFT VOLUME -{ - //if(vol&0xc000) - //printf("%d %08x\n",right,vol); - if(right) - s_chan[ch].iRightVolRaw=vol; - else - s_chan[ch].iLeftVolRaw=vol; - - if(vol&0x8000) // sweep? - { - s16 sInc=1; // -> sweep up? - if(vol&0x2000) sInc=-1; // -> or down? - if(vol&0x1000) vol^=0xffff; // -> mmm... phase inverted? have to investigate this - vol=((vol&0x7f)+1)/2; // -> sweep: 0..127 -> 0..64 - vol+=vol/(2*sInc); // -> HACK: we don't sweep right now, so we just raise/lower the volume by the half! - vol*=128; - vol&=0x3fff; - //puts("Sweep"); - } - else // no sweep: - { - if(vol&0x4000) - vol=(vol&0x3FFF)-0x4000; - else - vol&=0x3FFF; - - //if(vol&0x4000) // -> mmm... phase inverted? have to investigate this - // vol=0-(0x3fff-(vol&0x3fff)); - //else - // vol&=0x3fff; - } - if(right) - s_chan[ch].iRightVolume=vol; - else - s_chan[ch].iLeftVolume=vol; // store volume -} - -//////////////////////////////////////////////////////////////////////// -// PITCH register write -//////////////////////////////////////////////////////////////////////// - -static void SetPitch(int ch,u16 val) // SET PITCH -{ - int NP; - if(val>0x3fff) NP=0x3fff; // get pitch val - else NP=val; - - s_chan[ch].iRawPitch=NP; - - NP=(44100L*NP)/4096L; // calc frequency - if(NP<1) NP=1; // some security - s_chan[ch].iActFreq=NP; // store frequency -} diff --git a/Frameworks/AudioOverload/aosdk/eng_psf/peops/registers.h b/Frameworks/AudioOverload/aosdk/eng_psf/peops/registers.h deleted file mode 100644 index dc453cfac..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_psf/peops/registers.h +++ /dev/null @@ -1,153 +0,0 @@ -/*************************************************************************** - registers.h - description - ------------------- - begin : Wed May 15 2002 - copyright : (C) 2002 by Pete Bernert - email : BlackDove@addcom.de - ***************************************************************************/ - -/*************************************************************************** - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. See also the license.txt file for * - * additional informations. * - * * - ***************************************************************************/ - -//*************************************************************************// -// History of changes: -// -// 2002/05/15 - Pete -// - generic cleanup for the Peops release -// -//*************************************************************************// - -#define H_SPUReverbAddr 0x0da2 -#define H_SPUirqAddr 0x0da4 -#define H_SPUaddr 0x0da6 -#define H_SPUdata 0x0da8 -#define H_SPUctrl 0x0daa -#define H_SPUstat 0x0dae -#define H_SPUmvolL 0x0d80 -#define H_SPUmvolR 0x0d82 -#define H_SPUrvolL 0x0d84 -#define H_SPUrvolR 0x0d86 -#define H_SPUon1 0x0d88 -#define H_SPUon2 0x0d8a -#define H_SPUoff1 0x0d8c -#define H_SPUoff2 0x0d8e -#define H_FMod1 0x0d90 -#define H_FMod2 0x0d92 -#define H_Noise1 0x0d94 -#define H_Noise2 0x0d96 -#define H_RVBon1 0x0d98 -#define H_RVBon2 0x0d9a -#define H_SPUMute1 0x0d9c -#define H_SPUMute2 0x0d9e -#define H_CDLeft 0x0db0 -#define H_CDRight 0x0db2 -#define H_ExtLeft 0x0db4 -#define H_ExtRight 0x0db6 -#define H_Reverb 0x0dc0 -#define H_SPUPitch0 0x0c04 -#define H_SPUPitch1 0x0c14 -#define H_SPUPitch2 0x0c24 -#define H_SPUPitch3 0x0c34 -#define H_SPUPitch4 0x0c44 -#define H_SPUPitch5 0x0c54 -#define H_SPUPitch6 0x0c64 -#define H_SPUPitch7 0x0c74 -#define H_SPUPitch8 0x0c84 -#define H_SPUPitch9 0x0c94 -#define H_SPUPitch10 0x0ca4 -#define H_SPUPitch11 0x0cb4 -#define H_SPUPitch12 0x0cc4 -#define H_SPUPitch13 0x0cd4 -#define H_SPUPitch14 0x0ce4 -#define H_SPUPitch15 0x0cf4 -#define H_SPUPitch16 0x0d04 -#define H_SPUPitch17 0x0d14 -#define H_SPUPitch18 0x0d24 -#define H_SPUPitch19 0x0d34 -#define H_SPUPitch20 0x0d44 -#define H_SPUPitch21 0x0d54 -#define H_SPUPitch22 0x0d64 -#define H_SPUPitch23 0x0d74 - -#define H_SPUStartAdr0 0x0c06 -#define H_SPUStartAdr1 0x0c16 -#define H_SPUStartAdr2 0x0c26 -#define H_SPUStartAdr3 0x0c36 -#define H_SPUStartAdr4 0x0c46 -#define H_SPUStartAdr5 0x0c56 -#define H_SPUStartAdr6 0x0c66 -#define H_SPUStartAdr7 0x0c76 -#define H_SPUStartAdr8 0x0c86 -#define H_SPUStartAdr9 0x0c96 -#define H_SPUStartAdr10 0x0ca6 -#define H_SPUStartAdr11 0x0cb6 -#define H_SPUStartAdr12 0x0cc6 -#define H_SPUStartAdr13 0x0cd6 -#define H_SPUStartAdr14 0x0ce6 -#define H_SPUStartAdr15 0x0cf6 -#define H_SPUStartAdr16 0x0d06 -#define H_SPUStartAdr17 0x0d16 -#define H_SPUStartAdr18 0x0d26 -#define H_SPUStartAdr19 0x0d36 -#define H_SPUStartAdr20 0x0d46 -#define H_SPUStartAdr21 0x0d56 -#define H_SPUStartAdr22 0x0d66 -#define H_SPUStartAdr23 0x0d76 - -#define H_SPULoopAdr0 0x0c0e -#define H_SPULoopAdr1 0x0c1e -#define H_SPULoopAdr2 0x0c2e -#define H_SPULoopAdr3 0x0c3e -#define H_SPULoopAdr4 0x0c4e -#define H_SPULoopAdr5 0x0c5e -#define H_SPULoopAdr6 0x0c6e -#define H_SPULoopAdr7 0x0c7e -#define H_SPULoopAdr8 0x0c8e -#define H_SPULoopAdr9 0x0c9e -#define H_SPULoopAdr10 0x0cae -#define H_SPULoopAdr11 0x0cbe -#define H_SPULoopAdr12 0x0cce -#define H_SPULoopAdr13 0x0cde -#define H_SPULoopAdr14 0x0cee -#define H_SPULoopAdr15 0x0cfe -#define H_SPULoopAdr16 0x0d0e -#define H_SPULoopAdr17 0x0d1e -#define H_SPULoopAdr18 0x0d2e -#define H_SPULoopAdr19 0x0d3e -#define H_SPULoopAdr20 0x0d4e -#define H_SPULoopAdr21 0x0d5e -#define H_SPULoopAdr22 0x0d6e -#define H_SPULoopAdr23 0x0d7e - -#define H_SPU_ADSRLevel0 0x0c08 -#define H_SPU_ADSRLevel1 0x0c18 -#define H_SPU_ADSRLevel2 0x0c28 -#define H_SPU_ADSRLevel3 0x0c38 -#define H_SPU_ADSRLevel4 0x0c48 -#define H_SPU_ADSRLevel5 0x0c58 -#define H_SPU_ADSRLevel6 0x0c68 -#define H_SPU_ADSRLevel7 0x0c78 -#define H_SPU_ADSRLevel8 0x0c88 -#define H_SPU_ADSRLevel9 0x0c98 -#define H_SPU_ADSRLevel10 0x0ca8 -#define H_SPU_ADSRLevel11 0x0cb8 -#define H_SPU_ADSRLevel12 0x0cc8 -#define H_SPU_ADSRLevel13 0x0cd8 -#define H_SPU_ADSRLevel14 0x0ce8 -#define H_SPU_ADSRLevel15 0x0cf8 -#define H_SPU_ADSRLevel16 0x0d08 -#define H_SPU_ADSRLevel17 0x0d18 -#define H_SPU_ADSRLevel18 0x0d28 -#define H_SPU_ADSRLevel19 0x0d38 -#define H_SPU_ADSRLevel20 0x0d48 -#define H_SPU_ADSRLevel21 0x0d58 -#define H_SPU_ADSRLevel22 0x0d68 -#define H_SPU_ADSRLevel23 0x0d78 - diff --git a/Frameworks/AudioOverload/aosdk/eng_psf/peops/regs.h b/Frameworks/AudioOverload/aosdk/eng_psf/peops/regs.h deleted file mode 100644 index e46755475..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_psf/peops/regs.h +++ /dev/null @@ -1,34 +0,0 @@ -/*************************************************************************** - regs.h - description - ------------------- - begin : Wed May 15 2002 - copyright : (C) 2002 by Pete Bernert - email : BlackDove@addcom.de - ***************************************************************************/ - -/*************************************************************************** - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. See also the license.txt file for * - * additional informations. * - * * - ***************************************************************************/ - -//*************************************************************************// -// History of changes: -// -// 2002/05/15 - Pete -// - generic cleanup for the Peops release -// -//*************************************************************************// - - -static void SoundOn(int start,int end,u16 val); -static void SoundOff(int start,int end,u16 val); -static void FModOn(int start,int end,u16 val); -static void NoiseOn(int start,int end,u16 val); -static void SetVolumeLR(int right, u8 ch,s16 vol); -static void SetPitch(int ch,u16 val); -void SPUwriteRegister(u32 reg, u16 val); diff --git a/Frameworks/AudioOverload/aosdk/eng_psf/peops/reverb.c b/Frameworks/AudioOverload/aosdk/eng_psf/peops/reverb.c deleted file mode 100644 index aa27f33c2..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_psf/peops/reverb.c +++ /dev/null @@ -1,383 +0,0 @@ -/*************************************************************************** - reverb.c - description - ------------------- - begin : Wed May 15 2002 - copyright : (C) 2002 by Pete Bernert - email : BlackDove@addcom.de - ***************************************************************************/ - -/*************************************************************************** - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. See also the license.txt file for * - * additional informations. * - * * - ***************************************************************************/ - -//*************************************************************************// -// History of changes: -// -// 2003/03/17 - xodnizel -// - Implemented Neill's 44.1Khz-22050Hz downsampling data -// I also need to check if the ~4 sample delay doesn't screw any sounds -// up by making things too out of phase. It could be fixed easily(elsewhere). -// -// 2003/01/19 - Pete -// - added Neill's reverb (see at the end of file) -// -// 2002/12/26 - Pete -// - adjusted reverb handling -// -// 2002/08/14 - Pete -// - added extra reverb -// -// 2002/05/15 - Pete -// - generic cleanup for the Peops release -// -//*************************************************************************// - -#define _IN_REVERB - -// will be included from spu.c -#ifdef _IN_SPU - -//////////////////////////////////////////////////////////////////////// -// globals -//////////////////////////////////////////////////////////////////////// - -// REVERB info and timing vars... - -//////////////////////////////////////////////////////////////////////// - -static INLINE s64 g_buffer(int iOff) // get_buffer content helper: takes care about wraps -{ - s16 * p=(s16 *)spuMem; - iOff=(iOff*4)+rvb.CurrAddr; - while(iOff>0x3FFFF) iOff=rvb.StartAddr+(iOff-0x40000); - while(iOff0x3FFFF) iOff=rvb.StartAddr+(iOff-0x40000); - while(iOff32767L) iVal=32767L; - *(p+iOff)=(s16)BFLIP16((s16)iVal); -} - -//////////////////////////////////////////////////////////////////////// - -static INLINE void s_buffer1(int iOff,int iVal) // set_buffer (+1 sample) content helper: takes care about wraps and clipping -{ - s16 * p=(s16 *)spuMem; - iOff=(iOff*4)+rvb.CurrAddr+1; - while(iOff>0x3FFFF) iOff=rvb.StartAddr+(iOff-0x40000); - while(iOff32767L) iVal=32767L; - *(p+iOff)=(s16)BFLIP16((s16)iVal); -} - -static INLINE void MixREVERBLeftRight(s32 *oleft, s32 *oright, s32 inleft, s32 inright) -{ - static s32 downbuf[2][8]; - static s32 upbuf[2][8]; - static int dbpos=0,ubpos=0; - static s32 downcoeffs[8]={ /* Symmetry is sexy. */ - 1283,5344,10895,15243, - 15243,10895,5344,1283 - }; - int x; - - if(!rvb.StartAddr) // reverb is off - { - rvb.iRVBLeft=rvb.iRVBRight=0; - return; - } - - //if(inleft<-32767 || inleft>32767) printf("%d\n",inleft); - //if(inright<-32767 || inright>32767) printf("%d\n",inright); - downbuf[0][dbpos]=inleft; - downbuf[1][dbpos]=inright; - dbpos=(dbpos+1)&7; - - if(dbpos&1) // we work on every second left value: downsample to 22 khz - { - if(spuCtrl&0x80) // -> reverb on? oki - { - int ACC0,ACC1,FB_A0,FB_A1,FB_B0,FB_B1; - s32 INPUT_SAMPLE_L=0; - s32 INPUT_SAMPLE_R=0; - - for(x=0;x<8;x++) - { - INPUT_SAMPLE_L+=(downbuf[0][(dbpos+x)&7]*downcoeffs[x])>>8; /* Lose insignificant - digits to prevent - overflow(check this) */ - INPUT_SAMPLE_R+=(downbuf[1][(dbpos+x)&7]*downcoeffs[x])>>8; - } - - INPUT_SAMPLE_L>>=(16-8); - INPUT_SAMPLE_R>>=(16-8); - { - const s64 IIR_INPUT_A0 = ((g_buffer(rvb.IIR_SRC_A0) * rvb.IIR_COEF)>>15) + ((INPUT_SAMPLE_L * rvb.IN_COEF_L)>>15); - const s64 IIR_INPUT_A1 = ((g_buffer(rvb.IIR_SRC_A1) * rvb.IIR_COEF)>>15) + ((INPUT_SAMPLE_R * rvb.IN_COEF_R)>>15); - const s64 IIR_INPUT_B0 = ((g_buffer(rvb.IIR_SRC_B0) * rvb.IIR_COEF)>>15) + ((INPUT_SAMPLE_L * rvb.IN_COEF_L)>>15); - const s64 IIR_INPUT_B1 = ((g_buffer(rvb.IIR_SRC_B1) * rvb.IIR_COEF)>>15) + ((INPUT_SAMPLE_R * rvb.IN_COEF_R)>>15); - const s64 IIR_A0 = ((IIR_INPUT_A0 * rvb.IIR_ALPHA)>>15) + ((g_buffer(rvb.IIR_DEST_A0) * (32768L - rvb.IIR_ALPHA))>>15); - const s64 IIR_A1 = ((IIR_INPUT_A1 * rvb.IIR_ALPHA)>>15) + ((g_buffer(rvb.IIR_DEST_A1) * (32768L - rvb.IIR_ALPHA))>>15); - const s64 IIR_B0 = ((IIR_INPUT_B0 * rvb.IIR_ALPHA)>>15) + ((g_buffer(rvb.IIR_DEST_B0) * (32768L - rvb.IIR_ALPHA))>>15); - const s64 IIR_B1 = ((IIR_INPUT_B1 * rvb.IIR_ALPHA)>>15) + ((g_buffer(rvb.IIR_DEST_B1) * (32768L - rvb.IIR_ALPHA))>>15); - - s_buffer1(rvb.IIR_DEST_A0, IIR_A0); - s_buffer1(rvb.IIR_DEST_A1, IIR_A1); - s_buffer1(rvb.IIR_DEST_B0, IIR_B0); - s_buffer1(rvb.IIR_DEST_B1, IIR_B1); - - ACC0 = ((g_buffer(rvb.ACC_SRC_A0) * rvb.ACC_COEF_A)>>15) + - ((g_buffer(rvb.ACC_SRC_B0) * rvb.ACC_COEF_B)>>15) + - ((g_buffer(rvb.ACC_SRC_C0) * rvb.ACC_COEF_C)>>15) + - ((g_buffer(rvb.ACC_SRC_D0) * rvb.ACC_COEF_D)>>15); - ACC1 = ((g_buffer(rvb.ACC_SRC_A1) * rvb.ACC_COEF_A)>>15) + - ((g_buffer(rvb.ACC_SRC_B1) * rvb.ACC_COEF_B)>>15) + - ((g_buffer(rvb.ACC_SRC_C1) * rvb.ACC_COEF_C)>>15) + - ((g_buffer(rvb.ACC_SRC_D1) * rvb.ACC_COEF_D)>>15); - - FB_A0 = g_buffer(rvb.MIX_DEST_A0 - rvb.FB_SRC_A); - FB_A1 = g_buffer(rvb.MIX_DEST_A1 - rvb.FB_SRC_A); - FB_B0 = g_buffer(rvb.MIX_DEST_B0 - rvb.FB_SRC_B); - FB_B1 = g_buffer(rvb.MIX_DEST_B1 - rvb.FB_SRC_B); - - s_buffer(rvb.MIX_DEST_A0, ACC0 - ((FB_A0 * rvb.FB_ALPHA)>>15)); - s_buffer(rvb.MIX_DEST_A1, ACC1 - ((FB_A1 * rvb.FB_ALPHA)>>15)); - - s_buffer(rvb.MIX_DEST_B0, ((rvb.FB_ALPHA * ACC0)>>15) - ((FB_A0 * (int)(rvb.FB_ALPHA^0xFFFF8000))>>15) - ((FB_B0 * rvb.FB_X)>>15)); - s_buffer(rvb.MIX_DEST_B1, ((rvb.FB_ALPHA * ACC1)>>15) - ((FB_A1 * (int)(rvb.FB_ALPHA^0xFFFF8000))>>15) - ((FB_B1 * rvb.FB_X)>>15)); - - rvb.iRVBLeft = (g_buffer(rvb.MIX_DEST_A0)+g_buffer(rvb.MIX_DEST_B0))/3; - rvb.iRVBRight = (g_buffer(rvb.MIX_DEST_A1)+g_buffer(rvb.MIX_DEST_B1))/3; - - rvb.iRVBLeft = ((s64)rvb.iRVBLeft * rvb.VolLeft) >> 14; - rvb.iRVBRight = ((s64)rvb.iRVBRight * rvb.VolRight) >> 14; - - upbuf[0][ubpos]=rvb.iRVBLeft; - upbuf[1][ubpos]=rvb.iRVBRight; - ubpos=(ubpos+1)&7; - } // Bracket hack(et). - } - else // -> reverb off - { - rvb.iRVBLeft=rvb.iRVBRight=0; - return; - } - rvb.CurrAddr++; - if(rvb.CurrAddr>0x3ffff) rvb.CurrAddr=rvb.StartAddr; - } - else - { - upbuf[0][ubpos]=0; - upbuf[1][ubpos]=0; - ubpos=(ubpos+1)&7; - } - { - s32 retl=0,retr=0; - for(x=0;x<8;x++) - { - retl+=(upbuf[0][(ubpos+x)&7]*downcoeffs[x])>>8; - retr+=(upbuf[1][(ubpos+x)&7]*downcoeffs[x])>>8; - } - retl>>=(16-8-1); /* -1 To adjust for the null padding. */ - retr>>=(16-8-1); - - *oleft+=retl; - *oright+=retr; - } -} - -//////////////////////////////////////////////////////////////////////// - -#endif - -/* ------------------------------------------------------------------------------ -PSX reverb hardware notes -by Neill Corlett ------------------------------------------------------------------------------ - -Yadda yadda disclaimer yadda probably not perfect yadda well it's okay anyway -yadda yadda. - ------------------------------------------------------------------------------ - -Basics ------- - -- The reverb buffer is 22khz 16-bit mono PCM. -- It starts at the reverb address given by 1DA2, extends to - the end of sound RAM, and wraps back to the 1DA2 address. - -Setting the address at 1DA2 resets the current reverb work address. - -This work address ALWAYS increments every 1/22050 sec., regardless of -whether reverb is enabled (bit 7 of 1DAA set). - -And the contents of the reverb buffer ALWAYS play, scaled by the -"reverberation depth left/right" volumes (1D84/1D86). -(which, by the way, appear to be scaled so 3FFF=approx. 1.0, 4000=-1.0) - ------------------------------------------------------------------------------ - -Register names --------------- - -These are probably not their real names. -These are probably not even correct names. -We will use them anyway, because we can. - -1DC0: FB_SRC_A (offset) -1DC2: FB_SRC_B (offset) -1DC4: IIR_ALPHA (coef.) -1DC6: ACC_COEF_A (coef.) -1DC8: ACC_COEF_B (coef.) -1DCA: ACC_COEF_C (coef.) -1DCC: ACC_COEF_D (coef.) -1DCE: IIR_COEF (coef.) -1DD0: FB_ALPHA (coef.) -1DD2: FB_X (coef.) -1DD4: IIR_DEST_A0 (offset) -1DD6: IIR_DEST_A1 (offset) -1DD8: ACC_SRC_A0 (offset) -1DDA: ACC_SRC_A1 (offset) -1DDC: ACC_SRC_B0 (offset) -1DDE: ACC_SRC_B1 (offset) -1DE0: IIR_SRC_A0 (offset) -1DE2: IIR_SRC_A1 (offset) -1DE4: IIR_DEST_B0 (offset) -1DE6: IIR_DEST_B1 (offset) -1DE8: ACC_SRC_C0 (offset) -1DEA: ACC_SRC_C1 (offset) -1DEC: ACC_SRC_D0 (offset) -1DEE: ACC_SRC_D1 (offset) -1DF0: IIR_SRC_B1 (offset) -1DF2: IIR_SRC_B0 (offset) -1DF4: MIX_DEST_A0 (offset) -1DF6: MIX_DEST_A1 (offset) -1DF8: MIX_DEST_B0 (offset) -1DFA: MIX_DEST_B1 (offset) -1DFC: IN_COEF_L (coef.) -1DFE: IN_COEF_R (coef.) - -The coefficients are signed fractional values. --32768 would be -1.0 - 32768 would be 1.0 (if it were possible... the highest is of course 32767) - -The offsets are (byte/8) offsets into the reverb buffer. -i.e. you multiply them by 8, you get byte offsets. -You can also think of them as (samples/4) offsets. -They appear to be signed. They can be negative. -None of the documented presets make them negative, though. - -Yes, 1DF0 and 1DF2 appear to be backwards. Not a typo. - ------------------------------------------------------------------------------ - -What it does ------------- - -We take all reverb sources: -- regular channels that have the reverb bit on -- cd and external sources, if their reverb bits are on -and mix them into one stereo 44100hz signal. - -Lowpass/downsample that to 22050hz. The PSX uses a proper bandlimiting -algorithm here, but I haven't figured out the hysterically exact specifics. -I use an 8-tap filter with these coefficients, which are nice but probably -not the real ones: - -0.037828187894 -0.157538631280 -0.321159685278 -0.449322115345 -0.449322115345 -0.321159685278 -0.157538631280 -0.037828187894 - -So we have two input samples (INPUT_SAMPLE_L, INPUT_SAMPLE_R) every 22050hz. - -* IN MY EMULATION, I divide these by 2 to make it clip less. - (and of course the L/R output coefficients are adjusted to compensate) - The real thing appears to not do this. - -At every 22050hz tick: -- If the reverb bit is enabled (bit 7 of 1DAA), execute the reverb - steady-state algorithm described below -- AFTERWARDS, retrieve the "wet out" L and R samples from the reverb buffer - (This part may not be exactly right and I guessed at the coefs. TODO: check later.) - L is: 0.333 * (buffer[MIX_DEST_A0] + buffer[MIX_DEST_B0]) - R is: 0.333 * (buffer[MIX_DEST_A1] + buffer[MIX_DEST_B1]) -- Advance the current buffer position by 1 sample - -The wet out L and R are then upsampled to 44100hz and played at the -"reverberation depth left/right" (1D84/1D86) volume, independent of the main -volume. - ------------------------------------------------------------------------------ - -Reverb steady-state -------------------- - -The reverb steady-state algorithm is fairly clever, and of course by -"clever" I mean "batshit insane". - -buffer[x] is relative to the current buffer position, not the beginning of -the buffer. Note that all buffer offsets must wrap around so they're -contained within the reverb work area. - -Clipping is performed at the end... maybe also sooner, but definitely at -the end. - -IIR_INPUT_A0 = buffer[IIR_SRC_A0] * IIR_COEF + INPUT_SAMPLE_L * IN_COEF_L; -IIR_INPUT_A1 = buffer[IIR_SRC_A1] * IIR_COEF + INPUT_SAMPLE_R * IN_COEF_R; -IIR_INPUT_B0 = buffer[IIR_SRC_B0] * IIR_COEF + INPUT_SAMPLE_L * IN_COEF_L; -IIR_INPUT_B1 = buffer[IIR_SRC_B1] * IIR_COEF + INPUT_SAMPLE_R * IN_COEF_R; - -IIR_A0 = IIR_INPUT_A0 * IIR_ALPHA + buffer[IIR_DEST_A0] * (1.0 - IIR_ALPHA); -IIR_A1 = IIR_INPUT_A1 * IIR_ALPHA + buffer[IIR_DEST_A1] * (1.0 - IIR_ALPHA); -IIR_B0 = IIR_INPUT_B0 * IIR_ALPHA + buffer[IIR_DEST_B0] * (1.0 - IIR_ALPHA); -IIR_B1 = IIR_INPUT_B1 * IIR_ALPHA + buffer[IIR_DEST_B1] * (1.0 - IIR_ALPHA); - -buffer[IIR_DEST_A0 + 1sample] = IIR_A0; -buffer[IIR_DEST_A1 + 1sample] = IIR_A1; -buffer[IIR_DEST_B0 + 1sample] = IIR_B0; -buffer[IIR_DEST_B1 + 1sample] = IIR_B1; - -ACC0 = buffer[ACC_SRC_A0] * ACC_COEF_A + - buffer[ACC_SRC_B0] * ACC_COEF_B + - buffer[ACC_SRC_C0] * ACC_COEF_C + - buffer[ACC_SRC_D0] * ACC_COEF_D; -ACC1 = buffer[ACC_SRC_A1] * ACC_COEF_A + - buffer[ACC_SRC_B1] * ACC_COEF_B + - buffer[ACC_SRC_C1] * ACC_COEF_C + - buffer[ACC_SRC_D1] * ACC_COEF_D; - -FB_A0 = buffer[MIX_DEST_A0 - FB_SRC_A]; -FB_A1 = buffer[MIX_DEST_A1 - FB_SRC_A]; -FB_B0 = buffer[MIX_DEST_B0 - FB_SRC_B]; -FB_B1 = buffer[MIX_DEST_B1 - FB_SRC_B]; - -buffer[MIX_DEST_A0] = ACC0 - FB_A0 * FB_ALPHA; -buffer[MIX_DEST_A1] = ACC1 - FB_A1 * FB_ALPHA; -buffer[MIX_DEST_B0] = (FB_ALPHA * ACC0) - FB_A0 * (FB_ALPHA^0x8000) - FB_B0 * FB_X; -buffer[MIX_DEST_B1] = (FB_ALPHA * ACC1) - FB_A1 * (FB_ALPHA^0x8000) - FB_B1 * FB_X; - ------------------------------------------------------------------------------ -*/ - diff --git a/Frameworks/AudioOverload/aosdk/eng_psf/peops/spu.c b/Frameworks/AudioOverload/aosdk/eng_psf/peops/spu.c deleted file mode 100644 index dc2f5b27c..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_psf/peops/spu.c +++ /dev/null @@ -1,641 +0,0 @@ -/*************************************************************************** - spu.c - description - ------------------- - begin : Wed May 15 2002 - copyright : (C) 2002 by Pete Bernert - email : BlackDove@addcom.de - ***************************************************************************/ - -/*************************************************************************** - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. See also the license.txt file for * - * additional informations. * - * * - ***************************************************************************/ - -//*************************************************************************// -// History of changes: -// -// 2003/03/01 - linuzappz -// - libraryName changes using ALSA -// -// 2003/02/28 - Pete -// - added option for type of interpolation -// - adjusted spu irqs again (Thousant Arms, Valkyrie Profile) -// - added MONO support for MSWindows DirectSound -// -// 2003/02/20 - kode54 -// - amended interpolation code, goto GOON could skip initialization of gpos and cause segfault -// -// 2003/02/19 - kode54 -// - moved SPU IRQ handler and changed sample flag processing -// -// 2003/02/18 - kode54 -// - moved ADSR calculation outside of the sample decode loop, somehow I doubt that -// ADSR timing is relative to the frequency at which a sample is played... I guess -// this remains to be seen, and I don't know whether ADSR is applied to noise channels... -// -// 2003/02/09 - kode54 -// - one-shot samples now process the end block before stopping -// - in light of removing fmod hack, now processing ADSR on frequency channel as well -// -// 2003/02/08 - kode54 -// - replaced easy interpolation with gaussian -// - removed fmod averaging hack -// - changed .sinc to be updated from .iRawPitch, no idea why it wasn't done this way already (<- Pete: because I sometimes fail to see the obvious, haharhar :) -// -// 2003/02/08 - linuzappz -// - small bugfix for one usleep that was 1 instead of 1000 -// - added iDisStereo for no stereo (Linux) -// -// 2003/01/22 - Pete -// - added easy interpolation & small noise adjustments -// -// 2003/01/19 - Pete -// - added Neill's reverb -// -// 2003/01/12 - Pete -// - added recording window handlers -// -// 2003/01/06 - Pete -// - added Neill's ADSR timings -// -// 2002/12/28 - Pete -// - adjusted spu irq handling, fmod handling and loop handling -// -// 2002/08/14 - Pete -// - added extra reverb -// -// 2002/06/08 - linuzappz -// - SPUupdate changed for SPUasync -// -// 2002/05/15 - Pete -// - generic cleanup for the Peops release -// -//*************************************************************************// - -#define _IN_SPU - -#include "../peops/stdafx.h" -#include "../peops/externals.h" -#include "../peops/regs.h" -#include "../peops/registers.h" -#include "../peops/spu.h" - -void SPUirq(void) ; - -//#include "PsxMem.h" -//#include "driver.h" - -//////////////////////////////////////////////////////////////////////// -// globals -//////////////////////////////////////////////////////////////////////// - -// psx buffer / addresses - -static u16 regArea[0x200]; -static u16 spuMem[256*1024]; -static u8 * spuMemC; -static u8 * pSpuIrq=0; -static u8 * pSpuBuffer; - -// user settings -static int iVolume; - -// MAIN infos struct for each channel - -static SPUCHAN s_chan[MAXCHAN+1]; // channel + 1 infos (1 is security for fmod handling) -static REVERBInfo rvb; - -static u32 dwNoiseVal=1; // global noise generator - -static u16 spuCtrl=0; // some vars to store psx reg infos -static u16 spuStat=0; -static u16 spuIrq=0; -static u32 spuAddr=0xffffffff; // address into spu mem -static int bSPUIsOpen=0; - -static const int f[5][2] = { - { 0, 0 }, - { 60, 0 }, - { 115, -52 }, - { 98, -55 }, - { 122, -60 } }; -s16 * pS; -static s32 ttemp; - -//////////////////////////////////////////////////////////////////////// -// CODE AREA -//////////////////////////////////////////////////////////////////////// - -// dirty inline func includes - -#include "../peops/reverb.c" -#include "../peops/adsr.c" - -// Try this to increase speed. -#include "../peops/registers.c" -#include "../peops/dma.c" - -//////////////////////////////////////////////////////////////////////// -// helpers for so-called "gauss interpolation" - -#define gval0 (((int *)(&s_chan[ch].SB[29]))[gpos]) -#define gval(x) (((int *)(&s_chan[ch].SB[29]))[(gpos+x)&3]) - -#include "gauss_i.h" - -//////////////////////////////////////////////////////////////////////// - -//////////////////////////////////////////////////////////////////////// -// START SOUND... called by main thread to setup a new sound on a channel -//////////////////////////////////////////////////////////////////////// - -static INLINE void StartSound(int ch) -{ - StartADSR(ch); - - s_chan[ch].pCurr=s_chan[ch].pStart; // set sample start - - s_chan[ch].s_1=0; // init mixing vars - s_chan[ch].s_2=0; - s_chan[ch].iSBPos=28; - - s_chan[ch].bNew=0; // init channel flags - s_chan[ch].bStop=0; - s_chan[ch].bOn=1; - - s_chan[ch].SB[29]=0; // init our interpolation helpers - s_chan[ch].SB[30]=0; - - s_chan[ch].spos=0x40000L;s_chan[ch].SB[28]=0; // -> start with more decoding -} - -//////////////////////////////////////////////////////////////////////// -// MAIN SPU FUNCTION -// here is the main job handler... thread, timer or direct func call -// basically the whole sound processing is done in this fat func! -//////////////////////////////////////////////////////////////////////// - -static u32 sampcount; -static u32 decaybegin; -static u32 decayend; - -// Counting to 65536 results in full volume offage. -void setlength(s32 stop, s32 fade) -{ - if(stop==~0) - { - decaybegin=~0; - } - else - { - stop=(stop*441)/10; - fade=(fade*441)/10; - - decaybegin=stop; - decayend=stop+fade; - } -} - -#define CLIP(_x) {if(_x>32767) _x=32767; if(_x<-32767) _x=-32767;} -int SPUasync(u32 cycles) -{ - int volmul=iVolume; - static s32 dosampies; - s32 temp; - - ttemp+=cycles; - dosampies=ttemp/384; - if(!dosampies) return(1); - ttemp-=dosampies*384; - temp=dosampies; - - while(temp) - { - s32 revLeft=0, revRight=0; - s32 sl=0, sr=0; - int ch,fa; - - temp--; - //--------------------------------------------------// - //- main channel loop -// - //--------------------------------------------------// - { - for(ch=0;ch take it and calc steps - s_chan[ch].sinc=s_chan[ch].iRawPitch<<4; - if(!s_chan[ch].sinc) s_chan[ch].sinc=1; - } - - while(s_chan[ch].spos>=0x10000L) - { - if(s_chan[ch].iSBPos==28) // 28 reached? - { - int predict_nr,shift_factor,flags,d,s; - u8* start;unsigned int nSample; - int s_1,s_2; - - start=s_chan[ch].pCurr; // set up the current pos - - if (start == (u8*)-1) // special "stop" sign - { - s_chan[ch].bOn=0; // -> turn everything off - s_chan[ch].ADSRX.lVolume=0; - s_chan[ch].ADSRX.EnvelopeVol=0; - goto ENDX; // -> and done for this channel - } - - s_chan[ch].iSBPos=0; // Reset buffer play index. - - //////////////////////////////////////////// spu irq handler here? mmm... do it later - - s_1=s_chan[ch].s_1; - s_2=s_chan[ch].s_2; - - predict_nr=(int)*start;start++; - shift_factor=predict_nr&0xf; - predict_nr >>= 4; - flags=(int)*start;start++; - - // -------------------------------------- // - // Decode new samples into s_chan[ch].SB[0 through 27] - for (nSample=0;nSample<28;start++) - { - d=(int)*start; - s=((d&0xf)<<12); - if(s&0x8000) s|=0xffff0000; - - fa=(s >> shift_factor); - fa=fa + ((s_1 * f[predict_nr][0])>>6) + ((s_2 * f[predict_nr][1])>>6); - s_2=s_1;s_1=fa; - s=((d & 0xf0) << 8); - - s_chan[ch].SB[nSample++]=fa; - - if(s&0x8000) s|=0xffff0000; - fa=(s>>shift_factor); - fa=fa + ((s_1 * f[predict_nr][0])>>6) + ((s_2 * f[predict_nr][1])>>6); - s_2=s_1;s_1=fa; - - s_chan[ch].SB[nSample++]=fa; - } - - //////////////////////////////////////////// irq check - - if(spuCtrl&0x40) // irq active? - { - if((pSpuIrq > start-16 && // irq address reached? - pSpuIrq <= start) || - ((flags&1) && // special: irq on looping addr, when stop/loop flag is set - (pSpuIrq > s_chan[ch].pLoop-16 && - pSpuIrq <= s_chan[ch].pLoop))) - { - //extern s32 spuirqvoodoo; - s_chan[ch].iIrqDone=1; // -> debug flag - SPUirq(); - //puts("IRQ"); - //if(spuirqvoodoo!=-1) - //{ - // spuirqvoodoo=temp*384; - // temp=0; - //} - } - } - - //////////////////////////////////////////// flag handler - - if((flags&4) && (!s_chan[ch].bIgnoreLoop)) - s_chan[ch].pLoop=start-16; // loop adress - - if(flags&1) // 1: stop/loop - { - // We play this block out first... - //if(!(flags&2)) // 1+2: do loop... otherwise: stop - if(flags!=3 || s_chan[ch].pLoop==NULL) // PETE: if we don't check exactly for 3, loop hang ups will happen (DQ4, for example) - { // and checking if pLoop is set avoids crashes, yeah - start = (u8*)-1; - } - else - { - start = s_chan[ch].pLoop; - } - } - - s_chan[ch].pCurr=start; // store values for next cycle - s_chan[ch].s_1=s_1; - s_chan[ch].s_2=s_2; - - //////////////////////////////////////////// - } - - fa=s_chan[ch].SB[s_chan[ch].iSBPos++]; // get sample data - - if((spuCtrl&0x4000)==0) fa=0; // muted? - else CLIP(fa); - - { - int gpos; - gpos = s_chan[ch].SB[28]; - gval0 = fa; - gpos = (gpos+1) & 3; - s_chan[ch].SB[28] = gpos; - } - s_chan[ch].spos -= 0x10000L; - } - - //////////////////////////////////////////////// - // noise handler... just produces some noise data - // surely wrong... and no noise frequency (spuCtrl&0x3f00) will be used... - // and sometimes the noise will be used as fmod modulation... pfff - - if(s_chan[ch].bNoise) - { - //puts("Noise"); - if((dwNoiseVal<<=1)&0x80000000L) - { - dwNoiseVal^=0x0040001L; - fa=((dwNoiseVal>>2)&0x7fff); - fa=-fa; - } - else fa=(dwNoiseVal>>2)&0x7fff; - - // mmm... depending on the noise freq we allow bigger/smaller changes to the previous val - fa=s_chan[ch].iOldNoise+((fa-s_chan[ch].iOldNoise)/((0x001f-((spuCtrl&0x3f00)>>9))+1)); - if(fa>32767L) fa=32767L; - if(fa<-32767L) fa=-32767L; - s_chan[ch].iOldNoise=fa; - - } //---------------------------------------- - else // NO NOISE (NORMAL SAMPLE DATA) HERE - { - int vl, vr, gpos; - vl = (s_chan[ch].spos >> 6) & ~3; - gpos = s_chan[ch].SB[28]; - vr=(gauss[vl]*gval0)>>9; - vr+=(gauss[vl+1]*gval(1))>>9; - vr+=(gauss[vl+2]*gval(2))>>9; - vr+=(gauss[vl+3]*gval(3))>>9; - fa = vr>>2; - } - - s_chan[ch].sval = (MixADSR(ch) * fa)>>10; // / 1023; // add adsr - if(s_chan[ch].bFMod==2) // fmod freq channel - { - int NP=s_chan[ch+1].iRawPitch; - NP=((32768L+s_chan[ch].sval)*NP)>>15; ///32768L; - - if(NP>0x3fff) NP=0x3fff; - if(NP<0x1) NP=0x1; - - // mmmm... if I do this, all is screwed - // s_chan[ch+1].iRawPitch=NP; - - NP=(44100L*NP)/(4096L); // calc frequency - - s_chan[ch+1].iActFreq=NP; - s_chan[ch+1].iUsedFreq=NP; - s_chan[ch+1].sinc=(((NP/10)<<16)/4410); - if(!s_chan[ch+1].sinc) s_chan[ch+1].sinc=1; - - // mmmm... set up freq decoding positions? - // s_chan[ch+1].iSBPos=28; - // s_chan[ch+1].spos=0x10000L; - } - else - { - ////////////////////////////////////////////// - // ok, left/right sound volume (psx volume goes from 0 ... 0x3fff) - int tmpl,tmpr; - - if (1) //ao_channel_enable[ch+PSF_1]) { - { - tmpl=(s_chan[ch].sval*s_chan[ch].iLeftVolume)>>14; - tmpr=(s_chan[ch].sval*s_chan[ch].iRightVolume)>>14; - } else { - tmpl = 0; - tmpr = 0; - } - sl+=tmpl; - sr+=tmpr; - - if(((rvb.Enabled>>ch)&1) && (spuCtrl&0x80)) - { - revLeft+=tmpl; - revRight+=tmpr; - } - } - - s_chan[ch].spos += s_chan[ch].sinc; - ENDX: ; - } - } - - /////////////////////////////////////////////////////// - // mix all channels (including reverb) into one buffer - MixREVERBLeftRight(&sl,&sr,revLeft,revRight); -// printf("sampcount %d decaybegin %d decayend %d\n", sampcount, decaybegin, decayend); - if(sampcount>=decaybegin) - { - s32 dmul; - if(decaybegin!=~0) // Is anyone REALLY going to be playing a song - // for 13 hours? - { - if(sampcount>=decayend) - { -// ao_song_done = 1; - return(0); - } - dmul=256-(256*(sampcount-decaybegin)/(decayend-decaybegin)); - sl=(sl*dmul)>>8; - sr=(sr*dmul)>>8; - } - } - - sampcount++; - sl=(sl*volmul)>>8; - sr=(sr*volmul)>>8; - - //{ - // static double asl=0; - // static double asr=0; - - // asl+=(sl-asl)/5; - // asr+=(sl-asr)/5; - - //sl-=asl; - //sr-=asr; - - // if(sl>32767 || sl < -32767) printf("Left: %d, %f\n",sl,asl); - // if(sr>32767 || sr < -32767) printf("Right: %d, %f\n",sl,asl); - //} - - if(sl>32767) sl=32767; if(sl<-32767) sl=-32767; - if(sr>32767) sr=32767; if(sr<-32767) sr=-32767; - - *pS++=sl; - *pS++=sr; - } - - return(1); -} - -void SPU_flushboot(void) -{ - if((u8*)pS>((u8*)pSpuBuffer+1024)) - { - spu_update((u8*)pSpuBuffer,(u8*)pS-(u8*)pSpuBuffer); - pS=(s16 *)pSpuBuffer; - } -} - -#ifdef TIMEO -static u64 begintime; -static u64 gettime64(void) -{ - struct timeval tv; - u64 ret; - - gettimeofday(&tv,0); - ret=tv.tv_sec; - ret*=1000000; - ret+=tv.tv_usec; - return(ret); -} -#endif -//////////////////////////////////////////////////////////////////////// -// INIT/EXIT STUFF -//////////////////////////////////////////////////////////////////////// - -//////////////////////////////////////////////////////////////////////// -// SPUINIT: this func will be called first by the main emu -//////////////////////////////////////////////////////////////////////// - -int SPUinit(void) -{ - spuMemC=(u8*)spuMem; // just small setup - memset((void *)s_chan,0,MAXCHAN*sizeof(SPUCHAN)); - memset((void *)&rvb,0,sizeof(REVERBInfo)); - memset(regArea,0,sizeof(regArea)); - memset(spuMem,0,sizeof(spuMem)); - InitADSR(); - sampcount=ttemp=0; - #ifdef TIMEO - begintime=gettime64(); - #endif - return 0; -} - -//////////////////////////////////////////////////////////////////////// -// SETUPSTREAMS: init most of the spu buffers -//////////////////////////////////////////////////////////////////////// - -void SetupStreams(void) -{ - int i; - - pSpuBuffer=(u8*)malloc(32768); // alloc mixing buffer - pS=(s16 *)pSpuBuffer; - - for(i=0;i init sustain - s_chan[i].iIrqDone=0; - s_chan[i].pLoop=spuMemC; - s_chan[i].pStart=spuMemC; - s_chan[i].pCurr=spuMemC; - } -} - -//////////////////////////////////////////////////////////////////////// -// REMOVESTREAMS: free most buffer -//////////////////////////////////////////////////////////////////////// - -void RemoveStreams(void) -{ - free(pSpuBuffer); // free mixing buffer - pSpuBuffer=NULL; - - #ifdef TIMEO - { - u64 tmp; - tmp=gettime64(); - tmp-=begintime; - if(tmp) - tmp=(u64)sampcount*1000000/tmp; - printf("%lld samples per second\n",tmp); - } - #endif -} - - -//////////////////////////////////////////////////////////////////////// -// SPUOPEN: called by main emu after init -//////////////////////////////////////////////////////////////////////// - -int SPUopen(void) -{ - if(bSPUIsOpen) return 0; // security for some stupid main emus - spuIrq=0; - - spuStat=spuCtrl=0; - spuAddr=0xffffffff; - dwNoiseVal=1; - - spuMemC=(u8*)spuMem; - memset((void *)s_chan,0,(MAXCHAN+1)*sizeof(SPUCHAN)); - pSpuIrq=0; - - iVolume=255; //85; - SetupStreams(); // prepare streaming - - bSPUIsOpen=1; - - return 1; -} - -//////////////////////////////////////////////////////////////////////// - -//////////////////////////////////////////////////////////////////////// -// SPUCLOSE: called before shutdown -//////////////////////////////////////////////////////////////////////// - -int SPUclose(void) -{ - if(!bSPUIsOpen) return 0; // some security - - bSPUIsOpen=0; // no more open - - RemoveStreams(); // no more streaming - - return 0; -} - -//////////////////////////////////////////////////////////////////////// -// SPUSHUTDOWN: called by main emu on final exit -//////////////////////////////////////////////////////////////////////// - -int SPUshutdown(void) -{ - return 0; -} - -void SPUinjectRAMImage(u16 *pIncoming) -{ - int i; - - for (i = 0; i < (256*1024); i++) - { - spuMem[i] = pIncoming[i]; - } -} diff --git a/Frameworks/AudioOverload/aosdk/eng_psf/peops/spu.h b/Frameworks/AudioOverload/aosdk/eng_psf/peops/spu.h deleted file mode 100644 index 3c2cee414..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_psf/peops/spu.h +++ /dev/null @@ -1,39 +0,0 @@ -/*************************************************************************** - spu.h - description - ------------------- - begin : Wed May 15 2002 - copyright : (C) 2002 by Pete Bernert - email : BlackDove@addcom.de - ***************************************************************************/ - -/*************************************************************************** - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. See also the license.txt file for * - * additional informations. * - * * - ***************************************************************************/ - -//*************************************************************************// -// History of changes: -// -// 2002/05/15 - Pete -// - generic cleanup for the Peops release -// -//*************************************************************************// - -void sexyd_update(unsigned char* pSound,long lBytes); - -int SPUasync(u32 cycles); -void SPU_flushboot(void); -int SPUinit(void); -int SPUopen(void); -int SPUclose(void); -int SPUshutdown(void); -void SPUinjectRAMImage(u16 *pIncoming); -void SPUreadDMAMem(u32 usPSXMem,int iSize); -void SPUwriteDMAMem(u32 usPSXMem,int iSize); -u16 SPUreadRegister(u32 reg); - diff --git a/Frameworks/AudioOverload/aosdk/eng_psf/peops/stdafx.h b/Frameworks/AudioOverload/aosdk/eng_psf/peops/stdafx.h deleted file mode 100644 index 6506f324a..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_psf/peops/stdafx.h +++ /dev/null @@ -1,29 +0,0 @@ -/*************************************************************************** - StdAfx.h - description - ------------------- - begin : Wed May 15 2002 - copyright : (C) 2002 by Pete Bernert - email : BlackDove@addcom.de - ***************************************************************************/ - -/*************************************************************************** - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. See also the license.txt file for * - * additional informations. * - * * - ***************************************************************************/ - -//*************************************************************************// -// History of changes: -// -// 2002/05/15 - Pete -// - generic cleanup for the Peops release -// -//*************************************************************************// - -#include -#include -#include diff --git a/Frameworks/AudioOverload/aosdk/eng_psf/peops2/adsr.c b/Frameworks/AudioOverload/aosdk/eng_psf/peops2/adsr.c deleted file mode 100644 index a0f348155..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_psf/peops2/adsr.c +++ /dev/null @@ -1,656 +0,0 @@ -/*************************************************************************** - adsr.c - description - ------------------- - begin : Wed May 15 2002 - copyright : (C) 2002 by Pete Bernert - email : BlackDove@addcom.de - ***************************************************************************/ - -/*************************************************************************** - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. See also the license.txt file for * - * additional informations. * - * * - ***************************************************************************/ - -//*************************************************************************// -// History of changes: -// -// 2003/05/14 - xodnizel -// - removed stopping of reverb on sample end -// -// 2003/01/06 - Pete -// - added Neill's ADSR timings -// -// 2002/05/15 - Pete -// - generic cleanup for the Peops release -// -//*************************************************************************// - -#include "stdafx.h" - -#define _IN_ADSR - -// will be included from spu.c -#ifdef _IN_SPU - -//////////////////////////////////////////////////////////////////////// -// ADSR func -//////////////////////////////////////////////////////////////////////// - -unsigned long RateTable[160]; - -void InitADSR(void) // INIT ADSR -{ - unsigned long r,rs,rd;int i; - - memset(RateTable,0,sizeof(unsigned long)*160); // build the rate table according to Neill's rules (see at bottom of file) - - r=3;rs=1;rd=0; - - for(i=32;i<160;i++) // we start at pos 32 with the real values... everything before is 0 - { - if(r<0x3FFFFFFF) - { - r+=rs; - rd++;if(rd==5) {rd=1;rs*=2;} - } - if(r>0x3FFFFFFF) r=0x3FFFFFFF; - - RateTable[i]=r; - } -} - -//////////////////////////////////////////////////////////////////////// - -static INLINE void StartADSR(int ch) // MIX ADSR -{ - s_chan[ch].ADSRX.lVolume=1; // and init some adsr vars - s_chan[ch].ADSRX.State=0; - s_chan[ch].ADSRX.EnvelopeVol=0; -} - -//////////////////////////////////////////////////////////////////////// - -static INLINE int MixADSR(int ch) // MIX ADSR -{ - if(s_chan[ch].bStop) // should be stopped: - { // do release - if(s_chan[ch].ADSRX.ReleaseModeExp) - { - switch((s_chan[ch].ADSRX.EnvelopeVol>>28)&0x7) - { - case 0: s_chan[ch].ADSRX.EnvelopeVol-=RateTable[(4*(s_chan[ch].ADSRX.ReleaseRate^0x1F))-0x18 +0 + 32]; break; - case 1: s_chan[ch].ADSRX.EnvelopeVol-=RateTable[(4*(s_chan[ch].ADSRX.ReleaseRate^0x1F))-0x18 +4 + 32]; break; - case 2: s_chan[ch].ADSRX.EnvelopeVol-=RateTable[(4*(s_chan[ch].ADSRX.ReleaseRate^0x1F))-0x18 +6 + 32]; break; - case 3: s_chan[ch].ADSRX.EnvelopeVol-=RateTable[(4*(s_chan[ch].ADSRX.ReleaseRate^0x1F))-0x18 +8 + 32]; break; - case 4: s_chan[ch].ADSRX.EnvelopeVol-=RateTable[(4*(s_chan[ch].ADSRX.ReleaseRate^0x1F))-0x18 +9 + 32]; break; - case 5: s_chan[ch].ADSRX.EnvelopeVol-=RateTable[(4*(s_chan[ch].ADSRX.ReleaseRate^0x1F))-0x18 +10+ 32]; break; - case 6: s_chan[ch].ADSRX.EnvelopeVol-=RateTable[(4*(s_chan[ch].ADSRX.ReleaseRate^0x1F))-0x18 +11+ 32]; break; - case 7: s_chan[ch].ADSRX.EnvelopeVol-=RateTable[(4*(s_chan[ch].ADSRX.ReleaseRate^0x1F))-0x18 +12+ 32]; break; - } - } - else - { - s_chan[ch].ADSRX.EnvelopeVol-=RateTable[(4*(s_chan[ch].ADSRX.ReleaseRate^0x1F))-0x0C + 32]; - } - - if(s_chan[ch].ADSRX.EnvelopeVol<0) - { - s_chan[ch].ADSRX.EnvelopeVol=0; - s_chan[ch].bOn=0; - //s_chan[ch].bReverb=0; - //s_chan[ch].bNoise=0; - } - - s_chan[ch].ADSRX.lVolume=s_chan[ch].ADSRX.EnvelopeVol>>21; - return s_chan[ch].ADSRX.lVolume; - } - else // not stopped yet? - { - if(s_chan[ch].ADSRX.State==0) // -> attack - { - if(s_chan[ch].ADSRX.AttackModeExp) - { - if(s_chan[ch].ADSRX.EnvelopeVol<0x60000000) - s_chan[ch].ADSRX.EnvelopeVol+=RateTable[(s_chan[ch].ADSRX.AttackRate^0x7F)-0x10 + 32]; - else - s_chan[ch].ADSRX.EnvelopeVol+=RateTable[(s_chan[ch].ADSRX.AttackRate^0x7F)-0x18 + 32]; - } - else - { - s_chan[ch].ADSRX.EnvelopeVol+=RateTable[(s_chan[ch].ADSRX.AttackRate^0x7F)-0x10 + 32]; - } - - if(s_chan[ch].ADSRX.EnvelopeVol<0) - { - s_chan[ch].ADSRX.EnvelopeVol=0x7FFFFFFF; - s_chan[ch].ADSRX.State=1; - } - - s_chan[ch].ADSRX.lVolume=s_chan[ch].ADSRX.EnvelopeVol>>21; - return s_chan[ch].ADSRX.lVolume; - } - //--------------------------------------------------// - if(s_chan[ch].ADSRX.State==1) // -> decay - { - switch((s_chan[ch].ADSRX.EnvelopeVol>>28)&0x7) - { - case 0: s_chan[ch].ADSRX.EnvelopeVol-=RateTable[(4*(s_chan[ch].ADSRX.DecayRate^0x1F))-0x18+0 + 32]; break; - case 1: s_chan[ch].ADSRX.EnvelopeVol-=RateTable[(4*(s_chan[ch].ADSRX.DecayRate^0x1F))-0x18+4 + 32]; break; - case 2: s_chan[ch].ADSRX.EnvelopeVol-=RateTable[(4*(s_chan[ch].ADSRX.DecayRate^0x1F))-0x18+6 + 32]; break; - case 3: s_chan[ch].ADSRX.EnvelopeVol-=RateTable[(4*(s_chan[ch].ADSRX.DecayRate^0x1F))-0x18+8 + 32]; break; - case 4: s_chan[ch].ADSRX.EnvelopeVol-=RateTable[(4*(s_chan[ch].ADSRX.DecayRate^0x1F))-0x18+9 + 32]; break; - case 5: s_chan[ch].ADSRX.EnvelopeVol-=RateTable[(4*(s_chan[ch].ADSRX.DecayRate^0x1F))-0x18+10+ 32]; break; - case 6: s_chan[ch].ADSRX.EnvelopeVol-=RateTable[(4*(s_chan[ch].ADSRX.DecayRate^0x1F))-0x18+11+ 32]; break; - case 7: s_chan[ch].ADSRX.EnvelopeVol-=RateTable[(4*(s_chan[ch].ADSRX.DecayRate^0x1F))-0x18+12+ 32]; break; - } - - if(s_chan[ch].ADSRX.EnvelopeVol<0) s_chan[ch].ADSRX.EnvelopeVol=0; - if(((s_chan[ch].ADSRX.EnvelopeVol>>27)&0xF) <= s_chan[ch].ADSRX.SustainLevel) - { - s_chan[ch].ADSRX.State=2; - } - - s_chan[ch].ADSRX.lVolume=s_chan[ch].ADSRX.EnvelopeVol>>21; - return s_chan[ch].ADSRX.lVolume; - } - //--------------------------------------------------// - if(s_chan[ch].ADSRX.State==2) // -> sustain - { - if(s_chan[ch].ADSRX.SustainIncrease) - { - if(s_chan[ch].ADSRX.SustainModeExp) - { - if(s_chan[ch].ADSRX.EnvelopeVol<0x60000000) - s_chan[ch].ADSRX.EnvelopeVol+=RateTable[(s_chan[ch].ADSRX.SustainRate^0x7F)-0x10 + 32]; - else - s_chan[ch].ADSRX.EnvelopeVol+=RateTable[(s_chan[ch].ADSRX.SustainRate^0x7F)-0x18 + 32]; - } - else - { - s_chan[ch].ADSRX.EnvelopeVol+=RateTable[(s_chan[ch].ADSRX.SustainRate^0x7F)-0x10 + 32]; - } - - if(s_chan[ch].ADSRX.EnvelopeVol<0) - { - s_chan[ch].ADSRX.EnvelopeVol=0x7FFFFFFF; - } - } - else - { - if(s_chan[ch].ADSRX.SustainModeExp) - { - switch((s_chan[ch].ADSRX.EnvelopeVol>>28)&0x7) - { - case 0: s_chan[ch].ADSRX.EnvelopeVol-=RateTable[((s_chan[ch].ADSRX.SustainRate^0x7F))-0x1B +0 + 32];break; - case 1: s_chan[ch].ADSRX.EnvelopeVol-=RateTable[((s_chan[ch].ADSRX.SustainRate^0x7F))-0x1B +4 + 32];break; - case 2: s_chan[ch].ADSRX.EnvelopeVol-=RateTable[((s_chan[ch].ADSRX.SustainRate^0x7F))-0x1B +6 + 32];break; - case 3: s_chan[ch].ADSRX.EnvelopeVol-=RateTable[((s_chan[ch].ADSRX.SustainRate^0x7F))-0x1B +8 + 32];break; - case 4: s_chan[ch].ADSRX.EnvelopeVol-=RateTable[((s_chan[ch].ADSRX.SustainRate^0x7F))-0x1B +9 + 32];break; - case 5: s_chan[ch].ADSRX.EnvelopeVol-=RateTable[((s_chan[ch].ADSRX.SustainRate^0x7F))-0x1B +10+ 32];break; - case 6: s_chan[ch].ADSRX.EnvelopeVol-=RateTable[((s_chan[ch].ADSRX.SustainRate^0x7F))-0x1B +11+ 32];break; - case 7: s_chan[ch].ADSRX.EnvelopeVol-=RateTable[((s_chan[ch].ADSRX.SustainRate^0x7F))-0x1B +12+ 32];break; - } - } - else - { - s_chan[ch].ADSRX.EnvelopeVol-=RateTable[((s_chan[ch].ADSRX.SustainRate^0x7F))-0x0F + 32]; - } - - if(s_chan[ch].ADSRX.EnvelopeVol<0) - { - s_chan[ch].ADSRX.EnvelopeVol=0; - } - } - s_chan[ch].ADSRX.lVolume=s_chan[ch].ADSRX.EnvelopeVol>>21; - return s_chan[ch].ADSRX.lVolume; - } - } - return 0; -} - -#endif - -/* -James Higgs ADSR investigations: - -PSX SPU Envelope Timings -~~~~~~~~~~~~~~~~~~~~~~~~ - -First, here is an extract from doomed's SPU doc, which explains the basics -of the SPU "volume envelope": - -*** doomed doc extract start *** - --------------------------------------------------------------------------- -Voices. --------------------------------------------------------------------------- -The SPU has 24 hardware voices. These voices can be used to reproduce sample -data, noise or can be used as frequency modulator on the next voice. -Each voice has it's own programmable ADSR envelope filter. The main volume -can be programmed independently for left and right output. - -The ADSR envelope filter works as follows: -Ar = Attack rate, which specifies the speed at which the volume increases - from zero to it's maximum value, as soon as the note on is given. The - slope can be set to lineair or exponential. -Dr = Decay rate specifies the speed at which the volume decreases to the - sustain level. Decay is always decreasing exponentially. -Sl = Sustain level, base level from which sustain starts. -Sr = Sustain rate is the rate at which the volume of the sustained note - increases or decreases. This can be either lineair or exponential. -Rr = Release rate is the rate at which the volume of the note decreases - as soon as the note off is given. - - lvl | - ^ | /\Dr __ - Sl _| _ / _ \__--- \ - | / ---__ \ Rr - | /Ar Sr \ \ - | / \\ - |/___________________\________ - ->time - -The overal volume can also be set to sweep up or down lineairly or -exponentially from it's current value. This can be done seperately -for left and right. - -Relevant SPU registers: -------------------------------------------------------------- -$1f801xx8 Attack/Decay/Sustain level -bit |0f|0e 0d 0c 0b 0a 09 08|07 06 05 04|03 02 01 00| -desc.|Am| Ar |Dr |Sl | - -Am 0 Attack mode Linear - 1 Exponential - -Ar 0-7f attack rate -Dr 0-f decay rate -Sl 0-f sustain level -------------------------------------------------------------- -$1f801xxa Sustain rate, Release Rate. -bit |0f|0e|0d|0c 0b 0a 09 08 07 06|05|04 03 02 01 00| -desc.|Sm|Sd| 0| Sr |Rm|Rr | - -Sm 0 sustain rate mode linear - 1 exponential -Sd 0 sustain rate mode increase - 1 decrease -Sr 0-7f Sustain Rate -Rm 0 Linear decrease - 1 Exponential decrease -Rr 0-1f Release Rate - -Note: decay mode is always Expontial decrease, and thus cannot -be set. -------------------------------------------------------------- -$1f801xxc Current ADSR volume -bit |0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00| -desc.|ADSRvol | - -ADSRvol Returns the current envelope volume when - read. --- James' Note: return range: 0 -> 32767 - -*** doomed doc extract end *** - -By using a small PSX proggie to visualise the envelope as it was played, -the following results for envelope timing were obtained: - -1. Attack rate value (linear mode) - - Attack value range: 0 -> 127 - - Value | 48 | 52 | 56 | 60 | 64 | 68 | 72 | | 80 | - ----------------------------------------------------------------- - Frames | 11 | 21 | 42 | 84 | 169| 338| 676| |2890| - - Note: frames is no. of PAL frames to reach full volume (100% - amplitude) - - Hmm, noticing that the time taken to reach full volume doubles - every time we add 4 to our attack value, we know the equation is - of form: - frames = k * 2 ^ (value / 4) - - (You may ponder about envelope generator hardware at this point, - or maybe not... :) - - By substituting some stuff and running some checks, we get: - - k = 0.00257 (close enuf) - - therefore, - frames = 0.00257 * 2 ^ (value / 4) - If you just happen to be writing an emulator, then you can probably - use an equation like: - - %volume_increase_per_tick = 1 / frames - - - ------------------------------------ - Pete: - ms=((1<<(value>>2))*514)/10000 - ------------------------------------ - -2. Decay rate value (only has log mode) - - Decay value range: 0 -> 15 - - Value | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | - ------------------------------------------------ - frames | | | | | 6 | 12 | 24 | 47 | - - Note: frames here is no. of PAL frames to decay to 50% volume. - - formula: frames = k * 2 ^ (value) - - Substituting, we get: k = 0.00146 - - Further info on logarithmic nature: - frames to decay to sustain level 3 = 3 * frames to decay to - sustain level 9 - - Also no. of frames to 25% volume = roughly 1.85 * no. of frames to - 50% volume. - - Frag it - just use linear approx. - - ------------------------------------ - Pete: - ms=((1< 127 - - Value | 48 | 52 | 56 | 60 | 64 | 68 | 72 | - ------------------------------------------- - frames | 9 | 19 | 37 | 74 | 147| 293| 587| - - Here, frames = no. of PAL frames for volume amplitude to go from 100% - to 0% (or vice-versa). - - Same formula as for attack value, just a different value for k: - - k = 0.00225 - - ie: frames = 0.00225 * 2 ^ (value / 4) - - For emulation purposes: - - %volume_increase_or_decrease_per_tick = 1 / frames - - ------------------------------------ - Pete: - ms=((1<<(value>>2))*450)/10000 - ------------------------------------ - - -4. Release rate (linear mode) - - Release rate range: 0 -> 31 - - Value | 13 | 14 | 15 | 16 | 17 | - --------------------------------------------------------------- - frames | 18 | 36 | 73 | 146| 292| - - Here, frames = no. of PAL frames to decay from 100% vol to 0% vol - after "note-off" is triggered. - - Formula: frames = k * 2 ^ (value) - - And so: k = 0.00223 - - ------------------------------------ - Pete: - ms=((1< release phase - { - if(s_chan[ch].ADSR.ReleaseVal!=0) // -> release not 0: do release (if 0: stop right now) - { - if(!s_chan[ch].ADSR.ReleaseVol) // --> release just started? set up the release stuff - { - s_chan[ch].ADSR.ReleaseStartTime=s_chan[ch].ADSR.lTime; - s_chan[ch].ADSR.ReleaseVol=s_chan[ch].ADSR.lVolume; - s_chan[ch].ADSR.ReleaseTime = // --> calc how long does it take to reach the wanted sus level - (s_chan[ch].ADSR.ReleaseTime* - s_chan[ch].ADSR.ReleaseVol)/1024; - } - // -> NO release exp mode used (yet) - v=s_chan[ch].ADSR.ReleaseVol; // -> get last volume - lT=s_chan[ch].ADSR.lTime- // -> how much time is past? - s_chan[ch].ADSR.ReleaseStartTime; - l1=s_chan[ch].ADSR.ReleaseTime; - - if(lT we still have to release - { - v=v-((v*lT)/l1); // --> calc new volume - } - else // -> release is over: now really stop that sample - {v=0;s_chan[ch].bOn=0;s_chan[ch].ADSR.ReleaseVol=0;s_chan[ch].bNoise=0;} - } - else // -> release IS 0: release at once - { - v=0;s_chan[ch].bOn=0;s_chan[ch].ADSR.ReleaseVol=0;s_chan[ch].bNoise=0; - } - } - else - {//--------------------------------------------------// not in release phase: - v=1024; - lT=s_chan[ch].ADSR.lTime; - l1=s_chan[ch].ADSR.AttackTime; - - if(lT0) - { - if(l3!=0) v2+=((v-v2)*lT)/l3; - else v2=v; - } - else - { - if(l3!=0) v2-=(v2*lT)/l3; - else v2=v; - } - - if(v2>v) v2=v; - if(v2<=0) {v2=0;s_chan[ch].bOn=0;s_chan[ch].ADSR.ReleaseVol=0;s_chan[ch].bNoise=0;} - - v=v2; - } - } - } - - //----------------------------------------------------// - // ok, done for this channel, so increase time - - s_chan[ch].ADSR.lTime+=1; // 1 = 1.020408f ms; - - if(v>1024) v=1024; // adjust volume - if(v<0) v=0; - s_chan[ch].ADSR.lVolume=v; // store act volume - - return v; // return the volume factor -*/ - - -//----------------------------------------------------------------------------- -//----------------------------------------------------------------------------- -//----------------------------------------------------------------------------- - - -/* ------------------------------------------------------------------------------ -Neill Corlett -Playstation SPU envelope timing notes ------------------------------------------------------------------------------ - -This is preliminary. This may be wrong. But the model described herein fits -all of my experimental data, and it's just simple enough to sound right. - -ADSR envelope level ranges from 0x00000000 to 0x7FFFFFFF internally. -The value returned by channel reg 0xC is (envelope_level>>16). - -Each sample, an increment or decrement value will be added to or -subtracted from this envelope level. - -Create the rate log table. The values double every 4 entries. - entry #0 = 4 - - 4, 5, 6, 7, - 8,10,12,14, - 16,20,24,28, ... - - entry #40 = 4096... - entry #44 = 8192... - entry #48 = 16384... - entry #52 = 32768... - entry #56 = 65536... - -increments and decrements are in terms of ratelogtable[n] -n may exceed the table bounds (plan on n being between -32 and 127). -table values are all clipped between 0x00000000 and 0x3FFFFFFF - -when you "voice on", the envelope is always fully reset. -(yes, it may click. the real thing does this too.) - -envelope level begins at zero. - -each state happens for at least 1 cycle -(transitions are not instantaneous) -this may result in some oddness: if the decay rate is uberfast, it will cut -the envelope from full down to half in one sample, potentially skipping over -the sustain level - -ATTACK ------- -- if the envelope level has overflowed past the max, clip to 0x7FFFFFFF and - proceed to DECAY. - -Linear attack mode: -- line extends upward to 0x7FFFFFFF -- increment per sample is ratelogtable[(Ar^0x7F)-0x10] - -Logarithmic attack mode: -if envelope_level < 0x60000000: - - line extends upward to 0x60000000 - - increment per sample is ratelogtable[(Ar^0x7F)-0x10] -else: - - line extends upward to 0x7FFFFFFF - - increment per sample is ratelogtable[(Ar^0x7F)-0x18] - -DECAY ------ -- if ((envelope_level>>27)&0xF) <= Sl, proceed to SUSTAIN. - Do not clip to the sustain level. -- current line ends at (envelope_level & 0x07FFFFFF) -- decrement per sample depends on (envelope_level>>28)&0x7 - 0: ratelogtable[(4*(Dr^0x1F))-0x18+0] - 1: ratelogtable[(4*(Dr^0x1F))-0x18+4] - 2: ratelogtable[(4*(Dr^0x1F))-0x18+6] - 3: ratelogtable[(4*(Dr^0x1F))-0x18+8] - 4: ratelogtable[(4*(Dr^0x1F))-0x18+9] - 5: ratelogtable[(4*(Dr^0x1F))-0x18+10] - 6: ratelogtable[(4*(Dr^0x1F))-0x18+11] - 7: ratelogtable[(4*(Dr^0x1F))-0x18+12] - (note that this is the same as the release rate formula, except that - decay rates 10-1F aren't possible... those would be slower in theory) - -SUSTAIN -------- -- no terminating condition except for voice off -- Sd=0 (increase) behavior is identical to ATTACK for both log and linear. -- Sd=1 (decrease) behavior: -Linear sustain decrease: -- line extends to 0x00000000 -- decrement per sample is ratelogtable[(Sr^0x7F)-0x0F] -Logarithmic sustain decrease: -- current line ends at (envelope_level & 0x07FFFFFF) -- decrement per sample depends on (envelope_level>>28)&0x7 - 0: ratelogtable[(Sr^0x7F)-0x1B+0] - 1: ratelogtable[(Sr^0x7F)-0x1B+4] - 2: ratelogtable[(Sr^0x7F)-0x1B+6] - 3: ratelogtable[(Sr^0x7F)-0x1B+8] - 4: ratelogtable[(Sr^0x7F)-0x1B+9] - 5: ratelogtable[(Sr^0x7F)-0x1B+10] - 6: ratelogtable[(Sr^0x7F)-0x1B+11] - 7: ratelogtable[(Sr^0x7F)-0x1B+12] - -RELEASE -------- -- if the envelope level has overflowed to negative, clip to 0 and QUIT. - -Linear release mode: -- line extends to 0x00000000 -- decrement per sample is ratelogtable[(4*(Rr^0x1F))-0x0C] - -Logarithmic release mode: -- line extends to (envelope_level & 0x0FFFFFFF) -- decrement per sample depends on (envelope_level>>28)&0x7 - 0: ratelogtable[(4*(Rr^0x1F))-0x18+0] - 1: ratelogtable[(4*(Rr^0x1F))-0x18+4] - 2: ratelogtable[(4*(Rr^0x1F))-0x18+6] - 3: ratelogtable[(4*(Rr^0x1F))-0x18+8] - 4: ratelogtable[(4*(Rr^0x1F))-0x18+9] - 5: ratelogtable[(4*(Rr^0x1F))-0x18+10] - 6: ratelogtable[(4*(Rr^0x1F))-0x18+11] - 7: ratelogtable[(4*(Rr^0x1F))-0x18+12] - ------------------------------------------------------------------------------ -*/ - diff --git a/Frameworks/AudioOverload/aosdk/eng_psf/peops2/adsr.h b/Frameworks/AudioOverload/aosdk/eng_psf/peops2/adsr.h deleted file mode 100644 index 777a0d84c..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_psf/peops2/adsr.h +++ /dev/null @@ -1,28 +0,0 @@ -/*************************************************************************** - adsr.h - description - ------------------- - begin : Wed May 15 2002 - copyright : (C) 2002 by Pete Bernert - email : BlackDove@addcom.de - ***************************************************************************/ - -/*************************************************************************** - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. See also the license.txt file for * - * additional informations. * - * * - ***************************************************************************/ - -//*************************************************************************// -// History of changes: -// -// 2002/05/15 - Pete -// - generic cleanup for the Peops release -// -//*************************************************************************// - -INLINE void StartADSR(int ch); -INLINE int MixADSR(int ch); diff --git a/Frameworks/AudioOverload/aosdk/eng_psf/peops2/dma.c b/Frameworks/AudioOverload/aosdk/eng_psf/peops2/dma.c deleted file mode 100644 index d137dfc24..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_psf/peops2/dma.c +++ /dev/null @@ -1,175 +0,0 @@ -/*************************************************************************** - dma.c - description - ------------------- - begin : Wed May 15 2002 - copyright : (C) 2002 by Pete Bernert - email : BlackDove@addcom.de - ***************************************************************************/ - -/*************************************************************************** - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. See also the license.txt file for * - * additional informations. * - * * - ***************************************************************************/ - -//*************************************************************************// -// History of changes: -// -// 2004/04/04 - Pete -// - changed plugin to emulate PS2 spu -// -// 2002/05/15 - Pete -// - generic cleanup for the Peops release -// -//*************************************************************************// - -#include "../peops2/stdafx.h" - -#define _IN_DMA - -#include "../peops2/externals.h" -#include "../peops2/registers.h" -//#include "debug.h" - -extern uint32 psx_ram[(2*1024*1024)/4]; - -//////////////////////////////////////////////////////////////////////// -// READ DMA (many values) -//////////////////////////////////////////////////////////////////////// - -EXPORT_GCC void CALLBACK SPU2readDMA4Mem(u32 usPSXMem,int iSize) -{ - int i; - u16 *ram16 = (u16 *)&psx_ram[0]; - - for(i=0;i>1]=spuMem[spuAddr2[0]]; // spu addr 0 got by writeregister - usPSXMem+=2; - spuAddr2[0]++; // inc spu addr - if(spuAddr2[0]>0xfffff) spuAddr2[0]=0; // wrap - } - - spuAddr2[0]+=0x20; //????? - - - iSpuAsyncWait=0; - - // got from J.F. and Kanodin... is it needed? - regArea[(PS2_C0_ADMAS)>>1]=0; // Auto DMA complete - spuStat2[0]=0x80; // DMA complete -} - -EXPORT_GCC void CALLBACK SPU2readDMA7Mem(u32 usPSXMem,int iSize) -{ - int i; - u16 *ram16 = (u16 *)&psx_ram[0]; - - for(i=0;i>1]=spuMem[spuAddr2[1]]; // spu addr 1 got by writeregister - usPSXMem+=2; - spuAddr2[1]++; // inc spu addr - if(spuAddr2[1]>0xfffff) spuAddr2[1]=0; // wrap - } - - spuAddr2[1]+=0x20; //????? - - iSpuAsyncWait=0; - - // got from J.F. and Kanodin... is it needed? - regArea[(PS2_C1_ADMAS)>>1]=0; // Auto DMA complete - spuStat2[1]=0x80; // DMA complete -} - -//////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////// - -// to investigate: do sound data updates by writedma affect spu -// irqs? Will an irq be triggered, if new data is written to -// the memory irq address? - -//////////////////////////////////////////////////////////////////////// -// WRITE DMA (many values) -//////////////////////////////////////////////////////////////////////// - -EXPORT_GCC void CALLBACK SPU2writeDMA4Mem(u32 usPSXMem,int iSize) -{ - int i; - u16 *ram16 = (u16 *)&psx_ram[0]; - - for(i=0;i>1]; // spu addr 0 got by writeregister - usPSXMem+=2; - spuAddr2[0]++; // inc spu addr - if(spuAddr2[0]>0xfffff) spuAddr2[0]=0; // wrap - } - - iSpuAsyncWait=0; - - // got from J.F. and Kanodin... is it needed? - spuStat2[0]=0x80; // DMA complete -} - -EXPORT_GCC void CALLBACK SPU2writeDMA7Mem(u32 usPSXMem,int iSize) -{ - int i; - u16 *ram16 = (u16 *)&psx_ram[0]; - - for(i=0;i>1]; // spu addr 1 got by writeregister - spuAddr2[1]++; // inc spu addr - if(spuAddr2[1]>0xfffff) spuAddr2[1]=0; // wrap - } - - iSpuAsyncWait=0; - - // got from J.F. and Kanodin... is it needed? - spuStat2[1]=0x80; // DMA complete -} - -//////////////////////////////////////////////////////////////////////// -// INTERRUPTS -//////////////////////////////////////////////////////////////////////// - -void InterruptDMA4(void) -{ -// taken from linuzappz NULL spu2 -// spu2Rs16(CORE0_ATTR)&= ~0x30; -// spu2Rs16(REG__1B0) = 0; -// spu2Rs16(SPU2_STATX_WRDY_M)|= 0x80; - - spuCtrl2[0]&=~0x30; - regArea[(PS2_C0_ADMAS)>>1]=0; - spuStat2[0]|=0x80; -} - -EXPORT_GCC void CALLBACK SPU2interruptDMA4(void) -{ - InterruptDMA4(); -} - -void InterruptDMA7(void) -{ -// taken from linuzappz NULL spu2 -// spu2Rs16(CORE1_ATTR)&= ~0x30; -// spu2Rs16(REG__5B0) = 0; -// spu2Rs16(SPU2_STATX_DREQ)|= 0x80; - - spuCtrl2[1]&=~0x30; - regArea[(PS2_C1_ADMAS)>>1]=0; - spuStat2[1]|=0x80; -} - -EXPORT_GCC void CALLBACK SPU2interruptDMA7(void) -{ - InterruptDMA7(); -} - diff --git a/Frameworks/AudioOverload/aosdk/eng_psf/peops2/dma.h b/Frameworks/AudioOverload/aosdk/eng_psf/peops2/dma.h deleted file mode 100644 index e11ece6d4..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_psf/peops2/dma.h +++ /dev/null @@ -1,29 +0,0 @@ -/*************************************************************************** - dma.h - description - ------------------- - begin : Wed May 15 2002 - copyright : (C) 2002 by Pete Bernert - email : BlackDove@addcom.de - ***************************************************************************/ - -/*************************************************************************** - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. See also the license.txt file for * - * additional informations. * - * * - ***************************************************************************/ - -//*************************************************************************// -// History of changes: -// -// 2002/05/15 - Pete -// - generic cleanup for the Peops release -// -//*************************************************************************// - -void InterruptDMA4(void); -void InterruptDMA7(void); - diff --git a/Frameworks/AudioOverload/aosdk/eng_psf/peops2/externals.h b/Frameworks/AudioOverload/aosdk/eng_psf/peops2/externals.h deleted file mode 100644 index 83e74c088..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_psf/peops2/externals.h +++ /dev/null @@ -1,385 +0,0 @@ -/*************************************************************************** - externals.h - description - ------------------- - begin : Wed May 15 2002 - copyright : (C) 2002 by Pete Bernert - email : BlackDove@addcom.de - ***************************************************************************/ - -/*************************************************************************** - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. See also the license.txt file for * - * additional informations. * - * * - ***************************************************************************/ - -//*************************************************************************// -// History of changes: -// -// 2004/04/04 - Pete -// - changed plugin to emulate PS2 spu -// -// 2002/04/04 - Pete -// - increased channel struct for interpolation -// -// 2002/05/15 - Pete -// - generic cleanup for the Peops release -// -//*************************************************************************// - -#ifndef PEOPS2_EXTERNALS -#define PEOPS2_EXTERNALS - -#include "ao.h" - -typedef int8 s8; -typedef int16 s16; -typedef int32 s32; -typedef int64 s64; - -typedef uint8 u8; -typedef uint16 u16; -typedef uint32 u32; -typedef uint64 u64; - -#if LSB_FIRST -static INLINE u16 BFLIP16(u16 x) -{ - return x; -} -#else -static INLINE u16 BFLIP16(u16 x) -{ - return( ((x>>8)&0xFF)| ((x&0xFF)<<8) ); -} -#endif - -///////////////////////////////////////////////////////// -// generic defines -///////////////////////////////////////////////////////// - -//#define PSE_LT_SPU 4 -//#define PSE_SPU_ERR_SUCCESS 0 -//#define PSE_SPU_ERR -60 -//#define PSE_SPU_ERR_NOTCONFIGURED PSE_SPU_ERR - 1 -//#define PSE_SPU_ERR_INIT PSE_SPU_ERR - 2 - -#ifndef max -#define max(a,b) (((a) > (b)) ? (a) : (b)) -#define min(a,b) (((a) < (b)) ? (a) : (b)) -#endif - -//////////////////////////////////////////////////////////////////////// -// spu defines -//////////////////////////////////////////////////////////////////////// - -// sound buffer sizes -// 400 ms complete sound buffer -#define SOUNDSIZE 76800 -// 137 ms test buffer... if less than that is buffered, a new upload will happen -#define TESTSIZE 26304 - -// num of channels -#define MAXCHAN 48 -#define HLFCHAN 24 - -// ~ 1 ms of data (was 45) -#define NSSIZE 1 -//45 - -/////////////////////////////////////////////////////////// -// struct defines -/////////////////////////////////////////////////////////// - -// ADSR INFOS PER CHANNEL -typedef struct -{ - int AttackModeExp; - long AttackTime; - long DecayTime; - long SustainLevel; - int SustainModeExp; - long SustainModeDec; - long SustainTime; - int ReleaseModeExp; - unsigned long ReleaseVal; - long ReleaseTime; - long ReleaseStartTime; - long ReleaseVol; - long lTime; - long lVolume; -} ADSRInfo; - -typedef struct -{ - int State; - int AttackModeExp; - int AttackRate; - int DecayRate; - int SustainLevel; - int SustainModeExp; - int SustainIncrease; - int SustainRate; - int ReleaseModeExp; - int ReleaseRate; - int EnvelopeVol; - long lVolume; - long lDummy1; - long lDummy2; -} ADSRInfoEx; - -/////////////////////////////////////////////////////////// - -// Tmp Flags - -// used for debug channel muting -#define FLAG_MUTE 1 - -// used for simple interpolation -#define FLAG_IPOL0 2 -#define FLAG_IPOL1 4 - -/////////////////////////////////////////////////////////// - -// MAIN CHANNEL STRUCT -typedef struct -{ - // no mutexes used anymore... don't need them to sync access - //HANDLE hMutex; - - int bNew; // start flag - - int iSBPos; // mixing stuff - int spos; - int sinc; - int SB[32+32]; // Pete added another 32 dwords in 1.6 ... prevents overflow issues with gaussian/cubic interpolation (thanx xodnizel!), and can be used for even better interpolations, eh? :) - int sval; - - unsigned char * pStart; // start ptr into sound mem - unsigned char * pCurr; // current pos in sound mem - unsigned char * pLoop; // loop ptr in sound mem - - int iStartAdr; - int iLoopAdr; - int iNextAdr; - - int bOn; // is channel active (sample playing?) - int bStop; // is channel stopped (sample _can_ still be playing, ADSR Release phase) - int bEndPoint; // end point reached - int bReverbL; // can we do reverb on this channel? must have ctrl register bit, to get active - int bReverbR; - - int bVolumeL; // Volume on/off - int bVolumeR; - - int iActFreq; // current psx pitch - int iUsedFreq; // current pc pitch - int iLeftVolume; // left volume - int iLeftVolRaw; // left psx volume value - int bIgnoreLoop; // ignore loop bit, if an external loop address is used - int iMute; // mute mode - int iRightVolume; // right volume - int iRightVolRaw; // right psx volume value - int iRawPitch; // raw pitch (0...3fff) - int iIrqDone; // debug irq done flag - int s_1; // last decoding infos - int s_2; - int bRVBActive; // reverb active flag - int bNoise; // noise active flag - int bFMod; // freq mod (0=off, 1=sound channel, 2=freq channel) - int iOldNoise; // old noise val for this channel - ADSRInfo ADSR; // active ADSR settings - ADSRInfoEx ADSRX; // next ADSR settings (will be moved to active on sample start) - -} SPUCHAN; - -/////////////////////////////////////////////////////////// - -typedef struct -{ - int StartAddr; // reverb area start addr in samples - int EndAddr; // reverb area end addr in samples - int CurrAddr; // reverb area curr addr in samples - - int VolLeft; - int VolRight; - int iLastRVBLeft; - int iLastRVBRight; - int iRVBLeft; - int iRVBRight; - int iCnt; - - int FB_SRC_A; // (offset) - int FB_SRC_B; // (offset) - int IIR_ALPHA; // (coef.) - int ACC_COEF_A; // (coef.) - int ACC_COEF_B; // (coef.) - int ACC_COEF_C; // (coef.) - int ACC_COEF_D; // (coef.) - int IIR_COEF; // (coef.) - int FB_ALPHA; // (coef.) - int FB_X; // (coef.) - int IIR_DEST_A0; // (offset) - int IIR_DEST_A1; // (offset) - int ACC_SRC_A0; // (offset) - int ACC_SRC_A1; // (offset) - int ACC_SRC_B0; // (offset) - int ACC_SRC_B1; // (offset) - int IIR_SRC_A0; // (offset) - int IIR_SRC_A1; // (offset) - int IIR_DEST_B0; // (offset) - int IIR_DEST_B1; // (offset) - int ACC_SRC_C0; // (offset) - int ACC_SRC_C1; // (offset) - int ACC_SRC_D0; // (offset) - int ACC_SRC_D1; // (offset) - int IIR_SRC_B1; // (offset) - int IIR_SRC_B0; // (offset) - int MIX_DEST_A0; // (offset) - int MIX_DEST_A1; // (offset) - int MIX_DEST_B0; // (offset) - int MIX_DEST_B1; // (offset) - int IN_COEF_L; // (coef.) - int IN_COEF_R; // (coef.) -} REVERBInfo; - -#ifdef _WINDOWS -//extern HINSTANCE hInst; -//#define WM_MUTE (WM_USER+543) -#endif - -/////////////////////////////////////////////////////////// -// SPU.C globals -/////////////////////////////////////////////////////////// - -#ifndef _IN_SPU - -// psx buffers / addresses - -extern unsigned short regArea[]; -extern unsigned short spuMem[]; -extern unsigned char * spuMemC; -extern unsigned char * pSpuIrq[]; -extern unsigned char * pSpuBuffer; - -// user settings - -extern int iUseXA; -extern int iVolume; -extern int iXAPitch; -extern int iUseTimer; -extern int iSPUIRQWait; -extern int iDebugMode; -extern int iRecordMode; -extern int iUseReverb; -extern int iUseInterpolation; -extern int iDisStereo; -// MISC - -extern SPUCHAN s_chan[]; -extern REVERBInfo rvb[]; - -extern unsigned long dwNoiseVal; -extern unsigned short spuCtrl2[]; -extern unsigned short spuStat2[]; -extern unsigned long spuIrq2[]; -extern unsigned long spuAddr2[]; -extern unsigned long spuRvbAddr2[]; -extern unsigned long spuRvbAEnd2[]; - -extern int bEndThread; -extern int bThreadEnded; -extern int bSpuInit; - -extern int SSumR[]; -extern int SSumL[]; -extern int iCycle; -extern short * pS; -extern unsigned long dwNewChannel2[]; -extern unsigned long dwEndChannel2[]; - -extern int iSpuAsyncWait; - -#ifdef _WINDOWS -//extern HWND hWMain; // window handle -//extern HWND hWDebug; -#endif - -extern void (CALLBACK *cddavCallback)(unsigned short,unsigned short); - -#endif - -/////////////////////////////////////////////////////////// -// CFG.C globals -/////////////////////////////////////////////////////////// - -#ifndef _IN_CFG - -#ifndef _WINDOWS -extern char * pConfigFile; -#endif - -#endif - -/////////////////////////////////////////////////////////// -// DSOUND.C globals -/////////////////////////////////////////////////////////// - -#ifndef _IN_DSOUND - -#ifdef _WINDOWS -extern unsigned long LastWrite; -extern unsigned long LastPlay; -#endif - -#endif - -/////////////////////////////////////////////////////////// -// RECORD.C globals -/////////////////////////////////////////////////////////// - -#ifndef _IN_RECORD - -#ifdef _WINDOWS -extern int iDoRecord; -#endif - -#endif - -/////////////////////////////////////////////////////////// -// XA.C globals -/////////////////////////////////////////////////////////// - -#ifndef _IN_XA - -extern xa_decode_t * xapGlobal; - -extern unsigned long * XAFeed; -extern unsigned long * XAPlay; -extern unsigned long * XAStart; -extern unsigned long * XAEnd; - -extern unsigned long XARepeat; -extern unsigned long XALastVal; - -extern int iLeftXAVol; -extern int iRightXAVol; - -#endif - -/////////////////////////////////////////////////////////// -// REVERB.C globals -/////////////////////////////////////////////////////////// - -#ifndef _IN_REVERB - -extern int * sRVBPlay[]; -extern int * sRVBEnd[]; -extern int * sRVBStart[]; - -#endif - -#endif // PEOPS2_EXTERNALS diff --git a/Frameworks/AudioOverload/aosdk/eng_psf/peops2/gauss_i.h b/Frameworks/AudioOverload/aosdk/eng_psf/peops2/gauss_i.h deleted file mode 100644 index 83ecf5b7a..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_psf/peops2/gauss_i.h +++ /dev/null @@ -1,162 +0,0 @@ -/*************************************************************************** - gauss_i.h - description - ----------------------- - begin : Sun Feb 08 2003 - copyright : (C) 2003 by Chris Moeller, eh, whatever - email : chris@kode54.tk - ***************************************************************************/ - -/*************************************************************************** - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. See also the license.txt file for * - * additional informations. * - * * - ***************************************************************************/ - -//*************************************************************************// -// History of changes: -// -// 2003/02/08 - kode54 -// - generated by interleaving table from gauss.h from the libopenspc -// project; a gaussian bell curve table logged from the SPC-700, -// though Neill says he logged the same curve from a PSX SPU. Also -// says that interleaving the coefficients together runs faster. Meh. -// -//*************************************************************************// - -#ifndef GAUSS_H -#define GAUSS_H - -static const int gauss[]={ - 0x172, 0x519, 0x176, 0x000, 0x16E, 0x519, 0x17A, 0x000, - 0x16A, 0x518, 0x17D, 0x000, 0x166, 0x518, 0x181, 0x000, - 0x162, 0x518, 0x185, 0x000, 0x15F, 0x518, 0x189, 0x000, - 0x15B, 0x518, 0x18D, 0x000, 0x157, 0x517, 0x191, 0x000, - 0x153, 0x517, 0x195, 0x000, 0x150, 0x517, 0x19A, 0x000, - 0x14C, 0x516, 0x19E, 0x000, 0x148, 0x516, 0x1A2, 0x000, - 0x145, 0x515, 0x1A6, 0x000, 0x141, 0x514, 0x1AA, 0x000, - 0x13E, 0x514, 0x1AE, 0x000, 0x13A, 0x513, 0x1B2, 0x000, - 0x137, 0x512, 0x1B7, 0x001, 0x133, 0x511, 0x1BB, 0x001, - 0x130, 0x511, 0x1BF, 0x001, 0x12C, 0x510, 0x1C3, 0x001, - 0x129, 0x50F, 0x1C8, 0x001, 0x125, 0x50E, 0x1CC, 0x001, - 0x122, 0x50D, 0x1D0, 0x001, 0x11E, 0x50C, 0x1D5, 0x001, - 0x11B, 0x50B, 0x1D9, 0x001, 0x118, 0x50A, 0x1DD, 0x001, - 0x114, 0x508, 0x1E2, 0x001, 0x111, 0x507, 0x1E6, 0x002, - 0x10E, 0x506, 0x1EB, 0x002, 0x10B, 0x504, 0x1EF, 0x002, - 0x107, 0x503, 0x1F3, 0x002, 0x104, 0x502, 0x1F8, 0x002, - 0x101, 0x500, 0x1FC, 0x002, 0x0FE, 0x4FF, 0x201, 0x002, - 0x0FB, 0x4FD, 0x205, 0x003, 0x0F8, 0x4FB, 0x20A, 0x003, - 0x0F5, 0x4FA, 0x20F, 0x003, 0x0F2, 0x4F8, 0x213, 0x003, - 0x0EF, 0x4F6, 0x218, 0x003, 0x0EC, 0x4F5, 0x21C, 0x004, - 0x0E9, 0x4F3, 0x221, 0x004, 0x0E6, 0x4F1, 0x226, 0x004, - 0x0E3, 0x4EF, 0x22A, 0x004, 0x0E0, 0x4ED, 0x22F, 0x004, - 0x0DD, 0x4EB, 0x233, 0x005, 0x0DA, 0x4E9, 0x238, 0x005, - 0x0D7, 0x4E7, 0x23D, 0x005, 0x0D4, 0x4E5, 0x241, 0x005, - 0x0D2, 0x4E3, 0x246, 0x006, 0x0CF, 0x4E0, 0x24B, 0x006, - 0x0CC, 0x4DE, 0x250, 0x006, 0x0C9, 0x4DC, 0x254, 0x006, - 0x0C7, 0x4D9, 0x259, 0x007, 0x0C4, 0x4D7, 0x25E, 0x007, - 0x0C1, 0x4D5, 0x263, 0x007, 0x0BF, 0x4D2, 0x267, 0x008, - 0x0BC, 0x4D0, 0x26C, 0x008, 0x0BA, 0x4CD, 0x271, 0x008, - 0x0B7, 0x4CB, 0x276, 0x009, 0x0B4, 0x4C8, 0x27B, 0x009, - 0x0B2, 0x4C5, 0x280, 0x009, 0x0AF, 0x4C3, 0x284, 0x00A, - 0x0AD, 0x4C0, 0x289, 0x00A, 0x0AB, 0x4BD, 0x28E, 0x00A, - 0x0A8, 0x4BA, 0x293, 0x00B, 0x0A6, 0x4B7, 0x298, 0x00B, - 0x0A3, 0x4B5, 0x29D, 0x00B, 0x0A1, 0x4B2, 0x2A2, 0x00C, - 0x09F, 0x4AF, 0x2A6, 0x00C, 0x09C, 0x4AC, 0x2AB, 0x00D, - 0x09A, 0x4A9, 0x2B0, 0x00D, 0x098, 0x4A6, 0x2B5, 0x00E, - 0x096, 0x4A2, 0x2BA, 0x00E, 0x093, 0x49F, 0x2BF, 0x00F, - 0x091, 0x49C, 0x2C4, 0x00F, 0x08F, 0x499, 0x2C9, 0x00F, - 0x08D, 0x496, 0x2CE, 0x010, 0x08B, 0x492, 0x2D3, 0x010, - 0x089, 0x48F, 0x2D8, 0x011, 0x086, 0x48C, 0x2DC, 0x011, - 0x084, 0x488, 0x2E1, 0x012, 0x082, 0x485, 0x2E6, 0x013, - 0x080, 0x481, 0x2EB, 0x013, 0x07E, 0x47E, 0x2F0, 0x014, - 0x07C, 0x47A, 0x2F5, 0x014, 0x07A, 0x477, 0x2FA, 0x015, - 0x078, 0x473, 0x2FF, 0x015, 0x076, 0x470, 0x304, 0x016, - 0x075, 0x46C, 0x309, 0x017, 0x073, 0x468, 0x30E, 0x017, - 0x071, 0x465, 0x313, 0x018, 0x06F, 0x461, 0x318, 0x018, - 0x06D, 0x45D, 0x31D, 0x019, 0x06B, 0x459, 0x322, 0x01A, - 0x06A, 0x455, 0x326, 0x01B, 0x068, 0x452, 0x32B, 0x01B, - 0x066, 0x44E, 0x330, 0x01C, 0x064, 0x44A, 0x335, 0x01D, - 0x063, 0x446, 0x33A, 0x01D, 0x061, 0x442, 0x33F, 0x01E, - 0x05F, 0x43E, 0x344, 0x01F, 0x05E, 0x43A, 0x349, 0x020, - 0x05C, 0x436, 0x34E, 0x020, 0x05A, 0x432, 0x353, 0x021, - 0x059, 0x42E, 0x357, 0x022, 0x057, 0x42A, 0x35C, 0x023, - 0x056, 0x425, 0x361, 0x024, 0x054, 0x421, 0x366, 0x024, - 0x053, 0x41D, 0x36B, 0x025, 0x051, 0x419, 0x370, 0x026, - 0x050, 0x415, 0x374, 0x027, 0x04E, 0x410, 0x379, 0x028, - 0x04D, 0x40C, 0x37E, 0x029, 0x04C, 0x408, 0x383, 0x02A, - 0x04A, 0x403, 0x388, 0x02B, 0x049, 0x3FF, 0x38C, 0x02C, - 0x047, 0x3FB, 0x391, 0x02D, 0x046, 0x3F6, 0x396, 0x02E, - 0x045, 0x3F2, 0x39B, 0x02F, 0x043, 0x3ED, 0x39F, 0x030, - 0x042, 0x3E9, 0x3A4, 0x031, 0x041, 0x3E5, 0x3A9, 0x032, - 0x040, 0x3E0, 0x3AD, 0x033, 0x03E, 0x3DC, 0x3B2, 0x034, - 0x03D, 0x3D7, 0x3B7, 0x035, 0x03C, 0x3D2, 0x3BB, 0x036, - 0x03B, 0x3CE, 0x3C0, 0x037, 0x03A, 0x3C9, 0x3C5, 0x038, - 0x038, 0x3C5, 0x3C9, 0x03A, 0x037, 0x3C0, 0x3CE, 0x03B, - 0x036, 0x3BB, 0x3D2, 0x03C, 0x035, 0x3B7, 0x3D7, 0x03D, - 0x034, 0x3B2, 0x3DC, 0x03E, 0x033, 0x3AD, 0x3E0, 0x040, - 0x032, 0x3A9, 0x3E5, 0x041, 0x031, 0x3A4, 0x3E9, 0x042, - 0x030, 0x39F, 0x3ED, 0x043, 0x02F, 0x39B, 0x3F2, 0x045, - 0x02E, 0x396, 0x3F6, 0x046, 0x02D, 0x391, 0x3FB, 0x047, - 0x02C, 0x38C, 0x3FF, 0x049, 0x02B, 0x388, 0x403, 0x04A, - 0x02A, 0x383, 0x408, 0x04C, 0x029, 0x37E, 0x40C, 0x04D, - 0x028, 0x379, 0x410, 0x04E, 0x027, 0x374, 0x415, 0x050, - 0x026, 0x370, 0x419, 0x051, 0x025, 0x36B, 0x41D, 0x053, - 0x024, 0x366, 0x421, 0x054, 0x024, 0x361, 0x425, 0x056, - 0x023, 0x35C, 0x42A, 0x057, 0x022, 0x357, 0x42E, 0x059, - 0x021, 0x353, 0x432, 0x05A, 0x020, 0x34E, 0x436, 0x05C, - 0x020, 0x349, 0x43A, 0x05E, 0x01F, 0x344, 0x43E, 0x05F, - 0x01E, 0x33F, 0x442, 0x061, 0x01D, 0x33A, 0x446, 0x063, - 0x01D, 0x335, 0x44A, 0x064, 0x01C, 0x330, 0x44E, 0x066, - 0x01B, 0x32B, 0x452, 0x068, 0x01B, 0x326, 0x455, 0x06A, - 0x01A, 0x322, 0x459, 0x06B, 0x019, 0x31D, 0x45D, 0x06D, - 0x018, 0x318, 0x461, 0x06F, 0x018, 0x313, 0x465, 0x071, - 0x017, 0x30E, 0x468, 0x073, 0x017, 0x309, 0x46C, 0x075, - 0x016, 0x304, 0x470, 0x076, 0x015, 0x2FF, 0x473, 0x078, - 0x015, 0x2FA, 0x477, 0x07A, 0x014, 0x2F5, 0x47A, 0x07C, - 0x014, 0x2F0, 0x47E, 0x07E, 0x013, 0x2EB, 0x481, 0x080, - 0x013, 0x2E6, 0x485, 0x082, 0x012, 0x2E1, 0x488, 0x084, - 0x011, 0x2DC, 0x48C, 0x086, 0x011, 0x2D8, 0x48F, 0x089, - 0x010, 0x2D3, 0x492, 0x08B, 0x010, 0x2CE, 0x496, 0x08D, - 0x00F, 0x2C9, 0x499, 0x08F, 0x00F, 0x2C4, 0x49C, 0x091, - 0x00F, 0x2BF, 0x49F, 0x093, 0x00E, 0x2BA, 0x4A2, 0x096, - 0x00E, 0x2B5, 0x4A6, 0x098, 0x00D, 0x2B0, 0x4A9, 0x09A, - 0x00D, 0x2AB, 0x4AC, 0x09C, 0x00C, 0x2A6, 0x4AF, 0x09F, - 0x00C, 0x2A2, 0x4B2, 0x0A1, 0x00B, 0x29D, 0x4B5, 0x0A3, - 0x00B, 0x298, 0x4B7, 0x0A6, 0x00B, 0x293, 0x4BA, 0x0A8, - 0x00A, 0x28E, 0x4BD, 0x0AB, 0x00A, 0x289, 0x4C0, 0x0AD, - 0x00A, 0x284, 0x4C3, 0x0AF, 0x009, 0x280, 0x4C5, 0x0B2, - 0x009, 0x27B, 0x4C8, 0x0B4, 0x009, 0x276, 0x4CB, 0x0B7, - 0x008, 0x271, 0x4CD, 0x0BA, 0x008, 0x26C, 0x4D0, 0x0BC, - 0x008, 0x267, 0x4D2, 0x0BF, 0x007, 0x263, 0x4D5, 0x0C1, - 0x007, 0x25E, 0x4D7, 0x0C4, 0x007, 0x259, 0x4D9, 0x0C7, - 0x006, 0x254, 0x4DC, 0x0C9, 0x006, 0x250, 0x4DE, 0x0CC, - 0x006, 0x24B, 0x4E0, 0x0CF, 0x006, 0x246, 0x4E3, 0x0D2, - 0x005, 0x241, 0x4E5, 0x0D4, 0x005, 0x23D, 0x4E7, 0x0D7, - 0x005, 0x238, 0x4E9, 0x0DA, 0x005, 0x233, 0x4EB, 0x0DD, - 0x004, 0x22F, 0x4ED, 0x0E0, 0x004, 0x22A, 0x4EF, 0x0E3, - 0x004, 0x226, 0x4F1, 0x0E6, 0x004, 0x221, 0x4F3, 0x0E9, - 0x004, 0x21C, 0x4F5, 0x0EC, 0x003, 0x218, 0x4F6, 0x0EF, - 0x003, 0x213, 0x4F8, 0x0F2, 0x003, 0x20F, 0x4FA, 0x0F5, - 0x003, 0x20A, 0x4FB, 0x0F8, 0x003, 0x205, 0x4FD, 0x0FB, - 0x002, 0x201, 0x4FF, 0x0FE, 0x002, 0x1FC, 0x500, 0x101, - 0x002, 0x1F8, 0x502, 0x104, 0x002, 0x1F3, 0x503, 0x107, - 0x002, 0x1EF, 0x504, 0x10B, 0x002, 0x1EB, 0x506, 0x10E, - 0x002, 0x1E6, 0x507, 0x111, 0x001, 0x1E2, 0x508, 0x114, - 0x001, 0x1DD, 0x50A, 0x118, 0x001, 0x1D9, 0x50B, 0x11B, - 0x001, 0x1D5, 0x50C, 0x11E, 0x001, 0x1D0, 0x50D, 0x122, - 0x001, 0x1CC, 0x50E, 0x125, 0x001, 0x1C8, 0x50F, 0x129, - 0x001, 0x1C3, 0x510, 0x12C, 0x001, 0x1BF, 0x511, 0x130, - 0x001, 0x1BB, 0x511, 0x133, 0x001, 0x1B7, 0x512, 0x137, - 0x000, 0x1B2, 0x513, 0x13A, 0x000, 0x1AE, 0x514, 0x13E, - 0x000, 0x1AA, 0x514, 0x141, 0x000, 0x1A6, 0x515, 0x145, - 0x000, 0x1A2, 0x516, 0x148, 0x000, 0x19E, 0x516, 0x14C, - 0x000, 0x19A, 0x517, 0x150, 0x000, 0x195, 0x517, 0x153, - 0x000, 0x191, 0x517, 0x157, 0x000, 0x18D, 0x518, 0x15B, - 0x000, 0x189, 0x518, 0x15F, 0x000, 0x185, 0x518, 0x162, - 0x000, 0x181, 0x518, 0x166, 0x000, 0x17D, 0x518, 0x16A, - 0x000, 0x17A, 0x519, 0x16E, 0x000, 0x176, 0x519, 0x172}; -#endif diff --git a/Frameworks/AudioOverload/aosdk/eng_psf/peops2/psemuxa.h b/Frameworks/AudioOverload/aosdk/eng_psf/peops2/psemuxa.h deleted file mode 100755 index 84c626043..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_psf/peops2/psemuxa.h +++ /dev/null @@ -1,28 +0,0 @@ -//============================================ -//=== Audio XA decoding -//=== Kazzuya -//============================================ - -#ifndef DECODEXA_H -#define DECODEXA_H - -typedef struct -{ - long y0, y1; -} ADPCM_Decode_t; - -typedef struct -{ - int freq; - int nbits; - int stereo; - int nsamples; - ADPCM_Decode_t left, right; - short pcm[16384]; -} xa_decode_t; - -long xa_decode_sector( xa_decode_t *xdp, - unsigned char *sectorp, - int is_first_sector ); - -#endif diff --git a/Frameworks/AudioOverload/aosdk/eng_psf/peops2/registers.c b/Frameworks/AudioOverload/aosdk/eng_psf/peops2/registers.c deleted file mode 100644 index 0f3a82423..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_psf/peops2/registers.c +++ /dev/null @@ -1,1343 +0,0 @@ -/*************************************************************************** - registers.c - description - ------------------- - begin : Wed May 15 2002 - copyright : (C) 2002 by Pete Bernert - email : BlackDove@addcom.de - ***************************************************************************/ - -/*************************************************************************** - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. See also the license.txt file for * - * additional informations. * - * * - ***************************************************************************/ - -//*************************************************************************// -// History of changes: -// -// 2004/04/04 - Pete -// - changed plugin to emulate PS2 spu -// -// 2003/02/09 - kode54 -// - removed &0x3fff from reverb volume registers, fixes a few games, -// hopefully won't be breaking anything -// -// 2003/01/19 - Pete -// - added Neill's reverb -// -// 2003/01/06 - Pete -// - added Neill's ADSR timings -// -// 2002/05/15 - Pete -// - generic cleanup for the Peops release -// -//*************************************************************************// - -#include "stdafx.h" - -#define _IN_REGISTERS - -#include "../peops2/externals.h" -#include "../peops2/registers.h" -#include "../peops2/regs.h" -#include "../peops2/reverb.h" - -/* -// adsr time values (in ms) by James Higgs ... see the end of -// the adsr.c source for details - -#define ATTACK_MS 514L -#define DECAYHALF_MS 292L -#define DECAY_MS 584L -#define SUSTAIN_MS 450L -#define RELEASE_MS 446L -*/ - -// we have a timebase of 1.020408f ms, not 1 ms... so adjust adsr defines -#define ATTACK_MS 494L -#define DECAYHALF_MS 286L -#define DECAY_MS 572L -#define SUSTAIN_MS 441L -#define RELEASE_MS 437L - -// Prototypes -void SetVolumeL(unsigned char ch,short vol); -void SetVolumeR(unsigned char ch,short vol); -void ReverbOn(int start,int end,unsigned short val,int iRight); -void SetReverbAddr(int core); -void VolumeOn(int start,int end,unsigned short val,int iRight); - -//////////////////////////////////////////////////////////////////////// -// WRITE REGISTERS: called by main emu -//////////////////////////////////////////////////////////////////////// - -EXPORT_GCC void CALLBACK SPU2write(unsigned long reg, unsigned short val) -{ - long r=reg&0xffff; - - regArea[r>>1] = val; - -// printf("SPU2: %04x to %08x\n", val, reg); - - if((r>=0x0000 && r<0x0180)||(r>=0x0400 && r<0x0580)) // some channel info? - { - int ch=(r>>4)&0x1f; - if(r>=0x400) ch+=24; - - switch(r&0x0f) - { - //------------------------------------------------// r volume - case 0: - SetVolumeL((unsigned char)ch,val); - break; - //------------------------------------------------// l volume - case 2: - SetVolumeR((unsigned char)ch,val); - break; - //------------------------------------------------// pitch - case 4: - SetPitch(ch,val); - break; - //------------------------------------------------// level with pre-calcs - case 6: - { - const unsigned long lval=val;unsigned long lx; - //---------------------------------------------// - s_chan[ch].ADSRX.AttackModeExp=(lval&0x8000)?1:0; - s_chan[ch].ADSRX.AttackRate=(lval>>8) & 0x007f; - s_chan[ch].ADSRX.DecayRate=(lval>>4) & 0x000f; - s_chan[ch].ADSRX.SustainLevel=lval & 0x000f; - //---------------------------------------------// - if(!iDebugMode) break; - //---------------------------------------------// stuff below is only for debug mode - - s_chan[ch].ADSR.AttackModeExp=(lval&0x8000)?1:0; //0x007f - - lx=(((lval>>8) & 0x007f)>>2); // attack time to run from 0 to 100% volume - lx=min(31,lx); // no overflow on shift! - if(lx) - { - lx = (1<>4) & 0x000f; // decay: - if(lx) // our const decay value is time it takes from 100% to 0% of volume - { - lx = ((1<<(lx))*DECAY_MS)/10000L; - if(!lx) lx=1; - } - s_chan[ch].ADSR.DecayTime = // so calc how long does it take to run from 100% to the wanted sus level - (lx*(1024-s_chan[ch].ADSR.SustainLevel))/1024; - } - break; - //------------------------------------------------// adsr times with pre-calcs - case 8: - { - const unsigned long lval=val;unsigned long lx; - - //----------------------------------------------// - s_chan[ch].ADSRX.SustainModeExp = (lval&0x8000)?1:0; - s_chan[ch].ADSRX.SustainIncrease= (lval&0x4000)?0:1; - s_chan[ch].ADSRX.SustainRate = (lval>>6) & 0x007f; - s_chan[ch].ADSRX.ReleaseModeExp = (lval&0x0020)?1:0; - s_chan[ch].ADSRX.ReleaseRate = lval & 0x001f; - //----------------------------------------------// - if(!iDebugMode) break; - //----------------------------------------------// stuff below is only for debug mode - - s_chan[ch].ADSR.SustainModeExp = (lval&0x8000)?1:0; - s_chan[ch].ADSR.ReleaseModeExp = (lval&0x0020)?1:0; - - lx=((((lval>>6) & 0x007f)>>2)); // sustain time... often very high - lx=min(31,lx); // values are used to hold the volume - if(lx) // until a sound stop occurs - { // the highest value we reach (due to - lx = (1<=0x01c0 && r<0x02E0)||(r>=0x05c0 && r<0x06E0)) // some channel info? - { - int ch=0; - if(r>=0x400) {ch=24;r-=0x400;} - - ch+=(r-0x1c0)/12; - r-=(ch%24)*12; - switch(r) - { - //------------------------------------------------// - case 0x1C0: - s_chan[ch].iStartAdr=(((unsigned long)val&0xf)<<16)|(s_chan[ch].iStartAdr&0xFFFF); - s_chan[ch].pStart=spuMemC+(s_chan[ch].iStartAdr<<1); - break; - case 0x1C2: - s_chan[ch].iStartAdr=(s_chan[ch].iStartAdr & 0xF0000) | (val & 0xFFFF); - s_chan[ch].pStart=spuMemC+(s_chan[ch].iStartAdr<<1); - break; - //------------------------------------------------// - case 0x1C4: - s_chan[ch].iLoopAdr=(((unsigned long)val&0xf)<<16)|(s_chan[ch].iLoopAdr&0xFFFF); - s_chan[ch].pLoop=spuMemC+(s_chan[ch].iLoopAdr<<1); - s_chan[ch].bIgnoreLoop=1; - break; - case 0x1C6: - s_chan[ch].iLoopAdr=(s_chan[ch].iLoopAdr & 0xF0000) | (val & 0xFFFF); - s_chan[ch].pLoop=spuMemC+(s_chan[ch].iLoopAdr<<1); - s_chan[ch].bIgnoreLoop=1; - break; - //------------------------------------------------// - case 0x1C8: - // unused... check if it gets written as well - s_chan[ch].iNextAdr=(((unsigned long)val&0xf)<<16)|(s_chan[ch].iNextAdr&0xFFFF); - break; - case 0x1CA: - // unused... check if it gets written as well - s_chan[ch].iNextAdr=(s_chan[ch].iNextAdr & 0xF0000) | (val & 0xFFFF); - break; - //------------------------------------------------// - } - - iSpuAsyncWait=0; - - return; - } - - switch(r) - { - //-------------------------------------------------// - case PS2_C0_SPUaddr_Hi: - spuAddr2[0] = (((unsigned long)val&0xf)<<16)|(spuAddr2[0]&0xFFFF); - break; - //-------------------------------------------------// - case PS2_C0_SPUaddr_Lo: - spuAddr2[0] = (spuAddr2[0] & 0xF0000) | (val & 0xFFFF); - break; - //-------------------------------------------------// - case PS2_C1_SPUaddr_Hi: - spuAddr2[1] = (((unsigned long)val&0xf)<<16)|(spuAddr2[1]&0xFFFF); - break; - //-------------------------------------------------// - case PS2_C1_SPUaddr_Lo: - spuAddr2[1] = (spuAddr2[1] & 0xF0000) | (val & 0xFFFF); - break; - //-------------------------------------------------// - case PS2_C0_SPUdata: - spuMem[spuAddr2[0]] = val; - spuAddr2[0]++; - if(spuAddr2[0]>0xfffff) spuAddr2[0]=0; - break; - //-------------------------------------------------// - case PS2_C1_SPUdata: - spuMem[spuAddr2[1]] = val; - spuAddr2[1]++; - if(spuAddr2[1]>0xfffff) spuAddr2[1]=0; - break; - //-------------------------------------------------// - case PS2_C0_ATTR: - spuCtrl2[0]=val; - break; - //-------------------------------------------------// - case PS2_C1_ATTR: - spuCtrl2[1]=val; - break; - //-------------------------------------------------// - case PS2_C0_SPUstat: - spuStat2[0]=val; - break; - //-------------------------------------------------// - case PS2_C1_SPUstat: - spuStat2[1]=val; - break; - //-------------------------------------------------// - case PS2_C0_ReverbAddr_Hi: - spuRvbAddr2[0] = (((unsigned long)val&0xf)<<16)|(spuRvbAddr2[0]&0xFFFF); - SetReverbAddr(0); - break; - //-------------------------------------------------// - case PS2_C0_ReverbAddr_Lo: - spuRvbAddr2[0] = (spuRvbAddr2[0] & 0xF0000) | (val & 0xFFFF); - SetReverbAddr(0); - break; - //-------------------------------------------------// - case PS2_C0_ReverbAEnd_Hi: - spuRvbAEnd2[0] = (((unsigned long)val&0xf)<<16)|(/*spuRvbAEnd2[0]&*/0xFFFF); - rvb[0].EndAddr=spuRvbAEnd2[0]; - break; - //-------------------------------------------------// - case PS2_C1_ReverbAEnd_Hi: - spuRvbAEnd2[1] = (((unsigned long)val&0xf)<<16)|(/*spuRvbAEnd2[1]&*/0xFFFF); - rvb[1].EndAddr=spuRvbAEnd2[1]; - break; - //-------------------------------------------------// - case PS2_C1_ReverbAddr_Hi: - spuRvbAddr2[1] = (((unsigned long)val&0xf)<<16)|(spuRvbAddr2[1]&0xFFFF); - SetReverbAddr(1); - break; - //-------------------------------------------------// - case PS2_C1_ReverbAddr_Lo: - spuRvbAddr2[1] = (spuRvbAddr2[1] & 0xF0000) | (val & 0xFFFF); - SetReverbAddr(1); - break; - //-------------------------------------------------// - case PS2_C0_SPUirqAddr_Hi: - spuIrq2[0] = (((unsigned long)val&0xf)<<16)|(spuIrq2[0]&0xFFFF); - pSpuIrq[0]=spuMemC+(spuIrq2[0]<<1); - break; - //-------------------------------------------------// - case PS2_C0_SPUirqAddr_Lo: - spuIrq2[0] = (spuIrq2[0] & 0xF0000) | (val & 0xFFFF); - pSpuIrq[0]=spuMemC+(spuIrq2[0]<<1); - break; - //-------------------------------------------------// - case PS2_C1_SPUirqAddr_Hi: - spuIrq2[1] = (((unsigned long)val&0xf)<<16)|(spuIrq2[1]&0xFFFF); - pSpuIrq[1]=spuMemC+(spuIrq2[1]<<1); - break; - //-------------------------------------------------// - case PS2_C1_SPUirqAddr_Lo: - spuIrq2[1] = (spuIrq2[1] & 0xF0000) | (val & 0xFFFF); - pSpuIrq[1]=spuMemC+(spuIrq2[1]<<1); - break; - //-------------------------------------------------// - case PS2_C0_SPUrvolL: - rvb[0].VolLeft=val; - break; - //-------------------------------------------------// - case PS2_C0_SPUrvolR: - rvb[0].VolRight=val; - break; - //-------------------------------------------------// - case PS2_C1_SPUrvolL: - rvb[1].VolLeft=val; - break; - //-------------------------------------------------// - case PS2_C1_SPUrvolR: - rvb[1].VolRight=val; - break; - //-------------------------------------------------// - case PS2_C0_SPUon1: - SoundOn(0,16,val); - break; - //-------------------------------------------------// - case PS2_C0_SPUon2: - SoundOn(16,24,val); - break; - //-------------------------------------------------// - case PS2_C1_SPUon1: - SoundOn(24,40,val); - break; - //-------------------------------------------------// - case PS2_C1_SPUon2: - SoundOn(40,48,val); - break; - //-------------------------------------------------// - case PS2_C0_SPUoff1: - SoundOff(0,16,val); - break; - //-------------------------------------------------// - case PS2_C0_SPUoff2: - SoundOff(16,24,val); - break; - //-------------------------------------------------// - case PS2_C1_SPUoff1: - SoundOff(24,40,val); - break; - //-------------------------------------------------// - case PS2_C1_SPUoff2: - SoundOff(40,48,val); - break; - //-------------------------------------------------// - case PS2_C0_SPUend1: - case PS2_C0_SPUend2: - if(val) dwEndChannel2[0]=0; - break; - //-------------------------------------------------// - case PS2_C1_SPUend1: - case PS2_C1_SPUend2: - if(val) dwEndChannel2[1]=0; - break; - //-------------------------------------------------// - case PS2_C0_FMod1: - FModOn(0,16,val); - break; - //-------------------------------------------------// - case PS2_C0_FMod2: - FModOn(16,24,val); - break; - //-------------------------------------------------// - case PS2_C1_FMod1: - FModOn(24,40,val); - break; - //-------------------------------------------------// - case PS2_C1_FMod2: - FModOn(40,48,val); - break; - //-------------------------------------------------// - case PS2_C0_Noise1: - NoiseOn(0,16,val); - break; - //-------------------------------------------------// - case PS2_C0_Noise2: - NoiseOn(16,24,val); - break; - //-------------------------------------------------// - case PS2_C1_Noise1: - NoiseOn(24,40,val); - break; - //-------------------------------------------------// - case PS2_C1_Noise2: - NoiseOn(40,48,val); - break; - //-------------------------------------------------// - case PS2_C0_DryL1: - VolumeOn(0,16,val,0); - break; - //-------------------------------------------------// - case PS2_C0_DryL2: - VolumeOn(16,24,val,0); - break; - //-------------------------------------------------// - case PS2_C1_DryL1: - VolumeOn(24,40,val,0); - break; - //-------------------------------------------------// - case PS2_C1_DryL2: - VolumeOn(40,48,val,0); - break; - //-------------------------------------------------// - case PS2_C0_DryR1: - VolumeOn(0,16,val,1); - break; - //-------------------------------------------------// - case PS2_C0_DryR2: - VolumeOn(16,24,val,1); - break; - //-------------------------------------------------// - case PS2_C1_DryR1: - VolumeOn(24,40,val,1); - break; - //-------------------------------------------------// - case PS2_C1_DryR2: - VolumeOn(40,48,val,1); - break; - //-------------------------------------------------// - case PS2_C0_RVBon1_L: - ReverbOn(0,16,val,0); - break; - //-------------------------------------------------// - case PS2_C0_RVBon2_L: - ReverbOn(16,24,val,0); - break; - //-------------------------------------------------// - case PS2_C1_RVBon1_L: - ReverbOn(24,40,val,0); - break; - //-------------------------------------------------// - case PS2_C1_RVBon2_L: - ReverbOn(40,48,val,0); - break; - //-------------------------------------------------// - case PS2_C0_RVBon1_R: - ReverbOn(0,16,val,1); - break; - //-------------------------------------------------// - case PS2_C0_RVBon2_R: - ReverbOn(16,24,val,1); - break; - //-------------------------------------------------// - case PS2_C1_RVBon1_R: - ReverbOn(24,40,val,1); - break; - //-------------------------------------------------// - case PS2_C1_RVBon2_R: - ReverbOn(40,48,val,1); - break; - //-------------------------------------------------// - case PS2_C0_Reverb+0: - rvb[0].FB_SRC_A=(((unsigned long)val&0xf)<<16)|(rvb[0].FB_SRC_A&0xFFFF); - break; - case PS2_C0_Reverb+2: - rvb[0].FB_SRC_A=(rvb[0].FB_SRC_A & 0xF0000) | ((val) & 0xFFFF); - break; - case PS2_C0_Reverb+4: - rvb[0].FB_SRC_B=(((unsigned long)val&0xf)<<16)|(rvb[0].FB_SRC_B&0xFFFF); - break; - case PS2_C0_Reverb+6: - rvb[0].FB_SRC_B=(rvb[0].FB_SRC_B & 0xF0000) | ((val) & 0xFFFF); - break; - case PS2_C0_Reverb+8: - rvb[0].IIR_DEST_A0=(((unsigned long)val&0xf)<<16)|(rvb[0].IIR_DEST_A0&0xFFFF); - break; - case PS2_C0_Reverb+10: - rvb[0].IIR_DEST_A0=(rvb[0].IIR_DEST_A0 & 0xF0000) | ((val) & 0xFFFF); - break; - case PS2_C0_Reverb+12: - rvb[0].IIR_DEST_A1=(((unsigned long)val&0xf)<<16)|(rvb[0].IIR_DEST_A1&0xFFFF); - break; - case PS2_C0_Reverb+14: - rvb[0].IIR_DEST_A1=(rvb[0].IIR_DEST_A1 & 0xF0000) | ((val) & 0xFFFF); - break; - case PS2_C0_Reverb+16: - rvb[0].ACC_SRC_A0=(((unsigned long)val&0xf)<<16)|(rvb[0].ACC_SRC_A0&0xFFFF); - break; - case PS2_C0_Reverb+18: - rvb[0].ACC_SRC_A0=(rvb[0].ACC_SRC_A0 & 0xF0000) | ((val) & 0xFFFF); - break; - case PS2_C0_Reverb+20: - rvb[0].ACC_SRC_A1=(((unsigned long)val&0xf)<<16)|(rvb[0].ACC_SRC_A1&0xFFFF); - break; - case PS2_C0_Reverb+22: - rvb[0].ACC_SRC_A1=(rvb[0].ACC_SRC_A1 & 0xF0000) | ((val) & 0xFFFF); - break; - case PS2_C0_Reverb+24: - rvb[0].ACC_SRC_B0=(((unsigned long)val&0xf)<<16)|(rvb[0].ACC_SRC_B0&0xFFFF); - break; - case PS2_C0_Reverb+26: - rvb[0].ACC_SRC_B0=(rvb[0].ACC_SRC_B0 & 0xF0000) | ((val) & 0xFFFF); - break; - case PS2_C0_Reverb+28: - rvb[0].ACC_SRC_B1=(((unsigned long)val&0xf)<<16)|(rvb[0].ACC_SRC_B1&0xFFFF); - break; - case PS2_C0_Reverb+30: - rvb[0].ACC_SRC_B1=(rvb[0].ACC_SRC_B1 & 0xF0000) | ((val) & 0xFFFF); - break; - case PS2_C0_Reverb+32: - rvb[0].IIR_SRC_A0=(((unsigned long)val&0xf)<<16)|(rvb[0].IIR_SRC_A0&0xFFFF); - break; - case PS2_C0_Reverb+34: - rvb[0].IIR_SRC_A0=(rvb[0].IIR_SRC_A0 & 0xF0000) | ((val) & 0xFFFF); - break; - case PS2_C0_Reverb+36: - rvb[0].IIR_SRC_A1=(((unsigned long)val&0xf)<<16)|(rvb[0].IIR_SRC_A1&0xFFFF); - break; - case PS2_C0_Reverb+38: - rvb[0].IIR_SRC_A1=(rvb[0].IIR_SRC_A1 & 0xF0000) | ((val) & 0xFFFF); - break; - case PS2_C0_Reverb+40: - rvb[0].IIR_DEST_B0=(((unsigned long)val&0xf)<<16)|(rvb[0].IIR_DEST_B0&0xFFFF); - break; - case PS2_C0_Reverb+42: - rvb[0].IIR_DEST_B0=(rvb[0].IIR_DEST_B0 & 0xF0000) | ((val) & 0xFFFF); - break; - case PS2_C0_Reverb+44: - rvb[0].IIR_DEST_B1=(((unsigned long)val&0xf)<<16)|(rvb[0].IIR_DEST_B1&0xFFFF); - break; - case PS2_C0_Reverb+46: - rvb[0].IIR_DEST_B1=(rvb[0].IIR_DEST_B1 & 0xF0000) | ((val) & 0xFFFF); - break; - case PS2_C0_Reverb+48: - rvb[0].ACC_SRC_C0=(((unsigned long)val&0xf)<<16)|(rvb[0].ACC_SRC_C0&0xFFFF); - break; - case PS2_C0_Reverb+50: - rvb[0].ACC_SRC_C0=(rvb[0].ACC_SRC_C0 & 0xF0000) | ((val) & 0xFFFF); - break; - case PS2_C0_Reverb+52: - rvb[0].ACC_SRC_C1=(((unsigned long)val&0xf)<<16)|(rvb[0].ACC_SRC_C1&0xFFFF); - break; - case PS2_C0_Reverb+54: - rvb[0].ACC_SRC_C1=(rvb[0].ACC_SRC_C1 & 0xF0000) | ((val) & 0xFFFF); - break; - case PS2_C0_Reverb+56: - rvb[0].ACC_SRC_D0=(((unsigned long)val&0xf)<<16)|(rvb[0].ACC_SRC_D0&0xFFFF); - break; - case PS2_C0_Reverb+58: - rvb[0].ACC_SRC_D0=(rvb[0].ACC_SRC_D0 & 0xF0000) | ((val) & 0xFFFF); - break; - case PS2_C0_Reverb+60: - rvb[0].ACC_SRC_D1=(((unsigned long)val&0xf)<<16)|(rvb[0].ACC_SRC_D1&0xFFFF); - break; - case PS2_C0_Reverb+62: - rvb[0].ACC_SRC_D1=(rvb[0].ACC_SRC_D1 & 0xF0000) | ((val) & 0xFFFF); - break; - case PS2_C0_Reverb+64: - rvb[0].IIR_SRC_B1=(((unsigned long)val&0xf)<<16)|(rvb[0].IIR_SRC_B1&0xFFFF); - break; - case PS2_C0_Reverb+66: - rvb[0].IIR_SRC_B1=(rvb[0].IIR_SRC_B1 & 0xF0000) | ((val) & 0xFFFF); - break; - case PS2_C0_Reverb+68: - rvb[0].IIR_SRC_B0=(((unsigned long)val&0xf)<<16)|(rvb[0].IIR_SRC_B0&0xFFFF); - break; - case PS2_C0_Reverb+70: - rvb[0].IIR_SRC_B0=(rvb[0].IIR_SRC_B0 & 0xF0000) | ((val) & 0xFFFF); - break; - case PS2_C0_Reverb+72: - rvb[0].MIX_DEST_A0=(((unsigned long)val&0xf)<<16)|(rvb[0].MIX_DEST_A0&0xFFFF); - break; - case PS2_C0_Reverb+74: - rvb[0].MIX_DEST_A0=(rvb[0].MIX_DEST_A0 & 0xF0000) | ((val) & 0xFFFF); - break; - case PS2_C0_Reverb+76: - rvb[0].MIX_DEST_A1=(((unsigned long)val&0xf)<<16)|(rvb[0].MIX_DEST_A1&0xFFFF); - break; - case PS2_C0_Reverb+78: - rvb[0].MIX_DEST_A1=(rvb[0].MIX_DEST_A1 & 0xF0000) | ((val) & 0xFFFF); - break; - case PS2_C0_Reverb+80: - rvb[0].MIX_DEST_B0=(((unsigned long)val&0xf)<<16)|(rvb[0].MIX_DEST_B0&0xFFFF); - break; - case PS2_C0_Reverb+82: - rvb[0].MIX_DEST_B0=(rvb[0].MIX_DEST_B0 & 0xF0000) | ((val) & 0xFFFF); - break; - case PS2_C0_Reverb+84: - rvb[0].MIX_DEST_B1=(((unsigned long)val&0xf)<<16)|(rvb[0].MIX_DEST_B1&0xFFFF); - break; - case PS2_C0_Reverb+86: - rvb[0].MIX_DEST_B1=(rvb[0].MIX_DEST_B1 & 0xF0000) | ((val) & 0xFFFF); - break; - case PS2_C0_ReverbX+0: rvb[0].IIR_ALPHA=(short)val; break; - case PS2_C0_ReverbX+2: rvb[0].ACC_COEF_A=(short)val; break; - case PS2_C0_ReverbX+4: rvb[0].ACC_COEF_B=(short)val; break; - case PS2_C0_ReverbX+6: rvb[0].ACC_COEF_C=(short)val; break; - case PS2_C0_ReverbX+8: rvb[0].ACC_COEF_D=(short)val; break; - case PS2_C0_ReverbX+10: rvb[0].IIR_COEF=(short)val; break; - case PS2_C0_ReverbX+12: rvb[0].FB_ALPHA=(short)val; break; - case PS2_C0_ReverbX+14: rvb[0].FB_X=(short)val; break; - case PS2_C0_ReverbX+16: rvb[0].IN_COEF_L=(short)val; break; - case PS2_C0_ReverbX+18: rvb[0].IN_COEF_R=(short)val; break; - //-------------------------------------------------// - case PS2_C1_Reverb+0: - rvb[1].FB_SRC_A=(((unsigned long)val&0xf)<<16)|(rvb[1].FB_SRC_A&0xFFFF); - break; - case PS2_C1_Reverb+2: - rvb[1].FB_SRC_A=(rvb[1].FB_SRC_A & 0xF0000) | ((val) & 0xFFFF); - break; - case PS2_C1_Reverb+4: - rvb[1].FB_SRC_B=(((unsigned long)val&0xf)<<16)|(rvb[1].FB_SRC_B&0xFFFF); - break; - case PS2_C1_Reverb+6: - rvb[1].FB_SRC_B=(rvb[1].FB_SRC_B & 0xF0000) | ((val) & 0xFFFF); - break; - case PS2_C1_Reverb+8: - rvb[1].IIR_DEST_A0=(((unsigned long)val&0xf)<<16)|(rvb[1].IIR_DEST_A0&0xFFFF); - break; - case PS2_C1_Reverb+10: - rvb[1].IIR_DEST_A0=(rvb[1].IIR_DEST_A0 & 0xF0000) | ((val) & 0xFFFF); - break; - case PS2_C1_Reverb+12: - rvb[1].IIR_DEST_A1=(((unsigned long)val&0xf)<<16)|(rvb[1].IIR_DEST_A1&0xFFFF); - break; - case PS2_C1_Reverb+14: - rvb[1].IIR_DEST_A1=(rvb[1].IIR_DEST_A1 & 0xF0000) | ((val) & 0xFFFF); - break; - case PS2_C1_Reverb+16: - rvb[1].ACC_SRC_A0=(((unsigned long)val&0xf)<<16)|(rvb[1].ACC_SRC_A0&0xFFFF); - break; - case PS2_C1_Reverb+18: - rvb[1].ACC_SRC_A0=(rvb[1].ACC_SRC_A0 & 0xF0000) | ((val) & 0xFFFF); - break; - case PS2_C1_Reverb+20: - rvb[1].ACC_SRC_A1=(((unsigned long)val&0xf)<<16)|(rvb[1].ACC_SRC_A1&0xFFFF); - break; - case PS2_C1_Reverb+22: - rvb[1].ACC_SRC_A1=(rvb[1].ACC_SRC_A1 & 0xF0000) | ((val) & 0xFFFF); - break; - case PS2_C1_Reverb+24: - rvb[1].ACC_SRC_B0=(((unsigned long)val&0xf)<<16)|(rvb[1].ACC_SRC_B0&0xFFFF); - break; - case PS2_C1_Reverb+26: - rvb[1].ACC_SRC_B0=(rvb[1].ACC_SRC_B0 & 0xF0000) | ((val) & 0xFFFF); - break; - case PS2_C1_Reverb+28: - rvb[1].ACC_SRC_B1=(((unsigned long)val&0xf)<<16)|(rvb[1].ACC_SRC_B1&0xFFFF); - break; - case PS2_C1_Reverb+30: - rvb[1].ACC_SRC_B1=(rvb[1].ACC_SRC_B1 & 0xF0000) | ((val) & 0xFFFF); - break; - case PS2_C1_Reverb+32: - rvb[1].IIR_SRC_A0=(((unsigned long)val&0xf)<<16)|(rvb[1].IIR_SRC_A0&0xFFFF); - break; - case PS2_C1_Reverb+34: - rvb[1].IIR_SRC_A0=(rvb[1].IIR_SRC_A0 & 0xF0000) | ((val) & 0xFFFF); - break; - case PS2_C1_Reverb+36: - rvb[1].IIR_SRC_A1=(((unsigned long)val&0xf)<<16)|(rvb[1].IIR_SRC_A1&0xFFFF); - break; - case PS2_C1_Reverb+38: - rvb[1].IIR_SRC_A1=(rvb[1].IIR_SRC_A1 & 0xF0000) | ((val) & 0xFFFF); - break; - case PS2_C1_Reverb+40: - rvb[1].IIR_DEST_B0=(((unsigned long)val&0xf)<<16)|(rvb[1].IIR_DEST_B0&0xFFFF); - break; - case PS2_C1_Reverb+42: - rvb[1].IIR_DEST_B0=(rvb[1].IIR_DEST_B0 & 0xF0000) | ((val) & 0xFFFF); - break; - case PS2_C1_Reverb+44: - rvb[1].IIR_DEST_B1=(((unsigned long)val&0xf)<<16)|(rvb[1].IIR_DEST_B1&0xFFFF); - break; - case PS2_C1_Reverb+46: - rvb[1].IIR_DEST_B1=(rvb[1].IIR_DEST_B1 & 0xF0000) | ((val) & 0xFFFF); - break; - case PS2_C1_Reverb+48: - rvb[1].ACC_SRC_C0=(((unsigned long)val&0xf)<<16)|(rvb[1].ACC_SRC_C0&0xFFFF); - break; - case PS2_C1_Reverb+50: - rvb[1].ACC_SRC_C0=(rvb[1].ACC_SRC_C0 & 0xF0000) | ((val) & 0xFFFF); - break; - case PS2_C1_Reverb+52: - rvb[1].ACC_SRC_C1=(((unsigned long)val&0xf)<<16)|(rvb[1].ACC_SRC_C1&0xFFFF); - break; - case PS2_C1_Reverb+54: - rvb[1].ACC_SRC_C1=(rvb[1].ACC_SRC_C1 & 0xF0000) | ((val) & 0xFFFF); - break; - case PS2_C1_Reverb+56: - rvb[1].ACC_SRC_D0=(((unsigned long)val&0xf)<<16)|(rvb[1].ACC_SRC_D0&0xFFFF); - break; - case PS2_C1_Reverb+58: - rvb[1].ACC_SRC_D0=(rvb[1].ACC_SRC_D0 & 0xF0000) | ((val) & 0xFFFF); - break; - case PS2_C1_Reverb+60: - rvb[1].ACC_SRC_D1=(((unsigned long)val&0xf)<<16)|(rvb[1].ACC_SRC_D1&0xFFFF); - break; - case PS2_C1_Reverb+62: - rvb[1].ACC_SRC_D1=(rvb[1].ACC_SRC_D1 & 0xF0000) | ((val) & 0xFFFF); - break; - case PS2_C1_Reverb+64: - rvb[1].IIR_SRC_B1=(((unsigned long)val&0xf)<<16)|(rvb[1].IIR_SRC_B1&0xFFFF); - break; - case PS2_C1_Reverb+66: - rvb[1].IIR_SRC_B1=(rvb[1].IIR_SRC_B1 & 0xF0000) | ((val) & 0xFFFF); - break; - case PS2_C1_Reverb+68: - rvb[1].IIR_SRC_B0=(((unsigned long)val&0xf)<<16)|(rvb[1].IIR_SRC_B0&0xFFFF); - break; - case PS2_C1_Reverb+70: - rvb[1].IIR_SRC_B0=(rvb[1].IIR_SRC_B0 & 0xF0000) | ((val) & 0xFFFF); - break; - case PS2_C1_Reverb+72: - rvb[1].MIX_DEST_A0=(((unsigned long)val&0xf)<<16)|(rvb[1].MIX_DEST_A0&0xFFFF); - break; - case PS2_C1_Reverb+74: - rvb[1].MIX_DEST_A0=(rvb[1].MIX_DEST_A0 & 0xF0000) | ((val) & 0xFFFF); - break; - case PS2_C1_Reverb+76: - rvb[1].MIX_DEST_A1=(((unsigned long)val&0xf)<<16)|(rvb[1].MIX_DEST_A1&0xFFFF); - break; - case PS2_C1_Reverb+78: - rvb[1].MIX_DEST_A1=(rvb[1].MIX_DEST_A1 & 0xF0000) | ((val) & 0xFFFF); - break; - case PS2_C1_Reverb+80: - rvb[1].MIX_DEST_B0=(((unsigned long)val&0xf)<<16)|(rvb[1].MIX_DEST_B0&0xFFFF); - break; - case PS2_C1_Reverb+82: - rvb[1].MIX_DEST_B0=(rvb[1].MIX_DEST_B0 & 0xF0000) | ((val) & 0xFFFF); - break; - case PS2_C1_Reverb+84: - rvb[1].MIX_DEST_B1=(((unsigned long)val&0xf)<<16)|(rvb[1].MIX_DEST_B1&0xFFFF); - break; - case PS2_C1_Reverb+86: - rvb[1].MIX_DEST_B1=(rvb[1].MIX_DEST_B1 & 0xF0000) | ((val) & 0xFFFF); - break; - case PS2_C1_ReverbX+0: rvb[1].IIR_ALPHA=(short)val; break; - case PS2_C1_ReverbX+2: rvb[1].ACC_COEF_A=(short)val; break; - case PS2_C1_ReverbX+4: rvb[1].ACC_COEF_B=(short)val; break; - case PS2_C1_ReverbX+6: rvb[1].ACC_COEF_C=(short)val; break; - case PS2_C1_ReverbX+8: rvb[1].ACC_COEF_D=(short)val; break; - case PS2_C1_ReverbX+10: rvb[1].IIR_COEF=(short)val; break; - case PS2_C1_ReverbX+12: rvb[1].FB_ALPHA=(short)val; break; - case PS2_C1_ReverbX+14: rvb[1].FB_X=(short)val; break; - case PS2_C1_ReverbX+16: rvb[1].IN_COEF_L=(short)val; break; - case PS2_C1_ReverbX+18: rvb[1].IN_COEF_R=(short)val; break; - } - - iSpuAsyncWait=0; - -} - -//////////////////////////////////////////////////////////////////////// -// READ REGISTER: called by main emu -//////////////////////////////////////////////////////////////////////// - -EXPORT_GCC unsigned short CALLBACK SPU2read(unsigned long reg) -{ - long r=reg&0xffff; - -#ifdef _WINDOWS -// if(iDebugMode==1) logprintf("R_REG %X\r\n",reg&0xFFFF); -#endif - - iSpuAsyncWait=0; - - if((r>=0x0000 && r<0x0180)||(r>=0x0400 && r<0x0580)) // some channel info? - { - switch(r&0x0f) - { - //------------------------------------------------// env value - case 10: - { - int ch=(r>>4)&0x1f; - if(r>=0x400) ch+=24; - if(s_chan[ch].bNew) return 1; // we are started, but not processed? return 1 - if(s_chan[ch].ADSRX.lVolume && // same here... we haven't decoded one sample yet, so no envelope yet. return 1 as well - !s_chan[ch].ADSRX.EnvelopeVol) - return 1; - return (unsigned short)(s_chan[ch].ADSRX.EnvelopeVol>>16); - }break; - } - } - - if((r>=0x01c0 && r<0x02E0)||(r>=0x05c0 && r<0x06E0)) // some channel info? - { - int ch=0;unsigned long rx=r; - if(rx>=0x400) {ch=24;rx-=0x400;} - - ch+=(rx-0x1c0)/12; - rx-=(ch%24)*12; - - switch(rx) - { - //------------------------------------------------// - case 0x1C4: - return (((s_chan[ch].pLoop-spuMemC)>>17)&0xF); - break; - case 0x1C6: - return (((s_chan[ch].pLoop-spuMemC)>>1)&0xFFFF); - break; - //------------------------------------------------// - case 0x1C8: - return (((s_chan[ch].pCurr-spuMemC)>>17)&0xF); - break; - case 0x1CA: - return (((s_chan[ch].pCurr-spuMemC)>>1)&0xFFFF); - break; - //------------------------------------------------// - } - } - - switch(r) - { - //--------------------------------------------------// - case PS2_C0_SPUend1: - return (unsigned short)((dwEndChannel2[0]&0xFFFF)); - case PS2_C0_SPUend2: - return (unsigned short)((dwEndChannel2[0]>>16)); - //--------------------------------------------------// - case PS2_C1_SPUend1: - return (unsigned short)((dwEndChannel2[1]&0xFFFF)); - case PS2_C1_SPUend2: - return (unsigned short)((dwEndChannel2[1]>>16)); - //--------------------------------------------------// - case PS2_C0_ATTR: - return spuCtrl2[0]; - break; - //--------------------------------------------------// - case PS2_C1_ATTR: - return spuCtrl2[1]; - break; - //--------------------------------------------------// - case PS2_C0_SPUstat: - return spuStat2[0]; - break; - //--------------------------------------------------// - case PS2_C1_SPUstat: - return spuStat2[1]; - break; - //--------------------------------------------------// - case PS2_C0_SPUdata: - { - unsigned short s=spuMem[spuAddr2[0]]; - spuAddr2[0]++; - if(spuAddr2[0]>0xfffff) spuAddr2[0]=0; - return s; - } - //--------------------------------------------------// - case PS2_C1_SPUdata: - { - unsigned short s=spuMem[spuAddr2[1]]; - spuAddr2[1]++; - if(spuAddr2[1]>0xfffff) spuAddr2[1]=0; - return s; - } - //--------------------------------------------------// - case PS2_C0_SPUaddr_Hi: - return (unsigned short)((spuAddr2[0]>>16)&0xF); - break; - case PS2_C0_SPUaddr_Lo: - return (unsigned short)((spuAddr2[0]&0xFFFF)); - break; - //--------------------------------------------------// - case PS2_C1_SPUaddr_Hi: - return (unsigned short)((spuAddr2[1]>>16)&0xF); - break; - case PS2_C1_SPUaddr_Lo: - return (unsigned short)((spuAddr2[1]&0xFFFF)); - break; - //--------------------------------------------------// - } - - return regArea[r>>1]; -} - -EXPORT_GCC void CALLBACK SPU2writePS1Port(unsigned long reg, unsigned short val) -{ - const u32 r=reg&0xfff; - - if(r>=0xc00 && r<0xd80) // channel info - { - SPU2write(r-0xc00, val); - return; - } - - switch(r) - { - //-------------------------------------------------// - case H_SPUaddr: - spuAddr2[0] = (u32) val<<2; - break; - //-------------------------------------------------// - case H_SPUdata: - spuMem[spuAddr2[0]] = BFLIP16(val); - spuAddr2[0]++; - if(spuAddr2[0]>0xfffff) spuAddr2[0]=0; - break; - //-------------------------------------------------// - case H_SPUctrl: -// spuCtrl=val; - break; - //-------------------------------------------------// - case H_SPUstat: - spuStat2[0]=val & 0xf800; - break; - //-------------------------------------------------// - case H_SPUReverbAddr: - spuRvbAddr2[0] = val; - SetReverbAddr(0); - break; - //-------------------------------------------------// - case H_SPUirqAddr: - spuIrq2[0] = val<<2; - pSpuIrq[0]=spuMemC+((u32) val<<1); - break; - //-------------------------------------------------// - /* Volume settings appear to be at least 15-bit unsigned in this case. - Definitely NOT 15-bit signed. Probably 16-bit signed, so s16 type cast. - Check out "Chrono Cross: Shadow's End Forest" - */ - case H_SPUrvolL: - rvb[0].VolLeft=(s16)val; - //printf("%d\n",val); - break; - //-------------------------------------------------// - case H_SPUrvolR: - rvb[0].VolRight=(s16)val; - //printf("%d\n",val); - break; - //-------------------------------------------------// - -/* - case H_ExtLeft: - //auxprintf("EL %d\n",val); - break; - //-------------------------------------------------// - case H_ExtRight: - //auxprintf("ER %d\n",val); - break; - //-------------------------------------------------// - case H_SPUmvolL: - //auxprintf("ML %d\n",val); - break; - //-------------------------------------------------// - case H_SPUmvolR: - //auxprintf("MR %d\n",val); - break; - //-------------------------------------------------// - case H_SPUMute1: - //printf("M0 %04x\n",val); - break; - //-------------------------------------------------// - case H_SPUMute2: - // printf("M1 %04x\n",val); - break; -*/ - //-------------------------------------------------// - case H_SPUon1: - SoundOn(0,16,val); - break; - //-------------------------------------------------// - case H_SPUon2: - //printf("Boop: %08x: %04x\n",reg,val); - SoundOn(16,24,val); - break; - //-------------------------------------------------// - case H_SPUoff1: - SoundOff(0,16,val); - break; - //-------------------------------------------------// - case H_SPUoff2: - SoundOff(16,24,val); - // printf("Boop: %08x: %04x\n",reg,val); - break; - //-------------------------------------------------// - case H_FMod1: - FModOn(0,16,val); - break; - //-------------------------------------------------// - case H_FMod2: - FModOn(16,24,val); - break; - //-------------------------------------------------// - case H_Noise1: - NoiseOn(0,16,val); - break; - //-------------------------------------------------// - case H_Noise2: - NoiseOn(16,24,val); - break; - //-------------------------------------------------// - case H_RVBon1: - ReverbOn(0,16,val,0); - break; - - //-------------------------------------------------// - case H_RVBon2: - ReverbOn(16,24,val,0); - break; - - //-------------------------------------------------// - case H_Reverb+0: - rvb[0].FB_SRC_A=val; - break; - - case H_Reverb+2 : rvb[0].FB_SRC_B=(s16)val; break; - case H_Reverb+4 : rvb[0].IIR_ALPHA=(s16)val; break; - case H_Reverb+6 : rvb[0].ACC_COEF_A=(s16)val; break; - case H_Reverb+8 : rvb[0].ACC_COEF_B=(s16)val; break; - case H_Reverb+10 : rvb[0].ACC_COEF_C=(s16)val; break; - case H_Reverb+12 : rvb[0].ACC_COEF_D=(s16)val; break; - case H_Reverb+14 : rvb[0].IIR_COEF=(s16)val; break; - case H_Reverb+16 : rvb[0].FB_ALPHA=(s16)val; break; - case H_Reverb+18 : rvb[0].FB_X=(s16)val; break; - case H_Reverb+20 : rvb[0].IIR_DEST_A0=(s16)val; break; - case H_Reverb+22 : rvb[0].IIR_DEST_A1=(s16)val; break; - case H_Reverb+24 : rvb[0].ACC_SRC_A0=(s16)val; break; - case H_Reverb+26 : rvb[0].ACC_SRC_A1=(s16)val; break; - case H_Reverb+28 : rvb[0].ACC_SRC_B0=(s16)val; break; - case H_Reverb+30 : rvb[0].ACC_SRC_B1=(s16)val; break; - case H_Reverb+32 : rvb[0].IIR_SRC_A0=(s16)val; break; - case H_Reverb+34 : rvb[0].IIR_SRC_A1=(s16)val; break; - case H_Reverb+36 : rvb[0].IIR_DEST_B0=(s16)val; break; - case H_Reverb+38 : rvb[0].IIR_DEST_B1=(s16)val; break; - case H_Reverb+40 : rvb[0].ACC_SRC_C0=(s16)val; break; - case H_Reverb+42 : rvb[0].ACC_SRC_C1=(s16)val; break; - case H_Reverb+44 : rvb[0].ACC_SRC_D0=(s16)val; break; - case H_Reverb+46 : rvb[0].ACC_SRC_D1=(s16)val; break; - case H_Reverb+48 : rvb[0].IIR_SRC_B1=(s16)val; break; - case H_Reverb+50 : rvb[0].IIR_SRC_B0=(s16)val; break; - case H_Reverb+52 : rvb[0].MIX_DEST_A0=(s16)val; break; - case H_Reverb+54 : rvb[0].MIX_DEST_A1=(s16)val; break; - case H_Reverb+56 : rvb[0].MIX_DEST_B0=(s16)val; break; - case H_Reverb+58 : rvb[0].MIX_DEST_B1=(s16)val; break; - case H_Reverb+60 : rvb[0].IN_COEF_L=(s16)val; break; - case H_Reverb+62 : rvb[0].IN_COEF_R=(s16)val; break; - } -} - -EXPORT_GCC unsigned short CALLBACK SPU2readPS1Port(unsigned long reg) -{ - const u32 r=reg&0xfff; - - if(r>=0x0c00 && r<0x0d80) - { - return SPU2read(r-0xc00); - } - - switch(r) - { -// case H_SPUctrl: -// return spuCtrl; - break; - - case H_SPUstat: - return spuStat2[0]; - break; - - case H_SPUaddr: - return (u16)(spuAddr2[0]>>2); - break; - - case H_SPUdata: - { - u16 s=BFLIP16(spuMem[spuAddr2[0]]); - spuAddr2[0]++; - if(spuAddr2[0]>0xfffff) spuAddr2[0]=0; - return s; - } - break; - - case H_SPUirqAddr: - return spuIrq2[0]>>2; - break; - } - - return 0; -} - -//////////////////////////////////////////////////////////////////////// -// SOUND ON register write -//////////////////////////////////////////////////////////////////////// - -void SoundOn(int start,int end,unsigned short val) // SOUND ON PSX COMAND -{ - int ch; - - for(ch=start;ch>=1) // loop channels - { - if((val&1) && s_chan[ch].pStart) // mmm... start has to be set before key on !?! - { - s_chan[ch].bIgnoreLoop=0; - s_chan[ch].bNew=1; - dwNewChannel2[ch/24]|=(1<<(ch%24)); // bitfield for faster testing - } - } -} - -//////////////////////////////////////////////////////////////////////// -// SOUND OFF register write -//////////////////////////////////////////////////////////////////////// - -void SoundOff(int start,int end,unsigned short val) // SOUND OFF PSX COMMAND -{ - int ch; - for(ch=start;ch>=1) // loop channels - { - if(val&1) // && s_chan[i].bOn) mmm... - { - s_chan[ch].bStop=1; - } - } -} - -//////////////////////////////////////////////////////////////////////// -// FMOD register write -//////////////////////////////////////////////////////////////////////// - -void FModOn(int start,int end,unsigned short val) // FMOD ON PSX COMMAND -{ - int ch; - - for(ch=start;ch>=1) // loop channels - { - if(val&1) // -> fmod on/off - { - if(ch>0) - { - s_chan[ch].bFMod=1; // --> sound channel - s_chan[ch-1].bFMod=2; // --> freq channel - } - } - else - { - s_chan[ch].bFMod=0; // --> turn off fmod - } - } -} - -//////////////////////////////////////////////////////////////////////// -// NOISE register write -//////////////////////////////////////////////////////////////////////// - -void NoiseOn(int start,int end,unsigned short val) // NOISE ON PSX COMMAND -{ - int ch; - - for(ch=start;ch>=1) // loop channels - { - if(val&1) // -> noise on/off - { - s_chan[ch].bNoise=1; - } - else - { - s_chan[ch].bNoise=0; - } - } -} - -//////////////////////////////////////////////////////////////////////// -// LEFT VOLUME register write -//////////////////////////////////////////////////////////////////////// - -// please note: sweep and phase invert are wrong... but I've never seen -// them used - -void SetVolumeL(unsigned char ch,short vol) // LEFT VOLUME -{ - s_chan[ch].iLeftVolRaw=vol; - - if(vol&0x8000) // sweep? - { - short sInc=1; // -> sweep up? - if(vol&0x2000) sInc=-1; // -> or down? - if(vol&0x1000) vol^=0xffff; // -> mmm... phase inverted? have to investigate this - vol=((vol&0x7f)+1)/2; // -> sweep: 0..127 -> 0..64 - vol+=vol/(2*sInc); // -> HACK: we don't sweep right now, so we just raise/lower the volume by the half! - vol*=128; - } - else // no sweep: - { - if(vol&0x4000) // -> mmm... phase inverted? have to investigate this - //vol^=0xffff; - vol=0x3fff-(vol&0x3fff); - } - - vol&=0x3fff; - s_chan[ch].iLeftVolume=vol; // store volume -} - -//////////////////////////////////////////////////////////////////////// -// RIGHT VOLUME register write -//////////////////////////////////////////////////////////////////////// - -void SetVolumeR(unsigned char ch,short vol) // RIGHT VOLUME -{ - s_chan[ch].iRightVolRaw=vol; - - if(vol&0x8000) // comments... see above :) - { - short sInc=1; - if(vol&0x2000) sInc=-1; - if(vol&0x1000) vol^=0xffff; - vol=((vol&0x7f)+1)/2; - vol+=vol/(2*sInc); - vol*=128; - } - else - { - if(vol&0x4000) //vol=vol^=0xffff; - vol=0x3fff-(vol&0x3fff); - } - - vol&=0x3fff; - s_chan[ch].iRightVolume=vol; -} - -//////////////////////////////////////////////////////////////////////// -// PITCH register write -//////////////////////////////////////////////////////////////////////// - -void SetPitch(int ch,unsigned short val) // SET PITCH -{ - int NP; - double intr; - - if(val>0x3fff) NP=0x3fff; // get pitch val - else NP=val; - - intr = (double)48000.0f / (double)44100.0f * (double)NP; - NP = (UINT32)intr; - - s_chan[ch].iRawPitch=NP; - - NP=(44100L*NP)/4096L; // calc frequency - - if(NP<1) NP=1; // some security - s_chan[ch].iActFreq=NP; // store frequency -} - -//////////////////////////////////////////////////////////////////////// -// REVERB register write -//////////////////////////////////////////////////////////////////////// - -void ReverbOn(int start,int end,unsigned short val,int iRight) // REVERB ON PSX COMMAND -{ - int ch; - - for(ch=start;ch>=1) // loop channels - { - if(val&1) // -> reverb on/off - { - if(iRight) s_chan[ch].bReverbR=1; - else s_chan[ch].bReverbL=1; - } - else - { - if(iRight) s_chan[ch].bReverbR=0; - else s_chan[ch].bReverbL=0; - } - } -} - -//////////////////////////////////////////////////////////////////////// -// REVERB START register write -//////////////////////////////////////////////////////////////////////// - -void SetReverbAddr(int core) -{ - long val=spuRvbAddr2[core]; - - if(rvb[core].StartAddr!=val) - { - if(val<=0x27ff) - { - rvb[core].StartAddr=rvb[core].CurrAddr=0; - } - else - { - rvb[core].StartAddr=val; - rvb[core].CurrAddr=rvb[core].StartAddr; - } - } -} - -//////////////////////////////////////////////////////////////////////// -// DRY LEFT/RIGHT per voice switches -//////////////////////////////////////////////////////////////////////// - -void VolumeOn(int start,int end,unsigned short val,int iRight) // VOLUME ON PSX COMMAND -{ - int ch; - - for(ch=start;ch>=1) // loop channels - { - if(val&1) // -> reverb on/off - { - if(iRight) s_chan[ch].bVolumeR=1; - else s_chan[ch].bVolumeL=1; - } - else - { - if(iRight) s_chan[ch].bVolumeR=0; - else s_chan[ch].bVolumeL=0; - } - } -} - - diff --git a/Frameworks/AudioOverload/aosdk/eng_psf/peops2/registers.h b/Frameworks/AudioOverload/aosdk/eng_psf/peops2/registers.h deleted file mode 100644 index 75e1c3954..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_psf/peops2/registers.h +++ /dev/null @@ -1,845 +0,0 @@ -/*************************************************************************** - registers.h - description - ***************************************************************************/ - -/*************************************************************************** - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. See also the license.txt file for * - * additional informations. * - * * - ***************************************************************************/ - -//*************************************************************************// -// History of changes: -// -// 2004/04/04 - Pete -// - generic cleanup for the Peops release... register values by Kanodin & -// his team -// -//*************************************************************************// - -//########################################################################### - -#define PS2_C0_SPUaddr_Hi (0x000 + 0x1A8) -#define PS2_C0_SPUaddr_Lo (0x000 + 0x1AA) -#define PS2_C1_SPUaddr_Hi (0x400 + 0x1A8) -#define PS2_C1_SPUaddr_Lo (0x400 + 0x1AA) -#define PS2_C0_SPUdata (0x000 + 0x1AC) -#define PS2_C1_SPUdata (0x400 + 0x1AC) - -#define PS2_C0_SPUDMActrl (0x000 + 0x1AE) -#define PS2_C1_SPUDMActrl (0x400 + 0x1AE) - -#define PS2_C0_SPUstat (0x000 + 0x344) -#define PS2_C1_SPUstat (0x400 + 0x344) -#define PS2_C0_ReverbAddr_Hi (0x000 + 0x2E0) -#define PS2_C0_ReverbAddr_Lo (0x000 + 0x2E2) -#define PS2_C1_ReverbAddr_Hi (0x400 + 0x2E0) -#define PS2_C1_ReverbAddr_Lo (0x400 + 0x2E2) - -#define PS2_C0_ReverbAEnd_Hi (0x000 + 0x33C) -#define PS2_C0_ReverbAEnd_Lo (0x000 + 0x33E) -#define PS2_C1_ReverbAEnd_Hi (0x400 + 0x33C) -#define PS2_C1_ReverbAEnd_Lo (0x400 + 0x33E) - -#define PS2_C0_DryL1 (0x000 + 0x188) -#define PS2_C1_DryL1 (0x400 + 0x188) -#define PS2_C0_DryL2 (0x000 + 0x18A) -#define PS2_C1_DryL2 (0x400 + 0x18A) - -#define PS2_C0_DryR1 (0x000 + 0x190) -#define PS2_C1_DryR1 (0x400 + 0x190) -#define PS2_C0_DryR2 (0x000 + 0x192) -#define PS2_C1_DryR2 (0x400 + 0x192) - -#define PS2_C0_ATTR (0x000 + 0x19A) -#define PS2_C1_ATTR (0x400 + 0x19A) -#define PS2_C0_ADMAS (0x000 + 0x1B0) -#define PS2_C1_ADMAS (0x400 + 0x1B0) - -#define PS2_C0_SPUirqAddr_Hi (0x000 + 0x19C) -#define PS2_C0_SPUirqAddr_Lo (0x000 + 0x19D) -#define PS2_C1_SPUirqAddr_Hi (0x400 + 0x19C) -#define PS2_C1_SPUirqAddr_Lo (0x400 + 0x19D) -#define PS2_C0_SPUrvolL (0x000 + 0x764) -#define PS2_C0_SPUrvolR (0x000 + 0x766) -#define PS2_C1_SPUrvolL (0x028 + 0x764) -#define PS2_C1_SPUrvolR (0x028 + 0x766) -#define PS2_C0_SPUon1 (0x000 + 0x1A0) -#define PS2_C0_SPUon2 (0x000 + 0x1A2) -#define PS2_C1_SPUon1 (0x400 + 0x1A0) -#define PS2_C1_SPUon2 (0x400 + 0x1A2) -#define PS2_C0_SPUoff1 (0x000 + 0x1A4) -#define PS2_C0_SPUoff2 (0x000 + 0x1A6) -#define PS2_C1_SPUoff1 (0x400 + 0x1A4) -#define PS2_C1_SPUoff2 (0x400 + 0x1A6) -#define PS2_C0_FMod1 (0x000 + 0x180) -#define PS2_C0_FMod2 (0x000 + 0x182) -#define PS2_C1_FMod1 (0x400 + 0x180) -#define PS2_C1_FMod2 (0x400 + 0x182) -#define PS2_C0_Noise1 (0x000 + 0x184) -#define PS2_C0_Noise2 (0x000 + 0x186) -#define PS2_C1_Noise1 (0x400 + 0x184) -#define PS2_C1_Noise2 (0x400 + 0x186) - -#define PS2_C0_RVBon1_L (0x000 + 0x18C) -#define PS2_C0_RVBon2_L (0x000 + 0x18E) -#define PS2_C0_RVBon1_R (0x000 + 0x194) -#define PS2_C0_RVBon2_R (0x000 + 0x196) - -#define PS2_C1_RVBon1_L (0x400 + 0x18C) -#define PS2_C1_RVBon2_L (0x400 + 0x18E) -#define PS2_C1_RVBon1_R (0x400 + 0x194) -#define PS2_C1_RVBon2_R (0x400 + 0x196) -#define PS2_C0_Reverb (0x000 + 0x2E4) -#define PS2_C1_Reverb (0x400 + 0x2E4) -#define PS2_C0_ReverbX (0x000 + 0x774) -#define PS2_C1_ReverbX (0x028 + 0x774) -#define PS2_C0_SPUend1 (0x000 + 0x340) -#define PS2_C0_SPUend2 (0x000 + 0x342) -#define PS2_C1_SPUend1 (0x400 + 0x340) -#define PS2_C1_SPUend2 (0x400 + 0x342) - -#define H_SPUReverbAddr 0x0da2 - -#define H_SPUirqAddr 0x0da4 - -#define H_SPUaddr 0x0da6 - -#define H_SPUdata 0x0da8 - -#define H_SPUctrl 0x0daa - -#define H_SPUstat 0x0dae - -#define H_SPUmvolL 0x0d80 - -#define H_SPUmvolR 0x0d82 - -#define H_SPUrvolL 0x0d84 - -#define H_SPUrvolR 0x0d86 - -#define H_SPUon1 0x0d88 - -#define H_SPUon2 0x0d8a - -#define H_SPUoff1 0x0d8c - -#define H_SPUoff2 0x0d8e - -#define H_FMod1 0x0d90 - -#define H_FMod2 0x0d92 - -#define H_Noise1 0x0d94 - -#define H_Noise2 0x0d96 - -#define H_RVBon1 0x0d98 - -#define H_RVBon2 0x0d9a -#define H_SPUMute1 0x0d9c -#define H_SPUMute2 0x0d9e -#define H_CDLeft 0x0db0 -#define H_CDRight 0x0db2 -#define H_ExtLeft 0x0db4 -#define H_ExtRight 0x0db6 -#define H_Reverb 0x0dc0 - - -//########################################################################### - -/* - Included the info received in Regs.txt list by Neill Corlett - Kanodin - - Voice parameters: - SD_VP_VOLL, SD_VP_VOLR - Volume left/right per voice. Assuming identical to PS1. - SD_VP_PITCH - Pitch scaler 0000-3FFF. Assuming identical to PS1. - SD_VP_ADSR1, SD_VP_ADSR1 - Envelope data. Bitfields are documented as identical to PS1. - SD_VP_ENVX - Current envelope value. Assuming identical to PS1. - SD_VP_VOLXL, SD_VP_VOLXR - Current voice volume left/right. Does not exist on the PS1. - Guessing that this is handy for the increase/decrease modes. - - Voice addresses: - - SD_VA_SSA - Sample start address; assuming identical to PS1 - SD_VA_LSAX - Loop start address; assuming identical to PS1 - SD_VA_NAX - Seems to be documented as the current playing address. - Does not exist on PS1. - - Switches: - - SD_S_PMON - Pitch mod; assuming identical to PS1 - SD_S_NON - Noise; assuming identical to PS1 - SD_S_VMIXL, SD_S_VMIXR - Voice mix L/R. Guessing this is just a separate L/R version - of the "voice enable" bits on the PS1. - SD_S_VMIXEL, SD_S_VMIXER - Voice effect mix L/R. Guessing this is just a separate L/R - version of the "voice reverb enable" bits on the PS1. - SD_S_KON, SD_S_KOFF - Key on/off; assuming identical to PS1 - - - Addresses: - - SD_A_TSA - Transfer start address; assuming identical to PS1 - SD_A_ESA - Effect start address - this is probably analogous to the - PS1's reverb work area start address - SD_A_EEA - Effect end address - this would've been fixed to 0x7FFFF on - the PS1; settable in 128K increments on the PS2. - SD_A_IRQA - IRQ address; assuming identical to PS1 - - Volume parameters: - - SD_P_MVOLL, SD_P_MVOLR - Master volume L/R; assuming identical to PS1 - SD_P_EVOLL, SD_P_EVOLR - Effect volume L/R; assuming analogous to RVOL on the PS1 - SD_P_AVOLL, SD_P_AVOLR - External input volume L/R - This is probably where CORE0 connects to CORE1 - SD_P_BVOLL, SD_P_BVOLR - Sound data input volume - perhaps this is the volume of - the raw PCM auto-DMA input? analogous to CD input volume? - SD_P_MVOLXL, SD_P_MVOLXR - Current master volume L/R; seems self-explanatory - - SD_P_MMIX - Mixer / effect enable bits. - bit 11 = MSNDL = voice output dry L - 10 = MSNDR = voice output dry R - 9 = MSNDEL = voice output wet L - 8 = MSNDER = voice output wet R - 7 = MINL = sound data input dry L - 6 = MINR = sound data input dry R - 5 = MINEL = sound data input wet L - 4 = MINER = sound data input wet R - 3 = SINL = core external input dry L - 2 = SINR = core external input dry R - 1 = SINEL = core external input wet L - 0 = SINER = core external input wet R - -Core attributes (SD_C) - - bit 4..5 - DMA related - bit 6 - IRQ enable - bit 7 - effect enable (reverb enable) - bit 13..8 - noise clock - bit 14 - mute - - - if you READ the two DMA related bits, if either are set, the channel is - considered "busy" by sceSdVoiceTrans - - - -Reverb parameters: - - Same as PS1 reverb (I used the names from my reverb doc). - - -Other PS2 IOP notes - - There's two DMA controllers: - The original one at 1F801080-1F8010FF (channels 0-6) - A new one at 1F801500-1F80157F (channels 7-13) - - They appear to function the same way - 7 channels each. - - SPU CORE0's DMA channel is 4 as per usual - SPU CORE1's DMA channel is 7 - -DMA channel 10 is SIF - - Original INTR controller at 1F801000-1F80107F - - All interrupt handling seems to be done using the old INTR, but - with some new bits defined: - - - - Reading from 1F801078 masks interrupts and returns 1 if they weren't - masked before. Writing 1 to 1F801078 re-enables interrupts. - Writing 0 doesn't. Maybe it was like that on the original PS1 too. - -Six root counters: - - RTC# address sources size prescale interrupt# -0 0x1F801100 sysclock,pixel 16 bit 1 only 4 -1 0x1F801110 sysclock,hline 16 bit 1 only 5 -2 0x1F801120 sysclock 16 bit 1,8 6 -3 0x1F801480 sysclock,hline 32 bit 1 only 14 -4 0x1F801490 sysclock 32 bit 1,8,16,256 15 -5 0x1F8014A0 sysclock 32 bit 1,8,16,256 16 - -Count (0x0) and Compare (0x8) registers work as before, only with more bits -in the new counters. - -Mode (0x4) works like this when written: - - bits 0..2 gate - bit 3 reset on target - bit 4 target interrupt enable - bit 5 overflow interrupt enable - bit 6 master enable (?) - bit 7 ? - bit 8 clock select - bit 9 prescale (OLD) - bit 10..12 ? - bit 13..14 prescale (NEW) - bit 15 ? always set to 1 - -Gate: - TM_NO_GATE 000 - TM_GATE_ON_Count 001 - TM_GATE_ON_ClearStart 011 - TM_GATE_ON_Clear_OFF_Start 101 - TM_GATE_ON_Start 111 - - V-blank ----+ +----------------------------+ +------ - | | | | - | | | | - +----+ +----+ - TM_NO_GATE: - - 0================================>============ - - TM_GATE_ON_Count: - - <---->0==========================><---->0===== - - TM_GATE_ON_ClearStart: - - 0====>0================================>0===== - - TM_GATE_ON_Clear_OFF_Start: - - 0====><-------------------------->0====><----- - - TM_GATE_ON_Start: - - <---->0==========================>============ - - reset on target: if set, counter resets to 0 when Compare value is reached - - target interrupt enable: if set, interrupt when Compare value is reached - overflow interrupt enable: if set, interrupt when counter overflows - - master enable: if this bit is clear, the timer should do nothing. - - clock select: for counters 0, 1, and 3, setting this will select the alternate - counter (pixel or hline) - - prescale (OLD): for counter 2 only. set this to prescale (divide) by 8. - - prescale (NEW): for counters 4 and 5 only: - - 00 = prescale by 1 - 01 = prescale by 8 - 10 = prescale by 16 - 11 = prescale by 256 - -Writing 0x4 also clears the counter. (I think.) - -When 0x4 is read, it becomes Status: - - bit 0..10 ? - bit 11 compare value was reached - bit 12 count overflowed - bit 13..15 ? - -Reading probably clears these bits. - - - - 1F8014B0 (word) - timer-related but otherwise unknown - 1F8014C0 (word) - timer-related but otherwise unknown - - - don't currently know how the interrupts work for DMA ch7 yet - - 1F801060 (word) - address of some kind. - - 1F801450 (word) - - if bit 3 is SET, we're in PS1 mode. - if bit 3 is CLEAR, we're in PS2 IOP mode. - - 1F802070 (byte) - unknown. status byte of some kind? visible to EE? - - 1D000000-1D00007F (?) - SIF related - - 1D000020 (word) - read counter of some sort? - sceSifInit waits for bit 0x10000 of this to be set. - 1D000030 (word) - read counter of some sort? - 1D000040 (word) - read bits 0x20, 0x40 mean something - 1D000060 (word) - used to detect whether the SIF interface exists - read must be 0x1D000060, or the top 20 bits must be zero -*/ - -/* - -// DirectX Audio SPU2 Driver for PCSX2 -// audio.c by J.F. and Kanodin (hooper1@cox.net) -// -// Copyright 2003 J.F. and Kanodin, and distributed under the -// terms of the GNU General Public License, v2 or later. -// http://www.gnu.org/copyleft/gpl.html. - -Included these just in case you need them J.F. - Kanodin - -// Core Start Addresses -#define CORE0 0x1f900000 -#define CORE1 0x1f900400 - - - #define IOP_INT_VBLANK (1<<0) - #define IOP_INT_GM (1<<1) - #define IOP_INT_CDROM (1<<2) - #define IOP_INT_DMA (1<<3) - #define IOP_INT_RTC0 (1<<4) - #define IOP_INT_RTC1 (1<<5) - #define IOP_INT_RTC2 (1<<6) - #define IOP_INT_SIO0 (1<<7) - #define IOP_INT_SIO1 (1<<8) - #define IOP_INT_SPU (1<<9) - #define IOP_INT_PIO (1<<10) - #define IOP_INT_EVBLANK (1<<11) - #define IOP_INT_DVD (1<<12) - #define IOP_INT_PCMCIA (1<<13) - #define IOP_INT_RTC3 (1<<14) - #define IOP_INT_RTC4 (1<<15) - #define IOP_INT_RTC5 (1<<16) - #define IOP_INT_SIO2 (1<<17) - #define IOP_INT_HTR0 (1<<18) - #define IOP_INT_HTR1 (1<<19) - #define IOP_INT_HTR2 (1<<20) - #define IOP_INT_HTR3 (1<<21) - #define IOP_INT_USB (1<<22) - #define IOP_INT_EXTR (1<<23) - #define IOP_INT_FWRE (1<<24) - #define IOP_INT_FDMA (1<<25) - -// CORE0 => +0x000, CORE1 => +0x400 - -// individual voice parameter regs - -#define VP_VOLL(cr, vc) (0x400 * cr + 0x000 + (vc << 4)) // voice volume (left) -#define VP_VOLR(cr, vc) (0x400 * cr + 0x002 + (vc << 4)) // voice volume (right) -#define VP_PITCH(cr, vc) (0x400 * cr + 0x004 + (vc << 4)) // voice pitch -#define VP_ADSR1(cr, vc) (0x400 * cr + 0x006 + (vc << 4)) // voice envelope (AR, DR, SL) -#define VP_ADSR2(cr, vc) (0x400 * cr + 0x008 + (vc << 4)) // voice envelope (SR, RR) -#define VP_ENVX(cr, vc) (0x400 * cr + 0x00A + (vc << 4)) // voice envelope (current value) -#define VP_VOLXL(cr, vc) (0x400 * cr + 0x00C + (vc << 4)) // voice volume (current value left) -#define VP_VOLXR(cr, vc) (0x400 * cr + 0x00E + (vc << 4)) // voice volume (current value right) - -#define VA_SSA(cr, vc) (0x400 * cr + 0x1C0 + (vc * 12)) // voice waveform data start address -#define VA_LSAX(cr, vc) (0x400 * cr + 0x1C4 + (vc * 12)) // voice waveform data loop address -#define VA_NAX(cr, vc) (0x400 * cr + 0x1C8 + (vc * 12)) // voice waveform data next address - -// common settings - -#define S_PMON(cr) (0x400 * cr + 0x180) // pitch modulation on -#define S_NON(cr) (0x400 * cr + 0x184) // noise generator on -#define S_VMIXL(cr) (0x400 * cr + 0x188) // voice output mixing (dry left) -#define S_VMIXEL(cr) (0x400 * cr + 0x18C) // voice output mixing (wet left) -#define S_VMIXR(cr) (0x400 * cr + 0x190) // voice output mixing (dry right) -#define S_VMIXER(cr) (0x400 * cr + 0x194) // voice output mixing (wet right) -#define P_MMIX(cr) (0x400 * cr + 0x198) // output type after voice mixing (See paragraph below) -#define P_ATTR(cr) (0x400 * cr + 0x19A) // core attributes (See paragraph below) -#define A_IRQA(cr) (0x400 * cr + 0x19C) // IRQ address -#define S_KON(cr) (0x400 * cr + 0x1A0) // key on (start voice sound generation) -#define S_KOFF(cr) (0x400 * cr + 0x1A4) // key off (end voice sound generation) -#define A_TSA(cr) (0x400 * cr + 0x1A8) // DMA transfer start address -#define P_DATA(cr) (0x400 * cr + 0x1AC) // DMA data register -#define P_CTRL(cr) (0x400 * cr + 0x1AE) // DMA control register -#define P_ADMAS(cr) (0x400 * cr + 0x1B0) // AutoDMA status - -#define A_ESA(cr) (0x400 * cr + 0x2E0) // effects work area start address - -#define FB_SRC_A(cr) (0x400 * cr + 0x2E4) -#define FB_SRC_B(cr) (0x400 * cr + 0x2E8) -#define IIR_DEST_A0(cr) (0x400 * cr + 0x2EC) -#define IIR_DEST_A1(cr) (0x400 * cr + 0x2F0) -#define ACC_SRC_A0(cr) (0x400 * cr + 0x2F4) -#define ACC_SRC_A1(cr) (0x400 * cr + 0x2F8) -#define ACC_SRC_B0(cr) (0x400 * cr + 0x2FC) - -#define ACC_SRC_B1(cr) (0x400 * cr + 0x300) -#define IIR_SRC_A0(cr) (0x400 * cr + 0x304) -#define IIR_SRC_A1(cr) (0x400 * cr + 0x308) -#define IIR_DEST_B0(cr) (0x400 * cr + 0x30C) -#define IIR_DEST_B1(cr) (0x400 * cr + 0x310) -#define ACC_SRC_C0(cr) (0x400 * cr + 0x314) -#define ACC_SRC_C1(cr) (0x400 * cr + 0x318) - -#define ACC_SRC_D0(cr) (0x400 * cr + 0x31C) -#define ACC_SRC_D1(cr) (0x400 * cr + 0x320) -#define IIR_SRC_B1(cr) (0x400 * cr + 0x324) -#define IIR_SRC_B0(cr) (0x400 * cr + 0x328) -#define MIX_DEST_A0(cr) (0x400 * cr + 0x32C) -#define MIX_DEST_A1(cr) (0x400 * cr + 0x330) -#define MIX_DEST_B0(cr) (0x400 * cr + 0x334) -#define MIX_DEST_B1(cr) (0x400 * cr + 0x338) - -#define A_EEA(cr) (0x400 * cr + 0x33C) // effects work area end address - -#define P_ENDX(cr) (0x400 * cr + 0x340) // voice loop end status -#define P_STAT(cr) (0x400 * cr + 0x344) // DMA status register -#define P_ENDS(cr) (0x400 * cr + 0x346) // ? - -// CORE0 => +0x400, CORE1 => +0x428 - -#define P_MVOLL(cr) (0x28 * cr + 0x760) // master volume (left) -#define P_MVOLR(cr) (0x28 * cr + 0x762) // master volume (right) -#define P_EVOLL(cr) (0x28 * cr + 0x764) // effect return volume (left) -#define P_EVOLR(cr) (0x28 * cr + 0x766) // effect return volume (right) -#define P_AVOLL(cr) (0x28 * cr + 0x768) // core external input volume (left) -#define P_AVOLR(cr) (0x28 * cr + 0x76A) // core external input volume (right) -#define P_BVOLL(cr) (0x28 * cr + 0x76C) // sound data input volume (left) -#define P_BVOLR(cr) (0x28 * cr + 0x76E) // sound data input volume (right) -#define P_MVOLXL(cr) (0x28 * cr + 0x770) // current master volume (left) -#define P_MVOLXR(cr) (0x28 * cr + 0x772) // current master volume (right) - -#define IIR_ALPHA(cr) (0x28 * cr + 0x774) -#define ACC_COEF_A(cr) (0x28 * cr + 0x776) -#define ACC_COEF_B(cr) (0x28 * cr + 0x778) -#define ACC_COEF_C(cr) (0x28 * cr + 0x77A) -#define ACC_COEF_D(cr) (0x28 * cr + 0x77C) -#define IIR_COEF(cr) (0x28 * cr + 0x77E) -#define FB_ALPHA(cr) (0x28 * cr + 0x780) -#define FB_X(cr) (0x28 * cr + 0x782) -#define IN_COEF_L(cr) (0x28 * cr + 0x784) -#define IN_COEF_R(cr) (0x28 * cr + 0x786) - -// CORE1 only => +0x400 - -#define SPDIF_OUT 0x7C0 // SPDIF Out: OFF/'PCM'/Bitstream/Bypass -#define SPDIF_MODE 0x7C6 -#define SPDIF_MEDIA 0x7C8 // SPDIF Media: 'CD'/DVD -#define SPDIF_COPY 0x7CA // SPDIF Copy Protection - -// PS1 SPU CORE - -// individual voice settings - -#define SPU_VP_PITCH(vc) (0xC04 + (vc << 4)) // voice pitch -#define SPU_VA_SSA(vc) (0xC06 + (vc << 4)) // voice waveform data start address -#define SPU_VP_ADSR(vc) (0xC08 + (vc << 4)) // voice envelope -#define SPU_VA_SSA(vc) (0xC0E + (vc << 4)) // voice waveform data loop address - -// common settings - -#define SPU_P_MVOLL 0xD80 // master volume (left) -#define SPU_P_MVOLR 0xD82 // master volume (right) -#define SPU_P_RVOLL 0xD84 // effect return volume (left) -#define SPU_P_RVOLR 0xD86 // effect return volume (right) -#define SPU_S_KON1 0xD88 // key on -#define SPU_S_KON2 0xD8A // -#define SPU_S_KOFF1 0xD8C // key off -#define SPU_S_KOFF2 0xD8E // -#define SPU_S_PMON1 0xD90 // pitch modulation on -#define SPU_S_PMON2 0xD92 // -#define SPU_S_NON1 0xD94 // noise generator on -#define SPU_S_NON2 0xD96 // -#define SPU_S_RVBON1 0xD98 // effects on -#define SPU_S_RVBON2 0xD9A // -#define SPU_S_MUTE1 0xD9C // voice mute -#define SPU_S_MUTE2 0xD9E // - -#define SPU_A_ESA 0xDA2 // effects work area start -#define SPU_A_IRQA 0xDA4 // IRQ address -#define SPU_A_TSA 0xDA6 // DMA transfer start address -#define SPU_P_DATA 0xDA8 // DMA data register -#define SPU_P_CTRL 0xDAA // DMA control register -#define SPU_P_STAT 0xDAE // DMA status register - -#define SPU_P_CDL 0xDB0 // sound data input volume (left) -#define SPU_P_CDR 0xDB2 // sound data input volume (right) -#define SPU_P_EXTL 0xDB4 // external input volume (left) -#define SPU_P_EXTR 0xDB6 // external input volume (right) - -#define SPU_P_REVERB 0xDC0 // effects control - - -// Individual voice parameter regs CORE 0 -// Only - - -#define VP_VOLL(cr, vc) (0x400 * cr + 0x000 + (vc << 4)) // voice volume (left) -#define VP_VOLR(cr, vc) (0x400 * cr + 0x002 + (vc << 4)) // voice volume (right) -#define VP_PITCH(cr, vc) (0x400 * cr + 0x004 + (vc << 4)) // voice pitch -#define VP_ADSR1(cr, vc) (0x400 * cr + 0x006 + (vc << 4)) // voice envelope (AR, DR, SL) -#define VP_ADSR2(cr, vc) (0x400 * cr + 0x008 + (vc << 4)) // voice envelope (SR, RR) -#define VP_ENVX(cr, vc) (0x400 * cr + 0x00A + (vc << 4)) // voice envelope (current value) -#define VP_VOLXL(cr, vc) (0x400 * cr + 0x00C + (vc << 4)) // voice volume (current value left) -#define VP_VOLXR(cr, vc) (0x400 * cr + 0x00E + (vc << 4)) // voice volume (current value right) - -#define VA_SSA(cr, vc) (0x400 * cr + 0x1C0 + (vc * 12)) // voice waveform data start address -#define VA_LSAX(cr, vc) (0x400 * cr + 0x1C4 + (vc * 12)) // voice waveform data loop address -#define VA_NAX(cr, vc) (0x400 * cr + 0x1C8 + (vc * 12)) // voice waveform data next address - - -// CORE 0 Common Settings - - -#define S_PMON(cr) (0x400 * cr + 0x180) // pitch modulation on -#define S_NON(cr) (0x400 * cr + 0x184) // noise generator on -#define S_VMIXL(cr) (0x400 * cr + 0x188) // voice output mixing (dry left) -#define S_VMIXEL(cr) (0x400 * cr + 0x18C) // voice output mixing (wet left) -#define S_VMIXR(cr) (0x400 * cr + 0x190) // voice output mixing (dry right) -#define S_VMIXER(cr) (0x400 * cr + 0x194) // voice output mixing (wet right) -#define P_MMIX(cr) (0x400 * cr + 0x198) // output type after voice mixing (See paragraph below) -#define P_ATTR(cr) (0x400 * cr + 0x19A) // core attributes (See paragraph below) -#define A_IRQA(cr) (0x400 * cr + 0x19C) // IRQ address -#define S_KON(cr) (0x400 * cr + 0x1A0) // key on (start voice sound generation) -#define S_KOFF(cr) (0x400 * cr + 0x1A4) // key off (end voice sound generation) -#define A_TSA(cr) (0x400 * cr + 0x1A8) // DMA transfer start address -#define P_DATA(cr) (0x400 * cr + 0x1AC) // DMA data register -#define P_CTRL(cr) (0x400 * cr + 0x1AE) // DMA control register -#define P_ADMAS(cr) (0x400 * cr + 0x1B0) // AutoDMA status - -#define A_ESA(cr) (0x400 * cr + 0x2E0) // effects work area start address - - -// Core 0 Reverb Addresses - - -#define FB_SRC_A(cr) (0x400 * cr + 0x2E4) -#define FB_SRC_B(cr) (0x400 * cr + 0x2E8) -#define IIR_DEST_A0(cr) (0x400 * cr + 0x2EC) -#define IIR_DEST_A1(cr) (0x400 * cr + 0x2F0) -#define ACC_SRC_A0(cr) (0x400 * cr + 0x2F4) -#define ACC_SRC_A1(cr) (0x400 * cr + 0x2F8) -#define ACC_SRC_B0(cr) (0x400 * cr + 0x2FC) - -#define ACC_SRC_B1(cr) (0x400 * cr + 0x300) -#define IIR_SRC_A0(cr) (0x400 * cr + 0x304) -#define IIR_SRC_A1(cr) (0x400 * cr + 0x308) -#define IIR_DEST_B0(cr) (0x400 * cr + 0x30C) -#define IIR_DEST_B1(cr) (0x400 * cr + 0x310) -#define ACC_SRC_C0(cr) (0x400 * cr + 0x314) -#define ACC_SRC_C1(cr) (0x400 * cr + 0x318) - -#define ACC_SRC_D0(cr) (0x400 * cr + 0x31C) -#define ACC_SRC_D1(cr) (0x400 * cr + 0x320) -#define IIR_SRC_B1(cr) (0x400 * cr + 0x324) -#define IIR_SRC_B0(cr) (0x400 * cr + 0x328) -#define MIX_DEST_A0(cr) (0x400 * cr + 0x32C) -#define MIX_DEST_A1(cr) (0x400 * cr + 0x330) -#define MIX_DEST_B0(cr) (0x400 * cr + 0x334) -#define MIX_DEST_B1(cr) (0x400 * cr + 0x338) - -#define A_EEA(cr) (0x400 * cr + 0x33C) // effects work area end address - -#define P_ENDX(cr) (0x400 * cr + 0x340) // voice loop end status -#define P_STAT(cr) (0x400 * cr + 0x344) // DMA status register -#define P_ENDS(cr) (0x400 * cr + 0x346) // ? - - -// CORE 0 Specific - - -#define P_MVOLL(cr) (0x28 * cr + 0x760) // master volume (left) -#define P_MVOLR(cr) (0x28 * cr + 0x762) // master volume (right) -#define P_EVOLL(cr) (0x28 * cr + 0x764) // effect return volume (left) -#define P_EVOLR(cr) (0x28 * cr + 0x766) // effect return volume (right) -#define P_AVOLL(cr) (0x28 * cr + 0x768) // core external input volume (left) -#define P_AVOLR(cr) (0x28 * cr + 0x76A) // core external input volume (right) -#define P_BVOLL(cr) (0x28 * cr + 0x76C) // sound data input volume (left) -#define P_BVOLR(cr) (0x28 * cr + 0x76E) // sound data input volume (right) -#define P_MVOLXL(cr) (0x28 * cr + 0x770) // current master volume (left) -#define P_MVOLXR(cr) (0x28 * cr + 0x772) // current master volume (right) - - -// More CORE 0 Reverb - - -#define IIR_ALPHA(cr) (0x28 * cr + 0x774) -#define ACC_COEF_A(cr) (0x28 * cr + 0x776) -#define ACC_COEF_B(cr) (0x28 * cr + 0x778) -#define ACC_COEF_C(cr) (0x28 * cr + 0x77A) -#define ACC_COEF_D(cr) (0x28 * cr + 0x77C) -#define IIR_COEF(cr) (0x28 * cr + 0x77E) -#define FB_ALPHA(cr) (0x28 * cr + 0x780) -#define FB_X(cr) (0x28 * cr + 0x782) -#define IN_COEF_L(cr) (0x28 * cr + 0x784) -#define IN_COEF_R(cr) (0x28 * cr + 0x786) - - -// CORE 1 only - -#define SPDIF_OUT 0x7C0 // SPDIF Out: OFF/'PCM'/Bitstream/Bypass -#define SPDIF_MODE 0x7C6 -#define SPDIF_MEDIA 0x7C8 // SPDIF Media: 'CD'/DVD -#define SPDIF_COPY 0x7CA // SPDIF Copy Protection -*/ - -/* PS1 SPU CORE - -*** The below really isn't needed, only if you *** -*** want to add SPU support to the plugin *** -*** which I see no need to add at this time. *** -*** individual voice settings *** - -#define SPU_VP_PITCH(vc) (0xC04 + (vc << 4)) // voice pitch -#define SPU_VA_SSA(vc) (0xC06 + (vc << 4)) // voice waveform data start address -#define SPU_VP_ADSR(vc) (0xC08 + (vc << 4)) // voice envelope -#define SPU_VA_SSA(vc) (0xC0E + (vc << 4)) // voice waveform data loop address - -// common settings - -#define SPU_P_MVOLL 0xD80 // master volume (left) -#define SPU_P_MVOLR 0xD82 // master volume (right) -#define SPU_P_RVOLL 0xD84 // effect return volume (left) -#define SPU_P_RVOLR 0xD86 // effect return volume (right) -#define SPU_S_KON1 0xD88 // key on -#define SPU_S_KON2 0xD8A // -#define SPU_S_KOFF1 0xD8C // key off -#define SPU_S_KOFF2 0xD8E // -#define SPU_S_PMON1 0xD90 // pitch modulation on -#define SPU_S_PMON2 0xD92 // -#define SPU_S_NON1 0xD94 // noise generator on -#define SPU_S_NON2 0xD96 // -#define SPU_S_RVBON1 0xD98 // effects on -#define SPU_S_RVBON2 0xD9A // -#define SPU_S_MUTE1 0xD9C // voice mute -#define SPU_S_MUTE2 0xD9E // - -#define SPU_A_ESA 0xDA2 // effects work area start -#define SPU_A_IRQA 0xDA4 // IRQ address -#define SPU_A_TSA 0xDA6 // DMA transfer start address -#define SPU_P_DATA 0xDA8 // DMA data register -#define SPU_P_CTRL 0xDAA // DMA control register -#define SPU_P_STAT 0xDAE // DMA status register - -#define SPU_P_CDL 0xDB0 // sound data input volume (left) -#define SPU_P_CDR 0xDB2 // sound data input volume (right) -#define SPU_P_EXTL 0xDB4 // external input volume (left) -#define SPU_P_EXTR 0xDB6 // external input volume (right) - -#define SPU_P_REVERB 0xDC0 // effects control -*/ - -/* -#define H_SPUReverbAddr 0x0da2 -#define H_SPUirqAddr 0x0da4 -#define H_SPUaddr 0x0da6 -#define H_SPUdata 0x0da8 -#define H_SPUctrl 0x0daa -#define H_SPUstat 0x0dae -#define H_SPUmvolL 0x0d80 -#define H_SPUmvolR 0x0d82 -#define H_SPUrvolL 0x0d84 -#define H_SPUrvolR 0x0d86 -#define H_SPUon1 0x0d88 -#define H_SPUon2 0x0d8a -#define H_SPUoff1 0x0d8c -#define H_SPUoff2 0x0d8e -#define H_FMod1 0x0d90 -#define H_FMod2 0x0d92 -#define H_Noise1 0x0d94 -#define H_Noise2 0x0d96 -#define H_RVBon1 0x0d98 -#define H_RVBon2 0x0d9a -#define H_SPUMute1 0x0d9c -#define H_SPUMute2 0x0d9e -#define H_CDLeft 0x0db0 -#define H_CDRight 0x0db2 -#define H_ExtLeft 0x0db4 -#define H_ExtRight 0x0db6 -#define H_Reverb 0x0dc0 -#define H_SPUPitch0 0x0c04 -#define H_SPUPitch1 0x0c14 -#define H_SPUPitch2 0x0c24 -#define H_SPUPitch3 0x0c34 -#define H_SPUPitch4 0x0c44 -#define H_SPUPitch5 0x0c54 -#define H_SPUPitch6 0x0c64 -#define H_SPUPitch7 0x0c74 -#define H_SPUPitch8 0x0c84 -#define H_SPUPitch9 0x0c94 -#define H_SPUPitch10 0x0ca4 -#define H_SPUPitch11 0x0cb4 -#define H_SPUPitch12 0x0cc4 -#define H_SPUPitch13 0x0cd4 -#define H_SPUPitch14 0x0ce4 -#define H_SPUPitch15 0x0cf4 -#define H_SPUPitch16 0x0d04 -#define H_SPUPitch17 0x0d14 -#define H_SPUPitch18 0x0d24 -#define H_SPUPitch19 0x0d34 -#define H_SPUPitch20 0x0d44 -#define H_SPUPitch21 0x0d54 -#define H_SPUPitch22 0x0d64 -#define H_SPUPitch23 0x0d74 - -#define H_SPUStartAdr0 0x0c06 -#define H_SPUStartAdr1 0x0c16 -#define H_SPUStartAdr2 0x0c26 -#define H_SPUStartAdr3 0x0c36 -#define H_SPUStartAdr4 0x0c46 -#define H_SPUStartAdr5 0x0c56 -#define H_SPUStartAdr6 0x0c66 -#define H_SPUStartAdr7 0x0c76 -#define H_SPUStartAdr8 0x0c86 -#define H_SPUStartAdr9 0x0c96 -#define H_SPUStartAdr10 0x0ca6 -#define H_SPUStartAdr11 0x0cb6 -#define H_SPUStartAdr12 0x0cc6 -#define H_SPUStartAdr13 0x0cd6 -#define H_SPUStartAdr14 0x0ce6 -#define H_SPUStartAdr15 0x0cf6 -#define H_SPUStartAdr16 0x0d06 -#define H_SPUStartAdr17 0x0d16 -#define H_SPUStartAdr18 0x0d26 -#define H_SPUStartAdr19 0x0d36 -#define H_SPUStartAdr20 0x0d46 -#define H_SPUStartAdr21 0x0d56 -#define H_SPUStartAdr22 0x0d66 -#define H_SPUStartAdr23 0x0d76 - -#define H_SPULoopAdr0 0x0c0e -#define H_SPULoopAdr1 0x0c1e -#define H_SPULoopAdr2 0x0c2e -#define H_SPULoopAdr3 0x0c3e -#define H_SPULoopAdr4 0x0c4e -#define H_SPULoopAdr5 0x0c5e -#define H_SPULoopAdr6 0x0c6e -#define H_SPULoopAdr7 0x0c7e -#define H_SPULoopAdr8 0x0c8e -#define H_SPULoopAdr9 0x0c9e -#define H_SPULoopAdr10 0x0cae -#define H_SPULoopAdr11 0x0cbe -#define H_SPULoopAdr12 0x0cce -#define H_SPULoopAdr13 0x0cde -#define H_SPULoopAdr14 0x0cee -#define H_SPULoopAdr15 0x0cfe -#define H_SPULoopAdr16 0x0d0e -#define H_SPULoopAdr17 0x0d1e -#define H_SPULoopAdr18 0x0d2e -#define H_SPULoopAdr19 0x0d3e -#define H_SPULoopAdr20 0x0d4e -#define H_SPULoopAdr21 0x0d5e -#define H_SPULoopAdr22 0x0d6e -#define H_SPULoopAdr23 0x0d7e - -#define H_SPU_ADSRLevel0 0x0c08 -#define H_SPU_ADSRLevel1 0x0c18 -#define H_SPU_ADSRLevel2 0x0c28 -#define H_SPU_ADSRLevel3 0x0c38 -#define H_SPU_ADSRLevel4 0x0c48 -#define H_SPU_ADSRLevel5 0x0c58 -#define H_SPU_ADSRLevel6 0x0c68 -#define H_SPU_ADSRLevel7 0x0c78 -#define H_SPU_ADSRLevel8 0x0c88 -#define H_SPU_ADSRLevel9 0x0c98 -#define H_SPU_ADSRLevel10 0x0ca8 -#define H_SPU_ADSRLevel11 0x0cb8 -#define H_SPU_ADSRLevel12 0x0cc8 -#define H_SPU_ADSRLevel13 0x0cd8 -#define H_SPU_ADSRLevel14 0x0ce8 -#define H_SPU_ADSRLevel15 0x0cf8 -#define H_SPU_ADSRLevel16 0x0d08 -#define H_SPU_ADSRLevel17 0x0d18 -#define H_SPU_ADSRLevel18 0x0d28 -#define H_SPU_ADSRLevel19 0x0d38 -#define H_SPU_ADSRLevel20 0x0d48 -#define H_SPU_ADSRLevel21 0x0d58 -#define H_SPU_ADSRLevel22 0x0d68 -#define H_SPU_ADSRLevel23 0x0d78 -*/ diff --git a/Frameworks/AudioOverload/aosdk/eng_psf/peops2/regs.h b/Frameworks/AudioOverload/aosdk/eng_psf/peops2/regs.h deleted file mode 100644 index 2cacafe1a..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_psf/peops2/regs.h +++ /dev/null @@ -1,43 +0,0 @@ -/*************************************************************************** - regs.h - description - ------------------- - begin : Wed May 15 2002 - copyright : (C) 2002 by Pete Bernert - email : BlackDove@addcom.de - ***************************************************************************/ - -/*************************************************************************** - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. See also the license.txt file for * - * additional informations. * - * * - ***************************************************************************/ - -//*************************************************************************// -// History of changes: -// -// 2004/04/04 - Pete -// - changed plugin to emulate PS2 spu -// -// 2002/05/15 - Pete -// - generic cleanup for the Peops release -// -//*************************************************************************// - - -void SoundOn(int start,int end,unsigned short val); -void SoundOff(int start,int end,unsigned short val); -void VolumeOn(int start,int end,unsigned short val,int iRight); -void FModOn(int start,int end,unsigned short val); -void NoiseOn(int start,int end,unsigned short val); -void SetVolumeL(unsigned char ch,short vol); -void SetVolumeR(unsigned char ch,short vol); -void SetPitch(int ch,unsigned short val); -void ReverbOn(int start,int end,unsigned short val,int iRight); -void SetReverbAddr(int core); - -EXPORT_GCC void CALLBACK SPU2write(unsigned long reg, unsigned short val); - diff --git a/Frameworks/AudioOverload/aosdk/eng_psf/peops2/reverb.c b/Frameworks/AudioOverload/aosdk/eng_psf/peops2/reverb.c deleted file mode 100644 index 55d0a35f9..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_psf/peops2/reverb.c +++ /dev/null @@ -1,420 +0,0 @@ -/*************************************************************************** - reverb.c - description - ------------------- - begin : Wed May 15 2002 - copyright : (C) 2002 by Pete Bernert - email : BlackDove@addcom.de - ***************************************************************************/ - -/*************************************************************************** - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. See also the license.txt file for * - * additional informations. * - * * - ***************************************************************************/ - -//*************************************************************************// -// History of changes: -// -// 2004/04/04 - Pete -// - changed to SPU2 functionality -// -// 2003/01/19 - Pete -// - added Neill's reverb (see at the end of file) -// -// 2002/12/26 - Pete -// - adjusted reverb handling -// -// 2002/08/14 - Pete -// - added extra reverb -// -// 2002/05/15 - Pete -// - generic cleanup for the Peops release -// -//*************************************************************************// - -#include "stdafx.h" - -#define _IN_REVERB - -// will be included from spu.c -#ifdef _IN_SPU - -//////////////////////////////////////////////////////////////////////// -// globals -//////////////////////////////////////////////////////////////////////// - -// REVERB info and timing vars... - -int * sRVBPlay[2]; -int * sRVBEnd[2]; -int * sRVBStart[2]; - -//////////////////////////////////////////////////////////////////////// -// START REVERB -//////////////////////////////////////////////////////////////////////// - -static INLINE void StartREVERB(int ch) -{ - int core=ch/24; - - if((s_chan[ch].bReverbL || s_chan[ch].bReverbR) && (spuCtrl2[core]&0x80)) // reverb possible? - { - if(iUseReverb==1) s_chan[ch].bRVBActive=1; - } - else s_chan[ch].bRVBActive=0; // else -> no reverb -} - -//////////////////////////////////////////////////////////////////////// -// HELPER FOR NEILL'S REVERB: re-inits our reverb mixing buf -//////////////////////////////////////////////////////////////////////// - -static INLINE void InitREVERB(void) -{ - if(iUseReverb==1) - { - memset(sRVBStart[0],0,NSSIZE*2*4); - memset(sRVBStart[1],0,NSSIZE*2*4); - } -} - -//////////////////////////////////////////////////////////////////////// -// STORE REVERB -//////////////////////////////////////////////////////////////////////// - -static INLINE void StoreREVERB(int ch,int ns) -{ - int core=ch/24; - - if(iUseReverb==0) return; - else - if(iUseReverb==1) // -------------------------------- // Neil's reverb - { - const int iRxl=(s_chan[ch].sval*s_chan[ch].iLeftVolume*s_chan[ch].bReverbL)/0x4000; - const int iRxr=(s_chan[ch].sval*s_chan[ch].iRightVolume*s_chan[ch].bReverbR)/0x4000; - - ns<<=1; - - *(sRVBStart[core]+ns) +=iRxl; // -> we mix all active reverb channels into an extra buffer - *(sRVBStart[core]+ns+1)+=iRxr; - } -} - -//////////////////////////////////////////////////////////////////////// - -static INLINE int g_buffer(int iOff,int core) // get_buffer content helper: takes care about wraps -{ - short * p=(short *)spuMem; - iOff=(iOff)+rvb[core].CurrAddr; - while(iOff>rvb[core].EndAddr) iOff=rvb[core].StartAddr+(iOff-(rvb[core].EndAddr+1)); - while(iOffrvb[core].EndAddr) iOff=rvb[core].StartAddr+(iOff-(rvb[core].EndAddr+1)); - while(iOff32767L) iVal=32767L; - *(p+iOff)=(short)iVal; -} - -//////////////////////////////////////////////////////////////////////// - -static INLINE void s_buffer1(int iOff,int iVal,int core) // set_buffer (+1 sample) content helper: takes care about wraps and clipping -{ - short * p=(short *)spuMem; - iOff=(iOff)+rvb[core].CurrAddr+1; - while(iOff>rvb[core].EndAddr) iOff=rvb[core].StartAddr+(iOff-(rvb[core].EndAddr+1)); - while(iOff32767L) iVal=32767L; - *(p+iOff)=(short)iVal; -} - -//////////////////////////////////////////////////////////////////////// - -static INLINE int MixREVERBLeft(int ns,int core) -{ - if(iUseReverb==1) - { - if(!rvb[core].StartAddr || !rvb[core].EndAddr || - rvb[core].StartAddr>=rvb[core].EndAddr) // reverb is off - { - rvb[core].iLastRVBLeft=rvb[core].iLastRVBRight=rvb[core].iRVBLeft=rvb[core].iRVBRight=0; - return 0; - } - - rvb[core].iCnt++; - - if(rvb[core].iCnt&1) // we work on every second left value: downsample to 22 khz - { - if((spuCtrl2[core]&0x80)) // -> reverb on? oki - { - int ACC0,ACC1,FB_A0,FB_A1,FB_B0,FB_B1; - - const int INPUT_SAMPLE_L=*(sRVBStart[core]+(ns<<1)); - const int INPUT_SAMPLE_R=*(sRVBStart[core]+(ns<<1)+1); - - const int IIR_INPUT_A0 = (g_buffer(rvb[core].IIR_SRC_A0,core) * rvb[core].IIR_COEF)/32768L + (INPUT_SAMPLE_L * rvb[core].IN_COEF_L)/32768L; - const int IIR_INPUT_A1 = (g_buffer(rvb[core].IIR_SRC_A1,core) * rvb[core].IIR_COEF)/32768L + (INPUT_SAMPLE_R * rvb[core].IN_COEF_R)/32768L; - const int IIR_INPUT_B0 = (g_buffer(rvb[core].IIR_SRC_B0,core) * rvb[core].IIR_COEF)/32768L + (INPUT_SAMPLE_L * rvb[core].IN_COEF_L)/32768L; - const int IIR_INPUT_B1 = (g_buffer(rvb[core].IIR_SRC_B1,core) * rvb[core].IIR_COEF)/32768L + (INPUT_SAMPLE_R * rvb[core].IN_COEF_R)/32768L; - - const int IIR_A0 = (IIR_INPUT_A0 * rvb[core].IIR_ALPHA)/32768L + (g_buffer(rvb[core].IIR_DEST_A0,core) * (32768L - rvb[core].IIR_ALPHA))/32768L; - const int IIR_A1 = (IIR_INPUT_A1 * rvb[core].IIR_ALPHA)/32768L + (g_buffer(rvb[core].IIR_DEST_A1,core) * (32768L - rvb[core].IIR_ALPHA))/32768L; - const int IIR_B0 = (IIR_INPUT_B0 * rvb[core].IIR_ALPHA)/32768L + (g_buffer(rvb[core].IIR_DEST_B0,core) * (32768L - rvb[core].IIR_ALPHA))/32768L; - const int IIR_B1 = (IIR_INPUT_B1 * rvb[core].IIR_ALPHA)/32768L + (g_buffer(rvb[core].IIR_DEST_B1,core) * (32768L - rvb[core].IIR_ALPHA))/32768L; - - s_buffer1(rvb[core].IIR_DEST_A0, IIR_A0,core); - s_buffer1(rvb[core].IIR_DEST_A1, IIR_A1,core); - s_buffer1(rvb[core].IIR_DEST_B0, IIR_B0,core); - s_buffer1(rvb[core].IIR_DEST_B1, IIR_B1,core); - - ACC0 = (g_buffer(rvb[core].ACC_SRC_A0,core) * rvb[core].ACC_COEF_A)/32768L + - (g_buffer(rvb[core].ACC_SRC_B0,core) * rvb[core].ACC_COEF_B)/32768L + - (g_buffer(rvb[core].ACC_SRC_C0,core) * rvb[core].ACC_COEF_C)/32768L + - (g_buffer(rvb[core].ACC_SRC_D0,core) * rvb[core].ACC_COEF_D)/32768L; - ACC1 = (g_buffer(rvb[core].ACC_SRC_A1,core) * rvb[core].ACC_COEF_A)/32768L + - (g_buffer(rvb[core].ACC_SRC_B1,core) * rvb[core].ACC_COEF_B)/32768L + - (g_buffer(rvb[core].ACC_SRC_C1,core) * rvb[core].ACC_COEF_C)/32768L + - (g_buffer(rvb[core].ACC_SRC_D1,core) * rvb[core].ACC_COEF_D)/32768L; - - FB_A0 = g_buffer(rvb[core].MIX_DEST_A0 - rvb[core].FB_SRC_A,core); - FB_A1 = g_buffer(rvb[core].MIX_DEST_A1 - rvb[core].FB_SRC_A,core); - FB_B0 = g_buffer(rvb[core].MIX_DEST_B0 - rvb[core].FB_SRC_B,core); - FB_B1 = g_buffer(rvb[core].MIX_DEST_B1 - rvb[core].FB_SRC_B,core); - - s_buffer(rvb[core].MIX_DEST_A0, ACC0 - (FB_A0 * rvb[core].FB_ALPHA)/32768L,core); - s_buffer(rvb[core].MIX_DEST_A1, ACC1 - (FB_A1 * rvb[core].FB_ALPHA)/32768L,core); - - s_buffer(rvb[core].MIX_DEST_B0, (rvb[core].FB_ALPHA * ACC0)/32768L - (FB_A0 * (int)(rvb[core].FB_ALPHA^0xFFFF8000))/32768L - (FB_B0 * rvb[core].FB_X)/32768L,core); - s_buffer(rvb[core].MIX_DEST_B1, (rvb[core].FB_ALPHA * ACC1)/32768L - (FB_A1 * (int)(rvb[core].FB_ALPHA^0xFFFF8000))/32768L - (FB_B1 * rvb[core].FB_X)/32768L,core); - - rvb[core].iLastRVBLeft = rvb[core].iRVBLeft; - rvb[core].iLastRVBRight = rvb[core].iRVBRight; - - rvb[core].iRVBLeft = (g_buffer(rvb[core].MIX_DEST_A0,core)+g_buffer(rvb[core].MIX_DEST_B0,core))/3; - rvb[core].iRVBRight = (g_buffer(rvb[core].MIX_DEST_A1,core)+g_buffer(rvb[core].MIX_DEST_B1,core))/3; - - rvb[core].iRVBLeft = (rvb[core].iRVBLeft * rvb[core].VolLeft) / 0x4000; - rvb[core].iRVBRight = (rvb[core].iRVBRight * rvb[core].VolRight) / 0x4000; - - rvb[core].CurrAddr++; - if(rvb[core].CurrAddr>rvb[core].EndAddr) rvb[core].CurrAddr=rvb[core].StartAddr; - - return rvb[core].iLastRVBLeft+(rvb[core].iRVBLeft-rvb[core].iLastRVBLeft)/2; - } - else // -> reverb off - { - rvb[core].iLastRVBLeft=rvb[core].iLastRVBRight=rvb[core].iRVBLeft=rvb[core].iRVBRight=0; - } - - rvb[core].CurrAddr++; - if(rvb[core].CurrAddr>rvb[core].EndAddr) rvb[core].CurrAddr=rvb[core].StartAddr; - } - - return rvb[core].iLastRVBLeft; - } - return 0; -} - -//////////////////////////////////////////////////////////////////////// - -static INLINE int MixREVERBRight(int core) -{ - if(iUseReverb==1) // Neill's reverb: - { - int i=rvb[core].iLastRVBRight+(rvb[core].iRVBRight-rvb[core].iLastRVBRight)/2; - rvb[core].iLastRVBRight=rvb[core].iRVBRight; - return i; // -> just return the last right reverb val (little bit scaled by the previous right val) - } - return 0; -} - -//////////////////////////////////////////////////////////////////////// - -#endif - -/* ------------------------------------------------------------------------------ -PSX reverb hardware notes -by Neill Corlett ------------------------------------------------------------------------------ - -Yadda yadda disclaimer yadda probably not perfect yadda well it's okay anyway -yadda yadda. - ------------------------------------------------------------------------------ - -Basics ------- - -- The reverb buffer is 22khz 16-bit mono PCM. -- It starts at the reverb address given by 1DA2, extends to - the end of sound RAM, and wraps back to the 1DA2 address. - -Setting the address at 1DA2 resets the current reverb work address. - -This work address ALWAYS increments every 1/22050 sec., regardless of -whether reverb is enabled (bit 7 of 1DAA set). - -And the contents of the reverb buffer ALWAYS play, scaled by the -"reverberation depth left/right" volumes (1D84/1D86). -(which, by the way, appear to be scaled so 3FFF=approx. 1.0, 4000=-1.0) - ------------------------------------------------------------------------------ - -Register names --------------- - -These are probably not their real names. -These are probably not even correct names. -We will use them anyway, because we can. - -1DC0: FB_SRC_A (offset) -1DC2: FB_SRC_B (offset) -1DC4: IIR_ALPHA (coef.) -1DC6: ACC_COEF_A (coef.) -1DC8: ACC_COEF_B (coef.) -1DCA: ACC_COEF_C (coef.) -1DCC: ACC_COEF_D (coef.) -1DCE: IIR_COEF (coef.) -1DD0: FB_ALPHA (coef.) -1DD2: FB_X (coef.) -1DD4: IIR_DEST_A0 (offset) -1DD6: IIR_DEST_A1 (offset) -1DD8: ACC_SRC_A0 (offset) -1DDA: ACC_SRC_A1 (offset) -1DDC: ACC_SRC_B0 (offset) -1DDE: ACC_SRC_B1 (offset) -1DE0: IIR_SRC_A0 (offset) -1DE2: IIR_SRC_A1 (offset) -1DE4: IIR_DEST_B0 (offset) -1DE6: IIR_DEST_B1 (offset) -1DE8: ACC_SRC_C0 (offset) -1DEA: ACC_SRC_C1 (offset) -1DEC: ACC_SRC_D0 (offset) -1DEE: ACC_SRC_D1 (offset) -1DF0: IIR_SRC_B1 (offset) -1DF2: IIR_SRC_B0 (offset) -1DF4: MIX_DEST_A0 (offset) -1DF6: MIX_DEST_A1 (offset) -1DF8: MIX_DEST_B0 (offset) -1DFA: MIX_DEST_B1 (offset) -1DFC: IN_COEF_L (coef.) -1DFE: IN_COEF_R (coef.) - -The coefficients are signed fractional values. --32768 would be -1.0 - 32768 would be 1.0 (if it were possible... the highest is of course 32767) - -The offsets are (byte/8) offsets into the reverb buffer. -i.e. you multiply them by 8, you get byte offsets. -You can also think of them as (samples/4) offsets. -They appear to be signed. They can be negative. -None of the documented presets make them negative, though. - -Yes, 1DF0 and 1DF2 appear to be backwards. Not a typo. - ------------------------------------------------------------------------------ - -What it does ------------- - -We take all reverb sources: -- regular channels that have the reverb bit on -- cd and external sources, if their reverb bits are on -and mix them into one stereo 44100hz signal. - -Lowpass/downsample that to 22050hz. The PSX uses a proper bandlimiting -algorithm here, but I haven't figured out the hysterically exact specifics. -I use an 8-tap filter with these coefficients, which are nice but probably -not the real ones: - -0.037828187894 -0.157538631280 -0.321159685278 -0.449322115345 -0.449322115345 -0.321159685278 -0.157538631280 -0.037828187894 - -So we have two input samples (INPUT_SAMPLE_L, INPUT_SAMPLE_R) every 22050hz. - -* IN MY EMULATION, I divide these by 2 to make it clip less. - (and of course the L/R output coefficients are adjusted to compensate) - The real thing appears to not do this. - -At every 22050hz tick: -- If the reverb bit is enabled (bit 7 of 1DAA), execute the reverb - steady-state algorithm described below -- AFTERWARDS, retrieve the "wet out" L and R samples from the reverb buffer - (This part may not be exactly right and I guessed at the coefs. TODO: check later.) - L is: 0.333 * (buffer[MIX_DEST_A0] + buffer[MIX_DEST_B0]) - R is: 0.333 * (buffer[MIX_DEST_A1] + buffer[MIX_DEST_B1]) -- Advance the current buffer position by 1 sample - -The wet out L and R are then upsampled to 44100hz and played at the -"reverberation depth left/right" (1D84/1D86) volume, independent of the main -volume. - ------------------------------------------------------------------------------ - -Reverb steady-state -------------------- - -The reverb steady-state algorithm is fairly clever, and of course by -"clever" I mean "batshit insane". - -buffer[x] is relative to the current buffer position, not the beginning of -the buffer. Note that all buffer offsets must wrap around so they're -contained within the reverb work area. - -Clipping is performed at the end... maybe also sooner, but definitely at -the end. - -IIR_INPUT_A0 = buffer[IIR_SRC_A0] * IIR_COEF + INPUT_SAMPLE_L * IN_COEF_L; -IIR_INPUT_A1 = buffer[IIR_SRC_A1] * IIR_COEF + INPUT_SAMPLE_R * IN_COEF_R; -IIR_INPUT_B0 = buffer[IIR_SRC_B0] * IIR_COEF + INPUT_SAMPLE_L * IN_COEF_L; -IIR_INPUT_B1 = buffer[IIR_SRC_B1] * IIR_COEF + INPUT_SAMPLE_R * IN_COEF_R; - -IIR_A0 = IIR_INPUT_A0 * IIR_ALPHA + buffer[IIR_DEST_A0] * (1.0 - IIR_ALPHA); -IIR_A1 = IIR_INPUT_A1 * IIR_ALPHA + buffer[IIR_DEST_A1] * (1.0 - IIR_ALPHA); -IIR_B0 = IIR_INPUT_B0 * IIR_ALPHA + buffer[IIR_DEST_B0] * (1.0 - IIR_ALPHA); -IIR_B1 = IIR_INPUT_B1 * IIR_ALPHA + buffer[IIR_DEST_B1] * (1.0 - IIR_ALPHA); - -buffer[IIR_DEST_A0 + 1sample] = IIR_A0; -buffer[IIR_DEST_A1 + 1sample] = IIR_A1; -buffer[IIR_DEST_B0 + 1sample] = IIR_B0; -buffer[IIR_DEST_B1 + 1sample] = IIR_B1; - -ACC0 = buffer[ACC_SRC_A0] * ACC_COEF_A + - buffer[ACC_SRC_B0] * ACC_COEF_B + - buffer[ACC_SRC_C0] * ACC_COEF_C + - buffer[ACC_SRC_D0] * ACC_COEF_D; -ACC1 = buffer[ACC_SRC_A1] * ACC_COEF_A + - buffer[ACC_SRC_B1] * ACC_COEF_B + - buffer[ACC_SRC_C1] * ACC_COEF_C + - buffer[ACC_SRC_D1] * ACC_COEF_D; - -FB_A0 = buffer[MIX_DEST_A0 - FB_SRC_A]; -FB_A1 = buffer[MIX_DEST_A1 - FB_SRC_A]; -FB_B0 = buffer[MIX_DEST_B0 - FB_SRC_B]; -FB_B1 = buffer[MIX_DEST_B1 - FB_SRC_B]; - -buffer[MIX_DEST_A0] = ACC0 - FB_A0 * FB_ALPHA; -buffer[MIX_DEST_A1] = ACC1 - FB_A1 * FB_ALPHA; -buffer[MIX_DEST_B0] = (FB_ALPHA * ACC0) - FB_A0 * (FB_ALPHA^0x8000) - FB_B0 * FB_X; -buffer[MIX_DEST_B1] = (FB_ALPHA * ACC1) - FB_A1 * (FB_ALPHA^0x8000) - FB_B1 * FB_X; - ------------------------------------------------------------------------------ -*/ - diff --git a/Frameworks/AudioOverload/aosdk/eng_psf/peops2/reverb.h b/Frameworks/AudioOverload/aosdk/eng_psf/peops2/reverb.h deleted file mode 100755 index 5305030c1..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_psf/peops2/reverb.h +++ /dev/null @@ -1,33 +0,0 @@ -/*************************************************************************** - reverb.h - description - ------------------- - begin : Wed May 15 2002 - copyright : (C) 2002 by Pete Bernert - email : BlackDove@addcom.de - ***************************************************************************/ - -/*************************************************************************** - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. See also the license.txt file for * - * additional informations. * - * * - ***************************************************************************/ - -//*************************************************************************// -// History of changes: -// -// 2004/04/04 - Pete -// - changed plugin to emulate PS2 spu -// -// 2002/05/15 - Pete -// - generic cleanup for the Peops release -// -//*************************************************************************// - - -INLINE void StartREVERB(int ch); -INLINE void StoreREVERB(int ch,int ns); - diff --git a/Frameworks/AudioOverload/aosdk/eng_psf/peops2/spu.c b/Frameworks/AudioOverload/aosdk/eng_psf/peops2/spu.c deleted file mode 100644 index 5b73ab000..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_psf/peops2/spu.c +++ /dev/null @@ -1,1013 +0,0 @@ -/*************************************************************************** - spu.c - description - ------------------- - begin : Wed May 15 2002 - copyright : (C) 2002 by Pete Bernert - email : BlackDove@addcom.de - ***************************************************************************/ - -/*************************************************************************** - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. See also the license.txt file for * - * additional informations. * - * * - ***************************************************************************/ - -//*************************************************************************// -// History of changes: -// -// 2005/08/29 - Pete -// - changed to 48Khz output -// -// 2004/12/25 - Pete -// - inc'd version for pcsx2-0.7 -// -// 2004/04/18 - Pete -// - changed all kind of things in the plugin -// -// 2004/04/04 - Pete -// - changed plugin to emulate PS2 spu -// -// 2003/04/07 - Eric -// - adjusted cubic interpolation algorithm -// -// 2003/03/16 - Eric -// - added cubic interpolation -// -// 2003/03/01 - linuzappz -// - libraryName changes using ALSA -// -// 2003/02/28 - Pete -// - added option for type of interpolation -// - adjusted spu irqs again (Thousant Arms, Valkyrie Profile) -// - added MONO support for MSWindows DirectSound -// -// 2003/02/20 - kode54 -// - amended interpolation code, goto GOON could skip initialization of gpos and cause segfault -// -// 2003/02/19 - kode54 -// - moved SPU IRQ handler and changed sample flag processing -// -// 2003/02/18 - kode54 -// - moved ADSR calculation outside of the sample decode loop, somehow I doubt that -// ADSR timing is relative to the frequency at which a sample is played... I guess -// this remains to be seen, and I don't know whether ADSR is applied to noise channels... -// -// 2003/02/09 - kode54 -// - one-shot samples now process the end block before stopping -// - in light of removing fmod hack, now processing ADSR on frequency channel as well -// -// 2003/02/08 - kode54 -// - replaced easy interpolation with gaussian -// - removed fmod averaging hack -// - changed .sinc to be updated from .iRawPitch, no idea why it wasn't done this way already (<- Pete: because I sometimes fail to see the obvious, haharhar :) -// -// 2003/02/08 - linuzappz -// - small bugfix for one usleep that was 1 instead of 1000 -// - added iDisStereo for no stereo (Linux) -// -// 2003/01/22 - Pete -// - added easy interpolation & small noise adjustments -// -// 2003/01/19 - Pete -// - added Neill's reverb -// -// 2003/01/12 - Pete -// - added recording window handlers -// -// 2003/01/06 - Pete -// - added Neill's ADSR timings -// -// 2002/12/28 - Pete -// - adjusted spu irq handling, fmod handling and loop handling -// -// 2002/08/14 - Pete -// - added extra reverb -// -// 2002/06/08 - linuzappz -// - SPUupdate changed for SPUasync -// -// 2002/05/15 - Pete -// - generic cleanup for the Peops release -// -//*************************************************************************// - -#include "stdafx.h" - -#define _IN_SPU - -#include "../peops2/externals.h" -#include "../peops2/regs.h" -#include "../peops2/dma.h" - -//////////////////////////////////////////////////////////////////////// -// globals -//////////////////////////////////////////////////////////////////////// - -// psx buffer / addresses - -unsigned short regArea[32*1024]; -unsigned short spuMem[1*1024*1024]; -unsigned char * spuMemC; -unsigned char * pSpuIrq[2]; -unsigned char * pSpuBuffer; - -// user settings - -int iUseXA=0; -int iVolume=3; -int iXAPitch=1; -int iUseTimer=2; -int iSPUIRQWait=1; -int iDebugMode=0; -int iRecordMode=0; -int iUseReverb=1; -int iUseInterpolation=2; - -// MAIN infos struct for each channel - -SPUCHAN s_chan[MAXCHAN+1]; // channel + 1 infos (1 is security for fmod handling) -REVERBInfo rvb[2]; - -unsigned long dwNoiseVal=1; // global noise generator - -unsigned short spuCtrl2[2]; // some vars to store psx reg infos -unsigned short spuStat2[2]; -unsigned long spuIrq2[2]; -unsigned long spuAddr2[2]; // address into spu mem -unsigned long spuRvbAddr2[2]; -unsigned long spuRvbAEnd2[2]; -int bEndThread=0; // thread handlers -int bThreadEnded=0; -int bSpuInit=0; -int bSPUIsOpen=0; - -unsigned long dwNewChannel2[2]; // flags for faster testing, if new channel starts -unsigned long dwEndChannel2[2]; - -// UNUSED IN PS2 YET -void (CALLBACK *irqCallback)(void)=0; // func of main emu, called on spu irq -void (CALLBACK *cddavCallback)(unsigned short,unsigned short)=0; - -// certain globals (were local before, but with the new timeproc I need em global) - -const int f[5][2] = { { 0, 0 }, - { 60, 0 }, - { 115, -52 }, - { 98, -55 }, - { 122, -60 } }; -int SSumR[NSSIZE]; -int SSumL[NSSIZE]; -int iCycle=0; -short * pS; - -static int lastch=-1; // last channel processed on spu irq in timer mode -static int lastns=0; // last ns pos -static int iSecureStart=0; // secure start counter - -extern void ps2_update(unsigned char *samples, long lBytes); - -//////////////////////////////////////////////////////////////////////// -// CODE AREA -//////////////////////////////////////////////////////////////////////// - -// dirty inline func includes - -#include "reverb.c" -#include "adsr.c" - -//////////////////////////////////////////////////////////////////////// -// helpers for simple interpolation - -// -// easy interpolation on upsampling, no special filter, just "Pete's common sense" tm -// -// instead of having n equal sample values in a row like: -// ____ -// |____ -// -// we compare the current delta change with the next delta change. -// -// if curr_delta is positive, -// -// - and next delta is smaller (or changing direction): -// \. -// -__ -// -// - and next delta significant (at least twice) bigger: -// --_ -// \. -// -// - and next delta is nearly same: -// \. -// \. -// -// -// if curr_delta is negative, -// -// - and next delta is smaller (or changing direction): -// _-- -// / -// -// - and next delta significant (at least twice) bigger: -// / -// __- -// -// - and next delta is nearly same: -// / -// / -// - - -static INLINE void InterpolateUp(int ch) -{ - if(s_chan[ch].SB[32]==1) // flag == 1? calc step and set flag... and don't change the value in this pass - { - const int id1=s_chan[ch].SB[30]-s_chan[ch].SB[29]; // curr delta to next val - const int id2=s_chan[ch].SB[31]-s_chan[ch].SB[30]; // and next delta to next-next val :) - - s_chan[ch].SB[32]=0; - - if(id1>0) // curr delta positive - { - if(id2id1) - {s_chan[ch].SB[28]=id1;s_chan[ch].SB[32]=2;} - else - if(id2>(id1<<1)) - s_chan[ch].SB[28]=(id1*s_chan[ch].sinc)/0x10000L; - else - s_chan[ch].SB[28]=(id1*s_chan[ch].sinc)/0x20000L; - } - } - else - if(s_chan[ch].SB[32]==2) // flag 1: calc step and set flag... and don't change the value in this pass - { - s_chan[ch].SB[32]=0; - - s_chan[ch].SB[28]=(s_chan[ch].SB[28]*s_chan[ch].sinc)/0x20000L; - if(s_chan[ch].sinc<=0x8000) - s_chan[ch].SB[29]=s_chan[ch].SB[30]-(s_chan[ch].SB[28]*((0x10000/s_chan[ch].sinc)-1)); - else s_chan[ch].SB[29]+=s_chan[ch].SB[28]; - } - else // no flags? add bigger val (if possible), calc smaller step, set flag1 - s_chan[ch].SB[29]+=s_chan[ch].SB[28]; -} - -// -// even easier interpolation on downsampling, also no special filter, again just "Pete's common sense" tm -// - -static INLINE void InterpolateDown(int ch) -{ - if(s_chan[ch].sinc>=0x20000L) // we would skip at least one val? - { - s_chan[ch].SB[29]+=(s_chan[ch].SB[30]-s_chan[ch].SB[29])/2; // add easy weight - if(s_chan[ch].sinc>=0x30000L) // we would skip even more vals? - s_chan[ch].SB[29]+=(s_chan[ch].SB[31]-s_chan[ch].SB[30])/2;// add additional next weight - } -} - -//////////////////////////////////////////////////////////////////////// -// helpers for gauss interpolation - -#define gval0 (((short*)(&s_chan[ch].SB[29]))[gpos]) -#define gval(x) (((short*)(&s_chan[ch].SB[29]))[(gpos+x)&3]) - -#include "gauss_i.h" - -//////////////////////////////////////////////////////////////////////// - -//#include "xa.c" - -//////////////////////////////////////////////////////////////////////// -// START SOUND... called by main thread to setup a new sound on a channel -//////////////////////////////////////////////////////////////////////// - -static INLINE void StartSound(int ch) -{ - dwNewChannel2[ch/24]&=~(1<<(ch%24)); // clear new channel bit - dwEndChannel2[ch/24]&=~(1<<(ch%24)); // clear end channel bit - - StartADSR(ch); - StartREVERB(ch); - - s_chan[ch].pCurr=s_chan[ch].pStart; // set sample start - - s_chan[ch].s_1=0; // init mixing vars - s_chan[ch].s_2=0; - s_chan[ch].iSBPos=28; - - s_chan[ch].bNew=0; // init channel flags - s_chan[ch].bStop=0; - s_chan[ch].bOn=1; - - s_chan[ch].SB[29]=0; // init our interpolation helpers - s_chan[ch].SB[30]=0; - - if(iUseInterpolation>=2) // gauss interpolation? - {s_chan[ch].spos=0x30000L;s_chan[ch].SB[28]=0;} // -> start with more decoding - else {s_chan[ch].spos=0x10000L;s_chan[ch].SB[31]=0;} // -> no/simple interpolation starts with one 44100 decoding -} - -//////////////////////////////////////////////////////////////////////// -// MAIN SPU FUNCTION -// here is the main job handler... thread, timer or direct func call -// basically the whole sound processing is done in this fat func! -//////////////////////////////////////////////////////////////////////// - -static u32 sampcount; -static u32 decaybegin; -static u32 decayend; - -// Counting to 65536 results in full volume offage. -void setlength2(s32 stop, s32 fade) -{ - if(stop==~0) - { - decaybegin=~0; - } - else - { - stop=(stop*441)/10; - fade=(fade*441)/10; - - decaybegin=stop; - decayend=stop+fade; - } -} -// 5 ms waiting phase, if buffer is full and no new sound has to get started -// .. can be made smaller (smallest val: 1 ms), but bigger waits give -// better performance - -#define PAUSE_W 5 -#define PAUSE_L 5000 - -//////////////////////////////////////////////////////////////////////// - -int iSpuAsyncWait=0; - -static void *MAINThread(int samp2run) -{ - int s_1,s_2,fa,voldiv=iVolume; - unsigned char * start;unsigned int nSample; - int ch,predict_nr,shift_factor,flags,d,d2,s; - int gpos,bIRQReturn=0; - -// while(!bEndThread) // until we are shutting down - { - //--------------------------------------------------// - // ok, at the beginning we are looking if there is - // enuff free place in the dsound/oss buffer to - // fill in new data, or if there is a new channel to start. - // if not, we wait (thread) or return (timer/spuasync) - // until enuff free place is available/a new channel gets - // started - - if(dwNewChannel2[0] || dwNewChannel2[1]) // new channel should start immedately? - { // (at least one bit 0 ... MAXCHANNEL is set?) - iSecureStart++; // -> set iSecure - if(iSecureStart>5) iSecureStart=0; // (if it is set 5 times - that means on 5 tries a new samples has been started - in a row, we will reset it, to give the sound update a chance) - } - else iSecureStart=0; // 0: no new channel should start - -/* if (!iSecureStart) - { - iSecureStart=0; // reset secure - return; - }*/ - -#if 0 - while(!iSecureStart && !bEndThread) // && // no new start? no thread end? -// (SoundGetBytesBuffered()>TESTSIZE)) // and still enuff data in sound buffer? - { - iSecureStart=0; // reset secure - - if(iUseTimer) return 0; // linux no-thread mode? bye - - if(dwNewChannel2[0] || dwNewChannel2[1]) - iSecureStart=1; // if a new channel kicks in (or, of course, sound buffer runs low), we will leave the loop - } -#endif - - //--------------------------------------------------// continue from irq handling in timer mode? - - if(lastch>=0) // will be -1 if no continue is pending - { - ch=lastch; lastch=-1; // -> setup all kind of vars to continue - goto GOON; // -> directly jump to the continue point - } - - //--------------------------------------------------// - //- main channel loop -// - //--------------------------------------------------// - { - for(ch=0;ch take it and calc steps - s_chan[ch].sinc=s_chan[ch].iRawPitch<<4; - if(!s_chan[ch].sinc) s_chan[ch].sinc=1; - if(iUseInterpolation==1) s_chan[ch].SB[32]=1; // -> freq change in simle imterpolation mode: set flag - } -// ns=0; -// while(ns=0x10000L) - { - if(s_chan[ch].iSBPos==28) // 28 reached? - { - start=s_chan[ch].pCurr; // set up the current pos - - if (start == (unsigned char*)-1) // special "stop" sign - { - s_chan[ch].bOn=0; // -> turn everything off - s_chan[ch].ADSRX.lVolume=0; - s_chan[ch].ADSRX.EnvelopeVol=0; - goto ENDX; // -> and done for this channel - } - - s_chan[ch].iSBPos=0; - - //////////////////////////////////////////// spu irq handler here? mmm... do it later - - s_1=s_chan[ch].s_1; - s_2=s_chan[ch].s_2; - - predict_nr=(int)*start;start++; - shift_factor=predict_nr&0xf; - predict_nr >>= 4; - flags=(int)*start;start++; - - // -------------------------------------- // - - for (nSample=0;nSample<28;start++) - { - d=(int)*start; - s=((d&0xf)<<12); - if(s&0x8000) s|=0xffff0000; - - fa=(s >> shift_factor); - fa=fa + ((s_1 * f[predict_nr][0])>>6) + ((s_2 * f[predict_nr][1])>>6); - s_2=s_1;s_1=fa; - s=((d & 0xf0) << 8); - - s_chan[ch].SB[nSample++]=fa; - - if(s&0x8000) s|=0xffff0000; - fa=(s>>shift_factor); - fa=fa + ((s_1 * f[predict_nr][0])>>6) + ((s_2 * f[predict_nr][1])>>6); - s_2=s_1;s_1=fa; - - s_chan[ch].SB[nSample++]=fa; - } - - //////////////////////////////////////////// irq check - - if(spuCtrl2[ch/24]&0x40) // some irq active? - { - if((pSpuIrq[ch/24] > start-16 && // irq address reached? - pSpuIrq[ch/24] <= start) || - ((flags&1) && // special: irq on looping addr, when stop/loop flag is set - (pSpuIrq[ch/24] > s_chan[ch].pLoop-16 && - pSpuIrq[ch/24] <= s_chan[ch].pLoop))) - { - s_chan[ch].iIrqDone=1; // -> debug flag - - if(irqCallback) irqCallback(); // -> call main emu (not supported in SPU2 right now) - else - { - if(ch<24) InterruptDMA4(); // -> let's see what is happening if we call our irqs instead ;) - else InterruptDMA7(); - } - - if(iSPUIRQWait) // -> option: wait after irq for main emu - { - iSpuAsyncWait=1; - bIRQReturn=1; - } - } - } - - //////////////////////////////////////////// flag handler - - if((flags&4) && (!s_chan[ch].bIgnoreLoop)) - s_chan[ch].pLoop=start-16; // loop adress - - if(flags&1) // 1: stop/loop - { - dwEndChannel2[ch/24]|=(1<<(ch%24)); - - // We play this block out first... - //if(!(flags&2)|| s_chan[ch].pLoop==NULL) - // 1+2: do loop... otherwise: stop - if(flags!=3 || s_chan[ch].pLoop==NULL) // PETE: if we don't check exactly for 3, loop hang ups will happen (DQ4, for example) - { // and checking if pLoop is set avoids crashes, yeah - start = (unsigned char*)-1; - } - else - { - start = s_chan[ch].pLoop; - } - } - - s_chan[ch].pCurr=start; // store values for next cycle - s_chan[ch].s_1=s_1; - s_chan[ch].s_2=s_2; - - //////////////////////////////////////////// - - if(bIRQReturn) // special return for "spu irq - wait for cpu action" - { - bIRQReturn=0; - { - lastch=ch; -// lastns=ns; // changemeback - - return 0; - } - } - - //////////////////////////////////////////// - -GOON: ; - - } - - fa=s_chan[ch].SB[s_chan[ch].iSBPos++]; // get sample data - -// if((spuCtrl2[ch/24]&0x4000)==0) fa=0; // muted? -// else // else adjust - { - if(fa>32767L) fa=32767L; - if(fa<-32767L) fa=-32767L; - } - - if(iUseInterpolation>=2) // gauss/cubic interpolation - { - gpos = s_chan[ch].SB[28]; - gval0 = fa; - gpos = (gpos+1) & 3; - s_chan[ch].SB[28] = gpos; - } - else - if(iUseInterpolation==1) // simple interpolation - { - s_chan[ch].SB[28] = 0; - s_chan[ch].SB[29] = s_chan[ch].SB[30]; // -> helpers for simple linear interpolation: delay real val for two slots, and calc the two deltas, for a 'look at the future behaviour' - s_chan[ch].SB[30] = s_chan[ch].SB[31]; - s_chan[ch].SB[31] = fa; - s_chan[ch].SB[32] = 1; // -> flag: calc new interolation - } - else s_chan[ch].SB[29]=fa; // no interpolation - - s_chan[ch].spos -= 0x10000L; - } - - //////////////////////////////////////////////// - // noise handler... just produces some noise data - // surely wrong... and no noise frequency (spuCtrl&0x3f00) will be used... - // and sometimes the noise will be used as fmod modulation... pfff - - if(s_chan[ch].bNoise) - { - if((dwNoiseVal<<=1)&0x80000000L) - { - dwNoiseVal^=0x0040001L; - fa=((dwNoiseVal>>2)&0x7fff); - fa=-fa; - } - else fa=(dwNoiseVal>>2)&0x7fff; - - // mmm... depending on the noise freq we allow bigger/smaller changes to the previous val - fa=s_chan[ch].iOldNoise+((fa-s_chan[ch].iOldNoise)/((0x001f-((spuCtrl2[ch/24]&0x3f00)>>9))+1)); - if(fa>32767L) fa=32767L; - if(fa<-32767L) fa=-32767L; - s_chan[ch].iOldNoise=fa; - - if(iUseInterpolation<2) // no gauss/cubic interpolation? - s_chan[ch].SB[29] = fa; // -> store noise val in "current sample" slot - } //---------------------------------------- - else // NO NOISE (NORMAL SAMPLE DATA) HERE - {//------------------------------------------// - if(iUseInterpolation==3) // cubic interpolation - { - long xd; - xd = ((s_chan[ch].spos) >> 1)+1; - gpos = s_chan[ch].SB[28]; - - fa = gval(3) - 3*gval(2) + 3*gval(1) - gval0; - fa *= (xd - (2<<15)) / 6; - fa >>= 15; - fa += gval(2) - gval(1) - gval(1) + gval0; - fa *= (xd - (1<<15)) >> 1; - fa >>= 15; - fa += gval(1) - gval0; - fa *= xd; - fa >>= 15; - fa = fa + gval0; - } - //------------------------------------------// - else - if(iUseInterpolation==2) // gauss interpolation - { - int vl, vr; - vl = (s_chan[ch].spos >> 6) & ~3; - gpos = s_chan[ch].SB[28]; - vr=(gauss[vl]*gval0)&~2047; - vr+=(gauss[vl+1]*gval(1))&~2047; - vr+=(gauss[vl+2]*gval(2))&~2047; - vr+=(gauss[vl+3]*gval(3))&~2047; - fa = vr>>11; -/* - vr=(gauss[vl]*gval0)>>9; - vr+=(gauss[vl+1]*gval(1))>>9; - vr+=(gauss[vl+2]*gval(2))>>9; - vr+=(gauss[vl+3]*gval(3))>>9; - fa = vr>>2; -*/ - } - //------------------------------------------// - else - if(iUseInterpolation==1) // simple interpolation - { - if(s_chan[ch].sinc<0x10000L) // -> upsampling? - InterpolateUp(ch); // --> interpolate up - else InterpolateDown(ch); // --> else down - fa=s_chan[ch].SB[29]; - } - //------------------------------------------// - else fa=s_chan[ch].SB[29]; // no interpolation - } - - s_chan[ch].sval = (MixADSR(ch) * fa) / 1023; // add adsr - - if(s_chan[ch].bFMod==2) // fmod freq channel - { - int NP=s_chan[ch+1].iRawPitch; - double intr; - - NP=((32768L+s_chan[ch].sval)*NP)/32768L; // mmm... I still need to adjust that to 1/48 khz... we will wait for the first game/demo using it to decide how to do it :) - - if(NP>0x3fff) NP=0x3fff; - if(NP<0x1) NP=0x1; - - intr = (double)48000.0f / (double)44100.0f * (double)NP; - NP = (UINT32)intr; - - NP=(44100L*NP)/(4096L); // calc frequency - - s_chan[ch+1].iActFreq=NP; - s_chan[ch+1].iUsedFreq=NP; - s_chan[ch+1].sinc=(((NP/10)<<16)/4410); - if(!s_chan[ch+1].sinc) s_chan[ch+1].sinc=1; - if(iUseInterpolation==1) // freq change in sipmle interpolation mode - s_chan[ch+1].SB[32]=1; - -// mmmm... set up freq decoding positions? -// s_chan[ch+1].iSBPos=28; -// s_chan[ch+1].spos=0x10000L; - } - else - { - ////////////////////////////////////////////// - // ok, left/right sound volume (psx volume goes from 0 ... 0x3fff) - - if(s_chan[ch].iMute) - s_chan[ch].sval=0; // debug mute - else - { - if(s_chan[ch].bVolumeL) - SSumL[0]+=(s_chan[ch].sval*s_chan[ch].iLeftVolume)/0x4000L; - if(s_chan[ch].bVolumeR) - SSumR[0]+=(s_chan[ch].sval*s_chan[ch].iRightVolume)/0x4000L; - } - - ////////////////////////////////////////////// - // now let us store sound data for reverb - - if(s_chan[ch].bRVBActive) StoreREVERB(ch,0); - } - - //////////////////////////////////////////////// - // ok, go on until 1 ms data of this channel is collected - - s_chan[ch].spos += s_chan[ch].sinc; - - } -ENDX: ; - } - } - - //---------------------------------------------------// - //- here we have another 1 ms of sound data - //---------------------------------------------------// - - /////////////////////////////////////////////////////// - // mix all channels (including reverb) into one buffer - - SSumL[0]+=MixREVERBLeft(0,0); - SSumL[0]+=MixREVERBLeft(0,1); - SSumR[0]+=MixREVERBRight(0); - SSumR[0]+=MixREVERBRight(1); - - d=SSumL[0]/voldiv;SSumL[0]=0; - d2=SSumR[0]/voldiv;SSumR[0]=0; - - if(d<-32767) d=-32767;if(d>32767) d=32767; - if(d2<-32767) d2=-32767;if(d2>32767) d2=32767; - - if(sampcount>=decaybegin) - { - s32 dmul; - if(decaybegin!=~0) // Is anyone REALLY going to be playing a song - // for 13 hours? - { - if(sampcount>=decayend) - { -// ao_song_done = 1; - return(0); - } - - dmul=256-(256*(sampcount-decaybegin)/(decayend-decaybegin)); - d=(d*dmul)>>8; - d2=(d2*dmul)>>8; - } - } - sampcount++; - - *pS++=d; - *pS++=d2; - - InitREVERB(); - - ////////////////////////////////////////////////////// - // feed the sound - // wanna have around 1/60 sec (16.666 ms) updates - if ((((unsigned char *)pS)-((unsigned char *)pSpuBuffer)) == (735*4)) - { - ps2_update((u8*)pSpuBuffer,(u8*)pS-(u8*)pSpuBuffer); - pS=(short *)pSpuBuffer; - } - } - - // end of big main loop... - - bThreadEnded=1; - - return 0; -} - -//////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////// - -//////////////////////////////////////////////////////////////////////// -// SPU ASYNC... even newer epsxe func -// 1 time every 'cycle' cycles... harhar -//////////////////////////////////////////////////////////////////////// - -EXPORT_GCC void CALLBACK SPU2async(unsigned long cycle) -{ - if(iSpuAsyncWait) - { - iSpuAsyncWait++; - if(iSpuAsyncWait<=64) return; - iSpuAsyncWait=0; - } - - MAINThread(0); // -> linux high-compat mode -} - -//////////////////////////////////////////////////////////////////////// -// INIT/EXIT STUFF -//////////////////////////////////////////////////////////////////////// - -//////////////////////////////////////////////////////////////////////// -// SPUINIT: this func will be called first by the main emu -//////////////////////////////////////////////////////////////////////// - - -EXPORT_GCC long CALLBACK SPU2init(void) -{ - spuMemC=(unsigned char *)spuMem; // just small setup - memset((void *)s_chan,0,MAXCHAN*sizeof(SPUCHAN)); - memset(rvb,0,2*sizeof(REVERBInfo)); - - sampcount = 0; - - InitADSR(); - - return 0; -} - -//////////////////////////////////////////////////////////////////////// -// SETUPTIMER: init of certain buffers and threads/timers -//////////////////////////////////////////////////////////////////////// - -static void SetupTimer(void) -{ - memset(SSumR,0,NSSIZE*sizeof(int)); // init some mixing buffers - memset(SSumL,0,NSSIZE*sizeof(int)); - pS=(short *)pSpuBuffer; // setup soundbuffer pointer - - bEndThread=0; // init thread vars - bThreadEnded=0; - bSpuInit=1; // flag: we are inited -} - -//////////////////////////////////////////////////////////////////////// -// REMOVETIMER: kill threads/timers -//////////////////////////////////////////////////////////////////////// - -static void RemoveTimer(void) -{ - bEndThread=1; // raise flag to end thread - bThreadEnded=0; // no more spu is running - bSpuInit=0; -} - -//////////////////////////////////////////////////////////////////////// -// SETUPSTREAMS: init most of the spu buffers -//////////////////////////////////////////////////////////////////////// - -static void SetupStreams(void) -{ - int i; - - pSpuBuffer=(unsigned char *)malloc(32768); // alloc mixing buffer - - i=NSSIZE*2; - - sRVBStart[0] = (int *)malloc(i*4); // alloc reverb buffer - memset(sRVBStart[0],0,i*4); - sRVBEnd[0] = sRVBStart[0] + i; - sRVBPlay[0] = sRVBStart[0]; - sRVBStart[1] = (int *)malloc(i*4); // alloc reverb buffer - memset(sRVBStart[1],0,i*4); - sRVBEnd[1] = sRVBStart[1] + i; - sRVBPlay[1] = sRVBStart[1]; - - for(i=0;i init sustain - s_chan[i].iMute=0; - s_chan[i].iIrqDone=0; - s_chan[i].pLoop=spuMemC; - s_chan[i].pStart=spuMemC; - s_chan[i].pCurr=spuMemC; - } -} - -//////////////////////////////////////////////////////////////////////// -// REMOVESTREAMS: free most buffer -//////////////////////////////////////////////////////////////////////// - -static void RemoveStreams(void) -{ - free(pSpuBuffer); // free mixing buffer - pSpuBuffer=NULL; - free(sRVBStart[0]); // free reverb buffer - sRVBStart[0]=0; - free(sRVBStart[1]); // free reverb buffer - sRVBStart[1]=0; - -/* - int i; - for(i=0;i -#define RRand(range) (random()%range) -#include -#include - -#undef CALLBACK -#define CALLBACK -#define DWORD unsigned long -#define LOWORD(l) ((unsigned short)(l)) -#define HIWORD(l) ((unsigned short)(((unsigned long)(l) >> 16) & 0xFFFF)) - -#include "psemuxa.h" - diff --git a/Frameworks/AudioOverload/aosdk/eng_psf/peops2/xa.c b/Frameworks/AudioOverload/aosdk/eng_psf/peops2/xa.c deleted file mode 100755 index fb63ad407..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_psf/peops2/xa.c +++ /dev/null @@ -1,363 +0,0 @@ -/*************************************************************************** - xa.c - description - ------------------- - begin : Wed May 15 2002 - copyright : (C) 2002 by Pete Bernert - email : BlackDove@addcom.de - ***************************************************************************/ - -/*************************************************************************** - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. See also the license.txt file for * - * additional informations. * - * * - ***************************************************************************/ - -//*************************************************************************// -// History of changes: -// -// 2003/02/18 - kode54 -// - added gaussian interpolation -// -// 2002/05/15 - Pete -// - generic cleanup for the Peops release -// -//*************************************************************************// - -#include "stdafx.h" - -#define _IN_XA - -// will be included from spu.c -#ifdef _IN_SPU - -//////////////////////////////////////////////////////////////////////// -// XA GLOBALS -//////////////////////////////////////////////////////////////////////// - -xa_decode_t * xapGlobal=0; - -unsigned long * XAFeed = NULL; -unsigned long * XAPlay = NULL; -unsigned long * XAStart = NULL; -unsigned long * XAEnd = NULL; - -unsigned long XARepeat = 0; -unsigned long XALastVal = 0; - -int iLeftXAVol = 32767; -int iRightXAVol = 32767; - -static int gauss_ptr = 0; -static int gauss_window[8] = {0, 0, 0, 0, 0, 0, 0, 0}; - -#define gvall0 gauss_window[gauss_ptr] -#define gvall(x) gauss_window[(gauss_ptr+x)&3] -#define gvalr0 gauss_window[4+gauss_ptr] -#define gvalr(x) gauss_window[4+((gauss_ptr+x)&3)] - -//////////////////////////////////////////////////////////////////////// -// MIX XA -//////////////////////////////////////////////////////////////////////// - -INLINE void MixXA(void) -{ - int ns; - - for(ns=0;ns>16)&0xffff)) * iRightXAVol)/32767; - } - - if(XAPlay==XAFeed && XARepeat) - { - XARepeat--; - for(;ns>16)&0xffff)) * iRightXAVol)/32767; - } - } -} - -//////////////////////////////////////////////////////////////////////// -// FEED XA -//////////////////////////////////////////////////////////////////////// - -INLINE void FeedXA(xa_decode_t *xap) -{ - int sinc,spos,i,iSize,iPlace,vl,vr; - - if(!bSPUIsOpen) return; - - xapGlobal = xap; // store info for save states - XARepeat = 100; // set up repeat - - iSize=((44100*xap->nsamples)/xap->freq); // get size - if(!iSize) return; // none? bye - - if(XAFeed=10) - { - if(!dwFPS) dwFPS=1; - dw1=1000000/dwFPS; - if(dw1>=(dwL1-100) && dw1<=(dwL1+100)) dw1=dwL1; - else dwL1=dw1; - dw2=(xap->freq*100/xap->nsamples); - if((!dw1)||((dw2+100)>=dw1)) iLastSize=0; - else - { - iLastSize=iSize*dw2/dw1; - if(iLastSize>iPlace) iLastSize=iPlace; - iSize=iLastSize; - } - iFPSCnt=0;dwFPS=0; - } - else - { - if(iLastSize) iSize=iLastSize; - } - } - //----------------------------------------------------// - - spos=0x10000L; - sinc = (xap->nsamples << 16) / iSize; // calc freq by num / size - - if(xap->stereo) - { - unsigned long * pS=(unsigned long *)xap->pcm; - unsigned long l=0; - - if(iXAPitch) - { - long l1,l2;short s; - for(i=0;i=0x10000L) - { - l = *pS++; - gauss_window[gauss_ptr] = (short)LOWORD(l); - gauss_window[4+gauss_ptr] = (short)HIWORD(l); - gauss_ptr = (gauss_ptr+1) & 3; - spos -= 0x10000L; - } - vl = (spos >> 6) & ~3; - vr=(gauss[vl]*gvall0)&~2047; - vr+=(gauss[vl+1]*gvall(1))&~2047; - vr+=(gauss[vl+2]*gvall(2))&~2047; - vr+=(gauss[vl+3]*gvall(3))&~2047; - l= (vr >> 11) & 0xffff; - vr=(gauss[vl]*gvalr0)&~2047; - vr+=(gauss[vl+1]*gvalr(1))&~2047; - vr+=(gauss[vl+2]*gvalr(2))&~2047; - vr+=(gauss[vl+3]*gvalr(3))&~2047; - l |= vr << 5; - } - else - { - while(spos>=0x10000L) - { - l = *pS++; - spos -= 0x10000L; - } - } - - s=(short)LOWORD(l); - l1=s; - l1=(l1*iPlace)/iSize; - if(l1<-32767) l1=-32767; - if(l1> 32767) l1=32767; - s=(short)HIWORD(l); - l2=s; - l2=(l2*iPlace)/iSize; - if(l2<-32767) l2=-32767; - if(l2> 32767) l2=32767; - l=(l1&0xffff)|(l2<<16); - - *XAFeed++=l; - - if(XAFeed==XAEnd) XAFeed=XAStart; - if(XAFeed==XAPlay) - { - if(XAPlay!=XAStart) XAFeed=XAPlay-1; - break; - } - - spos += sinc; - } - } - else - { - for(i=0;i=0x10000L) - { - l = *pS++; - gauss_window[gauss_ptr] = (short)LOWORD(l); - gauss_window[4+gauss_ptr] = (short)HIWORD(l); - gauss_ptr = (gauss_ptr+1) & 3; - spos -= 0x10000L; - } - vl = (spos >> 6) & ~3; - vr=(gauss[vl]*gvall0)&~2047; - vr+=(gauss[vl+1]*gvall(1))&~2047; - vr+=(gauss[vl+2]*gvall(2))&~2047; - vr+=(gauss[vl+3]*gvall(3))&~2047; - l= (vr >> 11) & 0xffff; - vr=(gauss[vl]*gvalr0)&~2047; - vr+=(gauss[vl+1]*gvalr(1))&~2047; - vr+=(gauss[vl+2]*gvalr(2))&~2047; - vr+=(gauss[vl+3]*gvalr(3))&~2047; - l |= vr << 5; - } - else - { - while(spos>=0x10000L) - { - l = *pS++; - spos -= 0x10000L; - } - } - - *XAFeed++=l; - - if(XAFeed==XAEnd) XAFeed=XAStart; - if(XAFeed==XAPlay) - { - if(XAPlay!=XAStart) XAFeed=XAPlay-1; - break; - } - - spos += sinc; - } - } - } - else - { - unsigned short * pS=(unsigned short *)xap->pcm; - unsigned long l;short s=0; - - if(iXAPitch) - { - long l1; - for(i=0;i=0x10000L) - { - gauss_window[gauss_ptr] = (short)*pS++; - gauss_ptr = (gauss_ptr+1) & 3; - spos -= 0x10000L; - } - vl = (spos >> 6) & ~3; - vr=(gauss[vl]*gvall0)&~2047; - vr+=(gauss[vl+1]*gvall(1))&~2047; - vr+=(gauss[vl+2]*gvall(2))&~2047; - vr+=(gauss[vl+3]*gvall(3))&~2047; - l1=s= vr >> 11; - l1 &= 0xffff; - } - else - { - while(spos>=0x10000L) - { - s = *pS++; - spos -= 0x10000L; - } - l1=s; - } - - l1=(l1*iPlace)/iSize; - if(l1<-32767) l1=-32767; - if(l1> 32767) l1=32767; - l=(l1&0xffff)|(l1<<16); - *XAFeed++=l; - - if(XAFeed==XAEnd) XAFeed=XAStart; - if(XAFeed==XAPlay) - { - if(XAPlay!=XAStart) XAFeed=XAPlay-1; - break; - } - - spos += sinc; - } - } - else - { - for(i=0;i=0x10000L) - { - gauss_window[gauss_ptr] = (short)*pS++; - gauss_ptr = (gauss_ptr+1) & 3; - spos -= 0x10000L; - } - vl = (spos >> 6) & ~3; - vr=(gauss[vl]*gvall0)&~2047; - vr+=(gauss[vl+1]*gvall(1))&~2047; - vr+=(gauss[vl+2]*gvall(2))&~2047; - vr+=(gauss[vl+3]*gvall(3))&~2047; - l=s= vr >> 11; - l &= 0xffff; - } - else - { - while(spos>=0x10000L) - { - s = *pS++; - spos -= 0x10000L; - } - l=s; - } - - *XAFeed++=(l|(l<<16)); - - if(XAFeed==XAEnd) XAFeed=XAStart; - if(XAFeed==XAPlay) - { - if(XAPlay!=XAStart) XAFeed=XAPlay-1; - break; - } - - spos += sinc; - } - } - } -} - -#endif - diff --git a/Frameworks/AudioOverload/aosdk/eng_psf/psx.c b/Frameworks/AudioOverload/aosdk/eng_psf/psx.c deleted file mode 100644 index ea452f95e..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_psf/psx.c +++ /dev/null @@ -1,3159 +0,0 @@ -/* - * Sony CXD8530AQ/CXD8530BQ/CXD8530CQ/CXD8661R - * - * PSX CPU emulator for the MAME project written by smf - * Thanks to Farfetch'd for information on the delay slot bug - * - * The PSX CPU is a custom r3000a with a built in - * geometry transform engine, no mmu & no data cache. - * - * There is a stall circuit for load delays, but - * it doesn't work if the load occurs in a branch - * delay slot. - * - */ - -#include -#include "ao.h" -#include "cpuintrf.h" -#include "psx.h" - -#define EXC_INT ( 0 ) -#define EXC_ADEL ( 4 ) -#define EXC_ADES ( 5 ) -#define EXC_SYS ( 8 ) -#define EXC_BP ( 9 ) -#define EXC_RI ( 10 ) -#define EXC_CPU ( 11 ) -#define EXC_OVF ( 12 ) - -#define CP0_RANDOM ( 1 ) -#define CP0_BADVADDR ( 8 ) -#define CP0_SR ( 12 ) -#define CP0_CAUSE ( 13 ) -#define CP0_EPC ( 14 ) -#define CP0_PRID ( 15 ) - -#define SR_IEC ( 1L << 0 ) -#define SR_KUC ( 1L << 1 ) -#define SR_ISC ( 1L << 16 ) -#define SR_SWC ( 1L << 17 ) -#define SR_TS ( 1L << 21 ) -#define SR_BEV ( 1L << 22 ) -#define SR_RE ( 1L << 25 ) -#define SR_CU0 ( 1L << 28 ) -#define SR_CU1 ( 1L << 29 ) -#define SR_CU2 ( 1L << 30 ) -#define SR_CU3 ( 1L << 31 ) - -#define CAUSE_EXC ( 31L << 2 ) -#define CAUSE_IP ( 255L << 8 ) -#define CAUSE_IP2 ( 1L << 10 ) -#define CAUSE_IP3 ( 1L << 11 ) -#define CAUSE_IP4 ( 1L << 12 ) -#define CAUSE_IP5 ( 1L << 13 ) -#define CAUSE_IP6 ( 1L << 14 ) -#define CAUSE_IP7 ( 1L << 15 ) -#define CAUSE_CE ( 3L << 28 ) -#define CAUSE_CE0 ( 0L << 28 ) -#define CAUSE_CE1 ( 1L << 28 ) -#define CAUSE_CE2 ( 2L << 28 ) -#define CAUSE_BD ( 1L << 31 ) - -extern void psx_bios_hle(uint32 pc); -extern void psx_iop_call(uint32 pc, uint32 callnum); -extern uint8 program_read_byte_32le(offs_t address); -extern uint16 program_read_word_32le(offs_t address); -extern uint32 program_read_dword_32le(offs_t address); -extern void program_write_byte_32le(offs_t address, uint8 data); -extern void program_write_word_32le(offs_t address, uint16 data); -extern void program_write_dword_32le(offs_t address, uint32 data); - -static UINT8 mips_reg_layout[] = -{ - MIPS_PC, -1, - MIPS_DELAYV, MIPS_DELAYR, -1, - MIPS_HI, MIPS_LO, -1, - -1, - MIPS_R0, MIPS_R1, -1, - MIPS_R2, MIPS_R3, -1, - MIPS_R4, MIPS_R5, -1, - MIPS_R6, MIPS_R7, -1, - MIPS_R8, MIPS_R9, -1, - MIPS_R10, MIPS_R11, -1, - MIPS_R12, MIPS_R13, -1, - MIPS_R14, MIPS_R15, -1, - MIPS_R16, MIPS_R17, -1, - MIPS_R18, MIPS_R19, -1, - MIPS_R20, MIPS_R21, -1, - MIPS_R22, MIPS_R23, -1, - MIPS_R24, MIPS_R25, -1, - MIPS_R26, MIPS_R27, -1, - MIPS_R28, MIPS_R29, -1, - MIPS_R30, MIPS_R31, -1, - -1, - MIPS_CP0R0, MIPS_CP0R1, -1, - MIPS_CP0R2, MIPS_CP0R3, -1, - MIPS_CP0R4, MIPS_CP0R5, -1, - MIPS_CP0R6, MIPS_CP0R7, -1, - MIPS_CP0R8, MIPS_CP0R9, -1, - MIPS_CP0R10, MIPS_CP0R11, -1, - MIPS_CP0R12, MIPS_CP0R13, -1, - MIPS_CP0R14, MIPS_CP0R15, -1, - MIPS_CP0R16, MIPS_CP0R17, -1, - MIPS_CP0R18, MIPS_CP0R19, -1, - MIPS_CP0R20, MIPS_CP0R21, -1, - MIPS_CP0R22, MIPS_CP0R23, -1, - MIPS_CP0R24, MIPS_CP0R25, -1, - MIPS_CP0R26, MIPS_CP0R27, -1, - MIPS_CP0R28, MIPS_CP0R29, -1, - MIPS_CP0R30, MIPS_CP0R31, -1, - -1, - MIPS_CP2DR0, MIPS_CP2DR1, -1, - MIPS_CP2DR2, MIPS_CP2DR3, -1, - MIPS_CP2DR4, MIPS_CP2DR5, -1, - MIPS_CP2DR6, MIPS_CP2DR7, -1, - MIPS_CP2DR8, MIPS_CP2DR9, -1, - MIPS_CP2DR10, MIPS_CP2DR11, -1, - MIPS_CP2DR12, MIPS_CP2DR13, -1, - MIPS_CP2DR14, MIPS_CP2DR15, -1, - MIPS_CP2DR16, MIPS_CP2DR17, -1, - MIPS_CP2DR18, MIPS_CP2DR19, -1, - MIPS_CP2DR20, MIPS_CP2DR21, -1, - MIPS_CP2DR22, MIPS_CP2DR23, -1, - MIPS_CP2DR24, MIPS_CP2DR25, -1, - MIPS_CP2DR26, MIPS_CP2DR27, -1, - MIPS_CP2DR28, MIPS_CP2DR29, -1, - MIPS_CP2DR30, MIPS_CP2DR31, -1, - -1, - MIPS_CP2CR0, MIPS_CP2CR1, -1, - MIPS_CP2CR2, MIPS_CP2CR3, -1, - MIPS_CP2CR4, MIPS_CP2CR5, -1, - MIPS_CP2CR6, MIPS_CP2CR7, -1, - MIPS_CP2CR8, MIPS_CP2CR9, -1, - MIPS_CP2CR10, MIPS_CP2CR11, -1, - MIPS_CP2CR12, MIPS_CP2CR13, -1, - MIPS_CP2CR14, MIPS_CP2CR15, -1, - MIPS_CP2CR16, MIPS_CP2CR17, -1, - MIPS_CP2CR18, MIPS_CP2CR19, -1, - MIPS_CP2CR20, MIPS_CP2CR21, -1, - MIPS_CP2CR22, MIPS_CP2CR23, -1, - MIPS_CP2CR24, MIPS_CP2CR25, -1, - MIPS_CP2CR26, MIPS_CP2CR27, -1, - MIPS_CP2CR28, MIPS_CP2CR29, -1, - MIPS_CP2CR30, MIPS_CP2CR31, - 0 -}; - -static UINT8 mips_win_layout[] = { - 45, 0,35,13, /* register window (top right) */ - 0, 0,44,13, /* disassembler window (left, upper) */ - 0,14,44, 8, /* memory #1 window (left, middle) */ - 45,14,35, 8, /* memory #2 window (lower) */ - 0,23,80, 1 /* command line window (bottom rows) */ -}; - -static const char *delayn[] = -{ - "pc", "at", "v0", "v1", "a0", "a1", "a2", "a3", - "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", - "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", - "t8", "t9", "k0", "k1", "gp", "sp", "fp", "ra", - "pc" -}; - -#define REGPC ( 32 ) - -typedef struct -{ - UINT32 op; - UINT32 pc; - UINT32 prevpc; - UINT32 delayv; - UINT32 delayr; - UINT32 hi; - UINT32 lo; - UINT32 r[ 32 ]; - UINT32 cp0r[ 32 ]; - PAIR cp2cr[ 32 ]; - PAIR cp2dr[ 32 ]; - int (*irq_callback)(int irqline); -} mips_cpu_context; - -static mips_cpu_context mipscpu; - -static int mips_ICount = 0; - -static UINT32 mips_mtc0_writemask[]= -{ - 0xffffffff, /* INDEX */ - 0x00000000, /* RANDOM */ - 0xffffff00, /* ENTRYLO */ - 0x00000000, - 0xffe00000, /* CONTEXT */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, /* BADVADDR */ - 0x00000000, - 0xffffffc0, /* ENTRYHI */ - 0x00000000, - 0xf27fff3f, /* SR */ - 0x00000300, /* CAUSE */ - 0x00000000, /* EPC */ - 0x00000000, /* PRID */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000 -}; - -#if 0 -void GTELOG(const char *a,...) -{ - va_list va; - char s_text[ 1024 ]; - va_start( va, a ); - vsprintf( s_text, a, va ); - va_end( va ); - logerror( "%08x: GTE: %08x %s\n", mipscpu.pc, INS_COFUN( mipscpu.op ), s_text ); -} -#else -static INLINE void GTELOG(const char *a, ...) {} -#endif - -static UINT32 getcp2dr( int n_reg ); -static void setcp2dr( int n_reg, UINT32 n_value ); -static UINT32 getcp2cr( int n_reg ); -static void setcp2cr( int n_reg, UINT32 n_value ); -static void docop2( int gteop ); -static void mips_exception( int exception ); - -void mips_stop( void ) -{ -#ifdef MAME_DEBUG - extern int debug_key_pressed; - debug_key_pressed = 1; - CALL_MAME_DEBUG; -#endif -} - -static INLINE void mips_set_cp0r( int reg, UINT32 value ) -{ - mipscpu.cp0r[ reg ] = value; - if( reg == CP0_SR || reg == CP0_CAUSE ) - { - if( ( mipscpu.cp0r[ CP0_SR ] & SR_IEC ) != 0 && ( mipscpu.cp0r[ CP0_SR ] & mipscpu.cp0r[ CP0_CAUSE ] & CAUSE_IP ) != 0 ) - { - mips_exception( EXC_INT ); - } - else if( mipscpu.delayr != REGPC && ( mipscpu.pc & ( ( ( mipscpu.cp0r[ CP0_SR ] & SR_KUC ) << 30 ) | 3 ) ) != 0 ) - { - mips_exception( EXC_ADEL ); - mips_set_cp0r( CP0_BADVADDR, mipscpu.pc ); - } - } -} - -static INLINE void mips_commit_delayed_load( void ) -{ - if( mipscpu.delayr != 0 ) - { - mipscpu.r[ mipscpu.delayr ] = mipscpu.delayv; - mipscpu.delayr = 0; - mipscpu.delayv = 0; - } -} - -static INLINE void mips_delayed_branch( UINT32 n_adr ) -{ - if( ( n_adr & ( ( ( mipscpu.cp0r[ CP0_SR ] & SR_KUC ) << 30 ) | 3 ) ) != 0 ) - { - mips_exception( EXC_ADEL ); - mips_set_cp0r( CP0_BADVADDR, n_adr ); - } - else - { - mips_commit_delayed_load(); - mipscpu.delayr = REGPC; - mipscpu.delayv = n_adr; - mipscpu.pc += 4; - } -} - -static INLINE void mips_set_pc( unsigned val ) -{ - mipscpu.pc = val; - change_pc( val ); - mipscpu.delayr = 0; - mipscpu.delayv = 0; -} - -static INLINE void mips_advance_pc( void ) -{ - if( mipscpu.delayr == REGPC ) - { - mips_set_pc( mipscpu.delayv ); - } - else - { - mips_commit_delayed_load(); - mipscpu.pc += 4; - } -} - -static INLINE void mips_load( UINT32 n_r, UINT32 n_v ) -{ - mips_advance_pc(); - if( n_r != 0 ) - { - mipscpu.r[ n_r ] = n_v; - } -} - -static INLINE void mips_delayed_load( UINT32 n_r, UINT32 n_v ) -{ - if( mipscpu.delayr == REGPC ) - { - mips_set_pc( mipscpu.delayv ); - mipscpu.delayr = n_r; - mipscpu.delayv = n_v; - } - else - { - mips_commit_delayed_load(); - mipscpu.pc += 4; - if( n_r != 0 ) - { - mipscpu.r[ n_r ] = n_v; - } - } -} - -static void mips_exception( int exception ) -{ - mips_set_cp0r( CP0_SR, ( mipscpu.cp0r[ CP0_SR ] & ~0x3f ) | ( ( mipscpu.cp0r[ CP0_SR ] << 2 ) & 0x3f ) ); - if( mipscpu.delayr == REGPC ) - { - mips_set_cp0r( CP0_EPC, mipscpu.pc - 4 ); - mips_set_cp0r( CP0_CAUSE, ( mipscpu.cp0r[ CP0_CAUSE ] & ~CAUSE_EXC ) | CAUSE_BD | ( exception << 2 ) ); - } - else - { - mips_commit_delayed_load(); - mips_set_cp0r( CP0_EPC, mipscpu.pc ); - mips_set_cp0r( CP0_CAUSE, ( mipscpu.cp0r[ CP0_CAUSE ] & ~( CAUSE_EXC | CAUSE_BD ) ) | ( exception << 2 ) ); - } - if( mipscpu.cp0r[ CP0_SR ] & SR_BEV ) - { - mips_set_pc( 0xbfc00180 ); - } - else - { - mips_set_pc( 0x80000080 ); - } -} - -void mips_init( void ) -{ -#if 0 - int cpu = cpu_getactivecpu(); - - state_save_register_UINT32( "psxcpu", cpu, "op", &mipscpu.op, 1 ); - state_save_register_UINT32( "psxcpu", cpu, "pc", &mipscpu.pc, 1 ); - state_save_register_UINT32( "psxcpu", cpu, "delayv", &mipscpu.delayv, 1 ); - state_save_register_UINT32( "psxcpu", cpu, "delayr", &mipscpu.delayr, 1 ); - state_save_register_UINT32( "psxcpu", cpu, "hi", &mipscpu.hi, 1 ); - state_save_register_UINT32( "psxcpu", cpu, "lo", &mipscpu.lo, 1 ); - state_save_register_UINT32( "psxcpu", cpu, "r", &mipscpu.r[ 0 ], 32 ); - state_save_register_UINT32( "psxcpu", cpu, "cp0r", &mipscpu.cp0r[ 0 ], 32 ); - state_save_register_UINT32( "psxcpu", cpu, "cp2cr", &mipscpu.cp2cr[ 0 ].d, 32 ); - state_save_register_UINT32( "psxcpu", cpu, "cp2dr", &mipscpu.cp2dr[ 0 ].d, 32 ); -#endif -} - -void mips_reset( void *param ) -{ - mips_set_cp0r( CP0_SR, ( mipscpu.cp0r[ CP0_SR ] & ~( SR_TS | SR_SWC | SR_KUC | SR_IEC ) ) | SR_BEV ); - mips_set_cp0r( CP0_RANDOM, 63 ); /* todo: */ - mips_set_cp0r( CP0_PRID, 0x00000200 ); /* todo: */ - mips_set_pc( 0xbfc00000 ); - mipscpu.prevpc = 0xffffffff; -} - -static void mips_exit( void ) -{ -} - -void mips_shorten_frame(void) -{ - mips_ICount = 0; -} - -void psx_hw_runcounters(void); - -int psxcpu_verbose = 0; - -int mips_execute( int cycles ) -{ - UINT32 n_res; - - mips_ICount = cycles; - do - { -// CALL_MAME_DEBUG; - -// psx_hw_runcounters(); - - mipscpu.op = cpu_readop32( mipscpu.pc ); - -#if 0 - while (mipscpu.prevpc == mipscpu.pc) - { - psx_hw_runcounters(); - mips_ICount--; - - if (mips_ICount == 0) return cycles; - } - - // if we're not in a delay slot, update - // if we're in a delay slot and the delay instruction is not NOP, update - if (( mipscpu.delayr == 0 ) || ((mipscpu.delayr != 0) && (mipscpu.op != 0))) - { - mipscpu.prevpc = mipscpu.pc; - } -#endif -#if 0 - if (1) //psxcpu_verbose) - { - printf("[%08x: %08x] [SP %08x RA %08x V0 %08x V1 %08x A0 %08x S0 %08x S1 %08x]\n", mipscpu.pc, mipscpu.op, mipscpu.r[29], mipscpu.r[31], mipscpu.r[2], mipscpu.r[3], mipscpu.r[4], mipscpu.r[ 16 ], mipscpu.r[ 17 ]); -// psxcpu_verbose--; - } -#endif - switch( INS_OP( mipscpu.op ) ) - { - case OP_SPECIAL: - switch( INS_FUNCT( mipscpu.op ) ) - { - case FUNCT_HLECALL: -// printf("HLECALL, PC = %08x\n", mipscpu.pc); - psx_bios_hle(mipscpu.pc); - break; - case FUNCT_SLL: - mips_load( INS_RD( mipscpu.op ), mipscpu.r[ INS_RT( mipscpu.op ) ] << INS_SHAMT( mipscpu.op ) ); - break; - case FUNCT_SRL: - mips_load( INS_RD( mipscpu.op ), mipscpu.r[ INS_RT( mipscpu.op ) ] >> INS_SHAMT( mipscpu.op ) ); - break; - case FUNCT_SRA: - mips_load( INS_RD( mipscpu.op ), (INT32)mipscpu.r[ INS_RT( mipscpu.op ) ] >> INS_SHAMT( mipscpu.op ) ); - break; - case FUNCT_SLLV: - mips_load( INS_RD( mipscpu.op ), mipscpu.r[ INS_RT( mipscpu.op ) ] << ( mipscpu.r[ INS_RS( mipscpu.op ) ] & 31 ) ); - break; - case FUNCT_SRLV: - mips_load( INS_RD( mipscpu.op ), mipscpu.r[ INS_RT( mipscpu.op ) ] >> ( mipscpu.r[ INS_RS( mipscpu.op ) ] & 31 ) ); - break; - case FUNCT_SRAV: - mips_load( INS_RD( mipscpu.op ), (INT32)mipscpu.r[ INS_RT( mipscpu.op ) ] >> ( mipscpu.r[ INS_RS( mipscpu.op ) ] & 31 ) ); - break; - case FUNCT_JR: - if( INS_RD( mipscpu.op ) != 0 ) - { - mips_exception( EXC_RI ); - } - else - { - mips_delayed_branch( mipscpu.r[ INS_RS( mipscpu.op ) ] ); - } - break; - case FUNCT_JALR: - n_res = mipscpu.pc + 8; - mips_delayed_branch( mipscpu.r[ INS_RS( mipscpu.op ) ] ); - if( INS_RD( mipscpu.op ) != 0 ) - { - mipscpu.r[ INS_RD( mipscpu.op ) ] = n_res; - } - break; - case FUNCT_SYSCALL: - mips_exception( EXC_SYS ); - break; - case FUNCT_BREAK: - printf("BREAK!\n"); - exit(-1); -// mips_exception( EXC_BP ); - mips_advance_pc(); - break; - case FUNCT_MFHI: - mips_load( INS_RD( mipscpu.op ), mipscpu.hi ); - break; - case FUNCT_MTHI: - if( INS_RD( mipscpu.op ) != 0 ) - { - mips_exception( EXC_RI ); - } - else - { - mips_advance_pc(); - mipscpu.hi = mipscpu.r[ INS_RS( mipscpu.op ) ]; - } - break; - case FUNCT_MFLO: - mips_load( INS_RD( mipscpu.op ), mipscpu.lo ); - break; - case FUNCT_MTLO: - if( INS_RD( mipscpu.op ) != 0 ) - { - mips_exception( EXC_RI ); - } - else - { - mips_advance_pc(); - mipscpu.lo = mipscpu.r[ INS_RS( mipscpu.op ) ]; - } - break; - case FUNCT_MULT: - if( INS_RD( mipscpu.op ) != 0 ) - { - mips_exception( EXC_RI ); - } - else - { - INT64 n_res64; - n_res64 = MUL_64_32_32( (INT32)mipscpu.r[ INS_RS( mipscpu.op ) ], (INT32)mipscpu.r[ INS_RT( mipscpu.op ) ] ); - mips_advance_pc(); - mipscpu.lo = LO32_32_64( n_res64 ); - mipscpu.hi = HI32_32_64( n_res64 ); - } - break; - case FUNCT_MULTU: - if( INS_RD( mipscpu.op ) != 0 ) - { - mips_exception( EXC_RI ); - } - else - { - UINT64 n_res64; - n_res64 = MUL_U64_U32_U32( mipscpu.r[ INS_RS( mipscpu.op ) ], mipscpu.r[ INS_RT( mipscpu.op ) ] ); - mips_advance_pc(); - mipscpu.lo = LO32_U32_U64( n_res64 ); - mipscpu.hi = HI32_U32_U64( n_res64 ); - } - break; - case FUNCT_DIV: - if( INS_RD( mipscpu.op ) != 0 ) - { - mips_exception( EXC_RI ); - } - else - { - UINT32 n_div; - UINT32 n_mod; - if( mipscpu.r[ INS_RT( mipscpu.op ) ] != 0 ) - { - n_div = (INT32)mipscpu.r[ INS_RS( mipscpu.op ) ] / (INT32)mipscpu.r[ INS_RT( mipscpu.op ) ]; - n_mod = (INT32)mipscpu.r[ INS_RS( mipscpu.op ) ] % (INT32)mipscpu.r[ INS_RT( mipscpu.op ) ]; - mips_advance_pc(); - mipscpu.lo = n_div; - mipscpu.hi = n_mod; - } - else - { - mips_advance_pc(); - } - } - break; - case FUNCT_DIVU: - if( INS_RD( mipscpu.op ) != 0 ) - { - mips_exception( EXC_RI ); - } - else - { - UINT32 n_div; - UINT32 n_mod; - if( mipscpu.r[ INS_RT( mipscpu.op ) ] != 0 ) - { - n_div = mipscpu.r[ INS_RS( mipscpu.op ) ] / mipscpu.r[ INS_RT( mipscpu.op ) ]; - n_mod = mipscpu.r[ INS_RS( mipscpu.op ) ] % mipscpu.r[ INS_RT( mipscpu.op ) ]; - mips_advance_pc(); - mipscpu.lo = n_div; - mipscpu.hi = n_mod; - } - else - { - mips_advance_pc(); - } - } - break; - case FUNCT_ADD: - { - n_res = mipscpu.r[ INS_RS( mipscpu.op ) ] + mipscpu.r[ INS_RT( mipscpu.op ) ]; - if( (INT32)( ~( mipscpu.r[ INS_RS( mipscpu.op ) ] ^ mipscpu.r[ INS_RT( mipscpu.op ) ] ) & ( mipscpu.r[ INS_RS( mipscpu.op ) ] ^ n_res ) ) < 0 ) - { - mips_exception( EXC_OVF ); - } - else - { - mips_load( INS_RD( mipscpu.op ), n_res ); - } - } - break; - case FUNCT_ADDU: - mips_load( INS_RD( mipscpu.op ), mipscpu.r[ INS_RS( mipscpu.op ) ] + mipscpu.r[ INS_RT( mipscpu.op ) ] ); - break; - case FUNCT_SUB: - n_res = mipscpu.r[ INS_RS( mipscpu.op ) ] - mipscpu.r[ INS_RT( mipscpu.op ) ]; - if( (INT32)( ( mipscpu.r[ INS_RS( mipscpu.op ) ] ^ mipscpu.r[ INS_RT( mipscpu.op ) ] ) & ( mipscpu.r[ INS_RS( mipscpu.op ) ] ^ n_res ) ) < 0 ) - { - mips_exception( EXC_OVF ); - } - else - { - mips_load( INS_RD( mipscpu.op ), n_res ); - } - break; - case FUNCT_SUBU: - mips_load( INS_RD( mipscpu.op ), mipscpu.r[ INS_RS( mipscpu.op ) ] - mipscpu.r[ INS_RT( mipscpu.op ) ] ); - break; - case FUNCT_AND: - mips_load( INS_RD( mipscpu.op ), mipscpu.r[ INS_RS( mipscpu.op ) ] & mipscpu.r[ INS_RT( mipscpu.op ) ] ); - break; - case FUNCT_OR: - mips_load( INS_RD( mipscpu.op ), mipscpu.r[ INS_RS( mipscpu.op ) ] | mipscpu.r[ INS_RT( mipscpu.op ) ] ); - break; - case FUNCT_XOR: - mips_load( INS_RD( mipscpu.op ), mipscpu.r[ INS_RS( mipscpu.op ) ] ^ mipscpu.r[ INS_RT( mipscpu.op ) ] ); - break; - case FUNCT_NOR: - mips_load( INS_RD( mipscpu.op ), ~( mipscpu.r[ INS_RS( mipscpu.op ) ] | mipscpu.r[ INS_RT( mipscpu.op ) ] ) ); - break; - case FUNCT_SLT: - mips_load( INS_RD( mipscpu.op ), (INT32)mipscpu.r[ INS_RS( mipscpu.op ) ] < (INT32)mipscpu.r[ INS_RT( mipscpu.op ) ] ); - break; - case FUNCT_SLTU: - mips_load( INS_RD( mipscpu.op ), mipscpu.r[ INS_RS( mipscpu.op ) ] < mipscpu.r[ INS_RT( mipscpu.op ) ] ); - break; - default: - mips_exception( EXC_RI ); - break; - } - break; - case OP_REGIMM: - switch( INS_RT( mipscpu.op ) ) - { - case RT_BLTZ: - if( (INT32)mipscpu.r[ INS_RS( mipscpu.op ) ] < 0 ) - { - mips_delayed_branch( mipscpu.pc + 4 + ( MIPS_WORD_EXTEND( INS_IMMEDIATE( mipscpu.op ) ) << 2 ) ); - } - else - { - mips_advance_pc(); - } - break; - case RT_BGEZ: - if( (INT32)mipscpu.r[ INS_RS( mipscpu.op ) ] >= 0 ) - { - mips_delayed_branch( mipscpu.pc + 4 + ( MIPS_WORD_EXTEND( INS_IMMEDIATE( mipscpu.op ) ) << 2 ) ); - } - else - { - mips_advance_pc(); - } - break; - case RT_BLTZAL: - n_res = mipscpu.pc + 8; - if( (INT32)mipscpu.r[ INS_RS( mipscpu.op ) ] < 0 ) - { - mips_delayed_branch( mipscpu.pc + 4 + ( MIPS_WORD_EXTEND( INS_IMMEDIATE( mipscpu.op ) ) << 2 ) ); - } - else - { - mips_advance_pc(); - } - mipscpu.r[ 31 ] = n_res; - break; - case RT_BGEZAL: - n_res = mipscpu.pc + 8; - if( (INT32)mipscpu.r[ INS_RS( mipscpu.op ) ] >= 0 ) - { - mips_delayed_branch( mipscpu.pc + 4 + ( MIPS_WORD_EXTEND( INS_IMMEDIATE( mipscpu.op ) ) << 2 ) ); - } - else - { - mips_advance_pc(); - } - mipscpu.r[ 31 ] = n_res; - break; - } - break; - case OP_J: - mips_delayed_branch( ( ( mipscpu.pc + 4 ) & 0xf0000000 ) + ( INS_TARGET( mipscpu.op ) << 2 ) ); - break; - case OP_JAL: - n_res = mipscpu.pc + 8; - mips_delayed_branch( ( ( mipscpu.pc + 4 ) & 0xf0000000 ) + ( INS_TARGET( mipscpu.op ) << 2 ) ); - mipscpu.r[ 31 ] = n_res; - break; - case OP_BEQ: - if( mipscpu.r[ INS_RS( mipscpu.op ) ] == mipscpu.r[ INS_RT( mipscpu.op ) ] ) - { - mips_delayed_branch( mipscpu.pc + 4 + ( MIPS_WORD_EXTEND( INS_IMMEDIATE( mipscpu.op ) ) << 2 ) ); - } - else - { - mips_advance_pc(); - } - break; - case OP_BNE: - if( mipscpu.r[ INS_RS( mipscpu.op ) ] != mipscpu.r[ INS_RT( mipscpu.op ) ] ) - { - mips_delayed_branch( mipscpu.pc + 4 + ( MIPS_WORD_EXTEND( INS_IMMEDIATE( mipscpu.op ) ) << 2 ) ); - } - else - { - mips_advance_pc(); - } - break; - case OP_BLEZ: - if( INS_RT( mipscpu.op ) != 0 ) - { - mips_exception( EXC_RI ); - } - else if( (INT32)mipscpu.r[ INS_RS( mipscpu.op ) ] <= 0 ) - { - mips_delayed_branch( mipscpu.pc + 4 + ( MIPS_WORD_EXTEND( INS_IMMEDIATE( mipscpu.op ) ) << 2 ) ); - } - else - { - mips_advance_pc(); - } - break; - case OP_BGTZ: - if( INS_RT( mipscpu.op ) != 0 ) - { - mips_exception( EXC_RI ); - } - else if( (INT32)mipscpu.r[ INS_RS( mipscpu.op ) ] > 0 ) - { - mips_delayed_branch( mipscpu.pc + 4 + ( MIPS_WORD_EXTEND( INS_IMMEDIATE( mipscpu.op ) ) << 2 ) ); - } - else - { - mips_advance_pc(); - } - break; - case OP_ADDI: - { - UINT32 n_imm; - n_imm = MIPS_WORD_EXTEND( INS_IMMEDIATE( mipscpu.op ) ); - n_res = mipscpu.r[ INS_RS( mipscpu.op ) ] + n_imm; - if( (INT32)( ~( mipscpu.r[ INS_RS( mipscpu.op ) ] ^ n_imm ) & ( mipscpu.r[ INS_RS( mipscpu.op ) ] ^ n_res ) ) < 0 ) - { - mips_exception( EXC_OVF ); - } - else - { - mips_load( INS_RT( mipscpu.op ), n_res ); - } - } - break; - case OP_ADDIU: - if (INS_RT( mipscpu.op ) == 0) - { - psx_iop_call(mipscpu.pc, INS_IMMEDIATE(mipscpu.op)); - mips_advance_pc(); - } - else - { - mips_load( INS_RT( mipscpu.op ), mipscpu.r[ INS_RS( mipscpu.op ) ] + MIPS_WORD_EXTEND( INS_IMMEDIATE( mipscpu.op ) ) ); - } - break; - case OP_SLTI: - mips_load( INS_RT( mipscpu.op ), (INT32)mipscpu.r[ INS_RS( mipscpu.op ) ] < MIPS_WORD_EXTEND( INS_IMMEDIATE( mipscpu.op ) ) ); - break; - case OP_SLTIU: - mips_load( INS_RT( mipscpu.op ), mipscpu.r[ INS_RS( mipscpu.op ) ] < (UINT32)MIPS_WORD_EXTEND( INS_IMMEDIATE( mipscpu.op ) ) ); - break; - case OP_ANDI: - mips_load( INS_RT( mipscpu.op ), mipscpu.r[ INS_RS( mipscpu.op ) ] & INS_IMMEDIATE( mipscpu.op ) ); - break; - case OP_ORI: - mips_load( INS_RT( mipscpu.op ), mipscpu.r[ INS_RS( mipscpu.op ) ] | INS_IMMEDIATE( mipscpu.op ) ); - break; - case OP_XORI: - mips_load( INS_RT( mipscpu.op ), mipscpu.r[ INS_RS( mipscpu.op ) ] ^ INS_IMMEDIATE( mipscpu.op ) ); - break; - case OP_LUI: - mips_load( INS_RT( mipscpu.op ), INS_IMMEDIATE( mipscpu.op ) << 16 ); - break; - case OP_COP0: - if( ( mipscpu.cp0r[ CP0_SR ] & SR_KUC ) != 0 && ( mipscpu.cp0r[ CP0_SR ] & SR_CU0 ) == 0 ) - { - mips_exception( EXC_CPU ); - mips_set_cp0r( CP0_CAUSE, ( mipscpu.cp0r[ CP0_CAUSE ] & ~CAUSE_CE ) | CAUSE_CE0 ); - } - else - { - switch( INS_RS( mipscpu.op ) ) - { - case RS_MFC: - mips_delayed_load( INS_RT( mipscpu.op ), mipscpu.cp0r[ INS_RD( mipscpu.op ) ] ); - break; - case RS_CFC: - /* todo: */ - logerror( "%08x: COP0 CFC not supported\n", mipscpu.pc ); - mips_stop(); - mips_advance_pc(); - break; - case RS_MTC: - n_res = ( mipscpu.cp0r[ INS_RD( mipscpu.op ) ] & ~mips_mtc0_writemask[ INS_RD( mipscpu.op ) ] ) | - ( mipscpu.r[ INS_RT( mipscpu.op ) ] & mips_mtc0_writemask[ INS_RD( mipscpu.op ) ] ); - mips_advance_pc(); - mips_set_cp0r( INS_RD( mipscpu.op ), n_res ); - break; - case RS_CTC: - /* todo: */ - logerror( "%08x: COP0 CTC not supported\n", mipscpu.pc ); - mips_stop(); - mips_advance_pc(); - break; - case RS_BC: - switch( INS_RT( mipscpu.op ) ) - { - case RT_BCF: - /* todo: */ - logerror( "%08x: COP0 BCF not supported\n", mipscpu.pc ); - mips_stop(); - mips_advance_pc(); - break; - case RT_BCT: - /* todo: */ - logerror( "%08x: COP0 BCT not supported\n", mipscpu.pc ); - mips_stop(); - mips_advance_pc(); - break; - default: - /* todo: */ - logerror( "%08x: COP0 unknown command %08x\n", mipscpu.pc, mipscpu.op ); - mips_stop(); - mips_advance_pc(); - break; - } - break; - default: - switch( INS_CO( mipscpu.op ) ) - { - case 1: - switch( INS_CF( mipscpu.op ) ) - { - case CF_RFE: - mips_advance_pc(); - mips_set_cp0r( CP0_SR, ( mipscpu.cp0r[ CP0_SR ] & ~0xf ) | ( ( mipscpu.cp0r[ CP0_SR ] >> 2 ) & 0xf ) ); - break; - default: - /* todo: */ - logerror( "%08x: COP0 unknown command %08x\n", mipscpu.pc, mipscpu.op ); - mips_stop(); - mips_advance_pc(); - break; - } - break; - default: - /* todo: */ - logerror( "%08x: COP0 unknown command %08x\n", mipscpu.pc, mipscpu.op ); - mips_stop(); - mips_advance_pc(); - break; - } - break; - } - } - break; - case OP_COP1: - if( ( mipscpu.cp0r[ CP0_SR ] & SR_CU1 ) == 0 ) - { - mips_exception( EXC_CPU ); - mips_set_cp0r( CP0_CAUSE, ( mipscpu.cp0r[ CP0_CAUSE ] & ~CAUSE_CE ) | CAUSE_CE1 ); - } - else - { - switch( INS_RS( mipscpu.op ) ) - { - case RS_MFC: - /* todo: */ - logerror( "%08x: COP1 BCT not supported\n", mipscpu.pc ); - mips_stop(); - mips_advance_pc(); - break; - case RS_CFC: - /* todo: */ - logerror( "%08x: COP1 CFC not supported\n", mipscpu.pc ); - mips_stop(); - mips_advance_pc(); - break; - case RS_MTC: - /* todo: */ - logerror( "%08x: COP1 MTC not supported\n", mipscpu.pc ); - mips_stop(); - mips_advance_pc(); - break; - case RS_CTC: - /* todo: */ - logerror( "%08x: COP1 CTC not supported\n", mipscpu.pc ); - mips_stop(); - mips_advance_pc(); - break; - case RS_BC: - switch( INS_RT( mipscpu.op ) ) - { - case RT_BCF: - /* todo: */ - logerror( "%08x: COP1 BCF not supported\n", mipscpu.pc ); - mips_stop(); - mips_advance_pc(); - break; - case RT_BCT: - /* todo: */ - logerror( "%08x: COP1 BCT not supported\n", mipscpu.pc ); - mips_stop(); - mips_advance_pc(); - break; - default: - /* todo: */ - logerror( "%08x: COP1 unknown command %08x\n", mipscpu.pc, mipscpu.op ); - mips_stop(); - mips_advance_pc(); - break; - } - break; - default: - switch( INS_CO( mipscpu.op ) ) - { - case 1: - /* todo: */ - logerror( "%08x: COP1 unknown command %08x\n", mipscpu.pc, mipscpu.op ); - mips_stop(); - mips_advance_pc(); - break; - default: - /* todo: */ - logerror( "%08x: COP1 unknown command %08x\n", mipscpu.pc, mipscpu.op ); - mips_stop(); - mips_advance_pc(); - break; - } - break; - } - } - break; - case OP_COP2: - if( ( mipscpu.cp0r[ CP0_SR ] & SR_CU2 ) == 0 ) - { - mips_exception( EXC_CPU ); - mips_set_cp0r( CP0_CAUSE, ( mipscpu.cp0r[ CP0_CAUSE ] & ~CAUSE_CE ) | CAUSE_CE2 ); - } - else - { - switch( INS_RS( mipscpu.op ) ) - { - case RS_MFC: - mips_delayed_load( INS_RT( mipscpu.op ), getcp2dr( INS_RD( mipscpu.op ) ) ); - break; - case RS_CFC: - mips_delayed_load( INS_RT( mipscpu.op ), getcp2cr( INS_RD( mipscpu.op ) ) ); - break; - case RS_MTC: - setcp2dr( INS_RD( mipscpu.op ), mipscpu.r[ INS_RT( mipscpu.op ) ] ); - mips_advance_pc(); - break; - case RS_CTC: - setcp2cr( INS_RD( mipscpu.op ), mipscpu.r[ INS_RT( mipscpu.op ) ] ); - mips_advance_pc(); - break; - case RS_BC: - switch( INS_RT( mipscpu.op ) ) - { - case RT_BCF: - /* todo: */ - logerror( "%08x: COP2 BCF not supported\n", mipscpu.pc ); - mips_stop(); - mips_advance_pc(); - break; - case RT_BCT: - /* todo: */ - logerror( "%08x: COP2 BCT not supported\n", mipscpu.pc ); - mips_stop(); - mips_advance_pc(); - break; - default: - /* todo: */ - logerror( "%08x: COP2 unknown command %08x\n", mipscpu.pc, mipscpu.op ); - mips_stop(); - mips_advance_pc(); - break; - } - break; - default: - switch( INS_CO( mipscpu.op ) ) - { - case 1: - docop2( INS_COFUN( mipscpu.op ) ); - mips_advance_pc(); - break; - default: - /* todo: */ - logerror( "%08x: COP2 unknown command %08x\n", mipscpu.pc, mipscpu.op ); - mips_stop(); - mips_advance_pc(); - break; - } - break; - } - } - break; - case OP_LB: - if( ( mipscpu.cp0r[ CP0_SR ] & SR_ISC ) != 0 ) - { - /* todo: */ - logerror( "%08x: LB SR_ISC not supported\n", mipscpu.pc ); - mips_stop(); - mips_advance_pc(); - } - else if( ( mipscpu.cp0r[ CP0_SR ] & ( SR_RE | SR_KUC ) ) == ( SR_RE | SR_KUC ) ) - { - UINT32 n_adr; - n_adr = mipscpu.r[ INS_RS( mipscpu.op ) ] + MIPS_WORD_EXTEND( INS_IMMEDIATE( mipscpu.op ) ); - if( ( n_adr & ( ( mipscpu.cp0r[ CP0_SR ] & SR_KUC ) << 30 ) ) != 0 ) - { - mips_exception( EXC_ADEL ); - mips_set_cp0r( CP0_BADVADDR, n_adr ); - } - else - { - mips_delayed_load( INS_RT( mipscpu.op ), MIPS_BYTE_EXTEND( program_read_byte_32le( n_adr ^ 3 ) ) ); - } - } - else - { - UINT32 n_adr; - n_adr = mipscpu.r[ INS_RS( mipscpu.op ) ] + MIPS_WORD_EXTEND( INS_IMMEDIATE( mipscpu.op ) ); - if( ( n_adr & ( ( mipscpu.cp0r[ CP0_SR ] & SR_KUC ) << 30 ) ) != 0 ) - { - mips_exception( EXC_ADEL ); - mips_set_cp0r( CP0_BADVADDR, n_adr ); - } - else - { - mips_delayed_load( INS_RT( mipscpu.op ), MIPS_BYTE_EXTEND( program_read_byte_32le( n_adr ) ) ); - } - } - break; - case OP_LH: - if( ( mipscpu.cp0r[ CP0_SR ] & SR_ISC ) != 0 ) - { - /* todo: */ - logerror( "%08x: LH SR_ISC not supported\n", mipscpu.pc ); - mips_stop(); - mips_advance_pc(); - } - else if( ( mipscpu.cp0r[ CP0_SR ] & ( SR_RE | SR_KUC ) ) == ( SR_RE | SR_KUC ) ) - { - UINT32 n_adr; - n_adr = mipscpu.r[ INS_RS( mipscpu.op ) ] + MIPS_WORD_EXTEND( INS_IMMEDIATE( mipscpu.op ) ); - if( ( n_adr & ( ( ( mipscpu.cp0r[ CP0_SR ] & SR_KUC ) << 30 ) | 1 ) ) != 0 ) - { - mips_exception( EXC_ADEL ); - mips_set_cp0r( CP0_BADVADDR, n_adr ); - } - else - { - mips_delayed_load( INS_RT( mipscpu.op ), MIPS_WORD_EXTEND( program_read_word_32le( n_adr ^ 2 ) ) ); - } - } - else - { - UINT32 n_adr; - n_adr = mipscpu.r[ INS_RS( mipscpu.op ) ] + MIPS_WORD_EXTEND( INS_IMMEDIATE( mipscpu.op ) ); - if( ( n_adr & ( ( ( mipscpu.cp0r[ CP0_SR ] & SR_KUC ) << 30 ) | 1 ) ) != 0 ) - { - mips_exception( EXC_ADEL ); - mips_set_cp0r( CP0_BADVADDR, n_adr ); - } - else - { - mips_delayed_load( INS_RT( mipscpu.op ), MIPS_WORD_EXTEND( program_read_word_32le( n_adr ) ) ); - } - } - break; - case OP_LWL: - if( ( mipscpu.cp0r[ CP0_SR ] & SR_ISC ) != 0 ) - { - /* todo: */ - logerror( "%08x: LWL SR_ISC not supported\n", mipscpu.pc ); - mips_stop(); - mips_advance_pc(); - } - else if( ( mipscpu.cp0r[ CP0_SR ] & ( SR_RE | SR_KUC ) ) == ( SR_RE | SR_KUC ) ) - { - UINT32 n_adr; - n_adr = mipscpu.r[ INS_RS( mipscpu.op ) ] + MIPS_WORD_EXTEND( INS_IMMEDIATE( mipscpu.op ) ); - if( ( n_adr & ( ( mipscpu.cp0r[ CP0_SR ] & SR_KUC ) << 30 ) ) != 0 ) - { - mips_exception( EXC_ADEL ); - mips_set_cp0r( CP0_BADVADDR, n_adr ); - } - else - { - switch( n_adr & 3 ) - { - case 0: - n_res = ( mipscpu.r[ INS_RT( mipscpu.op ) ] & 0x00ffffff ) | ( (UINT32)program_read_byte_32le( n_adr + 3 ) << 24 ); - break; - case 1: - n_res = ( mipscpu.r[ INS_RT( mipscpu.op ) ] & 0x0000ffff ) | ( (UINT32)program_read_word_32le( n_adr + 1 ) << 16 ); - break; - case 2: - n_res = ( mipscpu.r[ INS_RT( mipscpu.op ) ] & 0x000000ff ) | ( (UINT32)program_read_byte_32le( n_adr - 1 ) << 8 ) | ( (UINT32)program_read_word_32le( n_adr ) << 16 ); - break; - default: - n_res = program_read_dword_32le( n_adr - 3 ); - break; - } - mips_delayed_load( INS_RT( mipscpu.op ), n_res ); - } - } - else - { - UINT32 n_adr; - n_adr = mipscpu.r[ INS_RS( mipscpu.op ) ] + MIPS_WORD_EXTEND( INS_IMMEDIATE( mipscpu.op ) ); - if( ( n_adr & ( ( mipscpu.cp0r[ CP0_SR ] & SR_KUC ) << 30 ) ) != 0 ) - { - mips_exception( EXC_ADEL ); - mips_set_cp0r( CP0_BADVADDR, n_adr ); - } - else - { - switch( n_adr & 3 ) - { - case 0: - n_res = ( mipscpu.r[ INS_RT( mipscpu.op ) ] & 0x00ffffff ) | ( (UINT32)program_read_byte_32le( n_adr ) << 24 ); - break; - case 1: - n_res = ( mipscpu.r[ INS_RT( mipscpu.op ) ] & 0x0000ffff ) | ( (UINT32)program_read_word_32le( n_adr - 1 ) << 16 ); - break; - case 2: - n_res = ( mipscpu.r[ INS_RT( mipscpu.op ) ] & 0x000000ff ) | ( (UINT32)program_read_word_32le( n_adr - 2 ) << 8 ) | ( (UINT32)program_read_byte_32le( n_adr ) << 24 ); - break; - default: - n_res = program_read_dword_32le( n_adr - 3 ); - break; - } - mips_delayed_load( INS_RT( mipscpu.op ), n_res ); - } - } - break; - case OP_LW: - if( ( mipscpu.cp0r[ CP0_SR ] & SR_ISC ) != 0 ) - { - /* todo: */ - logerror( "%08x: LW SR_ISC not supported\n", mipscpu.pc ); - mips_stop(); - mips_advance_pc(); - } - else - { - UINT32 n_adr; - n_adr = mipscpu.r[ INS_RS( mipscpu.op ) ] + MIPS_WORD_EXTEND( INS_IMMEDIATE( mipscpu.op ) ); -#if 0 - if( ( n_adr & ( ( ( mipscpu.cp0r[ CP0_SR ] & SR_KUC ) << 30 ) | 3 ) ) != 0 ) - { - printf("ADEL\n"); - mips_exception( EXC_ADEL ); - mips_set_cp0r( CP0_BADVADDR, n_adr ); - } - else -#endif - { - mips_delayed_load( INS_RT( mipscpu.op ), program_read_dword_32le( n_adr ) ); - } - } - break; - case OP_LBU: - if( ( mipscpu.cp0r[ CP0_SR ] & SR_ISC ) != 0 ) - { - /* todo: */ - logerror( "%08x: LBU SR_ISC not supported\n", mipscpu.pc ); - mips_stop(); - mips_advance_pc(); - } - else if( ( mipscpu.cp0r[ CP0_SR ] & ( SR_RE | SR_KUC ) ) == ( SR_RE | SR_KUC ) ) - { - UINT32 n_adr; - n_adr = mipscpu.r[ INS_RS( mipscpu.op ) ] + MIPS_WORD_EXTEND( INS_IMMEDIATE( mipscpu.op ) ); - if( ( n_adr & ( ( mipscpu.cp0r[ CP0_SR ] & SR_KUC ) << 30 ) ) != 0 ) - { - mips_exception( EXC_ADEL ); - mips_set_cp0r( CP0_BADVADDR, n_adr ); - } - else - { - mips_delayed_load( INS_RT( mipscpu.op ), program_read_byte_32le( n_adr ^ 3 ) ); - } - } - else - { - UINT32 n_adr; - n_adr = mipscpu.r[ INS_RS( mipscpu.op ) ] + MIPS_WORD_EXTEND( INS_IMMEDIATE( mipscpu.op ) ); - if( ( n_adr & ( ( mipscpu.cp0r[ CP0_SR ] & SR_KUC ) << 30 ) ) != 0 ) - { - mips_exception( EXC_ADEL ); - mips_set_cp0r( CP0_BADVADDR, n_adr ); - } - else - { - mips_delayed_load( INS_RT( mipscpu.op ), program_read_byte_32le( n_adr ) ); - } - } - break; - case OP_LHU: - if( ( mipscpu.cp0r[ CP0_SR ] & SR_ISC ) != 0 ) - { - /* todo: */ - logerror( "%08x: LHU SR_ISC not supported\n", mipscpu.pc ); - mips_stop(); - mips_advance_pc(); - } - else if( ( mipscpu.cp0r[ CP0_SR ] & ( SR_RE | SR_KUC ) ) == ( SR_RE | SR_KUC ) ) - { - UINT32 n_adr; - n_adr = mipscpu.r[ INS_RS( mipscpu.op ) ] + MIPS_WORD_EXTEND( INS_IMMEDIATE( mipscpu.op ) ); - if( ( n_adr & ( ( ( mipscpu.cp0r[ CP0_SR ] & SR_KUC ) << 30 ) | 1 ) ) != 0 ) - { - mips_exception( EXC_ADEL ); - mips_set_cp0r( CP0_BADVADDR, n_adr ); - } - else - { - mips_delayed_load( INS_RT( mipscpu.op ), program_read_word_32le( n_adr ^ 2 ) ); - } - } - else - { - UINT32 n_adr; - n_adr = mipscpu.r[ INS_RS( mipscpu.op ) ] + MIPS_WORD_EXTEND( INS_IMMEDIATE( mipscpu.op ) ); - if( ( n_adr & ( ( ( mipscpu.cp0r[ CP0_SR ] & SR_KUC ) << 30 ) | 1 ) ) != 0 ) - { - mips_exception( EXC_ADEL ); - mips_set_cp0r( CP0_BADVADDR, n_adr ); - } - else - { - mips_delayed_load( INS_RT( mipscpu.op ), program_read_word_32le( n_adr ) ); - } - } - break; - case OP_LWR: - if( ( mipscpu.cp0r[ CP0_SR ] & SR_ISC ) != 0 ) - { - /* todo: */ - logerror( "%08x: LWR SR_ISC not supported\n", mipscpu.pc ); - mips_stop(); - mips_advance_pc(); - } - else if( ( mipscpu.cp0r[ CP0_SR ] & ( SR_RE | SR_KUC ) ) == ( SR_RE | SR_KUC ) ) - { - UINT32 n_adr; - n_adr = mipscpu.r[ INS_RS( mipscpu.op ) ] + MIPS_WORD_EXTEND( INS_IMMEDIATE( mipscpu.op ) ); - if( ( n_adr & ( ( mipscpu.cp0r[ CP0_SR ] & SR_KUC ) << 30 ) ) != 0 ) - { - mips_exception( EXC_ADEL ); - mips_set_cp0r( CP0_BADVADDR, n_adr ); - } - else - { - switch( n_adr & 3 ) - { - case 3: - n_res = ( mipscpu.r[ INS_RT( mipscpu.op ) ] & 0xffffff00 ) | program_read_byte_32le( n_adr - 3 ); - break; - case 2: - n_res = ( mipscpu.r[ INS_RT( mipscpu.op ) ] & 0xffff0000 ) | program_read_word_32le( n_adr - 2 ); - break; - case 1: - n_res = ( mipscpu.r[ INS_RT( mipscpu.op ) ] & 0xff000000 ) | program_read_word_32le( n_adr - 1 ) | ( (UINT32)program_read_byte_32le( n_adr + 1 ) << 16 ); - break; - default: - n_res = program_read_dword_32le( n_adr ); - break; - } - mips_delayed_load( INS_RT( mipscpu.op ), n_res ); - } - } - else - { - UINT32 n_adr; - n_adr = mipscpu.r[ INS_RS( mipscpu.op ) ] + MIPS_WORD_EXTEND( INS_IMMEDIATE( mipscpu.op ) ); - if( ( n_adr & ( ( mipscpu.cp0r[ CP0_SR ] & SR_KUC ) << 30 ) ) != 0 ) - { - mips_exception( EXC_ADEL ); - mips_set_cp0r( CP0_BADVADDR, n_adr ); - } - else - { - switch( n_adr & 3 ) - { - case 3: - n_res = ( mipscpu.r[ INS_RT( mipscpu.op ) ] & 0xffffff00 ) | program_read_byte_32le( n_adr ); - break; - case 2: - n_res = ( mipscpu.r[ INS_RT( mipscpu.op ) ] & 0xffff0000 ) | program_read_word_32le( n_adr ); - break; - case 1: - n_res = ( mipscpu.r[ INS_RT( mipscpu.op ) ] & 0xff000000 ) | program_read_byte_32le( n_adr ) | ( (UINT32)program_read_word_32le( n_adr + 1 ) << 8 ); - break; - default: - n_res = program_read_dword_32le( n_adr ); - break; - } - mips_delayed_load( INS_RT( mipscpu.op ), n_res ); - } - } - break; - case OP_SB: - if( ( mipscpu.cp0r[ CP0_SR ] & SR_ISC ) != 0 ) - { - /* todo: */ - logerror( "%08x: SB SR_ISC not supported\n", mipscpu.pc ); - mips_stop(); - mips_advance_pc(); - } - else if( ( mipscpu.cp0r[ CP0_SR ] & ( SR_RE | SR_KUC ) ) == ( SR_RE | SR_KUC ) ) - { - UINT32 n_adr; - n_adr = mipscpu.r[ INS_RS( mipscpu.op ) ] + MIPS_WORD_EXTEND( INS_IMMEDIATE( mipscpu.op ) ); - if( ( n_adr & ( ( mipscpu.cp0r[ CP0_SR ] & SR_KUC ) << 30 ) ) != 0 ) - { - mips_exception( EXC_ADES ); - mips_set_cp0r( CP0_BADVADDR, n_adr ); - } - else - { - program_write_byte_32le( n_adr ^ 3, mipscpu.r[ INS_RT( mipscpu.op ) ] ); - mips_advance_pc(); - } - } - else - { - UINT32 n_adr; - n_adr = mipscpu.r[ INS_RS( mipscpu.op ) ] + MIPS_WORD_EXTEND( INS_IMMEDIATE( mipscpu.op ) ); - if( ( n_adr & ( ( mipscpu.cp0r[ CP0_SR ] & SR_KUC ) << 30 ) ) != 0 ) - { - mips_exception( EXC_ADES ); - mips_set_cp0r( CP0_BADVADDR, n_adr ); - } - else - { - program_write_byte_32le( n_adr, mipscpu.r[ INS_RT( mipscpu.op ) ] ); - mips_advance_pc(); - } - } - break; - case OP_SH: - if( ( mipscpu.cp0r[ CP0_SR ] & SR_ISC ) != 0 ) - { - /* todo: */ - logerror( "%08x: SH SR_ISC not supported\n", mipscpu.pc ); - mips_stop(); - mips_advance_pc(); - } - else if( ( mipscpu.cp0r[ CP0_SR ] & ( SR_RE | SR_KUC ) ) == ( SR_RE | SR_KUC ) ) - { - UINT32 n_adr; - n_adr = mipscpu.r[ INS_RS( mipscpu.op ) ] + MIPS_WORD_EXTEND( INS_IMMEDIATE( mipscpu.op ) ); - if( ( n_adr & ( ( ( mipscpu.cp0r[ CP0_SR ] & SR_KUC ) << 30 ) | 1 ) ) != 0 ) - { - mips_exception( EXC_ADES ); - mips_set_cp0r( CP0_BADVADDR, n_adr ); - } - else - { - program_write_word_32le( n_adr ^ 2, mipscpu.r[ INS_RT( mipscpu.op ) ] ); - mips_advance_pc(); - } - } - else - { - UINT32 n_adr; - n_adr = mipscpu.r[ INS_RS( mipscpu.op ) ] + MIPS_WORD_EXTEND( INS_IMMEDIATE( mipscpu.op ) ); - if( ( n_adr & ( ( ( mipscpu.cp0r[ CP0_SR ] & SR_KUC ) << 30 ) | 1 ) ) != 0 ) - { - mips_exception( EXC_ADES ); - mips_set_cp0r( CP0_BADVADDR, n_adr ); - } - else - { - program_write_word_32le( n_adr, mipscpu.r[ INS_RT( mipscpu.op ) ] ); - mips_advance_pc(); - } - } - break; - case OP_SWL: - if( ( mipscpu.cp0r[ CP0_SR ] & SR_ISC ) != 0 ) - { - /* todo: */ - printf("SR_ISC not supported\n"); - logerror( "%08x: SWL SR_ISC not supported\n", mipscpu.pc ); - mips_stop(); - mips_advance_pc(); - } - else if( ( mipscpu.cp0r[ CP0_SR ] & ( SR_RE | SR_KUC ) ) == ( SR_RE | SR_KUC ) ) - { - UINT32 n_adr; - n_adr = mipscpu.r[ INS_RS( mipscpu.op ) ] + MIPS_WORD_EXTEND( INS_IMMEDIATE( mipscpu.op ) ); - if( ( n_adr & ( ( mipscpu.cp0r[ CP0_SR ] & SR_KUC ) << 30 ) ) != 0 ) - { - printf("permission violation?\n"); - mips_exception( EXC_ADES ); - mips_set_cp0r( CP0_BADVADDR, n_adr ); - } - else - { - switch( n_adr & 3 ) - { - case 0: - program_write_byte_32le( n_adr + 3, mipscpu.r[ INS_RT( mipscpu.op ) ] >> 24 ); - break; - case 1: - program_write_word_32le( n_adr + 1, mipscpu.r[ INS_RT( mipscpu.op ) ] >> 16 ); - break; - case 2: - program_write_byte_32le( n_adr - 1, mipscpu.r[ INS_RT( mipscpu.op ) ] >> 8 ); - program_write_word_32le( n_adr, mipscpu.r[ INS_RT( mipscpu.op ) ] >> 16 ); - break; - case 3: - program_write_dword_32le( n_adr - 3, mipscpu.r[ INS_RT( mipscpu.op ) ] ); - break; - } - mips_advance_pc(); - } - } - else - { - UINT32 n_adr; - n_adr = mipscpu.r[ INS_RS( mipscpu.op ) ] + MIPS_WORD_EXTEND( INS_IMMEDIATE( mipscpu.op ) ); - if( ( n_adr & ( ( mipscpu.cp0r[ CP0_SR ] & SR_KUC ) << 30 ) ) != 0 ) - { - printf("permission violation 2\n"); - mips_exception( EXC_ADES ); - mips_set_cp0r( CP0_BADVADDR, n_adr ); - } - else - { - switch( n_adr & 3 ) - { - case 0: - program_write_byte_32le( n_adr, mipscpu.r[ INS_RT( mipscpu.op ) ] >> 24 ); - break; - case 1: - program_write_word_32le( n_adr - 1, mipscpu.r[ INS_RT( mipscpu.op ) ] >> 16 ); - break; - case 2: - program_write_word_32le( n_adr - 2, mipscpu.r[ INS_RT( mipscpu.op ) ] >> 8 ); - program_write_byte_32le( n_adr, mipscpu.r[ INS_RT( mipscpu.op ) ] >> 24 ); - break; - case 3: - program_write_dword_32le( n_adr - 3, mipscpu.r[ INS_RT( mipscpu.op ) ] ); - break; - } - mips_advance_pc(); - } - } - break; - case OP_SW: - if( ( mipscpu.cp0r[ CP0_SR ] & SR_ISC ) != 0 ) - { - /* todo: */ -/* used by bootstrap - logerror( "%08x: SW SR_ISC not supported\n", mipscpu.pc ); - mips_stop(); -*/ - mips_advance_pc(); - } - else - { - UINT32 n_adr; - n_adr = mipscpu.r[ INS_RS( mipscpu.op ) ] + MIPS_WORD_EXTEND( INS_IMMEDIATE( mipscpu.op ) ); - if(0) // ( n_adr & ( ( ( mipscpu.cp0r[ CP0_SR ] & SR_KUC ) << 30 ) | 3 ) ) != 0 ) - { - mips_exception( EXC_ADES ); - mips_set_cp0r( CP0_BADVADDR, n_adr ); - } - else - { - program_write_dword_32le( n_adr, mipscpu.r[ INS_RT( mipscpu.op ) ] ); - mips_advance_pc(); - } - } - break; - case OP_SWR: - if( ( mipscpu.cp0r[ CP0_SR ] & SR_ISC ) != 0 ) - { - /* todo: */ - logerror( "%08x: SWR SR_ISC not supported\n", mipscpu.pc ); - mips_stop(); - mips_advance_pc(); - } - else if( ( mipscpu.cp0r[ CP0_SR ] & ( SR_RE | SR_KUC ) ) == ( SR_RE | SR_KUC ) ) - { - UINT32 n_adr; - n_adr = mipscpu.r[ INS_RS( mipscpu.op ) ] + MIPS_WORD_EXTEND( INS_IMMEDIATE( mipscpu.op ) ); - if( ( n_adr & ( ( mipscpu.cp0r[ CP0_SR ] & SR_KUC ) << 30 ) ) != 0 ) - { - mips_exception( EXC_ADES ); - mips_set_cp0r( CP0_BADVADDR, n_adr ); - } - else - { - switch( n_adr & 3 ) - { - case 0: - program_write_dword_32le( n_adr, mipscpu.r[ INS_RT( mipscpu.op ) ] ); - break; - case 1: - program_write_word_32le( n_adr - 1, mipscpu.r[ INS_RT( mipscpu.op ) ] ); - program_write_byte_32le( n_adr + 1, mipscpu.r[ INS_RT( mipscpu.op ) ] >> 16 ); - break; - case 2: - program_write_word_32le( n_adr - 2, mipscpu.r[ INS_RT( mipscpu.op ) ] ); - break; - case 3: - program_write_byte_32le( n_adr - 3, mipscpu.r[ INS_RT( mipscpu.op ) ] ); - break; - } - mips_advance_pc(); - } - } - else - { - UINT32 n_adr; - n_adr = mipscpu.r[ INS_RS( mipscpu.op ) ] + MIPS_WORD_EXTEND( INS_IMMEDIATE( mipscpu.op ) ); - if( ( n_adr & ( ( mipscpu.cp0r[ CP0_SR ] & SR_KUC ) << 30 ) ) != 0 ) - { - mips_exception( EXC_ADES ); - mips_set_cp0r( CP0_BADVADDR, n_adr ); - } - else - { - switch( n_adr & 3 ) - { - case 0: - program_write_dword_32le( n_adr, mipscpu.r[ INS_RT( mipscpu.op ) ] ); - break; - case 1: - program_write_byte_32le( n_adr, mipscpu.r[ INS_RT( mipscpu.op ) ] ); - program_write_word_32le( n_adr + 1, mipscpu.r[ INS_RT( mipscpu.op ) ] >> 8 ); - break; - case 2: - program_write_word_32le( n_adr, mipscpu.r[ INS_RT( mipscpu.op ) ] ); - break; - case 3: - program_write_byte_32le( n_adr, mipscpu.r[ INS_RT( mipscpu.op ) ] ); - break; - } - mips_advance_pc(); - } - } - break; - case OP_LWC1: - /* todo: */ - logerror( "%08x: COP1 LWC not supported\n", mipscpu.pc ); - mips_stop(); - mips_advance_pc(); - break; - case OP_LWC2: - if( ( mipscpu.cp0r[ CP0_SR ] & SR_CU2 ) == 0 ) - { - mips_exception( EXC_CPU ); - mips_set_cp0r( CP0_CAUSE, ( mipscpu.cp0r[ CP0_CAUSE ] & ~CAUSE_CE ) | CAUSE_CE2 ); - } - else if( ( mipscpu.cp0r[ CP0_SR ] & SR_ISC ) != 0 ) - { - /* todo: */ - logerror( "%08x: LWC2 SR_ISC not supported\n", mipscpu.pc ); - mips_stop(); - mips_advance_pc(); - } - else - { - UINT32 n_adr; - n_adr = mipscpu.r[ INS_RS( mipscpu.op ) ] + MIPS_WORD_EXTEND( INS_IMMEDIATE( mipscpu.op ) ); - if( ( n_adr & ( ( ( mipscpu.cp0r[ CP0_SR ] & SR_KUC ) << 30 ) | 3 ) ) != 0 ) - { - mips_exception( EXC_ADEL ); - mips_set_cp0r( CP0_BADVADDR, n_adr ); - } - else - { - /* todo: delay? */ - setcp2dr( INS_RT( mipscpu.op ), program_read_dword_32le( n_adr ) ); - mips_advance_pc(); - } - } - break; - case OP_SWC1: - /* todo: */ - logerror( "%08x: COP1 SWC not supported\n", mipscpu.pc ); - mips_stop(); - mips_advance_pc(); - break; - case OP_SWC2: - if( ( mipscpu.cp0r[ CP0_SR ] & SR_CU2 ) == 0 ) - { - mips_exception( EXC_CPU ); - mips_set_cp0r( CP0_CAUSE, ( mipscpu.cp0r[ CP0_CAUSE ] & ~CAUSE_CE ) | CAUSE_CE2 ); - } - else if( ( mipscpu.cp0r[ CP0_SR ] & SR_ISC ) != 0 ) - { - /* todo: */ - logerror( "%08x: SWC2 SR_ISC not supported\n", mipscpu.pc ); - mips_stop(); - mips_advance_pc(); - } - else - { - UINT32 n_adr; - n_adr = mipscpu.r[ INS_RS( mipscpu.op ) ] + MIPS_WORD_EXTEND( INS_IMMEDIATE( mipscpu.op ) ); - if( ( n_adr & ( ( ( mipscpu.cp0r[ CP0_SR ] & SR_KUC ) << 30 ) | 3 ) ) != 0 ) - { - mips_exception( EXC_ADES ); - mips_set_cp0r( CP0_BADVADDR, n_adr ); - } - else - { - program_write_dword_32le( n_adr, getcp2dr( INS_RT( mipscpu.op ) ) ); - mips_advance_pc(); - } - } - break; - default: -// printf( "%08x: unknown opcode %08x (prev %08x, RA %08x)\n", mipscpu.pc, mipscpu.op, mipscpu.prevpc, mipscpu.r[31] ); -// mips_stop(); -// mips_exception( EXC_RI ); - break; - } -skipinterp: - mips_ICount--; - } while( mips_ICount > 0 ); - - return cycles - mips_ICount; -} - -static void mips_get_context( void *dst ) -{ - if( dst ) - { - *(mips_cpu_context *)dst = mipscpu; - } -} - -static void mips_set_context( void *src ) -{ - if( src ) - { - mipscpu = *(mips_cpu_context *)src; - change_pc( mipscpu.pc ); - } -} - -static void set_irq_line( int irqline, int state ) -{ - UINT32 ip; - - switch( irqline ) - { - case MIPS_IRQ0: - ip = CAUSE_IP2; - break; - case MIPS_IRQ1: - ip = CAUSE_IP3; - break; - case MIPS_IRQ2: - ip = CAUSE_IP4; - break; - case MIPS_IRQ3: - ip = CAUSE_IP5; - break; - case MIPS_IRQ4: - ip = CAUSE_IP6; - break; - case MIPS_IRQ5: - ip = CAUSE_IP7; - break; - default: - return; - } - - switch( state ) - { - case CLEAR_LINE: - mips_set_cp0r( CP0_CAUSE, mipscpu.cp0r[ CP0_CAUSE ] & ~ip ); - break; - case ASSERT_LINE: - mips_set_cp0r( CP0_CAUSE, mipscpu.cp0r[ CP0_CAUSE ] |= ip ); - if( mipscpu.irq_callback ) - { - /* HOLD_LINE interrupts are not supported by the architecture. - By acknowledging the interupt here they are treated like PULSE_LINE - interrupts, so if the interrupt isn't enabled it will be ignored. - There is also a problem with PULSE_LINE interrupts as the interrupt - pending bits aren't latched the emulated code won't know what caused - the interrupt. */ - (*mipscpu.irq_callback)( irqline ); - } - break; - } -} - -/**************************************************************************** - * Return a formatted string for a register - ****************************************************************************/ - -offs_t mips_dasm( char *buffer, offs_t pc ) -{ - offs_t ret; - change_pc( pc ); -#ifdef MAME_DEBUG - ret = DasmMIPS( buffer, pc ); -#else - sprintf( buffer, "$%08x", cpu_readop32( pc ) ); - ret = 4; -#endif - change_pc( mipscpu.pc ); - return ret; -} - -/* preliminary gte code */ - -#define VXY0 ( mipscpu.cp2dr[ 0 ].d ) -#define VX0 ( mipscpu.cp2dr[ 0 ].w.l ) -#define VY0 ( mipscpu.cp2dr[ 0 ].w.h ) -#define VZ0 ( mipscpu.cp2dr[ 1 ].w.l ) -#define VXY1 ( mipscpu.cp2dr[ 2 ].d ) -#define VX1 ( mipscpu.cp2dr[ 2 ].w.l ) -#define VY1 ( mipscpu.cp2dr[ 2 ].w.h ) -#define VZ1 ( mipscpu.cp2dr[ 3 ].w.l ) -#define VXY2 ( mipscpu.cp2dr[ 4 ].d ) -#define VX2 ( mipscpu.cp2dr[ 4 ].w.l ) -#define VY2 ( mipscpu.cp2dr[ 4 ].w.h ) -#define VZ2 ( mipscpu.cp2dr[ 5 ].w.l ) -#define RGB ( mipscpu.cp2dr[ 6 ].d ) -#define R ( mipscpu.cp2dr[ 6 ].b.l ) -#define G ( mipscpu.cp2dr[ 6 ].b.h ) -#define B ( mipscpu.cp2dr[ 6 ].b.h2 ) -#define CODE ( mipscpu.cp2dr[ 6 ].b.h3 ) -#define OTZ ( mipscpu.cp2dr[ 7 ].w.l ) -#define IR0 ( mipscpu.cp2dr[ 8 ].d ) -#define IR1 ( mipscpu.cp2dr[ 9 ].d ) -#define IR2 ( mipscpu.cp2dr[ 10 ].d ) -#define IR3 ( mipscpu.cp2dr[ 11 ].d ) -#define SXY0 ( mipscpu.cp2dr[ 12 ].d ) -#define SX0 ( mipscpu.cp2dr[ 12 ].w.l ) -#define SY0 ( mipscpu.cp2dr[ 12 ].w.h ) -#define SXY1 ( mipscpu.cp2dr[ 13 ].d ) -#define SX1 ( mipscpu.cp2dr[ 13 ].w.l ) -#define SY1 ( mipscpu.cp2dr[ 13 ].w.h ) -#define SXY2 ( mipscpu.cp2dr[ 14 ].d ) -#define SX2 ( mipscpu.cp2dr[ 14 ].w.l ) -#define SY2 ( mipscpu.cp2dr[ 14 ].w.h ) -#define SXYP ( mipscpu.cp2dr[ 15 ].d ) -#define SXP ( mipscpu.cp2dr[ 15 ].w.l ) -#define SYP ( mipscpu.cp2dr[ 15 ].w.h ) -#define SZ0 ( mipscpu.cp2dr[ 16 ].w.l ) -#define SZ1 ( mipscpu.cp2dr[ 17 ].w.l ) -#define SZ2 ( mipscpu.cp2dr[ 18 ].w.l ) -#define SZ3 ( mipscpu.cp2dr[ 19 ].w.l ) -#define RGB0 ( mipscpu.cp2dr[ 20 ].d ) -#define R0 ( mipscpu.cp2dr[ 20 ].b.l ) -#define G0 ( mipscpu.cp2dr[ 20 ].b.h ) -#define B0 ( mipscpu.cp2dr[ 20 ].b.h2 ) -#define CD0 ( mipscpu.cp2dr[ 20 ].b.h3 ) -#define RGB1 ( mipscpu.cp2dr[ 21 ].d ) -#define R1 ( mipscpu.cp2dr[ 21 ].b.l ) -#define G1 ( mipscpu.cp2dr[ 21 ].b.h ) -#define B1 ( mipscpu.cp2dr[ 21 ].b.h2 ) -#define CD1 ( mipscpu.cp2dr[ 21 ].b.h3 ) -#define RGB2 ( mipscpu.cp2dr[ 22 ].d ) -#define R2 ( mipscpu.cp2dr[ 22 ].b.l ) -#define G2 ( mipscpu.cp2dr[ 22 ].b.h ) -#define B2 ( mipscpu.cp2dr[ 22 ].b.h2 ) -#define CD2 ( mipscpu.cp2dr[ 22 ].b.h3 ) -#define RES1 ( mipscpu.cp2dr[ 23 ].d ) -#define MAC0 ( mipscpu.cp2dr[ 24 ].d ) -#define MAC1 ( mipscpu.cp2dr[ 25 ].d ) -#define MAC2 ( mipscpu.cp2dr[ 26 ].d ) -#define MAC3 ( mipscpu.cp2dr[ 27 ].d ) -#define IRGB ( mipscpu.cp2dr[ 28 ].d ) -#define ORGB ( mipscpu.cp2dr[ 29 ].d ) -#define LZCS ( mipscpu.cp2dr[ 30 ].d ) -#define LZCR ( mipscpu.cp2dr[ 31 ].d ) - -#define D1 ( mipscpu.cp2cr[ 0 ].d ) -#define R11 ( mipscpu.cp2cr[ 0 ].w.l ) -#define R12 ( mipscpu.cp2cr[ 0 ].w.h ) -#define R13 ( mipscpu.cp2cr[ 1 ].w.l ) -#define R21 ( mipscpu.cp2cr[ 1 ].w.h ) -#define D2 ( mipscpu.cp2cr[ 2 ].d ) -#define R22 ( mipscpu.cp2cr[ 2 ].w.l ) -#define R23 ( mipscpu.cp2cr[ 2 ].w.h ) -#define R31 ( mipscpu.cp2cr[ 3 ].w.l ) -#define R32 ( mipscpu.cp2cr[ 3 ].w.h ) -#define D3 ( mipscpu.cp2cr[ 4 ].d ) -#define R33 ( mipscpu.cp2cr[ 4 ].w.l ) -#define TRX ( mipscpu.cp2cr[ 5 ].d ) -#define TRY ( mipscpu.cp2cr[ 6 ].d ) -#define TRZ ( mipscpu.cp2cr[ 7 ].d ) -#define L11 ( mipscpu.cp2cr[ 8 ].w.l ) -#define L12 ( mipscpu.cp2cr[ 8 ].w.h ) -#define L13 ( mipscpu.cp2cr[ 9 ].w.l ) -#define L21 ( mipscpu.cp2cr[ 9 ].w.h ) -#define L22 ( mipscpu.cp2cr[ 10 ].w.l ) -#define L23 ( mipscpu.cp2cr[ 10 ].w.h ) -#define L31 ( mipscpu.cp2cr[ 11 ].w.l ) -#define L32 ( mipscpu.cp2cr[ 11 ].w.h ) -#define L33 ( mipscpu.cp2cr[ 12 ].w.l ) -#define RBK ( mipscpu.cp2cr[ 13 ].d ) -#define GBK ( mipscpu.cp2cr[ 14 ].d ) -#define BBK ( mipscpu.cp2cr[ 15 ].d ) -#define LR1 ( mipscpu.cp2cr[ 16 ].w.l ) -#define LR2 ( mipscpu.cp2cr[ 16 ].w.h ) -#define LR3 ( mipscpu.cp2cr[ 17 ].w.l ) -#define LG1 ( mipscpu.cp2cr[ 17 ].w.h ) -#define LG2 ( mipscpu.cp2cr[ 18 ].w.l ) -#define LG3 ( mipscpu.cp2cr[ 18 ].w.h ) -#define LB1 ( mipscpu.cp2cr[ 19 ].w.l ) -#define LB2 ( mipscpu.cp2cr[ 19 ].w.h ) -#define LB3 ( mipscpu.cp2cr[ 20 ].w.l ) -#define RFC ( mipscpu.cp2cr[ 21 ].d ) -#define GFC ( mipscpu.cp2cr[ 22 ].d ) -#define BFC ( mipscpu.cp2cr[ 23 ].d ) -#define OFX ( mipscpu.cp2cr[ 24 ].d ) -#define OFY ( mipscpu.cp2cr[ 25 ].d ) -#define H ( mipscpu.cp2cr[ 26 ].w.l ) -#define DQA ( mipscpu.cp2cr[ 27 ].w.l ) -#define DQB ( mipscpu.cp2cr[ 28 ].d ) -#define ZSF3 ( mipscpu.cp2cr[ 29 ].w.l ) -#define ZSF4 ( mipscpu.cp2cr[ 30 ].w.l ) -#define FLAG ( mipscpu.cp2cr[ 31 ].d ) - -static UINT32 getcp2dr( int n_reg ) -{ - if( n_reg == 1 || n_reg == 3 || n_reg == 5 || n_reg == 8 || n_reg == 9 || n_reg == 10 || n_reg == 11 ) - { - mipscpu.cp2dr[ n_reg ].d = (INT32)(INT16)mipscpu.cp2dr[ n_reg ].d; - } - else if( n_reg == 17 || n_reg == 18 || n_reg == 19 ) - { - mipscpu.cp2dr[ n_reg ].d = (UINT32)(UINT16)mipscpu.cp2dr[ n_reg ].d; - } - else if( n_reg == 29 ) - { - ORGB = ( ( IR1 >> 7 ) & 0x1f ) | ( ( IR2 >> 2 ) & 0x3e0 ) | ( ( IR3 << 3 ) & 0x7c00 ); - } - GTELOG( "get CP2DR%u=%08x", n_reg, mipscpu.cp2dr[ n_reg ].d ); - return mipscpu.cp2dr[ n_reg ].d; -} - -static void setcp2dr( int n_reg, UINT32 n_value ) -{ - GTELOG( "set CP2DR%u=%08x", n_reg, n_value ); - mipscpu.cp2dr[ n_reg ].d = n_value; - - if( n_reg == 15 ) - { - SXY0 = SXY1; - SXY1 = SXY2; - SXY2 = SXYP; - } - else if( n_reg == 28 ) - { - IR1 = ( IRGB & 0x1f ) << 4; - IR2 = ( IRGB & 0x3e0 ) >> 1; - IR3 = ( IRGB & 0x7c00 ) >> 6; - } - else if( n_reg == 30 ) - { - UINT32 n_lzcs = LZCS; - UINT32 n_lzcr = 0; - - if( ( n_lzcs & 0x80000000 ) == 0 ) - { - n_lzcs = ~n_lzcs; - } - while( ( n_lzcs & 0x80000000 ) != 0 ) - { - n_lzcr++; - n_lzcs <<= 1; - } - LZCR = n_lzcr; - } -} - -static UINT32 getcp2cr( int n_reg ) -{ - GTELOG( "get CP2CR%u=%08x", n_reg, mipscpu.cp2cr[ n_reg ].d ); - return mipscpu.cp2cr[ n_reg ].d; -} - -static void setcp2cr( int n_reg, UINT32 n_value ) -{ - GTELOG( "set CP2CR%u=%08x", n_reg, n_value ); - mipscpu.cp2cr[ n_reg ].d = n_value; -} - -static INLINE INT32 LIM( INT32 n_value, INT32 n_max, INT32 n_min, UINT32 n_flag ) -{ - if( n_value > n_max ) - { - FLAG |= n_flag; - return n_max; - } - else if( n_value < n_min ) - { - FLAG |= n_flag; - return n_min; - } - return n_value; -} - -static INLINE INT64 BOUNDS( INT64 n_value, INT64 n_max, int n_maxflag, INT64 n_min, int n_minflag ) -{ - if( n_value > n_max ) - { - FLAG |= n_maxflag; - } - else if( n_value < n_min ) - { - FLAG |= n_minflag; - } - return n_value; -} - -#define A1( a ) BOUNDS( ( a ), 0x7fffffff, 30, -(INT64)0x80000000, ( 1 << 27 ) ) -#define A2( a ) BOUNDS( ( a ), 0x7fffffff, 29, -(INT64)0x80000000, ( 1 << 26 ) ) -#define A3( a ) BOUNDS( ( a ), 0x7fffffff, 28, -(INT64)0x80000000, ( 1 << 25 ) ) -#define Lm_B1( a, l ) LIM( ( a ), 0x7fff, -0x8000 * !l, ( 1 << 31 ) | ( 1 << 24 ) ) -#define Lm_B2( a, l ) LIM( ( a ), 0x7fff, -0x8000 * !l, ( 1 << 31 ) | ( 1 << 23 ) ) -#define Lm_B3( a, l ) LIM( ( a ), 0x7fff, -0x8000 * !l, ( 1 << 22 ) ) -#define Lm_C1( a ) LIM( ( a ), 0x00ff, 0x0000, ( 1 << 21 ) ) -#define Lm_C2( a ) LIM( ( a ), 0x00ff, 0x0000, ( 1 << 20 ) ) -#define Lm_C3( a ) LIM( ( a ), 0x00ff, 0x0000, ( 1 << 19 ) ) -#define Lm_D( a ) LIM( ( a ), 0xffff, 0x0000, ( 1 << 31 ) | ( 1 << 18 ) ) - -static INLINE UINT32 Lm_E( UINT32 n_z ) -{ - if( n_z <= H / 2 ) - { - n_z = H / 2; - FLAG |= ( 1 << 31 ) | ( 1 << 17 ); - } - if( n_z == 0 ) - { - n_z = 1; - } - return n_z; -} - -#define F( a ) BOUNDS( ( a ), 0x7fffffff, ( 1 << 31 ) | ( 1 << 16 ), -(INT64)0x80000000, ( 1 << 31 ) | ( 1 << 15 ) ) -#define Lm_G1( a ) LIM( ( a ), 0x3ff, -0x400, ( 1 << 31 ) | ( 1 << 14 ) ) -#define Lm_G2( a ) LIM( ( a ), 0x3ff, -0x400, ( 1 << 31 ) | ( 1 << 13 ) ) -#define Lm_H( a ) LIM( ( a ), 0xfff, 0x000, ( 1 << 12 ) ) - -static void docop2( int gteop ) -{ - int n_sf; - int n_v; - int n_lm; - int n_pass; - UINT16 n_v1; - UINT16 n_v2; - UINT16 n_v3; - const UINT16 **p_n_mx; - const UINT32 **p_n_cv; - static const UINT16 n_zm = 0; - static const UINT32 n_zc = 0; - static const UINT16 *p_n_vx[] = { &VX0, &VX1, &VX2 }; - static const UINT16 *p_n_vy[] = { &VY0, &VY1, &VY2 }; - static const UINT16 *p_n_vz[] = { &VZ0, &VZ1, &VZ2 }; - static const UINT16 *p_n_rm[] = { &R11, &R12, &R13, &R21, &R22, &R23, &R31, &R32, &R33 }; - static const UINT16 *p_n_lm[] = { &L11, &L12, &L13, &L21, &L22, &L23, &L31, &L32, &L33 }; - static const UINT16 *p_n_cm[] = { &LR1, &LR2, &LR3, &LG1, &LG2, &LG3, &LB1, &LB2, &LB3 }; - static const UINT16 *p_n_zm[] = { &n_zm, &n_zm, &n_zm, &n_zm, &n_zm, &n_zm, &n_zm, &n_zm, &n_zm }; - static const UINT16 **p_p_n_mx[] = { p_n_rm, p_n_lm, p_n_cm, p_n_zm }; - static const UINT32 *p_n_tr[] = { &TRX, &TRY, &TRZ }; - static const UINT32 *p_n_bk[] = { &RBK, &GBK, &BBK }; - static const UINT32 *p_n_fc[] = { &RFC, &GFC, &BFC }; - static const UINT32 *p_n_zc[] = { &n_zc, &n_zc, &n_zc }; - static const UINT32 **p_p_n_cv[] = { p_n_tr, p_n_bk, p_n_fc, p_n_zc }; - - switch( GTE_FUNCT( gteop ) ) - { - case 0x01: - if( gteop == 0x0180001 ) - { - GTELOG( "RTPS" ); - FLAG = 0; - - MAC1 = A1( ( ( (INT64)(INT32)TRX << 12 ) + ( (INT16)R11 * (INT16)VX0 ) + ( (INT16)R12 * (INT16)VY0 ) + ( (INT16)R13 * (INT16)VZ0 ) ) >> 12 ); - MAC2 = A2( ( ( (INT64)(INT32)TRY << 12 ) + ( (INT16)R21 * (INT16)VX0 ) + ( (INT16)R22 * (INT16)VY0 ) + ( (INT16)R23 * (INT16)VZ0 ) ) >> 12 ); - MAC3 = A3( ( ( (INT64)(INT32)TRZ << 12 ) + ( (INT16)R31 * (INT16)VX0 ) + ( (INT16)R32 * (INT16)VY0 ) + ( (INT16)R33 * (INT16)VZ0 ) ) >> 12 ); - IR1 = Lm_B1( (INT32)MAC1, 0 ); - IR2 = Lm_B2( (INT32)MAC2, 0 ); - IR3 = Lm_B3( (INT32)MAC3, 0 ); - SZ0 = SZ1; - SZ1 = SZ2; - SZ2 = SZ3; - SZ3 = Lm_D( (INT32)MAC3 ); - SXY0 = SXY1; - SXY1 = SXY2; - SX2 = Lm_G1( F( (INT64)(INT32)OFX + ( (INT64)(INT16)IR1 * ( ( (UINT32)H << 16 ) / Lm_E( SZ3 ) ) ) ) >> 16 ); - SY2 = Lm_G2( F( (INT64)(INT32)OFY + ( (INT64)(INT16)IR2 * ( ( (UINT32)H << 16 ) / Lm_E( SZ3 ) ) ) ) >> 16 ); - MAC0 = F( (INT64)(INT32)DQB + ( (INT64)(INT16)DQA * ( ( (UINT32)H << 16 ) / Lm_E( SZ3 ) ) ) ); - IR0 = Lm_H( (INT32)MAC0 >> 12 ); - return; - } - break; - case 0x06: - if( gteop == 0x0400006 || - gteop == 0x1400006 || - gteop == 0x0155cc6 ) - { - GTELOG( "NCLIP" ); - FLAG = 0; - - MAC0 = F( ( (INT64)(INT16)SX0 * (INT16)SY1 ) + ( (INT16)SX1 * (INT16)SY2 ) + ( (INT16)SX2 * (INT16)SY0 ) - ( (INT16)SX0 * (INT16)SY2 ) - ( (INT16)SX1 * (INT16)SY0 ) - ( (INT16)SX2 * (INT16)SY1 ) ); - return; - } - break; - case 0x0c: - if( GTE_OP( gteop ) == 0x17 ) - { - GTELOG( "OP" ); - n_sf = 12 * GTE_SF( gteop ); - FLAG = 0; - - MAC1 = A1( ( ( (INT64)(INT32)D2 * (INT16)IR3 ) - ( (INT64)(INT32)D3 * (INT16)IR2 ) ) >> n_sf ); - MAC2 = A2( ( ( (INT64)(INT32)D3 * (INT16)IR1 ) - ( (INT64)(INT32)D1 * (INT16)IR3 ) ) >> n_sf ); - MAC3 = A3( ( ( (INT64)(INT32)D1 * (INT16)IR2 ) - ( (INT64)(INT32)D2 * (INT16)IR1 ) ) >> n_sf ); - IR1 = Lm_B1( (INT32)MAC1, 0 ); - IR2 = Lm_B2( (INT32)MAC2, 0 ); - IR3 = Lm_B3( (INT32)MAC3, 0 ); - return; - } - break; - case 0x10: - if( gteop == 0x0780010 ) - { - GTELOG( "DPCS" ); - FLAG = 0; - - MAC1 = A1( ( ( (INT64)R << 16 ) + ( (INT64)(INT16)IR0 * ( Lm_B1( (INT32)RFC - ( R << 4 ), 0 ) ) ) ) >> 12 ); - MAC2 = A2( ( ( (INT64)G << 16 ) + ( (INT64)(INT16)IR0 * ( Lm_B1( (INT32)GFC - ( G << 4 ), 0 ) ) ) ) >> 12 ); - MAC3 = A3( ( ( (INT64)B << 16 ) + ( (INT64)(INT16)IR0 * ( Lm_B1( (INT32)BFC - ( B << 4 ), 0 ) ) ) ) >> 12 ); - IR1 = Lm_B1( (INT32)MAC1, 0 ); - IR2 = Lm_B2( (INT32)MAC2, 0 ); - IR3 = Lm_B3( (INT32)MAC3, 0 ); - CD0 = CD1; - CD1 = CD2; - CD2 = CODE; - R0 = R1; - R1 = R2; - R2 = Lm_C1( (INT32)MAC1 >> 4 ); - G0 = G1; - G1 = G2; - G2 = Lm_C2( (INT32)MAC2 >> 4 ); - B0 = B1; - B1 = B2; - B2 = Lm_C3( (INT32)MAC3 >> 4 ); - return; - } - break; - case 0x11: - if( gteop == 0x0980011 ) - { - GTELOG( "INTPL" ); - FLAG = 0; - - MAC1 = A1( ( ( (INT64)(INT16)IR1 << 12 ) + ( (INT64)(INT16)IR0 * ( Lm_B1( (INT32)RFC - (INT16)IR1, 0 ) ) ) ) >> 12 ); - MAC2 = A2( ( ( (INT64)(INT16)IR2 << 12 ) + ( (INT64)(INT16)IR0 * ( Lm_B1( (INT32)GFC - (INT16)IR2, 0 ) ) ) ) >> 12 ); - MAC3 = A3( ( ( (INT64)(INT16)IR3 << 12 ) + ( (INT64)(INT16)IR0 * ( Lm_B1( (INT32)BFC - (INT16)IR3, 0 ) ) ) ) >> 12 ); - IR1 = Lm_B1( (INT32)MAC1, 0 ); - IR2 = Lm_B2( (INT32)MAC2, 0 ); - IR3 = Lm_B3( (INT32)MAC3, 0 ); - CD0 = CD1; - CD1 = CD2; - CD2 = CODE; - R0 = R1; - R1 = R2; - R2 = Lm_C1( (INT32)MAC1 ); - G0 = G1; - G1 = G2; - G2 = Lm_C2( (INT32)MAC2 ); - B0 = B1; - B1 = B2; - B2 = Lm_C3( (INT32)MAC3 ); - return; - } - break; - case 0x12: - if( GTE_OP( gteop ) == 0x04 ) - { - GTELOG( "MVMVA" ); - n_sf = 12 * GTE_SF( gteop ); - p_n_mx = p_p_n_mx[ GTE_MX( gteop ) ]; - n_v = GTE_V( gteop ); - if( n_v < 3 ) - { - n_v1 = *p_n_vx[ n_v ]; - n_v2 = *p_n_vy[ n_v ]; - n_v3 = *p_n_vz[ n_v ]; - } - else - { - n_v1 = IR1; - n_v2 = IR2; - n_v3 = IR3; - } - p_n_cv = p_p_n_cv[ GTE_CV( gteop ) ]; - n_lm = GTE_LM( gteop ); - FLAG = 0; - - MAC1 = A1( ( ( (INT64)(INT32)*p_n_cv[ 0 ] << 12 ) + ( (INT16)*p_n_mx[ 0 ] * (INT16)n_v1 ) + ( (INT16)*p_n_mx[ 1 ] * (INT16)n_v2 ) + ( (INT16)*p_n_mx[ 2 ] * (INT16)n_v3 ) ) >> n_sf ); - MAC2 = A2( ( ( (INT64)(INT32)*p_n_cv[ 1 ] << 12 ) + ( (INT16)*p_n_mx[ 3 ] * (INT16)n_v1 ) + ( (INT16)*p_n_mx[ 4 ] * (INT16)n_v2 ) + ( (INT16)*p_n_mx[ 5 ] * (INT16)n_v3 ) ) >> n_sf ); - MAC3 = A3( ( ( (INT64)(INT32)*p_n_cv[ 2 ] << 12 ) + ( (INT16)*p_n_mx[ 6 ] * (INT16)n_v1 ) + ( (INT16)*p_n_mx[ 7 ] * (INT16)n_v2 ) + ( (INT16)*p_n_mx[ 8 ] * (INT16)n_v3 ) ) >> n_sf ); - - IR1 = Lm_B1( (INT32)MAC1, n_lm ); - IR2 = Lm_B2( (INT32)MAC2, n_lm ); - IR3 = Lm_B3( (INT32)MAC3, n_lm ); - return; - } - break; - case 0x13: - if( gteop == 0x0e80413 ) - { - GTELOG( "NCDS" ); - FLAG = 0; - - MAC1 = A1( ( ( (INT64)(INT16)L11 * (INT16)VX0 ) + ( (INT16)L12 * (INT16)VY0 ) + ( (INT16)L13 * (INT16)VZ0 ) ) >> 12 ); - MAC2 = A2( ( ( (INT64)(INT16)L21 * (INT16)VX0 ) + ( (INT16)L22 * (INT16)VY0 ) + ( (INT16)L23 * (INT16)VZ0 ) ) >> 12 ); - MAC3 = A3( ( ( (INT64)(INT16)L31 * (INT16)VX0 ) + ( (INT16)L32 * (INT16)VY0 ) + ( (INT16)L33 * (INT16)VZ0 ) ) >> 12 ); - IR1 = Lm_B1( (INT32)MAC1, 1 ); - IR2 = Lm_B2( (INT32)MAC2, 1 ); - IR3 = Lm_B3( (INT32)MAC3, 1 ); - MAC1 = A1( ( ( (INT64)RBK << 12 ) + ( (INT16)LR1 * (INT16)IR1 ) + ( (INT16)LR2 * (INT16)IR2 ) + ( (INT16)LR3 * (INT16)IR3 ) ) >> 12 ); - MAC2 = A2( ( ( (INT64)GBK << 12 ) + ( (INT16)LG1 * (INT16)IR1 ) + ( (INT16)LG2 * (INT16)IR2 ) + ( (INT16)LG3 * (INT16)IR3 ) ) >> 12 ); - MAC3 = A3( ( ( (INT64)BBK << 12 ) + ( (INT16)LB1 * (INT16)IR1 ) + ( (INT16)LB2 * (INT16)IR2 ) + ( (INT16)LB3 * (INT16)IR3 ) ) >> 12 ); - IR1 = Lm_B1( (INT32)MAC1, 1 ); - IR2 = Lm_B2( (INT32)MAC2, 1 ); - IR3 = Lm_B3( (INT32)MAC3, 1 ); - MAC1 = A1( ( ( ( (INT64)R << 4 ) * (INT16)IR1 ) + ( (INT16)IR0 * Lm_B1( (INT32)RFC - ( ( R * (INT16)IR1 ) >> 8 ), 0 ) ) ) >> 12 ); - MAC2 = A2( ( ( ( (INT64)G << 4 ) * (INT16)IR2 ) + ( (INT16)IR0 * Lm_B2( (INT32)GFC - ( ( G * (INT16)IR2 ) >> 8 ), 0 ) ) ) >> 12 ); - MAC3 = A3( ( ( ( (INT64)B << 4 ) * (INT16)IR3 ) + ( (INT16)IR0 * Lm_B3( (INT32)BFC - ( ( B * (INT16)IR3 ) >> 8 ), 0 ) ) ) >> 12 ); - IR1 = Lm_B1( (INT32)MAC1, 1 ); - IR2 = Lm_B2( (INT32)MAC2, 1 ); - IR3 = Lm_B3( (INT32)MAC3, 1 ); - CD0 = CD1; - CD1 = CD2; - CD2 = CODE; - R0 = R1; - R1 = R2; - R2 = Lm_C1( (INT32)MAC1 >> 4 ); - G0 = G1; - G1 = G2; - G2 = Lm_C2( (INT32)MAC2 >> 4 ); - B0 = B1; - B1 = B2; - B2 = Lm_C3( (INT32)MAC3 >> 4 ); - return; - } - break; - case 0x14: - if( gteop == 0x1280414 ) - { - GTELOG( "CDP" ); - FLAG = 0; - - MAC1 = A1( ( ( (INT64)RBK << 12 ) + ( (INT16)LR1 * (INT16)IR1 ) + ( (INT16)LR2 * (INT16)IR2 ) + ( (INT16)LR3 * (INT16)IR3 ) ) >> 12 ); - MAC2 = A2( ( ( (INT64)GBK << 12 ) + ( (INT16)LG1 * (INT16)IR1 ) + ( (INT16)LG2 * (INT16)IR2 ) + ( (INT16)LG3 * (INT16)IR3 ) ) >> 12 ); - MAC3 = A3( ( ( (INT64)BBK << 12 ) + ( (INT16)LB1 * (INT16)IR1 ) + ( (INT16)LB2 * (INT16)IR2 ) + ( (INT16)LB3 * (INT16)IR3 ) ) >> 12 ); - IR1 = Lm_B1( MAC1, 1 ); - IR2 = Lm_B2( MAC2, 1 ); - IR3 = Lm_B3( MAC3, 1 ); - MAC1 = A1( ( ( ( (INT64)R << 4 ) * (INT16)IR1 ) + ( (INT16)IR0 * Lm_B1( (INT32)RFC - ( ( R * (INT16)IR1 ) >> 8 ), 0 ) ) ) >> 12 ); - MAC2 = A2( ( ( ( (INT64)G << 4 ) * (INT16)IR2 ) + ( (INT16)IR0 * Lm_B2( (INT32)GFC - ( ( G * (INT16)IR2 ) >> 8 ), 0 ) ) ) >> 12 ); - MAC3 = A3( ( ( ( (INT64)B << 4 ) * (INT16)IR3 ) + ( (INT16)IR0 * Lm_B3( (INT32)BFC - ( ( B * (INT16)IR3 ) >> 8 ), 0 ) ) ) >> 12 ); - IR1 = Lm_B1( MAC1, 1 ); - IR2 = Lm_B2( MAC2, 1 ); - IR3 = Lm_B3( MAC3, 1 ); - CD0 = CD1; - CD1 = CD2; - CD2 = CODE; - R0 = R1; - R1 = R2; - R2 = Lm_C1( (INT32)MAC1 >> 4 ); - G0 = G1; - G1 = G2; - G2 = Lm_C2( (INT32)MAC2 >> 4 ); - B0 = B1; - B1 = B2; - B2 = Lm_C3( (INT32)MAC3 >> 4 ); - return; - } - break; - case 0x16: - if( gteop == 0x0f80416 ) - { - GTELOG( "NCDT" ); - FLAG = 0; - - for( n_v = 0; n_v < 3; n_v++ ) - { - MAC1 = A1( ( ( (INT64)(INT16)L11 * (INT16)*p_n_vx[ n_v ] ) + ( (INT16)L12 * (INT16)*p_n_vy[ n_v ] ) + ( (INT16)L13 * (INT16)*p_n_vz[ n_v ] ) ) >> 12 ); - MAC2 = A2( ( ( (INT64)(INT16)L21 * (INT16)*p_n_vx[ n_v ] ) + ( (INT16)L22 * (INT16)*p_n_vy[ n_v ] ) + ( (INT16)L23 * (INT16)*p_n_vz[ n_v ] ) ) >> 12 ); - MAC3 = A3( ( ( (INT64)(INT16)L31 * (INT16)*p_n_vx[ n_v ] ) + ( (INT16)L32 * (INT16)*p_n_vy[ n_v ] ) + ( (INT16)L33 * (INT16)*p_n_vz[ n_v ] ) ) >> 12 ); - IR1 = Lm_B1( (INT32)MAC1, 1 ); - IR2 = Lm_B2( (INT32)MAC2, 1 ); - IR3 = Lm_B3( (INT32)MAC3, 1 ); - MAC1 = A1( ( ( (INT64)RBK << 12 ) + ( (INT16)LR1 * (INT16)IR1 ) + ( (INT16)LR2 * (INT16)IR2 ) + ( (INT16)LR3 * (INT16)IR3 ) ) >> 12 ); - MAC2 = A2( ( ( (INT64)GBK << 12 ) + ( (INT16)LG1 * (INT16)IR1 ) + ( (INT16)LG2 * (INT16)IR2 ) + ( (INT16)LG3 * (INT16)IR3 ) ) >> 12 ); - MAC3 = A3( ( ( (INT64)BBK << 12 ) + ( (INT16)LB1 * (INT16)IR1 ) + ( (INT16)LB2 * (INT16)IR2 ) + ( (INT16)LB3 * (INT16)IR3 ) ) >> 12 ); - IR1 = Lm_B1( (INT32)MAC1, 1 ); - IR2 = Lm_B2( (INT32)MAC2, 1 ); - IR3 = Lm_B3( (INT32)MAC3, 1 ); - MAC1 = A1( ( ( ( (INT64)R << 4 ) * (INT16)IR1 ) + ( (INT16)IR0 * Lm_B1( (INT32)RFC - ( ( R * (INT16)IR1 ) >> 8 ), 0 ) ) ) >> 12 ); - MAC2 = A2( ( ( ( (INT64)G << 4 ) * (INT16)IR2 ) + ( (INT16)IR0 * Lm_B2( (INT32)GFC - ( ( G * (INT16)IR2 ) >> 8 ), 0 ) ) ) >> 12 ); - MAC3 = A3( ( ( ( (INT64)B << 4 ) * (INT16)IR3 ) + ( (INT16)IR0 * Lm_B3( (INT32)BFC - ( ( B * (INT16)IR3 ) >> 8 ), 0 ) ) ) >> 12 ); - IR1 = Lm_B1( (INT32)MAC1, 1 ); - IR2 = Lm_B2( (INT32)MAC2, 1 ); - IR3 = Lm_B3( (INT32)MAC3, 1 ); - CD0 = CD1; - CD1 = CD2; - CD2 = CODE; - R0 = R1; - R1 = R2; - R2 = Lm_C1( (INT32)MAC1 >> 4 ); - G0 = G1; - G1 = G2; - G2 = Lm_C2( (INT32)MAC2 >> 4 ); - B0 = B1; - B1 = B2; - B2 = Lm_C3( (INT32)MAC3 >> 4 ); - } - return; - } - break; - case 0x1b: - if( gteop == 0x108041b ) - { - GTELOG( "NCCS" ); - FLAG = 0; - - MAC1 = A1( ( ( (INT64)(INT16)L11 * (INT16)VX0 ) + ( (INT16)L12 * (INT16)VY0 ) + ( (INT16)L13 * (INT16)VZ0 ) ) >> 12 ); - MAC2 = A2( ( ( (INT64)(INT16)L21 * (INT16)VX0 ) + ( (INT16)L22 * (INT16)VY0 ) + ( (INT16)L23 * (INT16)VZ0 ) ) >> 12 ); - MAC3 = A3( ( ( (INT64)(INT16)L31 * (INT16)VX0 ) + ( (INT16)L32 * (INT16)VY0 ) + ( (INT16)L33 * (INT16)VZ0 ) ) >> 12 ); - IR1 = Lm_B1( (INT32)MAC1, 1 ); - IR2 = Lm_B2( (INT32)MAC2, 1 ); - IR3 = Lm_B3( (INT32)MAC3, 1 ); - MAC1 = A1( ( ( (INT64)RBK << 12 ) + ( (INT16)LR1 * (INT16)IR1 ) + ( (INT16)LR2 * (INT16)IR2 ) + ( (INT16)LR3 * (INT16)IR3 ) ) >> 12 ); - MAC2 = A2( ( ( (INT64)GBK << 12 ) + ( (INT16)LG1 * (INT16)IR1 ) + ( (INT16)LG2 * (INT16)IR2 ) + ( (INT16)LG3 * (INT16)IR3 ) ) >> 12 ); - MAC3 = A3( ( ( (INT64)BBK << 12 ) + ( (INT16)LB1 * (INT16)IR1 ) + ( (INT16)LB2 * (INT16)IR2 ) + ( (INT16)LB3 * (INT16)IR3 ) ) >> 12 ); - IR1 = Lm_B1( (INT32)MAC1, 1 ); - IR2 = Lm_B2( (INT32)MAC2, 1 ); - IR3 = Lm_B3( (INT32)MAC3, 1 ); - MAC1 = A1( ( (INT64)R * (INT16)IR1 ) >> 8 ); - MAC2 = A2( ( (INT64)G * (INT16)IR2 ) >> 8 ); - MAC3 = A3( ( (INT64)B * (INT16)IR3 ) >> 8 ); - IR1 = Lm_B1( (INT32)MAC1, 1 ); - IR2 = Lm_B2( (INT32)MAC2, 1 ); - IR3 = Lm_B3( (INT32)MAC3, 1 ); - CD0 = CD1; - CD1 = CD2; - CD2 = CODE; - R0 = R1; - R1 = R2; - R2 = Lm_C1( (INT32)MAC1 >> 4 ); - G0 = G1; - G1 = G2; - G2 = Lm_C2( (INT32)MAC2 >> 4 ); - B0 = B1; - B1 = B2; - B2 = Lm_C3( (INT32)MAC3 >> 4 ); - return; - } - break; - case 0x1c: - if( gteop == 0x138041c ) - { - GTELOG( "CC" ); - FLAG = 0; - - MAC1 = A1( ( ( (INT64)RBK << 12 ) + ( (INT16)LR1 * (INT16)IR1 ) + ( (INT16)LR2 * (INT16)IR2 ) + ( (INT16)LR3 * (INT16)IR3 ) ) >> 12 ); - MAC2 = A2( ( ( (INT64)GBK << 12 ) + ( (INT16)LG1 * (INT16)IR1 ) + ( (INT16)LG2 * (INT16)IR2 ) + ( (INT16)LG3 * (INT16)IR3 ) ) >> 12 ); - MAC3 = A3( ( ( (INT64)BBK << 12 ) + ( (INT16)LB1 * (INT16)IR1 ) + ( (INT16)LB2 * (INT16)IR2 ) + ( (INT16)LB3 * (INT16)IR3 ) ) >> 12 ); - IR1 = Lm_B1( MAC1, 1 ); - IR2 = Lm_B2( MAC2, 1 ); - IR3 = Lm_B3( MAC3, 1 ); - MAC1 = A1( ( (INT64)R * (INT16)IR1 ) >> 8 ); - MAC2 = A2( ( (INT64)G * (INT16)IR2 ) >> 8 ); - MAC3 = A3( ( (INT64)B * (INT16)IR3 ) >> 8 ); - IR1 = Lm_B1( MAC1, 1 ); - IR2 = Lm_B2( MAC2, 1 ); - IR3 = Lm_B3( MAC3, 1 ); - CD0 = CD1; - CD1 = CD2; - CD2 = CODE; - R0 = R1; - R1 = R2; - R2 = Lm_C1( (INT32)MAC1 >> 4 ); - G0 = G1; - G1 = G2; - G2 = Lm_C2( (INT32)MAC2 >> 4 ); - B0 = B1; - B1 = B2; - B2 = Lm_C3( (INT32)MAC3 >> 4 ); - return; - } - break; - case 0x1e: - if( gteop == 0x0c8041e ) - { - GTELOG( "NCS" ); - FLAG = 0; - - MAC1 = A1( ( ( (INT64)(INT16)L11 * (INT16)VX0 ) + ( (INT16)L12 * (INT16)VY0 ) + ( (INT16)L13 * (INT16)VZ0 ) ) >> 12 ); - MAC2 = A2( ( ( (INT64)(INT16)L21 * (INT16)VX0 ) + ( (INT16)L22 * (INT16)VY0 ) + ( (INT16)L23 * (INT16)VZ0 ) ) >> 12 ); - MAC3 = A3( ( ( (INT64)(INT16)L31 * (INT16)VX0 ) + ( (INT16)L32 * (INT16)VY0 ) + ( (INT16)L33 * (INT16)VZ0 ) ) >> 12 ); - IR1 = Lm_B1( (INT32)MAC1, 1 ); - IR2 = Lm_B2( (INT32)MAC2, 1 ); - IR3 = Lm_B3( (INT32)MAC3, 1 ); - MAC1 = A1( ( ( (INT64)RBK << 12 ) + ( (INT16)LR1 * (INT16)IR1 ) + ( (INT16)LR2 * (INT16)IR2 ) + ( (INT16)LR3 * (INT16)IR3 ) ) >> 12 ); - MAC2 = A2( ( ( (INT64)GBK << 12 ) + ( (INT16)LG1 * (INT16)IR1 ) + ( (INT16)LG2 * (INT16)IR2 ) + ( (INT16)LG3 * (INT16)IR3 ) ) >> 12 ); - MAC3 = A3( ( ( (INT64)BBK << 12 ) + ( (INT16)LB1 * (INT16)IR1 ) + ( (INT16)LB2 * (INT16)IR2 ) + ( (INT16)LB3 * (INT16)IR3 ) ) >> 12 ); - IR1 = Lm_B1( (INT32)MAC1, 1 ); - IR2 = Lm_B2( (INT32)MAC2, 1 ); - IR3 = Lm_B3( (INT32)MAC3, 1 ); - CD0 = CD1; - CD1 = CD2; - CD2 = CODE; - R0 = R1; - R1 = R2; - R2 = Lm_C1( (INT32)MAC1 >> 4 ); - G0 = G1; - G1 = G2; - G2 = Lm_C2( (INT32)MAC2 >> 4 ); - B0 = B1; - B1 = B2; - B2 = Lm_C3( (INT32)MAC3 >> 4 ); - return; - } - break; - case 0x20: - if( gteop == 0x0d80420 ) - { - GTELOG( "NCT" ); - FLAG = 0; - - for( n_v = 0; n_v < 3; n_v++ ) - { - MAC1 = A1( ( ( (INT64)(INT16)L11 * (INT16)*p_n_vx[ n_v ] ) + ( (INT16)L12 * (INT16)*p_n_vy[ n_v ] ) + ( (INT16)L13 * (INT16)*p_n_vz[ n_v ] ) ) >> 12 ); - MAC2 = A2( ( ( (INT64)(INT16)L21 * (INT16)*p_n_vx[ n_v ] ) + ( (INT16)L22 * (INT16)*p_n_vy[ n_v ] ) + ( (INT16)L23 * (INT16)*p_n_vz[ n_v ] ) ) >> 12 ); - MAC3 = A3( ( ( (INT64)(INT16)L31 * (INT16)*p_n_vx[ n_v ] ) + ( (INT16)L32 * (INT16)*p_n_vy[ n_v ] ) + ( (INT16)L33 * (INT16)*p_n_vz[ n_v ] ) ) >> 12 ); - IR1 = Lm_B1( (INT32)MAC1, 1 ); - IR2 = Lm_B2( (INT32)MAC2, 1 ); - IR3 = Lm_B3( (INT32)MAC3, 1 ); - MAC1 = A1( ( ( (INT64)RBK << 12 ) + ( (INT16)LR1 * (INT16)IR1 ) + ( (INT16)LR2 * (INT16)IR2 ) + ( (INT16)LR3 * (INT16)IR3 ) ) >> 12 ); - MAC2 = A2( ( ( (INT64)GBK << 12 ) + ( (INT16)LG1 * (INT16)IR1 ) + ( (INT16)LG2 * (INT16)IR2 ) + ( (INT16)LG3 * (INT16)IR3 ) ) >> 12 ); - MAC3 = A3( ( ( (INT64)BBK << 12 ) + ( (INT16)LB1 * (INT16)IR1 ) + ( (INT16)LB2 * (INT16)IR2 ) + ( (INT16)LB3 * (INT16)IR3 ) ) >> 12 ); - IR1 = Lm_B1( (INT32)MAC1, 1 ); - IR2 = Lm_B2( (INT32)MAC2, 1 ); - IR3 = Lm_B3( (INT32)MAC3, 1 ); - CD0 = CD1; - CD1 = CD2; - CD2 = CODE; - R0 = R1; - R1 = R2; - R2 = Lm_C1( (INT32)MAC1 >> 4 ); - G0 = G1; - G1 = G2; - G2 = Lm_C2( (INT32)MAC2 >> 4 ); - B0 = B1; - B1 = B2; - B2 = Lm_C3( (INT32)MAC3 >> 4 ); - } - return; - } - break; - case 0x28: - if( GTE_OP( gteop ) == 0x0a && GTE_LM( gteop ) == 1 ) - { - GTELOG( "SQR" ); - n_sf = 12 * GTE_SF( gteop ); - FLAG = 0; - - MAC1 = A1( ( (INT64)(INT16)IR1 * (INT16)IR1 ) >> n_sf ); - MAC2 = A2( ( (INT64)(INT16)IR2 * (INT16)IR2 ) >> n_sf ); - MAC3 = A3( ( (INT64)(INT16)IR3 * (INT16)IR3 ) >> n_sf ); - IR1 = Lm_B1( MAC1, 1 ); - IR2 = Lm_B2( MAC2, 1 ); - IR3 = Lm_B3( MAC3, 1 ); - return; - } - break; - // DCPL 0x29 - case 0x2a: - if( gteop == 0x0f8002a ) - { - GTELOG( "DPCT" ); - FLAG = 0; - - for( n_pass = 0; n_pass < 3; n_pass++ ) - { - MAC1 = A1( ( ( (INT64)R0 << 16 ) + ( (INT64)(INT16)IR0 * ( Lm_B1( (INT32)RFC - ( R0 << 4 ), 0 ) ) ) ) >> 12 ); - MAC2 = A2( ( ( (INT64)G0 << 16 ) + ( (INT64)(INT16)IR0 * ( Lm_B1( (INT32)GFC - ( G0 << 4 ), 0 ) ) ) ) >> 12 ); - MAC3 = A3( ( ( (INT64)B0 << 16 ) + ( (INT64)(INT16)IR0 * ( Lm_B1( (INT32)BFC - ( B0 << 4 ), 0 ) ) ) ) >> 12 ); - IR1 = Lm_B1( (INT32)MAC1, 0 ); - IR2 = Lm_B2( (INT32)MAC2, 0 ); - IR3 = Lm_B3( (INT32)MAC3, 0 ); - CD0 = CD1; - CD1 = CD2; - CD2 = CODE; - R0 = R1; - R1 = R2; - R2 = Lm_C1( (INT32)MAC1 >> 4 ); - G0 = G1; - G1 = G2; - G2 = Lm_C2( (INT32)MAC2 >> 4 ); - B0 = B1; - B1 = B2; - B2 = Lm_C3( (INT32)MAC3 >> 4 ); - } - return; - } - break; - case 0x2d: - if( gteop == 0x158002d ) - { - GTELOG( "AVSZ3" ); - FLAG = 0; - - MAC0 = F( ( (INT64)(INT16)ZSF3 * SZ1 ) + ( (INT16)ZSF3 * SZ2 ) + ( (INT16)ZSF3 * SZ3 ) ); - OTZ = Lm_D( (INT32)MAC0 >> 12 ); - return; - } - break; - case 0x2e: - if( gteop == 0x168002e ) - { - GTELOG( "AVSZ4" ); - FLAG = 0; - - MAC0 = F( ( (INT64)(INT16)ZSF4 * SZ0 ) + ( (INT16)ZSF4 * SZ1 ) + ( (INT16)ZSF4 * SZ2 ) + ( (INT16)ZSF4 * SZ3 ) ); - OTZ = Lm_D( (INT32)MAC0 >> 12 ); - return; - } - break; - case 0x30: - if( gteop == 0x0280030 ) - { - GTELOG( "RTPT" ); - FLAG = 0; - - for( n_v = 0; n_v < 3; n_v++ ) - { - MAC1 = A1( ( ( (INT64)(INT32)TRX << 12 ) + ( (INT16)R11 * (INT16)*p_n_vx[ n_v ] ) + ( (INT16)R12 * (INT16)*p_n_vy[ n_v ] ) + ( (INT16)R13 * (INT16)*p_n_vz[ n_v ] ) ) >> 12 ); - MAC2 = A2( ( ( (INT64)(INT32)TRY << 12 ) + ( (INT16)R21 * (INT16)*p_n_vx[ n_v ] ) + ( (INT16)R22 * (INT16)*p_n_vy[ n_v ] ) + ( (INT16)R23 * (INT16)*p_n_vz[ n_v ] ) ) >> 12 ); - MAC3 = A3( ( ( (INT64)(INT32)TRZ << 12 ) + ( (INT16)R31 * (INT16)*p_n_vx[ n_v ] ) + ( (INT16)R32 * (INT16)*p_n_vy[ n_v ] ) + ( (INT16)R33 * (INT16)*p_n_vz[ n_v ] ) ) >> 12 ); - IR1 = Lm_B1( (INT32)MAC1, 0 ); - IR2 = Lm_B2( (INT32)MAC2, 0 ); - IR3 = Lm_B3( (INT32)MAC3, 0 ); - SZ0 = SZ1; - SZ1 = SZ2; - SZ2 = SZ3; - SZ3 = Lm_D( (INT32)MAC3 ); - SXY0 = SXY1; - SXY1 = SXY2; - SX2 = Lm_G1( F( ( (INT64)(INT32)OFX + ( (INT64)(INT16)IR1 * ( ( (UINT32)H << 16 ) / Lm_E( SZ3 ) ) ) ) >> 16 ) ); - SY2 = Lm_G2( F( ( (INT64)(INT32)OFY + ( (INT64)(INT16)IR2 * ( ( (UINT32)H << 16 ) / Lm_E( SZ3 ) ) ) ) >> 16 ) ); - MAC0 = F( (INT64)(INT32)DQB + ( (INT64)(INT16)DQA * ( ( (UINT32)H << 16 ) / Lm_E( SZ3 ) ) ) ); - IR0 = Lm_H( (INT32)MAC0 >> 12 ); - } - return; - } - break; - case 0x3d: - if( GTE_OP( gteop ) == 0x09 || - GTE_OP( gteop ) == 0x19 ) - { - GTELOG( "GPF" ); - n_sf = 12 * GTE_SF( gteop ); - FLAG = 0; - - MAC1 = A1( ( (INT64)(INT16)IR0 * (INT16)IR1 ) >> n_sf ); - MAC2 = A2( ( (INT64)(INT16)IR0 * (INT16)IR2 ) >> n_sf ); - MAC3 = A3( ( (INT64)(INT16)IR0 * (INT16)IR3 ) >> n_sf ); - IR1 = Lm_B1( (INT32)MAC1, 0 ); - IR2 = Lm_B2( (INT32)MAC2, 0 ); - IR3 = Lm_B3( (INT32)MAC3, 0 ); - CD0 = CD1; - CD1 = CD2; - CD2 = CODE; - R0 = R1; - R1 = R2; - R2 = Lm_C1( (INT32)MAC1 >> 4 ); - G0 = G1; - G1 = G2; - G2 = Lm_C2( (INT32)MAC2 >> 4 ); - B0 = B1; - B1 = B2; - B2 = Lm_C3( (INT32)MAC3 >> 4 ); - return; - } - break; - case 0x3e: - if( GTE_OP( gteop ) == 0x1a ) - { - GTELOG( "GPL" ); - n_sf = 12 * GTE_SF( gteop ); - FLAG = 0; - - MAC1 = A1( ( ( (INT64)(INT32)MAC1 << n_sf ) + ( (INT16)IR0 * (INT16)IR1 ) ) >> n_sf ); - MAC2 = A2( ( ( (INT64)(INT32)MAC2 << n_sf ) + ( (INT16)IR0 * (INT16)IR2 ) ) >> n_sf ); - MAC3 = A3( ( ( (INT64)(INT32)MAC3 << n_sf ) + ( (INT16)IR0 * (INT16)IR3 ) ) >> n_sf ); - IR1 = Lm_B1( (INT32)MAC1, 0 ); - IR2 = Lm_B2( (INT32)MAC2, 0 ); - IR3 = Lm_B3( (INT32)MAC3, 0 ); - CD0 = CD1; - CD1 = CD2; - CD2 = CODE; - R0 = R1; - R1 = R2; - R2 = Lm_C1( (INT32)MAC1 >> 4 ); - G0 = G1; - G1 = G2; - G2 = Lm_C2( (INT32)MAC2 >> 4 ); - B0 = B1; - B1 = B2; - B2 = Lm_C3( (INT32)MAC3 >> 4 ); - return; - } - break; - case 0x3f: - if( gteop == 0x108043f || - gteop == 0x118043f ) - { - GTELOG( "NCCT" ); - FLAG = 0; - - for( n_v = 0; n_v < 3; n_v++ ) - { - MAC1 = A1( ( ( (INT64)(INT16)L11 * (INT16)*p_n_vx[ n_v ] ) + ( (INT16)L12 * (INT16)*p_n_vy[ n_v ] ) + ( (INT16)L13 * (INT16)*p_n_vz[ n_v ] ) ) >> 12 ); - MAC2 = A2( ( ( (INT64)(INT16)L21 * (INT16)*p_n_vx[ n_v ] ) + ( (INT16)L22 * (INT16)*p_n_vy[ n_v ] ) + ( (INT16)L23 * (INT16)*p_n_vz[ n_v ] ) ) >> 12 ); - MAC3 = A3( ( ( (INT64)(INT16)L31 * (INT16)*p_n_vx[ n_v ] ) + ( (INT16)L32 * (INT16)*p_n_vy[ n_v ] ) + ( (INT16)L33 * (INT16)*p_n_vz[ n_v ] ) ) >> 12 ); - IR1 = Lm_B1( (INT32)MAC1, 1 ); - IR2 = Lm_B2( (INT32)MAC2, 1 ); - IR3 = Lm_B3( (INT32)MAC3, 1 ); - MAC1 = A1( ( ( (INT64)RBK << 12 ) + ( (INT16)LR1 * (INT16)IR1 ) + ( (INT16)LR2 * (INT16)IR2 ) + ( (INT16)LR3 * (INT16)IR3 ) ) >> 12 ); - MAC2 = A2( ( ( (INT64)GBK << 12 ) + ( (INT16)LG1 * (INT16)IR1 ) + ( (INT16)LG2 * (INT16)IR2 ) + ( (INT16)LG3 * (INT16)IR3 ) ) >> 12 ); - MAC3 = A3( ( ( (INT64)BBK << 12 ) + ( (INT16)LB1 * (INT16)IR1 ) + ( (INT16)LB2 * (INT16)IR2 ) + ( (INT16)LB3 * (INT16)IR3 ) ) >> 12 ); - IR1 = Lm_B1( (INT32)MAC1, 1 ); - IR2 = Lm_B2( (INT32)MAC2, 1 ); - IR3 = Lm_B3( (INT32)MAC3, 1 ); - MAC1 = A1( ( (INT64)R * (INT16)IR1 ) >> 8 ); - MAC2 = A2( ( (INT64)G * (INT16)IR2 ) >> 8 ); - MAC3 = A3( ( (INT64)B * (INT16)IR3 ) >> 8 ); - IR1 = Lm_B1( (INT32)MAC1, 1 ); - IR2 = Lm_B2( (INT32)MAC2, 1 ); - IR3 = Lm_B3( (INT32)MAC3, 1 ); - CD0 = CD1; - CD1 = CD2; - CD2 = CODE; - R0 = R1; - R1 = R2; - R2 = Lm_C1( (INT32)MAC1 >> 4 ); - G0 = G1; - G1 = G2; - G2 = Lm_C2( (INT32)MAC2 >> 4 ); - B0 = B1; - B1 = B2; - B2 = Lm_C3( (INT32)MAC3 >> 4 ); - } - return; - } - break; - } -// usrintf_showmessage_secs( 1, "unknown GTE op %08x", gteop ); - logerror( "%08x: unknown GTE op %08x\n", mipscpu.pc, gteop ); - mips_stop(); -} - -/************************************************************************** - * Generic set_info - **************************************************************************/ - -void mips_set_info(UINT32 state, union cpuinfo *info) -{ - switch (state) - { - /* --- the following bits of info are set as 64-bit signed integers --- */ - case CPUINFO_INT_INPUT_STATE + MIPS_IRQ0: set_irq_line(MIPS_IRQ0, info->i); break; - case CPUINFO_INT_INPUT_STATE + MIPS_IRQ1: set_irq_line(MIPS_IRQ1, info->i); break; - case CPUINFO_INT_INPUT_STATE + MIPS_IRQ2: set_irq_line(MIPS_IRQ2, info->i); break; - case CPUINFO_INT_INPUT_STATE + MIPS_IRQ3: set_irq_line(MIPS_IRQ3, info->i); break; - case CPUINFO_INT_INPUT_STATE + MIPS_IRQ4: set_irq_line(MIPS_IRQ4, info->i); break; - case CPUINFO_INT_INPUT_STATE + MIPS_IRQ5: set_irq_line(MIPS_IRQ5, info->i); break; - - case CPUINFO_INT_PC: mips_set_pc( info->i ); break; - case CPUINFO_INT_REGISTER + MIPS_PC: mips_set_pc( info->i ); break; - case CPUINFO_INT_SP: /* no stack */ break; - case CPUINFO_INT_REGISTER + MIPS_DELAYV: mipscpu.delayv = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_DELAYR: if( info->i <= REGPC ) mipscpu.delayr = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_HI: mipscpu.hi = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_LO: mipscpu.lo = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_R0: mipscpu.r[ 0 ] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_R1: mipscpu.r[ 1 ] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_R2: mipscpu.r[ 2 ] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_R3: mipscpu.r[ 3 ] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_R4: mipscpu.r[ 4 ] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_R5: mipscpu.r[ 5 ] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_R6: mipscpu.r[ 6 ] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_R7: mipscpu.r[ 7 ] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_R8: mipscpu.r[ 8 ] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_R9: mipscpu.r[ 9 ] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_R10: mipscpu.r[ 10 ] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_R11: mipscpu.r[ 11 ] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_R12: mipscpu.r[ 12 ] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_R13: mipscpu.r[ 13 ] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_R14: mipscpu.r[ 14 ] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_R15: mipscpu.r[ 15 ] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_R16: mipscpu.r[ 16 ] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_R17: mipscpu.r[ 17 ] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_R18: mipscpu.r[ 18 ] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_R19: mipscpu.r[ 19 ] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_R20: mipscpu.r[ 20 ] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_R21: mipscpu.r[ 21 ] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_R22: mipscpu.r[ 22 ] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_R23: mipscpu.r[ 23 ] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_R24: mipscpu.r[ 24 ] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_R25: mipscpu.r[ 25 ] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_R26: mipscpu.r[ 26 ] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_R27: mipscpu.r[ 27 ] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_R28: mipscpu.r[ 28 ] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_R29: mipscpu.r[ 29 ] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_R30: mipscpu.r[ 30 ] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_R31: mipscpu.r[ 31 ] = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP0R0: mips_set_cp0r( 0, info->i ); break; - case CPUINFO_INT_REGISTER + MIPS_CP0R1: mips_set_cp0r( 1, info->i ); break; - case CPUINFO_INT_REGISTER + MIPS_CP0R2: mips_set_cp0r( 2, info->i ); break; - case CPUINFO_INT_REGISTER + MIPS_CP0R3: mips_set_cp0r( 3, info->i ); break; - case CPUINFO_INT_REGISTER + MIPS_CP0R4: mips_set_cp0r( 4, info->i ); break; - case CPUINFO_INT_REGISTER + MIPS_CP0R5: mips_set_cp0r( 5, info->i ); break; - case CPUINFO_INT_REGISTER + MIPS_CP0R6: mips_set_cp0r( 6, info->i ); break; - case CPUINFO_INT_REGISTER + MIPS_CP0R7: mips_set_cp0r( 7, info->i ); break; - case CPUINFO_INT_REGISTER + MIPS_CP0R8: mips_set_cp0r( 8, info->i ); break; - case CPUINFO_INT_REGISTER + MIPS_CP0R9: mips_set_cp0r( 9, info->i ); break; - case CPUINFO_INT_REGISTER + MIPS_CP0R10: mips_set_cp0r( 10, info->i ); break; - case CPUINFO_INT_REGISTER + MIPS_CP0R11: mips_set_cp0r( 11, info->i ); break; - case CPUINFO_INT_REGISTER + MIPS_CP0R12: mips_set_cp0r( 12, info->i ); break; - case CPUINFO_INT_REGISTER + MIPS_CP0R13: mips_set_cp0r( 13, info->i ); break; - case CPUINFO_INT_REGISTER + MIPS_CP0R14: mips_set_cp0r( 14, info->i ); break; - case CPUINFO_INT_REGISTER + MIPS_CP0R15: mips_set_cp0r( 15, info->i ); break; - case CPUINFO_INT_REGISTER + MIPS_CP0R16: mips_set_cp0r( 16, info->i ); break; - case CPUINFO_INT_REGISTER + MIPS_CP0R17: mips_set_cp0r( 17, info->i ); break; - case CPUINFO_INT_REGISTER + MIPS_CP0R18: mips_set_cp0r( 18, info->i ); break; - case CPUINFO_INT_REGISTER + MIPS_CP0R19: mips_set_cp0r( 19, info->i ); break; - case CPUINFO_INT_REGISTER + MIPS_CP0R20: mips_set_cp0r( 20, info->i ); break; - case CPUINFO_INT_REGISTER + MIPS_CP0R21: mips_set_cp0r( 21, info->i ); break; - case CPUINFO_INT_REGISTER + MIPS_CP0R22: mips_set_cp0r( 22, info->i ); break; - case CPUINFO_INT_REGISTER + MIPS_CP0R23: mips_set_cp0r( 23, info->i ); break; - case CPUINFO_INT_REGISTER + MIPS_CP0R24: mips_set_cp0r( 24, info->i ); break; - case CPUINFO_INT_REGISTER + MIPS_CP0R25: mips_set_cp0r( 25, info->i ); break; - case CPUINFO_INT_REGISTER + MIPS_CP0R26: mips_set_cp0r( 26, info->i ); break; - case CPUINFO_INT_REGISTER + MIPS_CP0R27: mips_set_cp0r( 27, info->i ); break; - case CPUINFO_INT_REGISTER + MIPS_CP0R28: mips_set_cp0r( 28, info->i ); break; - case CPUINFO_INT_REGISTER + MIPS_CP0R29: mips_set_cp0r( 29, info->i ); break; - case CPUINFO_INT_REGISTER + MIPS_CP0R30: mips_set_cp0r( 30, info->i ); break; - case CPUINFO_INT_REGISTER + MIPS_CP0R31: mips_set_cp0r( 31, info->i ); break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR0: mipscpu.cp2dr[ 0 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR1: mipscpu.cp2dr[ 1 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR2: mipscpu.cp2dr[ 2 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR3: mipscpu.cp2dr[ 3 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR4: mipscpu.cp2dr[ 4 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR5: mipscpu.cp2dr[ 5 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR6: mipscpu.cp2dr[ 6 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR7: mipscpu.cp2dr[ 7 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR8: mipscpu.cp2dr[ 8 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR9: mipscpu.cp2dr[ 9 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR10: mipscpu.cp2dr[ 10 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR11: mipscpu.cp2dr[ 11 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR12: mipscpu.cp2dr[ 12 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR13: mipscpu.cp2dr[ 13 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR14: mipscpu.cp2dr[ 14 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR15: mipscpu.cp2dr[ 15 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR16: mipscpu.cp2dr[ 16 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR17: mipscpu.cp2dr[ 17 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR18: mipscpu.cp2dr[ 18 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR19: mipscpu.cp2dr[ 19 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR20: mipscpu.cp2dr[ 20 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR21: mipscpu.cp2dr[ 21 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR22: mipscpu.cp2dr[ 22 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR23: mipscpu.cp2dr[ 23 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR24: mipscpu.cp2dr[ 24 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR25: mipscpu.cp2dr[ 25 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR26: mipscpu.cp2dr[ 26 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR27: mipscpu.cp2dr[ 27 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR28: mipscpu.cp2dr[ 28 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR29: mipscpu.cp2dr[ 29 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR30: mipscpu.cp2dr[ 30 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR31: mipscpu.cp2dr[ 31 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR0: mipscpu.cp2cr[ 0 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR1: mipscpu.cp2cr[ 1 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR2: mipscpu.cp2cr[ 2 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR3: mipscpu.cp2cr[ 3 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR4: mipscpu.cp2cr[ 4 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR5: mipscpu.cp2cr[ 5 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR6: mipscpu.cp2cr[ 6 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR7: mipscpu.cp2cr[ 7 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR8: mipscpu.cp2cr[ 8 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR9: mipscpu.cp2cr[ 9 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR10: mipscpu.cp2cr[ 10 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR11: mipscpu.cp2cr[ 11 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR12: mipscpu.cp2cr[ 12 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR13: mipscpu.cp2cr[ 13 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR14: mipscpu.cp2cr[ 14 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR15: mipscpu.cp2cr[ 15 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR16: mipscpu.cp2cr[ 16 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR17: mipscpu.cp2cr[ 17 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR18: mipscpu.cp2cr[ 18 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR19: mipscpu.cp2cr[ 19 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR20: mipscpu.cp2cr[ 20 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR21: mipscpu.cp2cr[ 21 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR22: mipscpu.cp2cr[ 22 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR23: mipscpu.cp2cr[ 23 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR24: mipscpu.cp2cr[ 24 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR25: mipscpu.cp2cr[ 25 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR26: mipscpu.cp2cr[ 26 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR27: mipscpu.cp2cr[ 27 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR28: mipscpu.cp2cr[ 28 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR29: mipscpu.cp2cr[ 29 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR30: mipscpu.cp2cr[ 30 ].d = info->i; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR31: mipscpu.cp2cr[ 31 ].d = info->i; break; - - /* --- the following bits of info are set as pointers to data or functions --- */ - case CPUINFO_PTR_IRQ_CALLBACK: mipscpu.irq_callback = info->irqcallback; break; - } -} - - - -/************************************************************************** - * Generic get_info - **************************************************************************/ - -void mips_get_info(UINT32 state, union cpuinfo *info) -{ - switch (state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(mipscpu); break; - case CPUINFO_INT_INPUT_LINES: info->i = 6; break; - case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break; - case CPUINFO_INT_ENDIANNESS: info->i = CPU_IS_LE; break; - case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break; - case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 4; break; - case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 4; break; - case CPUINFO_INT_MIN_CYCLES: info->i = 1; break; - case CPUINFO_INT_MAX_CYCLES: info->i = 40; break; - - case CPUINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_PROGRAM: info->i = 32; break; - case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_PROGRAM: info->i = 32; break; - case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_PROGRAM: info->i = 0; break; - case CPUINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_DATA: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_DATA: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_DATA: info->i = 0; break; - case CPUINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_IO: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_IO: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_IO: info->i = 0; break; - - case CPUINFO_INT_INPUT_STATE + MIPS_IRQ0: info->i = (mipscpu.cp0r[ CP0_CAUSE ] & 0x400) ? ASSERT_LINE : CLEAR_LINE; break; - case CPUINFO_INT_INPUT_STATE + MIPS_IRQ1: info->i = (mipscpu.cp0r[ CP0_CAUSE ] & 0x800) ? ASSERT_LINE : CLEAR_LINE; break; - case CPUINFO_INT_INPUT_STATE + MIPS_IRQ2: info->i = (mipscpu.cp0r[ CP0_CAUSE ] & 0x1000) ? ASSERT_LINE : CLEAR_LINE; break; - case CPUINFO_INT_INPUT_STATE + MIPS_IRQ3: info->i = (mipscpu.cp0r[ CP0_CAUSE ] & 0x2000) ? ASSERT_LINE : CLEAR_LINE; break; - case CPUINFO_INT_INPUT_STATE + MIPS_IRQ4: info->i = (mipscpu.cp0r[ CP0_CAUSE ] & 0x4000) ? ASSERT_LINE : CLEAR_LINE; break; - case CPUINFO_INT_INPUT_STATE + MIPS_IRQ5: info->i = (mipscpu.cp0r[ CP0_CAUSE ] & 0x8000) ? ASSERT_LINE : CLEAR_LINE; break; - - case CPUINFO_INT_PREVIOUSPC: /* not implemented */ break; - - case CPUINFO_INT_PC: info->i = mipscpu.pc; break; - case CPUINFO_INT_REGISTER + MIPS_PC: info->i = mipscpu.pc; break; - case CPUINFO_INT_SP: - /* because there is no hardware stack and the pipeline causes the cpu to execute the - instruction after a subroutine call before the subroutine is executed there is little - chance of cmd_step_over() in mamedbg.c working. */ - info->i = 0; break; - case CPUINFO_INT_REGISTER + MIPS_DELAYV: info->i = mipscpu.delayv; break; - case CPUINFO_INT_REGISTER + MIPS_DELAYR: info->i = mipscpu.delayr; break; - case CPUINFO_INT_REGISTER + MIPS_HI: info->i = mipscpu.hi; break; - case CPUINFO_INT_REGISTER + MIPS_LO: info->i = mipscpu.lo; break; - case CPUINFO_INT_REGISTER + MIPS_R0: info->i = mipscpu.r[ 0 ]; break; - case CPUINFO_INT_REGISTER + MIPS_R1: info->i = mipscpu.r[ 1 ]; break; - case CPUINFO_INT_REGISTER + MIPS_R2: info->i = mipscpu.r[ 2 ]; break; - case CPUINFO_INT_REGISTER + MIPS_R3: info->i = mipscpu.r[ 3 ]; break; - case CPUINFO_INT_REGISTER + MIPS_R4: info->i = mipscpu.r[ 4 ]; break; - case CPUINFO_INT_REGISTER + MIPS_R5: info->i = mipscpu.r[ 5 ]; break; - case CPUINFO_INT_REGISTER + MIPS_R6: info->i = mipscpu.r[ 6 ]; break; - case CPUINFO_INT_REGISTER + MIPS_R7: info->i = mipscpu.r[ 7 ]; break; - case CPUINFO_INT_REGISTER + MIPS_R8: info->i = mipscpu.r[ 8 ]; break; - case CPUINFO_INT_REGISTER + MIPS_R9: info->i = mipscpu.r[ 9 ]; break; - case CPUINFO_INT_REGISTER + MIPS_R10: info->i = mipscpu.r[ 10 ]; break; - case CPUINFO_INT_REGISTER + MIPS_R11: info->i = mipscpu.r[ 11 ]; break; - case CPUINFO_INT_REGISTER + MIPS_R12: info->i = mipscpu.r[ 12 ]; break; - case CPUINFO_INT_REGISTER + MIPS_R13: info->i = mipscpu.r[ 13 ]; break; - case CPUINFO_INT_REGISTER + MIPS_R14: info->i = mipscpu.r[ 14 ]; break; - case CPUINFO_INT_REGISTER + MIPS_R15: info->i = mipscpu.r[ 15 ]; break; - case CPUINFO_INT_REGISTER + MIPS_R16: info->i = mipscpu.r[ 16 ]; break; - case CPUINFO_INT_REGISTER + MIPS_R17: info->i = mipscpu.r[ 17 ]; break; - case CPUINFO_INT_REGISTER + MIPS_R18: info->i = mipscpu.r[ 18 ]; break; - case CPUINFO_INT_REGISTER + MIPS_R19: info->i = mipscpu.r[ 19 ]; break; - case CPUINFO_INT_REGISTER + MIPS_R20: info->i = mipscpu.r[ 20 ]; break; - case CPUINFO_INT_REGISTER + MIPS_R21: info->i = mipscpu.r[ 21 ]; break; - case CPUINFO_INT_REGISTER + MIPS_R22: info->i = mipscpu.r[ 22 ]; break; - case CPUINFO_INT_REGISTER + MIPS_R23: info->i = mipscpu.r[ 23 ]; break; - case CPUINFO_INT_REGISTER + MIPS_R24: info->i = mipscpu.r[ 24 ]; break; - case CPUINFO_INT_REGISTER + MIPS_R25: info->i = mipscpu.r[ 25 ]; break; - case CPUINFO_INT_REGISTER + MIPS_R26: info->i = mipscpu.r[ 26 ]; break; - case CPUINFO_INT_REGISTER + MIPS_R27: info->i = mipscpu.r[ 27 ]; break; - case CPUINFO_INT_REGISTER + MIPS_R28: info->i = mipscpu.r[ 28 ]; break; - case CPUINFO_INT_REGISTER + MIPS_R29: info->i = mipscpu.r[ 29 ]; break; - case CPUINFO_INT_REGISTER + MIPS_R30: info->i = mipscpu.r[ 30 ]; break; - case CPUINFO_INT_REGISTER + MIPS_R31: info->i = mipscpu.r[ 31 ]; break; - case CPUINFO_INT_REGISTER + MIPS_CP0R0: info->i = mipscpu.cp0r[ 0 ]; break; - case CPUINFO_INT_REGISTER + MIPS_CP0R1: info->i = mipscpu.cp0r[ 1 ]; break; - case CPUINFO_INT_REGISTER + MIPS_CP0R2: info->i = mipscpu.cp0r[ 2 ]; break; - case CPUINFO_INT_REGISTER + MIPS_CP0R3: info->i = mipscpu.cp0r[ 3 ]; break; - case CPUINFO_INT_REGISTER + MIPS_CP0R4: info->i = mipscpu.cp0r[ 4 ]; break; - case CPUINFO_INT_REGISTER + MIPS_CP0R5: info->i = mipscpu.cp0r[ 5 ]; break; - case CPUINFO_INT_REGISTER + MIPS_CP0R6: info->i = mipscpu.cp0r[ 6 ]; break; - case CPUINFO_INT_REGISTER + MIPS_CP0R7: info->i = mipscpu.cp0r[ 7 ]; break; - case CPUINFO_INT_REGISTER + MIPS_CP0R8: info->i = mipscpu.cp0r[ 8 ]; break; - case CPUINFO_INT_REGISTER + MIPS_CP0R9: info->i = mipscpu.cp0r[ 9 ]; break; - case CPUINFO_INT_REGISTER + MIPS_CP0R10: info->i = mipscpu.cp0r[ 10 ]; break; - case CPUINFO_INT_REGISTER + MIPS_CP0R11: info->i = mipscpu.cp0r[ 11 ]; break; - case CPUINFO_INT_REGISTER + MIPS_CP0R12: info->i = mipscpu.cp0r[ 12 ]; break; - case CPUINFO_INT_REGISTER + MIPS_CP0R13: info->i = mipscpu.cp0r[ 13 ]; break; - case CPUINFO_INT_REGISTER + MIPS_CP0R14: info->i = mipscpu.cp0r[ 14 ]; break; - case CPUINFO_INT_REGISTER + MIPS_CP0R15: info->i = mipscpu.cp0r[ 15 ]; break; - case CPUINFO_INT_REGISTER + MIPS_CP0R16: info->i = mipscpu.cp0r[ 16 ]; break; - case CPUINFO_INT_REGISTER + MIPS_CP0R17: info->i = mipscpu.cp0r[ 17 ]; break; - case CPUINFO_INT_REGISTER + MIPS_CP0R18: info->i = mipscpu.cp0r[ 18 ]; break; - case CPUINFO_INT_REGISTER + MIPS_CP0R19: info->i = mipscpu.cp0r[ 19 ]; break; - case CPUINFO_INT_REGISTER + MIPS_CP0R20: info->i = mipscpu.cp0r[ 20 ]; break; - case CPUINFO_INT_REGISTER + MIPS_CP0R21: info->i = mipscpu.cp0r[ 21 ]; break; - case CPUINFO_INT_REGISTER + MIPS_CP0R22: info->i = mipscpu.cp0r[ 22 ]; break; - case CPUINFO_INT_REGISTER + MIPS_CP0R23: info->i = mipscpu.cp0r[ 23 ]; break; - case CPUINFO_INT_REGISTER + MIPS_CP0R24: info->i = mipscpu.cp0r[ 24 ]; break; - case CPUINFO_INT_REGISTER + MIPS_CP0R25: info->i = mipscpu.cp0r[ 25 ]; break; - case CPUINFO_INT_REGISTER + MIPS_CP0R26: info->i = mipscpu.cp0r[ 26 ]; break; - case CPUINFO_INT_REGISTER + MIPS_CP0R27: info->i = mipscpu.cp0r[ 27 ]; break; - case CPUINFO_INT_REGISTER + MIPS_CP0R28: info->i = mipscpu.cp0r[ 28 ]; break; - case CPUINFO_INT_REGISTER + MIPS_CP0R29: info->i = mipscpu.cp0r[ 29 ]; break; - case CPUINFO_INT_REGISTER + MIPS_CP0R30: info->i = mipscpu.cp0r[ 30 ]; break; - case CPUINFO_INT_REGISTER + MIPS_CP0R31: info->i = mipscpu.cp0r[ 31 ]; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR0: info->i = mipscpu.cp2dr[ 0 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR1: info->i = mipscpu.cp2dr[ 1 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR2: info->i = mipscpu.cp2dr[ 2 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR3: info->i = mipscpu.cp2dr[ 3 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR4: info->i = mipscpu.cp2dr[ 4 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR5: info->i = mipscpu.cp2dr[ 5 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR6: info->i = mipscpu.cp2dr[ 6 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR7: info->i = mipscpu.cp2dr[ 7 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR8: info->i = mipscpu.cp2dr[ 8 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR9: info->i = mipscpu.cp2dr[ 9 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR10: info->i = mipscpu.cp2dr[ 10 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR11: info->i = mipscpu.cp2dr[ 11 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR12: info->i = mipscpu.cp2dr[ 12 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR13: info->i = mipscpu.cp2dr[ 13 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR14: info->i = mipscpu.cp2dr[ 14 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR15: info->i = mipscpu.cp2dr[ 15 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR16: info->i = mipscpu.cp2dr[ 16 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR17: info->i = mipscpu.cp2dr[ 17 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR18: info->i = mipscpu.cp2dr[ 18 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR19: info->i = mipscpu.cp2dr[ 19 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR20: info->i = mipscpu.cp2dr[ 20 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR21: info->i = mipscpu.cp2dr[ 21 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR22: info->i = mipscpu.cp2dr[ 22 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR23: info->i = mipscpu.cp2dr[ 23 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR24: info->i = mipscpu.cp2dr[ 24 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR25: info->i = mipscpu.cp2dr[ 25 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR26: info->i = mipscpu.cp2dr[ 26 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR27: info->i = mipscpu.cp2dr[ 27 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR28: info->i = mipscpu.cp2dr[ 28 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR29: info->i = mipscpu.cp2dr[ 29 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR30: info->i = mipscpu.cp2dr[ 30 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2DR31: info->i = mipscpu.cp2dr[ 31 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR0: info->i = mipscpu.cp2cr[ 0 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR1: info->i = mipscpu.cp2cr[ 1 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR2: info->i = mipscpu.cp2cr[ 2 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR3: info->i = mipscpu.cp2cr[ 3 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR4: info->i = mipscpu.cp2cr[ 4 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR5: info->i = mipscpu.cp2cr[ 5 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR6: info->i = mipscpu.cp2cr[ 6 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR7: info->i = mipscpu.cp2cr[ 7 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR8: info->i = mipscpu.cp2cr[ 8 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR9: info->i = mipscpu.cp2cr[ 9 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR10: info->i = mipscpu.cp2cr[ 10 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR11: info->i = mipscpu.cp2cr[ 11 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR12: info->i = mipscpu.cp2cr[ 12 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR13: info->i = mipscpu.cp2cr[ 13 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR14: info->i = mipscpu.cp2cr[ 14 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR15: info->i = mipscpu.cp2cr[ 15 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR16: info->i = mipscpu.cp2cr[ 16 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR17: info->i = mipscpu.cp2cr[ 17 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR18: info->i = mipscpu.cp2cr[ 18 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR19: info->i = mipscpu.cp2cr[ 19 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR20: info->i = mipscpu.cp2cr[ 20 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR21: info->i = mipscpu.cp2cr[ 21 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR22: info->i = mipscpu.cp2cr[ 22 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR23: info->i = mipscpu.cp2cr[ 23 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR24: info->i = mipscpu.cp2cr[ 24 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR25: info->i = mipscpu.cp2cr[ 25 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR26: info->i = mipscpu.cp2cr[ 26 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR27: info->i = mipscpu.cp2cr[ 27 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR28: info->i = mipscpu.cp2cr[ 28 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR29: info->i = mipscpu.cp2cr[ 29 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR30: info->i = mipscpu.cp2cr[ 30 ].d; break; - case CPUINFO_INT_REGISTER + MIPS_CP2CR31: info->i = mipscpu.cp2cr[ 31 ].d; break; - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_PTR_SET_INFO: info->setinfo = mips_set_info; break; - case CPUINFO_PTR_GET_CONTEXT: info->getcontext = mips_get_context; break; - case CPUINFO_PTR_SET_CONTEXT: info->setcontext = mips_set_context; break; - case CPUINFO_PTR_INIT: info->init = mips_init; break; - case CPUINFO_PTR_RESET: info->reset = mips_reset; break; - case CPUINFO_PTR_EXIT: info->exit = mips_exit; break; - case CPUINFO_PTR_EXECUTE: info->execute = mips_execute; break; - case CPUINFO_PTR_BURN: info->burn = NULL; break; - case CPUINFO_PTR_DISASSEMBLE: info->disassemble = mips_dasm; break; - case CPUINFO_PTR_IRQ_CALLBACK: info->irqcallback = mipscpu.irq_callback; break; - case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &mips_ICount; break; - case CPUINFO_PTR_REGISTER_LAYOUT: info->p = mips_reg_layout; break; - case CPUINFO_PTR_WINDOW_LAYOUT: info->p = mips_win_layout; break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ -#if 0 - case CPUINFO_STR_NAME: strcpy(info->s = cpuintrf_temp_str(), "PSX CPU"); break; - case CPUINFO_STR_CORE_FAMILY: strcpy(info->s = cpuintrf_temp_str(), "mipscpu"); break; - case CPUINFO_STR_CORE_VERSION: strcpy(info->s = cpuintrf_temp_str(), "1.4"); break; - case CPUINFO_STR_CORE_FILE: strcpy(info->s = cpuintrf_temp_str(), __FILE__); break; - case CPUINFO_STR_CORE_CREDITS: strcpy(info->s = cpuintrf_temp_str(), "Copyright 2003 smf"); break; - - case CPUINFO_STR_FLAGS: strcpy(info->s = cpuintrf_temp_str(), " "); break; - - case CPUINFO_STR_REGISTER + MIPS_PC: sprintf( info->s = cpuintrf_temp_str(), "pc :%08x", mipscpu.pc ); break; - case CPUINFO_STR_REGISTER + MIPS_DELAYV: sprintf( info->s = cpuintrf_temp_str(), "delay :%08x", mipscpu.delayv ); break; - case CPUINFO_STR_REGISTER + MIPS_DELAYR: sprintf( info->s = cpuintrf_temp_str(), "delay %s:%02x", delayn[ mipscpu.delayr ], mipscpu.delayr ); break; - case CPUINFO_STR_REGISTER + MIPS_HI: sprintf( info->s = cpuintrf_temp_str(), "hi :%08x", mipscpu.hi ); break; - case CPUINFO_STR_REGISTER + MIPS_LO: sprintf( info->s = cpuintrf_temp_str(), "lo :%08x", mipscpu.lo ); break; - case CPUINFO_STR_REGISTER + MIPS_R0: sprintf( info->s = cpuintrf_temp_str(), "zero :%08x", mipscpu.r[ 0 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_R1: sprintf( info->s = cpuintrf_temp_str(), "at :%08x", mipscpu.r[ 1 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_R2: sprintf( info->s = cpuintrf_temp_str(), "v0 :%08x", mipscpu.r[ 2 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_R3: sprintf( info->s = cpuintrf_temp_str(), "v1 :%08x", mipscpu.r[ 3 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_R4: sprintf( info->s = cpuintrf_temp_str(), "a0 :%08x", mipscpu.r[ 4 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_R5: sprintf( info->s = cpuintrf_temp_str(), "a1 :%08x", mipscpu.r[ 5 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_R6: sprintf( info->s = cpuintrf_temp_str(), "a2 :%08x", mipscpu.r[ 6 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_R7: sprintf( info->s = cpuintrf_temp_str(), "a3 :%08x", mipscpu.r[ 7 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_R8: sprintf( info->s = cpuintrf_temp_str(), "t0 :%08x", mipscpu.r[ 8 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_R9: sprintf( info->s = cpuintrf_temp_str(), "t1 :%08x", mipscpu.r[ 9 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_R10: sprintf( info->s = cpuintrf_temp_str(), "t2 :%08x", mipscpu.r[ 10 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_R11: sprintf( info->s = cpuintrf_temp_str(), "t3 :%08x", mipscpu.r[ 11 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_R12: sprintf( info->s = cpuintrf_temp_str(), "t4 :%08x", mipscpu.r[ 12 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_R13: sprintf( info->s = cpuintrf_temp_str(), "t5 :%08x", mipscpu.r[ 13 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_R14: sprintf( info->s = cpuintrf_temp_str(), "t6 :%08x", mipscpu.r[ 14 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_R15: sprintf( info->s = cpuintrf_temp_str(), "t7 :%08x", mipscpu.r[ 15 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_R16: sprintf( info->s = cpuintrf_temp_str(), "s0 :%08x", mipscpu.r[ 16 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_R17: sprintf( info->s = cpuintrf_temp_str(), "s1 :%08x", mipscpu.r[ 17 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_R18: sprintf( info->s = cpuintrf_temp_str(), "s2 :%08x", mipscpu.r[ 18 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_R19: sprintf( info->s = cpuintrf_temp_str(), "s3 :%08x", mipscpu.r[ 19 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_R20: sprintf( info->s = cpuintrf_temp_str(), "s4 :%08x", mipscpu.r[ 20 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_R21: sprintf( info->s = cpuintrf_temp_str(), "s5 :%08x", mipscpu.r[ 21 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_R22: sprintf( info->s = cpuintrf_temp_str(), "s6 :%08x", mipscpu.r[ 22 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_R23: sprintf( info->s = cpuintrf_temp_str(), "s7 :%08x", mipscpu.r[ 23 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_R24: sprintf( info->s = cpuintrf_temp_str(), "t8 :%08x", mipscpu.r[ 24 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_R25: sprintf( info->s = cpuintrf_temp_str(), "t9 :%08x", mipscpu.r[ 25 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_R26: sprintf( info->s = cpuintrf_temp_str(), "k0 :%08x", mipscpu.r[ 26 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_R27: sprintf( info->s = cpuintrf_temp_str(), "k1 :%08x", mipscpu.r[ 27 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_R28: sprintf( info->s = cpuintrf_temp_str(), "gp :%08x", mipscpu.r[ 28 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_R29: sprintf( info->s = cpuintrf_temp_str(), "sp :%08x", mipscpu.r[ 29 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_R30: sprintf( info->s = cpuintrf_temp_str(), "fp :%08x", mipscpu.r[ 30 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_R31: sprintf( info->s = cpuintrf_temp_str(), "ra :%08x", mipscpu.r[ 31 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_CP0R0: sprintf( info->s = cpuintrf_temp_str(), "Index :%08x", mipscpu.cp0r[ 0 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_CP0R1: sprintf( info->s = cpuintrf_temp_str(), "Random :%08x", mipscpu.cp0r[ 1 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_CP0R2: sprintf( info->s = cpuintrf_temp_str(), "EntryLo :%08x", mipscpu.cp0r[ 2 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_CP0R3: sprintf( info->s = cpuintrf_temp_str(), "cp0r3 :%08x", mipscpu.cp0r[ 3 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_CP0R4: sprintf( info->s = cpuintrf_temp_str(), "Context :%08x", mipscpu.cp0r[ 4 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_CP0R5: sprintf( info->s = cpuintrf_temp_str(), "cp0r5 :%08x", mipscpu.cp0r[ 5 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_CP0R6: sprintf( info->s = cpuintrf_temp_str(), "cp0r6 :%08x", mipscpu.cp0r[ 6 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_CP0R7: sprintf( info->s = cpuintrf_temp_str(), "cp0r7 :%08x", mipscpu.cp0r[ 7 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_CP0R8: sprintf( info->s = cpuintrf_temp_str(), "BadVAddr:%08x", mipscpu.cp0r[ 8 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_CP0R9: sprintf( info->s = cpuintrf_temp_str(), "cp0r9 :%08x", mipscpu.cp0r[ 9 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_CP0R10: sprintf( info->s = cpuintrf_temp_str(), "EntryHi :%08x", mipscpu.cp0r[ 10 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_CP0R11: sprintf( info->s = cpuintrf_temp_str(), "cp0r11 :%08x", mipscpu.cp0r[ 11 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_CP0R12: sprintf( info->s = cpuintrf_temp_str(), "SR :%08x", mipscpu.cp0r[ 12 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_CP0R13: sprintf( info->s = cpuintrf_temp_str(), "Cause :%08x", mipscpu.cp0r[ 13 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_CP0R14: sprintf( info->s = cpuintrf_temp_str(), "EPC :%08x", mipscpu.cp0r[ 14 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_CP0R15: sprintf( info->s = cpuintrf_temp_str(), "PRId :%08x", mipscpu.cp0r[ 15 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_CP0R16: sprintf( info->s = cpuintrf_temp_str(), "cp0r16 :%08x", mipscpu.cp0r[ 16 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_CP0R17: sprintf( info->s = cpuintrf_temp_str(), "cp0r17 :%08x", mipscpu.cp0r[ 17 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_CP0R18: sprintf( info->s = cpuintrf_temp_str(), "cp0r18 :%08x", mipscpu.cp0r[ 18 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_CP0R19: sprintf( info->s = cpuintrf_temp_str(), "cp0r19 :%08x", mipscpu.cp0r[ 19 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_CP0R20: sprintf( info->s = cpuintrf_temp_str(), "cp0r20 :%08x", mipscpu.cp0r[ 20 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_CP0R21: sprintf( info->s = cpuintrf_temp_str(), "cp0r21 :%08x", mipscpu.cp0r[ 21 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_CP0R22: sprintf( info->s = cpuintrf_temp_str(), "cp0r22 :%08x", mipscpu.cp0r[ 22 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_CP0R23: sprintf( info->s = cpuintrf_temp_str(), "cp0r23 :%08x", mipscpu.cp0r[ 23 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_CP0R24: sprintf( info->s = cpuintrf_temp_str(), "cp0r24 :%08x", mipscpu.cp0r[ 24 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_CP0R25: sprintf( info->s = cpuintrf_temp_str(), "cp0r25 :%08x", mipscpu.cp0r[ 25 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_CP0R26: sprintf( info->s = cpuintrf_temp_str(), "cp0r26 :%08x", mipscpu.cp0r[ 26 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_CP0R27: sprintf( info->s = cpuintrf_temp_str(), "cp0r27 :%08x", mipscpu.cp0r[ 27 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_CP0R28: sprintf( info->s = cpuintrf_temp_str(), "cp0r28 :%08x", mipscpu.cp0r[ 28 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_CP0R29: sprintf( info->s = cpuintrf_temp_str(), "cp0r29 :%08x", mipscpu.cp0r[ 29 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_CP0R30: sprintf( info->s = cpuintrf_temp_str(), "cp0r30 :%08x", mipscpu.cp0r[ 30 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_CP0R31: sprintf( info->s = cpuintrf_temp_str(), "cp0r31 :%08x", mipscpu.cp0r[ 31 ] ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2DR0: sprintf( info->s = cpuintrf_temp_str(), "vxy0 :%08x", mipscpu.cp2dr[ 0 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2DR1: sprintf( info->s = cpuintrf_temp_str(), "vz0 :%08x", mipscpu.cp2dr[ 1 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2DR2: sprintf( info->s = cpuintrf_temp_str(), "vxy1 :%08x", mipscpu.cp2dr[ 2 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2DR3: sprintf( info->s = cpuintrf_temp_str(), "vz1 :%08x", mipscpu.cp2dr[ 3 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2DR4: sprintf( info->s = cpuintrf_temp_str(), "vxy2 :%08x", mipscpu.cp2dr[ 4 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2DR5: sprintf( info->s = cpuintrf_temp_str(), "vz2 :%08x", mipscpu.cp2dr[ 5 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2DR6: sprintf( info->s = cpuintrf_temp_str(), "rgb :%08x", mipscpu.cp2dr[ 6 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2DR7: sprintf( info->s = cpuintrf_temp_str(), "otz :%08x", mipscpu.cp2dr[ 7 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2DR8: sprintf( info->s = cpuintrf_temp_str(), "ir0 :%08x", mipscpu.cp2dr[ 8 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2DR9: sprintf( info->s = cpuintrf_temp_str(), "ir1 :%08x", mipscpu.cp2dr[ 9 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2DR10: sprintf( info->s = cpuintrf_temp_str(), "ir2 :%08x", mipscpu.cp2dr[ 10 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2DR11: sprintf( info->s = cpuintrf_temp_str(), "ir3 :%08x", mipscpu.cp2dr[ 11 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2DR12: sprintf( info->s = cpuintrf_temp_str(), "sxy0 :%08x", mipscpu.cp2dr[ 12 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2DR13: sprintf( info->s = cpuintrf_temp_str(), "sxy1 :%08x", mipscpu.cp2dr[ 13 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2DR14: sprintf( info->s = cpuintrf_temp_str(), "sxy2 :%08x", mipscpu.cp2dr[ 14 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2DR15: sprintf( info->s = cpuintrf_temp_str(), "sxyp :%08x", mipscpu.cp2dr[ 15 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2DR16: sprintf( info->s = cpuintrf_temp_str(), "sz0 :%08x", mipscpu.cp2dr[ 16 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2DR17: sprintf( info->s = cpuintrf_temp_str(), "sz1 :%08x", mipscpu.cp2dr[ 17 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2DR18: sprintf( info->s = cpuintrf_temp_str(), "sz2 :%08x", mipscpu.cp2dr[ 18 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2DR19: sprintf( info->s = cpuintrf_temp_str(), "sz3 :%08x", mipscpu.cp2dr[ 19 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2DR20: sprintf( info->s = cpuintrf_temp_str(), "rgb0 :%08x", mipscpu.cp2dr[ 20 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2DR21: sprintf( info->s = cpuintrf_temp_str(), "rgb1 :%08x", mipscpu.cp2dr[ 21 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2DR22: sprintf( info->s = cpuintrf_temp_str(), "rgb2 :%08x", mipscpu.cp2dr[ 22 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2DR23: sprintf( info->s = cpuintrf_temp_str(), "res1 :%08x", mipscpu.cp2dr[ 23 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2DR24: sprintf( info->s = cpuintrf_temp_str(), "mac0 :%08x", mipscpu.cp2dr[ 24 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2DR25: sprintf( info->s = cpuintrf_temp_str(), "mac1 :%08x", mipscpu.cp2dr[ 25 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2DR26: sprintf( info->s = cpuintrf_temp_str(), "mac2 :%08x", mipscpu.cp2dr[ 26 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2DR27: sprintf( info->s = cpuintrf_temp_str(), "mac3 :%08x", mipscpu.cp2dr[ 27 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2DR28: sprintf( info->s = cpuintrf_temp_str(), "irgb :%08x", mipscpu.cp2dr[ 28 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2DR29: sprintf( info->s = cpuintrf_temp_str(), "orgb :%08x", mipscpu.cp2dr[ 29 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2DR30: sprintf( info->s = cpuintrf_temp_str(), "lzcs :%08x", mipscpu.cp2dr[ 30 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2DR31: sprintf( info->s = cpuintrf_temp_str(), "lzcr :%08x", mipscpu.cp2dr[ 31 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2CR0: sprintf( info->s = cpuintrf_temp_str(), "r11r12 :%08x", mipscpu.cp2cr[ 0 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2CR1: sprintf( info->s = cpuintrf_temp_str(), "r13r21 :%08x", mipscpu.cp2cr[ 1 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2CR2: sprintf( info->s = cpuintrf_temp_str(), "r22r23 :%08x", mipscpu.cp2cr[ 2 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2CR3: sprintf( info->s = cpuintrf_temp_str(), "r31r32 :%08x", mipscpu.cp2cr[ 3 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2CR4: sprintf( info->s = cpuintrf_temp_str(), "r33 :%08x", mipscpu.cp2cr[ 4 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2CR5: sprintf( info->s = cpuintrf_temp_str(), "trx :%08x", mipscpu.cp2cr[ 5 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2CR6: sprintf( info->s = cpuintrf_temp_str(), "try :%08x", mipscpu.cp2cr[ 6 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2CR7: sprintf( info->s = cpuintrf_temp_str(), "trz :%08x", mipscpu.cp2cr[ 7 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2CR8: sprintf( info->s = cpuintrf_temp_str(), "l11l12 :%08x", mipscpu.cp2cr[ 8 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2CR9: sprintf( info->s = cpuintrf_temp_str(), "l13l21 :%08x", mipscpu.cp2cr[ 9 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2CR10: sprintf( info->s = cpuintrf_temp_str(), "l22l23 :%08x", mipscpu.cp2cr[ 10 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2CR11: sprintf( info->s = cpuintrf_temp_str(), "l31l32 :%08x", mipscpu.cp2cr[ 11 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2CR12: sprintf( info->s = cpuintrf_temp_str(), "l33 :%08x", mipscpu.cp2cr[ 12 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2CR13: sprintf( info->s = cpuintrf_temp_str(), "rbk :%08x", mipscpu.cp2cr[ 13 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2CR14: sprintf( info->s = cpuintrf_temp_str(), "gbk :%08x", mipscpu.cp2cr[ 14 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2CR15: sprintf( info->s = cpuintrf_temp_str(), "bbk :%08x", mipscpu.cp2cr[ 15 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2CR16: sprintf( info->s = cpuintrf_temp_str(), "lr1lr2 :%08x", mipscpu.cp2cr[ 16 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2CR17: sprintf( info->s = cpuintrf_temp_str(), "lr31g1 :%08x", mipscpu.cp2cr[ 17 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2CR18: sprintf( info->s = cpuintrf_temp_str(), "lg2lg3 :%08x", mipscpu.cp2cr[ 18 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2CR19: sprintf( info->s = cpuintrf_temp_str(), "lb1lb2 :%08x", mipscpu.cp2cr[ 19 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2CR20: sprintf( info->s = cpuintrf_temp_str(), "lb3 :%08x", mipscpu.cp2cr[ 20 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2CR21: sprintf( info->s = cpuintrf_temp_str(), "rfc :%08x", mipscpu.cp2cr[ 21 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2CR22: sprintf( info->s = cpuintrf_temp_str(), "gfc :%08x", mipscpu.cp2cr[ 22 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2CR23: sprintf( info->s = cpuintrf_temp_str(), "bfc :%08x", mipscpu.cp2cr[ 23 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2CR24: sprintf( info->s = cpuintrf_temp_str(), "ofx :%08x", mipscpu.cp2cr[ 24 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2CR25: sprintf( info->s = cpuintrf_temp_str(), "ofy :%08x", mipscpu.cp2cr[ 25 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2CR26: sprintf( info->s = cpuintrf_temp_str(), "h :%08x", mipscpu.cp2cr[ 26 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2CR27: sprintf( info->s = cpuintrf_temp_str(), "dqa :%08x", mipscpu.cp2cr[ 27 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2CR28: sprintf( info->s = cpuintrf_temp_str(), "dqb :%08x", mipscpu.cp2cr[ 28 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2CR29: sprintf( info->s = cpuintrf_temp_str(), "zsf3 :%08x", mipscpu.cp2cr[ 29 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2CR30: sprintf( info->s = cpuintrf_temp_str(), "zsf4 :%08x", mipscpu.cp2cr[ 30 ].d ); break; - case CPUINFO_STR_REGISTER + MIPS_CP2CR31: sprintf( info->s = cpuintrf_temp_str(), "flag :%08x", mipscpu.cp2cr[ 31 ].d ); break; -#endif - } -} - -uint32 mips_get_cause(void) -{ - return mipscpu.cp0r[ CP0_CAUSE ]; -} - -uint32 mips_get_status(void) -{ - return mipscpu.cp0r[ CP0_SR ]; -} - -void mips_set_status(uint32 status) -{ - mipscpu.cp0r[ CP0_SR ] = status; -} - -uint32 mips_get_ePC(void) -{ - return mipscpu.cp0r[ CP0_EPC ]; -} - -int mips_get_icount(void) -{ - return mips_ICount; -} - -void mips_set_icount(int count) -{ - mips_ICount = count; -} - - -#if (HAS_PSXCPU) -/************************************************************************** - * CPU-specific set_info - **************************************************************************/ - -void psxcpu_get_info(UINT32 state, union cpuinfo *info) -{ - switch (state) - { - /* --- the following bits of info are returned as NULL-terminated strings --- */ -// case CPUINFO_STR_NAME: strcpy(info->s = cpuintrf_temp_str(), "PSX CPU"); break; - - default: - mips_get_info(state, info); - break; - } -} -#endif diff --git a/Frameworks/AudioOverload/aosdk/eng_psf/psx.h b/Frameworks/AudioOverload/aosdk/eng_psf/psx.h deleted file mode 100644 index 79e57edf7..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_psf/psx.h +++ /dev/null @@ -1,288 +0,0 @@ -#ifndef _MIPS_H -#define _MIPS_H - -#include "ao.h" -//#include "driver.h" - -typedef void genf(void); -typedef int offs_t; - -#define cpu_readop32(pc) program_read_dword_32le(pc) -#define change_pc(pc) \ - - -#ifdef __GNUC__ -#if (__GNUC__ < 2) || ((__GNUC__ == 2) && (__GNUC_MINOR__ <= 7)) -#define UNUSEDARG -#else -#define UNUSEDARG __attribute__((__unused__)) -#endif -#else -#define UNUSEDARG -#endif - -typedef int8 (*read8_handler) (UNUSEDARG offs_t offset); -typedef void (*write8_handler) (UNUSEDARG offs_t offset, UNUSEDARG int8 data); -typedef int16 (*read16_handler) (UNUSEDARG offs_t offset, UNUSEDARG int16 mem_mask); -typedef void (*write16_handler)(UNUSEDARG offs_t offset, UNUSEDARG int16 data, UNUSEDARG int16 mem_mask); -typedef int32 (*read32_handler) (UNUSEDARG offs_t offset, UNUSEDARG int32 mem_mask); -typedef void (*write32_handler)(UNUSEDARG offs_t offset, UNUSEDARG int32 data, UNUSEDARG int32 mem_mask); -typedef int64 (*read64_handler) (UNUSEDARG offs_t offset, UNUSEDARG int64 mem_mask); -typedef void (*write64_handler)(UNUSEDARG offs_t offset, UNUSEDARG int64 data, UNUSEDARG int64 mem_mask); - -union read_handlers_t -{ - genf * handler; - read8_handler handler8; - read16_handler handler16; - read32_handler handler32; - read64_handler handler64; -}; - -union write_handlers_t -{ - genf * handler; - write8_handler handler8; - write16_handler handler16; - write32_handler handler32; - write64_handler handler64; -}; - -struct address_map_t -{ - uint32 flags; /* flags and additional info about this entry */ - offs_t start, end; /* start/end (or mask/match) values */ - offs_t mirror; /* mirror bits */ - offs_t mask; /* mask bits */ - union read_handlers_t read; /* read handler callback */ - union write_handlers_t write; /* write handler callback */ - void * memory; /* pointer to memory backing this entry */ - uint32 share; /* index of a shared memory block */ - void ** base; /* receives pointer to memory (optional) */ - size_t * size; /* receives size of area in bytes (optional) */ -}; -typedef struct address_map_t *(*construct_map_t)(struct address_map_t *map); - -union cpuinfo -{ - int64 i; /* generic integers */ - void * p; /* generic pointers */ - genf * f; /* generic function pointers */ - char * s; /* generic strings */ - - void (*setinfo)(UINT32 state, union cpuinfo *info);/* CPUINFO_PTR_SET_INFO */ - void (*getcontext)(void *context); /* CPUINFO_PTR_GET_CONTEXT */ - void (*setcontext)(void *context); /* CPUINFO_PTR_SET_CONTEXT */ - void (*init)(void); /* CPUINFO_PTR_INIT */ - void (*reset)(void *param); /* CPUINFO_PTR_RESET */ - void (*exit)(void); /* CPUINFO_PTR_EXIT */ - int (*execute)(int cycles); /* CPUINFO_PTR_EXECUTE */ - void (*burn)(int cycles); /* CPUINFO_PTR_BURN */ - offs_t (*disassemble)(char *buffer, offs_t pc); /* CPUINFO_PTR_DISASSEMBLE */ - int (*irqcallback)(int state); /* CPUINFO_PTR_IRQCALLBACK */ - int * icount; /* CPUINFO_PTR_INSTRUCTION_COUNTER */ - construct_map_t internal_map; /* CPUINFO_PTR_INTERNAL_MEMORY_MAP */ -}; - -enum -{ - MIPS_PC = 1, - MIPS_DELAYV, MIPS_DELAYR, - MIPS_HI, MIPS_LO, - MIPS_R0, MIPS_R1, - MIPS_R2, MIPS_R3, - MIPS_R4, MIPS_R5, - MIPS_R6, MIPS_R7, - MIPS_R8, MIPS_R9, - MIPS_R10, MIPS_R11, - MIPS_R12, MIPS_R13, - MIPS_R14, MIPS_R15, - MIPS_R16, MIPS_R17, - MIPS_R18, MIPS_R19, - MIPS_R20, MIPS_R21, - MIPS_R22, MIPS_R23, - MIPS_R24, MIPS_R25, - MIPS_R26, MIPS_R27, - MIPS_R28, MIPS_R29, - MIPS_R30, MIPS_R31, - MIPS_CP0R0, MIPS_CP0R1, - MIPS_CP0R2, MIPS_CP0R3, - MIPS_CP0R4, MIPS_CP0R5, - MIPS_CP0R6, MIPS_CP0R7, - MIPS_CP0R8, MIPS_CP0R9, - MIPS_CP0R10, MIPS_CP0R11, - MIPS_CP0R12, MIPS_CP0R13, - MIPS_CP0R14, MIPS_CP0R15, - MIPS_CP0R16, MIPS_CP0R17, - MIPS_CP0R18, MIPS_CP0R19, - MIPS_CP0R20, MIPS_CP0R21, - MIPS_CP0R22, MIPS_CP0R23, - MIPS_CP0R24, MIPS_CP0R25, - MIPS_CP0R26, MIPS_CP0R27, - MIPS_CP0R28, MIPS_CP0R29, - MIPS_CP0R30, MIPS_CP0R31, - MIPS_CP2DR0, MIPS_CP2DR1, - MIPS_CP2DR2, MIPS_CP2DR3, - MIPS_CP2DR4, MIPS_CP2DR5, - MIPS_CP2DR6, MIPS_CP2DR7, - MIPS_CP2DR8, MIPS_CP2DR9, - MIPS_CP2DR10, MIPS_CP2DR11, - MIPS_CP2DR12, MIPS_CP2DR13, - MIPS_CP2DR14, MIPS_CP2DR15, - MIPS_CP2DR16, MIPS_CP2DR17, - MIPS_CP2DR18, MIPS_CP2DR19, - MIPS_CP2DR20, MIPS_CP2DR21, - MIPS_CP2DR22, MIPS_CP2DR23, - MIPS_CP2DR24, MIPS_CP2DR25, - MIPS_CP2DR26, MIPS_CP2DR27, - MIPS_CP2DR28, MIPS_CP2DR29, - MIPS_CP2DR30, MIPS_CP2DR31, - MIPS_CP2CR0, MIPS_CP2CR1, - MIPS_CP2CR2, MIPS_CP2CR3, - MIPS_CP2CR4, MIPS_CP2CR5, - MIPS_CP2CR6, MIPS_CP2CR7, - MIPS_CP2CR8, MIPS_CP2CR9, - MIPS_CP2CR10, MIPS_CP2CR11, - MIPS_CP2CR12, MIPS_CP2CR13, - MIPS_CP2CR14, MIPS_CP2CR15, - MIPS_CP2CR16, MIPS_CP2CR17, - MIPS_CP2CR18, MIPS_CP2CR19, - MIPS_CP2CR20, MIPS_CP2CR21, - MIPS_CP2CR22, MIPS_CP2CR23, - MIPS_CP2CR24, MIPS_CP2CR25, - MIPS_CP2CR26, MIPS_CP2CR27, - MIPS_CP2CR28, MIPS_CP2CR29, - MIPS_CP2CR30, MIPS_CP2CR31 -}; - -#define MIPS_INT_NONE ( -1 ) - -#define MIPS_IRQ0 ( 0 ) -#define MIPS_IRQ1 ( 1 ) -#define MIPS_IRQ2 ( 2 ) -#define MIPS_IRQ3 ( 3 ) -#define MIPS_IRQ4 ( 4 ) -#define MIPS_IRQ5 ( 5 ) - -#define MIPS_BYTE_EXTEND( a ) ( (INT32)(INT8)a ) -#define MIPS_WORD_EXTEND( a ) ( (INT32)(INT16)a ) - -#define INS_OP( op ) ( ( op >> 26 ) & 63 ) -#define INS_RS( op ) ( ( op >> 21 ) & 31 ) -#define INS_RT( op ) ( ( op >> 16 ) & 31 ) -#define INS_IMMEDIATE( op ) ( op & 0xffff ) -#define INS_TARGET( op ) ( op & 0x3ffffff ) -#define INS_RD( op ) ( ( op >> 11 ) & 31 ) -#define INS_SHAMT( op ) ( ( op >> 6 ) & 31 ) -#define INS_FUNCT( op ) ( op & 63 ) -#define INS_CODE( op ) ( ( op >> 6 ) & 0xfffff ) -#define INS_CO( op ) ( ( op >> 25 ) & 1 ) -#define INS_COFUN( op ) ( op & 0x1ffffff ) -#define INS_CF( op ) ( op & 63 ) - -#define GTE_OP( op ) ( ( op >> 20 ) & 31 ) -#define GTE_SF( op ) ( ( op >> 19 ) & 1 ) -#define GTE_MX( op ) ( ( op >> 17 ) & 3 ) -#define GTE_V( op ) ( ( op >> 15 ) & 3 ) -#define GTE_CV( op ) ( ( op >> 13 ) & 3 ) -#define GTE_CD( op ) ( ( op >> 11 ) & 3 ) /* not used */ -#define GTE_LM( op ) ( ( op >> 10 ) & 1 ) -#define GTE_CT( op ) ( ( op >> 6 ) & 15 ) /* not used */ -#define GTE_FUNCT( op ) ( op & 63 ) - -#define OP_SPECIAL ( 0 ) -#define OP_REGIMM ( 1 ) -#define OP_J ( 2 ) -#define OP_JAL ( 3 ) -#define OP_BEQ ( 4 ) -#define OP_BNE ( 5 ) -#define OP_BLEZ ( 6 ) -#define OP_BGTZ ( 7 ) -#define OP_ADDI ( 8 ) -#define OP_ADDIU ( 9 ) -#define OP_SLTI ( 10 ) -#define OP_SLTIU ( 11 ) -#define OP_ANDI ( 12 ) -#define OP_ORI ( 13 ) -#define OP_XORI ( 14 ) -#define OP_LUI ( 15 ) -#define OP_COP0 ( 16 ) -#define OP_COP1 ( 17 ) -#define OP_COP2 ( 18 ) -#define OP_LB ( 32 ) -#define OP_LH ( 33 ) -#define OP_LWL ( 34 ) -#define OP_LW ( 35 ) -#define OP_LBU ( 36 ) -#define OP_LHU ( 37 ) -#define OP_LWR ( 38 ) -#define OP_SB ( 40 ) -#define OP_SH ( 41 ) -#define OP_SWL ( 42 ) -#define OP_SW ( 43 ) -#define OP_SWR ( 46 ) -#define OP_LWC1 ( 49 ) -#define OP_LWC2 ( 50 ) -#define OP_SWC1 ( 57 ) -#define OP_SWC2 ( 58 ) - -/* OP_SPECIAL */ -#define FUNCT_SLL ( 0 ) -#define FUNCT_SRL ( 2 ) -#define FUNCT_SRA ( 3 ) -#define FUNCT_SLLV ( 4 ) -#define FUNCT_SRLV ( 6 ) -#define FUNCT_SRAV ( 7 ) -#define FUNCT_JR ( 8 ) -#define FUNCT_JALR ( 9 ) -#define FUNCT_HLECALL ( 11 ) -#define FUNCT_SYSCALL ( 12 ) -#define FUNCT_BREAK ( 13 ) -#define FUNCT_MFHI ( 16 ) -#define FUNCT_MTHI ( 17 ) -#define FUNCT_MFLO ( 18 ) -#define FUNCT_MTLO ( 19 ) -#define FUNCT_MULT ( 24 ) -#define FUNCT_MULTU ( 25 ) -#define FUNCT_DIV ( 26 ) -#define FUNCT_DIVU ( 27 ) -#define FUNCT_ADD ( 32 ) -#define FUNCT_ADDU ( 33 ) -#define FUNCT_SUB ( 34 ) -#define FUNCT_SUBU ( 35 ) -#define FUNCT_AND ( 36 ) -#define FUNCT_OR ( 37 ) -#define FUNCT_XOR ( 38 ) -#define FUNCT_NOR ( 39 ) -#define FUNCT_SLT ( 42 ) -#define FUNCT_SLTU ( 43 ) - -/* OP_REGIMM */ -#define RT_BLTZ ( 0 ) -#define RT_BGEZ ( 1 ) -#define RT_BLTZAL ( 16 ) -#define RT_BGEZAL ( 17 ) - -/* OP_COP0/OP_COP1/OP_COP2 */ -#define RS_MFC ( 0 ) -#define RS_CFC ( 2 ) -#define RS_MTC ( 4 ) -#define RS_CTC ( 6 ) -#define RS_BC ( 8 ) - -/* RS_BC */ -#define RT_BCF ( 0 ) -#define RT_BCT ( 1 ) - -/* OP_COP0 */ -#define CF_RFE ( 16 ) - -#ifdef MAME_DEBUG -extern unsigned DasmMIPS(char *buff, unsigned _pc); -#endif - -#if (HAS_PSXCPU) -extern void psxcpu_get_info(UINT32 state, union cpuinfo *info); -#endif - -#endif diff --git a/Frameworks/AudioOverload/aosdk/eng_psf/psx_hw.c b/Frameworks/AudioOverload/aosdk/eng_psf/psx_hw.c deleted file mode 100644 index c6ccc3ea5..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_psf/psx_hw.c +++ /dev/null @@ -1,3540 +0,0 @@ -/* - Audio Overload SDK - PSX and IOP hardware emulation - - Copyright (c) 2007 R. Belmont and Richard Bannister. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - * Neither the names of R. Belmont and Richard Bannister nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -/* - psx_hw.c - Minimal PSX/IOP hardware glue/emulation/whatever - - supported: main RAM (2 MB, mirrored to fill an 8 MB space like on real HW) - DMA channel 4 (SPURAM) in both directions (including completion IRQ) - VBL IRQ - Root counters 2 and 3 including completion events and IRQs - Some BIOS services including exception handling (via HLE) - HLE emulation of IOP operating system, including multithreading - SPU(2), SPU(2)RAM (via PEOpS) - - - - Special notes: - PSF1 - - Chocobo's Dungeon 2 contains an illegal code sequence (patched) - - PSF2 - - Shadow Hearts assumes that the wave buffer alloc will go to 0x80060000 and the sequence buffer to 0x80170000. - Our memory management doesn't work out that way, so we have to (wait for it) cheese it. -*/ - -#include -#include "ao.h" -#include "cpuintrf.h" -#include "psx.h" - -#define DEBUG_HLE_BIOS (0) // debug PS1 HLE BIOS -#define DEBUG_HLE_IOP (0) // debug PS2 IOP OS calls -#define DEBUG_UNK_RW (0) // debug unknown reads/writes -#define DEBUG_THREADING (0) // debug PS2 IOP threading - -extern void mips_get_info(UINT32 state, union cpuinfo *info); -extern void mips_set_info(UINT32 state, union cpuinfo *info); -extern int psxcpu_verbose; -extern uint16 SPUreadRegister(uint32 reg); -extern void SPUwriteRegister(uint32 reg, uint16 val); -extern void SPUwriteDMAMem(uint32 usPSXMem,int iSize); -extern void SPUreadDMAMem(uint32 usPSXMem,int iSize); -extern void mips_shorten_frame(void); -extern int mips_execute( int cycles ); -extern uint32 psf2_load_file(char *file, uint8 *buf, uint32 buflen); -extern uint32 psf2_load_elf(uint8 *start, uint32 len); -void psx_hw_runcounters(void); -int mips_get_icount(void); -void mips_set_icount(int count); - -extern int psf_refresh; - -static int skipyet = 0; - -// SPU2 -extern void SPU2write(unsigned long reg, unsigned short val); -extern unsigned short SPU2read(unsigned long reg); -extern void SPU2readDMA4Mem(uint32 usPSXMem,int iSize); -extern void SPU2writeDMA4Mem(uint32 usPSXMem,int iSize); -extern void SPU2readDMA7Mem(uint32 usPSXMem,int iSize); -extern void SPU2writeDMA7Mem(uint32 usPSXMem,int iSize); -extern void SPU2interruptDMA4(void); -extern void SPU2interruptDMA7(void); - -#define MAX_FILE_SLOTS (32) - -static volatile int softcall_target = 0; -static int filestat[MAX_FILE_SLOTS]; -static uint8 *filedata[MAX_FILE_SLOTS]; -static uint32 filesize[MAX_FILE_SLOTS], filepos[MAX_FILE_SLOTS]; -uint32 psf2_get_loadaddr(void); -void psf2_set_loadaddr(uint32 new); -static void call_irq_routine(uint32 routine, uint32 parameter); -static int intr_susp = 0; - -static uint64 sys_time; -static int timerexp = 0; - -typedef struct -{ - char name[10]; - uint32 dispatch; -} ExternLibEntries; - -static int32 iNumLibs; -static ExternLibEntries reglibs[32]; - -typedef struct -{ - uint32 type; - uint32 value; - uint32 param; - int inUse; -} EventFlag; - -static int32 iNumFlags; -static EventFlag evflags[32]; - -typedef struct -{ - uint32 attr; - uint32 option; - int32 init; - int32 current; - int32 max; - int32 threadsWaiting; - int32 inuse; -} Semaphore; - -#define SEMA_MAX (64) - -static int32 iNumSema; -static Semaphore semaphores[SEMA_MAX]; - -// thread states -enum -{ - TS_RUNNING = 0, // now running - TS_READY, // ready to run - TS_WAITEVFLAG, // waiting on an event flag - TS_WAITSEMA, // waiting on a semaphore - TS_WAITDELAY, // waiting on a time delay - TS_SLEEPING, // sleeping - TS_CREATED, // newly created, hasn't run yet - - TS_MAXSTATE -}; - -typedef struct -{ - int32 iState; // state of thread - - uint32 flags; // flags - uint32 routine; // start of code for the thread - uint32 stackloc; // stack location in IOP RAM - uint32 stacksize; // stack size - uint32 refCon; // user value passed in at CreateThread time - - uint32 waitparm; // what we're waiting on if in one the TS_WAIT* states - - uint32 save_regs[37]; // CPU registers belonging to this thread -} Thread; - -static int32 iNumThreads, iCurThread; -static Thread threads[32]; - -#if DEBUG_THREADING -static char *_ThreadStateNames[TS_MAXSTATE] = { "RUNNING", "READY", "WAITEVFLAG", "WAITSEMA", "WAITDELAY", "SLEEPING", "CREATED" }; -#endif - -#if DEBUG_HLE_IOP -static char *seek_types[3] = { "SEEK_SET", "SEEK_CUR", "SEEK_END" }; -#endif - -typedef struct -{ - int32 iActive; - uint32 count; - uint32 target; - uint32 source; - uint32 prescale; - uint32 handler; - uint32 hparam; - uint32 mode; -} IOPTimer; - -static IOPTimer iop_timers[8]; -static int32 iNumTimers; - -typedef struct -{ - uint32 count; - uint32 mode; - uint32 target; - uint32 sysclock; -} Counter; - -static Counter root_cnts[3]; // 3 of the bastards - -#define CLOCK_DIV (8) // 33 MHz / this = what we run the R3000 at to keep the CPU usage not insane - -// counter modes -#define RC_EN (0x0001) // halt -#define RC_RESET (0x0008) // automatically wrap -#define RC_IQ1 (0x0010) // IRQ when target reached -#define RC_IQ2 (0x0040) // IRQ when target reached (pSX treats same as IQ1?) -#define RC_CLC (0x0100) // counter uses direct system clock -#define RC_DIV8 (0x0200) // (counter 2 only) system clock/8 - -typedef struct -{ - uint32 desc; - int32 status; - int32 mode; - uint32 fhandler; -} EvtCtrlBlk[32]; - -static EvtCtrlBlk *Event; -static EvtCtrlBlk *CounterEvent; - -// Sony event states -#define EvStUNUSED 0x0000 -#define EvStWAIT 0x1000 -#define EvStACTIVE 0x2000 -#define EvStALREADY 0x4000 - -// Sony event modes -#define EvMdINTR 0x1000 -#define EvMdNOINTR 0x2000 - -// PSX main RAM -uint32 psx_ram[(2*1024*1024)/4]; -uint32 psx_scratch[0x400]; -// backup image to restart songs -uint32 initial_ram[(2*1024*1024)/4]; -uint32 initial_scratch[0x400]; - -static uint32 spu_delay, dma_icr, irq_data, irq_mask, dma_timer, WAI; -static uint32 dma4_madr, dma4_bcr, dma4_chcr, dma4_delay; -static uint32 dma7_madr, dma7_bcr, dma7_chcr, dma7_delay; -static uint32 dma4_cb, dma7_cb, dma4_fval, dma4_flag, dma7_fval, dma7_flag; -static uint32 irq9_cb, irq9_fval, irq9_flag; - -// take a snapshot of the CPU state for a thread -static void FreezeThread(int32 iThread, int flag) -{ - int i; - union cpuinfo mipsinfo; - - #if DEBUG_THREADING -// printf("IOP: FreezeThread(%d)\n", iThread); - #endif - - for (i = 0; i < 32; i++) - { - mips_get_info(CPUINFO_INT_REGISTER + MIPS_R0 + i, &mipsinfo); - threads[iThread].save_regs[i] = mipsinfo.i; - } - mips_get_info(CPUINFO_INT_REGISTER + MIPS_HI, &mipsinfo); - threads[iThread].save_regs[32] = mipsinfo.i; - mips_get_info(CPUINFO_INT_REGISTER + MIPS_LO, &mipsinfo); - threads[iThread].save_regs[33] = mipsinfo.i; - mips_get_info(CPUINFO_INT_REGISTER + MIPS_DELAYV, &mipsinfo); - threads[iThread].save_regs[35] = mipsinfo.i; - mips_get_info(CPUINFO_INT_REGISTER + MIPS_DELAYR, &mipsinfo); - threads[iThread].save_regs[36] = mipsinfo.i; - - - // if a thread is freezing itself due to a IOP syscall, we must save the RA as the PC - // to come back to or else the syscall will recurse - if (flag) - { - mips_get_info(CPUINFO_INT_REGISTER + MIPS_R31, &mipsinfo); - } - else - { - mips_get_info(CPUINFO_INT_PC, &mipsinfo); - } - threads[iThread].save_regs[34] = mipsinfo.i; - - #if DEBUG_THREADING - { - char buffer[256]; - - DasmMIPS(buffer, mipsinfo.i, &psx_ram[(mipsinfo.i & 0x7fffffff)/4]); - - printf("IOP: FreezeThread(%d) => %08x [%s]\n", iThread, threads[iThread].save_regs[34], buffer); - } - #endif - - // if thread was running, now it's ready - if (threads[iThread].iState == TS_RUNNING) - { - threads[iThread].iState = TS_READY; - } -} - -// restore the CPU state from a thread's snapshot -static void ThawThread(int32 iThread) -{ - int i; - union cpuinfo mipsinfo; - - // the first time a thread is put on the CPU, - // some special setup is required - if (threads[iThread].iState == TS_CREATED) - { - // PC = starting routine - threads[iThread].save_regs[34] = threads[iThread].routine-4; // compensate for weird delay slot effects - // SP = thread's stack area - threads[iThread].save_regs[29] = (threads[iThread].stackloc + threads[iThread].stacksize) - 16; - threads[iThread].save_regs[29] |= 0x80000000; - - threads[iThread].save_regs[35] = threads[iThread].save_regs[36] = 0; - - #if DEBUG_THREADING -// printf("IOP: Initial setup for thread %d => PC %x SP %x\n", iThread, threads[iThread].save_regs[34]+4, threads[iThread].save_regs[29]); - #endif - } - - #if DEBUG_THREADING - { - char buffer[256]; - - mips_get_info(CPUINFO_INT_PC, &mipsinfo); - DasmMIPS(buffer, mipsinfo.i, &psx_ram[(mipsinfo.i & 0x7fffffff)/4]); - - printf("IOP: ThawThread(%d) => %08x [%s] (wake %d)\n", iThread, threads[iThread].save_regs[34], buffer, wakecount); - } - #endif - - for (i = 0; i < 32; i++) - { - mipsinfo.i = threads[iThread].save_regs[i]; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R0 + i, &mipsinfo); - } - - mipsinfo.i = threads[iThread].save_regs[32]; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_HI, &mipsinfo); - mipsinfo.i = threads[iThread].save_regs[33]; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_LO, &mipsinfo); - mipsinfo.i = threads[iThread].save_regs[34]; - mips_set_info(CPUINFO_INT_PC, &mipsinfo); - mipsinfo.i = threads[iThread].save_regs[35]; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_DELAYV, &mipsinfo); - mipsinfo.i = threads[iThread].save_regs[36]; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_DELAYR, &mipsinfo); - - threads[iThread].iState = TS_RUNNING; -} - -// find a new thread to run -static void ps2_reschedule(void) -{ - int i, starti, iNextThread; - - iNextThread = -1; - - // see if any thread other than the current one is ready to run - i = iCurThread+1; - if (i >= iNumThreads) - { - i = 0; - } - - starti = i; - - // starting with the next thread after this one, - // see who wants to run - while (i < iNumThreads) - { - if (i != iCurThread) - { - if (threads[i].iState == TS_READY) - { - iNextThread = i; - break; - } - } - - i++; - } - - // if we started above thread 0 and didn't pick one, - // go around and try from zero - if ((starti > 0) && (iNextThread == -1)) - { - for (i = 0; i < iNumThreads; i++) - { - if (i != iCurThread) - { - if (threads[i].iState == TS_READY) - { - iNextThread = i; - break; - } - } - } - } - - if (iNextThread != -1) - { - #if DEBUG_THREADING - for (i = 0; i < iNumThreads; i++) - { - printf("Thread %02d: %s\n", i, _ThreadStateNames[threads[i].iState]); - } - #endif - - if (iCurThread != -1) - { - FreezeThread(iCurThread, 0); - } - ThawThread(iNextThread); - iCurThread = iNextThread; - threads[iCurThread].iState = TS_RUNNING; - } - else - { - // no thread to switch to, is the current one still running? - if (iCurThread != -1) - { - if (threads[iCurThread].iState != TS_RUNNING) - { - #if DEBUG_THREADING - printf("IOP: no threads to run\n"); - - for (i = 0; i < iNumThreads; i++) - { - printf("Thread %02d: %s\n", i, _ThreadStateNames[threads[i].iState]); - } - #endif - - mips_shorten_frame(); // kill the CPU - iCurThread = -1; // no threads are active - } - } - else - { - mips_shorten_frame(); // kill the CPU - iCurThread = -1; // no threads are active - } - } -} - -static void psx_irq_update(void) -{ - union cpuinfo mipsinfo; - - if ((irq_data & irq_mask) != 0) - { // assert the line - WAI = 0; - mipsinfo.i = ASSERT_LINE; - mips_set_info( CPUINFO_INT_INPUT_STATE + MIPS_IRQ0, &mipsinfo ); - } - else - { - // clear the line - mipsinfo.i = CLEAR_LINE; - mips_set_info( CPUINFO_INT_INPUT_STATE + MIPS_IRQ0, &mipsinfo ); - } -} - -void psx_irq_set(uint32 irq) -{ - irq_data |= irq; - - psx_irq_update(); -} - -static uint32 gpu_stat = 0; - -uint32 psx_hw_read(offs_t offset, uint32 mem_mask) -{ - if (offset >= 0x00000000 && offset <= 0x007fffff) - { - offset &= 0x1fffff; - return LE32(psx_ram[offset>>2]); - } - - if (offset >= 0x80000000 && offset <= 0x807fffff) - { - offset &= 0x1fffff; - return LE32(psx_ram[offset>>2]); - } - - if (offset == 0xbfc00180 || offset == 0xbfc00184) // exception vector - { - return FUNCT_HLECALL; - } - - if (offset == 0x1f801014) - { - return spu_delay; - } - - if (offset == 0xbf801014) - { - return spu_delay; - } - - if (offset == 0x1f801814) - { - gpu_stat ^= 0xffffffff; - return gpu_stat; - } - - if (offset >= 0x1f801c00 && offset <= 0x1f801dff) - { - if ((mem_mask == 0xffff0000) || (mem_mask == 0xffffff00)) - { - return SPUreadRegister(offset) & ~mem_mask; - } - else if (mem_mask == 0x0000ffff) - { - return SPUreadRegister(offset)<<16; - } - else printf("SPU: read unknown mask %08x\n", mem_mask); - } - - if (offset >= 0xbf900000 && offset <= 0xbf9007ff) - { - if ((mem_mask == 0xffff0000) || (mem_mask == 0xffffff00)) - { - return SPU2read(offset) & ~mem_mask; - } - else if (mem_mask == 0x0000ffff) - { - return SPU2read(offset)<<16; - } - else if (mem_mask == 0) - { - return SPU2read(offset) | SPU2read(offset+2)<<16; - } - else printf("SPU2: read unknown mask %08x\n", mem_mask); - } - - if (offset >= 0x1f801100 && offset <= 0x1f801128) - { - int cnt = (offset>>4) & 0xf; - - switch (offset & 0xf) - { - case 0: -// printf("RC: read counter %d count = %x\n", cnt, root_cnts[cnt].count); - return root_cnts[cnt].count; - break; - case 4: -// printf("RC: read counter %d mode\n", cnt); - return root_cnts[cnt].mode; - break; - case 8: -// printf("RC: read counter %d target\n", cnt); - return root_cnts[cnt].target; - break; - } - - return 0; - } - - if (offset == 0x1f8010f4) - { - return dma_icr; - } - else if (offset == 0x1f801070) - { -// printf("Read IRQ_data %x (mask %08x)\n", irq_data, mem_mask); - return irq_data; - } - else if (offset == 0x1f801074) - { - return irq_mask; - } - -/* if (offset == 0xbf801508) - { - return dma7_bcr; - }*/ - - if (offset == 0xbf920344) - { - return 0x80808080; - } - - #if DEBUG_UNK_RW - { - union cpuinfo mipsinfo; - - mips_get_info(CPUINFO_INT_PC, &mipsinfo); - printf("Unknown read: %08x, mask %08x (PC=%x)\n", offset&~3, mem_mask, mipsinfo.i); - } - #endif - return 0; -} - -static void psx_dma4(uint32 madr, uint32 bcr, uint32 chcr) -{ - if (chcr == 0x01000201) // cpu to SPU - { -// printf("DMA4: RAM %08x to SPU\n", madr); - bcr = (bcr>>16) * (bcr & 0xffff) * 2; - SPUwriteDMAMem(madr&0x1fffff, bcr); - } - else - { -// printf("DMA4: SPU to RAM %08x\n", madr); - bcr = (bcr>>16) * (bcr & 0xffff) * 2; - SPUreadDMAMem(madr&0x1fffff, bcr); - } -} - -static void ps2_dma4(uint32 madr, uint32 bcr, uint32 chcr) -{ - if (chcr == 0x01000201) // cpu to SPU2 - { - #if DEBUG_HLE_IOP - printf("DMA4: RAM %08x to SPU2\n", madr); - #endif - bcr = (bcr>>16) * (bcr & 0xffff) * 4; - SPU2writeDMA4Mem(madr&0x1fffff, bcr); - } - else - { - #if DEBUG_HLE_IOP - printf("DMA4: SPU2 to RAM %08x\n", madr); - #endif - bcr = (bcr>>16) * (bcr & 0xffff) * 4; - SPU2readDMA4Mem(madr&0x1fffff, bcr); - } - - dma4_delay = 80; -} - -static void ps2_dma7(uint32 madr, uint32 bcr, uint32 chcr) -{ - if ((chcr == 0x01000201) || (chcr == 0x00100010) || (chcr == 0x000f0010) || (chcr == 0x00010010)) // cpu to SPU2 - { - #if DEBUG_HLE_IOP - printf("DMA7: RAM %08x to SPU2\n", madr); - #endif - bcr = (bcr>>16) * (bcr & 0xffff) * 4; - SPU2writeDMA7Mem(madr&0x1fffff, bcr); - } - else - { - #if DEBUG_HLE_IOP - printf("DMA7: SPU2 to RAM %08x\n", madr); - #endif - bcr = (bcr>>16) * (bcr & 0xffff) * 4; -// SPU2readDMA7Mem(madr&0x1fffff, bcr); - } - - dma7_delay = 80; -} - -void psx_hw_write(offs_t offset, uint32 data, uint32 mem_mask) -{ - union cpuinfo mipsinfo; - - if (offset >= 0x00000000 && offset <= 0x007fffff) - { - offset &= 0x1fffff; -// if (offset < 0x10000) printf("Write %x to kernel @ %x\n", data, offset); - - mips_get_info(CPUINFO_INT_PC, &mipsinfo); - - psx_ram[offset>>2] &= LE32(mem_mask); - psx_ram[offset>>2] |= LE32(data); - return; - } - - if (offset >= 0x80000000 && offset <= 0x807fffff) - { - offset &= 0x1fffff; -// if (offset < 0x10000) printf("Write %x to kernel @ %x\n", data, offset); - mips_get_info(CPUINFO_INT_PC, &mipsinfo); - psx_ram[offset>>2] &= LE32(mem_mask); - psx_ram[offset>>2] |= LE32(data); - return; - } - - if (offset == 0x1f801014 || offset == 0xbf801014) - { - spu_delay &= mem_mask; - spu_delay |= data; - return; - } - - if (offset >= 0x1f801c00 && offset <= 0x1f801dff) - { - // printf("SPU2 wrote %x to SPU1 address %x!\n", data, offset); - if (mem_mask == 0xffff0000) - { - SPUwriteRegister(offset, data); - return; - } - else if (mem_mask == 0x0000ffff) - { - SPUwriteRegister(offset, data>>16); - return; - } - else printf("SPU: write unknown mask %08x\n", mem_mask); - } - - if (offset >= 0xbf900000 && offset <= 0xbf9007ff) - { - if (mem_mask == 0xffff0000) - { - SPU2write(offset, data); - return; - } - else if (mem_mask == 0x0000ffff) - { - SPU2write(offset, data>>16); - return; - } - else if (mem_mask == 0) - { - SPU2write(offset, data & 0xffff); - SPU2write(offset+2, data>>16); - return; - } - else printf("SPU2: write unknown mask %08x\n", mem_mask); - } - - if (offset >= 0x1f801100 && offset <= 0x1f801128) - { - int cnt = (offset>>4) & 0xf; - - switch (offset & 0xf) - { - case 0: - root_cnts[cnt].count = data; -// printf("RC: counter %d count = %x\n", cnt, data); - break; - case 4: - root_cnts[cnt].mode = data; -// printf("RC: counter %d mode = %x\n", cnt, data); - break; - case 8: - root_cnts[cnt].target = data; -// printf("RC: counter %d target = %x\n", cnt, data); - break; - } - - return; - } - - // DMA4 - if (offset == 0x1f8010c0) - { - dma4_madr = data; - return; - } - else if (offset == 0x1f8010c4) - { - dma4_bcr = data; - return; - } - else if (offset == 0x1f8010c8) - { - dma4_chcr = data; - psx_dma4(dma4_madr, dma4_bcr, dma4_chcr); - - if (dma_icr & (1 << (16+4))) - { - dma_timer = 3; - } - return; - } - else if (offset == 0x1f8010f4) - { - dma_icr = ( dma_icr & mem_mask ) | - ( ~mem_mask & 0x80000000 & dma_icr) | - ( ~data & ~mem_mask & 0x7f000000 & dma_icr) | - ( data & ~mem_mask & 0x00ffffff); - - if ((dma_icr & 0x7f000000) != 0) - { - dma_icr &= ~0x80000000; - } - - return; - } - else if (offset == 0x1f801070) - { - irq_data = (irq_data & mem_mask) | (irq_data & irq_mask & data); - psx_irq_update(); - return; - } - else if (offset == 0x1f801074) - { - irq_mask &= mem_mask; - irq_mask |= data; - psx_irq_update(); - return; - } - - // PS2 DMA4 - if (offset == 0xbf8010c0) - { - dma4_madr = data; - return; - } - else if (offset == 0xbf8010c8) - { - dma4_chcr = data; - ps2_dma4(dma4_madr, dma4_bcr, dma4_chcr); - - if (dma_icr & (1 << (16+4))) - { - dma_timer = 3; - } - return; - } - - if (offset == 0xbf8010c4 || offset == 0xbf8010c6) - { - dma4_bcr &= mem_mask; - dma4_bcr |= data; - return; - } - - // PS2 DMA7 - if (offset == 0xbf801500) - { - dma7_madr = data; - return; - } - else if (offset == 0xbf801504) - { - dma7_chcr = data; - ps2_dma7(dma7_madr, dma7_bcr, dma7_chcr); - return; - } - - if (offset == 0xbf801508 || offset == 0xbf80150a) - { - dma7_bcr &= mem_mask; - dma7_bcr |= data; - return; - } - - #if DEBUG_UNK_RW - { - union cpuinfo mipsinfo; - - mips_get_info(CPUINFO_INT_PC, &mipsinfo); - printf("Unknown write: %08x to %08x, mask %08x (PC=%x)\n", data, offset&~3, mem_mask, mipsinfo.i); - } - #endif -} - -// called per sample, 1/44100th of a second (768 clock cycles) -void psx_hw_slice(void) -{ - psx_hw_runcounters(); - - if (!WAI) - mips_execute(768/CLOCK_DIV); - - if (dma_timer) - { - dma_timer--; - if (dma_timer == 0) - { - dma_icr |= (1 << (24+4)); - psx_irq_set(0x0008); - } - } -} - -void ps2_hw_slice(void) -{ - int i = 0; - - timerexp = 0; - psx_hw_runcounters(); - - if (iCurThread != -1) - { - mips_execute(836/CLOCK_DIV); - } - else // no thread, don't run CPU, just update counters - { - if (timerexp) - { - ps2_reschedule(); - - if (iCurThread != -1) - { - mips_execute((836/CLOCK_DIV)-i); - i = (836/CLOCK_DIV); - } - } - } -} - -static int fcnt = 0; - -void psx_hw_frame(void) -{ - if (psf_refresh == 50) - { - fcnt++;; - - if (fcnt < 6) - { - psx_irq_set(1); - } - else - { - fcnt = 0; - } - } - else // NTSC - { - psx_irq_set(1); - } -} - -void ps2_hw_frame(void) -{ - ps2_reschedule(); -} - -// BIOS HLE - -// heap block struct offsets -enum -{ - BLK_STAT = 0, - BLK_SIZE = 4, - BLK_FD = 8, - BLK_BK = 12 -}; - -static uint32 heap_addr, entry_int = 0; - -extern uint32 mips_get_cause(void); -extern uint32 mips_get_status(void); -extern void mips_set_status(uint32 status); -extern uint32 mips_get_ePC(void); - -static uint32 irq_regs[37]; - -static int irq_mutex = 0; - -static void call_irq_routine(uint32 routine, uint32 parameter) -{ - int j, oldICount; - union cpuinfo mipsinfo; - - if (!irq_mutex) - { - irq_mutex = 1; - } - else - { - printf("IOP: ERROR! IRQ reentry!\n"); - return; - } - - // save regs for IRQ - for (j = 0; j < 32; j++) - { - mips_get_info(CPUINFO_INT_REGISTER + MIPS_R0 + j, &mipsinfo); - irq_regs[j] = mipsinfo.i; - } - mips_get_info(CPUINFO_INT_REGISTER + MIPS_HI, &mipsinfo); - irq_regs[32] = mipsinfo.i; - mips_get_info(CPUINFO_INT_REGISTER + MIPS_LO, &mipsinfo); - irq_regs[33] = mipsinfo.i; - mips_get_info(CPUINFO_INT_PC, &mipsinfo); - irq_regs[34] = mipsinfo.i; - mips_get_info(CPUINFO_INT_REGISTER + MIPS_DELAYV, &mipsinfo); - irq_regs[35] = mipsinfo.i; - mips_get_info(CPUINFO_INT_REGISTER + MIPS_DELAYR, &mipsinfo); - irq_regs[36] = mipsinfo.i; - - // PC = timer handler routine - mipsinfo.i = routine; - mips_set_info(CPUINFO_INT_PC, &mipsinfo); - - // parameter in a0 - mipsinfo.i = parameter; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R4, &mipsinfo); - - // RA = a trap address we can set - mipsinfo.i = 0x80001000; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R31, &mipsinfo); - - // make sure we're set - psx_ram[0x1000/4] = LE32(FUNCT_HLECALL); - - softcall_target = 0; - oldICount = mips_get_icount(); - while (!softcall_target) - { - mips_execute(10); - } - mips_set_icount(oldICount); - - // restore IRQ regs - for (j = 0; j < 32; j++) - { - mipsinfo.i = irq_regs[j]; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R0 + j, &mipsinfo); - } - - mipsinfo.i = irq_regs[32]; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_HI, &mipsinfo); - mipsinfo.i = irq_regs[33]; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_LO, &mipsinfo); - mipsinfo.i = irq_regs[34]; - mips_set_info(CPUINFO_INT_PC, &mipsinfo); - mipsinfo.i = irq_regs[35]; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_DELAYV, &mipsinfo); - mipsinfo.i = irq_regs[36]; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_DELAYR, &mipsinfo); - - irq_mutex = 0; -} - -void psx_bios_exception(uint32 pc) -{ - uint32 a0, status; - union cpuinfo mipsinfo; - int i, oldICount; - -// printf("bios_exception: cause %x\n", mips_get_cause() & 0x3c); - - // get a0 - mips_get_info(CPUINFO_INT_REGISTER + MIPS_R4, &mipsinfo); - a0 = mipsinfo.i; - - switch (mips_get_cause() & 0x3c) - { - case 0: // IRQ -// printf("IRQ: %x, mask %x\n", irq_data, irq_mask); - // save all regs - for (i = 0; i < 32; i++) - { - mips_get_info(CPUINFO_INT_REGISTER + MIPS_R0 + i, &mipsinfo); - irq_regs[i] = mipsinfo.i; - } - mips_get_info(CPUINFO_INT_REGISTER + MIPS_HI, &mipsinfo); - irq_regs[32] = mipsinfo.i; - mips_get_info(CPUINFO_INT_REGISTER + MIPS_LO, &mipsinfo); - irq_regs[33] = mipsinfo.i; - - // check BIOS-driven interrupts - if (irq_data & 1) // VSync - { - if (CounterEvent[3][1].status == LE32(EvStACTIVE)) - { - // run the handler - mipsinfo.i = LE32(CounterEvent[3][1].fhandler); -// printf("Cause = %x, ePC = %x\n", mips_get_cause(), mips_get_ePC()); -// printf("VBL running handler @ %x\n", mipsinfo.i); - mips_set_info(CPUINFO_INT_PC, &mipsinfo); - mipsinfo.i = 0x80001000; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R31, &mipsinfo); - - // make sure we're set - psx_ram[0x1000/4] = LE32(FUNCT_HLECALL); - - softcall_target = 0; - oldICount = mips_get_icount(); - while (!softcall_target) - { - mips_execute(10); - } - mips_set_icount(oldICount); - -// printf("Exiting softcall handler\n"); - - irq_data &= ~1; // clear the VBL IRQ if we handled it - } - } - else if (irq_data & 0x70) // root counters - { - for (i = 0; i < 3; i++) - { - if (irq_data & (1 << (i+4))) - { - if (CounterEvent[i][1].status == LE32(EvStACTIVE)) - { - // run the handler - mipsinfo.i = LE32(CounterEvent[i][1].fhandler); -// printf("Cause = %x, ePC = %x\n", mips_get_cause(), mips_get_ePC()); -// printf("Counter %d running handler @ %x\n", i, mipsinfo.i); - mips_set_info(CPUINFO_INT_PC, &mipsinfo); - mipsinfo.i = 0x80001000; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R31, &mipsinfo); - - // make sure we're set - psx_ram[0x1000/4] = LE32(FUNCT_HLECALL); - - softcall_target = 0; - oldICount = mips_get_icount(); - while (!softcall_target) - { - mips_execute(10); - } - mips_set_icount(oldICount); - -// printf("Exiting softcall handler\n"); - irq_data &= ~(1 << (i+4)); - } - else - { -// printf("CEvt %d not active\n", i); - } - } - } - } - - if (entry_int) - { - psx_hw_write(0x1f801070, 0xffffffff, 0); - - a0 = entry_int; - -// printf("taking entry_int\n"); - - // RA (and PC) - mipsinfo.i = LE32(psx_ram[((a0&0x1fffff)+0)/4]); - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R31, &mipsinfo); - mips_set_info(CPUINFO_INT_PC, &mipsinfo); - // SP - mipsinfo.i = LE32(psx_ram[((a0&0x1fffff)+4)/4]); - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R29, &mipsinfo); - // FP - mipsinfo.i = LE32(psx_ram[((a0&0x1fffff)+8)/4]); - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R30, &mipsinfo); - - // S0-S7 are next - for (i = 0; i < 8; i++) - { - mipsinfo.i = LE32(psx_ram[((a0&0x1fffff)+12+(i*4))/4]); - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R16 + i, &mipsinfo); - } - - // GP - mipsinfo.i = LE32(psx_ram[((a0&0x1fffff)+44)/4]); - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R28, &mipsinfo); - - // v0 = 1 - mipsinfo.i = 1; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - } - else - { - psx_hw_write(0x1f801070, 0, 0xffff0000); - - // note: the entry_int won't be bailing us out here, so do it ourselves - for (i = 0; i < 32; i++) - { - mipsinfo.i = irq_regs[i]; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R0 + i, &mipsinfo); - } - - mipsinfo.i = irq_regs[32]; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_HI, &mipsinfo); - mipsinfo.i = irq_regs[33]; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_LO, &mipsinfo); - mipsinfo.i = mips_get_ePC(); - mips_set_info(CPUINFO_INT_PC, &mipsinfo); - - status = mips_get_status(); - status = (status & 0xfffffff0) | ((status & 0x3c)>>2); - mips_set_status(status); - } - break; - - case 0x20: // syscall - // syscall always farks with the status, so get it now - status = mips_get_status(); - - switch (a0) - { - case 1: // EnterCritical - #if DEBUG_HLE_BIOS - printf("HLEBIOS: EnterCritical\n"); - #endif - status &= ~0x0404; - break; - - case 2: // ExitCritical - #if DEBUG_HLE_BIOS - printf("HLEBIOS: ExitCritical\n"); - #endif - status |= 0x0404; - break; - - default: - #if DEBUG_HLE_BIOS - printf("HLEBIOS: Unknown syscall %x\n", a0); - #endif - break; - } - - // PC = ePC + 4 - mipsinfo.i = mips_get_ePC() + 4; - mips_set_info(CPUINFO_INT_PC, &mipsinfo); - - // and update the status accordingly - status = (status & 0xfffffff0) | ((status & 0x3c)>>2); - mips_set_status(status); - break; - - default: - #if DEBUG_HLE_BIOS - printf("HLEBIOS: Unknown exception %x\n", mips_get_cause()); - #endif - break; - } -} - -static uint32 calc_ev(uint32 a0) -{ - uint32 ev; - - ev = (a0 >> 24) & 0xf; - if (ev == 0xf) - { - ev = 0x5; - } - ev *= 32; - ev += (a0 & 0x1f); - - return ev; -} - -static uint32 calc_spec(uint32 a1) -{ - uint32 spec = 0; - int i; - - if (a1 == 0x301) - { - spec = 16; - } - else if (a1 == 0x302) - { - spec = 17; - } - else - { - for (i = 0; i < 16; i++) - { - if (a1 & (1< PC %08x\n", a0, mipsinfo.i); - #endif - // SP - mips_get_info(CPUINFO_INT_REGISTER + MIPS_R29, &mipsinfo); - psx_ram[((a0&0x1fffff)+4)/4] = LE32(mipsinfo.i); - // FP - mips_get_info(CPUINFO_INT_REGISTER + MIPS_R30, &mipsinfo); - psx_ram[((a0&0x1fffff)+8)/4] = LE32(mipsinfo.i); - - // S0-S7 are next - for (i = 0; i < 8; i++) - { - mips_get_info(CPUINFO_INT_REGISTER + MIPS_R16 + i, &mipsinfo); - psx_ram[((a0&0x1fffff)+12+(i*4))/4] = LE32(mipsinfo.i); - } - - // GP - mips_get_info(CPUINFO_INT_REGISTER + MIPS_R28, &mipsinfo); - psx_ram[((a0&0x1fffff)+44)/4] = LE32(mipsinfo.i); - - // v0 = 0 - mipsinfo.i = 0; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - break; - - case 0x18: // strncmp - { - uint8 *dst, *src; - - #if DEBUG_HLE_BIOS - printf("HLEBIOS: strncmp(%08x, %08x, %d)\n", a0, a1, a2); - #endif - - dst = (uint8 *)psx_ram; - src = (uint8 *)psx_ram; - dst += (a0 & 0x1fffff); - src += (a1 & 0x1fffff); - - // v0 = result - mipsinfo.i = strncmp((char *)dst, (char *)src, a2); - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - } - break; - - case 0x19: // strcpy - { - uint8 *dst, *src; - - #if DEBUG_HLE_BIOS - printf("HLEBIOS: strcpy(%08x, %08x)\n", a0, a1); - #endif - - dst = (uint8 *)psx_ram; - src = (uint8 *)psx_ram; - dst += (a0 & 0x1fffff); - src += (a1 & 0x1fffff); - - while (*src) - { - *dst = *src; - dst++; - src++; - } - - // v0 = a0 - mipsinfo.i = a0; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - } - break; - - case 0x28: // bzero - { - uint8 *dst; - - #if DEBUG_HLE_BIOS - printf("HLEBIOS: bzero(%08x, %08x)\n", a0, a1); - #endif - - dst = (uint8 *)psx_ram; - dst += (a0 & 0x1fffff); - memset(dst, 0, a1); - } - break; - - case 0x2a: // memcpy - { - uint8 *dst, *src; - - #if DEBUG_HLE_BIOS - printf("HLEBIOS: memcpy(%08x, %08x, %08x)\n", a0, a1, a2); - #endif - - dst = (uint8 *)psx_ram; - src = (uint8 *)psx_ram; - dst += (a0 & 0x1fffff); - src += (a1 & 0x1fffff); - - while (a2) - { - *dst = *src; - dst++; - src++; - a2--; - } - - // v0 = a0 - mipsinfo.i = a0; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - } - break; - - case 0x2b: // memset - { - uint8 *dst; - - #if DEBUG_HLE_BIOS - printf("HLEBIOS: memset(%08x, %08x, %08x)\n", a0, a1, a2); - #endif - - dst = (uint8 *)psx_ram; - dst += (a0 & 0x1fffff); - - while (a2) - { - *dst = a1; - dst++; - a2--; - } - - // v0 = a0 - mipsinfo.i = a0; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - } - break; - - case 0x2f: // rand - #if DEBUG_HLE_BIOS - printf("HLEBIOS: rand\n"); - #endif - - // v0 = result - mipsinfo.i = 1 + (int)(32767.0*rand()/(RAND_MAX+1.0)); - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - break; - - case 0x30: // srand - #if DEBUG_HLE_BIOS - printf("HLEBIOS: srand(%x)\n", a0); - #endif - srand(a0); - break; - - case 0x33: // malloc - { - uint32 chunk, fd; - - #if DEBUG_HLE_BIOS - printf("HLEBIOS: malloc(%x)\n", a0); - #endif - - chunk = heap_addr; - - // find a free block that's big enough - while ((a0 > LE32(psx_ram[(chunk+BLK_SIZE)/4])) || - (LE32(psx_ram[(chunk+BLK_STAT)/4]) == 1)) - { - chunk = LE32(psx_ram[(chunk+BLK_FD)]); - } - - // split free block - fd = chunk + 16 + a0; // free block starts after block record and allocation size - psx_ram[(fd+BLK_STAT)/4] = psx_ram[(chunk+BLK_STAT)/4]; - psx_ram[(fd+BLK_SIZE)/4] = LE32(LE32(psx_ram[(chunk+BLK_SIZE)/4]) - a0); - psx_ram[(fd+BLK_FD)/4] = psx_ram[(chunk+BLK_FD)/4]; - psx_ram[(fd+BLK_BK)/4] = chunk; - - psx_ram[(chunk+BLK_STAT)/4] = LE32(1); - psx_ram[(chunk+BLK_SIZE)/4] = LE32(a0); - psx_ram[(chunk+BLK_FD)/4] = LE32(fd); - - mipsinfo.i = chunk + 16; - mipsinfo.i |= 0x80000000; - #if DEBUG_HLE_BIOS - printf("== %08x\n", mipsinfo.i); - #endif - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - } - break; - - case 0x39: // InitHeap - // heap address in A0, length in A1 - #if DEBUG_HLE_BIOS - printf("HLEBIOS: InitHeap(%08x, %08x)\n", a0, a1); - #endif - - heap_addr = a0 & 0x3fffffff; - - psx_ram[(heap_addr+BLK_STAT)/4] = LE32(0); - psx_ram[(heap_addr+BLK_FD)/4] = LE32(0); - psx_ram[(heap_addr+BLK_BK)/4] = LE32(0); - - // if heap size out of range, clamp it - if (((a0 & 0x1fffff) + a1) >= 2*1024*1024) - { - psx_ram[(heap_addr+BLK_SIZE)/4] = LE32(0x1ffffc - (a0 & 0x1fffff)); - } - else - { - psx_ram[(heap_addr+BLK_SIZE)/4] = LE32(a1); - } - break; - - case 0x3f: // printf - #if DEBUG_HLE_BIOS - printf("HLEBIOS: printf(%08x) = %s\n", a0, &psx_ram[(a0&0x1fffff)/4]); - #endif - break; - - case 0x72: //__96_remove - #if DEBUG_HLE_BIOS - printf("HLEBIOS: __96_remove\n"); - #endif - break; - - default: - #if DEBUG_HLE_BIOS - printf("Unknown BIOS A0 call = %x\n", subcall); - #endif - break; - } - break; - - case 0xb0: // b0 syscalls - switch (subcall) - { - case 0x07: // DeliverEvent - { - int ev, spec; - - - ev = calc_ev(a0); - spec = calc_spec(a1); - - #if DEBUG_HLE_BIOS - printf("HLEBIOS: DeliverEvent(ev %d, spec %d)\n", ev, spec); - #endif - - if (Event[ev][spec].status != LE32(EvStACTIVE)) - { - #if DEBUG_HLE_BIOS - printf("event not active\n"); - #endif - return; - } - - // if interrupt mode, do the call - if (Event[ev][spec].mode == LE32(EvMdINTR)) - { - #if DEBUG_HLE_BIOS - printf("INTR type, need to call handler %x\n", LE32(Event[ev][spec].fhandler)); - #endif - } - else - { - Event[ev][spec].status = LE32(EvStALREADY); - } - } - break; - - case 0x08: // OpenEvent - { - int ev, spec; - - ev = calc_ev(a0); - spec = calc_spec(a1); - - #if DEBUG_HLE_BIOS - printf("HLEBIOS: OpenEvent(%08x, %08x, %08x, %08x) = ev %d spec %d\n", a0, a1, a2, a3, ev, spec); - if (ev >= 64 && ev <= 67) - { - printf("HLEBIOS: event %d maps to root counter %d\n", ev, ev-64); - } - #endif - - Event[ev][spec].status = LE32(EvStWAIT); - Event[ev][spec].mode = LE32(a2); - Event[ev][spec].fhandler = LE32(a3); - - // v0 = ev | spec<<8; - mipsinfo.i = ev | (spec<<8); - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - } - break; - - case 0x0a: // WaitEvent - { - int ev, spec; - - ev = a0 & 0xff; - spec = (a0 >> 8) & 0xff; - - mips_get_info(CPUINFO_INT_REGISTER + MIPS_R31, &mipsinfo); - #if DEBUG_HLE_BIOS - printf("HLEBIOS: WaitEvent(ev %d spec %d) PC=%x\n", ev, spec, mipsinfo.i); - #endif - - Event[ev][spec].status = LE32(EvStACTIVE); - - // v0 = 1 - mipsinfo.i = 1; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - - WAI = 1; - mips_shorten_frame(); - } - break; - - case 0x0b: // TestEvent - { - int ev, spec; - - ev = a0 & 0xff; - spec = (a0 >> 8) & 0xff; - - #if DEBUG_HLE_BIOS - printf("HLEBIOS: TestEvent(ev %d spec %d)\n", ev, spec); - #endif - - // v0 = (is event ready?) - if (Event[ev][spec].status == LE32(EvStALREADY)) - { - Event[ev][spec].status = LE32(EvStACTIVE); - mipsinfo.i = 1; - } - else - { - mipsinfo.i = 0; - } - - WAI = 1; - - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - - // it looks like this sets v1 to something non-zero too - // (code in Crash 2 & 3 actually relies on that behavior) - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R3, &mipsinfo); - } - break; - - case 0x0c: // EnableEvent - { - int ev, spec; - - ev = a0 & 0xff; - spec = (a0 >> 8) & 0xff; - - #if DEBUG_HLE_BIOS - printf("HLEBIOS: EnableEvent(ev %d spec %d)\n", ev, spec); - #endif - - Event[ev][spec].status = LE32(EvStACTIVE); - - // v0 = 1 - mipsinfo.i = 1; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - } - break; - - case 0x0d: // DisableEvent - { - int ev, spec; - - ev = a0 & 0xff; - spec = (a0 >> 8) & 0xff; - - #if DEBUG_HLE_BIOS - printf("HLEBIOS: DisableEvent(ev %d spec %d)\n", ev, spec); - #endif - - Event[ev][spec].status = LE32(EvStWAIT); - - // v0 = 1 - mipsinfo.i = 1; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - } - break; - - case 0x17: // ReturnFromException - for (i = 0; i < 32; i++) - { - mipsinfo.i = irq_regs[i]; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R0 + i, &mipsinfo); - } - - mipsinfo.i = irq_regs[32]; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_HI, &mipsinfo); - mipsinfo.i = irq_regs[33]; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_LO, &mipsinfo); - mipsinfo.i = mips_get_ePC(); -// printf("ReturnFromException: IRQ state %x\n", irq_data & irq_mask); -// printf("HLEBIOS: ReturnFromException, cause = %08x, PC = %08x\n", mips_get_cause(), mipsinfo.i); - mips_set_info(CPUINFO_INT_PC, &mipsinfo); - - status = mips_get_status(); - status = (status & 0xfffffff0) | ((status & 0x3c)>>2); - mips_set_status(status); - return; // force return to avoid PC=RA below - break; - - case 0x19: // HookEntryInt - #if DEBUG_HLE_BIOS - printf("HLEBIOS: HookEntryInt(%08x)\n", a0); - #endif - entry_int = a0; - break; - - case 0x3f: // puts -// printf("HLEBIOS: puts\n"); - break; - - case 0x5b: // ChangeClearPAD - #if DEBUG_HLE_BIOS - printf("HLEBIOS: ChangeClearPAD\n"); - #endif - break; - - default: - #if DEBUG_HLE_BIOS - printf("Unknown BIOS B0 call = %x\n", subcall); - #endif - break; - } - break; - - case 0xc0: // c0 syscalls - switch (subcall) - { - case 0xa: // ChangeClearRCnt - #if DEBUG_HLE_BIOS - printf("HLEBIOS: ChangeClearRCnt(%08x, %08x)\n", a0, a1); - #endif - - // v0 = (a0*4)+0x8600 - mipsinfo.i = LE32(psx_ram[((a0<<2) + 0x8600)/4]); - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - - // (a0*4)+0x8600 = a1; - psx_ram[((a0<<2) + 0x8600)/4] = LE32(a1); - break; - - default: - #if DEBUG_HLE_BIOS - printf("Unknown BIOS C0 call = %x\n", subcall); - #endif - break; - } - break; - } - - // PC = RA - mips_get_info(CPUINFO_INT_REGISTER + MIPS_R31, &mipsinfo); - mips_set_info(CPUINFO_INT_PC, &mipsinfo); -} - -// root counters - -void psx_hw_runcounters(void) -{ - int i, j; - union cpuinfo mipsinfo; - - // don't process any IRQ sources when interrupts are suspended - if (!intr_susp) - { - if (dma4_delay) - { - dma4_delay--; - - if (dma4_delay == 0) - { - SPU2interruptDMA4(); - - if (dma4_cb) - { - call_irq_routine(dma4_cb, dma4_flag); - } - } - } - - if (dma7_delay) - { - dma7_delay--; - - if (dma7_delay == 0) - { - SPU2interruptDMA7(); - - if (dma7_cb) - { - call_irq_routine(dma7_cb, dma7_flag); - } - } - } - - for (i = 0; i < iNumThreads; i++) - { - if (threads[i].iState == TS_WAITDELAY) - { - if (threads[i].waitparm > CLOCK_DIV) - { - threads[i].waitparm -= CLOCK_DIV; - } - else // time's up - { - threads[i].waitparm = 0; - threads[i].iState = TS_READY; - - timerexp = 1; - - ps2_reschedule(); - } - } - } - - sys_time += 836; - - if (iNumTimers > 0) - { - for (i = 0; i < iNumTimers; i++) - { - if (iop_timers[i].iActive > 0) - { - iop_timers[i].count += 836; - if (iop_timers[i].count >= iop_timers[i].target) - { - iop_timers[i].count -= iop_timers[i].target; - - // printf("Timer %d: handler = %08x, param = %08x\n", i, iop_timers[i].handler, iop_timers[i].hparam); - call_irq_routine(iop_timers[i].handler, iop_timers[i].hparam); - - timerexp = 1; - } - } - } - } - } - -// PS1 root counters - for (i = 0; i < 3; i++) - { - if ((!(root_cnts[i].mode & RC_EN)) && (root_cnts[i].mode != 0)) - { - if (root_cnts[i].mode & RC_DIV8) - { - root_cnts[i].count += 768/8; - } - else - { - root_cnts[i].count += 768; - } - - if (root_cnts[i].count >= root_cnts[i].target) - { - if (!(root_cnts[i].mode & RC_RESET)) - { - root_cnts[i].mode |= RC_EN; - } - else - { - root_cnts[i].count %= root_cnts[i].target; - } - - psx_irq_set(1<<(4+i)); - } - } - } -} - -// PEOpS callbacks - -void SPUirq(void) -{ -// psx_irq_set(0x200); -} - -// PSXCPU callbacks - -uint8 program_read_byte_32le(offs_t address) -{ - switch (address & 0x3) - { - case 0: - return psx_hw_read(address, 0xffffff00); - break; - case 1: - return psx_hw_read(address, 0xffff00ff)>>8; - break; - case 2: - return psx_hw_read(address, 0xff00ffff)>>16; - break; - case 3: - return psx_hw_read(address, 0x00ffffff)>>24; - break; - } -} - -uint16 program_read_word_32le(offs_t address) -{ - if (address & 2) - return psx_hw_read(address, 0x0000ffff)>>16; - - return psx_hw_read(address, 0xffff0000); -} - -uint32 program_read_dword_32le(offs_t address) -{ - return psx_hw_read(address, 0); -} - -void program_write_byte_32le(offs_t address, uint8 data) -{ - switch (address & 0x3) - { - case 0: - psx_hw_write(address, data, 0xffffff00); - break; - case 1: - psx_hw_write(address, data<<8, 0xffff00ff); - break; - case 2: - psx_hw_write(address, data<<16, 0xff00ffff); - break; - case 3: - psx_hw_write(address, data<<24, 0x00ffffff); - break; - } -} - -void program_write_word_32le(offs_t address, uint16 data) -{ - if (address & 2) - { - psx_hw_write(address, data<<16, 0x0000ffff); - return; - } - - psx_hw_write(address, data, 0xffff0000); -} - -void program_write_dword_32le(offs_t address, uint32 data) -{ - psx_hw_write(address, data, 0); -} - -// sprintf replacement -static iop_sprintf(char *out, char *fmt, uint32 pstart) -{ - char temp[64], tfmt[64]; - char *cf, *pstr; - union cpuinfo mipsinfo; - int curparm, fp, isnum; - - curparm = pstart; - cf = fmt; - - while (*cf != '\0') - { - if (*cf != '%') - { - if (*cf == 27) - { - *out++ = '['; - *out++ = 'E'; - *out++ = 'S'; - *out++ = 'C'; - *out = ']'; - } - else - { - *out = *cf; - } - out++; - cf++; - } - else // got format - { - cf++; - - tfmt[0] = '%'; - fp = 1; - while (((*cf >= '0') && (*cf <= '9')) || (*cf == '.')) - { - tfmt[fp] = *cf; - fp++; - cf++; - } - - tfmt[fp] = *cf; - tfmt[fp+1] = '\0'; - - isnum = 0; - switch (*cf) - { - case 'x': - case 'X': - case 'd': - case 'D': - case 'c': - case 'C': - case 'u': - case 'U': - isnum = 1; - break; - } - -// printf("]]] temp format: [%s] [%d]\n", tfmt, isnum); - - if (isnum) - { - mips_get_info(curparm, &mipsinfo); -// printf("parameter %d = %x\n", curparm-pstart, mipsinfo.i); - curparm++; - sprintf(temp, tfmt, (int32)mipsinfo.i); - } - else - { - mips_get_info(curparm, &mipsinfo); - curparm++; - - pstr = (char *)psx_ram; - pstr += (mipsinfo.i & 0x1fffff); - - sprintf(temp, tfmt, pstr); - } - - pstr = &temp[0]; - while (*pstr != '\0') - { - *out = *pstr; - out++; - pstr++; - } - - cf++; - } - } - - *out = '\0'; -} - -// PS2 IOP callbacks -void psx_iop_call(uint32 pc, uint32 callnum) -{ - uint32 scan; - char *mname, *str1, *str2, *str3, name[9], out[512]; - uint32 a0, a1, a2, a3; - union cpuinfo mipsinfo; - int i; - -// printf("IOP call @ %08x\n", pc); - - // prefetch parameters - mips_get_info(CPUINFO_INT_REGISTER + MIPS_R4, &mipsinfo); - a0 = mipsinfo.i; - mips_get_info(CPUINFO_INT_REGISTER + MIPS_R5, &mipsinfo); - a1 = mipsinfo.i; - mips_get_info(CPUINFO_INT_REGISTER + MIPS_R6, &mipsinfo); - a2 = mipsinfo.i; - mips_get_info(CPUINFO_INT_REGISTER + MIPS_R7, &mipsinfo); - a3 = mipsinfo.i; - - scan = (pc&0x0fffffff)/4; - while ((psx_ram[scan] != LE32(0x41e00000)) && (scan >= (0x10000/4))) - { - scan--; - } - - if (psx_ram[scan] != LE32(0x41e00000)) - { - printf("FATAL ERROR: couldn't find IOP link signature\n"); - return; - } - - scan += 3; // skip zero and version - memcpy(name, &psx_ram[scan], 8); - name[8] = '\0'; - -// printf("IOP: call module [%s] service %d (PC=%08x)\n", name, callnum, pc); - - if (!strcmp(name, "stdio")) - { - switch (callnum) - { - case 4: // printf - mname = (char *)psx_ram; - mname += a0 & 0x1fffff; - mname += (a0 & 3); - - iop_sprintf(out, mname, CPUINFO_INT_REGISTER + MIPS_R5); // a1 is first parm - - /* if (out[strlen(out)-1] != '\n') - { - strcat(out, "\n"); - }*/ - - #if DEBUG_HLE_IOP - printf("%s", out); - #endif - break; - - default: - printf("IOP: Unhandled service %d for module %s\n", callnum, name); - break; - } - } - else if (!strcmp(name, "sifman")) - { - switch (callnum) - { - case 5: // sceSifInit - #if DEBUG_HLE_IOP - printf("IOP: sceSifInit()\n"); - #endif - - mipsinfo.i = 0; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - break; - - case 7: // sceSifSetDma - #if DEBUG_HLE_IOP - printf("IOP: sceSifSetDma(%08x %08x)\n", a0, a1); - #endif - - mipsinfo.i = 1; // nonzero = success - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - break; - - case 8: // sceSifDmaStat - #if DEBUG_HLE_IOP - printf("IOP: sceSifDmaStat(%08x)\n", a0); - #endif - - mipsinfo.i = -1; // dma completed - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - break; - - case 29: // sceSifCheckInit - #if DEBUG_HLE_IOP - printf("IOP: sceSifCheckInit()\n"); - #endif - - mipsinfo.i = 1; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - break; - - default: - printf("IOP: Unhandled service %d for module %s\n", callnum, name); - break; - } - } - else if (!strcmp(name, "thbase")) - { - uint32 newAlloc; - - switch (callnum) - { - case 4: // CreateThread - #if DEBUG_THREADING - printf("IOP: CreateThread(%08x)\n", a0); - #endif - a0 &= 0x1fffff; - a0 /= 4; - #if DEBUG_THREADING - printf(" : flags %x routine %08x pri %x stacksize %d refCon %08x\n", - psx_ram[a0], psx_ram[a0+1], psx_ram[a0+2], psx_ram[a0+3], psx_ram[a0+4]); - #endif - - newAlloc = psf2_get_loadaddr(); - // force 16-byte alignment - if (newAlloc & 0xf) - { - newAlloc &= ~0xf; - newAlloc += 16; - } - psf2_set_loadaddr(newAlloc + LE32(psx_ram[a0+3])); - - threads[iNumThreads].iState = TS_CREATED; - threads[iNumThreads].stackloc = newAlloc; - threads[iNumThreads].flags = LE32(psx_ram[a0]); - threads[iNumThreads].routine = LE32(psx_ram[a0+2]); - threads[iNumThreads].stacksize = LE32(psx_ram[a0+3]); - threads[iNumThreads].refCon = LE32(psx_ram[a0+4]); - - mipsinfo.i = iNumThreads; - iNumThreads++; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - break; - - case 6: // StartThread - #if DEBUG_THREADING - printf("IOP: StartThread(%d %d)\n", a0, a1); - #endif - - FreezeThread(iCurThread, 1); - ThawThread(a0); - iCurThread = a0; - break; - - case 20:// GetThreadID - #if DEBUG_THREADING - printf("IOP: GetThreadId()\n"); - #endif - - mipsinfo.i = iCurThread; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - break; - - case 24:// SleepThread - #if DEBUG_THREADING - mips_get_info(CPUINFO_INT_REGISTER + MIPS_R31, &mipsinfo); - printf("IOP: SleepThread() [curThread %d, PC=%x]\n", iCurThread, mipsinfo.i); - #endif - - FreezeThread(iCurThread, 1); - threads[iCurThread].iState = TS_SLEEPING; - iCurThread = -1; - - ps2_reschedule(); - break; - - case 25:// WakeupThread - #if DEBUG_THREADING - printf("IOP: WakeupThread(%d)\n", a0); - #endif - - // set thread to "ready to go" - threads[a0].iState = TS_READY; - break; - - case 26:// iWakeupThread - #if DEBUG_THREADING - printf("IOP: iWakeupThread(%d)\n", a0); - #endif - - // set thread to "ready to go" if it's not running - if (threads[a0].iState != TS_RUNNING) - { - threads[a0].iState = TS_READY; - } - break; - - case 33:// DelayThread - { - double dTicks; - int i; - - #if DEBUG_THREADING - mips_get_info(CPUINFO_INT_REGISTER + MIPS_R31, &mipsinfo); - printf("IOP: DelayThread(%d) (PC=%x) [curthread = %d]\n", a0, mipsinfo.i, iCurThread); - #endif - - if (a0 < 100) - { - a0 = 100; - } - dTicks = (double)a0; - - FreezeThread(iCurThread, 1); - threads[iCurThread].iState = TS_WAITDELAY; - dTicks /= (double)1000000.0; - dTicks *= (double)36864000.0; // 768*48000 = IOP native-mode clock rate - threads[iCurThread].waitparm = (uint32)dTicks; - iCurThread = -1; - - ps2_reschedule(); - } - break; - - case 34://GetSystemTime - #if DEBUG_HLE_IOP - printf("IOP: GetSystemTime(%x)\n", a0); - #endif - - a0 &= 0x1fffff; - a0 /= 4; - - psx_ram[a0] = LE32(sys_time & 0xffffffff); // low - psx_ram[a0+1] = LE32(sys_time >> 32); // high - - mipsinfo.i = 0; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - break; - - case 39:// USec2SysClock - { - uint64 dTicks = (uint64)a0; - uint32 hi, lo; - - #if DEBUG_HLE_IOP - printf("IOP: USec2SysClock(%d %08x)\n", a0, a1); - #endif - - dTicks *= (uint64)36864000; - dTicks /= (uint64)1000000; - - hi = dTicks>>32; - lo = dTicks & 0xffffffff; - - psx_ram[((a1 & 0x1fffff)/4)] = LE32(lo); - psx_ram[((a1 & 0x1fffff)/4)+1] = LE32(hi); - - mipsinfo.i = 0; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - } - break; - - case 40://SysClock2USec - { - uint64 temp; - uint32 seconds, usec; - - #if DEBUG_HLE_IOP - printf("IOP: SysClock2USec(%08x %08x %08x)\n", a0, a1, a2); - #endif - - a0 &= 0x1fffff; - a1 &= 0x1fffff; - a2 &= 0x1fffff; - a0 /= 4; - a1 /= 4; - a2 /= 4; - - temp = LE32(psx_ram[a0]); - temp |= (uint64)LE32(psx_ram[a0+1])<<32; - - temp *= (uint64)1000000; - temp /= (uint64)36864000; - - // temp now is USec - seconds = (temp / 1000000) & 0xffffffff; - usec = (temp % 1000000) & 0xffffffff; - - psx_ram[a1] = LE32(seconds); - psx_ram[a2] = LE32(usec); - } - break; - - default: - printf("IOP: Unhandled service %d for module %s\n", callnum, name); - break; - } - } - else if (!strcmp(name, "thevent")) - { - switch (callnum) - { - case 4: // CreateEventFlag - mips_get_info(CPUINFO_INT_REGISTER + MIPS_R31, &mipsinfo); - #if DEBUG_HLE_IOP - printf("IOP: CreateEventFlag(%08x) (PC=%x)\n", a0, mipsinfo.i); - #endif - - a0 &= 0x1fffff; - a0 /= 4; - - evflags[iNumFlags].type = LE32(psx_ram[a0]); - evflags[iNumFlags].value = LE32(psx_ram[a0+1]); - evflags[iNumFlags].param = LE32(psx_ram[a0+2]); - evflags[iNumFlags].inUse = 1; - - #if DEBUG_HLE_IOP - printf(" Flag %02d: type %d init %08x param %08x\n", iNumFlags, evflags[iNumFlags].type, evflags[iNumFlags].value, evflags[iNumFlags].param); - #endif - - mipsinfo.i = iNumFlags+1; - iNumFlags++; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - break; - - case 6: // SetEventFlag - a0--; - #if DEBUG_HLE_IOP - printf("IOP: SetEventFlag(%d %08x)\n", a0, a1); - #endif - - evflags[a0].value |= a1; - - mipsinfo.i = 0; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - break; - - case 7: // iSetEventFlag - a0--; - #if DEBUG_HLE_IOP - printf("IOP: iSetEventFlag(%08x %08x)\n", a0, a1); - #endif - - evflags[a0].value |= a1; - - mipsinfo.i = 0; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - - for (i=0; i < iNumThreads; i++) - { - if ((threads[i].iState == TS_WAITEVFLAG) && (threads[i].waitparm == a0)) - { - threads[i].iState = TS_READY; - } - } - break; - - case 8: // ClearEventFlag - a0--; - mips_get_info(CPUINFO_INT_REGISTER + MIPS_R31, &mipsinfo); - #if DEBUG_HLE_IOP - printf("IOP: ClearEventFlag(%d %08x) (PC=%x)\n", a0, a1, mipsinfo.i); - #endif - - evflags[a0].value &= a1; - - mipsinfo.i = 0; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - break; - - case 9: // iClearEventFlag - a0--; - #if DEBUG_HLE_IOP - printf("IOP: iClearEventFlag(%d %08x)\n", a0, a1); - #endif - - evflags[a0].value &= a1; - - mipsinfo.i = 0; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - break; - - case 10:// WaitEventFlag - a0--; - #if DEBUG_HLE_IOP - mips_get_info(CPUINFO_INT_REGISTER + MIPS_R31, &mipsinfo); - printf("IOP: WaitEventFlag(%d %08x %d %08x PC=%x)\n", a0, a1, a2, a3, mipsinfo.i); - #endif - - // if we're not set, freeze this thread - if (!(evflags[a0].value & a1)) - { - FreezeThread(iCurThread, 1); - threads[iCurThread].iState = TS_WAITEVFLAG; - threads[iCurThread].waitparm = a0; - iCurThread = -1; - - ps2_reschedule(); - } - else - { - mipsinfo.i = 0; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - } - break; - - default: - printf("IOP: Unhandled service %d for module %s\n", callnum, name); - break; - } - } - else if (!strcmp(name, "thsemap")) - { - int foundthread; - - switch (callnum) - { - case 4: // CreateSema - #if DEBUG_HLE_IOP - printf("IOP: CreateSema(%08x)\n", a0); - #endif - - mipsinfo.i = -1; - for (i = 0; i < SEMA_MAX; i++) - { - if (!semaphores[i].inuse) - { - mipsinfo.i = i; - break; - } - } - - if (mipsinfo.i == -1) - { - printf("IOP: out of semaphores!\n"); - } - - a0 &= 0x7fffffff; - a0 /= 4; - -// printf("Sema %d Parms: %08x %08x %08x %08x\n", mipsinfo.i, psx_ram[a0], psx_ram[a0+1], psx_ram[a0+2], psx_ram[a0+3]); - - if (mipsinfo.i != -1) - { - semaphores[mipsinfo.i].attr = LE32(psx_ram[a0]); - semaphores[mipsinfo.i].option = LE32(psx_ram[a0+1]); - semaphores[mipsinfo.i].init = LE32(psx_ram[a0+2]); - semaphores[mipsinfo.i].max = LE32(psx_ram[a0+3]); - - semaphores[mipsinfo.i].current = semaphores[mipsinfo.i].init; - - semaphores[mipsinfo.i].inuse = 1; - } - - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - break; - - case 6: // SignalSema - #if DEBUG_HLE_IOP - printf("IOP: SignalSema(%d) (current %d)\n", a0, semaphores[a0].current); - #endif - - foundthread = 0; - for (i=0; i < iNumThreads; i++) - { - if ((threads[i].iState == TS_WAITSEMA) && (threads[i].waitparm == a0)) - { - threads[i].iState = TS_READY; - semaphores[a0].threadsWaiting--; - foundthread = 1; - break; - } - } - - mipsinfo.i = 0; - - if (!foundthread) - { - if (semaphores[a0].current < semaphores[a0].max) - { - semaphores[a0].current++; - } - else - { - mipsinfo.i = -420; // semaphore overflow - } - } - - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - break; - - case 7: // iSignalSema - #if DEBUG_HLE_IOP - printf("IOP: iSignalSema(%d)\n", a0); - #endif - - foundthread = 0; - for (i=0; i < iNumThreads; i++) - { - if ((threads[i].iState == TS_WAITSEMA) && (threads[i].waitparm == a0)) - { - threads[i].iState = TS_READY; - semaphores[a0].threadsWaiting--; - foundthread = 1; - break; - } - } - - mipsinfo.i = 0; - - if (!foundthread) - { - if (semaphores[a0].current < semaphores[a0].max) - { - semaphores[a0].current++; - } - else - { - mipsinfo.i = -420; // semaphore overflow - } - } - - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - break; - - case 8: // WaitSema - #if DEBUG_HLE_IOP - mips_get_info(CPUINFO_INT_REGISTER + MIPS_R31, &mipsinfo); - printf("IOP: WaitSema(%d) (cnt %d) (th %d) (PC=%x)\n", a0, iCurThread, semaphores[a0].current, mipsinfo.i); - #endif - - if (semaphores[a0].current > 0) - { - semaphores[a0].current--; - } - else - { - FreezeThread(iCurThread, 1); - threads[iCurThread].iState = TS_WAITSEMA; - threads[iCurThread].waitparm = a0; - ps2_reschedule(); - } - - mipsinfo.i = 0; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - break; - - default: - printf("IOP: Unhandled service %d for module %s\n", callnum, name); - break; - } - } - else if (!strcmp(name, "timrman")) - { - switch (callnum) - { - case 4: // AllocHardTimer - #if DEBUG_HLE_IOP - printf("IOP: AllocHardTimer(%d %d %d)\n", a0, a1, a2); - #endif - // source, size, prescale - - if (a1 != 32) - { - printf("IOP: AllocHardTimer doesn't support 16-bit timers!\n"); - } - - iop_timers[iNumTimers].source = a0; - iop_timers[iNumTimers].prescale = a2; - - mipsinfo.i = iNumTimers+1; - iNumTimers++; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - break; - - case 6: // FreeHardTimer - #if DEBUG_HLE_IOP - printf("IOP: FreeHardTimer(%d)\n", a0); - #endif - mipsinfo.i = 0; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - break; - - case 10:// GetTimerCounter - mipsinfo.i = iop_timers[a0-1].count; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - break; - - case 20: // SetTimerHandler - #if DEBUG_HLE_IOP - printf("IOP: SetTimerHandler(%d %d %08x %08x)\n", a0, a1, a2, a3); - #endif - // id, compare, handler, common (last is param for handler) - - iop_timers[a0-1].target = a1; - iop_timers[a0-1].handler = a2; - iop_timers[a0-1].hparam = a3; - - mipsinfo.i = 0; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - break; - - case 22: // SetupHardTimer - #if DEBUG_HLE_IOP - printf("IOP: SetupHardTimer(%d %d %d %d)\n", a0, a1, a2, a3); - #endif - // id, source, mode, prescale - - iop_timers[a0-1].source = a1; - iop_timers[a0-1].mode = a2; - iop_timers[a0-1].prescale = a3; - - mipsinfo.i = 0; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - break; - - case 23: // StartHardTimer - #if DEBUG_HLE_IOP - printf("IOP: StartHardTimer(%d)\n", a0); - #endif - - iop_timers[a0-1].iActive = 1; - iop_timers[a0-1].count = 0; - - mipsinfo.i = 0; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - break; - - case 24: // StopHardTimer - #if DEBUG_HLE_IOP - printf("IOP: StopHardTimer(%d)\n", a0); - #endif - - iop_timers[a0-1].iActive = 0; - - mipsinfo.i = 0; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - break; - - default: - printf("IOP: Unhandled service %d for module %s\n", callnum, name); - break; - } - } - else if (!strcmp(name, "sysclib")) - { - switch (callnum) - { - case 12: // memcpy - { - uint8 *dst, *src; - - #if DEBUG_HLE_IOP - printf("IOP: memcpy(%08x, %08x, %d)\n", a0, a1, a2); - #endif - - dst = (uint8 *)&psx_ram[(a0&0x1fffff)/4]; - src = (uint8 *)&psx_ram[(a1&0x1fffff)/4]; - // get exact byte alignment - dst += a0 % 4; - src += a1 % 4; - - while (a2) - { - *dst = *src; - dst++; - src++; - a2--; - } - - // v0 = a0 - mipsinfo.i = a0; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - } - break; - - case 13: // memmove - { - uint8 *dst, *src; - - #if DEBUG_HLE_IOP - printf("IOP: memmove(%08x, %08x, %d)\n", a0, a1, a2); - #endif - - dst = (uint8 *)&psx_ram[(a0&0x1fffff)/4]; - src = (uint8 *)&psx_ram[(a1&0x1fffff)/4]; - // get exact byte alignment - dst += a0 % 4; - src += a1 % 4; - - dst += a2 - 1; - src += a2 - 1; - - while (a2) - { - *dst = *src; - dst--; - src--; - a2--; - } - - // v0 = a0 - mipsinfo.i = a0; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - } - break; - - case 14: // memset - { - uint8 *dst; - - #if DEBUG_HLE_IOP - mips_get_info(CPUINFO_INT_REGISTER + MIPS_R31, &mipsinfo); - printf("IOP: memset(%08x, %02x, %d) [PC=%x]\n", a0, a1, a2, mipsinfo.i); - #endif - - dst = (uint8 *)&psx_ram[(a0&0x1fffff)/4]; - dst += (a0 & 3); - - memset(dst, a1, a2); - } - break; - - case 17: // bzero - { - uint8 *dst; - - #if DEBUG_HLE_IOP - printf("IOP: bzero(%08x, %08x)\n", a0, a1); - #endif - - dst = (uint8 *)&psx_ram[(a0&0x1fffff)/4]; - dst += (a0 & 3); - memset(dst, 0, a1); - } - break; - - case 19: // sprintf - mname = (char *)psx_ram; - str1 = (char *)psx_ram; - mname += a0 & 0x1fffff; - str1 += a1 & 0x1fffff; - - #if DEBUG_HLE_IOP - mips_get_info(CPUINFO_INT_REGISTER + MIPS_R31, &mipsinfo); - printf("IOP: sprintf(%08x, %s, ...) [PC=%08x]\n", a0, str1, (uint32)mipsinfo.i); - printf("%x %x %x %x\n", a0, a1, a2, a3); - #endif - - iop_sprintf(mname, str1, CPUINFO_INT_REGISTER + MIPS_R6); // a2 is first parameter - - #if DEBUG_HLE_IOP - printf(" = [%s]\n", mname); - #endif - break; - - case 23: // strcpy - { - uint8 *dst, *src; - - #if DEBUG_HLE_IOP - printf("IOP: strcpy(%08x, %08x)\n", a0, a1); - #endif - - dst = (uint8 *)&psx_ram[(a0&0x1fffff)/4]; - src = (uint8 *)&psx_ram[(a1&0x1fffff)/4]; - // get exact byte alignment - dst += a0 % 4; - src += a1 % 4; - - while (*src != '\0') - { - *dst = *src; - dst++; - src++; - } - *dst = '\0'; - - // v0 = a0 - mipsinfo.i = a0; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - } - break; - - case 27: // strlen - { - char *dst; - - #if DEBUG_HLE_IOP - mips_get_info(CPUINFO_INT_REGISTER + MIPS_R31, &mipsinfo); - printf("IOP: strlen(%08x) [PC=%x]\n", a0, mipsinfo.i); - #endif - - dst = (char *)&psx_ram[(a0&0x1fffff)/4]; - dst += (a0 & 3); - mipsinfo.i = strlen(dst); - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - } - break; - - case 30: // strncpy - { - char *dst, *src; - - #if DEBUG_HLE_IOP - printf("IOP: strncpy(%08x, %08x, %d)\n", a0, a1, a2); - #endif - - dst = (char *)&psx_ram[(a0&0x1fffff)/4]; - src = (char *)&psx_ram[(a1&0x1fffff)/4]; - // get exact byte alignment - dst += a0 % 4; - src += a1 % 4; - - while ((*src != '\0') && (a2 > 0)) - { - *dst = *src; - dst++; - src++; - a2--; - } - *dst = '\0'; - - // v0 = a0 - mipsinfo.i = a0; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - } - break; - - - case 36: // strtol - mname = (char *)&psx_ram[(a0 & 0x1fffff)/4]; - mname += (a0 & 3); - - if (a1) - { - printf("IOP: Unhandled strtol with non-NULL second parm\n"); - } - - mipsinfo.i = strtol(mname, NULL, a2); - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - break; - - default: - printf("IOP: Unhandled service %d for module %s\n", callnum, name); - break; - } - } - else if (!strcmp(name, "intrman")) - { - switch (callnum) - { - case 4: // RegisterIntrHandler - #if DEBUG_HLE_IOP - printf("IOP: RegisterIntrHandler(%d %08x %08x %08x)\n", a0, a1, a2, a3); - #endif - - if (a0 == 9) - { - irq9_fval = a1; - irq9_cb = a2; - irq9_flag = a3; - } - - // DMA4? - if (a0 == 36) - { - dma4_fval = a1; - dma4_cb = a2; - dma4_flag = a3; - } - - // DMA7? - if (a0 == 40) - { - dma7_fval = a1; - dma7_cb = a2; - dma7_flag = a3; - } - break; - - case 5: // ReleaseIntrHandler - #if DEBUG_HLE_IOP - printf("IOP: ReleaseIntrHandler(%d)\n", a0); - #endif - break; - - case 6: // EnableIntr - #if DEBUG_HLE_IOP - printf("IOP: EnableIntr(%d)\n", a0); - #endif - break; - - case 7: // DisableIntr - #if DEBUG_HLE_IOP - printf("IOP: DisableIntr(%d)\n", a0); - #endif - break; - - case 8: // CpuDisableIntr - #if DEBUG_HLE_IOP - printf("IOP: CpuDisableIntr(%d)\n", a0); - #endif - break; - - case 9: // CpuEnableIntr - #if DEBUG_HLE_IOP - printf("IOP: CpuEnableIntr(%d)\n", a0); - #endif - break; - - case 17: // CpuSuspendIntr - #if DEBUG_HLE_IOP - printf("IOP: CpuSuspendIntr\n"); - #endif - - // if already suspended, return an error code - if (intr_susp) - { - mipsinfo.i = -102; - } - else - { - mipsinfo.i = 0; - } - intr_susp = 1; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - break; - - case 18: // CpuResumeIntr - #if DEBUG_HLE_IOP - printf("IOP: CpuResumeIntr\n"); - #endif - intr_susp = 0; - mipsinfo.i = 0; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - break; - - case 23: // QueryIntrContext - #if DEBUG_HLE_IOP - mips_get_info(CPUINFO_INT_REGISTER + MIPS_R31, &mipsinfo); - printf("IOP: QueryIntrContext(PC=%x)\n", mipsinfo.i); - #endif - mipsinfo.i = 0; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - break; - - default: - printf("IOP: Unhandled service %d for module %s\n", callnum, name); - break; - } - } - else if (!strcmp(name, "loadcore")) - { - switch (callnum) - { - case 5: // FlushDcache - #if DEBUG_HLE_IOP - printf("IOP: FlushDcache()\n"); - #endif - break; - - case 6: // RegisterLibraryEntries - a0 &= 0x1fffff; - #if DEBUG_HLE_IOP - mips_get_info(CPUINFO_INT_REGISTER + MIPS_R31, &mipsinfo); - printf("IOP: RegisterLibraryEntries(%08x) (PC=%x)\n", a0, mipsinfo.i); - #endif - - if (psx_ram[a0/4] == LE32(0x41c00000)) - { - a0 += 3*4; - memcpy(®libs[iNumLibs].name, &psx_ram[a0/4], 8); - reglibs[iNumLibs].name[8] = '\0'; - #if DEBUG_HLE_IOP - printf("Lib name [%s]\n", ®libs[iNumLibs].name); - #endif - a0 += 2*4; - reglibs[iNumLibs].dispatch = a0; - iNumLibs++; - } - else - { - printf("ERROR: Entry table signature missing\n"); - - } - - mipsinfo.i = 0; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - break; - - default: - printf("IOP: Unhandled service %d for module %s\n", callnum, name); - break; - } - } - else if (!strcmp(name, "sysmem")) - { - uint32 newAlloc; - - switch (callnum) - { - case 4: // AllocMemory - newAlloc = psf2_get_loadaddr(); - // make sure we're 16-byte aligned - if (newAlloc & 15) - { - newAlloc &= ~15; - newAlloc += 16; - } - - if (a1 & 15) - { - a1 &= ~15; - a1 += 16; - } - - if (a1 == 1114112) // HACK for crappy code in Shadow Hearts rip that assumes the buffer address - { - printf("SH Hack: was %x now %x\n", newAlloc, 0x60000); - newAlloc = 0x60000; - } - - psf2_set_loadaddr(newAlloc + a1); - - #if DEBUG_HLE_IOP - printf("IOP: AllocMemory(%d, %d, %x) = %08x\n", a0, a1, a2, newAlloc|0x80000000); - #endif - - mipsinfo.i = newAlloc; // | 0x80000000; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - break; - - case 5: // FreeMemory - #if DEBUG_HLE_IOP - printf("IOP: FreeMemory(%x)\n", a0); - #endif - break; - - case 7: // QueryMaxFreeMemSize - #if DEBUG_HLE_IOP - printf("IOP: QueryMaxFreeMemSize\n"); - #endif - - mipsinfo.i = (2*1024*1024) - psf2_get_loadaddr(); - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - break; - - case 8: // QueryTotalFreeMemSize - #if DEBUG_HLE_IOP - printf("IOP: QueryTotalFreeMemSize\n"); - #endif - - mipsinfo.i = (2*1024*1024) - psf2_get_loadaddr(); - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - break; - - case 14: // Kprintf - mname = (char *)psx_ram; - mname += a0 & 0x1fffff; - mname += (a0 & 3); - - iop_sprintf(out, mname, CPUINFO_INT_REGISTER + MIPS_R5); // a1 is first parm - - if (out[strlen(out)-1] != '\n') - { - strcat(out, "\n"); - } - - // filter out ESC characters - { - int ch; - - for (ch = 0; ch < strlen(out); ch++) - { - if (out[ch] == 27) - { - out[ch] = ']'; - } - } - } - - #if DEBUG_HLE_IOP - mips_get_info(CPUINFO_INT_REGISTER + MIPS_R31, &mipsinfo); - printf("KTTY: %s [PC=%x]\n", out, mipsinfo.i); - #endif - - #if 0 - { - FILE *f; - f = fopen("psxram.bin", "wb"); - fwrite(psx_ram, 2*1024*1024, 1, f); - fclose(f); - } - #endif - break; - - default: - printf("IOP: Unhandled service %d for module %s\n", callnum, name); - break; - } - } - else if (!strcmp(name, "modload")) - { - uint8 *tempmem; - uint32 newAlloc; - - switch (callnum) - { - case 7: // LoadStartModule - mname = (char *)&psx_ram[(a0 & 0x1fffff)/4]; - mname += 8; - str1 = (char *)&psx_ram[(a2 & 0x1fffff)/4]; - #if DEBUG_HLE_IOP - printf("LoadStartModule: %s\n", mname); - #endif - - // get 2k for our parameters - newAlloc = psf2_get_loadaddr(); - // force 16-byte alignment - if (newAlloc & 0xf) - { - newAlloc &= ~0xf; - newAlloc += 16; - } - psf2_set_loadaddr(newAlloc + 2048); - - tempmem = (uint8 *)malloc(2*1024*1024); - if (psf2_load_file(mname, tempmem, 2*1024*1024) != 0xffffffff) - { - uint32 start; - int i; - - start = psf2_load_elf(tempmem, 2*1024*1024); - - if (start != 0xffffffff) - { - uint32 args[20], numargs = 1, argofs; - uint8 *argwalk = (uint8 *)psx_ram, *argbase; - - argwalk += (a2 & 0x1fffff); - argbase = argwalk; - - args[0] = a0; // program name is argc[0] - - argofs = 0; - - if (a1 > 0) - { - args[numargs] = a2; - numargs++; - - while (a1) - { - if ((*argwalk == 0) && (a1 > 1)) - { - args[numargs] = a2 + argofs + 1; - numargs++; - } - argwalk++; - argofs++; - a1--; - } - } - - for (i = 0; i < numargs; i++) - { - #if DEBUG_HLE_IOP -// printf("Arg %d: %08x [%s]\n", i, args[i], &argbase[args[i]-a2]); - #endif - psx_ram[(newAlloc/4)+i] = LE32(args[i]); - } - - // set argv and argc - mipsinfo.i = numargs; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R4, &mipsinfo); - mipsinfo.i = 0x80000000 | newAlloc; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R5, &mipsinfo); - - // leave RA alone, PC = module start - // (NOTE: we get called in the delay slot!) - mipsinfo.i = start - 4; - mips_set_info(CPUINFO_INT_PC, &mipsinfo); - } - } - free(tempmem); - break; - - default: - printf("IOP: Unhandled service %d for module %s\n", callnum, name); - break; - } - - } - else if (!strcmp(name, "ioman")) - { - switch (callnum) - { - case 4: // open - { - int i, slot2use; - - slot2use = -1; - for (i = 0; i < MAX_FILE_SLOTS; i++) - { - if (filestat[i] == 0) - { - slot2use = i; - break; - } - } - - if (slot2use == -1) - { - printf("IOP: out of file slots!\n"); - mipsinfo.i = 0xffffffff; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - return; - } - - mname = (char *)psx_ram; - mname += (a0 & 0x1fffff); - - if (!strncmp(mname, "aofile:", 7)) - { - mname += 8; - } - else if (!strncmp(mname, "hefile:", 7)) - { - mname += 8; - } - else if (!strncmp(mname, "host0:", 6)) - { - mname += 7; - } - - mips_get_info(CPUINFO_INT_REGISTER + MIPS_R31, &mipsinfo); - #if DEBUG_HLE_IOP - printf("IOP: open(\"%s\") (PC=%08x)\n", mname, mipsinfo.i); - #endif - - filedata[slot2use] = malloc(6*1024*1024); - filesize[slot2use] = psf2_load_file(mname, filedata[slot2use], 6*1024*1024); - filepos[slot2use] = 0; - filestat[slot2use] = 1; - - if (filesize[slot2use] == 0xffffffff) - { - mipsinfo.i = filesize[slot2use]; - } - else - { - mipsinfo.i = slot2use; - } - } - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - break; - - case 5: // close - #if DEBUG_HLE_IOP - mips_get_info(CPUINFO_INT_REGISTER + MIPS_R31, &mipsinfo); - printf("IOP: close(%d) (PC=%08x)\n", a0, mipsinfo.i); - #endif - free(filedata[a0]); - filedata[a0] = (uint8 *)NULL; - filepos[a0] = 0; - filesize[a0] = 0; - filestat[a0] = 0; - break; - - case 6: // read - #if DEBUG_HLE_IOP - printf("IOP: read(%x %x %d) [pos %d size %d]\n", a0, a1, a2, filepos[a0], filesize[a0]); - #endif - - if (filepos[a0] >= filesize[a0]) - { - mipsinfo.i = 0; - } - else - { - uint8 *rp; - - if ((filepos[a0] + a2) > filesize[a0]) - { - a2 = filesize[a0] - filepos[a0]; - } - - rp = (uint8 *)psx_ram; - rp += (a1 & 0x1fffff); - memcpy(rp, &filedata[a0][filepos[a0]], a2); - - filepos[a0] += a2; - mipsinfo.i = a2; - } - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - break; - - case 8: // lseek - #if DEBUG_HLE_IOP - mips_get_info(CPUINFO_INT_REGISTER + MIPS_R31, &mipsinfo); - printf("IOP: lseek(%d, %d, %s) (PC=%08x)\n", a0, a1, seek_types[a2], mipsinfo.i); - #endif - - switch (a2) - { - case 0: // SEEK_SET - if (a1 <= filesize[a0]) - { - filepos[a0] = a1; - } - break; - case 1: // SEEK_CUR - if ((a1 + filepos[a0]) < filesize[a0]) - { - filepos[a0] += a1; - } - break; - case 2: // SEEK_END - filepos[a0] = filesize[a0] - a1; - break; - } - - mipsinfo.i = filepos[a0]; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - break; - - case 20: // AddDrv - #if DEBUG_HLE_IOP - printf("IOP: AddDrv(%x)\n", a0); - #endif - - mipsinfo.i = 0; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - break; - - case 21: // DelDrv - #if DEBUG_HLE_IOP - printf("IOP: DelDrv(%x)\n", a0); - #endif - - mipsinfo.i = 0; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_R2, &mipsinfo); - break; - - default: - printf("IOP: Unhandled service %d for module %s\n", callnum, name); - } - } - else - { - int lib; - - if (iNumLibs > 0) - { - for (lib = 0; lib < iNumLibs; lib++) - { - if (!strcmp(name, reglibs[lib].name)) - { - #if DEBUG_HLE_IOP - uint32 PC; - - mips_get_info(CPUINFO_INT_REGISTER + MIPS_R31, &mipsinfo); - PC = mipsinfo.i; - #endif - - // zap the delay slot handling - mipsinfo.i = 0; - mips_set_info(CPUINFO_INT_REGISTER + MIPS_DELAYV, &mipsinfo); - mips_set_info(CPUINFO_INT_REGISTER + MIPS_DELAYR, &mipsinfo); - - mipsinfo.i = LE32(psx_ram[(reglibs[lib].dispatch/4) + callnum]); - - // (NOTE: we get called in the delay slot!) - #if DEBUG_HLE_IOP - printf("IOP: Calling %s (%d) service %d => %08x (parms %08x %08x %08x %08x) (PC=%x)\n", - reglibs[lib].name, - lib, - callnum, - (uint32)mipsinfo.i, - a0, a1, a2, a3, PC); - #endif - - #if 0 - if (!strcmp(reglibs[lib].name, "ssd")) - { - if (callnum == 37) - { - psxcpu_verbose = 4096; - } - } - #endif - - mipsinfo.i -= 4; - mips_set_info(CPUINFO_INT_PC, &mipsinfo); - - return; - } - } - } - - printf("IOP: Unhandled service %d for module %s\n", callnum, name); - } -} - diff --git a/Frameworks/AudioOverload/aosdk/eng_qsf/eng_qsf.c b/Frameworks/AudioOverload/aosdk/eng_qsf/eng_qsf.c deleted file mode 100644 index 642ef95ab..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_qsf/eng_qsf.c +++ /dev/null @@ -1,446 +0,0 @@ -/* - Audio Overload SDK - QSF file engine - - Copyright (c) 2007, R. Belmont and Richard Bannister. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - * Neither the names of R. Belmont and Richard Bannister nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -// -// eng_qsf.c -// by R. Belmont -// - -/* -The program section of a QSF file, once decompressed, contains a series of -data blocks of the form: - -3 bytes - ASCII section name tag -4 bytes - Starting offset (LSB-first) -4 bytes - Length (N) (LSB-first) -N bytes - Data - -The data is then loaded to the given starting offset in the section described -by the ASCII tag. - -The following sections are defined: - -"KEY" - Kabuki decryption key. This section should be 11 bytes and contain - the following: - 4 bytes - swap_key1 (MSB-first) - 4 bytes - swap_key2 (MSB-first) - 2 bytes - addr_key (MSB-first) - 1 bytes - xor_key -"Z80" - Z80 program ROM. -"SMP" - QSound sample ROM. - -If the KEY section isn't given or both swap_keys are zero, then it is assumed -that no encryption is used. -*/ - -#include -#include -#include - -#include "ao.h" -#include "qsound.h" -#include "z80.h" - -#include "corlett.h" - -#define DEBUG_LOADER (0) - -// timer rate is 285 Hz -static int32 samples_per_tick = 44100/285; -static int32 samples_to_next_tick = 44100/285; - -static corlett_t *c = NULL; -static char qsfby[256]; -static uint32 skey1, skey2; -static uint16 akey; -static uint8 xkey; -static int32 uses_kabuki = 0; - -static char *Z80ROM, *QSamples; -static char RAM[0x1000], RAM2[0x1000]; -static int32 cur_bank; - -static struct QSound_interface qsintf = -{ - QSOUND_CLOCK, - NULL -}; - -extern void cps1_decode(unsigned char *rom, int swap_key1,int swap_key2,int addr_key,int xor_key); - -static void qsf_walktags(uint8 *buffer, uint8 *end) -{ - uint8 *cbuf = buffer; - uint32 offset, length; - - while (cbuf < end) - { - #if DEBUG_LOADER - printf("cbuf: %08x end: %08x\n", (uint32)cbuf, (uint32)end); - #endif - offset = cbuf[3] | cbuf[4]<<8 | cbuf[5]<<16 | cbuf[6]<<24; - length = cbuf[7] | cbuf[8]<<8 | cbuf[9]<<16 | cbuf[10]<<24; - - #if DEBUG_LOADER - printf("Tag: %c%c%c @ %08x, length %08x\n", cbuf[0], cbuf[1], cbuf[2], offset, length); - #endif - - switch (cbuf[0]) - { - case 'Z': - memcpy(&Z80ROM[offset], &cbuf[11], length); - break; - - case 'S': - memcpy(&QSamples[offset], &cbuf[11], length); - break; - - case 'K': - skey1 = cbuf[11]<<24 | cbuf[12]<<16 | cbuf[13]<<8 | cbuf[14]; - skey2 = cbuf[15]<<24 | cbuf[16]<<16 | cbuf[17]<<8 | cbuf[18]; - akey = cbuf[19]<<8 | cbuf[20]; - xkey = cbuf[20]; - break; - - default: - printf("ERROR: Unknown QSF tag!\n"); - break; - } - - cbuf += 11; - cbuf += length; - } -} - -static int32 qsf_irq_cb(int param) -{ - return 0x000000ff; // RST_38 -} - -int32 qsf_start(uint8 *buffer, uint32 length) -{ - uint8 *file, *lib_decoded, *lib_raw_file; - uint64 file_len, lib_len, lib_raw_length; - corlett_t *lib; - - z80_init(); - - Z80ROM = malloc(512*1024); - QSamples = malloc(8*1024*1024); - - skey1 = skey2 = 0; - akey = 0; - xkey = 0; - cur_bank = 0; - - memset(RAM, 0, 0x1000); - memset(RAM2, 0, 0x1000); - - // Decode the current QSF - if (corlett_decode(buffer, length, &file, &file_len, &c) != AO_SUCCESS) - { - return AO_FAIL; - } - - // Get the library file - if (c->lib[0] != 0) - { - uint64 tmp_length; - - #if DEBUG_LOADER - printf("Loading library: %s\n", c->lib); - #endif - if (ao_get_lib(c->lib, &lib_raw_file, &tmp_length) != AO_SUCCESS) - { - return AO_FAIL; - } - lib_raw_length = tmp_length; - - if (corlett_decode(lib_raw_file, lib_raw_length, &lib_decoded, &lib_len, &lib) != AO_SUCCESS) - { - free(lib_raw_file); - return AO_FAIL; - } - - // Free up raw file - free(lib_raw_file); - - // use the contents - qsf_walktags(lib_decoded, lib_decoded+lib_len); - - // Dispose the corlett structure for the lib - we don't use it - free(lib); - free(lib_decoded); - } - - // now patch the file into RAM OVER the libraries - qsf_walktags(file, file+file_len); - - free(file); - - if ((skey1 != 0) && (skey2 != 0)) - { - #if DEBUG_LOADER - printf("Decoding Kabuki: skey1 %08x skey2 %08x akey %04x xkey %02x\n", skey1, skey2, akey, xkey); - #endif - - uses_kabuki = 1; - cps1_decode((unsigned char *)Z80ROM, skey1, skey2, akey, xkey); - } - - // set qsfby tag - strcpy(qsfby, "n/a"); - if (c) - { - int i; - for (i = 0; i < MAX_UNKNOWN_TAGS; i++) - { - if (!strcasecmp(c->tag_name[i], "qsfby")) - { - strcpy(qsfby, c->tag_data[i]); - } - } - } - - z80_reset(NULL); - z80_set_irq_callback(qsf_irq_cb); - qsintf.sample_rom = QSamples; - qsound_sh_start(&qsintf); - - return AO_SUCCESS; -} - -static void timer_tick(void) -{ - z80_set_irq_line(0, ASSERT_LINE); - z80_set_irq_line(0, CLEAR_LINE); -} - -int32 qsf_gen(int16 *buffer, uint32 samples) -{ - int16 output[44100/30], output2[44100/30]; - int16 *stereo[2]; - int16 *outp = buffer; - int32 i, opos, tickinc, loops; - - // our largest possible step is samples_per_tick or samples, whichever is smaller - if (samples_to_next_tick > samples) - { - tickinc = samples; - } - else - { - tickinc = samples_to_next_tick; - } - - loops = samples / tickinc; - opos = 0; - - for (i = 0; i < loops; i++) - { - z80_execute((8000000/44100)*tickinc); - stereo[0] = &output[opos]; - stereo[1] = &output2[opos]; - qsound_update(0, stereo, tickinc); - - opos += tickinc; - samples_to_next_tick -= tickinc; - - if (samples_to_next_tick <= 0) - { - timer_tick(); - samples_to_next_tick = samples_per_tick; - } - } - - // are there "leftovers"? - if (opos < samples) - { - z80_execute((8000000/44100)*(samples-opos)); - stereo[0] = &output[opos]; - stereo[1] = &output2[opos]; - qsound_update(0, stereo, (samples-opos)); - - samples_to_next_tick -= (samples-opos); - - if (samples_to_next_tick <= 0) - { - timer_tick(); - samples_to_next_tick = samples_per_tick; - } - } - - for (i = 0; i < samples; i++) - { - *outp++ = output[i]; - *outp++ = output2[i]; - } - - return AO_SUCCESS; -} - -int32 qsf_stop(void) -{ - z80_exit(); - free(Z80ROM); - free(QSamples); - free(c); - - return AO_SUCCESS; -} - -int32 qsf_command(int32 command, int32 parameter) -{ - switch (command) - { - case COMMAND_RESTART: - return AO_SUCCESS; - - } - return AO_FAIL; -} - -int32 qsf_fill_info(ao_display_info *info) -{ - if (c == NULL) - return AO_FAIL; - - strcpy(info->title[1], "Name: "); - sprintf(info->info[1], "%s", c->inf_title); - - strcpy(info->title[2], "Game: "); - sprintf(info->info[2], "%s", c->inf_game); - - strcpy(info->title[3], "Artist: "); - sprintf(info->info[3], "%s", c->inf_artist); - - strcpy(info->title[4], "Copyright: "); - sprintf(info->info[4], "%s", c->inf_copy); - - strcpy(info->title[5], "Year: "); - sprintf(info->info[5], "%s", c->inf_year); - - strcpy(info->title[6], "Length: "); - sprintf(info->info[6], "%s", c->inf_length); - - strcpy(info->title[7], "Fade: "); - sprintf(info->info[7], "%s", c->inf_fade); - - strcpy(info->title[8], "Ripper: "); - sprintf(info->info[8], "%s", qsfby); - - return AO_SUCCESS; -} - -uint8 qsf_memory_read(uint16 addr) -{ - if (addr < 0x8000) - { - return Z80ROM[addr]; - } - else if (addr < 0xc000) - { - return Z80ROM[(addr - 0x8000) + cur_bank]; - } - else if (addr <= 0xcfff) - { - return RAM[addr - 0xc000]; - } - else if (addr == 0xd007) - { - return qsound_status_r(); - } - else if (addr >= 0xf000) - { - return RAM2[addr-0xf000]; - } -} - -uint8 qsf_memory_readop(uint16 addr) -{ - if (!uses_kabuki) - { - return qsf_memory_read(addr); - } - - if (addr < 0x8000) - { - return Z80ROM[addr + (256*1024)]; - } - - return qsf_memory_read(addr); -} - -uint8 qsf_memory_readport(uint16 addr) -{ - return Z80ROM[0x11]; -} - -void qsf_memory_write(uint16 addr, uint8 byte) -{ - if (addr >= 0xc000 && addr <= 0xcfff) - { - - RAM[addr-0xc000] = byte; - return; - } - else if (addr == 0xd000) - { - qsound_data_h_w(byte); - return; - } - else if (addr == 0xd001) - { - qsound_data_l_w(byte); - return; - } - else if (addr == 0xd002) - { - qsound_cmd_w(byte); - return; - } - else if (addr == 0xd003) - { - cur_bank = (0x8000 + (byte & 0xf) * 0x4000); - if (cur_bank > (256*1024)) - { - cur_bank = 0; - } -// printf("Z80 bank to %x (%x)\n", cur_bank, byte); - return; - } - else if (addr >= 0xf000) - { - RAM2[addr-0xf000] = byte; - return; - } -} - -void qsf_memory_writeport(uint16 addr, uint8 byte) -{ - printf("Unk port %x @ %x\n", byte, addr); -} - diff --git a/Frameworks/AudioOverload/aosdk/eng_qsf/kabuki.c b/Frameworks/AudioOverload/aosdk/eng_qsf/kabuki.c deleted file mode 100644 index 611003042..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_qsf/kabuki.c +++ /dev/null @@ -1,156 +0,0 @@ -/*************************************************************************** - -"Kabuki" Z80 encryption - - -The "Kabuki" is a custom Z80 module which runs encrypted code. The encryption -key is stored in some battery-backed RAM, therefore the chip has the annoying -habit of stopping working every few years, when the battery dies. -Check at the bottom of this text to see a list of all the known games which -use this chip. - - -How it works: -The base operation is a bit swap which affects couples of adjacent bits. -Each of the 4 couples may or may not be swapped, depending on the address of -the byte and on whether it is an opcode or data. -The decryption consists of these steps: -- bitswap -- ROL -- bitswap -- XOR with a key -- ROL -- bitswap -- ROL -- bitswap - -To know how to apply the bit swap, take the address of the byte to decode and: -- if the byte is an opcode, add addr_key to the address -- if the byte is data, XOR the address with 1FC0, add 1, and then add addr_key -You'll get a 16-bit word. The first two bitswaps depend on bits 0-7 of that -word, while the second two on bits 8-15. When a bit in the word is 1, swap the -two bits, oherwise don't. The exact couple of bits affected depends on the -game and is identified in this file with two keys: swap_key1 and swap_key2 -(which are just permutations of the numbers 0-7, not full 32-bit integers). - - -Key space size: -- swap_key1 8! = 40320 -- swap_key2 8! = 40320 -- addr_key 2^16 = 65536 -- xor_key 2^8 = 256 -- total 2.7274 * 10^16 - - -Weaknesses: -- 0x00 and 0xff, having all the bits set to the same value, are not affected - by bit permutations after the XOR. Therefore, their encryption is the same - regardless of the high 8 bits of the address, and of the value of - swap_key2. If there is a long stream of 0x00 or 0xff in the original data, - this can be used to find by brute force all the candidates for swap_key1, - xor_key, and for the low 8 bits of addr_key. This is a serious weakness - which dramatically reduces the security of the encryption. -- A 0x00 is always encrypted as a byte with as many 1s as xor_key; a 0xff is - always encrypted as a byte with as many 0s as xor_key has 1s. So you just - need to know one 0x00 or 0xff in the unencrypted data to know how many 1s - there are in xor_key. -- Once you have restricted the range for swap_key1 and you know the number of - 1s in the xor_key, you can easily use known plaintext attacks and brute - force to find the remaining keys. Long strings like THIS GAME IS FOR USE IN - and ABCDEFGHIJKLMNOPQRSTUVWXYZ can be found by comparing the number of 1s - in the clear and encrypted data, taking xor_key into account. When you have - found where the string is, use brute force to reduce the key space. - - -Known games: - swap_key1 swap_key2 addr_key xor_key -Mahjong Gakuen 2 Gakuen-chou no Fukushuu 76543210 01234567 aa55 a5 -Poker Ladies " " " " "" "" -Dokaben " " " " "" "" -Dokaben 2 unknown -Pang / Buster Bros / Pomping World 01234567 76543210 6548 24 -Capcom Baseball " " " " "" "" -Capcom World 04152637 40516273 5751 43 -Adventure Quiz 2 Hatena ? no Dai-Bouken 45670123 45670123 5751 43 -Super Pang 45670123 45670123 5852 43 -Super Buster Bros 45670123 45670123 2130 12 -Super Marukin-Ban 54321076 54321076 4854 4f -Quiz Tonosama no Yabou 12345670 12345670 1111 11 -Ashita Tenki ni Naare unknown -Quiz Sangokushi 23456701 23456701 1828 18 -Block Block 02461357 64207531 0002 01 - -Warriors of Fate 01234567 54163072 5151 51 -Cadillacs and Dinosaurs 76543210 24601357 4343 43 -Punisher 67452103 75316024 2222 22 -Slam Masters 54321076 65432107 3131 19 - -***************************************************************************/ - -#include "cpuintrf.h" - -static int bitswap1(int src,int key,int sel) -{ - if (sel & (1 << ((key >> 0) & 7))) - src = (src & 0xfc) | ((src & 0x01) << 1) | ((src & 0x02) >> 1); - if (sel & (1 << ((key >> 4) & 7))) - src = (src & 0xf3) | ((src & 0x04) << 1) | ((src & 0x08) >> 1); - if (sel & (1 << ((key >> 8) & 7))) - src = (src & 0xcf) | ((src & 0x10) << 1) | ((src & 0x20) >> 1); - if (sel & (1 << ((key >>12) & 7))) - src = (src & 0x3f) | ((src & 0x40) << 1) | ((src & 0x80) >> 1); - - return src; -} - -static int bitswap2(int src,int key,int sel) -{ - if (sel & (1 << ((key >>12) & 7))) - src = (src & 0xfc) | ((src & 0x01) << 1) | ((src & 0x02) >> 1); - if (sel & (1 << ((key >> 8) & 7))) - src = (src & 0xf3) | ((src & 0x04) << 1) | ((src & 0x08) >> 1); - if (sel & (1 << ((key >> 4) & 7))) - src = (src & 0xcf) | ((src & 0x10) << 1) | ((src & 0x20) >> 1); - if (sel & (1 << ((key >> 0) & 7))) - src = (src & 0x3f) | ((src & 0x40) << 1) | ((src & 0x80) >> 1); - - return src; -} - -static int bytedecode(int src,int swap_key1,int swap_key2,int xor_key,int sel) -{ - src = bitswap1(src,swap_key1 & 0xffff,sel & 0xff); - src = ((src & 0x7f) << 1) | ((src & 0x80) >> 7); - src = bitswap2(src,swap_key1 >> 16,sel & 0xff); - src ^= xor_key; - src = ((src & 0x7f) << 1) | ((src & 0x80) >> 7); - src = bitswap2(src,swap_key2 & 0xffff,sel >> 8); - src = ((src & 0x7f) << 1) | ((src & 0x80) >> 7); - src = bitswap1(src,swap_key2 >> 16,sel >> 8); - return src; -} - -static void kabuki_decode(unsigned char *src,unsigned char *dest_op,unsigned char *dest_data, - int base_addr,int length,int swap_key1,int swap_key2,int addr_key,int xor_key) -{ - int A; - int sel; - - for (A = 0; A < length; A++) - { - /* decode opcodes */ - sel = (A + base_addr) + addr_key; - dest_op[A] = bytedecode(src[A],swap_key1,swap_key2,xor_key,sel); - - /* decode data */ - sel = ((A + base_addr) ^ 0x1fc0) + addr_key + 1; - dest_data[A] = bytedecode(src[A],swap_key1,swap_key2,xor_key,sel); - } -} - -void cps1_decode(unsigned char *rom, int swap_key1,int swap_key2,int addr_key,int xor_key) -{ - int diff = (512*1024)/2; - - kabuki_decode(rom, rom+diff, rom, 0x0000, 0x8000, swap_key1, swap_key2, addr_key, xor_key); -} diff --git a/Frameworks/AudioOverload/aosdk/eng_qsf/qsound.c b/Frameworks/AudioOverload/aosdk/eng_qsf/qsound.c deleted file mode 100644 index 10b500b4b..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_qsf/qsound.c +++ /dev/null @@ -1,525 +0,0 @@ -/*************************************************************************** - - Capcom System QSound(tm) - ======================== - - Driver by Paul Leaman (paul@vortexcomputing.demon.co.uk) - and Miguel Angel Horna (mahorna@teleline.es) - - A 16 channel stereo sample player. - - QSpace position is simulated by panning the sound in the stereo space. - - Register - 0 xxbb xx = unknown bb = start high address - 1 ssss ssss = sample start address - 2 pitch - 3 unknown (always 0x8000) - 4 loop offset from end address - 5 end - 6 master channel volume - 7 not used - 8 Balance (left=0x0110 centre=0x0120 right=0x0130) - 9 unknown (most fixed samples use 0 for this register) - - Many thanks to CAB (the author of Amuse), without whom this probably would - never have been finished. - - If anybody has some information about this hardware, please send it to me - to mahorna@teleline.es or 432937@cepsz.unizar.es. - http://teleline.terra.es/personal/mahorna - -***************************************************************************/ - -#include -#include "cpuintrf.h" -#include "qsound.h" - -/* -Two Q sound drivers: -DRIVER1 Based on the Amuse source -DRIVER2 Miguel Angel Horna (mahorna@teleline.es) -*/ -#define QSOUND_DRIVER1 1 -/* -I don't know whether this system uses 8 bit or 16 bit samples. -If it uses 16 bit samples then the sample ROM loading macros need -to be modified to work with non-intel machines. -*/ -#define QSOUND_8BIT_SAMPLES 1 - -/* -Debug defines -*/ -#define LOG_WAVE 0 -#define LOG_QSOUND 0 - -/* Typedefs & defines */ - -#define QSOUND_DRIVER2 !QSOUND_DRIVER1 - -#if QSOUND_8BIT_SAMPLES -/* 8 bit source ROM samples */ -typedef signed char QSOUND_SRC_SAMPLE; -#define LENGTH_DIV 1 -#else -/* 8 bit source ROM samples */ -typedef signed short QSOUND_SRC_SAMPLE; -#define LENGTH_DIV 2 -#endif - -#define QSOUND_CLOCKDIV 166 /* Clock divider */ -#define QSOUND_CHANNELS 16 -typedef INT16 QSOUND_SAMPLE; - -struct QSOUND_CHANNEL -{ - int bank; /* bank (x16) */ - int address; /* start address */ - int pitch; /* pitch */ - int reg3; /* unknown (always 0x8000) */ - int loop; /* loop address */ - int end; /* end address */ - int vol; /* master volume */ - int pan; /* Pan value */ - int reg9; /* unknown */ - - /* Work variables */ - int key; /* Key on / key off */ - -#if QSOUND_DRIVER1 - int lvol; /* left volume */ - int rvol; /* right volume */ - int lastdt; /* last sample value */ - int offset; /* current offset counter */ -#else - QSOUND_SRC_SAMPLE *buffer; - int factor; /*step factor (fixed point 8-bit)*/ - int mixl,mixr; /*mixing factor (fixed point)*/ - int cursor; /*current sample position (fixed point)*/ - int lpos; /*last cursor pos*/ - int lastsaml; /*last left sample (to avoid any calculation)*/ - int lastsamr; /*last right sample*/ -#endif -}; - - -/* Private variables */ -static struct QSound_interface *intf; /* Interface */ -static int qsound_stream; /* Audio stream */ -static struct QSOUND_CHANNEL qsound_channel[QSOUND_CHANNELS]; -static int qsound_data; /* register latch data */ -QSOUND_SRC_SAMPLE *qsound_sample_rom; /* Q sound sample ROM */ - -#if QSOUND_DRIVER1 -static int qsound_pan_table[33]; /* Pan volume table */ -static float qsound_frq_ratio; /* Frequency ratio */ -#endif - -#if LOG_WAVE -static FILE *fpRawDataL; -static FILE *fpRawDataR; -#endif - -/* Function prototypes */ -void qsound_update( int num, INT16 **buffer, int length ); -void qsound_set_command(int data, int value); - -#if QSOUND_DRIVER2 -void setchannel(int channel,signed short *buffer,int length,int vol,int pan); -void setchloop(int channel,int loops,int loope); -void stopchan(int channel); -void calcula_mix(int channel); -#endif - -int qsound_sh_start( struct QSound_interface *qsintf ) -{ - int i; - - intf = qsintf; - - qsound_sample_rom = (QSOUND_SRC_SAMPLE *)intf->sample_rom; - - memset(qsound_channel, 0, sizeof(qsound_channel)); - -#if QSOUND_DRIVER1 - qsound_frq_ratio = ((float)intf->clock / (float)QSOUND_CLOCKDIV) / - (float) 44100; - qsound_frq_ratio *= 16.0; - - /* Create pan table */ - for (i=0; i<33; i++) - { - qsound_pan_table[i]=(int)((256/sqrt(32)) * sqrt(i)); - } -#else - i=0; -#endif - -#if LOG_QSOUND - logerror("Pan table\n"); - for (i=0; i<33; i++) - logerror("%02x ", qsound_pan_table[i]); -#endif -#if 0 - { - /* Allocate stream */ -#define CHANNELS ( 2 ) - char buf[CHANNELS][40]; - const char *name[CHANNELS]; - int vol[2]; - name[0] = buf[0]; - name[1] = buf[1]; - sprintf( buf[0], "%s L", sound_name(msound) ); - sprintf( buf[1], "%s R", sound_name(msound) ); - vol[0]=MIXER(intf->mixing_level[0], MIXER_PAN_LEFT); - vol[1]=MIXER(intf->mixing_level[1], MIXER_PAN_RIGHT); - qsound_stream = stream_init_multi( - CHANNELS, - name, - vol, - Machine->sample_rate, - 0, - qsound_update ); - } -#endif -#if LOG_WAVE - fpRawDataR=fopen("qsoundr.raw", "w+b"); - fpRawDataL=fopen("qsoundl.raw", "w+b"); - if (!fpRawDataR || !fpRawDataL) - { - return 1; - } -#endif - - return 0; -} - -void qsound_sh_stop (void) -{ -#if LOG_WAVE - if (fpRawDataR) - { - fclose(fpRawDataR); - } - if (fpRawDataL) - { - fclose(fpRawDataL); - } -#endif -} - -void qsound_data_h_w(int data) -{ - qsound_data=(qsound_data&0xff)|(data<<8); -} - -void qsound_data_l_w(int data) -{ - qsound_data=(qsound_data&0xff00)|data; -} - -void qsound_cmd_w(int data) -{ -// printf("QS: cmd %x, data %x\n", data, qsound_data); - qsound_set_command(data, qsound_data); -} - -int qsound_status_r(void) -{ - /* Port ready bit (0x80 if ready) */ - return 0x80; -} - -void qsound_set_command(int data, int value) -{ - int ch=0,reg=0; - if (data < 0x80) - { - ch=data>>3; - reg=data & 0x07; - } - else - { - if (data < 0x90) - { - ch=data-0x80; - reg=8; - } - else - { - if (data >= 0xba && data < 0xca) - { - ch=data-0xba; - reg=9; - } - else - { - /* Unknown registers */ - ch=99; - reg=99; - } - } - } - - switch (reg) - { - case 0: /* Bank */ - ch=(ch+1)&0x0f; /* strange ... */ - qsound_channel[ch].bank=(value&0x7f)<<16; - qsound_channel[ch].bank /= LENGTH_DIV; -#ifdef MAME_DEBUG - if (!value & 0x8000) - { - char baf[40]; - sprintf(baf,"Register3=%04x",value); - usrintf_showmessage(baf); - } -#endif - - break; - case 1: /* start */ -// printf("QS: key on ch %02d\n", ch); - qsound_channel[ch].address=value; - qsound_channel[ch].address/=LENGTH_DIV; - break; - case 2: /* pitch */ -#if QSOUND_DRIVER1 - qsound_channel[ch].pitch=(long) - ((float)value * qsound_frq_ratio ); - qsound_channel[ch].pitch/=LENGTH_DIV; -#else - qsound_channel[ch].factor=((float) (value*(6/LENGTH_DIV)) / - (float) Machine->sample_rate)*256.0; - -#endif - if (!value) - { - /* Key off */ -// printf("QS: key off ch %02d\n", ch); - qsound_channel[ch].key=0; - } - break; - case 3: /* unknown */ - qsound_channel[ch].reg3=value; -#ifdef MAME_DEBUG - if (value != 0x8000) - { - char baf[40]; - sprintf(baf,"Register3=%04x",value); - usrintf_showmessage(baf); - } -#endif - break; - case 4: /* loop offset */ - qsound_channel[ch].loop=value/LENGTH_DIV; - break; - case 5: /* end */ - qsound_channel[ch].end=value/LENGTH_DIV; - break; - case 6: /* master volume */ - if (value==0) - { - /* Key off */ - qsound_channel[ch].key=0; - } - else if (qsound_channel[ch].key==0) - { - /* Key on */ - qsound_channel[ch].key=1; -#if QSOUND_DRIVER1 - qsound_channel[ch].offset=0; - qsound_channel[ch].lastdt=0; -#else - qsound_channel[ch].cursor=qsound_channel[ch].address <<8 ; - qsound_channel[ch].buffer=qsound_sample_rom+ - qsound_channel[ch].bank; -#endif - } - qsound_channel[ch].vol=value; -#if QSOUND_DRIVER2 - calcula_mix(ch); -#endif - break; - - case 7: /* unused */ -#ifdef MAME_DEBUG - { - char baf[40]; - sprintf(baf,"UNUSED QSOUND REG 7=%04x",value); - usrintf_showmessage(baf); - } -#endif - - break; - case 8: - { -#if QSOUND_DRIVER1 - int pandata=(value-0x10)&0x3f; - if (pandata > 32) - { - pandata=32; - } - qsound_channel[ch].rvol=qsound_pan_table[pandata]; - qsound_channel[ch].lvol=qsound_pan_table[32-pandata]; -#endif - qsound_channel[ch].pan = value; -#if QSOUND_DRIVER2 - calcula_mix(ch); -#endif - } - break; - case 9: - qsound_channel[ch].reg9=value; -/* -#ifdef MAME_DEBUG - { - char baf[40]; - sprintf(baf,"QSOUND REG 9=%04x",value); - usrintf_showmessage(baf); - } -#endif -*/ - break; - } -#if LOG_QSOUND - logerror("QSOUND WRITE %02x CH%02d-R%02d =%04x\n", data, ch, reg, value); -#endif -} - -#if QSOUND_DRIVER1 - -/* Driver 1 - based on the Amuse source */ - -void qsound_update( int num, INT16 **buffer, int length ) -{ - int i,j; - int rvol, lvol, count; - struct QSOUND_CHANNEL *pC=&qsound_channel[0]; - QSOUND_SRC_SAMPLE * pST; - QSOUND_SAMPLE *datap[2]; - - datap[0] = buffer[0]; - datap[1] = buffer[1]; - memset( datap[0], 0x00, length * sizeof(QSOUND_SAMPLE) ); - memset( datap[1], 0x00, length * sizeof(QSOUND_SAMPLE) ); - - - for (i=0; ikey) - { - QSOUND_SAMPLE *pOutL=datap[0]; - QSOUND_SAMPLE *pOutR=datap[1]; - pST=qsound_sample_rom+pC->bank; - - rvol=(pC->rvol*pC->vol)>>(8*LENGTH_DIV); - lvol=(pC->lvol*pC->vol)>>(8*LENGTH_DIV); - - for (j=length-1; j>=0; j--) - { - count=(pC->offset)>>16; - pC->offset &= 0xffff; - if (count) - { - pC->address += count; - if (pC->address >= pC->end) - { - if (!pC->loop) - { - /* Reached the end of a non-looped sample */ - pC->key=0; - break; - } - /* Reached the end, restart the loop */ - pC->address = (pC->end - pC->loop) & 0xffff; - } - pC->lastdt = pST[pC->address]; - } - - (*pOutL) += ((pC->lastdt * lvol) >> 6); - (*pOutR) += ((pC->lastdt * rvol) >> 6); - pOutL++; - pOutR++; - pC->offset += pC->pitch; - } - } - pC++; - } - -#if LOG_WAVE - fwrite(datap[0], length*sizeof(QSOUND_SAMPLE), 1, fpRawDataL); - fwrite(datap[1], length*sizeof(QSOUND_SAMPLE), 1, fpRawDataR); -#endif -} - -#else - -/* ---------------------------------------------------------------- - QSound Sample Mixer (Slow) - Miguel Angel Horna mahorna@teleline.es - - ------------------------------------------------------------------ */ - - -void calcula_mix(int channel) -{ - int factl,factr; - struct QSOUND_CHANNEL *pC=&qsound_channel[channel]; - int vol=pC->vol>>5; - int pan=((pC->pan&0xFF)-0x10)<<3; - pC->mixl=vol; - pC->mixr=vol; - factr=pan; - factl=255-factr; - pC->mixl=(pC->mixl * factl)>>8; - pC->mixr=(pC->mixr * factr)>>8; -#if QSOUND_8BIT_SAMPLES - pC->mixl<<=8; - pC->mixr<<=8; -#endif -} - -void qsound_update(int num,void **buffer,int length) -{ - int i,j; - QSOUND_SAMPLE *bufL,*bufR, sample; - struct QSOUND_CHANNEL *pC=qsound_channel; - - memset( buffer[0], 0x00, length * sizeof(QSOUND_SAMPLE) ); - memset( buffer[1], 0x00, length * sizeof(QSOUND_SAMPLE) ); - - for(j=0;jkey) - { - for(i=0;icursor>>8; - if(pos!=pC->lpos) /*next sample*/ - { - sample=pC->buffer[pos]; - pC->lastsaml=(sample*pC->mixl)>>8; - pC->lastsamr=(sample*pC->mixr)>>8; - pC->lpos=pos; - } - (*bufL++)+=pC->lastsaml; - (*bufR++)+=pC->lastsamr; - pC->cursor+=pC->factor; - if(pC->loop && (pC->cursor>>8) > pC->end) - { - pC->cursor=(pC->end-pC->loop)<<8; - } - else if((pC->cursor>>8) > pC->end) - pC->key=0; - } - } - pC++; - } -} -#endif - - -/**************** end of file ****************/ diff --git a/Frameworks/AudioOverload/aosdk/eng_qsf/qsound.h b/Frameworks/AudioOverload/aosdk/eng_qsf/qsound.h deleted file mode 100644 index 0a9462cf3..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_qsf/qsound.h +++ /dev/null @@ -1,27 +0,0 @@ -/********************************************************* - - Capcom Q-Sound system - -*********************************************************/ - -#ifndef __QSOUND_H__ -#define __QSOUND_H__ - -#define QSOUND_CLOCK 4000000 /* default 4MHz clock */ - -struct QSound_interface -{ - int clock; /* clock */ - char *sample_rom; /* sample data */ -}; - -int qsound_sh_start( struct QSound_interface *qsintf ); -void qsound_sh_stop( void ); - -void qsound_data_h_w(int data); -void qsound_data_l_w(int data); -void qsound_cmd_w(int data); -int qsound_status_r(void); -void qsound_update( int num, INT16 **buffer, int length ); - -#endif /* __QSOUND_H__ */ diff --git a/Frameworks/AudioOverload/aosdk/eng_qsf/z80.c b/Frameworks/AudioOverload/aosdk/eng_qsf/z80.c deleted file mode 100644 index a323c4d64..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_qsf/z80.c +++ /dev/null @@ -1,4477 +0,0 @@ -/***************************************************************************** - * - * z80.c - * Portable Z80 emulator V3.5 - * - * Copyright (C) 1998,1999,2000 Juergen Buchmueller, all rights reserved. - * - * - This source code is released as freeware for non-commercial purposes. - * - You are free to use and redistribute this code in modified or - * unmodified form, provided you list me in the credits. - * - If you modify this source code, you must add a notice to each modified - * source file that it has been changed. If you're a nice person, you - * will clearly mark each change too. :) - * - If you wish to use this for commercial purposes, please contact me at - * pullmoll@t-online.de - * - The author of this copywritten work reserves the right to change the - * terms of its usage and license at any time, including retroactively - * - This entire notice must remain in the source code. - * - * Changes in 3.5 - * - Implemented OTIR, INIR, etc. without look-up table for PF flag. - * [Ramsoft, Sean Young] - * Changes in 3.4 - * - Removed Z80-MSX specific code as it's not needed any more. - * - Implemented DAA without look-up table [Ramsoft, Sean Young] - * Changes in 3.3 - * - Fixed undocumented flags XF & YF in the non-asm versions of CP, - * and all the 16 bit arithmetic instructions. [Sean Young] - * Changes in 3.2 - * - Fixed undocumented flags XF & YF of RRCA, and CF and HF of - * INI/IND/OUTI/OUTD/INIR/INDR/OTIR/OTDR [Sean Young] - * Changes in 3.1 - * - removed the REPEAT_AT_ONCE execution of LDIR/CPIR etc. opcodes - * for readabilities sake and because the implementation was buggy - * (and I was not able to find the difference) - * Changes in 3.0 - * - 'finished' switch to dynamically overrideable cycle count tables - * Changes in 2.9: - * - added methods to access and override the cycle count tables - * - fixed handling and timing of multiple DD/FD prefixed opcodes - * Changes in 2.8: - * - OUTI/OUTD/OTIR/OTDR also pre-decrement the B register now. - * This was wrong because of a bug fix on the wrong side - * (astrocade sound driver). - * Changes in 2.7: - * - removed z80_vm specific code, it's not needed (and never was). - * Changes in 2.6: - * - BUSY_LOOP_HACKS needed to call change_pc16() earlier, before - * checking the opcodes at the new address, because otherwise they - * might access the old (wrong or even NULL) banked memory region. - * Thanks to Sean Young for finding this nasty bug. - * Changes in 2.5: - * - Burning cycles always adjusts the ICount by a multiple of 4. - * - In REPEAT_AT_ONCE cases the R register wasn't incremented twice - * per repetition as it should have been. Those repeated opcodes - * could also underflow the ICount. - * - Simplified TIME_LOOP_HACKS for BC and added two more for DE + HL - * timing loops. I think those hacks weren't endian safe before too. - * Changes in 2.4: - * - z80_reset zaps the entire context, sets IX and IY to 0xffff(!) and - * sets the Z flag. With these changes the Tehkan World Cup driver - * _seems_ to work again. - * Changes in 2.3: - * - External termination of the execution loop calls z80_burn() and - * z80_vm_burn() to burn an amount of cycles (R adjustment) - * - Shortcuts which burn CPU cycles (BUSY_LOOP_HACKS and TIME_LOOP_HACKS) - * now also adjust the R register depending on the skipped opcodes. - * Changes in 2.2: - * - Fixed bugs in CPL, SCF and CCF instructions flag handling. - * - Changed variable EA and ARG16() function to UINT32; this - * produces slightly more efficient code. - * - The DD/FD XY CB opcodes where XY is 40-7F and Y is not 6/E - * are changed to calls to the X6/XE opcodes to reduce object size. - * They're hardly ever used so this should not yield a speed penalty. - * New in 2.0: - * - Optional more exact Z80 emulation (#define Z80_EXACT 1) according - * to a detailed description by Sean Young which can be found at: - * http://www.msxnet.org/tech/z80-documented.pdf - *****************************************************************************/ - -#include "ao.h" - -#include "cpuintrf.h" -#include "z80.h" - -#include "mem.h" - -#define INLINE static inline - -#undef VERBOSE -#define VERBOSE 0 - -#if VERBOSE -#define LOG(x) logerror x -#else -#define LOG(x) -#endif - -/* execute main opcodes inside a big switch statement */ -#ifndef BIG_SWITCH -#define BIG_SWITCH 1 -#endif - -/* big flags array for ADD/ADC/SUB/SBC/CP results */ -#define BIG_FLAGS_ARRAY 1 - -/* Set to 1 for a more exact (but somewhat slower) Z80 emulation */ -#define Z80_EXACT 1 - -/* on JP and JR opcodes check for tight loops */ -#define BUSY_LOOP_HACKS 1 - -/* check for delay loops counting down BC */ -#define TIME_LOOP_HACKS 1 - -#ifdef X86_ASM -#undef BIG_FLAGS_ARRAY -#define BIG_FLAGS_ARRAY 0 -#endif - -static UINT8 z80_reg_layout[] = { - Z80_PC, Z80_SP, Z80_AF, Z80_BC, Z80_DE, Z80_HL, -1, - Z80_IX, Z80_IY, Z80_AF2,Z80_BC2,Z80_DE2,Z80_HL2,-1, - Z80_R, Z80_I, Z80_IM, Z80_IFF1,Z80_IFF2, -1, - Z80_NMI_STATE,Z80_IRQ_STATE,Z80_DC0,Z80_DC1,Z80_DC2,Z80_DC3, 0 -}; - -static UINT8 z80_win_layout[] = { - 27, 0,53, 4, /* register window (top rows) */ - 0, 0,26,22, /* disassembler window (left colums) */ - 27, 5,53, 8, /* memory #1 window (right, upper middle) */ - 27,14,53, 8, /* memory #2 window (right, lower middle) */ - 0,23,80, 1, /* command line window (bottom rows) */ -}; - -/****************************************************************************/ -/* The Z80 registers. HALT is set to 1 when the CPU is halted, the refresh */ -/* register is calculated as follows: refresh=(Regs.R&127)|(Regs.R2&128) */ -/****************************************************************************/ -typedef struct { -/* 00 */ PAIR PREPC,PC,SP,AF,BC,DE,HL,IX,IY; -/* 24 */ PAIR AF2,BC2,DE2,HL2; -/* 34 */ UINT8 R,R2,IFF1,IFF2,HALT,IM,I; -/* 3B */ UINT8 irq_max; /* number of daisy chain devices */ -/* 3C */ INT8 request_irq; /* daisy chain next request device */ -/* 3D */ INT8 service_irq; /* daisy chain next reti handling device */ -/* 3E */ UINT8 nmi_state; /* nmi line state */ -/* 3F */ UINT8 irq_state; /* irq line state */ -/* 40 */ UINT8 int_state[Z80_MAXDAISY]; -/* 44 */ Z80_DaisyChain irq[Z80_MAXDAISY]; -/* 84 */ int (*irq_callback)(int irqline); -/* 88 */ int extra_cycles; /* extra cycles for interrupts */ -} Z80_Regs; - -#define CF 0x01 -#define NF 0x02 -#define PF 0x04 -#define VF PF -#define XF 0x08 -#define HF 0x10 -#define YF 0x20 -#define ZF 0x40 -#define SF 0x80 - -#define INT_IRQ 0x01 -#define NMI_IRQ 0x02 - -#define _PPC Z80.PREPC.d /* previous program counter */ - -#define _PCD Z80.PC.d -#define _PC Z80.PC.w.l - -#define _SPD Z80.SP.d -#define _SP Z80.SP.w.l - -#define _AFD Z80.AF.d -#define _AF Z80.AF.w.l -#define _Z80_A Z80.AF.b.h -#define _F Z80.AF.b.l - -#define _BCD Z80.BC.d -#define _BC Z80.BC.w.l -#define _Z80_B Z80.BC.b.h -#define _Z80_C Z80.BC.b.l - -#define _DED Z80.DE.d -#define _DE Z80.DE.w.l -#define _Z80_D Z80.DE.b.h -#define _Z80_E Z80.DE.b.l - -#define _HLD Z80.HL.d -#define _HL Z80.HL.w.l -#define _Z80_H Z80.HL.b.h -#define _Z80_L Z80.HL.b.l - -#define _IXD Z80.IX.d -#define _IX Z80.IX.w.l -#define _HX Z80.IX.b.h -#define _LX Z80.IX.b.l - -#define _IYD Z80.IY.d -#define _IY Z80.IY.w.l -#define _HY Z80.IY.b.h -#define _LY Z80.IY.b.l - -#define _Z80_I Z80.I -#define _Z80_R Z80.R -#define _R2 Z80.R2 -#define _IM Z80.IM -#define _IFF1 Z80.IFF1 -#define _IFF2 Z80.IFF2 -#define _HALT Z80.HALT - -int z80_ICount; -static Z80_Regs Z80; -static UINT32 EA; -static int after_EI = 0; - -static UINT8 SZ[256]; /* zero and sign flags */ -static UINT8 SZ_BIT[256]; /* zero, sign and parity/overflow (=zero) flags for BIT opcode */ -static UINT8 SZP[256]; /* zero, sign and parity flags */ -static UINT8 SZHV_inc[256]; /* zero, sign, half carry and overflow flags INC r8 */ -static UINT8 SZHV_dec[256]; /* zero, sign, half carry and overflow flags DEC r8 */ - -#if BIG_FLAGS_ARRAY -static UINT8 *SZHVC_add = 0; -static UINT8 *SZHVC_sub = 0; -#endif - -static const UINT8 cc_op[0x100] = { - 4,10, 7, 6, 4, 4, 7, 4, 4,11, 7, 6, 4, 4, 7, 4, - 8,10, 7, 6, 4, 4, 7, 4,12,11, 7, 6, 4, 4, 7, 4, - 7,10,16, 6, 4, 4, 7, 4, 7,11,16, 6, 4, 4, 7, 4, - 7,10,13, 6,11,11,10, 4, 7,11,13, 6, 4, 4, 7, 4, - 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4, - 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4, - 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4, - 7, 7, 7, 7, 7, 7, 4, 7, 4, 4, 4, 4, 4, 4, 7, 4, - 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4, - 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4, - 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4, - 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4, - 5,10,10,10,10,11, 7,11, 5,10,10, 0,10,17, 7,11, - 5,10,10,11,10,11, 7,11, 5, 4,10,11,10, 0, 7,11, - 5,10,10,19,10,11, 7,11, 5, 4,10, 4,10, 0, 7,11, - 5,10,10, 4,10,11, 7,11, 5, 6,10, 4,10, 0, 7,11}; - -static const UINT8 cc_cb[0x100] = { - 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8, - 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8, - 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8, - 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8, - 8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8, - 8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8, - 8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8, - 8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8, - 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8, - 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8, - 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8, - 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8, - 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8, - 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8, - 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8, - 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8}; - -static const UINT8 cc_ed[0x100] = { - 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, - 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, - 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, - 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, -12,12,15,20, 8, 8, 8, 9,12,12,15,20, 8, 8, 8, 9, -12,12,15,20, 8, 8, 8, 9,12,12,15,20, 8, 8, 8, 9, -12,12,15,20, 8, 8, 8,18,12,12,15,20, 8, 8, 8,18, -12,12,15,20, 8, 8, 8, 8,12,12,15,20, 8, 8, 8, 8, - 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, - 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, -16,16,16,16, 8, 8, 8, 8,16,16,16,16, 8, 8, 8, 8, -16,16,16,16, 8, 8, 8, 8,16,16,16,16, 8, 8, 8, 8, - 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, - 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, - 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, - 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8}; - -static const UINT8 cc_xy[0x100] = { - 4, 4, 4, 4, 4, 4, 4, 4, 4,15, 4, 4, 4, 4, 4, 4, - 4, 4, 4, 4, 4, 4, 4, 4, 4,15, 4, 4, 4, 4, 4, 4, - 4,14,20,10, 9, 9, 9, 4, 4,15,20,10, 9, 9, 9, 4, - 4, 4, 4, 4,23,23,19, 4, 4,15, 4, 4, 4, 4, 4, 4, - 4, 4, 4, 4, 9, 9,19, 4, 4, 4, 4, 4, 9, 9,19, 4, - 4, 4, 4, 4, 9, 9,19, 4, 4, 4, 4, 4, 9, 9,19, 4, - 9, 9, 9, 9, 9, 9,19, 9, 9, 9, 9, 9, 9, 9,19, 9, -19,19,19,19,19,19, 4,19, 4, 4, 4, 4, 9, 9,19, 4, - 4, 4, 4, 4, 9, 9,19, 4, 4, 4, 4, 4, 9, 9,19, 4, - 4, 4, 4, 4, 9, 9,19, 4, 4, 4, 4, 4, 9, 9,19, 4, - 4, 4, 4, 4, 9, 9,19, 4, 4, 4, 4, 4, 9, 9,19, 4, - 4, 4, 4, 4, 9, 9,19, 4, 4, 4, 4, 4, 9, 9,19, 4, - 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 4, 4, 4, 4, - 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, - 4,14, 4,23, 4,15, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4, - 4, 4, 4, 4, 4, 4, 4, 4, 4,10, 4, 4, 4, 4, 4, 4}; - -static const UINT8 cc_xycb[0x100] = { -23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23, -23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23, -23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23, -23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23, -20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20, -20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20, -20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20, -20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20, -23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23, -23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23, -23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23, -23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23, -23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23, -23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23, -23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23, -23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23}; - -/* extra cycles if jr/jp/call taken and 'interrupt latency' on rst 0-7 */ -static const UINT8 cc_ex[0x100] = { - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* DJNZ */ - 5, 0, 0, 0, 0, 0, 0, 0, 5, 0, 0, 0, 0, 0, 0, 0, /* JR NZ/JR Z */ - 5, 0, 0, 0, 0, 0, 0, 0, 5, 0, 0, 0, 0, 0, 0, 0, /* JR NC/JR C */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 5, 5, 5, 5, 0, 0, 0, 0, 5, 5, 5, 5, 0, 0, 0, 0, /* LDIR/CPIR/INIR/OTIR LDDR/CPDR/INDR/OTDR */ - 6, 0, 0, 0, 7, 0, 0, 2, 6, 0, 0, 0, 7, 0, 0, 2, - 6, 0, 0, 0, 7, 0, 0, 2, 6, 0, 0, 0, 7, 0, 0, 2, - 6, 0, 0, 0, 7, 0, 0, 2, 6, 0, 0, 0, 7, 0, 0, 2, - 6, 0, 0, 0, 7, 0, 0, 2, 6, 0, 0, 0, 7, 0, 0, 2}; - -static const UINT8 *cc[6] = { cc_op, cc_cb, cc_ed, cc_xy, cc_xycb, cc_ex }; -#define Z80_TABLE_dd Z80_TABLE_xy -#define Z80_TABLE_fd Z80_TABLE_xy - -static void take_interrupt(void); - -typedef void (*funcptr)(void); - -#define PROTOTYPES(tablename,prefix) \ - INLINE void prefix##_00(void); INLINE void prefix##_01(void); INLINE void prefix##_02(void); INLINE void prefix##_03(void); \ - INLINE void prefix##_04(void); INLINE void prefix##_05(void); INLINE void prefix##_06(void); INLINE void prefix##_07(void); \ - INLINE void prefix##_08(void); INLINE void prefix##_09(void); INLINE void prefix##_0a(void); INLINE void prefix##_0b(void); \ - INLINE void prefix##_0c(void); INLINE void prefix##_0d(void); INLINE void prefix##_0e(void); INLINE void prefix##_0f(void); \ - INLINE void prefix##_10(void); INLINE void prefix##_11(void); INLINE void prefix##_12(void); INLINE void prefix##_13(void); \ - INLINE void prefix##_14(void); INLINE void prefix##_15(void); INLINE void prefix##_16(void); INLINE void prefix##_17(void); \ - INLINE void prefix##_18(void); INLINE void prefix##_19(void); INLINE void prefix##_1a(void); INLINE void prefix##_1b(void); \ - INLINE void prefix##_1c(void); INLINE void prefix##_1d(void); INLINE void prefix##_1e(void); INLINE void prefix##_1f(void); \ - INLINE void prefix##_20(void); INLINE void prefix##_21(void); INLINE void prefix##_22(void); INLINE void prefix##_23(void); \ - INLINE void prefix##_24(void); INLINE void prefix##_25(void); INLINE void prefix##_26(void); INLINE void prefix##_27(void); \ - INLINE void prefix##_28(void); INLINE void prefix##_29(void); INLINE void prefix##_2a(void); INLINE void prefix##_2b(void); \ - INLINE void prefix##_2c(void); INLINE void prefix##_2d(void); INLINE void prefix##_2e(void); INLINE void prefix##_2f(void); \ - INLINE void prefix##_30(void); INLINE void prefix##_31(void); INLINE void prefix##_32(void); INLINE void prefix##_33(void); \ - INLINE void prefix##_34(void); INLINE void prefix##_35(void); INLINE void prefix##_36(void); INLINE void prefix##_37(void); \ - INLINE void prefix##_38(void); INLINE void prefix##_39(void); INLINE void prefix##_3a(void); INLINE void prefix##_3b(void); \ - INLINE void prefix##_3c(void); INLINE void prefix##_3d(void); INLINE void prefix##_3e(void); INLINE void prefix##_3f(void); \ - INLINE void prefix##_40(void); INLINE void prefix##_41(void); INLINE void prefix##_42(void); INLINE void prefix##_43(void); \ - INLINE void prefix##_44(void); INLINE void prefix##_45(void); INLINE void prefix##_46(void); INLINE void prefix##_47(void); \ - INLINE void prefix##_48(void); INLINE void prefix##_49(void); INLINE void prefix##_4a(void); INLINE void prefix##_4b(void); \ - INLINE void prefix##_4c(void); INLINE void prefix##_4d(void); INLINE void prefix##_4e(void); INLINE void prefix##_4f(void); \ - INLINE void prefix##_50(void); INLINE void prefix##_51(void); INLINE void prefix##_52(void); INLINE void prefix##_53(void); \ - INLINE void prefix##_54(void); INLINE void prefix##_55(void); INLINE void prefix##_56(void); INLINE void prefix##_57(void); \ - INLINE void prefix##_58(void); INLINE void prefix##_59(void); INLINE void prefix##_5a(void); INLINE void prefix##_5b(void); \ - INLINE void prefix##_5c(void); INLINE void prefix##_5d(void); INLINE void prefix##_5e(void); INLINE void prefix##_5f(void); \ - INLINE void prefix##_60(void); INLINE void prefix##_61(void); INLINE void prefix##_62(void); INLINE void prefix##_63(void); \ - INLINE void prefix##_64(void); INLINE void prefix##_65(void); INLINE void prefix##_66(void); INLINE void prefix##_67(void); \ - INLINE void prefix##_68(void); INLINE void prefix##_69(void); INLINE void prefix##_6a(void); INLINE void prefix##_6b(void); \ - INLINE void prefix##_6c(void); INLINE void prefix##_6d(void); INLINE void prefix##_6e(void); INLINE void prefix##_6f(void); \ - INLINE void prefix##_70(void); INLINE void prefix##_71(void); INLINE void prefix##_72(void); INLINE void prefix##_73(void); \ - INLINE void prefix##_74(void); INLINE void prefix##_75(void); INLINE void prefix##_76(void); INLINE void prefix##_77(void); \ - INLINE void prefix##_78(void); INLINE void prefix##_79(void); INLINE void prefix##_7a(void); INLINE void prefix##_7b(void); \ - INLINE void prefix##_7c(void); INLINE void prefix##_7d(void); INLINE void prefix##_7e(void); INLINE void prefix##_7f(void); \ - INLINE void prefix##_80(void); INLINE void prefix##_81(void); INLINE void prefix##_82(void); INLINE void prefix##_83(void); \ - INLINE void prefix##_84(void); INLINE void prefix##_85(void); INLINE void prefix##_86(void); INLINE void prefix##_87(void); \ - INLINE void prefix##_88(void); INLINE void prefix##_89(void); INLINE void prefix##_8a(void); INLINE void prefix##_8b(void); \ - INLINE void prefix##_8c(void); INLINE void prefix##_8d(void); INLINE void prefix##_8e(void); INLINE void prefix##_8f(void); \ - INLINE void prefix##_90(void); INLINE void prefix##_91(void); INLINE void prefix##_92(void); INLINE void prefix##_93(void); \ - INLINE void prefix##_94(void); INLINE void prefix##_95(void); INLINE void prefix##_96(void); INLINE void prefix##_97(void); \ - INLINE void prefix##_98(void); INLINE void prefix##_99(void); INLINE void prefix##_9a(void); INLINE void prefix##_9b(void); \ - INLINE void prefix##_9c(void); INLINE void prefix##_9d(void); INLINE void prefix##_9e(void); INLINE void prefix##_9f(void); \ - INLINE void prefix##_a0(void); INLINE void prefix##_a1(void); INLINE void prefix##_a2(void); INLINE void prefix##_a3(void); \ - INLINE void prefix##_a4(void); INLINE void prefix##_a5(void); INLINE void prefix##_a6(void); INLINE void prefix##_a7(void); \ - INLINE void prefix##_a8(void); INLINE void prefix##_a9(void); INLINE void prefix##_aa(void); INLINE void prefix##_ab(void); \ - INLINE void prefix##_ac(void); INLINE void prefix##_ad(void); INLINE void prefix##_ae(void); INLINE void prefix##_af(void); \ - INLINE void prefix##_b0(void); INLINE void prefix##_b1(void); INLINE void prefix##_b2(void); INLINE void prefix##_b3(void); \ - INLINE void prefix##_b4(void); INLINE void prefix##_b5(void); INLINE void prefix##_b6(void); INLINE void prefix##_b7(void); \ - INLINE void prefix##_b8(void); INLINE void prefix##_b9(void); INLINE void prefix##_ba(void); INLINE void prefix##_bb(void); \ - INLINE void prefix##_bc(void); INLINE void prefix##_bd(void); INLINE void prefix##_be(void); INLINE void prefix##_bf(void); \ - INLINE void prefix##_c0(void); INLINE void prefix##_c1(void); INLINE void prefix##_c2(void); INLINE void prefix##_c3(void); \ - INLINE void prefix##_c4(void); INLINE void prefix##_c5(void); INLINE void prefix##_c6(void); INLINE void prefix##_c7(void); \ - INLINE void prefix##_c8(void); INLINE void prefix##_c9(void); INLINE void prefix##_ca(void); INLINE void prefix##_cb(void); \ - INLINE void prefix##_cc(void); INLINE void prefix##_cd(void); INLINE void prefix##_ce(void); INLINE void prefix##_cf(void); \ - INLINE void prefix##_d0(void); INLINE void prefix##_d1(void); INLINE void prefix##_d2(void); INLINE void prefix##_d3(void); \ - INLINE void prefix##_d4(void); INLINE void prefix##_d5(void); INLINE void prefix##_d6(void); INLINE void prefix##_d7(void); \ - INLINE void prefix##_d8(void); INLINE void prefix##_d9(void); INLINE void prefix##_da(void); INLINE void prefix##_db(void); \ - INLINE void prefix##_dc(void); INLINE void prefix##_dd(void); INLINE void prefix##_de(void); INLINE void prefix##_df(void); \ - INLINE void prefix##_e0(void); INLINE void prefix##_e1(void); INLINE void prefix##_e2(void); INLINE void prefix##_e3(void); \ - INLINE void prefix##_e4(void); INLINE void prefix##_e5(void); INLINE void prefix##_e6(void); INLINE void prefix##_e7(void); \ - INLINE void prefix##_e8(void); INLINE void prefix##_e9(void); INLINE void prefix##_ea(void); INLINE void prefix##_eb(void); \ - INLINE void prefix##_ec(void); INLINE void prefix##_ed(void); INLINE void prefix##_ee(void); INLINE void prefix##_ef(void); \ - INLINE void prefix##_f0(void); INLINE void prefix##_f1(void); INLINE void prefix##_f2(void); INLINE void prefix##_f3(void); \ - INLINE void prefix##_f4(void); INLINE void prefix##_f5(void); INLINE void prefix##_f6(void); INLINE void prefix##_f7(void); \ - INLINE void prefix##_f8(void); INLINE void prefix##_f9(void); INLINE void prefix##_fa(void); INLINE void prefix##_fb(void); \ - INLINE void prefix##_fc(void); INLINE void prefix##_fd(void); INLINE void prefix##_fe(void); INLINE void prefix##_ff(void); \ -static const funcptr tablename[0x100] = { \ - prefix##_00,prefix##_01,prefix##_02,prefix##_03,prefix##_04,prefix##_05,prefix##_06,prefix##_07, \ - prefix##_08,prefix##_09,prefix##_0a,prefix##_0b,prefix##_0c,prefix##_0d,prefix##_0e,prefix##_0f, \ - prefix##_10,prefix##_11,prefix##_12,prefix##_13,prefix##_14,prefix##_15,prefix##_16,prefix##_17, \ - prefix##_18,prefix##_19,prefix##_1a,prefix##_1b,prefix##_1c,prefix##_1d,prefix##_1e,prefix##_1f, \ - prefix##_20,prefix##_21,prefix##_22,prefix##_23,prefix##_24,prefix##_25,prefix##_26,prefix##_27, \ - prefix##_28,prefix##_29,prefix##_2a,prefix##_2b,prefix##_2c,prefix##_2d,prefix##_2e,prefix##_2f, \ - prefix##_30,prefix##_31,prefix##_32,prefix##_33,prefix##_34,prefix##_35,prefix##_36,prefix##_37, \ - prefix##_38,prefix##_39,prefix##_3a,prefix##_3b,prefix##_3c,prefix##_3d,prefix##_3e,prefix##_3f, \ - prefix##_40,prefix##_41,prefix##_42,prefix##_43,prefix##_44,prefix##_45,prefix##_46,prefix##_47, \ - prefix##_48,prefix##_49,prefix##_4a,prefix##_4b,prefix##_4c,prefix##_4d,prefix##_4e,prefix##_4f, \ - prefix##_50,prefix##_51,prefix##_52,prefix##_53,prefix##_54,prefix##_55,prefix##_56,prefix##_57, \ - prefix##_58,prefix##_59,prefix##_5a,prefix##_5b,prefix##_5c,prefix##_5d,prefix##_5e,prefix##_5f, \ - prefix##_60,prefix##_61,prefix##_62,prefix##_63,prefix##_64,prefix##_65,prefix##_66,prefix##_67, \ - prefix##_68,prefix##_69,prefix##_6a,prefix##_6b,prefix##_6c,prefix##_6d,prefix##_6e,prefix##_6f, \ - prefix##_70,prefix##_71,prefix##_72,prefix##_73,prefix##_74,prefix##_75,prefix##_76,prefix##_77, \ - prefix##_78,prefix##_79,prefix##_7a,prefix##_7b,prefix##_7c,prefix##_7d,prefix##_7e,prefix##_7f, \ - prefix##_80,prefix##_81,prefix##_82,prefix##_83,prefix##_84,prefix##_85,prefix##_86,prefix##_87, \ - prefix##_88,prefix##_89,prefix##_8a,prefix##_8b,prefix##_8c,prefix##_8d,prefix##_8e,prefix##_8f, \ - prefix##_90,prefix##_91,prefix##_92,prefix##_93,prefix##_94,prefix##_95,prefix##_96,prefix##_97, \ - prefix##_98,prefix##_99,prefix##_9a,prefix##_9b,prefix##_9c,prefix##_9d,prefix##_9e,prefix##_9f, \ - prefix##_a0,prefix##_a1,prefix##_a2,prefix##_a3,prefix##_a4,prefix##_a5,prefix##_a6,prefix##_a7, \ - prefix##_a8,prefix##_a9,prefix##_aa,prefix##_ab,prefix##_ac,prefix##_ad,prefix##_ae,prefix##_af, \ - prefix##_b0,prefix##_b1,prefix##_b2,prefix##_b3,prefix##_b4,prefix##_b5,prefix##_b6,prefix##_b7, \ - prefix##_b8,prefix##_b9,prefix##_ba,prefix##_bb,prefix##_bc,prefix##_bd,prefix##_be,prefix##_bf, \ - prefix##_c0,prefix##_c1,prefix##_c2,prefix##_c3,prefix##_c4,prefix##_c5,prefix##_c6,prefix##_c7, \ - prefix##_c8,prefix##_c9,prefix##_ca,prefix##_cb,prefix##_cc,prefix##_cd,prefix##_ce,prefix##_cf, \ - prefix##_d0,prefix##_d1,prefix##_d2,prefix##_d3,prefix##_d4,prefix##_d5,prefix##_d6,prefix##_d7, \ - prefix##_d8,prefix##_d9,prefix##_da,prefix##_db,prefix##_dc,prefix##_dd,prefix##_de,prefix##_df, \ - prefix##_e0,prefix##_e1,prefix##_e2,prefix##_e3,prefix##_e4,prefix##_e5,prefix##_e6,prefix##_e7, \ - prefix##_e8,prefix##_e9,prefix##_ea,prefix##_eb,prefix##_ec,prefix##_ed,prefix##_ee,prefix##_ef, \ - prefix##_f0,prefix##_f1,prefix##_f2,prefix##_f3,prefix##_f4,prefix##_f5,prefix##_f6,prefix##_f7, \ - prefix##_f8,prefix##_f9,prefix##_fa,prefix##_fb,prefix##_fc,prefix##_fd,prefix##_fe,prefix##_ff \ -} - -PROTOTYPES(Z80op,op); -PROTOTYPES(Z80cb,cb); -PROTOTYPES(Z80dd,dd); -PROTOTYPES(Z80ed,ed); -PROTOTYPES(Z80fd,fd); -PROTOTYPES(Z80xycb,xycb); - -/****************************************************************************/ -/* Burn an odd amount of cycles, that is instructions taking something */ -/* different from 4 T-states per opcode (and R increment) */ -/****************************************************************************/ -INLINE void BURNODD(int cycles, int opcodes, int cyclesum) -{ - if( cycles > 0 ) - { - _Z80_R += (cycles / cyclesum) * opcodes; - z80_ICount -= (cycles / cyclesum) * cyclesum; - } -} - -/*************************************************************** - * define an opcode function - ***************************************************************/ -#define OP(prefix,opcode) INLINE void prefix##_##opcode(void) - -/*************************************************************** - * adjust cycle count by n T-states - ***************************************************************/ -#define CC(prefix,opcode) z80_ICount -= cc[Z80_TABLE_##prefix][opcode] - -/*************************************************************** - * execute an opcode - ***************************************************************/ -#define EXEC(prefix,opcode) \ -{ \ - unsigned op = opcode; \ - CC(prefix,op); \ - (*Z80##prefix[op])(); \ -} - -#if BIG_SWITCH -#define EXEC_INLINE(prefix,opcode) \ -{ \ - unsigned op = opcode; \ - CC(prefix,op); \ - switch(op) \ - { \ - case 0x00:prefix##_##00();break; case 0x01:prefix##_##01();break; case 0x02:prefix##_##02();break; case 0x03:prefix##_##03();break; \ - case 0x04:prefix##_##04();break; case 0x05:prefix##_##05();break; case 0x06:prefix##_##06();break; case 0x07:prefix##_##07();break; \ - case 0x08:prefix##_##08();break; case 0x09:prefix##_##09();break; case 0x0a:prefix##_##0a();break; case 0x0b:prefix##_##0b();break; \ - case 0x0c:prefix##_##0c();break; case 0x0d:prefix##_##0d();break; case 0x0e:prefix##_##0e();break; case 0x0f:prefix##_##0f();break; \ - case 0x10:prefix##_##10();break; case 0x11:prefix##_##11();break; case 0x12:prefix##_##12();break; case 0x13:prefix##_##13();break; \ - case 0x14:prefix##_##14();break; case 0x15:prefix##_##15();break; case 0x16:prefix##_##16();break; case 0x17:prefix##_##17();break; \ - case 0x18:prefix##_##18();break; case 0x19:prefix##_##19();break; case 0x1a:prefix##_##1a();break; case 0x1b:prefix##_##1b();break; \ - case 0x1c:prefix##_##1c();break; case 0x1d:prefix##_##1d();break; case 0x1e:prefix##_##1e();break; case 0x1f:prefix##_##1f();break; \ - case 0x20:prefix##_##20();break; case 0x21:prefix##_##21();break; case 0x22:prefix##_##22();break; case 0x23:prefix##_##23();break; \ - case 0x24:prefix##_##24();break; case 0x25:prefix##_##25();break; case 0x26:prefix##_##26();break; case 0x27:prefix##_##27();break; \ - case 0x28:prefix##_##28();break; case 0x29:prefix##_##29();break; case 0x2a:prefix##_##2a();break; case 0x2b:prefix##_##2b();break; \ - case 0x2c:prefix##_##2c();break; case 0x2d:prefix##_##2d();break; case 0x2e:prefix##_##2e();break; case 0x2f:prefix##_##2f();break; \ - case 0x30:prefix##_##30();break; case 0x31:prefix##_##31();break; case 0x32:prefix##_##32();break; case 0x33:prefix##_##33();break; \ - case 0x34:prefix##_##34();break; case 0x35:prefix##_##35();break; case 0x36:prefix##_##36();break; case 0x37:prefix##_##37();break; \ - case 0x38:prefix##_##38();break; case 0x39:prefix##_##39();break; case 0x3a:prefix##_##3a();break; case 0x3b:prefix##_##3b();break; \ - case 0x3c:prefix##_##3c();break; case 0x3d:prefix##_##3d();break; case 0x3e:prefix##_##3e();break; case 0x3f:prefix##_##3f();break; \ - case 0x40:prefix##_##40();break; case 0x41:prefix##_##41();break; case 0x42:prefix##_##42();break; case 0x43:prefix##_##43();break; \ - case 0x44:prefix##_##44();break; case 0x45:prefix##_##45();break; case 0x46:prefix##_##46();break; case 0x47:prefix##_##47();break; \ - case 0x48:prefix##_##48();break; case 0x49:prefix##_##49();break; case 0x4a:prefix##_##4a();break; case 0x4b:prefix##_##4b();break; \ - case 0x4c:prefix##_##4c();break; case 0x4d:prefix##_##4d();break; case 0x4e:prefix##_##4e();break; case 0x4f:prefix##_##4f();break; \ - case 0x50:prefix##_##50();break; case 0x51:prefix##_##51();break; case 0x52:prefix##_##52();break; case 0x53:prefix##_##53();break; \ - case 0x54:prefix##_##54();break; case 0x55:prefix##_##55();break; case 0x56:prefix##_##56();break; case 0x57:prefix##_##57();break; \ - case 0x58:prefix##_##58();break; case 0x59:prefix##_##59();break; case 0x5a:prefix##_##5a();break; case 0x5b:prefix##_##5b();break; \ - case 0x5c:prefix##_##5c();break; case 0x5d:prefix##_##5d();break; case 0x5e:prefix##_##5e();break; case 0x5f:prefix##_##5f();break; \ - case 0x60:prefix##_##60();break; case 0x61:prefix##_##61();break; case 0x62:prefix##_##62();break; case 0x63:prefix##_##63();break; \ - case 0x64:prefix##_##64();break; case 0x65:prefix##_##65();break; case 0x66:prefix##_##66();break; case 0x67:prefix##_##67();break; \ - case 0x68:prefix##_##68();break; case 0x69:prefix##_##69();break; case 0x6a:prefix##_##6a();break; case 0x6b:prefix##_##6b();break; \ - case 0x6c:prefix##_##6c();break; case 0x6d:prefix##_##6d();break; case 0x6e:prefix##_##6e();break; case 0x6f:prefix##_##6f();break; \ - case 0x70:prefix##_##70();break; case 0x71:prefix##_##71();break; case 0x72:prefix##_##72();break; case 0x73:prefix##_##73();break; \ - case 0x74:prefix##_##74();break; case 0x75:prefix##_##75();break; case 0x76:prefix##_##76();break; case 0x77:prefix##_##77();break; \ - case 0x78:prefix##_##78();break; case 0x79:prefix##_##79();break; case 0x7a:prefix##_##7a();break; case 0x7b:prefix##_##7b();break; \ - case 0x7c:prefix##_##7c();break; case 0x7d:prefix##_##7d();break; case 0x7e:prefix##_##7e();break; case 0x7f:prefix##_##7f();break; \ - case 0x80:prefix##_##80();break; case 0x81:prefix##_##81();break; case 0x82:prefix##_##82();break; case 0x83:prefix##_##83();break; \ - case 0x84:prefix##_##84();break; case 0x85:prefix##_##85();break; case 0x86:prefix##_##86();break; case 0x87:prefix##_##87();break; \ - case 0x88:prefix##_##88();break; case 0x89:prefix##_##89();break; case 0x8a:prefix##_##8a();break; case 0x8b:prefix##_##8b();break; \ - case 0x8c:prefix##_##8c();break; case 0x8d:prefix##_##8d();break; case 0x8e:prefix##_##8e();break; case 0x8f:prefix##_##8f();break; \ - case 0x90:prefix##_##90();break; case 0x91:prefix##_##91();break; case 0x92:prefix##_##92();break; case 0x93:prefix##_##93();break; \ - case 0x94:prefix##_##94();break; case 0x95:prefix##_##95();break; case 0x96:prefix##_##96();break; case 0x97:prefix##_##97();break; \ - case 0x98:prefix##_##98();break; case 0x99:prefix##_##99();break; case 0x9a:prefix##_##9a();break; case 0x9b:prefix##_##9b();break; \ - case 0x9c:prefix##_##9c();break; case 0x9d:prefix##_##9d();break; case 0x9e:prefix##_##9e();break; case 0x9f:prefix##_##9f();break; \ - case 0xa0:prefix##_##a0();break; case 0xa1:prefix##_##a1();break; case 0xa2:prefix##_##a2();break; case 0xa3:prefix##_##a3();break; \ - case 0xa4:prefix##_##a4();break; case 0xa5:prefix##_##a5();break; case 0xa6:prefix##_##a6();break; case 0xa7:prefix##_##a7();break; \ - case 0xa8:prefix##_##a8();break; case 0xa9:prefix##_##a9();break; case 0xaa:prefix##_##aa();break; case 0xab:prefix##_##ab();break; \ - case 0xac:prefix##_##ac();break; case 0xad:prefix##_##ad();break; case 0xae:prefix##_##ae();break; case 0xaf:prefix##_##af();break; \ - case 0xb0:prefix##_##b0();break; case 0xb1:prefix##_##b1();break; case 0xb2:prefix##_##b2();break; case 0xb3:prefix##_##b3();break; \ - case 0xb4:prefix##_##b4();break; case 0xb5:prefix##_##b5();break; case 0xb6:prefix##_##b6();break; case 0xb7:prefix##_##b7();break; \ - case 0xb8:prefix##_##b8();break; case 0xb9:prefix##_##b9();break; case 0xba:prefix##_##ba();break; case 0xbb:prefix##_##bb();break; \ - case 0xbc:prefix##_##bc();break; case 0xbd:prefix##_##bd();break; case 0xbe:prefix##_##be();break; case 0xbf:prefix##_##bf();break; \ - case 0xc0:prefix##_##c0();break; case 0xc1:prefix##_##c1();break; case 0xc2:prefix##_##c2();break; case 0xc3:prefix##_##c3();break; \ - case 0xc4:prefix##_##c4();break; case 0xc5:prefix##_##c5();break; case 0xc6:prefix##_##c6();break; case 0xc7:prefix##_##c7();break; \ - case 0xc8:prefix##_##c8();break; case 0xc9:prefix##_##c9();break; case 0xca:prefix##_##ca();break; case 0xcb:prefix##_##cb();break; \ - case 0xcc:prefix##_##cc();break; case 0xcd:prefix##_##cd();break; case 0xce:prefix##_##ce();break; case 0xcf:prefix##_##cf();break; \ - case 0xd0:prefix##_##d0();break; case 0xd1:prefix##_##d1();break; case 0xd2:prefix##_##d2();break; case 0xd3:prefix##_##d3();break; \ - case 0xd4:prefix##_##d4();break; case 0xd5:prefix##_##d5();break; case 0xd6:prefix##_##d6();break; case 0xd7:prefix##_##d7();break; \ - case 0xd8:prefix##_##d8();break; case 0xd9:prefix##_##d9();break; case 0xda:prefix##_##da();break; case 0xdb:prefix##_##db();break; \ - case 0xdc:prefix##_##dc();break; case 0xdd:prefix##_##dd();break; case 0xde:prefix##_##de();break; case 0xdf:prefix##_##df();break; \ - case 0xe0:prefix##_##e0();break; case 0xe1:prefix##_##e1();break; case 0xe2:prefix##_##e2();break; case 0xe3:prefix##_##e3();break; \ - case 0xe4:prefix##_##e4();break; case 0xe5:prefix##_##e5();break; case 0xe6:prefix##_##e6();break; case 0xe7:prefix##_##e7();break; \ - case 0xe8:prefix##_##e8();break; case 0xe9:prefix##_##e9();break; case 0xea:prefix##_##ea();break; case 0xeb:prefix##_##eb();break; \ - case 0xec:prefix##_##ec();break; case 0xed:prefix##_##ed();break; case 0xee:prefix##_##ee();break; case 0xef:prefix##_##ef();break; \ - case 0xf0:prefix##_##f0();break; case 0xf1:prefix##_##f1();break; case 0xf2:prefix##_##f2();break; case 0xf3:prefix##_##f3();break; \ - case 0xf4:prefix##_##f4();break; case 0xf5:prefix##_##f5();break; case 0xf6:prefix##_##f6();break; case 0xf7:prefix##_##f7();break; \ - case 0xf8:prefix##_##f8();break; case 0xf9:prefix##_##f9();break; case 0xfa:prefix##_##fa();break; case 0xfb:prefix##_##fb();break; \ - case 0xfc:prefix##_##fc();break; case 0xfd:prefix##_##fd();break; case 0xfe:prefix##_##fe();break; case 0xff:prefix##_##ff();break; \ - } \ -} -#else -#define EXEC_INLINE EXEC -#endif - - -/*************************************************************** - * Enter HALT state; write 1 to fake port on first execution - ***************************************************************/ -#define ENTER_HALT { \ - _PC--; \ - _HALT = 1; \ - if( !after_EI ) \ - z80_burn( z80_ICount ); \ -} - -/*************************************************************** - * Leave HALT state; write 0 to fake port - ***************************************************************/ -#define LEAVE_HALT { \ - if( _HALT ) \ - { \ - _HALT = 0; \ - _PC++; \ - } \ -} - -/*************************************************************** - * Input a byte from given I/O port - ***************************************************************/ -#define IN(port) ((UINT8)cpu_readport16(port)) - -/*************************************************************** - * Output a byte to given I/O port - ***************************************************************/ -#define OUT(port,value) cpu_writeport16(port,value) - -/*************************************************************** - * Read a byte from given memory location - ***************************************************************/ -#define RM(addr) (UINT8)cpu_readmem16(addr) - -/*************************************************************** - * Read a word from given memory location - ***************************************************************/ -INLINE void RM16( UINT32 addr, PAIR *r ) -{ - r->b.l = RM(addr); - r->b.h = RM((addr+1)&0xffff); -} - -/*************************************************************** - * Write a byte to given memory location - ***************************************************************/ -#define WM(addr,value) cpu_writemem16(addr,value) - -/*************************************************************** - * Write a word to given memory location - ***************************************************************/ -INLINE void WM16( UINT32 addr, PAIR *r ) -{ - WM(addr,r->b.l); - WM((addr+1)&0xffff,r->b.h); -} - -/*************************************************************** - * ROP() is identical to RM() except it is used for - * reading opcodes. In case of system with memory mapped I/O, - * this function can be used to greatly speed up emulation - ***************************************************************/ -INLINE UINT8 ROP(void) -{ - unsigned pc = _PCD; - _PC++; - return cpu_readop(pc); -} - -/**************************************************************** - * ARG() is identical to ROP() except it is used - * for reading opcode arguments. This difference can be used to - * support systems that use different encoding mechanisms for - * opcodes and opcode arguments - ***************************************************************/ -INLINE UINT8 ARG(void) -{ - unsigned pc = _PCD; - _PC++; - return cpu_readop_arg(pc); -} - -INLINE UINT32 ARG16(void) -{ - unsigned pc = _PCD; - _PC += 2; - return cpu_readop_arg(pc) | (cpu_readop_arg((pc+1)&0xffff) << 8); -} - -/*************************************************************** - * Calculate the effective address EA of an opcode using - * IX+offset resp. IY+offset addressing. - ***************************************************************/ -#define EAX EA = (UINT32)(UINT16)(_IX+(INT8)ARG()) -#define EAY EA = (UINT32)(UINT16)(_IY+(INT8)ARG()) - -/*************************************************************** - * POP - ***************************************************************/ -#define POP(DR) { RM16( _SPD, &Z80.DR ); _SP += 2; } - -/*************************************************************** - * PUSH - ***************************************************************/ -#define PUSH(SR) { _SP -= 2; WM16( _SPD, &Z80.SR ); } - -/*************************************************************** - * JP - ***************************************************************/ -#if BUSY_LOOP_HACKS -#define JP { \ - unsigned oldpc = _PCD-1; \ - _PCD = ARG16(); \ - change_pc16(_PCD); \ - /* speed up busy loop */ \ - if( _PCD == oldpc ) \ - { \ - if( !after_EI ) \ - BURNODD( z80_ICount, 1, cc[Z80_TABLE_op][0xc3] ); \ - } \ - else \ - { \ - UINT8 op = cpu_readop(_PCD); \ - if( _PCD == oldpc-1 ) \ - { \ - /* NOP - JP $-1 or EI - JP $-1 */ \ - if ( op == 0x00 || op == 0xfb ) \ - { \ - if( !after_EI ) \ - BURNODD( z80_ICount-cc[Z80_TABLE_op][0x00], \ - 2, cc[Z80_TABLE_op][0x00]+cc[Z80_TABLE_op][0xc3]); \ - } \ - } \ - else \ - /* LD SP,#xxxx - JP $-3 (Galaga) */ \ - if( _PCD == oldpc-3 && op == 0x31 ) \ - { \ - if( !after_EI ) \ - BURNODD( z80_ICount-cc[Z80_TABLE_op][0x31], \ - 2, cc[Z80_TABLE_op][0x31]+cc[Z80_TABLE_op][0xc3]); \ - } \ - } \ -} -#else -#define JP { \ - _PCD = ARG16(); \ - change_pc16(_PCD); \ -} -#endif - -/*************************************************************** - * JP_COND - ***************************************************************/ - -#define JP_COND(cond) \ - if( cond ) \ - { \ - _PCD = ARG16(); \ - change_pc16(_PCD); \ - } \ - else \ - { \ - _PC += 2; \ - } - -/*************************************************************** - * JR - ***************************************************************/ -#define JR() \ -{ \ - unsigned oldpc = _PCD-1; \ - INT8 arg = (INT8)ARG(); /* ARG() also increments _PC */ \ - _PC += arg; /* so don't do _PC += ARG() */ \ - change_pc16(_PCD); \ - /* speed up busy loop */ \ - if( _PCD == oldpc ) \ - { \ - if( !after_EI ) \ - BURNODD( z80_ICount, 1, cc[Z80_TABLE_op][0x18] ); \ - } \ - else \ - { \ - UINT8 op = cpu_readop(_PCD); \ - if( _PCD == oldpc-1 ) \ - { \ - /* NOP - JR $-1 or EI - JR $-1 */ \ - if ( op == 0x00 || op == 0xfb ) \ - { \ - if( !after_EI ) \ - BURNODD( z80_ICount-cc[Z80_TABLE_op][0x00], \ - 2, cc[Z80_TABLE_op][0x00]+cc[Z80_TABLE_op][0x18]); \ - } \ - } \ - else \ - /* LD SP,#xxxx - JR $-3 */ \ - if( _PCD == oldpc-3 && op == 0x31 ) \ - { \ - if( !after_EI ) \ - BURNODD( z80_ICount-cc[Z80_TABLE_op][0x31], \ - 2, cc[Z80_TABLE_op][0x31]+cc[Z80_TABLE_op][0x18]); \ - } \ - } \ -} - -/*************************************************************** - * JR_COND - ***************************************************************/ -#define JR_COND(cond,opcode) \ - if( cond ) \ - { \ - INT8 arg = (INT8)ARG(); /* ARG() also increments _PC */ \ - _PC += arg; /* so don't do _PC += ARG() */ \ - CC(ex,opcode); \ - change_pc16(_PCD); \ - } \ - else _PC++; \ - -/*************************************************************** - * CALL - ***************************************************************/ -#define CALL() \ - EA = ARG16(); \ - PUSH( PC ); \ - _PCD = EA; \ - change_pc16(_PCD) - -/*************************************************************** - * CALL_COND - ***************************************************************/ -#define CALL_COND(cond,opcode) \ - if( cond ) \ - { \ - EA = ARG16(); \ - PUSH( PC ); \ - _PCD = EA; \ - CC(ex,opcode); \ - change_pc16(_PCD); \ - } \ - else \ - { \ - _PC+=2; \ - } - -/*************************************************************** - * RET_COND - ***************************************************************/ -#define RET_COND(cond,opcode) \ - if( cond ) \ - { \ - POP(PC); \ - change_pc16(_PCD); \ - CC(ex,opcode); \ - } - -/*************************************************************** - * RETN - ***************************************************************/ -#define RETN { \ - POP(PC); \ - change_pc16(_PCD); \ - if( _IFF1 == 0 && _IFF2 == 1 ) \ - { \ - _IFF1 = 1; \ - if( Z80.irq_state != CLEAR_LINE || \ - Z80.request_irq >= 0 ) \ - { \ - take_interrupt(); \ - } \ - } \ - else _IFF1 = _IFF2; \ -} - -/*************************************************************** - * RETI - ***************************************************************/ -#define RETI { \ - int device = Z80.service_irq; \ - POP(PC); \ - change_pc16(_PCD); \ -/* according to http://www.msxnet.org/tech/z80-documented.pdf */\ -/* _IFF1 = _IFF2; */ \ - if( device >= 0 ) \ - { \ - Z80.irq[device].interrupt_reti(Z80.irq[device].irq_param); \ - } \ -} - -/*************************************************************** - * LD R,A - ***************************************************************/ -#define LD_R_A { \ - _Z80_R = _Z80_A; \ - _R2 = _Z80_A & 0x80; /* keep bit 7 of R */ \ -} - -/*************************************************************** - * LD A,R - ***************************************************************/ -#define LD_A_R { \ - _Z80_A = (_Z80_R & 0x7f) | _R2; \ - _F = (_F & CF) | SZ[_Z80_A] | ( _IFF2 << 2 ); \ -} - -/*************************************************************** - * LD I,A - ***************************************************************/ -#define LD_I_A { \ - _Z80_I = _Z80_A; \ -} - -/*************************************************************** - * LD A,I - ***************************************************************/ -#define LD_A_I { \ - _Z80_A = _Z80_I; \ - _F = (_F & CF) | SZ[_Z80_A] | ( _IFF2 << 2 ); \ -} - -/*************************************************************** - * RST - ***************************************************************/ -#define RST(addr) \ - PUSH( PC ); \ - _PCD = addr; \ - change_pc16(_PCD) - -/*************************************************************** - * INC r8 - ***************************************************************/ -INLINE UINT8 INC(UINT8 value) -{ - UINT8 res = value + 1; - _F = (_F & CF) | SZHV_inc[res]; - return (UINT8)res; -} - -/*************************************************************** - * DEC r8 - ***************************************************************/ -INLINE UINT8 DEC(UINT8 value) -{ - UINT8 res = value - 1; - _F = (_F & CF) | SZHV_dec[res]; - return res; -} - -/*************************************************************** - * RLCA - ***************************************************************/ -#if Z80_EXACT -#define RLCA \ - _Z80_A = (_Z80_A << 1) | (_Z80_A >> 7); \ - _F = (_F & (SF | ZF | PF)) | (_Z80_A & (YF | XF | CF)) -#else -#define RLCA \ - _Z80_A = (_Z80_A << 1) | (_Z80_A >> 7); \ - _F = (_F & (SF | ZF | YF | XF | PF)) | (_Z80_A & CF) -#endif - -/*************************************************************** - * RRCA - ***************************************************************/ -#if Z80_EXACT -#define RRCA \ - _F = (_F & (SF | ZF | PF)) | (_Z80_A & CF); \ - _Z80_A = (_Z80_A >> 1) | (_Z80_A << 7); \ - _F |= (_Z80_A & (YF | XF) ) -#else -#define RRCA \ - _F = (_F & (SF | ZF | YF | XF | PF)) | (_Z80_A & CF); \ - _Z80_A = (_Z80_A >> 1) | (_Z80_A << 7) -#endif - -/*************************************************************** - * RLA - ***************************************************************/ -#if Z80_EXACT -#define RLA { \ - UINT8 res = (_Z80_A << 1) | (_F & CF); \ - UINT8 c = (_Z80_A & 0x80) ? CF : 0; \ - _F = (_F & (SF | ZF | PF)) | c | (res & (YF | XF)); \ - _Z80_A = res; \ -} -#else -#define RLA { \ - UINT8 res = (_Z80_A << 1) | (_F & CF); \ - UINT8 c = (_Z80_A & 0x80) ? CF : 0; \ - _F = (_F & (SF | ZF | YF | XF | PF)) | c; \ - _Z80_A = res; \ -} -#endif - -/*************************************************************** - * RRA - ***************************************************************/ -#if Z80_EXACT -#define RRA { \ - UINT8 res = (_Z80_A >> 1) | (_F << 7); \ - UINT8 c = (_Z80_A & 0x01) ? CF : 0; \ - _F = (_F & (SF | ZF | PF)) | c | (res & (YF | XF)); \ - _Z80_A = res; \ -} -#else -#define RRA { \ - UINT8 res = (_Z80_A >> 1) | (_F << 7); \ - UINT8 c = (_Z80_A & 0x01) ? CF : 0; \ - _F = (_F & (SF | ZF | YF | XF | PF)) | c; \ - _Z80_A = res; \ -} -#endif - -/*************************************************************** - * RRD - ***************************************************************/ -#define RRD { \ - UINT8 n = RM(_HL); \ - WM( _HL, (n >> 4) | (_Z80_A << 4) ); \ - _Z80_A = (_Z80_A & 0xf0) | (n & 0x0f); \ - _F = (_F & CF) | SZP[_Z80_A]; \ -} - -/*************************************************************** - * RLD - ***************************************************************/ -#define RLD { \ - UINT8 n = RM(_HL); \ - WM( _HL, (n << 4) | (_Z80_A & 0x0f) ); \ - _Z80_A = (_Z80_A & 0xf0) | (n >> 4); \ - _F = (_F & CF) | SZP[_Z80_A]; \ -} - -/*************************************************************** - * ADD A,n - ***************************************************************/ -#ifdef X86_ASM -#if Z80_EXACT -#define ADD(value) \ - asm ( \ - " addb %2,%0 \n" \ - " lahf \n" \ - " setob %1 \n" /* al = 1 if overflow */ \ - " addb %1,%1 \n" \ - " addb %1,%1 \n" /* shift to P/V bit position */ \ - " andb $0xd1,%%ah \n" /* sign, zero, half carry, carry */ \ - " orb %%ah,%1 \n" \ - " movb %0,%%ah \n" /* get result */ \ - " andb $0x28,%%ah \n" /* maks flags 5+3 */ \ - " orb %%ah,%1 \n" /* put them into flags */ \ - :"=q" (_Z80_A), "=q" (_F) \ - :"q" (value), "1" (_F), "0" (_Z80_A) \ - ) -#else -#define ADD(value) \ - asm ( \ - " addb %2,%0 \n" \ - " lahf \n" \ - " setob %1 \n" /* al = 1 if overflow */ \ - " addb %1,%1 \n" \ - " addb %1,%1 \n" /* shift to P/V bit position */ \ - " andb $0xd1,%%ah \n" /* sign, zero, half carry, carry */ \ - " orb %%ah,%1 \n" \ - :"=q" (_Z80_A), "=q" (_F) \ - :"q" (value), "1" (_F), "0" (_Z80_A) \ - ) -#endif -#else -#if BIG_FLAGS_ARRAY -#define ADD(value) \ -{ \ - UINT32 ah = _AFD & 0xff00; \ - UINT32 res = (UINT8)((ah >> 8) + value); \ - _F = SZHVC_add[ah | res]; \ - _Z80_A = res; \ -} -#else -#define ADD(value) \ -{ \ - unsigned val = value; \ - unsigned res = _Z80_A + val; \ - _F = SZ[(UINT8)res] | ((res >> 8) & CF) | \ - ((_Z80_A ^ res ^ val) & HF) | \ - (((val ^ _Z80_A ^ 0x80) & (val ^ res) & 0x80) >> 5); \ - _Z80_A = (UINT8)res; \ -} -#endif -#endif - -/*************************************************************** - * ADC A,n - ***************************************************************/ -#ifdef X86_ASM -#if Z80_EXACT -#define ADC(value) \ - asm ( \ - " shrb $1,%1 \n" \ - " adcb %2,%0 \n" \ - " lahf \n" \ - " setob %1 \n" /* al = 1 if overflow */ \ - " addb %1,%1 \n" /* shift to P/V bit position */ \ - " addb %1,%1 \n" \ - " andb $0xd1,%%ah \n" /* sign, zero, half carry, carry */ \ - " orb %%ah,%1 \n" /* combine with P/V */ \ - " movb %0,%%ah \n" /* get result */ \ - " andb $0x28,%%ah \n" /* maks flags 5+3 */ \ - " orb %%ah,%1 \n" /* put them into flags */ \ - :"=q" (_Z80_A), "=q" (_F) \ - :"q" (value), "1" (_F), "0" (_Z80_A) \ - ) -#else -#define ADC(value) \ - asm ( \ - " shrb $1,%1 \n" \ - " adcb %2,%0 \n" \ - " lahf \n" \ - " setob %1 \n" /* al = 1 if overflow */ \ - " addb %1,%1 \n" /* shift to P/V bit position */ \ - " addb %1,%1 \n" \ - " andb $0xd1,%%ah \n" /* sign, zero, half carry, carry */ \ - " orb %%ah,%1 \n" /* combine with P/V */ \ - :"=q" (_Z80_A), "=q" (_F) \ - :"q" (value), "1" (_F), "0" (_Z80_A) \ - ) -#endif -#else -#if BIG_FLAGS_ARRAY -#define ADC(value) \ -{ \ - UINT32 ah = _AFD & 0xff00, c = _AFD & 1; \ - UINT32 res = (UINT8)((ah >> 8) + value + c); \ - _F = SZHVC_add[(c << 16) | ah | res]; \ - _Z80_A = res; \ -} -#else -#define ADC(value) \ -{ \ - unsigned val = value; \ - unsigned res = _Z80_A + val + (_F & CF); \ - _F = SZ[res & 0xff] | ((res >> 8) & CF) | \ - ((_Z80_A ^ res ^ val) & HF) | \ - (((val ^ _Z80_A ^ 0x80) & (val ^ res) & 0x80) >> 5); \ - _Z80_A = res; \ -} -#endif -#endif - -/*************************************************************** - * SUB n - ***************************************************************/ -#ifdef X86_ASM -#if Z80_EXACT -#define SUB(value) \ - asm ( \ - " subb %2,%0 \n" \ - " lahf \n" \ - " setob %1 \n" /* al = 1 if overflow */ \ - " stc \n" /* prepare to set N flag */ \ - " adcb %1,%1 \n" /* shift to P/V bit position */ \ - " addb %1,%1 \n" \ - " andb $0xd1,%%ah \n" /* sign, zero, half carry, carry */ \ - " orb %%ah,%1 \n" /* combine with P/V */ \ - " movb %0,%%ah \n" /* get result */ \ - " andb $0x28,%%ah \n" /* maks flags 5+3 */ \ - " orb %%ah,%1 \n" /* put them into flags */ \ - :"=q" (_Z80_A), "=q" (_F) \ - :"q" (value), "1" (_F), "0" (_Z80_A) \ - ) -#else -#define SUB(value) \ - asm ( \ - " subb %2,%0 \n" \ - " lahf \n" \ - " setob %1 \n" /* al = 1 if overflow */ \ - " stc \n" /* prepare to set N flag */ \ - " adcb %1,%1 \n" /* shift to P/V bit position */ \ - " addb %1,%1 \n" \ - " andb $0xd1,%%ah \n" /* sign, zero, half carry, carry */ \ - " orb %%ah,%1 \n" /* combine with P/V */ \ - :"=q" (_Z80_A), "=q" (_F) \ - :"q" (value), "1" (_F), "0" (_Z80_A) \ - ) -#endif -#else -#if BIG_FLAGS_ARRAY -#define SUB(value) \ -{ \ - UINT32 ah = _AFD & 0xff00; \ - UINT32 res = (UINT8)((ah >> 8) - value); \ - _F = SZHVC_sub[ah | res]; \ - _Z80_A = res; \ -} -#else -#define SUB(value) \ -{ \ - unsigned val = value; \ - unsigned res = _Z80_A - val; \ - _F = SZ[res & 0xff] | ((res >> 8) & CF) | NF | \ - ((_Z80_A ^ res ^ val) & HF) | \ - (((val ^ _Z80_A) & (_Z80_A ^ res) & 0x80) >> 5); \ - _Z80_A = res; \ -} -#endif -#endif - -/*************************************************************** - * SBC A,n - ***************************************************************/ -#ifdef X86_ASM -#if Z80_EXACT -#define SBC(value) \ - asm ( \ - " shrb $1,%1 \n" \ - " sbbb %2,%0 \n" \ - " lahf \n" \ - " setob %1 \n" /* al = 1 if overflow */ \ - " stc \n" /* prepare to set N flag */ \ - " adcb %1,%1 \n" /* shift to P/V bit position */ \ - " addb %1,%1 \n" \ - " andb $0xd1,%%ah \n" /* sign, zero, half carry, carry */ \ - " orb %%ah,%1 \n" /* combine with P/V */ \ - " movb %0,%%ah \n" /* get result */ \ - " andb $0x28,%%ah \n" /* maks flags 5+3 */ \ - " orb %%ah,%1 \n" /* put them into flags */ \ - :"=q" (_Z80_A), "=q" (_F) \ - :"q" (value), "1" (_F), "0" (_Z80_A) \ - ) -#else -#define SBC(value) \ - asm ( \ - " shrb $1,%1 \n" \ - " sbbb %2,%0 \n" \ - " lahf \n" \ - " setob %1 \n" /* al = 1 if overflow */ \ - " stc \n" /* prepare to set N flag */ \ - " adcb %1,%1 \n" /* shift to P/V bit position */ \ - " addb %1,%1 \n" \ - " andb $0xd1,%%ah \n" /* sign, zero, half carry, carry */ \ - " orb %%ah,%1 \n" /* combine with P/V */ \ - :"=q" (_Z80_A), "=q" (_F) \ - :"q" (value), "1" (_F), "0" (_Z80_A) \ - ) -#endif -#else -#if BIG_FLAGS_ARRAY -#define SBC(value) \ -{ \ - UINT32 ah = _AFD & 0xff00, c = _AFD & 1; \ - UINT32 res = (UINT8)((ah >> 8) - value - c); \ - _F = SZHVC_sub[(c<<16) | ah | res]; \ - _Z80_A = res; \ -} -#else -#define SBC(value) \ -{ \ - unsigned val = value; \ - unsigned res = _Z80_A - val - (_F & CF); \ - _F = SZ[res & 0xff] | ((res >> 8) & CF) | NF | \ - ((_Z80_A ^ res ^ val) & HF) | \ - (((val ^ _Z80_A) & (_Z80_A ^ res) & 0x80) >> 5); \ - _Z80_A = res; \ -} -#endif -#endif - -/*************************************************************** - * NEG - ***************************************************************/ -#define NEG { \ - UINT8 value = _Z80_A; \ - _Z80_A = 0; \ - SUB(value); \ -} - -/*************************************************************** - * DAA - ***************************************************************/ -#define DAA { \ - UINT8 cf, nf, hf, lo, hi, diff; \ - cf = _F & CF; \ - nf = _F & NF; \ - hf = _F & HF; \ - lo = _Z80_A & 15; \ - hi = _Z80_A / 16; \ - \ - if (cf) \ - { \ - diff = (lo <= 9 && !hf) ? 0x60 : 0x66; \ - } \ - else \ - { \ - if (lo >= 10) \ - { \ - diff = hi <= 8 ? 0x06 : 0x66; \ - } \ - else \ - { \ - if (hi >= 10) \ - { \ - diff = hf ? 0x66 : 0x60; \ - } \ - else \ - { \ - diff = hf ? 0x06 : 0x00; \ - } \ - } \ - } \ - if (nf) _Z80_A -= diff; \ - else _Z80_A += diff; \ - \ - _F = SZP[_Z80_A] | (_F & NF); \ - if (cf || (lo <= 9 ? hi >= 10 : hi >= 9)) _F |= CF; \ - if (nf ? hf && lo <= 5 : lo >= 10) _F |= HF; \ -} - -/*************************************************************** - * AND n - ***************************************************************/ -#define AND(value) \ - _Z80_A &= value; \ - _F = SZP[_Z80_A] | HF - -/*************************************************************** - * OR n - ***************************************************************/ -#define OR(value) \ - _Z80_A |= value; \ - _F = SZP[_Z80_A] - -/*************************************************************** - * XOR n - ***************************************************************/ -#define XOR(value) \ - _Z80_A ^= value; \ - _F = SZP[_Z80_A] - -/*************************************************************** - * CP n - ***************************************************************/ -#ifdef X86_ASM -#if Z80_EXACT -#define CP(value) \ - asm ( \ - " cmpb %2,%0 \n" \ - " lahf \n" \ - " setob %1 \n" /* al = 1 if overflow */ \ - " stc \n" /* prepare to set N flag */ \ - " adcb %1,%1 \n" /* shift to P/V bit position */ \ - " addb %1,%1 \n" \ - " andb $0xd1,%%ah \n" /* sign, zero, half carry, carry */ \ - " orb %%ah,%1 \n" /* combine with P/V */ \ - " movb %2,%%ah \n" /* get result */ \ - " andb $0x28,%%ah \n" /* maks flags 5+3 */ \ - " orb %%ah,%1 \n" /* put them into flags */ \ - :"=q" (_Z80_A), "=q" (_F) \ - :"q" (value), "1" (_F), "0" (_Z80_A) \ - ) -#else -#define CP(value) \ - asm ( \ - " cmpb %2,%0 \n" \ - " lahf \n" \ - " setob %1 \n" /* al = 1 if overflow */ \ - " stc \n" /* prepare to set N flag */ \ - " adcb %1,%1 \n" /* shift to P/V bit position */ \ - " addb %1,%1 \n" \ - " andb $0xd1,%%ah \n" /* sign, zero, half carry, carry */ \ - " orb %%ah,%1 \n" /* combine with P/V */ \ - :"=q" (_Z80_A), "=q" (_F) \ - :"q" (value), "1" (_F), "0" (_Z80_A) \ - ) -#endif -#else -#if BIG_FLAGS_ARRAY -#define CP(value) \ -{ \ - unsigned val = value; \ - UINT32 ah = _AFD & 0xff00; \ - UINT32 res = (UINT8)((ah >> 8) - val); \ - _F = (SZHVC_sub[ah | res] & ~(YF | XF)) | \ - (val & (YF | XF)); \ -} -#else -#define CP(value) \ -{ \ - unsigned val = value; \ - unsigned res = _Z80_A - val; \ - _F = (SZ[res & 0xff] & (SF | ZF)) | \ - (val & (YF | XF)) | ((res >> 8) & CF) | NF | \ - ((_Z80_A ^ res ^ val) & HF) | \ - ((((val ^ _Z80_A) & (_Z80_A ^ res)) >> 5) & VF); \ -} -#endif -#endif - -/*************************************************************** - * EX AF,AF' - ***************************************************************/ -#define EX_AF { \ - PAIR tmp; \ - tmp = Z80.AF; Z80.AF = Z80.AF2; Z80.AF2 = tmp; \ -} - -/*************************************************************** - * EX DE,HL - ***************************************************************/ -#define EX_DE_HL { \ - PAIR tmp; \ - tmp = Z80.DE; Z80.DE = Z80.HL; Z80.HL = tmp; \ -} - -/*************************************************************** - * EXX - ***************************************************************/ -#define EXX { \ - PAIR tmp; \ - tmp = Z80.BC; Z80.BC = Z80.BC2; Z80.BC2 = tmp; \ - tmp = Z80.DE; Z80.DE = Z80.DE2; Z80.DE2 = tmp; \ - tmp = Z80.HL; Z80.HL = Z80.HL2; Z80.HL2 = tmp; \ -} - -/*************************************************************** - * EX (SP),r16 - ***************************************************************/ -#define EXSP(DR) \ -{ \ - PAIR tmp = { { 0, 0, 0, 0 } }; \ - RM16( _SPD, &tmp ); \ - WM16( _SPD, &Z80.DR ); \ - Z80.DR = tmp; \ -} - - -/*************************************************************** - * ADD16 - ***************************************************************/ -#ifdef X86_ASM -#if Z80_EXACT -#define ADD16(DR,SR) \ - asm ( \ - " andb $0xc4,%1 \n" \ - " addb %%dl,%%cl \n" \ - " adcb %%dh,%%ch \n" \ - " lahf \n" \ - " andb $0x11,%%ah \n" \ - " orb %%ah,%1 \n" \ - " movb %%ch,%%ah \n" /* get result MSB */ \ - " andb $0x28,%%ah \n" /* maks flags 5+3 */ \ - " orb %%ah,%1 \n" /* put them into flags */ \ - :"=c" (Z80.DR.d), "=q" (_F) \ - :"0" (Z80.DR.d), "1" (_F), "d" (Z80.SR.d) \ - ) -#else -#define ADD16(DR,SR) \ - asm ( \ - " andb $0xc4,%1 \n" \ - " addb %%dl,%%cl \n" \ - " adcb %%dh,%%ch \n" \ - " lahf \n" \ - " andb $0x11,%%ah \n" \ - " orb %%ah,%1 \n" \ - :"=c" (Z80.DR.d), "=q" (_F) \ - :"0" (Z80.DR.d), "1" (_F), "d" (Z80.SR.d) \ - ) -#endif -#else -#define ADD16(DR,SR) \ -{ \ - UINT32 res = Z80.DR.d + Z80.SR.d; \ - _F = (_F & (SF | ZF | VF)) | \ - (((Z80.DR.d ^ res ^ Z80.SR.d) >> 8) & HF) | \ - ((res >> 16) & CF) | ((res >> 8) & (YF | XF)); \ - Z80.DR.w.l = (UINT16)res; \ -} -#endif - -/*************************************************************** - * ADC r16,r16 - ***************************************************************/ -#ifdef X86_ASM -#if Z80_EXACT -#define ADC16(Reg) \ - asm ( \ - " shrb $1,%1 \n" \ - " adcb %%dl,%%cl \n" \ - " lahf \n" \ - " movb %%ah,%%dl \n" \ - " adcb %%dh,%%ch \n" \ - " lahf \n" \ - " setob %1 \n" \ - " orb $0xbf,%%dl \n" /* set all but zero */ \ - " addb %1,%1 \n" \ - " andb $0xd1,%%ah \n" /* sign,zero,half carry and carry */\ - " addb %1,%1 \n" \ - " orb %%ah,%1 \n" /* overflow into P/V */ \ - " andb %%dl,%1 \n" /* mask zero */ \ - " movb %%ch,%%ah \n" /* get result MSB */ \ - " andb $0x28,%%ah \n" /* maks flags 5+3 */ \ - " orb %%ah,%1 \n" /* put them into flags */ \ - :"=c" (_HLD), "=q" (_F) \ - :"0" (_HLD), "1" (_F), "d" (Z80.Reg.d) \ - ) -#else -#define ADC16(Reg) \ - asm ( \ - " shrb $1,%1 \n" \ - " adcb %%dl,%%cl \n" \ - " lahf \n" \ - " movb %%ah,%%dl \n" \ - " adcb %%dh,%%ch \n" \ - " lahf \n" \ - " setob %1 \n" \ - " orb $0xbf,%%dl \n" /* set all but zero */ \ - " addb %1,%1 \n" \ - " andb $0xd1,%%ah \n" /* sign,zero,half carry and carry */\ - " addb %1,%1 \n" \ - " orb %%ah,%1 \n" /* overflow into P/V */ \ - " andb %%dl,%1 \n" /* mask zero */ \ - :"=c" (_HLD), "=q" (_F) \ - :"0" (_HLD), "1" (_F), "d" (Z80.Reg.d) \ - ) -#endif -#else -#define ADC16(Reg) \ -{ \ - UINT32 res = _HLD + Z80.Reg.d + (_F & CF); \ - _F = (((_HLD ^ res ^ Z80.Reg.d) >> 8) & HF) | \ - ((res >> 16) & CF) | \ - ((res >> 8) & (SF | YF | XF)) | \ - ((res & 0xffff) ? 0 : ZF) | \ - (((Z80.Reg.d ^ _HLD ^ 0x8000) & (Z80.Reg.d ^ res) & 0x8000) >> 13); \ - _HL = (UINT16)res; \ -} -#endif - -/*************************************************************** - * SBC r16,r16 - ***************************************************************/ -#ifdef X86_ASM -#if Z80_EXACT -#define SBC16(Reg) \ -asm ( \ - " shrb $1,%1 \n" \ - " sbbb %%dl,%%cl \n" \ - " lahf \n" \ - " movb %%ah,%%dl \n" \ - " sbbb %%dh,%%ch \n" \ - " lahf \n" \ - " setob %1 \n" \ - " orb $0xbf,%%dl \n" /* set all but zero */ \ - " stc \n" \ - " adcb %1,%1 \n" \ - " andb $0xd1,%%ah \n" /* sign,zero,half carry and carry */\ - " addb %1,%1 \n" \ - " orb %%ah,%1 \n" /* overflow into P/V */ \ - " andb %%dl,%1 \n" /* mask zero */ \ - " movb %%ch,%%ah \n" /* get result MSB */ \ - " andb $0x28,%%ah \n" /* maks flags 5+3 */ \ - " orb %%ah,%1 \n" /* put them into flags */ \ - :"=c" (_HLD), "=q" (_F) \ - :"0" (_HLD), "1" (_F), "d" (Z80.Reg.d) \ - ) -#else -#define SBC16(Reg) \ -asm ( \ - " shrb $1,%1 \n" \ - " sbbb %%dl,%%cl \n" \ - " lahf \n" \ - " movb %%ah,%%dl \n" \ - " sbbb %%dh,%%ch \n" \ - " lahf \n" \ - " setob %1 \n" \ - " orb $0xbf,%%dl \n" /* set all but zero */ \ - " stc \n" \ - " adcb %1,%1 \n" \ - " andb $0xd1,%%ah \n" /* sign,zero,half carry and carry */\ - " addb %1,%1 \n" \ - " orb %%ah,%1 \n" /* overflow into P/V */ \ - " andb %%dl,%1 \n" /* mask zero */ \ - :"=c" (_HLD), "=q" (_F) \ - :"0" (_HLD), "1" (_F), "d" (Z80.Reg.d) \ - ) -#endif -#else -#define SBC16(Reg) \ -{ \ - UINT32 res = _HLD - Z80.Reg.d - (_F & CF); \ - _F = (((_HLD ^ res ^ Z80.Reg.d) >> 8) & HF) | NF | \ - ((res >> 16) & CF) | \ - ((res >> 8) & (SF | YF | XF)) | \ - ((res & 0xffff) ? 0 : ZF) | \ - (((Z80.Reg.d ^ _HLD) & (_HLD ^ res) &0x8000) >> 13); \ - _HL = (UINT16)res; \ -} -#endif - -/*************************************************************** - * RLC r8 - ***************************************************************/ -INLINE UINT8 RLC(UINT8 value) -{ - unsigned res = value; - unsigned c = (res & 0x80) ? CF : 0; - res = ((res << 1) | (res >> 7)) & 0xff; - _F = SZP[res] | c; - return res; -} - -/*************************************************************** - * RRC r8 - ***************************************************************/ -INLINE UINT8 RRC(UINT8 value) -{ - unsigned res = value; - unsigned c = (res & 0x01) ? CF : 0; - res = ((res >> 1) | (res << 7)) & 0xff; - _F = SZP[res] | c; - return res; -} - -/*************************************************************** - * RL r8 - ***************************************************************/ -INLINE UINT8 RL(UINT8 value) -{ - unsigned res = value; - unsigned c = (res & 0x80) ? CF : 0; - res = ((res << 1) | (_F & CF)) & 0xff; - _F = SZP[res] | c; - return res; -} - -/*************************************************************** - * RR r8 - ***************************************************************/ -INLINE UINT8 RR(UINT8 value) -{ - unsigned res = value; - unsigned c = (res & 0x01) ? CF : 0; - res = ((res >> 1) | (_F << 7)) & 0xff; - _F = SZP[res] | c; - return res; -} - -/*************************************************************** - * SLA r8 - ***************************************************************/ -INLINE UINT8 SLA(UINT8 value) -{ - unsigned res = value; - unsigned c = (res & 0x80) ? CF : 0; - res = (res << 1) & 0xff; - _F = SZP[res] | c; - return res; -} - -/*************************************************************** - * SRA r8 - ***************************************************************/ -INLINE UINT8 SRA(UINT8 value) -{ - unsigned res = value; - unsigned c = (res & 0x01) ? CF : 0; - res = ((res >> 1) | (res & 0x80)) & 0xff; - _F = SZP[res] | c; - return res; -} - -/*************************************************************** - * SLL r8 - ***************************************************************/ -INLINE UINT8 SLL(UINT8 value) -{ - unsigned res = value; - unsigned c = (res & 0x80) ? CF : 0; - res = ((res << 1) | 0x01) & 0xff; - _F = SZP[res] | c; - return res; -} - -/*************************************************************** - * SRL r8 - ***************************************************************/ -INLINE UINT8 SRL(UINT8 value) -{ - unsigned res = value; - unsigned c = (res & 0x01) ? CF : 0; - res = (res >> 1) & 0xff; - _F = SZP[res] | c; - return res; -} - -/*************************************************************** - * BIT bit,r8 - ***************************************************************/ -#undef BIT -#define BIT(bit,reg) \ - _F = (_F & CF) | HF | SZ_BIT[reg & (1<>8) & (YF|XF)) -#else -#define BIT_XY BIT -#endif - -/*************************************************************** - * RES bit,r8 - ***************************************************************/ -INLINE UINT8 RES(UINT8 bit, UINT8 value) -{ - return value & ~(1< flag 5 */ \ - if( (_Z80_A + io) & 0x08 ) _F |= XF; /* bit 3 -> flag 3 */ \ - _HL++; _DE++; _BC--; \ - if( _BC ) _F |= VF; \ -} -#else -#define LDI { \ - WM( _DE, RM(_HL) ); \ - _F &= SF | ZF | YF | XF | CF; \ - _HL++; _DE++; _BC--; \ - if( _BC ) _F |= VF; \ -} -#endif - -/*************************************************************** - * CPI - ***************************************************************/ -#if Z80_EXACT -#define CPI { \ - UINT8 val = RM(_HL); \ - UINT8 res = _Z80_A - val; \ - _HL++; _BC--; \ - _F = (_F & CF) | (SZ[res] & ~(YF|XF)) | ((_Z80_A ^ val ^ res) & HF) | NF; \ - if( _F & HF ) res -= 1; \ - if( res & 0x02 ) _F |= YF; /* bit 1 -> flag 5 */ \ - if( res & 0x08 ) _F |= XF; /* bit 3 -> flag 3 */ \ - if( _BC ) _F |= VF; \ -} -#else -#define CPI { \ - UINT8 val = RM(_HL); \ - UINT8 res = _Z80_A - val; \ - _HL++; _BC--; \ - _F = (_F & CF) | SZ[res] | ((_Z80_A ^ val ^ res) & HF) | NF; \ - if( _BC ) _F |= VF; \ -} -#endif - -/*************************************************************** - * INI - ***************************************************************/ -#if Z80_EXACT -#define INI { \ - unsigned t; \ - UINT8 io = IN(_BC); \ - _Z80_B--; \ - WM( _HL, io ); \ - _HL++; \ - _F = SZ[_Z80_B]; \ - t = (unsigned)((_Z80_C + 1) & 0xff) + (unsigned)io; \ - if( io & SF ) _F |= NF; \ - if( t & 0x100 ) _F |= HF | CF; \ - _F |= SZP[(UINT8)(t & 0x07) ^ _Z80_B] & PF; \ -} -#else -#define INI { \ - _Z80_B--; \ - WM( _HL, IN(_BC) ); \ - _HL++; \ - _F = (_Z80_B) ? NF : NF | ZF; \ -} -#endif - -/*************************************************************** - * OUTI - ***************************************************************/ -#if Z80_EXACT -#define OUTI { \ - unsigned t; \ - UINT8 io = RM(_HL); \ - _Z80_B--; \ - OUT( _BC, io ); \ - _HL++; \ - _F = SZ[_Z80_B]; \ - t = (unsigned)_Z80_L + (unsigned)io; \ - if( io & SF ) _F |= NF; \ - if( t & 0x100 ) _F |= HF | CF; \ - _F |= SZP[(UINT8)(t & 0x07) ^ _Z80_B] & PF; \ -} -#else -#define OUTI { \ - _Z80_B--; \ - OUT( _BC, RM(_HL) ); \ - _HL++; \ - _F = (_Z80_B) ? NF : NF | ZF; \ -} -#endif - -/*************************************************************** - * LDD - ***************************************************************/ -#if Z80_EXACT -#define LDD { \ - UINT8 io = RM(_HL); \ - WM( _DE, io ); \ - _F &= SF | ZF | CF; \ - if( (_Z80_A + io) & 0x02 ) _F |= YF; /* bit 1 -> flag 5 */ \ - if( (_Z80_A + io) & 0x08 ) _F |= XF; /* bit 3 -> flag 3 */ \ - _HL--; _DE--; _BC--; \ - if( _BC ) _F |= VF; \ -} -#else -#define LDD { \ - WM( _DE, RM(_HL) ); \ - _F &= SF | ZF | YF | XF | CF; \ - _HL--; _DE--; _BC--; \ - if( _BC ) _F |= VF; \ -} -#endif - -/*************************************************************** - * CPD - ***************************************************************/ -#if Z80_EXACT -#define CPD { \ - UINT8 val = RM(_HL); \ - UINT8 res = _Z80_A - val; \ - _HL--; _BC--; \ - _F = (_F & CF) | (SZ[res] & ~(YF|XF)) | ((_Z80_A ^ val ^ res) & HF) | NF; \ - if( _F & HF ) res -= 1; \ - if( res & 0x02 ) _F |= YF; /* bit 1 -> flag 5 */ \ - if( res & 0x08 ) _F |= XF; /* bit 3 -> flag 3 */ \ - if( _BC ) _F |= VF; \ -} -#else -#define CPD { \ - UINT8 val = RM(_HL); \ - UINT8 res = _Z80_A - val; \ - _HL--; _BC--; \ - _F = (_F & CF) | SZ[res] | ((_Z80_A ^ val ^ res) & HF) | NF; \ - if( _BC ) _F |= VF; \ -} -#endif - -/*************************************************************** - * IND - ***************************************************************/ -#if Z80_EXACT -#define IND { \ - unsigned t; \ - UINT8 io = IN(_BC); \ - _Z80_B--; \ - WM( _HL, io ); \ - _HL--; \ - _F = SZ[_Z80_B]; \ - t = ((unsigned)(_Z80_C - 1) & 0xff) + (unsigned)io; \ - if( io & SF ) _F |= NF; \ - if( t & 0x100 ) _F |= HF | CF; \ - _F |= SZP[(UINT8)(t & 0x07) ^ _Z80_B] & PF; \ -} -#else -#define IND { \ - _Z80_B--; \ - WM( _HL, IN(_BC) ); \ - _HL--; \ - _F = (_Z80_B) ? NF : NF | ZF; \ -} -#endif - -/*************************************************************** - * OUTD - ***************************************************************/ -#if Z80_EXACT -#define OUTD { \ - unsigned t; \ - UINT8 io = RM(_HL); \ - _Z80_B--; \ - OUT( _BC, io ); \ - _HL--; \ - _F = SZ[_Z80_B]; \ - t = (unsigned)_Z80_L + (unsigned)io; \ - if( io & SF ) _F |= NF; \ - if( t & 0x100 ) _F |= HF | CF; \ - _F |= SZP[(UINT8)(t & 0x07) ^ _Z80_B] & PF; \ -} -#else -#define OUTD { \ - _Z80_B--; \ - OUT( _BC, RM(_HL) ); \ - _HL--; \ - _F = (_Z80_B) ? NF : NF | ZF; \ -} -#endif - -/*************************************************************** - * LDIR - ***************************************************************/ -#define LDIR \ - LDI; \ - if( _BC ) \ - { \ - _PC -= 2; \ - CC(ex,0xb0); \ - } - -/*************************************************************** - * CPIR - ***************************************************************/ -#define CPIR \ - CPI; \ - if( _BC && !(_F & ZF) ) \ - { \ - _PC -= 2; \ - CC(ex,0xb1); \ - } - -/*************************************************************** - * INIR - ***************************************************************/ -#define INIR \ - INI; \ - if( _Z80_B ) \ - { \ - _PC -= 2; \ - CC(ex,0xb2); \ - } - -/*************************************************************** - * OTIR - ***************************************************************/ -#define OTIR \ - OUTI; \ - if( _Z80_B ) \ - { \ - _PC -= 2; \ - CC(ex,0xb3); \ - } - -/*************************************************************** - * LDDR - ***************************************************************/ -#define LDDR \ - LDD; \ - if( _BC ) \ - { \ - _PC -= 2; \ - CC(ex,0xb8); \ - } - -/*************************************************************** - * CPDR - ***************************************************************/ -#define CPDR \ - CPD; \ - if( _BC && !(_F & ZF) ) \ - { \ - _PC -= 2; \ - CC(ex,0xb9); \ - } - -/*************************************************************** - * INDR - ***************************************************************/ -#define INDR \ - IND; \ - if( _Z80_B ) \ - { \ - _PC -= 2; \ - CC(ex,0xba); \ - } - -/*************************************************************** - * OTDR - ***************************************************************/ -#define OTDR \ - OUTD; \ - if( _Z80_B ) \ - { \ - _PC -= 2; \ - CC(ex,0xbb); \ - } - -/*************************************************************** - * EI - ***************************************************************/ -#define EI { \ - /* If interrupts were disabled, execute one more \ - * instruction and check the IRQ line. \ - * If not, simply set interrupt flip-flop 2 \ - */ \ - if( _IFF1 == 0 ) \ - { \ - _IFF1 = _IFF2 = 1; \ - _PPC = _PCD; \ - CALL_MAME_DEBUG; \ - _Z80_R++; \ - while( cpu_readop(_PCD) == 0xfb ) /* more EIs? */ \ - { \ - CC(op,0xfb); \ - _PPC =_PCD; \ - CALL_MAME_DEBUG; \ - _PC++; \ - _Z80_R++; \ - } \ - if( Z80.irq_state != CLEAR_LINE || \ - Z80.request_irq >= 0 ) \ - { \ - after_EI = 1; /* avoid cycle skip hacks */ \ - EXEC(op,ROP()); \ - after_EI = 0; \ - take_interrupt(); \ - } else EXEC(op,ROP()); \ - } else _IFF2 = 1; \ -} - -/********************************************************** - * opcodes with CB prefix - * rotate, shift and bit operations - **********************************************************/ -OP(cb,00) { _Z80_B = RLC(_Z80_B); } /* RLC B */ -OP(cb,01) { _Z80_C = RLC(_Z80_C); } /* RLC C */ -OP(cb,02) { _Z80_D = RLC(_Z80_D); } /* RLC D */ -OP(cb,03) { _Z80_E = RLC(_Z80_E); } /* RLC E */ -OP(cb,04) { _Z80_H = RLC(_Z80_H); } /* RLC H */ -OP(cb,05) { _Z80_L = RLC(_Z80_L); } /* RLC L */ -OP(cb,06) { WM( _HL, RLC(RM(_HL)) ); } /* RLC (HL) */ -OP(cb,07) { _Z80_A = RLC(_Z80_A); } /* RLC A */ - -OP(cb,08) { _Z80_B = RRC(_Z80_B); } /* RRC B */ -OP(cb,09) { _Z80_C = RRC(_Z80_C); } /* RRC C */ -OP(cb,0a) { _Z80_D = RRC(_Z80_D); } /* RRC D */ -OP(cb,0b) { _Z80_E = RRC(_Z80_E); } /* RRC E */ -OP(cb,0c) { _Z80_H = RRC(_Z80_H); } /* RRC H */ -OP(cb,0d) { _Z80_L = RRC(_Z80_L); } /* RRC L */ -OP(cb,0e) { WM( _HL, RRC(RM(_HL)) ); } /* RRC (HL) */ -OP(cb,0f) { _Z80_A = RRC(_Z80_A); } /* RRC A */ - -OP(cb,10) { _Z80_B = RL(_Z80_B); } /* RL B */ -OP(cb,11) { _Z80_C = RL(_Z80_C); } /* RL C */ -OP(cb,12) { _Z80_D = RL(_Z80_D); } /* RL D */ -OP(cb,13) { _Z80_E = RL(_Z80_E); } /* RL E */ -OP(cb,14) { _Z80_H = RL(_Z80_H); } /* RL H */ -OP(cb,15) { _Z80_L = RL(_Z80_L); } /* RL L */ -OP(cb,16) { WM( _HL, RL(RM(_HL)) ); } /* RL (HL) */ -OP(cb,17) { _Z80_A = RL(_Z80_A); } /* RL A */ - -OP(cb,18) { _Z80_B = RR(_Z80_B); } /* RR B */ -OP(cb,19) { _Z80_C = RR(_Z80_C); } /* RR C */ -OP(cb,1a) { _Z80_D = RR(_Z80_D); } /* RR D */ -OP(cb,1b) { _Z80_E = RR(_Z80_E); } /* RR E */ -OP(cb,1c) { _Z80_H = RR(_Z80_H); } /* RR H */ -OP(cb,1d) { _Z80_L = RR(_Z80_L); } /* RR L */ -OP(cb,1e) { WM( _HL, RR(RM(_HL)) ); } /* RR (HL) */ -OP(cb,1f) { _Z80_A = RR(_Z80_A); } /* RR A */ - -OP(cb,20) { _Z80_B = SLA(_Z80_B); } /* SLA B */ -OP(cb,21) { _Z80_C = SLA(_Z80_C); } /* SLA C */ -OP(cb,22) { _Z80_D = SLA(_Z80_D); } /* SLA D */ -OP(cb,23) { _Z80_E = SLA(_Z80_E); } /* SLA E */ -OP(cb,24) { _Z80_H = SLA(_Z80_H); } /* SLA H */ -OP(cb,25) { _Z80_L = SLA(_Z80_L); } /* SLA L */ -OP(cb,26) { WM( _HL, SLA(RM(_HL)) ); } /* SLA (HL) */ -OP(cb,27) { _Z80_A = SLA(_Z80_A); } /* SLA A */ - -OP(cb,28) { _Z80_B = SRA(_Z80_B); } /* SRA B */ -OP(cb,29) { _Z80_C = SRA(_Z80_C); } /* SRA C */ -OP(cb,2a) { _Z80_D = SRA(_Z80_D); } /* SRA D */ -OP(cb,2b) { _Z80_E = SRA(_Z80_E); } /* SRA E */ -OP(cb,2c) { _Z80_H = SRA(_Z80_H); } /* SRA H */ -OP(cb,2d) { _Z80_L = SRA(_Z80_L); } /* SRA L */ -OP(cb,2e) { WM( _HL, SRA(RM(_HL)) ); } /* SRA (HL) */ -OP(cb,2f) { _Z80_A = SRA(_Z80_A); } /* SRA A */ - -OP(cb,30) { _Z80_B = SLL(_Z80_B); } /* SLL B */ -OP(cb,31) { _Z80_C = SLL(_Z80_C); } /* SLL C */ -OP(cb,32) { _Z80_D = SLL(_Z80_D); } /* SLL D */ -OP(cb,33) { _Z80_E = SLL(_Z80_E); } /* SLL E */ -OP(cb,34) { _Z80_H = SLL(_Z80_H); } /* SLL H */ -OP(cb,35) { _Z80_L = SLL(_Z80_L); } /* SLL L */ -OP(cb,36) { WM( _HL, SLL(RM(_HL)) ); } /* SLL (HL) */ -OP(cb,37) { _Z80_A = SLL(_Z80_A); } /* SLL A */ - -OP(cb,38) { _Z80_B = SRL(_Z80_B); } /* SRL B */ -OP(cb,39) { _Z80_C = SRL(_Z80_C); } /* SRL C */ -OP(cb,3a) { _Z80_D = SRL(_Z80_D); } /* SRL D */ -OP(cb,3b) { _Z80_E = SRL(_Z80_E); } /* SRL E */ -OP(cb,3c) { _Z80_H = SRL(_Z80_H); } /* SRL H */ -OP(cb,3d) { _Z80_L = SRL(_Z80_L); } /* SRL L */ -OP(cb,3e) { WM( _HL, SRL(RM(_HL)) ); } /* SRL (HL) */ -OP(cb,3f) { _Z80_A = SRL(_Z80_A); } /* SRL A */ - -OP(cb,40) { BIT(0,_Z80_B); } /* BIT 0,B */ -OP(cb,41) { BIT(0,_Z80_C); } /* BIT 0,C */ -OP(cb,42) { BIT(0,_Z80_D); } /* BIT 0,D */ -OP(cb,43) { BIT(0,_Z80_E); } /* BIT 0,E */ -OP(cb,44) { BIT(0,_Z80_H); } /* BIT 0,H */ -OP(cb,45) { BIT(0,_Z80_L); } /* BIT 0,L */ -OP(cb,46) { BIT(0,RM(_HL)); } /* BIT 0,(HL) */ -OP(cb,47) { BIT(0,_Z80_A); } /* BIT 0,A */ - -OP(cb,48) { BIT(1,_Z80_B); } /* BIT 1,B */ -OP(cb,49) { BIT(1,_Z80_C); } /* BIT 1,C */ -OP(cb,4a) { BIT(1,_Z80_D); } /* BIT 1,D */ -OP(cb,4b) { BIT(1,_Z80_E); } /* BIT 1,E */ -OP(cb,4c) { BIT(1,_Z80_H); } /* BIT 1,H */ -OP(cb,4d) { BIT(1,_Z80_L); } /* BIT 1,L */ -OP(cb,4e) { BIT(1,RM(_HL)); } /* BIT 1,(HL) */ -OP(cb,4f) { BIT(1,_Z80_A); } /* BIT 1,A */ - -OP(cb,50) { BIT(2,_Z80_B); } /* BIT 2,B */ -OP(cb,51) { BIT(2,_Z80_C); } /* BIT 2,C */ -OP(cb,52) { BIT(2,_Z80_D); } /* BIT 2,D */ -OP(cb,53) { BIT(2,_Z80_E); } /* BIT 2,E */ -OP(cb,54) { BIT(2,_Z80_H); } /* BIT 2,H */ -OP(cb,55) { BIT(2,_Z80_L); } /* BIT 2,L */ -OP(cb,56) { BIT(2,RM(_HL)); } /* BIT 2,(HL) */ -OP(cb,57) { BIT(2,_Z80_A); } /* BIT 2,A */ - -OP(cb,58) { BIT(3,_Z80_B); } /* BIT 3,B */ -OP(cb,59) { BIT(3,_Z80_C); } /* BIT 3,C */ -OP(cb,5a) { BIT(3,_Z80_D); } /* BIT 3,D */ -OP(cb,5b) { BIT(3,_Z80_E); } /* BIT 3,E */ -OP(cb,5c) { BIT(3,_Z80_H); } /* BIT 3,H */ -OP(cb,5d) { BIT(3,_Z80_L); } /* BIT 3,L */ -OP(cb,5e) { BIT(3,RM(_HL)); } /* BIT 3,(HL) */ -OP(cb,5f) { BIT(3,_Z80_A); } /* BIT 3,A */ - -OP(cb,60) { BIT(4,_Z80_B); } /* BIT 4,B */ -OP(cb,61) { BIT(4,_Z80_C); } /* BIT 4,C */ -OP(cb,62) { BIT(4,_Z80_D); } /* BIT 4,D */ -OP(cb,63) { BIT(4,_Z80_E); } /* BIT 4,E */ -OP(cb,64) { BIT(4,_Z80_H); } /* BIT 4,H */ -OP(cb,65) { BIT(4,_Z80_L); } /* BIT 4,L */ -OP(cb,66) { BIT(4,RM(_HL)); } /* BIT 4,(HL) */ -OP(cb,67) { BIT(4,_Z80_A); } /* BIT 4,A */ - -OP(cb,68) { BIT(5,_Z80_B); } /* BIT 5,B */ -OP(cb,69) { BIT(5,_Z80_C); } /* BIT 5,C */ -OP(cb,6a) { BIT(5,_Z80_D); } /* BIT 5,D */ -OP(cb,6b) { BIT(5,_Z80_E); } /* BIT 5,E */ -OP(cb,6c) { BIT(5,_Z80_H); } /* BIT 5,H */ -OP(cb,6d) { BIT(5,_Z80_L); } /* BIT 5,L */ -OP(cb,6e) { BIT(5,RM(_HL)); } /* BIT 5,(HL) */ -OP(cb,6f) { BIT(5,_Z80_A); } /* BIT 5,A */ - -OP(cb,70) { BIT(6,_Z80_B); } /* BIT 6,B */ -OP(cb,71) { BIT(6,_Z80_C); } /* BIT 6,C */ -OP(cb,72) { BIT(6,_Z80_D); } /* BIT 6,D */ -OP(cb,73) { BIT(6,_Z80_E); } /* BIT 6,E */ -OP(cb,74) { BIT(6,_Z80_H); } /* BIT 6,H */ -OP(cb,75) { BIT(6,_Z80_L); } /* BIT 6,L */ -OP(cb,76) { BIT(6,RM(_HL)); } /* BIT 6,(HL) */ -OP(cb,77) { BIT(6,_Z80_A); } /* BIT 6,A */ - -OP(cb,78) { BIT(7,_Z80_B); } /* BIT 7,B */ -OP(cb,79) { BIT(7,_Z80_C); } /* BIT 7,C */ -OP(cb,7a) { BIT(7,_Z80_D); } /* BIT 7,D */ -OP(cb,7b) { BIT(7,_Z80_E); } /* BIT 7,E */ -OP(cb,7c) { BIT(7,_Z80_H); } /* BIT 7,H */ -OP(cb,7d) { BIT(7,_Z80_L); } /* BIT 7,L */ -OP(cb,7e) { BIT(7,RM(_HL)); } /* BIT 7,(HL) */ -OP(cb,7f) { BIT(7,_Z80_A); } /* BIT 7,A */ - -OP(cb,80) { _Z80_B = RES(0,_Z80_B); } /* RES 0,B */ -OP(cb,81) { _Z80_C = RES(0,_Z80_C); } /* RES 0,C */ -OP(cb,82) { _Z80_D = RES(0,_Z80_D); } /* RES 0,D */ -OP(cb,83) { _Z80_E = RES(0,_Z80_E); } /* RES 0,E */ -OP(cb,84) { _Z80_H = RES(0,_Z80_H); } /* RES 0,H */ -OP(cb,85) { _Z80_L = RES(0,_Z80_L); } /* RES 0,L */ -OP(cb,86) { WM( _HL, RES(0,RM(_HL)) ); } /* RES 0,(HL) */ -OP(cb,87) { _Z80_A = RES(0,_Z80_A); } /* RES 0,A */ - -OP(cb,88) { _Z80_B = RES(1,_Z80_B); } /* RES 1,B */ -OP(cb,89) { _Z80_C = RES(1,_Z80_C); } /* RES 1,C */ -OP(cb,8a) { _Z80_D = RES(1,_Z80_D); } /* RES 1,D */ -OP(cb,8b) { _Z80_E = RES(1,_Z80_E); } /* RES 1,E */ -OP(cb,8c) { _Z80_H = RES(1,_Z80_H); } /* RES 1,H */ -OP(cb,8d) { _Z80_L = RES(1,_Z80_L); } /* RES 1,L */ -OP(cb,8e) { WM( _HL, RES(1,RM(_HL)) ); } /* RES 1,(HL) */ -OP(cb,8f) { _Z80_A = RES(1,_Z80_A); } /* RES 1,A */ - -OP(cb,90) { _Z80_B = RES(2,_Z80_B); } /* RES 2,B */ -OP(cb,91) { _Z80_C = RES(2,_Z80_C); } /* RES 2,C */ -OP(cb,92) { _Z80_D = RES(2,_Z80_D); } /* RES 2,D */ -OP(cb,93) { _Z80_E = RES(2,_Z80_E); } /* RES 2,E */ -OP(cb,94) { _Z80_H = RES(2,_Z80_H); } /* RES 2,H */ -OP(cb,95) { _Z80_L = RES(2,_Z80_L); } /* RES 2,L */ -OP(cb,96) { WM( _HL, RES(2,RM(_HL)) ); } /* RES 2,(HL) */ -OP(cb,97) { _Z80_A = RES(2,_Z80_A); } /* RES 2,A */ - -OP(cb,98) { _Z80_B = RES(3,_Z80_B); } /* RES 3,B */ -OP(cb,99) { _Z80_C = RES(3,_Z80_C); } /* RES 3,C */ -OP(cb,9a) { _Z80_D = RES(3,_Z80_D); } /* RES 3,D */ -OP(cb,9b) { _Z80_E = RES(3,_Z80_E); } /* RES 3,E */ -OP(cb,9c) { _Z80_H = RES(3,_Z80_H); } /* RES 3,H */ -OP(cb,9d) { _Z80_L = RES(3,_Z80_L); } /* RES 3,L */ -OP(cb,9e) { WM( _HL, RES(3,RM(_HL)) ); } /* RES 3,(HL) */ -OP(cb,9f) { _Z80_A = RES(3,_Z80_A); } /* RES 3,A */ - -OP(cb,a0) { _Z80_B = RES(4,_Z80_B); } /* RES 4,B */ -OP(cb,a1) { _Z80_C = RES(4,_Z80_C); } /* RES 4,C */ -OP(cb,a2) { _Z80_D = RES(4,_Z80_D); } /* RES 4,D */ -OP(cb,a3) { _Z80_E = RES(4,_Z80_E); } /* RES 4,E */ -OP(cb,a4) { _Z80_H = RES(4,_Z80_H); } /* RES 4,H */ -OP(cb,a5) { _Z80_L = RES(4,_Z80_L); } /* RES 4,L */ -OP(cb,a6) { WM( _HL, RES(4,RM(_HL)) ); } /* RES 4,(HL) */ -OP(cb,a7) { _Z80_A = RES(4,_Z80_A); } /* RES 4,A */ - -OP(cb,a8) { _Z80_B = RES(5,_Z80_B); } /* RES 5,B */ -OP(cb,a9) { _Z80_C = RES(5,_Z80_C); } /* RES 5,C */ -OP(cb,aa) { _Z80_D = RES(5,_Z80_D); } /* RES 5,D */ -OP(cb,ab) { _Z80_E = RES(5,_Z80_E); } /* RES 5,E */ -OP(cb,ac) { _Z80_H = RES(5,_Z80_H); } /* RES 5,H */ -OP(cb,ad) { _Z80_L = RES(5,_Z80_L); } /* RES 5,L */ -OP(cb,ae) { WM( _HL, RES(5,RM(_HL)) ); } /* RES 5,(HL) */ -OP(cb,af) { _Z80_A = RES(5,_Z80_A); } /* RES 5,A */ - -OP(cb,b0) { _Z80_B = RES(6,_Z80_B); } /* RES 6,B */ -OP(cb,b1) { _Z80_C = RES(6,_Z80_C); } /* RES 6,C */ -OP(cb,b2) { _Z80_D = RES(6,_Z80_D); } /* RES 6,D */ -OP(cb,b3) { _Z80_E = RES(6,_Z80_E); } /* RES 6,E */ -OP(cb,b4) { _Z80_H = RES(6,_Z80_H); } /* RES 6,H */ -OP(cb,b5) { _Z80_L = RES(6,_Z80_L); } /* RES 6,L */ -OP(cb,b6) { WM( _HL, RES(6,RM(_HL)) ); } /* RES 6,(HL) */ -OP(cb,b7) { _Z80_A = RES(6,_Z80_A); } /* RES 6,A */ - -OP(cb,b8) { _Z80_B = RES(7,_Z80_B); } /* RES 7,B */ -OP(cb,b9) { _Z80_C = RES(7,_Z80_C); } /* RES 7,C */ -OP(cb,ba) { _Z80_D = RES(7,_Z80_D); } /* RES 7,D */ -OP(cb,bb) { _Z80_E = RES(7,_Z80_E); } /* RES 7,E */ -OP(cb,bc) { _Z80_H = RES(7,_Z80_H); } /* RES 7,H */ -OP(cb,bd) { _Z80_L = RES(7,_Z80_L); } /* RES 7,L */ -OP(cb,be) { WM( _HL, RES(7,RM(_HL)) ); } /* RES 7,(HL) */ -OP(cb,bf) { _Z80_A = RES(7,_Z80_A); } /* RES 7,A */ - -OP(cb,c0) { _Z80_B = SET(0,_Z80_B); } /* SET 0,B */ -OP(cb,c1) { _Z80_C = SET(0,_Z80_C); } /* SET 0,C */ -OP(cb,c2) { _Z80_D = SET(0,_Z80_D); } /* SET 0,D */ -OP(cb,c3) { _Z80_E = SET(0,_Z80_E); } /* SET 0,E */ -OP(cb,c4) { _Z80_H = SET(0,_Z80_H); } /* SET 0,H */ -OP(cb,c5) { _Z80_L = SET(0,_Z80_L); } /* SET 0,L */ -OP(cb,c6) { WM( _HL, SET(0,RM(_HL)) ); } /* SET 0,(HL) */ -OP(cb,c7) { _Z80_A = SET(0,_Z80_A); } /* SET 0,A */ - -OP(cb,c8) { _Z80_B = SET(1,_Z80_B); } /* SET 1,B */ -OP(cb,c9) { _Z80_C = SET(1,_Z80_C); } /* SET 1,C */ -OP(cb,ca) { _Z80_D = SET(1,_Z80_D); } /* SET 1,D */ -OP(cb,cb) { _Z80_E = SET(1,_Z80_E); } /* SET 1,E */ -OP(cb,cc) { _Z80_H = SET(1,_Z80_H); } /* SET 1,H */ -OP(cb,cd) { _Z80_L = SET(1,_Z80_L); } /* SET 1,L */ -OP(cb,ce) { WM( _HL, SET(1,RM(_HL)) ); } /* SET 1,(HL) */ -OP(cb,cf) { _Z80_A = SET(1,_Z80_A); } /* SET 1,A */ - -OP(cb,d0) { _Z80_B = SET(2,_Z80_B); } /* SET 2,B */ -OP(cb,d1) { _Z80_C = SET(2,_Z80_C); } /* SET 2,C */ -OP(cb,d2) { _Z80_D = SET(2,_Z80_D); } /* SET 2,D */ -OP(cb,d3) { _Z80_E = SET(2,_Z80_E); } /* SET 2,E */ -OP(cb,d4) { _Z80_H = SET(2,_Z80_H); } /* SET 2,H */ -OP(cb,d5) { _Z80_L = SET(2,_Z80_L); } /* SET 2,L */ -OP(cb,d6) { WM( _HL, SET(2,RM(_HL)) ); }/* SET 2,(HL) */ -OP(cb,d7) { _Z80_A = SET(2,_Z80_A); } /* SET 2,A */ - -OP(cb,d8) { _Z80_B = SET(3,_Z80_B); } /* SET 3,B */ -OP(cb,d9) { _Z80_C = SET(3,_Z80_C); } /* SET 3,C */ -OP(cb,da) { _Z80_D = SET(3,_Z80_D); } /* SET 3,D */ -OP(cb,db) { _Z80_E = SET(3,_Z80_E); } /* SET 3,E */ -OP(cb,dc) { _Z80_H = SET(3,_Z80_H); } /* SET 3,H */ -OP(cb,dd) { _Z80_L = SET(3,_Z80_L); } /* SET 3,L */ -OP(cb,de) { WM( _HL, SET(3,RM(_HL)) ); } /* SET 3,(HL) */ -OP(cb,df) { _Z80_A = SET(3,_Z80_A); } /* SET 3,A */ - -OP(cb,e0) { _Z80_B = SET(4,_Z80_B); } /* SET 4,B */ -OP(cb,e1) { _Z80_C = SET(4,_Z80_C); } /* SET 4,C */ -OP(cb,e2) { _Z80_D = SET(4,_Z80_D); } /* SET 4,D */ -OP(cb,e3) { _Z80_E = SET(4,_Z80_E); } /* SET 4,E */ -OP(cb,e4) { _Z80_H = SET(4,_Z80_H); } /* SET 4,H */ -OP(cb,e5) { _Z80_L = SET(4,_Z80_L); } /* SET 4,L */ -OP(cb,e6) { WM( _HL, SET(4,RM(_HL)) ); } /* SET 4,(HL) */ -OP(cb,e7) { _Z80_A = SET(4,_Z80_A); } /* SET 4,A */ - -OP(cb,e8) { _Z80_B = SET(5,_Z80_B); } /* SET 5,B */ -OP(cb,e9) { _Z80_C = SET(5,_Z80_C); } /* SET 5,C */ -OP(cb,ea) { _Z80_D = SET(5,_Z80_D); } /* SET 5,D */ -OP(cb,eb) { _Z80_E = SET(5,_Z80_E); } /* SET 5,E */ -OP(cb,ec) { _Z80_H = SET(5,_Z80_H); } /* SET 5,H */ -OP(cb,ed) { _Z80_L = SET(5,_Z80_L); } /* SET 5,L */ -OP(cb,ee) { WM( _HL, SET(5,RM(_HL)) ); } /* SET 5,(HL) */ -OP(cb,ef) { _Z80_A = SET(5,_Z80_A); } /* SET 5,A */ - -OP(cb,f0) { _Z80_B = SET(6,_Z80_B); } /* SET 6,B */ -OP(cb,f1) { _Z80_C = SET(6,_Z80_C); } /* SET 6,C */ -OP(cb,f2) { _Z80_D = SET(6,_Z80_D); } /* SET 6,D */ -OP(cb,f3) { _Z80_E = SET(6,_Z80_E); } /* SET 6,E */ -OP(cb,f4) { _Z80_H = SET(6,_Z80_H); } /* SET 6,H */ -OP(cb,f5) { _Z80_L = SET(6,_Z80_L); } /* SET 6,L */ -OP(cb,f6) { WM( _HL, SET(6,RM(_HL)) ); } /* SET 6,(HL) */ -OP(cb,f7) { _Z80_A = SET(6,_Z80_A); } /* SET 6,A */ - -OP(cb,f8) { _Z80_B = SET(7,_Z80_B); } /* SET 7,B */ -OP(cb,f9) { _Z80_C = SET(7,_Z80_C); } /* SET 7,C */ -OP(cb,fa) { _Z80_D = SET(7,_Z80_D); } /* SET 7,D */ -OP(cb,fb) { _Z80_E = SET(7,_Z80_E); } /* SET 7,E */ -OP(cb,fc) { _Z80_H = SET(7,_Z80_H); } /* SET 7,H */ -OP(cb,fd) { _Z80_L = SET(7,_Z80_L); } /* SET 7,L */ -OP(cb,fe) { WM( _HL, SET(7,RM(_HL)) ); } /* SET 7,(HL) */ -OP(cb,ff) { _Z80_A = SET(7,_Z80_A); } /* SET 7,A */ - - -/********************************************************** -* opcodes with DD/FD CB prefix -* rotate, shift and bit operations with (IX+o) -**********************************************************/ -OP(xycb,00) { _Z80_B = RLC( RM(EA) ); WM( EA,_Z80_B ); } /* RLC B=(XY+o) */ -OP(xycb,01) { _Z80_C = RLC( RM(EA) ); WM( EA,_Z80_C ); } /* RLC C=(XY+o) */ -OP(xycb,02) { _Z80_D = RLC( RM(EA) ); WM( EA,_Z80_D ); } /* RLC D=(XY+o) */ -OP(xycb,03) { _Z80_E = RLC( RM(EA) ); WM( EA,_Z80_E ); } /* RLC E=(XY+o) */ -OP(xycb,04) { _Z80_H = RLC( RM(EA) ); WM( EA,_Z80_H ); } /* RLC H=(XY+o) */ -OP(xycb,05) { _Z80_L = RLC( RM(EA) ); WM( EA,_Z80_L ); } /* RLC L=(XY+o) */ -OP(xycb,06) { WM( EA, RLC( RM(EA) ) ); } /* RLC (XY+o) */ -OP(xycb,07) { _Z80_A = RLC( RM(EA) ); WM( EA,_Z80_A ); } /* RLC A=(XY+o) */ - -OP(xycb,08) { _Z80_B = RRC( RM(EA) ); WM( EA,_Z80_B ); } /* RRC B=(XY+o) */ -OP(xycb,09) { _Z80_C = RRC( RM(EA) ); WM( EA,_Z80_C ); } /* RRC C=(XY+o) */ -OP(xycb,0a) { _Z80_D = RRC( RM(EA) ); WM( EA,_Z80_D ); } /* RRC D=(XY+o) */ -OP(xycb,0b) { _Z80_E = RRC( RM(EA) ); WM( EA,_Z80_E ); } /* RRC E=(XY+o) */ -OP(xycb,0c) { _Z80_H = RRC( RM(EA) ); WM( EA,_Z80_H ); } /* RRC H=(XY+o) */ -OP(xycb,0d) { _Z80_L = RRC( RM(EA) ); WM( EA,_Z80_L ); } /* RRC L=(XY+o) */ -OP(xycb,0e) { WM( EA,RRC( RM(EA) ) ); } /* RRC (XY+o) */ -OP(xycb,0f) { _Z80_A = RRC( RM(EA) ); WM( EA,_Z80_A ); } /* RRC A=(XY+o) */ - -OP(xycb,10) { _Z80_B = RL( RM(EA) ); WM( EA,_Z80_B ); } /* RL B=(XY+o) */ -OP(xycb,11) { _Z80_C = RL( RM(EA) ); WM( EA,_Z80_C ); } /* RL C=(XY+o) */ -OP(xycb,12) { _Z80_D = RL( RM(EA) ); WM( EA,_Z80_D ); } /* RL D=(XY+o) */ -OP(xycb,13) { _Z80_E = RL( RM(EA) ); WM( EA,_Z80_E ); } /* RL E=(XY+o) */ -OP(xycb,14) { _Z80_H = RL( RM(EA) ); WM( EA,_Z80_H ); } /* RL H=(XY+o) */ -OP(xycb,15) { _Z80_L = RL( RM(EA) ); WM( EA,_Z80_L ); } /* RL L=(XY+o) */ -OP(xycb,16) { WM( EA,RL( RM(EA) ) ); } /* RL (XY+o) */ -OP(xycb,17) { _Z80_A = RL( RM(EA) ); WM( EA,_Z80_A ); } /* RL A=(XY+o) */ - -OP(xycb,18) { _Z80_B = RR( RM(EA) ); WM( EA,_Z80_B ); } /* RR B=(XY+o) */ -OP(xycb,19) { _Z80_C = RR( RM(EA) ); WM( EA,_Z80_C ); } /* RR C=(XY+o) */ -OP(xycb,1a) { _Z80_D = RR( RM(EA) ); WM( EA,_Z80_D ); } /* RR D=(XY+o) */ -OP(xycb,1b) { _Z80_E = RR( RM(EA) ); WM( EA,_Z80_E ); } /* RR E=(XY+o) */ -OP(xycb,1c) { _Z80_H = RR( RM(EA) ); WM( EA,_Z80_H ); } /* RR H=(XY+o) */ -OP(xycb,1d) { _Z80_L = RR( RM(EA) ); WM( EA,_Z80_L ); } /* RR L=(XY+o) */ -OP(xycb,1e) { WM( EA,RR( RM(EA) ) ); } /* RR (XY+o) */ -OP(xycb,1f) { _Z80_A = RR( RM(EA) ); WM( EA,_Z80_A ); } /* RR A=(XY+o) */ - -OP(xycb,20) { _Z80_B = SLA( RM(EA) ); WM( EA,_Z80_B ); } /* SLA B=(XY+o) */ -OP(xycb,21) { _Z80_C = SLA( RM(EA) ); WM( EA,_Z80_C ); } /* SLA C=(XY+o) */ -OP(xycb,22) { _Z80_D = SLA( RM(EA) ); WM( EA,_Z80_D ); } /* SLA D=(XY+o) */ -OP(xycb,23) { _Z80_E = SLA( RM(EA) ); WM( EA,_Z80_E ); } /* SLA E=(XY+o) */ -OP(xycb,24) { _Z80_H = SLA( RM(EA) ); WM( EA,_Z80_H ); } /* SLA H=(XY+o) */ -OP(xycb,25) { _Z80_L = SLA( RM(EA) ); WM( EA,_Z80_L ); } /* SLA L=(XY+o) */ -OP(xycb,26) { WM( EA,SLA( RM(EA) ) ); } /* SLA (XY+o) */ -OP(xycb,27) { _Z80_A = SLA( RM(EA) ); WM( EA,_Z80_A ); } /* SLA A=(XY+o) */ - -OP(xycb,28) { _Z80_B = SRA( RM(EA) ); WM( EA,_Z80_B ); } /* SRA B=(XY+o) */ -OP(xycb,29) { _Z80_C = SRA( RM(EA) ); WM( EA,_Z80_C ); } /* SRA C=(XY+o) */ -OP(xycb,2a) { _Z80_D = SRA( RM(EA) ); WM( EA,_Z80_D ); } /* SRA D=(XY+o) */ -OP(xycb,2b) { _Z80_E = SRA( RM(EA) ); WM( EA,_Z80_E ); } /* SRA E=(XY+o) */ -OP(xycb,2c) { _Z80_H = SRA( RM(EA) ); WM( EA,_Z80_H ); } /* SRA H=(XY+o) */ -OP(xycb,2d) { _Z80_L = SRA( RM(EA) ); WM( EA,_Z80_L ); } /* SRA L=(XY+o) */ -OP(xycb,2e) { WM( EA,SRA( RM(EA) ) ); } /* SRA (XY+o) */ -OP(xycb,2f) { _Z80_A = SRA( RM(EA) ); WM( EA,_Z80_A ); } /* SRA A=(XY+o) */ - -OP(xycb,30) { _Z80_B = SLL( RM(EA) ); WM( EA,_Z80_B ); } /* SLL B=(XY+o) */ -OP(xycb,31) { _Z80_C = SLL( RM(EA) ); WM( EA,_Z80_C ); } /* SLL C=(XY+o) */ -OP(xycb,32) { _Z80_D = SLL( RM(EA) ); WM( EA,_Z80_D ); } /* SLL D=(XY+o) */ -OP(xycb,33) { _Z80_E = SLL( RM(EA) ); WM( EA,_Z80_E ); } /* SLL E=(XY+o) */ -OP(xycb,34) { _Z80_H = SLL( RM(EA) ); WM( EA,_Z80_H ); } /* SLL H=(XY+o) */ -OP(xycb,35) { _Z80_L = SLL( RM(EA) ); WM( EA,_Z80_L ); } /* SLL L=(XY+o) */ -OP(xycb,36) { WM( EA,SLL( RM(EA) ) ); } /* SLL (XY+o) */ -OP(xycb,37) { _Z80_A = SLL( RM(EA) ); WM( EA,_Z80_A ); } /* SLL A=(XY+o) */ - -OP(xycb,38) { _Z80_B = SRL( RM(EA) ); WM( EA,_Z80_B ); } /* SRL B=(XY+o) */ -OP(xycb,39) { _Z80_C = SRL( RM(EA) ); WM( EA,_Z80_C ); } /* SRL C=(XY+o) */ -OP(xycb,3a) { _Z80_D = SRL( RM(EA) ); WM( EA,_Z80_D ); } /* SRL D=(XY+o) */ -OP(xycb,3b) { _Z80_E = SRL( RM(EA) ); WM( EA,_Z80_E ); } /* SRL E=(XY+o) */ -OP(xycb,3c) { _Z80_H = SRL( RM(EA) ); WM( EA,_Z80_H ); } /* SRL H=(XY+o) */ -OP(xycb,3d) { _Z80_L = SRL( RM(EA) ); WM( EA,_Z80_L ); } /* SRL L=(XY+o) */ -OP(xycb,3e) { WM( EA,SRL( RM(EA) ) ); } /* SRL (XY+o) */ -OP(xycb,3f) { _Z80_A = SRL( RM(EA) ); WM( EA,_Z80_A ); } /* SRL A=(XY+o) */ - -OP(xycb,40) { xycb_46(); } /* BIT 0,B=(XY+o) */ -OP(xycb,41) { xycb_46(); } /* BIT 0,C=(XY+o) */ -OP(xycb,42) { xycb_46(); } /* BIT 0,D=(XY+o) */ -OP(xycb,43) { xycb_46(); } /* BIT 0,E=(XY+o) */ -OP(xycb,44) { xycb_46(); } /* BIT 0,H=(XY+o) */ -OP(xycb,45) { xycb_46(); } /* BIT 0,L=(XY+o) */ -OP(xycb,46) { BIT_XY(0,RM(EA)); } /* BIT 0,(XY+o) */ -OP(xycb,47) { xycb_46(); } /* BIT 0,A=(XY+o) */ - -OP(xycb,48) { xycb_4e(); } /* BIT 1,B=(XY+o) */ -OP(xycb,49) { xycb_4e(); } /* BIT 1,C=(XY+o) */ -OP(xycb,4a) { xycb_4e(); } /* BIT 1,D=(XY+o) */ -OP(xycb,4b) { xycb_4e(); } /* BIT 1,E=(XY+o) */ -OP(xycb,4c) { xycb_4e(); } /* BIT 1,H=(XY+o) */ -OP(xycb,4d) { xycb_4e(); } /* BIT 1,L=(XY+o) */ -OP(xycb,4e) { BIT_XY(1,RM(EA)); } /* BIT 1,(XY+o) */ -OP(xycb,4f) { xycb_4e(); } /* BIT 1,A=(XY+o) */ - -OP(xycb,50) { xycb_56(); } /* BIT 2,B=(XY+o) */ -OP(xycb,51) { xycb_56(); } /* BIT 2,C=(XY+o) */ -OP(xycb,52) { xycb_56(); } /* BIT 2,D=(XY+o) */ -OP(xycb,53) { xycb_56(); } /* BIT 2,E=(XY+o) */ -OP(xycb,54) { xycb_56(); } /* BIT 2,H=(XY+o) */ -OP(xycb,55) { xycb_56(); } /* BIT 2,L=(XY+o) */ -OP(xycb,56) { BIT_XY(2,RM(EA)); } /* BIT 2,(XY+o) */ -OP(xycb,57) { xycb_56(); } /* BIT 2,A=(XY+o) */ - -OP(xycb,58) { xycb_5e(); } /* BIT 3,B=(XY+o) */ -OP(xycb,59) { xycb_5e(); } /* BIT 3,C=(XY+o) */ -OP(xycb,5a) { xycb_5e(); } /* BIT 3,D=(XY+o) */ -OP(xycb,5b) { xycb_5e(); } /* BIT 3,E=(XY+o) */ -OP(xycb,5c) { xycb_5e(); } /* BIT 3,H=(XY+o) */ -OP(xycb,5d) { xycb_5e(); } /* BIT 3,L=(XY+o) */ -OP(xycb,5e) { BIT_XY(3,RM(EA)); } /* BIT 3,(XY+o) */ -OP(xycb,5f) { xycb_5e(); } /* BIT 3,A=(XY+o) */ - -OP(xycb,60) { xycb_66(); } /* BIT 4,B=(XY+o) */ -OP(xycb,61) { xycb_66(); } /* BIT 4,C=(XY+o) */ -OP(xycb,62) { xycb_66(); } /* BIT 4,D=(XY+o) */ -OP(xycb,63) { xycb_66(); } /* BIT 4,E=(XY+o) */ -OP(xycb,64) { xycb_66(); } /* BIT 4,H=(XY+o) */ -OP(xycb,65) { xycb_66(); } /* BIT 4,L=(XY+o) */ -OP(xycb,66) { BIT_XY(4,RM(EA)); } /* BIT 4,(XY+o) */ -OP(xycb,67) { xycb_66(); } /* BIT 4,A=(XY+o) */ - -OP(xycb,68) { xycb_6e(); } /* BIT 5,B=(XY+o) */ -OP(xycb,69) { xycb_6e(); } /* BIT 5,C=(XY+o) */ -OP(xycb,6a) { xycb_6e(); } /* BIT 5,D=(XY+o) */ -OP(xycb,6b) { xycb_6e(); } /* BIT 5,E=(XY+o) */ -OP(xycb,6c) { xycb_6e(); } /* BIT 5,H=(XY+o) */ -OP(xycb,6d) { xycb_6e(); } /* BIT 5,L=(XY+o) */ -OP(xycb,6e) { BIT_XY(5,RM(EA)); } /* BIT 5,(XY+o) */ -OP(xycb,6f) { xycb_6e(); } /* BIT 5,A=(XY+o) */ - -OP(xycb,70) { xycb_76(); } /* BIT 6,B=(XY+o) */ -OP(xycb,71) { xycb_76(); } /* BIT 6,C=(XY+o) */ -OP(xycb,72) { xycb_76(); } /* BIT 6,D=(XY+o) */ -OP(xycb,73) { xycb_76(); } /* BIT 6,E=(XY+o) */ -OP(xycb,74) { xycb_76(); } /* BIT 6,H=(XY+o) */ -OP(xycb,75) { xycb_76(); } /* BIT 6,L=(XY+o) */ -OP(xycb,76) { BIT_XY(6,RM(EA)); } /* BIT 6,(XY+o) */ -OP(xycb,77) { xycb_76(); } /* BIT 6,A=(XY+o) */ - -OP(xycb,78) { xycb_7e(); } /* BIT 7,B=(XY+o) */ -OP(xycb,79) { xycb_7e(); } /* BIT 7,C=(XY+o) */ -OP(xycb,7a) { xycb_7e(); } /* BIT 7,D=(XY+o) */ -OP(xycb,7b) { xycb_7e(); } /* BIT 7,E=(XY+o) */ -OP(xycb,7c) { xycb_7e(); } /* BIT 7,H=(XY+o) */ -OP(xycb,7d) { xycb_7e(); } /* BIT 7,L=(XY+o) */ -OP(xycb,7e) { BIT_XY(7,RM(EA)); } /* BIT 7,(XY+o) */ -OP(xycb,7f) { xycb_7e(); } /* BIT 7,A=(XY+o) */ - -OP(xycb,80) { _Z80_B = RES(0, RM(EA) ); WM( EA,_Z80_B ); } /* RES 0,B=(XY+o) */ -OP(xycb,81) { _Z80_C = RES(0, RM(EA) ); WM( EA,_Z80_C ); } /* RES 0,C=(XY+o) */ -OP(xycb,82) { _Z80_D = RES(0, RM(EA) ); WM( EA,_Z80_D ); } /* RES 0,D=(XY+o) */ -OP(xycb,83) { _Z80_E = RES(0, RM(EA) ); WM( EA,_Z80_E ); } /* RES 0,E=(XY+o) */ -OP(xycb,84) { _Z80_H = RES(0, RM(EA) ); WM( EA,_Z80_H ); } /* RES 0,H=(XY+o) */ -OP(xycb,85) { _Z80_L = RES(0, RM(EA) ); WM( EA,_Z80_L ); } /* RES 0,L=(XY+o) */ -OP(xycb,86) { WM( EA, RES(0,RM(EA)) ); } /* RES 0,(XY+o) */ -OP(xycb,87) { _Z80_A = RES(0, RM(EA) ); WM( EA,_Z80_A ); } /* RES 0,A=(XY+o) */ - -OP(xycb,88) { _Z80_B = RES(1, RM(EA) ); WM( EA,_Z80_B ); } /* RES 1,B=(XY+o) */ -OP(xycb,89) { _Z80_C = RES(1, RM(EA) ); WM( EA,_Z80_C ); } /* RES 1,C=(XY+o) */ -OP(xycb,8a) { _Z80_D = RES(1, RM(EA) ); WM( EA,_Z80_D ); } /* RES 1,D=(XY+o) */ -OP(xycb,8b) { _Z80_E = RES(1, RM(EA) ); WM( EA,_Z80_E ); } /* RES 1,E=(XY+o) */ -OP(xycb,8c) { _Z80_H = RES(1, RM(EA) ); WM( EA,_Z80_H ); } /* RES 1,H=(XY+o) */ -OP(xycb,8d) { _Z80_L = RES(1, RM(EA) ); WM( EA,_Z80_L ); } /* RES 1,L=(XY+o) */ -OP(xycb,8e) { WM( EA, RES(1,RM(EA)) ); } /* RES 1,(XY+o) */ -OP(xycb,8f) { _Z80_A = RES(1, RM(EA) ); WM( EA,_Z80_A ); } /* RES 1,A=(XY+o) */ - -OP(xycb,90) { _Z80_B = RES(2, RM(EA) ); WM( EA,_Z80_B ); } /* RES 2,B=(XY+o) */ -OP(xycb,91) { _Z80_C = RES(2, RM(EA) ); WM( EA,_Z80_C ); } /* RES 2,C=(XY+o) */ -OP(xycb,92) { _Z80_D = RES(2, RM(EA) ); WM( EA,_Z80_D ); } /* RES 2,D=(XY+o) */ -OP(xycb,93) { _Z80_E = RES(2, RM(EA) ); WM( EA,_Z80_E ); } /* RES 2,E=(XY+o) */ -OP(xycb,94) { _Z80_H = RES(2, RM(EA) ); WM( EA,_Z80_H ); } /* RES 2,H=(XY+o) */ -OP(xycb,95) { _Z80_L = RES(2, RM(EA) ); WM( EA,_Z80_L ); } /* RES 2,L=(XY+o) */ -OP(xycb,96) { WM( EA, RES(2,RM(EA)) ); } /* RES 2,(XY+o) */ -OP(xycb,97) { _Z80_A = RES(2, RM(EA) ); WM( EA,_Z80_A ); } /* RES 2,A=(XY+o) */ - -OP(xycb,98) { _Z80_B = RES(3, RM(EA) ); WM( EA,_Z80_B ); } /* RES 3,B=(XY+o) */ -OP(xycb,99) { _Z80_C = RES(3, RM(EA) ); WM( EA,_Z80_C ); } /* RES 3,C=(XY+o) */ -OP(xycb,9a) { _Z80_D = RES(3, RM(EA) ); WM( EA,_Z80_D ); } /* RES 3,D=(XY+o) */ -OP(xycb,9b) { _Z80_E = RES(3, RM(EA) ); WM( EA,_Z80_E ); } /* RES 3,E=(XY+o) */ -OP(xycb,9c) { _Z80_H = RES(3, RM(EA) ); WM( EA,_Z80_H ); } /* RES 3,H=(XY+o) */ -OP(xycb,9d) { _Z80_L = RES(3, RM(EA) ); WM( EA,_Z80_L ); } /* RES 3,L=(XY+o) */ -OP(xycb,9e) { WM( EA, RES(3,RM(EA)) ); } /* RES 3,(XY+o) */ -OP(xycb,9f) { _Z80_A = RES(3, RM(EA) ); WM( EA,_Z80_A ); } /* RES 3,A=(XY+o) */ - -OP(xycb,a0) { _Z80_B = RES(4, RM(EA) ); WM( EA,_Z80_B ); } /* RES 4,B=(XY+o) */ -OP(xycb,a1) { _Z80_C = RES(4, RM(EA) ); WM( EA,_Z80_C ); } /* RES 4,C=(XY+o) */ -OP(xycb,a2) { _Z80_D = RES(4, RM(EA) ); WM( EA,_Z80_D ); } /* RES 4,D=(XY+o) */ -OP(xycb,a3) { _Z80_E = RES(4, RM(EA) ); WM( EA,_Z80_E ); } /* RES 4,E=(XY+o) */ -OP(xycb,a4) { _Z80_H = RES(4, RM(EA) ); WM( EA,_Z80_H ); } /* RES 4,H=(XY+o) */ -OP(xycb,a5) { _Z80_L = RES(4, RM(EA) ); WM( EA,_Z80_L ); } /* RES 4,L=(XY+o) */ -OP(xycb,a6) { WM( EA, RES(4,RM(EA)) ); } /* RES 4,(XY+o) */ -OP(xycb,a7) { _Z80_A = RES(4, RM(EA) ); WM( EA,_Z80_A ); } /* RES 4,A=(XY+o) */ - -OP(xycb,a8) { _Z80_B = RES(5, RM(EA) ); WM( EA,_Z80_B ); } /* RES 5,B=(XY+o) */ -OP(xycb,a9) { _Z80_C = RES(5, RM(EA) ); WM( EA,_Z80_C ); } /* RES 5,C=(XY+o) */ -OP(xycb,aa) { _Z80_D = RES(5, RM(EA) ); WM( EA,_Z80_D ); } /* RES 5,D=(XY+o) */ -OP(xycb,ab) { _Z80_E = RES(5, RM(EA) ); WM( EA,_Z80_E ); } /* RES 5,E=(XY+o) */ -OP(xycb,ac) { _Z80_H = RES(5, RM(EA) ); WM( EA,_Z80_H ); } /* RES 5,H=(XY+o) */ -OP(xycb,ad) { _Z80_L = RES(5, RM(EA) ); WM( EA,_Z80_L ); } /* RES 5,L=(XY+o) */ -OP(xycb,ae) { WM( EA, RES(5,RM(EA)) ); } /* RES 5,(XY+o) */ -OP(xycb,af) { _Z80_A = RES(5, RM(EA) ); WM( EA,_Z80_A ); } /* RES 5,A=(XY+o) */ - -OP(xycb,b0) { _Z80_B = RES(6, RM(EA) ); WM( EA,_Z80_B ); } /* RES 6,B=(XY+o) */ -OP(xycb,b1) { _Z80_C = RES(6, RM(EA) ); WM( EA,_Z80_C ); } /* RES 6,C=(XY+o) */ -OP(xycb,b2) { _Z80_D = RES(6, RM(EA) ); WM( EA,_Z80_D ); } /* RES 6,D=(XY+o) */ -OP(xycb,b3) { _Z80_E = RES(6, RM(EA) ); WM( EA,_Z80_E ); } /* RES 6,E=(XY+o) */ -OP(xycb,b4) { _Z80_H = RES(6, RM(EA) ); WM( EA,_Z80_H ); } /* RES 6,H=(XY+o) */ -OP(xycb,b5) { _Z80_L = RES(6, RM(EA) ); WM( EA,_Z80_L ); } /* RES 6,L=(XY+o) */ -OP(xycb,b6) { WM( EA, RES(6,RM(EA)) ); } /* RES 6,(XY+o) */ -OP(xycb,b7) { _Z80_A = RES(6, RM(EA) ); WM( EA,_Z80_A ); } /* RES 6,A=(XY+o) */ - -OP(xycb,b8) { _Z80_B = RES(7, RM(EA) ); WM( EA,_Z80_B ); } /* RES 7,B=(XY+o) */ -OP(xycb,b9) { _Z80_C = RES(7, RM(EA) ); WM( EA,_Z80_C ); } /* RES 7,C=(XY+o) */ -OP(xycb,ba) { _Z80_D = RES(7, RM(EA) ); WM( EA,_Z80_D ); } /* RES 7,D=(XY+o) */ -OP(xycb,bb) { _Z80_E = RES(7, RM(EA) ); WM( EA,_Z80_E ); } /* RES 7,E=(XY+o) */ -OP(xycb,bc) { _Z80_H = RES(7, RM(EA) ); WM( EA,_Z80_H ); } /* RES 7,H=(XY+o) */ -OP(xycb,bd) { _Z80_L = RES(7, RM(EA) ); WM( EA,_Z80_L ); } /* RES 7,L=(XY+o) */ -OP(xycb,be) { WM( EA, RES(7,RM(EA)) ); } /* RES 7,(XY+o) */ -OP(xycb,bf) { _Z80_A = RES(7, RM(EA) ); WM( EA,_Z80_A ); } /* RES 7,A=(XY+o) */ - -OP(xycb,c0) { _Z80_B = SET(0, RM(EA) ); WM( EA,_Z80_B ); } /* SET 0,B=(XY+o) */ -OP(xycb,c1) { _Z80_C = SET(0, RM(EA) ); WM( EA,_Z80_C ); } /* SET 0,C=(XY+o) */ -OP(xycb,c2) { _Z80_D = SET(0, RM(EA) ); WM( EA,_Z80_D ); } /* SET 0,D=(XY+o) */ -OP(xycb,c3) { _Z80_E = SET(0, RM(EA) ); WM( EA,_Z80_E ); } /* SET 0,E=(XY+o) */ -OP(xycb,c4) { _Z80_H = SET(0, RM(EA) ); WM( EA,_Z80_H ); } /* SET 0,H=(XY+o) */ -OP(xycb,c5) { _Z80_L = SET(0, RM(EA) ); WM( EA,_Z80_L ); } /* SET 0,L=(XY+o) */ -OP(xycb,c6) { WM( EA, SET(0,RM(EA)) ); } /* SET 0,(XY+o) */ -OP(xycb,c7) { _Z80_A = SET(0, RM(EA) ); WM( EA,_Z80_A ); } /* SET 0,A=(XY+o) */ - -OP(xycb,c8) { _Z80_B = SET(1, RM(EA) ); WM( EA,_Z80_B ); } /* SET 1,B=(XY+o) */ -OP(xycb,c9) { _Z80_C = SET(1, RM(EA) ); WM( EA,_Z80_C ); } /* SET 1,C=(XY+o) */ -OP(xycb,ca) { _Z80_D = SET(1, RM(EA) ); WM( EA,_Z80_D ); } /* SET 1,D=(XY+o) */ -OP(xycb,cb) { _Z80_E = SET(1, RM(EA) ); WM( EA,_Z80_E ); } /* SET 1,E=(XY+o) */ -OP(xycb,cc) { _Z80_H = SET(1, RM(EA) ); WM( EA,_Z80_H ); } /* SET 1,H=(XY+o) */ -OP(xycb,cd) { _Z80_L = SET(1, RM(EA) ); WM( EA,_Z80_L ); } /* SET 1,L=(XY+o) */ -OP(xycb,ce) { WM( EA, SET(1,RM(EA)) ); } /* SET 1,(XY+o) */ -OP(xycb,cf) { _Z80_A = SET(1, RM(EA) ); WM( EA,_Z80_A ); } /* SET 1,A=(XY+o) */ - -OP(xycb,d0) { _Z80_B = SET(2, RM(EA) ); WM( EA,_Z80_B ); } /* SET 2,B=(XY+o) */ -OP(xycb,d1) { _Z80_C = SET(2, RM(EA) ); WM( EA,_Z80_C ); } /* SET 2,C=(XY+o) */ -OP(xycb,d2) { _Z80_D = SET(2, RM(EA) ); WM( EA,_Z80_D ); } /* SET 2,D=(XY+o) */ -OP(xycb,d3) { _Z80_E = SET(2, RM(EA) ); WM( EA,_Z80_E ); } /* SET 2,E=(XY+o) */ -OP(xycb,d4) { _Z80_H = SET(2, RM(EA) ); WM( EA,_Z80_H ); } /* SET 2,H=(XY+o) */ -OP(xycb,d5) { _Z80_L = SET(2, RM(EA) ); WM( EA,_Z80_L ); } /* SET 2,L=(XY+o) */ -OP(xycb,d6) { WM( EA, SET(2,RM(EA)) ); } /* SET 2,(XY+o) */ -OP(xycb,d7) { _Z80_A = SET(2, RM(EA) ); WM( EA,_Z80_A ); } /* SET 2,A=(XY+o) */ - -OP(xycb,d8) { _Z80_B = SET(3, RM(EA) ); WM( EA,_Z80_B ); } /* SET 3,B=(XY+o) */ -OP(xycb,d9) { _Z80_C = SET(3, RM(EA) ); WM( EA,_Z80_C ); } /* SET 3,C=(XY+o) */ -OP(xycb,da) { _Z80_D = SET(3, RM(EA) ); WM( EA,_Z80_D ); } /* SET 3,D=(XY+o) */ -OP(xycb,db) { _Z80_E = SET(3, RM(EA) ); WM( EA,_Z80_E ); } /* SET 3,E=(XY+o) */ -OP(xycb,dc) { _Z80_H = SET(3, RM(EA) ); WM( EA,_Z80_H ); } /* SET 3,H=(XY+o) */ -OP(xycb,dd) { _Z80_L = SET(3, RM(EA) ); WM( EA,_Z80_L ); } /* SET 3,L=(XY+o) */ -OP(xycb,de) { WM( EA, SET(3,RM(EA)) ); } /* SET 3,(XY+o) */ -OP(xycb,df) { _Z80_A = SET(3, RM(EA) ); WM( EA,_Z80_A ); } /* SET 3,A=(XY+o) */ - -OP(xycb,e0) { _Z80_B = SET(4, RM(EA) ); WM( EA,_Z80_B ); } /* SET 4,B=(XY+o) */ -OP(xycb,e1) { _Z80_C = SET(4, RM(EA) ); WM( EA,_Z80_C ); } /* SET 4,C=(XY+o) */ -OP(xycb,e2) { _Z80_D = SET(4, RM(EA) ); WM( EA,_Z80_D ); } /* SET 4,D=(XY+o) */ -OP(xycb,e3) { _Z80_E = SET(4, RM(EA) ); WM( EA,_Z80_E ); } /* SET 4,E=(XY+o) */ -OP(xycb,e4) { _Z80_H = SET(4, RM(EA) ); WM( EA,_Z80_H ); } /* SET 4,H=(XY+o) */ -OP(xycb,e5) { _Z80_L = SET(4, RM(EA) ); WM( EA,_Z80_L ); } /* SET 4,L=(XY+o) */ -OP(xycb,e6) { WM( EA, SET(4,RM(EA)) ); } /* SET 4,(XY+o) */ -OP(xycb,e7) { _Z80_A = SET(4, RM(EA) ); WM( EA,_Z80_A ); } /* SET 4,A=(XY+o) */ - -OP(xycb,e8) { _Z80_B = SET(5, RM(EA) ); WM( EA,_Z80_B ); } /* SET 5,B=(XY+o) */ -OP(xycb,e9) { _Z80_C = SET(5, RM(EA) ); WM( EA,_Z80_C ); } /* SET 5,C=(XY+o) */ -OP(xycb,ea) { _Z80_D = SET(5, RM(EA) ); WM( EA,_Z80_D ); } /* SET 5,D=(XY+o) */ -OP(xycb,eb) { _Z80_E = SET(5, RM(EA) ); WM( EA,_Z80_E ); } /* SET 5,E=(XY+o) */ -OP(xycb,ec) { _Z80_H = SET(5, RM(EA) ); WM( EA,_Z80_H ); } /* SET 5,H=(XY+o) */ -OP(xycb,ed) { _Z80_L = SET(5, RM(EA) ); WM( EA,_Z80_L ); } /* SET 5,L=(XY+o) */ -OP(xycb,ee) { WM( EA, SET(5,RM(EA)) ); } /* SET 5,(XY+o) */ -OP(xycb,ef) { _Z80_A = SET(5, RM(EA) ); WM( EA,_Z80_A ); } /* SET 5,A=(XY+o) */ - -OP(xycb,f0) { _Z80_B = SET(6, RM(EA) ); WM( EA,_Z80_B ); } /* SET 6,B=(XY+o) */ -OP(xycb,f1) { _Z80_C = SET(6, RM(EA) ); WM( EA,_Z80_C ); } /* SET 6,C=(XY+o) */ -OP(xycb,f2) { _Z80_D = SET(6, RM(EA) ); WM( EA,_Z80_D ); } /* SET 6,D=(XY+o) */ -OP(xycb,f3) { _Z80_E = SET(6, RM(EA) ); WM( EA,_Z80_E ); } /* SET 6,E=(XY+o) */ -OP(xycb,f4) { _Z80_H = SET(6, RM(EA) ); WM( EA,_Z80_H ); } /* SET 6,H=(XY+o) */ -OP(xycb,f5) { _Z80_L = SET(6, RM(EA) ); WM( EA,_Z80_L ); } /* SET 6,L=(XY+o) */ -OP(xycb,f6) { WM( EA, SET(6,RM(EA)) ); } /* SET 6,(XY+o) */ -OP(xycb,f7) { _Z80_A = SET(6, RM(EA) ); WM( EA,_Z80_A ); } /* SET 6,A=(XY+o) */ - -OP(xycb,f8) { _Z80_B = SET(7, RM(EA) ); WM( EA,_Z80_B ); } /* SET 7,B=(XY+o) */ -OP(xycb,f9) { _Z80_C = SET(7, RM(EA) ); WM( EA,_Z80_C ); } /* SET 7,C=(XY+o) */ -OP(xycb,fa) { _Z80_D = SET(7, RM(EA) ); WM( EA,_Z80_D ); } /* SET 7,D=(XY+o) */ -OP(xycb,fb) { _Z80_E = SET(7, RM(EA) ); WM( EA,_Z80_E ); } /* SET 7,E=(XY+o) */ -OP(xycb,fc) { _Z80_H = SET(7, RM(EA) ); WM( EA,_Z80_H ); } /* SET 7,H=(XY+o) */ -OP(xycb,fd) { _Z80_L = SET(7, RM(EA) ); WM( EA,_Z80_L ); } /* SET 7,L=(XY+o) */ -OP(xycb,fe) { WM( EA, SET(7,RM(EA)) ); } /* SET 7,(XY+o) */ -OP(xycb,ff) { _Z80_A = SET(7, RM(EA) ); WM( EA,_Z80_A ); } /* SET 7,A=(XY+o) */ - -OP(illegal,1) { - logerror("Z80 #%d ill. opcode $%02x $%02x\n", - cpu_getactivecpu(), cpu_readop((_PCD-1)&0xffff), cpu_readop(_PCD)); -} - -/********************************************************** - * IX register related opcodes (DD prefix) - **********************************************************/ -OP(dd,00) { illegal_1(); op_00(); } /* DB DD */ -OP(dd,01) { illegal_1(); op_01(); } /* DB DD */ -OP(dd,02) { illegal_1(); op_02(); } /* DB DD */ -OP(dd,03) { illegal_1(); op_03(); } /* DB DD */ -OP(dd,04) { illegal_1(); op_04(); } /* DB DD */ -OP(dd,05) { illegal_1(); op_05(); } /* DB DD */ -OP(dd,06) { illegal_1(); op_06(); } /* DB DD */ -OP(dd,07) { illegal_1(); op_07(); } /* DB DD */ - -OP(dd,08) { illegal_1(); op_08(); } /* DB DD */ -OP(dd,09) { _Z80_R++; ADD16(IX,BC); } /* ADD IX,BC */ -OP(dd,0a) { illegal_1(); op_0a(); } /* DB DD */ -OP(dd,0b) { illegal_1(); op_0b(); } /* DB DD */ -OP(dd,0c) { illegal_1(); op_0c(); } /* DB DD */ -OP(dd,0d) { illegal_1(); op_0d(); } /* DB DD */ -OP(dd,0e) { illegal_1(); op_0e(); } /* DB DD */ -OP(dd,0f) { illegal_1(); op_0f(); } /* DB DD */ - -OP(dd,10) { illegal_1(); op_10(); } /* DB DD */ -OP(dd,11) { illegal_1(); op_11(); } /* DB DD */ -OP(dd,12) { illegal_1(); op_12(); } /* DB DD */ -OP(dd,13) { illegal_1(); op_13(); } /* DB DD */ -OP(dd,14) { illegal_1(); op_14(); } /* DB DD */ -OP(dd,15) { illegal_1(); op_15(); } /* DB DD */ -OP(dd,16) { illegal_1(); op_16(); } /* DB DD */ -OP(dd,17) { illegal_1(); op_17(); } /* DB DD */ - -OP(dd,18) { illegal_1(); op_18(); } /* DB DD */ -OP(dd,19) { _Z80_R++; ADD16(IX,DE); } /* ADD IX,DE */ -OP(dd,1a) { illegal_1(); op_1a(); } /* DB DD */ -OP(dd,1b) { illegal_1(); op_1b(); } /* DB DD */ -OP(dd,1c) { illegal_1(); op_1c(); } /* DB DD */ -OP(dd,1d) { illegal_1(); op_1d(); } /* DB DD */ -OP(dd,1e) { illegal_1(); op_1e(); } /* DB DD */ -OP(dd,1f) { illegal_1(); op_1f(); } /* DB DD */ - -OP(dd,20) { illegal_1(); op_20(); } /* DB DD */ -OP(dd,21) { _Z80_R++; _IX = ARG16(); } /* LD IX,w */ -OP(dd,22) { _Z80_R++; EA = ARG16(); WM16( EA, &Z80.IX ); } /* LD (w),IX */ -OP(dd,23) { _Z80_R++; _IX++; } /* INC IX */ -OP(dd,24) { _Z80_R++; _HX = INC(_HX); } /* INC HX */ -OP(dd,25) { _Z80_R++; _HX = DEC(_HX); } /* DEC HX */ -OP(dd,26) { _Z80_R++; _HX = ARG(); } /* LD HX,n */ -OP(dd,27) { illegal_1(); op_27(); } /* DB DD */ - -OP(dd,28) { illegal_1(); op_28(); } /* DB DD */ -OP(dd,29) { _Z80_R++; ADD16(IX,IX); } /* ADD IX,IX */ -OP(dd,2a) { _Z80_R++; EA = ARG16(); RM16( EA, &Z80.IX ); } /* LD IX,(w) */ -OP(dd,2b) { _Z80_R++; _IX--; } /* DEC IX */ -OP(dd,2c) { _Z80_R++; _LX = INC(_LX); } /* INC LX */ -OP(dd,2d) { _Z80_R++; _LX = DEC(_LX); } /* DEC LX */ -OP(dd,2e) { _Z80_R++; _LX = ARG(); } /* LD LX,n */ -OP(dd,2f) { illegal_1(); op_2f(); } /* DB DD */ - -OP(dd,30) { illegal_1(); op_30(); } /* DB DD */ -OP(dd,31) { illegal_1(); op_31(); } /* DB DD */ -OP(dd,32) { illegal_1(); op_32(); } /* DB DD */ -OP(dd,33) { illegal_1(); op_33(); } /* DB DD */ -OP(dd,34) { _Z80_R++; EAX; WM( EA, INC(RM(EA)) ); } /* INC (IX+o) */ -OP(dd,35) { _Z80_R++; EAX; WM( EA, DEC(RM(EA)) ); } /* DEC (IX+o) */ -OP(dd,36) { _Z80_R++; EAX; WM( EA, ARG() ); } /* LD (IX+o),n */ -OP(dd,37) { illegal_1(); op_37(); } /* DB DD */ - -OP(dd,38) { illegal_1(); op_38(); } /* DB DD */ -OP(dd,39) { _Z80_R++; ADD16(IX,SP); } /* ADD IX,SP */ -OP(dd,3a) { illegal_1(); op_3a(); } /* DB DD */ -OP(dd,3b) { illegal_1(); op_3b(); } /* DB DD */ -OP(dd,3c) { illegal_1(); op_3c(); } /* DB DD */ -OP(dd,3d) { illegal_1(); op_3d(); } /* DB DD */ -OP(dd,3e) { illegal_1(); op_3e(); } /* DB DD */ -OP(dd,3f) { illegal_1(); op_3f(); } /* DB DD */ - -OP(dd,40) { illegal_1(); op_40(); } /* DB DD */ -OP(dd,41) { illegal_1(); op_41(); } /* DB DD */ -OP(dd,42) { illegal_1(); op_42(); } /* DB DD */ -OP(dd,43) { illegal_1(); op_43(); } /* DB DD */ -OP(dd,44) { _Z80_R++; _Z80_B = _HX; } /* LD B,HX */ -OP(dd,45) { _Z80_R++; _Z80_B = _LX; } /* LD B,LX */ -OP(dd,46) { _Z80_R++; EAX; _Z80_B = RM(EA); } /* LD B,(IX+o) */ -OP(dd,47) { illegal_1(); op_47(); } /* DB DD */ - -OP(dd,48) { illegal_1(); op_48(); } /* DB DD */ -OP(dd,49) { illegal_1(); op_49(); } /* DB DD */ -OP(dd,4a) { illegal_1(); op_4a(); } /* DB DD */ -OP(dd,4b) { illegal_1(); op_4b(); } /* DB DD */ -OP(dd,4c) { _Z80_R++; _Z80_C = _HX; } /* LD C,HX */ -OP(dd,4d) { _Z80_R++; _Z80_C = _LX; } /* LD C,LX */ -OP(dd,4e) { _Z80_R++; EAX; _Z80_C = RM(EA); } /* LD C,(IX+o) */ -OP(dd,4f) { illegal_1(); op_4f(); } /* DB DD */ - -OP(dd,50) { illegal_1(); op_50(); } /* DB DD */ -OP(dd,51) { illegal_1(); op_51(); } /* DB DD */ -OP(dd,52) { illegal_1(); op_52(); } /* DB DD */ -OP(dd,53) { illegal_1(); op_53(); } /* DB DD */ -OP(dd,54) { _Z80_R++; _Z80_D = _HX; } /* LD D,HX */ -OP(dd,55) { _Z80_R++; _Z80_D = _LX; } /* LD D,LX */ -OP(dd,56) { _Z80_R++; EAX; _Z80_D = RM(EA); } /* LD D,(IX+o) */ -OP(dd,57) { illegal_1(); op_57(); } /* DB DD */ - -OP(dd,58) { illegal_1(); op_58(); } /* DB DD */ -OP(dd,59) { illegal_1(); op_59(); } /* DB DD */ -OP(dd,5a) { illegal_1(); op_5a(); } /* DB DD */ -OP(dd,5b) { illegal_1(); op_5b(); } /* DB DD */ -OP(dd,5c) { _Z80_R++; _Z80_E = _HX; } /* LD E,HX */ -OP(dd,5d) { _Z80_R++; _Z80_E = _LX; } /* LD E,LX */ -OP(dd,5e) { _Z80_R++; EAX; _Z80_E = RM(EA); } /* LD E,(IX+o) */ -OP(dd,5f) { illegal_1(); op_5f(); } /* DB DD */ - -OP(dd,60) { _Z80_R++; _HX = _Z80_B; } /* LD HX,B */ -OP(dd,61) { _Z80_R++; _HX = _Z80_C; } /* LD HX,C */ -OP(dd,62) { _Z80_R++; _HX = _Z80_D; } /* LD HX,D */ -OP(dd,63) { _Z80_R++; _HX = _Z80_E; } /* LD HX,E */ -OP(dd,64) { } /* LD HX,HX */ -OP(dd,65) { _Z80_R++; _HX = _LX; } /* LD HX,LX */ -OP(dd,66) { _Z80_R++; EAX; _Z80_H = RM(EA); } /* LD H,(IX+o) */ -OP(dd,67) { _Z80_R++; _HX = _Z80_A; } /* LD HX,A */ - -OP(dd,68) { _Z80_R++; _LX = _Z80_B; } /* LD LX,B */ -OP(dd,69) { _Z80_R++; _LX = _Z80_C; } /* LD LX,C */ -OP(dd,6a) { _Z80_R++; _LX = _Z80_D; } /* LD LX,D */ -OP(dd,6b) { _Z80_R++; _LX = _Z80_E; } /* LD LX,E */ -OP(dd,6c) { _Z80_R++; _LX = _HX; } /* LD LX,HX */ -OP(dd,6d) { } /* LD LX,LX */ -OP(dd,6e) { _Z80_R++; EAX; _Z80_L = RM(EA); } /* LD L,(IX+o) */ -OP(dd,6f) { _Z80_R++; _LX = _Z80_A; } /* LD LX,A */ - -OP(dd,70) { _Z80_R++; EAX; WM( EA, _Z80_B ); } /* LD (IX+o),B */ -OP(dd,71) { _Z80_R++; EAX; WM( EA, _Z80_C ); } /* LD (IX+o),C */ -OP(dd,72) { _Z80_R++; EAX; WM( EA, _Z80_D ); } /* LD (IX+o),D */ -OP(dd,73) { _Z80_R++; EAX; WM( EA, _Z80_E ); } /* LD (IX+o),E */ -OP(dd,74) { _Z80_R++; EAX; WM( EA, _Z80_H ); } /* LD (IX+o),H */ -OP(dd,75) { _Z80_R++; EAX; WM( EA, _Z80_L ); } /* LD (IX+o),L */ -OP(dd,76) { illegal_1(); op_76(); } /* DB DD */ -OP(dd,77) { _Z80_R++; EAX; WM( EA, _Z80_A ); } /* LD (IX+o),A */ - -OP(dd,78) { illegal_1(); op_78(); } /* DB DD */ -OP(dd,79) { illegal_1(); op_79(); } /* DB DD */ -OP(dd,7a) { illegal_1(); op_7a(); } /* DB DD */ -OP(dd,7b) { illegal_1(); op_7b(); } /* DB DD */ -OP(dd,7c) { _Z80_R++; _Z80_A = _HX; } /* LD A,HX */ -OP(dd,7d) { _Z80_R++; _Z80_A = _LX; } /* LD A,LX */ -OP(dd,7e) { _Z80_R++; EAX; _Z80_A = RM(EA); } /* LD A,(IX+o) */ -OP(dd,7f) { illegal_1(); op_7f(); } /* DB DD */ - -OP(dd,80) { illegal_1(); op_80(); } /* DB DD */ -OP(dd,81) { illegal_1(); op_81(); } /* DB DD */ -OP(dd,82) { illegal_1(); op_82(); } /* DB DD */ -OP(dd,83) { illegal_1(); op_83(); } /* DB DD */ -OP(dd,84) { _Z80_R++; ADD(_HX); } /* ADD A,HX */ -OP(dd,85) { _Z80_R++; ADD(_LX); } /* ADD A,LX */ -OP(dd,86) { _Z80_R++; EAX; ADD(RM(EA)); } /* ADD A,(IX+o) */ -OP(dd,87) { illegal_1(); op_87(); } /* DB DD */ - -OP(dd,88) { illegal_1(); op_88(); } /* DB DD */ -OP(dd,89) { illegal_1(); op_89(); } /* DB DD */ -OP(dd,8a) { illegal_1(); op_8a(); } /* DB DD */ -OP(dd,8b) { illegal_1(); op_8b(); } /* DB DD */ -OP(dd,8c) { _Z80_R++; ADC(_HX); } /* ADC A,HX */ -OP(dd,8d) { _Z80_R++; ADC(_LX); } /* ADC A,LX */ -OP(dd,8e) { _Z80_R++; EAX; ADC(RM(EA)); } /* ADC A,(IX+o) */ -OP(dd,8f) { illegal_1(); op_8f(); } /* DB DD */ - -OP(dd,90) { illegal_1(); op_90(); } /* DB DD */ -OP(dd,91) { illegal_1(); op_91(); } /* DB DD */ -OP(dd,92) { illegal_1(); op_92(); } /* DB DD */ -OP(dd,93) { illegal_1(); op_93(); } /* DB DD */ -OP(dd,94) { _Z80_R++; SUB(_HX); } /* SUB HX */ -OP(dd,95) { _Z80_R++; SUB(_LX); } /* SUB LX */ -OP(dd,96) { _Z80_R++; EAX; SUB(RM(EA)); } /* SUB (IX+o) */ -OP(dd,97) { illegal_1(); op_97(); } /* DB DD */ - -OP(dd,98) { illegal_1(); op_98(); } /* DB DD */ -OP(dd,99) { illegal_1(); op_99(); } /* DB DD */ -OP(dd,9a) { illegal_1(); op_9a(); } /* DB DD */ -OP(dd,9b) { illegal_1(); op_9b(); } /* DB DD */ -OP(dd,9c) { _Z80_R++; SBC(_HX); } /* SBC A,HX */ -OP(dd,9d) { _Z80_R++; SBC(_LX); } /* SBC A,LX */ -OP(dd,9e) { _Z80_R++; EAX; SBC(RM(EA)); } /* SBC A,(IX+o) */ -OP(dd,9f) { illegal_1(); op_9f(); } /* DB DD */ - -OP(dd,a0) { illegal_1(); op_a0(); } /* DB DD */ -OP(dd,a1) { illegal_1(); op_a1(); } /* DB DD */ -OP(dd,a2) { illegal_1(); op_a2(); } /* DB DD */ -OP(dd,a3) { illegal_1(); op_a3(); } /* DB DD */ -OP(dd,a4) { _Z80_R++; AND(_HX); } /* AND HX */ -OP(dd,a5) { _Z80_R++; AND(_LX); } /* AND LX */ -OP(dd,a6) { _Z80_R++; EAX; AND(RM(EA)); } /* AND (IX+o) */ -OP(dd,a7) { illegal_1(); op_a7(); } /* DB DD */ - -OP(dd,a8) { illegal_1(); op_a8(); } /* DB DD */ -OP(dd,a9) { illegal_1(); op_a9(); } /* DB DD */ -OP(dd,aa) { illegal_1(); op_aa(); } /* DB DD */ -OP(dd,ab) { illegal_1(); op_ab(); } /* DB DD */ -OP(dd,ac) { _Z80_R++; XOR(_HX); } /* XOR HX */ -OP(dd,ad) { _Z80_R++; XOR(_LX); } /* XOR LX */ -OP(dd,ae) { _Z80_R++; EAX; XOR(RM(EA)); } /* XOR (IX+o) */ -OP(dd,af) { illegal_1(); op_af(); } /* DB DD */ - -OP(dd,b0) { illegal_1(); op_b0(); } /* DB DD */ -OP(dd,b1) { illegal_1(); op_b1(); } /* DB DD */ -OP(dd,b2) { illegal_1(); op_b2(); } /* DB DD */ -OP(dd,b3) { illegal_1(); op_b3(); } /* DB DD */ -OP(dd,b4) { _Z80_R++; OR(_HX); } /* OR HX */ -OP(dd,b5) { _Z80_R++; OR(_LX); } /* OR LX */ -OP(dd,b6) { _Z80_R++; EAX; OR(RM(EA)); } /* OR (IX+o) */ -OP(dd,b7) { illegal_1(); op_b7(); } /* DB DD */ - -OP(dd,b8) { illegal_1(); op_b8(); } /* DB DD */ -OP(dd,b9) { illegal_1(); op_b9(); } /* DB DD */ -OP(dd,ba) { illegal_1(); op_ba(); } /* DB DD */ -OP(dd,bb) { illegal_1(); op_bb(); } /* DB DD */ -OP(dd,bc) { _Z80_R++; CP(_HX); } /* CP HX */ -OP(dd,bd) { _Z80_R++; CP(_LX); } /* CP LX */ -OP(dd,be) { _Z80_R++; EAX; CP(RM(EA)); } /* CP (IX+o) */ -OP(dd,bf) { illegal_1(); op_bf(); } /* DB DD */ - -OP(dd,c0) { illegal_1(); op_c0(); } /* DB DD */ -OP(dd,c1) { illegal_1(); op_c1(); } /* DB DD */ -OP(dd,c2) { illegal_1(); op_c2(); } /* DB DD */ -OP(dd,c3) { illegal_1(); op_c3(); } /* DB DD */ -OP(dd,c4) { illegal_1(); op_c4(); } /* DB DD */ -OP(dd,c5) { illegal_1(); op_c5(); } /* DB DD */ -OP(dd,c6) { illegal_1(); op_c6(); } /* DB DD */ -OP(dd,c7) { illegal_1(); op_c7(); } /* DB DD */ - -OP(dd,c8) { illegal_1(); op_c8(); } /* DB DD */ -OP(dd,c9) { illegal_1(); op_c9(); } /* DB DD */ -OP(dd,ca) { illegal_1(); op_ca(); } /* DB DD */ -OP(dd,cb) { _Z80_R++; EAX; EXEC(xycb,ARG()); } /* ** DD CB xx */ -OP(dd,cc) { illegal_1(); op_cc(); } /* DB DD */ -OP(dd,cd) { illegal_1(); op_cd(); } /* DB DD */ -OP(dd,ce) { illegal_1(); op_ce(); } /* DB DD */ -OP(dd,cf) { illegal_1(); op_cf(); } /* DB DD */ - -OP(dd,d0) { illegal_1(); op_d0(); } /* DB DD */ -OP(dd,d1) { illegal_1(); op_d1(); } /* DB DD */ -OP(dd,d2) { illegal_1(); op_d2(); } /* DB DD */ -OP(dd,d3) { illegal_1(); op_d3(); } /* DB DD */ -OP(dd,d4) { illegal_1(); op_d4(); } /* DB DD */ -OP(dd,d5) { illegal_1(); op_d5(); } /* DB DD */ -OP(dd,d6) { illegal_1(); op_d6(); } /* DB DD */ -OP(dd,d7) { illegal_1(); op_d7(); } /* DB DD */ - -OP(dd,d8) { illegal_1(); op_d8(); } /* DB DD */ -OP(dd,d9) { illegal_1(); op_d9(); } /* DB DD */ -OP(dd,da) { illegal_1(); op_da(); } /* DB DD */ -OP(dd,db) { illegal_1(); op_db(); } /* DB DD */ -OP(dd,dc) { illegal_1(); op_dc(); } /* DB DD */ -OP(dd,dd) { illegal_1(); op_dd(); } /* DB DD */ -OP(dd,de) { illegal_1(); op_de(); } /* DB DD */ -OP(dd,df) { illegal_1(); op_df(); } /* DB DD */ - -OP(dd,e0) { illegal_1(); op_e0(); } /* DB DD */ -OP(dd,e1) { _Z80_R++; POP(IX); } /* POP IX */ -OP(dd,e2) { illegal_1(); op_e2(); } /* DB DD */ -OP(dd,e3) { _Z80_R++; EXSP(IX); } /* EX (SP),IX */ -OP(dd,e4) { illegal_1(); op_e4(); } /* DB DD */ -OP(dd,e5) { _Z80_R++; PUSH( IX ); } /* PUSH IX */ -OP(dd,e6) { illegal_1(); op_e6(); } /* DB DD */ -OP(dd,e7) { illegal_1(); op_e7(); } /* DB DD */ - -OP(dd,e8) { illegal_1(); op_e8(); } /* DB DD */ -OP(dd,e9) { _Z80_R++; _PC = _IX; change_pc16(_PCD); } /* JP (IX) */ -OP(dd,ea) { illegal_1(); op_ea(); } /* DB DD */ -OP(dd,eb) { illegal_1(); op_eb(); } /* DB DD */ -OP(dd,ec) { illegal_1(); op_ec(); } /* DB DD */ -OP(dd,ed) { illegal_1(); op_ed(); } /* DB DD */ -OP(dd,ee) { illegal_1(); op_ee(); } /* DB DD */ -OP(dd,ef) { illegal_1(); op_ef(); } /* DB DD */ - -OP(dd,f0) { illegal_1(); op_f0(); } /* DB DD */ -OP(dd,f1) { illegal_1(); op_f1(); } /* DB DD */ -OP(dd,f2) { illegal_1(); op_f2(); } /* DB DD */ -OP(dd,f3) { illegal_1(); op_f3(); } /* DB DD */ -OP(dd,f4) { illegal_1(); op_f4(); } /* DB DD */ -OP(dd,f5) { illegal_1(); op_f5(); } /* DB DD */ -OP(dd,f6) { illegal_1(); op_f6(); } /* DB DD */ -OP(dd,f7) { illegal_1(); op_f7(); } /* DB DD */ - -OP(dd,f8) { illegal_1(); op_f8(); } /* DB DD */ -OP(dd,f9) { _Z80_R++; _SP = _IX; } /* LD SP,IX */ -OP(dd,fa) { illegal_1(); op_fa(); } /* DB DD */ -OP(dd,fb) { illegal_1(); op_fb(); } /* DB DD */ -OP(dd,fc) { illegal_1(); op_fc(); } /* DB DD */ -OP(dd,fd) { illegal_1(); op_fd(); } /* DB DD */ -OP(dd,fe) { illegal_1(); op_fe(); } /* DB DD */ -OP(dd,ff) { illegal_1(); op_ff(); } /* DB DD */ - -/********************************************************** - * IY register related opcodes (FD prefix) - **********************************************************/ -OP(fd,00) { illegal_1(); op_00(); } /* DB FD */ -OP(fd,01) { illegal_1(); op_01(); } /* DB FD */ -OP(fd,02) { illegal_1(); op_02(); } /* DB FD */ -OP(fd,03) { illegal_1(); op_03(); } /* DB FD */ -OP(fd,04) { illegal_1(); op_04(); } /* DB FD */ -OP(fd,05) { illegal_1(); op_05(); } /* DB FD */ -OP(fd,06) { illegal_1(); op_06(); } /* DB FD */ -OP(fd,07) { illegal_1(); op_07(); } /* DB FD */ - -OP(fd,08) { illegal_1(); op_08(); } /* DB FD */ -OP(fd,09) { _Z80_R++; ADD16(IY,BC); } /* ADD IY,BC */ -OP(fd,0a) { illegal_1(); op_0a(); } /* DB FD */ -OP(fd,0b) { illegal_1(); op_0b(); } /* DB FD */ -OP(fd,0c) { illegal_1(); op_0c(); } /* DB FD */ -OP(fd,0d) { illegal_1(); op_0d(); } /* DB FD */ -OP(fd,0e) { illegal_1(); op_0e(); } /* DB FD */ -OP(fd,0f) { illegal_1(); op_0f(); } /* DB FD */ - -OP(fd,10) { illegal_1(); op_10(); } /* DB FD */ -OP(fd,11) { illegal_1(); op_11(); } /* DB FD */ -OP(fd,12) { illegal_1(); op_12(); } /* DB FD */ -OP(fd,13) { illegal_1(); op_13(); } /* DB FD */ -OP(fd,14) { illegal_1(); op_14(); } /* DB FD */ -OP(fd,15) { illegal_1(); op_15(); } /* DB FD */ -OP(fd,16) { illegal_1(); op_16(); } /* DB FD */ -OP(fd,17) { illegal_1(); op_17(); } /* DB FD */ - -OP(fd,18) { illegal_1(); op_18(); } /* DB FD */ -OP(fd,19) { _Z80_R++; ADD16(IY,DE); } /* ADD IY,DE */ -OP(fd,1a) { illegal_1(); op_1a(); } /* DB FD */ -OP(fd,1b) { illegal_1(); op_1b(); } /* DB FD */ -OP(fd,1c) { illegal_1(); op_1c(); } /* DB FD */ -OP(fd,1d) { illegal_1(); op_1d(); } /* DB FD */ -OP(fd,1e) { illegal_1(); op_1e(); } /* DB FD */ -OP(fd,1f) { illegal_1(); op_1f(); } /* DB FD */ - -OP(fd,20) { illegal_1(); op_20(); } /* DB FD */ -OP(fd,21) { _Z80_R++; _IY = ARG16(); } /* LD IY,w */ -OP(fd,22) { _Z80_R++; EA = ARG16(); WM16( EA, &Z80.IY ); } /* LD (w),IY */ -OP(fd,23) { _Z80_R++; _IY++; } /* INC IY */ -OP(fd,24) { _Z80_R++; _HY = INC(_HY); } /* INC HY */ -OP(fd,25) { _Z80_R++; _HY = DEC(_HY); } /* DEC HY */ -OP(fd,26) { _Z80_R++; _HY = ARG(); } /* LD HY,n */ -OP(fd,27) { illegal_1(); op_27(); } /* DB FD */ - -OP(fd,28) { illegal_1(); op_28(); } /* DB FD */ -OP(fd,29) { _Z80_R++; ADD16(IY,IY); } /* ADD IY,IY */ -OP(fd,2a) { _Z80_R++; EA = ARG16(); RM16( EA, &Z80.IY ); } /* LD IY,(w) */ -OP(fd,2b) { _Z80_R++; _IY--; } /* DEC IY */ -OP(fd,2c) { _Z80_R++; _LY = INC(_LY); } /* INC LY */ -OP(fd,2d) { _Z80_R++; _LY = DEC(_LY); } /* DEC LY */ -OP(fd,2e) { _Z80_R++; _LY = ARG(); } /* LD LY,n */ -OP(fd,2f) { illegal_1(); op_2f(); } /* DB FD */ - -OP(fd,30) { illegal_1(); op_30(); } /* DB FD */ -OP(fd,31) { illegal_1(); op_31(); } /* DB FD */ -OP(fd,32) { illegal_1(); op_32(); } /* DB FD */ -OP(fd,33) { illegal_1(); op_33(); } /* DB FD */ -OP(fd,34) { _Z80_R++; EAY; WM( EA, INC(RM(EA)) ); } /* INC (IY+o) */ -OP(fd,35) { _Z80_R++; EAY; WM( EA, DEC(RM(EA)) ); } /* DEC (IY+o) */ -OP(fd,36) { _Z80_R++; EAY; WM( EA, ARG() ); } /* LD (IY+o),n */ -OP(fd,37) { illegal_1(); op_37(); } /* DB FD */ - -OP(fd,38) { illegal_1(); op_38(); } /* DB FD */ -OP(fd,39) { _Z80_R++; ADD16(IY,SP); } /* ADD IY,SP */ -OP(fd,3a) { illegal_1(); op_3a(); } /* DB FD */ -OP(fd,3b) { illegal_1(); op_3b(); } /* DB FD */ -OP(fd,3c) { illegal_1(); op_3c(); } /* DB FD */ -OP(fd,3d) { illegal_1(); op_3d(); } /* DB FD */ -OP(fd,3e) { illegal_1(); op_3e(); } /* DB FD */ -OP(fd,3f) { illegal_1(); op_3f(); } /* DB FD */ - -OP(fd,40) { illegal_1(); op_40(); } /* DB FD */ -OP(fd,41) { illegal_1(); op_41(); } /* DB FD */ -OP(fd,42) { illegal_1(); op_42(); } /* DB FD */ -OP(fd,43) { illegal_1(); op_43(); } /* DB FD */ -OP(fd,44) { _Z80_R++; _Z80_B = _HY; } /* LD B,HY */ -OP(fd,45) { _Z80_R++; _Z80_B = _LY; } /* LD B,LY */ -OP(fd,46) { _Z80_R++; EAY; _Z80_B = RM(EA); } /* LD B,(IY+o) */ -OP(fd,47) { illegal_1(); op_47(); } /* DB FD */ - -OP(fd,48) { illegal_1(); op_48(); } /* DB FD */ -OP(fd,49) { illegal_1(); op_49(); } /* DB FD */ -OP(fd,4a) { illegal_1(); op_4a(); } /* DB FD */ -OP(fd,4b) { illegal_1(); op_4b(); } /* DB FD */ -OP(fd,4c) { _Z80_R++; _Z80_C = _HY; } /* LD C,HY */ -OP(fd,4d) { _Z80_R++; _Z80_C = _LY; } /* LD C,LY */ -OP(fd,4e) { _Z80_R++; EAY; _Z80_C = RM(EA); } /* LD C,(IY+o) */ -OP(fd,4f) { illegal_1(); op_4f(); } /* DB FD */ - -OP(fd,50) { illegal_1(); op_50(); } /* DB FD */ -OP(fd,51) { illegal_1(); op_51(); } /* DB FD */ -OP(fd,52) { illegal_1(); op_52(); } /* DB FD */ -OP(fd,53) { illegal_1(); op_53(); } /* DB FD */ -OP(fd,54) { _Z80_R++; _Z80_D = _HY; } /* LD D,HY */ -OP(fd,55) { _Z80_R++; _Z80_D = _LY; } /* LD D,LY */ -OP(fd,56) { _Z80_R++; EAY; _Z80_D = RM(EA); } /* LD D,(IY+o) */ -OP(fd,57) { illegal_1(); op_57(); } /* DB FD */ - -OP(fd,58) { illegal_1(); op_58(); } /* DB FD */ -OP(fd,59) { illegal_1(); op_59(); } /* DB FD */ -OP(fd,5a) { illegal_1(); op_5a(); } /* DB FD */ -OP(fd,5b) { illegal_1(); op_5b(); } /* DB FD */ -OP(fd,5c) { _Z80_R++; _Z80_E = _HY; } /* LD E,HY */ -OP(fd,5d) { _Z80_R++; _Z80_E = _LY; } /* LD E,LY */ -OP(fd,5e) { _Z80_R++; EAY; _Z80_E = RM(EA); } /* LD E,(IY+o) */ -OP(fd,5f) { illegal_1(); op_5f(); } /* DB FD */ - -OP(fd,60) { _Z80_R++; _HY = _Z80_B; } /* LD HY,B */ -OP(fd,61) { _Z80_R++; _HY = _Z80_C; } /* LD HY,C */ -OP(fd,62) { _Z80_R++; _HY = _Z80_D; } /* LD HY,D */ -OP(fd,63) { _Z80_R++; _HY = _Z80_E; } /* LD HY,E */ -OP(fd,64) { _Z80_R++; } /* LD HY,HY */ -OP(fd,65) { _Z80_R++; _HY = _LY; } /* LD HY,LY */ -OP(fd,66) { _Z80_R++; EAY; _Z80_H = RM(EA); } /* LD H,(IY+o) */ -OP(fd,67) { _Z80_R++; _HY = _Z80_A; } /* LD HY,A */ - -OP(fd,68) { _Z80_R++; _LY = _Z80_B; } /* LD LY,B */ -OP(fd,69) { _Z80_R++; _LY = _Z80_C; } /* LD LY,C */ -OP(fd,6a) { _Z80_R++; _LY = _Z80_D; } /* LD LY,D */ -OP(fd,6b) { _Z80_R++; _LY = _Z80_E; } /* LD LY,E */ -OP(fd,6c) { _Z80_R++; _LY = _HY; } /* LD LY,HY */ -OP(fd,6d) { _Z80_R++; } /* LD LY,LY */ -OP(fd,6e) { _Z80_R++; EAY; _Z80_L = RM(EA); } /* LD L,(IY+o) */ -OP(fd,6f) { _Z80_R++; _LY = _Z80_A; } /* LD LY,A */ - -OP(fd,70) { _Z80_R++; EAY; WM( EA, _Z80_B ); } /* LD (IY+o),B */ -OP(fd,71) { _Z80_R++; EAY; WM( EA, _Z80_C ); } /* LD (IY+o),C */ -OP(fd,72) { _Z80_R++; EAY; WM( EA, _Z80_D ); } /* LD (IY+o),D */ -OP(fd,73) { _Z80_R++; EAY; WM( EA, _Z80_E ); } /* LD (IY+o),E */ -OP(fd,74) { _Z80_R++; EAY; WM( EA, _Z80_H ); } /* LD (IY+o),H */ -OP(fd,75) { _Z80_R++; EAY; WM( EA, _Z80_L ); } /* LD (IY+o),L */ -OP(fd,76) { illegal_1(); op_76(); } /* DB FD */ -OP(fd,77) { _Z80_R++; EAY; WM( EA, _Z80_A ); } /* LD (IY+o),A */ - -OP(fd,78) { illegal_1(); op_78(); } /* DB FD */ -OP(fd,79) { illegal_1(); op_79(); } /* DB FD */ -OP(fd,7a) { illegal_1(); op_7a(); } /* DB FD */ -OP(fd,7b) { illegal_1(); op_7b(); } /* DB FD */ -OP(fd,7c) { _Z80_R++; _Z80_A = _HY; } /* LD A,HY */ -OP(fd,7d) { _Z80_R++; _Z80_A = _LY; } /* LD A,LY */ -OP(fd,7e) { _Z80_R++; EAY; _Z80_A = RM(EA); } /* LD A,(IY+o) */ -OP(fd,7f) { illegal_1(); op_7f(); } /* DB FD */ - -OP(fd,80) { illegal_1(); op_80(); } /* DB FD */ -OP(fd,81) { illegal_1(); op_81(); } /* DB FD */ -OP(fd,82) { illegal_1(); op_82(); } /* DB FD */ -OP(fd,83) { illegal_1(); op_83(); } /* DB FD */ -OP(fd,84) { _Z80_R++; ADD(_HY); } /* ADD A,HY */ -OP(fd,85) { _Z80_R++; ADD(_LY); } /* ADD A,LY */ -OP(fd,86) { _Z80_R++; EAY; ADD(RM(EA)); } /* ADD A,(IY+o) */ -OP(fd,87) { illegal_1(); op_87(); } /* DB FD */ - -OP(fd,88) { illegal_1(); op_88(); } /* DB FD */ -OP(fd,89) { illegal_1(); op_89(); } /* DB FD */ -OP(fd,8a) { illegal_1(); op_8a(); } /* DB FD */ -OP(fd,8b) { illegal_1(); op_8b(); } /* DB FD */ -OP(fd,8c) { _Z80_R++; ADC(_HY); } /* ADC A,HY */ -OP(fd,8d) { _Z80_R++; ADC(_LY); } /* ADC A,LY */ -OP(fd,8e) { _Z80_R++; EAY; ADC(RM(EA)); } /* ADC A,(IY+o) */ -OP(fd,8f) { illegal_1(); op_8f(); } /* DB FD */ - -OP(fd,90) { illegal_1(); op_90(); } /* DB FD */ -OP(fd,91) { illegal_1(); op_91(); } /* DB FD */ -OP(fd,92) { illegal_1(); op_92(); } /* DB FD */ -OP(fd,93) { illegal_1(); op_93(); } /* DB FD */ -OP(fd,94) { _Z80_R++; SUB(_HY); } /* SUB HY */ -OP(fd,95) { _Z80_R++; SUB(_LY); } /* SUB LY */ -OP(fd,96) { _Z80_R++; EAY; SUB(RM(EA)); } /* SUB (IY+o) */ -OP(fd,97) { illegal_1(); op_97(); } /* DB FD */ - -OP(fd,98) { illegal_1(); op_98(); } /* DB FD */ -OP(fd,99) { illegal_1(); op_99(); } /* DB FD */ -OP(fd,9a) { illegal_1(); op_9a(); } /* DB FD */ -OP(fd,9b) { illegal_1(); op_9b(); } /* DB FD */ -OP(fd,9c) { _Z80_R++; SBC(_HY); } /* SBC A,HY */ -OP(fd,9d) { _Z80_R++; SBC(_LY); } /* SBC A,LY */ -OP(fd,9e) { _Z80_R++; EAY; SBC(RM(EA)); } /* SBC A,(IY+o) */ -OP(fd,9f) { illegal_1(); op_9f(); } /* DB FD */ - -OP(fd,a0) { illegal_1(); op_a0(); } /* DB FD */ -OP(fd,a1) { illegal_1(); op_a1(); } /* DB FD */ -OP(fd,a2) { illegal_1(); op_a2(); } /* DB FD */ -OP(fd,a3) { illegal_1(); op_a3(); } /* DB FD */ -OP(fd,a4) { _Z80_R++; AND(_HY); } /* AND HY */ -OP(fd,a5) { _Z80_R++; AND(_LY); } /* AND LY */ -OP(fd,a6) { _Z80_R++; EAY; AND(RM(EA)); } /* AND (IY+o) */ -OP(fd,a7) { illegal_1(); op_a7(); } /* DB FD */ - -OP(fd,a8) { illegal_1(); op_a8(); } /* DB FD */ -OP(fd,a9) { illegal_1(); op_a9(); } /* DB FD */ -OP(fd,aa) { illegal_1(); op_aa(); } /* DB FD */ -OP(fd,ab) { illegal_1(); op_ab(); } /* DB FD */ -OP(fd,ac) { _Z80_R++; XOR(_HY); } /* XOR HY */ -OP(fd,ad) { _Z80_R++; XOR(_LY); } /* XOR LY */ -OP(fd,ae) { _Z80_R++; EAY; XOR(RM(EA)); } /* XOR (IY+o) */ -OP(fd,af) { illegal_1(); op_af(); } /* DB FD */ - -OP(fd,b0) { illegal_1(); op_b0(); } /* DB FD */ -OP(fd,b1) { illegal_1(); op_b1(); } /* DB FD */ -OP(fd,b2) { illegal_1(); op_b2(); } /* DB FD */ -OP(fd,b3) { illegal_1(); op_b3(); } /* DB FD */ -OP(fd,b4) { _Z80_R++; OR(_HY); } /* OR HY */ -OP(fd,b5) { _Z80_R++; OR(_LY); } /* OR LY */ -OP(fd,b6) { _Z80_R++; EAY; OR(RM(EA)); } /* OR (IY+o) */ -OP(fd,b7) { illegal_1(); op_b7(); } /* DB FD */ - -OP(fd,b8) { illegal_1(); op_b8(); } /* DB FD */ -OP(fd,b9) { illegal_1(); op_b9(); } /* DB FD */ -OP(fd,ba) { illegal_1(); op_ba(); } /* DB FD */ -OP(fd,bb) { illegal_1(); op_bb(); } /* DB FD */ -OP(fd,bc) { _Z80_R++; CP(_HY); } /* CP HY */ -OP(fd,bd) { _Z80_R++; CP(_LY); } /* CP LY */ -OP(fd,be) { _Z80_R++; EAY; CP(RM(EA)); } /* CP (IY+o) */ -OP(fd,bf) { illegal_1(); op_bf(); } /* DB FD */ - -OP(fd,c0) { illegal_1(); op_c0(); } /* DB FD */ -OP(fd,c1) { illegal_1(); op_c1(); } /* DB FD */ -OP(fd,c2) { illegal_1(); op_c2(); } /* DB FD */ -OP(fd,c3) { illegal_1(); op_c3(); } /* DB FD */ -OP(fd,c4) { illegal_1(); op_c4(); } /* DB FD */ -OP(fd,c5) { illegal_1(); op_c5(); } /* DB FD */ -OP(fd,c6) { illegal_1(); op_c6(); } /* DB FD */ -OP(fd,c7) { illegal_1(); op_c7(); } /* DB FD */ - -OP(fd,c8) { illegal_1(); op_c8(); } /* DB FD */ -OP(fd,c9) { illegal_1(); op_c9(); } /* DB FD */ -OP(fd,ca) { illegal_1(); op_ca(); } /* DB FD */ -OP(fd,cb) { _Z80_R++; EAY; EXEC(xycb,ARG()); } /* ** FD CB xx */ -OP(fd,cc) { illegal_1(); op_cc(); } /* DB FD */ -OP(fd,cd) { illegal_1(); op_cd(); } /* DB FD */ -OP(fd,ce) { illegal_1(); op_ce(); } /* DB FD */ -OP(fd,cf) { illegal_1(); op_cf(); } /* DB FD */ - -OP(fd,d0) { illegal_1(); op_d0(); } /* DB FD */ -OP(fd,d1) { illegal_1(); op_d1(); } /* DB FD */ -OP(fd,d2) { illegal_1(); op_d2(); } /* DB FD */ -OP(fd,d3) { illegal_1(); op_d3(); } /* DB FD */ -OP(fd,d4) { illegal_1(); op_d4(); } /* DB FD */ -OP(fd,d5) { illegal_1(); op_d5(); } /* DB FD */ -OP(fd,d6) { illegal_1(); op_d6(); } /* DB FD */ -OP(fd,d7) { illegal_1(); op_d7(); } /* DB FD */ - -OP(fd,d8) { illegal_1(); op_d8(); } /* DB FD */ -OP(fd,d9) { illegal_1(); op_d9(); } /* DB FD */ -OP(fd,da) { illegal_1(); op_da(); } /* DB FD */ -OP(fd,db) { illegal_1(); op_db(); } /* DB FD */ -OP(fd,dc) { illegal_1(); op_dc(); } /* DB FD */ -OP(fd,dd) { illegal_1(); op_dd(); } /* DB FD */ -OP(fd,de) { illegal_1(); op_de(); } /* DB FD */ -OP(fd,df) { illegal_1(); op_df(); } /* DB FD */ - -OP(fd,e0) { illegal_1(); op_e0(); } /* DB FD */ -OP(fd,e1) { _Z80_R++; POP(IY); } /* POP IY */ -OP(fd,e2) { illegal_1(); op_e2(); } /* DB FD */ -OP(fd,e3) { _Z80_R++; EXSP(IY); } /* EX (SP),IY */ -OP(fd,e4) { illegal_1(); op_e4(); } /* DB FD */ -OP(fd,e5) { _Z80_R++; PUSH( IY ); } /* PUSH IY */ -OP(fd,e6) { illegal_1(); op_e6(); } /* DB FD */ -OP(fd,e7) { illegal_1(); op_e7(); } /* DB FD */ - -OP(fd,e8) { illegal_1(); op_e8(); } /* DB FD */ -OP(fd,e9) { _Z80_R++; _PC = _IY; change_pc16(_PCD); } /* JP (IY) */ -OP(fd,ea) { illegal_1(); op_ea(); } /* DB FD */ -OP(fd,eb) { illegal_1(); op_eb(); } /* DB FD */ -OP(fd,ec) { illegal_1(); op_ec(); } /* DB FD */ -OP(fd,ed) { illegal_1(); op_ed(); } /* DB FD */ -OP(fd,ee) { illegal_1(); op_ee(); } /* DB FD */ -OP(fd,ef) { illegal_1(); op_ef(); } /* DB FD */ - -OP(fd,f0) { illegal_1(); op_f0(); } /* DB FD */ -OP(fd,f1) { illegal_1(); op_f1(); } /* DB FD */ -OP(fd,f2) { illegal_1(); op_f2(); } /* DB FD */ -OP(fd,f3) { illegal_1(); op_f3(); } /* DB FD */ -OP(fd,f4) { illegal_1(); op_f4(); } /* DB FD */ -OP(fd,f5) { illegal_1(); op_f5(); } /* DB FD */ -OP(fd,f6) { illegal_1(); op_f6(); } /* DB FD */ -OP(fd,f7) { illegal_1(); op_f7(); } /* DB FD */ - -OP(fd,f8) { illegal_1(); op_f8(); } /* DB FD */ -OP(fd,f9) { _Z80_R++; _SP = _IY; } /* LD SP,IY */ -OP(fd,fa) { illegal_1(); op_fa(); } /* DB FD */ -OP(fd,fb) { illegal_1(); op_fb(); } /* DB FD */ -OP(fd,fc) { illegal_1(); op_fc(); } /* DB FD */ -OP(fd,fd) { illegal_1(); op_fd(); } /* DB FD */ -OP(fd,fe) { illegal_1(); op_fe(); } /* DB FD */ -OP(fd,ff) { illegal_1(); op_ff(); } /* DB FD */ - -OP(illegal,2) -{ - logerror("Z80 #%d ill. opcode $ed $%02x\n", - cpu_getactivecpu(), cpu_readop((_PCD-1)&0xffff)); -} - -/********************************************************** - * special opcodes (ED prefix) - **********************************************************/ -OP(ed,00) { illegal_2(); } /* DB ED */ -OP(ed,01) { illegal_2(); } /* DB ED */ -OP(ed,02) { illegal_2(); } /* DB ED */ -OP(ed,03) { illegal_2(); } /* DB ED */ -OP(ed,04) { illegal_2(); } /* DB ED */ -OP(ed,05) { illegal_2(); } /* DB ED */ -OP(ed,06) { illegal_2(); } /* DB ED */ -OP(ed,07) { illegal_2(); } /* DB ED */ - -OP(ed,08) { illegal_2(); } /* DB ED */ -OP(ed,09) { illegal_2(); } /* DB ED */ -OP(ed,0a) { illegal_2(); } /* DB ED */ -OP(ed,0b) { illegal_2(); } /* DB ED */ -OP(ed,0c) { illegal_2(); } /* DB ED */ -OP(ed,0d) { illegal_2(); } /* DB ED */ -OP(ed,0e) { illegal_2(); } /* DB ED */ -OP(ed,0f) { illegal_2(); } /* DB ED */ - -OP(ed,10) { illegal_2(); } /* DB ED */ -OP(ed,11) { illegal_2(); } /* DB ED */ -OP(ed,12) { illegal_2(); } /* DB ED */ -OP(ed,13) { illegal_2(); } /* DB ED */ -OP(ed,14) { illegal_2(); } /* DB ED */ -OP(ed,15) { illegal_2(); } /* DB ED */ -OP(ed,16) { illegal_2(); } /* DB ED */ -OP(ed,17) { illegal_2(); } /* DB ED */ - -OP(ed,18) { illegal_2(); } /* DB ED */ -OP(ed,19) { illegal_2(); } /* DB ED */ -OP(ed,1a) { illegal_2(); } /* DB ED */ -OP(ed,1b) { illegal_2(); } /* DB ED */ -OP(ed,1c) { illegal_2(); } /* DB ED */ -OP(ed,1d) { illegal_2(); } /* DB ED */ -OP(ed,1e) { illegal_2(); } /* DB ED */ -OP(ed,1f) { illegal_2(); } /* DB ED */ - -OP(ed,20) { illegal_2(); } /* DB ED */ -OP(ed,21) { illegal_2(); } /* DB ED */ -OP(ed,22) { illegal_2(); } /* DB ED */ -OP(ed,23) { illegal_2(); } /* DB ED */ -OP(ed,24) { illegal_2(); } /* DB ED */ -OP(ed,25) { illegal_2(); } /* DB ED */ -OP(ed,26) { illegal_2(); } /* DB ED */ -OP(ed,27) { illegal_2(); } /* DB ED */ - -OP(ed,28) { illegal_2(); } /* DB ED */ -OP(ed,29) { illegal_2(); } /* DB ED */ -OP(ed,2a) { illegal_2(); } /* DB ED */ -OP(ed,2b) { illegal_2(); } /* DB ED */ -OP(ed,2c) { illegal_2(); } /* DB ED */ -OP(ed,2d) { illegal_2(); } /* DB ED */ -OP(ed,2e) { illegal_2(); } /* DB ED */ -OP(ed,2f) { illegal_2(); } /* DB ED */ - -OP(ed,30) { illegal_2(); } /* DB ED */ -OP(ed,31) { illegal_2(); } /* DB ED */ -OP(ed,32) { illegal_2(); } /* DB ED */ -OP(ed,33) { illegal_2(); } /* DB ED */ -OP(ed,34) { illegal_2(); } /* DB ED */ -OP(ed,35) { illegal_2(); } /* DB ED */ -OP(ed,36) { illegal_2(); } /* DB ED */ -OP(ed,37) { illegal_2(); } /* DB ED */ - -OP(ed,38) { illegal_2(); } /* DB ED */ -OP(ed,39) { illegal_2(); } /* DB ED */ -OP(ed,3a) { illegal_2(); } /* DB ED */ -OP(ed,3b) { illegal_2(); } /* DB ED */ -OP(ed,3c) { illegal_2(); } /* DB ED */ -OP(ed,3d) { illegal_2(); } /* DB ED */ -OP(ed,3e) { illegal_2(); } /* DB ED */ -OP(ed,3f) { illegal_2(); } /* DB ED */ - -OP(ed,40) { _Z80_B = IN(_BC); _F = (_F & CF) | SZP[_Z80_B]; } /* IN B,(C) */ -OP(ed,41) { OUT(_BC,_Z80_B); } /* OUT (C),B */ -OP(ed,42) { SBC16( BC ); } /* SBC HL,BC */ -OP(ed,43) { EA = ARG16(); WM16( EA, &Z80.BC ); } /* LD (w),BC */ -OP(ed,44) { NEG; } /* NEG */ -OP(ed,45) { RETN; } /* RETN; */ -OP(ed,46) { _IM = 0; } /* IM 0 */ -OP(ed,47) { LD_I_A; } /* LD I,A */ - -OP(ed,48) { _Z80_C = IN(_BC); _F = (_F & CF) | SZP[_Z80_C]; } /* IN C,(C) */ -OP(ed,49) { OUT(_BC,_Z80_C); } /* OUT (C),C */ -OP(ed,4a) { ADC16( BC ); } /* ADC HL,BC */ -OP(ed,4b) { EA = ARG16(); RM16( EA, &Z80.BC ); } /* LD BC,(w) */ -OP(ed,4c) { NEG; } /* NEG */ -OP(ed,4d) { RETI; } /* RETI */ -OP(ed,4e) { _IM = 0; } /* IM 0 */ -OP(ed,4f) { LD_R_A; } /* LD R,A */ - -OP(ed,50) { _Z80_D = IN(_BC); _F = (_F & CF) | SZP[_Z80_D]; } /* IN D,(C) */ -OP(ed,51) { OUT(_BC,_Z80_D); } /* OUT (C),D */ -OP(ed,52) { SBC16( DE ); } /* SBC HL,DE */ -OP(ed,53) { EA = ARG16(); WM16( EA, &Z80.DE ); } /* LD (w),DE */ -OP(ed,54) { NEG; } /* NEG */ -OP(ed,55) { RETN; } /* RETN; */ -OP(ed,56) { _IM = 1; } /* IM 1 */ -OP(ed,57) { LD_A_I; } /* LD A,I */ - -OP(ed,58) { _Z80_E = IN(_BC); _F = (_F & CF) | SZP[_Z80_E]; } /* IN E,(C) */ -OP(ed,59) { OUT(_BC,_Z80_E); } /* OUT (C),E */ -OP(ed,5a) { ADC16( DE ); } /* ADC HL,DE */ -OP(ed,5b) { EA = ARG16(); RM16( EA, &Z80.DE ); } /* LD DE,(w) */ -OP(ed,5c) { NEG; } /* NEG */ -OP(ed,5d) { RETI; } /* RETI */ -OP(ed,5e) { _IM = 2; } /* IM 2 */ -OP(ed,5f) { LD_A_R; } /* LD A,R */ - -OP(ed,60) { _Z80_H = IN(_BC); _F = (_F & CF) | SZP[_Z80_H]; } /* IN H,(C) */ -OP(ed,61) { OUT(_BC,_Z80_H); } /* OUT (C),H */ -OP(ed,62) { SBC16( HL ); } /* SBC HL,HL */ -OP(ed,63) { EA = ARG16(); WM16( EA, &Z80.HL ); } /* LD (w),HL */ -OP(ed,64) { NEG; } /* NEG */ -OP(ed,65) { RETN; } /* RETN; */ -OP(ed,66) { _IM = 0; } /* IM 0 */ -OP(ed,67) { RRD; } /* RRD (HL) */ - -OP(ed,68) { _Z80_L = IN(_BC); _F = (_F & CF) | SZP[_Z80_L]; } /* IN L,(C) */ -OP(ed,69) { OUT(_BC,_Z80_L); } /* OUT (C),L */ -OP(ed,6a) { ADC16( HL ); } /* ADC HL,HL */ -OP(ed,6b) { EA = ARG16(); RM16( EA, &Z80.HL ); } /* LD HL,(w) */ -OP(ed,6c) { NEG; } /* NEG */ -OP(ed,6d) { RETI; } /* RETI */ -OP(ed,6e) { _IM = 0; } /* IM 0 */ -OP(ed,6f) { RLD; } /* RLD (HL) */ - -OP(ed,70) { UINT8 res = IN(_BC); _F = (_F & CF) | SZP[res]; } /* IN 0,(C) */ -OP(ed,71) { OUT(_BC,0); } /* OUT (C),0 */ -OP(ed,72) { SBC16( SP ); } /* SBC HL,SP */ -OP(ed,73) { EA = ARG16(); WM16( EA, &Z80.SP ); } /* LD (w),SP */ -OP(ed,74) { NEG; } /* NEG */ -OP(ed,75) { RETN; } /* RETN; */ -OP(ed,76) { _IM = 1; } /* IM 1 */ -OP(ed,77) { illegal_2(); } /* DB ED,77 */ - -OP(ed,78) { _Z80_A = IN(_BC); _F = (_F & CF) | SZP[_Z80_A]; } /* IN E,(C) */ -OP(ed,79) { OUT(_BC,_Z80_A); } /* OUT (C),E */ -OP(ed,7a) { ADC16( SP ); } /* ADC HL,SP */ -OP(ed,7b) { EA = ARG16(); RM16( EA, &Z80.SP ); } /* LD SP,(w) */ -OP(ed,7c) { NEG; } /* NEG */ -OP(ed,7d) { RETI; } /* RETI */ -OP(ed,7e) { _IM = 2; } /* IM 2 */ -OP(ed,7f) { illegal_2(); } /* DB ED,7F */ - -OP(ed,80) { illegal_2(); } /* DB ED */ -OP(ed,81) { illegal_2(); } /* DB ED */ -OP(ed,82) { illegal_2(); } /* DB ED */ -OP(ed,83) { illegal_2(); } /* DB ED */ -OP(ed,84) { illegal_2(); } /* DB ED */ -OP(ed,85) { illegal_2(); } /* DB ED */ -OP(ed,86) { illegal_2(); } /* DB ED */ -OP(ed,87) { illegal_2(); } /* DB ED */ - -OP(ed,88) { illegal_2(); } /* DB ED */ -OP(ed,89) { illegal_2(); } /* DB ED */ -OP(ed,8a) { illegal_2(); } /* DB ED */ -OP(ed,8b) { illegal_2(); } /* DB ED */ -OP(ed,8c) { illegal_2(); } /* DB ED */ -OP(ed,8d) { illegal_2(); } /* DB ED */ -OP(ed,8e) { illegal_2(); } /* DB ED */ -OP(ed,8f) { illegal_2(); } /* DB ED */ - -OP(ed,90) { illegal_2(); } /* DB ED */ -OP(ed,91) { illegal_2(); } /* DB ED */ -OP(ed,92) { illegal_2(); } /* DB ED */ -OP(ed,93) { illegal_2(); } /* DB ED */ -OP(ed,94) { illegal_2(); } /* DB ED */ -OP(ed,95) { illegal_2(); } /* DB ED */ -OP(ed,96) { illegal_2(); } /* DB ED */ -OP(ed,97) { illegal_2(); } /* DB ED */ - -OP(ed,98) { illegal_2(); } /* DB ED */ -OP(ed,99) { illegal_2(); } /* DB ED */ -OP(ed,9a) { illegal_2(); } /* DB ED */ -OP(ed,9b) { illegal_2(); } /* DB ED */ -OP(ed,9c) { illegal_2(); } /* DB ED */ -OP(ed,9d) { illegal_2(); } /* DB ED */ -OP(ed,9e) { illegal_2(); } /* DB ED */ -OP(ed,9f) { illegal_2(); } /* DB ED */ - -OP(ed,a0) { LDI; } /* LDI */ -OP(ed,a1) { CPI; } /* CPI */ -OP(ed,a2) { INI; } /* INI */ -OP(ed,a3) { OUTI; } /* OUTI */ -OP(ed,a4) { illegal_2(); } /* DB ED */ -OP(ed,a5) { illegal_2(); } /* DB ED */ -OP(ed,a6) { illegal_2(); } /* DB ED */ -OP(ed,a7) { illegal_2(); } /* DB ED */ - -OP(ed,a8) { LDD; } /* LDD */ -OP(ed,a9) { CPD; } /* CPD */ -OP(ed,aa) { IND; } /* IND */ -OP(ed,ab) { OUTD; } /* OUTD */ -OP(ed,ac) { illegal_2(); } /* DB ED */ -OP(ed,ad) { illegal_2(); } /* DB ED */ -OP(ed,ae) { illegal_2(); } /* DB ED */ -OP(ed,af) { illegal_2(); } /* DB ED */ - -OP(ed,b0) { LDIR; } /* LDIR */ -OP(ed,b1) { CPIR; } /* CPIR */ -OP(ed,b2) { INIR; } /* INIR */ -OP(ed,b3) { OTIR; } /* OTIR */ -OP(ed,b4) { illegal_2(); } /* DB ED */ -OP(ed,b5) { illegal_2(); } /* DB ED */ -OP(ed,b6) { illegal_2(); } /* DB ED */ -OP(ed,b7) { illegal_2(); } /* DB ED */ - -OP(ed,b8) { LDDR; } /* LDDR */ -OP(ed,b9) { CPDR; } /* CPDR */ -OP(ed,ba) { INDR; } /* INDR */ -OP(ed,bb) { OTDR; } /* OTDR */ -OP(ed,bc) { illegal_2(); } /* DB ED */ -OP(ed,bd) { illegal_2(); } /* DB ED */ -OP(ed,be) { illegal_2(); } /* DB ED */ -OP(ed,bf) { illegal_2(); } /* DB ED */ - -OP(ed,c0) { illegal_2(); } /* DB ED */ -OP(ed,c1) { illegal_2(); } /* DB ED */ -OP(ed,c2) { illegal_2(); } /* DB ED */ -OP(ed,c3) { illegal_2(); } /* DB ED */ -OP(ed,c4) { illegal_2(); } /* DB ED */ -OP(ed,c5) { illegal_2(); } /* DB ED */ -OP(ed,c6) { illegal_2(); } /* DB ED */ -OP(ed,c7) { illegal_2(); } /* DB ED */ - -OP(ed,c8) { illegal_2(); } /* DB ED */ -OP(ed,c9) { illegal_2(); } /* DB ED */ -OP(ed,ca) { illegal_2(); } /* DB ED */ -OP(ed,cb) { illegal_2(); } /* DB ED */ -OP(ed,cc) { illegal_2(); } /* DB ED */ -OP(ed,cd) { illegal_2(); } /* DB ED */ -OP(ed,ce) { illegal_2(); } /* DB ED */ -OP(ed,cf) { illegal_2(); } /* DB ED */ - -OP(ed,d0) { illegal_2(); } /* DB ED */ -OP(ed,d1) { illegal_2(); } /* DB ED */ -OP(ed,d2) { illegal_2(); } /* DB ED */ -OP(ed,d3) { illegal_2(); } /* DB ED */ -OP(ed,d4) { illegal_2(); } /* DB ED */ -OP(ed,d5) { illegal_2(); } /* DB ED */ -OP(ed,d6) { illegal_2(); } /* DB ED */ -OP(ed,d7) { illegal_2(); } /* DB ED */ - -OP(ed,d8) { illegal_2(); } /* DB ED */ -OP(ed,d9) { illegal_2(); } /* DB ED */ -OP(ed,da) { illegal_2(); } /* DB ED */ -OP(ed,db) { illegal_2(); } /* DB ED */ -OP(ed,dc) { illegal_2(); } /* DB ED */ -OP(ed,dd) { illegal_2(); } /* DB ED */ -OP(ed,de) { illegal_2(); } /* DB ED */ -OP(ed,df) { illegal_2(); } /* DB ED */ - -OP(ed,e0) { illegal_2(); } /* DB ED */ -OP(ed,e1) { illegal_2(); } /* DB ED */ -OP(ed,e2) { illegal_2(); } /* DB ED */ -OP(ed,e3) { illegal_2(); } /* DB ED */ -OP(ed,e4) { illegal_2(); } /* DB ED */ -OP(ed,e5) { illegal_2(); } /* DB ED */ -OP(ed,e6) { illegal_2(); } /* DB ED */ -OP(ed,e7) { illegal_2(); } /* DB ED */ - -OP(ed,e8) { illegal_2(); } /* DB ED */ -OP(ed,e9) { illegal_2(); } /* DB ED */ -OP(ed,ea) { illegal_2(); } /* DB ED */ -OP(ed,eb) { illegal_2(); } /* DB ED */ -OP(ed,ec) { illegal_2(); } /* DB ED */ -OP(ed,ed) { illegal_2(); } /* DB ED */ -OP(ed,ee) { illegal_2(); } /* DB ED */ -OP(ed,ef) { illegal_2(); } /* DB ED */ - -OP(ed,f0) { illegal_2(); } /* DB ED */ -OP(ed,f1) { illegal_2(); } /* DB ED */ -OP(ed,f2) { illegal_2(); } /* DB ED */ -OP(ed,f3) { illegal_2(); } /* DB ED */ -OP(ed,f4) { illegal_2(); } /* DB ED */ -OP(ed,f5) { illegal_2(); } /* DB ED */ -OP(ed,f6) { illegal_2(); } /* DB ED */ -OP(ed,f7) { illegal_2(); } /* DB ED */ - -OP(ed,f8) { illegal_2(); } /* DB ED */ -OP(ed,f9) { illegal_2(); } /* DB ED */ -OP(ed,fa) { illegal_2(); } /* DB ED */ -OP(ed,fb) { illegal_2(); } /* DB ED */ -OP(ed,fc) { illegal_2(); } /* DB ED */ -OP(ed,fd) { illegal_2(); } /* DB ED */ -OP(ed,fe) { illegal_2(); } /* DB ED */ -OP(ed,ff) { illegal_2(); } /* DB ED */ - -#if TIME_LOOP_HACKS - -#define CHECK_BC_LOOP \ -if( _BC > 1 && _PCD < 0xfffc ) { \ - UINT8 op1 = cpu_readop(_PCD); \ - UINT8 op2 = cpu_readop(_PCD+1); \ - if( (op1==0x78 && op2==0xb1) || (op1==0x79 && op2==0xb0) ) \ - { \ - UINT8 op3 = cpu_readop(_PCD+2); \ - UINT8 op4 = cpu_readop(_PCD+3); \ - if( op3==0x20 && op4==0xfb ) \ - { \ - int cnt = \ - cc[Z80_TABLE_op][0x78] + \ - cc[Z80_TABLE_op][0xb1] + \ - cc[Z80_TABLE_op][0x20] + \ - cc[Z80_TABLE_ex][0x20]; \ - while( _BC > 0 && z80_ICount > cnt ) \ - { \ - BURNODD( cnt, 4, cnt ); \ - _BC--; \ - } \ - } \ - else \ - if( op3 == 0xc2 ) \ - { \ - UINT8 ad1 = cpu_readop_arg(_PCD+3); \ - UINT8 ad2 = cpu_readop_arg(_PCD+4); \ - if( (ad1 + 256 * ad2) == (_PCD - 1) ) \ - { \ - int cnt = \ - cc[Z80_TABLE_op][0x78] + \ - cc[Z80_TABLE_op][0xb1] + \ - cc[Z80_TABLE_op][0xc2] + \ - cc[Z80_TABLE_ex][0xc2]; \ - while( _BC > 0 && z80_ICount > cnt ) \ - { \ - BURNODD( cnt, 4, cnt ); \ - _BC--; \ - } \ - } \ - } \ - } \ -} - -#define CHECK_DE_LOOP \ -if( _DE > 1 && _PCD < 0xfffc ) { \ - UINT8 op1 = cpu_readop(_PCD); \ - UINT8 op2 = cpu_readop(_PCD+1); \ - if( (op1==0x7a && op2==0xb3) || (op1==0x7b && op2==0xb2) ) \ - { \ - UINT8 op3 = cpu_readop(_PCD+2); \ - UINT8 op4 = cpu_readop(_PCD+3); \ - if( op3==0x20 && op4==0xfb ) \ - { \ - int cnt = \ - cc[Z80_TABLE_op][0x7a] + \ - cc[Z80_TABLE_op][0xb3] + \ - cc[Z80_TABLE_op][0x20] + \ - cc[Z80_TABLE_ex][0x20]; \ - while( _DE > 0 && z80_ICount > cnt ) \ - { \ - BURNODD( cnt, 4, cnt ); \ - _DE--; \ - } \ - } \ - else \ - if( op3==0xc2 ) \ - { \ - UINT8 ad1 = cpu_readop_arg(_PCD+3); \ - UINT8 ad2 = cpu_readop_arg(_PCD+4); \ - if( (ad1 + 256 * ad2) == (_PCD - 1) ) \ - { \ - int cnt = \ - cc[Z80_TABLE_op][0x7a] + \ - cc[Z80_TABLE_op][0xb3] + \ - cc[Z80_TABLE_op][0xc2] + \ - cc[Z80_TABLE_ex][0xc2]; \ - while( _DE > 0 && z80_ICount > cnt ) \ - { \ - BURNODD( cnt, 4, cnt ); \ - _DE--; \ - } \ - } \ - } \ - } \ -} - -#define CHECK_HL_LOOP \ -if( _HL > 1 && _PCD < 0xfffc ) { \ - UINT8 op1 = cpu_readop(_PCD); \ - UINT8 op2 = cpu_readop(_PCD+1); \ - if( (op1==0x7c && op2==0xb5) || (op1==0x7d && op2==0xb4) ) \ - { \ - UINT8 op3 = cpu_readop(_PCD+2); \ - UINT8 op4 = cpu_readop(_PCD+3); \ - if( op3==0x20 && op4==0xfb ) \ - { \ - int cnt = \ - cc[Z80_TABLE_op][0x7c] + \ - cc[Z80_TABLE_op][0xb5] + \ - cc[Z80_TABLE_op][0x20] + \ - cc[Z80_TABLE_ex][0x20]; \ - while( _HL > 0 && z80_ICount > cnt ) \ - { \ - BURNODD( cnt, 4, cnt ); \ - _HL--; \ - } \ - } \ - else \ - if( op3==0xc2 ) \ - { \ - UINT8 ad1 = cpu_readop_arg(_PCD+3); \ - UINT8 ad2 = cpu_readop_arg(_PCD+4); \ - if( (ad1 + 256 * ad2) == (_PCD - 1) ) \ - { \ - int cnt = \ - cc[Z80_TABLE_op][0x7c] + \ - cc[Z80_TABLE_op][0xb5] + \ - cc[Z80_TABLE_op][0xc2] + \ - cc[Z80_TABLE_ex][0xc2]; \ - while( _HL > 0 && z80_ICount > cnt ) \ - { \ - BURNODD( cnt, 4, cnt ); \ - _HL--; \ - } \ - } \ - } \ - } \ -} - -#else - -#define CHECK_BC_LOOP -#define CHECK_DE_LOOP -#define CHECK_HL_LOOP - -#endif - -/********************************************************** - * main opcodes - **********************************************************/ -OP(op,00) { } /* NOP */ -OP(op,01) { _BC = ARG16(); } /* LD BC,w */ -OP(op,02) { WM( _BC, _Z80_A ); } /* LD (BC),A */ -OP(op,03) { _BC++; } /* INC BC */ -OP(op,04) { _Z80_B = INC(_Z80_B); } /* INC B */ -OP(op,05) { _Z80_B = DEC(_Z80_B); } /* DEC B */ -OP(op,06) { _Z80_B = ARG(); } /* LD B,n */ -OP(op,07) { RLCA; } /* RLCA */ - -OP(op,08) { EX_AF; } /* EX AF,AF' */ -OP(op,09) { ADD16(HL,BC); } /* ADD HL,BC */ -OP(op,0a) { _Z80_A = RM(_BC); } /* LD A,(BC) */ -OP(op,0b) { _BC--; CHECK_BC_LOOP; } /* DEC BC */ -OP(op,0c) { _Z80_C = INC(_Z80_C); } /* INC C */ -OP(op,0d) { _Z80_C = DEC(_Z80_C); } /* DEC C */ -OP(op,0e) { _Z80_C = ARG(); } /* LD C,n */ -OP(op,0f) { RRCA; } /* RRCA */ - -OP(op,10) { _Z80_B--; JR_COND( _Z80_B, 0x10 ); } /* DJNZ o */ -OP(op,11) { _DE = ARG16(); } /* LD DE,w */ -OP(op,12) { WM( _DE, _Z80_A ); } /* LD (DE),A */ -OP(op,13) { _DE++; } /* INC DE */ -OP(op,14) { _Z80_D = INC(_Z80_D); } /* INC D */ -OP(op,15) { _Z80_D = DEC(_Z80_D); } /* DEC D */ -OP(op,16) { _Z80_D = ARG(); } /* LD D,n */ -OP(op,17) { RLA; } /* RLA */ - -OP(op,18) { JR(); } /* JR o */ -OP(op,19) { ADD16(HL,DE); } /* ADD HL,DE */ -OP(op,1a) { _Z80_A = RM(_DE); } /* LD A,(DE) */ -OP(op,1b) { _DE--; CHECK_DE_LOOP; } /* DEC DE */ -OP(op,1c) { _Z80_E = INC(_Z80_E); } /* INC E */ -OP(op,1d) { _Z80_E = DEC(_Z80_E); } /* DEC E */ -OP(op,1e) { _Z80_E = ARG(); } /* LD E,n */ -OP(op,1f) { RRA; } /* RRA */ - -OP(op,20) { JR_COND( !(_F & ZF), 0x20 ); } /* JR NZ,o */ -OP(op,21) { _HL = ARG16(); } /* LD HL,w */ -OP(op,22) { EA = ARG16(); WM16( EA, &Z80.HL ); } /* LD (w),HL */ -OP(op,23) { _HL++; } /* INC HL */ -OP(op,24) { _Z80_H = INC(_Z80_H); } /* INC H */ -OP(op,25) { _Z80_H = DEC(_Z80_H); } /* DEC H */ -OP(op,26) { _Z80_H = ARG(); } /* LD H,n */ -OP(op,27) { DAA; } /* DAA */ - -OP(op,28) { JR_COND( _F & ZF, 0x28 ); } /* JR Z,o */ -OP(op,29) { ADD16(HL,HL); } /* ADD HL,HL */ -OP(op,2a) { EA = ARG16(); RM16( EA, &Z80.HL ); } /* LD HL,(w) */ -OP(op,2b) { _HL--; CHECK_HL_LOOP; } /* DEC HL */ -OP(op,2c) { _Z80_L = INC(_Z80_L); } /* INC L */ -OP(op,2d) { _Z80_L = DEC(_Z80_L); } /* DEC L */ -OP(op,2e) { _Z80_L = ARG(); } /* LD L,n */ -OP(op,2f) { _Z80_A ^= 0xff; _F = (_F&(SF|ZF|PF|CF))|HF|NF|(_Z80_A&(YF|XF)); } /* CPL */ - -OP(op,30) { JR_COND( !(_F & CF), 0x30 ); } /* JR NC,o */ -OP(op,31) { _SP = ARG16(); } /* LD SP,w */ -OP(op,32) { EA = ARG16(); WM( EA, _Z80_A ); } /* LD (w),A */ -OP(op,33) { _SP++; } /* INC SP */ -OP(op,34) { WM( _HL, INC(RM(_HL)) ); } /* INC (HL) */ -OP(op,35) { WM( _HL, DEC(RM(_HL)) ); } /* DEC (HL) */ -OP(op,36) { WM( _HL, ARG() ); } /* LD (HL),n */ -OP(op,37) { _F = (_F & (SF|ZF|PF)) | CF | (_Z80_A & (YF|XF)); } /* SCF */ - -OP(op,38) { JR_COND( _F & CF, 0x38 ); } /* JR C,o */ -OP(op,39) { ADD16(HL,SP); } /* ADD HL,SP */ -OP(op,3a) { EA = ARG16(); _Z80_A = RM( EA ); } /* LD A,(w) */ -OP(op,3b) { _SP--; } /* DEC SP */ -OP(op,3c) { _Z80_A = INC(_Z80_A); } /* INC A */ -OP(op,3d) { _Z80_A = DEC(_Z80_A); } /* DEC A */ -OP(op,3e) { _Z80_A = ARG(); } /* LD A,n */ -OP(op,3f) { _F = ((_F&(SF|ZF|PF|CF))|((_F&CF)<<4)|(_Z80_A&(YF|XF)))^CF; } /* CCF */ -/*OP(op,3f) { _F = ((_F & ~(HF|NF)) | ((_F & CF)<<4)) ^ CF; } CCF */ - -OP(op,40) { } /* LD B,B */ -OP(op,41) { _Z80_B = _Z80_C; } /* LD B,C */ -OP(op,42) { _Z80_B = _Z80_D; } /* LD B,D */ -OP(op,43) { _Z80_B = _Z80_E; } /* LD B,E */ -OP(op,44) { _Z80_B = _Z80_H; } /* LD B,H */ -OP(op,45) { _Z80_B = _Z80_L; } /* LD B,L */ -OP(op,46) { _Z80_B = RM(_HL); } /* LD B,(HL) */ -OP(op,47) { _Z80_B = _Z80_A; } /* LD B,A */ - -OP(op,48) { _Z80_C = _Z80_B; } /* LD C,B */ -OP(op,49) { } /* LD C,C */ -OP(op,4a) { _Z80_C = _Z80_D; } /* LD C,D */ -OP(op,4b) { _Z80_C = _Z80_E; } /* LD C,E */ -OP(op,4c) { _Z80_C = _Z80_H; } /* LD C,H */ -OP(op,4d) { _Z80_C = _Z80_L; } /* LD C,L */ -OP(op,4e) { _Z80_C = RM(_HL); } /* LD C,(HL) */ -OP(op,4f) { _Z80_C = _Z80_A; } /* LD C,A */ - -OP(op,50) { _Z80_D = _Z80_B; } /* LD D,B */ -OP(op,51) { _Z80_D = _Z80_C; } /* LD D,C */ -OP(op,52) { } /* LD D,D */ -OP(op,53) { _Z80_D = _Z80_E; } /* LD D,E */ -OP(op,54) { _Z80_D = _Z80_H; } /* LD D,H */ -OP(op,55) { _Z80_D = _Z80_L; } /* LD D,L */ -OP(op,56) { _Z80_D = RM(_HL); } /* LD D,(HL) */ -OP(op,57) { _Z80_D = _Z80_A; } /* LD D,A */ - -OP(op,58) { _Z80_E = _Z80_B; } /* LD E,B */ -OP(op,59) { _Z80_E = _Z80_C; } /* LD E,C */ -OP(op,5a) { _Z80_E = _Z80_D; } /* LD E,D */ -OP(op,5b) { } /* LD E,E */ -OP(op,5c) { _Z80_E = _Z80_H; } /* LD E,H */ -OP(op,5d) { _Z80_E = _Z80_L; } /* LD E,L */ -OP(op,5e) { _Z80_E = RM(_HL); } /* LD E,(HL) */ -OP(op,5f) { _Z80_E = _Z80_A; } /* LD E,A */ - -OP(op,60) { _Z80_H = _Z80_B; } /* LD H,B */ -OP(op,61) { _Z80_H = _Z80_C; } /* LD H,C */ -OP(op,62) { _Z80_H = _Z80_D; } /* LD H,D */ -OP(op,63) { _Z80_H = _Z80_E; } /* LD H,E */ -OP(op,64) { } /* LD H,H */ -OP(op,65) { _Z80_H = _Z80_L; } /* LD H,L */ -OP(op,66) { _Z80_H = RM(_HL); } /* LD H,(HL) */ -OP(op,67) { _Z80_H = _Z80_A; } /* LD H,A */ - -OP(op,68) { _Z80_L = _Z80_B; } /* LD L,B */ -OP(op,69) { _Z80_L = _Z80_C; } /* LD L,C */ -OP(op,6a) { _Z80_L = _Z80_D; } /* LD L,D */ -OP(op,6b) { _Z80_L = _Z80_E; } /* LD L,E */ -OP(op,6c) { _Z80_L = _Z80_H; } /* LD L,H */ -OP(op,6d) { } /* LD L,L */ -OP(op,6e) { _Z80_L = RM(_HL); } /* LD L,(HL) */ -OP(op,6f) { _Z80_L = _Z80_A; } /* LD L,A */ - -OP(op,70) { WM( _HL, _Z80_B ); } /* LD (HL),B */ -OP(op,71) { WM( _HL, _Z80_C ); } /* LD (HL),C */ -OP(op,72) { WM( _HL, _Z80_D ); } /* LD (HL),D */ -OP(op,73) { WM( _HL, _Z80_E ); } /* LD (HL),E */ -OP(op,74) { WM( _HL, _Z80_H ); } /* LD (HL),H */ -OP(op,75) { WM( _HL, _Z80_L ); } /* LD (HL),L */ -OP(op,76) { ENTER_HALT; } /* HALT */ -OP(op,77) { WM( _HL, _Z80_A ); } /* LD (HL),A */ - -OP(op,78) { _Z80_A = _Z80_B; } /* LD A,B */ -OP(op,79) { _Z80_A = _Z80_C; } /* LD A,C */ -OP(op,7a) { _Z80_A = _Z80_D; } /* LD A,D */ -OP(op,7b) { _Z80_A = _Z80_E; } /* LD A,E */ -OP(op,7c) { _Z80_A = _Z80_H; } /* LD A,H */ -OP(op,7d) { _Z80_A = _Z80_L; } /* LD A,L */ -OP(op,7e) { _Z80_A = RM(_HL); } /* LD A,(HL) */ -OP(op,7f) { } /* LD A,A */ - -OP(op,80) { ADD(_Z80_B); } /* ADD A,B */ -OP(op,81) { ADD(_Z80_C); } /* ADD A,C */ -OP(op,82) { ADD(_Z80_D); } /* ADD A,D */ -OP(op,83) { ADD(_Z80_E); } /* ADD A,E */ -OP(op,84) { ADD(_Z80_H); } /* ADD A,H */ -OP(op,85) { ADD(_Z80_L); } /* ADD A,L */ -OP(op,86) { ADD(RM(_HL)); } /* ADD A,(HL) */ -OP(op,87) { ADD(_Z80_A); } /* ADD A,A */ - -OP(op,88) { ADC(_Z80_B); } /* ADC A,B */ -OP(op,89) { ADC(_Z80_C); } /* ADC A,C */ -OP(op,8a) { ADC(_Z80_D); } /* ADC A,D */ -OP(op,8b) { ADC(_Z80_E); } /* ADC A,E */ -OP(op,8c) { ADC(_Z80_H); } /* ADC A,H */ -OP(op,8d) { ADC(_Z80_L); } /* ADC A,L */ -OP(op,8e) { ADC(RM(_HL)); } /* ADC A,(HL) */ -OP(op,8f) { ADC(_Z80_A); } /* ADC A,A */ - -OP(op,90) { SUB(_Z80_B); } /* SUB B */ -OP(op,91) { SUB(_Z80_C); } /* SUB C */ -OP(op,92) { SUB(_Z80_D); } /* SUB D */ -OP(op,93) { SUB(_Z80_E); } /* SUB E */ -OP(op,94) { SUB(_Z80_H); } /* SUB H */ -OP(op,95) { SUB(_Z80_L); } /* SUB L */ -OP(op,96) { SUB(RM(_HL)); } /* SUB (HL) */ -OP(op,97) { SUB(_Z80_A); } /* SUB A */ - -OP(op,98) { SBC(_Z80_B); } /* SBC A,B */ -OP(op,99) { SBC(_Z80_C); } /* SBC A,C */ -OP(op,9a) { SBC(_Z80_D); } /* SBC A,D */ -OP(op,9b) { SBC(_Z80_E); } /* SBC A,E */ -OP(op,9c) { SBC(_Z80_H); } /* SBC A,H */ -OP(op,9d) { SBC(_Z80_L); } /* SBC A,L */ -OP(op,9e) { SBC(RM(_HL)); } /* SBC A,(HL) */ -OP(op,9f) { SBC(_Z80_A); } /* SBC A,A */ - -OP(op,a0) { AND(_Z80_B); } /* AND B */ -OP(op,a1) { AND(_Z80_C); } /* AND C */ -OP(op,a2) { AND(_Z80_D); } /* AND D */ -OP(op,a3) { AND(_Z80_E); } /* AND E */ -OP(op,a4) { AND(_Z80_H); } /* AND H */ -OP(op,a5) { AND(_Z80_L); } /* AND L */ -OP(op,a6) { AND(RM(_HL)); } /* AND (HL) */ -OP(op,a7) { AND(_Z80_A); } /* AND A */ - -OP(op,a8) { XOR(_Z80_B); } /* XOR B */ -OP(op,a9) { XOR(_Z80_C); } /* XOR C */ -OP(op,aa) { XOR(_Z80_D); } /* XOR D */ -OP(op,ab) { XOR(_Z80_E); } /* XOR E */ -OP(op,ac) { XOR(_Z80_H); } /* XOR H */ -OP(op,ad) { XOR(_Z80_L); } /* XOR L */ -OP(op,ae) { XOR(RM(_HL)); } /* XOR (HL) */ -OP(op,af) { XOR(_Z80_A); } /* XOR A */ - -OP(op,b0) { OR(_Z80_B); } /* OR B */ -OP(op,b1) { OR(_Z80_C); } /* OR C */ -OP(op,b2) { OR(_Z80_D); } /* OR D */ -OP(op,b3) { OR(_Z80_E); } /* OR E */ -OP(op,b4) { OR(_Z80_H); } /* OR H */ -OP(op,b5) { OR(_Z80_L); } /* OR L */ -OP(op,b6) { OR(RM(_HL)); } /* OR (HL) */ -OP(op,b7) { OR(_Z80_A); } /* OR A */ - -OP(op,b8) { CP(_Z80_B); } /* CP B */ -OP(op,b9) { CP(_Z80_C); } /* CP C */ -OP(op,ba) { CP(_Z80_D); } /* CP D */ -OP(op,bb) { CP(_Z80_E); } /* CP E */ -OP(op,bc) { CP(_Z80_H); } /* CP H */ -OP(op,bd) { CP(_Z80_L); } /* CP L */ -OP(op,be) { CP(RM(_HL)); } /* CP (HL) */ -OP(op,bf) { CP(_Z80_A); } /* CP A */ - -OP(op,c0) { RET_COND( !(_F & ZF), 0xc0 ); } /* RET NZ */ -OP(op,c1) { POP(BC); } /* POP BC */ -OP(op,c2) { JP_COND( !(_F & ZF) ); } /* JP NZ,a */ -OP(op,c3) { JP; } /* JP a */ -OP(op,c4) { CALL_COND( !(_F & ZF), 0xc4 ); } /* CALL NZ,a */ -OP(op,c5) { PUSH( BC ); } /* PUSH BC */ -OP(op,c6) { ADD(ARG()); } /* ADD A,n */ -OP(op,c7) { RST(0x00); } /* RST 0 */ - -OP(op,c8) { RET_COND( _F & ZF, 0xc8 ); } /* RET Z */ -OP(op,c9) { POP(PC); change_pc16(_PCD); } /* RET */ -OP(op,ca) { JP_COND( _F & ZF ); } /* JP Z,a */ -OP(op,cb) { _Z80_R++; EXEC(cb,ROP()); } /* **** CB xx */ -OP(op,cc) { CALL_COND( _F & ZF, 0xcc ); } /* CALL Z,a */ -OP(op,cd) { CALL(); } /* CALL a */ -OP(op,ce) { ADC(ARG()); } /* ADC A,n */ -OP(op,cf) { RST(0x08); } /* RST 1 */ - -OP(op,d0) { RET_COND( !(_F & CF), 0xd0 ); } /* RET NC */ -OP(op,d1) { POP(DE); } /* POP DE */ -OP(op,d2) { JP_COND( !(_F & CF) ); } /* JP NC,a */ -OP(op,d3) { unsigned n = ARG() | (_Z80_A << 8); OUT( n, _Z80_A ); } /* OUT (n),A */ -OP(op,d4) { CALL_COND( !(_F & CF), 0xd4 ); } /* CALL NC,a */ -OP(op,d5) { PUSH( DE ); } /* PUSH DE */ -OP(op,d6) { SUB(ARG()); } /* SUB n */ -OP(op,d7) { RST(0x10); } /* RST 2 */ - -OP(op,d8) { RET_COND( _F & CF, 0xd8 ); } /* RET C */ -OP(op,d9) { EXX; } /* EXX */ -OP(op,da) { JP_COND( _F & CF ); } /* JP C,a */ -OP(op,db) { unsigned n = ARG() | (_Z80_A << 8); _Z80_A = IN( n ); } /* IN A,(n) */ -OP(op,dc) { CALL_COND( _F & CF, 0xdc ); } /* CALL C,a */ -OP(op,dd) { _Z80_R++; EXEC(dd,ROP()); } /* **** DD xx */ -OP(op,de) { SBC(ARG()); } /* SBC A,n */ -OP(op,df) { RST(0x18); } /* RST 3 */ - -OP(op,e0) { RET_COND( !(_F & PF), 0xe0 ); } /* RET PO */ -OP(op,e1) { POP(HL); } /* POP HL */ -OP(op,e2) { JP_COND( !(_F & PF) ); } /* JP PO,a */ -OP(op,e3) { EXSP(HL); } /* EX HL,(SP) */ -OP(op,e4) { CALL_COND( !(_F & PF), 0xe4 ); } /* CALL PO,a */ -OP(op,e5) { PUSH( HL ); } /* PUSH HL */ -OP(op,e6) { AND(ARG()); } /* AND n */ -OP(op,e7) { RST(0x20); } /* RST 4 */ - -OP(op,e8) { RET_COND( _F & PF, 0xe8 ); } /* RET PE */ -OP(op,e9) { _PC = _HL; change_pc16(_PCD); } /* JP (HL) */ -OP(op,ea) { JP_COND( _F & PF ); } /* JP PE,a */ -OP(op,eb) { EX_DE_HL; } /* EX DE,HL */ -OP(op,ec) { CALL_COND( _F & PF, 0xec ); } /* CALL PE,a */ -OP(op,ed) { _Z80_R++; EXEC(ed,ROP()); } /* **** ED xx */ -OP(op,ee) { XOR(ARG()); } /* XOR n */ -OP(op,ef) { RST(0x28); } /* RST 5 */ - -OP(op,f0) { RET_COND( !(_F & SF), 0xf0 ); } /* RET P */ -OP(op,f1) { POP(AF); } /* POP AF */ -OP(op,f2) { JP_COND( !(_F & SF) ); } /* JP P,a */ -OP(op,f3) { _IFF1 = _IFF2 = 0; } /* DI */ -OP(op,f4) { CALL_COND( !(_F & SF), 0xf4 ); } /* CALL P,a */ -OP(op,f5) { PUSH( AF ); } /* PUSH AF */ -OP(op,f6) { OR(ARG()); } /* OR n */ -OP(op,f7) { RST(0x30); } /* RST 6 */ - -OP(op,f8) { RET_COND( _F & SF, 0xf8 ); } /* RET M */ -OP(op,f9) { _SP = _HL; } /* LD SP,HL */ -OP(op,fa) { JP_COND(_F & SF); } /* JP M,a */ -OP(op,fb) { EI; } /* EI */ -OP(op,fc) { CALL_COND( _F & SF, 0xfc ); } /* CALL M,a */ -OP(op,fd) { _Z80_R++; EXEC(fd,ROP()); } /* **** FD xx */ -OP(op,fe) { CP(ARG()); } /* CP n */ -OP(op,ff) { RST(0x38); } /* RST 7 */ - - -static void take_interrupt(void) -{ - if( _IFF1 ) - { - int irq_vector; - - /* there isn't a valid previous program counter */ - _PPC = -1; - - /* Check if processor was halted */ - LEAVE_HALT; - - if( Z80.irq_max ) /* daisy chain mode */ - { - if( Z80.request_irq >= 0 ) - { - /* Clear both interrupt flip flops */ - _IFF1 = _IFF2 = 0; - irq_vector = Z80.irq[Z80.request_irq].interrupt_entry(Z80.irq[Z80.request_irq].irq_param); - LOG(("Z80 #%d daisy chain irq_vector $%02x\n", cpu_getactivecpu(), irq_vector)); - Z80.request_irq = -1; - } else return; - } - else - { - /* Clear both interrupt flip flops */ - _IFF1 = _IFF2 = 0; - /* call back the cpu interface to retrieve the vector */ - irq_vector = (*Z80.irq_callback)(0); - LOG(("Z80 #%d single int. irq_vector $%02x\n", cpu_getactivecpu(), irq_vector)); - } - - /* Interrupt mode 2. Call [Z80.I:databyte] */ - if( _IM == 2 ) - { - irq_vector = (irq_vector & 0xff) | (_Z80_I << 8); - PUSH( PC ); - RM16( irq_vector, &Z80.PC ); - LOG(("Z80 #%d IM2 [$%04x] = $%04x\n",cpu_getactivecpu() , irq_vector, _PCD)); - /* CALL opcode timing */ - Z80.extra_cycles += cc[Z80_TABLE_op][0xcd]; - } - else - /* Interrupt mode 1. RST 38h */ - if( _IM == 1 ) - { - LOG(("Z80 #%d IM1 $0038\n",cpu_getactivecpu() )); - PUSH( PC ); - _PCD = 0x0038; - /* RST $38 + 'interrupt latency' cycles */ - Z80.extra_cycles += cc[Z80_TABLE_op][0xff] + cc[Z80_TABLE_ex][0xff]; - } - else - { - /* Interrupt mode 0. We check for CALL and JP instructions, */ - /* if neither of these were found we assume a 1 byte opcode */ - /* was placed on the databus */ - LOG(("Z80 #%d IM0 $%04x\n",cpu_getactivecpu() , irq_vector)); - switch (irq_vector & 0xff0000) - { - case 0xcd0000: /* call */ - PUSH( PC ); - _PCD = irq_vector & 0xffff; - /* CALL $xxxx + 'interrupt latency' cycles */ - Z80.extra_cycles += cc[Z80_TABLE_op][0xcd] + cc[Z80_TABLE_ex][0xff]; - break; - case 0xc30000: /* jump */ - _PCD = irq_vector & 0xffff; - /* JP $xxxx + 2 cycles */ - Z80.extra_cycles += cc[Z80_TABLE_op][0xc3] + cc[Z80_TABLE_ex][0xff]; - break; - default: /* rst (or other opcodes?) */ - PUSH( PC ); - _PCD = irq_vector & 0x0038; - /* RST $xx + 2 cycles */ - Z80.extra_cycles += cc[Z80_TABLE_op][_PCD] + cc[Z80_TABLE_ex][_PCD]; - break; - } - } - change_pc16(_PCD); - } -} - -/**************************************************************************** - * Processor initialization - ****************************************************************************/ -void z80_init(void) -{ - int cpu = 0;//cpu_getactivecpu(); - int i, p; -#if BIG_FLAGS_ARRAY - if( !SZHVC_add || !SZHVC_sub ) - { - int oldval, newval, val; - UINT8 *padd, *padc, *psub, *psbc; - /* allocate big flag arrays once */ - SZHVC_add = (UINT8 *)malloc(2*256*256); - SZHVC_sub = (UINT8 *)malloc(2*256*256); - if( !SZHVC_add || !SZHVC_sub ) - { - LOG(("Z80: failed to allocate 2 * 128K flags arrays!!!\n")); - exit(1); - } - padd = &SZHVC_add[ 0*256]; - padc = &SZHVC_add[256*256]; - psub = &SZHVC_sub[ 0*256]; - psbc = &SZHVC_sub[256*256]; - for (oldval = 0; oldval < 256; oldval++) - { - for (newval = 0; newval < 256; newval++) - { - /* add or adc w/o carry set */ - val = newval - oldval; - *padd = (newval) ? ((newval & 0x80) ? SF : 0) : ZF; -#if Z80_EXACT - *padd |= (newval & (YF | XF)); /* undocumented flag bits 5+3 */ -#endif - if( (newval & 0x0f) < (oldval & 0x0f) ) *padd |= HF; - if( newval < oldval ) *padd |= CF; - if( (val^oldval^0x80) & (val^newval) & 0x80 ) *padd |= VF; - padd++; - - /* adc with carry set */ - val = newval - oldval - 1; - *padc = (newval) ? ((newval & 0x80) ? SF : 0) : ZF; -#if Z80_EXACT - *padc |= (newval & (YF | XF)); /* undocumented flag bits 5+3 */ -#endif - if( (newval & 0x0f) <= (oldval & 0x0f) ) *padc |= HF; - if( newval <= oldval ) *padc |= CF; - if( (val^oldval^0x80) & (val^newval) & 0x80 ) *padc |= VF; - padc++; - - /* cp, sub or sbc w/o carry set */ - val = oldval - newval; - *psub = NF | ((newval) ? ((newval & 0x80) ? SF : 0) : ZF); -#if Z80_EXACT - *psub |= (newval & (YF | XF)); /* undocumented flag bits 5+3 */ -#endif - if( (newval & 0x0f) > (oldval & 0x0f) ) *psub |= HF; - if( newval > oldval ) *psub |= CF; - if( (val^oldval) & (oldval^newval) & 0x80 ) *psub |= VF; - psub++; - - /* sbc with carry set */ - val = oldval - newval - 1; - *psbc = NF | ((newval) ? ((newval & 0x80) ? SF : 0) : ZF); -#if Z80_EXACT - *psbc |= (newval & (YF | XF)); /* undocumented flag bits 5+3 */ -#endif - if( (newval & 0x0f) >= (oldval & 0x0f) ) *psbc |= HF; - if( newval >= oldval ) *psbc |= CF; - if( (val^oldval) & (oldval^newval) & 0x80 ) *psbc |= VF; - psbc++; - } - } - } -#endif - for (i = 0; i < 256; i++) - { - p = 0; - if( i&0x01 ) ++p; - if( i&0x02 ) ++p; - if( i&0x04 ) ++p; - if( i&0x08 ) ++p; - if( i&0x10 ) ++p; - if( i&0x20 ) ++p; - if( i&0x40 ) ++p; - if( i&0x80 ) ++p; - SZ[i] = i ? i & SF : ZF; -#if Z80_EXACT - SZ[i] |= (i & (YF | XF)); /* undocumented flag bits 5+3 */ -#endif - SZ_BIT[i] = i ? i & SF : ZF | PF; -#if Z80_EXACT - SZ_BIT[i] |= (i & (YF | XF)); /* undocumented flag bits 5+3 */ -#endif - SZP[i] = SZ[i] | ((p & 1) ? 0 : PF); - SZHV_inc[i] = SZ[i]; - if( i == 0x80 ) SZHV_inc[i] |= VF; - if( (i & 0x0f) == 0x00 ) SZHV_inc[i] |= HF; - SZHV_dec[i] = SZ[i] | NF; - if( i == 0x7f ) SZHV_dec[i] |= VF; - if( (i & 0x0f) == 0x0f ) SZHV_dec[i] |= HF; - } - -/* - state_save_register_UINT16("z80", cpu, "AF", &Z80.AF.w.l, 1); - state_save_register_UINT16("z80", cpu, "BC", &Z80.BC.w.l, 1); - state_save_register_UINT16("z80", cpu, "DE", &Z80.DE.w.l, 1); - state_save_register_UINT16("z80", cpu, "HL", &Z80.HL.w.l, 1); - state_save_register_UINT16("z80", cpu, "IX", &Z80.IX.w.l, 1); - state_save_register_UINT16("z80", cpu, "IY", &Z80.IY.w.l, 1); - state_save_register_UINT16("z80", cpu, "PC", &Z80.PC.w.l, 1); - state_save_register_UINT16("z80", cpu, "SP", &Z80.SP.w.l, 1); - state_save_register_UINT16("z80", cpu, "AF2", &Z80.AF2.w.l, 1); - state_save_register_UINT16("z80", cpu, "BC2", &Z80.BC2.w.l, 1); - state_save_register_UINT16("z80", cpu, "DE2", &Z80.DE2.w.l, 1); - state_save_register_UINT16("z80", cpu, "HL2", &Z80.HL2.w.l, 1); - state_save_register_UINT8("z80", cpu, "R", &Z80.R, 1); - state_save_register_UINT8("z80", cpu, "R2", &Z80.R2, 1); - state_save_register_UINT8("z80", cpu, "IFF1", &Z80.IFF1, 1); - state_save_register_UINT8("z80", cpu, "IFF2", &Z80.IFF2, 1); - state_save_register_UINT8("z80", cpu, "HALT", &Z80.HALT, 1); - state_save_register_UINT8("z80", cpu, "IM", &Z80.IM, 1); - state_save_register_UINT8("z80", cpu, "I", &Z80.I, 1); - state_save_register_UINT8("z80", cpu, "irq_max", &Z80.irq_max, 1); - state_save_register_INT8("z80", cpu, "request_irq", &Z80.request_irq, 1); - state_save_register_INT8("z80", cpu, "service_irq", &Z80.service_irq, 1); - state_save_register_UINT8("z80", cpu, "int_state", Z80.int_state, 4); - state_save_register_UINT8("z80", cpu, "nmi_state", &Z80.nmi_state, 1); - state_save_register_UINT8("z80", cpu, "irq_state", &Z80.irq_state, 1); -*/ - /* daisy chain needs to be saved by z80ctc.c somehow */ -} - -/**************************************************************************** - * Reset registers to their initial values - ****************************************************************************/ -void z80_reset(void *param) -{ - Z80_DaisyChain *daisy_chain = (Z80_DaisyChain *)param; - memset(&Z80, 0, sizeof(Z80)); - _IX = _IY = 0xffff; /* IX and IY are FFFF after a reset! */ - _F = ZF; /* Zero flag is set */ - Z80.request_irq = -1; - Z80.service_irq = -1; - Z80.nmi_state = CLEAR_LINE; - Z80.irq_state = CLEAR_LINE; - - if( daisy_chain ) - { - while( daisy_chain->irq_param != -1 && Z80.irq_max < Z80_MAXDAISY ) - { - /* set callbackhandler after reti */ - Z80.irq[Z80.irq_max] = *daisy_chain; - /* device reset */ - if( Z80.irq[Z80.irq_max].reset ) - Z80.irq[Z80.irq_max].reset(Z80.irq[Z80.irq_max].irq_param); - Z80.irq_max++; - daisy_chain++; - } - } - - change_pc16(_PCD); -} - -void z80_exit(void) -{ -#if BIG_FLAGS_ARRAY - if (SZHVC_add) free(SZHVC_add); - SZHVC_add = NULL; - if (SZHVC_sub) free(SZHVC_sub); - SZHVC_sub = NULL; -#endif -} - -/**************************************************************************** - * Execute 'cycles' T-states. Return number of T-states really executed - ****************************************************************************/ -int z80_execute(int cycles) -{ - z80_ICount = cycles - Z80.extra_cycles; - Z80.extra_cycles = 0; - - do - { - _PPC = _PCD; - CALL_MAME_DEBUG; - _Z80_R++; - EXEC_INLINE(op,ROP()); - } while( z80_ICount > 0 ); - - z80_ICount -= Z80.extra_cycles; - Z80.extra_cycles = 0; - - return cycles - z80_ICount; -} - -/**************************************************************************** - * Burn 'cycles' T-states. Adjust R register for the lost time - ****************************************************************************/ -void z80_burn(int cycles) -{ - if( cycles > 0 ) - { - /* NOP takes 4 cycles per instruction */ - int n = (cycles + 3) / 4; - _Z80_R += n; - z80_ICount -= 4 * n; - } -} - -/**************************************************************************** - * Get all registers in given buffer - ****************************************************************************/ -unsigned z80_get_context (void *dst) -{ - if( dst ) - *(Z80_Regs*)dst = Z80; - return sizeof(Z80_Regs); -} - -/**************************************************************************** - * Set all registers to given values - ****************************************************************************/ -void z80_set_context (void *src) -{ - if( src ) - Z80 = *(Z80_Regs*)src; - change_pc16(_PCD); -} - -/**************************************************************************** - * Get a pointer to a cycle count table - ****************************************************************************/ -const void *z80_get_cycle_table (int which) -{ - if (which >= 0 && which <= Z80_TABLE_xycb) - return cc[which]; - return NULL; -} - -/**************************************************************************** - * Set a new cycle count table - ****************************************************************************/ -void z80_set_cycle_table (int which, void *new_table) -{ - if (which >= 0 && which <= Z80_TABLE_ex) - cc[which] = new_table; -} - -/**************************************************************************** - * Return a specific register - ****************************************************************************/ -unsigned z80_get_reg (int regnum) -{ - switch( regnum ) - { - //case REG_PC: return _PCD; - case Z80_PC: return Z80.PC.w.l; - //case REG_SP: return _SPD; - case Z80_SP: return Z80.SP.w.l; - case Z80_AF: return Z80.AF.w.l; - case Z80_BC: return Z80.BC.w.l; - case Z80_DE: return Z80.DE.w.l; - case Z80_HL: return Z80.HL.w.l; - case Z80_IX: return Z80.IX.w.l; - case Z80_IY: return Z80.IY.w.l; - case Z80_R: return (Z80.R & 0x7f) | (Z80.R2 & 0x80); - case Z80_I: return Z80.I; - case Z80_AF2: return Z80.AF2.w.l; - case Z80_BC2: return Z80.BC2.w.l; - case Z80_DE2: return Z80.DE2.w.l; - case Z80_HL2: return Z80.HL2.w.l; - case Z80_IM: return Z80.IM; - case Z80_IFF1: return Z80.IFF1; - case Z80_IFF2: return Z80.IFF2; - case Z80_HALT: return Z80.HALT; - case Z80_NMI_STATE: return Z80.nmi_state; - case Z80_IRQ_STATE: return Z80.irq_state; - case Z80_DC0: return Z80.int_state[0]; - case Z80_DC1: return Z80.int_state[1]; - case Z80_DC2: return Z80.int_state[2]; - case Z80_DC3: return Z80.int_state[3]; - case REG_PREVIOUSPC: return Z80.PREPC.w.l; - default: - if( regnum <= REG_SP_CONTENTS ) - { - unsigned offset = _SPD + 2 * (REG_SP_CONTENTS - regnum); - if( offset < 0xffff ) - return RM( offset ) | ( RM( offset + 1) << 8 ); - } - } - return 0; -} - -/**************************************************************************** - * Set a specific register - ****************************************************************************/ -void z80_set_reg (int regnum, unsigned val) -{ - switch( regnum ) - { - //case REG_PC: _PC = val; change_pc16(_PCD); break; - case Z80_PC: Z80.PC.w.l = val; break; - //case REG_SP: _SP = val; break; - case Z80_SP: Z80.SP.w.l = val; break; - case Z80_AF: Z80.AF.w.l = val; break; - case Z80_BC: Z80.BC.w.l = val; break; - case Z80_DE: Z80.DE.w.l = val; break; - case Z80_HL: Z80.HL.w.l = val; break; - case Z80_IX: Z80.IX.w.l = val; break; - case Z80_IY: Z80.IY.w.l = val; break; - case Z80_R: Z80.R = val; Z80.R2 = val & 0x80; break; - case Z80_I: Z80.I = val; break; - case Z80_AF2: Z80.AF2.w.l = val; break; - case Z80_BC2: Z80.BC2.w.l = val; break; - case Z80_DE2: Z80.DE2.w.l = val; break; - case Z80_HL2: Z80.HL2.w.l = val; break; - case Z80_IM: Z80.IM = val; break; - case Z80_IFF1: Z80.IFF1 = val; break; - case Z80_IFF2: Z80.IFF2 = val; break; - case Z80_HALT: Z80.HALT = val; break; - case Z80_NMI_STATE: z80_set_irq_line(IRQ_LINE_NMI,val); break; - case Z80_IRQ_STATE: z80_set_irq_line(0,val); break; - case Z80_DC0: Z80.int_state[0] = val; break; - case Z80_DC1: Z80.int_state[1] = val; break; - case Z80_DC2: Z80.int_state[2] = val; break; - case Z80_DC3: Z80.int_state[3] = val; break; - default: - if( regnum <= REG_SP_CONTENTS ) - { - unsigned offset = _SPD + 2 * (REG_SP_CONTENTS - regnum); - if( offset < 0xffff ) - { - WM( offset, val & 0xff ); - WM( offset+1, (val >> 8) & 0xff ); - } - } - } -} - -/**************************************************************************** - * Set IRQ line state - ****************************************************************************/ -void z80_set_irq_line(int irqline, int state) -{ - if (irqline == IRQ_LINE_NMI) - { - if( Z80.nmi_state == state ) return; - - LOG(("Z80 #%d set_irq_line (NMI) %d\n", cpu_getactivecpu(), state)); - Z80.nmi_state = state; - if( state == CLEAR_LINE ) return; - - LOG(("Z80 #%d take NMI\n", cpu_getactivecpu())); - _PPC = -1; /* there isn't a valid previous program counter */ - LEAVE_HALT; /* Check if processor was halted */ - - _IFF1 = 0; - PUSH( PC ); - _PCD = 0x0066; - Z80.extra_cycles += 11; - } - else - { - LOG(("Z80 #%d set_irq_line %d\n",cpu_getactivecpu() , state)); - Z80.irq_state = state; - if( state == CLEAR_LINE ) return; - - if( Z80.irq_max ) - { - int daisychain, device, int_state; - daisychain = (*Z80.irq_callback)(irqline); - device = daisychain >> 8; - int_state = daisychain & 0xff; - LOG(("Z80 #%d daisy chain $%04x -> device %d, state $%02x",cpu_getactivecpu(), daisychain, device, int_state)); - - if( Z80.int_state[device] != int_state ) - { - LOG((" change\n")); - /* set new interrupt status */ - Z80.int_state[device] = int_state; - /* check interrupt status */ - Z80.request_irq = Z80.service_irq = -1; - - /* search higher IRQ or IEO */ - for( device = 0 ; device < Z80.irq_max ; device ++ ) - { - /* IEO = disable ? */ - if( Z80.int_state[device] & Z80_INT_IEO ) - { - Z80.request_irq = -1; /* if IEO is disable , masking lower IRQ */ - Z80.service_irq = device; /* set highest interrupt service device */ - } - /* IRQ = request ? */ - if( Z80.int_state[device] & Z80_INT_REQ ) - Z80.request_irq = device; - } - LOG(("Z80 #%d daisy chain service_irq $%02x, request_irq $%02x\n", cpu_getactivecpu(), Z80.service_irq, Z80.request_irq)); - if( Z80.request_irq < 0 ) return; - } - else - { - LOG((" no change\n")); - return; - } - } - take_interrupt(); - } -} - -/**************************************************************************** - * Set IRQ vector callback - ****************************************************************************/ -void z80_set_irq_callback(int (*callback)(int)) -{ - LOG(("Z80 #%d set_irq_callback $%08x\n",cpu_getactivecpu() , (int)callback)); - Z80.irq_callback = callback; -} - -/**************************************************************************** - * Return a formatted string for a register - ****************************************************************************/ -const char *z80_info(void *context, int regnum) -{ - static char buffer[32][47+1]; - static int which = 0; - Z80_Regs *r = context; - - which = (which+1) % 32; - buffer[which][0] = '\0'; - if( !context ) - r = &Z80; - - switch( regnum ) - { - case CPU_INFO_REG+Z80_PC: sprintf(buffer[which], "PC:%04X", r->PC.w.l); break; - case CPU_INFO_REG+Z80_SP: sprintf(buffer[which], "SP:%04X", r->SP.w.l); break; - case CPU_INFO_REG+Z80_AF: sprintf(buffer[which], "AF:%04X", r->AF.w.l); break; - case CPU_INFO_REG+Z80_BC: sprintf(buffer[which], "BC:%04X", r->BC.w.l); break; - case CPU_INFO_REG+Z80_DE: sprintf(buffer[which], "DE:%04X", r->DE.w.l); break; - case CPU_INFO_REG+Z80_HL: sprintf(buffer[which], "HL:%04X", r->HL.w.l); break; - case CPU_INFO_REG+Z80_IX: sprintf(buffer[which], "IX:%04X", r->IX.w.l); break; - case CPU_INFO_REG+Z80_IY: sprintf(buffer[which], "IY:%04X", r->IY.w.l); break; - case CPU_INFO_REG+Z80_R: sprintf(buffer[which], "R:%02X", (r->R & 0x7f) | (r->R2 & 0x80)); break; - case CPU_INFO_REG+Z80_I: sprintf(buffer[which], "I:%02X", r->I); break; - case CPU_INFO_REG+Z80_AF2: sprintf(buffer[which], "AF'%04X", r->AF2.w.l); break; - case CPU_INFO_REG+Z80_BC2: sprintf(buffer[which], "BC'%04X", r->BC2.w.l); break; - case CPU_INFO_REG+Z80_DE2: sprintf(buffer[which], "DE'%04X", r->DE2.w.l); break; - case CPU_INFO_REG+Z80_HL2: sprintf(buffer[which], "HL'%04X", r->HL2.w.l); break; - case CPU_INFO_REG+Z80_IM: sprintf(buffer[which], "IM:%X", r->IM); break; - case CPU_INFO_REG+Z80_IFF1: sprintf(buffer[which], "IFF1:%X", r->IFF1); break; - case CPU_INFO_REG+Z80_IFF2: sprintf(buffer[which], "IFF2:%X", r->IFF2); break; - case CPU_INFO_REG+Z80_HALT: sprintf(buffer[which], "HALT:%X", r->HALT); break; - case CPU_INFO_REG+Z80_NMI_STATE: sprintf(buffer[which], "NMI:%X", r->nmi_state); break; - case CPU_INFO_REG+Z80_IRQ_STATE: sprintf(buffer[which], "IRQ:%X", r->irq_state); break; - case CPU_INFO_REG+Z80_DC0: if(Z80.irq_max >= 1) sprintf(buffer[which], "DC0:%X", r->int_state[0]); break; - case CPU_INFO_REG+Z80_DC1: if(Z80.irq_max >= 2) sprintf(buffer[which], "DC1:%X", r->int_state[1]); break; - case CPU_INFO_REG+Z80_DC2: if(Z80.irq_max >= 3) sprintf(buffer[which], "DC2:%X", r->int_state[2]); break; - case CPU_INFO_REG+Z80_DC3: if(Z80.irq_max >= 4) sprintf(buffer[which], "DC3:%X", r->int_state[3]); break; - case CPU_INFO_FLAGS: - sprintf(buffer[which], "%c%c%c%c%c%c%c%c", - r->AF.b.l & 0x80 ? 'S':'.', - r->AF.b.l & 0x40 ? 'Z':'.', - r->AF.b.l & 0x20 ? '5':'.', - r->AF.b.l & 0x10 ? 'H':'.', - r->AF.b.l & 0x08 ? '3':'.', - r->AF.b.l & 0x04 ? 'P':'.', - r->AF.b.l & 0x02 ? 'N':'.', - r->AF.b.l & 0x01 ? 'C':'.'); - break; - case CPU_INFO_NAME: return "Z80"; - case CPU_INFO_FAMILY: return "Zilog Z80"; - case CPU_INFO_VERSION: return "3.5"; - case CPU_INFO_FILE: return __FILE__; - case CPU_INFO_CREDITS: return "Copyright (C) 1998,1999,2000 Juergen Buchmueller, all rights reserved."; - case CPU_INFO_REG_LAYOUT: return (const char *)z80_reg_layout; - case CPU_INFO_WIN_LAYOUT: return (const char *)z80_win_layout; - } - return buffer[which]; -} - -unsigned z80_dasm( char *buffer, unsigned pc ) -{ -#ifdef MAME_DEBUG - return DasmZ80( buffer, pc ); -#else - sprintf( buffer, "$%02X", cpu_readop(pc) ); - return 1; -#endif -} - diff --git a/Frameworks/AudioOverload/aosdk/eng_qsf/z80.h b/Frameworks/AudioOverload/aosdk/eng_qsf/z80.h deleted file mode 100644 index 05d76c5b6..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_qsf/z80.h +++ /dev/null @@ -1,46 +0,0 @@ -#ifndef Z80_H -#define Z80_H - -#include "cpuintrf.h" -#include "osd_cpu.h" - -enum { - Z80_PC=1, Z80_SP, Z80_AF, Z80_BC, Z80_DE, Z80_HL, - Z80_IX, Z80_IY, Z80_AF2, Z80_BC2, Z80_DE2, Z80_HL2, - Z80_R, Z80_I, Z80_IM, Z80_IFF1, Z80_IFF2, Z80_HALT, - Z80_NMI_STATE, Z80_IRQ_STATE, Z80_DC0, Z80_DC1, Z80_DC2, Z80_DC3 -}; - -enum { - Z80_TABLE_op, - Z80_TABLE_cb, - Z80_TABLE_ed, - Z80_TABLE_xy, - Z80_TABLE_xycb, - Z80_TABLE_ex /* cycles counts for taken jr/jp/call and interrupt latency (rst opcodes) */ -}; - -extern int z80_ICount; /* T-state count */ - -extern void z80_init(void); -extern void z80_reset (void *param); -extern void z80_exit (void); -extern int z80_execute(int cycles); -extern void z80_burn(int cycles); -extern unsigned z80_get_context (void *dst); -extern void z80_set_context (void *src); -extern const void *z80_get_cycle_table (int which); -extern void z80_set_cycle_table (int which, void *new_tbl); -extern unsigned z80_get_reg (int regnum); -extern void z80_set_reg (int regnum, unsigned val); -extern void z80_set_irq_line(int irqline, int state); -extern void z80_set_irq_callback(int (*irq_callback)(int)); -extern const char *z80_info(void *context, int regnum); -extern unsigned z80_dasm(char *buffer, unsigned pc); - -#ifdef MAME_DEBUG -extern unsigned DasmZ80(char *buffer, unsigned pc); -#endif - -#endif - diff --git a/Frameworks/AudioOverload/aosdk/eng_qsf/z80dasm.c b/Frameworks/AudioOverload/aosdk/eng_qsf/z80dasm.c deleted file mode 100644 index 29cbb7692..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_qsf/z80dasm.c +++ /dev/null @@ -1,597 +0,0 @@ -/***************************************************************************** - * - * z80dasm.c - * Portable Z80 disassembler - * - * Copyright (C) 1998 Juergen Buchmueller, all rights reserved. - * - * - This source code is released as freeware for non-commercial purposes. - * - You are free to use and redistribute this code in modified or - * unmodified form, provided you list me in the credits. - * - If you modify this source code, you must add a notice to each modified - * source file that it has been changed. If you're a nice person, you - * will clearly mark each change too. :) - * - If you wish to use this for commercial purposes, please contact me at - * pullmoll@t-online.de - * - The author of this copywritten work reserves the right to change the - * terms of its usage and license at any time, including retroactively - * - This entire notice must remain in the source code. - * - *****************************************************************************/ - -#include -#include -#ifdef MAME_DEBUG -#include "driver.h" -#include "mamedbg.h" -#include "z80.h" - -enum e_mnemonics { - zADC ,zADD ,zAND ,zBIT ,zCALL ,zCCF ,zCP ,zCPD , - zCPDR ,zCPI ,zCPIR ,zCPL ,zDAA ,zDB ,zDEC ,zDI , - zDJNZ ,zEI ,zEX ,zEXX ,zHLT ,zIM ,zIN ,zINC , - zIND ,zINDR ,zINI ,zINIR ,zJP ,zJR ,zLD ,zLDD , - zLDDR ,zLDI ,zLDIR ,zNEG ,zNOP ,zOR ,zOTDR ,zOTIR , - zOUT ,zOUTD ,zOUTI ,zPOP ,zPUSH ,zRES ,zRET ,zRETI , - zRETN ,zRL ,zRLA ,zRLC ,zRLCA ,zRLD ,zRR ,zRRA , - zRRC ,zRRCA ,zRRD ,zRST ,zSBC ,zSCF ,zSET ,zSLA , - zSLL ,zSRA ,zSRL ,zSUB ,zXOR -}; - -static const char *s_mnemonic[] = { - "adc", "add", "and", "bit", "call","ccf", "cp", "cpd", - "cpdr","cpi", "cpir","cpl", "daa", "db", "dec", "di", - "djnz","ei", "ex", "exx", "halt","im", "in", "inc", - "ind", "indr","ini", "inir","jp", "jr", "ld", "ldd", - "lddr","ldi", "ldir","neg", "nop", "or", "otdr","otir", - "out", "outd","outi","pop", "push","res", "ret", "reti", - "retn","rl", "rla", "rlc", "rlca","rld", "rr", "rra", - "rrc", "rrca","rrd", "rst", "sbc", "scf", "set", "sla", - "sll", "sra", "srl", "sub", "xor " -}; - -typedef struct { - UINT8 access; - UINT8 mnemonic; - const char *arguments; -} z80dasm; - -#define _0 EA_NONE -#define _JP EA_ABS_PC -#define _JR EA_REL_PC -#define _RM EA_MEM_RD -#define _WM EA_MEM_WR -#define _RW EA_MEM_RDWR -#define _RP EA_PORT_RD -#define _WP EA_PORT_WR - -static z80dasm mnemonic_xx_cb[256]= { - {_RW,zRLC,"b=Y"}, {_RW,zRLC,"c=Y"}, {_RW,zRLC,"d=Y"}, {_RW,zRLC,"e=Y"}, - {_RW,zRLC,"h=Y"}, {_RW,zRLC,"l=Y"}, {_RW,zRLC,"Y"}, {_RW,zRLC,"a=Y"}, - {_RW,zRRC,"b=Y"}, {_RW,zRRC,"c=Y"}, {_RW,zRRC,"d=Y"}, {_RW,zRRC,"e=Y"}, - {_RW,zRRC,"h=Y"}, {_RW,zRRC,"l=Y"}, {_RW,zRRC,"Y"}, {_RW,zRRC,"a=Y"}, - {_RW,zRL,"b=Y"}, {_RW,zRL,"c=Y"}, {_RW,zRL,"d=Y"}, {_RW,zRL,"e=Y"}, - {_RW,zRL,"h=Y"}, {_RW,zRL,"l=Y"}, {_RW,zRL,"Y"}, {_RW,zRL,"a=Y"}, - {_RW,zRR,"b=Y"}, {_RW,zRR,"c=Y"}, {_RW,zRR,"d=Y"}, {_RW,zRR,"e=Y"}, - {_RW,zRR,"h=Y"}, {_RW,zRR,"l=Y"}, {_RW,zRR,"Y"}, {_RW,zRR,"a=Y"}, - {_RW,zSLA,"b=Y"}, {_RW,zSLA,"c=Y"}, {_RW,zSLA,"d=Y"}, {_RW,zSLA,"e=Y"}, - {_RW,zSLA,"h=Y"}, {_RW,zSLA,"l=Y"}, {_RW,zSLA,"Y"}, {_RW,zSLA,"a=Y"}, - {_RW,zSRA,"b=Y"}, {_RW,zSRA,"c=Y"}, {_RW,zSRA,"d=Y"}, {_RW,zSRA,"e=Y"}, - {_RW,zSRA,"h=Y"}, {_RW,zSRA,"l=Y"}, {_RW,zSRA,"Y"}, {_RW,zSRA,"a=Y"}, - {_RW,zSLL,"b=Y"}, {_RW,zSLL,"c=Y"}, {_RW,zSLL,"d=Y"}, {_RW,zSLL,"e=Y"}, - {_RW,zSLL,"h=Y"}, {_RW,zSLL,"l=Y"}, {_RW,zSLL,"Y"}, {_RW,zSLL,"a=Y"}, - {_RW,zSRL,"b=Y"}, {_RW,zSRL,"c=Y"}, {_RW,zSRL,"d=Y"}, {_RW,zSRL,"e=Y"}, - {_RW,zSRL,"h=Y"}, {_RW,zSRL,"l=Y"}, {_RW,zSRL,"Y"}, {_RW,zSRL,"a=Y"}, - {_RM,zBIT,"b=0,Y"}, {_RM,zBIT,"c=0,Y"}, {_RM,zBIT,"d=0,Y"}, {_RM,zBIT,"e=0,Y"}, - {_RM,zBIT,"h=0,Y"}, {_RM,zBIT,"l=0,Y"}, {_RM,zBIT,"0,Y"}, {_RM,zBIT,"a=0,Y"}, - {_RM,zBIT,"b=1,Y"}, {_RM,zBIT,"c=1,Y"}, {_RM,zBIT,"d=1,Y"}, {_RM,zBIT,"e=1,Y"}, - {_RM,zBIT,"h=1,Y"}, {_RM,zBIT,"l=1,Y"}, {_RM,zBIT,"1,Y"}, {_RM,zBIT,"a=1,Y"}, - {_RM,zBIT,"b=2,Y"}, {_RM,zBIT,"c=2,Y"}, {_RM,zBIT,"d=2,Y"}, {_RM,zBIT,"e=2,Y"}, - {_RM,zBIT,"h=2,Y"}, {_RM,zBIT,"l=2,Y"}, {_RM,zBIT,"2,Y"}, {_RM,zBIT,"a=2,Y"}, - {_RM,zBIT,"b=3,Y"}, {_RM,zBIT,"c=3,Y"}, {_RM,zBIT,"d=3,Y"}, {_RM,zBIT,"e=3,Y"}, - {_RM,zBIT,"h=3,Y"}, {_RM,zBIT,"l=3,Y"}, {_RM,zBIT,"3,Y"}, {_RM,zBIT,"a=3,Y"}, - {_RM,zBIT,"b=4,Y"}, {_RM,zBIT,"c=4,Y"}, {_RM,zBIT,"d=4,Y"}, {_RM,zBIT,"e=4,Y"}, - {_RM,zBIT,"h=4,Y"}, {_RM,zBIT,"l=4,Y"}, {_RM,zBIT,"4,Y"}, {_RM,zBIT,"a=4,Y"}, - {_RM,zBIT,"b=5,Y"}, {_RM,zBIT,"c=5,Y"}, {_RM,zBIT,"d=5,Y"}, {_RM,zBIT,"e=5,Y"}, - {_RM,zBIT,"h=5,Y"}, {_RM,zBIT,"l=5,Y"}, {_RM,zBIT,"5,Y"}, {_RM,zBIT,"a=5,Y"}, - {_RM,zBIT,"b=6,Y"}, {_RM,zBIT,"c=6,Y"}, {_RM,zBIT,"d=6,Y"}, {_RM,zBIT,"e=6,Y"}, - {_RM,zBIT,"h=6,Y"}, {_RM,zBIT,"l=6,Y"}, {_RM,zBIT,"6,Y"}, {_RM,zBIT,"a=6,Y"}, - {_RM,zBIT,"b=7,Y"}, {_RM,zBIT,"c=7,Y"}, {_RM,zBIT,"d=7,Y"}, {_RM,zBIT,"e=7,Y"}, - {_RM,zBIT,"h=7,Y"}, {_RM,zBIT,"l=7,Y"}, {_RM,zBIT,"7,Y"}, {_RM,zBIT,"a=7,Y"}, - {_WM,zRES,"b=0,Y"}, {_WM,zRES,"c=0,Y"}, {_WM,zRES,"d=0,Y"}, {_WM,zRES,"e=0,Y"}, - {_WM,zRES,"h=0,Y"}, {_WM,zRES,"l=0,Y"}, {_WM,zRES,"0,Y"}, {_WM,zRES,"a=0,Y"}, - {_WM,zRES,"b=1,Y"}, {_WM,zRES,"c=1,Y"}, {_WM,zRES,"d=1,Y"}, {_WM,zRES,"e=1,Y"}, - {_WM,zRES,"h=1,Y"}, {_WM,zRES,"l=1,Y"}, {_WM,zRES,"1,Y"}, {_WM,zRES,"a=1,Y"}, - {_WM,zRES,"b=2,Y"}, {_WM,zRES,"c=2,Y"}, {_WM,zRES,"d=2,Y"}, {_WM,zRES,"e=2,Y"}, - {_WM,zRES,"h=2,Y"}, {_WM,zRES,"l=2,Y"}, {_WM,zRES,"2,Y"}, {_WM,zRES,"a=2,Y"}, - {_WM,zRES,"b=3,Y"}, {_WM,zRES,"c=3,Y"}, {_WM,zRES,"d=3,Y"}, {_WM,zRES,"e=3,Y"}, - {_WM,zRES,"h=3,Y"}, {_WM,zRES,"l=3,Y"}, {_WM,zRES,"3,Y"}, {_WM,zRES,"a=3,Y"}, - {_WM,zRES,"b=4,Y"}, {_WM,zRES,"c=4,Y"}, {_WM,zRES,"d=4,Y"}, {_WM,zRES,"e=4,Y"}, - {_WM,zRES,"h=4,Y"}, {_WM,zRES,"l=4,Y"}, {_WM,zRES,"4,Y"}, {_WM,zRES,"a=4,Y"}, - {_WM,zRES,"b=5,Y"}, {_WM,zRES,"c=5,Y"}, {_WM,zRES,"d=5,Y"}, {_WM,zRES,"e=5,Y"}, - {_WM,zRES,"h=5,Y"}, {_WM,zRES,"l=5,Y"}, {_WM,zRES,"5,Y"}, {_WM,zRES,"a=5,Y"}, - {_WM,zRES,"b=6,Y"}, {_WM,zRES,"c=6,Y"}, {_WM,zRES,"d=6,Y"}, {_WM,zRES,"e=6,Y"}, - {_WM,zRES,"h=6,Y"}, {_WM,zRES,"l=6,Y"}, {_WM,zRES,"6,Y"}, {_WM,zRES,"a=6,Y"}, - {_WM,zRES,"b=7,Y"}, {_WM,zRES,"c=7,Y"}, {_WM,zRES,"d=7,Y"}, {_WM,zRES,"e=7,Y"}, - {_WM,zRES,"h=7,Y"}, {_WM,zRES,"l=7,Y"}, {_WM,zRES,"7,Y"}, {_WM,zRES,"a=7,Y"}, - {_WM,zSET,"b=0,Y"}, {_WM,zSET,"c=0,Y"}, {_WM,zSET,"d=0,Y"}, {_WM,zSET,"e=0,Y"}, - {_WM,zSET,"h=0,Y"}, {_WM,zSET,"l=0,Y"}, {_WM,zSET,"0,Y"}, {_WM,zSET,"a=0,Y"}, - {_WM,zSET,"b=1,Y"}, {_WM,zSET,"c=1,Y"}, {_WM,zSET,"d=1,Y"}, {_WM,zSET,"e=1,Y"}, - {_WM,zSET,"h=1,Y"}, {_WM,zSET,"l=1,Y"}, {_WM,zSET,"1,Y"}, {_WM,zSET,"a=1,Y"}, - {_WM,zSET,"b=2,Y"}, {_WM,zSET,"c=2,Y"}, {_WM,zSET,"d=2,Y"}, {_WM,zSET,"e=2,Y"}, - {_WM,zSET,"h=2,Y"}, {_WM,zSET,"l=2,Y"}, {_WM,zSET,"2,Y"}, {_WM,zSET,"a=2,Y"}, - {_WM,zSET,"b=3,Y"}, {_WM,zSET,"c=3,Y"}, {_WM,zSET,"d=3,Y"}, {_WM,zSET,"e=3,Y"}, - {_WM,zSET,"h=3,Y"}, {_WM,zSET,"l=3,Y"}, {_WM,zSET,"3,Y"}, {_WM,zSET,"a=3,Y"}, - {_WM,zSET,"b=4,Y"}, {_WM,zSET,"c=4,Y"}, {_WM,zSET,"d=4,Y"}, {_WM,zSET,"e=4,Y"}, - {_WM,zSET,"h=4,Y"}, {_WM,zSET,"l=4,Y"}, {_WM,zSET,"4,Y"}, {_WM,zSET,"a=4,Y"}, - {_WM,zSET,"b=5,Y"}, {_WM,zSET,"c=5,Y"}, {_WM,zSET,"d=5,Y"}, {_WM,zSET,"e=5,Y"}, - {_WM,zSET,"h=5,Y"}, {_WM,zSET,"l=5,Y"}, {_WM,zSET,"5,Y"}, {_WM,zSET,"a=5,Y"}, - {_WM,zSET,"b=6,Y"}, {_WM,zSET,"c=6,Y"}, {_WM,zSET,"d=6,Y"}, {_WM,zSET,"e=6,Y"}, - {_WM,zSET,"h=6,Y"}, {_WM,zSET,"l=6,Y"}, {_WM,zSET,"6,Y"}, {_WM,zSET,"a=6,Y"}, - {_WM,zSET,"b=7,Y"}, {_WM,zSET,"c=7,Y"}, {_WM,zSET,"d=7,Y"}, {_WM,zSET,"e=7,Y"}, - {_WM,zSET,"h=7,Y"}, {_WM,zSET,"l=7,Y"}, {_WM,zSET,"7,Y"}, {_WM,zSET,"a=7,Y"} -}; - -static z80dasm mnemonic_cb[256] = { - {_0, zRLC,"b"}, {_0, zRLC,"c"}, {_0, zRLC,"d"}, {_0, zRLC,"e"}, - {_0, zRLC,"h"}, {_0, zRLC,"l"}, {_RW,zRLC,"(hl)"}, {_0, zRLC,"a"}, - {_0, zRRC,"b"}, {_0, zRRC,"c"}, {_0, zRRC,"d"}, {_0, zRRC,"e"}, - {_0, zRRC,"h"}, {_0, zRRC,"l"}, {_RW,zRRC,"(hl)"}, {_0, zRRC,"a"}, - {_0, zRL,"b"}, {_0, zRL,"c"}, {_0, zRL,"d"}, {_0, zRL,"e"}, - {_0, zRL,"h"}, {_0, zRL,"l"}, {_RW,zRL,"(hl)"}, {_0, zRL,"a"}, - {_0, zRR,"b"}, {_0, zRR,"c"}, {_0, zRR,"d"}, {_0, zRR,"e"}, - {_0, zRR,"h"}, {_0, zRR,"l"}, {_RW,zRR,"(hl)"}, {_0, zRR,"a"}, - {_0, zSLA,"b"}, {_0, zSLA,"c"}, {_0, zSLA,"d"}, {_0, zSLA,"e"}, - {_0, zSLA,"h"}, {_0, zSLA,"l"}, {_RW,zSLA,"(hl)"}, {_0, zSLA,"a"}, - {_0, zSRA,"b"}, {_0, zSRA,"c"}, {_0, zSRA,"d"}, {_0, zSRA,"e"}, - {_0, zSRA,"h"}, {_0, zSRA,"l"}, {_RW,zSRA,"(hl)"}, {_0, zSRA,"a"}, - {_0, zSLL,"b"}, {_0, zSLL,"c"}, {_0, zSLL,"d"}, {_0, zSLL,"e"}, - {_0, zSLL,"h"}, {_0, zSLL,"l"}, {_RW,zSLL,"(hl)"}, {_0, zSLL,"a"}, - {_0, zSRL,"b"}, {_0, zSRL,"c"}, {_0, zSRL,"d"}, {_0, zSRL,"e"}, - {_0, zSRL,"h"}, {_0, zSRL,"l"}, {_RW,zSRL,"(hl)"}, {_0, zSRL,"a"}, - {_0, zBIT,"0,b"}, {_0, zBIT,"0,c"}, {_0, zBIT,"0,d"}, {_0, zBIT,"0,e"}, - {_0, zBIT,"0,h"}, {_0, zBIT,"0,l"}, {_RM,zBIT,"0,(hl)"},{_0, zBIT,"0,a"}, - {_0, zBIT,"1,b"}, {_0, zBIT,"1,c"}, {_0, zBIT,"1,d"}, {_0, zBIT,"1,e"}, - {_0, zBIT,"1,h"}, {_0, zBIT,"1,l"}, {_RM,zBIT,"1,(hl)"},{_0, zBIT,"1,a"}, - {_0, zBIT,"2,b"}, {_0, zBIT,"2,c"}, {_0, zBIT,"2,d"}, {_0, zBIT,"2,e"}, - {_0, zBIT,"2,h"}, {_0, zBIT,"2,l"}, {_RM,zBIT,"2,(hl)"},{_0, zBIT,"2,a"}, - {_0, zBIT,"3,b"}, {_0, zBIT,"3,c"}, {_0, zBIT,"3,d"}, {_0, zBIT,"3,e"}, - {_0, zBIT,"3,h"}, {_0, zBIT,"3,l"}, {_RM,zBIT,"3,(hl)"},{_0, zBIT,"3,a"}, - {_0, zBIT,"4,b"}, {_0, zBIT,"4,c"}, {_0, zBIT,"4,d"}, {_0, zBIT,"4,e"}, - {_0, zBIT,"4,h"}, {_0, zBIT,"4,l"}, {_RM,zBIT,"4,(hl)"},{_0, zBIT,"4,a"}, - {_0, zBIT,"5,b"}, {_0, zBIT,"5,c"}, {_0, zBIT,"5,d"}, {_0, zBIT,"5,e"}, - {_0, zBIT,"5,h"}, {_0, zBIT,"5,l"}, {_RM,zBIT,"5,(hl)"},{_0, zBIT,"5,a"}, - {_0, zBIT,"6,b"}, {_0, zBIT,"6,c"}, {_0, zBIT,"6,d"}, {_0, zBIT,"6,e"}, - {_0, zBIT,"6,h"}, {_0, zBIT,"6,l"}, {_RM,zBIT,"6,(hl)"},{_0, zBIT,"6,a"}, - {_0, zBIT,"7,b"}, {_0, zBIT,"7,c"}, {_0, zBIT,"7,d"}, {_0, zBIT,"7,e"}, - {_0, zBIT,"7,h"}, {_0, zBIT,"7,l"}, {_RM,zBIT,"7,(hl)"},{_0, zBIT,"7,a"}, - {_0, zRES,"0,b"}, {_0, zRES,"0,c"}, {_0, zRES,"0,d"}, {_0, zRES,"0,e"}, - {_0, zRES,"0,h"}, {_0, zRES,"0,l"}, {_WM,zRES,"0,(hl)"},{_0, zRES,"0,a"}, - {_0, zRES,"1,b"}, {_0, zRES,"1,c"}, {_0, zRES,"1,d"}, {_0, zRES,"1,e"}, - {_0, zRES,"1,h"}, {_0, zRES,"1,l"}, {_WM,zRES,"1,(hl)"},{_0, zRES,"1,a"}, - {_0, zRES,"2,b"}, {_0, zRES,"2,c"}, {_0, zRES,"2,d"}, {_0, zRES,"2,e"}, - {_0, zRES,"2,h"}, {_0, zRES,"2,l"}, {_WM,zRES,"2,(hl)"},{_0, zRES,"2,a"}, - {_0, zRES,"3,b"}, {_0, zRES,"3,c"}, {_0, zRES,"3,d"}, {_0, zRES,"3,e"}, - {_0, zRES,"3,h"}, {_0, zRES,"3,l"}, {_WM,zRES,"3,(hl)"},{_0, zRES,"3,a"}, - {_0, zRES,"4,b"}, {_0, zRES,"4,c"}, {_0, zRES,"4,d"}, {_0, zRES,"4,e"}, - {_0, zRES,"4,h"}, {_0, zRES,"4,l"}, {_WM,zRES,"4,(hl)"},{_0, zRES,"4,a"}, - {_0, zRES,"5,b"}, {_0, zRES,"5,c"}, {_0, zRES,"5,d"}, {_0, zRES,"5,e"}, - {_0, zRES,"5,h"}, {_0, zRES,"5,l"}, {_WM,zRES,"5,(hl)"},{_0, zRES,"5,a"}, - {_0, zRES,"6,b"}, {_0, zRES,"6,c"}, {_0, zRES,"6,d"}, {_0, zRES,"6,e"}, - {_0, zRES,"6,h"}, {_0, zRES,"6,l"}, {_WM,zRES,"6,(hl)"},{_0, zRES,"6,a"}, - {_0, zRES,"7,b"}, {_0, zRES,"7,c"}, {_0, zRES,"7,d"}, {_0, zRES,"7,e"}, - {_0, zRES,"7,h"}, {_0, zRES,"7,l"}, {_WM,zRES,"7,(hl)"},{_0, zRES,"7,a"}, - {_0, zSET,"0,b"}, {_0, zSET,"0,c"}, {_0, zSET,"0,d"}, {_0, zSET,"0,e"}, - {_0, zSET,"0,h"}, {_0, zSET,"0,l"}, {_WM,zSET,"0,(hl)"},{_0, zSET,"0,a"}, - {_0, zSET,"1,b"}, {_0, zSET,"1,c"}, {_0, zSET,"1,d"}, {_0, zSET,"1,e"}, - {_0, zSET,"1,h"}, {_0, zSET,"1,l"}, {_WM,zSET,"1,(hl)"},{_0, zSET,"1,a"}, - {_0, zSET,"2,b"}, {_0, zSET,"2,c"}, {_0, zSET,"2,d"}, {_0, zSET,"2,e"}, - {_0, zSET,"2,h"}, {_0, zSET,"2,l"}, {_WM,zSET,"2,(hl)"},{_0, zSET,"2,a"}, - {_0, zSET,"3,b"}, {_0, zSET,"3,c"}, {_0, zSET,"3,d"}, {_0, zSET,"3,e"}, - {_0, zSET,"3,h"}, {_0, zSET,"3,l"}, {_WM,zSET,"3,(hl)"},{_0, zSET,"3,a"}, - {_0, zSET,"4,b"}, {_0, zSET,"4,c"}, {_0, zSET,"4,d"}, {_0, zSET,"4,e"}, - {_0, zSET,"4,h"}, {_0, zSET,"4,l"}, {_WM,zSET,"4,(hl)"},{_0, zSET,"4,a"}, - {_0, zSET,"5,b"}, {_0, zSET,"5,c"}, {_0, zSET,"5,d"}, {_0, zSET,"5,e"}, - {_0, zSET,"5,h"}, {_0, zSET,"5,l"}, {_WM,zSET,"5,(hl)"},{_0, zSET,"5,a"}, - {_0, zSET,"6,b"}, {_0, zSET,"6,c"}, {_0, zSET,"6,d"}, {_0, zSET,"6,e"}, - {_0, zSET,"6,h"}, {_0, zSET,"6,l"}, {_WM,zSET,"6,(hl)"},{_0, zSET,"6,a"}, - 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{_0, zSBC,"a,b"}, {_0, zSBC,"a,c"}, {_0, zSBC,"a,d"}, {_0, zSBC,"a,e"}, - {_0, zSBC,"a,h"}, {_0, zSBC,"a,l"}, {_RM,zSBC,"a,(hl)"},{_0, zSBC,"a,a"}, - {_0, zAND,"b"}, {_0, zAND,"c"}, {_0, zAND,"d"}, {_0, zAND,"e"}, - {_0, zAND,"h"}, {_0, zAND,"l"}, {_RM,zAND,"(hl)"}, {_0, zAND,"a"}, - {_0, zXOR,"b"}, {_0, zXOR,"c"}, {_0, zXOR,"d"}, {_0, zXOR,"e"}, - {_0, zXOR,"h"}, {_0, zXOR,"l"}, {_RM,zXOR,"(hl)"}, {_0, zXOR,"a"}, - {_0, zOR,"b"}, {_0, zOR,"c"}, {_0, zOR,"d"}, {_0, zOR,"e"}, - {_0, zOR,"h"}, {_0, zOR,"l"}, {_RM,zOR,"(hl)"}, {_0, zOR,"a"}, - {_0, zCP,"b"}, {_0, zCP,"c"}, {_0, zCP,"d"}, {_0, zCP,"e"}, - {_0, zCP,"h"}, {_0, zCP,"l"}, {_RM,zCP,"(hl)"}, {_0, zCP,"a"}, - {_0, zRET,"nz"}, {_0, zPOP,"bc"}, {_JP,zJP,"nz,A"}, {_JP,zJP,"A"}, - {_JP,zCALL,"nz,A"}, {_0, zPUSH,"bc"}, {_0, zADD,"a,B"}, {_JP,zRST,"V"}, - {_0, zRET,"z"}, {_0, zRET,0}, {_JP,zJP,"z,A"}, {_0, zDB,"cb"}, - {_JP,zCALL,"z,A"}, {_JP,zCALL,"A"}, {_0, zADC,"a,B"}, {_JP,zRST,"V"}, - {_0, zRET,"nc"}, {_0, zPOP,"de"}, {_JP,zJP,"nc,A"}, {_WP,zOUT,"(P),a"}, - {_JP,zCALL,"nc,A"}, {_0, zPUSH,"de"}, {_0, zSUB,"B"}, {_JP,zRST,"V"}, - {_0, zRET,"c"}, {_0, zEXX,0}, {_JP,zJP,"c,A"}, {_RP,zIN,"a,(P)"}, - {_JP,zCALL,"c,A"}, {_0, zDB,"dd"}, {_0, zSBC,"a,B"}, {_JP,zRST,"V"}, - {_0, zRET,"po"}, {_0, zPOP,"hl"}, {_JP,zJP,"po,A"}, {_RW,zEX,"(sp),hl"}, - {_JP,zCALL,"po,A"}, {_0, zPUSH,"hl"}, {_0, zAND,"B"}, {_JP,zRST,"V"}, - {_0, zRET,"pe"}, {_JP,zJP,"(hl)"}, {_JP,zJP,"pe,A"}, {_0, zEX,"de,hl"}, - {_JP,zCALL,"pe,A"}, {_0, zDB,"ed"}, {_0, zXOR,"B"}, {_JP,zRST,"V"}, - {_0, zRET,"p"}, {_0, zPOP,"af"}, {_JP,zJP,"p,A"}, {_0, zDI,0}, - {_JP,zCALL,"p,A"}, {_0, zPUSH,"af"}, {_0, zOR,"B"}, {_JP,zRST,"V"}, - {_0, zRET,"m"}, {_0, zLD,"sp,hl"}, {_JP,zJP,"m,A"}, {_0, zEI,0}, - {_JP,zCALL,"m,A"}, {_0, zDB,"fd"}, {_0, zCP,"B"}, {_JP,zRST,"V"} -}; - -static char sign(INT8 offset) -{ - return (offset < 0)? '-':'+'; -} - -static int offs(INT8 offset) -{ - if (offset < 0) return -offset; - return offset; -} - -/**************************************************************************** - * Disassemble opcode at PC and return number of bytes it takes - ****************************************************************************/ -unsigned DasmZ80( char *buffer, unsigned pc ) -{ - z80dasm *d; - const char *symbol, *src; - const char *ixy; - char *dst; - unsigned PC = pc; - INT8 offset = 0; - UINT8 op, op1; - UINT16 ea = 0, xy = 0; - - ixy = "oops!!"; - dst = buffer; - symbol = NULL; - - op = cpu_readop( pc++ ); - op1 = 0; /* keep GCC happy */ - - switch (op) - { - case 0xcb: - op = cpu_readop(pc++); - d = &mnemonic_cb[op]; - break; - case 0xed: - op1 = cpu_readop(pc++); - d = &mnemonic_ed[op1]; - break; - case 0xdd: - ixy = "ix"; - op1 = cpu_readop(pc++); - if( op1 == 0xcb ) - { - offset = (INT8) cpu_readop_arg(pc++); - op1 = cpu_readop_arg(pc++); /* fourth byte from OP_RAM! */ - xy = z80_get_reg( Z80_IX ); - ea = (xy + offset) & 0xffff; - d = &mnemonic_xx_cb[op1]; - } - else d = &mnemonic_xx[op1]; - break; - case 0xfd: - ixy = "iy"; - op1 = cpu_readop(pc++); - if( op1 == 0xcb ) - { - offset = (INT8) cpu_readop_arg(pc++); - op1 = cpu_readop_arg(pc++); /* fourth byte from OP_RAM! */ - xy = z80_get_reg( Z80_IY ); - ea = (ea + offset) & 0xffff; - d = &mnemonic_xx_cb[op1]; - } - else d = &mnemonic_xx[op1]; - break; - default: - d = &mnemonic_main[op]; - break; - } - - if( d->arguments ) - { - dst += sprintf(dst, "%-4s ", s_mnemonic[d->mnemonic]); - src = d->arguments; - while( *src ) - { - switch( *src ) - { - case '?': /* illegal opcode */ - dst += sprintf( dst, "$%02x,$%02x", op, op1); - break; - case 'A': - ea = cpu_readop_arg(pc) + ( cpu_readop_arg((pc+1)&0xffff) << 8); - pc += 2; - symbol = set_ea_info(0, ea, EA_UINT16, d->access); - dst += sprintf( dst, "%s", symbol ); - break; - case 'B': /* Byte op arg */ - ea = cpu_readop_arg( pc++ ); - symbol = set_ea_info(1, ea, EA_UINT8, EA_VALUE); - dst += sprintf( dst, "%s", symbol ); - break; - case '(': /* Memory byte at (HL) */ - *dst++ = *src; - if( !strncmp( src, "(bc)", 4) ) - { - ea = z80_get_reg( Z80_BC ); - set_ea_info(0, ea, EA_UINT8, d->access); - } - else - if( !strncmp( src, "(de)", 4) ) - { - ea = z80_get_reg( Z80_DE ); - set_ea_info(0, ea, EA_UINT8, d->access); - } - else - if( !strncmp( src, "(hl)", 4) ) - { - ea = z80_get_reg( Z80_HL ); - if( d->access == EA_ABS_PC ) - set_ea_info(0, ea, EA_DEFAULT, EA_ABS_PC); - else - set_ea_info(0, ea, EA_UINT8, d->access); - } - else - if( !strncmp( src, "(sp)", 4) ) - { - ea = z80_get_reg( Z80_SP ); - set_ea_info(0, ea, EA_UINT16, d->access); - } - else - if( !strncmp( src, "(P)", 3) ) - { - ea = (z80_get_reg( Z80_AF ) & 0xff00) | cpu_readop_arg( pc ); - set_ea_info(0, ea, EA_UINT16, d->access); - } - else - if( !strncmp( src, "(c)", 3) ) - { - ea = z80_get_reg( Z80_BC ); - set_ea_info(0, ea, EA_UINT16, d->access); - } - else - if( !strncmp( src, "(I)", 3) ) - { - ea = xy; - set_ea_info(0, ea, EA_DEFAULT, d->access); - } - break; - case 'N': /* Immediate 16 bit */ - ea = cpu_readop_arg(pc) + ( cpu_readop_arg((pc+1)&0xffff) << 8 ); - pc += 2; - symbol = set_ea_info(1, ea, EA_UINT16, EA_VALUE ); - dst += sprintf( dst, "%s", symbol ); - break; - case 'O': /* Offset relative to PC */ - offset = (INT8) cpu_readop_arg(pc++); - symbol = set_ea_info(0, PC, offset + 2, d->access); - dst += sprintf( dst, "%s", symbol ); - break; - case 'P': /* Port number */ - ea = cpu_readop_arg( pc++ ); - dst += sprintf( dst, "$%02X", ea ); - break; - case 'V': /* Restart vector */ - ea = op & 0x38; - symbol = set_ea_info(0, ea, EA_UINT8, d->access); - dst += sprintf( dst, "%s", symbol ); - break; - case 'W': /* Memory address word */ - ea = cpu_readop_arg(pc) + ( cpu_readop_arg((pc+1)&0xffff) << 8); - pc += 2; - symbol = set_ea_info(0, ea, EA_UINT16, d->access); - dst += sprintf( dst, "%s", symbol ); - break; - case 'X': - offset = (INT8) cpu_readop_arg(pc++); - ea = (xy + offset) & 0xffff; - case 'Y': - symbol = set_ea_info(0, ea, EA_UINT8, d->access); - dst += sprintf( dst,"(%s%c$%02x)", ixy, sign(offset), offs(offset) ); - break; - case 'I': - dst += sprintf( dst, "%s", ixy); - break; - default: - *dst++ = *src; - } - src++; - } - *dst = '\0'; - } - else - { - dst += sprintf(dst, "%s", s_mnemonic[d->mnemonic]); - } - - return pc - PC; -} - -#endif - diff --git a/Frameworks/AudioOverload/aosdk/eng_qsf/z80dasm.h b/Frameworks/AudioOverload/aosdk/eng_qsf/z80dasm.h deleted file mode 100644 index aaca52045..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_qsf/z80dasm.h +++ /dev/null @@ -1,2 +0,0 @@ -extern int DasmZ80(char *buffer, int PC); - diff --git a/Frameworks/AudioOverload/aosdk/eng_ssf/eng_ssf.c b/Frameworks/AudioOverload/aosdk/eng_ssf/eng_ssf.c deleted file mode 100644 index 28cb40eac..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_ssf/eng_ssf.c +++ /dev/null @@ -1,323 +0,0 @@ -/* - Audio Overload SDK - SSF file format engine - - Copyright (c) 2007 R. Belmont and Richard Bannister. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - * Neither the names of R. Belmont and Richard Bannister nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -/* - -Sega driver commands: - -00 - NOP -01 - SEQUENCE_START -02 - SEQUENCE_STOP -03 - SEQUENCE_PAUSE -04 - SEQUENCE_CONTINUE -05 - SEQUENCE_VOLUME -06 - SEQUENCE_ALLSTOP -07 - SEQUENCE_TEMPO -08 - SEQUENCE_MAP -09 - HOST_MIDI -0A - VOLUME_ANALYZE_START -0B - VOLUME_ANALYZE_STOP -0C - DSP CLEAR -0D - ALL OFF -0E - SEQUENCE PAN -0F - N/A -10 - SOUND INITIALIZE -11 - Yamaha 3D check (8C) -12 - QSound check (8B) -13 - Yamaha 3D init (8D) -80 - CD level -81 - CD pan -82 - MASTER VOLUME -83 - EFFECT_CHANGE -84 - NOP -85 - PCM stream play start -86 - PCM stream play end -87 - MIXER_CHANGE -88 - Mixer parameter change -89 - Hardware check -8A - PCM parameter change -8B - QSound check -8C - Yamaha 3D check -8D - Yamaha 3D init - -*/ - -#include -#include -#include - -#include "ao.h" -#include "eng_protos.h" -#include "corlett.h" -#include "sat_hw.h" -#include "scsp.h" - -#define DEBUG_LOADER (0) - -static corlett_t *c = NULL; -static char psfby[256]; -static uint32 decaybegin, decayend, total_samples; - -void *scsp_start(const void *config); -void SCSP_Update(void *param, INT16 **inputs, INT16 **buf, int samples); - -int32 ssf_start(uint8 *buffer, uint32 length) -{ - uint8 *file, *lib_decoded, *lib_raw_file; - uint32 offset, plength, lengthMS, fadeMS; - uint64 file_len, lib_len, lib_raw_length; - corlett_t *lib; - char *libfile; - int i; - - // clear Saturn work RAM before we start scribbling in it - memset(sat_ram, 0, 512*1024); - - // Decode the current SSF - if (corlett_decode(buffer, length, &file, &file_len, &c) != AO_SUCCESS) - { - return AO_FAIL; - } - - #if DEBUG_LOADER - printf("%d bytes decoded\n", file_len); - #endif - - // Get the library file, if any - for (i=0; i<9; i++) - { - libfile = i ? c->libaux[i-1] : c->lib; - if (libfile[0] != 0) - { - uint64 tmp_length; - - #if DEBUG_LOADER - printf("Loading library: %s\n", c->lib); - #endif - if (ao_get_lib(libfile, &lib_raw_file, &tmp_length) != AO_SUCCESS) - { - return AO_FAIL; - } - lib_raw_length = tmp_length; - - if (corlett_decode(lib_raw_file, lib_raw_length, &lib_decoded, &lib_len, &lib) != AO_SUCCESS) - { - free(lib_raw_file); - return AO_FAIL; - } - - // Free up raw file - free(lib_raw_file); - - // patch the file into ram - offset = lib_decoded[0] | lib_decoded[1]<<8 | lib_decoded[2]<<16 | lib_decoded[3]<<24; - - // guard against invalid data - if ((offset + (lib_len-4)) > 0x7ffff) - { - lib_len = 0x80000-offset+4; - } - memcpy(&sat_ram[offset], lib_decoded+4, lib_len-4); - - // Dispose the corlett structure for the lib - we don't use it - free(lib); - free(lib_decoded); - } - } - - // now patch the file into RAM over the libraries - offset = file[3]<<24 | file[2]<<16 | file[1]<<8 | file[0]; - - // guard against invalid data - if ((offset + (file_len-4)) > 0x7ffff) - { - file_len = 0x80000-offset+4; - } - - memcpy(&sat_ram[offset], file+4, file_len-4); - - free(file); - - // Finally, set psfby tag - strcpy(psfby, "n/a"); - if (c) - { - for (i = 0; i < MAX_UNKNOWN_TAGS; i++) - { - if (!strcasecmp(c->tag_name[i], "psfby")) - strcpy(psfby, c->tag_data[i]); - } - } - - #if DEBUG_LOADER && 1 - { - FILE *f; - - f = fopen("satram.bin", "wb"); - fwrite(sat_ram, 512*1024, 1, f); - fclose(f); - } - #endif - - // now flip everything (this makes sense because he's using starscream) - for (i = 0; i < 512*1024; i+=2) - { - uint8 temp; - - temp = sat_ram[i]; - sat_ram[i] = sat_ram[i+1]; - sat_ram[i+1] = temp; - } - - sat_hw_init(); - - // now figure out the time in samples for the length/fade - lengthMS = psfTimeToMS(c->inf_length); - fadeMS = psfTimeToMS(c->inf_fade); - total_samples = 0; - - if (lengthMS == 0) - { - lengthMS = ~0; - } - - if (lengthMS == ~0) - { - decaybegin = lengthMS; - } - else - { - lengthMS = (lengthMS * 441) / 10; - fadeMS = (fadeMS * 441) / 10; - - decaybegin = lengthMS; - decayend = lengthMS + fadeMS; - } - - return AO_SUCCESS; -} - -int32 ssf_gen(int16 *buffer, uint32 samples) -{ - int i; - int16 output[44100/30], output2[44100/30]; - int16 *stereo[2]; - int16 *outp = buffer; - int opos; - - opos = 0; - for (i = 0; i < samples; i++) - { - m68k_execute((11300000/60)/735); - stereo[0] = &output[opos]; - stereo[1] = &output2[opos]; - SCSP_Update(NULL, NULL, stereo, 1); - opos++; - } - - for (i = 0; i < samples; i++) - { - // process the fade tags - if (total_samples >= decaybegin) - { - if (total_samples >= decayend) - { - // song is done here, call out as necessary to make your player stop - output[i] = 0; - output2[i] = 0; - } - else - { - int32 fader = 256 - (256*(total_samples - decaybegin)/(decayend-decaybegin)); - output[i] = (output[i] * fader)>>8; - output2[i] = (output2[i] * fader)>>8; - - total_samples++; - } - } - else - { - total_samples++; - } - - *outp++ = output[i]; - *outp++ = output2[i]; - } - - return AO_SUCCESS; -} - -int32 ssf_stop(void) -{ - scsp_stop(); - free(c); - - return AO_SUCCESS; -} - -int32 ssf_command(int32 command, int32 parameter) - -{ - switch (command) - { - case COMMAND_RESTART: - return AO_SUCCESS; - - } - return AO_FAIL; -} - -int32 ssf_fill_info(ao_display_info *info) -{ - if (c == NULL) - return AO_FAIL; - - strcpy(info->title[1], "Name: "); - sprintf(info->info[1], "%s", c->inf_title); - - strcpy(info->title[2], "Game: "); - sprintf(info->info[2], "%s", c->inf_game); - - strcpy(info->title[3], "Artist: "); - sprintf(info->info[3], "%s", c->inf_artist); - - strcpy(info->title[4], "Copyright: "); - sprintf(info->info[4], "%s", c->inf_copy); - - strcpy(info->title[5], "Year: "); - sprintf(info->info[5], "%s", c->inf_year); - - strcpy(info->title[6], "Length: "); - sprintf(info->info[6], "%s", c->inf_length); - - strcpy(info->title[7], "Fade: "); - sprintf(info->info[7], "%s", c->inf_fade); - - strcpy(info->title[8], "Ripper: "); - sprintf(info->info[8], "%s", psfby); - - return AO_SUCCESS; -} diff --git a/Frameworks/AudioOverload/aosdk/eng_ssf/m68k.h b/Frameworks/AudioOverload/aosdk/eng_ssf/m68k.h deleted file mode 100644 index 082ed4df6..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_ssf/m68k.h +++ /dev/null @@ -1,343 +0,0 @@ -#ifndef M68K__HEADER -#define M68K__HEADER - -/* ======================================================================== */ -/* ========================= LICENSING & COPYRIGHT ======================== */ -/* ======================================================================== */ -/* - * MUSASHI - * Version 3.3 - * - * A portable Motorola M680x0 processor emulation engine. - * Copyright 1998-2001 Karl Stenerud. All rights reserved. - * - * This code may be freely used for non-commercial purposes as long as this - * copyright notice remains unaltered in the source code and any binary files - * containing this code in compiled form. - * - * All other lisencing terms must be negotiated with the author - * (Karl Stenerud). - * - * The latest version of this code can be obtained at: - * http://kstenerud.cjb.net - */ - - - -/* ======================================================================== */ -/* ============================ GENERAL DEFINES =========================== */ - -/* ======================================================================== */ - -/* There are 7 levels of interrupt to the 68K. - * A transition from < 7 to 7 will cause a non-maskable interrupt (NMI). - */ -#define M68K_IRQ_NONE 0 -#define M68K_IRQ_1 1 -#define M68K_IRQ_2 2 -#define M68K_IRQ_3 3 -#define M68K_IRQ_4 4 -#define M68K_IRQ_5 5 -#define M68K_IRQ_6 6 -#define M68K_IRQ_7 7 - - -/* Special interrupt acknowledge values. - * Use these as special returns from the interrupt acknowledge callback - * (specified later in this header). - */ - -/* Causes an interrupt autovector (0x18 + interrupt level) to be taken. - * This happens in a real 68K if VPA or AVEC is asserted during an interrupt - * acknowledge cycle instead of DTACK. - */ -#define M68K_INT_ACK_AUTOVECTOR 0xffffffff - -/* Causes the spurious interrupt vector (0x18) to be taken - * This happens in a real 68K if BERR is asserted during the interrupt - * acknowledge cycle (i.e. no devices responded to the acknowledge). - */ -#define M68K_INT_ACK_SPURIOUS 0xfffffffe - - -/* CPU types for use in m68k_set_cpu_type() */ -enum -{ - M68K_CPU_TYPE_INVALID, - M68K_CPU_TYPE_68000, - M68K_CPU_TYPE_68010, - M68K_CPU_TYPE_68EC020, - M68K_CPU_TYPE_68020, - M68K_CPU_TYPE_68030, /* Supported by disassembler ONLY */ - M68K_CPU_TYPE_68040 /* Supported by disassembler ONLY */ -}; - -/* Registers used by m68k_get_reg() and m68k_set_reg() */ -typedef enum -{ - /* Real registers */ - M68K_REG_D0, /* Data registers */ - M68K_REG_D1, - M68K_REG_D2, - M68K_REG_D3, - M68K_REG_D4, - M68K_REG_D5, - M68K_REG_D6, - M68K_REG_D7, - M68K_REG_A0, /* Address registers */ - M68K_REG_A1, - M68K_REG_A2, - M68K_REG_A3, - M68K_REG_A4, - M68K_REG_A5, - M68K_REG_A6, - M68K_REG_A7, - M68K_REG_PC, /* Program Counter */ - M68K_REG_SR, /* Status Register */ - M68K_REG_SP, /* The current Stack Pointer (located in A7) */ - M68K_REG_USP, /* User Stack Pointer */ - M68K_REG_ISP, /* Interrupt Stack Pointer */ - M68K_REG_MSP, /* Master Stack Pointer */ - M68K_REG_SFC, /* Source Function Code */ - M68K_REG_DFC, /* Destination Function Code */ - M68K_REG_VBR, /* Vector Base Register */ - M68K_REG_CACR, /* Cache Control Register */ - M68K_REG_CAAR, /* Cache Address Register */ - - /* Assumed registers */ - /* These are cheat registers which emulate the 1-longword prefetch - * present in the 68000 and 68010. - */ - M68K_REG_PREF_ADDR, /* Last prefetch address */ - M68K_REG_PREF_DATA, /* Last prefetch data */ - - /* Convenience registers */ - M68K_REG_PPC, /* Previous value in the program counter */ - M68K_REG_IR, /* Instruction register */ - M68K_REG_CPU_TYPE /* Type of CPU being run */ -} m68k_register_t; - -/* ======================================================================== */ -/* ====================== FUNCTIONS CALLED BY THE CPU ===================== */ -/* ======================================================================== */ - -/* You will have to implement these functions */ - -/* read/write functions called by the CPU to access memory. - * while values used are 32 bits, only the appropriate number - * of bits are relevant (i.e. in write_memory_8, only the lower 8 bits - * of value should be written to memory). - * - * NOTE: I have separated the immediate and PC-relative memory fetches - * from the other memory fetches because some systems require - * differentiation between PROGRAM and DATA fetches (usually - * for security setups such as encryption). - * This separation can either be achieved by setting - * M68K_SEPARATE_READS in m68kconf.h and defining - * the read functions, or by setting M68K_EMULATE_FC and - * making a function code callback function. - * Using the callback offers better emulation coverage - * because you can also monitor whether the CPU is in SYSTEM or - * USER mode, but it is also slower. - */ - -/* Read from anywhere */ -unsigned int m68k_read_memory_8(unsigned int address); -unsigned int m68k_read_memory_16(unsigned int address); -unsigned int m68k_read_memory_32(unsigned int address); - -/* Read data immediately following the PC */ -//INLINE unsigned int m68k_read_immediate_16(unsigned int address); -//INLINE unsigned int m68k_read_immediate_32(unsigned int address); - -/* Read data relative to the PC */ -//INLINE unsigned int m68k_read_pcrelative_8(unsigned int address); -//INLINE unsigned int m68k_read_pcrelative_16(unsigned int address); -//INLINE unsigned int m68k_read_pcrelative_32(unsigned int address); - -/* Memory access for the disassembler */ -unsigned int m68k_read_disassembler_8 (unsigned int address); -unsigned int m68k_read_disassembler_16 (unsigned int address); -unsigned int m68k_read_disassembler_32 (unsigned int address); - -/* Write to anywhere */ -void m68k_write_memory_8(unsigned int address, unsigned int value); -void m68k_write_memory_16(unsigned int address, unsigned int value); -void m68k_write_memory_32(unsigned int address, unsigned int value); - -/* Special call to simulate undocumented 68k behavior when move.l with a - * predecrement destination mode is executed. - * To simulate real 68k behavior, first write the high word to - * [address+2], and then write the low word to [address]. - * - * Enable this functionality with M68K_SIMULATE_PD_WRITES in m68kconf.h. - */ -//INLINE void m68k_write_memory_32_pd(unsigned int address, unsigned int value); - - - -/* ======================================================================== */ -/* ============================== CALLBACKS =============================== */ -/* ======================================================================== */ - -/* These functions allow you to set callbacks to the host when specific events - * occur. Note that you must enable the corresponding value in m68kconf.h - * in order for these to do anything useful. - * Note: I have defined default callbacks which are used if you have enabled - * the corresponding #define in m68kconf.h but either haven't assigned a - * callback or have assigned a callback of NULL. - */ - -/* Set the callback for an interrupt acknowledge. - * You must enable M68K_EMULATE_INT_ACK in m68kconf.h. - * The CPU will call the callback with the interrupt level being acknowledged. - * The host program must return either a vector from 0x02-0xff, or one of the - * special interrupt acknowledge values specified earlier in this header. - * If this is not implemented, the CPU will always assume an autovectored - * interrupt, and will automatically clear the interrupt request when it - * services the interrupt. - * Default behavior: return M68K_INT_ACK_AUTOVECTOR. - */ -void m68k_set_int_ack_callback(int (*callback)(int int_level)); - - -/* Set the callback for a breakpoint acknowledge (68010+). - * You must enable M68K_EMULATE_BKPT_ACK in m68kconf.h. - * The CPU will call the callback with whatever was in the data field of the - * BKPT instruction for 68020+, or 0 for 68010. - * Default behavior: do nothing. - */ -void m68k_set_bkpt_ack_callback(void (*callback)(unsigned int data)); - - -/* Set the callback for the RESET instruction. - * You must enable M68K_EMULATE_RESET in m68kconf.h. - * The CPU calls this callback every time it encounters a RESET instruction. - * Default behavior: do nothing. - */ -void m68k_set_reset_instr_callback(void (*callback)(void)); - - -/* Set the callback for informing of a large PC change. - * You must enable M68K_MONITOR_PC in m68kconf.h. - * The CPU calls this callback with the new PC value every time the PC changes - * by a large value (currently set for changes by longwords). - * Default behavior: do nothing. - */ -void m68k_set_pc_changed_callback(void (*callback)(unsigned int new_pc)); - - -/* Set the callback for CPU function code changes. - * You must enable M68K_EMULATE_FC in m68kconf.h. - * The CPU calls this callback with the function code before every memory - * access to set the CPU's function code according to what kind of memory - * access it is (supervisor/user, program/data and such). - * Default behavior: do nothing. - */ -void m68k_set_fc_callback(void (*callback)(unsigned int new_fc)); - - -/* Set a callback for the instruction cycle of the CPU. - * You must enable M68K_INSTRUCTION_HOOK in m68kconf.h. - * The CPU calls this callback just before fetching the opcode in the - * instruction cycle. - * Default behavior: do nothing. - */ -void m68k_set_instr_hook_callback(void (*callback)(void)); - - - -/* ======================================================================== */ -/* ====================== FUNCTIONS TO ACCESS THE CPU ===================== */ -/* ======================================================================== */ - -/* Use this function to set the CPU type you want to emulate. - * Currently supported types are: M68K_CPU_TYPE_68000, M68K_CPU_TYPE_68010, - * M68K_CPU_TYPE_EC020, and M68K_CPU_TYPE_68020. - */ -void m68k_set_cpu_type(unsigned int cpu_type); - -/* Do whatever initialisations the core requires. Should be called - * at least once at init time. - */ -void m68k_init(void); - -/* Pulse the RESET pin on the CPU. - * You *MUST* reset the CPU at least once to initialize the emulation - * Note: If you didn't call m68k_set_cpu_type() before resetting - * the CPU for the first time, the CPU will be set to - * M68K_CPU_TYPE_68000. - */ -void m68k_pulse_reset(void); - -/* execute num_cycles worth of instructions. returns number of cycles used */ -int m68k_execute(int num_cycles); - -/* These functions let you read/write/modify the number of cycles left to run - * while m68k_execute() is running. - * These are useful if the 68k accesses a memory-mapped port on another device - * that requires immediate processing by another CPU. - */ -int m68k_cycles_run(void); /* Number of cycles run so far */ -int m68k_cycles_remaining(void); /* Number of cycles left */ -void m68k_modify_timeslice(int cycles); /* Modify cycles left */ -void m68k_end_timeslice(void); /* End timeslice now */ - -/* Set the IPL0-IPL2 pins on the CPU (IRQ). - * A transition from < 7 to 7 will cause a non-maskable interrupt (NMI). - * Setting IRQ to 0 will clear an interrupt request. - */ -void m68k_set_irq(unsigned int int_level); - - -/* Halt the CPU as if you pulsed the HALT pin. */ -void m68k_pulse_halt(void); - - -/* Context switching to allow multiple CPUs */ - -/* Get the size of the cpu context in bytes */ -unsigned int m68k_context_size(void); - -/* Get a cpu context */ -unsigned int m68k_get_context(void* dst); - -/* set the current cpu context */ -void m68k_set_context(void* dst); - -/* Register the CPU state information */ -void m68k_state_register(const char *type); - - -/* Peek at the internals of a CPU context. This can either be a context - * retrieved using m68k_get_context() or the currently running context. - * If context is NULL, the currently running CPU context will be used. - */ -unsigned int m68k_get_reg(void* context, m68k_register_t reg); - -/* Poke values into the internals of the currently running CPU context */ -void m68k_set_reg(m68k_register_t reg, unsigned int value); - -/* Check if an instruction is valid for the specified CPU type */ -unsigned int m68k_is_valid_instruction(unsigned int instruction, unsigned int cpu_type); - -/* Disassemble 1 instruction using the epecified CPU type at pc. Stores - * disassembly in str_buff and returns the size of the instruction in bytes. - */ -unsigned int m68k_disassemble(char* str_buff, unsigned int pc, unsigned int cpu_type); - - -/* ======================================================================== */ -/* ============================= CONFIGURATION ============================ */ -/* ======================================================================== */ - -/* Import the configuration for this build */ -#include "m68kconf.h" - - - -/* ======================================================================== */ -/* ============================== END OF FILE ============================= */ -/* ======================================================================== */ - -#endif /* M68K__HEADER */ diff --git a/Frameworks/AudioOverload/aosdk/eng_ssf/m68k_in.c b/Frameworks/AudioOverload/aosdk/eng_ssf/m68k_in.c deleted file mode 100644 index 65e317efd..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_ssf/m68k_in.c +++ /dev/null @@ -1,10336 +0,0 @@ -/* -must fix: - callm - chk -*/ -/* ======================================================================== */ -/* ========================= LICENSING & COPYRIGHT ======================== */ -/* ======================================================================== */ -/* - * MUSASHI - * Version 3.3 - * - * A portable Motorola M680x0 processor emulation engine. - * Copyright 1998-2001 Karl Stenerud. All rights reserved. - * - * This code may be freely used for non-commercial purposes as long as this - * copyright notice remains unaltered in the source code and any binary files - * containing this code in compiled form. - * - * All other lisencing terms must be negotiated with the author - * (Karl Stenerud). - * - * The latest version of this code can be obtained at: - * http://kstenerud.cjb.net - */ - -/* Special thanks to Bart Trzynadlowski for his insight into the - * undocumented features of this chip: - * - * http://dynarec.com/~bart/files/68knotes.txt - */ - - -/* Input file for m68kmake - * ----------------------- - * - * All sections begin with 80 X's in a row followed by an end-of-line - * sequence. - * After this, m68kmake will expect to find one of the following section - * identifiers: - * M68KMAKE_PROTOTYPE_HEADER - header for opcode handler prototypes - * M68KMAKE_PROTOTYPE_FOOTER - footer for opcode handler prototypes - * M68KMAKE_TABLE_HEADER - header for opcode handler jumptable - * M68KMAKE_TABLE_FOOTER - footer for opcode handler jumptable - * M68KMAKE_TABLE_BODY - the table itself - * M68KMAKE_OPCODE_HANDLER_HEADER - header for opcode handler implementation - * M68KMAKE_OPCODE_HANDLER_FOOTER - footer for opcode handler implementation - * M68KMAKE_OPCODE_HANDLER_BODY - body section for opcode handler implementation - * - * NOTE: M68KMAKE_OPCODE_HANDLER_BODY must be last in the file and - * M68KMAKE_TABLE_BODY must be second last in the file. - * - * The M68KMAKE_OPHANDLER_BODY section contains the opcode handler - * primitives themselves. Each opcode handler begins with: - * M68KMAKE_OP(A, B, C, D) - * - * where A is the opcode handler name, B is the size of the operation, - * C denotes any special processing mode, and D denotes a specific - * addressing mode. - * For C and D where nothing is specified, use "." - * - * Example: - * M68KMAKE_OP(abcd, 8, rr, .) abcd, size 8, register to register, default EA - * M68KMAKE_OP(abcd, 8, mm, ax7) abcd, size 8, memory to memory, register X is A7 - * M68KMAKE_OP(tst, 16, ., pcix) tst, size 16, PCIX addressing - * - * All opcode handler primitives end with a closing curly brace "}" at column 1 - * - * NOTE: Do not place a M68KMAKE_OP() directive inside the opcode handler, - * and do not put a closing curly brace at column 1 unless it is - * marking the end of the handler! - * - * Inside the handler, m68kmake will recognize M68KMAKE_GET_OPER_xx_xx, - * M68KMAKE_GET_EA_xx_xx, and M68KMAKE_CC directives, and create multiple - * opcode handlers to handle variations in the opcode handler. - * Note: M68KMAKE_CC will only be interpreted in condition code opcodes. - * As well, M68KMAKE_GET_EA_xx_xx and M68KMAKE_GET_OPER_xx_xx will only - * be interpreted on instructions where the corresponding table entry - * specifies multiple effective addressing modes. - * Example: - * clr 32 . . 0100001010...... A+-DXWL... U U U 12 6 4 - * - * This table entry says that the clr.l opcde has 7 variations (A+-DXWL). - * It is run in user or supervisor mode for all CPUs, and uses 12 cycles for - * 68000, 6 cycles for 68010, and 4 cycles for 68020. - */ - -XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -M68KMAKE_PROTOTYPE_HEADER - -#ifndef M68KOPS__HEADER -#define M68KOPS__HEADER - -/* ======================================================================== */ -/* ============================ OPCODE HANDLERS =========================== */ -/* ======================================================================== */ - - - -XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -M68KMAKE_PROTOTYPE_FOOTER - - -/* Build the opcode handler table */ -void m68ki_build_opcode_table(void); - -extern void (*m68ki_instruction_jump_table[0x10000])(void); /* opcode handler jump table */ -extern unsigned char m68ki_cycles[][0x10000]; - - -/* ======================================================================== */ -/* ============================== END OF FILE ============================= */ -/* ======================================================================== */ - -#endif /* M68KOPS__HEADER */ - - - -XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -M68KMAKE_TABLE_HEADER - -/* ======================================================================== */ -/* ========================= OPCODE TABLE BUILDER ========================= */ -/* ======================================================================== */ - -#include "m68kops.h" - -#define NUM_CPU_TYPES 3 - -void (*m68ki_instruction_jump_table[0x10000])(void); /* opcode handler jump table */ -unsigned char m68ki_cycles[NUM_CPU_TYPES][0x10000]; /* Cycles used by CPU type */ - -/* This is used to generate the opcode handler jump table */ -typedef struct -{ - void (*opcode_handler)(void); /* handler function */ - unsigned int mask; /* mask on opcode */ - unsigned int match; /* what to match after masking */ - unsigned char cycles[NUM_CPU_TYPES]; /* cycles each cpu type takes */ -} opcode_handler_struct; - - -/* Opcode handler table */ -static opcode_handler_struct m68k_opcode_handler_table[] = -{ -/* function mask match 000 010 020 */ - - - -XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -M68KMAKE_TABLE_FOOTER - - {0, 0, 0, {0, 0, 0}} -}; - - -/* Build the opcode handler jump table */ -void m68ki_build_opcode_table(void) -{ - opcode_handler_struct *ostruct; - int instr; - int i; - int j; - int k; - - for(i = 0; i < 0x10000; i++) - { - /* default to illegal */ - m68ki_instruction_jump_table[i] = m68k_op_illegal; - for(k=0;kmask != 0xff00) - { - for(i = 0;i < 0x10000;i++) - { - if((i & ostruct->mask) == ostruct->match) - { - m68ki_instruction_jump_table[i] = ostruct->opcode_handler; - for(k=0;kcycles[k]; - } - } - ostruct++; - } - while(ostruct->mask == 0xff00) - { - for(i = 0;i <= 0xff;i++) - { - m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler; - for(k=0;kmatch | i] = ostruct->cycles[k]; - } - ostruct++; - } - while(ostruct->mask == 0xf1f8) - { - for(i = 0;i < 8;i++) - { - for(j = 0;j < 8;j++) - { - instr = ostruct->match | (i << 9) | j; - m68ki_instruction_jump_table[instr] = ostruct->opcode_handler; - for(k=0;kcycles[k]; - if((instr & 0xf000) == 0xe000 && (!(instr & 0x20))) - m68ki_cycles[0][instr] = m68ki_cycles[1][instr] = ostruct->cycles[k] + ((((j-1)&7)+1)<<1); - } - } - ostruct++; - } - while(ostruct->mask == 0xfff0) - { - for(i = 0;i <= 0x0f;i++) - { - m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler; - for(k=0;kmatch | i] = ostruct->cycles[k]; - } - ostruct++; - } - while(ostruct->mask == 0xf1ff) - { - for(i = 0;i <= 0x07;i++) - { - m68ki_instruction_jump_table[ostruct->match | (i << 9)] = ostruct->opcode_handler; - for(k=0;kmatch | (i << 9)] = ostruct->cycles[k]; - } - ostruct++; - } - while(ostruct->mask == 0xfff8) - { - for(i = 0;i <= 0x07;i++) - { - m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler; - for(k=0;kmatch | i] = ostruct->cycles[k]; - } - ostruct++; - } - while(ostruct->mask == 0xffff) - { - m68ki_instruction_jump_table[ostruct->match] = ostruct->opcode_handler; - for(k=0;kmatch] = ostruct->cycles[k]; - ostruct++; - } -} - - -/* ======================================================================== */ -/* ============================== END OF FILE ============================= */ -/* ======================================================================== */ - - - -XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -M68KMAKE_OPCODE_HANDLER_HEADER - -#include "m68kcpu.h" - -/* ======================================================================== */ -/* ========================= INSTRUCTION HANDLERS ========================= */ -/* ======================================================================== */ - - - -XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -M68KMAKE_OPCODE_HANDLER_FOOTER - -/* ======================================================================== */ -/* ============================== END OF FILE ============================= */ -/* ======================================================================== */ - - - -XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -M68KMAKE_TABLE_BODY - -The following table is arranged as follows: - -name: Opcode mnemonic - -size: Operation size - -spec proc: Special processing mode: - .: normal - s: static operand - r: register operand - rr: register to register - mm: memory to memory - er: effective address to register - re: register to effective address - dd: data register to data register - da: data register to address register - aa: address register to address register - cr: control register to register - rc: register to control register - toc: to condition code register - tos: to status register - tou: to user stack pointer - frc: from condition code register - frs: from status register - fru: from user stack pointer - * for move.x, the special processing mode is a specific - destination effective addressing mode. - -spec ea: Specific effective addressing mode: - .: normal - i: immediate - d: data register - a: address register - ai: address register indirect - pi: address register indirect with postincrement - pd: address register indirect with predecrement - di: address register indirect with displacement - ix: address register indirect with index - aw: absolute word address - al: absolute long address - pcdi: program counter relative with displacement - pcix: program counter relative with index - a7: register specified in instruction is A7 - ax7: register field X of instruction is A7 - ay7: register field Y of instruction is A7 - axy7: register fields X and Y of instruction are A7 - -bit pattern: Pattern to recognize this opcode. "." means don't care. - -allowed ea: List of allowed addressing modes: - .: not present - A: address register indirect - +: ARI (address register indirect) with postincrement - -: ARI with predecrement - D: ARI with displacement - X: ARI with index - W: absolute word address - L: absolute long address - d: program counter indirect with displacement - x: program counter indirect with index - I: immediate -mode: CPU operating mode for each cpu type. U = user or supervisor, - S = supervisor only, "." = opcode not present. - -cpu cycles: Base number of cycles required to execute this opcode on the - specified CPU type. - Use "." if CPU does not have this opcode. - - - - spec spec allowed ea mode cpu cycles -name size proc ea bit pattern A+-DXWLdxI 0 1 2 000 010 020 comments -====== ==== ==== ==== ================ ========== = = = === === === ============= -M68KMAKE_TABLE_START -1010 0 . . 1010............ .......... U U U 4 4 4 -1111 0 . . 1111............ .......... U U U 4 4 4 -abcd 8 rr . 1100...100000... .......... U U U 6 6 4 -abcd 8 mm ax7 1100111100001... .......... U U U 18 18 16 -abcd 8 mm ay7 1100...100001111 .......... U U U 18 18 16 -abcd 8 mm axy7 1100111100001111 .......... U U U 18 18 16 -abcd 8 mm . 1100...100001... .......... U U U 18 18 16 -add 8 er d 1101...000000... .......... U U U 4 4 2 -add 8 er . 1101...000...... A+-DXWLdxI U U U 4 4 2 -add 16 er d 1101...001000... .......... U U U 4 4 2 -add 16 er a 1101...001001... .......... U U U 4 4 2 -add 16 er . 1101...001...... A+-DXWLdxI U U U 4 4 2 -add 32 er d 1101...010000... .......... U U U 6 6 2 -add 32 er a 1101...010001... .......... U U U 6 6 2 -add 32 er . 1101...010...... A+-DXWLdxI U U U 6 6 2 -add 8 re . 1101...100...... A+-DXWL... U U U 8 8 4 -add 16 re . 1101...101...... A+-DXWL... U U U 8 8 4 -add 32 re . 1101...110...... A+-DXWL... U U U 12 12 4 -adda 16 . d 1101...011000... .......... U U U 8 8 2 -adda 16 . a 1101...011001... .......... U U U 8 8 2 -adda 16 . . 1101...011...... A+-DXWLdxI U U U 8 8 2 -adda 32 . d 1101...111000... .......... U U U 6 6 2 -adda 32 . a 1101...111001... .......... U U U 6 6 2 -adda 32 . . 1101...111...... A+-DXWLdxI U U U 6 6 2 -addi 8 . d 0000011000000... .......... U U U 8 8 2 -addi 8 . . 0000011000...... A+-DXWL... U U U 12 12 4 -addi 16 . d 0000011001000... .......... U U U 8 8 2 -addi 16 . . 0000011001...... A+-DXWL... U U U 12 12 4 -addi 32 . d 0000011010000... .......... U U U 16 14 2 -addi 32 . . 0000011010...... A+-DXWL... U U U 20 20 4 -addq 8 . d 0101...000000... .......... U U U 4 4 2 -addq 8 . . 0101...000...... A+-DXWL... U U U 8 8 4 -addq 16 . d 0101...001000... .......... U U U 4 4 2 -addq 16 . a 0101...001001... .......... U U U 4 4 2 -addq 16 . . 0101...001...... A+-DXWL... U U U 8 8 4 -addq 32 . d 0101...010000... .......... U U U 8 8 2 -addq 32 . a 0101...010001... .......... U U U 8 8 2 -addq 32 . . 0101...010...... A+-DXWL... U U U 12 12 4 -addx 8 rr . 1101...100000... .......... U U U 4 4 2 -addx 16 rr . 1101...101000... .......... U U U 4 4 2 -addx 32 rr . 1101...110000... .......... U U U 8 6 2 -addx 8 mm ax7 1101111100001... .......... U U U 18 18 12 -addx 8 mm ay7 1101...100001111 .......... U U U 18 18 12 -addx 8 mm axy7 1101111100001111 .......... U U U 18 18 12 -addx 8 mm . 1101...100001... .......... U U U 18 18 12 -addx 16 mm . 1101...101001... .......... U U U 18 18 12 -addx 32 mm . 1101...110001... .......... U U U 30 30 12 -and 8 er d 1100...000000... .......... U U U 4 4 2 -and 8 er . 1100...000...... A+-DXWLdxI U U U 4 4 2 -and 16 er d 1100...001000... .......... U U U 4 4 2 -and 16 er . 1100...001...... A+-DXWLdxI U U U 4 4 2 -and 32 er d 1100...010000... .......... U U U 6 6 2 -and 32 er . 1100...010...... A+-DXWLdxI U U U 6 6 2 -and 8 re . 1100...100...... A+-DXWL... U U U 8 8 4 -and 16 re . 1100...101...... A+-DXWL... U U U 8 8 4 -and 32 re . 1100...110...... A+-DXWL... U U U 12 12 4 -andi 16 toc . 0000001000111100 .......... U U U 20 16 12 -andi 16 tos . 0000001001111100 .......... S S S 20 16 12 -andi 8 . d 0000001000000... .......... U U U 8 8 2 -andi 8 . . 0000001000...... A+-DXWL... U U U 12 12 4 -andi 16 . d 0000001001000... .......... U U U 8 8 2 -andi 16 . . 0000001001...... A+-DXWL... U U U 12 12 4 -andi 32 . d 0000001010000... .......... U U U 14 14 2 -andi 32 . . 0000001010...... A+-DXWL... U U U 20 20 4 -asr 8 s . 1110...000000... .......... U U U 6 6 6 -asr 16 s . 1110...001000... .......... U U U 6 6 6 -asr 32 s . 1110...010000... .......... U U U 8 8 6 -asr 8 r . 1110...000100... .......... U U U 6 6 6 -asr 16 r . 1110...001100... .......... U U U 6 6 6 -asr 32 r . 1110...010100... .......... U U U 8 8 6 -asr 16 . . 1110000011...... A+-DXWL... U U U 8 8 5 -asl 8 s . 1110...100000... .......... U U U 6 6 8 -asl 16 s . 1110...101000... .......... U U U 6 6 8 -asl 32 s . 1110...110000... .......... U U U 8 8 8 -asl 8 r . 1110...100100... .......... U U U 6 6 8 -asl 16 r . 1110...101100... .......... U U U 6 6 8 -asl 32 r . 1110...110100... .......... U U U 8 8 8 -asl 16 . . 1110000111...... A+-DXWL... U U U 8 8 6 -bcc 8 . . 0110............ .......... U U U 8 8 6 -bcc 16 . . 0110....00000000 .......... U U U 10 10 6 -bcc 32 . . 0110....11111111 .......... . . U . . 6 -bchg 8 r . 0000...101...... A+-DXWL... U U U 8 8 4 -bchg 32 r d 0000...101000... .......... U U U 8 8 4 -bchg 8 s . 0000100001...... A+-DXWL... U U U 12 12 4 -bchg 32 s d 0000100001000... .......... U U U 12 12 4 -bclr 8 r . 0000...110...... A+-DXWL... U U U 8 10 4 -bclr 32 r d 0000...110000... .......... U U U 10 10 4 -bclr 8 s . 0000100010...... A+-DXWL... U U U 12 12 4 -bclr 32 s d 0000100010000... .......... U U U 14 14 4 -bfchg 32 . d 1110101011000... .......... . . U . . 12 timing not quite correct -bfchg 32 . . 1110101011...... A..DXWL... . . U . . 20 -bfclr 32 . d 1110110011000... .......... . . U . . 12 -bfclr 32 . . 1110110011...... A..DXWL... . . U . . 20 -bfexts 32 . d 1110101111000... .......... . . U . . 8 -bfexts 32 . . 1110101111...... A..DXWLdx. . . U . . 15 -bfextu 32 . d 1110100111000... .......... . . U . . 8 -bfextu 32 . . 1110100111...... A..DXWLdx. . . U . . 15 -bfffo 32 . d 1110110111000... .......... . . U . . 18 -bfffo 32 . . 1110110111...... A..DXWLdx. . . U . . 28 -bfins 32 . d 1110111111000... .......... . . U . . 10 -bfins 32 . . 1110111111...... A..DXWL... . . U . . 17 -bfset 32 . d 1110111011000... .......... . . U . . 12 -bfset 32 . . 1110111011...... A..DXWL... . . U . . 20 -bftst 32 . d 1110100011000... .......... . . U . . 6 -bftst 32 . . 1110100011...... A..DXWLdx. . . U . . 13 -bkpt 0 . . 0100100001001... .......... . U U . 10 10 -bra 8 . . 01100000........ .......... U U U 10 10 10 -bra 16 . . 0110000000000000 .......... U U U 10 10 10 -bra 32 . . 0110000011111111 .......... U U U . . 10 -bset 32 r d 0000...111000... .......... U U U 8 8 4 -bset 8 r . 0000...111...... A+-DXWL... U U U 8 8 4 -bset 8 s . 0000100011...... A+-DXWL... U U U 12 12 4 -bset 32 s d 0000100011000... .......... U U U 12 12 4 -bsr 8 . . 01100001........ .......... U U U 18 18 7 -bsr 16 . . 0110000100000000 .......... U U U 18 18 7 -bsr 32 . . 0110000111111111 .......... . . U . . 7 -btst 8 r . 0000...100...... A+-DXWLdxI U U U 4 4 4 -btst 32 r d 0000...100000... .......... U U U 6 6 4 -btst 8 s . 0000100000...... A+-DXWLdx. U U U 8 8 4 -btst 32 s d 0000100000000... .......... U U U 10 10 4 -callm 32 . . 0000011011...... A..DXWLdx. . . U . . 60 not properly emulated -cas 8 . . 0000101011...... A+-DXWL... . . U . . 12 -cas 16 . . 0000110011...... A+-DXWL... . . U . . 12 -cas 32 . . 0000111011...... A+-DXWL... . . U . . 12 -cas2 16 . . 0000110011111100 .......... . . U . . 12 -cas2 32 . . 0000111011111100 .......... . . U . . 12 -chk 16 . d 0100...110000... .......... U U U 10 8 8 -chk 16 . . 0100...110...... A+-DXWLdxI U U U 10 8 8 -chk 32 . d 0100...100000... .......... . . U . . 8 -chk 32 . . 0100...100...... A+-DXWLdxI . . U . . 8 -chk2cmp2 8 . pcdi 0000000011111010 .......... . . U . . 23 -chk2cmp2 8 . pcix 0000000011111011 .......... . . U . . 23 -chk2cmp2 8 . . 0000000011...... A..DXWL... . . U . . 18 -chk2cmp2 16 . pcdi 0000001011111010 .......... . . U . . 23 -chk2cmp2 16 . pcix 0000001011111011 .......... . . U . . 23 -chk2cmp2 16 . . 0000001011...... A..DXWL... . . U . . 18 -chk2cmp2 32 . pcdi 0000010011111010 .......... . . U . . 23 -chk2cmp2 32 . pcix 0000010011111011 .......... . . U . . 23 -chk2cmp2 32 . . 0000010011...... A..DXWL... . . U . . 18 -clr 8 . d 0100001000000... .......... U U U 4 4 2 -clr 8 . . 0100001000...... A+-DXWL... U U U 8 4 4 -clr 16 . d 0100001001000... .......... U U U 4 4 2 -clr 16 . . 0100001001...... A+-DXWL... U U U 8 4 4 -clr 32 . d 0100001010000... .......... U U U 6 6 2 -clr 32 . . 0100001010...... A+-DXWL... U U U 12 6 4 -cmp 8 . d 1011...000000... .......... U U U 4 4 2 -cmp 8 . . 1011...000...... A+-DXWLdxI U U U 4 4 2 -cmp 16 . d 1011...001000... .......... U U U 4 4 2 -cmp 16 . a 1011...001001... .......... U U U 4 4 2 -cmp 16 . . 1011...001...... A+-DXWLdxI U U U 4 4 2 -cmp 32 . d 1011...010000... .......... U U U 6 6 2 -cmp 32 . a 1011...010001... .......... U U U 6 6 2 -cmp 32 . . 1011...010...... A+-DXWLdxI U U U 6 6 2 -cmpa 16 . d 1011...011000... .......... U U U 6 6 4 -cmpa 16 . a 1011...011001... .......... U U U 6 6 4 -cmpa 16 . . 1011...011...... A+-DXWLdxI U U U 6 6 4 -cmpa 32 . d 1011...111000... .......... U U U 6 6 4 -cmpa 32 . a 1011...111001... .......... U U U 6 6 4 -cmpa 32 . . 1011...111...... A+-DXWLdxI U U U 6 6 4 -cmpi 8 . d 0000110000000... .......... U U U 8 8 2 -cmpi 8 . . 0000110000...... A+-DXWL... U U U 8 8 2 -cmpi 8 . pcdi 0000110000111010 .......... . . U . . 7 -cmpi 8 . pcix 0000110000111011 .......... . . U . . 9 -cmpi 16 . d 0000110001000... .......... U U U 8 8 2 -cmpi 16 . . 0000110001...... A+-DXWL... U U U 8 8 2 -cmpi 16 . pcdi 0000110001111010 .......... . . U . . 7 -cmpi 16 . pcix 0000110001111011 .......... . . U . . 9 -cmpi 32 . d 0000110010000... .......... U U U 14 12 2 -cmpi 32 . . 0000110010...... A+-DXWL... U U U 12 12 2 -cmpi 32 . pcdi 0000110010111010 .......... . . U . . 7 -cmpi 32 . pcix 0000110010111011 .......... . . U . . 9 -cmpm 8 . ax7 1011111100001... .......... U U U 12 12 9 -cmpm 8 . ay7 1011...100001111 .......... U U U 12 12 9 -cmpm 8 . axy7 1011111100001111 .......... U U U 12 12 9 -cmpm 8 . . 1011...100001... .......... U U U 12 12 9 -cmpm 16 . . 1011...101001... .......... U U U 12 12 9 -cmpm 32 . . 1011...110001... .......... U U U 20 20 9 -cpbcc 32 . . 1111...01....... .......... . . U . . 4 unemulated -cpdbcc 32 . . 1111...001001... .......... . . U . . 4 unemulated -cpgen 32 . . 1111...000...... .......... . . U . . 4 unemulated -cpscc 32 . . 1111...001...... .......... . . U . . 4 unemulated -cptrapcc 32 . . 1111...001111... .......... . . U . . 4 unemulated -dbt 16 . . 0101000011001... .......... U U U 12 12 6 -dbf 16 . . 0101000111001... .......... U U U 14 14 6 -dbcc 16 . . 0101....11001... .......... U U U 12 12 6 -divs 16 . d 1000...111000... .......... U U U 158 122 56 -divs 16 . . 1000...111...... A+-DXWLdxI U U U 158 122 56 -divu 16 . d 1000...011000... .......... U U U 140 108 44 -divu 16 . . 1000...011...... A+-DXWLdxI U U U 140 108 44 -divl 32 . d 0100110001000... .......... . . U . . 84 -divl 32 . . 0100110001...... A+-DXWLdxI . . U . . 84 -eor 8 . d 1011...100000... .......... U U U 4 4 2 -eor 8 . . 1011...100...... A+-DXWL... U U U 8 8 4 -eor 16 . d 1011...101000... .......... U U U 4 4 2 -eor 16 . . 1011...101...... A+-DXWL... U U U 8 8 4 -eor 32 . d 1011...110000... .......... U U U 8 6 2 -eor 32 . . 1011...110...... A+-DXWL... U U U 12 12 4 -eori 16 toc . 0000101000111100 .......... U U U 20 16 12 -eori 16 tos . 0000101001111100 .......... S S S 20 16 12 -eori 8 . d 0000101000000... .......... U U U 8 8 2 -eori 8 . . 0000101000...... A+-DXWL... U U U 12 12 4 -eori 16 . d 0000101001000... .......... U U U 8 8 2 -eori 16 . . 0000101001...... A+-DXWL... U U U 12 12 4 -eori 32 . d 0000101010000... .......... U U U 16 14 2 -eori 32 . . 0000101010...... A+-DXWL... U U U 20 20 4 -exg 32 dd . 1100...101000... .......... U U U 6 6 2 -exg 32 aa . 1100...101001... .......... U U U 6 6 2 -exg 32 da . 1100...110001... .......... U U U 6 6 2 -ext 16 . . 0100100010000... .......... U U U 4 4 4 -ext 32 . . 0100100011000... .......... U U U 4 4 4 -extb 32 . . 0100100111000... .......... . . U . . 4 -illegal 0 . . 0100101011111100 .......... U U U 4 4 4 -jmp 32 . . 0100111011...... A..DXWLdx. U U U 4 4 0 -jsr 32 . . 0100111010...... A..DXWLdx. U U U 12 12 0 -lea 32 . . 0100...111...... A..DXWLdx. U U U 0 0 2 -link 16 . a7 0100111001010111 .......... U U U 16 16 5 -link 16 . . 0100111001010... .......... U U U 16 16 5 -link 32 . a7 0100100000001111 .......... . . U . . 6 -link 32 . . 0100100000001... .......... . . U . . 6 -lsr 8 s . 1110...000001... .......... U U U 6 6 4 -lsr 16 s . 1110...001001... .......... U U U 6 6 4 -lsr 32 s . 1110...010001... .......... U U U 8 8 4 -lsr 8 r . 1110...000101... .......... U U U 6 6 6 -lsr 16 r . 1110...001101... .......... U U U 6 6 6 -lsr 32 r . 1110...010101... .......... U U U 8 8 6 -lsr 16 . . 1110001011...... A+-DXWL... U U U 8 8 5 -lsl 8 s . 1110...100001... .......... U U U 6 6 4 -lsl 16 s . 1110...101001... .......... U U U 6 6 4 -lsl 32 s . 1110...110001... .......... U U U 8 8 4 -lsl 8 r . 1110...100101... .......... U U U 6 6 6 -lsl 16 r . 1110...101101... .......... U U U 6 6 6 -lsl 32 r . 1110...110101... .......... U U U 8 8 6 -lsl 16 . . 1110001111...... A+-DXWL... U U U 8 8 5 -move 8 d d 0001...000000... .......... U U U 4 4 2 -move 8 d . 0001...000...... A+-DXWLdxI U U U 4 4 2 -move 8 ai d 0001...010000... .......... U U U 8 8 4 -move 8 ai . 0001...010...... A+-DXWLdxI U U U 8 8 4 -move 8 pi d 0001...011000... .......... U U U 8 8 4 -move 8 pi . 0001...011...... A+-DXWLdxI U U U 8 8 4 -move 8 pi7 d 0001111011000... .......... U U U 8 8 4 -move 8 pi7 . 0001111011...... A+-DXWLdxI U U U 8 8 4 -move 8 pd d 0001...100000... .......... U U U 8 8 5 -move 8 pd . 0001...100...... A+-DXWLdxI U U U 8 8 5 -move 8 pd7 d 0001111100000... .......... U U U 8 8 5 -move 8 pd7 . 0001111100...... A+-DXWLdxI U U U 8 8 5 -move 8 di d 0001...101000... .......... U U U 12 12 5 -move 8 di . 0001...101...... A+-DXWLdxI U U U 12 12 5 -move 8 ix d 0001...110000... .......... U U U 14 14 7 -move 8 ix . 0001...110...... A+-DXWLdxI U U U 14 14 7 -move 8 aw d 0001000111000... .......... U U U 12 12 4 -move 8 aw . 0001000111...... A+-DXWLdxI U U U 12 12 4 -move 8 al d 0001001111000... .......... U U U 16 16 6 -move 8 al . 0001001111...... A+-DXWLdxI U U U 16 16 6 -move 16 d d 0011...000000... .......... U U U 4 4 2 -move 16 d a 0011...000001... .......... U U U 4 4 2 -move 16 d . 0011...000...... A+-DXWLdxI U U U 4 4 2 -move 16 ai d 0011...010000... .......... U U U 8 8 4 -move 16 ai a 0011...010001... .......... U U U 8 8 4 -move 16 ai . 0011...010...... A+-DXWLdxI U U U 8 8 4 -move 16 pi d 0011...011000... .......... U U U 8 8 4 -move 16 pi a 0011...011001... .......... U U U 8 8 4 -move 16 pi . 0011...011...... A+-DXWLdxI U U U 8 8 4 -move 16 pd d 0011...100000... .......... U U U 8 8 5 -move 16 pd a 0011...100001... .......... U U U 8 8 5 -move 16 pd . 0011...100...... A+-DXWLdxI U U U 8 8 5 -move 16 di d 0011...101000... .......... U U U 12 12 5 -move 16 di a 0011...101001... .......... U U U 12 12 5 -move 16 di . 0011...101...... A+-DXWLdxI U U U 12 12 5 -move 16 ix d 0011...110000... .......... U U U 14 14 7 -move 16 ix a 0011...110001... .......... U U U 14 14 7 -move 16 ix . 0011...110...... A+-DXWLdxI U U U 14 14 7 -move 16 aw d 0011000111000... .......... U U U 12 12 4 -move 16 aw a 0011000111001... .......... U U U 12 12 4 -move 16 aw . 0011000111...... A+-DXWLdxI U U U 12 12 4 -move 16 al d 0011001111000... .......... U U U 16 16 6 -move 16 al a 0011001111001... .......... U U U 16 16 6 -move 16 al . 0011001111...... A+-DXWLdxI U U U 16 16 6 -move 32 d d 0010...000000... .......... U U U 4 4 2 -move 32 d a 0010...000001... .......... U U U 4 4 2 -move 32 d . 0010...000...... A+-DXWLdxI U U U 4 4 2 -move 32 ai d 0010...010000... .......... U U U 12 12 4 -move 32 ai a 0010...010001... .......... U U U 12 12 4 -move 32 ai . 0010...010...... A+-DXWLdxI U U U 12 12 4 -move 32 pi d 0010...011000... .......... U U U 12 12 4 -move 32 pi a 0010...011001... .......... U U U 12 12 4 -move 32 pi . 0010...011...... A+-DXWLdxI U U U 12 12 4 -move 32 pd d 0010...100000... .......... U U U 12 14 5 -move 32 pd a 0010...100001... .......... U U U 12 14 5 -move 32 pd . 0010...100...... A+-DXWLdxI U U U 12 14 5 -move 32 di d 0010...101000... .......... U U U 16 16 5 -move 32 di a 0010...101001... .......... U U U 16 16 5 -move 32 di . 0010...101...... A+-DXWLdxI U U U 16 16 5 -move 32 ix d 0010...110000... .......... U U U 18 18 7 -move 32 ix a 0010...110001... .......... U U U 18 18 7 -move 32 ix . 0010...110...... A+-DXWLdxI U U U 18 18 7 -move 32 aw d 0010000111000... .......... U U U 16 16 4 -move 32 aw a 0010000111001... .......... U U U 16 16 4 -move 32 aw . 0010000111...... A+-DXWLdxI U U U 16 16 4 -move 32 al d 0010001111000... .......... U U U 20 20 6 -move 32 al a 0010001111001... .......... U U U 20 20 6 -move 32 al . 0010001111...... A+-DXWLdxI U U U 20 20 6 -movea 16 . d 0011...001000... .......... U U U 4 4 2 -movea 16 . a 0011...001001... .......... U U U 4 4 2 -movea 16 . . 0011...001...... A+-DXWLdxI U U U 4 4 2 -movea 32 . d 0010...001000... .......... U U U 4 4 2 -movea 32 . a 0010...001001... .......... U U U 4 4 2 -movea 32 . . 0010...001...... A+-DXWLdxI U U U 4 4 2 -move 16 frc d 0100001011000... .......... . U U . 4 4 -move 16 frc . 0100001011...... A+-DXWL... . U U . 8 4 -move 16 toc d 0100010011000... .......... U U U 12 12 4 -move 16 toc . 0100010011...... A+-DXWLdxI U U U 12 12 4 -move 16 frs d 0100000011000... .......... U S S 6 4 8 U only for 000 -move 16 frs . 0100000011...... A+-DXWL... U S S 8 8 8 U only for 000 -move 16 tos d 0100011011000... .......... S S S 12 12 8 -move 16 tos . 0100011011...... A+-DXWLdxI S S S 12 12 8 -move 32 fru . 0100111001101... .......... S S S 4 6 2 -move 32 tou . 0100111001100... .......... S S S 4 6 2 -movec 32 cr . 0100111001111010 .......... . S S . 12 6 -movec 32 rc . 0100111001111011 .......... . S S . 10 12 -movem 16 re pd 0100100010100... .......... U U U 8 8 4 -movem 16 re . 0100100010...... A..DXWL... U U U 8 8 4 -movem 32 re pd 0100100011100... .......... U U U 8 8 4 -movem 32 re . 0100100011...... A..DXWL... U U U 8 8 4 -movem 16 er pi 0100110010011... .......... U U U 12 12 8 -movem 16 er pcdi 0100110010111010 .......... U U U 16 16 9 -movem 16 er pcix 0100110010111011 .......... U U U 18 18 11 -movem 16 er . 0100110010...... A..DXWL... U U U 12 12 8 -movem 32 er pi 0100110011011... .......... U U U 12 12 8 -movem 32 er pcdi 0100110011111010 .......... U U U 20 20 9 -movem 32 er pcix 0100110011111011 .......... U U U 22 22 11 -movem 32 er . 0100110011...... A..DXWL... U U U 12 12 8 -movep 16 er . 0000...100001... .......... U U U 16 16 12 -movep 32 er . 0000...101001... .......... U U U 24 24 18 -movep 16 re . 0000...110001... .......... U U U 16 16 11 -movep 32 re . 0000...111001... .......... U U U 24 24 17 -moveq 32 . . 0111...0........ .......... U U U 4 4 2 -moves 8 . . 0000111000...... A+-DXWL... . S S . 14 5 -moves 16 . . 0000111001...... A+-DXWL... . S S . 14 5 -moves 32 . . 0000111010...... A+-DXWL... . S S . 16 5 -muls 16 . d 1100...111000... .......... U U U 54 32 27 -muls 16 . . 1100...111...... A+-DXWLdxI U U U 54 32 27 -mulu 16 . d 1100...011000... .......... U U U 54 30 27 -mulu 16 . . 1100...011...... A+-DXWLdxI U U U 54 30 27 -mull 32 . d 0100110000000... .......... . . U . . 43 -mull 32 . . 0100110000...... A+-DXWLdxI . . U . . 43 -nbcd 8 . d 0100100000000... .......... U U U 6 6 6 -nbcd 8 . . 0100100000...... A+-DXWL... U U U 8 8 6 -neg 8 . d 0100010000000... .......... U U U 4 4 2 -neg 8 . . 0100010000...... A+-DXWL... U U U 8 8 4 -neg 16 . d 0100010001000... .......... U U U 4 4 2 -neg 16 . . 0100010001...... A+-DXWL... U U U 8 8 4 -neg 32 . d 0100010010000... .......... U U U 6 6 2 -neg 32 . . 0100010010...... A+-DXWL... U U U 12 12 4 -negx 8 . d 0100000000000... .......... U U U 4 4 2 -negx 8 . . 0100000000...... A+-DXWL... U U U 8 8 4 -negx 16 . d 0100000001000... .......... U U U 4 4 2 -negx 16 . . 0100000001...... A+-DXWL... U U U 8 8 4 -negx 32 . d 0100000010000... .......... U U U 6 6 2 -negx 32 . . 0100000010...... A+-DXWL... U U U 12 12 4 -nop 0 . . 0100111001110001 .......... U U U 4 4 2 -not 8 . d 0100011000000... .......... U U U 4 4 2 -not 8 . . 0100011000...... A+-DXWL... U U U 8 8 4 -not 16 . d 0100011001000... .......... U U U 4 4 2 -not 16 . . 0100011001...... A+-DXWL... U U U 8 8 4 -not 32 . d 0100011010000... .......... U U U 6 6 2 -not 32 . . 0100011010...... A+-DXWL... U U U 12 12 4 -or 8 er d 1000...000000... .......... U U U 4 4 2 -or 8 er . 1000...000...... A+-DXWLdxI U U U 4 4 2 -or 16 er d 1000...001000... .......... U U U 4 4 2 -or 16 er . 1000...001...... A+-DXWLdxI U U U 4 4 2 -or 32 er d 1000...010000... .......... U U U 6 6 2 -or 32 er . 1000...010...... A+-DXWLdxI U U U 6 6 2 -or 8 re . 1000...100...... A+-DXWL... U U U 8 8 4 -or 16 re . 1000...101...... A+-DXWL... U U U 8 8 4 -or 32 re . 1000...110...... A+-DXWL... U U U 12 12 4 -ori 16 toc . 0000000000111100 .......... U U U 20 16 12 -ori 16 tos . 0000000001111100 .......... S S S 20 16 12 -ori 8 . d 0000000000000... .......... U U U 8 8 2 -ori 8 . . 0000000000...... A+-DXWL... U U U 12 12 4 -ori 16 . d 0000000001000... .......... U U U 8 8 2 -ori 16 . . 0000000001...... A+-DXWL... U U U 12 12 4 -ori 32 . d 0000000010000... .......... U U U 16 14 2 -ori 32 . . 0000000010...... A+-DXWL... U U U 20 20 4 -pack 16 rr . 1000...101000... .......... . . U . . 6 -pack 16 mm ax7 1000111101001... .......... . . U . . 13 -pack 16 mm ay7 1000...101001111 .......... . . U . . 13 -pack 16 mm axy7 1000111101001111 .......... . . U . . 13 -pack 16 mm . 1000...101001... .......... . . U . . 13 -pea 32 . . 0100100001...... A..DXWLdx. U U U 6 6 5 -reset 0 . . 0100111001110000 .......... S S S 0 0 0 -ror 8 s . 1110...000011... .......... U U U 6 6 8 -ror 16 s . 1110...001011... .......... U U U 6 6 8 -ror 32 s . 1110...010011... .......... U U U 8 8 8 -ror 8 r . 1110...000111... .......... U U U 6 6 8 -ror 16 r . 1110...001111... .......... U U U 6 6 8 -ror 32 r . 1110...010111... .......... U U U 8 8 8 -ror 16 . . 1110011011...... A+-DXWL... U U U 8 8 7 -rol 8 s . 1110...100011... .......... U U U 6 6 8 -rol 16 s . 1110...101011... .......... U U U 6 6 8 -rol 32 s . 1110...110011... .......... U U U 8 8 8 -rol 8 r . 1110...100111... .......... U U U 6 6 8 -rol 16 r . 1110...101111... .......... U U U 6 6 8 -rol 32 r . 1110...110111... .......... U U U 8 8 8 -rol 16 . . 1110011111...... A+-DXWL... U U U 8 8 7 -roxr 8 s . 1110...000010... .......... U U U 6 6 12 -roxr 16 s . 1110...001010... .......... U U U 6 6 12 -roxr 32 s . 1110...010010... .......... U U U 8 8 12 -roxr 8 r . 1110...000110... .......... U U U 6 6 12 -roxr 16 r . 1110...001110... .......... U U U 6 6 12 -roxr 32 r . 1110...010110... .......... U U U 8 8 12 -roxr 16 . . 1110010011...... A+-DXWL... U U U 8 8 5 -roxl 8 s . 1110...100010... .......... U U U 6 6 12 -roxl 16 s . 1110...101010... .......... U U U 6 6 12 -roxl 32 s . 1110...110010... .......... U U U 8 8 12 -roxl 8 r . 1110...100110... .......... U U U 6 6 12 -roxl 16 r . 1110...101110... .......... U U U 6 6 12 -roxl 32 r . 1110...110110... .......... U U U 8 8 12 -roxl 16 . . 1110010111...... A+-DXWL... U U U 8 8 5 -rtd 32 . . 0100111001110100 .......... . U U . 16 10 -rte 32 . . 0100111001110011 .......... S S S 20 24 20 bus fault not emulated -rtm 32 . . 000001101100.... .......... . . U . . 19 not properly emulated -rtr 32 . . 0100111001110111 .......... U U U 20 20 14 -rts 32 . . 0100111001110101 .......... U U U 16 16 10 -sbcd 8 rr . 1000...100000... .......... U U U 6 6 4 -sbcd 8 mm ax7 1000111100001... .......... U U U 18 18 16 -sbcd 8 mm ay7 1000...100001111 .......... U U U 18 18 16 -sbcd 8 mm axy7 1000111100001111 .......... U U U 18 18 16 -sbcd 8 mm . 1000...100001... .......... U U U 18 18 16 -st 8 . d 0101000011000... .......... U U U 6 4 4 -st 8 . . 0101000011...... A+-DXWL... U U U 8 8 6 -sf 8 . d 0101000111000... .......... U U U 4 4 4 -sf 8 . . 0101000111...... A+-DXWL... U U U 8 8 6 -scc 8 . d 0101....11000... .......... U U U 4 4 4 -scc 8 . . 0101....11...... A+-DXWL... U U U 8 8 6 -stop 0 . . 0100111001110010 .......... S S S 4 4 8 -sub 8 er d 1001...000000... .......... U U U 4 4 2 -sub 8 er . 1001...000...... A+-DXWLdxI U U U 4 4 2 -sub 16 er d 1001...001000... .......... U U U 4 4 2 -sub 16 er a 1001...001001... .......... U U U 4 4 2 -sub 16 er . 1001...001...... A+-DXWLdxI U U U 4 4 2 -sub 32 er d 1001...010000... .......... U U U 6 6 2 -sub 32 er a 1001...010001... .......... U U U 6 6 2 -sub 32 er . 1001...010...... A+-DXWLdxI U U U 6 6 2 -sub 8 re . 1001...100...... A+-DXWL... U U U 8 8 4 -sub 16 re . 1001...101...... A+-DXWL... U U U 8 8 4 -sub 32 re . 1001...110...... A+-DXWL... U U U 12 12 4 -suba 16 . d 1001...011000... .......... U U U 8 8 2 -suba 16 . a 1001...011001... .......... U U U 8 8 2 -suba 16 . . 1001...011...... A+-DXWLdxI U U U 8 8 2 -suba 32 . d 1001...111000... .......... U U U 6 6 2 -suba 32 . a 1001...111001... .......... U U U 6 6 2 -suba 32 . . 1001...111...... A+-DXWLdxI U U U 6 6 2 -subi 8 . d 0000010000000... .......... U U U 8 8 2 -subi 8 . . 0000010000...... A+-DXWL... U U U 12 12 4 -subi 16 . d 0000010001000... .......... U U U 8 8 2 -subi 16 . . 0000010001...... A+-DXWL... U U U 12 12 4 -subi 32 . d 0000010010000... .......... U U U 16 14 2 -subi 32 . . 0000010010...... A+-DXWL... U U U 20 20 4 -subq 8 . d 0101...100000... .......... U U U 4 4 2 -subq 8 . . 0101...100...... A+-DXWL... U U U 8 8 4 -subq 16 . d 0101...101000... .......... U U U 4 4 2 -subq 16 . a 0101...101001... .......... U U U 8 4 2 -subq 16 . . 0101...101...... A+-DXWL... U U U 8 8 4 -subq 32 . d 0101...110000... .......... U U U 8 8 2 -subq 32 . a 0101...110001... .......... U U U 8 8 2 -subq 32 . . 0101...110...... A+-DXWL... U U U 12 12 4 -subx 8 rr . 1001...100000... .......... U U U 4 4 2 -subx 16 rr . 1001...101000... .......... U U U 4 4 2 -subx 32 rr . 1001...110000... .......... U U U 8 6 2 -subx 8 mm ax7 1001111100001... .......... U U U 18 18 12 -subx 8 mm ay7 1001...100001111 .......... U U U 18 18 12 -subx 8 mm axy7 1001111100001111 .......... U U U 18 18 12 -subx 8 mm . 1001...100001... .......... U U U 18 18 12 -subx 16 mm . 1001...101001... .......... U U U 18 18 12 -subx 32 mm . 1001...110001... .......... U U U 30 30 12 -swap 32 . . 0100100001000... .......... U U U 4 4 4 -tas 8 . d 0100101011000... .......... U U U 4 4 4 -tas 8 . . 0100101011...... A+-DXWL... U U U 14 14 12 -trap 0 . . 010011100100.... .......... U U U 4 4 4 -trapt 0 . . 0101000011111100 .......... . . U . . 4 -trapt 16 . . 0101000011111010 .......... . . U . . 6 -trapt 32 . . 0101000011111011 .......... . . U . . 8 -trapf 0 . . 0101000111111100 .......... . . U . . 4 -trapf 16 . . 0101000111111010 .......... . . U . . 6 -trapf 32 . . 0101000111111011 .......... . . U . . 8 -trapcc 0 . . 0101....11111100 .......... . . U . . 4 -trapcc 16 . . 0101....11111010 .......... . . U . . 6 -trapcc 32 . . 0101....11111011 .......... . . U . . 8 -trapv 0 . . 0100111001110110 .......... U U U 4 4 4 -tst 8 . d 0100101000000... .......... U U U 4 4 2 -tst 8 . . 0100101000...... A+-DXWL... U U U 4 4 2 -tst 8 . pcdi 0100101000111010 .......... . . U . . 7 -tst 8 . pcix 0100101000111011 .......... . . U . . 9 -tst 8 . i 0100101000111100 .......... . . U . . 6 -tst 16 . d 0100101001000... .......... U U U 4 4 2 -tst 16 . a 0100101001001... .......... . . U . . 2 -tst 16 . . 0100101001...... A+-DXWL... U U U 4 4 2 -tst 16 . pcdi 0100101001111010 .......... . . U . . 7 -tst 16 . pcix 0100101001111011 .......... . . U . . 9 -tst 16 . i 0100101001111100 .......... . . U . . 6 -tst 32 . d 0100101010000... .......... U U U 4 4 2 -tst 32 . a 0100101010001... .......... . . U . . 2 -tst 32 . . 0100101010...... A+-DXWL... U U U 4 4 2 -tst 32 . pcdi 0100101010111010 .......... . . U . . 7 -tst 32 . pcix 0100101010111011 .......... . . U . . 9 -tst 32 . i 0100101010111100 .......... . . U . . 6 -unlk 32 . a7 0100111001011111 .......... U U U 12 12 6 -unlk 32 . . 0100111001011... .......... U U U 12 12 6 -unpk 16 rr . 1000...110000... .......... . . U . . 8 -unpk 16 mm ax7 1000111110001... .......... . . U . . 13 -unpk 16 mm ay7 1000...110001111 .......... . . U . . 13 -unpk 16 mm axy7 1000111110001111 .......... . . U . . 13 -unpk 16 mm . 1000...110001... .......... . . U . . 13 - - - -XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -M68KMAKE_OPCODE_HANDLER_BODY - -M68KMAKE_OP(1010, 0, ., .) -{ - m68ki_exception_1010(); -} - - -M68KMAKE_OP(1111, 0, ., .) -{ - m68ki_exception_1111(); -} - - -M68KMAKE_OP(abcd, 8, rr, .) -{ - uint* r_dst = &DX; - uint src = DY; - uint dst = *r_dst; - uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1(); - - FLAG_V = ~res; /* Undefined V behavior */ - - if(res > 9) - res += 6; - res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst); - FLAG_X = FLAG_C = (res > 0x99) << 8; - if(FLAG_C) - res -= 0xa0; - - FLAG_V &= res; /* Undefined V behavior part II */ - FLAG_N = NFLAG_8(res); /* Undefined N behavior */ - - res = MASK_OUT_ABOVE_8(res); - FLAG_Z |= res; - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; -} - - -M68KMAKE_OP(abcd, 8, mm, ax7) -{ - uint src = OPER_AY_PD_8(); - uint ea = EA_A7_PD_8(); - uint dst = m68ki_read_8(ea); - uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1(); - - FLAG_V = ~res; /* Undefined V behavior */ - - if(res > 9) - res += 6; - res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst); - FLAG_X = FLAG_C = (res > 0x99) << 8; - if(FLAG_C) - res -= 0xa0; - - FLAG_V &= res; /* Undefined V behavior part II */ - FLAG_N = NFLAG_8(res); /* Undefined N behavior */ - - res = MASK_OUT_ABOVE_8(res); - FLAG_Z |= res; - - m68ki_write_8(ea, res); -} - - -M68KMAKE_OP(abcd, 8, mm, ay7) -{ - uint src = OPER_A7_PD_8(); - uint ea = EA_AX_PD_8(); - uint dst = m68ki_read_8(ea); - uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1(); - - FLAG_V = ~res; /* Undefined V behavior */ - - if(res > 9) - res += 6; - res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst); - FLAG_X = FLAG_C = (res > 0x99) << 8; - if(FLAG_C) - res -= 0xa0; - - FLAG_V &= res; /* Undefined V behavior part II */ - FLAG_N = NFLAG_8(res); /* Undefined N behavior */ - - res = MASK_OUT_ABOVE_8(res); - FLAG_Z |= res; - - m68ki_write_8(ea, res); -} - - -M68KMAKE_OP(abcd, 8, mm, axy7) -{ - uint src = OPER_A7_PD_8(); - uint ea = EA_A7_PD_8(); - uint dst = m68ki_read_8(ea); - uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1(); - - FLAG_V = ~res; /* Undefined V behavior */ - - if(res > 9) - res += 6; - res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst); - FLAG_X = FLAG_C = (res > 0x99) << 8; - if(FLAG_C) - res -= 0xa0; - - FLAG_V &= res; /* Undefined V behavior part II */ - FLAG_N = NFLAG_8(res); /* Undefined N behavior */ - - res = MASK_OUT_ABOVE_8(res); - FLAG_Z |= res; - - m68ki_write_8(ea, res); -} - - -M68KMAKE_OP(abcd, 8, mm, .) -{ - uint src = OPER_AY_PD_8(); - uint ea = EA_AX_PD_8(); - uint dst = m68ki_read_8(ea); - uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1(); - - FLAG_V = ~res; /* Undefined V behavior */ - - if(res > 9) - res += 6; - res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst); - FLAG_X = FLAG_C = (res > 0x99) << 8; - if(FLAG_C) - res -= 0xa0; - - FLAG_V &= res; /* Undefined V behavior part II */ - FLAG_N = NFLAG_8(res); /* Undefined N behavior */ - - res = MASK_OUT_ABOVE_8(res); - FLAG_Z |= res; - - m68ki_write_8(ea, res); -} - - -M68KMAKE_OP(add, 8, er, d) -{ - uint* r_dst = &DX; - uint src = MASK_OUT_ABOVE_8(DY); - uint dst = MASK_OUT_ABOVE_8(*r_dst); - uint res = src + dst; - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; -} - - -M68KMAKE_OP(add, 8, er, .) -{ - uint* r_dst = &DX; - uint src = M68KMAKE_GET_OPER_AY_8; - uint dst = MASK_OUT_ABOVE_8(*r_dst); - uint res = src + dst; - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; -} - - -M68KMAKE_OP(add, 16, er, d) -{ - uint* r_dst = &DX; - uint src = MASK_OUT_ABOVE_16(DY); - uint dst = MASK_OUT_ABOVE_16(*r_dst); - uint res = src + dst; - - FLAG_N = NFLAG_16(res); - FLAG_V = VFLAG_ADD_16(src, dst, res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; -} - - -M68KMAKE_OP(add, 16, er, a) -{ - uint* r_dst = &DX; - uint src = MASK_OUT_ABOVE_16(AY); - uint dst = MASK_OUT_ABOVE_16(*r_dst); - uint res = src + dst; - - FLAG_N = NFLAG_16(res); - FLAG_V = VFLAG_ADD_16(src, dst, res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; -} - - -M68KMAKE_OP(add, 16, er, .) -{ - uint* r_dst = &DX; - uint src = M68KMAKE_GET_OPER_AY_16; - uint dst = MASK_OUT_ABOVE_16(*r_dst); - uint res = src + dst; - - FLAG_N = NFLAG_16(res); - FLAG_V = VFLAG_ADD_16(src, dst, res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; -} - - -M68KMAKE_OP(add, 32, er, d) -{ - uint* r_dst = &DX; - uint src = DY; - uint dst = *r_dst; - uint res = src + dst; - - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_ADD_32(src, dst, res); - FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - *r_dst = FLAG_Z; -} - - -M68KMAKE_OP(add, 32, er, a) -{ - uint* r_dst = &DX; - uint src = AY; - uint dst = *r_dst; - uint res = src + dst; - - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_ADD_32(src, dst, res); - FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - *r_dst = FLAG_Z; -} - - -M68KMAKE_OP(add, 32, er, .) -{ - uint* r_dst = &DX; - uint src = M68KMAKE_GET_OPER_AY_32; - uint dst = *r_dst; - uint res = src + dst; - - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_ADD_32(src, dst, res); - FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - *r_dst = FLAG_Z; -} - - -M68KMAKE_OP(add, 8, re, .) -{ - uint ea = M68KMAKE_GET_EA_AY_8; - uint src = MASK_OUT_ABOVE_8(DX); - uint dst = m68ki_read_8(ea); - uint res = src + dst; - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - m68ki_write_8(ea, FLAG_Z); -} - - -M68KMAKE_OP(add, 16, re, .) -{ - uint ea = M68KMAKE_GET_EA_AY_16; - uint src = MASK_OUT_ABOVE_16(DX); - uint dst = m68ki_read_16(ea); - uint res = src + dst; - - FLAG_N = NFLAG_16(res); - FLAG_V = VFLAG_ADD_16(src, dst, res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - m68ki_write_16(ea, FLAG_Z); -} - - -M68KMAKE_OP(add, 32, re, .) -{ - uint ea = M68KMAKE_GET_EA_AY_32; - uint src = DX; - uint dst = m68ki_read_32(ea); - uint res = src + dst; - - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_ADD_32(src, dst, res); - FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - m68ki_write_32(ea, FLAG_Z); -} - - -M68KMAKE_OP(adda, 16, ., d) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(DY)); -} - - -M68KMAKE_OP(adda, 16, ., a) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(AY)); -} - - -M68KMAKE_OP(adda, 16, ., .) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(M68KMAKE_GET_OPER_AY_16)); -} - - -M68KMAKE_OP(adda, 32, ., d) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst + DY); -} - - -M68KMAKE_OP(adda, 32, ., a) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst + AY); -} - - -M68KMAKE_OP(adda, 32, ., .) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst + M68KMAKE_GET_OPER_AY_32); -} - - -M68KMAKE_OP(addi, 8, ., d) -{ - uint* r_dst = &DY; - uint src = OPER_I_8(); - uint dst = MASK_OUT_ABOVE_8(*r_dst); - uint res = src + dst; - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; -} - - -M68KMAKE_OP(addi, 8, ., .) -{ - uint src = OPER_I_8(); - uint ea = M68KMAKE_GET_EA_AY_8; - uint dst = m68ki_read_8(ea); - uint res = src + dst; - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - m68ki_write_8(ea, FLAG_Z); -} - - -M68KMAKE_OP(addi, 16, ., d) -{ - uint* r_dst = &DY; - uint src = OPER_I_16(); - uint dst = MASK_OUT_ABOVE_16(*r_dst); - uint res = src + dst; - - FLAG_N = NFLAG_16(res); - FLAG_V = VFLAG_ADD_16(src, dst, res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; -} - - -M68KMAKE_OP(addi, 16, ., .) -{ - uint src = OPER_I_16(); - uint ea = M68KMAKE_GET_EA_AY_16; - uint dst = m68ki_read_16(ea); - uint res = src + dst; - - FLAG_N = NFLAG_16(res); - FLAG_V = VFLAG_ADD_16(src, dst, res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - m68ki_write_16(ea, FLAG_Z); -} - - -M68KMAKE_OP(addi, 32, ., d) -{ - uint* r_dst = &DY; - uint src = OPER_I_32(); - uint dst = *r_dst; - uint res = src + dst; - - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_ADD_32(src, dst, res); - FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - *r_dst = FLAG_Z; -} - - -M68KMAKE_OP(addi, 32, ., .) -{ - uint src = OPER_I_32(); - uint ea = M68KMAKE_GET_EA_AY_32; - uint dst = m68ki_read_32(ea); - uint res = src + dst; - - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_ADD_32(src, dst, res); - FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - m68ki_write_32(ea, FLAG_Z); -} - - -M68KMAKE_OP(addq, 8, ., d) -{ - uint* r_dst = &DY; - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint dst = MASK_OUT_ABOVE_8(*r_dst); - uint res = src + dst; - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; -} - - -M68KMAKE_OP(addq, 8, ., .) -{ - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint ea = M68KMAKE_GET_EA_AY_8; - uint dst = m68ki_read_8(ea); - uint res = src + dst; - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - m68ki_write_8(ea, FLAG_Z); -} - - -M68KMAKE_OP(addq, 16, ., d) -{ - uint* r_dst = &DY; - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint dst = MASK_OUT_ABOVE_16(*r_dst); - uint res = src + dst; - - FLAG_N = NFLAG_16(res); - FLAG_V = VFLAG_ADD_16(src, dst, res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; -} - - -M68KMAKE_OP(addq, 16, ., a) -{ - uint* r_dst = &AY; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1); -} - - -M68KMAKE_OP(addq, 16, ., .) -{ - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint ea = M68KMAKE_GET_EA_AY_16; - uint dst = m68ki_read_16(ea); - uint res = src + dst; - - FLAG_N = NFLAG_16(res); - FLAG_V = VFLAG_ADD_16(src, dst, res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - m68ki_write_16(ea, FLAG_Z); -} - - -M68KMAKE_OP(addq, 32, ., d) -{ - uint* r_dst = &DY; - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint dst = *r_dst; - uint res = src + dst; - - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_ADD_32(src, dst, res); - FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - *r_dst = FLAG_Z; -} - - -M68KMAKE_OP(addq, 32, ., a) -{ - uint* r_dst = &AY; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1); -} - - -M68KMAKE_OP(addq, 32, ., .) -{ - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint ea = M68KMAKE_GET_EA_AY_32; - uint dst = m68ki_read_32(ea); - uint res = src + dst; - - - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_ADD_32(src, dst, res); - FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - m68ki_write_32(ea, FLAG_Z); -} - - -M68KMAKE_OP(addx, 8, rr, .) -{ - uint* r_dst = &DX; - uint src = MASK_OUT_ABOVE_8(DY); - uint dst = MASK_OUT_ABOVE_8(*r_dst); - uint res = src + dst + XFLAG_AS_1(); - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - - res = MASK_OUT_ABOVE_8(res); - FLAG_Z |= res; - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; -} - - -M68KMAKE_OP(addx, 16, rr, .) -{ - uint* r_dst = &DX; - uint src = MASK_OUT_ABOVE_16(DY); - uint dst = MASK_OUT_ABOVE_16(*r_dst); - uint res = src + dst + XFLAG_AS_1(); - - FLAG_N = NFLAG_16(res); - FLAG_V = VFLAG_ADD_16(src, dst, res); - FLAG_X = FLAG_C = CFLAG_16(res); - - res = MASK_OUT_ABOVE_16(res); - FLAG_Z |= res; - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; -} - - -M68KMAKE_OP(addx, 32, rr, .) -{ - uint* r_dst = &DX; - uint src = DY; - uint dst = *r_dst; - uint res = src + dst + XFLAG_AS_1(); - - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_ADD_32(src, dst, res); - FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); - - res = MASK_OUT_ABOVE_32(res); - FLAG_Z |= res; - - *r_dst = res; -} - - -M68KMAKE_OP(addx, 8, mm, ax7) -{ - uint src = OPER_AY_PD_8(); - uint ea = EA_A7_PD_8(); - uint dst = m68ki_read_8(ea); - uint res = src + dst + XFLAG_AS_1(); - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - - res = MASK_OUT_ABOVE_8(res); - FLAG_Z |= res; - - m68ki_write_8(ea, res); -} - - -M68KMAKE_OP(addx, 8, mm, ay7) -{ - uint src = OPER_A7_PD_8(); - uint ea = EA_AX_PD_8(); - uint dst = m68ki_read_8(ea); - uint res = src + dst + XFLAG_AS_1(); - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - - res = MASK_OUT_ABOVE_8(res); - FLAG_Z |= res; - - m68ki_write_8(ea, res); -} - - -M68KMAKE_OP(addx, 8, mm, axy7) -{ - uint src = OPER_A7_PD_8(); - uint ea = EA_A7_PD_8(); - uint dst = m68ki_read_8(ea); - uint res = src + dst + XFLAG_AS_1(); - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - - res = MASK_OUT_ABOVE_8(res); - FLAG_Z |= res; - - m68ki_write_8(ea, res); -} - - -M68KMAKE_OP(addx, 8, mm, .) -{ - uint src = OPER_AY_PD_8(); - uint ea = EA_AX_PD_8(); - uint dst = m68ki_read_8(ea); - uint res = src + dst + XFLAG_AS_1(); - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - - res = MASK_OUT_ABOVE_8(res); - FLAG_Z |= res; - - m68ki_write_8(ea, res); -} - - -M68KMAKE_OP(addx, 16, mm, .) -{ - uint src = OPER_AY_PD_16(); - uint ea = EA_AX_PD_16(); - uint dst = m68ki_read_16(ea); - uint res = src + dst + XFLAG_AS_1(); - - FLAG_N = NFLAG_16(res); - FLAG_V = VFLAG_ADD_16(src, dst, res); - FLAG_X = FLAG_C = CFLAG_16(res); - - res = MASK_OUT_ABOVE_16(res); - FLAG_Z |= res; - - m68ki_write_16(ea, res); -} - - -M68KMAKE_OP(addx, 32, mm, .) -{ - uint src = OPER_AY_PD_32(); - uint ea = EA_AX_PD_32(); - uint dst = m68ki_read_32(ea); - uint res = src + dst + XFLAG_AS_1(); - - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_ADD_32(src, dst, res); - FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); - - res = MASK_OUT_ABOVE_32(res); - FLAG_Z |= res; - - m68ki_write_32(ea, res); -} - - -M68KMAKE_OP(and, 8, er, d) -{ - FLAG_Z = MASK_OUT_ABOVE_8(DX &= (DY | 0xffffff00)); - - FLAG_N = NFLAG_8(FLAG_Z); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(and, 8, er, .) -{ - FLAG_Z = MASK_OUT_ABOVE_8(DX &= (M68KMAKE_GET_OPER_AY_8 | 0xffffff00)); - - FLAG_N = NFLAG_8(FLAG_Z); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(and, 16, er, d) -{ - FLAG_Z = MASK_OUT_ABOVE_16(DX &= (DY | 0xffff0000)); - - FLAG_N = NFLAG_16(FLAG_Z); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(and, 16, er, .) -{ - FLAG_Z = MASK_OUT_ABOVE_16(DX &= (M68KMAKE_GET_OPER_AY_16 | 0xffff0000)); - - FLAG_N = NFLAG_16(FLAG_Z); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(and, 32, er, d) -{ - FLAG_Z = DX &= DY; - - FLAG_N = NFLAG_32(FLAG_Z); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(and, 32, er, .) -{ - FLAG_Z = DX &= M68KMAKE_GET_OPER_AY_32; - - FLAG_N = NFLAG_32(FLAG_Z); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(and, 8, re, .) -{ - uint ea = M68KMAKE_GET_EA_AY_8; - uint res = DX & m68ki_read_8(ea); - - FLAG_N = NFLAG_8(res); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_Z = MASK_OUT_ABOVE_8(res); - - m68ki_write_8(ea, FLAG_Z); -} - - -M68KMAKE_OP(and, 16, re, .) -{ - uint ea = M68KMAKE_GET_EA_AY_16; - uint res = DX & m68ki_read_16(ea); - - FLAG_N = NFLAG_16(res); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_Z = MASK_OUT_ABOVE_16(res); - - m68ki_write_16(ea, FLAG_Z); -} - - -M68KMAKE_OP(and, 32, re, .) -{ - uint ea = M68KMAKE_GET_EA_AY_32; - uint res = DX & m68ki_read_32(ea); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - - m68ki_write_32(ea, res); -} - - -M68KMAKE_OP(andi, 8, ., d) -{ - FLAG_Z = MASK_OUT_ABOVE_8(DY &= (OPER_I_8() | 0xffffff00)); - - FLAG_N = NFLAG_8(FLAG_Z); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(andi, 8, ., .) -{ - uint src = OPER_I_8(); - uint ea = M68KMAKE_GET_EA_AY_8; - uint res = src & m68ki_read_8(ea); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - - m68ki_write_8(ea, res); -} - - -M68KMAKE_OP(andi, 16, ., d) -{ - FLAG_Z = MASK_OUT_ABOVE_16(DY &= (OPER_I_16() | 0xffff0000)); - - FLAG_N = NFLAG_16(FLAG_Z); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(andi, 16, ., .) -{ - uint src = OPER_I_16(); - uint ea = M68KMAKE_GET_EA_AY_16; - uint res = src & m68ki_read_16(ea); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - - m68ki_write_16(ea, res); -} - - -M68KMAKE_OP(andi, 32, ., d) -{ - FLAG_Z = DY &= (OPER_I_32()); - - FLAG_N = NFLAG_32(FLAG_Z); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(andi, 32, ., .) -{ - uint src = OPER_I_32(); - uint ea = M68KMAKE_GET_EA_AY_32; - uint res = src & m68ki_read_32(ea); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - - m68ki_write_32(ea, res); -} - - -M68KMAKE_OP(andi, 16, toc, .) -{ - m68ki_set_ccr(m68ki_get_ccr() & OPER_I_16()); -} - - -M68KMAKE_OP(andi, 16, tos, .) -{ - if(FLAG_S) - { - uint src = OPER_I_16(); - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_set_sr(m68ki_get_sr() & src); - return; - } - m68ki_exception_privilege_violation(); -} - - -M68KMAKE_OP(asr, 8, s, .) -{ - uint* r_dst = &DY; - uint shift = (((REG_IR >> 9) - 1) & 7) + 1; - uint src = MASK_OUT_ABOVE_8(*r_dst); - uint res = src >> shift; - - if(GET_MSB_8(src)) - res |= m68ki_shift_8_table[shift]; - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_X = FLAG_C = src << (9-shift); -} - - -M68KMAKE_OP(asr, 16, s, .) -{ - uint* r_dst = &DY; - uint shift = (((REG_IR >> 9) - 1) & 7) + 1; - uint src = MASK_OUT_ABOVE_16(*r_dst); - uint res = src >> shift; - - if(GET_MSB_16(src)) - res |= m68ki_shift_16_table[shift]; - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_X = FLAG_C = src << (9-shift); -} - - -M68KMAKE_OP(asr, 32, s, .) -{ - uint* r_dst = &DY; - uint shift = (((REG_IR >> 9) - 1) & 7) + 1; - uint src = *r_dst; - uint res = src >> shift; - - if(GET_MSB_32(src)) - res |= m68ki_shift_32_table[shift]; - - *r_dst = res; - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_X = FLAG_C = src << (9-shift); -} - - -M68KMAKE_OP(asr, 8, r, .) -{ - uint* r_dst = &DY; - uint shift = DX & 0x3f; - uint src = MASK_OUT_ABOVE_8(*r_dst); - uint res = src >> shift; - - if(shift != 0) - { - USE_CYCLES(shift<> shift; - - if(shift != 0) - { - USE_CYCLES(shift<> (shift - 1))<<8; - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - return; - } - - if(GET_MSB_16(src)) - { - *r_dst |= 0xffff; - FLAG_C = CFLAG_SET; - FLAG_X = XFLAG_SET; - FLAG_N = NFLAG_SET; - FLAG_Z = ZFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - return; - } - - *r_dst &= 0xffff0000; - FLAG_C = CFLAG_CLEAR; - FLAG_X = XFLAG_CLEAR; - FLAG_N = NFLAG_CLEAR; - FLAG_Z = ZFLAG_SET; - FLAG_V = VFLAG_CLEAR; - return; - } - - FLAG_C = CFLAG_CLEAR; - FLAG_N = NFLAG_16(src); - FLAG_Z = src; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(asr, 32, r, .) -{ - uint* r_dst = &DY; - uint shift = DX & 0x3f; - uint src = *r_dst; - uint res = src >> shift; - - if(shift != 0) - { - USE_CYCLES(shift<> (shift - 1))<<8; - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - return; - } - - if(GET_MSB_32(src)) - { - *r_dst = 0xffffffff; - FLAG_C = CFLAG_SET; - FLAG_X = XFLAG_SET; - FLAG_N = NFLAG_SET; - FLAG_Z = ZFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - return; - } - - *r_dst = 0; - FLAG_C = CFLAG_CLEAR; - FLAG_X = XFLAG_CLEAR; - FLAG_N = NFLAG_CLEAR; - FLAG_Z = ZFLAG_SET; - FLAG_V = VFLAG_CLEAR; - return; - } - - FLAG_C = CFLAG_CLEAR; - FLAG_N = NFLAG_32(src); - FLAG_Z = src; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(asr, 16, ., .) -{ - uint ea = M68KMAKE_GET_EA_AY_16; - uint src = m68ki_read_16(ea); - uint res = src >> 1; - - if(GET_MSB_16(src)) - res |= 0x8000; - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = FLAG_X = src << 8; -} - - -M68KMAKE_OP(asl, 8, s, .) -{ - uint* r_dst = &DY; - uint shift = (((REG_IR >> 9) - 1) & 7) + 1; - uint src = MASK_OUT_ABOVE_8(*r_dst); - uint res = MASK_OUT_ABOVE_8(src << shift); - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; - - FLAG_X = FLAG_C = src << shift; - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - src &= m68ki_shift_8_table[shift + 1]; - FLAG_V = (!(src == 0 || (src == m68ki_shift_8_table[shift + 1] && shift < 8)))<<7; -} - - -M68KMAKE_OP(asl, 16, s, .) -{ - uint* r_dst = &DY; - uint shift = (((REG_IR >> 9) - 1) & 7) + 1; - uint src = MASK_OUT_ABOVE_16(*r_dst); - uint res = MASK_OUT_ABOVE_16(src << shift); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_X = FLAG_C = src >> (8-shift); - src &= m68ki_shift_16_table[shift + 1]; - FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7; -} - - -M68KMAKE_OP(asl, 32, s, .) -{ - uint* r_dst = &DY; - uint shift = (((REG_IR >> 9) - 1) & 7) + 1; - uint src = *r_dst; - uint res = MASK_OUT_ABOVE_32(src << shift); - - *r_dst = res; - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_X = FLAG_C = src >> (24-shift); - src &= m68ki_shift_32_table[shift + 1]; - FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7; -} - - -M68KMAKE_OP(asl, 8, r, .) -{ - uint* r_dst = &DY; - uint shift = DX & 0x3f; - uint src = MASK_OUT_ABOVE_8(*r_dst); - uint res = MASK_OUT_ABOVE_8(src << shift); - - if(shift != 0) - { - USE_CYCLES(shift<> 8; - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - src &= m68ki_shift_16_table[shift + 1]; - FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7; - return; - } - - *r_dst &= 0xffff0000; - FLAG_X = FLAG_C = ((shift == 16 ? src & 1 : 0))<<8; - FLAG_N = NFLAG_CLEAR; - FLAG_Z = ZFLAG_SET; - FLAG_V = (!(src == 0))<<7; - return; - } - - FLAG_C = CFLAG_CLEAR; - FLAG_N = NFLAG_16(src); - FLAG_Z = src; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(asl, 32, r, .) -{ - uint* r_dst = &DY; - uint shift = DX & 0x3f; - uint src = *r_dst; - uint res = MASK_OUT_ABOVE_32(src << shift); - - if(shift != 0) - { - USE_CYCLES(shift<> (32 - shift)) << 8; - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - src &= m68ki_shift_32_table[shift + 1]; - FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7; - return; - } - - *r_dst = 0; - FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8; - FLAG_N = NFLAG_CLEAR; - FLAG_Z = ZFLAG_SET; - FLAG_V = (!(src == 0))<<7; - return; - } - - FLAG_C = CFLAG_CLEAR; - FLAG_N = NFLAG_32(src); - FLAG_Z = src; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(asl, 16, ., .) -{ - uint ea = M68KMAKE_GET_EA_AY_16; - uint src = m68ki_read_16(ea); - uint res = MASK_OUT_ABOVE_16(src << 1); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_X = FLAG_C = src >> 7; - src &= 0xc000; - FLAG_V = (!(src == 0 || src == 0xc000))<<7; -} - - -M68KMAKE_OP(bcc, 8, ., .) -{ - if(M68KMAKE_CC) - { - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR)); - return; - } - USE_CYCLES(CYC_BCC_NOTAKE_B); -} - - -M68KMAKE_OP(bcc, 16, ., .) -{ - if(M68KMAKE_CC) - { - uint offset = OPER_I_16(); - REG_PC -= 2; - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_16(offset); - return; - } - REG_PC += 2; - USE_CYCLES(CYC_BCC_NOTAKE_W); -} - - -M68KMAKE_OP(bcc, 32, ., .) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(M68KMAKE_CC) - { - uint offset = OPER_I_32(); - REG_PC -= 4; - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_32(offset); - return; - } - REG_PC += 4; - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(bchg, 32, r, d) -{ - uint* r_dst = &DY; - uint mask = 1 << (DX & 0x1f); - - FLAG_Z = *r_dst & mask; - *r_dst ^= mask; -} - - -M68KMAKE_OP(bchg, 8, r, .) -{ - uint ea = M68KMAKE_GET_EA_AY_8; - uint src = m68ki_read_8(ea); - uint mask = 1 << (DX & 7); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src ^ mask); -} - - -M68KMAKE_OP(bchg, 32, s, d) -{ - uint* r_dst = &DY; - uint mask = 1 << (OPER_I_8() & 0x1f); - - FLAG_Z = *r_dst & mask; - *r_dst ^= mask; -} - - -M68KMAKE_OP(bchg, 8, s, .) -{ - uint mask = 1 << (OPER_I_8() & 7); - uint ea = M68KMAKE_GET_EA_AY_8; - uint src = m68ki_read_8(ea); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src ^ mask); -} - - -M68KMAKE_OP(bclr, 32, r, d) -{ - uint* r_dst = &DY; - uint mask = 1 << (DX & 0x1f); - - FLAG_Z = *r_dst & mask; - *r_dst &= ~mask; -} - - -M68KMAKE_OP(bclr, 8, r, .) -{ - uint ea = M68KMAKE_GET_EA_AY_8; - uint src = m68ki_read_8(ea); - uint mask = 1 << (DX & 7); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src & ~mask); -} - - -M68KMAKE_OP(bclr, 32, s, d) -{ - uint* r_dst = &DY; - uint mask = 1 << (OPER_I_8() & 0x1f); - - FLAG_Z = *r_dst & mask; - *r_dst &= ~mask; -} - - -M68KMAKE_OP(bclr, 8, s, .) -{ - uint mask = 1 << (OPER_I_8() & 7); - uint ea = M68KMAKE_GET_EA_AY_8; - uint src = m68ki_read_8(ea); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src & ~mask); -} - - -M68KMAKE_OP(bfchg, 32, ., d) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint offset = (word2>>6)&31; - uint width = word2; - uint* data = &DY; - uint64 mask; - - - if(BIT_B(word2)) - offset = REG_D[offset&7]; - if(BIT_5(word2)) - width = REG_D[width&7]; - - offset &= 31; - width = ((width-1) & 31) + 1; - - mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); - mask = ROR_32(mask, offset); - - FLAG_N = NFLAG_32(*data<>6)&31; - uint width = word2; - uint mask_base; - uint data_long; - uint mask_long; - uint data_byte = 0; - uint mask_byte = 0; - uint ea = M68KMAKE_GET_EA_AY_8; - - - if(BIT_B(word2)) - offset = MAKE_INT_32(REG_D[offset&7]); - if(BIT_5(word2)) - width = REG_D[width&7]; - - /* Offset is signed so we have to use ugly math =( */ - ea += offset / 8; - offset %= 8; - if(offset < 0) - { - offset += 8; - ea--; - } - width = ((width-1) & 31) + 1; - - mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); - mask_long = mask_base >> offset; - - data_long = m68ki_read_32(ea); - FLAG_N = NFLAG_32(data_long << offset); - FLAG_Z = data_long & mask_long; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - m68ki_write_32(ea, data_long ^ mask_long); - - if((width + offset) > 32) - { - mask_byte = MASK_OUT_ABOVE_8(mask_base); - data_byte = m68ki_read_8(ea+4); - FLAG_Z |= (data_byte & mask_byte); - m68ki_write_8(ea+4, data_byte ^ mask_byte); - } - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(bfclr, 32, ., d) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint offset = (word2>>6)&31; - uint width = word2; - uint* data = &DY; - uint64 mask; - - - if(BIT_B(word2)) - offset = REG_D[offset&7]; - if(BIT_5(word2)) - width = REG_D[width&7]; - - - offset &= 31; - width = ((width-1) & 31) + 1; - - - mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); - mask = ROR_32(mask, offset); - - FLAG_N = NFLAG_32(*data<>6)&31; - uint width = word2; - uint mask_base; - uint data_long; - uint mask_long; - uint data_byte = 0; - uint mask_byte = 0; - uint ea = M68KMAKE_GET_EA_AY_8; - - - if(BIT_B(word2)) - offset = MAKE_INT_32(REG_D[offset&7]); - if(BIT_5(word2)) - width = REG_D[width&7]; - - /* Offset is signed so we have to use ugly math =( */ - ea += offset / 8; - offset %= 8; - if(offset < 0) - { - offset += 8; - ea--; - } - width = ((width-1) & 31) + 1; - - mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); - mask_long = mask_base >> offset; - - data_long = m68ki_read_32(ea); - FLAG_N = NFLAG_32(data_long << offset); - FLAG_Z = data_long & mask_long; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - m68ki_write_32(ea, data_long & ~mask_long); - - if((width + offset) > 32) - { - mask_byte = MASK_OUT_ABOVE_8(mask_base); - data_byte = m68ki_read_8(ea+4); - FLAG_Z |= (data_byte & mask_byte); - m68ki_write_8(ea+4, data_byte & ~mask_byte); - } - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(bfexts, 32, ., d) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint offset = (word2>>6)&31; - uint width = word2; - uint64 data = DY; - - - if(BIT_B(word2)) - offset = REG_D[offset&7]; - if(BIT_5(word2)) - width = REG_D[width&7]; - - offset &= 31; - width = ((width-1) & 31) + 1; - - data = ROL_32(data, offset); - FLAG_N = NFLAG_32(data); - data = MAKE_INT_32(data) >> (32 - width); - - FLAG_Z = data; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - REG_D[(word2>>12)&7] = data; - - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(bfexts, 32, ., .) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - sint offset = (word2>>6)&31; - uint width = word2; - uint data; - uint ea = M68KMAKE_GET_EA_AY_8; - - - if(BIT_B(word2)) - offset = MAKE_INT_32(REG_D[offset&7]); - if(BIT_5(word2)) - width = REG_D[width&7]; - - /* Offset is signed so we have to use ugly math =( */ - ea += offset / 8; - offset %= 8; - if(offset < 0) - { - offset += 8; - ea--; - } - width = ((width-1) & 31) + 1; - - data = m68ki_read_32(ea); - - data = MASK_OUT_ABOVE_32(data< 32) - data |= (m68ki_read_8(ea+4) << offset) >> 8; - - FLAG_N = NFLAG_32(data); - data = MAKE_INT_32(data) >> (32 - width); - - FLAG_Z = data; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - REG_D[(word2 >> 12) & 7] = data; - - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(bfextu, 32, ., d) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint offset = (word2>>6)&31; - uint width = word2; - uint64 data = DY; - - - if(BIT_B(word2)) - offset = REG_D[offset&7]; - if(BIT_5(word2)) - width = REG_D[width&7]; - - offset &= 31; - width = ((width-1) & 31) + 1; - - data = ROL_32(data, offset); - FLAG_N = NFLAG_32(data); - data >>= 32 - width; - - FLAG_Z = data; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - REG_D[(word2>>12)&7] = data; - - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(bfextu, 32, ., .) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - sint offset = (word2>>6)&31; - uint width = word2; - uint data; - uint ea = M68KMAKE_GET_EA_AY_8; - - - if(BIT_B(word2)) - offset = MAKE_INT_32(REG_D[offset&7]); - if(BIT_5(word2)) - width = REG_D[width&7]; - - /* Offset is signed so we have to use ugly math =( */ - ea += offset / 8; - offset %= 8; - if(offset < 0) - { - offset += 8; - ea--; - } - width = ((width-1) & 31) + 1; - - data = m68ki_read_32(ea); - data = MASK_OUT_ABOVE_32(data< 32) - data |= (m68ki_read_8(ea+4) << offset) >> 8; - - FLAG_N = NFLAG_32(data); - data >>= (32 - width); - - FLAG_Z = data; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - REG_D[(word2 >> 12) & 7] = data; - - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(bfffo, 32, ., d) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint offset = (word2>>6)&31; - uint width = word2; - uint64 data = DY; - uint bit; - - - if(BIT_B(word2)) - offset = REG_D[offset&7]; - if(BIT_5(word2)) - width = REG_D[width&7]; - - offset &= 31; - width = ((width-1) & 31) + 1; - - data = ROL_32(data, offset); - FLAG_N = NFLAG_32(data); - data >>= 32 - width; - - FLAG_Z = data; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1) - offset++; - - REG_D[(word2>>12)&7] = offset; - - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(bfffo, 32, ., .) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - sint offset = (word2>>6)&31; - sint local_offset; - uint width = word2; - uint data; - uint bit; - uint ea = M68KMAKE_GET_EA_AY_8; - - - if(BIT_B(word2)) - offset = MAKE_INT_32(REG_D[offset&7]); - if(BIT_5(word2)) - width = REG_D[width&7]; - - /* Offset is signed so we have to use ugly math =( */ - ea += offset / 8; - local_offset = offset % 8; - if(local_offset < 0) - { - local_offset += 8; - ea--; - } - width = ((width-1) & 31) + 1; - - data = m68ki_read_32(ea); - data = MASK_OUT_ABOVE_32(data< 32) - data |= (m68ki_read_8(ea+4) << local_offset) >> 8; - - FLAG_N = NFLAG_32(data); - data >>= (32 - width); - - FLAG_Z = data; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1) - offset++; - - REG_D[(word2>>12)&7] = offset; - - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(bfins, 32, ., d) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint offset = (word2>>6)&31; - uint width = word2; - uint* data = &DY; - uint64 mask; - uint64 insert = REG_D[(word2>>12)&7]; - - - if(BIT_B(word2)) - offset = REG_D[offset&7]; - if(BIT_5(word2)) - width = REG_D[width&7]; - - - offset &= 31; - width = ((width-1) & 31) + 1; - - - mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); - mask = ROR_32(mask, offset); - - insert = MASK_OUT_ABOVE_32(insert << (32 - width)); - FLAG_N = NFLAG_32(insert); - FLAG_Z = insert; - insert = ROR_32(insert, offset); - - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - *data &= ~mask; - *data |= insert; - - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(bfins, 32, ., .) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - sint offset = (word2>>6)&31; - uint width = word2; - uint insert_base = REG_D[(word2>>12)&7]; - uint insert_long; - uint insert_byte; - uint mask_base; - uint data_long; - uint mask_long; - uint data_byte = 0; - uint mask_byte = 0; - uint ea = M68KMAKE_GET_EA_AY_8; - - - if(BIT_B(word2)) - offset = MAKE_INT_32(REG_D[offset&7]); - if(BIT_5(word2)) - width = REG_D[width&7]; - - /* Offset is signed so we have to use ugly math =( */ - ea += offset / 8; - offset %= 8; - if(offset < 0) - { - offset += 8; - ea--; - } - width = ((width-1) & 31) + 1; - - mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); - mask_long = mask_base >> offset; - - insert_base = MASK_OUT_ABOVE_32(insert_base << (32 - width)); - FLAG_N = NFLAG_32(insert_base); - FLAG_Z = insert_base; - insert_long = insert_base >> offset; - - data_long = m68ki_read_32(ea); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - m68ki_write_32(ea, (data_long & ~mask_long) | insert_long); - - if((width + offset) > 32) - { - mask_byte = MASK_OUT_ABOVE_8(mask_base); - insert_byte = MASK_OUT_ABOVE_8(insert_base); - data_byte = m68ki_read_8(ea+4); - FLAG_Z |= (data_byte & mask_byte); - m68ki_write_8(ea+4, (data_byte & ~mask_byte) | insert_byte); - } - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(bfset, 32, ., d) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint offset = (word2>>6)&31; - uint width = word2; - uint* data = &DY; - uint64 mask; - - - if(BIT_B(word2)) - offset = REG_D[offset&7]; - if(BIT_5(word2)) - width = REG_D[width&7]; - - - offset &= 31; - width = ((width-1) & 31) + 1; - - - mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); - mask = ROR_32(mask, offset); - - FLAG_N = NFLAG_32(*data<>6)&31; - uint width = word2; - uint mask_base; - uint data_long; - uint mask_long; - uint data_byte = 0; - uint mask_byte = 0; - uint ea = M68KMAKE_GET_EA_AY_8; - - - if(BIT_B(word2)) - offset = MAKE_INT_32(REG_D[offset&7]); - if(BIT_5(word2)) - width = REG_D[width&7]; - - /* Offset is signed so we have to use ugly math =( */ - ea += offset / 8; - offset %= 8; - if(offset < 0) - { - offset += 8; - ea--; - } - width = ((width-1) & 31) + 1; - - - mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); - mask_long = mask_base >> offset; - - data_long = m68ki_read_32(ea); - FLAG_N = NFLAG_32(data_long << offset); - FLAG_Z = data_long & mask_long; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - m68ki_write_32(ea, data_long | mask_long); - - if((width + offset) > 32) - { - mask_byte = MASK_OUT_ABOVE_8(mask_base); - data_byte = m68ki_read_8(ea+4); - FLAG_Z |= (data_byte & mask_byte); - m68ki_write_8(ea+4, data_byte | mask_byte); - } - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(bftst, 32, ., d) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint offset = (word2>>6)&31; - uint width = word2; - uint* data = &DY; - uint64 mask; - - - if(BIT_B(word2)) - offset = REG_D[offset&7]; - if(BIT_5(word2)) - width = REG_D[width&7]; - - - offset &= 31; - width = ((width-1) & 31) + 1; - - - mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); - mask = ROR_32(mask, offset); - - FLAG_N = NFLAG_32(*data<>6)&31; - uint width = word2; - uint mask_base; - uint data_long; - uint mask_long; - uint data_byte = 0; - uint mask_byte = 0; - uint ea = M68KMAKE_GET_EA_AY_8; - - if(BIT_B(word2)) - offset = MAKE_INT_32(REG_D[offset&7]); - if(BIT_5(word2)) - width = REG_D[width&7]; - - /* Offset is signed so we have to use ugly math =( */ - ea += offset / 8; - offset %= 8; - if(offset < 0) - { - offset += 8; - ea--; - } - width = ((width-1) & 31) + 1; - - - mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); - mask_long = mask_base >> offset; - - data_long = m68ki_read_32(ea); - FLAG_N = ((data_long & (0x80000000 >> offset))<>24; - FLAG_Z = data_long & mask_long; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - if((width + offset) > 32) - { - mask_byte = MASK_OUT_ABOVE_8(mask_base); - data_byte = m68ki_read_8(ea+4); - FLAG_Z |= (data_byte & mask_byte); - } - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(bkpt, 0, ., .) -{ - if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) - { - m68ki_bkpt_ack(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE) ? REG_IR & 7 : 0); /* auto-disable (see m68kcpu.h) */ - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(bra, 8, ., .) -{ - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR)); - if(REG_PC == REG_PPC) - USE_ALL_CYCLES(); -} - - -M68KMAKE_OP(bra, 16, ., .) -{ - uint offset = OPER_I_16(); - REG_PC -= 2; - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_16(offset); - if(REG_PC == REG_PPC) - USE_ALL_CYCLES(); -} - - -M68KMAKE_OP(bra, 32, ., .) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint offset = OPER_I_32(); - REG_PC -= 4; - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_32(offset); - if(REG_PC == REG_PPC) - USE_ALL_CYCLES(); - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(bset, 32, r, d) -{ - uint* r_dst = &DY; - uint mask = 1 << (DX & 0x1f); - - FLAG_Z = *r_dst & mask; - *r_dst |= mask; -} - - -M68KMAKE_OP(bset, 8, r, .) -{ - uint ea = M68KMAKE_GET_EA_AY_8; - uint src = m68ki_read_8(ea); - uint mask = 1 << (DX & 7); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src | mask); -} - - -M68KMAKE_OP(bset, 32, s, d) -{ - uint* r_dst = &DY; - uint mask = 1 << (OPER_I_8() & 0x1f); - - FLAG_Z = *r_dst & mask; - *r_dst |= mask; -} - - -M68KMAKE_OP(bset, 8, s, .) -{ - uint mask = 1 << (OPER_I_8() & 7); - uint ea = M68KMAKE_GET_EA_AY_8; - uint src = m68ki_read_8(ea); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src | mask); -} - - -M68KMAKE_OP(bsr, 8, ., .) -{ - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_push_32(REG_PC); - m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR)); -} - - -M68KMAKE_OP(bsr, 16, ., .) -{ - uint offset = OPER_I_16(); - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_push_32(REG_PC); - REG_PC -= 2; - m68ki_branch_16(offset); -} - - -M68KMAKE_OP(bsr, 32, ., .) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint offset = OPER_I_32(); - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_push_32(REG_PC); - REG_PC -= 4; - m68ki_branch_32(offset); - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(btst, 32, r, d) -{ - FLAG_Z = DY & (1 << (DX & 0x1f)); -} - - -M68KMAKE_OP(btst, 8, r, .) -{ - FLAG_Z = M68KMAKE_GET_OPER_AY_8 & (1 << (DX & 7)); -} - - -M68KMAKE_OP(btst, 32, s, d) -{ - FLAG_Z = DY & (1 << (OPER_I_8() & 0x1f)); -} - - -M68KMAKE_OP(btst, 8, s, .) -{ - uint bit = OPER_I_8() & 7; - - FLAG_Z = M68KMAKE_GET_OPER_AY_8 & (1 << bit); -} - - -M68KMAKE_OP(callm, 32, ., .) -{ - /* note: watch out for pcrelative modes */ - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - { - uint ea = M68KMAKE_GET_EA_AY_32; - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - REG_PC += 2; -(void)ea; /* just to avoid an 'unused variable' warning */ - M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", - m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, - m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(cas, 8, ., .) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint ea = M68KMAKE_GET_EA_AY_8; - uint dest = m68ki_read_8(ea); - uint* compare = ®_D[word2 & 7]; - uint res = dest - MASK_OUT_ABOVE_8(*compare); - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_V = VFLAG_SUB_8(*compare, dest, res); - FLAG_C = CFLAG_8(res); - - if(COND_NE()) - *compare = MASK_OUT_BELOW_8(*compare) | dest; - else - { - USE_CYCLES(3); - m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7])); - } - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(cas, 16, ., .) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint ea = M68KMAKE_GET_EA_AY_16; - uint dest = m68ki_read_16(ea); - uint* compare = ®_D[word2 & 7]; - uint res = dest - MASK_OUT_ABOVE_16(*compare); - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_V = VFLAG_SUB_16(*compare, dest, res); - FLAG_C = CFLAG_16(res); - - if(COND_NE()) - *compare = MASK_OUT_BELOW_16(*compare) | dest; - else - { - USE_CYCLES(3); - m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7])); - } - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(cas, 32, ., .) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint ea = M68KMAKE_GET_EA_AY_32; - uint dest = m68ki_read_32(ea); - uint* compare = ®_D[word2 & 7]; - uint res = dest - *compare; - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(*compare, dest, res); - FLAG_C = CFLAG_SUB_32(*compare, dest, res); - - if(COND_NE()) - *compare = dest; - else - { - USE_CYCLES(3); - m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]); - } - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(cas2, 16, ., .) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_32(); - uint* compare1 = ®_D[(word2 >> 16) & 7]; - uint ea1 = REG_DA[(word2 >> 28) & 15]; - uint dest1 = m68ki_read_16(ea1); - uint res1 = dest1 - MASK_OUT_ABOVE_16(*compare1); - uint* compare2 = ®_D[word2 & 7]; - uint ea2 = REG_DA[(word2 >> 12) & 15]; - uint dest2 = m68ki_read_16(ea2); - uint res2; - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - FLAG_N = NFLAG_16(res1); - FLAG_Z = MASK_OUT_ABOVE_16(res1); - FLAG_V = VFLAG_SUB_16(*compare1, dest1, res1); - FLAG_C = CFLAG_16(res1); - - if(COND_EQ()) - { - res2 = dest2 - MASK_OUT_ABOVE_16(*compare2); - - FLAG_N = NFLAG_16(res2); - FLAG_Z = MASK_OUT_ABOVE_16(res2); - FLAG_V = VFLAG_SUB_16(*compare2, dest2, res2); - FLAG_C = CFLAG_16(res2); - - if(COND_EQ()) - { - USE_CYCLES(3); - m68ki_write_16(ea1, REG_D[(word2 >> 22) & 7]); - m68ki_write_16(ea2, REG_D[(word2 >> 6) & 7]); - return; - } - } - *compare1 = BIT_1F(word2) ? MAKE_INT_16(dest1) : MASK_OUT_BELOW_16(*compare1) | dest1; - *compare2 = BIT_F(word2) ? MAKE_INT_16(dest2) : MASK_OUT_BELOW_16(*compare2) | dest2; - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(cas2, 32, ., .) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_32(); - uint* compare1 = ®_D[(word2 >> 16) & 7]; - uint ea1 = REG_DA[(word2 >> 28) & 15]; - uint dest1 = m68ki_read_32(ea1); - uint res1 = dest1 - *compare1; - uint* compare2 = ®_D[word2 & 7]; - uint ea2 = REG_DA[(word2 >> 12) & 15]; - uint dest2 = m68ki_read_32(ea2); - uint res2; - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - FLAG_N = NFLAG_32(res1); - FLAG_Z = MASK_OUT_ABOVE_32(res1); - FLAG_V = VFLAG_SUB_32(*compare1, dest1, res1); - FLAG_C = CFLAG_SUB_32(*compare1, dest1, res1); - - if(COND_EQ()) - { - res2 = dest2 - *compare2; - - FLAG_N = NFLAG_32(res2); - FLAG_Z = MASK_OUT_ABOVE_32(res2); - FLAG_V = VFLAG_SUB_32(*compare2, dest2, res2); - FLAG_C = CFLAG_SUB_32(*compare2, dest2, res2); - - if(COND_EQ()) - { - USE_CYCLES(3); - m68ki_write_32(ea1, REG_D[(word2 >> 22) & 7]); - m68ki_write_32(ea2, REG_D[(word2 >> 6) & 7]); - return; - } - } - *compare1 = dest1; - *compare2 = dest2; - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(chk, 16, ., d) -{ - sint src = MAKE_INT_16(DX); - sint bound = MAKE_INT_16(DY); - - FLAG_Z = ZFLAG_16(src); /* Undocumented */ - FLAG_V = VFLAG_CLEAR; /* Undocumented */ - FLAG_C = CFLAG_CLEAR; /* Undocumented */ - - if(src >= 0 && src <= bound) - { - return; - } - FLAG_N = (src < 0)<<7; - m68ki_exception_trap(EXCEPTION_CHK); -} - - -M68KMAKE_OP(chk, 16, ., .) -{ - sint src = MAKE_INT_16(DX); - sint bound = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16); - - FLAG_Z = ZFLAG_16(src); /* Undocumented */ - FLAG_V = VFLAG_CLEAR; /* Undocumented */ - FLAG_C = CFLAG_CLEAR; /* Undocumented */ - - if(src >= 0 && src <= bound) - { - return; - } - FLAG_N = (src < 0)<<7; - m68ki_exception_trap(EXCEPTION_CHK); -} - - -M68KMAKE_OP(chk, 32, ., d) -{ - logerror("%08x: Chk 32d\n",activecpu_get_pc()); - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - sint src = MAKE_INT_32(DX); - sint bound = MAKE_INT_32(DY); - - FLAG_Z = ZFLAG_32(src); /* Undocumented */ - FLAG_V = VFLAG_CLEAR; /* Undocumented */ - FLAG_C = CFLAG_CLEAR; /* Undocumented */ - - if(src >= 0 && src <= bound) - { - return; - } - FLAG_N = (src < 0)<<7; - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(chk, 32, ., .) -{ - logerror("%08x: Chk 32\n",activecpu_get_pc()); - - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - sint src = MAKE_INT_32(DX); - sint bound = MAKE_INT_32(M68KMAKE_GET_OPER_AY_32); - - FLAG_Z = ZFLAG_32(src); /* Undocumented */ - FLAG_V = VFLAG_CLEAR; /* Undocumented */ - FLAG_C = CFLAG_CLEAR; /* Undocumented */ - - if(src >= 0 && src <= bound) - { - return; - } - FLAG_N = (src < 0)<<7; - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(chk2cmp2, 8, ., pcdi) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint compare = REG_DA[(word2 >> 12) & 15]&0xff; - uint ea = EA_PCDI_8(); - uint lower_bound = m68ki_read_pcrel_8(ea); - uint upper_bound = m68ki_read_pcrel_8(ea + 1); - - if(!BIT_F(word2)) - FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound); - else - FLAG_C = compare - lower_bound; - FLAG_Z = !((upper_bound==compare) | (lower_bound==compare)); - if(COND_CS()) - { - if(BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - - FLAG_C = upper_bound - compare; - if(COND_CS() && BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(chk2cmp2, 8, ., pcix) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint compare = REG_DA[(word2 >> 12) & 15]&0xff; - uint ea = EA_PCIX_8(); - uint lower_bound = m68ki_read_pcrel_8(ea); - uint upper_bound = m68ki_read_pcrel_8(ea + 1); - - if(!BIT_F(word2)) - FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound); - else - FLAG_C = compare - lower_bound; - FLAG_Z = !((upper_bound==compare) | (lower_bound==compare)); - if(COND_CS()) - { - if(BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - - FLAG_C = upper_bound - compare; - if(COND_CS() && BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(chk2cmp2, 8, ., .) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint compare = REG_DA[(word2 >> 12) & 15]&0xff; - uint ea = M68KMAKE_GET_EA_AY_8; - uint lower_bound = m68ki_read_8(ea); - uint upper_bound = m68ki_read_8(ea + 1); - - if(!BIT_F(word2)) - FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound); - else - FLAG_C = compare - lower_bound; - FLAG_Z = !((upper_bound==compare) | (lower_bound==compare)); - if(COND_CS()) - { - if(BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - - FLAG_C = upper_bound - compare; - if(COND_CS() && BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(chk2cmp2, 16, ., pcdi) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint compare = REG_DA[(word2 >> 12) & 15]&0xffff; - uint ea = EA_PCDI_16(); - uint lower_bound = m68ki_read_pcrel_16(ea); - uint upper_bound = m68ki_read_pcrel_16(ea + 2); - - if(!BIT_F(word2)) - FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound); - else - FLAG_C = compare - lower_bound; - FLAG_Z = !((upper_bound==compare) | (lower_bound==compare)); - FLAG_C = CFLAG_16(FLAG_C); - if(COND_CS()) - { - if(BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - - if(!BIT_F(word2)) - FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare); - else - FLAG_C = upper_bound - compare; - FLAG_C = CFLAG_16(FLAG_C); - if(COND_CS() && BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(chk2cmp2, 16, ., pcix) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint compare = REG_DA[(word2 >> 12) & 15]&0xffff; - uint ea = EA_PCIX_16(); - uint lower_bound = m68ki_read_pcrel_16(ea); - uint upper_bound = m68ki_read_pcrel_16(ea + 2); - - if(!BIT_F(word2)) - FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound); - else - FLAG_C = compare - lower_bound; - FLAG_Z = !((upper_bound==compare) | (lower_bound==compare)); - FLAG_C = CFLAG_16(FLAG_C); - if(COND_CS()) - { - if(BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - - if(!BIT_F(word2)) - FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare); - else - FLAG_C = upper_bound - compare; - FLAG_C = CFLAG_16(FLAG_C); - if(COND_CS() && BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(chk2cmp2, 16, ., .) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint compare = REG_DA[(word2 >> 12) & 15]&0xffff; - uint ea = M68KMAKE_GET_EA_AY_16; - uint lower_bound = m68ki_read_16(ea); - uint upper_bound = m68ki_read_16(ea + 2); - - if(!BIT_F(word2)) - FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound); - else - FLAG_C = compare - lower_bound; - - FLAG_Z = !((upper_bound==compare) | (lower_bound==compare)); - FLAG_C = CFLAG_16(FLAG_C); - if(COND_CS()) - { - if(BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - if(!BIT_F(word2)) - FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare); - else - FLAG_C = upper_bound - compare; - - FLAG_C = CFLAG_16(FLAG_C); - if(COND_CS() && BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(chk2cmp2, 32, ., pcdi) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint compare = REG_DA[(word2 >> 12) & 15]; - uint ea = EA_PCDI_32(); - uint lower_bound = m68ki_read_pcrel_32(ea); - uint upper_bound = m68ki_read_pcrel_32(ea + 4); - - FLAG_C = compare - lower_bound; - FLAG_Z = !((upper_bound==compare) | (lower_bound==compare)); - FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C); - if(COND_CS()) - { - if(BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - - FLAG_C = upper_bound - compare; - FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C); - if(COND_CS() && BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(chk2cmp2, 32, ., pcix) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint compare = REG_DA[(word2 >> 12) & 15]; - uint ea = EA_PCIX_32(); - uint lower_bound = m68ki_read_pcrel_32(ea); - uint upper_bound = m68ki_read_pcrel_32(ea + 4); - - FLAG_C = compare - lower_bound; - FLAG_Z = !((upper_bound==compare) | (lower_bound==compare)); - FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C); - if(COND_CS()) - { - if(BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - - FLAG_C = upper_bound - compare; - FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C); - if(COND_CS() && BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(chk2cmp2, 32, ., .) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint compare = REG_DA[(word2 >> 12) & 15]; - uint ea = M68KMAKE_GET_EA_AY_32; - uint lower_bound = m68ki_read_32(ea); - uint upper_bound = m68ki_read_32(ea + 4); - - FLAG_C = compare - lower_bound; - FLAG_Z = !((upper_bound==compare) | (lower_bound==compare)); - FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C); - if(COND_CS()) - { - if(BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - - FLAG_C = upper_bound - compare; - FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C); - if(COND_CS() && BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(clr, 8, ., d) -{ - DY &= 0xffffff00; - - FLAG_N = NFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - FLAG_Z = ZFLAG_SET; -} - - -M68KMAKE_OP(clr, 8, ., .) -{ - m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0); - - FLAG_N = NFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - FLAG_Z = ZFLAG_SET; -} - - -M68KMAKE_OP(clr, 16, ., d) -{ - DY &= 0xffff0000; - - FLAG_N = NFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - FLAG_Z = ZFLAG_SET; -} - - -M68KMAKE_OP(clr, 16, ., .) -{ - m68ki_write_16(M68KMAKE_GET_EA_AY_16, 0); - - FLAG_N = NFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - FLAG_Z = ZFLAG_SET; -} - - -M68KMAKE_OP(clr, 32, ., d) -{ - DY = 0; - - FLAG_N = NFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - FLAG_Z = ZFLAG_SET; -} - - -M68KMAKE_OP(clr, 32, ., .) -{ - m68ki_write_32(M68KMAKE_GET_EA_AY_32, 0); - - FLAG_N = NFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - FLAG_Z = ZFLAG_SET; -} - - -M68KMAKE_OP(cmp, 8, ., d) -{ - uint src = MASK_OUT_ABOVE_8(DY); - uint dst = MASK_OUT_ABOVE_8(DX); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - FLAG_C = CFLAG_8(res); -} - - -M68KMAKE_OP(cmp, 8, ., .) -{ - uint src = M68KMAKE_GET_OPER_AY_8; - uint dst = MASK_OUT_ABOVE_8(DX); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - FLAG_C = CFLAG_8(res); -} - - -M68KMAKE_OP(cmp, 16, ., d) -{ - uint src = MASK_OUT_ABOVE_16(DY); - uint dst = MASK_OUT_ABOVE_16(DX); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - FLAG_C = CFLAG_16(res); -} - - -M68KMAKE_OP(cmp, 16, ., a) -{ - uint src = MASK_OUT_ABOVE_16(AY); - uint dst = MASK_OUT_ABOVE_16(DX); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - FLAG_C = CFLAG_16(res); -} - - -M68KMAKE_OP(cmp, 16, ., .) -{ - uint src = M68KMAKE_GET_OPER_AY_16; - uint dst = MASK_OUT_ABOVE_16(DX); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - FLAG_C = CFLAG_16(res); -} - - -M68KMAKE_OP(cmp, 32, ., d) -{ - uint src = DY; - uint dst = DX; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); -} - - -M68KMAKE_OP(cmp, 32, ., a) -{ - uint src = AY; - uint dst = DX; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); -} - - -M68KMAKE_OP(cmp, 32, ., .) -{ - uint src = M68KMAKE_GET_OPER_AY_32; - uint dst = DX; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); -} - - -M68KMAKE_OP(cmpa, 16, ., d) -{ - uint src = MAKE_INT_16(DY); - uint dst = AX; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); -} - - -M68KMAKE_OP(cmpa, 16, ., a) -{ - uint src = MAKE_INT_16(AY); - uint dst = AX; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); -} - - -M68KMAKE_OP(cmpa, 16, ., .) -{ - uint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16); - uint dst = AX; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); -} - - -M68KMAKE_OP(cmpa, 32, ., d) -{ - uint src = DY; - uint dst = AX; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); -} - - -M68KMAKE_OP(cmpa, 32, ., a) -{ - uint src = AY; - uint dst = AX; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); -} - - -M68KMAKE_OP(cmpa, 32, ., .) -{ - uint src = M68KMAKE_GET_OPER_AY_32; - uint dst = AX; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); -} - - -M68KMAKE_OP(cmpi, 8, ., d) -{ - uint src = OPER_I_8(); - uint dst = MASK_OUT_ABOVE_8(DY); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - FLAG_C = CFLAG_8(res); -} - - -M68KMAKE_OP(cmpi, 8, ., .) -{ - uint src = OPER_I_8(); - uint dst = M68KMAKE_GET_OPER_AY_8; - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - FLAG_C = CFLAG_8(res); -} - - -M68KMAKE_OP(cmpi, 8, ., pcdi) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint src = OPER_I_8(); - uint dst = OPER_PCDI_8(); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - FLAG_C = CFLAG_8(res); - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(cmpi, 8, ., pcix) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint src = OPER_I_8(); - uint dst = OPER_PCIX_8(); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - FLAG_C = CFLAG_8(res); - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(cmpi, 16, ., d) -{ - uint src = OPER_I_16(); - uint dst = MASK_OUT_ABOVE_16(DY); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - FLAG_C = CFLAG_16(res); -} - - -M68KMAKE_OP(cmpi, 16, ., .) -{ - uint src = OPER_I_16(); - uint dst = M68KMAKE_GET_OPER_AY_16; - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - FLAG_C = CFLAG_16(res); -} - - -M68KMAKE_OP(cmpi, 16, ., pcdi) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint src = OPER_I_16(); - uint dst = OPER_PCDI_16(); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - FLAG_C = CFLAG_16(res); - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(cmpi, 16, ., pcix) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint src = OPER_I_16(); - uint dst = OPER_PCIX_16(); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - FLAG_C = CFLAG_16(res); - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(cmpi, 32, ., d) -{ - uint src = OPER_I_32(); - uint dst = DY; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); -} - - -M68KMAKE_OP(cmpi, 32, ., .) -{ - uint src = OPER_I_32(); - uint dst = M68KMAKE_GET_OPER_AY_32; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); -} - - -M68KMAKE_OP(cmpi, 32, ., pcdi) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint src = OPER_I_32(); - uint dst = OPER_PCDI_32(); - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(cmpi, 32, ., pcix) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint src = OPER_I_32(); - uint dst = OPER_PCIX_32(); - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(cmpm, 8, ., ax7) -{ - uint src = OPER_AY_PI_8(); - uint dst = OPER_A7_PI_8(); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - FLAG_C = CFLAG_8(res); -} - - -M68KMAKE_OP(cmpm, 8, ., ay7) -{ - uint src = OPER_A7_PI_8(); - uint dst = OPER_AX_PI_8(); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - FLAG_C = CFLAG_8(res); -} - - -M68KMAKE_OP(cmpm, 8, ., axy7) -{ - uint src = OPER_A7_PI_8(); - uint dst = OPER_A7_PI_8(); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - FLAG_C = CFLAG_8(res); -} - - -M68KMAKE_OP(cmpm, 8, ., .) -{ - uint src = OPER_AY_PI_8(); - uint dst = OPER_AX_PI_8(); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - FLAG_C = CFLAG_8(res); -} - - -M68KMAKE_OP(cmpm, 16, ., .) -{ - uint src = OPER_AY_PI_16(); - uint dst = OPER_AX_PI_16(); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - FLAG_C = CFLAG_16(res); -} - - -M68KMAKE_OP(cmpm, 32, ., .) -{ - uint src = OPER_AY_PI_32(); - uint dst = OPER_AX_PI_32(); - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); -} - - -M68KMAKE_OP(cpbcc, 32, ., .) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", - m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, - m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); - return; - } - m68ki_exception_1111(); -} - - -M68KMAKE_OP(cpdbcc, 32, ., .) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", - m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, - m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); - return; - } - m68ki_exception_1111(); -} - - -M68KMAKE_OP(cpgen, 32, ., .) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", - m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, - m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); - return; - } - m68ki_exception_1111(); -} - - -M68KMAKE_OP(cpscc, 32, ., .) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", - m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, - m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); - return; - } - m68ki_exception_1111(); -} - - -M68KMAKE_OP(cptrapcc, 32, ., .) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", - m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, - m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); - return; - } - m68ki_exception_1111(); -} - - -M68KMAKE_OP(dbt, 16, ., .) -{ - REG_PC += 2; -} - - -M68KMAKE_OP(dbf, 16, ., .) -{ - uint* r_dst = &DY; - uint res = MASK_OUT_ABOVE_16(*r_dst - 1); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; - if(res != 0xffff) - { - uint offset = OPER_I_16(); - REG_PC -= 2; - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_16(offset); - return; - } - REG_PC += 2; -} - - -M68KMAKE_OP(dbcc, 16, ., .) -{ - if(M68KMAKE_NOT_CC) - { - uint* r_dst = &DY; - uint res = MASK_OUT_ABOVE_16(*r_dst - 1); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; - if(res != 0xffff) - { - uint offset = OPER_I_16(); - REG_PC -= 2; - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_16(offset); - USE_CYCLES(CYC_DBCC_F_NOEXP); - return; - } - REG_PC += 2; - USE_CYCLES(CYC_DBCC_F_EXP); - return; - } - REG_PC += 2; -} - - -M68KMAKE_OP(divs, 16, ., d) -{ - uint* r_dst = &DX; - sint src = MAKE_INT_16(DY); - sint quotient; - sint remainder; - - if(src != 0) - { - if((uint32)*r_dst == 0x80000000 && src == -1) - { - FLAG_Z = 0; - FLAG_N = NFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - *r_dst = 0; - return; - } - - quotient = MAKE_INT_32(*r_dst) / src; - remainder = MAKE_INT_32(*r_dst) % src; - - if(quotient == MAKE_INT_16(quotient)) - { - FLAG_Z = quotient; - FLAG_N = NFLAG_16(quotient); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); - return; - } - FLAG_V = VFLAG_SET; - return; - } - m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); -} - - -M68KMAKE_OP(divs, 16, ., .) -{ - uint* r_dst = &DX; - sint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16); - sint quotient; - sint remainder; - - if(src != 0) - { - if((uint32)*r_dst == 0x80000000 && src == -1) - { - FLAG_Z = 0; - FLAG_N = NFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - *r_dst = 0; - return; - } - - quotient = MAKE_INT_32(*r_dst) / src; - remainder = MAKE_INT_32(*r_dst) % src; - - if(quotient == MAKE_INT_16(quotient)) - { - FLAG_Z = quotient; - FLAG_N = NFLAG_16(quotient); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); - return; - } - FLAG_V = VFLAG_SET; - return; - } - m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); -} - - -M68KMAKE_OP(divu, 16, ., d) -{ - uint* r_dst = &DX; - uint src = MASK_OUT_ABOVE_16(DY); - - if(src != 0) - { - uint quotient = *r_dst / src; - uint remainder = *r_dst % src; - - if(quotient < 0x10000) - { - FLAG_Z = quotient; - FLAG_N = NFLAG_16(quotient); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); - return; - } - FLAG_V = VFLAG_SET; - return; - } - m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); -} - - -M68KMAKE_OP(divu, 16, ., .) -{ - uint* r_dst = &DX; - uint src = M68KMAKE_GET_OPER_AY_16; - - if(src != 0) - { - uint quotient = *r_dst / src; - uint remainder = *r_dst % src; - - if(quotient < 0x10000) - { - FLAG_Z = quotient; - FLAG_N = NFLAG_16(quotient); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); - return; - } - FLAG_V = VFLAG_SET; - return; - } - m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); -} - - -M68KMAKE_OP(divl, 32, ., d) -{ -#if M68K_USE_64_BIT - - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint64 divisor = DY; - uint64 dividend = 0; - uint64 quotient = 0; - uint64 remainder = 0; - - if(divisor != 0) - { - if(BIT_A(word2)) /* 64 bit */ - { - dividend = REG_D[word2 & 7]; - dividend <<= 32; - dividend |= REG_D[(word2 >> 12) & 7]; - - if(BIT_B(word2)) /* signed */ - { - quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor)); - remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor)); - if((sint64)quotient != (sint64)((sint32)quotient)) - { - FLAG_V = VFLAG_SET; - return; - } - } - else /* unsigned */ - { - quotient = dividend / divisor; - if(quotient > 0xffffffff) - { - FLAG_V = VFLAG_SET; - return; - } - remainder = dividend % divisor; - } - } - else /* 32 bit */ - { - dividend = REG_D[(word2 >> 12) & 7]; - if(BIT_B(word2)) /* signed */ - { - quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor)); - remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor)); - } - else /* unsigned */ - { - quotient = dividend / divisor; - remainder = dividend % divisor; - } - } - - REG_D[word2 & 7] = remainder; - REG_D[(word2 >> 12) & 7] = quotient; - - FLAG_N = NFLAG_32(quotient); - FLAG_Z = quotient; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); - return; - } - m68ki_exception_illegal(); - -#else - - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint divisor = DY; - uint dividend_hi = REG_D[word2 & 7]; - uint dividend_lo = REG_D[(word2 >> 12) & 7]; - uint quotient = 0; - uint remainder = 0; - uint dividend_neg = 0; - uint divisor_neg = 0; - sint i; - uint overflow; - - if(divisor != 0) - { - /* quad / long : long quotient, long remainder */ - if(BIT_A(word2)) - { - if(BIT_B(word2)) /* signed */ - { - /* special case in signed divide */ - if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff) - { - REG_D[word2 & 7] = 0; - REG_D[(word2 >> 12) & 7] = 0x80000000; - - FLAG_N = NFLAG_SET; - FLAG_Z = ZFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - if(GET_MSB_32(dividend_hi)) - { - dividend_neg = 1; - dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0)); - dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo); - } - if(GET_MSB_32(divisor)) - { - divisor_neg = 1; - divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor); - - } - } - - /* if the upper long is greater than the divisor, we're overflowing. */ - if(dividend_hi >= divisor) - { - FLAG_V = VFLAG_SET; - return; - } - - for(i = 31; i >= 0; i--) - { - quotient <<= 1; - remainder = (remainder << 1) + ((dividend_hi >> i) & 1); - if(remainder >= divisor) - { - remainder -= divisor; - quotient++; - } - } - for(i = 31; i >= 0; i--) - { - quotient <<= 1; - overflow = GET_MSB_32(remainder); - remainder = (remainder << 1) + ((dividend_lo >> i) & 1); - if(remainder >= divisor || overflow) - { - remainder -= divisor; - quotient++; - } - } - - if(BIT_B(word2)) /* signed */ - { - if(quotient > 0x7fffffff) - { - FLAG_V = VFLAG_SET; - return; - } - if(dividend_neg) - { - remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder); - quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); - } - if(divisor_neg) - quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); - } - - REG_D[word2 & 7] = remainder; - REG_D[(word2 >> 12) & 7] = quotient; - - FLAG_N = NFLAG_32(quotient); - FLAG_Z = quotient; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - - /* long / long: long quotient, maybe long remainder */ - if(BIT_B(word2)) /* signed */ - { - /* Special case in divide */ - if(dividend_lo == 0x80000000 && divisor == 0xffffffff) - { - FLAG_N = NFLAG_SET; - FLAG_Z = ZFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - REG_D[(word2 >> 12) & 7] = 0x80000000; - REG_D[word2 & 7] = 0; - return; - } - REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor); - quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor); - } - else - { - REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor); - quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor); - } - - FLAG_N = NFLAG_32(quotient); - FLAG_Z = quotient; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); - return; - } - m68ki_exception_illegal(); - -#endif -} - - -M68KMAKE_OP(divl, 32, ., .) -{ -#if M68K_USE_64_BIT - - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint64 divisor = M68KMAKE_GET_OPER_AY_32; - uint64 dividend = 0; - uint64 quotient = 0; - uint64 remainder = 0; - - if(divisor != 0) - { - if(BIT_A(word2)) /* 64 bit */ - { - dividend = REG_D[word2 & 7]; - dividend <<= 32; - dividend |= REG_D[(word2 >> 12) & 7]; - - if(BIT_B(word2)) /* signed */ - { - quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor)); - remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor)); - if((sint64)quotient != (sint64)((sint32)quotient)) - { - FLAG_V = VFLAG_SET; - return; - } - } - else /* unsigned */ - { - quotient = dividend / divisor; - if(quotient > 0xffffffff) - { - FLAG_V = VFLAG_SET; - return; - } - remainder = dividend % divisor; - } - } - else /* 32 bit */ - { - dividend = REG_D[(word2 >> 12) & 7]; - if(BIT_B(word2)) /* signed */ - { - quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor)); - remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor)); - } - else /* unsigned */ - { - quotient = dividend / divisor; - remainder = dividend % divisor; - } - } - - REG_D[word2 & 7] = remainder; - REG_D[(word2 >> 12) & 7] = quotient; - - FLAG_N = NFLAG_32(quotient); - FLAG_Z = quotient; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); - return; - } - m68ki_exception_illegal(); - -#else - - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint divisor = M68KMAKE_GET_OPER_AY_32; - uint dividend_hi = REG_D[word2 & 7]; - uint dividend_lo = REG_D[(word2 >> 12) & 7]; - uint quotient = 0; - uint remainder = 0; - uint dividend_neg = 0; - uint divisor_neg = 0; - sint i; - uint overflow; - - if(divisor != 0) - { - /* quad / long : long quotient, long remainder */ - if(BIT_A(word2)) - { - if(BIT_B(word2)) /* signed */ - { - /* special case in signed divide */ - if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff) - { - REG_D[word2 & 7] = 0; - REG_D[(word2 >> 12) & 7] = 0x80000000; - - FLAG_N = NFLAG_SET; - FLAG_Z = ZFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - if(GET_MSB_32(dividend_hi)) - { - dividend_neg = 1; - dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0)); - dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo); - } - if(GET_MSB_32(divisor)) - { - divisor_neg = 1; - divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor); - - } - } - - /* if the upper long is greater than the divisor, we're overflowing. */ - if(dividend_hi >= divisor) - { - FLAG_V = VFLAG_SET; - return; - } - - for(i = 31; i >= 0; i--) - { - quotient <<= 1; - remainder = (remainder << 1) + ((dividend_hi >> i) & 1); - if(remainder >= divisor) - { - remainder -= divisor; - quotient++; - } - } - for(i = 31; i >= 0; i--) - { - quotient <<= 1; - overflow = GET_MSB_32(remainder); - remainder = (remainder << 1) + ((dividend_lo >> i) & 1); - if(remainder >= divisor || overflow) - { - remainder -= divisor; - quotient++; - } - } - - if(BIT_B(word2)) /* signed */ - { - if(quotient > 0x7fffffff) - { - FLAG_V = VFLAG_SET; - return; - } - if(dividend_neg) - { - remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder); - quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); - } - if(divisor_neg) - quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); - } - - REG_D[word2 & 7] = remainder; - REG_D[(word2 >> 12) & 7] = quotient; - - FLAG_N = NFLAG_32(quotient); - FLAG_Z = quotient; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - - /* long / long: long quotient, maybe long remainder */ - if(BIT_B(word2)) /* signed */ - { - /* Special case in divide */ - if(dividend_lo == 0x80000000 && divisor == 0xffffffff) - { - FLAG_N = NFLAG_SET; - FLAG_Z = ZFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - REG_D[(word2 >> 12) & 7] = 0x80000000; - REG_D[word2 & 7] = 0; - return; - } - REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor); - quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor); - } - else - { - REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor); - quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor); - } - - FLAG_N = NFLAG_32(quotient); - FLAG_Z = quotient; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); - return; - } - m68ki_exception_illegal(); - -#endif -} - - -M68KMAKE_OP(eor, 8, ., d) -{ - uint res = MASK_OUT_ABOVE_8(DY ^= MASK_OUT_ABOVE_8(DX)); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(eor, 8, ., .) -{ - uint ea = M68KMAKE_GET_EA_AY_8; - uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea)); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(eor, 16, ., d) -{ - uint res = MASK_OUT_ABOVE_16(DY ^= MASK_OUT_ABOVE_16(DX)); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(eor, 16, ., .) -{ - uint ea = M68KMAKE_GET_EA_AY_16; - uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea)); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(eor, 32, ., d) -{ - uint res = DY ^= DX; - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(eor, 32, ., .) -{ - uint ea = M68KMAKE_GET_EA_AY_32; - uint res = DX ^ m68ki_read_32(ea); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(eori, 8, ., d) -{ - uint res = MASK_OUT_ABOVE_8(DY ^= OPER_I_8()); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(eori, 8, ., .) -{ - uint src = OPER_I_8(); - uint ea = M68KMAKE_GET_EA_AY_8; - uint res = src ^ m68ki_read_8(ea); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(eori, 16, ., d) -{ - uint res = MASK_OUT_ABOVE_16(DY ^= OPER_I_16()); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(eori, 16, ., .) -{ - uint src = OPER_I_16(); - uint ea = M68KMAKE_GET_EA_AY_16; - uint res = src ^ m68ki_read_16(ea); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(eori, 32, ., d) -{ - uint res = DY ^= OPER_I_32(); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(eori, 32, ., .) -{ - uint src = OPER_I_32(); - uint ea = M68KMAKE_GET_EA_AY_32; - uint res = src ^ m68ki_read_32(ea); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(eori, 16, toc, .) -{ - m68ki_set_ccr(m68ki_get_ccr() ^ OPER_I_16()); -} - - -M68KMAKE_OP(eori, 16, tos, .) -{ - if(FLAG_S) - { - uint src = OPER_I_16(); - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_set_sr(m68ki_get_sr() ^ src); - return; - } - m68ki_exception_privilege_violation(); -} - - -M68KMAKE_OP(exg, 32, dd, .) -{ - uint* reg_a = &DX; - uint* reg_b = &DY; - uint tmp = *reg_a; - *reg_a = *reg_b; - *reg_b = tmp; -} - - -M68KMAKE_OP(exg, 32, aa, .) -{ - uint* reg_a = &AX; - uint* reg_b = &AY; - uint tmp = *reg_a; - *reg_a = *reg_b; - *reg_b = tmp; -} - - -M68KMAKE_OP(exg, 32, da, .) -{ - uint* reg_a = &DX; - uint* reg_b = &AY; - uint tmp = *reg_a; - *reg_a = *reg_b; - *reg_b = tmp; -} - - -M68KMAKE_OP(ext, 16, ., .) -{ - uint* r_dst = &DY; - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xff00 : 0); - - FLAG_N = NFLAG_16(*r_dst); - FLAG_Z = MASK_OUT_ABOVE_16(*r_dst); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(ext, 32, ., .) -{ - uint* r_dst = &DY; - - *r_dst = MASK_OUT_ABOVE_16(*r_dst) | (GET_MSB_16(*r_dst) ? 0xffff0000 : 0); - - FLAG_N = NFLAG_32(*r_dst); - FLAG_Z = *r_dst; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(extb, 32, ., .) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint* r_dst = &DY; - - *r_dst = MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xffffff00 : 0); - - FLAG_N = NFLAG_32(*r_dst); - FLAG_Z = *r_dst; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(illegal, 0, ., .) -{ - m68ki_exception_illegal(); -} - -M68KMAKE_OP(jmp, 32, ., .) -{ - m68ki_jump(M68KMAKE_GET_EA_AY_32); - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - if(REG_PC == REG_PPC) - USE_ALL_CYCLES(); -} - - -M68KMAKE_OP(jsr, 32, ., .) -{ - uint ea = M68KMAKE_GET_EA_AY_32; - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_push_32(REG_PC); - m68ki_jump(ea); -} - - -M68KMAKE_OP(lea, 32, ., .) -{ - AX = M68KMAKE_GET_EA_AY_32; -} - - -M68KMAKE_OP(link, 16, ., a7) -{ - REG_A[7] -= 4; - m68ki_write_32(REG_A[7], REG_A[7]); - REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16())); -} - - -M68KMAKE_OP(link, 16, ., .) -{ - uint* r_dst = &AY; - - m68ki_push_32(*r_dst); - *r_dst = REG_A[7]; - REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16())); -} - - -M68KMAKE_OP(link, 32, ., a7) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - REG_A[7] -= 4; - m68ki_write_32(REG_A[7], REG_A[7]); - REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32()); - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(link, 32, ., .) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint* r_dst = &AY; - - m68ki_push_32(*r_dst); - *r_dst = REG_A[7]; - REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32()); - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(lsr, 8, s, .) -{ - uint* r_dst = &DY; - uint shift = (((REG_IR >> 9) - 1) & 7) + 1; - uint src = MASK_OUT_ABOVE_8(*r_dst); - uint res = src >> shift; - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; - - FLAG_N = NFLAG_CLEAR; - FLAG_Z = res; - FLAG_X = FLAG_C = src << (9-shift); - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(lsr, 16, s, .) -{ - uint* r_dst = &DY; - uint shift = (((REG_IR >> 9) - 1) & 7) + 1; - uint src = MASK_OUT_ABOVE_16(*r_dst); - uint res = src >> shift; - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; - - FLAG_N = NFLAG_CLEAR; - FLAG_Z = res; - FLAG_X = FLAG_C = src << (9-shift); - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(lsr, 32, s, .) -{ - uint* r_dst = &DY; - uint shift = (((REG_IR >> 9) - 1) & 7) + 1; - uint src = *r_dst; - uint res = src >> shift; - - *r_dst = res; - - FLAG_N = NFLAG_CLEAR; - FLAG_Z = res; - FLAG_X = FLAG_C = src << (9-shift); - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(lsr, 8, r, .) -{ - uint* r_dst = &DY; - uint shift = DX & 0x3f; - uint src = MASK_OUT_ABOVE_8(*r_dst); - uint res = src >> shift; - - if(shift != 0) - { - USE_CYCLES(shift<> shift; - - if(shift != 0) - { - USE_CYCLES(shift<> (shift - 1))<<8; - FLAG_N = NFLAG_CLEAR; - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - return; - } - - *r_dst &= 0xffff0000; - FLAG_X = XFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - FLAG_N = NFLAG_CLEAR; - FLAG_Z = ZFLAG_SET; - FLAG_V = VFLAG_CLEAR; - return; - } - - FLAG_C = CFLAG_CLEAR; - FLAG_N = NFLAG_16(src); - FLAG_Z = src; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(lsr, 32, r, .) -{ - uint* r_dst = &DY; - uint shift = DX & 0x3f; - uint src = *r_dst; - uint res = src >> shift; - - if(shift != 0) - { - USE_CYCLES(shift<> (shift - 1))<<8; - FLAG_N = NFLAG_CLEAR; - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - return; - } - - *r_dst = 0; - FLAG_X = FLAG_C = (shift == 32 ? GET_MSB_32(src)>>23 : 0); - FLAG_N = NFLAG_CLEAR; - FLAG_Z = ZFLAG_SET; - FLAG_V = VFLAG_CLEAR; - return; - } - - FLAG_C = CFLAG_CLEAR; - FLAG_N = NFLAG_32(src); - FLAG_Z = src; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(lsr, 16, ., .) -{ - uint ea = M68KMAKE_GET_EA_AY_16; - uint src = m68ki_read_16(ea); - uint res = src >> 1; - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_CLEAR; - FLAG_Z = res; - FLAG_C = FLAG_X = src << 8; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(lsl, 8, s, .) -{ - uint* r_dst = &DY; - uint shift = (((REG_IR >> 9) - 1) & 7) + 1; - uint src = MASK_OUT_ABOVE_8(*r_dst); - uint res = MASK_OUT_ABOVE_8(src << shift); - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_X = FLAG_C = src << shift; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(lsl, 16, s, .) -{ - uint* r_dst = &DY; - uint shift = (((REG_IR >> 9) - 1) & 7) + 1; - uint src = MASK_OUT_ABOVE_16(*r_dst); - uint res = MASK_OUT_ABOVE_16(src << shift); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_X = FLAG_C = src >> (8-shift); - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(lsl, 32, s, .) -{ - uint* r_dst = &DY; - uint shift = (((REG_IR >> 9) - 1) & 7) + 1; - uint src = *r_dst; - uint res = MASK_OUT_ABOVE_32(src << shift); - - *r_dst = res; - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_X = FLAG_C = src >> (24-shift); - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(lsl, 8, r, .) -{ - uint* r_dst = &DY; - uint shift = DX & 0x3f; - uint src = MASK_OUT_ABOVE_8(*r_dst); - uint res = MASK_OUT_ABOVE_8(src << shift); - - if(shift != 0) - { - USE_CYCLES(shift<> 8; - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - return; - } - - *r_dst &= 0xffff0000; - FLAG_X = XFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - FLAG_N = NFLAG_CLEAR; - FLAG_Z = ZFLAG_SET; - FLAG_V = VFLAG_CLEAR; - return; - } - - FLAG_C = CFLAG_CLEAR; - FLAG_N = NFLAG_16(src); - FLAG_Z = src; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(lsl, 32, r, .) -{ - uint* r_dst = &DY; - uint shift = DX & 0x3f; - uint src = *r_dst; - uint res = MASK_OUT_ABOVE_32(src << shift); - - if(shift != 0) - { - USE_CYCLES(shift<> (32 - shift)) << 8; - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - return; - } - - *r_dst = 0; - FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8; - FLAG_N = NFLAG_CLEAR; - FLAG_Z = ZFLAG_SET; - FLAG_V = VFLAG_CLEAR; - return; - } - - FLAG_C = CFLAG_CLEAR; - FLAG_N = NFLAG_32(src); - FLAG_Z = src; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(lsl, 16, ., .) -{ - uint ea = M68KMAKE_GET_EA_AY_16; - uint src = m68ki_read_16(ea); - uint res = MASK_OUT_ABOVE_16(src << 1); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_X = FLAG_C = src >> 7; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 8, d, d) -{ - uint res = MASK_OUT_ABOVE_8(DY); - uint* r_dst = &DX; - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 8, d, .) -{ - uint res = M68KMAKE_GET_OPER_AY_8; - uint* r_dst = &DX; - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 8, ai, d) -{ - uint res = MASK_OUT_ABOVE_8(DY); - uint ea = EA_AX_AI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 8, ai, .) -{ - uint res = M68KMAKE_GET_OPER_AY_8; - uint ea = EA_AX_AI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 8, pi7, d) -{ - uint res = MASK_OUT_ABOVE_8(DY); - uint ea = EA_A7_PI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 8, pi, d) -{ - uint res = MASK_OUT_ABOVE_8(DY); - uint ea = EA_AX_PI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 8, pi7, .) -{ - uint res = M68KMAKE_GET_OPER_AY_8; - uint ea = EA_A7_PI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 8, pi, .) -{ - uint res = M68KMAKE_GET_OPER_AY_8; - uint ea = EA_AX_PI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 8, pd7, d) -{ - uint res = MASK_OUT_ABOVE_8(DY); - uint ea = EA_A7_PD_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 8, pd, d) -{ - uint res = MASK_OUT_ABOVE_8(DY); - uint ea = EA_AX_PD_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 8, pd7, .) -{ - uint res = M68KMAKE_GET_OPER_AY_8; - uint ea = EA_A7_PD_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 8, pd, .) -{ - uint res = M68KMAKE_GET_OPER_AY_8; - uint ea = EA_AX_PD_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 8, di, d) -{ - uint res = MASK_OUT_ABOVE_8(DY); - uint ea = EA_AX_DI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 8, di, .) -{ - uint res = M68KMAKE_GET_OPER_AY_8; - uint ea = EA_AX_DI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 8, ix, d) -{ - uint res = MASK_OUT_ABOVE_8(DY); - uint ea = EA_AX_IX_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 8, ix, .) -{ - uint res = M68KMAKE_GET_OPER_AY_8; - uint ea = EA_AX_IX_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 8, aw, d) -{ - uint res = MASK_OUT_ABOVE_8(DY); - uint ea = EA_AW_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 8, aw, .) -{ - uint res = M68KMAKE_GET_OPER_AY_8; - uint ea = EA_AW_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 8, al, d) -{ - uint res = MASK_OUT_ABOVE_8(DY); - uint ea = EA_AL_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 8, al, .) -{ - uint res = M68KMAKE_GET_OPER_AY_8; - uint ea = EA_AL_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 16, d, d) -{ - uint res = MASK_OUT_ABOVE_16(DY); - uint* r_dst = &DX; - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 16, d, a) -{ - uint res = MASK_OUT_ABOVE_16(AY); - uint* r_dst = &DX; - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 16, d, .) -{ - uint res = M68KMAKE_GET_OPER_AY_16; - uint* r_dst = &DX; - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 16, ai, d) -{ - uint res = MASK_OUT_ABOVE_16(DY); - uint ea = EA_AX_AI_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 16, ai, a) -{ - uint res = MASK_OUT_ABOVE_16(AY); - uint ea = EA_AX_AI_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 16, ai, .) -{ - uint res = M68KMAKE_GET_OPER_AY_16; - uint ea = EA_AX_AI_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 16, pi, d) -{ - uint res = MASK_OUT_ABOVE_16(DY); - uint ea = EA_AX_PI_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 16, pi, a) -{ - uint res = MASK_OUT_ABOVE_16(AY); - uint ea = EA_AX_PI_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 16, pi, .) -{ - uint res = M68KMAKE_GET_OPER_AY_16; - uint ea = EA_AX_PI_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 16, pd, d) -{ - uint res = MASK_OUT_ABOVE_16(DY); - uint ea = EA_AX_PD_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 16, pd, a) -{ - uint res = MASK_OUT_ABOVE_16(AY); - uint ea = EA_AX_PD_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 16, pd, .) -{ - uint res = M68KMAKE_GET_OPER_AY_16; - uint ea = EA_AX_PD_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 16, di, d) -{ - uint res = MASK_OUT_ABOVE_16(DY); - uint ea = EA_AX_DI_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 16, di, a) -{ - uint res = MASK_OUT_ABOVE_16(AY); - uint ea = EA_AX_DI_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 16, di, .) -{ - uint res = M68KMAKE_GET_OPER_AY_16; - uint ea = EA_AX_DI_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 16, ix, d) -{ - uint res = MASK_OUT_ABOVE_16(DY); - uint ea = EA_AX_IX_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 16, ix, a) -{ - uint res = MASK_OUT_ABOVE_16(AY); - uint ea = EA_AX_IX_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 16, ix, .) -{ - uint res = M68KMAKE_GET_OPER_AY_16; - uint ea = EA_AX_IX_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 16, aw, d) -{ - uint res = MASK_OUT_ABOVE_16(DY); - uint ea = EA_AW_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 16, aw, a) -{ - uint res = MASK_OUT_ABOVE_16(AY); - uint ea = EA_AW_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 16, aw, .) -{ - uint res = M68KMAKE_GET_OPER_AY_16; - uint ea = EA_AW_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 16, al, d) -{ - uint res = MASK_OUT_ABOVE_16(DY); - uint ea = EA_AL_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 16, al, a) -{ - uint res = MASK_OUT_ABOVE_16(AY); - uint ea = EA_AL_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 16, al, .) -{ - uint res = M68KMAKE_GET_OPER_AY_16; - uint ea = EA_AL_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 32, d, d) -{ - uint res = DY; - uint* r_dst = &DX; - - *r_dst = res; - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 32, d, a) -{ - uint res = AY; - uint* r_dst = &DX; - - *r_dst = res; - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 32, d, .) -{ - uint res = M68KMAKE_GET_OPER_AY_32; - uint* r_dst = &DX; - - *r_dst = res; - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 32, ai, d) -{ - uint res = DY; - uint ea = EA_AX_AI_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 32, ai, a) -{ - uint res = AY; - uint ea = EA_AX_AI_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 32, ai, .) -{ - uint res = M68KMAKE_GET_OPER_AY_32; - uint ea = EA_AX_AI_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 32, pi, d) -{ - uint res = DY; - uint ea = EA_AX_PI_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 32, pi, a) -{ - uint res = AY; - uint ea = EA_AX_PI_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 32, pi, .) -{ - uint res = M68KMAKE_GET_OPER_AY_32; - uint ea = EA_AX_PI_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 32, pd, d) -{ - uint res = DY; - uint ea = EA_AX_PD_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 32, pd, a) -{ - uint res = AY; - uint ea = EA_AX_PD_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 32, pd, .) -{ - uint res = M68KMAKE_GET_OPER_AY_32; - uint ea = EA_AX_PD_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 32, di, d) -{ - uint res = DY; - uint ea = EA_AX_DI_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 32, di, a) -{ - uint res = AY; - uint ea = EA_AX_DI_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 32, di, .) -{ - uint res = M68KMAKE_GET_OPER_AY_32; - uint ea = EA_AX_DI_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 32, ix, d) -{ - uint res = DY; - uint ea = EA_AX_IX_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 32, ix, a) -{ - uint res = AY; - uint ea = EA_AX_IX_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 32, ix, .) -{ - uint res = M68KMAKE_GET_OPER_AY_32; - uint ea = EA_AX_IX_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 32, aw, d) -{ - uint res = DY; - uint ea = EA_AW_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 32, aw, a) -{ - uint res = AY; - uint ea = EA_AW_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 32, aw, .) -{ - uint res = M68KMAKE_GET_OPER_AY_32; - uint ea = EA_AW_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 32, al, d) -{ - uint res = DY; - uint ea = EA_AL_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 32, al, a) -{ - uint res = AY; - uint ea = EA_AL_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(move, 32, al, .) -{ - uint res = M68KMAKE_GET_OPER_AY_32; - uint ea = EA_AL_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(movea, 16, ., d) -{ - AX = MAKE_INT_16(DY); -} - - -M68KMAKE_OP(movea, 16, ., a) -{ - AX = MAKE_INT_16(AY); -} - - -M68KMAKE_OP(movea, 16, ., .) -{ - AX = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16); -} - - -M68KMAKE_OP(movea, 32, ., d) -{ - AX = DY; -} - - -M68KMAKE_OP(movea, 32, ., a) -{ - AX = AY; -} - - -M68KMAKE_OP(movea, 32, ., .) -{ - AX = M68KMAKE_GET_OPER_AY_32; -} - - -M68KMAKE_OP(move, 16, frc, d) -{ - if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) - { - DY = MASK_OUT_BELOW_16(DY) | m68ki_get_ccr(); - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(move, 16, frc, .) -{ - if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) - { - m68ki_write_16(M68KMAKE_GET_EA_AY_16, m68ki_get_ccr()); - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(move, 16, toc, d) -{ - m68ki_set_ccr(DY); -} - - -M68KMAKE_OP(move, 16, toc, .) -{ - m68ki_set_ccr(M68KMAKE_GET_OPER_AY_16); -} - - -M68KMAKE_OP(move, 16, frs, d) -{ - if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */ - { - DY = MASK_OUT_BELOW_16(DY) | m68ki_get_sr(); - return; - } - m68ki_exception_privilege_violation(); -} - - -M68KMAKE_OP(move, 16, frs, .) -{ - if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */ - { - uint ea = M68KMAKE_GET_EA_AY_16; - m68ki_write_16(ea, m68ki_get_sr()); - return; - } - m68ki_exception_privilege_violation(); -} - - -M68KMAKE_OP(move, 16, tos, d) -{ - if(FLAG_S) - { - m68ki_set_sr(DY); - return; - } - m68ki_exception_privilege_violation(); -} - - -M68KMAKE_OP(move, 16, tos, .) -{ - if(FLAG_S) - { - uint new_sr = M68KMAKE_GET_OPER_AY_16; - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_set_sr(new_sr); - return; - } - m68ki_exception_privilege_violation(); -} - - -M68KMAKE_OP(move, 32, fru, .) -{ - if(FLAG_S) - { - AY = REG_USP; - return; - } - m68ki_exception_privilege_violation(); -} - - -M68KMAKE_OP(move, 32, tou, .) -{ - if(FLAG_S) - { - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - REG_USP = AY; - return; - } - m68ki_exception_privilege_violation(); -} - - -M68KMAKE_OP(movec, 32, cr, .) -{ - if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) - { - if(FLAG_S) - { - uint word2 = OPER_I_16(); - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - switch (word2 & 0xfff) - { - case 0x000: /* SFC */ - REG_DA[(word2 >> 12) & 15] = REG_SFC; - return; - case 0x001: /* DFC */ - REG_DA[(word2 >> 12) & 15] = REG_DFC; - return; - case 0x002: /* CACR */ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - REG_DA[(word2 >> 12) & 15] = REG_CACR; - return; - } - return; - case 0x800: /* USP */ - REG_DA[(word2 >> 12) & 15] = REG_USP; - return; - case 0x801: /* VBR */ - REG_DA[(word2 >> 12) & 15] = REG_VBR; - return; - case 0x802: /* CAAR */ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - REG_DA[(word2 >> 12) & 15] = REG_CAAR; - return; - } - m68ki_exception_illegal(); - break; - case 0x803: /* MSP */ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - REG_DA[(word2 >> 12) & 15] = FLAG_M ? REG_SP : REG_MSP; - return; - } - m68ki_exception_illegal(); - return; - case 0x804: /* ISP */ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - REG_DA[(word2 >> 12) & 15] = FLAG_M ? REG_ISP : REG_SP; - return; - } - m68ki_exception_illegal(); - return; - default: - m68ki_exception_illegal(); - return; - } - } - m68ki_exception_privilege_violation(); - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(movec, 32, rc, .) -{ - if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) - { - if(FLAG_S) - { - uint word2 = OPER_I_16(); - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - switch (word2 & 0xfff) - { - case 0x000: /* SFC */ - REG_SFC = REG_DA[(word2 >> 12) & 15] & 7; - return; - case 0x001: /* DFC */ - REG_DFC = REG_DA[(word2 >> 12) & 15] & 7; - return; - case 0x002: /* CACR */ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - REG_CACR = REG_DA[(word2 >> 12) & 15]; - return; - } - m68ki_exception_illegal(); - return; - case 0x800: /* USP */ - REG_USP = REG_DA[(word2 >> 12) & 15]; - return; - case 0x801: /* VBR */ - REG_VBR = REG_DA[(word2 >> 12) & 15]; - return; - case 0x802: /* CAAR */ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - REG_CAAR = REG_DA[(word2 >> 12) & 15]; - return; - } - m68ki_exception_illegal(); - return; - case 0x803: /* MSP */ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - /* we are in supervisor mode so just check for M flag */ - if(!FLAG_M) - { - REG_MSP = REG_DA[(word2 >> 12) & 15]; - return; - } - REG_SP = REG_DA[(word2 >> 12) & 15]; - return; - } - m68ki_exception_illegal(); - return; - case 0x804: /* ISP */ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(!FLAG_M) - { - REG_SP = REG_DA[(word2 >> 12) & 15]; - return; - } - REG_ISP = REG_DA[(word2 >> 12) & 15]; - return; - } - m68ki_exception_illegal(); - return; - default: - m68ki_exception_illegal(); - return; - } - } - m68ki_exception_privilege_violation(); - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(movem, 16, re, pd) -{ - uint i = 0; - uint register_list = OPER_I_16(); - uint ea = AY; - uint count = 0; - - for(; i < 16; i++) - if(register_list & (1 << i)) - { - ea -= 2; - m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[15-i])); - count++; - } - AY = ea; - - USE_CYCLES(count<> 8)); - m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src)); -} - - -M68KMAKE_OP(movep, 32, re, .) -{ - uint ea = EA_AY_DI_32(); - uint src = DX; - - m68ki_write_8(ea, MASK_OUT_ABOVE_8(src >> 24)); - m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 16)); - m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 8)); - m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src)); -} - - -M68KMAKE_OP(movep, 16, er, .) -{ - uint ea = EA_AY_DI_16(); - uint* r_dst = &DX; - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | ((m68ki_read_8(ea) << 8) + m68ki_read_8(ea + 2)); -} - - -M68KMAKE_OP(movep, 32, er, .) -{ - uint ea = EA_AY_DI_32(); - - DX = (m68ki_read_8(ea) << 24) + (m68ki_read_8(ea + 2) << 16) - + (m68ki_read_8(ea + 4) << 8) + m68ki_read_8(ea + 6); -} - - -M68KMAKE_OP(moves, 8, ., .) -{ - if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) - { - if(FLAG_S) - { - uint word2 = OPER_I_16(); - uint ea = M68KMAKE_GET_EA_AY_8; - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - if(BIT_B(word2)) /* Register to memory */ - { - m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15])); - return; - } - if(BIT_F(word2)) /* Memory to address register */ - { - REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC)); - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - USE_CYCLES(2); - return; - } - /* Memory to data register */ - REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC); - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - USE_CYCLES(2); - return; - } - m68ki_exception_privilege_violation(); - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(moves, 16, ., .) -{ - if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) - { - if(FLAG_S) - { - uint word2 = OPER_I_16(); - uint ea = M68KMAKE_GET_EA_AY_16; - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - if(BIT_B(word2)) /* Register to memory */ - { - m68ki_write_16_fc(ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15])); - return; - } - if(BIT_F(word2)) /* Memory to address register */ - { - REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(ea, REG_SFC)); - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - USE_CYCLES(2); - return; - } - /* Memory to data register */ - REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(ea, REG_SFC); - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - USE_CYCLES(2); - return; - } - m68ki_exception_privilege_violation(); - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(moves, 32, ., .) -{ - if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) - { - if(FLAG_S) - { - uint word2 = OPER_I_16(); - uint ea = M68KMAKE_GET_EA_AY_32; - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - if(BIT_B(word2)) /* Register to memory */ - { - m68ki_write_32_fc(ea, REG_DFC, REG_DA[(word2 >> 12) & 15]); - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - USE_CYCLES(2); - return; - } - /* Memory to register */ - REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(ea, REG_SFC); - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - USE_CYCLES(2); - return; - } - m68ki_exception_privilege_violation(); - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(moveq, 32, ., .) -{ - uint res = DX = MAKE_INT_8(MASK_OUT_ABOVE_8(REG_IR)); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(muls, 16, ., d) -{ - uint* r_dst = &DX; - uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(DY) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst))); - - *r_dst = res; - - FLAG_Z = res; - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(muls, 16, ., .) -{ - uint* r_dst = &DX; - uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(M68KMAKE_GET_OPER_AY_16) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst))); - - *r_dst = res; - - FLAG_Z = res; - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(mulu, 16, ., d) -{ - uint* r_dst = &DX; - uint res = MASK_OUT_ABOVE_16(DY) * MASK_OUT_ABOVE_16(*r_dst); - - *r_dst = res; - - FLAG_Z = res; - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(mulu, 16, ., .) -{ - uint* r_dst = &DX; - uint res = M68KMAKE_GET_OPER_AY_16 * MASK_OUT_ABOVE_16(*r_dst); - - *r_dst = res; - - FLAG_Z = res; - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(mull, 32, ., d) -{ -#if M68K_USE_64_BIT - - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint64 src = DY; - uint64 dst = REG_D[(word2 >> 12) & 7]; - uint64 res; - - FLAG_C = CFLAG_CLEAR; - - if(BIT_B(word2)) /* signed */ - { - res = (sint64)((sint32)src) * (sint64)((sint32)dst); - if(!BIT_A(word2)) - { - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_N = NFLAG_32(res); - FLAG_V = ((sint64)res != (sint32)res)<<7; - REG_D[(word2 >> 12) & 7] = FLAG_Z; - return; - } - FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); - FLAG_N = NFLAG_64(res); - FLAG_V = VFLAG_CLEAR; - REG_D[word2 & 7] = (res >> 32); - REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); - return; - } - - res = src * dst; - if(!BIT_A(word2)) - { - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_N = NFLAG_32(res); - FLAG_V = (res > 0xffffffff)<<7; - REG_D[(word2 >> 12) & 7] = FLAG_Z; - return; - } - FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); - FLAG_N = NFLAG_64(res); - FLAG_V = VFLAG_CLEAR; - REG_D[word2 & 7] = (res >> 32); - REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); - return; - } - m68ki_exception_illegal(); - -#else - - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint src = DY; - uint dst = REG_D[(word2 >> 12) & 7]; - uint neg = GET_MSB_32(src ^ dst); - uint src1; - uint src2; - uint dst1; - uint dst2; - uint r1; - uint r2; - uint r3; - uint r4; - uint lo; - uint hi; - - FLAG_C = CFLAG_CLEAR; - - if(BIT_B(word2)) /* signed */ - { - if(GET_MSB_32(src)) - src = (uint)MASK_OUT_ABOVE_32(-(sint)src); - if(GET_MSB_32(dst)) - dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst); - } - - src1 = MASK_OUT_ABOVE_16(src); - src2 = src>>16; - dst1 = MASK_OUT_ABOVE_16(dst); - dst2 = dst>>16; - - - r1 = src1 * dst1; - r2 = src1 * dst2; - r3 = src2 * dst1; - r4 = src2 * dst2; - - lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16); - hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16); - - if(BIT_B(word2) && neg) - { - hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0)); - lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo); - } - - if(BIT_A(word2)) - { - REG_D[word2 & 7] = hi; - REG_D[(word2 >> 12) & 7] = lo; - FLAG_N = NFLAG_32(hi); - FLAG_Z = hi | lo; - FLAG_V = VFLAG_CLEAR; - return; - } - - REG_D[(word2 >> 12) & 7] = lo; - FLAG_N = NFLAG_32(lo); - FLAG_Z = lo; - if(BIT_B(word2)) - FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7; - else - FLAG_V = (hi != 0) << 7; - return; - } - m68ki_exception_illegal(); - -#endif -} - - -M68KMAKE_OP(mull, 32, ., .) -{ -#if M68K_USE_64_BIT - - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint64 src = M68KMAKE_GET_OPER_AY_32; - uint64 dst = REG_D[(word2 >> 12) & 7]; - uint64 res; - - FLAG_C = CFLAG_CLEAR; - - if(BIT_B(word2)) /* signed */ - { - res = (sint64)((sint32)src) * (sint64)((sint32)dst); - if(!BIT_A(word2)) - { - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_N = NFLAG_32(res); - FLAG_V = ((sint64)res != (sint32)res)<<7; - REG_D[(word2 >> 12) & 7] = FLAG_Z; - return; - } - FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); - FLAG_N = NFLAG_64(res); - FLAG_V = VFLAG_CLEAR; - REG_D[word2 & 7] = (res >> 32); - REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); - return; - } - - res = src * dst; - if(!BIT_A(word2)) - { - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_N = NFLAG_32(res); - FLAG_V = (res > 0xffffffff)<<7; - REG_D[(word2 >> 12) & 7] = FLAG_Z; - return; - } - FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); - FLAG_N = NFLAG_64(res); - FLAG_V = VFLAG_CLEAR; - REG_D[word2 & 7] = (res >> 32); - REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); - return; - } - m68ki_exception_illegal(); - -#else - - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint src = M68KMAKE_GET_OPER_AY_32; - uint dst = REG_D[(word2 >> 12) & 7]; - uint neg = GET_MSB_32(src ^ dst); - uint src1; - uint src2; - uint dst1; - uint dst2; - uint r1; - uint r2; - uint r3; - uint r4; - uint lo; - uint hi; - - FLAG_C = CFLAG_CLEAR; - - if(BIT_B(word2)) /* signed */ - { - if(GET_MSB_32(src)) - src = (uint)MASK_OUT_ABOVE_32(-(sint)src); - if(GET_MSB_32(dst)) - dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst); - } - - src1 = MASK_OUT_ABOVE_16(src); - src2 = src>>16; - dst1 = MASK_OUT_ABOVE_16(dst); - dst2 = dst>>16; - - - r1 = src1 * dst1; - r2 = src1 * dst2; - r3 = src2 * dst1; - r4 = src2 * dst2; - - lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16); - hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16); - - if(BIT_B(word2) && neg) - { - hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0)); - lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo); - } - - if(BIT_A(word2)) - { - REG_D[word2 & 7] = hi; - REG_D[(word2 >> 12) & 7] = lo; - FLAG_N = NFLAG_32(hi); - FLAG_Z = hi | lo; - FLAG_V = VFLAG_CLEAR; - return; - } - - REG_D[(word2 >> 12) & 7] = lo; - FLAG_N = NFLAG_32(lo); - FLAG_Z = lo; - if(BIT_B(word2)) - FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7; - else - FLAG_V = (hi != 0) << 7; - return; - } - m68ki_exception_illegal(); - -#endif -} - - -M68KMAKE_OP(nbcd, 8, ., d) -{ - uint* r_dst = &DY; - uint dst = *r_dst; - uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1()); - - if(res != 0x9a) - { - FLAG_V = ~res; /* Undefined V behavior */ - - if((res & 0x0f) == 0xa) - res = (res & 0xf0) + 0x10; - - res = MASK_OUT_ABOVE_8(res); - - FLAG_V &= res; /* Undefined V behavior part II */ - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; - - FLAG_Z |= res; - FLAG_C = CFLAG_SET; - FLAG_X = XFLAG_SET; - } - else - { - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - FLAG_X = XFLAG_CLEAR; - } - FLAG_N = NFLAG_8(res); /* Undefined N behavior */ -} - - -M68KMAKE_OP(nbcd, 8, ., .) -{ - uint ea = M68KMAKE_GET_EA_AY_8; - uint dst = m68ki_read_8(ea); - uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1()); - - if(res != 0x9a) - { - FLAG_V = ~res; /* Undefined V behavior */ - - if((res & 0x0f) == 0xa) - res = (res & 0xf0) + 0x10; - - res = MASK_OUT_ABOVE_8(res); - - FLAG_V &= res; /* Undefined V behavior part II */ - - m68ki_write_8(ea, MASK_OUT_ABOVE_8(res)); - - FLAG_Z |= res; - FLAG_C = CFLAG_SET; - FLAG_X = XFLAG_SET; - } - else - { - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - FLAG_X = XFLAG_CLEAR; - } - FLAG_N = NFLAG_8(res); /* Undefined N behavior */ -} - - -M68KMAKE_OP(neg, 8, ., d) -{ - uint* r_dst = &DY; - uint res = 0 - MASK_OUT_ABOVE_8(*r_dst); - - FLAG_N = NFLAG_8(res); - FLAG_C = FLAG_X = CFLAG_8(res); - FLAG_V = *r_dst & res; - FLAG_Z = MASK_OUT_ABOVE_8(res); - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; -} - - -M68KMAKE_OP(neg, 8, ., .) -{ - uint ea = M68KMAKE_GET_EA_AY_8; - uint src = m68ki_read_8(ea); - uint res = 0 - src; - - FLAG_N = NFLAG_8(res); - FLAG_C = FLAG_X = CFLAG_8(res); - FLAG_V = src & res; - FLAG_Z = MASK_OUT_ABOVE_8(res); - - m68ki_write_8(ea, FLAG_Z); -} - - -M68KMAKE_OP(neg, 16, ., d) -{ - uint* r_dst = &DY; - uint res = 0 - MASK_OUT_ABOVE_16(*r_dst); - - FLAG_N = NFLAG_16(res); - FLAG_C = FLAG_X = CFLAG_16(res); - FLAG_V = (*r_dst & res)>>8; - FLAG_Z = MASK_OUT_ABOVE_16(res); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; -} - - -M68KMAKE_OP(neg, 16, ., .) -{ - uint ea = M68KMAKE_GET_EA_AY_16; - uint src = m68ki_read_16(ea); - uint res = 0 - src; - - FLAG_N = NFLAG_16(res); - FLAG_C = FLAG_X = CFLAG_16(res); - FLAG_V = (src & res)>>8; - FLAG_Z = MASK_OUT_ABOVE_16(res); - - m68ki_write_16(ea, FLAG_Z); -} - - -M68KMAKE_OP(neg, 32, ., d) -{ - uint* r_dst = &DY; - uint res = 0 - *r_dst; - - FLAG_N = NFLAG_32(res); - FLAG_C = FLAG_X = CFLAG_SUB_32(*r_dst, 0, res); - FLAG_V = (*r_dst & res)>>24; - FLAG_Z = MASK_OUT_ABOVE_32(res); - - *r_dst = FLAG_Z; -} - - -M68KMAKE_OP(neg, 32, ., .) -{ - uint ea = M68KMAKE_GET_EA_AY_32; - uint src = m68ki_read_32(ea); - uint res = 0 - src; - - FLAG_N = NFLAG_32(res); - FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res); - FLAG_V = (src & res)>>24; - FLAG_Z = MASK_OUT_ABOVE_32(res); - - m68ki_write_32(ea, FLAG_Z); -} - - -M68KMAKE_OP(negx, 8, ., d) -{ - uint* r_dst = &DY; - uint res = 0 - MASK_OUT_ABOVE_8(*r_dst) - XFLAG_AS_1(); - - FLAG_N = NFLAG_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = *r_dst & res; - - res = MASK_OUT_ABOVE_8(res); - FLAG_Z |= res; - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; -} - - -M68KMAKE_OP(negx, 8, ., .) -{ - uint ea = M68KMAKE_GET_EA_AY_8; - uint src = m68ki_read_8(ea); - uint res = 0 - src - XFLAG_AS_1(); - - FLAG_N = NFLAG_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = src & res; - - res = MASK_OUT_ABOVE_8(res); - FLAG_Z |= res; - - m68ki_write_8(ea, res); -} - - -M68KMAKE_OP(negx, 16, ., d) -{ - uint* r_dst = &DY; - uint res = 0 - MASK_OUT_ABOVE_16(*r_dst) - XFLAG_AS_1(); - - FLAG_N = NFLAG_16(res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_V = (*r_dst & res)>>8; - - res = MASK_OUT_ABOVE_16(res); - FLAG_Z |= res; - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; -} - - -M68KMAKE_OP(negx, 16, ., .) -{ - uint ea = M68KMAKE_GET_EA_AY_16; - uint src = m68ki_read_16(ea); - uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1(); - - FLAG_N = NFLAG_16(res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_V = (src & res)>>8; - - res = MASK_OUT_ABOVE_16(res); - FLAG_Z |= res; - - m68ki_write_16(ea, res); -} - - -M68KMAKE_OP(negx, 32, ., d) -{ - uint* r_dst = &DY; - uint res = 0 - MASK_OUT_ABOVE_32(*r_dst) - XFLAG_AS_1(); - - FLAG_N = NFLAG_32(res); - FLAG_X = FLAG_C = CFLAG_SUB_32(*r_dst, 0, res); - FLAG_V = (*r_dst & res)>>24; - - res = MASK_OUT_ABOVE_32(res); - FLAG_Z |= res; - - *r_dst = res; -} - - -M68KMAKE_OP(negx, 32, ., .) -{ - uint ea = M68KMAKE_GET_EA_AY_32; - uint src = m68ki_read_32(ea); - uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1(); - - FLAG_N = NFLAG_32(res); - FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res); - FLAG_V = (src & res)>>24; - - res = MASK_OUT_ABOVE_32(res); - FLAG_Z |= res; - - m68ki_write_32(ea, res); -} - - -M68KMAKE_OP(nop, 0, ., .) -{ - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ -} - - -M68KMAKE_OP(not, 8, ., d) -{ - uint* r_dst = &DY; - uint res = MASK_OUT_ABOVE_8(~*r_dst); - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(not, 8, ., .) -{ - uint ea = M68KMAKE_GET_EA_AY_8; - uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea)); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(not, 16, ., d) -{ - uint* r_dst = &DY; - uint res = MASK_OUT_ABOVE_16(~*r_dst); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(not, 16, ., .) -{ - uint ea = M68KMAKE_GET_EA_AY_16; - uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea)); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(not, 32, ., d) -{ - uint* r_dst = &DY; - uint res = *r_dst = MASK_OUT_ABOVE_32(~*r_dst); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(not, 32, ., .) -{ - uint ea = M68KMAKE_GET_EA_AY_32; - uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea)); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(or, 8, er, d) -{ - uint res = MASK_OUT_ABOVE_8((DX |= MASK_OUT_ABOVE_8(DY))); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(or, 8, er, .) -{ - uint res = MASK_OUT_ABOVE_8((DX |= M68KMAKE_GET_OPER_AY_8)); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(or, 16, er, d) -{ - uint res = MASK_OUT_ABOVE_16((DX |= MASK_OUT_ABOVE_16(DY))); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(or, 16, er, .) -{ - uint res = MASK_OUT_ABOVE_16((DX |= M68KMAKE_GET_OPER_AY_16)); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(or, 32, er, d) -{ - uint res = DX |= DY; - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(or, 32, er, .) -{ - uint res = DX |= M68KMAKE_GET_OPER_AY_32; - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(or, 8, re, .) -{ - uint ea = M68KMAKE_GET_EA_AY_8; - uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea)); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(or, 16, re, .) -{ - uint ea = M68KMAKE_GET_EA_AY_16; - uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea)); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(or, 32, re, .) -{ - uint ea = M68KMAKE_GET_EA_AY_32; - uint res = DX | m68ki_read_32(ea); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(ori, 8, ., d) -{ - uint res = MASK_OUT_ABOVE_8((DY |= OPER_I_8())); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(ori, 8, ., .) -{ - uint src = OPER_I_8(); - uint ea = M68KMAKE_GET_EA_AY_8; - uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea)); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(ori, 16, ., d) -{ - uint res = MASK_OUT_ABOVE_16(DY |= OPER_I_16()); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(ori, 16, ., .) -{ - uint src = OPER_I_16(); - uint ea = M68KMAKE_GET_EA_AY_16; - uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea)); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(ori, 32, ., d) -{ - uint res = DY |= OPER_I_32(); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(ori, 32, ., .) -{ - uint src = OPER_I_32(); - uint ea = M68KMAKE_GET_EA_AY_32; - uint res = src | m68ki_read_32(ea); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(ori, 16, toc, .) -{ - m68ki_set_ccr(m68ki_get_ccr() | OPER_I_16()); -} - - -M68KMAKE_OP(ori, 16, tos, .) -{ - if(FLAG_S) - { - uint src = OPER_I_16(); - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_set_sr(m68ki_get_sr() | src); - return; - } - m68ki_exception_privilege_violation(); -} - - -M68KMAKE_OP(pack, 16, rr, .) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - /* Note: DX and DY are reversed in Motorola's docs */ - uint src = DY + OPER_I_16(); - uint* r_dst = &DX; - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | ((src >> 4) & 0x00f0) | (src & 0x000f); - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(pack, 16, mm, ax7) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - /* Note: AX and AY are reversed in Motorola's docs */ - uint ea_src = EA_AY_PD_8(); - uint src = m68ki_read_8(ea_src); - ea_src = EA_AY_PD_8(); - src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16(); - - m68ki_write_8(EA_A7_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f)); - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(pack, 16, mm, ay7) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - /* Note: AX and AY are reversed in Motorola's docs */ - uint ea_src = EA_A7_PD_8(); - uint src = m68ki_read_8(ea_src); - ea_src = EA_A7_PD_8(); - src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16(); - - m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f)); - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(pack, 16, mm, axy7) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint ea_src = EA_A7_PD_8(); - uint src = m68ki_read_8(ea_src); - ea_src = EA_A7_PD_8(); - src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16(); - - m68ki_write_8(EA_A7_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f)); - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(pack, 16, mm, .) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - /* Note: AX and AY are reversed in Motorola's docs */ - uint ea_src = EA_AY_PD_8(); - uint src = m68ki_read_8(ea_src); - ea_src = EA_AY_PD_8(); - src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16(); - - m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f)); - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(pea, 32, ., .) -{ - uint ea = M68KMAKE_GET_EA_AY_32; - - m68ki_push_32(ea); -} - - -M68KMAKE_OP(reset, 0, ., .) -{ - if(FLAG_S) - { - m68ki_output_reset(); /* auto-disable (see m68kcpu.h) */ - USE_CYCLES(CYC_RESET); - return; - } - m68ki_exception_privilege_violation(); -} - - -M68KMAKE_OP(ror, 8, s, .) -{ - uint* r_dst = &DY; - uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1; - uint shift = orig_shift & 7; - uint src = MASK_OUT_ABOVE_8(*r_dst); - uint res = ROR_8(src, shift); - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = src << (9-orig_shift); - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(ror, 16, s, .) -{ - uint* r_dst = &DY; - uint shift = (((REG_IR >> 9) - 1) & 7) + 1; - uint src = MASK_OUT_ABOVE_16(*r_dst); - uint res = ROR_16(src, shift); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = src << (9-shift); - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(ror, 32, s, .) -{ - uint* r_dst = &DY; - uint shift = (((REG_IR >> 9) - 1) & 7) + 1; - uint64 src = *r_dst; - uint res = ROR_32(src, shift); - - *r_dst = res; - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = src << (9-shift); - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(ror, 8, r, .) -{ - uint* r_dst = &DY; - uint orig_shift = DX & 0x3f; - uint shift = orig_shift & 7; - uint src = MASK_OUT_ABOVE_8(*r_dst); - uint res = ROR_8(src, shift); - - if(orig_shift != 0) - { - USE_CYCLES(orig_shift<> ((shift - 1) & 15)) << 8; - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - return; - } - - FLAG_C = CFLAG_CLEAR; - FLAG_N = NFLAG_16(src); - FLAG_Z = src; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(ror, 32, r, .) -{ - uint* r_dst = &DY; - uint orig_shift = DX & 0x3f; - uint shift = orig_shift & 31; - uint64 src = *r_dst; - uint res = ROR_32(src, shift); - - if(orig_shift != 0) - { - USE_CYCLES(orig_shift<> ((shift - 1) & 31)) << 8; - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - return; - } - - FLAG_C = CFLAG_CLEAR; - FLAG_N = NFLAG_32(src); - FLAG_Z = src; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(ror, 16, ., .) -{ - uint ea = M68KMAKE_GET_EA_AY_16; - uint src = m68ki_read_16(ea); - uint res = ROR_16(src, 1); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = src << 8; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(rol, 8, s, .) -{ - uint* r_dst = &DY; - uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1; - uint shift = orig_shift & 7; - uint src = MASK_OUT_ABOVE_8(*r_dst); - uint res = ROL_8(src, shift); - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = src << orig_shift; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(rol, 16, s, .) -{ - uint* r_dst = &DY; - uint shift = (((REG_IR >> 9) - 1) & 7) + 1; - uint src = MASK_OUT_ABOVE_16(*r_dst); - uint res = ROL_16(src, shift); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = src >> (8-shift); - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(rol, 32, s, .) -{ - uint* r_dst = &DY; - uint shift = (((REG_IR >> 9) - 1) & 7) + 1; - uint64 src = *r_dst; - uint res = ROL_32(src, shift); - - *r_dst = res; - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = src >> (24-shift); - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(rol, 8, r, .) -{ - uint* r_dst = &DY; - uint orig_shift = DX & 0x3f; - uint shift = orig_shift & 7; - uint src = MASK_OUT_ABOVE_8(*r_dst); - uint res = ROL_8(src, shift); - - if(orig_shift != 0) - { - USE_CYCLES(orig_shift<> 8; - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - return; - } - FLAG_C = (src & 1)<<8; - FLAG_N = NFLAG_16(src); - FLAG_Z = src; - FLAG_V = VFLAG_CLEAR; - return; - } - - FLAG_C = CFLAG_CLEAR; - FLAG_N = NFLAG_16(src); - FLAG_Z = src; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(rol, 32, r, .) -{ - uint* r_dst = &DY; - uint orig_shift = DX & 0x3f; - uint shift = orig_shift & 31; - uint64 src = *r_dst; - uint res = ROL_32(src, shift); - - if(orig_shift != 0) - { - USE_CYCLES(orig_shift<> (32 - shift)) << 8; - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - return; - } - - FLAG_C = CFLAG_CLEAR; - FLAG_N = NFLAG_32(src); - FLAG_Z = src; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(rol, 16, ., .) -{ - uint ea = M68KMAKE_GET_EA_AY_16; - uint src = m68ki_read_16(ea); - uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1)); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = src >> 7; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(roxr, 8, s, .) -{ - uint* r_dst = &DY; - uint shift = (((REG_IR >> 9) - 1) & 7) + 1; - uint src = MASK_OUT_ABOVE_8(*r_dst); - uint res = ROR_9(src | (XFLAG_AS_1() << 8), shift); - - FLAG_C = FLAG_X = res; - res = MASK_OUT_ABOVE_8(res); - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(roxr, 16, s, .) -{ - uint* r_dst = &DY; - uint shift = (((REG_IR >> 9) - 1) & 7) + 1; - uint src = MASK_OUT_ABOVE_16(*r_dst); - uint res = ROR_17(src | (XFLAG_AS_1() << 16), shift); - - FLAG_C = FLAG_X = res >> 8; - res = MASK_OUT_ABOVE_16(res); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(roxr, 32, s, .) -{ -#if M68K_USE_64_BIT - - uint* r_dst = &DY; - uint shift = (((REG_IR >> 9) - 1) & 7) + 1; - uint64 src = *r_dst; - uint64 res = src | (((uint64)XFLAG_AS_1()) << 32); - - res = ROR_33_64(res, shift); - - FLAG_C = FLAG_X = res >> 24; - res = MASK_OUT_ABOVE_32(res); - - *r_dst = res; - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - -#else - - uint* r_dst = &DY; - uint shift = (((REG_IR >> 9) - 1) & 7) + 1; - uint src = *r_dst; - uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift))); - uint new_x_flag = src & (1 << (shift - 1)); - - *r_dst = res; - - FLAG_C = FLAG_X = (new_x_flag != 0)<<8; - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - -#endif -} - - -M68KMAKE_OP(roxr, 8, r, .) -{ - uint* r_dst = &DY; - uint orig_shift = DX & 0x3f; - - if(orig_shift != 0) - { - uint shift = orig_shift % 9; - uint src = MASK_OUT_ABOVE_8(*r_dst); - uint res = ROR_9(src | (XFLAG_AS_1() << 8), shift); - - USE_CYCLES(orig_shift<> 8; - res = MASK_OUT_ABOVE_16(res); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - return; - } - - FLAG_C = FLAG_X; - FLAG_N = NFLAG_16(*r_dst); - FLAG_Z = MASK_OUT_ABOVE_16(*r_dst); - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(roxr, 32, r, .) -{ -#if M68K_USE_64_BIT - - uint* r_dst = &DY; - uint orig_shift = DX & 0x3f; - - if(orig_shift != 0) - { - uint shift = orig_shift % 33; - uint64 src = *r_dst; - uint64 res = src | (((uint64)XFLAG_AS_1()) << 32); - - res = ROR_33_64(res, shift); - - USE_CYCLES(orig_shift<> 24; - res = MASK_OUT_ABOVE_32(res); - - *r_dst = res; - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - return; - } - - FLAG_C = FLAG_X; - FLAG_N = NFLAG_32(*r_dst); - FLAG_Z = *r_dst; - FLAG_V = VFLAG_CLEAR; - -#else - - uint* r_dst = &DY; - uint orig_shift = DX & 0x3f; - uint shift = orig_shift % 33; - uint src = *r_dst; - uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift))); - uint new_x_flag = src & (1 << (shift - 1)); - - if(orig_shift != 0) - USE_CYCLES(orig_shift<> 8; - res = MASK_OUT_ABOVE_16(res); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(roxl, 8, s, .) -{ - uint* r_dst = &DY; - uint shift = (((REG_IR >> 9) - 1) & 7) + 1; - uint src = MASK_OUT_ABOVE_8(*r_dst); - uint res = ROL_9(src | (XFLAG_AS_1() << 8), shift); - - FLAG_C = FLAG_X = res; - res = MASK_OUT_ABOVE_8(res); - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(roxl, 16, s, .) -{ - uint* r_dst = &DY; - uint shift = (((REG_IR >> 9) - 1) & 7) + 1; - uint src = MASK_OUT_ABOVE_16(*r_dst); - uint res = ROL_17(src | (XFLAG_AS_1() << 16), shift); - - FLAG_C = FLAG_X = res >> 8; - res = MASK_OUT_ABOVE_16(res); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(roxl, 32, s, .) -{ -#if M68K_USE_64_BIT - - uint* r_dst = &DY; - uint shift = (((REG_IR >> 9) - 1) & 7) + 1; - uint64 src = *r_dst; - uint64 res = src | (((uint64)XFLAG_AS_1()) << 32); - - res = ROL_33_64(res, shift); - - FLAG_C = FLAG_X = res >> 24; - res = MASK_OUT_ABOVE_32(res); - - *r_dst = res; - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - -#else - - uint* r_dst = &DY; - uint shift = (((REG_IR >> 9) - 1) & 7) + 1; - uint src = *r_dst; - uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1))); - uint new_x_flag = src & (1 << (32 - shift)); - - *r_dst = res; - - FLAG_C = FLAG_X = (new_x_flag != 0)<<8; - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - -#endif -} - - -M68KMAKE_OP(roxl, 8, r, .) -{ - uint* r_dst = &DY; - uint orig_shift = DX & 0x3f; - - - if(orig_shift != 0) - { - uint shift = orig_shift % 9; - uint src = MASK_OUT_ABOVE_8(*r_dst); - uint res = ROL_9(src | (XFLAG_AS_1() << 8), shift); - - USE_CYCLES(orig_shift<> 8; - res = MASK_OUT_ABOVE_16(res); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - return; - } - - FLAG_C = FLAG_X; - FLAG_N = NFLAG_16(*r_dst); - FLAG_Z = MASK_OUT_ABOVE_16(*r_dst); - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(roxl, 32, r, .) -{ -#if M68K_USE_64_BIT - - uint* r_dst = &DY; - uint orig_shift = DX & 0x3f; - - if(orig_shift != 0) - { - uint shift = orig_shift % 33; - uint64 src = *r_dst; - uint64 res = src | (((uint64)XFLAG_AS_1()) << 32); - - res = ROL_33_64(res, shift); - - USE_CYCLES(orig_shift<> 24; - res = MASK_OUT_ABOVE_32(res); - - *r_dst = res; - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - return; - } - - FLAG_C = FLAG_X; - FLAG_N = NFLAG_32(*r_dst); - FLAG_Z = *r_dst; - FLAG_V = VFLAG_CLEAR; - -#else - - uint* r_dst = &DY; - uint orig_shift = DX & 0x3f; - uint shift = orig_shift % 33; - uint src = *r_dst; - uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1))); - uint new_x_flag = src & (1 << (32 - shift)); - - if(orig_shift != 0) - USE_CYCLES(orig_shift<> 8; - res = MASK_OUT_ABOVE_16(res); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(rtd, 32, ., .) -{ - if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) - { - uint new_pc = m68ki_pull_32(); - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16())); - m68ki_jump(new_pc); - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(rte, 32, ., .) -{ - if(FLAG_S) - { - uint new_sr; - uint new_pc; - uint format_word; - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - - if(CPU_TYPE_IS_000(CPU_TYPE)) - { - new_sr = m68ki_pull_16(); - new_pc = m68ki_pull_32(); - m68ki_jump(new_pc); - m68ki_set_sr(new_sr); - return; - } - - if(CPU_TYPE_IS_010(CPU_TYPE)) - { - format_word = m68ki_read_16(REG_A[7]+6) >> 12; - if(format_word == 0) - { - new_sr = m68ki_pull_16(); - new_pc = m68ki_pull_32(); - m68ki_fake_pull_16(); /* format word */ - m68ki_jump(new_pc); - m68ki_set_sr(new_sr); - return; - } - /* Not handling bus fault (9) */ - m68ki_exception_format_error(); - return; - } - - /* Otherwise it's 020 */ -rte_loop: - format_word = m68ki_read_16(REG_A[7]+6) >> 12; - switch(format_word) - { - case 0: /* Normal */ - new_sr = m68ki_pull_16(); - new_pc = m68ki_pull_32(); - m68ki_fake_pull_16(); /* format word */ - m68ki_jump(new_pc); - m68ki_set_sr(new_sr); - return; - case 1: /* Throwaway */ - new_sr = m68ki_pull_16(); - m68ki_fake_pull_32(); /* program counter */ - m68ki_fake_pull_16(); /* format word */ - m68ki_set_sr_noint(new_sr); - goto rte_loop; - case 2: /* Trap */ - new_sr = m68ki_pull_16(); - new_pc = m68ki_pull_32(); - m68ki_fake_pull_16(); /* format word */ - m68ki_fake_pull_32(); /* address */ - m68ki_jump(new_pc); - m68ki_set_sr(new_sr); - return; - } - /* Not handling long or short bus fault */ - m68ki_exception_format_error(); - return; - } - m68ki_exception_privilege_violation(); -} - - -M68KMAKE_OP(rtm, 32, ., .) -{ - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - { - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", - m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, - m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(rtr, 32, ., .) -{ - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_set_ccr(m68ki_pull_16()); - m68ki_jump(m68ki_pull_32()); -} - - -M68KMAKE_OP(rts, 32, ., .) -{ - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_jump(m68ki_pull_32()); -} - - -M68KMAKE_OP(sbcd, 8, rr, .) -{ - uint* r_dst = &DX; - uint src = DY; - uint dst = *r_dst; - uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1(); - - FLAG_V = ~res; /* Undefined V behavior */ - - if(res > 9) - res -= 6; - res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src); - FLAG_X = FLAG_C = (res > 0x99) << 8; - if(FLAG_C) - res += 0xa0; - - res = MASK_OUT_ABOVE_8(res); - - FLAG_V &= res; /* Undefined V behavior part II */ - FLAG_N = NFLAG_8(res); /* Undefined N behavior */ - FLAG_Z |= res; - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; -} - - -M68KMAKE_OP(sbcd, 8, mm, ax7) -{ - uint src = OPER_AY_PD_8(); - uint ea = EA_A7_PD_8(); - uint dst = m68ki_read_8(ea); - uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1(); - - FLAG_V = ~res; /* Undefined V behavior */ - - if(res > 9) - res -= 6; - res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src); - FLAG_X = FLAG_C = (res > 0x99) << 8; - if(FLAG_C) - res += 0xa0; - - res = MASK_OUT_ABOVE_8(res); - - FLAG_V &= res; /* Undefined V behavior part II */ - FLAG_N = NFLAG_8(res); /* Undefined N behavior */ - FLAG_Z |= res; - - m68ki_write_8(ea, res); -} - - -M68KMAKE_OP(sbcd, 8, mm, ay7) -{ - uint src = OPER_A7_PD_8(); - uint ea = EA_AX_PD_8(); - uint dst = m68ki_read_8(ea); - uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1(); - - FLAG_V = ~res; /* Undefined V behavior */ - - if(res > 9) - res -= 6; - res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src); - FLAG_X = FLAG_C = (res > 0x99) << 8; - if(FLAG_C) - res += 0xa0; - - res = MASK_OUT_ABOVE_8(res); - - FLAG_V &= res; /* Undefined V behavior part II */ - FLAG_N = NFLAG_8(res); /* Undefined N behavior */ - FLAG_Z |= res; - - m68ki_write_8(ea, res); -} - - -M68KMAKE_OP(sbcd, 8, mm, axy7) -{ - uint src = OPER_A7_PD_8(); - uint ea = EA_A7_PD_8(); - uint dst = m68ki_read_8(ea); - uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1(); - - FLAG_V = ~res; /* Undefined V behavior */ - - if(res > 9) - res -= 6; - res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src); - FLAG_X = FLAG_C = (res > 0x99) << 8; - if(FLAG_C) - res += 0xa0; - - res = MASK_OUT_ABOVE_8(res); - - FLAG_V &= res; /* Undefined V behavior part II */ - FLAG_N = NFLAG_8(res); /* Undefined N behavior */ - FLAG_Z |= res; - - m68ki_write_8(ea, res); -} - - -M68KMAKE_OP(sbcd, 8, mm, .) -{ - uint src = OPER_AY_PD_8(); - uint ea = EA_AX_PD_8(); - uint dst = m68ki_read_8(ea); - uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1(); - - FLAG_V = ~res; /* Undefined V behavior */ - - if(res > 9) - res -= 6; - res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src); - FLAG_X = FLAG_C = (res > 0x99) << 8; - if(FLAG_C) - res += 0xa0; - - res = MASK_OUT_ABOVE_8(res); - - FLAG_V &= res; /* Undefined V behavior part II */ - FLAG_N = NFLAG_8(res); /* Undefined N behavior */ - FLAG_Z |= res; - - m68ki_write_8(ea, res); -} - - -M68KMAKE_OP(st, 8, ., d) -{ - DY |= 0xff; -} - - -M68KMAKE_OP(st, 8, ., .) -{ - m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0xff); -} - - -M68KMAKE_OP(sf, 8, ., d) -{ - DY &= 0xffffff00; -} - - -M68KMAKE_OP(sf, 8, ., .) -{ - m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0); -} - - -M68KMAKE_OP(scc, 8, ., d) -{ - if(M68KMAKE_CC) - { - DY |= 0xff; - return; - } - DY &= 0xffffff00; -} - - -M68KMAKE_OP(scc, 8, ., .) -{ - m68ki_write_8(M68KMAKE_GET_EA_AY_8, M68KMAKE_CC ? 0xff : 0); -} - - -M68KMAKE_OP(stop, 0, ., .) -{ - if(FLAG_S) - { - uint new_sr = OPER_I_16(); - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - CPU_STOPPED |= STOP_LEVEL_STOP; - m68ki_set_sr(new_sr); - m68ki_remaining_cycles = 0; - return; - } - m68ki_exception_privilege_violation(); -} - - -M68KMAKE_OP(sub, 8, er, d) -{ - uint* r_dst = &DX; - uint src = MASK_OUT_ABOVE_8(DY); - uint dst = MASK_OUT_ABOVE_8(*r_dst); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; -} - - -M68KMAKE_OP(sub, 8, er, .) -{ - uint* r_dst = &DX; - uint src = M68KMAKE_GET_OPER_AY_8; - uint dst = MASK_OUT_ABOVE_8(*r_dst); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; -} - - -M68KMAKE_OP(sub, 16, er, d) -{ - uint* r_dst = &DX; - uint src = MASK_OUT_ABOVE_16(DY); - uint dst = MASK_OUT_ABOVE_16(*r_dst); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; -} - - -M68KMAKE_OP(sub, 16, er, a) -{ - uint* r_dst = &DX; - uint src = MASK_OUT_ABOVE_16(AY); - uint dst = MASK_OUT_ABOVE_16(*r_dst); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; -} - - -M68KMAKE_OP(sub, 16, er, .) -{ - uint* r_dst = &DX; - uint src = M68KMAKE_GET_OPER_AY_16; - uint dst = MASK_OUT_ABOVE_16(*r_dst); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; -} - - -M68KMAKE_OP(sub, 32, er, d) -{ - uint* r_dst = &DX; - uint src = DY; - uint dst = *r_dst; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - *r_dst = FLAG_Z; -} - - -M68KMAKE_OP(sub, 32, er, a) -{ - uint* r_dst = &DX; - uint src = AY; - uint dst = *r_dst; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - *r_dst = FLAG_Z; -} - - -M68KMAKE_OP(sub, 32, er, .) -{ - uint* r_dst = &DX; - uint src = M68KMAKE_GET_OPER_AY_32; - uint dst = *r_dst; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - *r_dst = FLAG_Z; -} - - -M68KMAKE_OP(sub, 8, re, .) -{ - uint ea = M68KMAKE_GET_EA_AY_8; - uint src = MASK_OUT_ABOVE_8(DX); - uint dst = m68ki_read_8(ea); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - - m68ki_write_8(ea, FLAG_Z); -} - - -M68KMAKE_OP(sub, 16, re, .) -{ - uint ea = M68KMAKE_GET_EA_AY_16; - uint src = MASK_OUT_ABOVE_16(DX); - uint dst = m68ki_read_16(ea); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - - m68ki_write_16(ea, FLAG_Z); -} - - -M68KMAKE_OP(sub, 32, re, .) -{ - uint ea = M68KMAKE_GET_EA_AY_32; - uint src = DX; - uint dst = m68ki_read_32(ea); - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - - m68ki_write_32(ea, FLAG_Z); -} - - -M68KMAKE_OP(suba, 16, ., d) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(DY)); -} - - -M68KMAKE_OP(suba, 16, ., a) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(AY)); -} - - -M68KMAKE_OP(suba, 16, ., .) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(M68KMAKE_GET_OPER_AY_16)); -} - - -M68KMAKE_OP(suba, 32, ., d) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst - DY); -} - - -M68KMAKE_OP(suba, 32, ., a) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst - AY); -} - - -M68KMAKE_OP(suba, 32, ., .) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst - M68KMAKE_GET_OPER_AY_32); -} - - -M68KMAKE_OP(subi, 8, ., d) -{ - uint* r_dst = &DY; - uint src = OPER_I_8(); - uint dst = MASK_OUT_ABOVE_8(*r_dst); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; -} - - -M68KMAKE_OP(subi, 8, ., .) -{ - uint src = OPER_I_8(); - uint ea = M68KMAKE_GET_EA_AY_8; - uint dst = m68ki_read_8(ea); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - - m68ki_write_8(ea, FLAG_Z); -} - - -M68KMAKE_OP(subi, 16, ., d) -{ - uint* r_dst = &DY; - uint src = OPER_I_16(); - uint dst = MASK_OUT_ABOVE_16(*r_dst); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; -} - - -M68KMAKE_OP(subi, 16, ., .) -{ - uint src = OPER_I_16(); - uint ea = M68KMAKE_GET_EA_AY_16; - uint dst = m68ki_read_16(ea); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - - m68ki_write_16(ea, FLAG_Z); -} - - -M68KMAKE_OP(subi, 32, ., d) -{ - uint* r_dst = &DY; - uint src = OPER_I_32(); - uint dst = *r_dst; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - - *r_dst = FLAG_Z; -} - - -M68KMAKE_OP(subi, 32, ., .) -{ - uint src = OPER_I_32(); - uint ea = M68KMAKE_GET_EA_AY_32; - uint dst = m68ki_read_32(ea); - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - - m68ki_write_32(ea, FLAG_Z); -} - - -M68KMAKE_OP(subq, 8, ., d) -{ - uint* r_dst = &DY; - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint dst = MASK_OUT_ABOVE_8(*r_dst); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; -} - - -M68KMAKE_OP(subq, 8, ., .) -{ - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint ea = M68KMAKE_GET_EA_AY_8; - uint dst = m68ki_read_8(ea); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - - m68ki_write_8(ea, FLAG_Z); -} - - -M68KMAKE_OP(subq, 16, ., d) -{ - uint* r_dst = &DY; - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint dst = MASK_OUT_ABOVE_16(*r_dst); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; -} - - -M68KMAKE_OP(subq, 16, ., a) -{ - uint* r_dst = &AY; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1)); -} - - -M68KMAKE_OP(subq, 16, ., .) -{ - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint ea = M68KMAKE_GET_EA_AY_16; - uint dst = m68ki_read_16(ea); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - - m68ki_write_16(ea, FLAG_Z); -} - - -M68KMAKE_OP(subq, 32, ., d) -{ - uint* r_dst = &DY; - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint dst = *r_dst; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - - *r_dst = FLAG_Z; -} - - -M68KMAKE_OP(subq, 32, ., a) -{ - uint* r_dst = &AY; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1)); -} - - -M68KMAKE_OP(subq, 32, ., .) -{ - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint ea = M68KMAKE_GET_EA_AY_32; - uint dst = m68ki_read_32(ea); - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - - m68ki_write_32(ea, FLAG_Z); -} - - -M68KMAKE_OP(subx, 8, rr, .) -{ - uint* r_dst = &DX; - uint src = MASK_OUT_ABOVE_8(DY); - uint dst = MASK_OUT_ABOVE_8(*r_dst); - uint res = dst - src - XFLAG_AS_1(); - - FLAG_N = NFLAG_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - - res = MASK_OUT_ABOVE_8(res); - FLAG_Z |= res; - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; -} - - -M68KMAKE_OP(subx, 16, rr, .) -{ - uint* r_dst = &DX; - uint src = MASK_OUT_ABOVE_16(DY); - uint dst = MASK_OUT_ABOVE_16(*r_dst); - uint res = dst - src - XFLAG_AS_1(); - - FLAG_N = NFLAG_16(res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - - res = MASK_OUT_ABOVE_16(res); - FLAG_Z |= res; - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; -} - - -M68KMAKE_OP(subx, 32, rr, .) -{ - uint* r_dst = &DX; - uint src = DY; - uint dst = *r_dst; - uint res = dst - src - XFLAG_AS_1(); - - FLAG_N = NFLAG_32(res); - FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - - res = MASK_OUT_ABOVE_32(res); - FLAG_Z |= res; - - *r_dst = res; -} - - -M68KMAKE_OP(subx, 8, mm, ax7) -{ - uint src = OPER_AY_PD_8(); - uint ea = EA_A7_PD_8(); - uint dst = m68ki_read_8(ea); - uint res = dst - src - XFLAG_AS_1(); - - FLAG_N = NFLAG_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - - res = MASK_OUT_ABOVE_8(res); - FLAG_Z |= res; - - m68ki_write_8(ea, res); -} - - -M68KMAKE_OP(subx, 8, mm, ay7) -{ - uint src = OPER_A7_PD_8(); - uint ea = EA_AX_PD_8(); - uint dst = m68ki_read_8(ea); - uint res = dst - src - XFLAG_AS_1(); - - FLAG_N = NFLAG_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - - res = MASK_OUT_ABOVE_8(res); - FLAG_Z |= res; - - m68ki_write_8(ea, res); -} - - -M68KMAKE_OP(subx, 8, mm, axy7) -{ - uint src = OPER_A7_PD_8(); - uint ea = EA_A7_PD_8(); - uint dst = m68ki_read_8(ea); - uint res = dst - src - XFLAG_AS_1(); - - FLAG_N = NFLAG_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - - res = MASK_OUT_ABOVE_8(res); - FLAG_Z |= res; - - m68ki_write_8(ea, res); -} - - -M68KMAKE_OP(subx, 8, mm, .) -{ - uint src = OPER_AY_PD_8(); - uint ea = EA_AX_PD_8(); - uint dst = m68ki_read_8(ea); - uint res = dst - src - XFLAG_AS_1(); - - FLAG_N = NFLAG_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - - res = MASK_OUT_ABOVE_8(res); - FLAG_Z |= res; - - m68ki_write_8(ea, res); -} - - -M68KMAKE_OP(subx, 16, mm, .) -{ - uint src = OPER_AY_PD_16(); - uint ea = EA_AX_PD_16(); - uint dst = m68ki_read_16(ea); - uint res = dst - src - XFLAG_AS_1(); - - FLAG_N = NFLAG_16(res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - - res = MASK_OUT_ABOVE_16(res); - FLAG_Z |= res; - - m68ki_write_16(ea, res); -} - - -M68KMAKE_OP(subx, 32, mm, .) -{ - uint src = OPER_AY_PD_32(); - uint ea = EA_AX_PD_32(); - uint dst = m68ki_read_32(ea); - uint res = dst - src - XFLAG_AS_1(); - - FLAG_N = NFLAG_32(res); - FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - - res = MASK_OUT_ABOVE_32(res); - FLAG_Z |= res; - - m68ki_write_32(ea, res); -} - - -M68KMAKE_OP(swap, 32, ., .) -{ - uint* r_dst = &DY; - - FLAG_Z = MASK_OUT_ABOVE_32(*r_dst<<16); - *r_dst = (*r_dst>>16) | FLAG_Z; - - FLAG_Z = *r_dst; - FLAG_N = NFLAG_32(*r_dst); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -M68KMAKE_OP(tas, 8, ., d) -{ - uint* r_dst = &DY; - - FLAG_Z = MASK_OUT_ABOVE_8(*r_dst); - FLAG_N = NFLAG_8(*r_dst); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - *r_dst |= 0x80; -} - - -M68KMAKE_OP(tas, 8, ., .) -{ - uint ea = M68KMAKE_GET_EA_AY_8; - uint dst = m68ki_read_8(ea); - - FLAG_Z = dst; - FLAG_N = NFLAG_8(dst); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - m68ki_write_8(ea, dst | 0x80); -} - - -M68KMAKE_OP(trap, 0, ., .) -{ - /* Trap#n stacks exception frame type 0 */ - m68ki_exception_trapN(EXCEPTION_TRAP_BASE + (REG_IR & 0xf)); /* HJB 990403 */ -} - - -M68KMAKE_OP(trapt, 0, ., .) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(trapt, 16, ., .) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(trapt, 32, ., .) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(trapf, 0, ., .) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(trapf, 16, ., .) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - REG_PC += 2; - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(trapf, 32, ., .) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - REG_PC += 4; - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(trapcc, 0, ., .) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(M68KMAKE_CC) - m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(trapcc, 16, ., .) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(M68KMAKE_CC) - { - m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ - return; - } - REG_PC += 2; - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(trapcc, 32, ., .) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(M68KMAKE_CC) - { - m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ - return; - } - REG_PC += 4; - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(trapv, 0, ., .) -{ - if(COND_VC()) - { - return; - } - m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ -} - - -M68KMAKE_OP(tst, 8, ., d) -{ - uint res = MASK_OUT_ABOVE_8(DY); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(tst, 8, ., .) -{ - uint res = M68KMAKE_GET_OPER_AY_8; - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(tst, 8, ., pcdi) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint res = OPER_PCDI_8(); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(tst, 8, ., pcix) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint res = OPER_PCIX_8(); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(tst, 8, ., i) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint res = OPER_I_8(); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(tst, 16, ., d) -{ - uint res = MASK_OUT_ABOVE_16(DY); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(tst, 16, ., a) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint res = MAKE_INT_16(AY); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(tst, 16, ., .) -{ - uint res = M68KMAKE_GET_OPER_AY_16; - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(tst, 16, ., pcdi) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint res = OPER_PCDI_16(); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(tst, 16, ., pcix) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint res = OPER_PCIX_16(); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(tst, 16, ., i) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint res = OPER_I_16(); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(tst, 32, ., d) -{ - uint res = DY; - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(tst, 32, ., a) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint res = AY; - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(tst, 32, ., .) -{ - uint res = M68KMAKE_GET_OPER_AY_32; - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -M68KMAKE_OP(tst, 32, ., pcdi) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint res = OPER_PCDI_32(); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(tst, 32, ., pcix) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint res = OPER_PCIX_32(); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(tst, 32, ., i) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint res = OPER_I_32(); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(unlk, 32, ., a7) -{ - REG_A[7] = m68ki_read_32(REG_A[7]); -} - - -M68KMAKE_OP(unlk, 32, ., .) -{ - uint* r_dst = &AY; - - REG_A[7] = *r_dst; - *r_dst = m68ki_pull_32(); -} - - -M68KMAKE_OP(unpk, 16, rr, .) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - /* Note: DX and DY are reversed in Motorola's docs */ - uint src = DY; - uint* r_dst = &DX; - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | (((((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16()) & 0xffff); - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(unpk, 16, mm, ax7) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - /* Note: AX and AY are reversed in Motorola's docs */ - uint src = OPER_AY_PD_8(); - uint ea_dst; - - src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16(); - ea_dst = EA_A7_PD_8(); - m68ki_write_8(ea_dst, (src >> 8) & 0xff); - ea_dst = EA_A7_PD_8(); - m68ki_write_8(ea_dst, src & 0xff); - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(unpk, 16, mm, ay7) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - /* Note: AX and AY are reversed in Motorola's docs */ - uint src = OPER_A7_PD_8(); - uint ea_dst; - - src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16(); - ea_dst = EA_AX_PD_8(); - m68ki_write_8(ea_dst, (src >> 8) & 0xff); - ea_dst = EA_AX_PD_8(); - m68ki_write_8(ea_dst, src & 0xff); - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(unpk, 16, mm, axy7) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint src = OPER_A7_PD_8(); - uint ea_dst; - - src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16(); - ea_dst = EA_A7_PD_8(); - m68ki_write_8(ea_dst, (src >> 8) & 0xff); - ea_dst = EA_A7_PD_8(); - m68ki_write_8(ea_dst, src & 0xff); - return; - } - m68ki_exception_illegal(); -} - - -M68KMAKE_OP(unpk, 16, mm, .) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - /* Note: AX and AY are reversed in Motorola's docs */ - uint src = OPER_AY_PD_8(); - uint ea_dst; - - src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16(); - ea_dst = EA_AX_PD_8(); - m68ki_write_8(ea_dst, (src >> 8) & 0xff); - ea_dst = EA_AX_PD_8(); - m68ki_write_8(ea_dst, src & 0xff); - return; - } - m68ki_exception_illegal(); -} - - - -XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -M68KMAKE_END diff --git a/Frameworks/AudioOverload/aosdk/eng_ssf/m68kconf.h b/Frameworks/AudioOverload/aosdk/eng_ssf/m68kconf.h deleted file mode 100644 index 74c2dd229..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_ssf/m68kconf.h +++ /dev/null @@ -1,181 +0,0 @@ -/* ======================================================================== */ -/* ========================= LICENSING & COPYRIGHT ======================== */ -/* ======================================================================== */ -/* - * MUSASHI - * Version 3.3 - * - * A portable Motorola M680x0 processor emulation engine. - * Copyright 1998-2001 Karl Stenerud. All rights reserved. - * - * This code may be freely used for non-commercial purposes as long as this - * copyright notice remains unaltered in the source code and any binary files - * containing this code in compiled form. - * - * All other lisencing terms must be negotiated with the author - * (Karl Stenerud). - * - * The latest version of this code can be obtained at: - * http://kstenerud.cjb.net - */ - - - -#ifndef M68KCONF__HEADER -#define M68KCONF__HEADER - - -/* Configuration switches. - * Use OPT_SPECIFY_HANDLER for configuration options that allow callbacks. - * OPT_SPECIFY_HANDLER causes the core to link directly to the function - * or macro you specify, rather than using callback functions whose pointer - * must be passed in using m68k_set_xxx_callback(). - */ -#define OPT_OFF 0 -#define OPT_ON 1 -#define OPT_SPECIFY_HANDLER 2 - - -/* ======================================================================== */ -/* ============================== MAME STUFF ============================== */ -/* ======================================================================== */ - -/* If you're compiling this for MAME, only change M68K_COMPILE_FOR_MAME - * to OPT_ON and use m68kmame.h to configure the 68k core. - */ -#ifndef M68K_COMPILE_FOR_MAME -#define M68K_COMPILE_FOR_MAME OPT_OFF -#endif /* M68K_COMPILE_FOR_MAME */ - -#if M68K_COMPILE_FOR_MAME == OPT_ON -#include "m68kmame.h" -#else - - - -/* ======================================================================== */ -/* ============================= CONFIGURATION ============================ */ -/* ======================================================================== */ - -/* Turn ON if you want to use the following M68K variants */ -#define M68K_EMULATE_010 OPT_OFF -#define M68K_EMULATE_EC020 OPT_OFF -#define M68K_EMULATE_020 OPT_OFF - - -/* If ON, the CPU will call m68k_read_immediate_xx() for immediate addressing - * and m68k_read_pcrelative_xx() for PC-relative addressing. - * If off, all read requests from the CPU will be redirected to m68k_read_xx() - */ -#define M68K_SEPARATE_READS OPT_OFF - -/* If ON, the CPU will call m68k_write_32_pd() when it executes move.l with a - * predecrement destination EA mode instead of m68k_write_32(). - * To simulate real 68k behavior, m68k_write_32_pd() must first write the high - * word to [address+2], and then write the low word to [address]. - */ -#define M68K_SIMULATE_PD_WRITES OPT_OFF - -/* If ON, CPU will call the interrupt acknowledge callback when it services an - * interrupt. - * If off, all interrupts will be autovectored and all interrupt requests will - * auto-clear when the interrupt is serviced. - */ -#define M68K_EMULATE_INT_ACK OPT_ON -#define M68K_INT_ACK_CALLBACK(A) your_int_ack_handler_function(A) - - -/* If ON, CPU will call the breakpoint acknowledge callback when it encounters - * a breakpoint instruction and it is running a 68010+. - */ -#define M68K_EMULATE_BKPT_ACK OPT_OFF -#define M68K_BKPT_ACK_CALLBACK() your_bkpt_ack_handler_function() - - -/* If ON, the CPU will monitor the trace flags and take trace exceptions - */ -#define M68K_EMULATE_TRACE OPT_OFF - - -/* If ON, CPU will call the output reset callback when it encounters a reset - * instruction. - */ -#define M68K_EMULATE_RESET OPT_OFF -#define M68K_RESET_CALLBACK() your_reset_handler_function() - - -/* If ON, CPU will call the set fc callback on every memory access to - * differentiate between user/supervisor, program/data access like a real - * 68000 would. This should be enabled and the callback should be set if you - * want to properly emulate the m68010 or higher. (moves uses function codes - * to read/write data from different address spaces) - */ -#define M68K_EMULATE_FC OPT_OFF -#define M68K_SET_FC_CALLBACK(A) your_set_fc_handler_function(A) - - -/* If ON, CPU will call the pc changed callback when it changes the PC by a - * large value. This allows host programs to be nicer when it comes to - * fetching immediate data and instructions on a banked memory system. - */ -#define M68K_MONITOR_PC OPT_OFF -#define M68K_SET_PC_CALLBACK(A) your_pc_changed_handler_function(A) - - -/* If ON, CPU will call the instruction hook callback before every - * instruction. - */ -#define M68K_INSTRUCTION_HOOK OPT_OFF -#define M68K_INSTRUCTION_CALLBACK() your_instruction_hook_function() - - -/* If ON, the CPU will emulate the 4-byte prefetch queue of a real 68000 */ -#define M68K_EMULATE_PREFETCH OPT_ON - - -/* If ON, the CPU will generate address error exceptions if it tries to - * access a word or longword at an odd address. - * NOTE: Do not enable this! It is not working! - */ -#define M68K_EMULATE_ADDRESS_ERROR OPT_OFF - - -/* Turn ON to enable logging of illegal instruction calls. - * M68K_LOG_FILEHANDLE must be #defined to a stdio file stream. - * Turn on M68K_LOG_1010_1111 to log all 1010 and 1111 calls. - */ -#define M68K_LOG_ENABLE OPT_OFF -#define M68K_LOG_1010_1111 OPT_OFF -#define M68K_LOG_FILEHANDLE some_file_handle - - -/* ----------------------------- COMPATIBILITY ---------------------------- */ - -/* The following options set optimizations that violate the current ANSI - * standard, but will be compliant under the forthcoming C9X standard. - */ - - -/* If ON, the enulation core will use 64-bit integers to speed up some - * operations. -*/ -#define M68K_USE_64_BIT OPT_OFF - - -/* Set to your compiler's static inline keyword to enable it, or - * set it to blank to disable it. - * If you define INLINE in the makefile, it will override this value. - * NOTE: not enabling inline functions will SEVERELY slow down emulation. - */ -#ifndef INLINE -#define INLINE static __inline__ -#endif /* INLINE */ - -#endif /* M68K_COMPILE_FOR_MAME */ - - -/* ======================================================================== */ -/* ============================== END OF FILE ============================= */ -/* ======================================================================== */ - -#endif /* M68KCONF__HEADER */ diff --git a/Frameworks/AudioOverload/aosdk/eng_ssf/m68kcpu.h b/Frameworks/AudioOverload/aosdk/eng_ssf/m68kcpu.h deleted file mode 100644 index 80d4e19a2..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_ssf/m68kcpu.h +++ /dev/null @@ -1,1973 +0,0 @@ -#include -#ifdef _MSC_VER -#include "ao.h" -#else -#define INLINE static inline -#endif -/* ======================================================================== */ -/* ========================= LICENSING & COPYRIGHT ======================== */ -/* ======================================================================== */ -/* - * MUSASHI - * Version 3.3 - * - * A portable Motorola M680x0 processor emulation engine. - * Copyright 1998-2001 Karl Stenerud. All rights reserved. - * - * This code may be freely used for non-commercial purposes as long as this - * copyright notice remains unaltered in the source code and any binary files - * containing this code in compiled form. - * - * All other lisencing terms must be negotiated with the author - * (Karl Stenerud). - * - * The latest version of this code can be obtained at: - * http://kstenerud.cjb.net - */ - - - - -#ifndef M68KCPU__HEADER -#define M68KCPU__HEADER - -#include "m68k.h" -#include - -#if M68K_EMULATE_ADDRESS_ERROR -#include -#endif /* M68K_EMULATE_ADDRESS_ERROR */ - -/* ======================================================================== */ -/* ==================== ARCHITECTURE-DEPENDANT DEFINES ==================== */ -/* ======================================================================== */ - -/* Check for > 32bit sizes */ -#if UINT_MAX > 0xffffffff - #define M68K_INT_GT_32_BIT 1 -#else - #define M68K_INT_GT_32_BIT 0 -#endif - -/* Data types used in this emulation core */ -#undef sint8 -#undef sint16 -#undef sint32 -#undef sint64 -#undef uint8 -#undef uint16 -#undef uint32 -#undef uint64 -#undef sint -#undef uint - -#define sint8 signed char /* ASG: changed from char to signed char */ -#define sint16 signed short -#define sint32 signed long -#define uint8 unsigned char -#define uint16 unsigned short -#define uint32 unsigned long - -/* signed and unsigned int must be at least 32 bits wide */ -#define sint signed int -#define uint unsigned int - - -#if M68K_USE_64_BIT -#define sint64 signed long long -#define uint64 unsigned long long -#else -#define sint64 sint32 -#define uint64 uint32 -#endif /* M68K_USE_64_BIT */ - - - -/* Allow for architectures that don't have 8-bit sizes */ -#if UCHAR_MAX == 0xff - #define MAKE_INT_8(A) (sint8)(A) -#else - #undef sint8 - #define sint8 signed int - #undef uint8 - #define uint8 unsigned int - INLINE sint MAKE_INT_8(uint value) - { - return (value & 0x80) ? value | ~0xff : value & 0xff; - } -#endif /* UCHAR_MAX == 0xff */ - - -/* Allow for architectures that don't have 16-bit sizes */ -#if USHRT_MAX == 0xffff - #define MAKE_INT_16(A) (sint16)(A) -#else - #undef sint16 - #define sint16 signed int - #undef uint16 - #define uint16 unsigned int - INLINE sint MAKE_INT_16(uint value) - { - return (value & 0x8000) ? value | ~0xffff : value & 0xffff; - } -#endif /* USHRT_MAX == 0xffff */ - - -/* Allow for architectures that don't have 32-bit sizes */ -#if ULONG_MAX == 0xffffffff - #define MAKE_INT_32(A) (sint32)(A) -#else - #undef sint32 - #define sint32 signed int - #undef uint32 - #define uint32 unsigned int - INLINE sint MAKE_INT_32(uint value) - { - return (value & 0x80000000) ? value | ~0xffffffff : value & 0xffffffff; - } -#endif /* ULONG_MAX == 0xffffffff */ - - - - -/* ======================================================================== */ -/* ============================ GENERAL DEFINES =========================== */ -/* ======================================================================== */ - -/* Exception Vectors handled by emulation */ -#define EXCEPTION_BUS_ERROR 2 /* This one is not emulated! */ -#define EXCEPTION_ADDRESS_ERROR 3 /* This one is partially emulated (doesn't stack a proper frame yet) */ -#define EXCEPTION_ILLEGAL_INSTRUCTION 4 -#define EXCEPTION_ZERO_DIVIDE 5 -#define EXCEPTION_CHK 6 -#define EXCEPTION_TRAPV 7 -#define EXCEPTION_PRIVILEGE_VIOLATION 8 -#define EXCEPTION_TRACE 9 -#define EXCEPTION_1010 10 -#define EXCEPTION_1111 11 -#define EXCEPTION_FORMAT_ERROR 14 -#define EXCEPTION_UNINITIALIZED_INTERRUPT 15 -#define EXCEPTION_SPURIOUS_INTERRUPT 24 -#define EXCEPTION_INTERRUPT_AUTOVECTOR 24 -#define EXCEPTION_TRAP_BASE 32 - -/* Function codes set by CPU during data/address bus activity */ -#define FUNCTION_CODE_USER_DATA 1 -#define FUNCTION_CODE_USER_PROGRAM 2 -#define FUNCTION_CODE_SUPERVISOR_DATA 5 -#define FUNCTION_CODE_SUPERVISOR_PROGRAM 6 -#define FUNCTION_CODE_CPU_SPACE 7 - -/* CPU types for deciding what to emulate */ -#define CPU_TYPE_000 1 -#define CPU_TYPE_010 2 -#define CPU_TYPE_EC020 4 -#define CPU_TYPE_020 8 - -/* Different ways to stop the CPU */ -#define STOP_LEVEL_STOP 1 -#define STOP_LEVEL_HALT 2 - -/* Used for 68000 address error processing */ -#define INSTRUCTION_YES 0 -#define INSTRUCTION_NO 0x08 -#define MODE_READ 0x10 -#define MODE_WRITE 0 - -#define RUN_MODE_NORMAL 0 -#define RUN_MODE_BERR_AERR_RESET 1 - -#ifndef NULL -#define NULL ((void*)0) -#endif - -/* ======================================================================== */ -/* ================================ MACROS ================================ */ -/* ======================================================================== */ - - -/* ---------------------------- General Macros ---------------------------- */ - -/* Bit Isolation Macros */ -#define BIT_0(A) ((A) & 0x00000001) -#define BIT_1(A) ((A) & 0x00000002) -#define BIT_2(A) ((A) & 0x00000004) -#define BIT_3(A) ((A) & 0x00000008) -#define BIT_4(A) ((A) & 0x00000010) -#define BIT_5(A) ((A) & 0x00000020) -#define BIT_6(A) ((A) & 0x00000040) -#define BIT_7(A) ((A) & 0x00000080) -#define BIT_8(A) ((A) & 0x00000100) -#define BIT_9(A) ((A) & 0x00000200) -#define BIT_A(A) ((A) & 0x00000400) -#define BIT_B(A) ((A) & 0x00000800) -#define BIT_C(A) ((A) & 0x00001000) -#define BIT_D(A) ((A) & 0x00002000) -#define BIT_E(A) ((A) & 0x00004000) -#define BIT_F(A) ((A) & 0x00008000) -#define BIT_10(A) ((A) & 0x00010000) -#define BIT_11(A) ((A) & 0x00020000) -#define BIT_12(A) ((A) & 0x00040000) -#define BIT_13(A) ((A) & 0x00080000) -#define BIT_14(A) ((A) & 0x00100000) -#define BIT_15(A) ((A) & 0x00200000) -#define BIT_16(A) ((A) & 0x00400000) -#define BIT_17(A) ((A) & 0x00800000) -#define BIT_18(A) ((A) & 0x01000000) -#define BIT_19(A) ((A) & 0x02000000) -#define BIT_1A(A) ((A) & 0x04000000) -#define BIT_1B(A) ((A) & 0x08000000) -#define BIT_1C(A) ((A) & 0x10000000) -#define BIT_1D(A) ((A) & 0x20000000) -#define BIT_1E(A) ((A) & 0x40000000) -#define BIT_1F(A) ((A) & 0x80000000) - -/* Get the most significant bit for specific sizes */ -#define GET_MSB_8(A) ((A) & 0x80) -#define GET_MSB_9(A) ((A) & 0x100) -#define GET_MSB_16(A) ((A) & 0x8000) -#define GET_MSB_17(A) ((A) & 0x10000) -#define GET_MSB_32(A) ((A) & 0x80000000) -#if M68K_USE_64_BIT -#define GET_MSB_33(A) ((A) & 0x100000000) -#endif /* M68K_USE_64_BIT */ - -/* Isolate nibbles */ -#define LOW_NIBBLE(A) ((A) & 0x0f) -#define HIGH_NIBBLE(A) ((A) & 0xf0) - -/* These are used to isolate 8, 16, and 32 bit sizes */ -#define MASK_OUT_ABOVE_2(A) ((A) & 3) -#define MASK_OUT_ABOVE_8(A) ((A) & 0xff) -#define MASK_OUT_ABOVE_16(A) ((A) & 0xffff) -#define MASK_OUT_BELOW_2(A) ((A) & ~3) -#define MASK_OUT_BELOW_8(A) ((A) & ~0xff) -#define MASK_OUT_BELOW_16(A) ((A) & ~0xffff) - -/* No need to mask if we are 32 bit */ -#if M68K_INT_GT_32_BIT || M68K_USE_64_BIT - #define MASK_OUT_ABOVE_32(A) ((A) & 0xffffffff) - #define MASK_OUT_BELOW_32(A) ((A) & ~0xffffffff) -#else - #define MASK_OUT_ABOVE_32(A) (A) - #define MASK_OUT_BELOW_32(A) 0 -#endif /* M68K_INT_GT_32_BIT || M68K_USE_64_BIT */ - -/* Simulate address lines of 68k family */ -#define ADDRESS_68K(A) ((A)&CPU_ADDRESS_MASK) - - -/* Shift & Rotate Macros. */ -#define LSL(A, C) ((A) << (C)) -#define LSR(A, C) ((A) >> (C)) - -/* Some > 32-bit optimizations */ -#if M68K_INT_GT_32_BIT - /* Shift left and right */ - #define LSR_32(A, C) ((A) >> (C)) - #define LSL_32(A, C) ((A) << (C)) -#else - /* We have to do this because the morons at ANSI decided that shifts - * by >= data size are undefined. - */ - #define LSR_32(A, C) ((C) < 32 ? (A) >> (C) : 0) - #define LSL_32(A, C) ((C) < 32 ? (A) << (C) : 0) -#endif /* M68K_INT_GT_32_BIT */ - -#if M68K_USE_64_BIT - #define LSL_32_64(A, C) ((A) << (C)) - #define LSR_32_64(A, C) ((A) >> (C)) - #define ROL_33_64(A, C) (LSL_32_64(A, C) | LSR_32_64(A, 33-(C))) - #define ROR_33_64(A, C) (LSR_32_64(A, C) | LSL_32_64(A, 33-(C))) -#endif /* M68K_USE_64_BIT */ - -#define ROL_8(A, C) MASK_OUT_ABOVE_8(LSL(A, C) | LSR(A, 8-(C))) -#define ROL_9(A, C) (LSL(A, C) | LSR(A, 9-(C))) -#define ROL_16(A, C) MASK_OUT_ABOVE_16(LSL(A, C) | LSR(A, 16-(C))) -#define ROL_17(A, C) (LSL(A, C) | LSR(A, 17-(C))) -#define ROL_32(A, C) MASK_OUT_ABOVE_32(LSL_32(A, C) | LSR_32(A, 32-(C))) -#define ROL_33(A, C) (LSL_32(A, C) | LSR_32(A, 33-(C))) - -#define ROR_8(A, C) MASK_OUT_ABOVE_8(LSR(A, C) | LSL(A, 8-(C))) -#define ROR_9(A, C) (LSR(A, C) | LSL(A, 9-(C))) -#define ROR_16(A, C) MASK_OUT_ABOVE_16(LSR(A, C) | LSL(A, 16-(C))) -#define ROR_17(A, C) (LSR(A, C) | LSL(A, 17-(C))) -#define ROR_32(A, C) MASK_OUT_ABOVE_32(LSR_32(A, C) | LSL_32(A, 32-(C))) -#define ROR_33(A, C) (LSR_32(A, C) | LSL_32(A, 33-(C))) - - - -/* ------------------------------ CPU Access ------------------------------ */ - -/* Access the CPU registers */ -#define CPU_TYPE m68ki_cpu.cpu_type - -#define REG_DA m68ki_cpu.dar /* easy access to data and address regs */ -#define REG_D m68ki_cpu.dar -#define REG_A (m68ki_cpu.dar+8) -#define REG_PPC m68ki_cpu.ppc -#define REG_PC m68ki_cpu.pc -#define REG_SP_BASE m68ki_cpu.sp -#define REG_USP m68ki_cpu.sp[0] -#define REG_ISP m68ki_cpu.sp[4] -#define REG_MSP m68ki_cpu.sp[6] -#define REG_SP m68ki_cpu.dar[15] -#define REG_VBR m68ki_cpu.vbr -#define REG_SFC m68ki_cpu.sfc -#define REG_DFC m68ki_cpu.dfc -#define REG_CACR m68ki_cpu.cacr -#define REG_CAAR m68ki_cpu.caar -#define REG_IR m68ki_cpu.ir - -#define FLAG_T1 m68ki_cpu.t1_flag -#define FLAG_T0 m68ki_cpu.t0_flag -#define FLAG_S m68ki_cpu.s_flag -#define FLAG_M m68ki_cpu.m_flag -#define FLAG_X m68ki_cpu.x_flag -#define FLAG_N m68ki_cpu.n_flag -#define FLAG_Z m68ki_cpu.not_z_flag -#define FLAG_V m68ki_cpu.v_flag -#define FLAG_C m68ki_cpu.c_flag -#define FLAG_INT_MASK m68ki_cpu.int_mask - -#define CPU_INT_LEVEL m68ki_cpu.int_level /* ASG: changed from CPU_INTS_PENDING */ -#define CPU_INT_CYCLES m68ki_cpu.int_cycles /* ASG */ -#define CPU_STOPPED m68ki_cpu.stopped -#define CPU_PREF_ADDR m68ki_cpu.pref_addr -#define CPU_PREF_DATA m68ki_cpu.pref_data -#define CPU_ADDRESS_MASK m68ki_cpu.address_mask -#define CPU_SR_MASK m68ki_cpu.sr_mask -#define CPU_INSTR_MODE m68ki_cpu.instr_mode -#define CPU_RUN_MODE m68ki_cpu.run_mode - -#define CYC_INSTRUCTION m68ki_cpu.cyc_instruction -#define CYC_EXCEPTION m68ki_cpu.cyc_exception -#define CYC_BCC_NOTAKE_B m68ki_cpu.cyc_bcc_notake_b -#define CYC_BCC_NOTAKE_W m68ki_cpu.cyc_bcc_notake_w -#define CYC_DBCC_F_NOEXP m68ki_cpu.cyc_dbcc_f_noexp -#define CYC_DBCC_F_EXP m68ki_cpu.cyc_dbcc_f_exp -#define CYC_SCC_R_FALSE m68ki_cpu.cyc_scc_r_false -#define CYC_MOVEM_W m68ki_cpu.cyc_movem_w -#define CYC_MOVEM_L m68ki_cpu.cyc_movem_l -#define CYC_SHIFT m68ki_cpu.cyc_shift -#define CYC_RESET m68ki_cpu.cyc_reset - - -#define CALLBACK_INT_ACK m68ki_cpu.int_ack_callback -#define CALLBACK_BKPT_ACK m68ki_cpu.bkpt_ack_callback -#define CALLBACK_RESET_INSTR m68ki_cpu.reset_instr_callback -#define CALLBACK_PC_CHANGED m68ki_cpu.pc_changed_callback -#define CALLBACK_SET_FC m68ki_cpu.set_fc_callback -#define CALLBACK_INSTR_HOOK m68ki_cpu.instr_hook_callback - - - -/* ----------------------------- Configuration ---------------------------- */ - -/* These defines are dependant on the configuration defines in m68kconf.h */ - -/* Disable certain comparisons if we're not using all CPU types */ -#if M68K_EMULATE_020 - #define CPU_TYPE_IS_020_PLUS(A) ((A) & CPU_TYPE_020) - #define CPU_TYPE_IS_020_LESS(A) 1 -#else - #define CPU_TYPE_IS_020_PLUS(A) 0 - #define CPU_TYPE_IS_020_LESS(A) 1 -#endif - -#if M68K_EMULATE_EC020 - #define CPU_TYPE_IS_EC020_PLUS(A) ((A) & (CPU_TYPE_EC020 | CPU_TYPE_020)) - #define CPU_TYPE_IS_EC020_LESS(A) ((A) & (CPU_TYPE_000 | CPU_TYPE_010 | CPU_TYPE_EC020)) -#else - #define CPU_TYPE_IS_EC020_PLUS(A) CPU_TYPE_IS_020_PLUS(A) - #define CPU_TYPE_IS_EC020_LESS(A) CPU_TYPE_IS_020_LESS(A) -#endif - -#if M68K_EMULATE_010 - #define CPU_TYPE_IS_010(A) ((A) == CPU_TYPE_010) - #define CPU_TYPE_IS_010_PLUS(A) ((A) & (CPU_TYPE_010 | CPU_TYPE_EC020 | CPU_TYPE_020)) - #define CPU_TYPE_IS_010_LESS(A) ((A) & (CPU_TYPE_000 | CPU_TYPE_010)) -#else - #define CPU_TYPE_IS_010(A) 0 - #define CPU_TYPE_IS_010_PLUS(A) CPU_TYPE_IS_EC020_PLUS(A) - #define CPU_TYPE_IS_010_LESS(A) CPU_TYPE_IS_EC020_LESS(A) -#endif - -#if M68K_EMULATE_020 || M68K_EMULATE_EC020 - #define CPU_TYPE_IS_020_VARIANT(A) ((A) & (CPU_TYPE_EC020 | CPU_TYPE_020)) -#else - #define CPU_TYPE_IS_020_VARIANT(A) 0 -#endif - -#if M68K_EMULATE_020 || M68K_EMULATE_EC020 || M68K_EMULATE_010 - #define CPU_TYPE_IS_000(A) ((A) == CPU_TYPE_000) -#else - #define CPU_TYPE_IS_000(A) 1 -#endif - - -#if !M68K_SEPARATE_READS -#define m68k_read_immediate_16(A) m68ki_read_program_16(A) -#define m68k_read_immediate_32(A) m68ki_read_program_32(A) - -#define m68k_read_pcrelative_8(A) m68ki_read_program_8(A) -#define m68k_read_pcrelative_16(A) m68ki_read_program_16(A) -#define m68k_read_pcrelative_32(A) m68ki_read_program_32(A) -#endif /* M68K_SEPARATE_READS */ - - -/* Enable or disable callback functions */ -#if M68K_EMULATE_INT_ACK - #if M68K_EMULATE_INT_ACK == OPT_SPECIFY_HANDLER - #define m68ki_int_ack(A) M68K_INT_ACK_CALLBACK(A) - #else - #define m68ki_int_ack(A) CALLBACK_INT_ACK(A) - #endif -#else - /* Default action is to used autovector mode, which is most common */ - #define m68ki_int_ack(A) M68K_INT_ACK_AUTOVECTOR -#endif /* M68K_EMULATE_INT_ACK */ - -#if M68K_EMULATE_BKPT_ACK - #if M68K_EMULATE_BKPT_ACK == OPT_SPECIFY_HANDLER - #define m68ki_bkpt_ack(A) M68K_BKPT_ACK_CALLBACK(A) - #else - #define m68ki_bkpt_ack(A) CALLBACK_BKPT_ACK(A) - #endif -#else - #define m68ki_bkpt_ack(A) -#endif /* M68K_EMULATE_BKPT_ACK */ - -#if M68K_EMULATE_RESET - #if M68K_EMULATE_RESET == OPT_SPECIFY_HANDLER - #define m68ki_output_reset() M68K_RESET_CALLBACK() - #else - #define m68ki_output_reset() CALLBACK_RESET_INSTR() - #endif -#else - #define m68ki_output_reset() -#endif /* M68K_EMULATE_RESET */ - -#if M68K_INSTRUCTION_HOOK - #if M68K_INSTRUCTION_HOOK == OPT_SPECIFY_HANDLER - #define m68ki_instr_hook() M68K_INSTRUCTION_CALLBACK() - #else - #define m68ki_instr_hook() CALLBACK_INSTR_HOOK() - #endif -#else - #define m68ki_instr_hook() -#endif /* M68K_INSTRUCTION_HOOK */ - -#if M68K_MONITOR_PC - #if M68K_MONITOR_PC == OPT_SPECIFY_HANDLER - #define m68ki_pc_changed(A) M68K_SET_PC_CALLBACK(ADDRESS_68K(A)) - #else - #define m68ki_pc_changed(A) CALLBACK_PC_CHANGED(ADDRESS_68K(A)) - #endif -#else - #define m68ki_pc_changed(A) -#endif /* M68K_MONITOR_PC */ - - -/* Enable or disable function code emulation */ -#if M68K_EMULATE_FC - #if M68K_EMULATE_FC == OPT_SPECIFY_HANDLER - #define m68ki_set_fc(A) M68K_SET_FC_CALLBACK(A) - #else - #define m68ki_set_fc(A) CALLBACK_SET_FC(A) - #endif - #define m68ki_use_data_space() m68ki_address_space = FUNCTION_CODE_USER_DATA - #define m68ki_use_program_space() m68ki_address_space = FUNCTION_CODE_USER_PROGRAM - #define m68ki_get_address_space() m68ki_address_space -#else - #define m68ki_set_fc(A) - #define m68ki_use_data_space() - #define m68ki_use_program_space() - #define m68ki_get_address_space() FUNCTION_CODE_USER_DATA -#endif /* M68K_EMULATE_FC */ - - -/* Enable or disable trace emulation */ -#if M68K_EMULATE_TRACE - /* Initiates trace checking before each instruction (t1) */ - #define m68ki_trace_t1() m68ki_tracing = FLAG_T1 - /* adds t0 to trace checking if we encounter change of flow */ - #define m68ki_trace_t0() m68ki_tracing |= FLAG_T0 - /* Clear all tracing */ - #define m68ki_clear_trace() m68ki_tracing = 0 - /* Cause a trace exception if we are tracing */ - #define m68ki_exception_if_trace() if(m68ki_tracing) m68ki_exception_trace() -#else - #define m68ki_trace_t1() - #define m68ki_trace_t0() - #define m68ki_clear_trace() - #define m68ki_exception_if_trace() -#endif /* M68K_EMULATE_TRACE */ - - - -/* Address error */ -#if M68K_EMULATE_ADDRESS_ERROR - #include - extern jmp_buf m68ki_aerr_trap; - - #define m68ki_set_address_error_trap() \ - if(setjmp(m68ki_aerr_trap) != 0) \ - { \ - m68ki_exception_address_error(); \ - if(CPU_STOPPED) \ - { \ - SET_CYCLES(0); \ - CPU_INT_CYCLES = 0; \ - return m68ki_initial_cycles; \ - } \ - } - - #define m68ki_check_address_error(ADDR, WRITE_MODE, FC) \ - if((ADDR)&1) \ - { \ - m68ki_aerr_address = ADDR; \ - m68ki_aerr_write_mode = WRITE_MODE; \ - m68ki_aerr_fc = FC; \ - longjmp(m68ki_aerr_trap, 1); \ - } -#else - #define m68ki_set_address_error_trap() - #define m68ki_check_address_error(ADDR, WRITE_MODE, FC) -#endif /* M68K_ADDRESS_ERROR */ - -/* Logging */ -#if M68K_LOG_ENABLE - #include - extern FILE* M68K_LOG_FILEHANDLE - extern char* m68ki_cpu_names[]; - - #define M68K_DO_LOG(A) if(M68K_LOG_FILEHANDLE) fprintf A - #if M68K_LOG_1010_1111 - #define M68K_DO_LOG_EMU(A) if(M68K_LOG_FILEHANDLE) fprintf A - #else - #define M68K_DO_LOG_EMU(A) - #endif -#else - #define M68K_DO_LOG(A) - #define M68K_DO_LOG_EMU(A) -#endif - - - -/* -------------------------- EA / Operand Access ------------------------- */ - -/* - * The general instruction format follows this pattern: - * .... XXX. .... .YYY - * where XXX is register X and YYY is register Y - */ -/* Data Register Isolation */ -#define DX (REG_D[(REG_IR >> 9) & 7]) -#define DY (REG_D[REG_IR & 7]) -/* Address Register Isolation */ -#define AX (REG_A[(REG_IR >> 9) & 7]) -#define AY (REG_A[REG_IR & 7]) - - -/* Effective Address Calculations */ -#define EA_AY_AI_8() AY /* address register indirect */ -#define EA_AY_AI_16() EA_AY_AI_8() -#define EA_AY_AI_32() EA_AY_AI_8() -#define EA_AY_PI_8() (AY++) /* postincrement (size = byte) */ -#define EA_AY_PI_16() ((AY+=2)-2) /* postincrement (size = word) */ -#define EA_AY_PI_32() ((AY+=4)-4) /* postincrement (size = long) */ -#define EA_AY_PD_8() (--AY) /* predecrement (size = byte) */ -#define EA_AY_PD_16() (AY-=2) /* predecrement (size = word) */ -#define EA_AY_PD_32() (AY-=4) /* predecrement (size = long) */ -#define EA_AY_DI_8() (AY+MAKE_INT_16(m68ki_read_imm_16())) /* displacement */ -#define EA_AY_DI_16() EA_AY_DI_8() -#define EA_AY_DI_32() EA_AY_DI_8() -#define EA_AY_IX_8() m68ki_get_ea_ix(AY) /* indirect + index */ -#define EA_AY_IX_16() EA_AY_IX_8() -#define EA_AY_IX_32() EA_AY_IX_8() - -#define EA_AX_AI_8() AX -#define EA_AX_AI_16() EA_AX_AI_8() -#define EA_AX_AI_32() EA_AX_AI_8() -#define EA_AX_PI_8() (AX++) -#define EA_AX_PI_16() ((AX+=2)-2) -#define EA_AX_PI_32() ((AX+=4)-4) -#define EA_AX_PD_8() (--AX) -#define EA_AX_PD_16() (AX-=2) -#define EA_AX_PD_32() (AX-=4) -#define EA_AX_DI_8() (AX+MAKE_INT_16(m68ki_read_imm_16())) -#define EA_AX_DI_16() EA_AX_DI_8() -#define EA_AX_DI_32() EA_AX_DI_8() -#define EA_AX_IX_8() m68ki_get_ea_ix(AX) -#define EA_AX_IX_16() EA_AX_IX_8() -#define EA_AX_IX_32() EA_AX_IX_8() - -#define EA_A7_PI_8() ((REG_A[7]+=2)-2) -#define EA_A7_PD_8() (REG_A[7]-=2) - -#define EA_AW_8() MAKE_INT_16(m68ki_read_imm_16()) /* absolute word */ -#define EA_AW_16() EA_AW_8() -#define EA_AW_32() EA_AW_8() -#define EA_AL_8() m68ki_read_imm_32() /* absolute long */ -#define EA_AL_16() EA_AL_8() -#define EA_AL_32() EA_AL_8() -#define EA_PCDI_8() m68ki_get_ea_pcdi() /* pc indirect + displacement */ -#define EA_PCDI_16() EA_PCDI_8() -#define EA_PCDI_32() EA_PCDI_8() -#define EA_PCIX_8() m68ki_get_ea_pcix() /* pc indirect + index */ -#define EA_PCIX_16() EA_PCIX_8() -#define EA_PCIX_32() EA_PCIX_8() - - -#define OPER_I_8() m68ki_read_imm_8() -#define OPER_I_16() m68ki_read_imm_16() -#define OPER_I_32() m68ki_read_imm_32() - - - -/* --------------------------- Status Register ---------------------------- */ - -/* Flag Calculation Macros */ -#define CFLAG_8(A) (A) -#define CFLAG_16(A) ((A)>>8) - -#if M68K_INT_GT_32_BIT - #define CFLAG_ADD_32(S, D, R) ((R)>>24) - #define CFLAG_SUB_32(S, D, R) ((R)>>24) -#else - #define CFLAG_ADD_32(S, D, R) (((S & D) | (~R & (S | D)))>>23) - #define CFLAG_SUB_32(S, D, R) (((S & R) | (~D & (S | R)))>>23) -#endif /* M68K_INT_GT_32_BIT */ - -#define VFLAG_ADD_8(S, D, R) ((S^R) & (D^R)) -#define VFLAG_ADD_16(S, D, R) (((S^R) & (D^R))>>8) -#define VFLAG_ADD_32(S, D, R) (((S^R) & (D^R))>>24) - -#define VFLAG_SUB_8(S, D, R) ((S^D) & (R^D)) -#define VFLAG_SUB_16(S, D, R) (((S^D) & (R^D))>>8) -#define VFLAG_SUB_32(S, D, R) (((S^D) & (R^D))>>24) - -#define NFLAG_8(A) (A) -#define NFLAG_16(A) ((A)>>8) -#define NFLAG_32(A) ((A)>>24) -#define NFLAG_64(A) ((A)>>56) - -#define ZFLAG_8(A) MASK_OUT_ABOVE_8(A) -#define ZFLAG_16(A) MASK_OUT_ABOVE_16(A) -#define ZFLAG_32(A) MASK_OUT_ABOVE_32(A) - - -/* Flag values */ -#define NFLAG_SET 0x80 -#define NFLAG_CLEAR 0 -#define CFLAG_SET 0x100 -#define CFLAG_CLEAR 0 -#define XFLAG_SET 0x100 -#define XFLAG_CLEAR 0 -#define VFLAG_SET 0x80 -#define VFLAG_CLEAR 0 -#define ZFLAG_SET 0 -#define ZFLAG_CLEAR 0xffffffff - -#define SFLAG_SET 4 -#define SFLAG_CLEAR 0 -#define MFLAG_SET 2 -#define MFLAG_CLEAR 0 - -/* Turn flag values into 1 or 0 */ -#define XFLAG_AS_1() ((FLAG_X>>8)&1) -#define NFLAG_AS_1() ((FLAG_N>>7)&1) -#define VFLAG_AS_1() ((FLAG_V>>7)&1) -#define ZFLAG_AS_1() (!FLAG_Z) -#define CFLAG_AS_1() ((FLAG_C>>8)&1) - - -/* Conditions */ -#define COND_CS() (FLAG_C&0x100) -#define COND_CC() (!COND_CS()) -#define COND_VS() (FLAG_V&0x80) -#define COND_VC() (!COND_VS()) -#define COND_NE() FLAG_Z -#define COND_EQ() (!COND_NE()) -#define COND_MI() (FLAG_N&0x80) -#define COND_PL() (!COND_MI()) -#define COND_LT() ((FLAG_N^FLAG_V)&0x80) -#define COND_GE() (!COND_LT()) -#define COND_HI() (COND_CC() && COND_NE()) -#define COND_LS() (COND_CS() || COND_EQ()) -#define COND_GT() (COND_GE() && COND_NE()) -#define COND_LE() (COND_LT() || COND_EQ()) - -/* Reversed conditions */ -#define COND_NOT_CS() COND_CC() -#define COND_NOT_CC() COND_CS() -#define COND_NOT_VS() COND_VC() -#define COND_NOT_VC() COND_VS() -#define COND_NOT_NE() COND_EQ() -#define COND_NOT_EQ() COND_NE() -#define COND_NOT_MI() COND_PL() -#define COND_NOT_PL() COND_MI() -#define COND_NOT_LT() COND_GE() -#define COND_NOT_GE() COND_LT() -#define COND_NOT_HI() COND_LS() -#define COND_NOT_LS() COND_HI() -#define COND_NOT_GT() COND_LE() -#define COND_NOT_LE() COND_GT() - -/* Not real conditions, but here for convenience */ -#define COND_XS() (FLAG_X&0x100) -#define COND_XC() (!COND_XS) - - -/* Get the condition code register */ -#define m68ki_get_ccr() ((COND_XS() >> 4) | \ - (COND_MI() >> 4) | \ - (COND_EQ() << 2) | \ - (COND_VS() >> 6) | \ - (COND_CS() >> 8)) - -/* Get the status register */ -#define m68ki_get_sr() ( FLAG_T1 | \ - FLAG_T0 | \ - (FLAG_S << 11) | \ - (FLAG_M << 11) | \ - FLAG_INT_MASK | \ - m68ki_get_ccr()) - - - -/* ---------------------------- Cycle Counting ---------------------------- */ - -#define ADD_CYCLES(A) m68ki_remaining_cycles += (A) -#define USE_CYCLES(A) m68ki_remaining_cycles -= (A) -#define SET_CYCLES(A) m68ki_remaining_cycles = A -#define GET_CYCLES() m68ki_remaining_cycles -#define USE_ALL_CYCLES() m68ki_remaining_cycles = 0 - - - -/* ----------------------------- Read / Write ----------------------------- */ - -/* Read from the current address space */ -#define m68ki_read_8(A) m68ki_read_8_fc (A, FLAG_S | m68ki_get_address_space()) -#define m68ki_read_16(A) m68ki_read_16_fc(A, FLAG_S | m68ki_get_address_space()) -#define m68ki_read_32(A) m68ki_read_32_fc(A, FLAG_S | m68ki_get_address_space()) - -/* Write to the current data space */ -#define m68ki_write_8(A, V) m68ki_write_8_fc (A, FLAG_S | FUNCTION_CODE_USER_DATA, V) -#define m68ki_write_16(A, V) m68ki_write_16_fc(A, FLAG_S | FUNCTION_CODE_USER_DATA, V) -#define m68ki_write_32(A, V) m68ki_write_32_fc(A, FLAG_S | FUNCTION_CODE_USER_DATA, V) - -#if M68K_SIMULATE_PD_WRITES -#define m68ki_write_32_pd(A, V) m68ki_write_32_pd_fc(A, FLAG_S | FUNCTION_CODE_USER_DATA, V) -#else -#define m68ki_write_32_pd(A, V) m68ki_write_32_fc(A, FLAG_S | FUNCTION_CODE_USER_DATA, V) -#endif - -/* map read immediate 8 to read immediate 16 */ -#define m68ki_read_imm_8() MASK_OUT_ABOVE_8(m68ki_read_imm_16()) - -/* Map PC-relative reads */ -#define m68ki_read_pcrel_8(A) m68k_read_pcrelative_8(A) -#define m68ki_read_pcrel_16(A) m68k_read_pcrelative_16(A) -#define m68ki_read_pcrel_32(A) m68k_read_pcrelative_32(A) - -/* Read from the program space */ -#define m68ki_read_program_8(A) m68ki_read_8_fc(A, FLAG_S | FUNCTION_CODE_USER_PROGRAM) -#define m68ki_read_program_16(A) m68ki_read_16_fc(A, FLAG_S | FUNCTION_CODE_USER_PROGRAM) -#define m68ki_read_program_32(A) m68ki_read_32_fc(A, FLAG_S | FUNCTION_CODE_USER_PROGRAM) - -/* Read from the data space */ -#define m68ki_read_data_8(A) m68ki_read_8_fc(A, FLAG_S | FUNCTION_CODE_USER_DATA) -#define m68ki_read_data_16(A) m68ki_read_16_fc(A, FLAG_S | FUNCTION_CODE_USER_DATA) -#define m68ki_read_data_32(A) m68ki_read_32_fc(A, FLAG_S | FUNCTION_CODE_USER_DATA) - - - -/* ======================================================================== */ -/* =============================== PROTOTYPES ============================= */ -/* ======================================================================== */ - -typedef struct -{ - uint cpu_type; /* CPU Type: 68000, 68010, 68EC020, or 68020 */ - uint dar[16]; /* Data and Address Registers */ - uint ppc; /* Previous program counter */ - uint pc; /* Program Counter */ - uint sp[7]; /* User, Interrupt, and Master Stack Pointers */ - uint vbr; /* Vector Base Register (m68010+) */ - uint sfc; /* Source Function Code Register (m68010+) */ - uint dfc; /* Destination Function Code Register (m68010+) */ - uint cacr; /* Cache Control Register (m68020, unemulated) */ - uint caar; /* Cache Address Register (m68020, unemulated) */ - uint ir; /* Instruction Register */ - uint t1_flag; /* Trace 1 */ - uint t0_flag; /* Trace 0 */ - uint s_flag; /* Supervisor */ - uint m_flag; /* Master/Interrupt state */ - uint x_flag; /* Extend */ - uint n_flag; /* Negative */ - uint not_z_flag; /* Zero, inverted for speedups */ - uint v_flag; /* Overflow */ - uint c_flag; /* Carry */ - uint int_mask; /* I0-I2 */ - uint int_level; /* State of interrupt pins IPL0-IPL2 -- ASG: changed from ints_pending */ - uint int_cycles; /* ASG: extra cycles from generated interrupts */ - uint stopped; /* Stopped state */ - uint pref_addr; /* Last prefetch address */ - uint pref_data; /* Data in the prefetch queue */ - uint address_mask; /* Available address pins */ - uint sr_mask; /* Implemented status register bits */ - uint instr_mode; /* Stores whether we are in instruction mode or group 0/1 exception mode */ - uint run_mode; /* Stores whether we are processing a reset, bus error, address error, or something else */ - - /* Clocks required for instructions / exceptions */ - uint cyc_bcc_notake_b; - uint cyc_bcc_notake_w; - uint cyc_dbcc_f_noexp; - uint cyc_dbcc_f_exp; - uint cyc_scc_r_false; - uint cyc_movem_w; - uint cyc_movem_l; - uint cyc_shift; - uint cyc_reset; - uint8* cyc_instruction; - uint8* cyc_exception; - - /* Callbacks to host */ - int (*int_ack_callback)(int int_line); /* Interrupt Acknowledge */ - void (*bkpt_ack_callback)(unsigned int data); /* Breakpoint Acknowledge */ - void (*reset_instr_callback)(void); /* Called when a RESET instruction is encountered */ - void (*pc_changed_callback)(unsigned int new_pc); /* Called when the PC changes by a large amount */ - void (*set_fc_callback)(unsigned int new_fc); /* Called when the CPU function code changes */ - void (*instr_hook_callback)(void); /* Called every instruction cycle prior to execution */ - -} m68ki_cpu_core; - - -extern m68ki_cpu_core m68ki_cpu; -extern sint m68ki_remaining_cycles; -extern uint m68ki_tracing; -extern uint8 m68ki_shift_8_table[]; -extern uint16 m68ki_shift_16_table[]; -extern uint m68ki_shift_32_table[]; -extern uint8 m68ki_exception_cycle_table[][256]; -extern uint m68ki_address_space; -extern uint8 m68ki_ea_idx_cycle_table[]; - -extern uint m68ki_aerr_address; -extern uint m68ki_aerr_write_mode; -extern uint m68ki_aerr_fc; - -/* Read data immediately after the program counter */ -INLINE uint m68ki_read_imm_16(void); -INLINE uint m68ki_read_imm_32(void); - -/* Read data with specific function code */ -INLINE uint m68ki_read_8_fc (uint address, uint fc); -INLINE uint m68ki_read_16_fc (uint address, uint fc); -INLINE uint m68ki_read_32_fc (uint address, uint fc); - -/* Write data with specific function code */ -INLINE void m68ki_write_8_fc (uint address, uint fc, uint value); -INLINE void m68ki_write_16_fc(uint address, uint fc, uint value); -INLINE void m68ki_write_32_fc(uint address, uint fc, uint value); -#if M68K_SIMULATE_PD_WRITES -INLINE void m68ki_write_32_pd_fc(uint address, uint fc, uint value); -#endif /* M68K_SIMULATE_PD_WRITES */ - -/* Indexed and PC-relative ea fetching */ -INLINE uint m68ki_get_ea_pcdi(void); -INLINE uint m68ki_get_ea_pcix(void); -INLINE uint m68ki_get_ea_ix(uint An); - -/* Operand fetching */ -INLINE uint OPER_AY_AI_8(void); -INLINE uint OPER_AY_AI_16(void); -INLINE uint OPER_AY_AI_32(void); -INLINE uint OPER_AY_PI_8(void); -INLINE uint OPER_AY_PI_16(void); -INLINE uint OPER_AY_PI_32(void); -INLINE uint OPER_AY_PD_8(void); -INLINE uint OPER_AY_PD_16(void); -INLINE uint OPER_AY_PD_32(void); -INLINE uint OPER_AY_DI_8(void); -INLINE uint OPER_AY_DI_16(void); -INLINE uint OPER_AY_DI_32(void); -INLINE uint OPER_AY_IX_8(void); -INLINE uint OPER_AY_IX_16(void); -INLINE uint OPER_AY_IX_32(void); - -INLINE uint OPER_AX_AI_8(void); -INLINE uint OPER_AX_AI_16(void); -INLINE uint OPER_AX_AI_32(void); -INLINE uint OPER_AX_PI_8(void); -INLINE uint OPER_AX_PI_16(void); -INLINE uint OPER_AX_PI_32(void); -INLINE uint OPER_AX_PD_8(void); -INLINE uint OPER_AX_PD_16(void); -INLINE uint OPER_AX_PD_32(void); -INLINE uint OPER_AX_DI_8(void); -INLINE uint OPER_AX_DI_16(void); -INLINE uint OPER_AX_DI_32(void); -INLINE uint OPER_AX_IX_8(void); -INLINE uint OPER_AX_IX_16(void); -INLINE uint OPER_AX_IX_32(void); - -INLINE uint OPER_A7_PI_8(void); -INLINE uint OPER_A7_PD_8(void); - -INLINE uint OPER_AW_8(void); -INLINE uint OPER_AW_16(void); -INLINE uint OPER_AW_32(void); -INLINE uint OPER_AL_8(void); -INLINE uint OPER_AL_16(void); -INLINE uint OPER_AL_32(void); -INLINE uint OPER_PCDI_8(void); -INLINE uint OPER_PCDI_16(void); -INLINE uint OPER_PCDI_32(void); -INLINE uint OPER_PCIX_8(void); -INLINE uint OPER_PCIX_16(void); -INLINE uint OPER_PCIX_32(void); - -/* Stack operations */ -INLINE void m68ki_push_16(uint value); -INLINE void m68ki_push_32(uint value); -INLINE uint m68ki_pull_16(void); -INLINE uint m68ki_pull_32(void); - -/* Program flow operations */ -INLINE void m68ki_jump(uint new_pc); -INLINE void m68ki_jump_vector(uint vector); -INLINE void m68ki_branch_8(uint offset); -INLINE void m68ki_branch_16(uint offset); -INLINE void m68ki_branch_32(uint offset); - -/* Status register operations. */ -INLINE void m68ki_set_s_flag(uint value); /* Only bit 2 of value should be set (i.e. 4 or 0) */ -INLINE void m68ki_set_sm_flag(uint value); /* only bits 1 and 2 of value should be set */ -INLINE void m68ki_set_ccr(uint value); /* set the condition code register */ -INLINE void m68ki_set_sr(uint value); /* set the status register */ -INLINE void m68ki_set_sr_noint(uint value); /* set the status register */ - -/* Exception processing */ -INLINE uint m68ki_init_exception(void); /* Initial exception processing */ - -INLINE void m68ki_stack_frame_3word(uint pc, uint sr); /* Stack various frame types */ -INLINE void m68ki_stack_frame_buserr(uint sr); - -INLINE void m68ki_stack_frame_0000(uint pc, uint sr, uint vector); -INLINE void m68ki_stack_frame_0001(uint pc, uint sr, uint vector); -INLINE void m68ki_stack_frame_0010(uint sr, uint vector); -INLINE void m68ki_stack_frame_1000(uint pc, uint sr, uint vector); -INLINE void m68ki_stack_frame_1010(uint sr, uint vector, uint pc); -INLINE void m68ki_stack_frame_1011(uint sr, uint vector, uint pc); - -INLINE void m68ki_exception_trap(uint vector); -INLINE void m68ki_exception_trapN(uint vector); -INLINE void m68ki_exception_trace(void); -INLINE void m68ki_exception_privilege_violation(void); -INLINE void m68ki_exception_1010(void); -INLINE void m68ki_exception_1111(void); -INLINE void m68ki_exception_illegal(void); -INLINE void m68ki_exception_format_error(void); -INLINE void m68ki_exception_address_error(void); -INLINE void m68ki_exception_interrupt(uint int_level); -INLINE void m68ki_check_interrupts(void); /* ASG: check for interrupts */ - -/* quick disassembly (used for logging) */ -char* m68ki_disassemble_quick(unsigned int pc, unsigned int cpu_type); - - -/* ======================================================================== */ -/* =========================== UTILITY FUNCTIONS ========================== */ -/* ======================================================================== */ - - -/* ---------------------------- Read Immediate ---------------------------- */ - -/* Handles all immediate reads, does address error check, function code setting, - * and prefetching if they are enabled in m68kconf.h - */ -INLINE uint m68ki_read_imm_16(void) -{ - m68ki_set_fc(FLAG_S | FUNCTION_CODE_USER_PROGRAM); /* auto-disable (see m68kcpu.h) */ - m68ki_check_address_error(REG_PC, MODE_READ, FLAG_S | FUNCTION_CODE_USER_PROGRAM); /* auto-disable (see m68kcpu.h) */ -#if M68K_EMULATE_PREFETCH - if(MASK_OUT_BELOW_2(REG_PC) != CPU_PREF_ADDR) - { - CPU_PREF_ADDR = MASK_OUT_BELOW_2(REG_PC); - CPU_PREF_DATA = m68k_read_immediate_32(ADDRESS_68K(CPU_PREF_ADDR)); - } - REG_PC += 2; - return MASK_OUT_ABOVE_16(CPU_PREF_DATA >> ((2-((REG_PC-2)&2))<<3)); -#else - REG_PC += 2; - return m68k_read_immediate_16(ADDRESS_68K(REG_PC-2)); -#endif /* M68K_EMULATE_PREFETCH */ -} -INLINE uint m68ki_read_imm_32(void) -{ -#if M68K_EMULATE_PREFETCH - uint temp_val; - - m68ki_set_fc(FLAG_S | FUNCTION_CODE_USER_PROGRAM); /* auto-disable (see m68kcpu.h) */ - m68ki_check_address_error(REG_PC, MODE_READ, FLAG_S | FUNCTION_CODE_USER_PROGRAM); /* auto-disable (see m68kcpu.h) */ - if(MASK_OUT_BELOW_2(REG_PC) != CPU_PREF_ADDR) - { - CPU_PREF_ADDR = MASK_OUT_BELOW_2(REG_PC); - CPU_PREF_DATA = m68k_read_immediate_32(ADDRESS_68K(CPU_PREF_ADDR)); - } - temp_val = CPU_PREF_DATA; - REG_PC += 2; - if(MASK_OUT_BELOW_2(REG_PC) != CPU_PREF_ADDR) - { - CPU_PREF_ADDR = MASK_OUT_BELOW_2(REG_PC); - CPU_PREF_DATA = m68k_read_immediate_32(ADDRESS_68K(CPU_PREF_ADDR)); - temp_val = MASK_OUT_ABOVE_32((temp_val << 16) | (CPU_PREF_DATA >> 16)); - } - REG_PC += 2; - - return temp_val; -#else - m68ki_set_fc(FLAG_S | FUNCTION_CODE_USER_PROGRAM); /* auto-disable (see m68kcpu.h) */ - m68ki_check_address_error(REG_PC, MODE_READ, FLAG_S | FUNCTION_CODE_USER_PROGRAM); /* auto-disable (see m68kcpu.h) */ - REG_PC += 4; - return m68k_read_immediate_32(ADDRESS_68K(REG_PC-4)); -#endif /* M68K_EMULATE_PREFETCH */ -} - - - -/* ------------------------- Top level read/write ------------------------- */ - -/* Handles all memory accesses (except for immediate reads if they are - * configured to use separate functions in m68kconf.h). - * All memory accesses must go through these top level functions. - * These functions will also check for address error and set the function - * code if they are enabled in m68kconf.h. - */ -INLINE uint m68ki_read_8_fc(uint address, uint fc) -{ - m68ki_set_fc(fc); /* auto-disable (see m68kcpu.h) */ - return m68k_read_memory_8(ADDRESS_68K(address)); -} -INLINE uint m68ki_read_16_fc(uint address, uint fc) -{ - m68ki_set_fc(fc); /* auto-disable (see m68kcpu.h) */ - m68ki_check_address_error(address, MODE_READ, fc); /* auto-disable (see m68kcpu.h) */ - return m68k_read_memory_16(ADDRESS_68K(address)); -} -INLINE uint m68ki_read_32_fc(uint address, uint fc) -{ - m68ki_set_fc(fc); /* auto-disable (see m68kcpu.h) */ - m68ki_check_address_error(address, MODE_READ, fc); /* auto-disable (see m68kcpu.h) */ - return m68k_read_memory_32(ADDRESS_68K(address)); -} - -INLINE void m68ki_write_8_fc(uint address, uint fc, uint value) -{ - m68ki_set_fc(fc); /* auto-disable (see m68kcpu.h) */ - m68k_write_memory_8(ADDRESS_68K(address), value); -} -INLINE void m68ki_write_16_fc(uint address, uint fc, uint value) -{ - m68ki_set_fc(fc); /* auto-disable (see m68kcpu.h) */ - m68ki_check_address_error(address, MODE_WRITE, fc); /* auto-disable (see m68kcpu.h) */ - m68k_write_memory_16(ADDRESS_68K(address), value); -} -INLINE void m68ki_write_32_fc(uint address, uint fc, uint value) -{ - m68ki_set_fc(fc); /* auto-disable (see m68kcpu.h) */ - m68ki_check_address_error(address, MODE_WRITE, fc); /* auto-disable (see m68kcpu.h) */ - m68k_write_memory_32(ADDRESS_68K(address), value); -} - -#if M68K_SIMULATE_PD_WRITES -INLINE void m68ki_write_32_pd_fc(uint address, uint fc, uint value) -{ - m68ki_set_fc(fc); /* auto-disable (see m68kcpu.h) */ - m68ki_check_address_error(address, MODE_WRITE, fc); /* auto-disable (see m68kcpu.h) */ - m68k_write_memory_32_pd(ADDRESS_68K(address), value); -} -#endif - - -/* --------------------- Effective Address Calculation -------------------- */ - -/* The program counter relative addressing modes cause operands to be - * retrieved from program space, not data space. - */ -INLINE uint m68ki_get_ea_pcdi(void) -{ - uint old_pc = REG_PC; - m68ki_use_program_space(); /* auto-disable */ - return old_pc + MAKE_INT_16(m68ki_read_imm_16()); -} - - -INLINE uint m68ki_get_ea_pcix(void) -{ - m68ki_use_program_space(); /* auto-disable */ - return m68ki_get_ea_ix(REG_PC); -} - -/* Indexed addressing modes are encoded as follows: - * - * Base instruction format: - * F E D C B A 9 8 7 6 | 5 4 3 | 2 1 0 - * x x x x x x x x x x | 1 1 0 | BASE REGISTER (An) - * - * Base instruction format for destination EA in move instructions: - * F E D C | B A 9 | 8 7 6 | 5 4 3 2 1 0 - * x x x x | BASE REG | 1 1 0 | X X X X X X (An) - * - * Brief extension format: - * F | E D C | B | A 9 | 8 | 7 6 5 4 3 2 1 0 - * D/A | REGISTER | W/L | SCALE | 0 | DISPLACEMENT - * - * Full extension format: - * F E D C B A 9 8 7 6 5 4 3 2 1 0 - * D/A | REGISTER | W/L | SCALE | 1 | BS | IS | BD SIZE | 0 | I/IS - * BASE DISPLACEMENT (0, 16, 32 bit) (bd) - * OUTER DISPLACEMENT (0, 16, 32 bit) (od) - * - * D/A: 0 = Dn, 1 = An (Xn) - * W/L: 0 = W (sign extend), 1 = L (.SIZE) - * SCALE: 00=1, 01=2, 10=4, 11=8 (*SCALE) - * BS: 0=add base reg, 1=suppress base reg (An suppressed) - * IS: 0=add index, 1=suppress index (Xn suppressed) - * BD SIZE: 00=reserved, 01=NULL, 10=Word, 11=Long (size of bd) - * - * IS I/IS Operation - * 0 000 No Memory Indirect - * 0 001 indir prex with null outer - * 0 010 indir prex with word outer - * 0 011 indir prex with long outer - * 0 100 reserved - * 0 101 indir postx with null outer - * 0 110 indir postx with word outer - * 0 111 indir postx with long outer - * 1 000 no memory indirect - * 1 001 mem indir with null outer - * 1 010 mem indir with word outer - * 1 011 mem indir with long outer - * 1 100-111 reserved - */ -INLINE uint m68ki_get_ea_ix(uint An) -{ - /* An = base register */ - uint extension = m68ki_read_imm_16(); - uint Xn = 0; /* Index register */ - uint bd = 0; /* Base Displacement */ - uint od = 0; /* Outer Displacement */ - - if(CPU_TYPE_IS_010_LESS(CPU_TYPE)) - { - /* Calculate index */ - Xn = REG_DA[extension>>12]; /* Xn */ - if(!BIT_B(extension)) /* W/L */ - Xn = MAKE_INT_16(Xn); - - /* Add base register and displacement and return */ - return An + Xn + MAKE_INT_8(extension); - } - - /* Brief extension format */ - if(!BIT_8(extension)) - { - /* Calculate index */ - Xn = REG_DA[extension>>12]; /* Xn */ - if(!BIT_B(extension)) /* W/L */ - Xn = MAKE_INT_16(Xn); - /* Add scale if proper CPU type */ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - Xn <<= (extension>>9) & 3; /* SCALE */ - - /* Add base register and displacement and return */ - return An + Xn + MAKE_INT_8(extension); - } - - /* Full extension format */ - - USE_CYCLES(m68ki_ea_idx_cycle_table[extension&0x3f]); - - /* Check if base register is present */ - if(BIT_7(extension)) /* BS */ - An = 0; /* An */ - - /* Check if index is present */ - if(!BIT_6(extension)) /* IS */ - { - Xn = REG_DA[extension>>12]; /* Xn */ - if(!BIT_B(extension)) /* W/L */ - Xn = MAKE_INT_16(Xn); - Xn <<= (extension>>9) & 3; /* SCALE */ - } - - /* Check if base displacement is present */ - if(BIT_5(extension)) /* BD SIZE */ - bd = BIT_4(extension) ? m68ki_read_imm_32() : MAKE_INT_16(m68ki_read_imm_16()); - - /* If no indirect action, we are done */ - if(!(extension&7)) /* No Memory Indirect */ - return An + bd + Xn; - - /* Check if outer displacement is present */ - if(BIT_1(extension)) /* I/IS: od */ - od = BIT_0(extension) ? m68ki_read_imm_32() : MAKE_INT_16(m68ki_read_imm_16()); - - /* Postindex */ - if(BIT_2(extension)) /* I/IS: 0 = preindex, 1 = postindex */ - return m68ki_read_32(An + bd) + Xn + od; - - /* Preindex */ - return m68ki_read_32(An + bd + Xn) + od; -} - - -/* Fetch operands */ -INLINE uint OPER_AY_AI_8(void) {uint ea = EA_AY_AI_8(); return m68ki_read_8(ea); } -INLINE uint OPER_AY_AI_16(void) {uint ea = EA_AY_AI_16(); return m68ki_read_16(ea);} -INLINE uint OPER_AY_AI_32(void) {uint ea = EA_AY_AI_32(); return m68ki_read_32(ea);} -INLINE uint OPER_AY_PI_8(void) {uint ea = EA_AY_PI_8(); return m68ki_read_8(ea); } -INLINE uint OPER_AY_PI_16(void) {uint ea = EA_AY_PI_16(); return m68ki_read_16(ea);} -INLINE uint OPER_AY_PI_32(void) {uint ea = EA_AY_PI_32(); return m68ki_read_32(ea);} -INLINE uint OPER_AY_PD_8(void) {uint ea = EA_AY_PD_8(); return m68ki_read_8(ea); } -INLINE uint OPER_AY_PD_16(void) {uint ea = EA_AY_PD_16(); return m68ki_read_16(ea);} -INLINE uint OPER_AY_PD_32(void) {uint ea = EA_AY_PD_32(); return m68ki_read_32(ea);} -INLINE uint OPER_AY_DI_8(void) {uint ea = EA_AY_DI_8(); return m68ki_read_8(ea); } -INLINE uint OPER_AY_DI_16(void) {uint ea = EA_AY_DI_16(); return m68ki_read_16(ea);} -INLINE uint OPER_AY_DI_32(void) {uint ea = EA_AY_DI_32(); return m68ki_read_32(ea);} -INLINE uint OPER_AY_IX_8(void) {uint ea = EA_AY_IX_8(); return m68ki_read_8(ea); } -INLINE uint OPER_AY_IX_16(void) {uint ea = EA_AY_IX_16(); return m68ki_read_16(ea);} -INLINE uint OPER_AY_IX_32(void) {uint ea = EA_AY_IX_32(); return m68ki_read_32(ea);} - -INLINE uint OPER_AX_AI_8(void) {uint ea = EA_AX_AI_8(); return m68ki_read_8(ea); } -INLINE uint OPER_AX_AI_16(void) {uint ea = EA_AX_AI_16(); return m68ki_read_16(ea);} -INLINE uint OPER_AX_AI_32(void) {uint ea = EA_AX_AI_32(); return m68ki_read_32(ea);} -INLINE uint OPER_AX_PI_8(void) {uint ea = EA_AX_PI_8(); return m68ki_read_8(ea); } -INLINE uint OPER_AX_PI_16(void) {uint ea = EA_AX_PI_16(); return m68ki_read_16(ea);} -INLINE uint OPER_AX_PI_32(void) {uint ea = EA_AX_PI_32(); return m68ki_read_32(ea);} -INLINE uint OPER_AX_PD_8(void) {uint ea = EA_AX_PD_8(); return m68ki_read_8(ea); } -INLINE uint OPER_AX_PD_16(void) {uint ea = EA_AX_PD_16(); return m68ki_read_16(ea);} -INLINE uint OPER_AX_PD_32(void) {uint ea = EA_AX_PD_32(); return m68ki_read_32(ea);} -INLINE uint OPER_AX_DI_8(void) {uint ea = EA_AX_DI_8(); return m68ki_read_8(ea); } -INLINE uint OPER_AX_DI_16(void) {uint ea = EA_AX_DI_16(); return m68ki_read_16(ea);} -INLINE uint OPER_AX_DI_32(void) {uint ea = EA_AX_DI_32(); return m68ki_read_32(ea);} -INLINE uint OPER_AX_IX_8(void) {uint ea = EA_AX_IX_8(); return m68ki_read_8(ea); } -INLINE uint OPER_AX_IX_16(void) {uint ea = EA_AX_IX_16(); return m68ki_read_16(ea);} -INLINE uint OPER_AX_IX_32(void) {uint ea = EA_AX_IX_32(); return m68ki_read_32(ea);} - -INLINE uint OPER_A7_PI_8(void) {uint ea = EA_A7_PI_8(); return m68ki_read_8(ea); } -INLINE uint OPER_A7_PD_8(void) {uint ea = EA_A7_PD_8(); return m68ki_read_8(ea); } - -INLINE uint OPER_AW_8(void) {uint ea = EA_AW_8(); return m68ki_read_8(ea); } -INLINE uint OPER_AW_16(void) {uint ea = EA_AW_16(); return m68ki_read_16(ea);} -INLINE uint OPER_AW_32(void) {uint ea = EA_AW_32(); return m68ki_read_32(ea);} -INLINE uint OPER_AL_8(void) {uint ea = EA_AL_8(); return m68ki_read_8(ea); } -INLINE uint OPER_AL_16(void) {uint ea = EA_AL_16(); return m68ki_read_16(ea);} -INLINE uint OPER_AL_32(void) {uint ea = EA_AL_32(); return m68ki_read_32(ea);} -INLINE uint OPER_PCDI_8(void) {uint ea = EA_PCDI_8(); return m68ki_read_pcrel_8(ea); } -INLINE uint OPER_PCDI_16(void) {uint ea = EA_PCDI_16(); return m68ki_read_pcrel_16(ea);} -INLINE uint OPER_PCDI_32(void) {uint ea = EA_PCDI_32(); return m68ki_read_pcrel_32(ea);} -INLINE uint OPER_PCIX_8(void) {uint ea = EA_PCIX_8(); return m68ki_read_pcrel_8(ea); } -INLINE uint OPER_PCIX_16(void) {uint ea = EA_PCIX_16(); return m68ki_read_pcrel_16(ea);} -INLINE uint OPER_PCIX_32(void) {uint ea = EA_PCIX_32(); return m68ki_read_pcrel_32(ea);} - - - -/* ---------------------------- Stack Functions --------------------------- */ - -/* Push/pull data from the stack */ -INLINE void m68ki_push_16(uint value) -{ - REG_SP = MASK_OUT_ABOVE_32(REG_SP - 2); - m68ki_write_16(REG_SP, value); -} - -INLINE void m68ki_push_32(uint value) -{ - REG_SP = MASK_OUT_ABOVE_32(REG_SP - 4); - m68ki_write_32(REG_SP, value); -} - -INLINE uint m68ki_pull_16(void) -{ - REG_SP = MASK_OUT_ABOVE_32(REG_SP + 2); - return m68ki_read_16(REG_SP-2); -} - -INLINE uint m68ki_pull_32(void) -{ - REG_SP = MASK_OUT_ABOVE_32(REG_SP + 4); - return m68ki_read_32(REG_SP-4); -} - - -/* Increment/decrement the stack as if doing a push/pull but - * don't do any memory access. - */ -INLINE void m68ki_fake_push_16(void) -{ - REG_SP = MASK_OUT_ABOVE_32(REG_SP - 2); -} - -INLINE void m68ki_fake_push_32(void) -{ - REG_SP = MASK_OUT_ABOVE_32(REG_SP - 4); -} - -INLINE void m68ki_fake_pull_16(void) -{ - REG_SP = MASK_OUT_ABOVE_32(REG_SP + 2); -} - -INLINE void m68ki_fake_pull_32(void) -{ - REG_SP = MASK_OUT_ABOVE_32(REG_SP + 4); -} - - -/* ----------------------------- Program Flow ----------------------------- */ - -/* Jump to a new program location or vector. - * These functions will also call the pc_changed callback if it was enabled - * in m68kconf.h. - */ -INLINE void m68ki_jump(uint new_pc) -{ - REG_PC = new_pc; - m68ki_pc_changed(REG_PC); -} - -INLINE void m68ki_jump_vector(uint vector) -{ - REG_PC = (vector<<2) + REG_VBR; - REG_PC = m68ki_read_data_32(REG_PC); - m68ki_pc_changed(REG_PC); -} - - -/* Branch to a new memory location. - * The 32-bit branch will call pc_changed if it was enabled in m68kconf.h. - * So far I've found no problems with not calling pc_changed for 8 or 16 - * bit branches. - */ -INLINE void m68ki_branch_8(uint offset) -{ - REG_PC += MAKE_INT_8(offset); -} - -INLINE void m68ki_branch_16(uint offset) -{ - REG_PC += MAKE_INT_16(offset); -} - -INLINE void m68ki_branch_32(uint offset) -{ - REG_PC += offset; - m68ki_pc_changed(REG_PC); -} - - - -/* ---------------------------- Status Register --------------------------- */ - -/* Set the S flag and change the active stack pointer. - * Note that value MUST be 4 or 0. - */ -INLINE void m68ki_set_s_flag(uint value) -{ - /* Backup the old stack pointer */ - REG_SP_BASE[FLAG_S | ((FLAG_S>>1) & FLAG_M)] = REG_SP; - /* Set the S flag */ - FLAG_S = value; - /* Set the new stack pointer */ - REG_SP = REG_SP_BASE[FLAG_S | ((FLAG_S>>1) & FLAG_M)]; -} - -/* Set the S and M flags and change the active stack pointer. - * Note that value MUST be 0, 2, 4, or 6 (bit2 = S, bit1 = M). - */ -INLINE void m68ki_set_sm_flag(uint value) -{ - /* Backup the old stack pointer */ - REG_SP_BASE[FLAG_S | ((FLAG_S>>1) & FLAG_M)] = REG_SP; - /* Set the S and M flags */ - FLAG_S = value & SFLAG_SET; - FLAG_M = value & MFLAG_SET; - /* Set the new stack pointer */ - REG_SP = REG_SP_BASE[FLAG_S | ((FLAG_S>>1) & FLAG_M)]; -} - -/* Set the S and M flags. Don't touch the stack pointer. */ -INLINE void m68ki_set_sm_flag_nosp(uint value) -{ - /* Set the S and M flags */ - FLAG_S = value & SFLAG_SET; - FLAG_M = value & MFLAG_SET; -} - - -/* Set the condition code register */ -INLINE void m68ki_set_ccr(uint value) -{ - FLAG_X = BIT_4(value) << 4; - FLAG_N = BIT_3(value) << 4; - FLAG_Z = !BIT_2(value); - FLAG_V = BIT_1(value) << 6; - FLAG_C = BIT_0(value) << 8; -} - -/* Set the status register but don't check for interrupts */ -INLINE void m68ki_set_sr_noint(uint value) -{ - /* Mask out the "unimplemented" bits */ - value &= CPU_SR_MASK; - - /* Now set the status register */ - FLAG_T1 = BIT_F(value); - FLAG_T0 = BIT_E(value); - FLAG_INT_MASK = value & 0x0700; - m68ki_set_ccr(value); - m68ki_set_sm_flag((value >> 11) & 6); -} - -/* Set the status register but don't check for interrupts nor - * change the stack pointer - */ -INLINE void m68ki_set_sr_noint_nosp(uint value) -{ - /* Mask out the "unimplemented" bits */ - value &= CPU_SR_MASK; - - /* Now set the status register */ - FLAG_T1 = BIT_F(value); - FLAG_T0 = BIT_E(value); - FLAG_INT_MASK = value & 0x0700; - m68ki_set_ccr(value); - m68ki_set_sm_flag_nosp((value >> 11) & 6); -} - -/* Set the status register and check for interrupts */ -INLINE void m68ki_set_sr(uint value) -{ - m68ki_set_sr_noint(value); - m68ki_check_interrupts(); -} - - -/* ------------------------- Exception Processing ------------------------- */ - -/* Initiate exception processing */ -INLINE uint m68ki_init_exception(void) -{ - /* Save the old status register */ - uint sr = m68ki_get_sr(); - - /* Turn off trace flag, clear pending traces */ - FLAG_T1 = FLAG_T0 = 0; - m68ki_clear_trace(); - /* Enter supervisor mode */ - m68ki_set_s_flag(SFLAG_SET); - - return sr; -} - -/* 3 word stack frame (68000 only) */ -INLINE void m68ki_stack_frame_3word(uint pc, uint sr) -{ - m68ki_push_32(pc); - m68ki_push_16(sr); -} - -/* Format 0 stack frame. - * This is the standard stack frame for 68010+. - */ -INLINE void m68ki_stack_frame_0000(uint pc, uint sr, uint vector) -{ - /* Stack a 3-word frame if we are 68000 */ - if(CPU_TYPE == CPU_TYPE_000) - { - m68ki_stack_frame_3word(pc, sr); - return; - } - m68ki_push_16(vector<<2); - m68ki_push_32(pc); - m68ki_push_16(sr); -} - -/* Format 1 stack frame (68020). - * For 68020, this is the 4 word throwaway frame. - */ -INLINE void m68ki_stack_frame_0001(uint pc, uint sr, uint vector) -{ - m68ki_push_16(0x1000 | (vector<<2)); - m68ki_push_32(pc); - m68ki_push_16(sr); -} - -/* Format 2 stack frame. - * This is used only by 68020 for trap exceptions. - */ -INLINE void m68ki_stack_frame_0010(uint sr, uint vector) -{ - m68ki_push_32(REG_PPC); - m68ki_push_16(0x2000 | (vector<<2)); - m68ki_push_32(REG_PC); - m68ki_push_16(sr); -} - - -/* Bus error stack frame (68000 only). - */ -INLINE void m68ki_stack_frame_buserr(uint sr) -{ - m68ki_push_32(REG_PC); - m68ki_push_16(sr); - m68ki_push_16(REG_IR); - m68ki_push_32(m68ki_aerr_address); /* access address */ - /* 0 0 0 0 0 0 0 0 0 0 0 R/W I/N FC - * R/W 0 = write, 1 = read - * I/N 0 = instruction, 1 = not - * FC 3-bit function code - */ - m68ki_push_16(m68ki_aerr_write_mode | CPU_INSTR_MODE | m68ki_aerr_fc); -} - -/* Format 8 stack frame (68010). - * 68010 only. This is the 29 word bus/address error frame. - */ -void m68ki_stack_frame_1000(uint pc, uint sr, uint vector) -{ - /* VERSION - * NUMBER - * INTERNAL INFORMATION, 16 WORDS - */ - m68ki_fake_push_32(); - m68ki_fake_push_32(); - m68ki_fake_push_32(); - m68ki_fake_push_32(); - m68ki_fake_push_32(); - m68ki_fake_push_32(); - m68ki_fake_push_32(); - m68ki_fake_push_32(); - - /* INSTRUCTION INPUT BUFFER */ - m68ki_push_16(0); - - /* UNUSED, RESERVED (not written) */ - m68ki_fake_push_16(); - - /* DATA INPUT BUFFER */ - m68ki_push_16(0); - - /* UNUSED, RESERVED (not written) */ - m68ki_fake_push_16(); - - /* DATA OUTPUT BUFFER */ - m68ki_push_16(0); - - /* UNUSED, RESERVED (not written) */ - m68ki_fake_push_16(); - - /* FAULT ADDRESS */ - m68ki_push_32(0); - - /* SPECIAL STATUS WORD */ - m68ki_push_16(0); - - /* 1000, VECTOR OFFSET */ - m68ki_push_16(0x8000 | (vector<<2)); - - /* PROGRAM COUNTER */ - m68ki_push_32(pc); - - /* STATUS REGISTER */ - m68ki_push_16(sr); -} - -/* Format A stack frame (short bus fault). - * This is used only by 68020 for bus fault and address error - * if the error happens at an instruction boundary. - * PC stacked is address of next instruction. - */ -void m68ki_stack_frame_1010(uint sr, uint vector, uint pc) -{ - /* INTERNAL REGISTER */ - m68ki_push_16(0); - - /* INTERNAL REGISTER */ - m68ki_push_16(0); - - /* DATA OUTPUT BUFFER (2 words) */ - m68ki_push_32(0); - - /* INTERNAL REGISTER */ - m68ki_push_16(0); - - /* INTERNAL REGISTER */ - m68ki_push_16(0); - - /* DATA CYCLE FAULT ADDRESS (2 words) */ - m68ki_push_32(0); - - /* INSTRUCTION PIPE STAGE B */ - m68ki_push_16(0); - - /* INSTRUCTION PIPE STAGE C */ - m68ki_push_16(0); - - /* SPECIAL STATUS REGISTER */ - m68ki_push_16(0); - - /* INTERNAL REGISTER */ - m68ki_push_16(0); - - /* 1010, VECTOR OFFSET */ - m68ki_push_16(0xa000 | (vector<<2)); - - /* PROGRAM COUNTER */ - m68ki_push_32(pc); - - /* STATUS REGISTER */ - m68ki_push_16(sr); -} - -/* Format B stack frame (long bus fault). - * This is used only by 68020 for bus fault and address error - * if the error happens during instruction execution. - * PC stacked is address of instruction in progress. - */ -void m68ki_stack_frame_1011(uint sr, uint vector, uint pc) -{ - /* INTERNAL REGISTERS (18 words) */ - m68ki_push_32(0); - m68ki_push_32(0); - m68ki_push_32(0); - m68ki_push_32(0); - m68ki_push_32(0); - m68ki_push_32(0); - m68ki_push_32(0); - m68ki_push_32(0); - m68ki_push_32(0); - - /* VERSION# (4 bits), INTERNAL INFORMATION */ - m68ki_push_16(0); - - /* INTERNAL REGISTERS (3 words) */ - m68ki_push_32(0); - m68ki_push_16(0); - - /* DATA INTPUT BUFFER (2 words) */ - m68ki_push_32(0); - - /* INTERNAL REGISTERS (2 words) */ - m68ki_push_32(0); - - /* STAGE B ADDRESS (2 words) */ - m68ki_push_32(0); - - /* INTERNAL REGISTER (4 words) */ - m68ki_push_32(0); - m68ki_push_32(0); - - /* DATA OUTPUT BUFFER (2 words) */ - m68ki_push_32(0); - - /* INTERNAL REGISTER */ - m68ki_push_16(0); - - /* INTERNAL REGISTER */ - m68ki_push_16(0); - - /* DATA CYCLE FAULT ADDRESS (2 words) */ - m68ki_push_32(0); - - /* INSTRUCTION PIPE STAGE B */ - m68ki_push_16(0); - - /* INSTRUCTION PIPE STAGE C */ - m68ki_push_16(0); - - /* SPECIAL STATUS REGISTER */ - m68ki_push_16(0); - - /* INTERNAL REGISTER */ - m68ki_push_16(0); - - /* 1011, VECTOR OFFSET */ - m68ki_push_16(0xb000 | (vector<<2)); - - /* PROGRAM COUNTER */ - m68ki_push_32(pc); - - /* STATUS REGISTER */ - m68ki_push_16(sr); -} - - -/* Used for Group 2 exceptions. - * These stack a type 2 frame on the 020. - */ -INLINE void m68ki_exception_trap(uint vector) -{ - uint sr = m68ki_init_exception(); - - if(CPU_TYPE_IS_010_LESS(CPU_TYPE)) - m68ki_stack_frame_0000(REG_PC, sr, vector); - else - m68ki_stack_frame_0010(sr, vector); - - m68ki_jump_vector(vector); - - /* Use up some clock cycles */ - USE_CYCLES(CYC_EXCEPTION[vector]); -} - -/* Trap#n stacks a 0 frame but behaves like group2 otherwise */ -INLINE void m68ki_exception_trapN(uint vector) -{ - uint sr = m68ki_init_exception(); - m68ki_stack_frame_0000(REG_PC, sr, vector); - m68ki_jump_vector(vector); - - /* Use up some clock cycles */ - USE_CYCLES(CYC_EXCEPTION[vector]); -} - -/* Exception for trace mode */ -INLINE void m68ki_exception_trace(void) -{ - uint sr = m68ki_init_exception(); - - if(CPU_TYPE_IS_010_LESS(CPU_TYPE)) - { - #if M68K_EMULATE_ADDRESS_ERROR == OPT_ON - if(CPU_TYPE_IS_000(CPU_TYPE)) - { - CPU_INSTR_MODE = INSTRUCTION_NO; - } - #endif /* M68K_EMULATE_ADDRESS_ERROR */ - m68ki_stack_frame_0000(REG_PC, sr, EXCEPTION_TRACE); - } - else - m68ki_stack_frame_0010(sr, EXCEPTION_TRACE); - - m68ki_jump_vector(EXCEPTION_TRACE); - - /* Trace nullifies a STOP instruction */ - CPU_STOPPED &= ~STOP_LEVEL_STOP; - - /* Use up some clock cycles */ - USE_CYCLES(CYC_EXCEPTION[EXCEPTION_TRACE]); -} - -/* Exception for privilege violation */ -INLINE void m68ki_exception_privilege_violation(void) -{ - uint sr = m68ki_init_exception(); - - #if M68K_EMULATE_ADDRESS_ERROR == OPT_ON - if(CPU_TYPE_IS_000(CPU_TYPE)) - { - CPU_INSTR_MODE = INSTRUCTION_NO; - } - #endif /* M68K_EMULATE_ADDRESS_ERROR */ - - m68ki_stack_frame_0000(REG_PPC, sr, EXCEPTION_PRIVILEGE_VIOLATION); - m68ki_jump_vector(EXCEPTION_PRIVILEGE_VIOLATION); - - /* Use up some clock cycles and undo the instruction's cycles */ - USE_CYCLES(CYC_EXCEPTION[EXCEPTION_PRIVILEGE_VIOLATION] - CYC_INSTRUCTION[REG_IR]); -} - -/* Exception for A-Line instructions */ -INLINE void m68ki_exception_1010(void) -{ - uint sr; -#if M68K_LOG_1010_1111 == OPT_ON - M68K_DO_LOG_EMU((M68K_LOG_FILEHANDLE "%s at %08x: called 1010 instruction %04x (%s)\n", - m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PPC), REG_IR, - m68ki_disassemble_quick(ADDRESS_68K(REG_PPC)))); -#endif - - sr = m68ki_init_exception(); - m68ki_stack_frame_0000(REG_PPC, sr, EXCEPTION_1010); - m68ki_jump_vector(EXCEPTION_1010); - - /* Use up some clock cycles and undo the instruction's cycles */ - USE_CYCLES(CYC_EXCEPTION[EXCEPTION_1010] - CYC_INSTRUCTION[REG_IR]); -} - -/* Exception for F-Line instructions */ -INLINE void m68ki_exception_1111(void) -{ - uint sr; - -#if M68K_LOG_1010_1111 == OPT_ON - M68K_DO_LOG_EMU((M68K_LOG_FILEHANDLE "%s at %08x: called 1111 instruction %04x (%s)\n", - m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PPC), REG_IR, - m68ki_disassemble_quick(ADDRESS_68K(REG_PPC)))); -#endif - - sr = m68ki_init_exception(); - m68ki_stack_frame_0000(REG_PPC, sr, EXCEPTION_1111); - m68ki_jump_vector(EXCEPTION_1111); - - /* Use up some clock cycles and undo the instruction's cycles */ - USE_CYCLES(CYC_EXCEPTION[EXCEPTION_1111] - CYC_INSTRUCTION[REG_IR]); -} - -/* Exception for illegal instructions */ -INLINE void m68ki_exception_illegal(void) -{ - uint sr; - - M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: illegal instruction %04x (%s)\n", - m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PPC), REG_IR, - m68ki_disassemble_quick(ADDRESS_68K(REG_PPC)))); - - sr = m68ki_init_exception(); - - #if M68K_EMULATE_ADDRESS_ERROR == OPT_ON - if(CPU_TYPE_IS_000(CPU_TYPE)) - { - CPU_INSTR_MODE = INSTRUCTION_NO; - } - #endif /* M68K_EMULATE_ADDRESS_ERROR */ - - m68ki_stack_frame_0000(REG_PPC, sr, EXCEPTION_ILLEGAL_INSTRUCTION); - m68ki_jump_vector(EXCEPTION_ILLEGAL_INSTRUCTION); - - /* Use up some clock cycles and undo the instruction's cycles */ - USE_CYCLES(CYC_EXCEPTION[EXCEPTION_ILLEGAL_INSTRUCTION] - CYC_INSTRUCTION[REG_IR]); -} - -/* Exception for format errror in RTE */ -INLINE void m68ki_exception_format_error(void) -{ - uint sr = m68ki_init_exception(); - m68ki_stack_frame_0000(REG_PC, sr, EXCEPTION_FORMAT_ERROR); - m68ki_jump_vector(EXCEPTION_FORMAT_ERROR); - - /* Use up some clock cycles and undo the instruction's cycles */ - USE_CYCLES(CYC_EXCEPTION[EXCEPTION_FORMAT_ERROR] - CYC_INSTRUCTION[REG_IR]); -} - -/* Exception for address error */ -INLINE void m68ki_exception_address_error(void) -{ - uint sr = m68ki_init_exception(); - - /* If we were processing a bus error, address error, or reset, - * this is a catastrophic failure. - * Halt the CPU - */ - if(CPU_RUN_MODE == RUN_MODE_BERR_AERR_RESET) - { -m68k_read_memory_8(0x00ffff01); - CPU_STOPPED = STOP_LEVEL_HALT; - return; - } - CPU_RUN_MODE = RUN_MODE_BERR_AERR_RESET; - - /* Note: This is implemented for 68000 only! */ - m68ki_stack_frame_buserr(sr); - - m68ki_jump_vector(EXCEPTION_ADDRESS_ERROR); - - /* Use up some clock cycles and undo the instruction's cycles */ - USE_CYCLES(CYC_EXCEPTION[EXCEPTION_ADDRESS_ERROR] - CYC_INSTRUCTION[REG_IR]); -} - - -/* Service an interrupt request and start exception processing */ -void m68ki_exception_interrupt(uint int_level) -{ - uint vector; - uint sr; - uint new_pc; - - #if M68K_EMULATE_ADDRESS_ERROR == OPT_ON - if(CPU_TYPE_IS_000(CPU_TYPE)) - { - CPU_INSTR_MODE = INSTRUCTION_NO; - } - #endif /* M68K_EMULATE_ADDRESS_ERROR */ - - /* Turn off the stopped state */ - CPU_STOPPED &= ~STOP_LEVEL_STOP; - - /* If we are halted, don't do anything */ - if(CPU_STOPPED) - return; - - /* Acknowledge the interrupt */ - vector = m68ki_int_ack(int_level); - - /* Get the interrupt vector */ - if(vector == M68K_INT_ACK_AUTOVECTOR) - /* Use the autovectors. This is the most commonly used implementation */ - vector = EXCEPTION_INTERRUPT_AUTOVECTOR+int_level; - else if(vector == M68K_INT_ACK_SPURIOUS) - /* Called if no devices respond to the interrupt acknowledge */ - vector = EXCEPTION_SPURIOUS_INTERRUPT; - else if(vector > 255) - { - M68K_DO_LOG_EMU((M68K_LOG_FILEHANDLE "%s at %08x: Interrupt acknowledge returned invalid vector $%x\n", - m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC), vector)); - return; - } - - /* Start exception processing */ - sr = m68ki_init_exception(); - - /* Set the interrupt mask to the level of the one being serviced */ - FLAG_INT_MASK = int_level<<8; - - /* Get the new PC */ - new_pc = m68ki_read_data_32((vector<<2) + REG_VBR); - - /* If vector is uninitialized, call the uninitialized interrupt vector */ - if(new_pc == 0) - new_pc = m68ki_read_data_32((EXCEPTION_UNINITIALIZED_INTERRUPT<<2) + REG_VBR); - - /* Generate a stack frame */ - m68ki_stack_frame_0000(REG_PC, sr, vector); - if(FLAG_M && CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - /* Create throwaway frame */ - m68ki_set_sm_flag(FLAG_S); /* clear M */ - sr |= 0x2000; /* Same as SR in master stack frame except S is forced high */ - m68ki_stack_frame_0001(REG_PC, sr, vector); - } - - m68ki_jump(new_pc); - - /* Defer cycle counting until later */ - CPU_INT_CYCLES += CYC_EXCEPTION[vector]; - -#if !M68K_EMULATE_INT_ACK - /* Automatically clear IRQ if we are not using an acknowledge scheme */ - CPU_INT_LEVEL = 0; -#endif /* M68K_EMULATE_INT_ACK */ -} - - -/* ASG: Check for interrupts */ -INLINE void m68ki_check_interrupts(void) -{ - if(CPU_INT_LEVEL > FLAG_INT_MASK) - m68ki_exception_interrupt(CPU_INT_LEVEL>>8); -} - - - -/* ======================================================================== */ -/* ============================== END OF FILE ============================= */ -/* ======================================================================== */ - -#endif /* M68KCPU__HEADER */ diff --git a/Frameworks/AudioOverload/aosdk/eng_ssf/m68kmame.h b/Frameworks/AudioOverload/aosdk/eng_ssf/m68kmame.h deleted file mode 100644 index 6ac0ec597..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_ssf/m68kmame.h +++ /dev/null @@ -1,172 +0,0 @@ -#ifndef M68KMAME__HEADER -#define M68KMAME__HEADER - -/* ======================================================================== */ -/* ============================== MAME STUFF ============================== */ -/* ======================================================================== */ - -#include "cpuintrf.h" -#include "memory.h" -#include "mamedbg.h" -#include "m68000.h" - -extern int m68ki_remaining_cycles; - -/* Configuration switches (see m68kconf.h for explanation) */ -#define M68K_SEPARATE_READS OPT_ON - -#define M68K_SIMULATE_PD_WRITES OPT_ON - -#define M68K_EMULATE_INT_ACK OPT_ON -#define M68K_INT_ACK_CALLBACK(A) - -#define M68K_EMULATE_BKPT_ACK OPT_OFF -#define M68K_BKPT_ACK_CALLBACK() - -#define M68K_EMULATE_TRACE OPT_OFF - -#define M68K_EMULATE_RESET OPT_ON -#define M68K_RESET_CALLBACK() - -#define M68K_EMULATE_FC OPT_OFF -#define M68K_SET_FC_CALLBACK(A) - -#define M68K_MONITOR_PC OPT_SPECIFY_HANDLER -#define M68K_SET_PC_CALLBACK(A) (*m68k_memory_intf.changepc)(A) - -#define M68K_INSTRUCTION_HOOK OPT_SPECIFY_HANDLER -#define M68K_INSTRUCTION_CALLBACK() CALL_MAME_DEBUG - -#define M68K_EMULATE_PREFETCH OPT_ON - -#define M68K_LOG_ENABLE OPT_OFF -#define M68K_LOG_1010_1111 OPT_OFF -#define M68K_LOG_FILEHANDLE errorlog - -#define M68K_EMULATE_ADDRESS_ERROR OPT_OFF - -#define M68K_USE_64_BIT OPT_OFF - -extern struct m68k_memory_interface m68k_memory_intf; - -#define m68k_read_memory_8(address) (*m68k_memory_intf.read8)(address) -#define m68k_read_memory_16(address) (*m68k_memory_intf.read16)(address) -#define m68k_read_memory_32(address) (*m68k_memory_intf.read32)(address) - -INLINE unsigned int m68k_read_immediate_16(unsigned int address) -{ - return cpu_readop16((address) ^ m68k_memory_intf.opcode_xor); -} - -INLINE unsigned int m68k_read_immediate_32(unsigned int address) -{ - return ((m68k_read_immediate_16(address) << 16) | m68k_read_immediate_16((address)+2)); -} - -INLINE unsigned int m68k_read_pcrelative_8(unsigned int address) -{ - if (address >= encrypted_opcode_start[cpu_getactivecpu()] && - address < encrypted_opcode_end[cpu_getactivecpu()]) - return ((m68k_read_immediate_16(address&~1)>>(8*(1-(address & 1))))&0xff); - else - return m68k_read_memory_8(address); -} - -INLINE unsigned int m68k_read_pcrelative_16(unsigned int address) -{ - if (address >= encrypted_opcode_start[cpu_getactivecpu()] && - address < encrypted_opcode_end[cpu_getactivecpu()]) - return m68k_read_immediate_16(address); - else - return m68k_read_memory_16(address); -} - -INLINE unsigned int m68k_read_pcrelative_32(unsigned int address) -{ - if (address >= encrypted_opcode_start[cpu_getactivecpu()] && - address < encrypted_opcode_end[cpu_getactivecpu()]) - return m68k_read_immediate_32(address); - else - return m68k_read_memory_32(address); -} - -#define m68k_read_disassembler_16(address) m68k_read_immediate_16(address) -#define m68k_read_disassembler_32(address) m68k_read_immediate_32(address) - - -#define m68k_write_memory_8(address, value) (*m68k_memory_intf.write8)(address, value) -#define m68k_write_memory_16(address, value) (*m68k_memory_intf.write16)(address, value) -#define m68k_write_memory_32(address, value) (*m68k_memory_intf.write32)(address, value) - -/* Special call to simulate undocumented 68k behavior when move.l with a - * predecrement destination mode is executed. - * A real 68k first writes the high word to [address+2], and then writes the - * low word to [address]. - */ -INLINE void m68k_write_memory_32_pd(unsigned int address, unsigned int value) -{ - (*m68k_memory_intf.write16)(address+2, value>>16); - (*m68k_memory_intf.write16)(address, value&0xffff); -} - - -#ifdef A68K0 -#define M68K_EMULATE_010 OPT_OFF -#else - -// The PPC 68k core defines A68K0 internal to itself to avoid recompiling -// all of MAME when you want to disable it. The downside is that the C and x86 -// cores can't agree on the same name for the icount variable, so we force the -// issue with a Mac-specific hack. -#ifdef macintosh -extern int m68k_ICount; -#else -#define m68ki_remaining_cycles m68k_ICount -#endif - -/* M68K Variants */ -#if HAS_M68010 -#define M68K_EMULATE_010 OPT_ON -#else -#define M68K_EMULATE_010 OPT_OFF -#endif - -#endif // A68K0 - -#ifdef A68K2 -#define M68K_EMULATE_EC020 OPT_OFF -#define M68K_EMULATE_020 OPT_OFF -#else - -// The PPC 68k core defines A68K2 internal to itself to avoid recompiling -// all of MAME when you want to disable it. The downside is that the C and x86 -// cores can't agree on the same name for the icount variable, so we force the -// issue with a Mac-specific hack. -#ifdef macintosh -extern int M68020_ICount; -#else -#define m68ki_remaining_cycles m68k_ICount -#endif - -#undef M68K_EMULATE_010 -#define M68K_EMULATE_010 OPT_ON - -#if HAS_M68EC020 -#define M68K_EMULATE_EC020 OPT_ON -#else -#define M68K_EMULATE_EC020 OPT_OFF -#endif - -#if HAS_M68020 -#define M68K_EMULATE_020 OPT_ON -#else -#define M68K_EMULATE_020 OPT_OFF -#endif - -#endif // A68K2 - -/* ======================================================================== */ -/* ============================== END OF FILE ============================= */ -/* ======================================================================== */ - -#endif /* M68KMAME__HEADER */ diff --git a/Frameworks/AudioOverload/aosdk/eng_ssf/m68kopac.c b/Frameworks/AudioOverload/aosdk/eng_ssf/m68kopac.c deleted file mode 100644 index 535eb888f..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_ssf/m68kopac.c +++ /dev/null @@ -1,12042 +0,0 @@ -#include "m68kcpu.h" - -/* ======================================================================== */ -/* ========================= INSTRUCTION HANDLERS ========================= */ -/* ======================================================================== */ - - -void m68k_op_1010(void) -{ - m68ki_exception_1010(); -} - - -void m68k_op_1111(void) -{ - m68ki_exception_1111(); -} - - -void m68k_op_abcd_8_rr(void) -{ - uint* r_dst = &DX; - uint src = DY; - uint dst = *r_dst; - uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1(); - - FLAG_V = ~res; /* Undefined V behavior */ - - if(res > 9) - res += 6; - res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst); - FLAG_X = FLAG_C = (res > 0x99) << 8; - if(FLAG_C) - res -= 0xa0; - - FLAG_V &= res; /* Undefined V behavior part II */ - FLAG_N = NFLAG_8(res); /* Undefined N behavior */ - - res = MASK_OUT_ABOVE_8(res); - FLAG_Z |= res; - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; -} - - -void m68k_op_abcd_8_mm_ax7(void) -{ - uint src = OPER_AY_PD_8(); - uint ea = EA_A7_PD_8(); - uint dst = m68ki_read_8(ea); - uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1(); - - FLAG_V = ~res; /* Undefined V behavior */ - - if(res > 9) - res += 6; - res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst); - FLAG_X = FLAG_C = (res > 0x99) << 8; - if(FLAG_C) - res -= 0xa0; - - FLAG_V &= res; /* Undefined V behavior part II */ - FLAG_N = NFLAG_8(res); /* Undefined N behavior */ - - res = MASK_OUT_ABOVE_8(res); - FLAG_Z |= res; - - m68ki_write_8(ea, res); -} - - -void m68k_op_abcd_8_mm_ay7(void) -{ - uint src = OPER_A7_PD_8(); - uint ea = EA_AX_PD_8(); - uint dst = m68ki_read_8(ea); - uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1(); - - FLAG_V = ~res; /* Undefined V behavior */ - - if(res > 9) - res += 6; - res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst); - FLAG_X = FLAG_C = (res > 0x99) << 8; - if(FLAG_C) - res -= 0xa0; - - FLAG_V &= res; /* Undefined V behavior part II */ - FLAG_N = NFLAG_8(res); /* Undefined N behavior */ - - res = MASK_OUT_ABOVE_8(res); - FLAG_Z |= res; - - m68ki_write_8(ea, res); -} - - -void m68k_op_abcd_8_mm_axy7(void) -{ - uint src = OPER_A7_PD_8(); - uint ea = EA_A7_PD_8(); - uint dst = m68ki_read_8(ea); - uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1(); - - FLAG_V = ~res; /* Undefined V behavior */ - - if(res > 9) - res += 6; - res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst); - FLAG_X = FLAG_C = (res > 0x99) << 8; - if(FLAG_C) - res -= 0xa0; - - FLAG_V &= res; /* Undefined V behavior part II */ - FLAG_N = NFLAG_8(res); /* Undefined N behavior */ - - res = MASK_OUT_ABOVE_8(res); - FLAG_Z |= res; - - m68ki_write_8(ea, res); -} - - -void m68k_op_abcd_8_mm(void) -{ - uint src = OPER_AY_PD_8(); - uint ea = EA_AX_PD_8(); - uint dst = m68ki_read_8(ea); - uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1(); - - FLAG_V = ~res; /* Undefined V behavior */ - - if(res > 9) - res += 6; - res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst); - FLAG_X = FLAG_C = (res > 0x99) << 8; - if(FLAG_C) - res -= 0xa0; - - FLAG_V &= res; /* Undefined V behavior part II */ - FLAG_N = NFLAG_8(res); /* Undefined N behavior */ - - res = MASK_OUT_ABOVE_8(res); - FLAG_Z |= res; - - m68ki_write_8(ea, res); -} - - -void m68k_op_add_8_er_d(void) -{ - uint* r_dst = &DX; - uint src = MASK_OUT_ABOVE_8(DY); - uint dst = MASK_OUT_ABOVE_8(*r_dst); - uint res = src + dst; - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; -} - - -void m68k_op_add_8_er_ai(void) -{ - uint* r_dst = &DX; - uint src = OPER_AY_AI_8(); - uint dst = MASK_OUT_ABOVE_8(*r_dst); - uint res = src + dst; - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; -} - - -void m68k_op_add_8_er_pi(void) -{ - uint* r_dst = &DX; - uint src = OPER_AY_PI_8(); - uint dst = MASK_OUT_ABOVE_8(*r_dst); - uint res = src + dst; - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; -} - - -void m68k_op_add_8_er_pi7(void) -{ - uint* r_dst = &DX; - uint src = OPER_A7_PI_8(); - uint dst = MASK_OUT_ABOVE_8(*r_dst); - uint res = src + dst; - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; -} - - -void m68k_op_add_8_er_pd(void) -{ - uint* r_dst = &DX; - uint src = OPER_AY_PD_8(); - uint dst = MASK_OUT_ABOVE_8(*r_dst); - uint res = src + dst; - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; -} - - -void m68k_op_add_8_er_pd7(void) -{ - uint* r_dst = &DX; - uint src = OPER_A7_PD_8(); - uint dst = MASK_OUT_ABOVE_8(*r_dst); - uint res = src + dst; - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; -} - - -void m68k_op_add_8_er_di(void) -{ - uint* r_dst = &DX; - uint src = OPER_AY_DI_8(); - uint dst = MASK_OUT_ABOVE_8(*r_dst); - uint res = src + dst; - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; -} - - -void m68k_op_add_8_er_ix(void) -{ - uint* r_dst = &DX; - uint src = OPER_AY_IX_8(); - uint dst = MASK_OUT_ABOVE_8(*r_dst); - uint res = src + dst; - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; -} - - -void m68k_op_add_8_er_aw(void) -{ - uint* r_dst = &DX; - uint src = OPER_AW_8(); - uint dst = MASK_OUT_ABOVE_8(*r_dst); - uint res = src + dst; - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; -} - - -void m68k_op_add_8_er_al(void) -{ - uint* r_dst = &DX; - uint src = OPER_AL_8(); - uint dst = MASK_OUT_ABOVE_8(*r_dst); - uint res = src + dst; - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; -} - - -void m68k_op_add_8_er_pcdi(void) -{ - uint* r_dst = &DX; - uint src = OPER_PCDI_8(); - uint dst = MASK_OUT_ABOVE_8(*r_dst); - uint res = src + dst; - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; -} - - -void m68k_op_add_8_er_pcix(void) -{ - uint* r_dst = &DX; - uint src = OPER_PCIX_8(); - uint dst = MASK_OUT_ABOVE_8(*r_dst); - uint res = src + dst; - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; -} - - -void m68k_op_add_8_er_i(void) -{ - uint* r_dst = &DX; - uint src = OPER_I_8(); - uint dst = MASK_OUT_ABOVE_8(*r_dst); - uint res = src + dst; - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; -} - - -void m68k_op_add_16_er_d(void) -{ - uint* r_dst = &DX; - uint src = MASK_OUT_ABOVE_16(DY); - uint dst = MASK_OUT_ABOVE_16(*r_dst); - uint res = src + dst; - - FLAG_N = NFLAG_16(res); - FLAG_V = VFLAG_ADD_16(src, dst, res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; -} - - -void m68k_op_add_16_er_a(void) -{ - uint* r_dst = &DX; - uint src = MASK_OUT_ABOVE_16(AY); - uint dst = MASK_OUT_ABOVE_16(*r_dst); - uint res = src + dst; - - FLAG_N = NFLAG_16(res); - FLAG_V = VFLAG_ADD_16(src, dst, res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; -} - - -void m68k_op_add_16_er_ai(void) -{ - uint* r_dst = &DX; - uint src = OPER_AY_AI_16(); - uint dst = MASK_OUT_ABOVE_16(*r_dst); - uint res = src + dst; - - FLAG_N = NFLAG_16(res); - FLAG_V = VFLAG_ADD_16(src, dst, res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; -} - - -void m68k_op_add_16_er_pi(void) -{ - uint* r_dst = &DX; - uint src = OPER_AY_PI_16(); - uint dst = MASK_OUT_ABOVE_16(*r_dst); - uint res = src + dst; - - FLAG_N = NFLAG_16(res); - FLAG_V = VFLAG_ADD_16(src, dst, res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; -} - - -void m68k_op_add_16_er_pd(void) -{ - uint* r_dst = &DX; - uint src = OPER_AY_PD_16(); - uint dst = MASK_OUT_ABOVE_16(*r_dst); - uint res = src + dst; - - FLAG_N = NFLAG_16(res); - FLAG_V = VFLAG_ADD_16(src, dst, res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; -} - - -void m68k_op_add_16_er_di(void) -{ - uint* r_dst = &DX; - uint src = OPER_AY_DI_16(); - uint dst = MASK_OUT_ABOVE_16(*r_dst); - uint res = src + dst; - - FLAG_N = NFLAG_16(res); - FLAG_V = VFLAG_ADD_16(src, dst, res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; -} - - -void m68k_op_add_16_er_ix(void) -{ - uint* r_dst = &DX; - uint src = OPER_AY_IX_16(); - uint dst = MASK_OUT_ABOVE_16(*r_dst); - uint res = src + dst; - - FLAG_N = NFLAG_16(res); - FLAG_V = VFLAG_ADD_16(src, dst, res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; -} - - -void m68k_op_add_16_er_aw(void) -{ - uint* r_dst = &DX; - uint src = OPER_AW_16(); - uint dst = MASK_OUT_ABOVE_16(*r_dst); - uint res = src + dst; - - FLAG_N = NFLAG_16(res); - FLAG_V = VFLAG_ADD_16(src, dst, res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; -} - - -void m68k_op_add_16_er_al(void) -{ - uint* r_dst = &DX; - uint src = OPER_AL_16(); - uint dst = MASK_OUT_ABOVE_16(*r_dst); - uint res = src + dst; - - FLAG_N = NFLAG_16(res); - FLAG_V = VFLAG_ADD_16(src, dst, res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; -} - - -void m68k_op_add_16_er_pcdi(void) -{ - uint* r_dst = &DX; - uint src = OPER_PCDI_16(); - uint dst = MASK_OUT_ABOVE_16(*r_dst); - uint res = src + dst; - - FLAG_N = NFLAG_16(res); - FLAG_V = VFLAG_ADD_16(src, dst, res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; -} - - -void m68k_op_add_16_er_pcix(void) -{ - uint* r_dst = &DX; - uint src = OPER_PCIX_16(); - uint dst = MASK_OUT_ABOVE_16(*r_dst); - uint res = src + dst; - - FLAG_N = NFLAG_16(res); - FLAG_V = VFLAG_ADD_16(src, dst, res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; -} - - -void m68k_op_add_16_er_i(void) -{ - uint* r_dst = &DX; - uint src = OPER_I_16(); - uint dst = MASK_OUT_ABOVE_16(*r_dst); - uint res = src + dst; - - FLAG_N = NFLAG_16(res); - FLAG_V = VFLAG_ADD_16(src, dst, res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; -} - - -void m68k_op_add_32_er_d(void) -{ - uint* r_dst = &DX; - uint src = DY; - uint dst = *r_dst; - uint res = src + dst; - - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_ADD_32(src, dst, res); - FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - *r_dst = FLAG_Z; -} - - -void m68k_op_add_32_er_a(void) -{ - uint* r_dst = &DX; - uint src = AY; - uint dst = *r_dst; - uint res = src + dst; - - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_ADD_32(src, dst, res); - FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - *r_dst = FLAG_Z; -} - - -void m68k_op_add_32_er_ai(void) -{ - uint* r_dst = &DX; - uint src = OPER_AY_AI_32(); - uint dst = *r_dst; - uint res = src + dst; - - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_ADD_32(src, dst, res); - FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - *r_dst = FLAG_Z; -} - - -void m68k_op_add_32_er_pi(void) -{ - uint* r_dst = &DX; - uint src = OPER_AY_PI_32(); - uint dst = *r_dst; - uint res = src + dst; - - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_ADD_32(src, dst, res); - FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - *r_dst = FLAG_Z; -} - - -void m68k_op_add_32_er_pd(void) -{ - uint* r_dst = &DX; - uint src = OPER_AY_PD_32(); - uint dst = *r_dst; - uint res = src + dst; - - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_ADD_32(src, dst, res); - FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - *r_dst = FLAG_Z; -} - - -void m68k_op_add_32_er_di(void) -{ - uint* r_dst = &DX; - uint src = OPER_AY_DI_32(); - uint dst = *r_dst; - uint res = src + dst; - - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_ADD_32(src, dst, res); - FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - *r_dst = FLAG_Z; -} - - -void m68k_op_add_32_er_ix(void) -{ - uint* r_dst = &DX; - uint src = OPER_AY_IX_32(); - uint dst = *r_dst; - uint res = src + dst; - - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_ADD_32(src, dst, res); - FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - *r_dst = FLAG_Z; -} - - -void m68k_op_add_32_er_aw(void) -{ - uint* r_dst = &DX; - uint src = OPER_AW_32(); - uint dst = *r_dst; - uint res = src + dst; - - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_ADD_32(src, dst, res); - FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - *r_dst = FLAG_Z; -} - - -void m68k_op_add_32_er_al(void) -{ - uint* r_dst = &DX; - uint src = OPER_AL_32(); - uint dst = *r_dst; - uint res = src + dst; - - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_ADD_32(src, dst, res); - FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - *r_dst = FLAG_Z; -} - - -void m68k_op_add_32_er_pcdi(void) -{ - uint* r_dst = &DX; - uint src = OPER_PCDI_32(); - uint dst = *r_dst; - uint res = src + dst; - - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_ADD_32(src, dst, res); - FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - *r_dst = FLAG_Z; -} - - -void m68k_op_add_32_er_pcix(void) -{ - uint* r_dst = &DX; - uint src = OPER_PCIX_32(); - uint dst = *r_dst; - uint res = src + dst; - - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_ADD_32(src, dst, res); - FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - *r_dst = FLAG_Z; -} - - -void m68k_op_add_32_er_i(void) -{ - uint* r_dst = &DX; - uint src = OPER_I_32(); - uint dst = *r_dst; - uint res = src + dst; - - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_ADD_32(src, dst, res); - FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - *r_dst = FLAG_Z; -} - - -void m68k_op_add_8_re_ai(void) -{ - uint ea = EA_AY_AI_8(); - uint src = MASK_OUT_ABOVE_8(DX); - uint dst = m68ki_read_8(ea); - uint res = src + dst; - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_add_8_re_pi(void) -{ - uint ea = EA_AY_PI_8(); - uint src = MASK_OUT_ABOVE_8(DX); - uint dst = m68ki_read_8(ea); - uint res = src + dst; - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_add_8_re_pi7(void) -{ - uint ea = EA_A7_PI_8(); - uint src = MASK_OUT_ABOVE_8(DX); - uint dst = m68ki_read_8(ea); - uint res = src + dst; - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_add_8_re_pd(void) -{ - uint ea = EA_AY_PD_8(); - uint src = MASK_OUT_ABOVE_8(DX); - uint dst = m68ki_read_8(ea); - uint res = src + dst; - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_add_8_re_pd7(void) -{ - uint ea = EA_A7_PD_8(); - uint src = MASK_OUT_ABOVE_8(DX); - uint dst = m68ki_read_8(ea); - uint res = src + dst; - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_add_8_re_di(void) -{ - uint ea = EA_AY_DI_8(); - uint src = MASK_OUT_ABOVE_8(DX); - uint dst = m68ki_read_8(ea); - uint res = src + dst; - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_add_8_re_ix(void) -{ - uint ea = EA_AY_IX_8(); - uint src = MASK_OUT_ABOVE_8(DX); - uint dst = m68ki_read_8(ea); - uint res = src + dst; - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_add_8_re_aw(void) -{ - uint ea = EA_AW_8(); - uint src = MASK_OUT_ABOVE_8(DX); - uint dst = m68ki_read_8(ea); - uint res = src + dst; - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_add_8_re_al(void) -{ - uint ea = EA_AL_8(); - uint src = MASK_OUT_ABOVE_8(DX); - uint dst = m68ki_read_8(ea); - uint res = src + dst; - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_add_16_re_ai(void) -{ - uint ea = EA_AY_AI_16(); - uint src = MASK_OUT_ABOVE_16(DX); - uint dst = m68ki_read_16(ea); - uint res = src + dst; - - FLAG_N = NFLAG_16(res); - FLAG_V = VFLAG_ADD_16(src, dst, res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - m68ki_write_16(ea, FLAG_Z); -} - - -void m68k_op_add_16_re_pi(void) -{ - uint ea = EA_AY_PI_16(); - uint src = MASK_OUT_ABOVE_16(DX); - uint dst = m68ki_read_16(ea); - uint res = src + dst; - - FLAG_N = NFLAG_16(res); - FLAG_V = VFLAG_ADD_16(src, dst, res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - m68ki_write_16(ea, FLAG_Z); -} - - -void m68k_op_add_16_re_pd(void) -{ - uint ea = EA_AY_PD_16(); - uint src = MASK_OUT_ABOVE_16(DX); - uint dst = m68ki_read_16(ea); - uint res = src + dst; - - FLAG_N = NFLAG_16(res); - FLAG_V = VFLAG_ADD_16(src, dst, res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - m68ki_write_16(ea, FLAG_Z); -} - - -void m68k_op_add_16_re_di(void) -{ - uint ea = EA_AY_DI_16(); - uint src = MASK_OUT_ABOVE_16(DX); - uint dst = m68ki_read_16(ea); - uint res = src + dst; - - FLAG_N = NFLAG_16(res); - FLAG_V = VFLAG_ADD_16(src, dst, res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - m68ki_write_16(ea, FLAG_Z); -} - - -void m68k_op_add_16_re_ix(void) -{ - uint ea = EA_AY_IX_16(); - uint src = MASK_OUT_ABOVE_16(DX); - uint dst = m68ki_read_16(ea); - uint res = src + dst; - - FLAG_N = NFLAG_16(res); - FLAG_V = VFLAG_ADD_16(src, dst, res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - m68ki_write_16(ea, FLAG_Z); -} - - -void m68k_op_add_16_re_aw(void) -{ - uint ea = EA_AW_16(); - uint src = MASK_OUT_ABOVE_16(DX); - uint dst = m68ki_read_16(ea); - uint res = src + dst; - - FLAG_N = NFLAG_16(res); - FLAG_V = VFLAG_ADD_16(src, dst, res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - m68ki_write_16(ea, FLAG_Z); -} - - -void m68k_op_add_16_re_al(void) -{ - uint ea = EA_AL_16(); - uint src = MASK_OUT_ABOVE_16(DX); - uint dst = m68ki_read_16(ea); - uint res = src + dst; - - FLAG_N = NFLAG_16(res); - FLAG_V = VFLAG_ADD_16(src, dst, res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - m68ki_write_16(ea, FLAG_Z); -} - - -void m68k_op_add_32_re_ai(void) -{ - uint ea = EA_AY_AI_32(); - uint src = DX; - uint dst = m68ki_read_32(ea); - uint res = src + dst; - - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_ADD_32(src, dst, res); - FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - m68ki_write_32(ea, FLAG_Z); -} - - -void m68k_op_add_32_re_pi(void) -{ - uint ea = EA_AY_PI_32(); - uint src = DX; - uint dst = m68ki_read_32(ea); - uint res = src + dst; - - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_ADD_32(src, dst, res); - FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - m68ki_write_32(ea, FLAG_Z); -} - - -void m68k_op_add_32_re_pd(void) -{ - uint ea = EA_AY_PD_32(); - uint src = DX; - uint dst = m68ki_read_32(ea); - uint res = src + dst; - - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_ADD_32(src, dst, res); - FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - m68ki_write_32(ea, FLAG_Z); -} - - -void m68k_op_add_32_re_di(void) -{ - uint ea = EA_AY_DI_32(); - uint src = DX; - uint dst = m68ki_read_32(ea); - uint res = src + dst; - - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_ADD_32(src, dst, res); - FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - m68ki_write_32(ea, FLAG_Z); -} - - -void m68k_op_add_32_re_ix(void) -{ - uint ea = EA_AY_IX_32(); - uint src = DX; - uint dst = m68ki_read_32(ea); - uint res = src + dst; - - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_ADD_32(src, dst, res); - FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - m68ki_write_32(ea, FLAG_Z); -} - - -void m68k_op_add_32_re_aw(void) -{ - uint ea = EA_AW_32(); - uint src = DX; - uint dst = m68ki_read_32(ea); - uint res = src + dst; - - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_ADD_32(src, dst, res); - FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - m68ki_write_32(ea, FLAG_Z); -} - - -void m68k_op_add_32_re_al(void) -{ - uint ea = EA_AL_32(); - uint src = DX; - uint dst = m68ki_read_32(ea); - uint res = src + dst; - - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_ADD_32(src, dst, res); - FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - m68ki_write_32(ea, FLAG_Z); -} - - -void m68k_op_adda_16_d(void) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(DY)); -} - - -void m68k_op_adda_16_a(void) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(AY)); -} - - -void m68k_op_adda_16_ai(void) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(OPER_AY_AI_16())); -} - - -void m68k_op_adda_16_pi(void) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(OPER_AY_PI_16())); -} - - -void m68k_op_adda_16_pd(void) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(OPER_AY_PD_16())); -} - - -void m68k_op_adda_16_di(void) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(OPER_AY_DI_16())); -} - - -void m68k_op_adda_16_ix(void) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(OPER_AY_IX_16())); -} - - -void m68k_op_adda_16_aw(void) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(OPER_AW_16())); -} - - -void m68k_op_adda_16_al(void) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(OPER_AL_16())); -} - - -void m68k_op_adda_16_pcdi(void) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(OPER_PCDI_16())); -} - - -void m68k_op_adda_16_pcix(void) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(OPER_PCIX_16())); -} - - -void m68k_op_adda_16_i(void) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(OPER_I_16())); -} - - -void m68k_op_adda_32_d(void) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst + DY); -} - - -void m68k_op_adda_32_a(void) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst + AY); -} - - -void m68k_op_adda_32_ai(void) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst + OPER_AY_AI_32()); -} - - -void m68k_op_adda_32_pi(void) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst + OPER_AY_PI_32()); -} - - -void m68k_op_adda_32_pd(void) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst + OPER_AY_PD_32()); -} - - -void m68k_op_adda_32_di(void) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst + OPER_AY_DI_32()); -} - - -void m68k_op_adda_32_ix(void) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst + OPER_AY_IX_32()); -} - - -void m68k_op_adda_32_aw(void) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst + OPER_AW_32()); -} - - -void m68k_op_adda_32_al(void) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst + OPER_AL_32()); -} - - -void m68k_op_adda_32_pcdi(void) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst + OPER_PCDI_32()); -} - - -void m68k_op_adda_32_pcix(void) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst + OPER_PCIX_32()); -} - - -void m68k_op_adda_32_i(void) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst + OPER_I_32()); -} - - -void m68k_op_addi_8_d(void) -{ - uint* r_dst = &DY; - uint src = OPER_I_8(); - uint dst = MASK_OUT_ABOVE_8(*r_dst); - uint res = src + dst; - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; -} - - -void m68k_op_addi_8_ai(void) -{ - uint src = OPER_I_8(); - uint ea = EA_AY_AI_8(); - uint dst = m68ki_read_8(ea); - uint res = src + dst; - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_addi_8_pi(void) -{ - uint src = OPER_I_8(); - uint ea = EA_AY_PI_8(); - uint dst = m68ki_read_8(ea); - uint res = src + dst; - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_addi_8_pi7(void) -{ - uint src = OPER_I_8(); - uint ea = EA_A7_PI_8(); - uint dst = m68ki_read_8(ea); - uint res = src + dst; - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_addi_8_pd(void) -{ - uint src = OPER_I_8(); - uint ea = EA_AY_PD_8(); - uint dst = m68ki_read_8(ea); - uint res = src + dst; - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_addi_8_pd7(void) -{ - uint src = OPER_I_8(); - uint ea = EA_A7_PD_8(); - uint dst = m68ki_read_8(ea); - uint res = src + dst; - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_addi_8_di(void) -{ - uint src = OPER_I_8(); - uint ea = EA_AY_DI_8(); - uint dst = m68ki_read_8(ea); - uint res = src + dst; - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_addi_8_ix(void) -{ - uint src = OPER_I_8(); - uint ea = EA_AY_IX_8(); - uint dst = m68ki_read_8(ea); - uint res = src + dst; - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_addi_8_aw(void) -{ - uint src = OPER_I_8(); - uint ea = EA_AW_8(); - uint dst = m68ki_read_8(ea); - uint res = src + dst; - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_addi_8_al(void) -{ - uint src = OPER_I_8(); - uint ea = EA_AL_8(); - uint dst = m68ki_read_8(ea); - uint res = src + dst; - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_addi_16_d(void) -{ - uint* r_dst = &DY; - uint src = OPER_I_16(); - uint dst = MASK_OUT_ABOVE_16(*r_dst); - uint res = src + dst; - - FLAG_N = NFLAG_16(res); - FLAG_V = VFLAG_ADD_16(src, dst, res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; -} - - -void m68k_op_addi_16_ai(void) -{ - uint src = OPER_I_16(); - uint ea = EA_AY_AI_16(); - uint dst = m68ki_read_16(ea); - uint res = src + dst; - - FLAG_N = NFLAG_16(res); - FLAG_V = VFLAG_ADD_16(src, dst, res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - m68ki_write_16(ea, FLAG_Z); -} - - -void m68k_op_addi_16_pi(void) -{ - uint src = OPER_I_16(); - uint ea = EA_AY_PI_16(); - uint dst = m68ki_read_16(ea); - uint res = src + dst; - - FLAG_N = NFLAG_16(res); - FLAG_V = VFLAG_ADD_16(src, dst, res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - m68ki_write_16(ea, FLAG_Z); -} - - -void m68k_op_addi_16_pd(void) -{ - uint src = OPER_I_16(); - uint ea = EA_AY_PD_16(); - uint dst = m68ki_read_16(ea); - uint res = src + dst; - - FLAG_N = NFLAG_16(res); - FLAG_V = VFLAG_ADD_16(src, dst, res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - m68ki_write_16(ea, FLAG_Z); -} - - -void m68k_op_addi_16_di(void) -{ - uint src = OPER_I_16(); - uint ea = EA_AY_DI_16(); - uint dst = m68ki_read_16(ea); - uint res = src + dst; - - FLAG_N = NFLAG_16(res); - FLAG_V = VFLAG_ADD_16(src, dst, res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - m68ki_write_16(ea, FLAG_Z); -} - - -void m68k_op_addi_16_ix(void) -{ - uint src = OPER_I_16(); - uint ea = EA_AY_IX_16(); - uint dst = m68ki_read_16(ea); - uint res = src + dst; - - FLAG_N = NFLAG_16(res); - FLAG_V = VFLAG_ADD_16(src, dst, res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - m68ki_write_16(ea, FLAG_Z); -} - - -void m68k_op_addi_16_aw(void) -{ - uint src = OPER_I_16(); - uint ea = EA_AW_16(); - uint dst = m68ki_read_16(ea); - uint res = src + dst; - - FLAG_N = NFLAG_16(res); - FLAG_V = VFLAG_ADD_16(src, dst, res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - m68ki_write_16(ea, FLAG_Z); -} - - -void m68k_op_addi_16_al(void) -{ - uint src = OPER_I_16(); - uint ea = EA_AL_16(); - uint dst = m68ki_read_16(ea); - uint res = src + dst; - - FLAG_N = NFLAG_16(res); - FLAG_V = VFLAG_ADD_16(src, dst, res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - m68ki_write_16(ea, FLAG_Z); -} - - -void m68k_op_addi_32_d(void) -{ - uint* r_dst = &DY; - uint src = OPER_I_32(); - uint dst = *r_dst; - uint res = src + dst; - - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_ADD_32(src, dst, res); - FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - *r_dst = FLAG_Z; -} - - -void m68k_op_addi_32_ai(void) -{ - uint src = OPER_I_32(); - uint ea = EA_AY_AI_32(); - uint dst = m68ki_read_32(ea); - uint res = src + dst; - - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_ADD_32(src, dst, res); - FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - m68ki_write_32(ea, FLAG_Z); -} - - -void m68k_op_addi_32_pi(void) -{ - uint src = OPER_I_32(); - uint ea = EA_AY_PI_32(); - uint dst = m68ki_read_32(ea); - uint res = src + dst; - - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_ADD_32(src, dst, res); - FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - m68ki_write_32(ea, FLAG_Z); -} - - -void m68k_op_addi_32_pd(void) -{ - uint src = OPER_I_32(); - uint ea = EA_AY_PD_32(); - uint dst = m68ki_read_32(ea); - uint res = src + dst; - - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_ADD_32(src, dst, res); - FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - m68ki_write_32(ea, FLAG_Z); -} - - -void m68k_op_addi_32_di(void) -{ - uint src = OPER_I_32(); - uint ea = EA_AY_DI_32(); - uint dst = m68ki_read_32(ea); - uint res = src + dst; - - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_ADD_32(src, dst, res); - FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - m68ki_write_32(ea, FLAG_Z); -} - - -void m68k_op_addi_32_ix(void) -{ - uint src = OPER_I_32(); - uint ea = EA_AY_IX_32(); - uint dst = m68ki_read_32(ea); - uint res = src + dst; - - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_ADD_32(src, dst, res); - FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - m68ki_write_32(ea, FLAG_Z); -} - - -void m68k_op_addi_32_aw(void) -{ - uint src = OPER_I_32(); - uint ea = EA_AW_32(); - uint dst = m68ki_read_32(ea); - uint res = src + dst; - - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_ADD_32(src, dst, res); - FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - m68ki_write_32(ea, FLAG_Z); -} - - -void m68k_op_addi_32_al(void) -{ - uint src = OPER_I_32(); - uint ea = EA_AL_32(); - uint dst = m68ki_read_32(ea); - uint res = src + dst; - - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_ADD_32(src, dst, res); - FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - m68ki_write_32(ea, FLAG_Z); -} - - -void m68k_op_addq_8_d(void) -{ - uint* r_dst = &DY; - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint dst = MASK_OUT_ABOVE_8(*r_dst); - uint res = src + dst; - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; -} - - -void m68k_op_addq_8_ai(void) -{ - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint ea = EA_AY_AI_8(); - uint dst = m68ki_read_8(ea); - uint res = src + dst; - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_addq_8_pi(void) -{ - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint ea = EA_AY_PI_8(); - uint dst = m68ki_read_8(ea); - uint res = src + dst; - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_addq_8_pi7(void) -{ - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint ea = EA_A7_PI_8(); - uint dst = m68ki_read_8(ea); - uint res = src + dst; - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_addq_8_pd(void) -{ - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint ea = EA_AY_PD_8(); - uint dst = m68ki_read_8(ea); - uint res = src + dst; - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_addq_8_pd7(void) -{ - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint ea = EA_A7_PD_8(); - uint dst = m68ki_read_8(ea); - uint res = src + dst; - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_addq_8_di(void) -{ - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint ea = EA_AY_DI_8(); - uint dst = m68ki_read_8(ea); - uint res = src + dst; - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_addq_8_ix(void) -{ - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint ea = EA_AY_IX_8(); - uint dst = m68ki_read_8(ea); - uint res = src + dst; - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_addq_8_aw(void) -{ - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint ea = EA_AW_8(); - uint dst = m68ki_read_8(ea); - uint res = src + dst; - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_addq_8_al(void) -{ - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint ea = EA_AL_8(); - uint dst = m68ki_read_8(ea); - uint res = src + dst; - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_addq_16_d(void) -{ - uint* r_dst = &DY; - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint dst = MASK_OUT_ABOVE_16(*r_dst); - uint res = src + dst; - - FLAG_N = NFLAG_16(res); - FLAG_V = VFLAG_ADD_16(src, dst, res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; -} - - -void m68k_op_addq_16_a(void) -{ - uint* r_dst = &AY; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1); -} - - -void m68k_op_addq_16_ai(void) -{ - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint ea = EA_AY_AI_16(); - uint dst = m68ki_read_16(ea); - uint res = src + dst; - - FLAG_N = NFLAG_16(res); - FLAG_V = VFLAG_ADD_16(src, dst, res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - m68ki_write_16(ea, FLAG_Z); -} - - -void m68k_op_addq_16_pi(void) -{ - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint ea = EA_AY_PI_16(); - uint dst = m68ki_read_16(ea); - uint res = src + dst; - - FLAG_N = NFLAG_16(res); - FLAG_V = VFLAG_ADD_16(src, dst, res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - m68ki_write_16(ea, FLAG_Z); -} - - -void m68k_op_addq_16_pd(void) -{ - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint ea = EA_AY_PD_16(); - uint dst = m68ki_read_16(ea); - uint res = src + dst; - - FLAG_N = NFLAG_16(res); - FLAG_V = VFLAG_ADD_16(src, dst, res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - m68ki_write_16(ea, FLAG_Z); -} - - -void m68k_op_addq_16_di(void) -{ - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint ea = EA_AY_DI_16(); - uint dst = m68ki_read_16(ea); - uint res = src + dst; - - FLAG_N = NFLAG_16(res); - FLAG_V = VFLAG_ADD_16(src, dst, res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - m68ki_write_16(ea, FLAG_Z); -} - - -void m68k_op_addq_16_ix(void) -{ - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint ea = EA_AY_IX_16(); - uint dst = m68ki_read_16(ea); - uint res = src + dst; - - FLAG_N = NFLAG_16(res); - FLAG_V = VFLAG_ADD_16(src, dst, res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - m68ki_write_16(ea, FLAG_Z); -} - - -void m68k_op_addq_16_aw(void) -{ - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint ea = EA_AW_16(); - uint dst = m68ki_read_16(ea); - uint res = src + dst; - - FLAG_N = NFLAG_16(res); - FLAG_V = VFLAG_ADD_16(src, dst, res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - m68ki_write_16(ea, FLAG_Z); -} - - -void m68k_op_addq_16_al(void) -{ - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint ea = EA_AL_16(); - uint dst = m68ki_read_16(ea); - uint res = src + dst; - - FLAG_N = NFLAG_16(res); - FLAG_V = VFLAG_ADD_16(src, dst, res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - m68ki_write_16(ea, FLAG_Z); -} - - -void m68k_op_addq_32_d(void) -{ - uint* r_dst = &DY; - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint dst = *r_dst; - uint res = src + dst; - - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_ADD_32(src, dst, res); - FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - *r_dst = FLAG_Z; -} - - -void m68k_op_addq_32_a(void) -{ - uint* r_dst = &AY; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1); -} - - -void m68k_op_addq_32_ai(void) -{ - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint ea = EA_AY_AI_32(); - uint dst = m68ki_read_32(ea); - uint res = src + dst; - - - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_ADD_32(src, dst, res); - FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - m68ki_write_32(ea, FLAG_Z); -} - - -void m68k_op_addq_32_pi(void) -{ - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint ea = EA_AY_PI_32(); - uint dst = m68ki_read_32(ea); - uint res = src + dst; - - - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_ADD_32(src, dst, res); - FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - m68ki_write_32(ea, FLAG_Z); -} - - -void m68k_op_addq_32_pd(void) -{ - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint ea = EA_AY_PD_32(); - uint dst = m68ki_read_32(ea); - uint res = src + dst; - - - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_ADD_32(src, dst, res); - FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - m68ki_write_32(ea, FLAG_Z); -} - - -void m68k_op_addq_32_di(void) -{ - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint ea = EA_AY_DI_32(); - uint dst = m68ki_read_32(ea); - uint res = src + dst; - - - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_ADD_32(src, dst, res); - FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - m68ki_write_32(ea, FLAG_Z); -} - - -void m68k_op_addq_32_ix(void) -{ - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint ea = EA_AY_IX_32(); - uint dst = m68ki_read_32(ea); - uint res = src + dst; - - - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_ADD_32(src, dst, res); - FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - m68ki_write_32(ea, FLAG_Z); -} - - -void m68k_op_addq_32_aw(void) -{ - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint ea = EA_AW_32(); - uint dst = m68ki_read_32(ea); - uint res = src + dst; - - - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_ADD_32(src, dst, res); - FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - m68ki_write_32(ea, FLAG_Z); -} - - -void m68k_op_addq_32_al(void) -{ - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint ea = EA_AL_32(); - uint dst = m68ki_read_32(ea); - uint res = src + dst; - - - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_ADD_32(src, dst, res); - FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - m68ki_write_32(ea, FLAG_Z); -} - - -void m68k_op_addx_8_rr(void) -{ - uint* r_dst = &DX; - uint src = MASK_OUT_ABOVE_8(DY); - uint dst = MASK_OUT_ABOVE_8(*r_dst); - uint res = src + dst + XFLAG_AS_1(); - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - - res = MASK_OUT_ABOVE_8(res); - FLAG_Z |= res; - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; -} - - -void m68k_op_addx_16_rr(void) -{ - uint* r_dst = &DX; - uint src = MASK_OUT_ABOVE_16(DY); - uint dst = MASK_OUT_ABOVE_16(*r_dst); - uint res = src + dst + XFLAG_AS_1(); - - FLAG_N = NFLAG_16(res); - FLAG_V = VFLAG_ADD_16(src, dst, res); - FLAG_X = FLAG_C = CFLAG_16(res); - - res = MASK_OUT_ABOVE_16(res); - FLAG_Z |= res; - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; -} - - -void m68k_op_addx_32_rr(void) -{ - uint* r_dst = &DX; - uint src = DY; - uint dst = *r_dst; - uint res = src + dst + XFLAG_AS_1(); - - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_ADD_32(src, dst, res); - FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); - - res = MASK_OUT_ABOVE_32(res); - FLAG_Z |= res; - - *r_dst = res; -} - - -void m68k_op_addx_8_mm_ax7(void) -{ - uint src = OPER_AY_PD_8(); - uint ea = EA_A7_PD_8(); - uint dst = m68ki_read_8(ea); - uint res = src + dst + XFLAG_AS_1(); - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - - res = MASK_OUT_ABOVE_8(res); - FLAG_Z |= res; - - m68ki_write_8(ea, res); -} - - -void m68k_op_addx_8_mm_ay7(void) -{ - uint src = OPER_A7_PD_8(); - uint ea = EA_AX_PD_8(); - uint dst = m68ki_read_8(ea); - uint res = src + dst + XFLAG_AS_1(); - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - - res = MASK_OUT_ABOVE_8(res); - FLAG_Z |= res; - - m68ki_write_8(ea, res); -} - - -void m68k_op_addx_8_mm_axy7(void) -{ - uint src = OPER_A7_PD_8(); - uint ea = EA_A7_PD_8(); - uint dst = m68ki_read_8(ea); - uint res = src + dst + XFLAG_AS_1(); - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - - res = MASK_OUT_ABOVE_8(res); - FLAG_Z |= res; - - m68ki_write_8(ea, res); -} - - -void m68k_op_addx_8_mm(void) -{ - uint src = OPER_AY_PD_8(); - uint ea = EA_AX_PD_8(); - uint dst = m68ki_read_8(ea); - uint res = src + dst + XFLAG_AS_1(); - - FLAG_N = NFLAG_8(res); - FLAG_V = VFLAG_ADD_8(src, dst, res); - FLAG_X = FLAG_C = CFLAG_8(res); - - res = MASK_OUT_ABOVE_8(res); - FLAG_Z |= res; - - m68ki_write_8(ea, res); -} - - -void m68k_op_addx_16_mm(void) -{ - uint src = OPER_AY_PD_16(); - uint ea = EA_AX_PD_16(); - uint dst = m68ki_read_16(ea); - uint res = src + dst + XFLAG_AS_1(); - - FLAG_N = NFLAG_16(res); - FLAG_V = VFLAG_ADD_16(src, dst, res); - FLAG_X = FLAG_C = CFLAG_16(res); - - res = MASK_OUT_ABOVE_16(res); - FLAG_Z |= res; - - m68ki_write_16(ea, res); -} - - -void m68k_op_addx_32_mm(void) -{ - uint src = OPER_AY_PD_32(); - uint ea = EA_AX_PD_32(); - uint dst = m68ki_read_32(ea); - uint res = src + dst + XFLAG_AS_1(); - - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_ADD_32(src, dst, res); - FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); - - res = MASK_OUT_ABOVE_32(res); - FLAG_Z |= res; - - m68ki_write_32(ea, res); -} - - -void m68k_op_and_8_er_d(void) -{ - FLAG_Z = MASK_OUT_ABOVE_8(DX &= (DY | 0xffffff00)); - - FLAG_N = NFLAG_8(FLAG_Z); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_and_8_er_ai(void) -{ - FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_AY_AI_8() | 0xffffff00)); - - FLAG_N = NFLAG_8(FLAG_Z); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_and_8_er_pi(void) -{ - FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_AY_PI_8() | 0xffffff00)); - - FLAG_N = NFLAG_8(FLAG_Z); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_and_8_er_pi7(void) -{ - FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_A7_PI_8() | 0xffffff00)); - - FLAG_N = NFLAG_8(FLAG_Z); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_and_8_er_pd(void) -{ - FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_AY_PD_8() | 0xffffff00)); - - FLAG_N = NFLAG_8(FLAG_Z); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_and_8_er_pd7(void) -{ - FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_A7_PD_8() | 0xffffff00)); - - FLAG_N = NFLAG_8(FLAG_Z); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_and_8_er_di(void) -{ - FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_AY_DI_8() | 0xffffff00)); - - FLAG_N = NFLAG_8(FLAG_Z); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_and_8_er_ix(void) -{ - FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_AY_IX_8() | 0xffffff00)); - - FLAG_N = NFLAG_8(FLAG_Z); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_and_8_er_aw(void) -{ - FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_AW_8() | 0xffffff00)); - - FLAG_N = NFLAG_8(FLAG_Z); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_and_8_er_al(void) -{ - FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_AL_8() | 0xffffff00)); - - FLAG_N = NFLAG_8(FLAG_Z); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_and_8_er_pcdi(void) -{ - FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_PCDI_8() | 0xffffff00)); - - FLAG_N = NFLAG_8(FLAG_Z); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_and_8_er_pcix(void) -{ - FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_PCIX_8() | 0xffffff00)); - - FLAG_N = NFLAG_8(FLAG_Z); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_and_8_er_i(void) -{ - FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_I_8() | 0xffffff00)); - - FLAG_N = NFLAG_8(FLAG_Z); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_and_16_er_d(void) -{ - FLAG_Z = MASK_OUT_ABOVE_16(DX &= (DY | 0xffff0000)); - - FLAG_N = NFLAG_16(FLAG_Z); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_and_16_er_ai(void) -{ - FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_AY_AI_16() | 0xffff0000)); - - FLAG_N = NFLAG_16(FLAG_Z); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_and_16_er_pi(void) -{ - FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_AY_PI_16() | 0xffff0000)); - - FLAG_N = NFLAG_16(FLAG_Z); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_and_16_er_pd(void) -{ - FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_AY_PD_16() | 0xffff0000)); - - FLAG_N = NFLAG_16(FLAG_Z); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_and_16_er_di(void) -{ - FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_AY_DI_16() | 0xffff0000)); - - FLAG_N = NFLAG_16(FLAG_Z); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_and_16_er_ix(void) -{ - FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_AY_IX_16() | 0xffff0000)); - - FLAG_N = NFLAG_16(FLAG_Z); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_and_16_er_aw(void) -{ - FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_AW_16() | 0xffff0000)); - - FLAG_N = NFLAG_16(FLAG_Z); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_and_16_er_al(void) -{ - FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_AL_16() | 0xffff0000)); - - FLAG_N = NFLAG_16(FLAG_Z); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_and_16_er_pcdi(void) -{ - FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_PCDI_16() | 0xffff0000)); - - FLAG_N = NFLAG_16(FLAG_Z); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_and_16_er_pcix(void) -{ - FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_PCIX_16() | 0xffff0000)); - - FLAG_N = NFLAG_16(FLAG_Z); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_and_16_er_i(void) -{ - FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_I_16() | 0xffff0000)); - - FLAG_N = NFLAG_16(FLAG_Z); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_and_32_er_d(void) -{ - FLAG_Z = DX &= DY; - - FLAG_N = NFLAG_32(FLAG_Z); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_and_32_er_ai(void) -{ - FLAG_Z = DX &= OPER_AY_AI_32(); - - FLAG_N = NFLAG_32(FLAG_Z); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_and_32_er_pi(void) -{ - FLAG_Z = DX &= OPER_AY_PI_32(); - - FLAG_N = NFLAG_32(FLAG_Z); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_and_32_er_pd(void) -{ - FLAG_Z = DX &= OPER_AY_PD_32(); - - FLAG_N = NFLAG_32(FLAG_Z); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_and_32_er_di(void) -{ - FLAG_Z = DX &= OPER_AY_DI_32(); - - FLAG_N = NFLAG_32(FLAG_Z); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_and_32_er_ix(void) -{ - FLAG_Z = DX &= OPER_AY_IX_32(); - - FLAG_N = NFLAG_32(FLAG_Z); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_and_32_er_aw(void) -{ - FLAG_Z = DX &= OPER_AW_32(); - - FLAG_N = NFLAG_32(FLAG_Z); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_and_32_er_al(void) -{ - FLAG_Z = DX &= OPER_AL_32(); - - FLAG_N = NFLAG_32(FLAG_Z); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_and_32_er_pcdi(void) -{ - FLAG_Z = DX &= OPER_PCDI_32(); - - FLAG_N = NFLAG_32(FLAG_Z); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_and_32_er_pcix(void) -{ - FLAG_Z = DX &= OPER_PCIX_32(); - - FLAG_N = NFLAG_32(FLAG_Z); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_and_32_er_i(void) -{ - FLAG_Z = DX &= OPER_I_32(); - - FLAG_N = NFLAG_32(FLAG_Z); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_and_8_re_ai(void) -{ - uint ea = EA_AY_AI_8(); - uint res = DX & m68ki_read_8(ea); - - FLAG_N = NFLAG_8(res); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_Z = MASK_OUT_ABOVE_8(res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_and_8_re_pi(void) -{ - uint ea = EA_AY_PI_8(); - uint res = DX & m68ki_read_8(ea); - - FLAG_N = NFLAG_8(res); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_Z = MASK_OUT_ABOVE_8(res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_and_8_re_pi7(void) -{ - uint ea = EA_A7_PI_8(); - uint res = DX & m68ki_read_8(ea); - - FLAG_N = NFLAG_8(res); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_Z = MASK_OUT_ABOVE_8(res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_and_8_re_pd(void) -{ - uint ea = EA_AY_PD_8(); - uint res = DX & m68ki_read_8(ea); - - FLAG_N = NFLAG_8(res); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_Z = MASK_OUT_ABOVE_8(res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_and_8_re_pd7(void) -{ - uint ea = EA_A7_PD_8(); - uint res = DX & m68ki_read_8(ea); - - FLAG_N = NFLAG_8(res); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_Z = MASK_OUT_ABOVE_8(res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_and_8_re_di(void) -{ - uint ea = EA_AY_DI_8(); - uint res = DX & m68ki_read_8(ea); - - FLAG_N = NFLAG_8(res); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_Z = MASK_OUT_ABOVE_8(res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_and_8_re_ix(void) -{ - uint ea = EA_AY_IX_8(); - uint res = DX & m68ki_read_8(ea); - - FLAG_N = NFLAG_8(res); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_Z = MASK_OUT_ABOVE_8(res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_and_8_re_aw(void) -{ - uint ea = EA_AW_8(); - uint res = DX & m68ki_read_8(ea); - - FLAG_N = NFLAG_8(res); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_Z = MASK_OUT_ABOVE_8(res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_and_8_re_al(void) -{ - uint ea = EA_AL_8(); - uint res = DX & m68ki_read_8(ea); - - FLAG_N = NFLAG_8(res); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_Z = MASK_OUT_ABOVE_8(res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_and_16_re_ai(void) -{ - uint ea = EA_AY_AI_16(); - uint res = DX & m68ki_read_16(ea); - - FLAG_N = NFLAG_16(res); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_Z = MASK_OUT_ABOVE_16(res); - - m68ki_write_16(ea, FLAG_Z); -} - - -void m68k_op_and_16_re_pi(void) -{ - uint ea = EA_AY_PI_16(); - uint res = DX & m68ki_read_16(ea); - - FLAG_N = NFLAG_16(res); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_Z = MASK_OUT_ABOVE_16(res); - - m68ki_write_16(ea, FLAG_Z); -} - - -void m68k_op_and_16_re_pd(void) -{ - uint ea = EA_AY_PD_16(); - uint res = DX & m68ki_read_16(ea); - - FLAG_N = NFLAG_16(res); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_Z = MASK_OUT_ABOVE_16(res); - - m68ki_write_16(ea, FLAG_Z); -} - - -void m68k_op_and_16_re_di(void) -{ - uint ea = EA_AY_DI_16(); - uint res = DX & m68ki_read_16(ea); - - FLAG_N = NFLAG_16(res); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_Z = MASK_OUT_ABOVE_16(res); - - m68ki_write_16(ea, FLAG_Z); -} - - -void m68k_op_and_16_re_ix(void) -{ - uint ea = EA_AY_IX_16(); - uint res = DX & m68ki_read_16(ea); - - FLAG_N = NFLAG_16(res); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_Z = MASK_OUT_ABOVE_16(res); - - m68ki_write_16(ea, FLAG_Z); -} - - -void m68k_op_and_16_re_aw(void) -{ - uint ea = EA_AW_16(); - uint res = DX & m68ki_read_16(ea); - - FLAG_N = NFLAG_16(res); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_Z = MASK_OUT_ABOVE_16(res); - - m68ki_write_16(ea, FLAG_Z); -} - - -void m68k_op_and_16_re_al(void) -{ - uint ea = EA_AL_16(); - uint res = DX & m68ki_read_16(ea); - - FLAG_N = NFLAG_16(res); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_Z = MASK_OUT_ABOVE_16(res); - - m68ki_write_16(ea, FLAG_Z); -} - - -void m68k_op_and_32_re_ai(void) -{ - uint ea = EA_AY_AI_32(); - uint res = DX & m68ki_read_32(ea); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - - m68ki_write_32(ea, res); -} - - -void m68k_op_and_32_re_pi(void) -{ - uint ea = EA_AY_PI_32(); - uint res = DX & m68ki_read_32(ea); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - - m68ki_write_32(ea, res); -} - - -void m68k_op_and_32_re_pd(void) -{ - uint ea = EA_AY_PD_32(); - uint res = DX & m68ki_read_32(ea); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - - m68ki_write_32(ea, res); -} - - -void m68k_op_and_32_re_di(void) -{ - uint ea = EA_AY_DI_32(); - uint res = DX & m68ki_read_32(ea); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - - m68ki_write_32(ea, res); -} - - -void m68k_op_and_32_re_ix(void) -{ - uint ea = EA_AY_IX_32(); - uint res = DX & m68ki_read_32(ea); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - - m68ki_write_32(ea, res); -} - - -void m68k_op_and_32_re_aw(void) -{ - uint ea = EA_AW_32(); - uint res = DX & m68ki_read_32(ea); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - - m68ki_write_32(ea, res); -} - - -void m68k_op_and_32_re_al(void) -{ - uint ea = EA_AL_32(); - uint res = DX & m68ki_read_32(ea); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - - m68ki_write_32(ea, res); -} - - -void m68k_op_andi_8_d(void) -{ - FLAG_Z = MASK_OUT_ABOVE_8(DY &= (OPER_I_8() | 0xffffff00)); - - FLAG_N = NFLAG_8(FLAG_Z); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_andi_8_ai(void) -{ - uint src = OPER_I_8(); - uint ea = EA_AY_AI_8(); - uint res = src & m68ki_read_8(ea); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - - m68ki_write_8(ea, res); -} - - -void m68k_op_andi_8_pi(void) -{ - uint src = OPER_I_8(); - uint ea = EA_AY_PI_8(); - uint res = src & m68ki_read_8(ea); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - - m68ki_write_8(ea, res); -} - - -void m68k_op_andi_8_pi7(void) -{ - uint src = OPER_I_8(); - uint ea = EA_A7_PI_8(); - uint res = src & m68ki_read_8(ea); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - - m68ki_write_8(ea, res); -} - - -void m68k_op_andi_8_pd(void) -{ - uint src = OPER_I_8(); - uint ea = EA_AY_PD_8(); - uint res = src & m68ki_read_8(ea); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - - m68ki_write_8(ea, res); -} - - -void m68k_op_andi_8_pd7(void) -{ - uint src = OPER_I_8(); - uint ea = EA_A7_PD_8(); - uint res = src & m68ki_read_8(ea); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - - m68ki_write_8(ea, res); -} - - -void m68k_op_andi_8_di(void) -{ - uint src = OPER_I_8(); - uint ea = EA_AY_DI_8(); - uint res = src & m68ki_read_8(ea); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - - m68ki_write_8(ea, res); -} - - -void m68k_op_andi_8_ix(void) -{ - uint src = OPER_I_8(); - uint ea = EA_AY_IX_8(); - uint res = src & m68ki_read_8(ea); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - - m68ki_write_8(ea, res); -} - - -void m68k_op_andi_8_aw(void) -{ - uint src = OPER_I_8(); - uint ea = EA_AW_8(); - uint res = src & m68ki_read_8(ea); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - - m68ki_write_8(ea, res); -} - - -void m68k_op_andi_8_al(void) -{ - uint src = OPER_I_8(); - uint ea = EA_AL_8(); - uint res = src & m68ki_read_8(ea); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - - m68ki_write_8(ea, res); -} - - -void m68k_op_andi_16_d(void) -{ - FLAG_Z = MASK_OUT_ABOVE_16(DY &= (OPER_I_16() | 0xffff0000)); - - FLAG_N = NFLAG_16(FLAG_Z); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_andi_16_ai(void) -{ - uint src = OPER_I_16(); - uint ea = EA_AY_AI_16(); - uint res = src & m68ki_read_16(ea); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - - m68ki_write_16(ea, res); -} - - -void m68k_op_andi_16_pi(void) -{ - uint src = OPER_I_16(); - uint ea = EA_AY_PI_16(); - uint res = src & m68ki_read_16(ea); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - - m68ki_write_16(ea, res); -} - - -void m68k_op_andi_16_pd(void) -{ - uint src = OPER_I_16(); - uint ea = EA_AY_PD_16(); - uint res = src & m68ki_read_16(ea); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - - m68ki_write_16(ea, res); -} - - -void m68k_op_andi_16_di(void) -{ - uint src = OPER_I_16(); - uint ea = EA_AY_DI_16(); - uint res = src & m68ki_read_16(ea); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - - m68ki_write_16(ea, res); -} - - -void m68k_op_andi_16_ix(void) -{ - uint src = OPER_I_16(); - uint ea = EA_AY_IX_16(); - uint res = src & m68ki_read_16(ea); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - - m68ki_write_16(ea, res); -} - - -void m68k_op_andi_16_aw(void) -{ - uint src = OPER_I_16(); - uint ea = EA_AW_16(); - uint res = src & m68ki_read_16(ea); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - - m68ki_write_16(ea, res); -} - - -void m68k_op_andi_16_al(void) -{ - uint src = OPER_I_16(); - uint ea = EA_AL_16(); - uint res = src & m68ki_read_16(ea); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - - m68ki_write_16(ea, res); -} - - -void m68k_op_andi_32_d(void) -{ - FLAG_Z = DY &= (OPER_I_32()); - - FLAG_N = NFLAG_32(FLAG_Z); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_andi_32_ai(void) -{ - uint src = OPER_I_32(); - uint ea = EA_AY_AI_32(); - uint res = src & m68ki_read_32(ea); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - - m68ki_write_32(ea, res); -} - - -void m68k_op_andi_32_pi(void) -{ - uint src = OPER_I_32(); - uint ea = EA_AY_PI_32(); - uint res = src & m68ki_read_32(ea); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - - m68ki_write_32(ea, res); -} - - -void m68k_op_andi_32_pd(void) -{ - uint src = OPER_I_32(); - uint ea = EA_AY_PD_32(); - uint res = src & m68ki_read_32(ea); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - - m68ki_write_32(ea, res); -} - - -void m68k_op_andi_32_di(void) -{ - uint src = OPER_I_32(); - uint ea = EA_AY_DI_32(); - uint res = src & m68ki_read_32(ea); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - - m68ki_write_32(ea, res); -} - - -void m68k_op_andi_32_ix(void) -{ - uint src = OPER_I_32(); - uint ea = EA_AY_IX_32(); - uint res = src & m68ki_read_32(ea); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - - m68ki_write_32(ea, res); -} - - -void m68k_op_andi_32_aw(void) -{ - uint src = OPER_I_32(); - uint ea = EA_AW_32(); - uint res = src & m68ki_read_32(ea); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - - m68ki_write_32(ea, res); -} - - -void m68k_op_andi_32_al(void) -{ - uint src = OPER_I_32(); - uint ea = EA_AL_32(); - uint res = src & m68ki_read_32(ea); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - - m68ki_write_32(ea, res); -} - - -void m68k_op_andi_16_toc(void) -{ - m68ki_set_ccr(m68ki_get_ccr() & OPER_I_16()); -} - - -void m68k_op_andi_16_tos(void) -{ - if(FLAG_S) - { - uint src = OPER_I_16(); - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_set_sr(m68ki_get_sr() & src); - return; - } - m68ki_exception_privilege_violation(); -} - - -void m68k_op_asr_8_s(void) -{ - uint* r_dst = &DY; - uint shift = (((REG_IR >> 9) - 1) & 7) + 1; - uint src = MASK_OUT_ABOVE_8(*r_dst); - uint res = src >> shift; - - if(GET_MSB_8(src)) - res |= m68ki_shift_8_table[shift]; - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_X = FLAG_C = src << (9-shift); -} - - -void m68k_op_asr_16_s(void) -{ - uint* r_dst = &DY; - uint shift = (((REG_IR >> 9) - 1) & 7) + 1; - uint src = MASK_OUT_ABOVE_16(*r_dst); - uint res = src >> shift; - - if(GET_MSB_16(src)) - res |= m68ki_shift_16_table[shift]; - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_X = FLAG_C = src << (9-shift); -} - - -void m68k_op_asr_32_s(void) -{ - uint* r_dst = &DY; - uint shift = (((REG_IR >> 9) - 1) & 7) + 1; - uint src = *r_dst; - uint res = src >> shift; - - if(GET_MSB_32(src)) - res |= m68ki_shift_32_table[shift]; - - *r_dst = res; - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_X = FLAG_C = src << (9-shift); -} - - -void m68k_op_asr_8_r(void) -{ - uint* r_dst = &DY; - uint shift = DX & 0x3f; - uint src = MASK_OUT_ABOVE_8(*r_dst); - uint res = src >> shift; - - if(shift != 0) - { - USE_CYCLES(shift<> shift; - - if(shift != 0) - { - USE_CYCLES(shift<> (shift - 1))<<8; - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - return; - } - - if(GET_MSB_16(src)) - { - *r_dst |= 0xffff; - FLAG_C = CFLAG_SET; - FLAG_X = XFLAG_SET; - FLAG_N = NFLAG_SET; - FLAG_Z = ZFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - return; - } - - *r_dst &= 0xffff0000; - FLAG_C = CFLAG_CLEAR; - FLAG_X = XFLAG_CLEAR; - FLAG_N = NFLAG_CLEAR; - FLAG_Z = ZFLAG_SET; - FLAG_V = VFLAG_CLEAR; - return; - } - - FLAG_C = CFLAG_CLEAR; - FLAG_N = NFLAG_16(src); - FLAG_Z = src; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_asr_32_r(void) -{ - uint* r_dst = &DY; - uint shift = DX & 0x3f; - uint src = *r_dst; - uint res = src >> shift; - - if(shift != 0) - { - USE_CYCLES(shift<> (shift - 1))<<8; - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - return; - } - - if(GET_MSB_32(src)) - { - *r_dst = 0xffffffff; - FLAG_C = CFLAG_SET; - FLAG_X = XFLAG_SET; - FLAG_N = NFLAG_SET; - FLAG_Z = ZFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - return; - } - - *r_dst = 0; - FLAG_C = CFLAG_CLEAR; - FLAG_X = XFLAG_CLEAR; - FLAG_N = NFLAG_CLEAR; - FLAG_Z = ZFLAG_SET; - FLAG_V = VFLAG_CLEAR; - return; - } - - FLAG_C = CFLAG_CLEAR; - FLAG_N = NFLAG_32(src); - FLAG_Z = src; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_asr_16_ai(void) -{ - uint ea = EA_AY_AI_16(); - uint src = m68ki_read_16(ea); - uint res = src >> 1; - - if(GET_MSB_16(src)) - res |= 0x8000; - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = FLAG_X = src << 8; -} - - -void m68k_op_asr_16_pi(void) -{ - uint ea = EA_AY_PI_16(); - uint src = m68ki_read_16(ea); - uint res = src >> 1; - - if(GET_MSB_16(src)) - res |= 0x8000; - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = FLAG_X = src << 8; -} - - -void m68k_op_asr_16_pd(void) -{ - uint ea = EA_AY_PD_16(); - uint src = m68ki_read_16(ea); - uint res = src >> 1; - - if(GET_MSB_16(src)) - res |= 0x8000; - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = FLAG_X = src << 8; -} - - -void m68k_op_asr_16_di(void) -{ - uint ea = EA_AY_DI_16(); - uint src = m68ki_read_16(ea); - uint res = src >> 1; - - if(GET_MSB_16(src)) - res |= 0x8000; - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = FLAG_X = src << 8; -} - - -void m68k_op_asr_16_ix(void) -{ - uint ea = EA_AY_IX_16(); - uint src = m68ki_read_16(ea); - uint res = src >> 1; - - if(GET_MSB_16(src)) - res |= 0x8000; - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = FLAG_X = src << 8; -} - - -void m68k_op_asr_16_aw(void) -{ - uint ea = EA_AW_16(); - uint src = m68ki_read_16(ea); - uint res = src >> 1; - - if(GET_MSB_16(src)) - res |= 0x8000; - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = FLAG_X = src << 8; -} - - -void m68k_op_asr_16_al(void) -{ - uint ea = EA_AL_16(); - uint src = m68ki_read_16(ea); - uint res = src >> 1; - - if(GET_MSB_16(src)) - res |= 0x8000; - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = FLAG_X = src << 8; -} - - -void m68k_op_asl_8_s(void) -{ - uint* r_dst = &DY; - uint shift = (((REG_IR >> 9) - 1) & 7) + 1; - uint src = MASK_OUT_ABOVE_8(*r_dst); - uint res = MASK_OUT_ABOVE_8(src << shift); - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; - - FLAG_X = FLAG_C = src << shift; - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - src &= m68ki_shift_8_table[shift + 1]; - FLAG_V = (!(src == 0 || (src == m68ki_shift_8_table[shift + 1] && shift < 8)))<<7; -} - - -void m68k_op_asl_16_s(void) -{ - uint* r_dst = &DY; - uint shift = (((REG_IR >> 9) - 1) & 7) + 1; - uint src = MASK_OUT_ABOVE_16(*r_dst); - uint res = MASK_OUT_ABOVE_16(src << shift); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_X = FLAG_C = src >> (8-shift); - src &= m68ki_shift_16_table[shift + 1]; - FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7; -} - - -void m68k_op_asl_32_s(void) -{ - uint* r_dst = &DY; - uint shift = (((REG_IR >> 9) - 1) & 7) + 1; - uint src = *r_dst; - uint res = MASK_OUT_ABOVE_32(src << shift); - - *r_dst = res; - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_X = FLAG_C = src >> (24-shift); - src &= m68ki_shift_32_table[shift + 1]; - FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7; -} - - -void m68k_op_asl_8_r(void) -{ - uint* r_dst = &DY; - uint shift = DX & 0x3f; - uint src = MASK_OUT_ABOVE_8(*r_dst); - uint res = MASK_OUT_ABOVE_8(src << shift); - - if(shift != 0) - { - USE_CYCLES(shift<> 8; - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - src &= m68ki_shift_16_table[shift + 1]; - FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7; - return; - } - - *r_dst &= 0xffff0000; - FLAG_X = FLAG_C = ((shift == 16 ? src & 1 : 0))<<8; - FLAG_N = NFLAG_CLEAR; - FLAG_Z = ZFLAG_SET; - FLAG_V = (!(src == 0))<<7; - return; - } - - FLAG_C = CFLAG_CLEAR; - FLAG_N = NFLAG_16(src); - FLAG_Z = src; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_asl_32_r(void) -{ - uint* r_dst = &DY; - uint shift = DX & 0x3f; - uint src = *r_dst; - uint res = MASK_OUT_ABOVE_32(src << shift); - - if(shift != 0) - { - USE_CYCLES(shift<> (32 - shift)) << 8; - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - src &= m68ki_shift_32_table[shift + 1]; - FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7; - return; - } - - *r_dst = 0; - FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8; - FLAG_N = NFLAG_CLEAR; - FLAG_Z = ZFLAG_SET; - FLAG_V = (!(src == 0))<<7; - return; - } - - FLAG_C = CFLAG_CLEAR; - FLAG_N = NFLAG_32(src); - FLAG_Z = src; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_asl_16_ai(void) -{ - uint ea = EA_AY_AI_16(); - uint src = m68ki_read_16(ea); - uint res = MASK_OUT_ABOVE_16(src << 1); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_X = FLAG_C = src >> 7; - src &= 0xc000; - FLAG_V = (!(src == 0 || src == 0xc000))<<7; -} - - -void m68k_op_asl_16_pi(void) -{ - uint ea = EA_AY_PI_16(); - uint src = m68ki_read_16(ea); - uint res = MASK_OUT_ABOVE_16(src << 1); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_X = FLAG_C = src >> 7; - src &= 0xc000; - FLAG_V = (!(src == 0 || src == 0xc000))<<7; -} - - -void m68k_op_asl_16_pd(void) -{ - uint ea = EA_AY_PD_16(); - uint src = m68ki_read_16(ea); - uint res = MASK_OUT_ABOVE_16(src << 1); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_X = FLAG_C = src >> 7; - src &= 0xc000; - FLAG_V = (!(src == 0 || src == 0xc000))<<7; -} - - -void m68k_op_asl_16_di(void) -{ - uint ea = EA_AY_DI_16(); - uint src = m68ki_read_16(ea); - uint res = MASK_OUT_ABOVE_16(src << 1); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_X = FLAG_C = src >> 7; - src &= 0xc000; - FLAG_V = (!(src == 0 || src == 0xc000))<<7; -} - - -void m68k_op_asl_16_ix(void) -{ - uint ea = EA_AY_IX_16(); - uint src = m68ki_read_16(ea); - uint res = MASK_OUT_ABOVE_16(src << 1); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_X = FLAG_C = src >> 7; - src &= 0xc000; - FLAG_V = (!(src == 0 || src == 0xc000))<<7; -} - - -void m68k_op_asl_16_aw(void) -{ - uint ea = EA_AW_16(); - uint src = m68ki_read_16(ea); - uint res = MASK_OUT_ABOVE_16(src << 1); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_X = FLAG_C = src >> 7; - src &= 0xc000; - FLAG_V = (!(src == 0 || src == 0xc000))<<7; -} - - -void m68k_op_asl_16_al(void) -{ - uint ea = EA_AL_16(); - uint src = m68ki_read_16(ea); - uint res = MASK_OUT_ABOVE_16(src << 1); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_X = FLAG_C = src >> 7; - src &= 0xc000; - FLAG_V = (!(src == 0 || src == 0xc000))<<7; -} - - -void m68k_op_bhi_8(void) -{ - if(COND_HI()) - { - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR)); - return; - } - USE_CYCLES(CYC_BCC_NOTAKE_B); -} - - -void m68k_op_bls_8(void) -{ - if(COND_LS()) - { - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR)); - return; - } - USE_CYCLES(CYC_BCC_NOTAKE_B); -} - - -void m68k_op_bcc_8(void) -{ - if(COND_CC()) - { - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR)); - return; - } - USE_CYCLES(CYC_BCC_NOTAKE_B); -} - - -void m68k_op_bcs_8(void) -{ - if(COND_CS()) - { - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR)); - return; - } - USE_CYCLES(CYC_BCC_NOTAKE_B); -} - - -void m68k_op_bne_8(void) -{ - if(COND_NE()) - { - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR)); - return; - } - USE_CYCLES(CYC_BCC_NOTAKE_B); -} - - -void m68k_op_beq_8(void) -{ - if(COND_EQ()) - { - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR)); - return; - } - USE_CYCLES(CYC_BCC_NOTAKE_B); -} - - -void m68k_op_bvc_8(void) -{ - if(COND_VC()) - { - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR)); - return; - } - USE_CYCLES(CYC_BCC_NOTAKE_B); -} - - -void m68k_op_bvs_8(void) -{ - if(COND_VS()) - { - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR)); - return; - } - USE_CYCLES(CYC_BCC_NOTAKE_B); -} - - -void m68k_op_bpl_8(void) -{ - if(COND_PL()) - { - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR)); - return; - } - USE_CYCLES(CYC_BCC_NOTAKE_B); -} - - -void m68k_op_bmi_8(void) -{ - if(COND_MI()) - { - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR)); - return; - } - USE_CYCLES(CYC_BCC_NOTAKE_B); -} - - -void m68k_op_bge_8(void) -{ - if(COND_GE()) - { - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR)); - return; - } - USE_CYCLES(CYC_BCC_NOTAKE_B); -} - - -void m68k_op_blt_8(void) -{ - if(COND_LT()) - { - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR)); - return; - } - USE_CYCLES(CYC_BCC_NOTAKE_B); -} - - -void m68k_op_bgt_8(void) -{ - if(COND_GT()) - { - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR)); - return; - } - USE_CYCLES(CYC_BCC_NOTAKE_B); -} - - -void m68k_op_ble_8(void) -{ - if(COND_LE()) - { - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR)); - return; - } - USE_CYCLES(CYC_BCC_NOTAKE_B); -} - - -void m68k_op_bhi_16(void) -{ - if(COND_HI()) - { - uint offset = OPER_I_16(); - REG_PC -= 2; - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_16(offset); - return; - } - REG_PC += 2; - USE_CYCLES(CYC_BCC_NOTAKE_W); -} - - -void m68k_op_bls_16(void) -{ - if(COND_LS()) - { - uint offset = OPER_I_16(); - REG_PC -= 2; - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_16(offset); - return; - } - REG_PC += 2; - USE_CYCLES(CYC_BCC_NOTAKE_W); -} - - -void m68k_op_bcc_16(void) -{ - if(COND_CC()) - { - uint offset = OPER_I_16(); - REG_PC -= 2; - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_16(offset); - return; - } - REG_PC += 2; - USE_CYCLES(CYC_BCC_NOTAKE_W); -} - - -void m68k_op_bcs_16(void) -{ - if(COND_CS()) - { - uint offset = OPER_I_16(); - REG_PC -= 2; - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_16(offset); - return; - } - REG_PC += 2; - USE_CYCLES(CYC_BCC_NOTAKE_W); -} - - -void m68k_op_bne_16(void) -{ - if(COND_NE()) - { - uint offset = OPER_I_16(); - REG_PC -= 2; - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_16(offset); - return; - } - REG_PC += 2; - USE_CYCLES(CYC_BCC_NOTAKE_W); -} - - -void m68k_op_beq_16(void) -{ - if(COND_EQ()) - { - uint offset = OPER_I_16(); - REG_PC -= 2; - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_16(offset); - return; - } - REG_PC += 2; - USE_CYCLES(CYC_BCC_NOTAKE_W); -} - - -void m68k_op_bvc_16(void) -{ - if(COND_VC()) - { - uint offset = OPER_I_16(); - REG_PC -= 2; - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_16(offset); - return; - } - REG_PC += 2; - USE_CYCLES(CYC_BCC_NOTAKE_W); -} - - -void m68k_op_bvs_16(void) -{ - if(COND_VS()) - { - uint offset = OPER_I_16(); - REG_PC -= 2; - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_16(offset); - return; - } - REG_PC += 2; - USE_CYCLES(CYC_BCC_NOTAKE_W); -} - - -void m68k_op_bpl_16(void) -{ - if(COND_PL()) - { - uint offset = OPER_I_16(); - REG_PC -= 2; - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_16(offset); - return; - } - REG_PC += 2; - USE_CYCLES(CYC_BCC_NOTAKE_W); -} - - -void m68k_op_bmi_16(void) -{ - if(COND_MI()) - { - uint offset = OPER_I_16(); - REG_PC -= 2; - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_16(offset); - return; - } - REG_PC += 2; - USE_CYCLES(CYC_BCC_NOTAKE_W); -} - - -void m68k_op_bge_16(void) -{ - if(COND_GE()) - { - uint offset = OPER_I_16(); - REG_PC -= 2; - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_16(offset); - return; - } - REG_PC += 2; - USE_CYCLES(CYC_BCC_NOTAKE_W); -} - - -void m68k_op_blt_16(void) -{ - if(COND_LT()) - { - uint offset = OPER_I_16(); - REG_PC -= 2; - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_16(offset); - return; - } - REG_PC += 2; - USE_CYCLES(CYC_BCC_NOTAKE_W); -} - - -void m68k_op_bgt_16(void) -{ - if(COND_GT()) - { - uint offset = OPER_I_16(); - REG_PC -= 2; - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_16(offset); - return; - } - REG_PC += 2; - USE_CYCLES(CYC_BCC_NOTAKE_W); -} - - -void m68k_op_ble_16(void) -{ - if(COND_LE()) - { - uint offset = OPER_I_16(); - REG_PC -= 2; - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_16(offset); - return; - } - REG_PC += 2; - USE_CYCLES(CYC_BCC_NOTAKE_W); -} - - -void m68k_op_bhi_32(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(COND_HI()) - { - uint offset = OPER_I_32(); - REG_PC -= 4; - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_32(offset); - return; - } - REG_PC += 4; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bls_32(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(COND_LS()) - { - uint offset = OPER_I_32(); - REG_PC -= 4; - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_32(offset); - return; - } - REG_PC += 4; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bcc_32(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(COND_CC()) - { - uint offset = OPER_I_32(); - REG_PC -= 4; - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_32(offset); - return; - } - REG_PC += 4; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bcs_32(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(COND_CS()) - { - uint offset = OPER_I_32(); - REG_PC -= 4; - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_32(offset); - return; - } - REG_PC += 4; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bne_32(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(COND_NE()) - { - uint offset = OPER_I_32(); - REG_PC -= 4; - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_32(offset); - return; - } - REG_PC += 4; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_beq_32(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(COND_EQ()) - { - uint offset = OPER_I_32(); - REG_PC -= 4; - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_32(offset); - return; - } - REG_PC += 4; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bvc_32(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(COND_VC()) - { - uint offset = OPER_I_32(); - REG_PC -= 4; - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_32(offset); - return; - } - REG_PC += 4; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bvs_32(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(COND_VS()) - { - uint offset = OPER_I_32(); - REG_PC -= 4; - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_32(offset); - return; - } - REG_PC += 4; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bpl_32(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(COND_PL()) - { - uint offset = OPER_I_32(); - REG_PC -= 4; - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_32(offset); - return; - } - REG_PC += 4; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bmi_32(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(COND_MI()) - { - uint offset = OPER_I_32(); - REG_PC -= 4; - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_32(offset); - return; - } - REG_PC += 4; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bge_32(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(COND_GE()) - { - uint offset = OPER_I_32(); - REG_PC -= 4; - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_32(offset); - return; - } - REG_PC += 4; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_blt_32(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(COND_LT()) - { - uint offset = OPER_I_32(); - REG_PC -= 4; - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_32(offset); - return; - } - REG_PC += 4; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bgt_32(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(COND_GT()) - { - uint offset = OPER_I_32(); - REG_PC -= 4; - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_32(offset); - return; - } - REG_PC += 4; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_ble_32(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(COND_LE()) - { - uint offset = OPER_I_32(); - REG_PC -= 4; - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_32(offset); - return; - } - REG_PC += 4; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bchg_32_r_d(void) -{ - uint* r_dst = &DY; - uint mask = 1 << (DX & 0x1f); - - FLAG_Z = *r_dst & mask; - *r_dst ^= mask; -} - - -void m68k_op_bchg_8_r_ai(void) -{ - uint ea = EA_AY_AI_8(); - uint src = m68ki_read_8(ea); - uint mask = 1 << (DX & 7); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src ^ mask); -} - - -void m68k_op_bchg_8_r_pi(void) -{ - uint ea = EA_AY_PI_8(); - uint src = m68ki_read_8(ea); - uint mask = 1 << (DX & 7); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src ^ mask); -} - - -void m68k_op_bchg_8_r_pi7(void) -{ - uint ea = EA_A7_PI_8(); - uint src = m68ki_read_8(ea); - uint mask = 1 << (DX & 7); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src ^ mask); -} - - -void m68k_op_bchg_8_r_pd(void) -{ - uint ea = EA_AY_PD_8(); - uint src = m68ki_read_8(ea); - uint mask = 1 << (DX & 7); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src ^ mask); -} - - -void m68k_op_bchg_8_r_pd7(void) -{ - uint ea = EA_A7_PD_8(); - uint src = m68ki_read_8(ea); - uint mask = 1 << (DX & 7); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src ^ mask); -} - - -void m68k_op_bchg_8_r_di(void) -{ - uint ea = EA_AY_DI_8(); - uint src = m68ki_read_8(ea); - uint mask = 1 << (DX & 7); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src ^ mask); -} - - -void m68k_op_bchg_8_r_ix(void) -{ - uint ea = EA_AY_IX_8(); - uint src = m68ki_read_8(ea); - uint mask = 1 << (DX & 7); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src ^ mask); -} - - -void m68k_op_bchg_8_r_aw(void) -{ - uint ea = EA_AW_8(); - uint src = m68ki_read_8(ea); - uint mask = 1 << (DX & 7); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src ^ mask); -} - - -void m68k_op_bchg_8_r_al(void) -{ - uint ea = EA_AL_8(); - uint src = m68ki_read_8(ea); - uint mask = 1 << (DX & 7); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src ^ mask); -} - - -void m68k_op_bchg_32_s_d(void) -{ - uint* r_dst = &DY; - uint mask = 1 << (OPER_I_8() & 0x1f); - - FLAG_Z = *r_dst & mask; - *r_dst ^= mask; -} - - -void m68k_op_bchg_8_s_ai(void) -{ - uint mask = 1 << (OPER_I_8() & 7); - uint ea = EA_AY_AI_8(); - uint src = m68ki_read_8(ea); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src ^ mask); -} - - -void m68k_op_bchg_8_s_pi(void) -{ - uint mask = 1 << (OPER_I_8() & 7); - uint ea = EA_AY_PI_8(); - uint src = m68ki_read_8(ea); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src ^ mask); -} - - -void m68k_op_bchg_8_s_pi7(void) -{ - uint mask = 1 << (OPER_I_8() & 7); - uint ea = EA_A7_PI_8(); - uint src = m68ki_read_8(ea); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src ^ mask); -} - - -void m68k_op_bchg_8_s_pd(void) -{ - uint mask = 1 << (OPER_I_8() & 7); - uint ea = EA_AY_PD_8(); - uint src = m68ki_read_8(ea); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src ^ mask); -} - - -void m68k_op_bchg_8_s_pd7(void) -{ - uint mask = 1 << (OPER_I_8() & 7); - uint ea = EA_A7_PD_8(); - uint src = m68ki_read_8(ea); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src ^ mask); -} - - -void m68k_op_bchg_8_s_di(void) -{ - uint mask = 1 << (OPER_I_8() & 7); - uint ea = EA_AY_DI_8(); - uint src = m68ki_read_8(ea); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src ^ mask); -} - - -void m68k_op_bchg_8_s_ix(void) -{ - uint mask = 1 << (OPER_I_8() & 7); - uint ea = EA_AY_IX_8(); - uint src = m68ki_read_8(ea); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src ^ mask); -} - - -void m68k_op_bchg_8_s_aw(void) -{ - uint mask = 1 << (OPER_I_8() & 7); - uint ea = EA_AW_8(); - uint src = m68ki_read_8(ea); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src ^ mask); -} - - -void m68k_op_bchg_8_s_al(void) -{ - uint mask = 1 << (OPER_I_8() & 7); - uint ea = EA_AL_8(); - uint src = m68ki_read_8(ea); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src ^ mask); -} - - -void m68k_op_bclr_32_r_d(void) -{ - uint* r_dst = &DY; - uint mask = 1 << (DX & 0x1f); - - FLAG_Z = *r_dst & mask; - *r_dst &= ~mask; -} - - -void m68k_op_bclr_8_r_ai(void) -{ - uint ea = EA_AY_AI_8(); - uint src = m68ki_read_8(ea); - uint mask = 1 << (DX & 7); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src & ~mask); -} - - -void m68k_op_bclr_8_r_pi(void) -{ - uint ea = EA_AY_PI_8(); - uint src = m68ki_read_8(ea); - uint mask = 1 << (DX & 7); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src & ~mask); -} - - -void m68k_op_bclr_8_r_pi7(void) -{ - uint ea = EA_A7_PI_8(); - uint src = m68ki_read_8(ea); - uint mask = 1 << (DX & 7); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src & ~mask); -} - - -void m68k_op_bclr_8_r_pd(void) -{ - uint ea = EA_AY_PD_8(); - uint src = m68ki_read_8(ea); - uint mask = 1 << (DX & 7); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src & ~mask); -} - - -void m68k_op_bclr_8_r_pd7(void) -{ - uint ea = EA_A7_PD_8(); - uint src = m68ki_read_8(ea); - uint mask = 1 << (DX & 7); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src & ~mask); -} - - -void m68k_op_bclr_8_r_di(void) -{ - uint ea = EA_AY_DI_8(); - uint src = m68ki_read_8(ea); - uint mask = 1 << (DX & 7); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src & ~mask); -} - - -void m68k_op_bclr_8_r_ix(void) -{ - uint ea = EA_AY_IX_8(); - uint src = m68ki_read_8(ea); - uint mask = 1 << (DX & 7); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src & ~mask); -} - - -void m68k_op_bclr_8_r_aw(void) -{ - uint ea = EA_AW_8(); - uint src = m68ki_read_8(ea); - uint mask = 1 << (DX & 7); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src & ~mask); -} - - -void m68k_op_bclr_8_r_al(void) -{ - uint ea = EA_AL_8(); - uint src = m68ki_read_8(ea); - uint mask = 1 << (DX & 7); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src & ~mask); -} - - -void m68k_op_bclr_32_s_d(void) -{ - uint* r_dst = &DY; - uint mask = 1 << (OPER_I_8() & 0x1f); - - FLAG_Z = *r_dst & mask; - *r_dst &= ~mask; -} - - -void m68k_op_bclr_8_s_ai(void) -{ - uint mask = 1 << (OPER_I_8() & 7); - uint ea = EA_AY_AI_8(); - uint src = m68ki_read_8(ea); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src & ~mask); -} - - -void m68k_op_bclr_8_s_pi(void) -{ - uint mask = 1 << (OPER_I_8() & 7); - uint ea = EA_AY_PI_8(); - uint src = m68ki_read_8(ea); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src & ~mask); -} - - -void m68k_op_bclr_8_s_pi7(void) -{ - uint mask = 1 << (OPER_I_8() & 7); - uint ea = EA_A7_PI_8(); - uint src = m68ki_read_8(ea); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src & ~mask); -} - - -void m68k_op_bclr_8_s_pd(void) -{ - uint mask = 1 << (OPER_I_8() & 7); - uint ea = EA_AY_PD_8(); - uint src = m68ki_read_8(ea); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src & ~mask); -} - - -void m68k_op_bclr_8_s_pd7(void) -{ - uint mask = 1 << (OPER_I_8() & 7); - uint ea = EA_A7_PD_8(); - uint src = m68ki_read_8(ea); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src & ~mask); -} - - -void m68k_op_bclr_8_s_di(void) -{ - uint mask = 1 << (OPER_I_8() & 7); - uint ea = EA_AY_DI_8(); - uint src = m68ki_read_8(ea); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src & ~mask); -} - - -void m68k_op_bclr_8_s_ix(void) -{ - uint mask = 1 << (OPER_I_8() & 7); - uint ea = EA_AY_IX_8(); - uint src = m68ki_read_8(ea); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src & ~mask); -} - - -void m68k_op_bclr_8_s_aw(void) -{ - uint mask = 1 << (OPER_I_8() & 7); - uint ea = EA_AW_8(); - uint src = m68ki_read_8(ea); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src & ~mask); -} - - -void m68k_op_bclr_8_s_al(void) -{ - uint mask = 1 << (OPER_I_8() & 7); - uint ea = EA_AL_8(); - uint src = m68ki_read_8(ea); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src & ~mask); -} - - -void m68k_op_bfchg_32_d(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint offset = (word2>>6)&31; - uint width = word2; - uint* data = &DY; - uint64 mask; - - - if(BIT_B(word2)) - offset = REG_D[offset&7]; - if(BIT_5(word2)) - width = REG_D[width&7]; - - offset &= 31; - width = ((width-1) & 31) + 1; - - mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); - mask = ROR_32(mask, offset); - - FLAG_N = NFLAG_32(*data<>6)&31; - uint width = word2; - uint mask_base; - uint data_long; - uint mask_long; - uint data_byte = 0; - uint mask_byte = 0; - uint ea = EA_AY_AI_8(); - - - if(BIT_B(word2)) - offset = MAKE_INT_32(REG_D[offset&7]); - if(BIT_5(word2)) - width = REG_D[width&7]; - - /* Offset is signed so we have to use ugly math =( */ - ea += offset / 8; - offset %= 8; - if(offset < 0) - { - offset += 8; - ea--; - } - width = ((width-1) & 31) + 1; - - mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); - mask_long = mask_base >> offset; - - data_long = m68ki_read_32(ea); - FLAG_N = NFLAG_32(data_long << offset); - FLAG_Z = data_long & mask_long; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - m68ki_write_32(ea, data_long ^ mask_long); - - if((width + offset) > 32) - { - mask_byte = MASK_OUT_ABOVE_8(mask_base); - data_byte = m68ki_read_8(ea+4); - FLAG_Z |= (data_byte & mask_byte); - m68ki_write_8(ea+4, data_byte ^ mask_byte); - } - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bfchg_32_di(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - sint offset = (word2>>6)&31; - uint width = word2; - uint mask_base; - uint data_long; - uint mask_long; - uint data_byte = 0; - uint mask_byte = 0; - uint ea = EA_AY_DI_8(); - - - if(BIT_B(word2)) - offset = MAKE_INT_32(REG_D[offset&7]); - if(BIT_5(word2)) - width = REG_D[width&7]; - - /* Offset is signed so we have to use ugly math =( */ - ea += offset / 8; - offset %= 8; - if(offset < 0) - { - offset += 8; - ea--; - } - width = ((width-1) & 31) + 1; - - mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); - mask_long = mask_base >> offset; - - data_long = m68ki_read_32(ea); - FLAG_N = NFLAG_32(data_long << offset); - FLAG_Z = data_long & mask_long; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - m68ki_write_32(ea, data_long ^ mask_long); - - if((width + offset) > 32) - { - mask_byte = MASK_OUT_ABOVE_8(mask_base); - data_byte = m68ki_read_8(ea+4); - FLAG_Z |= (data_byte & mask_byte); - m68ki_write_8(ea+4, data_byte ^ mask_byte); - } - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bfchg_32_ix(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - sint offset = (word2>>6)&31; - uint width = word2; - uint mask_base; - uint data_long; - uint mask_long; - uint data_byte = 0; - uint mask_byte = 0; - uint ea = EA_AY_IX_8(); - - - if(BIT_B(word2)) - offset = MAKE_INT_32(REG_D[offset&7]); - if(BIT_5(word2)) - width = REG_D[width&7]; - - /* Offset is signed so we have to use ugly math =( */ - ea += offset / 8; - offset %= 8; - if(offset < 0) - { - offset += 8; - ea--; - } - width = ((width-1) & 31) + 1; - - mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); - mask_long = mask_base >> offset; - - data_long = m68ki_read_32(ea); - FLAG_N = NFLAG_32(data_long << offset); - FLAG_Z = data_long & mask_long; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - m68ki_write_32(ea, data_long ^ mask_long); - - if((width + offset) > 32) - { - mask_byte = MASK_OUT_ABOVE_8(mask_base); - data_byte = m68ki_read_8(ea+4); - FLAG_Z |= (data_byte & mask_byte); - m68ki_write_8(ea+4, data_byte ^ mask_byte); - } - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bfchg_32_aw(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - sint offset = (word2>>6)&31; - uint width = word2; - uint mask_base; - uint data_long; - uint mask_long; - uint data_byte = 0; - uint mask_byte = 0; - uint ea = EA_AW_8(); - - - if(BIT_B(word2)) - offset = MAKE_INT_32(REG_D[offset&7]); - if(BIT_5(word2)) - width = REG_D[width&7]; - - /* Offset is signed so we have to use ugly math =( */ - ea += offset / 8; - offset %= 8; - if(offset < 0) - { - offset += 8; - ea--; - } - width = ((width-1) & 31) + 1; - - mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); - mask_long = mask_base >> offset; - - data_long = m68ki_read_32(ea); - FLAG_N = NFLAG_32(data_long << offset); - FLAG_Z = data_long & mask_long; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - m68ki_write_32(ea, data_long ^ mask_long); - - if((width + offset) > 32) - { - mask_byte = MASK_OUT_ABOVE_8(mask_base); - data_byte = m68ki_read_8(ea+4); - FLAG_Z |= (data_byte & mask_byte); - m68ki_write_8(ea+4, data_byte ^ mask_byte); - } - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bfchg_32_al(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - sint offset = (word2>>6)&31; - uint width = word2; - uint mask_base; - uint data_long; - uint mask_long; - uint data_byte = 0; - uint mask_byte = 0; - uint ea = EA_AL_8(); - - - if(BIT_B(word2)) - offset = MAKE_INT_32(REG_D[offset&7]); - if(BIT_5(word2)) - width = REG_D[width&7]; - - /* Offset is signed so we have to use ugly math =( */ - ea += offset / 8; - offset %= 8; - if(offset < 0) - { - offset += 8; - ea--; - } - width = ((width-1) & 31) + 1; - - mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); - mask_long = mask_base >> offset; - - data_long = m68ki_read_32(ea); - FLAG_N = NFLAG_32(data_long << offset); - FLAG_Z = data_long & mask_long; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - m68ki_write_32(ea, data_long ^ mask_long); - - if((width + offset) > 32) - { - mask_byte = MASK_OUT_ABOVE_8(mask_base); - data_byte = m68ki_read_8(ea+4); - FLAG_Z |= (data_byte & mask_byte); - m68ki_write_8(ea+4, data_byte ^ mask_byte); - } - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bfclr_32_d(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint offset = (word2>>6)&31; - uint width = word2; - uint* data = &DY; - uint64 mask; - - - if(BIT_B(word2)) - offset = REG_D[offset&7]; - if(BIT_5(word2)) - width = REG_D[width&7]; - - - offset &= 31; - width = ((width-1) & 31) + 1; - - - mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); - mask = ROR_32(mask, offset); - - FLAG_N = NFLAG_32(*data<>6)&31; - uint width = word2; - uint mask_base; - uint data_long; - uint mask_long; - uint data_byte = 0; - uint mask_byte = 0; - uint ea = EA_AY_AI_8(); - - - if(BIT_B(word2)) - offset = MAKE_INT_32(REG_D[offset&7]); - if(BIT_5(word2)) - width = REG_D[width&7]; - - /* Offset is signed so we have to use ugly math =( */ - ea += offset / 8; - offset %= 8; - if(offset < 0) - { - offset += 8; - ea--; - } - width = ((width-1) & 31) + 1; - - mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); - mask_long = mask_base >> offset; - - data_long = m68ki_read_32(ea); - FLAG_N = NFLAG_32(data_long << offset); - FLAG_Z = data_long & mask_long; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - m68ki_write_32(ea, data_long & ~mask_long); - - if((width + offset) > 32) - { - mask_byte = MASK_OUT_ABOVE_8(mask_base); - data_byte = m68ki_read_8(ea+4); - FLAG_Z |= (data_byte & mask_byte); - m68ki_write_8(ea+4, data_byte & ~mask_byte); - } - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bfclr_32_di(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - sint offset = (word2>>6)&31; - uint width = word2; - uint mask_base; - uint data_long; - uint mask_long; - uint data_byte = 0; - uint mask_byte = 0; - uint ea = EA_AY_DI_8(); - - - if(BIT_B(word2)) - offset = MAKE_INT_32(REG_D[offset&7]); - if(BIT_5(word2)) - width = REG_D[width&7]; - - /* Offset is signed so we have to use ugly math =( */ - ea += offset / 8; - offset %= 8; - if(offset < 0) - { - offset += 8; - ea--; - } - width = ((width-1) & 31) + 1; - - mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); - mask_long = mask_base >> offset; - - data_long = m68ki_read_32(ea); - FLAG_N = NFLAG_32(data_long << offset); - FLAG_Z = data_long & mask_long; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - m68ki_write_32(ea, data_long & ~mask_long); - - if((width + offset) > 32) - { - mask_byte = MASK_OUT_ABOVE_8(mask_base); - data_byte = m68ki_read_8(ea+4); - FLAG_Z |= (data_byte & mask_byte); - m68ki_write_8(ea+4, data_byte & ~mask_byte); - } - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bfclr_32_ix(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - sint offset = (word2>>6)&31; - uint width = word2; - uint mask_base; - uint data_long; - uint mask_long; - uint data_byte = 0; - uint mask_byte = 0; - uint ea = EA_AY_IX_8(); - - - if(BIT_B(word2)) - offset = MAKE_INT_32(REG_D[offset&7]); - if(BIT_5(word2)) - width = REG_D[width&7]; - - /* Offset is signed so we have to use ugly math =( */ - ea += offset / 8; - offset %= 8; - if(offset < 0) - { - offset += 8; - ea--; - } - width = ((width-1) & 31) + 1; - - mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); - mask_long = mask_base >> offset; - - data_long = m68ki_read_32(ea); - FLAG_N = NFLAG_32(data_long << offset); - FLAG_Z = data_long & mask_long; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - m68ki_write_32(ea, data_long & ~mask_long); - - if((width + offset) > 32) - { - mask_byte = MASK_OUT_ABOVE_8(mask_base); - data_byte = m68ki_read_8(ea+4); - FLAG_Z |= (data_byte & mask_byte); - m68ki_write_8(ea+4, data_byte & ~mask_byte); - } - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bfclr_32_aw(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - sint offset = (word2>>6)&31; - uint width = word2; - uint mask_base; - uint data_long; - uint mask_long; - uint data_byte = 0; - uint mask_byte = 0; - uint ea = EA_AW_8(); - - - if(BIT_B(word2)) - offset = MAKE_INT_32(REG_D[offset&7]); - if(BIT_5(word2)) - width = REG_D[width&7]; - - /* Offset is signed so we have to use ugly math =( */ - ea += offset / 8; - offset %= 8; - if(offset < 0) - { - offset += 8; - ea--; - } - width = ((width-1) & 31) + 1; - - mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); - mask_long = mask_base >> offset; - - data_long = m68ki_read_32(ea); - FLAG_N = NFLAG_32(data_long << offset); - FLAG_Z = data_long & mask_long; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - m68ki_write_32(ea, data_long & ~mask_long); - - if((width + offset) > 32) - { - mask_byte = MASK_OUT_ABOVE_8(mask_base); - data_byte = m68ki_read_8(ea+4); - FLAG_Z |= (data_byte & mask_byte); - m68ki_write_8(ea+4, data_byte & ~mask_byte); - } - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bfclr_32_al(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - sint offset = (word2>>6)&31; - uint width = word2; - uint mask_base; - uint data_long; - uint mask_long; - uint data_byte = 0; - uint mask_byte = 0; - uint ea = EA_AL_8(); - - - if(BIT_B(word2)) - offset = MAKE_INT_32(REG_D[offset&7]); - if(BIT_5(word2)) - width = REG_D[width&7]; - - /* Offset is signed so we have to use ugly math =( */ - ea += offset / 8; - offset %= 8; - if(offset < 0) - { - offset += 8; - ea--; - } - width = ((width-1) & 31) + 1; - - mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); - mask_long = mask_base >> offset; - - data_long = m68ki_read_32(ea); - FLAG_N = NFLAG_32(data_long << offset); - FLAG_Z = data_long & mask_long; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - m68ki_write_32(ea, data_long & ~mask_long); - - if((width + offset) > 32) - { - mask_byte = MASK_OUT_ABOVE_8(mask_base); - data_byte = m68ki_read_8(ea+4); - FLAG_Z |= (data_byte & mask_byte); - m68ki_write_8(ea+4, data_byte & ~mask_byte); - } - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bfexts_32_d(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint offset = (word2>>6)&31; - uint width = word2; - uint64 data = DY; - - - if(BIT_B(word2)) - offset = REG_D[offset&7]; - if(BIT_5(word2)) - width = REG_D[width&7]; - - offset &= 31; - width = ((width-1) & 31) + 1; - - data = ROL_32(data, offset); - FLAG_N = NFLAG_32(data); - data = MAKE_INT_32(data) >> (32 - width); - - FLAG_Z = data; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - REG_D[(word2>>12)&7] = data; - - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bfexts_32_ai(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - sint offset = (word2>>6)&31; - uint width = word2; - uint data; - uint ea = EA_AY_AI_8(); - - - if(BIT_B(word2)) - offset = MAKE_INT_32(REG_D[offset&7]); - if(BIT_5(word2)) - width = REG_D[width&7]; - - /* Offset is signed so we have to use ugly math =( */ - ea += offset / 8; - offset %= 8; - if(offset < 0) - { - offset += 8; - ea--; - } - width = ((width-1) & 31) + 1; - - data = m68ki_read_32(ea); - - data = MASK_OUT_ABOVE_32(data< 32) - data |= (m68ki_read_8(ea+4) << offset) >> 8; - - FLAG_N = NFLAG_32(data); - data = MAKE_INT_32(data) >> (32 - width); - - FLAG_Z = data; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - REG_D[(word2 >> 12) & 7] = data; - - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bfexts_32_di(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - sint offset = (word2>>6)&31; - uint width = word2; - uint data; - uint ea = EA_AY_DI_8(); - - - if(BIT_B(word2)) - offset = MAKE_INT_32(REG_D[offset&7]); - if(BIT_5(word2)) - width = REG_D[width&7]; - - /* Offset is signed so we have to use ugly math =( */ - ea += offset / 8; - offset %= 8; - if(offset < 0) - { - offset += 8; - ea--; - } - width = ((width-1) & 31) + 1; - - data = m68ki_read_32(ea); - - data = MASK_OUT_ABOVE_32(data< 32) - data |= (m68ki_read_8(ea+4) << offset) >> 8; - - FLAG_N = NFLAG_32(data); - data = MAKE_INT_32(data) >> (32 - width); - - FLAG_Z = data; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - REG_D[(word2 >> 12) & 7] = data; - - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bfexts_32_ix(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - sint offset = (word2>>6)&31; - uint width = word2; - uint data; - uint ea = EA_AY_IX_8(); - - - if(BIT_B(word2)) - offset = MAKE_INT_32(REG_D[offset&7]); - if(BIT_5(word2)) - width = REG_D[width&7]; - - /* Offset is signed so we have to use ugly math =( */ - ea += offset / 8; - offset %= 8; - if(offset < 0) - { - offset += 8; - ea--; - } - width = ((width-1) & 31) + 1; - - data = m68ki_read_32(ea); - - data = MASK_OUT_ABOVE_32(data< 32) - data |= (m68ki_read_8(ea+4) << offset) >> 8; - - FLAG_N = NFLAG_32(data); - data = MAKE_INT_32(data) >> (32 - width); - - FLAG_Z = data; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - REG_D[(word2 >> 12) & 7] = data; - - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bfexts_32_aw(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - sint offset = (word2>>6)&31; - uint width = word2; - uint data; - uint ea = EA_AW_8(); - - - if(BIT_B(word2)) - offset = MAKE_INT_32(REG_D[offset&7]); - if(BIT_5(word2)) - width = REG_D[width&7]; - - /* Offset is signed so we have to use ugly math =( */ - ea += offset / 8; - offset %= 8; - if(offset < 0) - { - offset += 8; - ea--; - } - width = ((width-1) & 31) + 1; - - data = m68ki_read_32(ea); - - data = MASK_OUT_ABOVE_32(data< 32) - data |= (m68ki_read_8(ea+4) << offset) >> 8; - - FLAG_N = NFLAG_32(data); - data = MAKE_INT_32(data) >> (32 - width); - - FLAG_Z = data; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - REG_D[(word2 >> 12) & 7] = data; - - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bfexts_32_al(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - sint offset = (word2>>6)&31; - uint width = word2; - uint data; - uint ea = EA_AL_8(); - - - if(BIT_B(word2)) - offset = MAKE_INT_32(REG_D[offset&7]); - if(BIT_5(word2)) - width = REG_D[width&7]; - - /* Offset is signed so we have to use ugly math =( */ - ea += offset / 8; - offset %= 8; - if(offset < 0) - { - offset += 8; - ea--; - } - width = ((width-1) & 31) + 1; - - data = m68ki_read_32(ea); - - data = MASK_OUT_ABOVE_32(data< 32) - data |= (m68ki_read_8(ea+4) << offset) >> 8; - - FLAG_N = NFLAG_32(data); - data = MAKE_INT_32(data) >> (32 - width); - - FLAG_Z = data; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - REG_D[(word2 >> 12) & 7] = data; - - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bfexts_32_pcdi(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - sint offset = (word2>>6)&31; - uint width = word2; - uint data; - uint ea = EA_PCDI_8(); - - - if(BIT_B(word2)) - offset = MAKE_INT_32(REG_D[offset&7]); - if(BIT_5(word2)) - width = REG_D[width&7]; - - /* Offset is signed so we have to use ugly math =( */ - ea += offset / 8; - offset %= 8; - if(offset < 0) - { - offset += 8; - ea--; - } - width = ((width-1) & 31) + 1; - - data = m68ki_read_32(ea); - - data = MASK_OUT_ABOVE_32(data< 32) - data |= (m68ki_read_8(ea+4) << offset) >> 8; - - FLAG_N = NFLAG_32(data); - data = MAKE_INT_32(data) >> (32 - width); - - FLAG_Z = data; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - REG_D[(word2 >> 12) & 7] = data; - - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bfexts_32_pcix(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - sint offset = (word2>>6)&31; - uint width = word2; - uint data; - uint ea = EA_PCIX_8(); - - - if(BIT_B(word2)) - offset = MAKE_INT_32(REG_D[offset&7]); - if(BIT_5(word2)) - width = REG_D[width&7]; - - /* Offset is signed so we have to use ugly math =( */ - ea += offset / 8; - offset %= 8; - if(offset < 0) - { - offset += 8; - ea--; - } - width = ((width-1) & 31) + 1; - - data = m68ki_read_32(ea); - - data = MASK_OUT_ABOVE_32(data< 32) - data |= (m68ki_read_8(ea+4) << offset) >> 8; - - FLAG_N = NFLAG_32(data); - data = MAKE_INT_32(data) >> (32 - width); - - FLAG_Z = data; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - REG_D[(word2 >> 12) & 7] = data; - - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bfextu_32_d(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint offset = (word2>>6)&31; - uint width = word2; - uint64 data = DY; - - - if(BIT_B(word2)) - offset = REG_D[offset&7]; - if(BIT_5(word2)) - width = REG_D[width&7]; - - offset &= 31; - width = ((width-1) & 31) + 1; - - data = ROL_32(data, offset); - FLAG_N = NFLAG_32(data); - data >>= 32 - width; - - FLAG_Z = data; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - REG_D[(word2>>12)&7] = data; - - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bfextu_32_ai(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - sint offset = (word2>>6)&31; - uint width = word2; - uint data; - uint ea = EA_AY_AI_8(); - - - if(BIT_B(word2)) - offset = MAKE_INT_32(REG_D[offset&7]); - if(BIT_5(word2)) - width = REG_D[width&7]; - - /* Offset is signed so we have to use ugly math =( */ - ea += offset / 8; - offset %= 8; - if(offset < 0) - { - offset += 8; - ea--; - } - width = ((width-1) & 31) + 1; - - data = m68ki_read_32(ea); - data = MASK_OUT_ABOVE_32(data< 32) - data |= (m68ki_read_8(ea+4) << offset) >> 8; - - FLAG_N = NFLAG_32(data); - data >>= (32 - width); - - FLAG_Z = data; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - REG_D[(word2 >> 12) & 7] = data; - - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bfextu_32_di(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - sint offset = (word2>>6)&31; - uint width = word2; - uint data; - uint ea = EA_AY_DI_8(); - - - if(BIT_B(word2)) - offset = MAKE_INT_32(REG_D[offset&7]); - if(BIT_5(word2)) - width = REG_D[width&7]; - - /* Offset is signed so we have to use ugly math =( */ - ea += offset / 8; - offset %= 8; - if(offset < 0) - { - offset += 8; - ea--; - } - width = ((width-1) & 31) + 1; - - data = m68ki_read_32(ea); - data = MASK_OUT_ABOVE_32(data< 32) - data |= (m68ki_read_8(ea+4) << offset) >> 8; - - FLAG_N = NFLAG_32(data); - data >>= (32 - width); - - FLAG_Z = data; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - REG_D[(word2 >> 12) & 7] = data; - - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bfextu_32_ix(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - sint offset = (word2>>6)&31; - uint width = word2; - uint data; - uint ea = EA_AY_IX_8(); - - - if(BIT_B(word2)) - offset = MAKE_INT_32(REG_D[offset&7]); - if(BIT_5(word2)) - width = REG_D[width&7]; - - /* Offset is signed so we have to use ugly math =( */ - ea += offset / 8; - offset %= 8; - if(offset < 0) - { - offset += 8; - ea--; - } - width = ((width-1) & 31) + 1; - - data = m68ki_read_32(ea); - data = MASK_OUT_ABOVE_32(data< 32) - data |= (m68ki_read_8(ea+4) << offset) >> 8; - - FLAG_N = NFLAG_32(data); - data >>= (32 - width); - - FLAG_Z = data; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - REG_D[(word2 >> 12) & 7] = data; - - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bfextu_32_aw(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - sint offset = (word2>>6)&31; - uint width = word2; - uint data; - uint ea = EA_AW_8(); - - - if(BIT_B(word2)) - offset = MAKE_INT_32(REG_D[offset&7]); - if(BIT_5(word2)) - width = REG_D[width&7]; - - /* Offset is signed so we have to use ugly math =( */ - ea += offset / 8; - offset %= 8; - if(offset < 0) - { - offset += 8; - ea--; - } - width = ((width-1) & 31) + 1; - - data = m68ki_read_32(ea); - data = MASK_OUT_ABOVE_32(data< 32) - data |= (m68ki_read_8(ea+4) << offset) >> 8; - - FLAG_N = NFLAG_32(data); - data >>= (32 - width); - - FLAG_Z = data; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - REG_D[(word2 >> 12) & 7] = data; - - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bfextu_32_al(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - sint offset = (word2>>6)&31; - uint width = word2; - uint data; - uint ea = EA_AL_8(); - - - if(BIT_B(word2)) - offset = MAKE_INT_32(REG_D[offset&7]); - if(BIT_5(word2)) - width = REG_D[width&7]; - - /* Offset is signed so we have to use ugly math =( */ - ea += offset / 8; - offset %= 8; - if(offset < 0) - { - offset += 8; - ea--; - } - width = ((width-1) & 31) + 1; - - data = m68ki_read_32(ea); - data = MASK_OUT_ABOVE_32(data< 32) - data |= (m68ki_read_8(ea+4) << offset) >> 8; - - FLAG_N = NFLAG_32(data); - data >>= (32 - width); - - FLAG_Z = data; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - REG_D[(word2 >> 12) & 7] = data; - - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bfextu_32_pcdi(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - sint offset = (word2>>6)&31; - uint width = word2; - uint data; - uint ea = EA_PCDI_8(); - - - if(BIT_B(word2)) - offset = MAKE_INT_32(REG_D[offset&7]); - if(BIT_5(word2)) - width = REG_D[width&7]; - - /* Offset is signed so we have to use ugly math =( */ - ea += offset / 8; - offset %= 8; - if(offset < 0) - { - offset += 8; - ea--; - } - width = ((width-1) & 31) + 1; - - data = m68ki_read_32(ea); - data = MASK_OUT_ABOVE_32(data< 32) - data |= (m68ki_read_8(ea+4) << offset) >> 8; - - FLAG_N = NFLAG_32(data); - data >>= (32 - width); - - FLAG_Z = data; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - REG_D[(word2 >> 12) & 7] = data; - - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bfextu_32_pcix(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - sint offset = (word2>>6)&31; - uint width = word2; - uint data; - uint ea = EA_PCIX_8(); - - - if(BIT_B(word2)) - offset = MAKE_INT_32(REG_D[offset&7]); - if(BIT_5(word2)) - width = REG_D[width&7]; - - /* Offset is signed so we have to use ugly math =( */ - ea += offset / 8; - offset %= 8; - if(offset < 0) - { - offset += 8; - ea--; - } - width = ((width-1) & 31) + 1; - - data = m68ki_read_32(ea); - data = MASK_OUT_ABOVE_32(data< 32) - data |= (m68ki_read_8(ea+4) << offset) >> 8; - - FLAG_N = NFLAG_32(data); - data >>= (32 - width); - - FLAG_Z = data; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - REG_D[(word2 >> 12) & 7] = data; - - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bfffo_32_d(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint offset = (word2>>6)&31; - uint width = word2; - uint64 data = DY; - uint bit; - - - if(BIT_B(word2)) - offset = REG_D[offset&7]; - if(BIT_5(word2)) - width = REG_D[width&7]; - - offset &= 31; - width = ((width-1) & 31) + 1; - - data = ROL_32(data, offset); - FLAG_N = NFLAG_32(data); - data >>= 32 - width; - - FLAG_Z = data; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1) - offset++; - - REG_D[(word2>>12)&7] = offset; - - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bfffo_32_ai(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - sint offset = (word2>>6)&31; - sint local_offset; - uint width = word2; - uint data; - uint bit; - uint ea = EA_AY_AI_8(); - - - if(BIT_B(word2)) - offset = MAKE_INT_32(REG_D[offset&7]); - if(BIT_5(word2)) - width = REG_D[width&7]; - - /* Offset is signed so we have to use ugly math =( */ - ea += offset / 8; - local_offset = offset % 8; - if(local_offset < 0) - { - local_offset += 8; - ea--; - } - width = ((width-1) & 31) + 1; - - data = m68ki_read_32(ea); - data = MASK_OUT_ABOVE_32(data< 32) - data |= (m68ki_read_8(ea+4) << local_offset) >> 8; - - FLAG_N = NFLAG_32(data); - data >>= (32 - width); - - FLAG_Z = data; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1) - offset++; - - REG_D[(word2>>12)&7] = offset; - - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bfffo_32_di(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - sint offset = (word2>>6)&31; - sint local_offset; - uint width = word2; - uint data; - uint bit; - uint ea = EA_AY_DI_8(); - - - if(BIT_B(word2)) - offset = MAKE_INT_32(REG_D[offset&7]); - if(BIT_5(word2)) - width = REG_D[width&7]; - - /* Offset is signed so we have to use ugly math =( */ - ea += offset / 8; - local_offset = offset % 8; - if(local_offset < 0) - { - local_offset += 8; - ea--; - } - width = ((width-1) & 31) + 1; - - data = m68ki_read_32(ea); - data = MASK_OUT_ABOVE_32(data< 32) - data |= (m68ki_read_8(ea+4) << local_offset) >> 8; - - FLAG_N = NFLAG_32(data); - data >>= (32 - width); - - FLAG_Z = data; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1) - offset++; - - REG_D[(word2>>12)&7] = offset; - - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bfffo_32_ix(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - sint offset = (word2>>6)&31; - sint local_offset; - uint width = word2; - uint data; - uint bit; - uint ea = EA_AY_IX_8(); - - - if(BIT_B(word2)) - offset = MAKE_INT_32(REG_D[offset&7]); - if(BIT_5(word2)) - width = REG_D[width&7]; - - /* Offset is signed so we have to use ugly math =( */ - ea += offset / 8; - local_offset = offset % 8; - if(local_offset < 0) - { - local_offset += 8; - ea--; - } - width = ((width-1) & 31) + 1; - - data = m68ki_read_32(ea); - data = MASK_OUT_ABOVE_32(data< 32) - data |= (m68ki_read_8(ea+4) << local_offset) >> 8; - - FLAG_N = NFLAG_32(data); - data >>= (32 - width); - - FLAG_Z = data; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1) - offset++; - - REG_D[(word2>>12)&7] = offset; - - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bfffo_32_aw(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - sint offset = (word2>>6)&31; - sint local_offset; - uint width = word2; - uint data; - uint bit; - uint ea = EA_AW_8(); - - - if(BIT_B(word2)) - offset = MAKE_INT_32(REG_D[offset&7]); - if(BIT_5(word2)) - width = REG_D[width&7]; - - /* Offset is signed so we have to use ugly math =( */ - ea += offset / 8; - local_offset = offset % 8; - if(local_offset < 0) - { - local_offset += 8; - ea--; - } - width = ((width-1) & 31) + 1; - - data = m68ki_read_32(ea); - data = MASK_OUT_ABOVE_32(data< 32) - data |= (m68ki_read_8(ea+4) << local_offset) >> 8; - - FLAG_N = NFLAG_32(data); - data >>= (32 - width); - - FLAG_Z = data; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1) - offset++; - - REG_D[(word2>>12)&7] = offset; - - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bfffo_32_al(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - sint offset = (word2>>6)&31; - sint local_offset; - uint width = word2; - uint data; - uint bit; - uint ea = EA_AL_8(); - - - if(BIT_B(word2)) - offset = MAKE_INT_32(REG_D[offset&7]); - if(BIT_5(word2)) - width = REG_D[width&7]; - - /* Offset is signed so we have to use ugly math =( */ - ea += offset / 8; - local_offset = offset % 8; - if(local_offset < 0) - { - local_offset += 8; - ea--; - } - width = ((width-1) & 31) + 1; - - data = m68ki_read_32(ea); - data = MASK_OUT_ABOVE_32(data< 32) - data |= (m68ki_read_8(ea+4) << local_offset) >> 8; - - FLAG_N = NFLAG_32(data); - data >>= (32 - width); - - FLAG_Z = data; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1) - offset++; - - REG_D[(word2>>12)&7] = offset; - - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bfffo_32_pcdi(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - sint offset = (word2>>6)&31; - sint local_offset; - uint width = word2; - uint data; - uint bit; - uint ea = EA_PCDI_8(); - - - if(BIT_B(word2)) - offset = MAKE_INT_32(REG_D[offset&7]); - if(BIT_5(word2)) - width = REG_D[width&7]; - - /* Offset is signed so we have to use ugly math =( */ - ea += offset / 8; - local_offset = offset % 8; - if(local_offset < 0) - { - local_offset += 8; - ea--; - } - width = ((width-1) & 31) + 1; - - data = m68ki_read_32(ea); - data = MASK_OUT_ABOVE_32(data< 32) - data |= (m68ki_read_8(ea+4) << local_offset) >> 8; - - FLAG_N = NFLAG_32(data); - data >>= (32 - width); - - FLAG_Z = data; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1) - offset++; - - REG_D[(word2>>12)&7] = offset; - - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bfffo_32_pcix(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - sint offset = (word2>>6)&31; - sint local_offset; - uint width = word2; - uint data; - uint bit; - uint ea = EA_PCIX_8(); - - - if(BIT_B(word2)) - offset = MAKE_INT_32(REG_D[offset&7]); - if(BIT_5(word2)) - width = REG_D[width&7]; - - /* Offset is signed so we have to use ugly math =( */ - ea += offset / 8; - local_offset = offset % 8; - if(local_offset < 0) - { - local_offset += 8; - ea--; - } - width = ((width-1) & 31) + 1; - - data = m68ki_read_32(ea); - data = MASK_OUT_ABOVE_32(data< 32) - data |= (m68ki_read_8(ea+4) << local_offset) >> 8; - - FLAG_N = NFLAG_32(data); - data >>= (32 - width); - - FLAG_Z = data; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1) - offset++; - - REG_D[(word2>>12)&7] = offset; - - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bfins_32_d(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint offset = (word2>>6)&31; - uint width = word2; - uint* data = &DY; - uint64 mask; - uint64 insert = REG_D[(word2>>12)&7]; - - - if(BIT_B(word2)) - offset = REG_D[offset&7]; - if(BIT_5(word2)) - width = REG_D[width&7]; - - - offset &= 31; - width = ((width-1) & 31) + 1; - - - mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); - mask = ROR_32(mask, offset); - - insert = MASK_OUT_ABOVE_32(insert << (32 - width)); - FLAG_N = NFLAG_32(insert); - FLAG_Z = insert; - insert = ROR_32(insert, offset); - - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - *data &= ~mask; - *data |= insert; - - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bfins_32_ai(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - sint offset = (word2>>6)&31; - uint width = word2; - uint insert_base = REG_D[(word2>>12)&7]; - uint insert_long; - uint insert_byte; - uint mask_base; - uint data_long; - uint mask_long; - uint data_byte = 0; - uint mask_byte = 0; - uint ea = EA_AY_AI_8(); - - - if(BIT_B(word2)) - offset = MAKE_INT_32(REG_D[offset&7]); - if(BIT_5(word2)) - width = REG_D[width&7]; - - /* Offset is signed so we have to use ugly math =( */ - ea += offset / 8; - offset %= 8; - if(offset < 0) - { - offset += 8; - ea--; - } - width = ((width-1) & 31) + 1; - - mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); - mask_long = mask_base >> offset; - - insert_base = MASK_OUT_ABOVE_32(insert_base << (32 - width)); - FLAG_N = NFLAG_32(insert_base); - FLAG_Z = insert_base; - insert_long = insert_base >> offset; - - data_long = m68ki_read_32(ea); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - m68ki_write_32(ea, (data_long & ~mask_long) | insert_long); - - if((width + offset) > 32) - { - mask_byte = MASK_OUT_ABOVE_8(mask_base); - insert_byte = MASK_OUT_ABOVE_8(insert_base); - data_byte = m68ki_read_8(ea+4); - FLAG_Z |= (data_byte & mask_byte); - m68ki_write_8(ea+4, (data_byte & ~mask_byte) | insert_byte); - } - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bfins_32_di(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - sint offset = (word2>>6)&31; - uint width = word2; - uint insert_base = REG_D[(word2>>12)&7]; - uint insert_long; - uint insert_byte; - uint mask_base; - uint data_long; - uint mask_long; - uint data_byte = 0; - uint mask_byte = 0; - uint ea = EA_AY_DI_8(); - - - if(BIT_B(word2)) - offset = MAKE_INT_32(REG_D[offset&7]); - if(BIT_5(word2)) - width = REG_D[width&7]; - - /* Offset is signed so we have to use ugly math =( */ - ea += offset / 8; - offset %= 8; - if(offset < 0) - { - offset += 8; - ea--; - } - width = ((width-1) & 31) + 1; - - mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); - mask_long = mask_base >> offset; - - insert_base = MASK_OUT_ABOVE_32(insert_base << (32 - width)); - FLAG_N = NFLAG_32(insert_base); - FLAG_Z = insert_base; - insert_long = insert_base >> offset; - - data_long = m68ki_read_32(ea); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - m68ki_write_32(ea, (data_long & ~mask_long) | insert_long); - - if((width + offset) > 32) - { - mask_byte = MASK_OUT_ABOVE_8(mask_base); - insert_byte = MASK_OUT_ABOVE_8(insert_base); - data_byte = m68ki_read_8(ea+4); - FLAG_Z |= (data_byte & mask_byte); - m68ki_write_8(ea+4, (data_byte & ~mask_byte) | insert_byte); - } - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bfins_32_ix(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - sint offset = (word2>>6)&31; - uint width = word2; - uint insert_base = REG_D[(word2>>12)&7]; - uint insert_long; - uint insert_byte; - uint mask_base; - uint data_long; - uint mask_long; - uint data_byte = 0; - uint mask_byte = 0; - uint ea = EA_AY_IX_8(); - - - if(BIT_B(word2)) - offset = MAKE_INT_32(REG_D[offset&7]); - if(BIT_5(word2)) - width = REG_D[width&7]; - - /* Offset is signed so we have to use ugly math =( */ - ea += offset / 8; - offset %= 8; - if(offset < 0) - { - offset += 8; - ea--; - } - width = ((width-1) & 31) + 1; - - mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); - mask_long = mask_base >> offset; - - insert_base = MASK_OUT_ABOVE_32(insert_base << (32 - width)); - FLAG_N = NFLAG_32(insert_base); - FLAG_Z = insert_base; - insert_long = insert_base >> offset; - - data_long = m68ki_read_32(ea); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - m68ki_write_32(ea, (data_long & ~mask_long) | insert_long); - - if((width + offset) > 32) - { - mask_byte = MASK_OUT_ABOVE_8(mask_base); - insert_byte = MASK_OUT_ABOVE_8(insert_base); - data_byte = m68ki_read_8(ea+4); - FLAG_Z |= (data_byte & mask_byte); - m68ki_write_8(ea+4, (data_byte & ~mask_byte) | insert_byte); - } - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bfins_32_aw(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - sint offset = (word2>>6)&31; - uint width = word2; - uint insert_base = REG_D[(word2>>12)&7]; - uint insert_long; - uint insert_byte; - uint mask_base; - uint data_long; - uint mask_long; - uint data_byte = 0; - uint mask_byte = 0; - uint ea = EA_AW_8(); - - - if(BIT_B(word2)) - offset = MAKE_INT_32(REG_D[offset&7]); - if(BIT_5(word2)) - width = REG_D[width&7]; - - /* Offset is signed so we have to use ugly math =( */ - ea += offset / 8; - offset %= 8; - if(offset < 0) - { - offset += 8; - ea--; - } - width = ((width-1) & 31) + 1; - - mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); - mask_long = mask_base >> offset; - - insert_base = MASK_OUT_ABOVE_32(insert_base << (32 - width)); - FLAG_N = NFLAG_32(insert_base); - FLAG_Z = insert_base; - insert_long = insert_base >> offset; - - data_long = m68ki_read_32(ea); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - m68ki_write_32(ea, (data_long & ~mask_long) | insert_long); - - if((width + offset) > 32) - { - mask_byte = MASK_OUT_ABOVE_8(mask_base); - insert_byte = MASK_OUT_ABOVE_8(insert_base); - data_byte = m68ki_read_8(ea+4); - FLAG_Z |= (data_byte & mask_byte); - m68ki_write_8(ea+4, (data_byte & ~mask_byte) | insert_byte); - } - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bfins_32_al(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - sint offset = (word2>>6)&31; - uint width = word2; - uint insert_base = REG_D[(word2>>12)&7]; - uint insert_long; - uint insert_byte; - uint mask_base; - uint data_long; - uint mask_long; - uint data_byte = 0; - uint mask_byte = 0; - uint ea = EA_AL_8(); - - - if(BIT_B(word2)) - offset = MAKE_INT_32(REG_D[offset&7]); - if(BIT_5(word2)) - width = REG_D[width&7]; - - /* Offset is signed so we have to use ugly math =( */ - ea += offset / 8; - offset %= 8; - if(offset < 0) - { - offset += 8; - ea--; - } - width = ((width-1) & 31) + 1; - - mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); - mask_long = mask_base >> offset; - - insert_base = MASK_OUT_ABOVE_32(insert_base << (32 - width)); - FLAG_N = NFLAG_32(insert_base); - FLAG_Z = insert_base; - insert_long = insert_base >> offset; - - data_long = m68ki_read_32(ea); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - m68ki_write_32(ea, (data_long & ~mask_long) | insert_long); - - if((width + offset) > 32) - { - mask_byte = MASK_OUT_ABOVE_8(mask_base); - insert_byte = MASK_OUT_ABOVE_8(insert_base); - data_byte = m68ki_read_8(ea+4); - FLAG_Z |= (data_byte & mask_byte); - m68ki_write_8(ea+4, (data_byte & ~mask_byte) | insert_byte); - } - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bfset_32_d(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint offset = (word2>>6)&31; - uint width = word2; - uint* data = &DY; - uint64 mask; - - - if(BIT_B(word2)) - offset = REG_D[offset&7]; - if(BIT_5(word2)) - width = REG_D[width&7]; - - - offset &= 31; - width = ((width-1) & 31) + 1; - - - mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); - mask = ROR_32(mask, offset); - - FLAG_N = NFLAG_32(*data<>6)&31; - uint width = word2; - uint mask_base; - uint data_long; - uint mask_long; - uint data_byte = 0; - uint mask_byte = 0; - uint ea = EA_AY_AI_8(); - - - if(BIT_B(word2)) - offset = MAKE_INT_32(REG_D[offset&7]); - if(BIT_5(word2)) - width = REG_D[width&7]; - - /* Offset is signed so we have to use ugly math =( */ - ea += offset / 8; - offset %= 8; - if(offset < 0) - { - offset += 8; - ea--; - } - width = ((width-1) & 31) + 1; - - - mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); - mask_long = mask_base >> offset; - - data_long = m68ki_read_32(ea); - FLAG_N = NFLAG_32(data_long << offset); - FLAG_Z = data_long & mask_long; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - m68ki_write_32(ea, data_long | mask_long); - - if((width + offset) > 32) - { - mask_byte = MASK_OUT_ABOVE_8(mask_base); - data_byte = m68ki_read_8(ea+4); - FLAG_Z |= (data_byte & mask_byte); - m68ki_write_8(ea+4, data_byte | mask_byte); - } - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bfset_32_di(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - sint offset = (word2>>6)&31; - uint width = word2; - uint mask_base; - uint data_long; - uint mask_long; - uint data_byte = 0; - uint mask_byte = 0; - uint ea = EA_AY_DI_8(); - - - if(BIT_B(word2)) - offset = MAKE_INT_32(REG_D[offset&7]); - if(BIT_5(word2)) - width = REG_D[width&7]; - - /* Offset is signed so we have to use ugly math =( */ - ea += offset / 8; - offset %= 8; - if(offset < 0) - { - offset += 8; - ea--; - } - width = ((width-1) & 31) + 1; - - - mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); - mask_long = mask_base >> offset; - - data_long = m68ki_read_32(ea); - FLAG_N = NFLAG_32(data_long << offset); - FLAG_Z = data_long & mask_long; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - m68ki_write_32(ea, data_long | mask_long); - - if((width + offset) > 32) - { - mask_byte = MASK_OUT_ABOVE_8(mask_base); - data_byte = m68ki_read_8(ea+4); - FLAG_Z |= (data_byte & mask_byte); - m68ki_write_8(ea+4, data_byte | mask_byte); - } - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bfset_32_ix(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - sint offset = (word2>>6)&31; - uint width = word2; - uint mask_base; - uint data_long; - uint mask_long; - uint data_byte = 0; - uint mask_byte = 0; - uint ea = EA_AY_IX_8(); - - - if(BIT_B(word2)) - offset = MAKE_INT_32(REG_D[offset&7]); - if(BIT_5(word2)) - width = REG_D[width&7]; - - /* Offset is signed so we have to use ugly math =( */ - ea += offset / 8; - offset %= 8; - if(offset < 0) - { - offset += 8; - ea--; - } - width = ((width-1) & 31) + 1; - - - mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); - mask_long = mask_base >> offset; - - data_long = m68ki_read_32(ea); - FLAG_N = NFLAG_32(data_long << offset); - FLAG_Z = data_long & mask_long; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - m68ki_write_32(ea, data_long | mask_long); - - if((width + offset) > 32) - { - mask_byte = MASK_OUT_ABOVE_8(mask_base); - data_byte = m68ki_read_8(ea+4); - FLAG_Z |= (data_byte & mask_byte); - m68ki_write_8(ea+4, data_byte | mask_byte); - } - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bfset_32_aw(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - sint offset = (word2>>6)&31; - uint width = word2; - uint mask_base; - uint data_long; - uint mask_long; - uint data_byte = 0; - uint mask_byte = 0; - uint ea = EA_AW_8(); - - - if(BIT_B(word2)) - offset = MAKE_INT_32(REG_D[offset&7]); - if(BIT_5(word2)) - width = REG_D[width&7]; - - /* Offset is signed so we have to use ugly math =( */ - ea += offset / 8; - offset %= 8; - if(offset < 0) - { - offset += 8; - ea--; - } - width = ((width-1) & 31) + 1; - - - mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); - mask_long = mask_base >> offset; - - data_long = m68ki_read_32(ea); - FLAG_N = NFLAG_32(data_long << offset); - FLAG_Z = data_long & mask_long; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - m68ki_write_32(ea, data_long | mask_long); - - if((width + offset) > 32) - { - mask_byte = MASK_OUT_ABOVE_8(mask_base); - data_byte = m68ki_read_8(ea+4); - FLAG_Z |= (data_byte & mask_byte); - m68ki_write_8(ea+4, data_byte | mask_byte); - } - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bfset_32_al(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - sint offset = (word2>>6)&31; - uint width = word2; - uint mask_base; - uint data_long; - uint mask_long; - uint data_byte = 0; - uint mask_byte = 0; - uint ea = EA_AL_8(); - - - if(BIT_B(word2)) - offset = MAKE_INT_32(REG_D[offset&7]); - if(BIT_5(word2)) - width = REG_D[width&7]; - - /* Offset is signed so we have to use ugly math =( */ - ea += offset / 8; - offset %= 8; - if(offset < 0) - { - offset += 8; - ea--; - } - width = ((width-1) & 31) + 1; - - - mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); - mask_long = mask_base >> offset; - - data_long = m68ki_read_32(ea); - FLAG_N = NFLAG_32(data_long << offset); - FLAG_Z = data_long & mask_long; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - m68ki_write_32(ea, data_long | mask_long); - - if((width + offset) > 32) - { - mask_byte = MASK_OUT_ABOVE_8(mask_base); - data_byte = m68ki_read_8(ea+4); - FLAG_Z |= (data_byte & mask_byte); - m68ki_write_8(ea+4, data_byte | mask_byte); - } - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bftst_32_d(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint offset = (word2>>6)&31; - uint width = word2; - uint* data = &DY; - uint64 mask; - - - if(BIT_B(word2)) - offset = REG_D[offset&7]; - if(BIT_5(word2)) - width = REG_D[width&7]; - - - offset &= 31; - width = ((width-1) & 31) + 1; - - - mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); - mask = ROR_32(mask, offset); - - FLAG_N = NFLAG_32(*data<>6)&31; - uint width = word2; - uint mask_base; - uint data_long; - uint mask_long; - uint data_byte = 0; - uint mask_byte = 0; - uint ea = EA_AY_AI_8(); - - if(BIT_B(word2)) - offset = MAKE_INT_32(REG_D[offset&7]); - if(BIT_5(word2)) - width = REG_D[width&7]; - - /* Offset is signed so we have to use ugly math =( */ - ea += offset / 8; - offset %= 8; - if(offset < 0) - { - offset += 8; - ea--; - } - width = ((width-1) & 31) + 1; - - - mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); - mask_long = mask_base >> offset; - - data_long = m68ki_read_32(ea); - FLAG_N = ((data_long & (0x80000000 >> offset))<>24; - FLAG_Z = data_long & mask_long; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - if((width + offset) > 32) - { - mask_byte = MASK_OUT_ABOVE_8(mask_base); - data_byte = m68ki_read_8(ea+4); - FLAG_Z |= (data_byte & mask_byte); - } - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bftst_32_di(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - sint offset = (word2>>6)&31; - uint width = word2; - uint mask_base; - uint data_long; - uint mask_long; - uint data_byte = 0; - uint mask_byte = 0; - uint ea = EA_AY_DI_8(); - - if(BIT_B(word2)) - offset = MAKE_INT_32(REG_D[offset&7]); - if(BIT_5(word2)) - width = REG_D[width&7]; - - /* Offset is signed so we have to use ugly math =( */ - ea += offset / 8; - offset %= 8; - if(offset < 0) - { - offset += 8; - ea--; - } - width = ((width-1) & 31) + 1; - - - mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); - mask_long = mask_base >> offset; - - data_long = m68ki_read_32(ea); - FLAG_N = ((data_long & (0x80000000 >> offset))<>24; - FLAG_Z = data_long & mask_long; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - if((width + offset) > 32) - { - mask_byte = MASK_OUT_ABOVE_8(mask_base); - data_byte = m68ki_read_8(ea+4); - FLAG_Z |= (data_byte & mask_byte); - } - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bftst_32_ix(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - sint offset = (word2>>6)&31; - uint width = word2; - uint mask_base; - uint data_long; - uint mask_long; - uint data_byte = 0; - uint mask_byte = 0; - uint ea = EA_AY_IX_8(); - - if(BIT_B(word2)) - offset = MAKE_INT_32(REG_D[offset&7]); - if(BIT_5(word2)) - width = REG_D[width&7]; - - /* Offset is signed so we have to use ugly math =( */ - ea += offset / 8; - offset %= 8; - if(offset < 0) - { - offset += 8; - ea--; - } - width = ((width-1) & 31) + 1; - - - mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); - mask_long = mask_base >> offset; - - data_long = m68ki_read_32(ea); - FLAG_N = ((data_long & (0x80000000 >> offset))<>24; - FLAG_Z = data_long & mask_long; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - if((width + offset) > 32) - { - mask_byte = MASK_OUT_ABOVE_8(mask_base); - data_byte = m68ki_read_8(ea+4); - FLAG_Z |= (data_byte & mask_byte); - } - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bftst_32_aw(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - sint offset = (word2>>6)&31; - uint width = word2; - uint mask_base; - uint data_long; - uint mask_long; - uint data_byte = 0; - uint mask_byte = 0; - uint ea = EA_AW_8(); - - if(BIT_B(word2)) - offset = MAKE_INT_32(REG_D[offset&7]); - if(BIT_5(word2)) - width = REG_D[width&7]; - - /* Offset is signed so we have to use ugly math =( */ - ea += offset / 8; - offset %= 8; - if(offset < 0) - { - offset += 8; - ea--; - } - width = ((width-1) & 31) + 1; - - - mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); - mask_long = mask_base >> offset; - - data_long = m68ki_read_32(ea); - FLAG_N = ((data_long & (0x80000000 >> offset))<>24; - FLAG_Z = data_long & mask_long; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - if((width + offset) > 32) - { - mask_byte = MASK_OUT_ABOVE_8(mask_base); - data_byte = m68ki_read_8(ea+4); - FLAG_Z |= (data_byte & mask_byte); - } - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bftst_32_al(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - sint offset = (word2>>6)&31; - uint width = word2; - uint mask_base; - uint data_long; - uint mask_long; - uint data_byte = 0; - uint mask_byte = 0; - uint ea = EA_AL_8(); - - if(BIT_B(word2)) - offset = MAKE_INT_32(REG_D[offset&7]); - if(BIT_5(word2)) - width = REG_D[width&7]; - - /* Offset is signed so we have to use ugly math =( */ - ea += offset / 8; - offset %= 8; - if(offset < 0) - { - offset += 8; - ea--; - } - width = ((width-1) & 31) + 1; - - - mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); - mask_long = mask_base >> offset; - - data_long = m68ki_read_32(ea); - FLAG_N = ((data_long & (0x80000000 >> offset))<>24; - FLAG_Z = data_long & mask_long; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - if((width + offset) > 32) - { - mask_byte = MASK_OUT_ABOVE_8(mask_base); - data_byte = m68ki_read_8(ea+4); - FLAG_Z |= (data_byte & mask_byte); - } - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bftst_32_pcdi(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - sint offset = (word2>>6)&31; - uint width = word2; - uint mask_base; - uint data_long; - uint mask_long; - uint data_byte = 0; - uint mask_byte = 0; - uint ea = EA_PCDI_8(); - - if(BIT_B(word2)) - offset = MAKE_INT_32(REG_D[offset&7]); - if(BIT_5(word2)) - width = REG_D[width&7]; - - /* Offset is signed so we have to use ugly math =( */ - ea += offset / 8; - offset %= 8; - if(offset < 0) - { - offset += 8; - ea--; - } - width = ((width-1) & 31) + 1; - - - mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); - mask_long = mask_base >> offset; - - data_long = m68ki_read_32(ea); - FLAG_N = ((data_long & (0x80000000 >> offset))<>24; - FLAG_Z = data_long & mask_long; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - if((width + offset) > 32) - { - mask_byte = MASK_OUT_ABOVE_8(mask_base); - data_byte = m68ki_read_8(ea+4); - FLAG_Z |= (data_byte & mask_byte); - } - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bftst_32_pcix(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - sint offset = (word2>>6)&31; - uint width = word2; - uint mask_base; - uint data_long; - uint mask_long; - uint data_byte = 0; - uint mask_byte = 0; - uint ea = EA_PCIX_8(); - - if(BIT_B(word2)) - offset = MAKE_INT_32(REG_D[offset&7]); - if(BIT_5(word2)) - width = REG_D[width&7]; - - /* Offset is signed so we have to use ugly math =( */ - ea += offset / 8; - offset %= 8; - if(offset < 0) - { - offset += 8; - ea--; - } - width = ((width-1) & 31) + 1; - - - mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); - mask_long = mask_base >> offset; - - data_long = m68ki_read_32(ea); - FLAG_N = ((data_long & (0x80000000 >> offset))<>24; - FLAG_Z = data_long & mask_long; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - - if((width + offset) > 32) - { - mask_byte = MASK_OUT_ABOVE_8(mask_base); - data_byte = m68ki_read_8(ea+4); - FLAG_Z |= (data_byte & mask_byte); - } - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bkpt(void) -{ - if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) - { - m68ki_bkpt_ack(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE) ? REG_IR & 7 : 0); /* auto-disable (see m68kcpu.h) */ - } - m68ki_exception_illegal(); -} - - -void m68k_op_bra_8(void) -{ - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR)); - if(REG_PC == REG_PPC) - USE_ALL_CYCLES(); -} - - -void m68k_op_bra_16(void) -{ - uint offset = OPER_I_16(); - REG_PC -= 2; - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_16(offset); - if(REG_PC == REG_PPC) - USE_ALL_CYCLES(); -} - - -void m68k_op_bra_32(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint offset = OPER_I_32(); - REG_PC -= 4; - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_32(offset); - if(REG_PC == REG_PPC) - USE_ALL_CYCLES(); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_bset_32_r_d(void) -{ - uint* r_dst = &DY; - uint mask = 1 << (DX & 0x1f); - - FLAG_Z = *r_dst & mask; - *r_dst |= mask; -} - - -void m68k_op_bset_8_r_ai(void) -{ - uint ea = EA_AY_AI_8(); - uint src = m68ki_read_8(ea); - uint mask = 1 << (DX & 7); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src | mask); -} - - -void m68k_op_bset_8_r_pi(void) -{ - uint ea = EA_AY_PI_8(); - uint src = m68ki_read_8(ea); - uint mask = 1 << (DX & 7); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src | mask); -} - - -void m68k_op_bset_8_r_pi7(void) -{ - uint ea = EA_A7_PI_8(); - uint src = m68ki_read_8(ea); - uint mask = 1 << (DX & 7); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src | mask); -} - - -void m68k_op_bset_8_r_pd(void) -{ - uint ea = EA_AY_PD_8(); - uint src = m68ki_read_8(ea); - uint mask = 1 << (DX & 7); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src | mask); -} - - -void m68k_op_bset_8_r_pd7(void) -{ - uint ea = EA_A7_PD_8(); - uint src = m68ki_read_8(ea); - uint mask = 1 << (DX & 7); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src | mask); -} - - -void m68k_op_bset_8_r_di(void) -{ - uint ea = EA_AY_DI_8(); - uint src = m68ki_read_8(ea); - uint mask = 1 << (DX & 7); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src | mask); -} - - -void m68k_op_bset_8_r_ix(void) -{ - uint ea = EA_AY_IX_8(); - uint src = m68ki_read_8(ea); - uint mask = 1 << (DX & 7); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src | mask); -} - - -void m68k_op_bset_8_r_aw(void) -{ - uint ea = EA_AW_8(); - uint src = m68ki_read_8(ea); - uint mask = 1 << (DX & 7); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src | mask); -} - - -void m68k_op_bset_8_r_al(void) -{ - uint ea = EA_AL_8(); - uint src = m68ki_read_8(ea); - uint mask = 1 << (DX & 7); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src | mask); -} - - -void m68k_op_bset_32_s_d(void) -{ - uint* r_dst = &DY; - uint mask = 1 << (OPER_I_8() & 0x1f); - - FLAG_Z = *r_dst & mask; - *r_dst |= mask; -} - - -void m68k_op_bset_8_s_ai(void) -{ - uint mask = 1 << (OPER_I_8() & 7); - uint ea = EA_AY_AI_8(); - uint src = m68ki_read_8(ea); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src | mask); -} - - -void m68k_op_bset_8_s_pi(void) -{ - uint mask = 1 << (OPER_I_8() & 7); - uint ea = EA_AY_PI_8(); - uint src = m68ki_read_8(ea); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src | mask); -} - - -void m68k_op_bset_8_s_pi7(void) -{ - uint mask = 1 << (OPER_I_8() & 7); - uint ea = EA_A7_PI_8(); - uint src = m68ki_read_8(ea); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src | mask); -} - - -void m68k_op_bset_8_s_pd(void) -{ - uint mask = 1 << (OPER_I_8() & 7); - uint ea = EA_AY_PD_8(); - uint src = m68ki_read_8(ea); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src | mask); -} - - -void m68k_op_bset_8_s_pd7(void) -{ - uint mask = 1 << (OPER_I_8() & 7); - uint ea = EA_A7_PD_8(); - uint src = m68ki_read_8(ea); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src | mask); -} - - -void m68k_op_bset_8_s_di(void) -{ - uint mask = 1 << (OPER_I_8() & 7); - uint ea = EA_AY_DI_8(); - uint src = m68ki_read_8(ea); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src | mask); -} - - -void m68k_op_bset_8_s_ix(void) -{ - uint mask = 1 << (OPER_I_8() & 7); - uint ea = EA_AY_IX_8(); - uint src = m68ki_read_8(ea); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src | mask); -} - - -void m68k_op_bset_8_s_aw(void) -{ - uint mask = 1 << (OPER_I_8() & 7); - uint ea = EA_AW_8(); - uint src = m68ki_read_8(ea); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src | mask); -} - - -void m68k_op_bset_8_s_al(void) -{ - uint mask = 1 << (OPER_I_8() & 7); - uint ea = EA_AL_8(); - uint src = m68ki_read_8(ea); - - FLAG_Z = src & mask; - m68ki_write_8(ea, src | mask); -} - - -void m68k_op_bsr_8(void) -{ - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_push_32(REG_PC); - m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR)); -} - - -void m68k_op_bsr_16(void) -{ - uint offset = OPER_I_16(); - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_push_32(REG_PC); - REG_PC -= 2; - m68ki_branch_16(offset); -} - - -void m68k_op_bsr_32(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint offset = OPER_I_32(); - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_push_32(REG_PC); - REG_PC -= 4; - m68ki_branch_32(offset); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_btst_32_r_d(void) -{ - FLAG_Z = DY & (1 << (DX & 0x1f)); -} - - -void m68k_op_btst_8_r_ai(void) -{ - FLAG_Z = OPER_AY_AI_8() & (1 << (DX & 7)); -} - - -void m68k_op_btst_8_r_pi(void) -{ - FLAG_Z = OPER_AY_PI_8() & (1 << (DX & 7)); -} - - -void m68k_op_btst_8_r_pi7(void) -{ - FLAG_Z = OPER_A7_PI_8() & (1 << (DX & 7)); -} - - -void m68k_op_btst_8_r_pd(void) -{ - FLAG_Z = OPER_AY_PD_8() & (1 << (DX & 7)); -} - - -void m68k_op_btst_8_r_pd7(void) -{ - FLAG_Z = OPER_A7_PD_8() & (1 << (DX & 7)); -} - - -void m68k_op_btst_8_r_di(void) -{ - FLAG_Z = OPER_AY_DI_8() & (1 << (DX & 7)); -} - - -void m68k_op_btst_8_r_ix(void) -{ - FLAG_Z = OPER_AY_IX_8() & (1 << (DX & 7)); -} - - -void m68k_op_btst_8_r_aw(void) -{ - FLAG_Z = OPER_AW_8() & (1 << (DX & 7)); -} - - -void m68k_op_btst_8_r_al(void) -{ - FLAG_Z = OPER_AL_8() & (1 << (DX & 7)); -} - - -void m68k_op_btst_8_r_pcdi(void) -{ - FLAG_Z = OPER_PCDI_8() & (1 << (DX & 7)); -} - - -void m68k_op_btst_8_r_pcix(void) -{ - FLAG_Z = OPER_PCIX_8() & (1 << (DX & 7)); -} - - -void m68k_op_btst_8_r_i(void) -{ - FLAG_Z = OPER_I_8() & (1 << (DX & 7)); -} - - -void m68k_op_btst_32_s_d(void) -{ - FLAG_Z = DY & (1 << (OPER_I_8() & 0x1f)); -} - - -void m68k_op_btst_8_s_ai(void) -{ - uint bit = OPER_I_8() & 7; - - FLAG_Z = OPER_AY_AI_8() & (1 << bit); -} - - -void m68k_op_btst_8_s_pi(void) -{ - uint bit = OPER_I_8() & 7; - - FLAG_Z = OPER_AY_PI_8() & (1 << bit); -} - - -void m68k_op_btst_8_s_pi7(void) -{ - uint bit = OPER_I_8() & 7; - - FLAG_Z = OPER_A7_PI_8() & (1 << bit); -} - - -void m68k_op_btst_8_s_pd(void) -{ - uint bit = OPER_I_8() & 7; - - FLAG_Z = OPER_AY_PD_8() & (1 << bit); -} - - -void m68k_op_btst_8_s_pd7(void) -{ - uint bit = OPER_I_8() & 7; - - FLAG_Z = OPER_A7_PD_8() & (1 << bit); -} - - -void m68k_op_btst_8_s_di(void) -{ - uint bit = OPER_I_8() & 7; - - FLAG_Z = OPER_AY_DI_8() & (1 << bit); -} - - -void m68k_op_btst_8_s_ix(void) -{ - uint bit = OPER_I_8() & 7; - - FLAG_Z = OPER_AY_IX_8() & (1 << bit); -} - - -void m68k_op_btst_8_s_aw(void) -{ - uint bit = OPER_I_8() & 7; - - FLAG_Z = OPER_AW_8() & (1 << bit); -} - - -void m68k_op_btst_8_s_al(void) -{ - uint bit = OPER_I_8() & 7; - - FLAG_Z = OPER_AL_8() & (1 << bit); -} - - -void m68k_op_btst_8_s_pcdi(void) -{ - uint bit = OPER_I_8() & 7; - - FLAG_Z = OPER_PCDI_8() & (1 << bit); -} - - -void m68k_op_btst_8_s_pcix(void) -{ - uint bit = OPER_I_8() & 7; - - FLAG_Z = OPER_PCIX_8() & (1 << bit); -} - - -void m68k_op_callm_32_ai(void) -{ - /* note: watch out for pcrelative modes */ - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - { - uint ea = EA_AY_AI_32(); - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - REG_PC += 2; -(void)ea; /* just to avoid an 'unused variable' warning */ - M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", - m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, - m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_callm_32_di(void) -{ - /* note: watch out for pcrelative modes */ - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - { - uint ea = EA_AY_DI_32(); - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - REG_PC += 2; -(void)ea; /* just to avoid an 'unused variable' warning */ - M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", - m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, - m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_callm_32_ix(void) -{ - /* note: watch out for pcrelative modes */ - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - { - uint ea = EA_AY_IX_32(); - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - REG_PC += 2; -(void)ea; /* just to avoid an 'unused variable' warning */ - M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", - m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, - m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_callm_32_aw(void) -{ - /* note: watch out for pcrelative modes */ - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - { - uint ea = EA_AW_32(); - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - REG_PC += 2; -(void)ea; /* just to avoid an 'unused variable' warning */ - M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", - m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, - m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_callm_32_al(void) -{ - /* note: watch out for pcrelative modes */ - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - { - uint ea = EA_AL_32(); - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - REG_PC += 2; -(void)ea; /* just to avoid an 'unused variable' warning */ - M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", - m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, - m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_callm_32_pcdi(void) -{ - /* note: watch out for pcrelative modes */ - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - { - uint ea = EA_PCDI_32(); - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - REG_PC += 2; -(void)ea; /* just to avoid an 'unused variable' warning */ - M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", - m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, - m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_callm_32_pcix(void) -{ - /* note: watch out for pcrelative modes */ - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - { - uint ea = EA_PCIX_32(); - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - REG_PC += 2; -(void)ea; /* just to avoid an 'unused variable' warning */ - M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", - m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, - m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_cas_8_ai(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint ea = EA_AY_AI_8(); - uint dest = m68ki_read_8(ea); - uint* compare = ®_D[word2 & 7]; - uint res = dest - MASK_OUT_ABOVE_8(*compare); - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_V = VFLAG_SUB_8(*compare, dest, res); - FLAG_C = CFLAG_8(res); - - if(COND_NE()) - *compare = MASK_OUT_BELOW_8(*compare) | dest; - else - { - USE_CYCLES(3); - m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7])); - } - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_cas_8_pi(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint ea = EA_AY_PI_8(); - uint dest = m68ki_read_8(ea); - uint* compare = ®_D[word2 & 7]; - uint res = dest - MASK_OUT_ABOVE_8(*compare); - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_V = VFLAG_SUB_8(*compare, dest, res); - FLAG_C = CFLAG_8(res); - - if(COND_NE()) - *compare = MASK_OUT_BELOW_8(*compare) | dest; - else - { - USE_CYCLES(3); - m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7])); - } - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_cas_8_pi7(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint ea = EA_A7_PI_8(); - uint dest = m68ki_read_8(ea); - uint* compare = ®_D[word2 & 7]; - uint res = dest - MASK_OUT_ABOVE_8(*compare); - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_V = VFLAG_SUB_8(*compare, dest, res); - FLAG_C = CFLAG_8(res); - - if(COND_NE()) - *compare = MASK_OUT_BELOW_8(*compare) | dest; - else - { - USE_CYCLES(3); - m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7])); - } - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_cas_8_pd(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint ea = EA_AY_PD_8(); - uint dest = m68ki_read_8(ea); - uint* compare = ®_D[word2 & 7]; - uint res = dest - MASK_OUT_ABOVE_8(*compare); - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_V = VFLAG_SUB_8(*compare, dest, res); - FLAG_C = CFLAG_8(res); - - if(COND_NE()) - *compare = MASK_OUT_BELOW_8(*compare) | dest; - else - { - USE_CYCLES(3); - m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7])); - } - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_cas_8_pd7(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint ea = EA_A7_PD_8(); - uint dest = m68ki_read_8(ea); - uint* compare = ®_D[word2 & 7]; - uint res = dest - MASK_OUT_ABOVE_8(*compare); - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_V = VFLAG_SUB_8(*compare, dest, res); - FLAG_C = CFLAG_8(res); - - if(COND_NE()) - *compare = MASK_OUT_BELOW_8(*compare) | dest; - else - { - USE_CYCLES(3); - m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7])); - } - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_cas_8_di(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint ea = EA_AY_DI_8(); - uint dest = m68ki_read_8(ea); - uint* compare = ®_D[word2 & 7]; - uint res = dest - MASK_OUT_ABOVE_8(*compare); - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_V = VFLAG_SUB_8(*compare, dest, res); - FLAG_C = CFLAG_8(res); - - if(COND_NE()) - *compare = MASK_OUT_BELOW_8(*compare) | dest; - else - { - USE_CYCLES(3); - m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7])); - } - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_cas_8_ix(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint ea = EA_AY_IX_8(); - uint dest = m68ki_read_8(ea); - uint* compare = ®_D[word2 & 7]; - uint res = dest - MASK_OUT_ABOVE_8(*compare); - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_V = VFLAG_SUB_8(*compare, dest, res); - FLAG_C = CFLAG_8(res); - - if(COND_NE()) - *compare = MASK_OUT_BELOW_8(*compare) | dest; - else - { - USE_CYCLES(3); - m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7])); - } - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_cas_8_aw(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint ea = EA_AW_8(); - uint dest = m68ki_read_8(ea); - uint* compare = ®_D[word2 & 7]; - uint res = dest - MASK_OUT_ABOVE_8(*compare); - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_V = VFLAG_SUB_8(*compare, dest, res); - FLAG_C = CFLAG_8(res); - - if(COND_NE()) - *compare = MASK_OUT_BELOW_8(*compare) | dest; - else - { - USE_CYCLES(3); - m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7])); - } - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_cas_8_al(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint ea = EA_AL_8(); - uint dest = m68ki_read_8(ea); - uint* compare = ®_D[word2 & 7]; - uint res = dest - MASK_OUT_ABOVE_8(*compare); - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_V = VFLAG_SUB_8(*compare, dest, res); - FLAG_C = CFLAG_8(res); - - if(COND_NE()) - *compare = MASK_OUT_BELOW_8(*compare) | dest; - else - { - USE_CYCLES(3); - m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7])); - } - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_cas_16_ai(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint ea = EA_AY_AI_16(); - uint dest = m68ki_read_16(ea); - uint* compare = ®_D[word2 & 7]; - uint res = dest - MASK_OUT_ABOVE_16(*compare); - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_V = VFLAG_SUB_16(*compare, dest, res); - FLAG_C = CFLAG_16(res); - - if(COND_NE()) - *compare = MASK_OUT_BELOW_16(*compare) | dest; - else - { - USE_CYCLES(3); - m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7])); - } - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_cas_16_pi(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint ea = EA_AY_PI_16(); - uint dest = m68ki_read_16(ea); - uint* compare = ®_D[word2 & 7]; - uint res = dest - MASK_OUT_ABOVE_16(*compare); - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_V = VFLAG_SUB_16(*compare, dest, res); - FLAG_C = CFLAG_16(res); - - if(COND_NE()) - *compare = MASK_OUT_BELOW_16(*compare) | dest; - else - { - USE_CYCLES(3); - m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7])); - } - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_cas_16_pd(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint ea = EA_AY_PD_16(); - uint dest = m68ki_read_16(ea); - uint* compare = ®_D[word2 & 7]; - uint res = dest - MASK_OUT_ABOVE_16(*compare); - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_V = VFLAG_SUB_16(*compare, dest, res); - FLAG_C = CFLAG_16(res); - - if(COND_NE()) - *compare = MASK_OUT_BELOW_16(*compare) | dest; - else - { - USE_CYCLES(3); - m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7])); - } - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_cas_16_di(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint ea = EA_AY_DI_16(); - uint dest = m68ki_read_16(ea); - uint* compare = ®_D[word2 & 7]; - uint res = dest - MASK_OUT_ABOVE_16(*compare); - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_V = VFLAG_SUB_16(*compare, dest, res); - FLAG_C = CFLAG_16(res); - - if(COND_NE()) - *compare = MASK_OUT_BELOW_16(*compare) | dest; - else - { - USE_CYCLES(3); - m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7])); - } - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_cas_16_ix(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint ea = EA_AY_IX_16(); - uint dest = m68ki_read_16(ea); - uint* compare = ®_D[word2 & 7]; - uint res = dest - MASK_OUT_ABOVE_16(*compare); - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_V = VFLAG_SUB_16(*compare, dest, res); - FLAG_C = CFLAG_16(res); - - if(COND_NE()) - *compare = MASK_OUT_BELOW_16(*compare) | dest; - else - { - USE_CYCLES(3); - m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7])); - } - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_cas_16_aw(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint ea = EA_AW_16(); - uint dest = m68ki_read_16(ea); - uint* compare = ®_D[word2 & 7]; - uint res = dest - MASK_OUT_ABOVE_16(*compare); - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_V = VFLAG_SUB_16(*compare, dest, res); - FLAG_C = CFLAG_16(res); - - if(COND_NE()) - *compare = MASK_OUT_BELOW_16(*compare) | dest; - else - { - USE_CYCLES(3); - m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7])); - } - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_cas_16_al(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint ea = EA_AL_16(); - uint dest = m68ki_read_16(ea); - uint* compare = ®_D[word2 & 7]; - uint res = dest - MASK_OUT_ABOVE_16(*compare); - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_V = VFLAG_SUB_16(*compare, dest, res); - FLAG_C = CFLAG_16(res); - - if(COND_NE()) - *compare = MASK_OUT_BELOW_16(*compare) | dest; - else - { - USE_CYCLES(3); - m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7])); - } - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_cas_32_ai(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint ea = EA_AY_AI_32(); - uint dest = m68ki_read_32(ea); - uint* compare = ®_D[word2 & 7]; - uint res = dest - *compare; - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(*compare, dest, res); - FLAG_C = CFLAG_SUB_32(*compare, dest, res); - - if(COND_NE()) - *compare = dest; - else - { - USE_CYCLES(3); - m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]); - } - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_cas_32_pi(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint ea = EA_AY_PI_32(); - uint dest = m68ki_read_32(ea); - uint* compare = ®_D[word2 & 7]; - uint res = dest - *compare; - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(*compare, dest, res); - FLAG_C = CFLAG_SUB_32(*compare, dest, res); - - if(COND_NE()) - *compare = dest; - else - { - USE_CYCLES(3); - m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]); - } - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_cas_32_pd(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint ea = EA_AY_PD_32(); - uint dest = m68ki_read_32(ea); - uint* compare = ®_D[word2 & 7]; - uint res = dest - *compare; - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(*compare, dest, res); - FLAG_C = CFLAG_SUB_32(*compare, dest, res); - - if(COND_NE()) - *compare = dest; - else - { - USE_CYCLES(3); - m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]); - } - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_cas_32_di(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint ea = EA_AY_DI_32(); - uint dest = m68ki_read_32(ea); - uint* compare = ®_D[word2 & 7]; - uint res = dest - *compare; - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(*compare, dest, res); - FLAG_C = CFLAG_SUB_32(*compare, dest, res); - - if(COND_NE()) - *compare = dest; - else - { - USE_CYCLES(3); - m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]); - } - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_cas_32_ix(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint ea = EA_AY_IX_32(); - uint dest = m68ki_read_32(ea); - uint* compare = ®_D[word2 & 7]; - uint res = dest - *compare; - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(*compare, dest, res); - FLAG_C = CFLAG_SUB_32(*compare, dest, res); - - if(COND_NE()) - *compare = dest; - else - { - USE_CYCLES(3); - m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]); - } - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_cas_32_aw(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint ea = EA_AW_32(); - uint dest = m68ki_read_32(ea); - uint* compare = ®_D[word2 & 7]; - uint res = dest - *compare; - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(*compare, dest, res); - FLAG_C = CFLAG_SUB_32(*compare, dest, res); - - if(COND_NE()) - *compare = dest; - else - { - USE_CYCLES(3); - m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]); - } - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_cas_32_al(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint ea = EA_AL_32(); - uint dest = m68ki_read_32(ea); - uint* compare = ®_D[word2 & 7]; - uint res = dest - *compare; - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(*compare, dest, res); - FLAG_C = CFLAG_SUB_32(*compare, dest, res); - - if(COND_NE()) - *compare = dest; - else - { - USE_CYCLES(3); - m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]); - } - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_cas2_16(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_32(); - uint* compare1 = ®_D[(word2 >> 16) & 7]; - uint ea1 = REG_DA[(word2 >> 28) & 15]; - uint dest1 = m68ki_read_16(ea1); - uint res1 = dest1 - MASK_OUT_ABOVE_16(*compare1); - uint* compare2 = ®_D[word2 & 7]; - uint ea2 = REG_DA[(word2 >> 12) & 15]; - uint dest2 = m68ki_read_16(ea2); - uint res2; - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - FLAG_N = NFLAG_16(res1); - FLAG_Z = MASK_OUT_ABOVE_16(res1); - FLAG_V = VFLAG_SUB_16(*compare1, dest1, res1); - FLAG_C = CFLAG_16(res1); - - if(COND_EQ()) - { - res2 = dest2 - MASK_OUT_ABOVE_16(*compare2); - - FLAG_N = NFLAG_16(res2); - FLAG_Z = MASK_OUT_ABOVE_16(res2); - FLAG_V = VFLAG_SUB_16(*compare2, dest2, res2); - FLAG_C = CFLAG_16(res2); - - if(COND_EQ()) - { - USE_CYCLES(3); - m68ki_write_16(ea1, REG_D[(word2 >> 22) & 7]); - m68ki_write_16(ea2, REG_D[(word2 >> 6) & 7]); - return; - } - } - *compare1 = BIT_1F(word2) ? MAKE_INT_16(dest1) : MASK_OUT_BELOW_16(*compare1) | dest1; - *compare2 = BIT_F(word2) ? MAKE_INT_16(dest2) : MASK_OUT_BELOW_16(*compare2) | dest2; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_cas2_32(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_32(); - uint* compare1 = ®_D[(word2 >> 16) & 7]; - uint ea1 = REG_DA[(word2 >> 28) & 15]; - uint dest1 = m68ki_read_32(ea1); - uint res1 = dest1 - *compare1; - uint* compare2 = ®_D[word2 & 7]; - uint ea2 = REG_DA[(word2 >> 12) & 15]; - uint dest2 = m68ki_read_32(ea2); - uint res2; - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - FLAG_N = NFLAG_32(res1); - FLAG_Z = MASK_OUT_ABOVE_32(res1); - FLAG_V = VFLAG_SUB_32(*compare1, dest1, res1); - FLAG_C = CFLAG_SUB_32(*compare1, dest1, res1); - - if(COND_EQ()) - { - res2 = dest2 - *compare2; - - FLAG_N = NFLAG_32(res2); - FLAG_Z = MASK_OUT_ABOVE_32(res2); - FLAG_V = VFLAG_SUB_32(*compare2, dest2, res2); - FLAG_C = CFLAG_SUB_32(*compare2, dest2, res2); - - if(COND_EQ()) - { - USE_CYCLES(3); - m68ki_write_32(ea1, REG_D[(word2 >> 22) & 7]); - m68ki_write_32(ea2, REG_D[(word2 >> 6) & 7]); - return; - } - } - *compare1 = dest1; - *compare2 = dest2; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_chk_16_d(void) -{ - sint src = MAKE_INT_16(DX); - sint bound = MAKE_INT_16(DY); - - FLAG_Z = ZFLAG_16(src); /* Undocumented */ - FLAG_V = VFLAG_CLEAR; /* Undocumented */ - FLAG_C = CFLAG_CLEAR; /* Undocumented */ - - if(src >= 0 && src <= bound) - { - return; - } - FLAG_N = (src < 0)<<7; - m68ki_exception_trap(EXCEPTION_CHK); -} - - -void m68k_op_chk_16_ai(void) -{ - sint src = MAKE_INT_16(DX); - sint bound = MAKE_INT_16(OPER_AY_AI_16()); - - FLAG_Z = ZFLAG_16(src); /* Undocumented */ - FLAG_V = VFLAG_CLEAR; /* Undocumented */ - FLAG_C = CFLAG_CLEAR; /* Undocumented */ - - if(src >= 0 && src <= bound) - { - return; - } - FLAG_N = (src < 0)<<7; - m68ki_exception_trap(EXCEPTION_CHK); -} - - -void m68k_op_chk_16_pi(void) -{ - sint src = MAKE_INT_16(DX); - sint bound = MAKE_INT_16(OPER_AY_PI_16()); - - FLAG_Z = ZFLAG_16(src); /* Undocumented */ - FLAG_V = VFLAG_CLEAR; /* Undocumented */ - FLAG_C = CFLAG_CLEAR; /* Undocumented */ - - if(src >= 0 && src <= bound) - { - return; - } - FLAG_N = (src < 0)<<7; - m68ki_exception_trap(EXCEPTION_CHK); -} - - -void m68k_op_chk_16_pd(void) -{ - sint src = MAKE_INT_16(DX); - sint bound = MAKE_INT_16(OPER_AY_PD_16()); - - FLAG_Z = ZFLAG_16(src); /* Undocumented */ - FLAG_V = VFLAG_CLEAR; /* Undocumented */ - FLAG_C = CFLAG_CLEAR; /* Undocumented */ - - if(src >= 0 && src <= bound) - { - return; - } - FLAG_N = (src < 0)<<7; - m68ki_exception_trap(EXCEPTION_CHK); -} - - -void m68k_op_chk_16_di(void) -{ - sint src = MAKE_INT_16(DX); - sint bound = MAKE_INT_16(OPER_AY_DI_16()); - - FLAG_Z = ZFLAG_16(src); /* Undocumented */ - FLAG_V = VFLAG_CLEAR; /* Undocumented */ - FLAG_C = CFLAG_CLEAR; /* Undocumented */ - - if(src >= 0 && src <= bound) - { - return; - } - FLAG_N = (src < 0)<<7; - m68ki_exception_trap(EXCEPTION_CHK); -} - - -void m68k_op_chk_16_ix(void) -{ - sint src = MAKE_INT_16(DX); - sint bound = MAKE_INT_16(OPER_AY_IX_16()); - - FLAG_Z = ZFLAG_16(src); /* Undocumented */ - FLAG_V = VFLAG_CLEAR; /* Undocumented */ - FLAG_C = CFLAG_CLEAR; /* Undocumented */ - - if(src >= 0 && src <= bound) - { - return; - } - FLAG_N = (src < 0)<<7; - m68ki_exception_trap(EXCEPTION_CHK); -} - - -void m68k_op_chk_16_aw(void) -{ - sint src = MAKE_INT_16(DX); - sint bound = MAKE_INT_16(OPER_AW_16()); - - FLAG_Z = ZFLAG_16(src); /* Undocumented */ - FLAG_V = VFLAG_CLEAR; /* Undocumented */ - FLAG_C = CFLAG_CLEAR; /* Undocumented */ - - if(src >= 0 && src <= bound) - { - return; - } - FLAG_N = (src < 0)<<7; - m68ki_exception_trap(EXCEPTION_CHK); -} - - -void m68k_op_chk_16_al(void) -{ - sint src = MAKE_INT_16(DX); - sint bound = MAKE_INT_16(OPER_AL_16()); - - FLAG_Z = ZFLAG_16(src); /* Undocumented */ - FLAG_V = VFLAG_CLEAR; /* Undocumented */ - FLAG_C = CFLAG_CLEAR; /* Undocumented */ - - if(src >= 0 && src <= bound) - { - return; - } - FLAG_N = (src < 0)<<7; - m68ki_exception_trap(EXCEPTION_CHK); -} - - -void m68k_op_chk_16_pcdi(void) -{ - sint src = MAKE_INT_16(DX); - sint bound = MAKE_INT_16(OPER_PCDI_16()); - - FLAG_Z = ZFLAG_16(src); /* Undocumented */ - FLAG_V = VFLAG_CLEAR; /* Undocumented */ - FLAG_C = CFLAG_CLEAR; /* Undocumented */ - - if(src >= 0 && src <= bound) - { - return; - } - FLAG_N = (src < 0)<<7; - m68ki_exception_trap(EXCEPTION_CHK); -} - - -void m68k_op_chk_16_pcix(void) -{ - sint src = MAKE_INT_16(DX); - sint bound = MAKE_INT_16(OPER_PCIX_16()); - - FLAG_Z = ZFLAG_16(src); /* Undocumented */ - FLAG_V = VFLAG_CLEAR; /* Undocumented */ - FLAG_C = CFLAG_CLEAR; /* Undocumented */ - - if(src >= 0 && src <= bound) - { - return; - } - FLAG_N = (src < 0)<<7; - m68ki_exception_trap(EXCEPTION_CHK); -} - - -void m68k_op_chk_16_i(void) -{ - sint src = MAKE_INT_16(DX); - sint bound = MAKE_INT_16(OPER_I_16()); - - FLAG_Z = ZFLAG_16(src); /* Undocumented */ - FLAG_V = VFLAG_CLEAR; /* Undocumented */ - FLAG_C = CFLAG_CLEAR; /* Undocumented */ - - if(src >= 0 && src <= bound) - { - return; - } - FLAG_N = (src < 0)<<7; - m68ki_exception_trap(EXCEPTION_CHK); -} - - -void m68k_op_chk_32_d(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - sint src = MAKE_INT_32(DX); - sint bound = MAKE_INT_32(DY); - - FLAG_Z = ZFLAG_32(src); /* Undocumented */ - FLAG_V = VFLAG_CLEAR; /* Undocumented */ - FLAG_C = CFLAG_CLEAR; /* Undocumented */ - - if(src >= 0 && src <= bound) - { - return; - } - FLAG_N = (src < 0)<<7; - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_chk_32_ai(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - sint src = MAKE_INT_32(DX); - sint bound = MAKE_INT_32(OPER_AY_AI_32()); - - FLAG_Z = ZFLAG_32(src); /* Undocumented */ - FLAG_V = VFLAG_CLEAR; /* Undocumented */ - FLAG_C = CFLAG_CLEAR; /* Undocumented */ - - if(src >= 0 && src <= bound) - { - return; - } - FLAG_N = (src < 0)<<7; - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_chk_32_pi(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - sint src = MAKE_INT_32(DX); - sint bound = MAKE_INT_32(OPER_AY_PI_32()); - - FLAG_Z = ZFLAG_32(src); /* Undocumented */ - FLAG_V = VFLAG_CLEAR; /* Undocumented */ - FLAG_C = CFLAG_CLEAR; /* Undocumented */ - - if(src >= 0 && src <= bound) - { - return; - } - FLAG_N = (src < 0)<<7; - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_chk_32_pd(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - sint src = MAKE_INT_32(DX); - sint bound = MAKE_INT_32(OPER_AY_PD_32()); - - FLAG_Z = ZFLAG_32(src); /* Undocumented */ - FLAG_V = VFLAG_CLEAR; /* Undocumented */ - FLAG_C = CFLAG_CLEAR; /* Undocumented */ - - if(src >= 0 && src <= bound) - { - return; - } - FLAG_N = (src < 0)<<7; - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_chk_32_di(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - sint src = MAKE_INT_32(DX); - sint bound = MAKE_INT_32(OPER_AY_DI_32()); - - FLAG_Z = ZFLAG_32(src); /* Undocumented */ - FLAG_V = VFLAG_CLEAR; /* Undocumented */ - FLAG_C = CFLAG_CLEAR; /* Undocumented */ - - if(src >= 0 && src <= bound) - { - return; - } - FLAG_N = (src < 0)<<7; - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_chk_32_ix(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - sint src = MAKE_INT_32(DX); - sint bound = MAKE_INT_32(OPER_AY_IX_32()); - - FLAG_Z = ZFLAG_32(src); /* Undocumented */ - FLAG_V = VFLAG_CLEAR; /* Undocumented */ - FLAG_C = CFLAG_CLEAR; /* Undocumented */ - - if(src >= 0 && src <= bound) - { - return; - } - FLAG_N = (src < 0)<<7; - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_chk_32_aw(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - sint src = MAKE_INT_32(DX); - sint bound = MAKE_INT_32(OPER_AW_32()); - - FLAG_Z = ZFLAG_32(src); /* Undocumented */ - FLAG_V = VFLAG_CLEAR; /* Undocumented */ - FLAG_C = CFLAG_CLEAR; /* Undocumented */ - - if(src >= 0 && src <= bound) - { - return; - } - FLAG_N = (src < 0)<<7; - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_chk_32_al(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - sint src = MAKE_INT_32(DX); - sint bound = MAKE_INT_32(OPER_AL_32()); - - FLAG_Z = ZFLAG_32(src); /* Undocumented */ - FLAG_V = VFLAG_CLEAR; /* Undocumented */ - FLAG_C = CFLAG_CLEAR; /* Undocumented */ - - if(src >= 0 && src <= bound) - { - return; - } - FLAG_N = (src < 0)<<7; - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_chk_32_pcdi(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - sint src = MAKE_INT_32(DX); - sint bound = MAKE_INT_32(OPER_PCDI_32()); - - FLAG_Z = ZFLAG_32(src); /* Undocumented */ - FLAG_V = VFLAG_CLEAR; /* Undocumented */ - FLAG_C = CFLAG_CLEAR; /* Undocumented */ - - if(src >= 0 && src <= bound) - { - return; - } - FLAG_N = (src < 0)<<7; - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_chk_32_pcix(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - sint src = MAKE_INT_32(DX); - sint bound = MAKE_INT_32(OPER_PCIX_32()); - - FLAG_Z = ZFLAG_32(src); /* Undocumented */ - FLAG_V = VFLAG_CLEAR; /* Undocumented */ - FLAG_C = CFLAG_CLEAR; /* Undocumented */ - - if(src >= 0 && src <= bound) - { - return; - } - FLAG_N = (src < 0)<<7; - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_chk_32_i(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - sint src = MAKE_INT_32(DX); - sint bound = MAKE_INT_32(OPER_I_32()); - - FLAG_Z = ZFLAG_32(src); /* Undocumented */ - FLAG_V = VFLAG_CLEAR; /* Undocumented */ - FLAG_C = CFLAG_CLEAR; /* Undocumented */ - - if(src >= 0 && src <= bound) - { - return; - } - FLAG_N = (src < 0)<<7; - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_chk2cmp2_8_pcdi(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint compare = REG_DA[(word2 >> 12) & 15]&0xff; - uint ea = EA_PCDI_8(); - uint lower_bound = m68ki_read_pcrel_8(ea); - uint upper_bound = m68ki_read_pcrel_8(ea + 1); - - if(!BIT_F(word2)) - FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound); - else - FLAG_C = compare - lower_bound; - FLAG_Z = !((upper_bound==compare) | (lower_bound==compare)); - if(COND_CS()) - { - if(BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - - FLAG_C = upper_bound - compare; - if(COND_CS() && BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_chk2cmp2_8_pcix(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint compare = REG_DA[(word2 >> 12) & 15]&0xff; - uint ea = EA_PCIX_8(); - uint lower_bound = m68ki_read_pcrel_8(ea); - uint upper_bound = m68ki_read_pcrel_8(ea + 1); - - if(!BIT_F(word2)) - FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound); - else - FLAG_C = compare - lower_bound; - FLAG_Z = !((upper_bound==compare) | (lower_bound==compare)); - if(COND_CS()) - { - if(BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - - FLAG_C = upper_bound - compare; - if(COND_CS() && BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_chk2cmp2_8_ai(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint compare = REG_DA[(word2 >> 12) & 15]&0xff; - uint ea = EA_AY_AI_8(); - uint lower_bound = m68ki_read_8(ea); - uint upper_bound = m68ki_read_8(ea + 1); - - if(!BIT_F(word2)) - FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound); - else - FLAG_C = compare - lower_bound; - FLAG_Z = !((upper_bound==compare) | (lower_bound==compare)); - if(COND_CS()) - { - if(BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - - FLAG_C = upper_bound - compare; - if(COND_CS() && BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_chk2cmp2_8_di(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint compare = REG_DA[(word2 >> 12) & 15]&0xff; - uint ea = EA_AY_DI_8(); - uint lower_bound = m68ki_read_8(ea); - uint upper_bound = m68ki_read_8(ea + 1); - - if(!BIT_F(word2)) - FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound); - else - FLAG_C = compare - lower_bound; - FLAG_Z = !((upper_bound==compare) | (lower_bound==compare)); - if(COND_CS()) - { - if(BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - - FLAG_C = upper_bound - compare; - if(COND_CS() && BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_chk2cmp2_8_ix(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint compare = REG_DA[(word2 >> 12) & 15]&0xff; - uint ea = EA_AY_IX_8(); - uint lower_bound = m68ki_read_8(ea); - uint upper_bound = m68ki_read_8(ea + 1); - - if(!BIT_F(word2)) - FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound); - else - FLAG_C = compare - lower_bound; - FLAG_Z = !((upper_bound==compare) | (lower_bound==compare)); - if(COND_CS()) - { - if(BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - - FLAG_C = upper_bound - compare; - if(COND_CS() && BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_chk2cmp2_8_aw(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint compare = REG_DA[(word2 >> 12) & 15]&0xff; - uint ea = EA_AW_8(); - uint lower_bound = m68ki_read_8(ea); - uint upper_bound = m68ki_read_8(ea + 1); - - if(!BIT_F(word2)) - FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound); - else - FLAG_C = compare - lower_bound; - FLAG_Z = !((upper_bound==compare) | (lower_bound==compare)); - if(COND_CS()) - { - if(BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - - FLAG_C = upper_bound - compare; - if(COND_CS() && BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_chk2cmp2_8_al(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint compare = REG_DA[(word2 >> 12) & 15]&0xff; - uint ea = EA_AL_8(); - uint lower_bound = m68ki_read_8(ea); - uint upper_bound = m68ki_read_8(ea + 1); - - if(!BIT_F(word2)) - FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound); - else - FLAG_C = compare - lower_bound; - FLAG_Z = !((upper_bound==compare) | (lower_bound==compare)); - if(COND_CS()) - { - if(BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - - FLAG_C = upper_bound - compare; - if(COND_CS() && BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_chk2cmp2_16_pcdi(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint compare = REG_DA[(word2 >> 12) & 15]&0xffff; - uint ea = EA_PCDI_16(); - uint lower_bound = m68ki_read_pcrel_16(ea); - uint upper_bound = m68ki_read_pcrel_16(ea + 2); - - if(!BIT_F(word2)) - FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound); - else - FLAG_C = compare - lower_bound; - FLAG_Z = !((upper_bound==compare) | (lower_bound==compare)); - FLAG_C = CFLAG_16(FLAG_C); - if(COND_CS()) - { - if(BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - - if(!BIT_F(word2)) - FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare); - else - FLAG_C = upper_bound - compare; - FLAG_C = CFLAG_16(FLAG_C); - if(COND_CS() && BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_chk2cmp2_16_pcix(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint compare = REG_DA[(word2 >> 12) & 15]&0xffff; - uint ea = EA_PCIX_16(); - uint lower_bound = m68ki_read_pcrel_16(ea); - uint upper_bound = m68ki_read_pcrel_16(ea + 2); - - if(!BIT_F(word2)) - FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound); - else - FLAG_C = compare - lower_bound; - FLAG_Z = !((upper_bound==compare) | (lower_bound==compare)); - FLAG_C = CFLAG_16(FLAG_C); - if(COND_CS()) - { - if(BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - - if(!BIT_F(word2)) - FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare); - else - FLAG_C = upper_bound - compare; - FLAG_C = CFLAG_16(FLAG_C); - if(COND_CS() && BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_chk2cmp2_16_ai(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint compare = REG_DA[(word2 >> 12) & 15]&0xffff; - uint ea = EA_AY_AI_16(); - uint lower_bound = m68ki_read_16(ea); - uint upper_bound = m68ki_read_16(ea + 2); - - if(!BIT_F(word2)) - FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound); - else - FLAG_C = compare - lower_bound; - - FLAG_Z = !((upper_bound==compare) | (lower_bound==compare)); - FLAG_C = CFLAG_16(FLAG_C); - if(COND_CS()) - { - if(BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - if(!BIT_F(word2)) - FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare); - else - FLAG_C = upper_bound - compare; - - FLAG_C = CFLAG_16(FLAG_C); - if(COND_CS() && BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_chk2cmp2_16_di(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint compare = REG_DA[(word2 >> 12) & 15]&0xffff; - uint ea = EA_AY_DI_16(); - uint lower_bound = m68ki_read_16(ea); - uint upper_bound = m68ki_read_16(ea + 2); - - if(!BIT_F(word2)) - FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound); - else - FLAG_C = compare - lower_bound; - - FLAG_Z = !((upper_bound==compare) | (lower_bound==compare)); - FLAG_C = CFLAG_16(FLAG_C); - if(COND_CS()) - { - if(BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - if(!BIT_F(word2)) - FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare); - else - FLAG_C = upper_bound - compare; - - FLAG_C = CFLAG_16(FLAG_C); - if(COND_CS() && BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_chk2cmp2_16_ix(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint compare = REG_DA[(word2 >> 12) & 15]&0xffff; - uint ea = EA_AY_IX_16(); - uint lower_bound = m68ki_read_16(ea); - uint upper_bound = m68ki_read_16(ea + 2); - - if(!BIT_F(word2)) - FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound); - else - FLAG_C = compare - lower_bound; - - FLAG_Z = !((upper_bound==compare) | (lower_bound==compare)); - FLAG_C = CFLAG_16(FLAG_C); - if(COND_CS()) - { - if(BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - if(!BIT_F(word2)) - FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare); - else - FLAG_C = upper_bound - compare; - - FLAG_C = CFLAG_16(FLAG_C); - if(COND_CS() && BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_chk2cmp2_16_aw(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint compare = REG_DA[(word2 >> 12) & 15]&0xffff; - uint ea = EA_AW_16(); - uint lower_bound = m68ki_read_16(ea); - uint upper_bound = m68ki_read_16(ea + 2); - - if(!BIT_F(word2)) - FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound); - else - FLAG_C = compare - lower_bound; - - FLAG_Z = !((upper_bound==compare) | (lower_bound==compare)); - FLAG_C = CFLAG_16(FLAG_C); - if(COND_CS()) - { - if(BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - if(!BIT_F(word2)) - FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare); - else - FLAG_C = upper_bound - compare; - - FLAG_C = CFLAG_16(FLAG_C); - if(COND_CS() && BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_chk2cmp2_16_al(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint compare = REG_DA[(word2 >> 12) & 15]&0xffff; - uint ea = EA_AL_16(); - uint lower_bound = m68ki_read_16(ea); - uint upper_bound = m68ki_read_16(ea + 2); - - if(!BIT_F(word2)) - FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound); - else - FLAG_C = compare - lower_bound; - - FLAG_Z = !((upper_bound==compare) | (lower_bound==compare)); - FLAG_C = CFLAG_16(FLAG_C); - if(COND_CS()) - { - if(BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - if(!BIT_F(word2)) - FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare); - else - FLAG_C = upper_bound - compare; - - FLAG_C = CFLAG_16(FLAG_C); - if(COND_CS() && BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_chk2cmp2_32_pcdi(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint compare = REG_DA[(word2 >> 12) & 15]; - uint ea = EA_PCDI_32(); - uint lower_bound = m68ki_read_pcrel_32(ea); - uint upper_bound = m68ki_read_pcrel_32(ea + 4); - - FLAG_C = compare - lower_bound; - FLAG_Z = !((upper_bound==compare) | (lower_bound==compare)); - FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C); - if(COND_CS()) - { - if(BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - - FLAG_C = upper_bound - compare; - FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C); - if(COND_CS() && BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_chk2cmp2_32_pcix(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint compare = REG_DA[(word2 >> 12) & 15]; - uint ea = EA_PCIX_32(); - uint lower_bound = m68ki_read_pcrel_32(ea); - uint upper_bound = m68ki_read_pcrel_32(ea + 4); - - FLAG_C = compare - lower_bound; - FLAG_Z = !((upper_bound==compare) | (lower_bound==compare)); - FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C); - if(COND_CS()) - { - if(BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - - FLAG_C = upper_bound - compare; - FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C); - if(COND_CS() && BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_chk2cmp2_32_ai(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint compare = REG_DA[(word2 >> 12) & 15]; - uint ea = EA_AY_AI_32(); - uint lower_bound = m68ki_read_32(ea); - uint upper_bound = m68ki_read_32(ea + 4); - - FLAG_C = compare - lower_bound; - FLAG_Z = !((upper_bound==compare) | (lower_bound==compare)); - FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C); - if(COND_CS()) - { - if(BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - - FLAG_C = upper_bound - compare; - FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C); - if(COND_CS() && BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_chk2cmp2_32_di(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint compare = REG_DA[(word2 >> 12) & 15]; - uint ea = EA_AY_DI_32(); - uint lower_bound = m68ki_read_32(ea); - uint upper_bound = m68ki_read_32(ea + 4); - - FLAG_C = compare - lower_bound; - FLAG_Z = !((upper_bound==compare) | (lower_bound==compare)); - FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C); - if(COND_CS()) - { - if(BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - - FLAG_C = upper_bound - compare; - FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C); - if(COND_CS() && BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_chk2cmp2_32_ix(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint compare = REG_DA[(word2 >> 12) & 15]; - uint ea = EA_AY_IX_32(); - uint lower_bound = m68ki_read_32(ea); - uint upper_bound = m68ki_read_32(ea + 4); - - FLAG_C = compare - lower_bound; - FLAG_Z = !((upper_bound==compare) | (lower_bound==compare)); - FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C); - if(COND_CS()) - { - if(BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - - FLAG_C = upper_bound - compare; - FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C); - if(COND_CS() && BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_chk2cmp2_32_aw(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint compare = REG_DA[(word2 >> 12) & 15]; - uint ea = EA_AW_32(); - uint lower_bound = m68ki_read_32(ea); - uint upper_bound = m68ki_read_32(ea + 4); - - FLAG_C = compare - lower_bound; - FLAG_Z = !((upper_bound==compare) | (lower_bound==compare)); - FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C); - if(COND_CS()) - { - if(BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - - FLAG_C = upper_bound - compare; - FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C); - if(COND_CS() && BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_chk2cmp2_32_al(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint compare = REG_DA[(word2 >> 12) & 15]; - uint ea = EA_AL_32(); - uint lower_bound = m68ki_read_32(ea); - uint upper_bound = m68ki_read_32(ea + 4); - - FLAG_C = compare - lower_bound; - FLAG_Z = !((upper_bound==compare) | (lower_bound==compare)); - FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C); - if(COND_CS()) - { - if(BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - - FLAG_C = upper_bound - compare; - FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C); - if(COND_CS() && BIT_B(word2)) - m68ki_exception_trap(EXCEPTION_CHK); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_clr_8_d(void) -{ - DY &= 0xffffff00; - - FLAG_N = NFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - FLAG_Z = ZFLAG_SET; -} - - -void m68k_op_clr_8_ai(void) -{ - m68ki_write_8(EA_AY_AI_8(), 0); - - FLAG_N = NFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - FLAG_Z = ZFLAG_SET; -} - - -void m68k_op_clr_8_pi(void) -{ - m68ki_write_8(EA_AY_PI_8(), 0); - - FLAG_N = NFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - FLAG_Z = ZFLAG_SET; -} - - -void m68k_op_clr_8_pi7(void) -{ - m68ki_write_8(EA_A7_PI_8(), 0); - - FLAG_N = NFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - FLAG_Z = ZFLAG_SET; -} - - -void m68k_op_clr_8_pd(void) -{ - m68ki_write_8(EA_AY_PD_8(), 0); - - FLAG_N = NFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - FLAG_Z = ZFLAG_SET; -} - - -void m68k_op_clr_8_pd7(void) -{ - m68ki_write_8(EA_A7_PD_8(), 0); - - FLAG_N = NFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - FLAG_Z = ZFLAG_SET; -} - - -void m68k_op_clr_8_di(void) -{ - m68ki_write_8(EA_AY_DI_8(), 0); - - FLAG_N = NFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - FLAG_Z = ZFLAG_SET; -} - - -void m68k_op_clr_8_ix(void) -{ - m68ki_write_8(EA_AY_IX_8(), 0); - - FLAG_N = NFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - FLAG_Z = ZFLAG_SET; -} - - -void m68k_op_clr_8_aw(void) -{ - m68ki_write_8(EA_AW_8(), 0); - - FLAG_N = NFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - FLAG_Z = ZFLAG_SET; -} - - -void m68k_op_clr_8_al(void) -{ - m68ki_write_8(EA_AL_8(), 0); - - FLAG_N = NFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - FLAG_Z = ZFLAG_SET; -} - - -void m68k_op_clr_16_d(void) -{ - DY &= 0xffff0000; - - FLAG_N = NFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - FLAG_Z = ZFLAG_SET; -} - - -void m68k_op_clr_16_ai(void) -{ - m68ki_write_16(EA_AY_AI_16(), 0); - - FLAG_N = NFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - FLAG_Z = ZFLAG_SET; -} - - -void m68k_op_clr_16_pi(void) -{ - m68ki_write_16(EA_AY_PI_16(), 0); - - FLAG_N = NFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - FLAG_Z = ZFLAG_SET; -} - - -void m68k_op_clr_16_pd(void) -{ - m68ki_write_16(EA_AY_PD_16(), 0); - - FLAG_N = NFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - FLAG_Z = ZFLAG_SET; -} - - -void m68k_op_clr_16_di(void) -{ - m68ki_write_16(EA_AY_DI_16(), 0); - - FLAG_N = NFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - FLAG_Z = ZFLAG_SET; -} - - -void m68k_op_clr_16_ix(void) -{ - m68ki_write_16(EA_AY_IX_16(), 0); - - FLAG_N = NFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - FLAG_Z = ZFLAG_SET; -} - - -void m68k_op_clr_16_aw(void) -{ - m68ki_write_16(EA_AW_16(), 0); - - FLAG_N = NFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - FLAG_Z = ZFLAG_SET; -} - - -void m68k_op_clr_16_al(void) -{ - m68ki_write_16(EA_AL_16(), 0); - - FLAG_N = NFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - FLAG_Z = ZFLAG_SET; -} - - -void m68k_op_clr_32_d(void) -{ - DY = 0; - - FLAG_N = NFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - FLAG_Z = ZFLAG_SET; -} - - -void m68k_op_clr_32_ai(void) -{ - m68ki_write_32(EA_AY_AI_32(), 0); - - FLAG_N = NFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - FLAG_Z = ZFLAG_SET; -} - - -void m68k_op_clr_32_pi(void) -{ - m68ki_write_32(EA_AY_PI_32(), 0); - - FLAG_N = NFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - FLAG_Z = ZFLAG_SET; -} - - -void m68k_op_clr_32_pd(void) -{ - m68ki_write_32(EA_AY_PD_32(), 0); - - FLAG_N = NFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - FLAG_Z = ZFLAG_SET; -} - - -void m68k_op_clr_32_di(void) -{ - m68ki_write_32(EA_AY_DI_32(), 0); - - FLAG_N = NFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - FLAG_Z = ZFLAG_SET; -} - - -void m68k_op_clr_32_ix(void) -{ - m68ki_write_32(EA_AY_IX_32(), 0); - - FLAG_N = NFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - FLAG_Z = ZFLAG_SET; -} - - -void m68k_op_clr_32_aw(void) -{ - m68ki_write_32(EA_AW_32(), 0); - - FLAG_N = NFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - FLAG_Z = ZFLAG_SET; -} - - -void m68k_op_clr_32_al(void) -{ - m68ki_write_32(EA_AL_32(), 0); - - FLAG_N = NFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - FLAG_Z = ZFLAG_SET; -} - - -void m68k_op_cmp_8_d(void) -{ - uint src = MASK_OUT_ABOVE_8(DY); - uint dst = MASK_OUT_ABOVE_8(DX); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - FLAG_C = CFLAG_8(res); -} - - -void m68k_op_cmp_8_ai(void) -{ - uint src = OPER_AY_AI_8(); - uint dst = MASK_OUT_ABOVE_8(DX); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - FLAG_C = CFLAG_8(res); -} - - -void m68k_op_cmp_8_pi(void) -{ - uint src = OPER_AY_PI_8(); - uint dst = MASK_OUT_ABOVE_8(DX); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - FLAG_C = CFLAG_8(res); -} - - -void m68k_op_cmp_8_pi7(void) -{ - uint src = OPER_A7_PI_8(); - uint dst = MASK_OUT_ABOVE_8(DX); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - FLAG_C = CFLAG_8(res); -} - - -void m68k_op_cmp_8_pd(void) -{ - uint src = OPER_AY_PD_8(); - uint dst = MASK_OUT_ABOVE_8(DX); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - FLAG_C = CFLAG_8(res); -} - - -void m68k_op_cmp_8_pd7(void) -{ - uint src = OPER_A7_PD_8(); - uint dst = MASK_OUT_ABOVE_8(DX); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - FLAG_C = CFLAG_8(res); -} - - -void m68k_op_cmp_8_di(void) -{ - uint src = OPER_AY_DI_8(); - uint dst = MASK_OUT_ABOVE_8(DX); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - FLAG_C = CFLAG_8(res); -} - - -void m68k_op_cmp_8_ix(void) -{ - uint src = OPER_AY_IX_8(); - uint dst = MASK_OUT_ABOVE_8(DX); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - FLAG_C = CFLAG_8(res); -} - - -void m68k_op_cmp_8_aw(void) -{ - uint src = OPER_AW_8(); - uint dst = MASK_OUT_ABOVE_8(DX); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - FLAG_C = CFLAG_8(res); -} - - -void m68k_op_cmp_8_al(void) -{ - uint src = OPER_AL_8(); - uint dst = MASK_OUT_ABOVE_8(DX); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - FLAG_C = CFLAG_8(res); -} - - -void m68k_op_cmp_8_pcdi(void) -{ - uint src = OPER_PCDI_8(); - uint dst = MASK_OUT_ABOVE_8(DX); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - FLAG_C = CFLAG_8(res); -} - - -void m68k_op_cmp_8_pcix(void) -{ - uint src = OPER_PCIX_8(); - uint dst = MASK_OUT_ABOVE_8(DX); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - FLAG_C = CFLAG_8(res); -} - - -void m68k_op_cmp_8_i(void) -{ - uint src = OPER_I_8(); - uint dst = MASK_OUT_ABOVE_8(DX); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - FLAG_C = CFLAG_8(res); -} - - -void m68k_op_cmp_16_d(void) -{ - uint src = MASK_OUT_ABOVE_16(DY); - uint dst = MASK_OUT_ABOVE_16(DX); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - FLAG_C = CFLAG_16(res); -} - - -void m68k_op_cmp_16_a(void) -{ - uint src = MASK_OUT_ABOVE_16(AY); - uint dst = MASK_OUT_ABOVE_16(DX); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - FLAG_C = CFLAG_16(res); -} - - -void m68k_op_cmp_16_ai(void) -{ - uint src = OPER_AY_AI_16(); - uint dst = MASK_OUT_ABOVE_16(DX); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - FLAG_C = CFLAG_16(res); -} - - -void m68k_op_cmp_16_pi(void) -{ - uint src = OPER_AY_PI_16(); - uint dst = MASK_OUT_ABOVE_16(DX); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - FLAG_C = CFLAG_16(res); -} - - -void m68k_op_cmp_16_pd(void) -{ - uint src = OPER_AY_PD_16(); - uint dst = MASK_OUT_ABOVE_16(DX); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - FLAG_C = CFLAG_16(res); -} - - -void m68k_op_cmp_16_di(void) -{ - uint src = OPER_AY_DI_16(); - uint dst = MASK_OUT_ABOVE_16(DX); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - FLAG_C = CFLAG_16(res); -} - - -void m68k_op_cmp_16_ix(void) -{ - uint src = OPER_AY_IX_16(); - uint dst = MASK_OUT_ABOVE_16(DX); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - FLAG_C = CFLAG_16(res); -} - - -void m68k_op_cmp_16_aw(void) -{ - uint src = OPER_AW_16(); - uint dst = MASK_OUT_ABOVE_16(DX); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - FLAG_C = CFLAG_16(res); -} - - -void m68k_op_cmp_16_al(void) -{ - uint src = OPER_AL_16(); - uint dst = MASK_OUT_ABOVE_16(DX); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - FLAG_C = CFLAG_16(res); -} - - -void m68k_op_cmp_16_pcdi(void) -{ - uint src = OPER_PCDI_16(); - uint dst = MASK_OUT_ABOVE_16(DX); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - FLAG_C = CFLAG_16(res); -} - - -void m68k_op_cmp_16_pcix(void) -{ - uint src = OPER_PCIX_16(); - uint dst = MASK_OUT_ABOVE_16(DX); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - FLAG_C = CFLAG_16(res); -} - - -void m68k_op_cmp_16_i(void) -{ - uint src = OPER_I_16(); - uint dst = MASK_OUT_ABOVE_16(DX); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - FLAG_C = CFLAG_16(res); -} - - -void m68k_op_cmp_32_d(void) -{ - uint src = DY; - uint dst = DX; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); -} - - -void m68k_op_cmp_32_a(void) -{ - uint src = AY; - uint dst = DX; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); -} - - -void m68k_op_cmp_32_ai(void) -{ - uint src = OPER_AY_AI_32(); - uint dst = DX; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); -} - - -void m68k_op_cmp_32_pi(void) -{ - uint src = OPER_AY_PI_32(); - uint dst = DX; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); -} - - -void m68k_op_cmp_32_pd(void) -{ - uint src = OPER_AY_PD_32(); - uint dst = DX; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); -} - - -void m68k_op_cmp_32_di(void) -{ - uint src = OPER_AY_DI_32(); - uint dst = DX; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); -} - - -void m68k_op_cmp_32_ix(void) -{ - uint src = OPER_AY_IX_32(); - uint dst = DX; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); -} - - -void m68k_op_cmp_32_aw(void) -{ - uint src = OPER_AW_32(); - uint dst = DX; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); -} - - -void m68k_op_cmp_32_al(void) -{ - uint src = OPER_AL_32(); - uint dst = DX; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); -} - - -void m68k_op_cmp_32_pcdi(void) -{ - uint src = OPER_PCDI_32(); - uint dst = DX; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); -} - - -void m68k_op_cmp_32_pcix(void) -{ - uint src = OPER_PCIX_32(); - uint dst = DX; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); -} - - -void m68k_op_cmp_32_i(void) -{ - uint src = OPER_I_32(); - uint dst = DX; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); -} - - -void m68k_op_cmpa_16_d(void) -{ - uint src = MAKE_INT_16(DY); - uint dst = AX; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); -} - - -void m68k_op_cmpa_16_a(void) -{ - uint src = MAKE_INT_16(AY); - uint dst = AX; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); -} - - -void m68k_op_cmpa_16_ai(void) -{ - uint src = MAKE_INT_16(OPER_AY_AI_16()); - uint dst = AX; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); -} - - -void m68k_op_cmpa_16_pi(void) -{ - uint src = MAKE_INT_16(OPER_AY_PI_16()); - uint dst = AX; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); -} - - -void m68k_op_cmpa_16_pd(void) -{ - uint src = MAKE_INT_16(OPER_AY_PD_16()); - uint dst = AX; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); -} - - -void m68k_op_cmpa_16_di(void) -{ - uint src = MAKE_INT_16(OPER_AY_DI_16()); - uint dst = AX; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); -} - - -void m68k_op_cmpa_16_ix(void) -{ - uint src = MAKE_INT_16(OPER_AY_IX_16()); - uint dst = AX; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); -} - - -void m68k_op_cmpa_16_aw(void) -{ - uint src = MAKE_INT_16(OPER_AW_16()); - uint dst = AX; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); -} - - -void m68k_op_cmpa_16_al(void) -{ - uint src = MAKE_INT_16(OPER_AL_16()); - uint dst = AX; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); -} - - -void m68k_op_cmpa_16_pcdi(void) -{ - uint src = MAKE_INT_16(OPER_PCDI_16()); - uint dst = AX; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); -} - - -void m68k_op_cmpa_16_pcix(void) -{ - uint src = MAKE_INT_16(OPER_PCIX_16()); - uint dst = AX; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); -} - - -void m68k_op_cmpa_16_i(void) -{ - uint src = MAKE_INT_16(OPER_I_16()); - uint dst = AX; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); -} - - -void m68k_op_cmpa_32_d(void) -{ - uint src = DY; - uint dst = AX; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); -} - - -void m68k_op_cmpa_32_a(void) -{ - uint src = AY; - uint dst = AX; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); -} - - -void m68k_op_cmpa_32_ai(void) -{ - uint src = OPER_AY_AI_32(); - uint dst = AX; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); -} - - -void m68k_op_cmpa_32_pi(void) -{ - uint src = OPER_AY_PI_32(); - uint dst = AX; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); -} - - -void m68k_op_cmpa_32_pd(void) -{ - uint src = OPER_AY_PD_32(); - uint dst = AX; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); -} - - -void m68k_op_cmpa_32_di(void) -{ - uint src = OPER_AY_DI_32(); - uint dst = AX; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); -} - - -void m68k_op_cmpa_32_ix(void) -{ - uint src = OPER_AY_IX_32(); - uint dst = AX; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); -} - - -void m68k_op_cmpa_32_aw(void) -{ - uint src = OPER_AW_32(); - uint dst = AX; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); -} - - -void m68k_op_cmpa_32_al(void) -{ - uint src = OPER_AL_32(); - uint dst = AX; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); -} - - -void m68k_op_cmpa_32_pcdi(void) -{ - uint src = OPER_PCDI_32(); - uint dst = AX; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); -} - - -void m68k_op_cmpa_32_pcix(void) -{ - uint src = OPER_PCIX_32(); - uint dst = AX; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); -} - - -void m68k_op_cmpa_32_i(void) -{ - uint src = OPER_I_32(); - uint dst = AX; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); -} - - -void m68k_op_cmpi_8_d(void) -{ - uint src = OPER_I_8(); - uint dst = MASK_OUT_ABOVE_8(DY); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - FLAG_C = CFLAG_8(res); -} - - -void m68k_op_cmpi_8_ai(void) -{ - uint src = OPER_I_8(); - uint dst = OPER_AY_AI_8(); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - FLAG_C = CFLAG_8(res); -} - - -void m68k_op_cmpi_8_pi(void) -{ - uint src = OPER_I_8(); - uint dst = OPER_AY_PI_8(); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - FLAG_C = CFLAG_8(res); -} - - -void m68k_op_cmpi_8_pi7(void) -{ - uint src = OPER_I_8(); - uint dst = OPER_A7_PI_8(); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - FLAG_C = CFLAG_8(res); -} - - -void m68k_op_cmpi_8_pd(void) -{ - uint src = OPER_I_8(); - uint dst = OPER_AY_PD_8(); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - FLAG_C = CFLAG_8(res); -} - - -void m68k_op_cmpi_8_pd7(void) -{ - uint src = OPER_I_8(); - uint dst = OPER_A7_PD_8(); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - FLAG_C = CFLAG_8(res); -} - - -void m68k_op_cmpi_8_di(void) -{ - uint src = OPER_I_8(); - uint dst = OPER_AY_DI_8(); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - FLAG_C = CFLAG_8(res); -} - - -void m68k_op_cmpi_8_ix(void) -{ - uint src = OPER_I_8(); - uint dst = OPER_AY_IX_8(); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - FLAG_C = CFLAG_8(res); -} - - -void m68k_op_cmpi_8_aw(void) -{ - uint src = OPER_I_8(); - uint dst = OPER_AW_8(); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - FLAG_C = CFLAG_8(res); -} - - -void m68k_op_cmpi_8_al(void) -{ - uint src = OPER_I_8(); - uint dst = OPER_AL_8(); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - FLAG_C = CFLAG_8(res); -} - - -void m68k_op_cmpi_8_pcdi(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint src = OPER_I_8(); - uint dst = OPER_PCDI_8(); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - FLAG_C = CFLAG_8(res); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_cmpi_8_pcix(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint src = OPER_I_8(); - uint dst = OPER_PCIX_8(); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - FLAG_C = CFLAG_8(res); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_cmpi_16_d(void) -{ - uint src = OPER_I_16(); - uint dst = MASK_OUT_ABOVE_16(DY); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - FLAG_C = CFLAG_16(res); -} - - -void m68k_op_cmpi_16_ai(void) -{ - uint src = OPER_I_16(); - uint dst = OPER_AY_AI_16(); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - FLAG_C = CFLAG_16(res); -} - - -void m68k_op_cmpi_16_pi(void) -{ - uint src = OPER_I_16(); - uint dst = OPER_AY_PI_16(); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - FLAG_C = CFLAG_16(res); -} - - -void m68k_op_cmpi_16_pd(void) -{ - uint src = OPER_I_16(); - uint dst = OPER_AY_PD_16(); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - FLAG_C = CFLAG_16(res); -} - - -void m68k_op_cmpi_16_di(void) -{ - uint src = OPER_I_16(); - uint dst = OPER_AY_DI_16(); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - FLAG_C = CFLAG_16(res); -} - - -void m68k_op_cmpi_16_ix(void) -{ - uint src = OPER_I_16(); - uint dst = OPER_AY_IX_16(); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - FLAG_C = CFLAG_16(res); -} - - -void m68k_op_cmpi_16_aw(void) -{ - uint src = OPER_I_16(); - uint dst = OPER_AW_16(); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - FLAG_C = CFLAG_16(res); -} - - -void m68k_op_cmpi_16_al(void) -{ - uint src = OPER_I_16(); - uint dst = OPER_AL_16(); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - FLAG_C = CFLAG_16(res); -} - - -void m68k_op_cmpi_16_pcdi(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint src = OPER_I_16(); - uint dst = OPER_PCDI_16(); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - FLAG_C = CFLAG_16(res); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_cmpi_16_pcix(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint src = OPER_I_16(); - uint dst = OPER_PCIX_16(); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - FLAG_C = CFLAG_16(res); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_cmpi_32_d(void) -{ - uint src = OPER_I_32(); - uint dst = DY; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); -} - - -void m68k_op_cmpi_32_ai(void) -{ - uint src = OPER_I_32(); - uint dst = OPER_AY_AI_32(); - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); -} - - -void m68k_op_cmpi_32_pi(void) -{ - uint src = OPER_I_32(); - uint dst = OPER_AY_PI_32(); - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); -} - - -void m68k_op_cmpi_32_pd(void) -{ - uint src = OPER_I_32(); - uint dst = OPER_AY_PD_32(); - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); -} - - -void m68k_op_cmpi_32_di(void) -{ - uint src = OPER_I_32(); - uint dst = OPER_AY_DI_32(); - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); -} - - -void m68k_op_cmpi_32_ix(void) -{ - uint src = OPER_I_32(); - uint dst = OPER_AY_IX_32(); - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); -} - - -void m68k_op_cmpi_32_aw(void) -{ - uint src = OPER_I_32(); - uint dst = OPER_AW_32(); - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); -} - - -void m68k_op_cmpi_32_al(void) -{ - uint src = OPER_I_32(); - uint dst = OPER_AL_32(); - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); -} - - -void m68k_op_cmpi_32_pcdi(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint src = OPER_I_32(); - uint dst = OPER_PCDI_32(); - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_cmpi_32_pcix(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint src = OPER_I_32(); - uint dst = OPER_PCIX_32(); - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_cmpm_8_ax7(void) -{ - uint src = OPER_AY_PI_8(); - uint dst = OPER_A7_PI_8(); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - FLAG_C = CFLAG_8(res); -} - - -void m68k_op_cmpm_8_ay7(void) -{ - uint src = OPER_A7_PI_8(); - uint dst = OPER_AX_PI_8(); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - FLAG_C = CFLAG_8(res); -} - - -void m68k_op_cmpm_8_axy7(void) -{ - uint src = OPER_A7_PI_8(); - uint dst = OPER_A7_PI_8(); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - FLAG_C = CFLAG_8(res); -} - - -void m68k_op_cmpm_8(void) -{ - uint src = OPER_AY_PI_8(); - uint dst = OPER_AX_PI_8(); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - FLAG_C = CFLAG_8(res); -} - - -void m68k_op_cmpm_16(void) -{ - uint src = OPER_AY_PI_16(); - uint dst = OPER_AX_PI_16(); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - FLAG_C = CFLAG_16(res); -} - - -void m68k_op_cmpm_32(void) -{ - uint src = OPER_AY_PI_32(); - uint dst = OPER_AX_PI_32(); - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_C = CFLAG_SUB_32(src, dst, res); -} - - -void m68k_op_cpbcc_32(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", - m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, - m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); - return; - } - m68ki_exception_1111(); -} - - -void m68k_op_cpdbcc_32(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", - m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, - m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); - return; - } - m68ki_exception_1111(); -} - - -void m68k_op_cpgen_32(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", - m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, - m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); - return; - } - m68ki_exception_1111(); -} - - -void m68k_op_cpscc_32(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", - m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, - m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); - return; - } - m68ki_exception_1111(); -} - - -void m68k_op_cptrapcc_32(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", - m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, - m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); - return; - } - m68ki_exception_1111(); -} - - -/* ======================================================================== */ -/* ============================== END OF FILE ============================= */ -/* ======================================================================== */ - - diff --git a/Frameworks/AudioOverload/aosdk/eng_ssf/m68kopdm.c b/Frameworks/AudioOverload/aosdk/eng_ssf/m68kopdm.c deleted file mode 100644 index deb3586bb..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_ssf/m68kopdm.c +++ /dev/null @@ -1,13221 +0,0 @@ -#include "m68kcpu.h" - -/* ======================================================================== */ -/* ========================= INSTRUCTION HANDLERS ========================= */ -/* ======================================================================== */ - - -void m68k_op_dbt_16(void) -{ - REG_PC += 2; -} - - -void m68k_op_dbf_16(void) -{ - uint* r_dst = &DY; - uint res = MASK_OUT_ABOVE_16(*r_dst - 1); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; - if(res != 0xffff) - { - uint offset = OPER_I_16(); - REG_PC -= 2; - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_16(offset); - return; - } - REG_PC += 2; -} - - -void m68k_op_dbhi_16(void) -{ - if(COND_NOT_HI()) - { - uint* r_dst = &DY; - uint res = MASK_OUT_ABOVE_16(*r_dst - 1); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; - if(res != 0xffff) - { - uint offset = OPER_I_16(); - REG_PC -= 2; - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_16(offset); - USE_CYCLES(CYC_DBCC_F_NOEXP); - return; - } - REG_PC += 2; - USE_CYCLES(CYC_DBCC_F_EXP); - return; - } - REG_PC += 2; -} - - -void m68k_op_dbls_16(void) -{ - if(COND_NOT_LS()) - { - uint* r_dst = &DY; - uint res = MASK_OUT_ABOVE_16(*r_dst - 1); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; - if(res != 0xffff) - { - uint offset = OPER_I_16(); - REG_PC -= 2; - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_16(offset); - USE_CYCLES(CYC_DBCC_F_NOEXP); - return; - } - REG_PC += 2; - USE_CYCLES(CYC_DBCC_F_EXP); - return; - } - REG_PC += 2; -} - - -void m68k_op_dbcc_16(void) -{ - if(COND_NOT_CC()) - { - uint* r_dst = &DY; - uint res = MASK_OUT_ABOVE_16(*r_dst - 1); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; - if(res != 0xffff) - { - uint offset = OPER_I_16(); - REG_PC -= 2; - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_16(offset); - USE_CYCLES(CYC_DBCC_F_NOEXP); - return; - } - REG_PC += 2; - USE_CYCLES(CYC_DBCC_F_EXP); - return; - } - REG_PC += 2; -} - - -void m68k_op_dbcs_16(void) -{ - if(COND_NOT_CS()) - { - uint* r_dst = &DY; - uint res = MASK_OUT_ABOVE_16(*r_dst - 1); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; - if(res != 0xffff) - { - uint offset = OPER_I_16(); - REG_PC -= 2; - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_16(offset); - USE_CYCLES(CYC_DBCC_F_NOEXP); - return; - } - REG_PC += 2; - USE_CYCLES(CYC_DBCC_F_EXP); - return; - } - REG_PC += 2; -} - - -void m68k_op_dbne_16(void) -{ - if(COND_NOT_NE()) - { - uint* r_dst = &DY; - uint res = MASK_OUT_ABOVE_16(*r_dst - 1); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; - if(res != 0xffff) - { - uint offset = OPER_I_16(); - REG_PC -= 2; - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_16(offset); - USE_CYCLES(CYC_DBCC_F_NOEXP); - return; - } - REG_PC += 2; - USE_CYCLES(CYC_DBCC_F_EXP); - return; - } - REG_PC += 2; -} - - -void m68k_op_dbeq_16(void) -{ - if(COND_NOT_EQ()) - { - uint* r_dst = &DY; - uint res = MASK_OUT_ABOVE_16(*r_dst - 1); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; - if(res != 0xffff) - { - uint offset = OPER_I_16(); - REG_PC -= 2; - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_16(offset); - USE_CYCLES(CYC_DBCC_F_NOEXP); - return; - } - REG_PC += 2; - USE_CYCLES(CYC_DBCC_F_EXP); - return; - } - REG_PC += 2; -} - - -void m68k_op_dbvc_16(void) -{ - if(COND_NOT_VC()) - { - uint* r_dst = &DY; - uint res = MASK_OUT_ABOVE_16(*r_dst - 1); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; - if(res != 0xffff) - { - uint offset = OPER_I_16(); - REG_PC -= 2; - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_16(offset); - USE_CYCLES(CYC_DBCC_F_NOEXP); - return; - } - REG_PC += 2; - USE_CYCLES(CYC_DBCC_F_EXP); - return; - } - REG_PC += 2; -} - - -void m68k_op_dbvs_16(void) -{ - if(COND_NOT_VS()) - { - uint* r_dst = &DY; - uint res = MASK_OUT_ABOVE_16(*r_dst - 1); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; - if(res != 0xffff) - { - uint offset = OPER_I_16(); - REG_PC -= 2; - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_16(offset); - USE_CYCLES(CYC_DBCC_F_NOEXP); - return; - } - REG_PC += 2; - USE_CYCLES(CYC_DBCC_F_EXP); - return; - } - REG_PC += 2; -} - - -void m68k_op_dbpl_16(void) -{ - if(COND_NOT_PL()) - { - uint* r_dst = &DY; - uint res = MASK_OUT_ABOVE_16(*r_dst - 1); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; - if(res != 0xffff) - { - uint offset = OPER_I_16(); - REG_PC -= 2; - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_16(offset); - USE_CYCLES(CYC_DBCC_F_NOEXP); - return; - } - REG_PC += 2; - USE_CYCLES(CYC_DBCC_F_EXP); - return; - } - REG_PC += 2; -} - - -void m68k_op_dbmi_16(void) -{ - if(COND_NOT_MI()) - { - uint* r_dst = &DY; - uint res = MASK_OUT_ABOVE_16(*r_dst - 1); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; - if(res != 0xffff) - { - uint offset = OPER_I_16(); - REG_PC -= 2; - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_16(offset); - USE_CYCLES(CYC_DBCC_F_NOEXP); - return; - } - REG_PC += 2; - USE_CYCLES(CYC_DBCC_F_EXP); - return; - } - REG_PC += 2; -} - - -void m68k_op_dbge_16(void) -{ - if(COND_NOT_GE()) - { - uint* r_dst = &DY; - uint res = MASK_OUT_ABOVE_16(*r_dst - 1); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; - if(res != 0xffff) - { - uint offset = OPER_I_16(); - REG_PC -= 2; - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_16(offset); - USE_CYCLES(CYC_DBCC_F_NOEXP); - return; - } - REG_PC += 2; - USE_CYCLES(CYC_DBCC_F_EXP); - return; - } - REG_PC += 2; -} - - -void m68k_op_dblt_16(void) -{ - if(COND_NOT_LT()) - { - uint* r_dst = &DY; - uint res = MASK_OUT_ABOVE_16(*r_dst - 1); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; - if(res != 0xffff) - { - uint offset = OPER_I_16(); - REG_PC -= 2; - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_16(offset); - USE_CYCLES(CYC_DBCC_F_NOEXP); - return; - } - REG_PC += 2; - USE_CYCLES(CYC_DBCC_F_EXP); - return; - } - REG_PC += 2; -} - - -void m68k_op_dbgt_16(void) -{ - if(COND_NOT_GT()) - { - uint* r_dst = &DY; - uint res = MASK_OUT_ABOVE_16(*r_dst - 1); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; - if(res != 0xffff) - { - uint offset = OPER_I_16(); - REG_PC -= 2; - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_16(offset); - USE_CYCLES(CYC_DBCC_F_NOEXP); - return; - } - REG_PC += 2; - USE_CYCLES(CYC_DBCC_F_EXP); - return; - } - REG_PC += 2; -} - - -void m68k_op_dble_16(void) -{ - if(COND_NOT_LE()) - { - uint* r_dst = &DY; - uint res = MASK_OUT_ABOVE_16(*r_dst - 1); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; - if(res != 0xffff) - { - uint offset = OPER_I_16(); - REG_PC -= 2; - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_branch_16(offset); - USE_CYCLES(CYC_DBCC_F_NOEXP); - return; - } - REG_PC += 2; - USE_CYCLES(CYC_DBCC_F_EXP); - return; - } - REG_PC += 2; -} - - -void m68k_op_divs_16_d(void) -{ - uint* r_dst = &DX; - sint src = MAKE_INT_16(DY); - sint quotient; - sint remainder; - - if(src != 0) - { - if((uint32)*r_dst == 0x80000000 && src == -1) - { - FLAG_Z = 0; - FLAG_N = NFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - *r_dst = 0; - return; - } - - quotient = MAKE_INT_32(*r_dst) / src; - remainder = MAKE_INT_32(*r_dst) % src; - - if(quotient == MAKE_INT_16(quotient)) - { - FLAG_Z = quotient; - FLAG_N = NFLAG_16(quotient); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); - return; - } - FLAG_V = VFLAG_SET; - return; - } - m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); -} - - -void m68k_op_divs_16_ai(void) -{ - uint* r_dst = &DX; - sint src = MAKE_INT_16(OPER_AY_AI_16()); - sint quotient; - sint remainder; - - if(src != 0) - { - if((uint32)*r_dst == 0x80000000 && src == -1) - { - FLAG_Z = 0; - FLAG_N = NFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - *r_dst = 0; - return; - } - - quotient = MAKE_INT_32(*r_dst) / src; - remainder = MAKE_INT_32(*r_dst) % src; - - if(quotient == MAKE_INT_16(quotient)) - { - FLAG_Z = quotient; - FLAG_N = NFLAG_16(quotient); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); - return; - } - FLAG_V = VFLAG_SET; - return; - } - m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); -} - - -void m68k_op_divs_16_pi(void) -{ - uint* r_dst = &DX; - sint src = MAKE_INT_16(OPER_AY_PI_16()); - sint quotient; - sint remainder; - - if(src != 0) - { - if((uint32)*r_dst == 0x80000000 && src == -1) - { - FLAG_Z = 0; - FLAG_N = NFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - *r_dst = 0; - return; - } - - quotient = MAKE_INT_32(*r_dst) / src; - remainder = MAKE_INT_32(*r_dst) % src; - - if(quotient == MAKE_INT_16(quotient)) - { - FLAG_Z = quotient; - FLAG_N = NFLAG_16(quotient); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); - return; - } - FLAG_V = VFLAG_SET; - return; - } - m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); -} - - -void m68k_op_divs_16_pd(void) -{ - uint* r_dst = &DX; - sint src = MAKE_INT_16(OPER_AY_PD_16()); - sint quotient; - sint remainder; - - if(src != 0) - { - if((uint32)*r_dst == 0x80000000 && src == -1) - { - FLAG_Z = 0; - FLAG_N = NFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - *r_dst = 0; - return; - } - - quotient = MAKE_INT_32(*r_dst) / src; - remainder = MAKE_INT_32(*r_dst) % src; - - if(quotient == MAKE_INT_16(quotient)) - { - FLAG_Z = quotient; - FLAG_N = NFLAG_16(quotient); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); - return; - } - FLAG_V = VFLAG_SET; - return; - } - m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); -} - - -void m68k_op_divs_16_di(void) -{ - uint* r_dst = &DX; - sint src = MAKE_INT_16(OPER_AY_DI_16()); - sint quotient; - sint remainder; - - if(src != 0) - { - if((uint32)*r_dst == 0x80000000 && src == -1) - { - FLAG_Z = 0; - FLAG_N = NFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - *r_dst = 0; - return; - } - - quotient = MAKE_INT_32(*r_dst) / src; - remainder = MAKE_INT_32(*r_dst) % src; - - if(quotient == MAKE_INT_16(quotient)) - { - FLAG_Z = quotient; - FLAG_N = NFLAG_16(quotient); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); - return; - } - FLAG_V = VFLAG_SET; - return; - } - m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); -} - - -void m68k_op_divs_16_ix(void) -{ - uint* r_dst = &DX; - sint src = MAKE_INT_16(OPER_AY_IX_16()); - sint quotient; - sint remainder; - - if(src != 0) - { - if((uint32)*r_dst == 0x80000000 && src == -1) - { - FLAG_Z = 0; - FLAG_N = NFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - *r_dst = 0; - return; - } - - quotient = MAKE_INT_32(*r_dst) / src; - remainder = MAKE_INT_32(*r_dst) % src; - - if(quotient == MAKE_INT_16(quotient)) - { - FLAG_Z = quotient; - FLAG_N = NFLAG_16(quotient); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); - return; - } - FLAG_V = VFLAG_SET; - return; - } - m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); -} - - -void m68k_op_divs_16_aw(void) -{ - uint* r_dst = &DX; - sint src = MAKE_INT_16(OPER_AW_16()); - sint quotient; - sint remainder; - - if(src != 0) - { - if((uint32)*r_dst == 0x80000000 && src == -1) - { - FLAG_Z = 0; - FLAG_N = NFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - *r_dst = 0; - return; - } - - quotient = MAKE_INT_32(*r_dst) / src; - remainder = MAKE_INT_32(*r_dst) % src; - - if(quotient == MAKE_INT_16(quotient)) - { - FLAG_Z = quotient; - FLAG_N = NFLAG_16(quotient); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); - return; - } - FLAG_V = VFLAG_SET; - return; - } - m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); -} - - -void m68k_op_divs_16_al(void) -{ - uint* r_dst = &DX; - sint src = MAKE_INT_16(OPER_AL_16()); - sint quotient; - sint remainder; - - if(src != 0) - { - if((uint32)*r_dst == 0x80000000 && src == -1) - { - FLAG_Z = 0; - FLAG_N = NFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - *r_dst = 0; - return; - } - - quotient = MAKE_INT_32(*r_dst) / src; - remainder = MAKE_INT_32(*r_dst) % src; - - if(quotient == MAKE_INT_16(quotient)) - { - FLAG_Z = quotient; - FLAG_N = NFLAG_16(quotient); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); - return; - } - FLAG_V = VFLAG_SET; - return; - } - m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); -} - - -void m68k_op_divs_16_pcdi(void) -{ - uint* r_dst = &DX; - sint src = MAKE_INT_16(OPER_PCDI_16()); - sint quotient; - sint remainder; - - if(src != 0) - { - if((uint32)*r_dst == 0x80000000 && src == -1) - { - FLAG_Z = 0; - FLAG_N = NFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - *r_dst = 0; - return; - } - - quotient = MAKE_INT_32(*r_dst) / src; - remainder = MAKE_INT_32(*r_dst) % src; - - if(quotient == MAKE_INT_16(quotient)) - { - FLAG_Z = quotient; - FLAG_N = NFLAG_16(quotient); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); - return; - } - FLAG_V = VFLAG_SET; - return; - } - m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); -} - - -void m68k_op_divs_16_pcix(void) -{ - uint* r_dst = &DX; - sint src = MAKE_INT_16(OPER_PCIX_16()); - sint quotient; - sint remainder; - - if(src != 0) - { - if((uint32)*r_dst == 0x80000000 && src == -1) - { - FLAG_Z = 0; - FLAG_N = NFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - *r_dst = 0; - return; - } - - quotient = MAKE_INT_32(*r_dst) / src; - remainder = MAKE_INT_32(*r_dst) % src; - - if(quotient == MAKE_INT_16(quotient)) - { - FLAG_Z = quotient; - FLAG_N = NFLAG_16(quotient); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); - return; - } - FLAG_V = VFLAG_SET; - return; - } - m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); -} - - -void m68k_op_divs_16_i(void) -{ - uint* r_dst = &DX; - sint src = MAKE_INT_16(OPER_I_16()); - sint quotient; - sint remainder; - - if(src != 0) - { - if((uint32)*r_dst == 0x80000000 && src == -1) - { - FLAG_Z = 0; - FLAG_N = NFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - *r_dst = 0; - return; - } - - quotient = MAKE_INT_32(*r_dst) / src; - remainder = MAKE_INT_32(*r_dst) % src; - - if(quotient == MAKE_INT_16(quotient)) - { - FLAG_Z = quotient; - FLAG_N = NFLAG_16(quotient); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); - return; - } - FLAG_V = VFLAG_SET; - return; - } - m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); -} - - -void m68k_op_divu_16_d(void) -{ - uint* r_dst = &DX; - uint src = MASK_OUT_ABOVE_16(DY); - - if(src != 0) - { - uint quotient = *r_dst / src; - uint remainder = *r_dst % src; - - if(quotient < 0x10000) - { - FLAG_Z = quotient; - FLAG_N = NFLAG_16(quotient); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); - return; - } - FLAG_V = VFLAG_SET; - return; - } - m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); -} - - -void m68k_op_divu_16_ai(void) -{ - uint* r_dst = &DX; - uint src = OPER_AY_AI_16(); - - if(src != 0) - { - uint quotient = *r_dst / src; - uint remainder = *r_dst % src; - - if(quotient < 0x10000) - { - FLAG_Z = quotient; - FLAG_N = NFLAG_16(quotient); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); - return; - } - FLAG_V = VFLAG_SET; - return; - } - m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); -} - - -void m68k_op_divu_16_pi(void) -{ - uint* r_dst = &DX; - uint src = OPER_AY_PI_16(); - - if(src != 0) - { - uint quotient = *r_dst / src; - uint remainder = *r_dst % src; - - if(quotient < 0x10000) - { - FLAG_Z = quotient; - FLAG_N = NFLAG_16(quotient); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); - return; - } - FLAG_V = VFLAG_SET; - return; - } - m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); -} - - -void m68k_op_divu_16_pd(void) -{ - uint* r_dst = &DX; - uint src = OPER_AY_PD_16(); - - if(src != 0) - { - uint quotient = *r_dst / src; - uint remainder = *r_dst % src; - - if(quotient < 0x10000) - { - FLAG_Z = quotient; - FLAG_N = NFLAG_16(quotient); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); - return; - } - FLAG_V = VFLAG_SET; - return; - } - m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); -} - - -void m68k_op_divu_16_di(void) -{ - uint* r_dst = &DX; - uint src = OPER_AY_DI_16(); - - if(src != 0) - { - uint quotient = *r_dst / src; - uint remainder = *r_dst % src; - - if(quotient < 0x10000) - { - FLAG_Z = quotient; - FLAG_N = NFLAG_16(quotient); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); - return; - } - FLAG_V = VFLAG_SET; - return; - } - m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); -} - - -void m68k_op_divu_16_ix(void) -{ - uint* r_dst = &DX; - uint src = OPER_AY_IX_16(); - - if(src != 0) - { - uint quotient = *r_dst / src; - uint remainder = *r_dst % src; - - if(quotient < 0x10000) - { - FLAG_Z = quotient; - FLAG_N = NFLAG_16(quotient); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); - return; - } - FLAG_V = VFLAG_SET; - return; - } - m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); -} - - -void m68k_op_divu_16_aw(void) -{ - uint* r_dst = &DX; - uint src = OPER_AW_16(); - - if(src != 0) - { - uint quotient = *r_dst / src; - uint remainder = *r_dst % src; - - if(quotient < 0x10000) - { - FLAG_Z = quotient; - FLAG_N = NFLAG_16(quotient); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); - return; - } - FLAG_V = VFLAG_SET; - return; - } - m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); -} - - -void m68k_op_divu_16_al(void) -{ - uint* r_dst = &DX; - uint src = OPER_AL_16(); - - if(src != 0) - { - uint quotient = *r_dst / src; - uint remainder = *r_dst % src; - - if(quotient < 0x10000) - { - FLAG_Z = quotient; - FLAG_N = NFLAG_16(quotient); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); - return; - } - FLAG_V = VFLAG_SET; - return; - } - m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); -} - - -void m68k_op_divu_16_pcdi(void) -{ - uint* r_dst = &DX; - uint src = OPER_PCDI_16(); - - if(src != 0) - { - uint quotient = *r_dst / src; - uint remainder = *r_dst % src; - - if(quotient < 0x10000) - { - FLAG_Z = quotient; - FLAG_N = NFLAG_16(quotient); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); - return; - } - FLAG_V = VFLAG_SET; - return; - } - m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); -} - - -void m68k_op_divu_16_pcix(void) -{ - uint* r_dst = &DX; - uint src = OPER_PCIX_16(); - - if(src != 0) - { - uint quotient = *r_dst / src; - uint remainder = *r_dst % src; - - if(quotient < 0x10000) - { - FLAG_Z = quotient; - FLAG_N = NFLAG_16(quotient); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); - return; - } - FLAG_V = VFLAG_SET; - return; - } - m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); -} - - -void m68k_op_divu_16_i(void) -{ - uint* r_dst = &DX; - uint src = OPER_I_16(); - - if(src != 0) - { - uint quotient = *r_dst / src; - uint remainder = *r_dst % src; - - if(quotient < 0x10000) - { - FLAG_Z = quotient; - FLAG_N = NFLAG_16(quotient); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); - return; - } - FLAG_V = VFLAG_SET; - return; - } - m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); -} - - -void m68k_op_divl_32_d(void) -{ -#if M68K_USE_64_BIT - - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint64 divisor = DY; - uint64 dividend = 0; - uint64 quotient = 0; - uint64 remainder = 0; - - if(divisor != 0) - { - if(BIT_A(word2)) /* 64 bit */ - { - dividend = REG_D[word2 & 7]; - dividend <<= 32; - dividend |= REG_D[(word2 >> 12) & 7]; - - if(BIT_B(word2)) /* signed */ - { - quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor)); - remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor)); - if((sint64)quotient != (sint64)((sint32)quotient)) - { - FLAG_V = VFLAG_SET; - return; - } - } - else /* unsigned */ - { - quotient = dividend / divisor; - if(quotient > 0xffffffff) - { - FLAG_V = VFLAG_SET; - return; - } - remainder = dividend % divisor; - } - } - else /* 32 bit */ - { - dividend = REG_D[(word2 >> 12) & 7]; - if(BIT_B(word2)) /* signed */ - { - quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor)); - remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor)); - } - else /* unsigned */ - { - quotient = dividend / divisor; - remainder = dividend % divisor; - } - } - - REG_D[word2 & 7] = remainder; - REG_D[(word2 >> 12) & 7] = quotient; - - FLAG_N = NFLAG_32(quotient); - FLAG_Z = quotient; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); - return; - } - m68ki_exception_illegal(); - -#else - - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint divisor = DY; - uint dividend_hi = REG_D[word2 & 7]; - uint dividend_lo = REG_D[(word2 >> 12) & 7]; - uint quotient = 0; - uint remainder = 0; - uint dividend_neg = 0; - uint divisor_neg = 0; - sint i; - uint overflow; - - if(divisor != 0) - { - /* quad / long : long quotient, long remainder */ - if(BIT_A(word2)) - { - if(BIT_B(word2)) /* signed */ - { - /* special case in signed divide */ - if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff) - { - REG_D[word2 & 7] = 0; - REG_D[(word2 >> 12) & 7] = 0x80000000; - - FLAG_N = NFLAG_SET; - FLAG_Z = ZFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - if(GET_MSB_32(dividend_hi)) - { - dividend_neg = 1; - dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0)); - dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo); - } - if(GET_MSB_32(divisor)) - { - divisor_neg = 1; - divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor); - - } - } - - /* if the upper long is greater than the divisor, we're overflowing. */ - if(dividend_hi >= divisor) - { - FLAG_V = VFLAG_SET; - return; - } - - for(i = 31; i >= 0; i--) - { - quotient <<= 1; - remainder = (remainder << 1) + ((dividend_hi >> i) & 1); - if(remainder >= divisor) - { - remainder -= divisor; - quotient++; - } - } - for(i = 31; i >= 0; i--) - { - quotient <<= 1; - overflow = GET_MSB_32(remainder); - remainder = (remainder << 1) + ((dividend_lo >> i) & 1); - if(remainder >= divisor || overflow) - { - remainder -= divisor; - quotient++; - } - } - - if(BIT_B(word2)) /* signed */ - { - if(quotient > 0x7fffffff) - { - FLAG_V = VFLAG_SET; - return; - } - if(dividend_neg) - { - remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder); - quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); - } - if(divisor_neg) - quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); - } - - REG_D[word2 & 7] = remainder; - REG_D[(word2 >> 12) & 7] = quotient; - - FLAG_N = NFLAG_32(quotient); - FLAG_Z = quotient; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - - /* long / long: long quotient, maybe long remainder */ - if(BIT_B(word2)) /* signed */ - { - /* Special case in divide */ - if(dividend_lo == 0x80000000 && divisor == 0xffffffff) - { - FLAG_N = NFLAG_SET; - FLAG_Z = ZFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - REG_D[(word2 >> 12) & 7] = 0x80000000; - REG_D[word2 & 7] = 0; - return; - } - REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor); - quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor); - } - else - { - REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor); - quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor); - } - - FLAG_N = NFLAG_32(quotient); - FLAG_Z = quotient; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); - return; - } - m68ki_exception_illegal(); - -#endif -} - - -void m68k_op_divl_32_ai(void) -{ -#if M68K_USE_64_BIT - - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint64 divisor = OPER_AY_AI_32(); - uint64 dividend = 0; - uint64 quotient = 0; - uint64 remainder = 0; - - if(divisor != 0) - { - if(BIT_A(word2)) /* 64 bit */ - { - dividend = REG_D[word2 & 7]; - dividend <<= 32; - dividend |= REG_D[(word2 >> 12) & 7]; - - if(BIT_B(word2)) /* signed */ - { - quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor)); - remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor)); - if((sint64)quotient != (sint64)((sint32)quotient)) - { - FLAG_V = VFLAG_SET; - return; - } - } - else /* unsigned */ - { - quotient = dividend / divisor; - if(quotient > 0xffffffff) - { - FLAG_V = VFLAG_SET; - return; - } - remainder = dividend % divisor; - } - } - else /* 32 bit */ - { - dividend = REG_D[(word2 >> 12) & 7]; - if(BIT_B(word2)) /* signed */ - { - quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor)); - remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor)); - } - else /* unsigned */ - { - quotient = dividend / divisor; - remainder = dividend % divisor; - } - } - - REG_D[word2 & 7] = remainder; - REG_D[(word2 >> 12) & 7] = quotient; - - FLAG_N = NFLAG_32(quotient); - FLAG_Z = quotient; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); - return; - } - m68ki_exception_illegal(); - -#else - - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint divisor = OPER_AY_AI_32(); - uint dividend_hi = REG_D[word2 & 7]; - uint dividend_lo = REG_D[(word2 >> 12) & 7]; - uint quotient = 0; - uint remainder = 0; - uint dividend_neg = 0; - uint divisor_neg = 0; - sint i; - uint overflow; - - if(divisor != 0) - { - /* quad / long : long quotient, long remainder */ - if(BIT_A(word2)) - { - if(BIT_B(word2)) /* signed */ - { - /* special case in signed divide */ - if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff) - { - REG_D[word2 & 7] = 0; - REG_D[(word2 >> 12) & 7] = 0x80000000; - - FLAG_N = NFLAG_SET; - FLAG_Z = ZFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - if(GET_MSB_32(dividend_hi)) - { - dividend_neg = 1; - dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0)); - dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo); - } - if(GET_MSB_32(divisor)) - { - divisor_neg = 1; - divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor); - - } - } - - /* if the upper long is greater than the divisor, we're overflowing. */ - if(dividend_hi >= divisor) - { - FLAG_V = VFLAG_SET; - return; - } - - for(i = 31; i >= 0; i--) - { - quotient <<= 1; - remainder = (remainder << 1) + ((dividend_hi >> i) & 1); - if(remainder >= divisor) - { - remainder -= divisor; - quotient++; - } - } - for(i = 31; i >= 0; i--) - { - quotient <<= 1; - overflow = GET_MSB_32(remainder); - remainder = (remainder << 1) + ((dividend_lo >> i) & 1); - if(remainder >= divisor || overflow) - { - remainder -= divisor; - quotient++; - } - } - - if(BIT_B(word2)) /* signed */ - { - if(quotient > 0x7fffffff) - { - FLAG_V = VFLAG_SET; - return; - } - if(dividend_neg) - { - remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder); - quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); - } - if(divisor_neg) - quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); - } - - REG_D[word2 & 7] = remainder; - REG_D[(word2 >> 12) & 7] = quotient; - - FLAG_N = NFLAG_32(quotient); - FLAG_Z = quotient; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - - /* long / long: long quotient, maybe long remainder */ - if(BIT_B(word2)) /* signed */ - { - /* Special case in divide */ - if(dividend_lo == 0x80000000 && divisor == 0xffffffff) - { - FLAG_N = NFLAG_SET; - FLAG_Z = ZFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - REG_D[(word2 >> 12) & 7] = 0x80000000; - REG_D[word2 & 7] = 0; - return; - } - REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor); - quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor); - } - else - { - REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor); - quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor); - } - - FLAG_N = NFLAG_32(quotient); - FLAG_Z = quotient; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); - return; - } - m68ki_exception_illegal(); - -#endif -} - - -void m68k_op_divl_32_pi(void) -{ -#if M68K_USE_64_BIT - - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint64 divisor = OPER_AY_PI_32(); - uint64 dividend = 0; - uint64 quotient = 0; - uint64 remainder = 0; - - if(divisor != 0) - { - if(BIT_A(word2)) /* 64 bit */ - { - dividend = REG_D[word2 & 7]; - dividend <<= 32; - dividend |= REG_D[(word2 >> 12) & 7]; - - if(BIT_B(word2)) /* signed */ - { - quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor)); - remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor)); - if((sint64)quotient != (sint64)((sint32)quotient)) - { - FLAG_V = VFLAG_SET; - return; - } - } - else /* unsigned */ - { - quotient = dividend / divisor; - if(quotient > 0xffffffff) - { - FLAG_V = VFLAG_SET; - return; - } - remainder = dividend % divisor; - } - } - else /* 32 bit */ - { - dividend = REG_D[(word2 >> 12) & 7]; - if(BIT_B(word2)) /* signed */ - { - quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor)); - remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor)); - } - else /* unsigned */ - { - quotient = dividend / divisor; - remainder = dividend % divisor; - } - } - - REG_D[word2 & 7] = remainder; - REG_D[(word2 >> 12) & 7] = quotient; - - FLAG_N = NFLAG_32(quotient); - FLAG_Z = quotient; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); - return; - } - m68ki_exception_illegal(); - -#else - - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint divisor = OPER_AY_PI_32(); - uint dividend_hi = REG_D[word2 & 7]; - uint dividend_lo = REG_D[(word2 >> 12) & 7]; - uint quotient = 0; - uint remainder = 0; - uint dividend_neg = 0; - uint divisor_neg = 0; - sint i; - uint overflow; - - if(divisor != 0) - { - /* quad / long : long quotient, long remainder */ - if(BIT_A(word2)) - { - if(BIT_B(word2)) /* signed */ - { - /* special case in signed divide */ - if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff) - { - REG_D[word2 & 7] = 0; - REG_D[(word2 >> 12) & 7] = 0x80000000; - - FLAG_N = NFLAG_SET; - FLAG_Z = ZFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - if(GET_MSB_32(dividend_hi)) - { - dividend_neg = 1; - dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0)); - dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo); - } - if(GET_MSB_32(divisor)) - { - divisor_neg = 1; - divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor); - - } - } - - /* if the upper long is greater than the divisor, we're overflowing. */ - if(dividend_hi >= divisor) - { - FLAG_V = VFLAG_SET; - return; - } - - for(i = 31; i >= 0; i--) - { - quotient <<= 1; - remainder = (remainder << 1) + ((dividend_hi >> i) & 1); - if(remainder >= divisor) - { - remainder -= divisor; - quotient++; - } - } - for(i = 31; i >= 0; i--) - { - quotient <<= 1; - overflow = GET_MSB_32(remainder); - remainder = (remainder << 1) + ((dividend_lo >> i) & 1); - if(remainder >= divisor || overflow) - { - remainder -= divisor; - quotient++; - } - } - - if(BIT_B(word2)) /* signed */ - { - if(quotient > 0x7fffffff) - { - FLAG_V = VFLAG_SET; - return; - } - if(dividend_neg) - { - remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder); - quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); - } - if(divisor_neg) - quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); - } - - REG_D[word2 & 7] = remainder; - REG_D[(word2 >> 12) & 7] = quotient; - - FLAG_N = NFLAG_32(quotient); - FLAG_Z = quotient; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - - /* long / long: long quotient, maybe long remainder */ - if(BIT_B(word2)) /* signed */ - { - /* Special case in divide */ - if(dividend_lo == 0x80000000 && divisor == 0xffffffff) - { - FLAG_N = NFLAG_SET; - FLAG_Z = ZFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - REG_D[(word2 >> 12) & 7] = 0x80000000; - REG_D[word2 & 7] = 0; - return; - } - REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor); - quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor); - } - else - { - REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor); - quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor); - } - - FLAG_N = NFLAG_32(quotient); - FLAG_Z = quotient; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); - return; - } - m68ki_exception_illegal(); - -#endif -} - - -void m68k_op_divl_32_pd(void) -{ -#if M68K_USE_64_BIT - - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint64 divisor = OPER_AY_PD_32(); - uint64 dividend = 0; - uint64 quotient = 0; - uint64 remainder = 0; - - if(divisor != 0) - { - if(BIT_A(word2)) /* 64 bit */ - { - dividend = REG_D[word2 & 7]; - dividend <<= 32; - dividend |= REG_D[(word2 >> 12) & 7]; - - if(BIT_B(word2)) /* signed */ - { - quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor)); - remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor)); - if((sint64)quotient != (sint64)((sint32)quotient)) - { - FLAG_V = VFLAG_SET; - return; - } - } - else /* unsigned */ - { - quotient = dividend / divisor; - if(quotient > 0xffffffff) - { - FLAG_V = VFLAG_SET; - return; - } - remainder = dividend % divisor; - } - } - else /* 32 bit */ - { - dividend = REG_D[(word2 >> 12) & 7]; - if(BIT_B(word2)) /* signed */ - { - quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor)); - remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor)); - } - else /* unsigned */ - { - quotient = dividend / divisor; - remainder = dividend % divisor; - } - } - - REG_D[word2 & 7] = remainder; - REG_D[(word2 >> 12) & 7] = quotient; - - FLAG_N = NFLAG_32(quotient); - FLAG_Z = quotient; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); - return; - } - m68ki_exception_illegal(); - -#else - - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint divisor = OPER_AY_PD_32(); - uint dividend_hi = REG_D[word2 & 7]; - uint dividend_lo = REG_D[(word2 >> 12) & 7]; - uint quotient = 0; - uint remainder = 0; - uint dividend_neg = 0; - uint divisor_neg = 0; - sint i; - uint overflow; - - if(divisor != 0) - { - /* quad / long : long quotient, long remainder */ - if(BIT_A(word2)) - { - if(BIT_B(word2)) /* signed */ - { - /* special case in signed divide */ - if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff) - { - REG_D[word2 & 7] = 0; - REG_D[(word2 >> 12) & 7] = 0x80000000; - - FLAG_N = NFLAG_SET; - FLAG_Z = ZFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - if(GET_MSB_32(dividend_hi)) - { - dividend_neg = 1; - dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0)); - dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo); - } - if(GET_MSB_32(divisor)) - { - divisor_neg = 1; - divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor); - - } - } - - /* if the upper long is greater than the divisor, we're overflowing. */ - if(dividend_hi >= divisor) - { - FLAG_V = VFLAG_SET; - return; - } - - for(i = 31; i >= 0; i--) - { - quotient <<= 1; - remainder = (remainder << 1) + ((dividend_hi >> i) & 1); - if(remainder >= divisor) - { - remainder -= divisor; - quotient++; - } - } - for(i = 31; i >= 0; i--) - { - quotient <<= 1; - overflow = GET_MSB_32(remainder); - remainder = (remainder << 1) + ((dividend_lo >> i) & 1); - if(remainder >= divisor || overflow) - { - remainder -= divisor; - quotient++; - } - } - - if(BIT_B(word2)) /* signed */ - { - if(quotient > 0x7fffffff) - { - FLAG_V = VFLAG_SET; - return; - } - if(dividend_neg) - { - remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder); - quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); - } - if(divisor_neg) - quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); - } - - REG_D[word2 & 7] = remainder; - REG_D[(word2 >> 12) & 7] = quotient; - - FLAG_N = NFLAG_32(quotient); - FLAG_Z = quotient; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - - /* long / long: long quotient, maybe long remainder */ - if(BIT_B(word2)) /* signed */ - { - /* Special case in divide */ - if(dividend_lo == 0x80000000 && divisor == 0xffffffff) - { - FLAG_N = NFLAG_SET; - FLAG_Z = ZFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - REG_D[(word2 >> 12) & 7] = 0x80000000; - REG_D[word2 & 7] = 0; - return; - } - REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor); - quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor); - } - else - { - REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor); - quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor); - } - - FLAG_N = NFLAG_32(quotient); - FLAG_Z = quotient; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); - return; - } - m68ki_exception_illegal(); - -#endif -} - - -void m68k_op_divl_32_di(void) -{ -#if M68K_USE_64_BIT - - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint64 divisor = OPER_AY_DI_32(); - uint64 dividend = 0; - uint64 quotient = 0; - uint64 remainder = 0; - - if(divisor != 0) - { - if(BIT_A(word2)) /* 64 bit */ - { - dividend = REG_D[word2 & 7]; - dividend <<= 32; - dividend |= REG_D[(word2 >> 12) & 7]; - - if(BIT_B(word2)) /* signed */ - { - quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor)); - remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor)); - if((sint64)quotient != (sint64)((sint32)quotient)) - { - FLAG_V = VFLAG_SET; - return; - } - } - else /* unsigned */ - { - quotient = dividend / divisor; - if(quotient > 0xffffffff) - { - FLAG_V = VFLAG_SET; - return; - } - remainder = dividend % divisor; - } - } - else /* 32 bit */ - { - dividend = REG_D[(word2 >> 12) & 7]; - if(BIT_B(word2)) /* signed */ - { - quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor)); - remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor)); - } - else /* unsigned */ - { - quotient = dividend / divisor; - remainder = dividend % divisor; - } - } - - REG_D[word2 & 7] = remainder; - REG_D[(word2 >> 12) & 7] = quotient; - - FLAG_N = NFLAG_32(quotient); - FLAG_Z = quotient; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); - return; - } - m68ki_exception_illegal(); - -#else - - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint divisor = OPER_AY_DI_32(); - uint dividend_hi = REG_D[word2 & 7]; - uint dividend_lo = REG_D[(word2 >> 12) & 7]; - uint quotient = 0; - uint remainder = 0; - uint dividend_neg = 0; - uint divisor_neg = 0; - sint i; - uint overflow; - - if(divisor != 0) - { - /* quad / long : long quotient, long remainder */ - if(BIT_A(word2)) - { - if(BIT_B(word2)) /* signed */ - { - /* special case in signed divide */ - if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff) - { - REG_D[word2 & 7] = 0; - REG_D[(word2 >> 12) & 7] = 0x80000000; - - FLAG_N = NFLAG_SET; - FLAG_Z = ZFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - if(GET_MSB_32(dividend_hi)) - { - dividend_neg = 1; - dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0)); - dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo); - } - if(GET_MSB_32(divisor)) - { - divisor_neg = 1; - divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor); - - } - } - - /* if the upper long is greater than the divisor, we're overflowing. */ - if(dividend_hi >= divisor) - { - FLAG_V = VFLAG_SET; - return; - } - - for(i = 31; i >= 0; i--) - { - quotient <<= 1; - remainder = (remainder << 1) + ((dividend_hi >> i) & 1); - if(remainder >= divisor) - { - remainder -= divisor; - quotient++; - } - } - for(i = 31; i >= 0; i--) - { - quotient <<= 1; - overflow = GET_MSB_32(remainder); - remainder = (remainder << 1) + ((dividend_lo >> i) & 1); - if(remainder >= divisor || overflow) - { - remainder -= divisor; - quotient++; - } - } - - if(BIT_B(word2)) /* signed */ - { - if(quotient > 0x7fffffff) - { - FLAG_V = VFLAG_SET; - return; - } - if(dividend_neg) - { - remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder); - quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); - } - if(divisor_neg) - quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); - } - - REG_D[word2 & 7] = remainder; - REG_D[(word2 >> 12) & 7] = quotient; - - FLAG_N = NFLAG_32(quotient); - FLAG_Z = quotient; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - - /* long / long: long quotient, maybe long remainder */ - if(BIT_B(word2)) /* signed */ - { - /* Special case in divide */ - if(dividend_lo == 0x80000000 && divisor == 0xffffffff) - { - FLAG_N = NFLAG_SET; - FLAG_Z = ZFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - REG_D[(word2 >> 12) & 7] = 0x80000000; - REG_D[word2 & 7] = 0; - return; - } - REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor); - quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor); - } - else - { - REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor); - quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor); - } - - FLAG_N = NFLAG_32(quotient); - FLAG_Z = quotient; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); - return; - } - m68ki_exception_illegal(); - -#endif -} - - -void m68k_op_divl_32_ix(void) -{ -#if M68K_USE_64_BIT - - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint64 divisor = OPER_AY_IX_32(); - uint64 dividend = 0; - uint64 quotient = 0; - uint64 remainder = 0; - - if(divisor != 0) - { - if(BIT_A(word2)) /* 64 bit */ - { - dividend = REG_D[word2 & 7]; - dividend <<= 32; - dividend |= REG_D[(word2 >> 12) & 7]; - - if(BIT_B(word2)) /* signed */ - { - quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor)); - remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor)); - if((sint64)quotient != (sint64)((sint32)quotient)) - { - FLAG_V = VFLAG_SET; - return; - } - } - else /* unsigned */ - { - quotient = dividend / divisor; - if(quotient > 0xffffffff) - { - FLAG_V = VFLAG_SET; - return; - } - remainder = dividend % divisor; - } - } - else /* 32 bit */ - { - dividend = REG_D[(word2 >> 12) & 7]; - if(BIT_B(word2)) /* signed */ - { - quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor)); - remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor)); - } - else /* unsigned */ - { - quotient = dividend / divisor; - remainder = dividend % divisor; - } - } - - REG_D[word2 & 7] = remainder; - REG_D[(word2 >> 12) & 7] = quotient; - - FLAG_N = NFLAG_32(quotient); - FLAG_Z = quotient; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); - return; - } - m68ki_exception_illegal(); - -#else - - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint divisor = OPER_AY_IX_32(); - uint dividend_hi = REG_D[word2 & 7]; - uint dividend_lo = REG_D[(word2 >> 12) & 7]; - uint quotient = 0; - uint remainder = 0; - uint dividend_neg = 0; - uint divisor_neg = 0; - sint i; - uint overflow; - - if(divisor != 0) - { - /* quad / long : long quotient, long remainder */ - if(BIT_A(word2)) - { - if(BIT_B(word2)) /* signed */ - { - /* special case in signed divide */ - if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff) - { - REG_D[word2 & 7] = 0; - REG_D[(word2 >> 12) & 7] = 0x80000000; - - FLAG_N = NFLAG_SET; - FLAG_Z = ZFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - if(GET_MSB_32(dividend_hi)) - { - dividend_neg = 1; - dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0)); - dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo); - } - if(GET_MSB_32(divisor)) - { - divisor_neg = 1; - divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor); - - } - } - - /* if the upper long is greater than the divisor, we're overflowing. */ - if(dividend_hi >= divisor) - { - FLAG_V = VFLAG_SET; - return; - } - - for(i = 31; i >= 0; i--) - { - quotient <<= 1; - remainder = (remainder << 1) + ((dividend_hi >> i) & 1); - if(remainder >= divisor) - { - remainder -= divisor; - quotient++; - } - } - for(i = 31; i >= 0; i--) - { - quotient <<= 1; - overflow = GET_MSB_32(remainder); - remainder = (remainder << 1) + ((dividend_lo >> i) & 1); - if(remainder >= divisor || overflow) - { - remainder -= divisor; - quotient++; - } - } - - if(BIT_B(word2)) /* signed */ - { - if(quotient > 0x7fffffff) - { - FLAG_V = VFLAG_SET; - return; - } - if(dividend_neg) - { - remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder); - quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); - } - if(divisor_neg) - quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); - } - - REG_D[word2 & 7] = remainder; - REG_D[(word2 >> 12) & 7] = quotient; - - FLAG_N = NFLAG_32(quotient); - FLAG_Z = quotient; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - - /* long / long: long quotient, maybe long remainder */ - if(BIT_B(word2)) /* signed */ - { - /* Special case in divide */ - if(dividend_lo == 0x80000000 && divisor == 0xffffffff) - { - FLAG_N = NFLAG_SET; - FLAG_Z = ZFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - REG_D[(word2 >> 12) & 7] = 0x80000000; - REG_D[word2 & 7] = 0; - return; - } - REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor); - quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor); - } - else - { - REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor); - quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor); - } - - FLAG_N = NFLAG_32(quotient); - FLAG_Z = quotient; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); - return; - } - m68ki_exception_illegal(); - -#endif -} - - -void m68k_op_divl_32_aw(void) -{ -#if M68K_USE_64_BIT - - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint64 divisor = OPER_AW_32(); - uint64 dividend = 0; - uint64 quotient = 0; - uint64 remainder = 0; - - if(divisor != 0) - { - if(BIT_A(word2)) /* 64 bit */ - { - dividend = REG_D[word2 & 7]; - dividend <<= 32; - dividend |= REG_D[(word2 >> 12) & 7]; - - if(BIT_B(word2)) /* signed */ - { - quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor)); - remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor)); - if((sint64)quotient != (sint64)((sint32)quotient)) - { - FLAG_V = VFLAG_SET; - return; - } - } - else /* unsigned */ - { - quotient = dividend / divisor; - if(quotient > 0xffffffff) - { - FLAG_V = VFLAG_SET; - return; - } - remainder = dividend % divisor; - } - } - else /* 32 bit */ - { - dividend = REG_D[(word2 >> 12) & 7]; - if(BIT_B(word2)) /* signed */ - { - quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor)); - remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor)); - } - else /* unsigned */ - { - quotient = dividend / divisor; - remainder = dividend % divisor; - } - } - - REG_D[word2 & 7] = remainder; - REG_D[(word2 >> 12) & 7] = quotient; - - FLAG_N = NFLAG_32(quotient); - FLAG_Z = quotient; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); - return; - } - m68ki_exception_illegal(); - -#else - - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint divisor = OPER_AW_32(); - uint dividend_hi = REG_D[word2 & 7]; - uint dividend_lo = REG_D[(word2 >> 12) & 7]; - uint quotient = 0; - uint remainder = 0; - uint dividend_neg = 0; - uint divisor_neg = 0; - sint i; - uint overflow; - - if(divisor != 0) - { - /* quad / long : long quotient, long remainder */ - if(BIT_A(word2)) - { - if(BIT_B(word2)) /* signed */ - { - /* special case in signed divide */ - if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff) - { - REG_D[word2 & 7] = 0; - REG_D[(word2 >> 12) & 7] = 0x80000000; - - FLAG_N = NFLAG_SET; - FLAG_Z = ZFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - if(GET_MSB_32(dividend_hi)) - { - dividend_neg = 1; - dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0)); - dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo); - } - if(GET_MSB_32(divisor)) - { - divisor_neg = 1; - divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor); - - } - } - - /* if the upper long is greater than the divisor, we're overflowing. */ - if(dividend_hi >= divisor) - { - FLAG_V = VFLAG_SET; - return; - } - - for(i = 31; i >= 0; i--) - { - quotient <<= 1; - remainder = (remainder << 1) + ((dividend_hi >> i) & 1); - if(remainder >= divisor) - { - remainder -= divisor; - quotient++; - } - } - for(i = 31; i >= 0; i--) - { - quotient <<= 1; - overflow = GET_MSB_32(remainder); - remainder = (remainder << 1) + ((dividend_lo >> i) & 1); - if(remainder >= divisor || overflow) - { - remainder -= divisor; - quotient++; - } - } - - if(BIT_B(word2)) /* signed */ - { - if(quotient > 0x7fffffff) - { - FLAG_V = VFLAG_SET; - return; - } - if(dividend_neg) - { - remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder); - quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); - } - if(divisor_neg) - quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); - } - - REG_D[word2 & 7] = remainder; - REG_D[(word2 >> 12) & 7] = quotient; - - FLAG_N = NFLAG_32(quotient); - FLAG_Z = quotient; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - - /* long / long: long quotient, maybe long remainder */ - if(BIT_B(word2)) /* signed */ - { - /* Special case in divide */ - if(dividend_lo == 0x80000000 && divisor == 0xffffffff) - { - FLAG_N = NFLAG_SET; - FLAG_Z = ZFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - REG_D[(word2 >> 12) & 7] = 0x80000000; - REG_D[word2 & 7] = 0; - return; - } - REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor); - quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor); - } - else - { - REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor); - quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor); - } - - FLAG_N = NFLAG_32(quotient); - FLAG_Z = quotient; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); - return; - } - m68ki_exception_illegal(); - -#endif -} - - -void m68k_op_divl_32_al(void) -{ -#if M68K_USE_64_BIT - - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint64 divisor = OPER_AL_32(); - uint64 dividend = 0; - uint64 quotient = 0; - uint64 remainder = 0; - - if(divisor != 0) - { - if(BIT_A(word2)) /* 64 bit */ - { - dividend = REG_D[word2 & 7]; - dividend <<= 32; - dividend |= REG_D[(word2 >> 12) & 7]; - - if(BIT_B(word2)) /* signed */ - { - quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor)); - remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor)); - if((sint64)quotient != (sint64)((sint32)quotient)) - { - FLAG_V = VFLAG_SET; - return; - } - } - else /* unsigned */ - { - quotient = dividend / divisor; - if(quotient > 0xffffffff) - { - FLAG_V = VFLAG_SET; - return; - } - remainder = dividend % divisor; - } - } - else /* 32 bit */ - { - dividend = REG_D[(word2 >> 12) & 7]; - if(BIT_B(word2)) /* signed */ - { - quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor)); - remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor)); - } - else /* unsigned */ - { - quotient = dividend / divisor; - remainder = dividend % divisor; - } - } - - REG_D[word2 & 7] = remainder; - REG_D[(word2 >> 12) & 7] = quotient; - - FLAG_N = NFLAG_32(quotient); - FLAG_Z = quotient; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); - return; - } - m68ki_exception_illegal(); - -#else - - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint divisor = OPER_AL_32(); - uint dividend_hi = REG_D[word2 & 7]; - uint dividend_lo = REG_D[(word2 >> 12) & 7]; - uint quotient = 0; - uint remainder = 0; - uint dividend_neg = 0; - uint divisor_neg = 0; - sint i; - uint overflow; - - if(divisor != 0) - { - /* quad / long : long quotient, long remainder */ - if(BIT_A(word2)) - { - if(BIT_B(word2)) /* signed */ - { - /* special case in signed divide */ - if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff) - { - REG_D[word2 & 7] = 0; - REG_D[(word2 >> 12) & 7] = 0x80000000; - - FLAG_N = NFLAG_SET; - FLAG_Z = ZFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - if(GET_MSB_32(dividend_hi)) - { - dividend_neg = 1; - dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0)); - dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo); - } - if(GET_MSB_32(divisor)) - { - divisor_neg = 1; - divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor); - - } - } - - /* if the upper long is greater than the divisor, we're overflowing. */ - if(dividend_hi >= divisor) - { - FLAG_V = VFLAG_SET; - return; - } - - for(i = 31; i >= 0; i--) - { - quotient <<= 1; - remainder = (remainder << 1) + ((dividend_hi >> i) & 1); - if(remainder >= divisor) - { - remainder -= divisor; - quotient++; - } - } - for(i = 31; i >= 0; i--) - { - quotient <<= 1; - overflow = GET_MSB_32(remainder); - remainder = (remainder << 1) + ((dividend_lo >> i) & 1); - if(remainder >= divisor || overflow) - { - remainder -= divisor; - quotient++; - } - } - - if(BIT_B(word2)) /* signed */ - { - if(quotient > 0x7fffffff) - { - FLAG_V = VFLAG_SET; - return; - } - if(dividend_neg) - { - remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder); - quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); - } - if(divisor_neg) - quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); - } - - REG_D[word2 & 7] = remainder; - REG_D[(word2 >> 12) & 7] = quotient; - - FLAG_N = NFLAG_32(quotient); - FLAG_Z = quotient; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - - /* long / long: long quotient, maybe long remainder */ - if(BIT_B(word2)) /* signed */ - { - /* Special case in divide */ - if(dividend_lo == 0x80000000 && divisor == 0xffffffff) - { - FLAG_N = NFLAG_SET; - FLAG_Z = ZFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - REG_D[(word2 >> 12) & 7] = 0x80000000; - REG_D[word2 & 7] = 0; - return; - } - REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor); - quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor); - } - else - { - REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor); - quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor); - } - - FLAG_N = NFLAG_32(quotient); - FLAG_Z = quotient; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); - return; - } - m68ki_exception_illegal(); - -#endif -} - - -void m68k_op_divl_32_pcdi(void) -{ -#if M68K_USE_64_BIT - - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint64 divisor = OPER_PCDI_32(); - uint64 dividend = 0; - uint64 quotient = 0; - uint64 remainder = 0; - - if(divisor != 0) - { - if(BIT_A(word2)) /* 64 bit */ - { - dividend = REG_D[word2 & 7]; - dividend <<= 32; - dividend |= REG_D[(word2 >> 12) & 7]; - - if(BIT_B(word2)) /* signed */ - { - quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor)); - remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor)); - if((sint64)quotient != (sint64)((sint32)quotient)) - { - FLAG_V = VFLAG_SET; - return; - } - } - else /* unsigned */ - { - quotient = dividend / divisor; - if(quotient > 0xffffffff) - { - FLAG_V = VFLAG_SET; - return; - } - remainder = dividend % divisor; - } - } - else /* 32 bit */ - { - dividend = REG_D[(word2 >> 12) & 7]; - if(BIT_B(word2)) /* signed */ - { - quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor)); - remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor)); - } - else /* unsigned */ - { - quotient = dividend / divisor; - remainder = dividend % divisor; - } - } - - REG_D[word2 & 7] = remainder; - REG_D[(word2 >> 12) & 7] = quotient; - - FLAG_N = NFLAG_32(quotient); - FLAG_Z = quotient; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); - return; - } - m68ki_exception_illegal(); - -#else - - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint divisor = OPER_PCDI_32(); - uint dividend_hi = REG_D[word2 & 7]; - uint dividend_lo = REG_D[(word2 >> 12) & 7]; - uint quotient = 0; - uint remainder = 0; - uint dividend_neg = 0; - uint divisor_neg = 0; - sint i; - uint overflow; - - if(divisor != 0) - { - /* quad / long : long quotient, long remainder */ - if(BIT_A(word2)) - { - if(BIT_B(word2)) /* signed */ - { - /* special case in signed divide */ - if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff) - { - REG_D[word2 & 7] = 0; - REG_D[(word2 >> 12) & 7] = 0x80000000; - - FLAG_N = NFLAG_SET; - FLAG_Z = ZFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - if(GET_MSB_32(dividend_hi)) - { - dividend_neg = 1; - dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0)); - dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo); - } - if(GET_MSB_32(divisor)) - { - divisor_neg = 1; - divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor); - - } - } - - /* if the upper long is greater than the divisor, we're overflowing. */ - if(dividend_hi >= divisor) - { - FLAG_V = VFLAG_SET; - return; - } - - for(i = 31; i >= 0; i--) - { - quotient <<= 1; - remainder = (remainder << 1) + ((dividend_hi >> i) & 1); - if(remainder >= divisor) - { - remainder -= divisor; - quotient++; - } - } - for(i = 31; i >= 0; i--) - { - quotient <<= 1; - overflow = GET_MSB_32(remainder); - remainder = (remainder << 1) + ((dividend_lo >> i) & 1); - if(remainder >= divisor || overflow) - { - remainder -= divisor; - quotient++; - } - } - - if(BIT_B(word2)) /* signed */ - { - if(quotient > 0x7fffffff) - { - FLAG_V = VFLAG_SET; - return; - } - if(dividend_neg) - { - remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder); - quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); - } - if(divisor_neg) - quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); - } - - REG_D[word2 & 7] = remainder; - REG_D[(word2 >> 12) & 7] = quotient; - - FLAG_N = NFLAG_32(quotient); - FLAG_Z = quotient; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - - /* long / long: long quotient, maybe long remainder */ - if(BIT_B(word2)) /* signed */ - { - /* Special case in divide */ - if(dividend_lo == 0x80000000 && divisor == 0xffffffff) - { - FLAG_N = NFLAG_SET; - FLAG_Z = ZFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - REG_D[(word2 >> 12) & 7] = 0x80000000; - REG_D[word2 & 7] = 0; - return; - } - REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor); - quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor); - } - else - { - REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor); - quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor); - } - - FLAG_N = NFLAG_32(quotient); - FLAG_Z = quotient; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); - return; - } - m68ki_exception_illegal(); - -#endif -} - - -void m68k_op_divl_32_pcix(void) -{ -#if M68K_USE_64_BIT - - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint64 divisor = OPER_PCIX_32(); - uint64 dividend = 0; - uint64 quotient = 0; - uint64 remainder = 0; - - if(divisor != 0) - { - if(BIT_A(word2)) /* 64 bit */ - { - dividend = REG_D[word2 & 7]; - dividend <<= 32; - dividend |= REG_D[(word2 >> 12) & 7]; - - if(BIT_B(word2)) /* signed */ - { - quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor)); - remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor)); - if((sint64)quotient != (sint64)((sint32)quotient)) - { - FLAG_V = VFLAG_SET; - return; - } - } - else /* unsigned */ - { - quotient = dividend / divisor; - if(quotient > 0xffffffff) - { - FLAG_V = VFLAG_SET; - return; - } - remainder = dividend % divisor; - } - } - else /* 32 bit */ - { - dividend = REG_D[(word2 >> 12) & 7]; - if(BIT_B(word2)) /* signed */ - { - quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor)); - remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor)); - } - else /* unsigned */ - { - quotient = dividend / divisor; - remainder = dividend % divisor; - } - } - - REG_D[word2 & 7] = remainder; - REG_D[(word2 >> 12) & 7] = quotient; - - FLAG_N = NFLAG_32(quotient); - FLAG_Z = quotient; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); - return; - } - m68ki_exception_illegal(); - -#else - - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint divisor = OPER_PCIX_32(); - uint dividend_hi = REG_D[word2 & 7]; - uint dividend_lo = REG_D[(word2 >> 12) & 7]; - uint quotient = 0; - uint remainder = 0; - uint dividend_neg = 0; - uint divisor_neg = 0; - sint i; - uint overflow; - - if(divisor != 0) - { - /* quad / long : long quotient, long remainder */ - if(BIT_A(word2)) - { - if(BIT_B(word2)) /* signed */ - { - /* special case in signed divide */ - if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff) - { - REG_D[word2 & 7] = 0; - REG_D[(word2 >> 12) & 7] = 0x80000000; - - FLAG_N = NFLAG_SET; - FLAG_Z = ZFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - if(GET_MSB_32(dividend_hi)) - { - dividend_neg = 1; - dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0)); - dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo); - } - if(GET_MSB_32(divisor)) - { - divisor_neg = 1; - divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor); - - } - } - - /* if the upper long is greater than the divisor, we're overflowing. */ - if(dividend_hi >= divisor) - { - FLAG_V = VFLAG_SET; - return; - } - - for(i = 31; i >= 0; i--) - { - quotient <<= 1; - remainder = (remainder << 1) + ((dividend_hi >> i) & 1); - if(remainder >= divisor) - { - remainder -= divisor; - quotient++; - } - } - for(i = 31; i >= 0; i--) - { - quotient <<= 1; - overflow = GET_MSB_32(remainder); - remainder = (remainder << 1) + ((dividend_lo >> i) & 1); - if(remainder >= divisor || overflow) - { - remainder -= divisor; - quotient++; - } - } - - if(BIT_B(word2)) /* signed */ - { - if(quotient > 0x7fffffff) - { - FLAG_V = VFLAG_SET; - return; - } - if(dividend_neg) - { - remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder); - quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); - } - if(divisor_neg) - quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); - } - - REG_D[word2 & 7] = remainder; - REG_D[(word2 >> 12) & 7] = quotient; - - FLAG_N = NFLAG_32(quotient); - FLAG_Z = quotient; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - - /* long / long: long quotient, maybe long remainder */ - if(BIT_B(word2)) /* signed */ - { - /* Special case in divide */ - if(dividend_lo == 0x80000000 && divisor == 0xffffffff) - { - FLAG_N = NFLAG_SET; - FLAG_Z = ZFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - REG_D[(word2 >> 12) & 7] = 0x80000000; - REG_D[word2 & 7] = 0; - return; - } - REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor); - quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor); - } - else - { - REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor); - quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor); - } - - FLAG_N = NFLAG_32(quotient); - FLAG_Z = quotient; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); - return; - } - m68ki_exception_illegal(); - -#endif -} - - -void m68k_op_divl_32_i(void) -{ -#if M68K_USE_64_BIT - - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint64 divisor = OPER_I_32(); - uint64 dividend = 0; - uint64 quotient = 0; - uint64 remainder = 0; - - if(divisor != 0) - { - if(BIT_A(word2)) /* 64 bit */ - { - dividend = REG_D[word2 & 7]; - dividend <<= 32; - dividend |= REG_D[(word2 >> 12) & 7]; - - if(BIT_B(word2)) /* signed */ - { - quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor)); - remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor)); - if((sint64)quotient != (sint64)((sint32)quotient)) - { - FLAG_V = VFLAG_SET; - return; - } - } - else /* unsigned */ - { - quotient = dividend / divisor; - if(quotient > 0xffffffff) - { - FLAG_V = VFLAG_SET; - return; - } - remainder = dividend % divisor; - } - } - else /* 32 bit */ - { - dividend = REG_D[(word2 >> 12) & 7]; - if(BIT_B(word2)) /* signed */ - { - quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor)); - remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor)); - } - else /* unsigned */ - { - quotient = dividend / divisor; - remainder = dividend % divisor; - } - } - - REG_D[word2 & 7] = remainder; - REG_D[(word2 >> 12) & 7] = quotient; - - FLAG_N = NFLAG_32(quotient); - FLAG_Z = quotient; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); - return; - } - m68ki_exception_illegal(); - -#else - - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint divisor = OPER_I_32(); - uint dividend_hi = REG_D[word2 & 7]; - uint dividend_lo = REG_D[(word2 >> 12) & 7]; - uint quotient = 0; - uint remainder = 0; - uint dividend_neg = 0; - uint divisor_neg = 0; - sint i; - uint overflow; - - if(divisor != 0) - { - /* quad / long : long quotient, long remainder */ - if(BIT_A(word2)) - { - if(BIT_B(word2)) /* signed */ - { - /* special case in signed divide */ - if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff) - { - REG_D[word2 & 7] = 0; - REG_D[(word2 >> 12) & 7] = 0x80000000; - - FLAG_N = NFLAG_SET; - FLAG_Z = ZFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - if(GET_MSB_32(dividend_hi)) - { - dividend_neg = 1; - dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0)); - dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo); - } - if(GET_MSB_32(divisor)) - { - divisor_neg = 1; - divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor); - - } - } - - /* if the upper long is greater than the divisor, we're overflowing. */ - if(dividend_hi >= divisor) - { - FLAG_V = VFLAG_SET; - return; - } - - for(i = 31; i >= 0; i--) - { - quotient <<= 1; - remainder = (remainder << 1) + ((dividend_hi >> i) & 1); - if(remainder >= divisor) - { - remainder -= divisor; - quotient++; - } - } - for(i = 31; i >= 0; i--) - { - quotient <<= 1; - overflow = GET_MSB_32(remainder); - remainder = (remainder << 1) + ((dividend_lo >> i) & 1); - if(remainder >= divisor || overflow) - { - remainder -= divisor; - quotient++; - } - } - - if(BIT_B(word2)) /* signed */ - { - if(quotient > 0x7fffffff) - { - FLAG_V = VFLAG_SET; - return; - } - if(dividend_neg) - { - remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder); - quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); - } - if(divisor_neg) - quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); - } - - REG_D[word2 & 7] = remainder; - REG_D[(word2 >> 12) & 7] = quotient; - - FLAG_N = NFLAG_32(quotient); - FLAG_Z = quotient; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - - /* long / long: long quotient, maybe long remainder */ - if(BIT_B(word2)) /* signed */ - { - /* Special case in divide */ - if(dividend_lo == 0x80000000 && divisor == 0xffffffff) - { - FLAG_N = NFLAG_SET; - FLAG_Z = ZFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - REG_D[(word2 >> 12) & 7] = 0x80000000; - REG_D[word2 & 7] = 0; - return; - } - REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor); - quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor); - } - else - { - REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor); - quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor); - } - - FLAG_N = NFLAG_32(quotient); - FLAG_Z = quotient; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); - return; - } - m68ki_exception_illegal(); - -#endif -} - - -void m68k_op_eor_8_d(void) -{ - uint res = MASK_OUT_ABOVE_8(DY ^= MASK_OUT_ABOVE_8(DX)); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_eor_8_ai(void) -{ - uint ea = EA_AY_AI_8(); - uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea)); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_eor_8_pi(void) -{ - uint ea = EA_AY_PI_8(); - uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea)); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_eor_8_pi7(void) -{ - uint ea = EA_A7_PI_8(); - uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea)); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_eor_8_pd(void) -{ - uint ea = EA_AY_PD_8(); - uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea)); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_eor_8_pd7(void) -{ - uint ea = EA_A7_PD_8(); - uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea)); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_eor_8_di(void) -{ - uint ea = EA_AY_DI_8(); - uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea)); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_eor_8_ix(void) -{ - uint ea = EA_AY_IX_8(); - uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea)); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_eor_8_aw(void) -{ - uint ea = EA_AW_8(); - uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea)); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_eor_8_al(void) -{ - uint ea = EA_AL_8(); - uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea)); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_eor_16_d(void) -{ - uint res = MASK_OUT_ABOVE_16(DY ^= MASK_OUT_ABOVE_16(DX)); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_eor_16_ai(void) -{ - uint ea = EA_AY_AI_16(); - uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea)); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_eor_16_pi(void) -{ - uint ea = EA_AY_PI_16(); - uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea)); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_eor_16_pd(void) -{ - uint ea = EA_AY_PD_16(); - uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea)); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_eor_16_di(void) -{ - uint ea = EA_AY_DI_16(); - uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea)); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_eor_16_ix(void) -{ - uint ea = EA_AY_IX_16(); - uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea)); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_eor_16_aw(void) -{ - uint ea = EA_AW_16(); - uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea)); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_eor_16_al(void) -{ - uint ea = EA_AL_16(); - uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea)); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_eor_32_d(void) -{ - uint res = DY ^= DX; - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_eor_32_ai(void) -{ - uint ea = EA_AY_AI_32(); - uint res = DX ^ m68ki_read_32(ea); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_eor_32_pi(void) -{ - uint ea = EA_AY_PI_32(); - uint res = DX ^ m68ki_read_32(ea); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_eor_32_pd(void) -{ - uint ea = EA_AY_PD_32(); - uint res = DX ^ m68ki_read_32(ea); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_eor_32_di(void) -{ - uint ea = EA_AY_DI_32(); - uint res = DX ^ m68ki_read_32(ea); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_eor_32_ix(void) -{ - uint ea = EA_AY_IX_32(); - uint res = DX ^ m68ki_read_32(ea); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_eor_32_aw(void) -{ - uint ea = EA_AW_32(); - uint res = DX ^ m68ki_read_32(ea); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_eor_32_al(void) -{ - uint ea = EA_AL_32(); - uint res = DX ^ m68ki_read_32(ea); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_eori_8_d(void) -{ - uint res = MASK_OUT_ABOVE_8(DY ^= OPER_I_8()); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_eori_8_ai(void) -{ - uint src = OPER_I_8(); - uint ea = EA_AY_AI_8(); - uint res = src ^ m68ki_read_8(ea); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_eori_8_pi(void) -{ - uint src = OPER_I_8(); - uint ea = EA_AY_PI_8(); - uint res = src ^ m68ki_read_8(ea); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_eori_8_pi7(void) -{ - uint src = OPER_I_8(); - uint ea = EA_A7_PI_8(); - uint res = src ^ m68ki_read_8(ea); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_eori_8_pd(void) -{ - uint src = OPER_I_8(); - uint ea = EA_AY_PD_8(); - uint res = src ^ m68ki_read_8(ea); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_eori_8_pd7(void) -{ - uint src = OPER_I_8(); - uint ea = EA_A7_PD_8(); - uint res = src ^ m68ki_read_8(ea); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_eori_8_di(void) -{ - uint src = OPER_I_8(); - uint ea = EA_AY_DI_8(); - uint res = src ^ m68ki_read_8(ea); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_eori_8_ix(void) -{ - uint src = OPER_I_8(); - uint ea = EA_AY_IX_8(); - uint res = src ^ m68ki_read_8(ea); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_eori_8_aw(void) -{ - uint src = OPER_I_8(); - uint ea = EA_AW_8(); - uint res = src ^ m68ki_read_8(ea); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_eori_8_al(void) -{ - uint src = OPER_I_8(); - uint ea = EA_AL_8(); - uint res = src ^ m68ki_read_8(ea); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_eori_16_d(void) -{ - uint res = MASK_OUT_ABOVE_16(DY ^= OPER_I_16()); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_eori_16_ai(void) -{ - uint src = OPER_I_16(); - uint ea = EA_AY_AI_16(); - uint res = src ^ m68ki_read_16(ea); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_eori_16_pi(void) -{ - uint src = OPER_I_16(); - uint ea = EA_AY_PI_16(); - uint res = src ^ m68ki_read_16(ea); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_eori_16_pd(void) -{ - uint src = OPER_I_16(); - uint ea = EA_AY_PD_16(); - uint res = src ^ m68ki_read_16(ea); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_eori_16_di(void) -{ - uint src = OPER_I_16(); - uint ea = EA_AY_DI_16(); - uint res = src ^ m68ki_read_16(ea); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_eori_16_ix(void) -{ - uint src = OPER_I_16(); - uint ea = EA_AY_IX_16(); - uint res = src ^ m68ki_read_16(ea); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_eori_16_aw(void) -{ - uint src = OPER_I_16(); - uint ea = EA_AW_16(); - uint res = src ^ m68ki_read_16(ea); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_eori_16_al(void) -{ - uint src = OPER_I_16(); - uint ea = EA_AL_16(); - uint res = src ^ m68ki_read_16(ea); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_eori_32_d(void) -{ - uint res = DY ^= OPER_I_32(); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_eori_32_ai(void) -{ - uint src = OPER_I_32(); - uint ea = EA_AY_AI_32(); - uint res = src ^ m68ki_read_32(ea); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_eori_32_pi(void) -{ - uint src = OPER_I_32(); - uint ea = EA_AY_PI_32(); - uint res = src ^ m68ki_read_32(ea); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_eori_32_pd(void) -{ - uint src = OPER_I_32(); - uint ea = EA_AY_PD_32(); - uint res = src ^ m68ki_read_32(ea); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_eori_32_di(void) -{ - uint src = OPER_I_32(); - uint ea = EA_AY_DI_32(); - uint res = src ^ m68ki_read_32(ea); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_eori_32_ix(void) -{ - uint src = OPER_I_32(); - uint ea = EA_AY_IX_32(); - uint res = src ^ m68ki_read_32(ea); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_eori_32_aw(void) -{ - uint src = OPER_I_32(); - uint ea = EA_AW_32(); - uint res = src ^ m68ki_read_32(ea); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_eori_32_al(void) -{ - uint src = OPER_I_32(); - uint ea = EA_AL_32(); - uint res = src ^ m68ki_read_32(ea); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_eori_16_toc(void) -{ - m68ki_set_ccr(m68ki_get_ccr() ^ OPER_I_16()); -} - - -void m68k_op_eori_16_tos(void) -{ - if(FLAG_S) - { - uint src = OPER_I_16(); - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_set_sr(m68ki_get_sr() ^ src); - return; - } - m68ki_exception_privilege_violation(); -} - - -void m68k_op_exg_32_dd(void) -{ - uint* reg_a = &DX; - uint* reg_b = &DY; - uint tmp = *reg_a; - *reg_a = *reg_b; - *reg_b = tmp; -} - - -void m68k_op_exg_32_aa(void) -{ - uint* reg_a = &AX; - uint* reg_b = &AY; - uint tmp = *reg_a; - *reg_a = *reg_b; - *reg_b = tmp; -} - - -void m68k_op_exg_32_da(void) -{ - uint* reg_a = &DX; - uint* reg_b = &AY; - uint tmp = *reg_a; - *reg_a = *reg_b; - *reg_b = tmp; -} - - -void m68k_op_ext_16(void) -{ - uint* r_dst = &DY; - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xff00 : 0); - - FLAG_N = NFLAG_16(*r_dst); - FLAG_Z = MASK_OUT_ABOVE_16(*r_dst); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_ext_32(void) -{ - uint* r_dst = &DY; - - *r_dst = MASK_OUT_ABOVE_16(*r_dst) | (GET_MSB_16(*r_dst) ? 0xffff0000 : 0); - - FLAG_N = NFLAG_32(*r_dst); - FLAG_Z = *r_dst; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_extb_32(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint* r_dst = &DY; - - *r_dst = MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xffffff00 : 0); - - FLAG_N = NFLAG_32(*r_dst); - FLAG_Z = *r_dst; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_illegal(void) -{ - m68ki_exception_illegal(); -} - - -void m68k_op_jmp_32_ai(void) -{ - m68ki_jump(EA_AY_AI_32()); - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - if(REG_PC == REG_PPC) - USE_ALL_CYCLES(); -} - - -void m68k_op_jmp_32_di(void) -{ - m68ki_jump(EA_AY_DI_32()); - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - if(REG_PC == REG_PPC) - USE_ALL_CYCLES(); -} - - -void m68k_op_jmp_32_ix(void) -{ - m68ki_jump(EA_AY_IX_32()); - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - if(REG_PC == REG_PPC) - USE_ALL_CYCLES(); -} - - -void m68k_op_jmp_32_aw(void) -{ - m68ki_jump(EA_AW_32()); - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - if(REG_PC == REG_PPC) - USE_ALL_CYCLES(); -} - - -void m68k_op_jmp_32_al(void) -{ - m68ki_jump(EA_AL_32()); - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - if(REG_PC == REG_PPC) - USE_ALL_CYCLES(); -} - - -void m68k_op_jmp_32_pcdi(void) -{ - m68ki_jump(EA_PCDI_32()); - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - if(REG_PC == REG_PPC) - USE_ALL_CYCLES(); -} - - -void m68k_op_jmp_32_pcix(void) -{ - m68ki_jump(EA_PCIX_32()); - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - if(REG_PC == REG_PPC) - USE_ALL_CYCLES(); -} - - -void m68k_op_jsr_32_ai(void) -{ - uint ea = EA_AY_AI_32(); - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_push_32(REG_PC); - m68ki_jump(ea); -} - - -void m68k_op_jsr_32_di(void) -{ - uint ea = EA_AY_DI_32(); - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_push_32(REG_PC); - m68ki_jump(ea); -} - - -void m68k_op_jsr_32_ix(void) -{ - uint ea = EA_AY_IX_32(); - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_push_32(REG_PC); - m68ki_jump(ea); -} - - -void m68k_op_jsr_32_aw(void) -{ - uint ea = EA_AW_32(); - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_push_32(REG_PC); - m68ki_jump(ea); -} - - -void m68k_op_jsr_32_al(void) -{ - uint ea = EA_AL_32(); - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_push_32(REG_PC); - m68ki_jump(ea); -} - - -void m68k_op_jsr_32_pcdi(void) -{ - uint ea = EA_PCDI_32(); - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_push_32(REG_PC); - m68ki_jump(ea); -} - - -void m68k_op_jsr_32_pcix(void) -{ - uint ea = EA_PCIX_32(); - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_push_32(REG_PC); - m68ki_jump(ea); -} - - -void m68k_op_lea_32_ai(void) -{ - AX = EA_AY_AI_32(); -} - - -void m68k_op_lea_32_di(void) -{ - AX = EA_AY_DI_32(); -} - - -void m68k_op_lea_32_ix(void) -{ - AX = EA_AY_IX_32(); -} - - -void m68k_op_lea_32_aw(void) -{ - AX = EA_AW_32(); -} - - -void m68k_op_lea_32_al(void) -{ - AX = EA_AL_32(); -} - - -void m68k_op_lea_32_pcdi(void) -{ - AX = EA_PCDI_32(); -} - - -void m68k_op_lea_32_pcix(void) -{ - AX = EA_PCIX_32(); -} - - -void m68k_op_link_16_a7(void) -{ - REG_A[7] -= 4; - m68ki_write_32(REG_A[7], REG_A[7]); - REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16())); -} - - -void m68k_op_link_16(void) -{ - uint* r_dst = &AY; - - m68ki_push_32(*r_dst); - *r_dst = REG_A[7]; - REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16())); -} - - -void m68k_op_link_32_a7(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - REG_A[7] -= 4; - m68ki_write_32(REG_A[7], REG_A[7]); - REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32()); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_link_32(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint* r_dst = &AY; - - m68ki_push_32(*r_dst); - *r_dst = REG_A[7]; - REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32()); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_lsr_8_s(void) -{ - uint* r_dst = &DY; - uint shift = (((REG_IR >> 9) - 1) & 7) + 1; - uint src = MASK_OUT_ABOVE_8(*r_dst); - uint res = src >> shift; - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; - - FLAG_N = NFLAG_CLEAR; - FLAG_Z = res; - FLAG_X = FLAG_C = src << (9-shift); - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_lsr_16_s(void) -{ - uint* r_dst = &DY; - uint shift = (((REG_IR >> 9) - 1) & 7) + 1; - uint src = MASK_OUT_ABOVE_16(*r_dst); - uint res = src >> shift; - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; - - FLAG_N = NFLAG_CLEAR; - FLAG_Z = res; - FLAG_X = FLAG_C = src << (9-shift); - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_lsr_32_s(void) -{ - uint* r_dst = &DY; - uint shift = (((REG_IR >> 9) - 1) & 7) + 1; - uint src = *r_dst; - uint res = src >> shift; - - *r_dst = res; - - FLAG_N = NFLAG_CLEAR; - FLAG_Z = res; - FLAG_X = FLAG_C = src << (9-shift); - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_lsr_8_r(void) -{ - uint* r_dst = &DY; - uint shift = DX & 0x3f; - uint src = MASK_OUT_ABOVE_8(*r_dst); - uint res = src >> shift; - - if(shift != 0) - { - USE_CYCLES(shift<> shift; - - if(shift != 0) - { - USE_CYCLES(shift<> (shift - 1))<<8; - FLAG_N = NFLAG_CLEAR; - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - return; - } - - *r_dst &= 0xffff0000; - FLAG_X = XFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - FLAG_N = NFLAG_CLEAR; - FLAG_Z = ZFLAG_SET; - FLAG_V = VFLAG_CLEAR; - return; - } - - FLAG_C = CFLAG_CLEAR; - FLAG_N = NFLAG_16(src); - FLAG_Z = src; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_lsr_32_r(void) -{ - uint* r_dst = &DY; - uint shift = DX & 0x3f; - uint src = *r_dst; - uint res = src >> shift; - - if(shift != 0) - { - USE_CYCLES(shift<> (shift - 1))<<8; - FLAG_N = NFLAG_CLEAR; - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - return; - } - - *r_dst = 0; - FLAG_X = FLAG_C = (shift == 32 ? GET_MSB_32(src)>>23 : 0); - FLAG_N = NFLAG_CLEAR; - FLAG_Z = ZFLAG_SET; - FLAG_V = VFLAG_CLEAR; - return; - } - - FLAG_C = CFLAG_CLEAR; - FLAG_N = NFLAG_32(src); - FLAG_Z = src; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_lsr_16_ai(void) -{ - uint ea = EA_AY_AI_16(); - uint src = m68ki_read_16(ea); - uint res = src >> 1; - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_CLEAR; - FLAG_Z = res; - FLAG_C = FLAG_X = src << 8; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_lsr_16_pi(void) -{ - uint ea = EA_AY_PI_16(); - uint src = m68ki_read_16(ea); - uint res = src >> 1; - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_CLEAR; - FLAG_Z = res; - FLAG_C = FLAG_X = src << 8; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_lsr_16_pd(void) -{ - uint ea = EA_AY_PD_16(); - uint src = m68ki_read_16(ea); - uint res = src >> 1; - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_CLEAR; - FLAG_Z = res; - FLAG_C = FLAG_X = src << 8; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_lsr_16_di(void) -{ - uint ea = EA_AY_DI_16(); - uint src = m68ki_read_16(ea); - uint res = src >> 1; - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_CLEAR; - FLAG_Z = res; - FLAG_C = FLAG_X = src << 8; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_lsr_16_ix(void) -{ - uint ea = EA_AY_IX_16(); - uint src = m68ki_read_16(ea); - uint res = src >> 1; - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_CLEAR; - FLAG_Z = res; - FLAG_C = FLAG_X = src << 8; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_lsr_16_aw(void) -{ - uint ea = EA_AW_16(); - uint src = m68ki_read_16(ea); - uint res = src >> 1; - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_CLEAR; - FLAG_Z = res; - FLAG_C = FLAG_X = src << 8; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_lsr_16_al(void) -{ - uint ea = EA_AL_16(); - uint src = m68ki_read_16(ea); - uint res = src >> 1; - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_CLEAR; - FLAG_Z = res; - FLAG_C = FLAG_X = src << 8; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_lsl_8_s(void) -{ - uint* r_dst = &DY; - uint shift = (((REG_IR >> 9) - 1) & 7) + 1; - uint src = MASK_OUT_ABOVE_8(*r_dst); - uint res = MASK_OUT_ABOVE_8(src << shift); - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_X = FLAG_C = src << shift; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_lsl_16_s(void) -{ - uint* r_dst = &DY; - uint shift = (((REG_IR >> 9) - 1) & 7) + 1; - uint src = MASK_OUT_ABOVE_16(*r_dst); - uint res = MASK_OUT_ABOVE_16(src << shift); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_X = FLAG_C = src >> (8-shift); - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_lsl_32_s(void) -{ - uint* r_dst = &DY; - uint shift = (((REG_IR >> 9) - 1) & 7) + 1; - uint src = *r_dst; - uint res = MASK_OUT_ABOVE_32(src << shift); - - *r_dst = res; - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_X = FLAG_C = src >> (24-shift); - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_lsl_8_r(void) -{ - uint* r_dst = &DY; - uint shift = DX & 0x3f; - uint src = MASK_OUT_ABOVE_8(*r_dst); - uint res = MASK_OUT_ABOVE_8(src << shift); - - if(shift != 0) - { - USE_CYCLES(shift<> 8; - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - return; - } - - *r_dst &= 0xffff0000; - FLAG_X = XFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - FLAG_N = NFLAG_CLEAR; - FLAG_Z = ZFLAG_SET; - FLAG_V = VFLAG_CLEAR; - return; - } - - FLAG_C = CFLAG_CLEAR; - FLAG_N = NFLAG_16(src); - FLAG_Z = src; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_lsl_32_r(void) -{ - uint* r_dst = &DY; - uint shift = DX & 0x3f; - uint src = *r_dst; - uint res = MASK_OUT_ABOVE_32(src << shift); - - if(shift != 0) - { - USE_CYCLES(shift<> (32 - shift)) << 8; - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - return; - } - - *r_dst = 0; - FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8; - FLAG_N = NFLAG_CLEAR; - FLAG_Z = ZFLAG_SET; - FLAG_V = VFLAG_CLEAR; - return; - } - - FLAG_C = CFLAG_CLEAR; - FLAG_N = NFLAG_32(src); - FLAG_Z = src; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_lsl_16_ai(void) -{ - uint ea = EA_AY_AI_16(); - uint src = m68ki_read_16(ea); - uint res = MASK_OUT_ABOVE_16(src << 1); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_X = FLAG_C = src >> 7; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_lsl_16_pi(void) -{ - uint ea = EA_AY_PI_16(); - uint src = m68ki_read_16(ea); - uint res = MASK_OUT_ABOVE_16(src << 1); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_X = FLAG_C = src >> 7; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_lsl_16_pd(void) -{ - uint ea = EA_AY_PD_16(); - uint src = m68ki_read_16(ea); - uint res = MASK_OUT_ABOVE_16(src << 1); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_X = FLAG_C = src >> 7; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_lsl_16_di(void) -{ - uint ea = EA_AY_DI_16(); - uint src = m68ki_read_16(ea); - uint res = MASK_OUT_ABOVE_16(src << 1); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_X = FLAG_C = src >> 7; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_lsl_16_ix(void) -{ - uint ea = EA_AY_IX_16(); - uint src = m68ki_read_16(ea); - uint res = MASK_OUT_ABOVE_16(src << 1); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_X = FLAG_C = src >> 7; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_lsl_16_aw(void) -{ - uint ea = EA_AW_16(); - uint src = m68ki_read_16(ea); - uint res = MASK_OUT_ABOVE_16(src << 1); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_X = FLAG_C = src >> 7; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_lsl_16_al(void) -{ - uint ea = EA_AL_16(); - uint src = m68ki_read_16(ea); - uint res = MASK_OUT_ABOVE_16(src << 1); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_X = FLAG_C = src >> 7; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_move_8_d_d(void) -{ - uint res = MASK_OUT_ABOVE_8(DY); - uint* r_dst = &DX; - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_d_ai(void) -{ - uint res = OPER_AY_AI_8(); - uint* r_dst = &DX; - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_d_pi(void) -{ - uint res = OPER_AY_PI_8(); - uint* r_dst = &DX; - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_d_pi7(void) -{ - uint res = OPER_A7_PI_8(); - uint* r_dst = &DX; - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_d_pd(void) -{ - uint res = OPER_AY_PD_8(); - uint* r_dst = &DX; - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_d_pd7(void) -{ - uint res = OPER_A7_PD_8(); - uint* r_dst = &DX; - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_d_di(void) -{ - uint res = OPER_AY_DI_8(); - uint* r_dst = &DX; - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_d_ix(void) -{ - uint res = OPER_AY_IX_8(); - uint* r_dst = &DX; - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_d_aw(void) -{ - uint res = OPER_AW_8(); - uint* r_dst = &DX; - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_d_al(void) -{ - uint res = OPER_AL_8(); - uint* r_dst = &DX; - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_d_pcdi(void) -{ - uint res = OPER_PCDI_8(); - uint* r_dst = &DX; - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_d_pcix(void) -{ - uint res = OPER_PCIX_8(); - uint* r_dst = &DX; - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_d_i(void) -{ - uint res = OPER_I_8(); - uint* r_dst = &DX; - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_ai_d(void) -{ - uint res = MASK_OUT_ABOVE_8(DY); - uint ea = EA_AX_AI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_ai_ai(void) -{ - uint res = OPER_AY_AI_8(); - uint ea = EA_AX_AI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_ai_pi(void) -{ - uint res = OPER_AY_PI_8(); - uint ea = EA_AX_AI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_ai_pi7(void) -{ - uint res = OPER_A7_PI_8(); - uint ea = EA_AX_AI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_ai_pd(void) -{ - uint res = OPER_AY_PD_8(); - uint ea = EA_AX_AI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_ai_pd7(void) -{ - uint res = OPER_A7_PD_8(); - uint ea = EA_AX_AI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_ai_di(void) -{ - uint res = OPER_AY_DI_8(); - uint ea = EA_AX_AI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_ai_ix(void) -{ - uint res = OPER_AY_IX_8(); - uint ea = EA_AX_AI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_ai_aw(void) -{ - uint res = OPER_AW_8(); - uint ea = EA_AX_AI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_ai_al(void) -{ - uint res = OPER_AL_8(); - uint ea = EA_AX_AI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_ai_pcdi(void) -{ - uint res = OPER_PCDI_8(); - uint ea = EA_AX_AI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_ai_pcix(void) -{ - uint res = OPER_PCIX_8(); - uint ea = EA_AX_AI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_ai_i(void) -{ - uint res = OPER_I_8(); - uint ea = EA_AX_AI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_pi7_d(void) -{ - uint res = MASK_OUT_ABOVE_8(DY); - uint ea = EA_A7_PI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_pi_d(void) -{ - uint res = MASK_OUT_ABOVE_8(DY); - uint ea = EA_AX_PI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_pi7_ai(void) -{ - uint res = OPER_AY_AI_8(); - uint ea = EA_A7_PI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_pi7_pi(void) -{ - uint res = OPER_AY_PI_8(); - uint ea = EA_A7_PI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_pi7_pi7(void) -{ - uint res = OPER_A7_PI_8(); - uint ea = EA_A7_PI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_pi7_pd(void) -{ - uint res = OPER_AY_PD_8(); - uint ea = EA_A7_PI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_pi7_pd7(void) -{ - uint res = OPER_A7_PD_8(); - uint ea = EA_A7_PI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_pi7_di(void) -{ - uint res = OPER_AY_DI_8(); - uint ea = EA_A7_PI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_pi7_ix(void) -{ - uint res = OPER_AY_IX_8(); - uint ea = EA_A7_PI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_pi7_aw(void) -{ - uint res = OPER_AW_8(); - uint ea = EA_A7_PI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_pi7_al(void) -{ - uint res = OPER_AL_8(); - uint ea = EA_A7_PI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_pi7_pcdi(void) -{ - uint res = OPER_PCDI_8(); - uint ea = EA_A7_PI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_pi7_pcix(void) -{ - uint res = OPER_PCIX_8(); - uint ea = EA_A7_PI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_pi7_i(void) -{ - uint res = OPER_I_8(); - uint ea = EA_A7_PI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_pi_ai(void) -{ - uint res = OPER_AY_AI_8(); - uint ea = EA_AX_PI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_pi_pi(void) -{ - uint res = OPER_AY_PI_8(); - uint ea = EA_AX_PI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_pi_pi7(void) -{ - uint res = OPER_A7_PI_8(); - uint ea = EA_AX_PI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_pi_pd(void) -{ - uint res = OPER_AY_PD_8(); - uint ea = EA_AX_PI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_pi_pd7(void) -{ - uint res = OPER_A7_PD_8(); - uint ea = EA_AX_PI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_pi_di(void) -{ - uint res = OPER_AY_DI_8(); - uint ea = EA_AX_PI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_pi_ix(void) -{ - uint res = OPER_AY_IX_8(); - uint ea = EA_AX_PI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_pi_aw(void) -{ - uint res = OPER_AW_8(); - uint ea = EA_AX_PI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_pi_al(void) -{ - uint res = OPER_AL_8(); - uint ea = EA_AX_PI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_pi_pcdi(void) -{ - uint res = OPER_PCDI_8(); - uint ea = EA_AX_PI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_pi_pcix(void) -{ - uint res = OPER_PCIX_8(); - uint ea = EA_AX_PI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_pi_i(void) -{ - uint res = OPER_I_8(); - uint ea = EA_AX_PI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_pd7_d(void) -{ - uint res = MASK_OUT_ABOVE_8(DY); - uint ea = EA_A7_PD_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_pd_d(void) -{ - uint res = MASK_OUT_ABOVE_8(DY); - uint ea = EA_AX_PD_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_pd7_ai(void) -{ - uint res = OPER_AY_AI_8(); - uint ea = EA_A7_PD_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_pd7_pi(void) -{ - uint res = OPER_AY_PI_8(); - uint ea = EA_A7_PD_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_pd7_pi7(void) -{ - uint res = OPER_A7_PI_8(); - uint ea = EA_A7_PD_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_pd7_pd(void) -{ - uint res = OPER_AY_PD_8(); - uint ea = EA_A7_PD_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_pd7_pd7(void) -{ - uint res = OPER_A7_PD_8(); - uint ea = EA_A7_PD_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_pd7_di(void) -{ - uint res = OPER_AY_DI_8(); - uint ea = EA_A7_PD_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_pd7_ix(void) -{ - uint res = OPER_AY_IX_8(); - uint ea = EA_A7_PD_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_pd7_aw(void) -{ - uint res = OPER_AW_8(); - uint ea = EA_A7_PD_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_pd7_al(void) -{ - uint res = OPER_AL_8(); - uint ea = EA_A7_PD_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_pd7_pcdi(void) -{ - uint res = OPER_PCDI_8(); - uint ea = EA_A7_PD_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_pd7_pcix(void) -{ - uint res = OPER_PCIX_8(); - uint ea = EA_A7_PD_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_pd7_i(void) -{ - uint res = OPER_I_8(); - uint ea = EA_A7_PD_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_pd_ai(void) -{ - uint res = OPER_AY_AI_8(); - uint ea = EA_AX_PD_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_pd_pi(void) -{ - uint res = OPER_AY_PI_8(); - uint ea = EA_AX_PD_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_pd_pi7(void) -{ - uint res = OPER_A7_PI_8(); - uint ea = EA_AX_PD_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_pd_pd(void) -{ - uint res = OPER_AY_PD_8(); - uint ea = EA_AX_PD_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_pd_pd7(void) -{ - uint res = OPER_A7_PD_8(); - uint ea = EA_AX_PD_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_pd_di(void) -{ - uint res = OPER_AY_DI_8(); - uint ea = EA_AX_PD_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_pd_ix(void) -{ - uint res = OPER_AY_IX_8(); - uint ea = EA_AX_PD_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_pd_aw(void) -{ - uint res = OPER_AW_8(); - uint ea = EA_AX_PD_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_pd_al(void) -{ - uint res = OPER_AL_8(); - uint ea = EA_AX_PD_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_pd_pcdi(void) -{ - uint res = OPER_PCDI_8(); - uint ea = EA_AX_PD_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_pd_pcix(void) -{ - uint res = OPER_PCIX_8(); - uint ea = EA_AX_PD_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_pd_i(void) -{ - uint res = OPER_I_8(); - uint ea = EA_AX_PD_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_di_d(void) -{ - uint res = MASK_OUT_ABOVE_8(DY); - uint ea = EA_AX_DI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_di_ai(void) -{ - uint res = OPER_AY_AI_8(); - uint ea = EA_AX_DI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_di_pi(void) -{ - uint res = OPER_AY_PI_8(); - uint ea = EA_AX_DI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_di_pi7(void) -{ - uint res = OPER_A7_PI_8(); - uint ea = EA_AX_DI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_di_pd(void) -{ - uint res = OPER_AY_PD_8(); - uint ea = EA_AX_DI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_di_pd7(void) -{ - uint res = OPER_A7_PD_8(); - uint ea = EA_AX_DI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_di_di(void) -{ - uint res = OPER_AY_DI_8(); - uint ea = EA_AX_DI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_di_ix(void) -{ - uint res = OPER_AY_IX_8(); - uint ea = EA_AX_DI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_di_aw(void) -{ - uint res = OPER_AW_8(); - uint ea = EA_AX_DI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_di_al(void) -{ - uint res = OPER_AL_8(); - uint ea = EA_AX_DI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_di_pcdi(void) -{ - uint res = OPER_PCDI_8(); - uint ea = EA_AX_DI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_di_pcix(void) -{ - uint res = OPER_PCIX_8(); - uint ea = EA_AX_DI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_di_i(void) -{ - uint res = OPER_I_8(); - uint ea = EA_AX_DI_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_ix_d(void) -{ - uint res = MASK_OUT_ABOVE_8(DY); - uint ea = EA_AX_IX_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_ix_ai(void) -{ - uint res = OPER_AY_AI_8(); - uint ea = EA_AX_IX_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_ix_pi(void) -{ - uint res = OPER_AY_PI_8(); - uint ea = EA_AX_IX_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_ix_pi7(void) -{ - uint res = OPER_A7_PI_8(); - uint ea = EA_AX_IX_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_ix_pd(void) -{ - uint res = OPER_AY_PD_8(); - uint ea = EA_AX_IX_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_ix_pd7(void) -{ - uint res = OPER_A7_PD_8(); - uint ea = EA_AX_IX_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_ix_di(void) -{ - uint res = OPER_AY_DI_8(); - uint ea = EA_AX_IX_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_ix_ix(void) -{ - uint res = OPER_AY_IX_8(); - uint ea = EA_AX_IX_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_ix_aw(void) -{ - uint res = OPER_AW_8(); - uint ea = EA_AX_IX_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_ix_al(void) -{ - uint res = OPER_AL_8(); - uint ea = EA_AX_IX_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_ix_pcdi(void) -{ - uint res = OPER_PCDI_8(); - uint ea = EA_AX_IX_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_ix_pcix(void) -{ - uint res = OPER_PCIX_8(); - uint ea = EA_AX_IX_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_ix_i(void) -{ - uint res = OPER_I_8(); - uint ea = EA_AX_IX_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_aw_d(void) -{ - uint res = MASK_OUT_ABOVE_8(DY); - uint ea = EA_AW_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_aw_ai(void) -{ - uint res = OPER_AY_AI_8(); - uint ea = EA_AW_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_aw_pi(void) -{ - uint res = OPER_AY_PI_8(); - uint ea = EA_AW_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_aw_pi7(void) -{ - uint res = OPER_A7_PI_8(); - uint ea = EA_AW_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_aw_pd(void) -{ - uint res = OPER_AY_PD_8(); - uint ea = EA_AW_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_aw_pd7(void) -{ - uint res = OPER_A7_PD_8(); - uint ea = EA_AW_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_aw_di(void) -{ - uint res = OPER_AY_DI_8(); - uint ea = EA_AW_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_aw_ix(void) -{ - uint res = OPER_AY_IX_8(); - uint ea = EA_AW_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_aw_aw(void) -{ - uint res = OPER_AW_8(); - uint ea = EA_AW_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_aw_al(void) -{ - uint res = OPER_AL_8(); - uint ea = EA_AW_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_aw_pcdi(void) -{ - uint res = OPER_PCDI_8(); - uint ea = EA_AW_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_aw_pcix(void) -{ - uint res = OPER_PCIX_8(); - uint ea = EA_AW_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_aw_i(void) -{ - uint res = OPER_I_8(); - uint ea = EA_AW_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_al_d(void) -{ - uint res = MASK_OUT_ABOVE_8(DY); - uint ea = EA_AL_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_al_ai(void) -{ - uint res = OPER_AY_AI_8(); - uint ea = EA_AL_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_al_pi(void) -{ - uint res = OPER_AY_PI_8(); - uint ea = EA_AL_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_al_pi7(void) -{ - uint res = OPER_A7_PI_8(); - uint ea = EA_AL_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_al_pd(void) -{ - uint res = OPER_AY_PD_8(); - uint ea = EA_AL_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_al_pd7(void) -{ - uint res = OPER_A7_PD_8(); - uint ea = EA_AL_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_al_di(void) -{ - uint res = OPER_AY_DI_8(); - uint ea = EA_AL_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_al_ix(void) -{ - uint res = OPER_AY_IX_8(); - uint ea = EA_AL_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_al_aw(void) -{ - uint res = OPER_AW_8(); - uint ea = EA_AL_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_al_al(void) -{ - uint res = OPER_AL_8(); - uint ea = EA_AL_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_al_pcdi(void) -{ - uint res = OPER_PCDI_8(); - uint ea = EA_AL_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_al_pcix(void) -{ - uint res = OPER_PCIX_8(); - uint ea = EA_AL_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_8_al_i(void) -{ - uint res = OPER_I_8(); - uint ea = EA_AL_8(); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_d_d(void) -{ - uint res = MASK_OUT_ABOVE_16(DY); - uint* r_dst = &DX; - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_d_a(void) -{ - uint res = MASK_OUT_ABOVE_16(AY); - uint* r_dst = &DX; - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_d_ai(void) -{ - uint res = OPER_AY_AI_16(); - uint* r_dst = &DX; - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_d_pi(void) -{ - uint res = OPER_AY_PI_16(); - uint* r_dst = &DX; - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_d_pd(void) -{ - uint res = OPER_AY_PD_16(); - uint* r_dst = &DX; - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_d_di(void) -{ - uint res = OPER_AY_DI_16(); - uint* r_dst = &DX; - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_d_ix(void) -{ - uint res = OPER_AY_IX_16(); - uint* r_dst = &DX; - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_d_aw(void) -{ - uint res = OPER_AW_16(); - uint* r_dst = &DX; - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_d_al(void) -{ - uint res = OPER_AL_16(); - uint* r_dst = &DX; - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_d_pcdi(void) -{ - uint res = OPER_PCDI_16(); - uint* r_dst = &DX; - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_d_pcix(void) -{ - uint res = OPER_PCIX_16(); - uint* r_dst = &DX; - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_d_i(void) -{ - uint res = OPER_I_16(); - uint* r_dst = &DX; - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_ai_d(void) -{ - uint res = MASK_OUT_ABOVE_16(DY); - uint ea = EA_AX_AI_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_ai_a(void) -{ - uint res = MASK_OUT_ABOVE_16(AY); - uint ea = EA_AX_AI_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_ai_ai(void) -{ - uint res = OPER_AY_AI_16(); - uint ea = EA_AX_AI_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_ai_pi(void) -{ - uint res = OPER_AY_PI_16(); - uint ea = EA_AX_AI_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_ai_pd(void) -{ - uint res = OPER_AY_PD_16(); - uint ea = EA_AX_AI_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_ai_di(void) -{ - uint res = OPER_AY_DI_16(); - uint ea = EA_AX_AI_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_ai_ix(void) -{ - uint res = OPER_AY_IX_16(); - uint ea = EA_AX_AI_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_ai_aw(void) -{ - uint res = OPER_AW_16(); - uint ea = EA_AX_AI_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_ai_al(void) -{ - uint res = OPER_AL_16(); - uint ea = EA_AX_AI_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_ai_pcdi(void) -{ - uint res = OPER_PCDI_16(); - uint ea = EA_AX_AI_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_ai_pcix(void) -{ - uint res = OPER_PCIX_16(); - uint ea = EA_AX_AI_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_ai_i(void) -{ - uint res = OPER_I_16(); - uint ea = EA_AX_AI_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_pi_d(void) -{ - uint res = MASK_OUT_ABOVE_16(DY); - uint ea = EA_AX_PI_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_pi_a(void) -{ - uint res = MASK_OUT_ABOVE_16(AY); - uint ea = EA_AX_PI_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_pi_ai(void) -{ - uint res = OPER_AY_AI_16(); - uint ea = EA_AX_PI_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_pi_pi(void) -{ - uint res = OPER_AY_PI_16(); - uint ea = EA_AX_PI_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_pi_pd(void) -{ - uint res = OPER_AY_PD_16(); - uint ea = EA_AX_PI_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_pi_di(void) -{ - uint res = OPER_AY_DI_16(); - uint ea = EA_AX_PI_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_pi_ix(void) -{ - uint res = OPER_AY_IX_16(); - uint ea = EA_AX_PI_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_pi_aw(void) -{ - uint res = OPER_AW_16(); - uint ea = EA_AX_PI_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_pi_al(void) -{ - uint res = OPER_AL_16(); - uint ea = EA_AX_PI_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_pi_pcdi(void) -{ - uint res = OPER_PCDI_16(); - uint ea = EA_AX_PI_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_pi_pcix(void) -{ - uint res = OPER_PCIX_16(); - uint ea = EA_AX_PI_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_pi_i(void) -{ - uint res = OPER_I_16(); - uint ea = EA_AX_PI_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_pd_d(void) -{ - uint res = MASK_OUT_ABOVE_16(DY); - uint ea = EA_AX_PD_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_pd_a(void) -{ - uint res = MASK_OUT_ABOVE_16(AY); - uint ea = EA_AX_PD_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_pd_ai(void) -{ - uint res = OPER_AY_AI_16(); - uint ea = EA_AX_PD_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_pd_pi(void) -{ - uint res = OPER_AY_PI_16(); - uint ea = EA_AX_PD_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_pd_pd(void) -{ - uint res = OPER_AY_PD_16(); - uint ea = EA_AX_PD_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_pd_di(void) -{ - uint res = OPER_AY_DI_16(); - uint ea = EA_AX_PD_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_pd_ix(void) -{ - uint res = OPER_AY_IX_16(); - uint ea = EA_AX_PD_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_pd_aw(void) -{ - uint res = OPER_AW_16(); - uint ea = EA_AX_PD_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_pd_al(void) -{ - uint res = OPER_AL_16(); - uint ea = EA_AX_PD_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_pd_pcdi(void) -{ - uint res = OPER_PCDI_16(); - uint ea = EA_AX_PD_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_pd_pcix(void) -{ - uint res = OPER_PCIX_16(); - uint ea = EA_AX_PD_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_pd_i(void) -{ - uint res = OPER_I_16(); - uint ea = EA_AX_PD_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_di_d(void) -{ - uint res = MASK_OUT_ABOVE_16(DY); - uint ea = EA_AX_DI_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_di_a(void) -{ - uint res = MASK_OUT_ABOVE_16(AY); - uint ea = EA_AX_DI_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_di_ai(void) -{ - uint res = OPER_AY_AI_16(); - uint ea = EA_AX_DI_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_di_pi(void) -{ - uint res = OPER_AY_PI_16(); - uint ea = EA_AX_DI_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_di_pd(void) -{ - uint res = OPER_AY_PD_16(); - uint ea = EA_AX_DI_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_di_di(void) -{ - uint res = OPER_AY_DI_16(); - uint ea = EA_AX_DI_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_di_ix(void) -{ - uint res = OPER_AY_IX_16(); - uint ea = EA_AX_DI_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_di_aw(void) -{ - uint res = OPER_AW_16(); - uint ea = EA_AX_DI_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_di_al(void) -{ - uint res = OPER_AL_16(); - uint ea = EA_AX_DI_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_di_pcdi(void) -{ - uint res = OPER_PCDI_16(); - uint ea = EA_AX_DI_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_di_pcix(void) -{ - uint res = OPER_PCIX_16(); - uint ea = EA_AX_DI_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_di_i(void) -{ - uint res = OPER_I_16(); - uint ea = EA_AX_DI_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_ix_d(void) -{ - uint res = MASK_OUT_ABOVE_16(DY); - uint ea = EA_AX_IX_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_ix_a(void) -{ - uint res = MASK_OUT_ABOVE_16(AY); - uint ea = EA_AX_IX_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_ix_ai(void) -{ - uint res = OPER_AY_AI_16(); - uint ea = EA_AX_IX_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_ix_pi(void) -{ - uint res = OPER_AY_PI_16(); - uint ea = EA_AX_IX_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_ix_pd(void) -{ - uint res = OPER_AY_PD_16(); - uint ea = EA_AX_IX_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_ix_di(void) -{ - uint res = OPER_AY_DI_16(); - uint ea = EA_AX_IX_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_ix_ix(void) -{ - uint res = OPER_AY_IX_16(); - uint ea = EA_AX_IX_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_ix_aw(void) -{ - uint res = OPER_AW_16(); - uint ea = EA_AX_IX_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_ix_al(void) -{ - uint res = OPER_AL_16(); - uint ea = EA_AX_IX_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_ix_pcdi(void) -{ - uint res = OPER_PCDI_16(); - uint ea = EA_AX_IX_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_ix_pcix(void) -{ - uint res = OPER_PCIX_16(); - uint ea = EA_AX_IX_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_ix_i(void) -{ - uint res = OPER_I_16(); - uint ea = EA_AX_IX_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_aw_d(void) -{ - uint res = MASK_OUT_ABOVE_16(DY); - uint ea = EA_AW_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_aw_a(void) -{ - uint res = MASK_OUT_ABOVE_16(AY); - uint ea = EA_AW_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_aw_ai(void) -{ - uint res = OPER_AY_AI_16(); - uint ea = EA_AW_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_aw_pi(void) -{ - uint res = OPER_AY_PI_16(); - uint ea = EA_AW_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_aw_pd(void) -{ - uint res = OPER_AY_PD_16(); - uint ea = EA_AW_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_aw_di(void) -{ - uint res = OPER_AY_DI_16(); - uint ea = EA_AW_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_aw_ix(void) -{ - uint res = OPER_AY_IX_16(); - uint ea = EA_AW_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_aw_aw(void) -{ - uint res = OPER_AW_16(); - uint ea = EA_AW_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_aw_al(void) -{ - uint res = OPER_AL_16(); - uint ea = EA_AW_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_aw_pcdi(void) -{ - uint res = OPER_PCDI_16(); - uint ea = EA_AW_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_aw_pcix(void) -{ - uint res = OPER_PCIX_16(); - uint ea = EA_AW_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_aw_i(void) -{ - uint res = OPER_I_16(); - uint ea = EA_AW_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_al_d(void) -{ - uint res = MASK_OUT_ABOVE_16(DY); - uint ea = EA_AL_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_al_a(void) -{ - uint res = MASK_OUT_ABOVE_16(AY); - uint ea = EA_AL_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_al_ai(void) -{ - uint res = OPER_AY_AI_16(); - uint ea = EA_AL_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_al_pi(void) -{ - uint res = OPER_AY_PI_16(); - uint ea = EA_AL_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_al_pd(void) -{ - uint res = OPER_AY_PD_16(); - uint ea = EA_AL_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_al_di(void) -{ - uint res = OPER_AY_DI_16(); - uint ea = EA_AL_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_al_ix(void) -{ - uint res = OPER_AY_IX_16(); - uint ea = EA_AL_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_al_aw(void) -{ - uint res = OPER_AW_16(); - uint ea = EA_AL_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_al_al(void) -{ - uint res = OPER_AL_16(); - uint ea = EA_AL_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_al_pcdi(void) -{ - uint res = OPER_PCDI_16(); - uint ea = EA_AL_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_al_pcix(void) -{ - uint res = OPER_PCIX_16(); - uint ea = EA_AL_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_16_al_i(void) -{ - uint res = OPER_I_16(); - uint ea = EA_AL_16(); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_d_d(void) -{ - uint res = DY; - uint* r_dst = &DX; - - *r_dst = res; - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_d_a(void) -{ - uint res = AY; - uint* r_dst = &DX; - - *r_dst = res; - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_d_ai(void) -{ - uint res = OPER_AY_AI_32(); - uint* r_dst = &DX; - - *r_dst = res; - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_d_pi(void) -{ - uint res = OPER_AY_PI_32(); - uint* r_dst = &DX; - - *r_dst = res; - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_d_pd(void) -{ - uint res = OPER_AY_PD_32(); - uint* r_dst = &DX; - - *r_dst = res; - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_d_di(void) -{ - uint res = OPER_AY_DI_32(); - uint* r_dst = &DX; - - *r_dst = res; - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_d_ix(void) -{ - uint res = OPER_AY_IX_32(); - uint* r_dst = &DX; - - *r_dst = res; - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_d_aw(void) -{ - uint res = OPER_AW_32(); - uint* r_dst = &DX; - - *r_dst = res; - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_d_al(void) -{ - uint res = OPER_AL_32(); - uint* r_dst = &DX; - - *r_dst = res; - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_d_pcdi(void) -{ - uint res = OPER_PCDI_32(); - uint* r_dst = &DX; - - *r_dst = res; - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_d_pcix(void) -{ - uint res = OPER_PCIX_32(); - uint* r_dst = &DX; - - *r_dst = res; - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_d_i(void) -{ - uint res = OPER_I_32(); - uint* r_dst = &DX; - - *r_dst = res; - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_ai_d(void) -{ - uint res = DY; - uint ea = EA_AX_AI_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_ai_a(void) -{ - uint res = AY; - uint ea = EA_AX_AI_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_ai_ai(void) -{ - uint res = OPER_AY_AI_32(); - uint ea = EA_AX_AI_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_ai_pi(void) -{ - uint res = OPER_AY_PI_32(); - uint ea = EA_AX_AI_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_ai_pd(void) -{ - uint res = OPER_AY_PD_32(); - uint ea = EA_AX_AI_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_ai_di(void) -{ - uint res = OPER_AY_DI_32(); - uint ea = EA_AX_AI_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_ai_ix(void) -{ - uint res = OPER_AY_IX_32(); - uint ea = EA_AX_AI_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_ai_aw(void) -{ - uint res = OPER_AW_32(); - uint ea = EA_AX_AI_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_ai_al(void) -{ - uint res = OPER_AL_32(); - uint ea = EA_AX_AI_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_ai_pcdi(void) -{ - uint res = OPER_PCDI_32(); - uint ea = EA_AX_AI_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_ai_pcix(void) -{ - uint res = OPER_PCIX_32(); - uint ea = EA_AX_AI_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_ai_i(void) -{ - uint res = OPER_I_32(); - uint ea = EA_AX_AI_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_pi_d(void) -{ - uint res = DY; - uint ea = EA_AX_PI_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_pi_a(void) -{ - uint res = AY; - uint ea = EA_AX_PI_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_pi_ai(void) -{ - uint res = OPER_AY_AI_32(); - uint ea = EA_AX_PI_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_pi_pi(void) -{ - uint res = OPER_AY_PI_32(); - uint ea = EA_AX_PI_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_pi_pd(void) -{ - uint res = OPER_AY_PD_32(); - uint ea = EA_AX_PI_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_pi_di(void) -{ - uint res = OPER_AY_DI_32(); - uint ea = EA_AX_PI_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_pi_ix(void) -{ - uint res = OPER_AY_IX_32(); - uint ea = EA_AX_PI_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_pi_aw(void) -{ - uint res = OPER_AW_32(); - uint ea = EA_AX_PI_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_pi_al(void) -{ - uint res = OPER_AL_32(); - uint ea = EA_AX_PI_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_pi_pcdi(void) -{ - uint res = OPER_PCDI_32(); - uint ea = EA_AX_PI_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_pi_pcix(void) -{ - uint res = OPER_PCIX_32(); - uint ea = EA_AX_PI_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_pi_i(void) -{ - uint res = OPER_I_32(); - uint ea = EA_AX_PI_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_pd_d(void) -{ - uint res = DY; - uint ea = EA_AX_PD_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_pd_a(void) -{ - uint res = AY; - uint ea = EA_AX_PD_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_pd_ai(void) -{ - uint res = OPER_AY_AI_32(); - uint ea = EA_AX_PD_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_pd_pi(void) -{ - uint res = OPER_AY_PI_32(); - uint ea = EA_AX_PD_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_pd_pd(void) -{ - uint res = OPER_AY_PD_32(); - uint ea = EA_AX_PD_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_pd_di(void) -{ - uint res = OPER_AY_DI_32(); - uint ea = EA_AX_PD_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_pd_ix(void) -{ - uint res = OPER_AY_IX_32(); - uint ea = EA_AX_PD_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_pd_aw(void) -{ - uint res = OPER_AW_32(); - uint ea = EA_AX_PD_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_pd_al(void) -{ - uint res = OPER_AL_32(); - uint ea = EA_AX_PD_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_pd_pcdi(void) -{ - uint res = OPER_PCDI_32(); - uint ea = EA_AX_PD_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_pd_pcix(void) -{ - uint res = OPER_PCIX_32(); - uint ea = EA_AX_PD_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_pd_i(void) -{ - uint res = OPER_I_32(); - uint ea = EA_AX_PD_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_di_d(void) -{ - uint res = DY; - uint ea = EA_AX_DI_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_di_a(void) -{ - uint res = AY; - uint ea = EA_AX_DI_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_di_ai(void) -{ - uint res = OPER_AY_AI_32(); - uint ea = EA_AX_DI_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_di_pi(void) -{ - uint res = OPER_AY_PI_32(); - uint ea = EA_AX_DI_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_di_pd(void) -{ - uint res = OPER_AY_PD_32(); - uint ea = EA_AX_DI_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_di_di(void) -{ - uint res = OPER_AY_DI_32(); - uint ea = EA_AX_DI_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_di_ix(void) -{ - uint res = OPER_AY_IX_32(); - uint ea = EA_AX_DI_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_di_aw(void) -{ - uint res = OPER_AW_32(); - uint ea = EA_AX_DI_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_di_al(void) -{ - uint res = OPER_AL_32(); - uint ea = EA_AX_DI_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_di_pcdi(void) -{ - uint res = OPER_PCDI_32(); - uint ea = EA_AX_DI_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_di_pcix(void) -{ - uint res = OPER_PCIX_32(); - uint ea = EA_AX_DI_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_di_i(void) -{ - uint res = OPER_I_32(); - uint ea = EA_AX_DI_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_ix_d(void) -{ - uint res = DY; - uint ea = EA_AX_IX_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_ix_a(void) -{ - uint res = AY; - uint ea = EA_AX_IX_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_ix_ai(void) -{ - uint res = OPER_AY_AI_32(); - uint ea = EA_AX_IX_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_ix_pi(void) -{ - uint res = OPER_AY_PI_32(); - uint ea = EA_AX_IX_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_ix_pd(void) -{ - uint res = OPER_AY_PD_32(); - uint ea = EA_AX_IX_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_ix_di(void) -{ - uint res = OPER_AY_DI_32(); - uint ea = EA_AX_IX_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_ix_ix(void) -{ - uint res = OPER_AY_IX_32(); - uint ea = EA_AX_IX_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_ix_aw(void) -{ - uint res = OPER_AW_32(); - uint ea = EA_AX_IX_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_ix_al(void) -{ - uint res = OPER_AL_32(); - uint ea = EA_AX_IX_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_ix_pcdi(void) -{ - uint res = OPER_PCDI_32(); - uint ea = EA_AX_IX_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_ix_pcix(void) -{ - uint res = OPER_PCIX_32(); - uint ea = EA_AX_IX_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_ix_i(void) -{ - uint res = OPER_I_32(); - uint ea = EA_AX_IX_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_aw_d(void) -{ - uint res = DY; - uint ea = EA_AW_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_aw_a(void) -{ - uint res = AY; - uint ea = EA_AW_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_aw_ai(void) -{ - uint res = OPER_AY_AI_32(); - uint ea = EA_AW_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_aw_pi(void) -{ - uint res = OPER_AY_PI_32(); - uint ea = EA_AW_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_aw_pd(void) -{ - uint res = OPER_AY_PD_32(); - uint ea = EA_AW_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_aw_di(void) -{ - uint res = OPER_AY_DI_32(); - uint ea = EA_AW_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_aw_ix(void) -{ - uint res = OPER_AY_IX_32(); - uint ea = EA_AW_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_aw_aw(void) -{ - uint res = OPER_AW_32(); - uint ea = EA_AW_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_aw_al(void) -{ - uint res = OPER_AL_32(); - uint ea = EA_AW_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_aw_pcdi(void) -{ - uint res = OPER_PCDI_32(); - uint ea = EA_AW_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_aw_pcix(void) -{ - uint res = OPER_PCIX_32(); - uint ea = EA_AW_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_aw_i(void) -{ - uint res = OPER_I_32(); - uint ea = EA_AW_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_al_d(void) -{ - uint res = DY; - uint ea = EA_AL_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_al_a(void) -{ - uint res = AY; - uint ea = EA_AL_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_al_ai(void) -{ - uint res = OPER_AY_AI_32(); - uint ea = EA_AL_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_al_pi(void) -{ - uint res = OPER_AY_PI_32(); - uint ea = EA_AL_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_al_pd(void) -{ - uint res = OPER_AY_PD_32(); - uint ea = EA_AL_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_al_di(void) -{ - uint res = OPER_AY_DI_32(); - uint ea = EA_AL_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_al_ix(void) -{ - uint res = OPER_AY_IX_32(); - uint ea = EA_AL_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_al_aw(void) -{ - uint res = OPER_AW_32(); - uint ea = EA_AL_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_al_al(void) -{ - uint res = OPER_AL_32(); - uint ea = EA_AL_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_al_pcdi(void) -{ - uint res = OPER_PCDI_32(); - uint ea = EA_AL_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_al_pcix(void) -{ - uint res = OPER_PCIX_32(); - uint ea = EA_AL_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_move_32_al_i(void) -{ - uint res = OPER_I_32(); - uint ea = EA_AL_32(); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_movea_16_d(void) -{ - AX = MAKE_INT_16(DY); -} - - -void m68k_op_movea_16_a(void) -{ - AX = MAKE_INT_16(AY); -} - - -void m68k_op_movea_16_ai(void) -{ - AX = MAKE_INT_16(OPER_AY_AI_16()); -} - - -void m68k_op_movea_16_pi(void) -{ - AX = MAKE_INT_16(OPER_AY_PI_16()); -} - - -void m68k_op_movea_16_pd(void) -{ - AX = MAKE_INT_16(OPER_AY_PD_16()); -} - - -void m68k_op_movea_16_di(void) -{ - AX = MAKE_INT_16(OPER_AY_DI_16()); -} - - -void m68k_op_movea_16_ix(void) -{ - AX = MAKE_INT_16(OPER_AY_IX_16()); -} - - -void m68k_op_movea_16_aw(void) -{ - AX = MAKE_INT_16(OPER_AW_16()); -} - - -void m68k_op_movea_16_al(void) -{ - AX = MAKE_INT_16(OPER_AL_16()); -} - - -void m68k_op_movea_16_pcdi(void) -{ - AX = MAKE_INT_16(OPER_PCDI_16()); -} - - -void m68k_op_movea_16_pcix(void) -{ - AX = MAKE_INT_16(OPER_PCIX_16()); -} - - -void m68k_op_movea_16_i(void) -{ - AX = MAKE_INT_16(OPER_I_16()); -} - - -void m68k_op_movea_32_d(void) -{ - AX = DY; -} - - -void m68k_op_movea_32_a(void) -{ - AX = AY; -} - - -void m68k_op_movea_32_ai(void) -{ - AX = OPER_AY_AI_32(); -} - - -void m68k_op_movea_32_pi(void) -{ - AX = OPER_AY_PI_32(); -} - - -void m68k_op_movea_32_pd(void) -{ - AX = OPER_AY_PD_32(); -} - - -void m68k_op_movea_32_di(void) -{ - AX = OPER_AY_DI_32(); -} - - -void m68k_op_movea_32_ix(void) -{ - AX = OPER_AY_IX_32(); -} - - -void m68k_op_movea_32_aw(void) -{ - AX = OPER_AW_32(); -} - - -void m68k_op_movea_32_al(void) -{ - AX = OPER_AL_32(); -} - - -void m68k_op_movea_32_pcdi(void) -{ - AX = OPER_PCDI_32(); -} - - -void m68k_op_movea_32_pcix(void) -{ - AX = OPER_PCIX_32(); -} - - -void m68k_op_movea_32_i(void) -{ - AX = OPER_I_32(); -} - - -void m68k_op_move_16_frc_d(void) -{ - if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) - { - DY = MASK_OUT_BELOW_16(DY) | m68ki_get_ccr(); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_move_16_frc_ai(void) -{ - if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) - { - m68ki_write_16(EA_AY_AI_16(), m68ki_get_ccr()); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_move_16_frc_pi(void) -{ - if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) - { - m68ki_write_16(EA_AY_PI_16(), m68ki_get_ccr()); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_move_16_frc_pd(void) -{ - if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) - { - m68ki_write_16(EA_AY_PD_16(), m68ki_get_ccr()); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_move_16_frc_di(void) -{ - if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) - { - m68ki_write_16(EA_AY_DI_16(), m68ki_get_ccr()); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_move_16_frc_ix(void) -{ - if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) - { - m68ki_write_16(EA_AY_IX_16(), m68ki_get_ccr()); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_move_16_frc_aw(void) -{ - if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) - { - m68ki_write_16(EA_AW_16(), m68ki_get_ccr()); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_move_16_frc_al(void) -{ - if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) - { - m68ki_write_16(EA_AL_16(), m68ki_get_ccr()); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_move_16_toc_d(void) -{ - m68ki_set_ccr(DY); -} - - -void m68k_op_move_16_toc_ai(void) -{ - m68ki_set_ccr(OPER_AY_AI_16()); -} - - -void m68k_op_move_16_toc_pi(void) -{ - m68ki_set_ccr(OPER_AY_PI_16()); -} - - -void m68k_op_move_16_toc_pd(void) -{ - m68ki_set_ccr(OPER_AY_PD_16()); -} - - -void m68k_op_move_16_toc_di(void) -{ - m68ki_set_ccr(OPER_AY_DI_16()); -} - - -void m68k_op_move_16_toc_ix(void) -{ - m68ki_set_ccr(OPER_AY_IX_16()); -} - - -void m68k_op_move_16_toc_aw(void) -{ - m68ki_set_ccr(OPER_AW_16()); -} - - -void m68k_op_move_16_toc_al(void) -{ - m68ki_set_ccr(OPER_AL_16()); -} - - -void m68k_op_move_16_toc_pcdi(void) -{ - m68ki_set_ccr(OPER_PCDI_16()); -} - - -void m68k_op_move_16_toc_pcix(void) -{ - m68ki_set_ccr(OPER_PCIX_16()); -} - - -void m68k_op_move_16_toc_i(void) -{ - m68ki_set_ccr(OPER_I_16()); -} - - -void m68k_op_move_16_frs_d(void) -{ - if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */ - { - DY = MASK_OUT_BELOW_16(DY) | m68ki_get_sr(); - return; - } - m68ki_exception_privilege_violation(); -} - - -void m68k_op_move_16_frs_ai(void) -{ - if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */ - { - uint ea = EA_AY_AI_16(); - m68ki_write_16(ea, m68ki_get_sr()); - return; - } - m68ki_exception_privilege_violation(); -} - - -void m68k_op_move_16_frs_pi(void) -{ - if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */ - { - uint ea = EA_AY_PI_16(); - m68ki_write_16(ea, m68ki_get_sr()); - return; - } - m68ki_exception_privilege_violation(); -} - - -void m68k_op_move_16_frs_pd(void) -{ - if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */ - { - uint ea = EA_AY_PD_16(); - m68ki_write_16(ea, m68ki_get_sr()); - return; - } - m68ki_exception_privilege_violation(); -} - - -void m68k_op_move_16_frs_di(void) -{ - if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */ - { - uint ea = EA_AY_DI_16(); - m68ki_write_16(ea, m68ki_get_sr()); - return; - } - m68ki_exception_privilege_violation(); -} - - -void m68k_op_move_16_frs_ix(void) -{ - if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */ - { - uint ea = EA_AY_IX_16(); - m68ki_write_16(ea, m68ki_get_sr()); - return; - } - m68ki_exception_privilege_violation(); -} - - -void m68k_op_move_16_frs_aw(void) -{ - if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */ - { - uint ea = EA_AW_16(); - m68ki_write_16(ea, m68ki_get_sr()); - return; - } - m68ki_exception_privilege_violation(); -} - - -void m68k_op_move_16_frs_al(void) -{ - if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */ - { - uint ea = EA_AL_16(); - m68ki_write_16(ea, m68ki_get_sr()); - return; - } - m68ki_exception_privilege_violation(); -} - - -void m68k_op_move_16_tos_d(void) -{ - if(FLAG_S) - { - m68ki_set_sr(DY); - return; - } - m68ki_exception_privilege_violation(); -} - - -void m68k_op_move_16_tos_ai(void) -{ - if(FLAG_S) - { - uint new_sr = OPER_AY_AI_16(); - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_set_sr(new_sr); - return; - } - m68ki_exception_privilege_violation(); -} - - -void m68k_op_move_16_tos_pi(void) -{ - if(FLAG_S) - { - uint new_sr = OPER_AY_PI_16(); - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_set_sr(new_sr); - return; - } - m68ki_exception_privilege_violation(); -} - - -void m68k_op_move_16_tos_pd(void) -{ - if(FLAG_S) - { - uint new_sr = OPER_AY_PD_16(); - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_set_sr(new_sr); - return; - } - m68ki_exception_privilege_violation(); -} - - -void m68k_op_move_16_tos_di(void) -{ - if(FLAG_S) - { - uint new_sr = OPER_AY_DI_16(); - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_set_sr(new_sr); - return; - } - m68ki_exception_privilege_violation(); -} - - -void m68k_op_move_16_tos_ix(void) -{ - if(FLAG_S) - { - uint new_sr = OPER_AY_IX_16(); - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_set_sr(new_sr); - return; - } - m68ki_exception_privilege_violation(); -} - - -void m68k_op_move_16_tos_aw(void) -{ - if(FLAG_S) - { - uint new_sr = OPER_AW_16(); - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_set_sr(new_sr); - return; - } - m68ki_exception_privilege_violation(); -} - - -void m68k_op_move_16_tos_al(void) -{ - if(FLAG_S) - { - uint new_sr = OPER_AL_16(); - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_set_sr(new_sr); - return; - } - m68ki_exception_privilege_violation(); -} - - -void m68k_op_move_16_tos_pcdi(void) -{ - if(FLAG_S) - { - uint new_sr = OPER_PCDI_16(); - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_set_sr(new_sr); - return; - } - m68ki_exception_privilege_violation(); -} - - -void m68k_op_move_16_tos_pcix(void) -{ - if(FLAG_S) - { - uint new_sr = OPER_PCIX_16(); - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_set_sr(new_sr); - return; - } - m68ki_exception_privilege_violation(); -} - - -void m68k_op_move_16_tos_i(void) -{ - if(FLAG_S) - { - uint new_sr = OPER_I_16(); - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_set_sr(new_sr); - return; - } - m68ki_exception_privilege_violation(); -} - - -void m68k_op_move_32_fru(void) -{ - if(FLAG_S) - { - AY = REG_USP; - return; - } - m68ki_exception_privilege_violation(); -} - - -void m68k_op_move_32_tou(void) -{ - if(FLAG_S) - { - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - REG_USP = AY; - return; - } - m68ki_exception_privilege_violation(); -} - - -void m68k_op_movec_32_cr(void) -{ - if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) - { - if(FLAG_S) - { - uint word2 = OPER_I_16(); - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - switch (word2 & 0xfff) - { - case 0x000: /* SFC */ - REG_DA[(word2 >> 12) & 15] = REG_SFC; - return; - case 0x001: /* DFC */ - REG_DA[(word2 >> 12) & 15] = REG_DFC; - return; - case 0x002: /* CACR */ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - REG_DA[(word2 >> 12) & 15] = REG_CACR; - return; - } - return; - case 0x800: /* USP */ - REG_DA[(word2 >> 12) & 15] = REG_USP; - return; - case 0x801: /* VBR */ - REG_DA[(word2 >> 12) & 15] = REG_VBR; - return; - case 0x802: /* CAAR */ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - REG_DA[(word2 >> 12) & 15] = REG_CAAR; - return; - } - m68ki_exception_illegal(); - break; - case 0x803: /* MSP */ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - REG_DA[(word2 >> 12) & 15] = FLAG_M ? REG_SP : REG_MSP; - return; - } - m68ki_exception_illegal(); - return; - case 0x804: /* ISP */ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - REG_DA[(word2 >> 12) & 15] = FLAG_M ? REG_ISP : REG_SP; - return; - } - m68ki_exception_illegal(); - return; - default: - m68ki_exception_illegal(); - return; - } - } - m68ki_exception_privilege_violation(); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_movec_32_rc(void) -{ - if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) - { - if(FLAG_S) - { - uint word2 = OPER_I_16(); - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - switch (word2 & 0xfff) - { - case 0x000: /* SFC */ - REG_SFC = REG_DA[(word2 >> 12) & 15] & 7; - return; - case 0x001: /* DFC */ - REG_DFC = REG_DA[(word2 >> 12) & 15] & 7; - return; - case 0x002: /* CACR */ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - REG_CACR = REG_DA[(word2 >> 12) & 15]; - return; - } - m68ki_exception_illegal(); - return; - case 0x800: /* USP */ - REG_USP = REG_DA[(word2 >> 12) & 15]; - return; - case 0x801: /* VBR */ - REG_VBR = REG_DA[(word2 >> 12) & 15]; - return; - case 0x802: /* CAAR */ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - REG_CAAR = REG_DA[(word2 >> 12) & 15]; - return; - } - m68ki_exception_illegal(); - return; - case 0x803: /* MSP */ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - /* we are in supervisor mode so just check for M flag */ - if(!FLAG_M) - { - REG_MSP = REG_DA[(word2 >> 12) & 15]; - return; - } - REG_SP = REG_DA[(word2 >> 12) & 15]; - return; - } - m68ki_exception_illegal(); - return; - case 0x804: /* ISP */ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(!FLAG_M) - { - REG_SP = REG_DA[(word2 >> 12) & 15]; - return; - } - REG_ISP = REG_DA[(word2 >> 12) & 15]; - return; - } - m68ki_exception_illegal(); - return; - default: - m68ki_exception_illegal(); - return; - } - } - m68ki_exception_privilege_violation(); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_movem_16_re_pd(void) -{ - uint i = 0; - uint register_list = OPER_I_16(); - uint ea = AY; - uint count = 0; - - for(; i < 16; i++) - if(register_list & (1 << i)) - { - ea -= 2; - m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[15-i])); - count++; - } - AY = ea; - - USE_CYCLES(count<> 8)); - m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src)); -} - - -void m68k_op_movep_32_re(void) -{ - uint ea = EA_AY_DI_32(); - uint src = DX; - - m68ki_write_8(ea, MASK_OUT_ABOVE_8(src >> 24)); - m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 16)); - m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 8)); - m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src)); -} - - -void m68k_op_movep_16_er(void) -{ - uint ea = EA_AY_DI_16(); - uint* r_dst = &DX; - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | ((m68ki_read_8(ea) << 8) + m68ki_read_8(ea + 2)); -} - - -void m68k_op_movep_32_er(void) -{ - uint ea = EA_AY_DI_32(); - - DX = (m68ki_read_8(ea) << 24) + (m68ki_read_8(ea + 2) << 16) - + (m68ki_read_8(ea + 4) << 8) + m68ki_read_8(ea + 6); -} - - -void m68k_op_moves_8_ai(void) -{ - if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) - { - if(FLAG_S) - { - uint word2 = OPER_I_16(); - uint ea = EA_AY_AI_8(); - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - if(BIT_B(word2)) /* Register to memory */ - { - m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15])); - return; - } - if(BIT_F(word2)) /* Memory to address register */ - { - REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC)); - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - USE_CYCLES(2); - return; - } - /* Memory to data register */ - REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC); - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - USE_CYCLES(2); - return; - } - m68ki_exception_privilege_violation(); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_moves_8_pi(void) -{ - if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) - { - if(FLAG_S) - { - uint word2 = OPER_I_16(); - uint ea = EA_AY_PI_8(); - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - if(BIT_B(word2)) /* Register to memory */ - { - m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15])); - return; - } - if(BIT_F(word2)) /* Memory to address register */ - { - REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC)); - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - USE_CYCLES(2); - return; - } - /* Memory to data register */ - REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC); - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - USE_CYCLES(2); - return; - } - m68ki_exception_privilege_violation(); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_moves_8_pi7(void) -{ - if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) - { - if(FLAG_S) - { - uint word2 = OPER_I_16(); - uint ea = EA_A7_PI_8(); - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - if(BIT_B(word2)) /* Register to memory */ - { - m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15])); - return; - } - if(BIT_F(word2)) /* Memory to address register */ - { - REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC)); - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - USE_CYCLES(2); - return; - } - /* Memory to data register */ - REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC); - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - USE_CYCLES(2); - return; - } - m68ki_exception_privilege_violation(); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_moves_8_pd(void) -{ - if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) - { - if(FLAG_S) - { - uint word2 = OPER_I_16(); - uint ea = EA_AY_PD_8(); - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - if(BIT_B(word2)) /* Register to memory */ - { - m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15])); - return; - } - if(BIT_F(word2)) /* Memory to address register */ - { - REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC)); - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - USE_CYCLES(2); - return; - } - /* Memory to data register */ - REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC); - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - USE_CYCLES(2); - return; - } - m68ki_exception_privilege_violation(); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_moves_8_pd7(void) -{ - if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) - { - if(FLAG_S) - { - uint word2 = OPER_I_16(); - uint ea = EA_A7_PD_8(); - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - if(BIT_B(word2)) /* Register to memory */ - { - m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15])); - return; - } - if(BIT_F(word2)) /* Memory to address register */ - { - REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC)); - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - USE_CYCLES(2); - return; - } - /* Memory to data register */ - REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC); - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - USE_CYCLES(2); - return; - } - m68ki_exception_privilege_violation(); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_moves_8_di(void) -{ - if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) - { - if(FLAG_S) - { - uint word2 = OPER_I_16(); - uint ea = EA_AY_DI_8(); - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - if(BIT_B(word2)) /* Register to memory */ - { - m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15])); - return; - } - if(BIT_F(word2)) /* Memory to address register */ - { - REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC)); - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - USE_CYCLES(2); - return; - } - /* Memory to data register */ - REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC); - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - USE_CYCLES(2); - return; - } - m68ki_exception_privilege_violation(); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_moves_8_ix(void) -{ - if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) - { - if(FLAG_S) - { - uint word2 = OPER_I_16(); - uint ea = EA_AY_IX_8(); - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - if(BIT_B(word2)) /* Register to memory */ - { - m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15])); - return; - } - if(BIT_F(word2)) /* Memory to address register */ - { - REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC)); - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - USE_CYCLES(2); - return; - } - /* Memory to data register */ - REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC); - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - USE_CYCLES(2); - return; - } - m68ki_exception_privilege_violation(); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_moves_8_aw(void) -{ - if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) - { - if(FLAG_S) - { - uint word2 = OPER_I_16(); - uint ea = EA_AW_8(); - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - if(BIT_B(word2)) /* Register to memory */ - { - m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15])); - return; - } - if(BIT_F(word2)) /* Memory to address register */ - { - REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC)); - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - USE_CYCLES(2); - return; - } - /* Memory to data register */ - REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC); - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - USE_CYCLES(2); - return; - } - m68ki_exception_privilege_violation(); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_moves_8_al(void) -{ - if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) - { - if(FLAG_S) - { - uint word2 = OPER_I_16(); - uint ea = EA_AL_8(); - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - if(BIT_B(word2)) /* Register to memory */ - { - m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15])); - return; - } - if(BIT_F(word2)) /* Memory to address register */ - { - REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC)); - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - USE_CYCLES(2); - return; - } - /* Memory to data register */ - REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC); - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - USE_CYCLES(2); - return; - } - m68ki_exception_privilege_violation(); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_moves_16_ai(void) -{ - if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) - { - if(FLAG_S) - { - uint word2 = OPER_I_16(); - uint ea = EA_AY_AI_16(); - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - if(BIT_B(word2)) /* Register to memory */ - { - m68ki_write_16_fc(ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15])); - return; - } - if(BIT_F(word2)) /* Memory to address register */ - { - REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(ea, REG_SFC)); - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - USE_CYCLES(2); - return; - } - /* Memory to data register */ - REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(ea, REG_SFC); - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - USE_CYCLES(2); - return; - } - m68ki_exception_privilege_violation(); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_moves_16_pi(void) -{ - if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) - { - if(FLAG_S) - { - uint word2 = OPER_I_16(); - uint ea = EA_AY_PI_16(); - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - if(BIT_B(word2)) /* Register to memory */ - { - m68ki_write_16_fc(ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15])); - return; - } - if(BIT_F(word2)) /* Memory to address register */ - { - REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(ea, REG_SFC)); - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - USE_CYCLES(2); - return; - } - /* Memory to data register */ - REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(ea, REG_SFC); - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - USE_CYCLES(2); - return; - } - m68ki_exception_privilege_violation(); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_moves_16_pd(void) -{ - if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) - { - if(FLAG_S) - { - uint word2 = OPER_I_16(); - uint ea = EA_AY_PD_16(); - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - if(BIT_B(word2)) /* Register to memory */ - { - m68ki_write_16_fc(ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15])); - return; - } - if(BIT_F(word2)) /* Memory to address register */ - { - REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(ea, REG_SFC)); - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - USE_CYCLES(2); - return; - } - /* Memory to data register */ - REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(ea, REG_SFC); - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - USE_CYCLES(2); - return; - } - m68ki_exception_privilege_violation(); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_moves_16_di(void) -{ - if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) - { - if(FLAG_S) - { - uint word2 = OPER_I_16(); - uint ea = EA_AY_DI_16(); - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - if(BIT_B(word2)) /* Register to memory */ - { - m68ki_write_16_fc(ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15])); - return; - } - if(BIT_F(word2)) /* Memory to address register */ - { - REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(ea, REG_SFC)); - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - USE_CYCLES(2); - return; - } - /* Memory to data register */ - REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(ea, REG_SFC); - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - USE_CYCLES(2); - return; - } - m68ki_exception_privilege_violation(); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_moves_16_ix(void) -{ - if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) - { - if(FLAG_S) - { - uint word2 = OPER_I_16(); - uint ea = EA_AY_IX_16(); - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - if(BIT_B(word2)) /* Register to memory */ - { - m68ki_write_16_fc(ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15])); - return; - } - if(BIT_F(word2)) /* Memory to address register */ - { - REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(ea, REG_SFC)); - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - USE_CYCLES(2); - return; - } - /* Memory to data register */ - REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(ea, REG_SFC); - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - USE_CYCLES(2); - return; - } - m68ki_exception_privilege_violation(); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_moves_16_aw(void) -{ - if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) - { - if(FLAG_S) - { - uint word2 = OPER_I_16(); - uint ea = EA_AW_16(); - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - if(BIT_B(word2)) /* Register to memory */ - { - m68ki_write_16_fc(ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15])); - return; - } - if(BIT_F(word2)) /* Memory to address register */ - { - REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(ea, REG_SFC)); - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - USE_CYCLES(2); - return; - } - /* Memory to data register */ - REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(ea, REG_SFC); - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - USE_CYCLES(2); - return; - } - m68ki_exception_privilege_violation(); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_moves_16_al(void) -{ - if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) - { - if(FLAG_S) - { - uint word2 = OPER_I_16(); - uint ea = EA_AL_16(); - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - if(BIT_B(word2)) /* Register to memory */ - { - m68ki_write_16_fc(ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15])); - return; - } - if(BIT_F(word2)) /* Memory to address register */ - { - REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(ea, REG_SFC)); - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - USE_CYCLES(2); - return; - } - /* Memory to data register */ - REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(ea, REG_SFC); - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - USE_CYCLES(2); - return; - } - m68ki_exception_privilege_violation(); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_moves_32_ai(void) -{ - if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) - { - if(FLAG_S) - { - uint word2 = OPER_I_16(); - uint ea = EA_AY_AI_32(); - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - if(BIT_B(word2)) /* Register to memory */ - { - m68ki_write_32_fc(ea, REG_DFC, REG_DA[(word2 >> 12) & 15]); - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - USE_CYCLES(2); - return; - } - /* Memory to register */ - REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(ea, REG_SFC); - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - USE_CYCLES(2); - return; - } - m68ki_exception_privilege_violation(); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_moves_32_pi(void) -{ - if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) - { - if(FLAG_S) - { - uint word2 = OPER_I_16(); - uint ea = EA_AY_PI_32(); - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - if(BIT_B(word2)) /* Register to memory */ - { - m68ki_write_32_fc(ea, REG_DFC, REG_DA[(word2 >> 12) & 15]); - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - USE_CYCLES(2); - return; - } - /* Memory to register */ - REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(ea, REG_SFC); - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - USE_CYCLES(2); - return; - } - m68ki_exception_privilege_violation(); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_moves_32_pd(void) -{ - if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) - { - if(FLAG_S) - { - uint word2 = OPER_I_16(); - uint ea = EA_AY_PD_32(); - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - if(BIT_B(word2)) /* Register to memory */ - { - m68ki_write_32_fc(ea, REG_DFC, REG_DA[(word2 >> 12) & 15]); - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - USE_CYCLES(2); - return; - } - /* Memory to register */ - REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(ea, REG_SFC); - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - USE_CYCLES(2); - return; - } - m68ki_exception_privilege_violation(); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_moves_32_di(void) -{ - if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) - { - if(FLAG_S) - { - uint word2 = OPER_I_16(); - uint ea = EA_AY_DI_32(); - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - if(BIT_B(word2)) /* Register to memory */ - { - m68ki_write_32_fc(ea, REG_DFC, REG_DA[(word2 >> 12) & 15]); - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - USE_CYCLES(2); - return; - } - /* Memory to register */ - REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(ea, REG_SFC); - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - USE_CYCLES(2); - return; - } - m68ki_exception_privilege_violation(); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_moves_32_ix(void) -{ - if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) - { - if(FLAG_S) - { - uint word2 = OPER_I_16(); - uint ea = EA_AY_IX_32(); - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - if(BIT_B(word2)) /* Register to memory */ - { - m68ki_write_32_fc(ea, REG_DFC, REG_DA[(word2 >> 12) & 15]); - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - USE_CYCLES(2); - return; - } - /* Memory to register */ - REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(ea, REG_SFC); - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - USE_CYCLES(2); - return; - } - m68ki_exception_privilege_violation(); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_moves_32_aw(void) -{ - if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) - { - if(FLAG_S) - { - uint word2 = OPER_I_16(); - uint ea = EA_AW_32(); - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - if(BIT_B(word2)) /* Register to memory */ - { - m68ki_write_32_fc(ea, REG_DFC, REG_DA[(word2 >> 12) & 15]); - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - USE_CYCLES(2); - return; - } - /* Memory to register */ - REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(ea, REG_SFC); - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - USE_CYCLES(2); - return; - } - m68ki_exception_privilege_violation(); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_moves_32_al(void) -{ - if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) - { - if(FLAG_S) - { - uint word2 = OPER_I_16(); - uint ea = EA_AL_32(); - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - if(BIT_B(word2)) /* Register to memory */ - { - m68ki_write_32_fc(ea, REG_DFC, REG_DA[(word2 >> 12) & 15]); - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - USE_CYCLES(2); - return; - } - /* Memory to register */ - REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(ea, REG_SFC); - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - USE_CYCLES(2); - return; - } - m68ki_exception_privilege_violation(); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_moveq_32(void) -{ - uint res = DX = MAKE_INT_8(MASK_OUT_ABOVE_8(REG_IR)); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_muls_16_d(void) -{ - uint* r_dst = &DX; - uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(DY) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst))); - - *r_dst = res; - - FLAG_Z = res; - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_muls_16_ai(void) -{ - uint* r_dst = &DX; - uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_AY_AI_16()) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst))); - - *r_dst = res; - - FLAG_Z = res; - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_muls_16_pi(void) -{ - uint* r_dst = &DX; - uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_AY_PI_16()) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst))); - - *r_dst = res; - - FLAG_Z = res; - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_muls_16_pd(void) -{ - uint* r_dst = &DX; - uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_AY_PD_16()) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst))); - - *r_dst = res; - - FLAG_Z = res; - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_muls_16_di(void) -{ - uint* r_dst = &DX; - uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_AY_DI_16()) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst))); - - *r_dst = res; - - FLAG_Z = res; - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_muls_16_ix(void) -{ - uint* r_dst = &DX; - uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_AY_IX_16()) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst))); - - *r_dst = res; - - FLAG_Z = res; - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_muls_16_aw(void) -{ - uint* r_dst = &DX; - uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_AW_16()) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst))); - - *r_dst = res; - - FLAG_Z = res; - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_muls_16_al(void) -{ - uint* r_dst = &DX; - uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_AL_16()) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst))); - - *r_dst = res; - - FLAG_Z = res; - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_muls_16_pcdi(void) -{ - uint* r_dst = &DX; - uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_PCDI_16()) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst))); - - *r_dst = res; - - FLAG_Z = res; - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_muls_16_pcix(void) -{ - uint* r_dst = &DX; - uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_PCIX_16()) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst))); - - *r_dst = res; - - FLAG_Z = res; - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_muls_16_i(void) -{ - uint* r_dst = &DX; - uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_I_16()) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst))); - - *r_dst = res; - - FLAG_Z = res; - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_mulu_16_d(void) -{ - uint* r_dst = &DX; - uint res = MASK_OUT_ABOVE_16(DY) * MASK_OUT_ABOVE_16(*r_dst); - - *r_dst = res; - - FLAG_Z = res; - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_mulu_16_ai(void) -{ - uint* r_dst = &DX; - uint res = OPER_AY_AI_16() * MASK_OUT_ABOVE_16(*r_dst); - - *r_dst = res; - - FLAG_Z = res; - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_mulu_16_pi(void) -{ - uint* r_dst = &DX; - uint res = OPER_AY_PI_16() * MASK_OUT_ABOVE_16(*r_dst); - - *r_dst = res; - - FLAG_Z = res; - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_mulu_16_pd(void) -{ - uint* r_dst = &DX; - uint res = OPER_AY_PD_16() * MASK_OUT_ABOVE_16(*r_dst); - - *r_dst = res; - - FLAG_Z = res; - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_mulu_16_di(void) -{ - uint* r_dst = &DX; - uint res = OPER_AY_DI_16() * MASK_OUT_ABOVE_16(*r_dst); - - *r_dst = res; - - FLAG_Z = res; - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_mulu_16_ix(void) -{ - uint* r_dst = &DX; - uint res = OPER_AY_IX_16() * MASK_OUT_ABOVE_16(*r_dst); - - *r_dst = res; - - FLAG_Z = res; - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_mulu_16_aw(void) -{ - uint* r_dst = &DX; - uint res = OPER_AW_16() * MASK_OUT_ABOVE_16(*r_dst); - - *r_dst = res; - - FLAG_Z = res; - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_mulu_16_al(void) -{ - uint* r_dst = &DX; - uint res = OPER_AL_16() * MASK_OUT_ABOVE_16(*r_dst); - - *r_dst = res; - - FLAG_Z = res; - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_mulu_16_pcdi(void) -{ - uint* r_dst = &DX; - uint res = OPER_PCDI_16() * MASK_OUT_ABOVE_16(*r_dst); - - *r_dst = res; - - FLAG_Z = res; - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_mulu_16_pcix(void) -{ - uint* r_dst = &DX; - uint res = OPER_PCIX_16() * MASK_OUT_ABOVE_16(*r_dst); - - *r_dst = res; - - FLAG_Z = res; - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_mulu_16_i(void) -{ - uint* r_dst = &DX; - uint res = OPER_I_16() * MASK_OUT_ABOVE_16(*r_dst); - - *r_dst = res; - - FLAG_Z = res; - FLAG_N = NFLAG_32(res); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_mull_32_d(void) -{ -#if M68K_USE_64_BIT - - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint64 src = DY; - uint64 dst = REG_D[(word2 >> 12) & 7]; - uint64 res; - - FLAG_C = CFLAG_CLEAR; - - if(BIT_B(word2)) /* signed */ - { - res = (sint64)((sint32)src) * (sint64)((sint32)dst); - if(!BIT_A(word2)) - { - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_N = NFLAG_32(res); - FLAG_V = ((sint64)res != (sint32)res)<<7; - REG_D[(word2 >> 12) & 7] = FLAG_Z; - return; - } - FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); - FLAG_N = NFLAG_64(res); - FLAG_V = VFLAG_CLEAR; - REG_D[word2 & 7] = (res >> 32); - REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); - return; - } - - res = src * dst; - if(!BIT_A(word2)) - { - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_N = NFLAG_32(res); - FLAG_V = (res > 0xffffffff)<<7; - REG_D[(word2 >> 12) & 7] = FLAG_Z; - return; - } - FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); - FLAG_N = NFLAG_64(res); - FLAG_V = VFLAG_CLEAR; - REG_D[word2 & 7] = (res >> 32); - REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); - return; - } - m68ki_exception_illegal(); - -#else - - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint src = DY; - uint dst = REG_D[(word2 >> 12) & 7]; - uint neg = GET_MSB_32(src ^ dst); - uint src1; - uint src2; - uint dst1; - uint dst2; - uint r1; - uint r2; - uint r3; - uint r4; - uint lo; - uint hi; - - FLAG_C = CFLAG_CLEAR; - - if(BIT_B(word2)) /* signed */ - { - if(GET_MSB_32(src)) - src = (uint)MASK_OUT_ABOVE_32(-(sint)src); - if(GET_MSB_32(dst)) - dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst); - } - - src1 = MASK_OUT_ABOVE_16(src); - src2 = src>>16; - dst1 = MASK_OUT_ABOVE_16(dst); - dst2 = dst>>16; - - - r1 = src1 * dst1; - r2 = src1 * dst2; - r3 = src2 * dst1; - r4 = src2 * dst2; - - lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16); - hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16); - - if(BIT_B(word2) && neg) - { - hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0)); - lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo); - } - - if(BIT_A(word2)) - { - REG_D[word2 & 7] = hi; - REG_D[(word2 >> 12) & 7] = lo; - FLAG_N = NFLAG_32(hi); - FLAG_Z = hi | lo; - FLAG_V = VFLAG_CLEAR; - return; - } - - REG_D[(word2 >> 12) & 7] = lo; - FLAG_N = NFLAG_32(lo); - FLAG_Z = lo; - if(BIT_B(word2)) - FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7; - else - FLAG_V = (hi != 0) << 7; - return; - } - m68ki_exception_illegal(); - -#endif -} - - -void m68k_op_mull_32_ai(void) -{ -#if M68K_USE_64_BIT - - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint64 src = OPER_AY_AI_32(); - uint64 dst = REG_D[(word2 >> 12) & 7]; - uint64 res; - - FLAG_C = CFLAG_CLEAR; - - if(BIT_B(word2)) /* signed */ - { - res = (sint64)((sint32)src) * (sint64)((sint32)dst); - if(!BIT_A(word2)) - { - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_N = NFLAG_32(res); - FLAG_V = ((sint64)res != (sint32)res)<<7; - REG_D[(word2 >> 12) & 7] = FLAG_Z; - return; - } - FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); - FLAG_N = NFLAG_64(res); - FLAG_V = VFLAG_CLEAR; - REG_D[word2 & 7] = (res >> 32); - REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); - return; - } - - res = src * dst; - if(!BIT_A(word2)) - { - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_N = NFLAG_32(res); - FLAG_V = (res > 0xffffffff)<<7; - REG_D[(word2 >> 12) & 7] = FLAG_Z; - return; - } - FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); - FLAG_N = NFLAG_64(res); - FLAG_V = VFLAG_CLEAR; - REG_D[word2 & 7] = (res >> 32); - REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); - return; - } - m68ki_exception_illegal(); - -#else - - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint src = OPER_AY_AI_32(); - uint dst = REG_D[(word2 >> 12) & 7]; - uint neg = GET_MSB_32(src ^ dst); - uint src1; - uint src2; - uint dst1; - uint dst2; - uint r1; - uint r2; - uint r3; - uint r4; - uint lo; - uint hi; - - FLAG_C = CFLAG_CLEAR; - - if(BIT_B(word2)) /* signed */ - { - if(GET_MSB_32(src)) - src = (uint)MASK_OUT_ABOVE_32(-(sint)src); - if(GET_MSB_32(dst)) - dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst); - } - - src1 = MASK_OUT_ABOVE_16(src); - src2 = src>>16; - dst1 = MASK_OUT_ABOVE_16(dst); - dst2 = dst>>16; - - - r1 = src1 * dst1; - r2 = src1 * dst2; - r3 = src2 * dst1; - r4 = src2 * dst2; - - lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16); - hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16); - - if(BIT_B(word2) && neg) - { - hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0)); - lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo); - } - - if(BIT_A(word2)) - { - REG_D[word2 & 7] = hi; - REG_D[(word2 >> 12) & 7] = lo; - FLAG_N = NFLAG_32(hi); - FLAG_Z = hi | lo; - FLAG_V = VFLAG_CLEAR; - return; - } - - REG_D[(word2 >> 12) & 7] = lo; - FLAG_N = NFLAG_32(lo); - FLAG_Z = lo; - if(BIT_B(word2)) - FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7; - else - FLAG_V = (hi != 0) << 7; - return; - } - m68ki_exception_illegal(); - -#endif -} - - -void m68k_op_mull_32_pi(void) -{ -#if M68K_USE_64_BIT - - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint64 src = OPER_AY_PI_32(); - uint64 dst = REG_D[(word2 >> 12) & 7]; - uint64 res; - - FLAG_C = CFLAG_CLEAR; - - if(BIT_B(word2)) /* signed */ - { - res = (sint64)((sint32)src) * (sint64)((sint32)dst); - if(!BIT_A(word2)) - { - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_N = NFLAG_32(res); - FLAG_V = ((sint64)res != (sint32)res)<<7; - REG_D[(word2 >> 12) & 7] = FLAG_Z; - return; - } - FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); - FLAG_N = NFLAG_64(res); - FLAG_V = VFLAG_CLEAR; - REG_D[word2 & 7] = (res >> 32); - REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); - return; - } - - res = src * dst; - if(!BIT_A(word2)) - { - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_N = NFLAG_32(res); - FLAG_V = (res > 0xffffffff)<<7; - REG_D[(word2 >> 12) & 7] = FLAG_Z; - return; - } - FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); - FLAG_N = NFLAG_64(res); - FLAG_V = VFLAG_CLEAR; - REG_D[word2 & 7] = (res >> 32); - REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); - return; - } - m68ki_exception_illegal(); - -#else - - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint src = OPER_AY_PI_32(); - uint dst = REG_D[(word2 >> 12) & 7]; - uint neg = GET_MSB_32(src ^ dst); - uint src1; - uint src2; - uint dst1; - uint dst2; - uint r1; - uint r2; - uint r3; - uint r4; - uint lo; - uint hi; - - FLAG_C = CFLAG_CLEAR; - - if(BIT_B(word2)) /* signed */ - { - if(GET_MSB_32(src)) - src = (uint)MASK_OUT_ABOVE_32(-(sint)src); - if(GET_MSB_32(dst)) - dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst); - } - - src1 = MASK_OUT_ABOVE_16(src); - src2 = src>>16; - dst1 = MASK_OUT_ABOVE_16(dst); - dst2 = dst>>16; - - - r1 = src1 * dst1; - r2 = src1 * dst2; - r3 = src2 * dst1; - r4 = src2 * dst2; - - lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16); - hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16); - - if(BIT_B(word2) && neg) - { - hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0)); - lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo); - } - - if(BIT_A(word2)) - { - REG_D[word2 & 7] = hi; - REG_D[(word2 >> 12) & 7] = lo; - FLAG_N = NFLAG_32(hi); - FLAG_Z = hi | lo; - FLAG_V = VFLAG_CLEAR; - return; - } - - REG_D[(word2 >> 12) & 7] = lo; - FLAG_N = NFLAG_32(lo); - FLAG_Z = lo; - if(BIT_B(word2)) - FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7; - else - FLAG_V = (hi != 0) << 7; - return; - } - m68ki_exception_illegal(); - -#endif -} - - -void m68k_op_mull_32_pd(void) -{ -#if M68K_USE_64_BIT - - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint64 src = OPER_AY_PD_32(); - uint64 dst = REG_D[(word2 >> 12) & 7]; - uint64 res; - - FLAG_C = CFLAG_CLEAR; - - if(BIT_B(word2)) /* signed */ - { - res = (sint64)((sint32)src) * (sint64)((sint32)dst); - if(!BIT_A(word2)) - { - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_N = NFLAG_32(res); - FLAG_V = ((sint64)res != (sint32)res)<<7; - REG_D[(word2 >> 12) & 7] = FLAG_Z; - return; - } - FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); - FLAG_N = NFLAG_64(res); - FLAG_V = VFLAG_CLEAR; - REG_D[word2 & 7] = (res >> 32); - REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); - return; - } - - res = src * dst; - if(!BIT_A(word2)) - { - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_N = NFLAG_32(res); - FLAG_V = (res > 0xffffffff)<<7; - REG_D[(word2 >> 12) & 7] = FLAG_Z; - return; - } - FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); - FLAG_N = NFLAG_64(res); - FLAG_V = VFLAG_CLEAR; - REG_D[word2 & 7] = (res >> 32); - REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); - return; - } - m68ki_exception_illegal(); - -#else - - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint src = OPER_AY_PD_32(); - uint dst = REG_D[(word2 >> 12) & 7]; - uint neg = GET_MSB_32(src ^ dst); - uint src1; - uint src2; - uint dst1; - uint dst2; - uint r1; - uint r2; - uint r3; - uint r4; - uint lo; - uint hi; - - FLAG_C = CFLAG_CLEAR; - - if(BIT_B(word2)) /* signed */ - { - if(GET_MSB_32(src)) - src = (uint)MASK_OUT_ABOVE_32(-(sint)src); - if(GET_MSB_32(dst)) - dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst); - } - - src1 = MASK_OUT_ABOVE_16(src); - src2 = src>>16; - dst1 = MASK_OUT_ABOVE_16(dst); - dst2 = dst>>16; - - - r1 = src1 * dst1; - r2 = src1 * dst2; - r3 = src2 * dst1; - r4 = src2 * dst2; - - lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16); - hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16); - - if(BIT_B(word2) && neg) - { - hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0)); - lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo); - } - - if(BIT_A(word2)) - { - REG_D[word2 & 7] = hi; - REG_D[(word2 >> 12) & 7] = lo; - FLAG_N = NFLAG_32(hi); - FLAG_Z = hi | lo; - FLAG_V = VFLAG_CLEAR; - return; - } - - REG_D[(word2 >> 12) & 7] = lo; - FLAG_N = NFLAG_32(lo); - FLAG_Z = lo; - if(BIT_B(word2)) - FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7; - else - FLAG_V = (hi != 0) << 7; - return; - } - m68ki_exception_illegal(); - -#endif -} - - -void m68k_op_mull_32_di(void) -{ -#if M68K_USE_64_BIT - - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint64 src = OPER_AY_DI_32(); - uint64 dst = REG_D[(word2 >> 12) & 7]; - uint64 res; - - FLAG_C = CFLAG_CLEAR; - - if(BIT_B(word2)) /* signed */ - { - res = (sint64)((sint32)src) * (sint64)((sint32)dst); - if(!BIT_A(word2)) - { - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_N = NFLAG_32(res); - FLAG_V = ((sint64)res != (sint32)res)<<7; - REG_D[(word2 >> 12) & 7] = FLAG_Z; - return; - } - FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); - FLAG_N = NFLAG_64(res); - FLAG_V = VFLAG_CLEAR; - REG_D[word2 & 7] = (res >> 32); - REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); - return; - } - - res = src * dst; - if(!BIT_A(word2)) - { - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_N = NFLAG_32(res); - FLAG_V = (res > 0xffffffff)<<7; - REG_D[(word2 >> 12) & 7] = FLAG_Z; - return; - } - FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); - FLAG_N = NFLAG_64(res); - FLAG_V = VFLAG_CLEAR; - REG_D[word2 & 7] = (res >> 32); - REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); - return; - } - m68ki_exception_illegal(); - -#else - - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint src = OPER_AY_DI_32(); - uint dst = REG_D[(word2 >> 12) & 7]; - uint neg = GET_MSB_32(src ^ dst); - uint src1; - uint src2; - uint dst1; - uint dst2; - uint r1; - uint r2; - uint r3; - uint r4; - uint lo; - uint hi; - - FLAG_C = CFLAG_CLEAR; - - if(BIT_B(word2)) /* signed */ - { - if(GET_MSB_32(src)) - src = (uint)MASK_OUT_ABOVE_32(-(sint)src); - if(GET_MSB_32(dst)) - dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst); - } - - src1 = MASK_OUT_ABOVE_16(src); - src2 = src>>16; - dst1 = MASK_OUT_ABOVE_16(dst); - dst2 = dst>>16; - - - r1 = src1 * dst1; - r2 = src1 * dst2; - r3 = src2 * dst1; - r4 = src2 * dst2; - - lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16); - hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16); - - if(BIT_B(word2) && neg) - { - hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0)); - lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo); - } - - if(BIT_A(word2)) - { - REG_D[word2 & 7] = hi; - REG_D[(word2 >> 12) & 7] = lo; - FLAG_N = NFLAG_32(hi); - FLAG_Z = hi | lo; - FLAG_V = VFLAG_CLEAR; - return; - } - - REG_D[(word2 >> 12) & 7] = lo; - FLAG_N = NFLAG_32(lo); - FLAG_Z = lo; - if(BIT_B(word2)) - FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7; - else - FLAG_V = (hi != 0) << 7; - return; - } - m68ki_exception_illegal(); - -#endif -} - - -void m68k_op_mull_32_ix(void) -{ -#if M68K_USE_64_BIT - - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint64 src = OPER_AY_IX_32(); - uint64 dst = REG_D[(word2 >> 12) & 7]; - uint64 res; - - FLAG_C = CFLAG_CLEAR; - - if(BIT_B(word2)) /* signed */ - { - res = (sint64)((sint32)src) * (sint64)((sint32)dst); - if(!BIT_A(word2)) - { - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_N = NFLAG_32(res); - FLAG_V = ((sint64)res != (sint32)res)<<7; - REG_D[(word2 >> 12) & 7] = FLAG_Z; - return; - } - FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); - FLAG_N = NFLAG_64(res); - FLAG_V = VFLAG_CLEAR; - REG_D[word2 & 7] = (res >> 32); - REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); - return; - } - - res = src * dst; - if(!BIT_A(word2)) - { - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_N = NFLAG_32(res); - FLAG_V = (res > 0xffffffff)<<7; - REG_D[(word2 >> 12) & 7] = FLAG_Z; - return; - } - FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); - FLAG_N = NFLAG_64(res); - FLAG_V = VFLAG_CLEAR; - REG_D[word2 & 7] = (res >> 32); - REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); - return; - } - m68ki_exception_illegal(); - -#else - - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint src = OPER_AY_IX_32(); - uint dst = REG_D[(word2 >> 12) & 7]; - uint neg = GET_MSB_32(src ^ dst); - uint src1; - uint src2; - uint dst1; - uint dst2; - uint r1; - uint r2; - uint r3; - uint r4; - uint lo; - uint hi; - - FLAG_C = CFLAG_CLEAR; - - if(BIT_B(word2)) /* signed */ - { - if(GET_MSB_32(src)) - src = (uint)MASK_OUT_ABOVE_32(-(sint)src); - if(GET_MSB_32(dst)) - dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst); - } - - src1 = MASK_OUT_ABOVE_16(src); - src2 = src>>16; - dst1 = MASK_OUT_ABOVE_16(dst); - dst2 = dst>>16; - - - r1 = src1 * dst1; - r2 = src1 * dst2; - r3 = src2 * dst1; - r4 = src2 * dst2; - - lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16); - hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16); - - if(BIT_B(word2) && neg) - { - hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0)); - lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo); - } - - if(BIT_A(word2)) - { - REG_D[word2 & 7] = hi; - REG_D[(word2 >> 12) & 7] = lo; - FLAG_N = NFLAG_32(hi); - FLAG_Z = hi | lo; - FLAG_V = VFLAG_CLEAR; - return; - } - - REG_D[(word2 >> 12) & 7] = lo; - FLAG_N = NFLAG_32(lo); - FLAG_Z = lo; - if(BIT_B(word2)) - FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7; - else - FLAG_V = (hi != 0) << 7; - return; - } - m68ki_exception_illegal(); - -#endif -} - - -void m68k_op_mull_32_aw(void) -{ -#if M68K_USE_64_BIT - - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint64 src = OPER_AW_32(); - uint64 dst = REG_D[(word2 >> 12) & 7]; - uint64 res; - - FLAG_C = CFLAG_CLEAR; - - if(BIT_B(word2)) /* signed */ - { - res = (sint64)((sint32)src) * (sint64)((sint32)dst); - if(!BIT_A(word2)) - { - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_N = NFLAG_32(res); - FLAG_V = ((sint64)res != (sint32)res)<<7; - REG_D[(word2 >> 12) & 7] = FLAG_Z; - return; - } - FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); - FLAG_N = NFLAG_64(res); - FLAG_V = VFLAG_CLEAR; - REG_D[word2 & 7] = (res >> 32); - REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); - return; - } - - res = src * dst; - if(!BIT_A(word2)) - { - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_N = NFLAG_32(res); - FLAG_V = (res > 0xffffffff)<<7; - REG_D[(word2 >> 12) & 7] = FLAG_Z; - return; - } - FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); - FLAG_N = NFLAG_64(res); - FLAG_V = VFLAG_CLEAR; - REG_D[word2 & 7] = (res >> 32); - REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); - return; - } - m68ki_exception_illegal(); - -#else - - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint src = OPER_AW_32(); - uint dst = REG_D[(word2 >> 12) & 7]; - uint neg = GET_MSB_32(src ^ dst); - uint src1; - uint src2; - uint dst1; - uint dst2; - uint r1; - uint r2; - uint r3; - uint r4; - uint lo; - uint hi; - - FLAG_C = CFLAG_CLEAR; - - if(BIT_B(word2)) /* signed */ - { - if(GET_MSB_32(src)) - src = (uint)MASK_OUT_ABOVE_32(-(sint)src); - if(GET_MSB_32(dst)) - dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst); - } - - src1 = MASK_OUT_ABOVE_16(src); - src2 = src>>16; - dst1 = MASK_OUT_ABOVE_16(dst); - dst2 = dst>>16; - - - r1 = src1 * dst1; - r2 = src1 * dst2; - r3 = src2 * dst1; - r4 = src2 * dst2; - - lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16); - hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16); - - if(BIT_B(word2) && neg) - { - hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0)); - lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo); - } - - if(BIT_A(word2)) - { - REG_D[word2 & 7] = hi; - REG_D[(word2 >> 12) & 7] = lo; - FLAG_N = NFLAG_32(hi); - FLAG_Z = hi | lo; - FLAG_V = VFLAG_CLEAR; - return; - } - - REG_D[(word2 >> 12) & 7] = lo; - FLAG_N = NFLAG_32(lo); - FLAG_Z = lo; - if(BIT_B(word2)) - FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7; - else - FLAG_V = (hi != 0) << 7; - return; - } - m68ki_exception_illegal(); - -#endif -} - - -void m68k_op_mull_32_al(void) -{ -#if M68K_USE_64_BIT - - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint64 src = OPER_AL_32(); - uint64 dst = REG_D[(word2 >> 12) & 7]; - uint64 res; - - FLAG_C = CFLAG_CLEAR; - - if(BIT_B(word2)) /* signed */ - { - res = (sint64)((sint32)src) * (sint64)((sint32)dst); - if(!BIT_A(word2)) - { - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_N = NFLAG_32(res); - FLAG_V = ((sint64)res != (sint32)res)<<7; - REG_D[(word2 >> 12) & 7] = FLAG_Z; - return; - } - FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); - FLAG_N = NFLAG_64(res); - FLAG_V = VFLAG_CLEAR; - REG_D[word2 & 7] = (res >> 32); - REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); - return; - } - - res = src * dst; - if(!BIT_A(word2)) - { - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_N = NFLAG_32(res); - FLAG_V = (res > 0xffffffff)<<7; - REG_D[(word2 >> 12) & 7] = FLAG_Z; - return; - } - FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); - FLAG_N = NFLAG_64(res); - FLAG_V = VFLAG_CLEAR; - REG_D[word2 & 7] = (res >> 32); - REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); - return; - } - m68ki_exception_illegal(); - -#else - - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint src = OPER_AL_32(); - uint dst = REG_D[(word2 >> 12) & 7]; - uint neg = GET_MSB_32(src ^ dst); - uint src1; - uint src2; - uint dst1; - uint dst2; - uint r1; - uint r2; - uint r3; - uint r4; - uint lo; - uint hi; - - FLAG_C = CFLAG_CLEAR; - - if(BIT_B(word2)) /* signed */ - { - if(GET_MSB_32(src)) - src = (uint)MASK_OUT_ABOVE_32(-(sint)src); - if(GET_MSB_32(dst)) - dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst); - } - - src1 = MASK_OUT_ABOVE_16(src); - src2 = src>>16; - dst1 = MASK_OUT_ABOVE_16(dst); - dst2 = dst>>16; - - - r1 = src1 * dst1; - r2 = src1 * dst2; - r3 = src2 * dst1; - r4 = src2 * dst2; - - lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16); - hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16); - - if(BIT_B(word2) && neg) - { - hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0)); - lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo); - } - - if(BIT_A(word2)) - { - REG_D[word2 & 7] = hi; - REG_D[(word2 >> 12) & 7] = lo; - FLAG_N = NFLAG_32(hi); - FLAG_Z = hi | lo; - FLAG_V = VFLAG_CLEAR; - return; - } - - REG_D[(word2 >> 12) & 7] = lo; - FLAG_N = NFLAG_32(lo); - FLAG_Z = lo; - if(BIT_B(word2)) - FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7; - else - FLAG_V = (hi != 0) << 7; - return; - } - m68ki_exception_illegal(); - -#endif -} - - -void m68k_op_mull_32_pcdi(void) -{ -#if M68K_USE_64_BIT - - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint64 src = OPER_PCDI_32(); - uint64 dst = REG_D[(word2 >> 12) & 7]; - uint64 res; - - FLAG_C = CFLAG_CLEAR; - - if(BIT_B(word2)) /* signed */ - { - res = (sint64)((sint32)src) * (sint64)((sint32)dst); - if(!BIT_A(word2)) - { - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_N = NFLAG_32(res); - FLAG_V = ((sint64)res != (sint32)res)<<7; - REG_D[(word2 >> 12) & 7] = FLAG_Z; - return; - } - FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); - FLAG_N = NFLAG_64(res); - FLAG_V = VFLAG_CLEAR; - REG_D[word2 & 7] = (res >> 32); - REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); - return; - } - - res = src * dst; - if(!BIT_A(word2)) - { - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_N = NFLAG_32(res); - FLAG_V = (res > 0xffffffff)<<7; - REG_D[(word2 >> 12) & 7] = FLAG_Z; - return; - } - FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); - FLAG_N = NFLAG_64(res); - FLAG_V = VFLAG_CLEAR; - REG_D[word2 & 7] = (res >> 32); - REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); - return; - } - m68ki_exception_illegal(); - -#else - - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint src = OPER_PCDI_32(); - uint dst = REG_D[(word2 >> 12) & 7]; - uint neg = GET_MSB_32(src ^ dst); - uint src1; - uint src2; - uint dst1; - uint dst2; - uint r1; - uint r2; - uint r3; - uint r4; - uint lo; - uint hi; - - FLAG_C = CFLAG_CLEAR; - - if(BIT_B(word2)) /* signed */ - { - if(GET_MSB_32(src)) - src = (uint)MASK_OUT_ABOVE_32(-(sint)src); - if(GET_MSB_32(dst)) - dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst); - } - - src1 = MASK_OUT_ABOVE_16(src); - src2 = src>>16; - dst1 = MASK_OUT_ABOVE_16(dst); - dst2 = dst>>16; - - - r1 = src1 * dst1; - r2 = src1 * dst2; - r3 = src2 * dst1; - r4 = src2 * dst2; - - lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16); - hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16); - - if(BIT_B(word2) && neg) - { - hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0)); - lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo); - } - - if(BIT_A(word2)) - { - REG_D[word2 & 7] = hi; - REG_D[(word2 >> 12) & 7] = lo; - FLAG_N = NFLAG_32(hi); - FLAG_Z = hi | lo; - FLAG_V = VFLAG_CLEAR; - return; - } - - REG_D[(word2 >> 12) & 7] = lo; - FLAG_N = NFLAG_32(lo); - FLAG_Z = lo; - if(BIT_B(word2)) - FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7; - else - FLAG_V = (hi != 0) << 7; - return; - } - m68ki_exception_illegal(); - -#endif -} - - -void m68k_op_mull_32_pcix(void) -{ -#if M68K_USE_64_BIT - - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint64 src = OPER_PCIX_32(); - uint64 dst = REG_D[(word2 >> 12) & 7]; - uint64 res; - - FLAG_C = CFLAG_CLEAR; - - if(BIT_B(word2)) /* signed */ - { - res = (sint64)((sint32)src) * (sint64)((sint32)dst); - if(!BIT_A(word2)) - { - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_N = NFLAG_32(res); - FLAG_V = ((sint64)res != (sint32)res)<<7; - REG_D[(word2 >> 12) & 7] = FLAG_Z; - return; - } - FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); - FLAG_N = NFLAG_64(res); - FLAG_V = VFLAG_CLEAR; - REG_D[word2 & 7] = (res >> 32); - REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); - return; - } - - res = src * dst; - if(!BIT_A(word2)) - { - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_N = NFLAG_32(res); - FLAG_V = (res > 0xffffffff)<<7; - REG_D[(word2 >> 12) & 7] = FLAG_Z; - return; - } - FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); - FLAG_N = NFLAG_64(res); - FLAG_V = VFLAG_CLEAR; - REG_D[word2 & 7] = (res >> 32); - REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); - return; - } - m68ki_exception_illegal(); - -#else - - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint src = OPER_PCIX_32(); - uint dst = REG_D[(word2 >> 12) & 7]; - uint neg = GET_MSB_32(src ^ dst); - uint src1; - uint src2; - uint dst1; - uint dst2; - uint r1; - uint r2; - uint r3; - uint r4; - uint lo; - uint hi; - - FLAG_C = CFLAG_CLEAR; - - if(BIT_B(word2)) /* signed */ - { - if(GET_MSB_32(src)) - src = (uint)MASK_OUT_ABOVE_32(-(sint)src); - if(GET_MSB_32(dst)) - dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst); - } - - src1 = MASK_OUT_ABOVE_16(src); - src2 = src>>16; - dst1 = MASK_OUT_ABOVE_16(dst); - dst2 = dst>>16; - - - r1 = src1 * dst1; - r2 = src1 * dst2; - r3 = src2 * dst1; - r4 = src2 * dst2; - - lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16); - hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16); - - if(BIT_B(word2) && neg) - { - hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0)); - lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo); - } - - if(BIT_A(word2)) - { - REG_D[word2 & 7] = hi; - REG_D[(word2 >> 12) & 7] = lo; - FLAG_N = NFLAG_32(hi); - FLAG_Z = hi | lo; - FLAG_V = VFLAG_CLEAR; - return; - } - - REG_D[(word2 >> 12) & 7] = lo; - FLAG_N = NFLAG_32(lo); - FLAG_Z = lo; - if(BIT_B(word2)) - FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7; - else - FLAG_V = (hi != 0) << 7; - return; - } - m68ki_exception_illegal(); - -#endif -} - - -void m68k_op_mull_32_i(void) -{ -#if M68K_USE_64_BIT - - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint64 src = OPER_I_32(); - uint64 dst = REG_D[(word2 >> 12) & 7]; - uint64 res; - - FLAG_C = CFLAG_CLEAR; - - if(BIT_B(word2)) /* signed */ - { - res = (sint64)((sint32)src) * (sint64)((sint32)dst); - if(!BIT_A(word2)) - { - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_N = NFLAG_32(res); - FLAG_V = ((sint64)res != (sint32)res)<<7; - REG_D[(word2 >> 12) & 7] = FLAG_Z; - return; - } - FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); - FLAG_N = NFLAG_64(res); - FLAG_V = VFLAG_CLEAR; - REG_D[word2 & 7] = (res >> 32); - REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); - return; - } - - res = src * dst; - if(!BIT_A(word2)) - { - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_N = NFLAG_32(res); - FLAG_V = (res > 0xffffffff)<<7; - REG_D[(word2 >> 12) & 7] = FLAG_Z; - return; - } - FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); - FLAG_N = NFLAG_64(res); - FLAG_V = VFLAG_CLEAR; - REG_D[word2 & 7] = (res >> 32); - REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); - return; - } - m68ki_exception_illegal(); - -#else - - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint word2 = OPER_I_16(); - uint src = OPER_I_32(); - uint dst = REG_D[(word2 >> 12) & 7]; - uint neg = GET_MSB_32(src ^ dst); - uint src1; - uint src2; - uint dst1; - uint dst2; - uint r1; - uint r2; - uint r3; - uint r4; - uint lo; - uint hi; - - FLAG_C = CFLAG_CLEAR; - - if(BIT_B(word2)) /* signed */ - { - if(GET_MSB_32(src)) - src = (uint)MASK_OUT_ABOVE_32(-(sint)src); - if(GET_MSB_32(dst)) - dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst); - } - - src1 = MASK_OUT_ABOVE_16(src); - src2 = src>>16; - dst1 = MASK_OUT_ABOVE_16(dst); - dst2 = dst>>16; - - - r1 = src1 * dst1; - r2 = src1 * dst2; - r3 = src2 * dst1; - r4 = src2 * dst2; - - lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16); - hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16); - - if(BIT_B(word2) && neg) - { - hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0)); - lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo); - } - - if(BIT_A(word2)) - { - REG_D[word2 & 7] = hi; - REG_D[(word2 >> 12) & 7] = lo; - FLAG_N = NFLAG_32(hi); - FLAG_Z = hi | lo; - FLAG_V = VFLAG_CLEAR; - return; - } - - REG_D[(word2 >> 12) & 7] = lo; - FLAG_N = NFLAG_32(lo); - FLAG_Z = lo; - if(BIT_B(word2)) - FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7; - else - FLAG_V = (hi != 0) << 7; - return; - } - m68ki_exception_illegal(); - -#endif -} - - -/* ======================================================================== */ -/* ============================== END OF FILE ============================= */ -/* ======================================================================== */ - - diff --git a/Frameworks/AudioOverload/aosdk/eng_ssf/m68kopnz.c b/Frameworks/AudioOverload/aosdk/eng_ssf/m68kopnz.c deleted file mode 100644 index 2c26ce3de..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_ssf/m68kopnz.c +++ /dev/null @@ -1,8780 +0,0 @@ -#include "m68kcpu.h" - -/* ======================================================================== */ -/* ========================= INSTRUCTION HANDLERS ========================= */ -/* ======================================================================== */ - - -void m68k_op_nbcd_8_d(void) -{ - uint* r_dst = &DY; - uint dst = *r_dst; - uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1()); - - if(res != 0x9a) - { - FLAG_V = ~res; /* Undefined V behavior */ - - if((res & 0x0f) == 0xa) - res = (res & 0xf0) + 0x10; - - res = MASK_OUT_ABOVE_8(res); - - FLAG_V &= res; /* Undefined V behavior part II */ - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; - - FLAG_Z |= res; - FLAG_C = CFLAG_SET; - FLAG_X = XFLAG_SET; - } - else - { - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - FLAG_X = XFLAG_CLEAR; - } - FLAG_N = NFLAG_8(res); /* Undefined N behavior */ -} - - -void m68k_op_nbcd_8_ai(void) -{ - uint ea = EA_AY_AI_8(); - uint dst = m68ki_read_8(ea); - uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1()); - - if(res != 0x9a) - { - FLAG_V = ~res; /* Undefined V behavior */ - - if((res & 0x0f) == 0xa) - res = (res & 0xf0) + 0x10; - - res = MASK_OUT_ABOVE_8(res); - - FLAG_V &= res; /* Undefined V behavior part II */ - - m68ki_write_8(ea, MASK_OUT_ABOVE_8(res)); - - FLAG_Z |= res; - FLAG_C = CFLAG_SET; - FLAG_X = XFLAG_SET; - } - else - { - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - FLAG_X = XFLAG_CLEAR; - } - FLAG_N = NFLAG_8(res); /* Undefined N behavior */ -} - - -void m68k_op_nbcd_8_pi(void) -{ - uint ea = EA_AY_PI_8(); - uint dst = m68ki_read_8(ea); - uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1()); - - if(res != 0x9a) - { - FLAG_V = ~res; /* Undefined V behavior */ - - if((res & 0x0f) == 0xa) - res = (res & 0xf0) + 0x10; - - res = MASK_OUT_ABOVE_8(res); - - FLAG_V &= res; /* Undefined V behavior part II */ - - m68ki_write_8(ea, MASK_OUT_ABOVE_8(res)); - - FLAG_Z |= res; - FLAG_C = CFLAG_SET; - FLAG_X = XFLAG_SET; - } - else - { - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - FLAG_X = XFLAG_CLEAR; - } - FLAG_N = NFLAG_8(res); /* Undefined N behavior */ -} - - -void m68k_op_nbcd_8_pi7(void) -{ - uint ea = EA_A7_PI_8(); - uint dst = m68ki_read_8(ea); - uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1()); - - if(res != 0x9a) - { - FLAG_V = ~res; /* Undefined V behavior */ - - if((res & 0x0f) == 0xa) - res = (res & 0xf0) + 0x10; - - res = MASK_OUT_ABOVE_8(res); - - FLAG_V &= res; /* Undefined V behavior part II */ - - m68ki_write_8(ea, MASK_OUT_ABOVE_8(res)); - - FLAG_Z |= res; - FLAG_C = CFLAG_SET; - FLAG_X = XFLAG_SET; - } - else - { - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - FLAG_X = XFLAG_CLEAR; - } - FLAG_N = NFLAG_8(res); /* Undefined N behavior */ -} - - -void m68k_op_nbcd_8_pd(void) -{ - uint ea = EA_AY_PD_8(); - uint dst = m68ki_read_8(ea); - uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1()); - - if(res != 0x9a) - { - FLAG_V = ~res; /* Undefined V behavior */ - - if((res & 0x0f) == 0xa) - res = (res & 0xf0) + 0x10; - - res = MASK_OUT_ABOVE_8(res); - - FLAG_V &= res; /* Undefined V behavior part II */ - - m68ki_write_8(ea, MASK_OUT_ABOVE_8(res)); - - FLAG_Z |= res; - FLAG_C = CFLAG_SET; - FLAG_X = XFLAG_SET; - } - else - { - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - FLAG_X = XFLAG_CLEAR; - } - FLAG_N = NFLAG_8(res); /* Undefined N behavior */ -} - - -void m68k_op_nbcd_8_pd7(void) -{ - uint ea = EA_A7_PD_8(); - uint dst = m68ki_read_8(ea); - uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1()); - - if(res != 0x9a) - { - FLAG_V = ~res; /* Undefined V behavior */ - - if((res & 0x0f) == 0xa) - res = (res & 0xf0) + 0x10; - - res = MASK_OUT_ABOVE_8(res); - - FLAG_V &= res; /* Undefined V behavior part II */ - - m68ki_write_8(ea, MASK_OUT_ABOVE_8(res)); - - FLAG_Z |= res; - FLAG_C = CFLAG_SET; - FLAG_X = XFLAG_SET; - } - else - { - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - FLAG_X = XFLAG_CLEAR; - } - FLAG_N = NFLAG_8(res); /* Undefined N behavior */ -} - - -void m68k_op_nbcd_8_di(void) -{ - uint ea = EA_AY_DI_8(); - uint dst = m68ki_read_8(ea); - uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1()); - - if(res != 0x9a) - { - FLAG_V = ~res; /* Undefined V behavior */ - - if((res & 0x0f) == 0xa) - res = (res & 0xf0) + 0x10; - - res = MASK_OUT_ABOVE_8(res); - - FLAG_V &= res; /* Undefined V behavior part II */ - - m68ki_write_8(ea, MASK_OUT_ABOVE_8(res)); - - FLAG_Z |= res; - FLAG_C = CFLAG_SET; - FLAG_X = XFLAG_SET; - } - else - { - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - FLAG_X = XFLAG_CLEAR; - } - FLAG_N = NFLAG_8(res); /* Undefined N behavior */ -} - - -void m68k_op_nbcd_8_ix(void) -{ - uint ea = EA_AY_IX_8(); - uint dst = m68ki_read_8(ea); - uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1()); - - if(res != 0x9a) - { - FLAG_V = ~res; /* Undefined V behavior */ - - if((res & 0x0f) == 0xa) - res = (res & 0xf0) + 0x10; - - res = MASK_OUT_ABOVE_8(res); - - FLAG_V &= res; /* Undefined V behavior part II */ - - m68ki_write_8(ea, MASK_OUT_ABOVE_8(res)); - - FLAG_Z |= res; - FLAG_C = CFLAG_SET; - FLAG_X = XFLAG_SET; - } - else - { - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - FLAG_X = XFLAG_CLEAR; - } - FLAG_N = NFLAG_8(res); /* Undefined N behavior */ -} - - -void m68k_op_nbcd_8_aw(void) -{ - uint ea = EA_AW_8(); - uint dst = m68ki_read_8(ea); - uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1()); - - if(res != 0x9a) - { - FLAG_V = ~res; /* Undefined V behavior */ - - if((res & 0x0f) == 0xa) - res = (res & 0xf0) + 0x10; - - res = MASK_OUT_ABOVE_8(res); - - FLAG_V &= res; /* Undefined V behavior part II */ - - m68ki_write_8(ea, MASK_OUT_ABOVE_8(res)); - - FLAG_Z |= res; - FLAG_C = CFLAG_SET; - FLAG_X = XFLAG_SET; - } - else - { - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - FLAG_X = XFLAG_CLEAR; - } - FLAG_N = NFLAG_8(res); /* Undefined N behavior */ -} - - -void m68k_op_nbcd_8_al(void) -{ - uint ea = EA_AL_8(); - uint dst = m68ki_read_8(ea); - uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1()); - - if(res != 0x9a) - { - FLAG_V = ~res; /* Undefined V behavior */ - - if((res & 0x0f) == 0xa) - res = (res & 0xf0) + 0x10; - - res = MASK_OUT_ABOVE_8(res); - - FLAG_V &= res; /* Undefined V behavior part II */ - - m68ki_write_8(ea, MASK_OUT_ABOVE_8(res)); - - FLAG_Z |= res; - FLAG_C = CFLAG_SET; - FLAG_X = XFLAG_SET; - } - else - { - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - FLAG_X = XFLAG_CLEAR; - } - FLAG_N = NFLAG_8(res); /* Undefined N behavior */ -} - - -void m68k_op_neg_8_d(void) -{ - uint* r_dst = &DY; - uint res = 0 - MASK_OUT_ABOVE_8(*r_dst); - - FLAG_N = NFLAG_8(res); - FLAG_C = FLAG_X = CFLAG_8(res); - FLAG_V = *r_dst & res; - FLAG_Z = MASK_OUT_ABOVE_8(res); - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; -} - - -void m68k_op_neg_8_ai(void) -{ - uint ea = EA_AY_AI_8(); - uint src = m68ki_read_8(ea); - uint res = 0 - src; - - FLAG_N = NFLAG_8(res); - FLAG_C = FLAG_X = CFLAG_8(res); - FLAG_V = src & res; - FLAG_Z = MASK_OUT_ABOVE_8(res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_neg_8_pi(void) -{ - uint ea = EA_AY_PI_8(); - uint src = m68ki_read_8(ea); - uint res = 0 - src; - - FLAG_N = NFLAG_8(res); - FLAG_C = FLAG_X = CFLAG_8(res); - FLAG_V = src & res; - FLAG_Z = MASK_OUT_ABOVE_8(res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_neg_8_pi7(void) -{ - uint ea = EA_A7_PI_8(); - uint src = m68ki_read_8(ea); - uint res = 0 - src; - - FLAG_N = NFLAG_8(res); - FLAG_C = FLAG_X = CFLAG_8(res); - FLAG_V = src & res; - FLAG_Z = MASK_OUT_ABOVE_8(res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_neg_8_pd(void) -{ - uint ea = EA_AY_PD_8(); - uint src = m68ki_read_8(ea); - uint res = 0 - src; - - FLAG_N = NFLAG_8(res); - FLAG_C = FLAG_X = CFLAG_8(res); - FLAG_V = src & res; - FLAG_Z = MASK_OUT_ABOVE_8(res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_neg_8_pd7(void) -{ - uint ea = EA_A7_PD_8(); - uint src = m68ki_read_8(ea); - uint res = 0 - src; - - FLAG_N = NFLAG_8(res); - FLAG_C = FLAG_X = CFLAG_8(res); - FLAG_V = src & res; - FLAG_Z = MASK_OUT_ABOVE_8(res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_neg_8_di(void) -{ - uint ea = EA_AY_DI_8(); - uint src = m68ki_read_8(ea); - uint res = 0 - src; - - FLAG_N = NFLAG_8(res); - FLAG_C = FLAG_X = CFLAG_8(res); - FLAG_V = src & res; - FLAG_Z = MASK_OUT_ABOVE_8(res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_neg_8_ix(void) -{ - uint ea = EA_AY_IX_8(); - uint src = m68ki_read_8(ea); - uint res = 0 - src; - - FLAG_N = NFLAG_8(res); - FLAG_C = FLAG_X = CFLAG_8(res); - FLAG_V = src & res; - FLAG_Z = MASK_OUT_ABOVE_8(res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_neg_8_aw(void) -{ - uint ea = EA_AW_8(); - uint src = m68ki_read_8(ea); - uint res = 0 - src; - - FLAG_N = NFLAG_8(res); - FLAG_C = FLAG_X = CFLAG_8(res); - FLAG_V = src & res; - FLAG_Z = MASK_OUT_ABOVE_8(res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_neg_8_al(void) -{ - uint ea = EA_AL_8(); - uint src = m68ki_read_8(ea); - uint res = 0 - src; - - FLAG_N = NFLAG_8(res); - FLAG_C = FLAG_X = CFLAG_8(res); - FLAG_V = src & res; - FLAG_Z = MASK_OUT_ABOVE_8(res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_neg_16_d(void) -{ - uint* r_dst = &DY; - uint res = 0 - MASK_OUT_ABOVE_16(*r_dst); - - FLAG_N = NFLAG_16(res); - FLAG_C = FLAG_X = CFLAG_16(res); - FLAG_V = (*r_dst & res)>>8; - FLAG_Z = MASK_OUT_ABOVE_16(res); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; -} - - -void m68k_op_neg_16_ai(void) -{ - uint ea = EA_AY_AI_16(); - uint src = m68ki_read_16(ea); - uint res = 0 - src; - - FLAG_N = NFLAG_16(res); - FLAG_C = FLAG_X = CFLAG_16(res); - FLAG_V = (src & res)>>8; - FLAG_Z = MASK_OUT_ABOVE_16(res); - - m68ki_write_16(ea, FLAG_Z); -} - - -void m68k_op_neg_16_pi(void) -{ - uint ea = EA_AY_PI_16(); - uint src = m68ki_read_16(ea); - uint res = 0 - src; - - FLAG_N = NFLAG_16(res); - FLAG_C = FLAG_X = CFLAG_16(res); - FLAG_V = (src & res)>>8; - FLAG_Z = MASK_OUT_ABOVE_16(res); - - m68ki_write_16(ea, FLAG_Z); -} - - -void m68k_op_neg_16_pd(void) -{ - uint ea = EA_AY_PD_16(); - uint src = m68ki_read_16(ea); - uint res = 0 - src; - - FLAG_N = NFLAG_16(res); - FLAG_C = FLAG_X = CFLAG_16(res); - FLAG_V = (src & res)>>8; - FLAG_Z = MASK_OUT_ABOVE_16(res); - - m68ki_write_16(ea, FLAG_Z); -} - - -void m68k_op_neg_16_di(void) -{ - uint ea = EA_AY_DI_16(); - uint src = m68ki_read_16(ea); - uint res = 0 - src; - - FLAG_N = NFLAG_16(res); - FLAG_C = FLAG_X = CFLAG_16(res); - FLAG_V = (src & res)>>8; - FLAG_Z = MASK_OUT_ABOVE_16(res); - - m68ki_write_16(ea, FLAG_Z); -} - - -void m68k_op_neg_16_ix(void) -{ - uint ea = EA_AY_IX_16(); - uint src = m68ki_read_16(ea); - uint res = 0 - src; - - FLAG_N = NFLAG_16(res); - FLAG_C = FLAG_X = CFLAG_16(res); - FLAG_V = (src & res)>>8; - FLAG_Z = MASK_OUT_ABOVE_16(res); - - m68ki_write_16(ea, FLAG_Z); -} - - -void m68k_op_neg_16_aw(void) -{ - uint ea = EA_AW_16(); - uint src = m68ki_read_16(ea); - uint res = 0 - src; - - FLAG_N = NFLAG_16(res); - FLAG_C = FLAG_X = CFLAG_16(res); - FLAG_V = (src & res)>>8; - FLAG_Z = MASK_OUT_ABOVE_16(res); - - m68ki_write_16(ea, FLAG_Z); -} - - -void m68k_op_neg_16_al(void) -{ - uint ea = EA_AL_16(); - uint src = m68ki_read_16(ea); - uint res = 0 - src; - - FLAG_N = NFLAG_16(res); - FLAG_C = FLAG_X = CFLAG_16(res); - FLAG_V = (src & res)>>8; - FLAG_Z = MASK_OUT_ABOVE_16(res); - - m68ki_write_16(ea, FLAG_Z); -} - - -void m68k_op_neg_32_d(void) -{ - uint* r_dst = &DY; - uint res = 0 - *r_dst; - - FLAG_N = NFLAG_32(res); - FLAG_C = FLAG_X = CFLAG_SUB_32(*r_dst, 0, res); - FLAG_V = (*r_dst & res)>>24; - FLAG_Z = MASK_OUT_ABOVE_32(res); - - *r_dst = FLAG_Z; -} - - -void m68k_op_neg_32_ai(void) -{ - uint ea = EA_AY_AI_32(); - uint src = m68ki_read_32(ea); - uint res = 0 - src; - - FLAG_N = NFLAG_32(res); - FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res); - FLAG_V = (src & res)>>24; - FLAG_Z = MASK_OUT_ABOVE_32(res); - - m68ki_write_32(ea, FLAG_Z); -} - - -void m68k_op_neg_32_pi(void) -{ - uint ea = EA_AY_PI_32(); - uint src = m68ki_read_32(ea); - uint res = 0 - src; - - FLAG_N = NFLAG_32(res); - FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res); - FLAG_V = (src & res)>>24; - FLAG_Z = MASK_OUT_ABOVE_32(res); - - m68ki_write_32(ea, FLAG_Z); -} - - -void m68k_op_neg_32_pd(void) -{ - uint ea = EA_AY_PD_32(); - uint src = m68ki_read_32(ea); - uint res = 0 - src; - - FLAG_N = NFLAG_32(res); - FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res); - FLAG_V = (src & res)>>24; - FLAG_Z = MASK_OUT_ABOVE_32(res); - - m68ki_write_32(ea, FLAG_Z); -} - - -void m68k_op_neg_32_di(void) -{ - uint ea = EA_AY_DI_32(); - uint src = m68ki_read_32(ea); - uint res = 0 - src; - - FLAG_N = NFLAG_32(res); - FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res); - FLAG_V = (src & res)>>24; - FLAG_Z = MASK_OUT_ABOVE_32(res); - - m68ki_write_32(ea, FLAG_Z); -} - - -void m68k_op_neg_32_ix(void) -{ - uint ea = EA_AY_IX_32(); - uint src = m68ki_read_32(ea); - uint res = 0 - src; - - FLAG_N = NFLAG_32(res); - FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res); - FLAG_V = (src & res)>>24; - FLAG_Z = MASK_OUT_ABOVE_32(res); - - m68ki_write_32(ea, FLAG_Z); -} - - -void m68k_op_neg_32_aw(void) -{ - uint ea = EA_AW_32(); - uint src = m68ki_read_32(ea); - uint res = 0 - src; - - FLAG_N = NFLAG_32(res); - FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res); - FLAG_V = (src & res)>>24; - FLAG_Z = MASK_OUT_ABOVE_32(res); - - m68ki_write_32(ea, FLAG_Z); -} - - -void m68k_op_neg_32_al(void) -{ - uint ea = EA_AL_32(); - uint src = m68ki_read_32(ea); - uint res = 0 - src; - - FLAG_N = NFLAG_32(res); - FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res); - FLAG_V = (src & res)>>24; - FLAG_Z = MASK_OUT_ABOVE_32(res); - - m68ki_write_32(ea, FLAG_Z); -} - - -void m68k_op_negx_8_d(void) -{ - uint* r_dst = &DY; - uint res = 0 - MASK_OUT_ABOVE_8(*r_dst) - XFLAG_AS_1(); - - FLAG_N = NFLAG_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = *r_dst & res; - - res = MASK_OUT_ABOVE_8(res); - FLAG_Z |= res; - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; -} - - -void m68k_op_negx_8_ai(void) -{ - uint ea = EA_AY_AI_8(); - uint src = m68ki_read_8(ea); - uint res = 0 - src - XFLAG_AS_1(); - - FLAG_N = NFLAG_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = src & res; - - res = MASK_OUT_ABOVE_8(res); - FLAG_Z |= res; - - m68ki_write_8(ea, res); -} - - -void m68k_op_negx_8_pi(void) -{ - uint ea = EA_AY_PI_8(); - uint src = m68ki_read_8(ea); - uint res = 0 - src - XFLAG_AS_1(); - - FLAG_N = NFLAG_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = src & res; - - res = MASK_OUT_ABOVE_8(res); - FLAG_Z |= res; - - m68ki_write_8(ea, res); -} - - -void m68k_op_negx_8_pi7(void) -{ - uint ea = EA_A7_PI_8(); - uint src = m68ki_read_8(ea); - uint res = 0 - src - XFLAG_AS_1(); - - FLAG_N = NFLAG_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = src & res; - - res = MASK_OUT_ABOVE_8(res); - FLAG_Z |= res; - - m68ki_write_8(ea, res); -} - - -void m68k_op_negx_8_pd(void) -{ - uint ea = EA_AY_PD_8(); - uint src = m68ki_read_8(ea); - uint res = 0 - src - XFLAG_AS_1(); - - FLAG_N = NFLAG_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = src & res; - - res = MASK_OUT_ABOVE_8(res); - FLAG_Z |= res; - - m68ki_write_8(ea, res); -} - - -void m68k_op_negx_8_pd7(void) -{ - uint ea = EA_A7_PD_8(); - uint src = m68ki_read_8(ea); - uint res = 0 - src - XFLAG_AS_1(); - - FLAG_N = NFLAG_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = src & res; - - res = MASK_OUT_ABOVE_8(res); - FLAG_Z |= res; - - m68ki_write_8(ea, res); -} - - -void m68k_op_negx_8_di(void) -{ - uint ea = EA_AY_DI_8(); - uint src = m68ki_read_8(ea); - uint res = 0 - src - XFLAG_AS_1(); - - FLAG_N = NFLAG_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = src & res; - - res = MASK_OUT_ABOVE_8(res); - FLAG_Z |= res; - - m68ki_write_8(ea, res); -} - - -void m68k_op_negx_8_ix(void) -{ - uint ea = EA_AY_IX_8(); - uint src = m68ki_read_8(ea); - uint res = 0 - src - XFLAG_AS_1(); - - FLAG_N = NFLAG_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = src & res; - - res = MASK_OUT_ABOVE_8(res); - FLAG_Z |= res; - - m68ki_write_8(ea, res); -} - - -void m68k_op_negx_8_aw(void) -{ - uint ea = EA_AW_8(); - uint src = m68ki_read_8(ea); - uint res = 0 - src - XFLAG_AS_1(); - - FLAG_N = NFLAG_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = src & res; - - res = MASK_OUT_ABOVE_8(res); - FLAG_Z |= res; - - m68ki_write_8(ea, res); -} - - -void m68k_op_negx_8_al(void) -{ - uint ea = EA_AL_8(); - uint src = m68ki_read_8(ea); - uint res = 0 - src - XFLAG_AS_1(); - - FLAG_N = NFLAG_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = src & res; - - res = MASK_OUT_ABOVE_8(res); - FLAG_Z |= res; - - m68ki_write_8(ea, res); -} - - -void m68k_op_negx_16_d(void) -{ - uint* r_dst = &DY; - uint res = 0 - MASK_OUT_ABOVE_16(*r_dst) - XFLAG_AS_1(); - - FLAG_N = NFLAG_16(res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_V = (*r_dst & res)>>8; - - res = MASK_OUT_ABOVE_16(res); - FLAG_Z |= res; - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; -} - - -void m68k_op_negx_16_ai(void) -{ - uint ea = EA_AY_AI_16(); - uint src = m68ki_read_16(ea); - uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1(); - - FLAG_N = NFLAG_16(res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_V = (src & res)>>8; - - res = MASK_OUT_ABOVE_16(res); - FLAG_Z |= res; - - m68ki_write_16(ea, res); -} - - -void m68k_op_negx_16_pi(void) -{ - uint ea = EA_AY_PI_16(); - uint src = m68ki_read_16(ea); - uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1(); - - FLAG_N = NFLAG_16(res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_V = (src & res)>>8; - - res = MASK_OUT_ABOVE_16(res); - FLAG_Z |= res; - - m68ki_write_16(ea, res); -} - - -void m68k_op_negx_16_pd(void) -{ - uint ea = EA_AY_PD_16(); - uint src = m68ki_read_16(ea); - uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1(); - - FLAG_N = NFLAG_16(res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_V = (src & res)>>8; - - res = MASK_OUT_ABOVE_16(res); - FLAG_Z |= res; - - m68ki_write_16(ea, res); -} - - -void m68k_op_negx_16_di(void) -{ - uint ea = EA_AY_DI_16(); - uint src = m68ki_read_16(ea); - uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1(); - - FLAG_N = NFLAG_16(res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_V = (src & res)>>8; - - res = MASK_OUT_ABOVE_16(res); - FLAG_Z |= res; - - m68ki_write_16(ea, res); -} - - -void m68k_op_negx_16_ix(void) -{ - uint ea = EA_AY_IX_16(); - uint src = m68ki_read_16(ea); - uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1(); - - FLAG_N = NFLAG_16(res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_V = (src & res)>>8; - - res = MASK_OUT_ABOVE_16(res); - FLAG_Z |= res; - - m68ki_write_16(ea, res); -} - - -void m68k_op_negx_16_aw(void) -{ - uint ea = EA_AW_16(); - uint src = m68ki_read_16(ea); - uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1(); - - FLAG_N = NFLAG_16(res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_V = (src & res)>>8; - - res = MASK_OUT_ABOVE_16(res); - FLAG_Z |= res; - - m68ki_write_16(ea, res); -} - - -void m68k_op_negx_16_al(void) -{ - uint ea = EA_AL_16(); - uint src = m68ki_read_16(ea); - uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1(); - - FLAG_N = NFLAG_16(res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_V = (src & res)>>8; - - res = MASK_OUT_ABOVE_16(res); - FLAG_Z |= res; - - m68ki_write_16(ea, res); -} - - -void m68k_op_negx_32_d(void) -{ - uint* r_dst = &DY; - uint res = 0 - MASK_OUT_ABOVE_32(*r_dst) - XFLAG_AS_1(); - - FLAG_N = NFLAG_32(res); - FLAG_X = FLAG_C = CFLAG_SUB_32(*r_dst, 0, res); - FLAG_V = (*r_dst & res)>>24; - - res = MASK_OUT_ABOVE_32(res); - FLAG_Z |= res; - - *r_dst = res; -} - - -void m68k_op_negx_32_ai(void) -{ - uint ea = EA_AY_AI_32(); - uint src = m68ki_read_32(ea); - uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1(); - - FLAG_N = NFLAG_32(res); - FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res); - FLAG_V = (src & res)>>24; - - res = MASK_OUT_ABOVE_32(res); - FLAG_Z |= res; - - m68ki_write_32(ea, res); -} - - -void m68k_op_negx_32_pi(void) -{ - uint ea = EA_AY_PI_32(); - uint src = m68ki_read_32(ea); - uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1(); - - FLAG_N = NFLAG_32(res); - FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res); - FLAG_V = (src & res)>>24; - - res = MASK_OUT_ABOVE_32(res); - FLAG_Z |= res; - - m68ki_write_32(ea, res); -} - - -void m68k_op_negx_32_pd(void) -{ - uint ea = EA_AY_PD_32(); - uint src = m68ki_read_32(ea); - uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1(); - - FLAG_N = NFLAG_32(res); - FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res); - FLAG_V = (src & res)>>24; - - res = MASK_OUT_ABOVE_32(res); - FLAG_Z |= res; - - m68ki_write_32(ea, res); -} - - -void m68k_op_negx_32_di(void) -{ - uint ea = EA_AY_DI_32(); - uint src = m68ki_read_32(ea); - uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1(); - - FLAG_N = NFLAG_32(res); - FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res); - FLAG_V = (src & res)>>24; - - res = MASK_OUT_ABOVE_32(res); - FLAG_Z |= res; - - m68ki_write_32(ea, res); -} - - -void m68k_op_negx_32_ix(void) -{ - uint ea = EA_AY_IX_32(); - uint src = m68ki_read_32(ea); - uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1(); - - FLAG_N = NFLAG_32(res); - FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res); - FLAG_V = (src & res)>>24; - - res = MASK_OUT_ABOVE_32(res); - FLAG_Z |= res; - - m68ki_write_32(ea, res); -} - - -void m68k_op_negx_32_aw(void) -{ - uint ea = EA_AW_32(); - uint src = m68ki_read_32(ea); - uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1(); - - FLAG_N = NFLAG_32(res); - FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res); - FLAG_V = (src & res)>>24; - - res = MASK_OUT_ABOVE_32(res); - FLAG_Z |= res; - - m68ki_write_32(ea, res); -} - - -void m68k_op_negx_32_al(void) -{ - uint ea = EA_AL_32(); - uint src = m68ki_read_32(ea); - uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1(); - - FLAG_N = NFLAG_32(res); - FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res); - FLAG_V = (src & res)>>24; - - res = MASK_OUT_ABOVE_32(res); - FLAG_Z |= res; - - m68ki_write_32(ea, res); -} - - -void m68k_op_nop(void) -{ - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ -} - - -void m68k_op_not_8_d(void) -{ - uint* r_dst = &DY; - uint res = MASK_OUT_ABOVE_8(~*r_dst); - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_not_8_ai(void) -{ - uint ea = EA_AY_AI_8(); - uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea)); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_not_8_pi(void) -{ - uint ea = EA_AY_PI_8(); - uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea)); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_not_8_pi7(void) -{ - uint ea = EA_A7_PI_8(); - uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea)); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_not_8_pd(void) -{ - uint ea = EA_AY_PD_8(); - uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea)); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_not_8_pd7(void) -{ - uint ea = EA_A7_PD_8(); - uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea)); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_not_8_di(void) -{ - uint ea = EA_AY_DI_8(); - uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea)); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_not_8_ix(void) -{ - uint ea = EA_AY_IX_8(); - uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea)); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_not_8_aw(void) -{ - uint ea = EA_AW_8(); - uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea)); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_not_8_al(void) -{ - uint ea = EA_AL_8(); - uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea)); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_not_16_d(void) -{ - uint* r_dst = &DY; - uint res = MASK_OUT_ABOVE_16(~*r_dst); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_not_16_ai(void) -{ - uint ea = EA_AY_AI_16(); - uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea)); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_not_16_pi(void) -{ - uint ea = EA_AY_PI_16(); - uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea)); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_not_16_pd(void) -{ - uint ea = EA_AY_PD_16(); - uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea)); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_not_16_di(void) -{ - uint ea = EA_AY_DI_16(); - uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea)); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_not_16_ix(void) -{ - uint ea = EA_AY_IX_16(); - uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea)); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_not_16_aw(void) -{ - uint ea = EA_AW_16(); - uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea)); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_not_16_al(void) -{ - uint ea = EA_AL_16(); - uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea)); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_not_32_d(void) -{ - uint* r_dst = &DY; - uint res = *r_dst = MASK_OUT_ABOVE_32(~*r_dst); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_not_32_ai(void) -{ - uint ea = EA_AY_AI_32(); - uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea)); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_not_32_pi(void) -{ - uint ea = EA_AY_PI_32(); - uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea)); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_not_32_pd(void) -{ - uint ea = EA_AY_PD_32(); - uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea)); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_not_32_di(void) -{ - uint ea = EA_AY_DI_32(); - uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea)); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_not_32_ix(void) -{ - uint ea = EA_AY_IX_32(); - uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea)); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_not_32_aw(void) -{ - uint ea = EA_AW_32(); - uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea)); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_not_32_al(void) -{ - uint ea = EA_AL_32(); - uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea)); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_8_er_d(void) -{ - uint res = MASK_OUT_ABOVE_8((DX |= MASK_OUT_ABOVE_8(DY))); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_8_er_ai(void) -{ - uint res = MASK_OUT_ABOVE_8((DX |= OPER_AY_AI_8())); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_8_er_pi(void) -{ - uint res = MASK_OUT_ABOVE_8((DX |= OPER_AY_PI_8())); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_8_er_pi7(void) -{ - uint res = MASK_OUT_ABOVE_8((DX |= OPER_A7_PI_8())); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_8_er_pd(void) -{ - uint res = MASK_OUT_ABOVE_8((DX |= OPER_AY_PD_8())); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_8_er_pd7(void) -{ - uint res = MASK_OUT_ABOVE_8((DX |= OPER_A7_PD_8())); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_8_er_di(void) -{ - uint res = MASK_OUT_ABOVE_8((DX |= OPER_AY_DI_8())); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_8_er_ix(void) -{ - uint res = MASK_OUT_ABOVE_8((DX |= OPER_AY_IX_8())); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_8_er_aw(void) -{ - uint res = MASK_OUT_ABOVE_8((DX |= OPER_AW_8())); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_8_er_al(void) -{ - uint res = MASK_OUT_ABOVE_8((DX |= OPER_AL_8())); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_8_er_pcdi(void) -{ - uint res = MASK_OUT_ABOVE_8((DX |= OPER_PCDI_8())); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_8_er_pcix(void) -{ - uint res = MASK_OUT_ABOVE_8((DX |= OPER_PCIX_8())); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_8_er_i(void) -{ - uint res = MASK_OUT_ABOVE_8((DX |= OPER_I_8())); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_16_er_d(void) -{ - uint res = MASK_OUT_ABOVE_16((DX |= MASK_OUT_ABOVE_16(DY))); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_16_er_ai(void) -{ - uint res = MASK_OUT_ABOVE_16((DX |= OPER_AY_AI_16())); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_16_er_pi(void) -{ - uint res = MASK_OUT_ABOVE_16((DX |= OPER_AY_PI_16())); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_16_er_pd(void) -{ - uint res = MASK_OUT_ABOVE_16((DX |= OPER_AY_PD_16())); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_16_er_di(void) -{ - uint res = MASK_OUT_ABOVE_16((DX |= OPER_AY_DI_16())); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_16_er_ix(void) -{ - uint res = MASK_OUT_ABOVE_16((DX |= OPER_AY_IX_16())); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_16_er_aw(void) -{ - uint res = MASK_OUT_ABOVE_16((DX |= OPER_AW_16())); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_16_er_al(void) -{ - uint res = MASK_OUT_ABOVE_16((DX |= OPER_AL_16())); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_16_er_pcdi(void) -{ - uint res = MASK_OUT_ABOVE_16((DX |= OPER_PCDI_16())); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_16_er_pcix(void) -{ - uint res = MASK_OUT_ABOVE_16((DX |= OPER_PCIX_16())); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_16_er_i(void) -{ - uint res = MASK_OUT_ABOVE_16((DX |= OPER_I_16())); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_32_er_d(void) -{ - uint res = DX |= DY; - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_32_er_ai(void) -{ - uint res = DX |= OPER_AY_AI_32(); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_32_er_pi(void) -{ - uint res = DX |= OPER_AY_PI_32(); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_32_er_pd(void) -{ - uint res = DX |= OPER_AY_PD_32(); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_32_er_di(void) -{ - uint res = DX |= OPER_AY_DI_32(); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_32_er_ix(void) -{ - uint res = DX |= OPER_AY_IX_32(); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_32_er_aw(void) -{ - uint res = DX |= OPER_AW_32(); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_32_er_al(void) -{ - uint res = DX |= OPER_AL_32(); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_32_er_pcdi(void) -{ - uint res = DX |= OPER_PCDI_32(); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_32_er_pcix(void) -{ - uint res = DX |= OPER_PCIX_32(); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_32_er_i(void) -{ - uint res = DX |= OPER_I_32(); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_8_re_ai(void) -{ - uint ea = EA_AY_AI_8(); - uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea)); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_8_re_pi(void) -{ - uint ea = EA_AY_PI_8(); - uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea)); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_8_re_pi7(void) -{ - uint ea = EA_A7_PI_8(); - uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea)); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_8_re_pd(void) -{ - uint ea = EA_AY_PD_8(); - uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea)); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_8_re_pd7(void) -{ - uint ea = EA_A7_PD_8(); - uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea)); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_8_re_di(void) -{ - uint ea = EA_AY_DI_8(); - uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea)); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_8_re_ix(void) -{ - uint ea = EA_AY_IX_8(); - uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea)); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_8_re_aw(void) -{ - uint ea = EA_AW_8(); - uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea)); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_8_re_al(void) -{ - uint ea = EA_AL_8(); - uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea)); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_16_re_ai(void) -{ - uint ea = EA_AY_AI_16(); - uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea)); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_16_re_pi(void) -{ - uint ea = EA_AY_PI_16(); - uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea)); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_16_re_pd(void) -{ - uint ea = EA_AY_PD_16(); - uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea)); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_16_re_di(void) -{ - uint ea = EA_AY_DI_16(); - uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea)); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_16_re_ix(void) -{ - uint ea = EA_AY_IX_16(); - uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea)); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_16_re_aw(void) -{ - uint ea = EA_AW_16(); - uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea)); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_16_re_al(void) -{ - uint ea = EA_AL_16(); - uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea)); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_32_re_ai(void) -{ - uint ea = EA_AY_AI_32(); - uint res = DX | m68ki_read_32(ea); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_32_re_pi(void) -{ - uint ea = EA_AY_PI_32(); - uint res = DX | m68ki_read_32(ea); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_32_re_pd(void) -{ - uint ea = EA_AY_PD_32(); - uint res = DX | m68ki_read_32(ea); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_32_re_di(void) -{ - uint ea = EA_AY_DI_32(); - uint res = DX | m68ki_read_32(ea); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_32_re_ix(void) -{ - uint ea = EA_AY_IX_32(); - uint res = DX | m68ki_read_32(ea); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_32_re_aw(void) -{ - uint ea = EA_AW_32(); - uint res = DX | m68ki_read_32(ea); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_or_32_re_al(void) -{ - uint ea = EA_AL_32(); - uint res = DX | m68ki_read_32(ea); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_ori_8_d(void) -{ - uint res = MASK_OUT_ABOVE_8((DY |= OPER_I_8())); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_ori_8_ai(void) -{ - uint src = OPER_I_8(); - uint ea = EA_AY_AI_8(); - uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea)); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_ori_8_pi(void) -{ - uint src = OPER_I_8(); - uint ea = EA_AY_PI_8(); - uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea)); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_ori_8_pi7(void) -{ - uint src = OPER_I_8(); - uint ea = EA_A7_PI_8(); - uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea)); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_ori_8_pd(void) -{ - uint src = OPER_I_8(); - uint ea = EA_AY_PD_8(); - uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea)); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_ori_8_pd7(void) -{ - uint src = OPER_I_8(); - uint ea = EA_A7_PD_8(); - uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea)); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_ori_8_di(void) -{ - uint src = OPER_I_8(); - uint ea = EA_AY_DI_8(); - uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea)); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_ori_8_ix(void) -{ - uint src = OPER_I_8(); - uint ea = EA_AY_IX_8(); - uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea)); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_ori_8_aw(void) -{ - uint src = OPER_I_8(); - uint ea = EA_AW_8(); - uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea)); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_ori_8_al(void) -{ - uint src = OPER_I_8(); - uint ea = EA_AL_8(); - uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea)); - - m68ki_write_8(ea, res); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_ori_16_d(void) -{ - uint res = MASK_OUT_ABOVE_16(DY |= OPER_I_16()); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_ori_16_ai(void) -{ - uint src = OPER_I_16(); - uint ea = EA_AY_AI_16(); - uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea)); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_ori_16_pi(void) -{ - uint src = OPER_I_16(); - uint ea = EA_AY_PI_16(); - uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea)); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_ori_16_pd(void) -{ - uint src = OPER_I_16(); - uint ea = EA_AY_PD_16(); - uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea)); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_ori_16_di(void) -{ - uint src = OPER_I_16(); - uint ea = EA_AY_DI_16(); - uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea)); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_ori_16_ix(void) -{ - uint src = OPER_I_16(); - uint ea = EA_AY_IX_16(); - uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea)); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_ori_16_aw(void) -{ - uint src = OPER_I_16(); - uint ea = EA_AW_16(); - uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea)); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_ori_16_al(void) -{ - uint src = OPER_I_16(); - uint ea = EA_AL_16(); - uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea)); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_ori_32_d(void) -{ - uint res = DY |= OPER_I_32(); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_ori_32_ai(void) -{ - uint src = OPER_I_32(); - uint ea = EA_AY_AI_32(); - uint res = src | m68ki_read_32(ea); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_ori_32_pi(void) -{ - uint src = OPER_I_32(); - uint ea = EA_AY_PI_32(); - uint res = src | m68ki_read_32(ea); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_ori_32_pd(void) -{ - uint src = OPER_I_32(); - uint ea = EA_AY_PD_32(); - uint res = src | m68ki_read_32(ea); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_ori_32_di(void) -{ - uint src = OPER_I_32(); - uint ea = EA_AY_DI_32(); - uint res = src | m68ki_read_32(ea); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_ori_32_ix(void) -{ - uint src = OPER_I_32(); - uint ea = EA_AY_IX_32(); - uint res = src | m68ki_read_32(ea); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_ori_32_aw(void) -{ - uint src = OPER_I_32(); - uint ea = EA_AW_32(); - uint res = src | m68ki_read_32(ea); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_ori_32_al(void) -{ - uint src = OPER_I_32(); - uint ea = EA_AL_32(); - uint res = src | m68ki_read_32(ea); - - m68ki_write_32(ea, res); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_ori_16_toc(void) -{ - m68ki_set_ccr(m68ki_get_ccr() | OPER_I_16()); -} - - -void m68k_op_ori_16_tos(void) -{ - if(FLAG_S) - { - uint src = OPER_I_16(); - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_set_sr(m68ki_get_sr() | src); - return; - } - m68ki_exception_privilege_violation(); -} - - -void m68k_op_pack_16_rr(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - /* Note: DX and DY are reversed in Motorola's docs */ - uint src = DY + OPER_I_16(); - uint* r_dst = &DX; - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | ((src >> 4) & 0x00f0) | (src & 0x000f); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_pack_16_mm_ax7(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - /* Note: AX and AY are reversed in Motorola's docs */ - uint ea_src = EA_AY_PD_8(); - uint src = m68ki_read_8(ea_src); - ea_src = EA_AY_PD_8(); - src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16(); - - m68ki_write_8(EA_A7_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f)); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_pack_16_mm_ay7(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - /* Note: AX and AY are reversed in Motorola's docs */ - uint ea_src = EA_A7_PD_8(); - uint src = m68ki_read_8(ea_src); - ea_src = EA_A7_PD_8(); - src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16(); - - m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f)); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_pack_16_mm_axy7(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint ea_src = EA_A7_PD_8(); - uint src = m68ki_read_8(ea_src); - ea_src = EA_A7_PD_8(); - src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16(); - - m68ki_write_8(EA_A7_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f)); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_pack_16_mm(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - /* Note: AX and AY are reversed in Motorola's docs */ - uint ea_src = EA_AY_PD_8(); - uint src = m68ki_read_8(ea_src); - ea_src = EA_AY_PD_8(); - src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16(); - - m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f)); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_pea_32_ai(void) -{ - uint ea = EA_AY_AI_32(); - - m68ki_push_32(ea); -} - - -void m68k_op_pea_32_di(void) -{ - uint ea = EA_AY_DI_32(); - - m68ki_push_32(ea); -} - - -void m68k_op_pea_32_ix(void) -{ - uint ea = EA_AY_IX_32(); - - m68ki_push_32(ea); -} - - -void m68k_op_pea_32_aw(void) -{ - uint ea = EA_AW_32(); - - m68ki_push_32(ea); -} - - -void m68k_op_pea_32_al(void) -{ - uint ea = EA_AL_32(); - - m68ki_push_32(ea); -} - - -void m68k_op_pea_32_pcdi(void) -{ - uint ea = EA_PCDI_32(); - - m68ki_push_32(ea); -} - - -void m68k_op_pea_32_pcix(void) -{ - uint ea = EA_PCIX_32(); - - m68ki_push_32(ea); -} - - -void m68k_op_reset(void) -{ - if(FLAG_S) - { - m68ki_output_reset(); /* auto-disable (see m68kcpu.h) */ - USE_CYCLES(CYC_RESET); - return; - } - m68ki_exception_privilege_violation(); -} - - -void m68k_op_ror_8_s(void) -{ - uint* r_dst = &DY; - uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1; - uint shift = orig_shift & 7; - uint src = MASK_OUT_ABOVE_8(*r_dst); - uint res = ROR_8(src, shift); - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = src << (9-orig_shift); - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_ror_16_s(void) -{ - uint* r_dst = &DY; - uint shift = (((REG_IR >> 9) - 1) & 7) + 1; - uint src = MASK_OUT_ABOVE_16(*r_dst); - uint res = ROR_16(src, shift); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = src << (9-shift); - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_ror_32_s(void) -{ - uint* r_dst = &DY; - uint shift = (((REG_IR >> 9) - 1) & 7) + 1; - uint64 src = *r_dst; - uint res = ROR_32(src, shift); - - *r_dst = res; - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = src << (9-shift); - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_ror_8_r(void) -{ - uint* r_dst = &DY; - uint orig_shift = DX & 0x3f; - uint shift = orig_shift & 7; - uint src = MASK_OUT_ABOVE_8(*r_dst); - uint res = ROR_8(src, shift); - - if(orig_shift != 0) - { - USE_CYCLES(orig_shift<> ((shift - 1) & 15)) << 8; - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - return; - } - - FLAG_C = CFLAG_CLEAR; - FLAG_N = NFLAG_16(src); - FLAG_Z = src; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_ror_32_r(void) -{ - uint* r_dst = &DY; - uint orig_shift = DX & 0x3f; - uint shift = orig_shift & 31; - uint64 src = *r_dst; - uint res = ROR_32(src, shift); - - if(orig_shift != 0) - { - USE_CYCLES(orig_shift<> ((shift - 1) & 31)) << 8; - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - return; - } - - FLAG_C = CFLAG_CLEAR; - FLAG_N = NFLAG_32(src); - FLAG_Z = src; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_ror_16_ai(void) -{ - uint ea = EA_AY_AI_16(); - uint src = m68ki_read_16(ea); - uint res = ROR_16(src, 1); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = src << 8; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_ror_16_pi(void) -{ - uint ea = EA_AY_PI_16(); - uint src = m68ki_read_16(ea); - uint res = ROR_16(src, 1); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = src << 8; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_ror_16_pd(void) -{ - uint ea = EA_AY_PD_16(); - uint src = m68ki_read_16(ea); - uint res = ROR_16(src, 1); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = src << 8; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_ror_16_di(void) -{ - uint ea = EA_AY_DI_16(); - uint src = m68ki_read_16(ea); - uint res = ROR_16(src, 1); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = src << 8; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_ror_16_ix(void) -{ - uint ea = EA_AY_IX_16(); - uint src = m68ki_read_16(ea); - uint res = ROR_16(src, 1); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = src << 8; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_ror_16_aw(void) -{ - uint ea = EA_AW_16(); - uint src = m68ki_read_16(ea); - uint res = ROR_16(src, 1); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = src << 8; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_ror_16_al(void) -{ - uint ea = EA_AL_16(); - uint src = m68ki_read_16(ea); - uint res = ROR_16(src, 1); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = src << 8; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_rol_8_s(void) -{ - uint* r_dst = &DY; - uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1; - uint shift = orig_shift & 7; - uint src = MASK_OUT_ABOVE_8(*r_dst); - uint res = ROL_8(src, shift); - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_C = src << orig_shift; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_rol_16_s(void) -{ - uint* r_dst = &DY; - uint shift = (((REG_IR >> 9) - 1) & 7) + 1; - uint src = MASK_OUT_ABOVE_16(*r_dst); - uint res = ROL_16(src, shift); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = src >> (8-shift); - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_rol_32_s(void) -{ - uint* r_dst = &DY; - uint shift = (((REG_IR >> 9) - 1) & 7) + 1; - uint64 src = *r_dst; - uint res = ROL_32(src, shift); - - *r_dst = res; - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_C = src >> (24-shift); - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_rol_8_r(void) -{ - uint* r_dst = &DY; - uint orig_shift = DX & 0x3f; - uint shift = orig_shift & 7; - uint src = MASK_OUT_ABOVE_8(*r_dst); - uint res = ROL_8(src, shift); - - if(orig_shift != 0) - { - USE_CYCLES(orig_shift<> 8; - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - return; - } - FLAG_C = (src & 1)<<8; - FLAG_N = NFLAG_16(src); - FLAG_Z = src; - FLAG_V = VFLAG_CLEAR; - return; - } - - FLAG_C = CFLAG_CLEAR; - FLAG_N = NFLAG_16(src); - FLAG_Z = src; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_rol_32_r(void) -{ - uint* r_dst = &DY; - uint orig_shift = DX & 0x3f; - uint shift = orig_shift & 31; - uint64 src = *r_dst; - uint res = ROL_32(src, shift); - - if(orig_shift != 0) - { - USE_CYCLES(orig_shift<> (32 - shift)) << 8; - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - return; - } - - FLAG_C = CFLAG_CLEAR; - FLAG_N = NFLAG_32(src); - FLAG_Z = src; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_rol_16_ai(void) -{ - uint ea = EA_AY_AI_16(); - uint src = m68ki_read_16(ea); - uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1)); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = src >> 7; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_rol_16_pi(void) -{ - uint ea = EA_AY_PI_16(); - uint src = m68ki_read_16(ea); - uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1)); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = src >> 7; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_rol_16_pd(void) -{ - uint ea = EA_AY_PD_16(); - uint src = m68ki_read_16(ea); - uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1)); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = src >> 7; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_rol_16_di(void) -{ - uint ea = EA_AY_DI_16(); - uint src = m68ki_read_16(ea); - uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1)); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = src >> 7; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_rol_16_ix(void) -{ - uint ea = EA_AY_IX_16(); - uint src = m68ki_read_16(ea); - uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1)); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = src >> 7; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_rol_16_aw(void) -{ - uint ea = EA_AW_16(); - uint src = m68ki_read_16(ea); - uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1)); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = src >> 7; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_rol_16_al(void) -{ - uint ea = EA_AL_16(); - uint src = m68ki_read_16(ea); - uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1)); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_C = src >> 7; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_roxr_8_s(void) -{ - uint* r_dst = &DY; - uint shift = (((REG_IR >> 9) - 1) & 7) + 1; - uint src = MASK_OUT_ABOVE_8(*r_dst); - uint res = ROR_9(src | (XFLAG_AS_1() << 8), shift); - - FLAG_C = FLAG_X = res; - res = MASK_OUT_ABOVE_8(res); - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_roxr_16_s(void) -{ - uint* r_dst = &DY; - uint shift = (((REG_IR >> 9) - 1) & 7) + 1; - uint src = MASK_OUT_ABOVE_16(*r_dst); - uint res = ROR_17(src | (XFLAG_AS_1() << 16), shift); - - FLAG_C = FLAG_X = res >> 8; - res = MASK_OUT_ABOVE_16(res); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_roxr_32_s(void) -{ -#if M68K_USE_64_BIT - - uint* r_dst = &DY; - uint shift = (((REG_IR >> 9) - 1) & 7) + 1; - uint64 src = *r_dst; - uint64 res = src | (((uint64)XFLAG_AS_1()) << 32); - - res = ROR_33_64(res, shift); - - FLAG_C = FLAG_X = res >> 24; - res = MASK_OUT_ABOVE_32(res); - - *r_dst = res; - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - -#else - - uint* r_dst = &DY; - uint shift = (((REG_IR >> 9) - 1) & 7) + 1; - uint src = *r_dst; - uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift))); - uint new_x_flag = src & (1 << (shift - 1)); - - *r_dst = res; - - FLAG_C = FLAG_X = (new_x_flag != 0)<<8; - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - -#endif -} - - -void m68k_op_roxr_8_r(void) -{ - uint* r_dst = &DY; - uint orig_shift = DX & 0x3f; - - if(orig_shift != 0) - { - uint shift = orig_shift % 9; - uint src = MASK_OUT_ABOVE_8(*r_dst); - uint res = ROR_9(src | (XFLAG_AS_1() << 8), shift); - - USE_CYCLES(orig_shift<> 8; - res = MASK_OUT_ABOVE_16(res); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - return; - } - - FLAG_C = FLAG_X; - FLAG_N = NFLAG_16(*r_dst); - FLAG_Z = MASK_OUT_ABOVE_16(*r_dst); - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_roxr_32_r(void) -{ -#if M68K_USE_64_BIT - - uint* r_dst = &DY; - uint orig_shift = DX & 0x3f; - - if(orig_shift != 0) - { - uint shift = orig_shift % 33; - uint64 src = *r_dst; - uint64 res = src | (((uint64)XFLAG_AS_1()) << 32); - - res = ROR_33_64(res, shift); - - USE_CYCLES(orig_shift<> 24; - res = MASK_OUT_ABOVE_32(res); - - *r_dst = res; - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - return; - } - - FLAG_C = FLAG_X; - FLAG_N = NFLAG_32(*r_dst); - FLAG_Z = *r_dst; - FLAG_V = VFLAG_CLEAR; - -#else - - uint* r_dst = &DY; - uint orig_shift = DX & 0x3f; - uint shift = orig_shift % 33; - uint src = *r_dst; - uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift))); - uint new_x_flag = src & (1 << (shift - 1)); - - if(orig_shift != 0) - USE_CYCLES(orig_shift<> 8; - res = MASK_OUT_ABOVE_16(res); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_roxr_16_pi(void) -{ - uint ea = EA_AY_PI_16(); - uint src = m68ki_read_16(ea); - uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1); - - FLAG_C = FLAG_X = res >> 8; - res = MASK_OUT_ABOVE_16(res); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_roxr_16_pd(void) -{ - uint ea = EA_AY_PD_16(); - uint src = m68ki_read_16(ea); - uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1); - - FLAG_C = FLAG_X = res >> 8; - res = MASK_OUT_ABOVE_16(res); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_roxr_16_di(void) -{ - uint ea = EA_AY_DI_16(); - uint src = m68ki_read_16(ea); - uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1); - - FLAG_C = FLAG_X = res >> 8; - res = MASK_OUT_ABOVE_16(res); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_roxr_16_ix(void) -{ - uint ea = EA_AY_IX_16(); - uint src = m68ki_read_16(ea); - uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1); - - FLAG_C = FLAG_X = res >> 8; - res = MASK_OUT_ABOVE_16(res); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_roxr_16_aw(void) -{ - uint ea = EA_AW_16(); - uint src = m68ki_read_16(ea); - uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1); - - FLAG_C = FLAG_X = res >> 8; - res = MASK_OUT_ABOVE_16(res); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_roxr_16_al(void) -{ - uint ea = EA_AL_16(); - uint src = m68ki_read_16(ea); - uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1); - - FLAG_C = FLAG_X = res >> 8; - res = MASK_OUT_ABOVE_16(res); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_roxl_8_s(void) -{ - uint* r_dst = &DY; - uint shift = (((REG_IR >> 9) - 1) & 7) + 1; - uint src = MASK_OUT_ABOVE_8(*r_dst); - uint res = ROL_9(src | (XFLAG_AS_1() << 8), shift); - - FLAG_C = FLAG_X = res; - res = MASK_OUT_ABOVE_8(res); - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_roxl_16_s(void) -{ - uint* r_dst = &DY; - uint shift = (((REG_IR >> 9) - 1) & 7) + 1; - uint src = MASK_OUT_ABOVE_16(*r_dst); - uint res = ROL_17(src | (XFLAG_AS_1() << 16), shift); - - FLAG_C = FLAG_X = res >> 8; - res = MASK_OUT_ABOVE_16(res); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_roxl_32_s(void) -{ -#if M68K_USE_64_BIT - - uint* r_dst = &DY; - uint shift = (((REG_IR >> 9) - 1) & 7) + 1; - uint64 src = *r_dst; - uint64 res = src | (((uint64)XFLAG_AS_1()) << 32); - - res = ROL_33_64(res, shift); - - FLAG_C = FLAG_X = res >> 24; - res = MASK_OUT_ABOVE_32(res); - - *r_dst = res; - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - -#else - - uint* r_dst = &DY; - uint shift = (((REG_IR >> 9) - 1) & 7) + 1; - uint src = *r_dst; - uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1))); - uint new_x_flag = src & (1 << (32 - shift)); - - *r_dst = res; - - FLAG_C = FLAG_X = (new_x_flag != 0)<<8; - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - -#endif -} - - -void m68k_op_roxl_8_r(void) -{ - uint* r_dst = &DY; - uint orig_shift = DX & 0x3f; - - - if(orig_shift != 0) - { - uint shift = orig_shift % 9; - uint src = MASK_OUT_ABOVE_8(*r_dst); - uint res = ROL_9(src | (XFLAG_AS_1() << 8), shift); - - USE_CYCLES(orig_shift<> 8; - res = MASK_OUT_ABOVE_16(res); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - return; - } - - FLAG_C = FLAG_X; - FLAG_N = NFLAG_16(*r_dst); - FLAG_Z = MASK_OUT_ABOVE_16(*r_dst); - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_roxl_32_r(void) -{ -#if M68K_USE_64_BIT - - uint* r_dst = &DY; - uint orig_shift = DX & 0x3f; - - if(orig_shift != 0) - { - uint shift = orig_shift % 33; - uint64 src = *r_dst; - uint64 res = src | (((uint64)XFLAG_AS_1()) << 32); - - res = ROL_33_64(res, shift); - - USE_CYCLES(orig_shift<> 24; - res = MASK_OUT_ABOVE_32(res); - - *r_dst = res; - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - return; - } - - FLAG_C = FLAG_X; - FLAG_N = NFLAG_32(*r_dst); - FLAG_Z = *r_dst; - FLAG_V = VFLAG_CLEAR; - -#else - - uint* r_dst = &DY; - uint orig_shift = DX & 0x3f; - uint shift = orig_shift % 33; - uint src = *r_dst; - uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1))); - uint new_x_flag = src & (1 << (32 - shift)); - - if(orig_shift != 0) - USE_CYCLES(orig_shift<> 8; - res = MASK_OUT_ABOVE_16(res); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_roxl_16_pi(void) -{ - uint ea = EA_AY_PI_16(); - uint src = m68ki_read_16(ea); - uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1); - - FLAG_C = FLAG_X = res >> 8; - res = MASK_OUT_ABOVE_16(res); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_roxl_16_pd(void) -{ - uint ea = EA_AY_PD_16(); - uint src = m68ki_read_16(ea); - uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1); - - FLAG_C = FLAG_X = res >> 8; - res = MASK_OUT_ABOVE_16(res); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_roxl_16_di(void) -{ - uint ea = EA_AY_DI_16(); - uint src = m68ki_read_16(ea); - uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1); - - FLAG_C = FLAG_X = res >> 8; - res = MASK_OUT_ABOVE_16(res); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_roxl_16_ix(void) -{ - uint ea = EA_AY_IX_16(); - uint src = m68ki_read_16(ea); - uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1); - - FLAG_C = FLAG_X = res >> 8; - res = MASK_OUT_ABOVE_16(res); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_roxl_16_aw(void) -{ - uint ea = EA_AW_16(); - uint src = m68ki_read_16(ea); - uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1); - - FLAG_C = FLAG_X = res >> 8; - res = MASK_OUT_ABOVE_16(res); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_roxl_16_al(void) -{ - uint ea = EA_AL_16(); - uint src = m68ki_read_16(ea); - uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1); - - FLAG_C = FLAG_X = res >> 8; - res = MASK_OUT_ABOVE_16(res); - - m68ki_write_16(ea, res); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_rtd_32(void) -{ - if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) - { - uint new_pc = m68ki_pull_32(); - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16())); - m68ki_jump(new_pc); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_rte_32(void) -{ - if(FLAG_S) - { - uint new_sr; - uint new_pc; - uint format_word; - - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - - if(CPU_TYPE_IS_000(CPU_TYPE)) - { - new_sr = m68ki_pull_16(); - new_pc = m68ki_pull_32(); - m68ki_jump(new_pc); - m68ki_set_sr(new_sr); - - CPU_INSTR_MODE = INSTRUCTION_YES; - CPU_RUN_MODE = RUN_MODE_NORMAL; - - return; - } - - if(CPU_TYPE_IS_010(CPU_TYPE)) - { - format_word = m68ki_read_16(REG_A[7]+6) >> 12; - if(format_word == 0) - { - new_sr = m68ki_pull_16(); - new_pc = m68ki_pull_32(); - m68ki_fake_pull_16(); /* format word */ - m68ki_jump(new_pc); - m68ki_set_sr(new_sr); - CPU_INSTR_MODE = INSTRUCTION_YES; - CPU_RUN_MODE = RUN_MODE_NORMAL; - return; - } - CPU_INSTR_MODE = INSTRUCTION_YES; - CPU_RUN_MODE = RUN_MODE_NORMAL; - /* Not handling bus fault (9) */ - m68ki_exception_format_error(); - return; - } - - /* Otherwise it's 020 */ -rte_loop: - format_word = m68ki_read_16(REG_A[7]+6) >> 12; - switch(format_word) - { - case 0: /* Normal */ - new_sr = m68ki_pull_16(); - new_pc = m68ki_pull_32(); - m68ki_fake_pull_16(); /* format word */ - m68ki_jump(new_pc); - m68ki_set_sr(new_sr); - CPU_INSTR_MODE = INSTRUCTION_YES; - CPU_RUN_MODE = RUN_MODE_NORMAL; - return; - case 1: /* Throwaway */ - new_sr = m68ki_pull_16(); - m68ki_fake_pull_32(); /* program counter */ - m68ki_fake_pull_16(); /* format word */ - m68ki_set_sr_noint(new_sr); - goto rte_loop; - case 2: /* Trap */ - new_sr = m68ki_pull_16(); - new_pc = m68ki_pull_32(); - m68ki_fake_pull_16(); /* format word */ - m68ki_fake_pull_32(); /* address */ - m68ki_jump(new_pc); - m68ki_set_sr(new_sr); - CPU_INSTR_MODE = INSTRUCTION_YES; - CPU_RUN_MODE = RUN_MODE_NORMAL; - return; - } - /* Not handling long or short bus fault */ - CPU_INSTR_MODE = INSTRUCTION_YES; - CPU_RUN_MODE = RUN_MODE_NORMAL; - m68ki_exception_format_error(); - return; - } - m68ki_exception_privilege_violation(); -} - - -void m68k_op_rtm_32(void) -{ - if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) - { - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", - m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, - m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_rtr_32(void) -{ - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_set_ccr(m68ki_pull_16()); - m68ki_jump(m68ki_pull_32()); -} - - -void m68k_op_rts_32(void) -{ - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - m68ki_jump(m68ki_pull_32()); -} - - -void m68k_op_sbcd_8_rr(void) -{ - uint* r_dst = &DX; - uint src = DY; - uint dst = *r_dst; - uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1(); - - FLAG_V = ~res; /* Undefined V behavior */ - - if(res > 9) - res -= 6; - res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src); - FLAG_X = FLAG_C = (res > 0x99) << 8; - if(FLAG_C) - res += 0xa0; - - res = MASK_OUT_ABOVE_8(res); - - FLAG_V &= res; /* Undefined V behavior part II */ - FLAG_N = NFLAG_8(res); /* Undefined N behavior */ - FLAG_Z |= res; - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; -} - - -void m68k_op_sbcd_8_mm_ax7(void) -{ - uint src = OPER_AY_PD_8(); - uint ea = EA_A7_PD_8(); - uint dst = m68ki_read_8(ea); - uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1(); - - FLAG_V = ~res; /* Undefined V behavior */ - - if(res > 9) - res -= 6; - res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src); - FLAG_X = FLAG_C = (res > 0x99) << 8; - if(FLAG_C) - res += 0xa0; - - res = MASK_OUT_ABOVE_8(res); - - FLAG_V &= res; /* Undefined V behavior part II */ - FLAG_N = NFLAG_8(res); /* Undefined N behavior */ - FLAG_Z |= res; - - m68ki_write_8(ea, res); -} - - -void m68k_op_sbcd_8_mm_ay7(void) -{ - uint src = OPER_A7_PD_8(); - uint ea = EA_AX_PD_8(); - uint dst = m68ki_read_8(ea); - uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1(); - - FLAG_V = ~res; /* Undefined V behavior */ - - if(res > 9) - res -= 6; - res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src); - FLAG_X = FLAG_C = (res > 0x99) << 8; - if(FLAG_C) - res += 0xa0; - - res = MASK_OUT_ABOVE_8(res); - - FLAG_V &= res; /* Undefined V behavior part II */ - FLAG_N = NFLAG_8(res); /* Undefined N behavior */ - FLAG_Z |= res; - - m68ki_write_8(ea, res); -} - - -void m68k_op_sbcd_8_mm_axy7(void) -{ - uint src = OPER_A7_PD_8(); - uint ea = EA_A7_PD_8(); - uint dst = m68ki_read_8(ea); - uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1(); - - FLAG_V = ~res; /* Undefined V behavior */ - - if(res > 9) - res -= 6; - res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src); - FLAG_X = FLAG_C = (res > 0x99) << 8; - if(FLAG_C) - res += 0xa0; - - res = MASK_OUT_ABOVE_8(res); - - FLAG_V &= res; /* Undefined V behavior part II */ - FLAG_N = NFLAG_8(res); /* Undefined N behavior */ - FLAG_Z |= res; - - m68ki_write_8(ea, res); -} - - -void m68k_op_sbcd_8_mm(void) -{ - uint src = OPER_AY_PD_8(); - uint ea = EA_AX_PD_8(); - uint dst = m68ki_read_8(ea); - uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1(); - - FLAG_V = ~res; /* Undefined V behavior */ - - if(res > 9) - res -= 6; - res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src); - FLAG_X = FLAG_C = (res > 0x99) << 8; - if(FLAG_C) - res += 0xa0; - - res = MASK_OUT_ABOVE_8(res); - - FLAG_V &= res; /* Undefined V behavior part II */ - FLAG_N = NFLAG_8(res); /* Undefined N behavior */ - FLAG_Z |= res; - - m68ki_write_8(ea, res); -} - - -void m68k_op_st_8_d(void) -{ - DY |= 0xff; -} - - -void m68k_op_st_8_ai(void) -{ - m68ki_write_8(EA_AY_AI_8(), 0xff); -} - - -void m68k_op_st_8_pi(void) -{ - m68ki_write_8(EA_AY_PI_8(), 0xff); -} - - -void m68k_op_st_8_pi7(void) -{ - m68ki_write_8(EA_A7_PI_8(), 0xff); -} - - -void m68k_op_st_8_pd(void) -{ - m68ki_write_8(EA_AY_PD_8(), 0xff); -} - - -void m68k_op_st_8_pd7(void) -{ - m68ki_write_8(EA_A7_PD_8(), 0xff); -} - - -void m68k_op_st_8_di(void) -{ - m68ki_write_8(EA_AY_DI_8(), 0xff); -} - - -void m68k_op_st_8_ix(void) -{ - m68ki_write_8(EA_AY_IX_8(), 0xff); -} - - -void m68k_op_st_8_aw(void) -{ - m68ki_write_8(EA_AW_8(), 0xff); -} - - -void m68k_op_st_8_al(void) -{ - m68ki_write_8(EA_AL_8(), 0xff); -} - - -void m68k_op_sf_8_d(void) -{ - DY &= 0xffffff00; -} - - -void m68k_op_sf_8_ai(void) -{ - m68ki_write_8(EA_AY_AI_8(), 0); -} - - -void m68k_op_sf_8_pi(void) -{ - m68ki_write_8(EA_AY_PI_8(), 0); -} - - -void m68k_op_sf_8_pi7(void) -{ - m68ki_write_8(EA_A7_PI_8(), 0); -} - - -void m68k_op_sf_8_pd(void) -{ - m68ki_write_8(EA_AY_PD_8(), 0); -} - - -void m68k_op_sf_8_pd7(void) -{ - m68ki_write_8(EA_A7_PD_8(), 0); -} - - -void m68k_op_sf_8_di(void) -{ - m68ki_write_8(EA_AY_DI_8(), 0); -} - - -void m68k_op_sf_8_ix(void) -{ - m68ki_write_8(EA_AY_IX_8(), 0); -} - - -void m68k_op_sf_8_aw(void) -{ - m68ki_write_8(EA_AW_8(), 0); -} - - -void m68k_op_sf_8_al(void) -{ - m68ki_write_8(EA_AL_8(), 0); -} - - -void m68k_op_shi_8_d(void) -{ - if(COND_HI()) - { - DY |= 0xff; - return; - } - DY &= 0xffffff00; -} - - -void m68k_op_sls_8_d(void) -{ - if(COND_LS()) - { - DY |= 0xff; - return; - } - DY &= 0xffffff00; -} - - -void m68k_op_scc_8_d(void) -{ - if(COND_CC()) - { - DY |= 0xff; - return; - } - DY &= 0xffffff00; -} - - -void m68k_op_scs_8_d(void) -{ - if(COND_CS()) - { - DY |= 0xff; - return; - } - DY &= 0xffffff00; -} - - -void m68k_op_sne_8_d(void) -{ - if(COND_NE()) - { - DY |= 0xff; - return; - } - DY &= 0xffffff00; -} - - -void m68k_op_seq_8_d(void) -{ - if(COND_EQ()) - { - DY |= 0xff; - return; - } - DY &= 0xffffff00; -} - - -void m68k_op_svc_8_d(void) -{ - if(COND_VC()) - { - DY |= 0xff; - return; - } - DY &= 0xffffff00; -} - - -void m68k_op_svs_8_d(void) -{ - if(COND_VS()) - { - DY |= 0xff; - return; - } - DY &= 0xffffff00; -} - - -void m68k_op_spl_8_d(void) -{ - if(COND_PL()) - { - DY |= 0xff; - return; - } - DY &= 0xffffff00; -} - - -void m68k_op_smi_8_d(void) -{ - if(COND_MI()) - { - DY |= 0xff; - return; - } - DY &= 0xffffff00; -} - - -void m68k_op_sge_8_d(void) -{ - if(COND_GE()) - { - DY |= 0xff; - return; - } - DY &= 0xffffff00; -} - - -void m68k_op_slt_8_d(void) -{ - if(COND_LT()) - { - DY |= 0xff; - return; - } - DY &= 0xffffff00; -} - - -void m68k_op_sgt_8_d(void) -{ - if(COND_GT()) - { - DY |= 0xff; - return; - } - DY &= 0xffffff00; -} - - -void m68k_op_sle_8_d(void) -{ - if(COND_LE()) - { - DY |= 0xff; - return; - } - DY &= 0xffffff00; -} - - -void m68k_op_shi_8_ai(void) -{ - m68ki_write_8(EA_AY_AI_8(), COND_HI() ? 0xff : 0); -} - - -void m68k_op_shi_8_pi(void) -{ - m68ki_write_8(EA_AY_PI_8(), COND_HI() ? 0xff : 0); -} - - -void m68k_op_shi_8_pi7(void) -{ - m68ki_write_8(EA_A7_PI_8(), COND_HI() ? 0xff : 0); -} - - -void m68k_op_shi_8_pd(void) -{ - m68ki_write_8(EA_AY_PD_8(), COND_HI() ? 0xff : 0); -} - - -void m68k_op_shi_8_pd7(void) -{ - m68ki_write_8(EA_A7_PD_8(), COND_HI() ? 0xff : 0); -} - - -void m68k_op_shi_8_di(void) -{ - m68ki_write_8(EA_AY_DI_8(), COND_HI() ? 0xff : 0); -} - - -void m68k_op_shi_8_ix(void) -{ - m68ki_write_8(EA_AY_IX_8(), COND_HI() ? 0xff : 0); -} - - -void m68k_op_shi_8_aw(void) -{ - m68ki_write_8(EA_AW_8(), COND_HI() ? 0xff : 0); -} - - -void m68k_op_shi_8_al(void) -{ - m68ki_write_8(EA_AL_8(), COND_HI() ? 0xff : 0); -} - - -void m68k_op_sls_8_ai(void) -{ - m68ki_write_8(EA_AY_AI_8(), COND_LS() ? 0xff : 0); -} - - -void m68k_op_sls_8_pi(void) -{ - m68ki_write_8(EA_AY_PI_8(), COND_LS() ? 0xff : 0); -} - - -void m68k_op_sls_8_pi7(void) -{ - m68ki_write_8(EA_A7_PI_8(), COND_LS() ? 0xff : 0); -} - - -void m68k_op_sls_8_pd(void) -{ - m68ki_write_8(EA_AY_PD_8(), COND_LS() ? 0xff : 0); -} - - -void m68k_op_sls_8_pd7(void) -{ - m68ki_write_8(EA_A7_PD_8(), COND_LS() ? 0xff : 0); -} - - -void m68k_op_sls_8_di(void) -{ - m68ki_write_8(EA_AY_DI_8(), COND_LS() ? 0xff : 0); -} - - -void m68k_op_sls_8_ix(void) -{ - m68ki_write_8(EA_AY_IX_8(), COND_LS() ? 0xff : 0); -} - - -void m68k_op_sls_8_aw(void) -{ - m68ki_write_8(EA_AW_8(), COND_LS() ? 0xff : 0); -} - - -void m68k_op_sls_8_al(void) -{ - m68ki_write_8(EA_AL_8(), COND_LS() ? 0xff : 0); -} - - -void m68k_op_scc_8_ai(void) -{ - m68ki_write_8(EA_AY_AI_8(), COND_CC() ? 0xff : 0); -} - - -void m68k_op_scc_8_pi(void) -{ - m68ki_write_8(EA_AY_PI_8(), COND_CC() ? 0xff : 0); -} - - -void m68k_op_scc_8_pi7(void) -{ - m68ki_write_8(EA_A7_PI_8(), COND_CC() ? 0xff : 0); -} - - -void m68k_op_scc_8_pd(void) -{ - m68ki_write_8(EA_AY_PD_8(), COND_CC() ? 0xff : 0); -} - - -void m68k_op_scc_8_pd7(void) -{ - m68ki_write_8(EA_A7_PD_8(), COND_CC() ? 0xff : 0); -} - - -void m68k_op_scc_8_di(void) -{ - m68ki_write_8(EA_AY_DI_8(), COND_CC() ? 0xff : 0); -} - - -void m68k_op_scc_8_ix(void) -{ - m68ki_write_8(EA_AY_IX_8(), COND_CC() ? 0xff : 0); -} - - -void m68k_op_scc_8_aw(void) -{ - m68ki_write_8(EA_AW_8(), COND_CC() ? 0xff : 0); -} - - -void m68k_op_scc_8_al(void) -{ - m68ki_write_8(EA_AL_8(), COND_CC() ? 0xff : 0); -} - - -void m68k_op_scs_8_ai(void) -{ - m68ki_write_8(EA_AY_AI_8(), COND_CS() ? 0xff : 0); -} - - -void m68k_op_scs_8_pi(void) -{ - m68ki_write_8(EA_AY_PI_8(), COND_CS() ? 0xff : 0); -} - - -void m68k_op_scs_8_pi7(void) -{ - m68ki_write_8(EA_A7_PI_8(), COND_CS() ? 0xff : 0); -} - - -void m68k_op_scs_8_pd(void) -{ - m68ki_write_8(EA_AY_PD_8(), COND_CS() ? 0xff : 0); -} - - -void m68k_op_scs_8_pd7(void) -{ - m68ki_write_8(EA_A7_PD_8(), COND_CS() ? 0xff : 0); -} - - -void m68k_op_scs_8_di(void) -{ - m68ki_write_8(EA_AY_DI_8(), COND_CS() ? 0xff : 0); -} - - -void m68k_op_scs_8_ix(void) -{ - m68ki_write_8(EA_AY_IX_8(), COND_CS() ? 0xff : 0); -} - - -void m68k_op_scs_8_aw(void) -{ - m68ki_write_8(EA_AW_8(), COND_CS() ? 0xff : 0); -} - - -void m68k_op_scs_8_al(void) -{ - m68ki_write_8(EA_AL_8(), COND_CS() ? 0xff : 0); -} - - -void m68k_op_sne_8_ai(void) -{ - m68ki_write_8(EA_AY_AI_8(), COND_NE() ? 0xff : 0); -} - - -void m68k_op_sne_8_pi(void) -{ - m68ki_write_8(EA_AY_PI_8(), COND_NE() ? 0xff : 0); -} - - -void m68k_op_sne_8_pi7(void) -{ - m68ki_write_8(EA_A7_PI_8(), COND_NE() ? 0xff : 0); -} - - -void m68k_op_sne_8_pd(void) -{ - m68ki_write_8(EA_AY_PD_8(), COND_NE() ? 0xff : 0); -} - - -void m68k_op_sne_8_pd7(void) -{ - m68ki_write_8(EA_A7_PD_8(), COND_NE() ? 0xff : 0); -} - - -void m68k_op_sne_8_di(void) -{ - m68ki_write_8(EA_AY_DI_8(), COND_NE() ? 0xff : 0); -} - - -void m68k_op_sne_8_ix(void) -{ - m68ki_write_8(EA_AY_IX_8(), COND_NE() ? 0xff : 0); -} - - -void m68k_op_sne_8_aw(void) -{ - m68ki_write_8(EA_AW_8(), COND_NE() ? 0xff : 0); -} - - -void m68k_op_sne_8_al(void) -{ - m68ki_write_8(EA_AL_8(), COND_NE() ? 0xff : 0); -} - - -void m68k_op_seq_8_ai(void) -{ - m68ki_write_8(EA_AY_AI_8(), COND_EQ() ? 0xff : 0); -} - - -void m68k_op_seq_8_pi(void) -{ - m68ki_write_8(EA_AY_PI_8(), COND_EQ() ? 0xff : 0); -} - - -void m68k_op_seq_8_pi7(void) -{ - m68ki_write_8(EA_A7_PI_8(), COND_EQ() ? 0xff : 0); -} - - -void m68k_op_seq_8_pd(void) -{ - m68ki_write_8(EA_AY_PD_8(), COND_EQ() ? 0xff : 0); -} - - -void m68k_op_seq_8_pd7(void) -{ - m68ki_write_8(EA_A7_PD_8(), COND_EQ() ? 0xff : 0); -} - - -void m68k_op_seq_8_di(void) -{ - m68ki_write_8(EA_AY_DI_8(), COND_EQ() ? 0xff : 0); -} - - -void m68k_op_seq_8_ix(void) -{ - m68ki_write_8(EA_AY_IX_8(), COND_EQ() ? 0xff : 0); -} - - -void m68k_op_seq_8_aw(void) -{ - m68ki_write_8(EA_AW_8(), COND_EQ() ? 0xff : 0); -} - - -void m68k_op_seq_8_al(void) -{ - m68ki_write_8(EA_AL_8(), COND_EQ() ? 0xff : 0); -} - - -void m68k_op_svc_8_ai(void) -{ - m68ki_write_8(EA_AY_AI_8(), COND_VC() ? 0xff : 0); -} - - -void m68k_op_svc_8_pi(void) -{ - m68ki_write_8(EA_AY_PI_8(), COND_VC() ? 0xff : 0); -} - - -void m68k_op_svc_8_pi7(void) -{ - m68ki_write_8(EA_A7_PI_8(), COND_VC() ? 0xff : 0); -} - - -void m68k_op_svc_8_pd(void) -{ - m68ki_write_8(EA_AY_PD_8(), COND_VC() ? 0xff : 0); -} - - -void m68k_op_svc_8_pd7(void) -{ - m68ki_write_8(EA_A7_PD_8(), COND_VC() ? 0xff : 0); -} - - -void m68k_op_svc_8_di(void) -{ - m68ki_write_8(EA_AY_DI_8(), COND_VC() ? 0xff : 0); -} - - -void m68k_op_svc_8_ix(void) -{ - m68ki_write_8(EA_AY_IX_8(), COND_VC() ? 0xff : 0); -} - - -void m68k_op_svc_8_aw(void) -{ - m68ki_write_8(EA_AW_8(), COND_VC() ? 0xff : 0); -} - - -void m68k_op_svc_8_al(void) -{ - m68ki_write_8(EA_AL_8(), COND_VC() ? 0xff : 0); -} - - -void m68k_op_svs_8_ai(void) -{ - m68ki_write_8(EA_AY_AI_8(), COND_VS() ? 0xff : 0); -} - - -void m68k_op_svs_8_pi(void) -{ - m68ki_write_8(EA_AY_PI_8(), COND_VS() ? 0xff : 0); -} - - -void m68k_op_svs_8_pi7(void) -{ - m68ki_write_8(EA_A7_PI_8(), COND_VS() ? 0xff : 0); -} - - -void m68k_op_svs_8_pd(void) -{ - m68ki_write_8(EA_AY_PD_8(), COND_VS() ? 0xff : 0); -} - - -void m68k_op_svs_8_pd7(void) -{ - m68ki_write_8(EA_A7_PD_8(), COND_VS() ? 0xff : 0); -} - - -void m68k_op_svs_8_di(void) -{ - m68ki_write_8(EA_AY_DI_8(), COND_VS() ? 0xff : 0); -} - - -void m68k_op_svs_8_ix(void) -{ - m68ki_write_8(EA_AY_IX_8(), COND_VS() ? 0xff : 0); -} - - -void m68k_op_svs_8_aw(void) -{ - m68ki_write_8(EA_AW_8(), COND_VS() ? 0xff : 0); -} - - -void m68k_op_svs_8_al(void) -{ - m68ki_write_8(EA_AL_8(), COND_VS() ? 0xff : 0); -} - - -void m68k_op_spl_8_ai(void) -{ - m68ki_write_8(EA_AY_AI_8(), COND_PL() ? 0xff : 0); -} - - -void m68k_op_spl_8_pi(void) -{ - m68ki_write_8(EA_AY_PI_8(), COND_PL() ? 0xff : 0); -} - - -void m68k_op_spl_8_pi7(void) -{ - m68ki_write_8(EA_A7_PI_8(), COND_PL() ? 0xff : 0); -} - - -void m68k_op_spl_8_pd(void) -{ - m68ki_write_8(EA_AY_PD_8(), COND_PL() ? 0xff : 0); -} - - -void m68k_op_spl_8_pd7(void) -{ - m68ki_write_8(EA_A7_PD_8(), COND_PL() ? 0xff : 0); -} - - -void m68k_op_spl_8_di(void) -{ - m68ki_write_8(EA_AY_DI_8(), COND_PL() ? 0xff : 0); -} - - -void m68k_op_spl_8_ix(void) -{ - m68ki_write_8(EA_AY_IX_8(), COND_PL() ? 0xff : 0); -} - - -void m68k_op_spl_8_aw(void) -{ - m68ki_write_8(EA_AW_8(), COND_PL() ? 0xff : 0); -} - - -void m68k_op_spl_8_al(void) -{ - m68ki_write_8(EA_AL_8(), COND_PL() ? 0xff : 0); -} - - -void m68k_op_smi_8_ai(void) -{ - m68ki_write_8(EA_AY_AI_8(), COND_MI() ? 0xff : 0); -} - - -void m68k_op_smi_8_pi(void) -{ - m68ki_write_8(EA_AY_PI_8(), COND_MI() ? 0xff : 0); -} - - -void m68k_op_smi_8_pi7(void) -{ - m68ki_write_8(EA_A7_PI_8(), COND_MI() ? 0xff : 0); -} - - -void m68k_op_smi_8_pd(void) -{ - m68ki_write_8(EA_AY_PD_8(), COND_MI() ? 0xff : 0); -} - - -void m68k_op_smi_8_pd7(void) -{ - m68ki_write_8(EA_A7_PD_8(), COND_MI() ? 0xff : 0); -} - - -void m68k_op_smi_8_di(void) -{ - m68ki_write_8(EA_AY_DI_8(), COND_MI() ? 0xff : 0); -} - - -void m68k_op_smi_8_ix(void) -{ - m68ki_write_8(EA_AY_IX_8(), COND_MI() ? 0xff : 0); -} - - -void m68k_op_smi_8_aw(void) -{ - m68ki_write_8(EA_AW_8(), COND_MI() ? 0xff : 0); -} - - -void m68k_op_smi_8_al(void) -{ - m68ki_write_8(EA_AL_8(), COND_MI() ? 0xff : 0); -} - - -void m68k_op_sge_8_ai(void) -{ - m68ki_write_8(EA_AY_AI_8(), COND_GE() ? 0xff : 0); -} - - -void m68k_op_sge_8_pi(void) -{ - m68ki_write_8(EA_AY_PI_8(), COND_GE() ? 0xff : 0); -} - - -void m68k_op_sge_8_pi7(void) -{ - m68ki_write_8(EA_A7_PI_8(), COND_GE() ? 0xff : 0); -} - - -void m68k_op_sge_8_pd(void) -{ - m68ki_write_8(EA_AY_PD_8(), COND_GE() ? 0xff : 0); -} - - -void m68k_op_sge_8_pd7(void) -{ - m68ki_write_8(EA_A7_PD_8(), COND_GE() ? 0xff : 0); -} - - -void m68k_op_sge_8_di(void) -{ - m68ki_write_8(EA_AY_DI_8(), COND_GE() ? 0xff : 0); -} - - -void m68k_op_sge_8_ix(void) -{ - m68ki_write_8(EA_AY_IX_8(), COND_GE() ? 0xff : 0); -} - - -void m68k_op_sge_8_aw(void) -{ - m68ki_write_8(EA_AW_8(), COND_GE() ? 0xff : 0); -} - - -void m68k_op_sge_8_al(void) -{ - m68ki_write_8(EA_AL_8(), COND_GE() ? 0xff : 0); -} - - -void m68k_op_slt_8_ai(void) -{ - m68ki_write_8(EA_AY_AI_8(), COND_LT() ? 0xff : 0); -} - - -void m68k_op_slt_8_pi(void) -{ - m68ki_write_8(EA_AY_PI_8(), COND_LT() ? 0xff : 0); -} - - -void m68k_op_slt_8_pi7(void) -{ - m68ki_write_8(EA_A7_PI_8(), COND_LT() ? 0xff : 0); -} - - -void m68k_op_slt_8_pd(void) -{ - m68ki_write_8(EA_AY_PD_8(), COND_LT() ? 0xff : 0); -} - - -void m68k_op_slt_8_pd7(void) -{ - m68ki_write_8(EA_A7_PD_8(), COND_LT() ? 0xff : 0); -} - - -void m68k_op_slt_8_di(void) -{ - m68ki_write_8(EA_AY_DI_8(), COND_LT() ? 0xff : 0); -} - - -void m68k_op_slt_8_ix(void) -{ - m68ki_write_8(EA_AY_IX_8(), COND_LT() ? 0xff : 0); -} - - -void m68k_op_slt_8_aw(void) -{ - m68ki_write_8(EA_AW_8(), COND_LT() ? 0xff : 0); -} - - -void m68k_op_slt_8_al(void) -{ - m68ki_write_8(EA_AL_8(), COND_LT() ? 0xff : 0); -} - - -void m68k_op_sgt_8_ai(void) -{ - m68ki_write_8(EA_AY_AI_8(), COND_GT() ? 0xff : 0); -} - - -void m68k_op_sgt_8_pi(void) -{ - m68ki_write_8(EA_AY_PI_8(), COND_GT() ? 0xff : 0); -} - - -void m68k_op_sgt_8_pi7(void) -{ - m68ki_write_8(EA_A7_PI_8(), COND_GT() ? 0xff : 0); -} - - -void m68k_op_sgt_8_pd(void) -{ - m68ki_write_8(EA_AY_PD_8(), COND_GT() ? 0xff : 0); -} - - -void m68k_op_sgt_8_pd7(void) -{ - m68ki_write_8(EA_A7_PD_8(), COND_GT() ? 0xff : 0); -} - - -void m68k_op_sgt_8_di(void) -{ - m68ki_write_8(EA_AY_DI_8(), COND_GT() ? 0xff : 0); -} - - -void m68k_op_sgt_8_ix(void) -{ - m68ki_write_8(EA_AY_IX_8(), COND_GT() ? 0xff : 0); -} - - -void m68k_op_sgt_8_aw(void) -{ - m68ki_write_8(EA_AW_8(), COND_GT() ? 0xff : 0); -} - - -void m68k_op_sgt_8_al(void) -{ - m68ki_write_8(EA_AL_8(), COND_GT() ? 0xff : 0); -} - - -void m68k_op_sle_8_ai(void) -{ - m68ki_write_8(EA_AY_AI_8(), COND_LE() ? 0xff : 0); -} - - -void m68k_op_sle_8_pi(void) -{ - m68ki_write_8(EA_AY_PI_8(), COND_LE() ? 0xff : 0); -} - - -void m68k_op_sle_8_pi7(void) -{ - m68ki_write_8(EA_A7_PI_8(), COND_LE() ? 0xff : 0); -} - - -void m68k_op_sle_8_pd(void) -{ - m68ki_write_8(EA_AY_PD_8(), COND_LE() ? 0xff : 0); -} - - -void m68k_op_sle_8_pd7(void) -{ - m68ki_write_8(EA_A7_PD_8(), COND_LE() ? 0xff : 0); -} - - -void m68k_op_sle_8_di(void) -{ - m68ki_write_8(EA_AY_DI_8(), COND_LE() ? 0xff : 0); -} - - -void m68k_op_sle_8_ix(void) -{ - m68ki_write_8(EA_AY_IX_8(), COND_LE() ? 0xff : 0); -} - - -void m68k_op_sle_8_aw(void) -{ - m68ki_write_8(EA_AW_8(), COND_LE() ? 0xff : 0); -} - - -void m68k_op_sle_8_al(void) -{ - m68ki_write_8(EA_AL_8(), COND_LE() ? 0xff : 0); -} - - -void m68k_op_stop(void) -{ - if(FLAG_S) - { - uint new_sr = OPER_I_16(); - m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ - CPU_STOPPED |= STOP_LEVEL_STOP; - m68ki_set_sr(new_sr); - m68ki_remaining_cycles = 0; - return; - } - m68ki_exception_privilege_violation(); -} - - -void m68k_op_sub_8_er_d(void) -{ - uint* r_dst = &DX; - uint src = MASK_OUT_ABOVE_8(DY); - uint dst = MASK_OUT_ABOVE_8(*r_dst); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; -} - - -void m68k_op_sub_8_er_ai(void) -{ - uint* r_dst = &DX; - uint src = OPER_AY_AI_8(); - uint dst = MASK_OUT_ABOVE_8(*r_dst); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; -} - - -void m68k_op_sub_8_er_pi(void) -{ - uint* r_dst = &DX; - uint src = OPER_AY_PI_8(); - uint dst = MASK_OUT_ABOVE_8(*r_dst); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; -} - - -void m68k_op_sub_8_er_pi7(void) -{ - uint* r_dst = &DX; - uint src = OPER_A7_PI_8(); - uint dst = MASK_OUT_ABOVE_8(*r_dst); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; -} - - -void m68k_op_sub_8_er_pd(void) -{ - uint* r_dst = &DX; - uint src = OPER_AY_PD_8(); - uint dst = MASK_OUT_ABOVE_8(*r_dst); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; -} - - -void m68k_op_sub_8_er_pd7(void) -{ - uint* r_dst = &DX; - uint src = OPER_A7_PD_8(); - uint dst = MASK_OUT_ABOVE_8(*r_dst); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; -} - - -void m68k_op_sub_8_er_di(void) -{ - uint* r_dst = &DX; - uint src = OPER_AY_DI_8(); - uint dst = MASK_OUT_ABOVE_8(*r_dst); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; -} - - -void m68k_op_sub_8_er_ix(void) -{ - uint* r_dst = &DX; - uint src = OPER_AY_IX_8(); - uint dst = MASK_OUT_ABOVE_8(*r_dst); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; -} - - -void m68k_op_sub_8_er_aw(void) -{ - uint* r_dst = &DX; - uint src = OPER_AW_8(); - uint dst = MASK_OUT_ABOVE_8(*r_dst); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; -} - - -void m68k_op_sub_8_er_al(void) -{ - uint* r_dst = &DX; - uint src = OPER_AL_8(); - uint dst = MASK_OUT_ABOVE_8(*r_dst); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; -} - - -void m68k_op_sub_8_er_pcdi(void) -{ - uint* r_dst = &DX; - uint src = OPER_PCDI_8(); - uint dst = MASK_OUT_ABOVE_8(*r_dst); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; -} - - -void m68k_op_sub_8_er_pcix(void) -{ - uint* r_dst = &DX; - uint src = OPER_PCIX_8(); - uint dst = MASK_OUT_ABOVE_8(*r_dst); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; -} - - -void m68k_op_sub_8_er_i(void) -{ - uint* r_dst = &DX; - uint src = OPER_I_8(); - uint dst = MASK_OUT_ABOVE_8(*r_dst); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; -} - - -void m68k_op_sub_16_er_d(void) -{ - uint* r_dst = &DX; - uint src = MASK_OUT_ABOVE_16(DY); - uint dst = MASK_OUT_ABOVE_16(*r_dst); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; -} - - -void m68k_op_sub_16_er_a(void) -{ - uint* r_dst = &DX; - uint src = MASK_OUT_ABOVE_16(AY); - uint dst = MASK_OUT_ABOVE_16(*r_dst); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; -} - - -void m68k_op_sub_16_er_ai(void) -{ - uint* r_dst = &DX; - uint src = OPER_AY_AI_16(); - uint dst = MASK_OUT_ABOVE_16(*r_dst); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; -} - - -void m68k_op_sub_16_er_pi(void) -{ - uint* r_dst = &DX; - uint src = OPER_AY_PI_16(); - uint dst = MASK_OUT_ABOVE_16(*r_dst); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; -} - - -void m68k_op_sub_16_er_pd(void) -{ - uint* r_dst = &DX; - uint src = OPER_AY_PD_16(); - uint dst = MASK_OUT_ABOVE_16(*r_dst); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; -} - - -void m68k_op_sub_16_er_di(void) -{ - uint* r_dst = &DX; - uint src = OPER_AY_DI_16(); - uint dst = MASK_OUT_ABOVE_16(*r_dst); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; -} - - -void m68k_op_sub_16_er_ix(void) -{ - uint* r_dst = &DX; - uint src = OPER_AY_IX_16(); - uint dst = MASK_OUT_ABOVE_16(*r_dst); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; -} - - -void m68k_op_sub_16_er_aw(void) -{ - uint* r_dst = &DX; - uint src = OPER_AW_16(); - uint dst = MASK_OUT_ABOVE_16(*r_dst); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; -} - - -void m68k_op_sub_16_er_al(void) -{ - uint* r_dst = &DX; - uint src = OPER_AL_16(); - uint dst = MASK_OUT_ABOVE_16(*r_dst); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; -} - - -void m68k_op_sub_16_er_pcdi(void) -{ - uint* r_dst = &DX; - uint src = OPER_PCDI_16(); - uint dst = MASK_OUT_ABOVE_16(*r_dst); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; -} - - -void m68k_op_sub_16_er_pcix(void) -{ - uint* r_dst = &DX; - uint src = OPER_PCIX_16(); - uint dst = MASK_OUT_ABOVE_16(*r_dst); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; -} - - -void m68k_op_sub_16_er_i(void) -{ - uint* r_dst = &DX; - uint src = OPER_I_16(); - uint dst = MASK_OUT_ABOVE_16(*r_dst); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; -} - - -void m68k_op_sub_32_er_d(void) -{ - uint* r_dst = &DX; - uint src = DY; - uint dst = *r_dst; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - *r_dst = FLAG_Z; -} - - -void m68k_op_sub_32_er_a(void) -{ - uint* r_dst = &DX; - uint src = AY; - uint dst = *r_dst; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - *r_dst = FLAG_Z; -} - - -void m68k_op_sub_32_er_ai(void) -{ - uint* r_dst = &DX; - uint src = OPER_AY_AI_32(); - uint dst = *r_dst; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - *r_dst = FLAG_Z; -} - - -void m68k_op_sub_32_er_pi(void) -{ - uint* r_dst = &DX; - uint src = OPER_AY_PI_32(); - uint dst = *r_dst; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - *r_dst = FLAG_Z; -} - - -void m68k_op_sub_32_er_pd(void) -{ - uint* r_dst = &DX; - uint src = OPER_AY_PD_32(); - uint dst = *r_dst; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - *r_dst = FLAG_Z; -} - - -void m68k_op_sub_32_er_di(void) -{ - uint* r_dst = &DX; - uint src = OPER_AY_DI_32(); - uint dst = *r_dst; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - *r_dst = FLAG_Z; -} - - -void m68k_op_sub_32_er_ix(void) -{ - uint* r_dst = &DX; - uint src = OPER_AY_IX_32(); - uint dst = *r_dst; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - *r_dst = FLAG_Z; -} - - -void m68k_op_sub_32_er_aw(void) -{ - uint* r_dst = &DX; - uint src = OPER_AW_32(); - uint dst = *r_dst; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - *r_dst = FLAG_Z; -} - - -void m68k_op_sub_32_er_al(void) -{ - uint* r_dst = &DX; - uint src = OPER_AL_32(); - uint dst = *r_dst; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - *r_dst = FLAG_Z; -} - - -void m68k_op_sub_32_er_pcdi(void) -{ - uint* r_dst = &DX; - uint src = OPER_PCDI_32(); - uint dst = *r_dst; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - *r_dst = FLAG_Z; -} - - -void m68k_op_sub_32_er_pcix(void) -{ - uint* r_dst = &DX; - uint src = OPER_PCIX_32(); - uint dst = *r_dst; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - *r_dst = FLAG_Z; -} - - -void m68k_op_sub_32_er_i(void) -{ - uint* r_dst = &DX; - uint src = OPER_I_32(); - uint dst = *r_dst; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - - *r_dst = FLAG_Z; -} - - -void m68k_op_sub_8_re_ai(void) -{ - uint ea = EA_AY_AI_8(); - uint src = MASK_OUT_ABOVE_8(DX); - uint dst = m68ki_read_8(ea); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_sub_8_re_pi(void) -{ - uint ea = EA_AY_PI_8(); - uint src = MASK_OUT_ABOVE_8(DX); - uint dst = m68ki_read_8(ea); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_sub_8_re_pi7(void) -{ - uint ea = EA_A7_PI_8(); - uint src = MASK_OUT_ABOVE_8(DX); - uint dst = m68ki_read_8(ea); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_sub_8_re_pd(void) -{ - uint ea = EA_AY_PD_8(); - uint src = MASK_OUT_ABOVE_8(DX); - uint dst = m68ki_read_8(ea); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_sub_8_re_pd7(void) -{ - uint ea = EA_A7_PD_8(); - uint src = MASK_OUT_ABOVE_8(DX); - uint dst = m68ki_read_8(ea); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_sub_8_re_di(void) -{ - uint ea = EA_AY_DI_8(); - uint src = MASK_OUT_ABOVE_8(DX); - uint dst = m68ki_read_8(ea); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_sub_8_re_ix(void) -{ - uint ea = EA_AY_IX_8(); - uint src = MASK_OUT_ABOVE_8(DX); - uint dst = m68ki_read_8(ea); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_sub_8_re_aw(void) -{ - uint ea = EA_AW_8(); - uint src = MASK_OUT_ABOVE_8(DX); - uint dst = m68ki_read_8(ea); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_sub_8_re_al(void) -{ - uint ea = EA_AL_8(); - uint src = MASK_OUT_ABOVE_8(DX); - uint dst = m68ki_read_8(ea); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_sub_16_re_ai(void) -{ - uint ea = EA_AY_AI_16(); - uint src = MASK_OUT_ABOVE_16(DX); - uint dst = m68ki_read_16(ea); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - - m68ki_write_16(ea, FLAG_Z); -} - - -void m68k_op_sub_16_re_pi(void) -{ - uint ea = EA_AY_PI_16(); - uint src = MASK_OUT_ABOVE_16(DX); - uint dst = m68ki_read_16(ea); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - - m68ki_write_16(ea, FLAG_Z); -} - - -void m68k_op_sub_16_re_pd(void) -{ - uint ea = EA_AY_PD_16(); - uint src = MASK_OUT_ABOVE_16(DX); - uint dst = m68ki_read_16(ea); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - - m68ki_write_16(ea, FLAG_Z); -} - - -void m68k_op_sub_16_re_di(void) -{ - uint ea = EA_AY_DI_16(); - uint src = MASK_OUT_ABOVE_16(DX); - uint dst = m68ki_read_16(ea); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - - m68ki_write_16(ea, FLAG_Z); -} - - -void m68k_op_sub_16_re_ix(void) -{ - uint ea = EA_AY_IX_16(); - uint src = MASK_OUT_ABOVE_16(DX); - uint dst = m68ki_read_16(ea); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - - m68ki_write_16(ea, FLAG_Z); -} - - -void m68k_op_sub_16_re_aw(void) -{ - uint ea = EA_AW_16(); - uint src = MASK_OUT_ABOVE_16(DX); - uint dst = m68ki_read_16(ea); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - - m68ki_write_16(ea, FLAG_Z); -} - - -void m68k_op_sub_16_re_al(void) -{ - uint ea = EA_AL_16(); - uint src = MASK_OUT_ABOVE_16(DX); - uint dst = m68ki_read_16(ea); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - - m68ki_write_16(ea, FLAG_Z); -} - - -void m68k_op_sub_32_re_ai(void) -{ - uint ea = EA_AY_AI_32(); - uint src = DX; - uint dst = m68ki_read_32(ea); - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - - m68ki_write_32(ea, FLAG_Z); -} - - -void m68k_op_sub_32_re_pi(void) -{ - uint ea = EA_AY_PI_32(); - uint src = DX; - uint dst = m68ki_read_32(ea); - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - - m68ki_write_32(ea, FLAG_Z); -} - - -void m68k_op_sub_32_re_pd(void) -{ - uint ea = EA_AY_PD_32(); - uint src = DX; - uint dst = m68ki_read_32(ea); - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - - m68ki_write_32(ea, FLAG_Z); -} - - -void m68k_op_sub_32_re_di(void) -{ - uint ea = EA_AY_DI_32(); - uint src = DX; - uint dst = m68ki_read_32(ea); - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - - m68ki_write_32(ea, FLAG_Z); -} - - -void m68k_op_sub_32_re_ix(void) -{ - uint ea = EA_AY_IX_32(); - uint src = DX; - uint dst = m68ki_read_32(ea); - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - - m68ki_write_32(ea, FLAG_Z); -} - - -void m68k_op_sub_32_re_aw(void) -{ - uint ea = EA_AW_32(); - uint src = DX; - uint dst = m68ki_read_32(ea); - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - - m68ki_write_32(ea, FLAG_Z); -} - - -void m68k_op_sub_32_re_al(void) -{ - uint ea = EA_AL_32(); - uint src = DX; - uint dst = m68ki_read_32(ea); - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - - m68ki_write_32(ea, FLAG_Z); -} - - -void m68k_op_suba_16_d(void) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(DY)); -} - - -void m68k_op_suba_16_a(void) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(AY)); -} - - -void m68k_op_suba_16_ai(void) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(OPER_AY_AI_16())); -} - - -void m68k_op_suba_16_pi(void) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(OPER_AY_PI_16())); -} - - -void m68k_op_suba_16_pd(void) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(OPER_AY_PD_16())); -} - - -void m68k_op_suba_16_di(void) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(OPER_AY_DI_16())); -} - - -void m68k_op_suba_16_ix(void) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(OPER_AY_IX_16())); -} - - -void m68k_op_suba_16_aw(void) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(OPER_AW_16())); -} - - -void m68k_op_suba_16_al(void) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(OPER_AL_16())); -} - - -void m68k_op_suba_16_pcdi(void) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(OPER_PCDI_16())); -} - - -void m68k_op_suba_16_pcix(void) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(OPER_PCIX_16())); -} - - -void m68k_op_suba_16_i(void) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(OPER_I_16())); -} - - -void m68k_op_suba_32_d(void) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst - DY); -} - - -void m68k_op_suba_32_a(void) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst - AY); -} - - -void m68k_op_suba_32_ai(void) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst - OPER_AY_AI_32()); -} - - -void m68k_op_suba_32_pi(void) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst - OPER_AY_PI_32()); -} - - -void m68k_op_suba_32_pd(void) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst - OPER_AY_PD_32()); -} - - -void m68k_op_suba_32_di(void) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst - OPER_AY_DI_32()); -} - - -void m68k_op_suba_32_ix(void) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst - OPER_AY_IX_32()); -} - - -void m68k_op_suba_32_aw(void) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst - OPER_AW_32()); -} - - -void m68k_op_suba_32_al(void) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst - OPER_AL_32()); -} - - -void m68k_op_suba_32_pcdi(void) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst - OPER_PCDI_32()); -} - - -void m68k_op_suba_32_pcix(void) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst - OPER_PCIX_32()); -} - - -void m68k_op_suba_32_i(void) -{ - uint* r_dst = &AX; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst - OPER_I_32()); -} - - -void m68k_op_subi_8_d(void) -{ - uint* r_dst = &DY; - uint src = OPER_I_8(); - uint dst = MASK_OUT_ABOVE_8(*r_dst); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; -} - - -void m68k_op_subi_8_ai(void) -{ - uint src = OPER_I_8(); - uint ea = EA_AY_AI_8(); - uint dst = m68ki_read_8(ea); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_subi_8_pi(void) -{ - uint src = OPER_I_8(); - uint ea = EA_AY_PI_8(); - uint dst = m68ki_read_8(ea); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_subi_8_pi7(void) -{ - uint src = OPER_I_8(); - uint ea = EA_A7_PI_8(); - uint dst = m68ki_read_8(ea); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_subi_8_pd(void) -{ - uint src = OPER_I_8(); - uint ea = EA_AY_PD_8(); - uint dst = m68ki_read_8(ea); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_subi_8_pd7(void) -{ - uint src = OPER_I_8(); - uint ea = EA_A7_PD_8(); - uint dst = m68ki_read_8(ea); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_subi_8_di(void) -{ - uint src = OPER_I_8(); - uint ea = EA_AY_DI_8(); - uint dst = m68ki_read_8(ea); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_subi_8_ix(void) -{ - uint src = OPER_I_8(); - uint ea = EA_AY_IX_8(); - uint dst = m68ki_read_8(ea); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_subi_8_aw(void) -{ - uint src = OPER_I_8(); - uint ea = EA_AW_8(); - uint dst = m68ki_read_8(ea); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_subi_8_al(void) -{ - uint src = OPER_I_8(); - uint ea = EA_AL_8(); - uint dst = m68ki_read_8(ea); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_subi_16_d(void) -{ - uint* r_dst = &DY; - uint src = OPER_I_16(); - uint dst = MASK_OUT_ABOVE_16(*r_dst); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; -} - - -void m68k_op_subi_16_ai(void) -{ - uint src = OPER_I_16(); - uint ea = EA_AY_AI_16(); - uint dst = m68ki_read_16(ea); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - - m68ki_write_16(ea, FLAG_Z); -} - - -void m68k_op_subi_16_pi(void) -{ - uint src = OPER_I_16(); - uint ea = EA_AY_PI_16(); - uint dst = m68ki_read_16(ea); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - - m68ki_write_16(ea, FLAG_Z); -} - - -void m68k_op_subi_16_pd(void) -{ - uint src = OPER_I_16(); - uint ea = EA_AY_PD_16(); - uint dst = m68ki_read_16(ea); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - - m68ki_write_16(ea, FLAG_Z); -} - - -void m68k_op_subi_16_di(void) -{ - uint src = OPER_I_16(); - uint ea = EA_AY_DI_16(); - uint dst = m68ki_read_16(ea); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - - m68ki_write_16(ea, FLAG_Z); -} - - -void m68k_op_subi_16_ix(void) -{ - uint src = OPER_I_16(); - uint ea = EA_AY_IX_16(); - uint dst = m68ki_read_16(ea); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - - m68ki_write_16(ea, FLAG_Z); -} - - -void m68k_op_subi_16_aw(void) -{ - uint src = OPER_I_16(); - uint ea = EA_AW_16(); - uint dst = m68ki_read_16(ea); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - - m68ki_write_16(ea, FLAG_Z); -} - - -void m68k_op_subi_16_al(void) -{ - uint src = OPER_I_16(); - uint ea = EA_AL_16(); - uint dst = m68ki_read_16(ea); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - - m68ki_write_16(ea, FLAG_Z); -} - - -void m68k_op_subi_32_d(void) -{ - uint* r_dst = &DY; - uint src = OPER_I_32(); - uint dst = *r_dst; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - - *r_dst = FLAG_Z; -} - - -void m68k_op_subi_32_ai(void) -{ - uint src = OPER_I_32(); - uint ea = EA_AY_AI_32(); - uint dst = m68ki_read_32(ea); - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - - m68ki_write_32(ea, FLAG_Z); -} - - -void m68k_op_subi_32_pi(void) -{ - uint src = OPER_I_32(); - uint ea = EA_AY_PI_32(); - uint dst = m68ki_read_32(ea); - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - - m68ki_write_32(ea, FLAG_Z); -} - - -void m68k_op_subi_32_pd(void) -{ - uint src = OPER_I_32(); - uint ea = EA_AY_PD_32(); - uint dst = m68ki_read_32(ea); - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - - m68ki_write_32(ea, FLAG_Z); -} - - -void m68k_op_subi_32_di(void) -{ - uint src = OPER_I_32(); - uint ea = EA_AY_DI_32(); - uint dst = m68ki_read_32(ea); - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - - m68ki_write_32(ea, FLAG_Z); -} - - -void m68k_op_subi_32_ix(void) -{ - uint src = OPER_I_32(); - uint ea = EA_AY_IX_32(); - uint dst = m68ki_read_32(ea); - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - - m68ki_write_32(ea, FLAG_Z); -} - - -void m68k_op_subi_32_aw(void) -{ - uint src = OPER_I_32(); - uint ea = EA_AW_32(); - uint dst = m68ki_read_32(ea); - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - - m68ki_write_32(ea, FLAG_Z); -} - - -void m68k_op_subi_32_al(void) -{ - uint src = OPER_I_32(); - uint ea = EA_AL_32(); - uint dst = m68ki_read_32(ea); - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - - m68ki_write_32(ea, FLAG_Z); -} - - -void m68k_op_subq_8_d(void) -{ - uint* r_dst = &DY; - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint dst = MASK_OUT_ABOVE_8(*r_dst); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; -} - - -void m68k_op_subq_8_ai(void) -{ - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint ea = EA_AY_AI_8(); - uint dst = m68ki_read_8(ea); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_subq_8_pi(void) -{ - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint ea = EA_AY_PI_8(); - uint dst = m68ki_read_8(ea); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_subq_8_pi7(void) -{ - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint ea = EA_A7_PI_8(); - uint dst = m68ki_read_8(ea); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_subq_8_pd(void) -{ - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint ea = EA_AY_PD_8(); - uint dst = m68ki_read_8(ea); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_subq_8_pd7(void) -{ - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint ea = EA_A7_PD_8(); - uint dst = m68ki_read_8(ea); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_subq_8_di(void) -{ - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint ea = EA_AY_DI_8(); - uint dst = m68ki_read_8(ea); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_subq_8_ix(void) -{ - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint ea = EA_AY_IX_8(); - uint dst = m68ki_read_8(ea); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_subq_8_aw(void) -{ - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint ea = EA_AW_8(); - uint dst = m68ki_read_8(ea); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_subq_8_al(void) -{ - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint ea = EA_AL_8(); - uint dst = m68ki_read_8(ea); - uint res = dst - src; - - FLAG_N = NFLAG_8(res); - FLAG_Z = MASK_OUT_ABOVE_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - - m68ki_write_8(ea, FLAG_Z); -} - - -void m68k_op_subq_16_d(void) -{ - uint* r_dst = &DY; - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint dst = MASK_OUT_ABOVE_16(*r_dst); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; -} - - -void m68k_op_subq_16_a(void) -{ - uint* r_dst = &AY; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1)); -} - - -void m68k_op_subq_16_ai(void) -{ - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint ea = EA_AY_AI_16(); - uint dst = m68ki_read_16(ea); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - - m68ki_write_16(ea, FLAG_Z); -} - - -void m68k_op_subq_16_pi(void) -{ - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint ea = EA_AY_PI_16(); - uint dst = m68ki_read_16(ea); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - - m68ki_write_16(ea, FLAG_Z); -} - - -void m68k_op_subq_16_pd(void) -{ - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint ea = EA_AY_PD_16(); - uint dst = m68ki_read_16(ea); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - - m68ki_write_16(ea, FLAG_Z); -} - - -void m68k_op_subq_16_di(void) -{ - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint ea = EA_AY_DI_16(); - uint dst = m68ki_read_16(ea); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - - m68ki_write_16(ea, FLAG_Z); -} - - -void m68k_op_subq_16_ix(void) -{ - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint ea = EA_AY_IX_16(); - uint dst = m68ki_read_16(ea); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - - m68ki_write_16(ea, FLAG_Z); -} - - -void m68k_op_subq_16_aw(void) -{ - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint ea = EA_AW_16(); - uint dst = m68ki_read_16(ea); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - - m68ki_write_16(ea, FLAG_Z); -} - - -void m68k_op_subq_16_al(void) -{ - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint ea = EA_AL_16(); - uint dst = m68ki_read_16(ea); - uint res = dst - src; - - FLAG_N = NFLAG_16(res); - FLAG_Z = MASK_OUT_ABOVE_16(res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - - m68ki_write_16(ea, FLAG_Z); -} - - -void m68k_op_subq_32_d(void) -{ - uint* r_dst = &DY; - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint dst = *r_dst; - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - - *r_dst = FLAG_Z; -} - - -void m68k_op_subq_32_a(void) -{ - uint* r_dst = &AY; - - *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1)); -} - - -void m68k_op_subq_32_ai(void) -{ - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint ea = EA_AY_AI_32(); - uint dst = m68ki_read_32(ea); - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - - m68ki_write_32(ea, FLAG_Z); -} - - -void m68k_op_subq_32_pi(void) -{ - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint ea = EA_AY_PI_32(); - uint dst = m68ki_read_32(ea); - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - - m68ki_write_32(ea, FLAG_Z); -} - - -void m68k_op_subq_32_pd(void) -{ - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint ea = EA_AY_PD_32(); - uint dst = m68ki_read_32(ea); - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - - m68ki_write_32(ea, FLAG_Z); -} - - -void m68k_op_subq_32_di(void) -{ - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint ea = EA_AY_DI_32(); - uint dst = m68ki_read_32(ea); - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - - m68ki_write_32(ea, FLAG_Z); -} - - -void m68k_op_subq_32_ix(void) -{ - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint ea = EA_AY_IX_32(); - uint dst = m68ki_read_32(ea); - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - - m68ki_write_32(ea, FLAG_Z); -} - - -void m68k_op_subq_32_aw(void) -{ - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint ea = EA_AW_32(); - uint dst = m68ki_read_32(ea); - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - - m68ki_write_32(ea, FLAG_Z); -} - - -void m68k_op_subq_32_al(void) -{ - uint src = (((REG_IR >> 9) - 1) & 7) + 1; - uint ea = EA_AL_32(); - uint dst = m68ki_read_32(ea); - uint res = dst - src; - - FLAG_N = NFLAG_32(res); - FLAG_Z = MASK_OUT_ABOVE_32(res); - FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - - m68ki_write_32(ea, FLAG_Z); -} - - -void m68k_op_subx_8_rr(void) -{ - uint* r_dst = &DX; - uint src = MASK_OUT_ABOVE_8(DY); - uint dst = MASK_OUT_ABOVE_8(*r_dst); - uint res = dst - src - XFLAG_AS_1(); - - FLAG_N = NFLAG_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - - res = MASK_OUT_ABOVE_8(res); - FLAG_Z |= res; - - *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; -} - - -void m68k_op_subx_16_rr(void) -{ - uint* r_dst = &DX; - uint src = MASK_OUT_ABOVE_16(DY); - uint dst = MASK_OUT_ABOVE_16(*r_dst); - uint res = dst - src - XFLAG_AS_1(); - - FLAG_N = NFLAG_16(res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - - res = MASK_OUT_ABOVE_16(res); - FLAG_Z |= res; - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; -} - - -void m68k_op_subx_32_rr(void) -{ - uint* r_dst = &DX; - uint src = DY; - uint dst = *r_dst; - uint res = dst - src - XFLAG_AS_1(); - - FLAG_N = NFLAG_32(res); - FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - - res = MASK_OUT_ABOVE_32(res); - FLAG_Z |= res; - - *r_dst = res; -} - - -void m68k_op_subx_8_mm_ax7(void) -{ - uint src = OPER_AY_PD_8(); - uint ea = EA_A7_PD_8(); - uint dst = m68ki_read_8(ea); - uint res = dst - src - XFLAG_AS_1(); - - FLAG_N = NFLAG_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - - res = MASK_OUT_ABOVE_8(res); - FLAG_Z |= res; - - m68ki_write_8(ea, res); -} - - -void m68k_op_subx_8_mm_ay7(void) -{ - uint src = OPER_A7_PD_8(); - uint ea = EA_AX_PD_8(); - uint dst = m68ki_read_8(ea); - uint res = dst - src - XFLAG_AS_1(); - - FLAG_N = NFLAG_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - - res = MASK_OUT_ABOVE_8(res); - FLAG_Z |= res; - - m68ki_write_8(ea, res); -} - - -void m68k_op_subx_8_mm_axy7(void) -{ - uint src = OPER_A7_PD_8(); - uint ea = EA_A7_PD_8(); - uint dst = m68ki_read_8(ea); - uint res = dst - src - XFLAG_AS_1(); - - FLAG_N = NFLAG_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - - res = MASK_OUT_ABOVE_8(res); - FLAG_Z |= res; - - m68ki_write_8(ea, res); -} - - -void m68k_op_subx_8_mm(void) -{ - uint src = OPER_AY_PD_8(); - uint ea = EA_AX_PD_8(); - uint dst = m68ki_read_8(ea); - uint res = dst - src - XFLAG_AS_1(); - - FLAG_N = NFLAG_8(res); - FLAG_X = FLAG_C = CFLAG_8(res); - FLAG_V = VFLAG_SUB_8(src, dst, res); - - res = MASK_OUT_ABOVE_8(res); - FLAG_Z |= res; - - m68ki_write_8(ea, res); -} - - -void m68k_op_subx_16_mm(void) -{ - uint src = OPER_AY_PD_16(); - uint ea = EA_AX_PD_16(); - uint dst = m68ki_read_16(ea); - uint res = dst - src - XFLAG_AS_1(); - - FLAG_N = NFLAG_16(res); - FLAG_X = FLAG_C = CFLAG_16(res); - FLAG_V = VFLAG_SUB_16(src, dst, res); - - res = MASK_OUT_ABOVE_16(res); - FLAG_Z |= res; - - m68ki_write_16(ea, res); -} - - -void m68k_op_subx_32_mm(void) -{ - uint src = OPER_AY_PD_32(); - uint ea = EA_AX_PD_32(); - uint dst = m68ki_read_32(ea); - uint res = dst - src - XFLAG_AS_1(); - - FLAG_N = NFLAG_32(res); - FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); - FLAG_V = VFLAG_SUB_32(src, dst, res); - - res = MASK_OUT_ABOVE_32(res); - FLAG_Z |= res; - - m68ki_write_32(ea, res); -} - - -void m68k_op_swap_32(void) -{ - uint* r_dst = &DY; - - FLAG_Z = MASK_OUT_ABOVE_32(*r_dst<<16); - *r_dst = (*r_dst>>16) | FLAG_Z; - - FLAG_Z = *r_dst; - FLAG_N = NFLAG_32(*r_dst); - FLAG_C = CFLAG_CLEAR; - FLAG_V = VFLAG_CLEAR; -} - - -void m68k_op_tas_8_d(void) -{ - uint* r_dst = &DY; - - FLAG_Z = MASK_OUT_ABOVE_8(*r_dst); - FLAG_N = NFLAG_8(*r_dst); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - *r_dst |= 0x80; -} - - -void m68k_op_tas_8_ai(void) -{ - uint ea = EA_AY_AI_8(); - uint dst = m68ki_read_8(ea); - - FLAG_Z = dst; - FLAG_N = NFLAG_8(dst); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - m68ki_write_8(ea, dst | 0x80); -} - - -void m68k_op_tas_8_pi(void) -{ - uint ea = EA_AY_PI_8(); - uint dst = m68ki_read_8(ea); - - FLAG_Z = dst; - FLAG_N = NFLAG_8(dst); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - m68ki_write_8(ea, dst | 0x80); -} - - -void m68k_op_tas_8_pi7(void) -{ - uint ea = EA_A7_PI_8(); - uint dst = m68ki_read_8(ea); - - FLAG_Z = dst; - FLAG_N = NFLAG_8(dst); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - m68ki_write_8(ea, dst | 0x80); -} - - -void m68k_op_tas_8_pd(void) -{ - uint ea = EA_AY_PD_8(); - uint dst = m68ki_read_8(ea); - - FLAG_Z = dst; - FLAG_N = NFLAG_8(dst); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - m68ki_write_8(ea, dst | 0x80); -} - - -void m68k_op_tas_8_pd7(void) -{ - uint ea = EA_A7_PD_8(); - uint dst = m68ki_read_8(ea); - - FLAG_Z = dst; - FLAG_N = NFLAG_8(dst); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - m68ki_write_8(ea, dst | 0x80); -} - - -void m68k_op_tas_8_di(void) -{ - uint ea = EA_AY_DI_8(); - uint dst = m68ki_read_8(ea); - - FLAG_Z = dst; - FLAG_N = NFLAG_8(dst); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - m68ki_write_8(ea, dst | 0x80); -} - - -void m68k_op_tas_8_ix(void) -{ - uint ea = EA_AY_IX_8(); - uint dst = m68ki_read_8(ea); - - FLAG_Z = dst; - FLAG_N = NFLAG_8(dst); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - m68ki_write_8(ea, dst | 0x80); -} - - -void m68k_op_tas_8_aw(void) -{ - uint ea = EA_AW_8(); - uint dst = m68ki_read_8(ea); - - FLAG_Z = dst; - FLAG_N = NFLAG_8(dst); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - m68ki_write_8(ea, dst | 0x80); -} - - -void m68k_op_tas_8_al(void) -{ - uint ea = EA_AL_8(); - uint dst = m68ki_read_8(ea); - - FLAG_Z = dst; - FLAG_N = NFLAG_8(dst); - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - m68ki_write_8(ea, dst | 0x80); -} - - -void m68k_op_trap(void) -{ - /* Trap#n stacks exception frame type 0 */ - m68ki_exception_trapN(EXCEPTION_TRAP_BASE + (REG_IR & 0xf)); /* HJB 990403 */ -} - - -void m68k_op_trapt(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_trapt_16(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_trapt_32(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_trapf(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_trapf_16(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - REG_PC += 2; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_trapf_32(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - REG_PC += 4; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_traphi(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(COND_HI()) - m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_trapls(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(COND_LS()) - m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_trapcc(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(COND_CC()) - m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_trapcs(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(COND_CS()) - m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_trapne(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(COND_NE()) - m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_trapeq(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(COND_EQ()) - m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_trapvc(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(COND_VC()) - m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_trapvs(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(COND_VS()) - m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_trappl(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(COND_PL()) - m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_trapmi(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(COND_MI()) - m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_trapge(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(COND_GE()) - m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_traplt(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(COND_LT()) - m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_trapgt(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(COND_GT()) - m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_traple(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(COND_LE()) - m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_traphi_16(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(COND_HI()) - { - m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ - return; - } - REG_PC += 2; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_trapls_16(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(COND_LS()) - { - m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ - return; - } - REG_PC += 2; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_trapcc_16(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(COND_CC()) - { - m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ - return; - } - REG_PC += 2; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_trapcs_16(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(COND_CS()) - { - m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ - return; - } - REG_PC += 2; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_trapne_16(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(COND_NE()) - { - m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ - return; - } - REG_PC += 2; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_trapeq_16(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(COND_EQ()) - { - m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ - return; - } - REG_PC += 2; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_trapvc_16(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(COND_VC()) - { - m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ - return; - } - REG_PC += 2; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_trapvs_16(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(COND_VS()) - { - m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ - return; - } - REG_PC += 2; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_trappl_16(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(COND_PL()) - { - m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ - return; - } - REG_PC += 2; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_trapmi_16(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(COND_MI()) - { - m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ - return; - } - REG_PC += 2; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_trapge_16(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(COND_GE()) - { - m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ - return; - } - REG_PC += 2; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_traplt_16(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(COND_LT()) - { - m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ - return; - } - REG_PC += 2; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_trapgt_16(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(COND_GT()) - { - m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ - return; - } - REG_PC += 2; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_traple_16(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(COND_LE()) - { - m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ - return; - } - REG_PC += 2; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_traphi_32(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(COND_HI()) - { - m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ - return; - } - REG_PC += 4; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_trapls_32(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(COND_LS()) - { - m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ - return; - } - REG_PC += 4; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_trapcc_32(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(COND_CC()) - { - m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ - return; - } - REG_PC += 4; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_trapcs_32(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(COND_CS()) - { - m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ - return; - } - REG_PC += 4; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_trapne_32(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(COND_NE()) - { - m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ - return; - } - REG_PC += 4; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_trapeq_32(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(COND_EQ()) - { - m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ - return; - } - REG_PC += 4; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_trapvc_32(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(COND_VC()) - { - m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ - return; - } - REG_PC += 4; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_trapvs_32(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(COND_VS()) - { - m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ - return; - } - REG_PC += 4; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_trappl_32(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(COND_PL()) - { - m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ - return; - } - REG_PC += 4; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_trapmi_32(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(COND_MI()) - { - m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ - return; - } - REG_PC += 4; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_trapge_32(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(COND_GE()) - { - m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ - return; - } - REG_PC += 4; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_traplt_32(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(COND_LT()) - { - m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ - return; - } - REG_PC += 4; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_trapgt_32(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(COND_GT()) - { - m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ - return; - } - REG_PC += 4; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_traple_32(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - if(COND_LE()) - { - m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ - return; - } - REG_PC += 4; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_trapv(void) -{ - if(COND_VC()) - { - return; - } - m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ -} - - -void m68k_op_tst_8_d(void) -{ - uint res = MASK_OUT_ABOVE_8(DY); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_tst_8_ai(void) -{ - uint res = OPER_AY_AI_8(); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_tst_8_pi(void) -{ - uint res = OPER_AY_PI_8(); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_tst_8_pi7(void) -{ - uint res = OPER_A7_PI_8(); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_tst_8_pd(void) -{ - uint res = OPER_AY_PD_8(); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_tst_8_pd7(void) -{ - uint res = OPER_A7_PD_8(); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_tst_8_di(void) -{ - uint res = OPER_AY_DI_8(); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_tst_8_ix(void) -{ - uint res = OPER_AY_IX_8(); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_tst_8_aw(void) -{ - uint res = OPER_AW_8(); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_tst_8_al(void) -{ - uint res = OPER_AL_8(); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_tst_8_pcdi(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint res = OPER_PCDI_8(); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_tst_8_pcix(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint res = OPER_PCIX_8(); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_tst_8_i(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint res = OPER_I_8(); - - FLAG_N = NFLAG_8(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_tst_16_d(void) -{ - uint res = MASK_OUT_ABOVE_16(DY); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_tst_16_a(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint res = MAKE_INT_16(AY); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_tst_16_ai(void) -{ - uint res = OPER_AY_AI_16(); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_tst_16_pi(void) -{ - uint res = OPER_AY_PI_16(); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_tst_16_pd(void) -{ - uint res = OPER_AY_PD_16(); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_tst_16_di(void) -{ - uint res = OPER_AY_DI_16(); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_tst_16_ix(void) -{ - uint res = OPER_AY_IX_16(); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_tst_16_aw(void) -{ - uint res = OPER_AW_16(); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_tst_16_al(void) -{ - uint res = OPER_AL_16(); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_tst_16_pcdi(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint res = OPER_PCDI_16(); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_tst_16_pcix(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint res = OPER_PCIX_16(); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_tst_16_i(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint res = OPER_I_16(); - - FLAG_N = NFLAG_16(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_tst_32_d(void) -{ - uint res = DY; - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_tst_32_a(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint res = AY; - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_tst_32_ai(void) -{ - uint res = OPER_AY_AI_32(); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_tst_32_pi(void) -{ - uint res = OPER_AY_PI_32(); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_tst_32_pd(void) -{ - uint res = OPER_AY_PD_32(); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_tst_32_di(void) -{ - uint res = OPER_AY_DI_32(); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_tst_32_ix(void) -{ - uint res = OPER_AY_IX_32(); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_tst_32_aw(void) -{ - uint res = OPER_AW_32(); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_tst_32_al(void) -{ - uint res = OPER_AL_32(); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; -} - - -void m68k_op_tst_32_pcdi(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint res = OPER_PCDI_32(); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_tst_32_pcix(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint res = OPER_PCIX_32(); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_tst_32_i(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint res = OPER_I_32(); - - FLAG_N = NFLAG_32(res); - FLAG_Z = res; - FLAG_V = VFLAG_CLEAR; - FLAG_C = CFLAG_CLEAR; - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_unlk_32_a7(void) -{ - REG_A[7] = m68ki_read_32(REG_A[7]); -} - - -void m68k_op_unlk_32(void) -{ - uint* r_dst = &AY; - - REG_A[7] = *r_dst; - *r_dst = m68ki_pull_32(); -} - - -void m68k_op_unpk_16_rr(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - /* Note: DX and DY are reversed in Motorola's docs */ - uint src = DY; - uint* r_dst = &DX; - - *r_dst = MASK_OUT_BELOW_16(*r_dst) | (((((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16()) & 0xffff); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_unpk_16_mm_ax7(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - /* Note: AX and AY are reversed in Motorola's docs */ - uint src = OPER_AY_PD_8(); - uint ea_dst; - - src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16(); - ea_dst = EA_A7_PD_8(); - m68ki_write_8(ea_dst, (src >> 8) & 0xff); - ea_dst = EA_A7_PD_8(); - m68ki_write_8(ea_dst, src & 0xff); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_unpk_16_mm_ay7(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - /* Note: AX and AY are reversed in Motorola's docs */ - uint src = OPER_A7_PD_8(); - uint ea_dst; - - src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16(); - ea_dst = EA_AX_PD_8(); - m68ki_write_8(ea_dst, (src >> 8) & 0xff); - ea_dst = EA_AX_PD_8(); - m68ki_write_8(ea_dst, src & 0xff); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_unpk_16_mm_axy7(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - uint src = OPER_A7_PD_8(); - uint ea_dst; - - src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16(); - ea_dst = EA_A7_PD_8(); - m68ki_write_8(ea_dst, (src >> 8) & 0xff); - ea_dst = EA_A7_PD_8(); - m68ki_write_8(ea_dst, src & 0xff); - return; - } - m68ki_exception_illegal(); -} - - -void m68k_op_unpk_16_mm(void) -{ - if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) - { - /* Note: AX and AY are reversed in Motorola's docs */ - uint src = OPER_AY_PD_8(); - uint ea_dst; - - src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16(); - ea_dst = EA_AX_PD_8(); - m68ki_write_8(ea_dst, (src >> 8) & 0xff); - ea_dst = EA_AX_PD_8(); - m68ki_write_8(ea_dst, src & 0xff); - return; - } - m68ki_exception_illegal(); -} - - -/* ======================================================================== */ -/* ============================== END OF FILE ============================= */ -/* ======================================================================== */ - - diff --git a/Frameworks/AudioOverload/aosdk/eng_ssf/m68kops.c b/Frameworks/AudioOverload/aosdk/eng_ssf/m68kops.c deleted file mode 100644 index 23613c730..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_ssf/m68kops.c +++ /dev/null @@ -1,2093 +0,0 @@ -/* ======================================================================== */ -/* ========================= OPCODE TABLE BUILDER ========================= */ -/* ======================================================================== */ - -#include "m68kops.h" - -#define NUM_CPU_TYPES 3 - -void (*m68ki_instruction_jump_table[0x10000])(void); /* opcode handler jump table */ -unsigned char m68ki_cycles[NUM_CPU_TYPES][0x10000]; /* Cycles used by CPU type */ - -/* This is used to generate the opcode handler jump table */ -typedef struct -{ - void (*opcode_handler)(void); /* handler function */ - unsigned int mask; /* mask on opcode */ - unsigned int match; /* what to match after masking */ - unsigned char cycles[NUM_CPU_TYPES]; /* cycles each cpu type takes */ -} opcode_handler_struct; - - -/* Opcode handler table */ -static opcode_handler_struct m68k_opcode_handler_table[] = -{ -/* function mask match 000 010 020 */ - {m68k_op_1010 , 0xf000, 0xa000, { 4, 4, 4}}, - {m68k_op_1111 , 0xf000, 0xf000, { 4, 4, 4}}, - {m68k_op_moveq_32 , 0xf100, 0x7000, { 4, 4, 2}}, - {m68k_op_cpbcc_32 , 0xf180, 0xf080, { 0, 0, 4}}, - {m68k_op_cpgen_32 , 0xf1c0, 0xf000, { 0, 0, 4}}, - {m68k_op_cpscc_32 , 0xf1c0, 0xf040, { 0, 0, 4}}, - {m68k_op_bra_8 , 0xff00, 0x6000, { 10, 10, 10}}, - {m68k_op_bsr_8 , 0xff00, 0x6100, { 18, 18, 7}}, - {m68k_op_bhi_8 , 0xff00, 0x6200, { 8, 8, 6}}, - {m68k_op_bls_8 , 0xff00, 0x6300, { 8, 8, 6}}, - {m68k_op_bcc_8 , 0xff00, 0x6400, { 8, 8, 6}}, - {m68k_op_bcs_8 , 0xff00, 0x6500, { 8, 8, 6}}, - {m68k_op_bne_8 , 0xff00, 0x6600, { 8, 8, 6}}, - {m68k_op_beq_8 , 0xff00, 0x6700, { 8, 8, 6}}, - {m68k_op_bvc_8 , 0xff00, 0x6800, { 8, 8, 6}}, - {m68k_op_bvs_8 , 0xff00, 0x6900, { 8, 8, 6}}, - {m68k_op_bpl_8 , 0xff00, 0x6a00, { 8, 8, 6}}, - {m68k_op_bmi_8 , 0xff00, 0x6b00, { 8, 8, 6}}, - {m68k_op_bge_8 , 0xff00, 0x6c00, { 8, 8, 6}}, - {m68k_op_blt_8 , 0xff00, 0x6d00, { 8, 8, 6}}, - {m68k_op_bgt_8 , 0xff00, 0x6e00, { 8, 8, 6}}, - {m68k_op_ble_8 , 0xff00, 0x6f00, { 8, 8, 6}}, - {m68k_op_btst_32_r_d , 0xf1f8, 0x0100, { 6, 6, 4}}, - {m68k_op_movep_16_er , 0xf1f8, 0x0108, { 16, 16, 12}}, - {m68k_op_btst_8_r_ai , 0xf1f8, 0x0110, { 8, 8, 8}}, - {m68k_op_btst_8_r_pi , 0xf1f8, 0x0118, { 8, 8, 8}}, - {m68k_op_btst_8_r_pd , 0xf1f8, 0x0120, { 10, 10, 9}}, - {m68k_op_btst_8_r_di , 0xf1f8, 0x0128, { 12, 12, 9}}, - {m68k_op_btst_8_r_ix , 0xf1f8, 0x0130, { 14, 14, 11}}, - {m68k_op_bchg_32_r_d , 0xf1f8, 0x0140, { 8, 8, 4}}, - {m68k_op_movep_32_er , 0xf1f8, 0x0148, { 24, 24, 18}}, - {m68k_op_bchg_8_r_ai , 0xf1f8, 0x0150, { 12, 12, 8}}, - {m68k_op_bchg_8_r_pi , 0xf1f8, 0x0158, { 12, 12, 8}}, - {m68k_op_bchg_8_r_pd , 0xf1f8, 0x0160, { 14, 14, 9}}, - {m68k_op_bchg_8_r_di , 0xf1f8, 0x0168, { 16, 16, 9}}, - {m68k_op_bchg_8_r_ix , 0xf1f8, 0x0170, { 18, 18, 11}}, - {m68k_op_bclr_32_r_d , 0xf1f8, 0x0180, { 10, 10, 4}}, - {m68k_op_movep_16_re , 0xf1f8, 0x0188, { 16, 16, 11}}, - {m68k_op_bclr_8_r_ai , 0xf1f8, 0x0190, { 12, 14, 8}}, - {m68k_op_bclr_8_r_pi , 0xf1f8, 0x0198, { 12, 14, 8}}, - {m68k_op_bclr_8_r_pd , 0xf1f8, 0x01a0, { 14, 16, 9}}, - {m68k_op_bclr_8_r_di , 0xf1f8, 0x01a8, { 16, 18, 9}}, - {m68k_op_bclr_8_r_ix , 0xf1f8, 0x01b0, { 18, 20, 11}}, - {m68k_op_bset_32_r_d , 0xf1f8, 0x01c0, { 8, 8, 4}}, - {m68k_op_movep_32_re , 0xf1f8, 0x01c8, { 24, 24, 17}}, - {m68k_op_bset_8_r_ai , 0xf1f8, 0x01d0, { 12, 12, 8}}, - {m68k_op_bset_8_r_pi , 0xf1f8, 0x01d8, { 12, 12, 8}}, - {m68k_op_bset_8_r_pd , 0xf1f8, 0x01e0, { 14, 14, 9}}, - {m68k_op_bset_8_r_di , 0xf1f8, 0x01e8, { 16, 16, 9}}, - {m68k_op_bset_8_r_ix , 0xf1f8, 0x01f0, { 18, 18, 11}}, - {m68k_op_move_8_d_d , 0xf1f8, 0x1000, { 4, 4, 2}}, - {m68k_op_move_8_d_ai , 0xf1f8, 0x1010, { 8, 8, 6}}, - {m68k_op_move_8_d_pi , 0xf1f8, 0x1018, { 8, 8, 6}}, - {m68k_op_move_8_d_pd , 0xf1f8, 0x1020, { 10, 10, 7}}, - {m68k_op_move_8_d_di , 0xf1f8, 0x1028, { 12, 12, 7}}, - {m68k_op_move_8_d_ix , 0xf1f8, 0x1030, { 14, 14, 9}}, - {m68k_op_move_8_ai_d , 0xf1f8, 0x1080, { 8, 8, 4}}, - {m68k_op_move_8_ai_ai , 0xf1f8, 0x1090, { 12, 12, 8}}, - {m68k_op_move_8_ai_pi , 0xf1f8, 0x1098, { 12, 12, 8}}, - {m68k_op_move_8_ai_pd , 0xf1f8, 0x10a0, { 14, 14, 9}}, - {m68k_op_move_8_ai_di , 0xf1f8, 0x10a8, { 16, 16, 9}}, - {m68k_op_move_8_ai_ix , 0xf1f8, 0x10b0, { 18, 18, 11}}, - {m68k_op_move_8_pi_d , 0xf1f8, 0x10c0, { 8, 8, 4}}, - {m68k_op_move_8_pi_ai , 0xf1f8, 0x10d0, { 12, 12, 8}}, - {m68k_op_move_8_pi_pi , 0xf1f8, 0x10d8, { 12, 12, 8}}, - {m68k_op_move_8_pi_pd , 0xf1f8, 0x10e0, { 14, 14, 9}}, - {m68k_op_move_8_pi_di , 0xf1f8, 0x10e8, { 16, 16, 9}}, - {m68k_op_move_8_pi_ix , 0xf1f8, 0x10f0, { 18, 18, 11}}, - {m68k_op_move_8_pd_d , 0xf1f8, 0x1100, { 8, 8, 5}}, - {m68k_op_move_8_pd_ai , 0xf1f8, 0x1110, { 12, 12, 9}}, - {m68k_op_move_8_pd_pi , 0xf1f8, 0x1118, { 12, 12, 9}}, - {m68k_op_move_8_pd_pd , 0xf1f8, 0x1120, { 14, 14, 10}}, - {m68k_op_move_8_pd_di , 0xf1f8, 0x1128, { 16, 16, 10}}, - {m68k_op_move_8_pd_ix , 0xf1f8, 0x1130, { 18, 18, 12}}, - {m68k_op_move_8_di_d , 0xf1f8, 0x1140, { 12, 12, 5}}, - {m68k_op_move_8_di_ai , 0xf1f8, 0x1150, { 16, 16, 9}}, - {m68k_op_move_8_di_pi , 0xf1f8, 0x1158, { 16, 16, 9}}, - {m68k_op_move_8_di_pd , 0xf1f8, 0x1160, { 18, 18, 10}}, - {m68k_op_move_8_di_di , 0xf1f8, 0x1168, { 20, 20, 10}}, - {m68k_op_move_8_di_ix , 0xf1f8, 0x1170, { 22, 22, 12}}, - {m68k_op_move_8_ix_d , 0xf1f8, 0x1180, { 14, 14, 7}}, - {m68k_op_move_8_ix_ai , 0xf1f8, 0x1190, { 18, 18, 11}}, - {m68k_op_move_8_ix_pi , 0xf1f8, 0x1198, { 18, 18, 11}}, - {m68k_op_move_8_ix_pd , 0xf1f8, 0x11a0, { 20, 20, 12}}, - {m68k_op_move_8_ix_di , 0xf1f8, 0x11a8, { 22, 22, 12}}, - {m68k_op_move_8_ix_ix , 0xf1f8, 0x11b0, { 24, 24, 14}}, - {m68k_op_move_32_d_d , 0xf1f8, 0x2000, { 4, 4, 2}}, - {m68k_op_move_32_d_a , 0xf1f8, 0x2008, { 4, 4, 2}}, - {m68k_op_move_32_d_ai , 0xf1f8, 0x2010, { 12, 12, 6}}, - {m68k_op_move_32_d_pi , 0xf1f8, 0x2018, { 12, 12, 6}}, - {m68k_op_move_32_d_pd , 0xf1f8, 0x2020, { 14, 14, 7}}, - {m68k_op_move_32_d_di , 0xf1f8, 0x2028, { 16, 16, 7}}, - {m68k_op_move_32_d_ix , 0xf1f8, 0x2030, { 18, 18, 9}}, - {m68k_op_movea_32_d , 0xf1f8, 0x2040, { 4, 4, 2}}, - {m68k_op_movea_32_a , 0xf1f8, 0x2048, { 4, 4, 2}}, - {m68k_op_movea_32_ai , 0xf1f8, 0x2050, { 12, 12, 6}}, - {m68k_op_movea_32_pi , 0xf1f8, 0x2058, { 12, 12, 6}}, - {m68k_op_movea_32_pd , 0xf1f8, 0x2060, { 14, 14, 7}}, - {m68k_op_movea_32_di , 0xf1f8, 0x2068, { 16, 16, 7}}, - {m68k_op_movea_32_ix , 0xf1f8, 0x2070, { 18, 18, 9}}, - {m68k_op_move_32_ai_d , 0xf1f8, 0x2080, { 12, 12, 4}}, - {m68k_op_move_32_ai_a , 0xf1f8, 0x2088, { 12, 12, 4}}, - {m68k_op_move_32_ai_ai , 0xf1f8, 0x2090, { 20, 20, 8}}, - {m68k_op_move_32_ai_pi , 0xf1f8, 0x2098, { 20, 20, 8}}, - {m68k_op_move_32_ai_pd , 0xf1f8, 0x20a0, { 22, 22, 9}}, - {m68k_op_move_32_ai_di , 0xf1f8, 0x20a8, { 24, 24, 9}}, - {m68k_op_move_32_ai_ix , 0xf1f8, 0x20b0, { 26, 26, 11}}, - {m68k_op_move_32_pi_d , 0xf1f8, 0x20c0, { 12, 12, 4}}, - {m68k_op_move_32_pi_a , 0xf1f8, 0x20c8, { 12, 12, 4}}, - {m68k_op_move_32_pi_ai , 0xf1f8, 0x20d0, { 20, 20, 8}}, - {m68k_op_move_32_pi_pi , 0xf1f8, 0x20d8, { 20, 20, 8}}, - {m68k_op_move_32_pi_pd , 0xf1f8, 0x20e0, { 22, 22, 9}}, - {m68k_op_move_32_pi_di , 0xf1f8, 0x20e8, { 24, 24, 9}}, - {m68k_op_move_32_pi_ix , 0xf1f8, 0x20f0, { 26, 26, 11}}, - {m68k_op_move_32_pd_d , 0xf1f8, 0x2100, { 12, 14, 5}}, - {m68k_op_move_32_pd_a , 0xf1f8, 0x2108, { 12, 14, 5}}, - {m68k_op_move_32_pd_ai , 0xf1f8, 0x2110, { 20, 22, 9}}, - {m68k_op_move_32_pd_pi , 0xf1f8, 0x2118, { 20, 22, 9}}, - {m68k_op_move_32_pd_pd , 0xf1f8, 0x2120, { 22, 24, 10}}, - {m68k_op_move_32_pd_di , 0xf1f8, 0x2128, { 24, 26, 10}}, - {m68k_op_move_32_pd_ix , 0xf1f8, 0x2130, { 26, 28, 12}}, - {m68k_op_move_32_di_d , 0xf1f8, 0x2140, { 16, 16, 5}}, - {m68k_op_move_32_di_a , 0xf1f8, 0x2148, { 16, 16, 5}}, - {m68k_op_move_32_di_ai , 0xf1f8, 0x2150, { 24, 24, 9}}, - {m68k_op_move_32_di_pi , 0xf1f8, 0x2158, { 24, 24, 9}}, - {m68k_op_move_32_di_pd , 0xf1f8, 0x2160, { 26, 26, 10}}, - {m68k_op_move_32_di_di , 0xf1f8, 0x2168, { 28, 28, 10}}, - {m68k_op_move_32_di_ix , 0xf1f8, 0x2170, { 30, 30, 12}}, - {m68k_op_move_32_ix_d , 0xf1f8, 0x2180, { 18, 18, 7}}, - {m68k_op_move_32_ix_a , 0xf1f8, 0x2188, { 18, 18, 7}}, - {m68k_op_move_32_ix_ai , 0xf1f8, 0x2190, { 26, 26, 11}}, - {m68k_op_move_32_ix_pi , 0xf1f8, 0x2198, { 26, 26, 11}}, - {m68k_op_move_32_ix_pd , 0xf1f8, 0x21a0, { 28, 28, 12}}, - {m68k_op_move_32_ix_di , 0xf1f8, 0x21a8, { 30, 30, 12}}, - {m68k_op_move_32_ix_ix , 0xf1f8, 0x21b0, { 32, 32, 14}}, - {m68k_op_move_16_d_d , 0xf1f8, 0x3000, { 4, 4, 2}}, - {m68k_op_move_16_d_a , 0xf1f8, 0x3008, { 4, 4, 2}}, - {m68k_op_move_16_d_ai , 0xf1f8, 0x3010, { 8, 8, 6}}, - {m68k_op_move_16_d_pi , 0xf1f8, 0x3018, { 8, 8, 6}}, - {m68k_op_move_16_d_pd , 0xf1f8, 0x3020, { 10, 10, 7}}, - {m68k_op_move_16_d_di , 0xf1f8, 0x3028, { 12, 12, 7}}, - {m68k_op_move_16_d_ix , 0xf1f8, 0x3030, { 14, 14, 9}}, - {m68k_op_movea_16_d , 0xf1f8, 0x3040, { 4, 4, 2}}, - {m68k_op_movea_16_a , 0xf1f8, 0x3048, { 4, 4, 2}}, - {m68k_op_movea_16_ai , 0xf1f8, 0x3050, { 8, 8, 6}}, - {m68k_op_movea_16_pi , 0xf1f8, 0x3058, { 8, 8, 6}}, - {m68k_op_movea_16_pd , 0xf1f8, 0x3060, { 10, 10, 7}}, - {m68k_op_movea_16_di , 0xf1f8, 0x3068, { 12, 12, 7}}, - {m68k_op_movea_16_ix , 0xf1f8, 0x3070, { 14, 14, 9}}, - {m68k_op_move_16_ai_d , 0xf1f8, 0x3080, { 8, 8, 4}}, - {m68k_op_move_16_ai_a , 0xf1f8, 0x3088, { 8, 8, 4}}, - {m68k_op_move_16_ai_ai , 0xf1f8, 0x3090, { 12, 12, 8}}, - {m68k_op_move_16_ai_pi , 0xf1f8, 0x3098, { 12, 12, 8}}, - {m68k_op_move_16_ai_pd , 0xf1f8, 0x30a0, { 14, 14, 9}}, - {m68k_op_move_16_ai_di , 0xf1f8, 0x30a8, { 16, 16, 9}}, - {m68k_op_move_16_ai_ix , 0xf1f8, 0x30b0, { 18, 18, 11}}, - {m68k_op_move_16_pi_d , 0xf1f8, 0x30c0, { 8, 8, 4}}, - {m68k_op_move_16_pi_a , 0xf1f8, 0x30c8, { 8, 8, 4}}, - {m68k_op_move_16_pi_ai , 0xf1f8, 0x30d0, { 12, 12, 8}}, - {m68k_op_move_16_pi_pi , 0xf1f8, 0x30d8, { 12, 12, 8}}, - {m68k_op_move_16_pi_pd , 0xf1f8, 0x30e0, { 14, 14, 9}}, - {m68k_op_move_16_pi_di , 0xf1f8, 0x30e8, { 16, 16, 9}}, - {m68k_op_move_16_pi_ix , 0xf1f8, 0x30f0, { 18, 18, 11}}, - {m68k_op_move_16_pd_d , 0xf1f8, 0x3100, { 8, 8, 5}}, - {m68k_op_move_16_pd_a , 0xf1f8, 0x3108, { 8, 8, 5}}, - {m68k_op_move_16_pd_ai , 0xf1f8, 0x3110, { 12, 12, 9}}, - {m68k_op_move_16_pd_pi , 0xf1f8, 0x3118, { 12, 12, 9}}, - {m68k_op_move_16_pd_pd , 0xf1f8, 0x3120, { 14, 14, 10}}, - {m68k_op_move_16_pd_di , 0xf1f8, 0x3128, { 16, 16, 10}}, - {m68k_op_move_16_pd_ix , 0xf1f8, 0x3130, { 18, 18, 12}}, - {m68k_op_move_16_di_d , 0xf1f8, 0x3140, { 12, 12, 5}}, - {m68k_op_move_16_di_a , 0xf1f8, 0x3148, { 12, 12, 5}}, - {m68k_op_move_16_di_ai , 0xf1f8, 0x3150, { 16, 16, 9}}, - {m68k_op_move_16_di_pi , 0xf1f8, 0x3158, { 16, 16, 9}}, - {m68k_op_move_16_di_pd , 0xf1f8, 0x3160, { 18, 18, 10}}, - {m68k_op_move_16_di_di , 0xf1f8, 0x3168, { 20, 20, 10}}, - {m68k_op_move_16_di_ix , 0xf1f8, 0x3170, { 22, 22, 12}}, - {m68k_op_move_16_ix_d , 0xf1f8, 0x3180, { 14, 14, 7}}, - {m68k_op_move_16_ix_a , 0xf1f8, 0x3188, { 14, 14, 7}}, - {m68k_op_move_16_ix_ai , 0xf1f8, 0x3190, { 18, 18, 11}}, - {m68k_op_move_16_ix_pi , 0xf1f8, 0x3198, { 18, 18, 11}}, - {m68k_op_move_16_ix_pd , 0xf1f8, 0x31a0, { 20, 20, 12}}, - {m68k_op_move_16_ix_di , 0xf1f8, 0x31a8, { 22, 22, 12}}, - {m68k_op_move_16_ix_ix , 0xf1f8, 0x31b0, { 24, 24, 14}}, - {m68k_op_chk_32_d , 0xf1f8, 0x4100, { 0, 0, 8}}, - {m68k_op_chk_32_ai , 0xf1f8, 0x4110, { 0, 0, 12}}, - {m68k_op_chk_32_pi , 0xf1f8, 0x4118, { 0, 0, 12}}, - {m68k_op_chk_32_pd , 0xf1f8, 0x4120, { 0, 0, 13}}, - {m68k_op_chk_32_di , 0xf1f8, 0x4128, { 0, 0, 13}}, - {m68k_op_chk_32_ix , 0xf1f8, 0x4130, { 0, 0, 15}}, - {m68k_op_chk_16_d , 0xf1f8, 0x4180, { 10, 8, 8}}, - {m68k_op_chk_16_ai , 0xf1f8, 0x4190, { 14, 12, 12}}, - {m68k_op_chk_16_pi , 0xf1f8, 0x4198, { 14, 12, 12}}, - {m68k_op_chk_16_pd , 0xf1f8, 0x41a0, { 16, 14, 13}}, - {m68k_op_chk_16_di , 0xf1f8, 0x41a8, { 18, 16, 13}}, - {m68k_op_chk_16_ix , 0xf1f8, 0x41b0, { 20, 18, 15}}, - {m68k_op_lea_32_ai , 0xf1f8, 0x41d0, { 4, 4, 6}}, - {m68k_op_lea_32_di , 0xf1f8, 0x41e8, { 8, 8, 7}}, - {m68k_op_lea_32_ix , 0xf1f8, 0x41f0, { 12, 12, 9}}, - {m68k_op_addq_8_d , 0xf1f8, 0x5000, { 4, 4, 2}}, - {m68k_op_addq_8_ai , 0xf1f8, 0x5010, { 12, 12, 8}}, - {m68k_op_addq_8_pi , 0xf1f8, 0x5018, { 12, 12, 8}}, - {m68k_op_addq_8_pd , 0xf1f8, 0x5020, { 14, 14, 9}}, - {m68k_op_addq_8_di , 0xf1f8, 0x5028, { 16, 16, 9}}, - {m68k_op_addq_8_ix , 0xf1f8, 0x5030, { 18, 18, 11}}, - {m68k_op_addq_16_d , 0xf1f8, 0x5040, { 4, 4, 2}}, - {m68k_op_addq_16_a , 0xf1f8, 0x5048, { 4, 4, 2}}, - {m68k_op_addq_16_ai , 0xf1f8, 0x5050, { 12, 12, 8}}, - {m68k_op_addq_16_pi , 0xf1f8, 0x5058, { 12, 12, 8}}, - {m68k_op_addq_16_pd , 0xf1f8, 0x5060, { 14, 14, 9}}, - {m68k_op_addq_16_di , 0xf1f8, 0x5068, { 16, 16, 9}}, - {m68k_op_addq_16_ix , 0xf1f8, 0x5070, { 18, 18, 11}}, - {m68k_op_addq_32_d , 0xf1f8, 0x5080, { 8, 8, 2}}, - {m68k_op_addq_32_a , 0xf1f8, 0x5088, { 8, 8, 2}}, - {m68k_op_addq_32_ai , 0xf1f8, 0x5090, { 20, 20, 8}}, - {m68k_op_addq_32_pi , 0xf1f8, 0x5098, { 20, 20, 8}}, - {m68k_op_addq_32_pd , 0xf1f8, 0x50a0, { 22, 22, 9}}, - {m68k_op_addq_32_di , 0xf1f8, 0x50a8, { 24, 24, 9}}, - {m68k_op_addq_32_ix , 0xf1f8, 0x50b0, { 26, 26, 11}}, - {m68k_op_subq_8_d , 0xf1f8, 0x5100, { 4, 4, 2}}, - {m68k_op_subq_8_ai , 0xf1f8, 0x5110, { 12, 12, 8}}, - {m68k_op_subq_8_pi , 0xf1f8, 0x5118, { 12, 12, 8}}, - {m68k_op_subq_8_pd , 0xf1f8, 0x5120, { 14, 14, 9}}, - {m68k_op_subq_8_di , 0xf1f8, 0x5128, { 16, 16, 9}}, - {m68k_op_subq_8_ix , 0xf1f8, 0x5130, { 18, 18, 11}}, - {m68k_op_subq_16_d , 0xf1f8, 0x5140, { 4, 4, 2}}, - {m68k_op_subq_16_a , 0xf1f8, 0x5148, { 8, 4, 2}}, - {m68k_op_subq_16_ai , 0xf1f8, 0x5150, { 12, 12, 8}}, - {m68k_op_subq_16_pi , 0xf1f8, 0x5158, { 12, 12, 8}}, - {m68k_op_subq_16_pd , 0xf1f8, 0x5160, { 14, 14, 9}}, - {m68k_op_subq_16_di , 0xf1f8, 0x5168, { 16, 16, 9}}, - {m68k_op_subq_16_ix , 0xf1f8, 0x5170, { 18, 18, 11}}, - {m68k_op_subq_32_d , 0xf1f8, 0x5180, { 8, 8, 2}}, - {m68k_op_subq_32_a , 0xf1f8, 0x5188, { 8, 8, 2}}, - {m68k_op_subq_32_ai , 0xf1f8, 0x5190, { 20, 20, 8}}, - {m68k_op_subq_32_pi , 0xf1f8, 0x5198, { 20, 20, 8}}, - {m68k_op_subq_32_pd , 0xf1f8, 0x51a0, { 22, 22, 9}}, - {m68k_op_subq_32_di , 0xf1f8, 0x51a8, { 24, 24, 9}}, - {m68k_op_subq_32_ix , 0xf1f8, 0x51b0, { 26, 26, 11}}, - {m68k_op_or_8_er_d , 0xf1f8, 0x8000, { 4, 4, 2}}, - {m68k_op_or_8_er_ai , 0xf1f8, 0x8010, { 8, 8, 6}}, - {m68k_op_or_8_er_pi , 0xf1f8, 0x8018, { 8, 8, 6}}, - {m68k_op_or_8_er_pd , 0xf1f8, 0x8020, { 10, 10, 7}}, - {m68k_op_or_8_er_di , 0xf1f8, 0x8028, { 12, 12, 7}}, - {m68k_op_or_8_er_ix , 0xf1f8, 0x8030, { 14, 14, 9}}, - {m68k_op_or_16_er_d , 0xf1f8, 0x8040, { 4, 4, 2}}, - {m68k_op_or_16_er_ai , 0xf1f8, 0x8050, { 8, 8, 6}}, - {m68k_op_or_16_er_pi , 0xf1f8, 0x8058, { 8, 8, 6}}, - {m68k_op_or_16_er_pd , 0xf1f8, 0x8060, { 10, 10, 7}}, - {m68k_op_or_16_er_di , 0xf1f8, 0x8068, { 12, 12, 7}}, - {m68k_op_or_16_er_ix , 0xf1f8, 0x8070, { 14, 14, 9}}, - {m68k_op_or_32_er_d , 0xf1f8, 0x8080, { 6, 6, 2}}, - {m68k_op_or_32_er_ai , 0xf1f8, 0x8090, { 14, 14, 6}}, - {m68k_op_or_32_er_pi , 0xf1f8, 0x8098, { 14, 14, 6}}, - {m68k_op_or_32_er_pd , 0xf1f8, 0x80a0, { 16, 16, 7}}, - {m68k_op_or_32_er_di , 0xf1f8, 0x80a8, { 18, 18, 7}}, - {m68k_op_or_32_er_ix , 0xf1f8, 0x80b0, { 20, 20, 9}}, - {m68k_op_divu_16_d , 0xf1f8, 0x80c0, {140, 108, 44}}, - {m68k_op_divu_16_ai , 0xf1f8, 0x80d0, {144, 112, 48}}, - {m68k_op_divu_16_pi , 0xf1f8, 0x80d8, {144, 112, 48}}, - {m68k_op_divu_16_pd , 0xf1f8, 0x80e0, {146, 114, 49}}, - {m68k_op_divu_16_di , 0xf1f8, 0x80e8, {148, 116, 49}}, - {m68k_op_divu_16_ix , 0xf1f8, 0x80f0, {150, 118, 51}}, - {m68k_op_sbcd_8_rr , 0xf1f8, 0x8100, { 6, 6, 4}}, - {m68k_op_sbcd_8_mm , 0xf1f8, 0x8108, { 18, 18, 16}}, - {m68k_op_or_8_re_ai , 0xf1f8, 0x8110, { 12, 12, 8}}, - {m68k_op_or_8_re_pi , 0xf1f8, 0x8118, { 12, 12, 8}}, - {m68k_op_or_8_re_pd , 0xf1f8, 0x8120, { 14, 14, 9}}, - {m68k_op_or_8_re_di , 0xf1f8, 0x8128, { 16, 16, 9}}, - {m68k_op_or_8_re_ix , 0xf1f8, 0x8130, { 18, 18, 11}}, - {m68k_op_pack_16_rr , 0xf1f8, 0x8140, { 0, 0, 6}}, - {m68k_op_pack_16_mm , 0xf1f8, 0x8148, { 0, 0, 13}}, - {m68k_op_or_16_re_ai , 0xf1f8, 0x8150, { 12, 12, 8}}, - {m68k_op_or_16_re_pi , 0xf1f8, 0x8158, { 12, 12, 8}}, - {m68k_op_or_16_re_pd , 0xf1f8, 0x8160, { 14, 14, 9}}, - {m68k_op_or_16_re_di , 0xf1f8, 0x8168, { 16, 16, 9}}, - {m68k_op_or_16_re_ix , 0xf1f8, 0x8170, { 18, 18, 11}}, - {m68k_op_unpk_16_rr , 0xf1f8, 0x8180, { 0, 0, 8}}, - {m68k_op_unpk_16_mm , 0xf1f8, 0x8188, { 0, 0, 13}}, - {m68k_op_or_32_re_ai , 0xf1f8, 0x8190, { 20, 20, 8}}, - {m68k_op_or_32_re_pi , 0xf1f8, 0x8198, { 20, 20, 8}}, - {m68k_op_or_32_re_pd , 0xf1f8, 0x81a0, { 22, 22, 9}}, - {m68k_op_or_32_re_di , 0xf1f8, 0x81a8, { 24, 24, 9}}, - {m68k_op_or_32_re_ix , 0xf1f8, 0x81b0, { 26, 26, 11}}, - {m68k_op_divs_16_d , 0xf1f8, 0x81c0, {158, 122, 56}}, - {m68k_op_divs_16_ai , 0xf1f8, 0x81d0, {162, 126, 60}}, - {m68k_op_divs_16_pi , 0xf1f8, 0x81d8, {162, 126, 60}}, - {m68k_op_divs_16_pd , 0xf1f8, 0x81e0, {164, 128, 61}}, - {m68k_op_divs_16_di , 0xf1f8, 0x81e8, {166, 130, 61}}, - {m68k_op_divs_16_ix , 0xf1f8, 0x81f0, {168, 132, 63}}, - {m68k_op_sub_8_er_d , 0xf1f8, 0x9000, { 4, 4, 2}}, - {m68k_op_sub_8_er_ai , 0xf1f8, 0x9010, { 8, 8, 6}}, - {m68k_op_sub_8_er_pi , 0xf1f8, 0x9018, { 8, 8, 6}}, - {m68k_op_sub_8_er_pd , 0xf1f8, 0x9020, { 10, 10, 7}}, - {m68k_op_sub_8_er_di , 0xf1f8, 0x9028, { 12, 12, 7}}, - {m68k_op_sub_8_er_ix , 0xf1f8, 0x9030, { 14, 14, 9}}, - {m68k_op_sub_16_er_d , 0xf1f8, 0x9040, { 4, 4, 2}}, - {m68k_op_sub_16_er_a , 0xf1f8, 0x9048, { 4, 4, 2}}, - {m68k_op_sub_16_er_ai , 0xf1f8, 0x9050, { 8, 8, 6}}, - {m68k_op_sub_16_er_pi , 0xf1f8, 0x9058, { 8, 8, 6}}, - {m68k_op_sub_16_er_pd , 0xf1f8, 0x9060, { 10, 10, 7}}, - {m68k_op_sub_16_er_di , 0xf1f8, 0x9068, { 12, 12, 7}}, - {m68k_op_sub_16_er_ix , 0xf1f8, 0x9070, { 14, 14, 9}}, - {m68k_op_sub_32_er_d , 0xf1f8, 0x9080, { 6, 6, 2}}, - {m68k_op_sub_32_er_a , 0xf1f8, 0x9088, { 6, 6, 2}}, - {m68k_op_sub_32_er_ai , 0xf1f8, 0x9090, { 14, 14, 6}}, - {m68k_op_sub_32_er_pi , 0xf1f8, 0x9098, { 14, 14, 6}}, - {m68k_op_sub_32_er_pd , 0xf1f8, 0x90a0, { 16, 16, 7}}, - {m68k_op_sub_32_er_di , 0xf1f8, 0x90a8, { 18, 18, 7}}, - {m68k_op_sub_32_er_ix , 0xf1f8, 0x90b0, { 20, 20, 9}}, - {m68k_op_suba_16_d , 0xf1f8, 0x90c0, { 8, 8, 2}}, - {m68k_op_suba_16_a , 0xf1f8, 0x90c8, { 8, 8, 2}}, - {m68k_op_suba_16_ai , 0xf1f8, 0x90d0, { 12, 12, 6}}, - {m68k_op_suba_16_pi , 0xf1f8, 0x90d8, { 12, 12, 6}}, - {m68k_op_suba_16_pd , 0xf1f8, 0x90e0, { 14, 14, 7}}, - {m68k_op_suba_16_di , 0xf1f8, 0x90e8, { 16, 16, 7}}, - {m68k_op_suba_16_ix , 0xf1f8, 0x90f0, { 18, 18, 9}}, - {m68k_op_subx_8_rr , 0xf1f8, 0x9100, { 4, 4, 2}}, - {m68k_op_subx_8_mm , 0xf1f8, 0x9108, { 18, 18, 12}}, - {m68k_op_sub_8_re_ai , 0xf1f8, 0x9110, { 12, 12, 8}}, - {m68k_op_sub_8_re_pi , 0xf1f8, 0x9118, { 12, 12, 8}}, - {m68k_op_sub_8_re_pd , 0xf1f8, 0x9120, { 14, 14, 9}}, - {m68k_op_sub_8_re_di , 0xf1f8, 0x9128, { 16, 16, 9}}, - {m68k_op_sub_8_re_ix , 0xf1f8, 0x9130, { 18, 18, 11}}, - {m68k_op_subx_16_rr , 0xf1f8, 0x9140, { 4, 4, 2}}, - {m68k_op_subx_16_mm , 0xf1f8, 0x9148, { 18, 18, 12}}, - {m68k_op_sub_16_re_ai , 0xf1f8, 0x9150, { 12, 12, 8}}, - {m68k_op_sub_16_re_pi , 0xf1f8, 0x9158, { 12, 12, 8}}, - {m68k_op_sub_16_re_pd , 0xf1f8, 0x9160, { 14, 14, 9}}, - {m68k_op_sub_16_re_di , 0xf1f8, 0x9168, { 16, 16, 9}}, - {m68k_op_sub_16_re_ix , 0xf1f8, 0x9170, { 18, 18, 11}}, - {m68k_op_subx_32_rr , 0xf1f8, 0x9180, { 8, 6, 2}}, - {m68k_op_subx_32_mm , 0xf1f8, 0x9188, { 30, 30, 12}}, - {m68k_op_sub_32_re_ai , 0xf1f8, 0x9190, { 20, 20, 8}}, - {m68k_op_sub_32_re_pi , 0xf1f8, 0x9198, { 20, 20, 8}}, - {m68k_op_sub_32_re_pd , 0xf1f8, 0x91a0, { 22, 22, 9}}, - {m68k_op_sub_32_re_di , 0xf1f8, 0x91a8, { 24, 24, 9}}, - {m68k_op_sub_32_re_ix , 0xf1f8, 0x91b0, { 26, 26, 11}}, - {m68k_op_suba_32_d , 0xf1f8, 0x91c0, { 6, 6, 2}}, - {m68k_op_suba_32_a , 0xf1f8, 0x91c8, { 6, 6, 2}}, - {m68k_op_suba_32_ai , 0xf1f8, 0x91d0, { 14, 14, 6}}, - {m68k_op_suba_32_pi , 0xf1f8, 0x91d8, { 14, 14, 6}}, - {m68k_op_suba_32_pd , 0xf1f8, 0x91e0, { 16, 16, 7}}, - {m68k_op_suba_32_di , 0xf1f8, 0x91e8, { 18, 18, 7}}, - {m68k_op_suba_32_ix , 0xf1f8, 0x91f0, { 20, 20, 9}}, - {m68k_op_cmp_8_d , 0xf1f8, 0xb000, { 4, 4, 2}}, - {m68k_op_cmp_8_ai , 0xf1f8, 0xb010, { 8, 8, 6}}, - {m68k_op_cmp_8_pi , 0xf1f8, 0xb018, { 8, 8, 6}}, - {m68k_op_cmp_8_pd , 0xf1f8, 0xb020, { 10, 10, 7}}, - {m68k_op_cmp_8_di , 0xf1f8, 0xb028, { 12, 12, 7}}, - {m68k_op_cmp_8_ix , 0xf1f8, 0xb030, { 14, 14, 9}}, - {m68k_op_cmp_16_d , 0xf1f8, 0xb040, { 4, 4, 2}}, - {m68k_op_cmp_16_a , 0xf1f8, 0xb048, { 4, 4, 2}}, - {m68k_op_cmp_16_ai , 0xf1f8, 0xb050, { 8, 8, 6}}, - {m68k_op_cmp_16_pi , 0xf1f8, 0xb058, { 8, 8, 6}}, - {m68k_op_cmp_16_pd , 0xf1f8, 0xb060, { 10, 10, 7}}, - {m68k_op_cmp_16_di , 0xf1f8, 0xb068, { 12, 12, 7}}, - {m68k_op_cmp_16_ix , 0xf1f8, 0xb070, { 14, 14, 9}}, - {m68k_op_cmp_32_d , 0xf1f8, 0xb080, { 6, 6, 2}}, - {m68k_op_cmp_32_a , 0xf1f8, 0xb088, { 6, 6, 2}}, - {m68k_op_cmp_32_ai , 0xf1f8, 0xb090, { 14, 14, 6}}, - {m68k_op_cmp_32_pi , 0xf1f8, 0xb098, { 14, 14, 6}}, - {m68k_op_cmp_32_pd , 0xf1f8, 0xb0a0, { 16, 16, 7}}, - {m68k_op_cmp_32_di , 0xf1f8, 0xb0a8, { 18, 18, 7}}, - {m68k_op_cmp_32_ix , 0xf1f8, 0xb0b0, { 20, 20, 9}}, - {m68k_op_cmpa_16_d , 0xf1f8, 0xb0c0, { 6, 6, 4}}, - {m68k_op_cmpa_16_a , 0xf1f8, 0xb0c8, { 6, 6, 4}}, - {m68k_op_cmpa_16_ai , 0xf1f8, 0xb0d0, { 10, 10, 8}}, - {m68k_op_cmpa_16_pi , 0xf1f8, 0xb0d8, { 10, 10, 8}}, - {m68k_op_cmpa_16_pd , 0xf1f8, 0xb0e0, { 12, 12, 9}}, - {m68k_op_cmpa_16_di , 0xf1f8, 0xb0e8, { 14, 14, 9}}, - {m68k_op_cmpa_16_ix , 0xf1f8, 0xb0f0, { 16, 16, 11}}, - {m68k_op_eor_8_d , 0xf1f8, 0xb100, { 4, 4, 2}}, - {m68k_op_cmpm_8 , 0xf1f8, 0xb108, { 12, 12, 9}}, - {m68k_op_eor_8_ai , 0xf1f8, 0xb110, { 12, 12, 8}}, - {m68k_op_eor_8_pi , 0xf1f8, 0xb118, { 12, 12, 8}}, - {m68k_op_eor_8_pd , 0xf1f8, 0xb120, { 14, 14, 9}}, - {m68k_op_eor_8_di , 0xf1f8, 0xb128, { 16, 16, 9}}, - {m68k_op_eor_8_ix , 0xf1f8, 0xb130, { 18, 18, 11}}, - {m68k_op_eor_16_d , 0xf1f8, 0xb140, { 4, 4, 2}}, - {m68k_op_cmpm_16 , 0xf1f8, 0xb148, { 12, 12, 9}}, - {m68k_op_eor_16_ai , 0xf1f8, 0xb150, { 12, 12, 8}}, - {m68k_op_eor_16_pi , 0xf1f8, 0xb158, { 12, 12, 8}}, - {m68k_op_eor_16_pd , 0xf1f8, 0xb160, { 14, 14, 9}}, - {m68k_op_eor_16_di , 0xf1f8, 0xb168, { 16, 16, 9}}, - {m68k_op_eor_16_ix , 0xf1f8, 0xb170, { 18, 18, 11}}, - {m68k_op_eor_32_d , 0xf1f8, 0xb180, { 8, 6, 2}}, - {m68k_op_cmpm_32 , 0xf1f8, 0xb188, { 20, 20, 9}}, - {m68k_op_eor_32_ai , 0xf1f8, 0xb190, { 20, 20, 8}}, - {m68k_op_eor_32_pi , 0xf1f8, 0xb198, { 20, 20, 8}}, - {m68k_op_eor_32_pd , 0xf1f8, 0xb1a0, { 22, 22, 9}}, - {m68k_op_eor_32_di , 0xf1f8, 0xb1a8, { 24, 24, 9}}, - {m68k_op_eor_32_ix , 0xf1f8, 0xb1b0, { 26, 26, 11}}, - {m68k_op_cmpa_32_d , 0xf1f8, 0xb1c0, { 6, 6, 4}}, - {m68k_op_cmpa_32_a , 0xf1f8, 0xb1c8, { 6, 6, 4}}, - {m68k_op_cmpa_32_ai , 0xf1f8, 0xb1d0, { 14, 14, 8}}, - {m68k_op_cmpa_32_pi , 0xf1f8, 0xb1d8, { 14, 14, 8}}, - {m68k_op_cmpa_32_pd , 0xf1f8, 0xb1e0, { 16, 16, 9}}, - {m68k_op_cmpa_32_di , 0xf1f8, 0xb1e8, { 18, 18, 9}}, - {m68k_op_cmpa_32_ix , 0xf1f8, 0xb1f0, { 20, 20, 11}}, - {m68k_op_and_8_er_d , 0xf1f8, 0xc000, { 4, 4, 2}}, - {m68k_op_and_8_er_ai , 0xf1f8, 0xc010, { 8, 8, 6}}, - {m68k_op_and_8_er_pi , 0xf1f8, 0xc018, { 8, 8, 6}}, - {m68k_op_and_8_er_pd , 0xf1f8, 0xc020, { 10, 10, 7}}, - {m68k_op_and_8_er_di , 0xf1f8, 0xc028, { 12, 12, 7}}, - {m68k_op_and_8_er_ix , 0xf1f8, 0xc030, { 14, 14, 9}}, - {m68k_op_and_16_er_d , 0xf1f8, 0xc040, { 4, 4, 2}}, - {m68k_op_and_16_er_ai , 0xf1f8, 0xc050, { 8, 8, 6}}, - {m68k_op_and_16_er_pi , 0xf1f8, 0xc058, { 8, 8, 6}}, - {m68k_op_and_16_er_pd , 0xf1f8, 0xc060, { 10, 10, 7}}, - {m68k_op_and_16_er_di , 0xf1f8, 0xc068, { 12, 12, 7}}, - {m68k_op_and_16_er_ix , 0xf1f8, 0xc070, { 14, 14, 9}}, - {m68k_op_and_32_er_d , 0xf1f8, 0xc080, { 6, 6, 2}}, - {m68k_op_and_32_er_ai , 0xf1f8, 0xc090, { 14, 14, 6}}, - {m68k_op_and_32_er_pi , 0xf1f8, 0xc098, { 14, 14, 6}}, - {m68k_op_and_32_er_pd , 0xf1f8, 0xc0a0, { 16, 16, 7}}, - {m68k_op_and_32_er_di , 0xf1f8, 0xc0a8, { 18, 18, 7}}, - {m68k_op_and_32_er_ix , 0xf1f8, 0xc0b0, { 20, 20, 9}}, - {m68k_op_mulu_16_d , 0xf1f8, 0xc0c0, { 54, 30, 27}}, - {m68k_op_mulu_16_ai , 0xf1f8, 0xc0d0, { 58, 34, 31}}, - {m68k_op_mulu_16_pi , 0xf1f8, 0xc0d8, { 58, 34, 31}}, - {m68k_op_mulu_16_pd , 0xf1f8, 0xc0e0, { 60, 36, 32}}, - {m68k_op_mulu_16_di , 0xf1f8, 0xc0e8, { 62, 38, 32}}, - {m68k_op_mulu_16_ix , 0xf1f8, 0xc0f0, { 64, 40, 34}}, - {m68k_op_abcd_8_rr , 0xf1f8, 0xc100, { 6, 6, 4}}, - {m68k_op_abcd_8_mm , 0xf1f8, 0xc108, { 18, 18, 16}}, - {m68k_op_and_8_re_ai , 0xf1f8, 0xc110, { 12, 12, 8}}, - {m68k_op_and_8_re_pi , 0xf1f8, 0xc118, { 12, 12, 8}}, - {m68k_op_and_8_re_pd , 0xf1f8, 0xc120, { 14, 14, 9}}, - {m68k_op_and_8_re_di , 0xf1f8, 0xc128, { 16, 16, 9}}, - {m68k_op_and_8_re_ix , 0xf1f8, 0xc130, { 18, 18, 11}}, - {m68k_op_exg_32_dd , 0xf1f8, 0xc140, { 6, 6, 2}}, - {m68k_op_exg_32_aa , 0xf1f8, 0xc148, { 6, 6, 2}}, - {m68k_op_and_16_re_ai , 0xf1f8, 0xc150, { 12, 12, 8}}, - {m68k_op_and_16_re_pi , 0xf1f8, 0xc158, { 12, 12, 8}}, - {m68k_op_and_16_re_pd , 0xf1f8, 0xc160, { 14, 14, 9}}, - {m68k_op_and_16_re_di , 0xf1f8, 0xc168, { 16, 16, 9}}, - {m68k_op_and_16_re_ix , 0xf1f8, 0xc170, { 18, 18, 11}}, - {m68k_op_exg_32_da , 0xf1f8, 0xc188, { 6, 6, 2}}, - {m68k_op_and_32_re_ai , 0xf1f8, 0xc190, { 20, 20, 8}}, - {m68k_op_and_32_re_pi , 0xf1f8, 0xc198, { 20, 20, 8}}, - {m68k_op_and_32_re_pd , 0xf1f8, 0xc1a0, { 22, 22, 9}}, - {m68k_op_and_32_re_di , 0xf1f8, 0xc1a8, { 24, 24, 9}}, - {m68k_op_and_32_re_ix , 0xf1f8, 0xc1b0, { 26, 26, 11}}, - {m68k_op_muls_16_d , 0xf1f8, 0xc1c0, { 54, 32, 27}}, - {m68k_op_muls_16_ai , 0xf1f8, 0xc1d0, { 58, 36, 31}}, - {m68k_op_muls_16_pi , 0xf1f8, 0xc1d8, { 58, 36, 31}}, - {m68k_op_muls_16_pd , 0xf1f8, 0xc1e0, { 60, 38, 32}}, - {m68k_op_muls_16_di , 0xf1f8, 0xc1e8, { 62, 40, 32}}, - {m68k_op_muls_16_ix , 0xf1f8, 0xc1f0, { 64, 42, 34}}, - {m68k_op_add_8_er_d , 0xf1f8, 0xd000, { 4, 4, 2}}, - {m68k_op_add_8_er_ai , 0xf1f8, 0xd010, { 8, 8, 6}}, - {m68k_op_add_8_er_pi , 0xf1f8, 0xd018, { 8, 8, 6}}, - {m68k_op_add_8_er_pd , 0xf1f8, 0xd020, { 10, 10, 7}}, - {m68k_op_add_8_er_di , 0xf1f8, 0xd028, { 12, 12, 7}}, - {m68k_op_add_8_er_ix , 0xf1f8, 0xd030, { 14, 14, 9}}, - {m68k_op_add_16_er_d , 0xf1f8, 0xd040, { 4, 4, 2}}, - {m68k_op_add_16_er_a , 0xf1f8, 0xd048, { 4, 4, 2}}, - {m68k_op_add_16_er_ai , 0xf1f8, 0xd050, { 8, 8, 6}}, - {m68k_op_add_16_er_pi , 0xf1f8, 0xd058, { 8, 8, 6}}, - {m68k_op_add_16_er_pd , 0xf1f8, 0xd060, { 10, 10, 7}}, - {m68k_op_add_16_er_di , 0xf1f8, 0xd068, { 12, 12, 7}}, - {m68k_op_add_16_er_ix , 0xf1f8, 0xd070, { 14, 14, 9}}, - {m68k_op_add_32_er_d , 0xf1f8, 0xd080, { 6, 6, 2}}, - {m68k_op_add_32_er_a , 0xf1f8, 0xd088, { 6, 6, 2}}, - {m68k_op_add_32_er_ai , 0xf1f8, 0xd090, { 14, 14, 6}}, - {m68k_op_add_32_er_pi , 0xf1f8, 0xd098, { 14, 14, 6}}, - {m68k_op_add_32_er_pd , 0xf1f8, 0xd0a0, { 16, 16, 7}}, - {m68k_op_add_32_er_di , 0xf1f8, 0xd0a8, { 18, 18, 7}}, - {m68k_op_add_32_er_ix , 0xf1f8, 0xd0b0, { 20, 20, 9}}, - {m68k_op_adda_16_d , 0xf1f8, 0xd0c0, { 8, 8, 2}}, - {m68k_op_adda_16_a , 0xf1f8, 0xd0c8, { 8, 8, 2}}, - {m68k_op_adda_16_ai , 0xf1f8, 0xd0d0, { 12, 12, 6}}, - {m68k_op_adda_16_pi , 0xf1f8, 0xd0d8, { 12, 12, 6}}, - {m68k_op_adda_16_pd , 0xf1f8, 0xd0e0, { 14, 14, 7}}, - {m68k_op_adda_16_di , 0xf1f8, 0xd0e8, { 16, 16, 7}}, - {m68k_op_adda_16_ix , 0xf1f8, 0xd0f0, { 18, 18, 9}}, - {m68k_op_addx_8_rr , 0xf1f8, 0xd100, { 4, 4, 2}}, - {m68k_op_addx_8_mm , 0xf1f8, 0xd108, { 18, 18, 12}}, - {m68k_op_add_8_re_ai , 0xf1f8, 0xd110, { 12, 12, 8}}, - {m68k_op_add_8_re_pi , 0xf1f8, 0xd118, { 12, 12, 8}}, - {m68k_op_add_8_re_pd , 0xf1f8, 0xd120, { 14, 14, 9}}, - {m68k_op_add_8_re_di , 0xf1f8, 0xd128, { 16, 16, 9}}, - {m68k_op_add_8_re_ix , 0xf1f8, 0xd130, { 18, 18, 11}}, - {m68k_op_addx_16_rr , 0xf1f8, 0xd140, { 4, 4, 2}}, - {m68k_op_addx_16_mm , 0xf1f8, 0xd148, { 18, 18, 12}}, - {m68k_op_add_16_re_ai , 0xf1f8, 0xd150, { 12, 12, 8}}, - {m68k_op_add_16_re_pi , 0xf1f8, 0xd158, { 12, 12, 8}}, - {m68k_op_add_16_re_pd , 0xf1f8, 0xd160, { 14, 14, 9}}, - {m68k_op_add_16_re_di , 0xf1f8, 0xd168, { 16, 16, 9}}, - {m68k_op_add_16_re_ix , 0xf1f8, 0xd170, { 18, 18, 11}}, - {m68k_op_addx_32_rr , 0xf1f8, 0xd180, { 8, 6, 2}}, - {m68k_op_addx_32_mm , 0xf1f8, 0xd188, { 30, 30, 12}}, - {m68k_op_add_32_re_ai , 0xf1f8, 0xd190, { 20, 20, 8}}, - {m68k_op_add_32_re_pi , 0xf1f8, 0xd198, { 20, 20, 8}}, - {m68k_op_add_32_re_pd , 0xf1f8, 0xd1a0, { 22, 22, 9}}, - {m68k_op_add_32_re_di , 0xf1f8, 0xd1a8, { 24, 24, 9}}, - {m68k_op_add_32_re_ix , 0xf1f8, 0xd1b0, { 26, 26, 11}}, - {m68k_op_adda_32_d , 0xf1f8, 0xd1c0, { 6, 6, 2}}, - {m68k_op_adda_32_a , 0xf1f8, 0xd1c8, { 6, 6, 2}}, - {m68k_op_adda_32_ai , 0xf1f8, 0xd1d0, { 14, 14, 6}}, - {m68k_op_adda_32_pi , 0xf1f8, 0xd1d8, { 14, 14, 6}}, - {m68k_op_adda_32_pd , 0xf1f8, 0xd1e0, { 16, 16, 7}}, - {m68k_op_adda_32_di , 0xf1f8, 0xd1e8, { 18, 18, 7}}, - {m68k_op_adda_32_ix , 0xf1f8, 0xd1f0, { 20, 20, 9}}, - {m68k_op_asr_8_s , 0xf1f8, 0xe000, { 6, 6, 6}}, - {m68k_op_lsr_8_s , 0xf1f8, 0xe008, { 6, 6, 4}}, - {m68k_op_roxr_8_s , 0xf1f8, 0xe010, { 6, 6, 12}}, - {m68k_op_ror_8_s , 0xf1f8, 0xe018, { 6, 6, 8}}, - {m68k_op_asr_8_r , 0xf1f8, 0xe020, { 6, 6, 6}}, - {m68k_op_lsr_8_r , 0xf1f8, 0xe028, { 6, 6, 6}}, - {m68k_op_roxr_8_r , 0xf1f8, 0xe030, { 6, 6, 12}}, - {m68k_op_ror_8_r , 0xf1f8, 0xe038, { 6, 6, 8}}, - {m68k_op_asr_16_s , 0xf1f8, 0xe040, { 6, 6, 6}}, - {m68k_op_lsr_16_s , 0xf1f8, 0xe048, { 6, 6, 4}}, - {m68k_op_roxr_16_s , 0xf1f8, 0xe050, { 6, 6, 12}}, - {m68k_op_ror_16_s , 0xf1f8, 0xe058, { 6, 6, 8}}, - {m68k_op_asr_16_r , 0xf1f8, 0xe060, { 6, 6, 6}}, - {m68k_op_lsr_16_r , 0xf1f8, 0xe068, { 6, 6, 6}}, - {m68k_op_roxr_16_r , 0xf1f8, 0xe070, { 6, 6, 12}}, - {m68k_op_ror_16_r , 0xf1f8, 0xe078, { 6, 6, 8}}, - {m68k_op_asr_32_s , 0xf1f8, 0xe080, { 8, 8, 6}}, - {m68k_op_lsr_32_s , 0xf1f8, 0xe088, { 8, 8, 4}}, - {m68k_op_roxr_32_s , 0xf1f8, 0xe090, { 8, 8, 12}}, - {m68k_op_ror_32_s , 0xf1f8, 0xe098, { 8, 8, 8}}, - {m68k_op_asr_32_r , 0xf1f8, 0xe0a0, { 8, 8, 6}}, - {m68k_op_lsr_32_r , 0xf1f8, 0xe0a8, { 8, 8, 6}}, - {m68k_op_roxr_32_r , 0xf1f8, 0xe0b0, { 8, 8, 12}}, - {m68k_op_ror_32_r , 0xf1f8, 0xe0b8, { 8, 8, 8}}, - {m68k_op_asl_8_s , 0xf1f8, 0xe100, { 6, 6, 8}}, - {m68k_op_lsl_8_s , 0xf1f8, 0xe108, { 6, 6, 4}}, - {m68k_op_roxl_8_s , 0xf1f8, 0xe110, { 6, 6, 12}}, - {m68k_op_rol_8_s , 0xf1f8, 0xe118, { 6, 6, 8}}, - {m68k_op_asl_8_r , 0xf1f8, 0xe120, { 6, 6, 8}}, - {m68k_op_lsl_8_r , 0xf1f8, 0xe128, { 6, 6, 6}}, - {m68k_op_roxl_8_r , 0xf1f8, 0xe130, { 6, 6, 12}}, - {m68k_op_rol_8_r , 0xf1f8, 0xe138, { 6, 6, 8}}, - {m68k_op_asl_16_s , 0xf1f8, 0xe140, { 6, 6, 8}}, - {m68k_op_lsl_16_s , 0xf1f8, 0xe148, { 6, 6, 4}}, - {m68k_op_roxl_16_s , 0xf1f8, 0xe150, { 6, 6, 12}}, - {m68k_op_rol_16_s , 0xf1f8, 0xe158, { 6, 6, 8}}, - {m68k_op_asl_16_r , 0xf1f8, 0xe160, { 6, 6, 8}}, - {m68k_op_lsl_16_r , 0xf1f8, 0xe168, { 6, 6, 6}}, - {m68k_op_roxl_16_r , 0xf1f8, 0xe170, { 6, 6, 12}}, - {m68k_op_rol_16_r , 0xf1f8, 0xe178, { 6, 6, 8}}, - {m68k_op_asl_32_s , 0xf1f8, 0xe180, { 8, 8, 8}}, - {m68k_op_lsl_32_s , 0xf1f8, 0xe188, { 8, 8, 4}}, - {m68k_op_roxl_32_s , 0xf1f8, 0xe190, { 8, 8, 12}}, - {m68k_op_rol_32_s , 0xf1f8, 0xe198, { 8, 8, 8}}, - {m68k_op_asl_32_r , 0xf1f8, 0xe1a0, { 8, 8, 8}}, - {m68k_op_lsl_32_r , 0xf1f8, 0xe1a8, { 8, 8, 6}}, - {m68k_op_roxl_32_r , 0xf1f8, 0xe1b0, { 8, 8, 12}}, - {m68k_op_rol_32_r , 0xf1f8, 0xe1b8, { 8, 8, 8}}, - {m68k_op_cpdbcc_32 , 0xf1f8, 0xf048, { 0, 0, 4}}, - {m68k_op_cptrapcc_32 , 0xf1f8, 0xf078, { 0, 0, 4}}, - {m68k_op_rtm_32 , 0xfff0, 0x06c0, { 0, 0, 19}}, - {m68k_op_trap , 0xfff0, 0x4e40, { 4, 4, 4}}, - {m68k_op_btst_8_r_pi7 , 0xf1ff, 0x011f, { 8, 8, 8}}, - {m68k_op_btst_8_r_pd7 , 0xf1ff, 0x0127, { 10, 10, 9}}, - {m68k_op_btst_8_r_aw , 0xf1ff, 0x0138, { 12, 12, 8}}, - {m68k_op_btst_8_r_al , 0xf1ff, 0x0139, { 16, 16, 8}}, - {m68k_op_btst_8_r_pcdi , 0xf1ff, 0x013a, { 12, 12, 9}}, - {m68k_op_btst_8_r_pcix , 0xf1ff, 0x013b, { 14, 14, 11}}, - {m68k_op_btst_8_r_i , 0xf1ff, 0x013c, { 8, 8, 6}}, - {m68k_op_bchg_8_r_pi7 , 0xf1ff, 0x015f, { 12, 12, 8}}, - {m68k_op_bchg_8_r_pd7 , 0xf1ff, 0x0167, { 14, 14, 9}}, - {m68k_op_bchg_8_r_aw , 0xf1ff, 0x0178, { 16, 16, 8}}, - {m68k_op_bchg_8_r_al , 0xf1ff, 0x0179, { 20, 20, 8}}, - {m68k_op_bclr_8_r_pi7 , 0xf1ff, 0x019f, { 12, 14, 8}}, - {m68k_op_bclr_8_r_pd7 , 0xf1ff, 0x01a7, { 14, 16, 9}}, - {m68k_op_bclr_8_r_aw , 0xf1ff, 0x01b8, { 16, 18, 8}}, - {m68k_op_bclr_8_r_al , 0xf1ff, 0x01b9, { 20, 22, 8}}, - {m68k_op_bset_8_r_pi7 , 0xf1ff, 0x01df, { 12, 12, 8}}, - {m68k_op_bset_8_r_pd7 , 0xf1ff, 0x01e7, { 14, 14, 9}}, - {m68k_op_bset_8_r_aw , 0xf1ff, 0x01f8, { 16, 16, 8}}, - {m68k_op_bset_8_r_al , 0xf1ff, 0x01f9, { 20, 20, 8}}, - {m68k_op_move_8_d_pi7 , 0xf1ff, 0x101f, { 8, 8, 6}}, - {m68k_op_move_8_d_pd7 , 0xf1ff, 0x1027, { 10, 10, 7}}, - {m68k_op_move_8_d_aw , 0xf1ff, 0x1038, { 12, 12, 6}}, - {m68k_op_move_8_d_al , 0xf1ff, 0x1039, { 16, 16, 6}}, - {m68k_op_move_8_d_pcdi , 0xf1ff, 0x103a, { 12, 12, 7}}, - {m68k_op_move_8_d_pcix , 0xf1ff, 0x103b, { 14, 14, 9}}, - {m68k_op_move_8_d_i , 0xf1ff, 0x103c, { 8, 8, 4}}, - {m68k_op_move_8_ai_pi7 , 0xf1ff, 0x109f, { 12, 12, 8}}, - {m68k_op_move_8_ai_pd7 , 0xf1ff, 0x10a7, { 14, 14, 9}}, - {m68k_op_move_8_ai_aw , 0xf1ff, 0x10b8, { 16, 16, 8}}, - {m68k_op_move_8_ai_al , 0xf1ff, 0x10b9, { 20, 20, 8}}, - {m68k_op_move_8_ai_pcdi , 0xf1ff, 0x10ba, { 16, 16, 9}}, - {m68k_op_move_8_ai_pcix , 0xf1ff, 0x10bb, { 18, 18, 11}}, - {m68k_op_move_8_ai_i , 0xf1ff, 0x10bc, { 12, 12, 6}}, - {m68k_op_move_8_pi_pi7 , 0xf1ff, 0x10df, { 12, 12, 8}}, - {m68k_op_move_8_pi_pd7 , 0xf1ff, 0x10e7, { 14, 14, 9}}, - {m68k_op_move_8_pi_aw , 0xf1ff, 0x10f8, { 16, 16, 8}}, - {m68k_op_move_8_pi_al , 0xf1ff, 0x10f9, { 20, 20, 8}}, - {m68k_op_move_8_pi_pcdi , 0xf1ff, 0x10fa, { 16, 16, 9}}, - {m68k_op_move_8_pi_pcix , 0xf1ff, 0x10fb, { 18, 18, 11}}, - {m68k_op_move_8_pi_i , 0xf1ff, 0x10fc, { 12, 12, 6}}, - {m68k_op_move_8_pd_pi7 , 0xf1ff, 0x111f, { 12, 12, 9}}, - {m68k_op_move_8_pd_pd7 , 0xf1ff, 0x1127, { 14, 14, 10}}, - {m68k_op_move_8_pd_aw , 0xf1ff, 0x1138, { 16, 16, 9}}, - {m68k_op_move_8_pd_al , 0xf1ff, 0x1139, { 20, 20, 9}}, - {m68k_op_move_8_pd_pcdi , 0xf1ff, 0x113a, { 16, 16, 10}}, - {m68k_op_move_8_pd_pcix , 0xf1ff, 0x113b, { 18, 18, 12}}, - {m68k_op_move_8_pd_i , 0xf1ff, 0x113c, { 12, 12, 7}}, - {m68k_op_move_8_di_pi7 , 0xf1ff, 0x115f, { 16, 16, 9}}, - {m68k_op_move_8_di_pd7 , 0xf1ff, 0x1167, { 18, 18, 10}}, - {m68k_op_move_8_di_aw , 0xf1ff, 0x1178, { 20, 20, 9}}, - {m68k_op_move_8_di_al , 0xf1ff, 0x1179, { 24, 24, 9}}, - {m68k_op_move_8_di_pcdi , 0xf1ff, 0x117a, { 20, 20, 10}}, - {m68k_op_move_8_di_pcix , 0xf1ff, 0x117b, { 22, 22, 12}}, - {m68k_op_move_8_di_i , 0xf1ff, 0x117c, { 16, 16, 7}}, - {m68k_op_move_8_ix_pi7 , 0xf1ff, 0x119f, { 18, 18, 11}}, - {m68k_op_move_8_ix_pd7 , 0xf1ff, 0x11a7, { 20, 20, 12}}, - {m68k_op_move_8_ix_aw , 0xf1ff, 0x11b8, { 22, 22, 11}}, - {m68k_op_move_8_ix_al , 0xf1ff, 0x11b9, { 26, 26, 11}}, - {m68k_op_move_8_ix_pcdi , 0xf1ff, 0x11ba, { 22, 22, 12}}, - {m68k_op_move_8_ix_pcix , 0xf1ff, 0x11bb, { 24, 24, 14}}, - {m68k_op_move_8_ix_i , 0xf1ff, 0x11bc, { 18, 18, 9}}, - {m68k_op_move_32_d_aw , 0xf1ff, 0x2038, { 16, 16, 6}}, - {m68k_op_move_32_d_al , 0xf1ff, 0x2039, { 20, 20, 6}}, - {m68k_op_move_32_d_pcdi , 0xf1ff, 0x203a, { 16, 16, 7}}, - {m68k_op_move_32_d_pcix , 0xf1ff, 0x203b, { 18, 18, 9}}, - {m68k_op_move_32_d_i , 0xf1ff, 0x203c, { 12, 12, 6}}, - {m68k_op_movea_32_aw , 0xf1ff, 0x2078, { 16, 16, 6}}, - {m68k_op_movea_32_al , 0xf1ff, 0x2079, { 20, 20, 6}}, - {m68k_op_movea_32_pcdi , 0xf1ff, 0x207a, { 16, 16, 7}}, - {m68k_op_movea_32_pcix , 0xf1ff, 0x207b, { 18, 18, 9}}, - {m68k_op_movea_32_i , 0xf1ff, 0x207c, { 12, 12, 6}}, - {m68k_op_move_32_ai_aw , 0xf1ff, 0x20b8, { 24, 24, 8}}, - {m68k_op_move_32_ai_al , 0xf1ff, 0x20b9, { 28, 28, 8}}, - {m68k_op_move_32_ai_pcdi , 0xf1ff, 0x20ba, { 24, 24, 9}}, - {m68k_op_move_32_ai_pcix , 0xf1ff, 0x20bb, { 26, 26, 11}}, - {m68k_op_move_32_ai_i , 0xf1ff, 0x20bc, { 20, 20, 8}}, - {m68k_op_move_32_pi_aw , 0xf1ff, 0x20f8, { 24, 24, 8}}, - {m68k_op_move_32_pi_al , 0xf1ff, 0x20f9, { 28, 28, 8}}, - {m68k_op_move_32_pi_pcdi , 0xf1ff, 0x20fa, { 24, 24, 9}}, - {m68k_op_move_32_pi_pcix , 0xf1ff, 0x20fb, { 26, 26, 11}}, - {m68k_op_move_32_pi_i , 0xf1ff, 0x20fc, { 20, 20, 8}}, - {m68k_op_move_32_pd_aw , 0xf1ff, 0x2138, { 24, 26, 9}}, - {m68k_op_move_32_pd_al , 0xf1ff, 0x2139, { 28, 30, 9}}, - {m68k_op_move_32_pd_pcdi , 0xf1ff, 0x213a, { 24, 26, 10}}, - {m68k_op_move_32_pd_pcix , 0xf1ff, 0x213b, { 26, 28, 12}}, - {m68k_op_move_32_pd_i , 0xf1ff, 0x213c, { 20, 22, 9}}, - {m68k_op_move_32_di_aw , 0xf1ff, 0x2178, { 28, 28, 9}}, - {m68k_op_move_32_di_al , 0xf1ff, 0x2179, { 32, 32, 9}}, - {m68k_op_move_32_di_pcdi , 0xf1ff, 0x217a, { 28, 28, 10}}, - {m68k_op_move_32_di_pcix , 0xf1ff, 0x217b, { 30, 30, 12}}, - {m68k_op_move_32_di_i , 0xf1ff, 0x217c, { 24, 24, 9}}, - {m68k_op_move_32_ix_aw , 0xf1ff, 0x21b8, { 30, 30, 11}}, - {m68k_op_move_32_ix_al , 0xf1ff, 0x21b9, { 34, 34, 11}}, - {m68k_op_move_32_ix_pcdi , 0xf1ff, 0x21ba, { 30, 30, 12}}, - {m68k_op_move_32_ix_pcix , 0xf1ff, 0x21bb, { 32, 32, 14}}, - {m68k_op_move_32_ix_i , 0xf1ff, 0x21bc, { 26, 26, 11}}, - {m68k_op_move_16_d_aw , 0xf1ff, 0x3038, { 12, 12, 6}}, - {m68k_op_move_16_d_al , 0xf1ff, 0x3039, { 16, 16, 6}}, - {m68k_op_move_16_d_pcdi , 0xf1ff, 0x303a, { 12, 12, 7}}, - {m68k_op_move_16_d_pcix , 0xf1ff, 0x303b, { 14, 14, 9}}, - {m68k_op_move_16_d_i , 0xf1ff, 0x303c, { 8, 8, 4}}, - {m68k_op_movea_16_aw , 0xf1ff, 0x3078, { 12, 12, 6}}, - {m68k_op_movea_16_al , 0xf1ff, 0x3079, { 16, 16, 6}}, - {m68k_op_movea_16_pcdi , 0xf1ff, 0x307a, { 12, 12, 7}}, - {m68k_op_movea_16_pcix , 0xf1ff, 0x307b, { 14, 14, 9}}, - {m68k_op_movea_16_i , 0xf1ff, 0x307c, { 8, 8, 4}}, - {m68k_op_move_16_ai_aw , 0xf1ff, 0x30b8, { 16, 16, 8}}, - {m68k_op_move_16_ai_al , 0xf1ff, 0x30b9, { 20, 20, 8}}, - {m68k_op_move_16_ai_pcdi , 0xf1ff, 0x30ba, { 16, 16, 9}}, - {m68k_op_move_16_ai_pcix , 0xf1ff, 0x30bb, { 18, 18, 11}}, - {m68k_op_move_16_ai_i , 0xf1ff, 0x30bc, { 12, 12, 6}}, - {m68k_op_move_16_pi_aw , 0xf1ff, 0x30f8, { 16, 16, 8}}, - {m68k_op_move_16_pi_al , 0xf1ff, 0x30f9, { 20, 20, 8}}, - {m68k_op_move_16_pi_pcdi , 0xf1ff, 0x30fa, { 16, 16, 9}}, - {m68k_op_move_16_pi_pcix , 0xf1ff, 0x30fb, { 18, 18, 11}}, - {m68k_op_move_16_pi_i , 0xf1ff, 0x30fc, { 12, 12, 6}}, - {m68k_op_move_16_pd_aw , 0xf1ff, 0x3138, { 16, 16, 9}}, - {m68k_op_move_16_pd_al , 0xf1ff, 0x3139, { 20, 20, 9}}, - {m68k_op_move_16_pd_pcdi , 0xf1ff, 0x313a, { 16, 16, 10}}, - {m68k_op_move_16_pd_pcix , 0xf1ff, 0x313b, { 18, 18, 12}}, - {m68k_op_move_16_pd_i , 0xf1ff, 0x313c, { 12, 12, 7}}, - {m68k_op_move_16_di_aw , 0xf1ff, 0x3178, { 20, 20, 9}}, - {m68k_op_move_16_di_al , 0xf1ff, 0x3179, { 24, 24, 9}}, - {m68k_op_move_16_di_pcdi , 0xf1ff, 0x317a, { 20, 20, 10}}, - {m68k_op_move_16_di_pcix , 0xf1ff, 0x317b, { 22, 22, 12}}, - {m68k_op_move_16_di_i , 0xf1ff, 0x317c, { 16, 16, 7}}, - {m68k_op_move_16_ix_aw , 0xf1ff, 0x31b8, { 22, 22, 11}}, - {m68k_op_move_16_ix_al , 0xf1ff, 0x31b9, { 26, 26, 11}}, - {m68k_op_move_16_ix_pcdi , 0xf1ff, 0x31ba, { 22, 22, 12}}, - {m68k_op_move_16_ix_pcix , 0xf1ff, 0x31bb, { 24, 24, 14}}, - {m68k_op_move_16_ix_i , 0xf1ff, 0x31bc, { 18, 18, 9}}, - {m68k_op_chk_32_aw , 0xf1ff, 0x4138, { 0, 0, 12}}, - {m68k_op_chk_32_al , 0xf1ff, 0x4139, { 0, 0, 12}}, - {m68k_op_chk_32_pcdi , 0xf1ff, 0x413a, { 0, 0, 13}}, - {m68k_op_chk_32_pcix , 0xf1ff, 0x413b, { 0, 0, 15}}, - {m68k_op_chk_32_i , 0xf1ff, 0x413c, { 0, 0, 12}}, - {m68k_op_chk_16_aw , 0xf1ff, 0x41b8, { 18, 16, 12}}, - {m68k_op_chk_16_al , 0xf1ff, 0x41b9, { 22, 20, 12}}, - {m68k_op_chk_16_pcdi , 0xf1ff, 0x41ba, { 18, 16, 13}}, - {m68k_op_chk_16_pcix , 0xf1ff, 0x41bb, { 20, 18, 15}}, - {m68k_op_chk_16_i , 0xf1ff, 0x41bc, { 14, 12, 10}}, - {m68k_op_lea_32_aw , 0xf1ff, 0x41f8, { 8, 8, 6}}, - {m68k_op_lea_32_al , 0xf1ff, 0x41f9, { 12, 12, 6}}, - {m68k_op_lea_32_pcdi , 0xf1ff, 0x41fa, { 8, 8, 7}}, - {m68k_op_lea_32_pcix , 0xf1ff, 0x41fb, { 12, 12, 9}}, - {m68k_op_addq_8_pi7 , 0xf1ff, 0x501f, { 12, 12, 8}}, - {m68k_op_addq_8_pd7 , 0xf1ff, 0x5027, { 14, 14, 9}}, - {m68k_op_addq_8_aw , 0xf1ff, 0x5038, { 16, 16, 8}}, - {m68k_op_addq_8_al , 0xf1ff, 0x5039, { 20, 20, 8}}, - {m68k_op_addq_16_aw , 0xf1ff, 0x5078, { 16, 16, 8}}, - {m68k_op_addq_16_al , 0xf1ff, 0x5079, { 20, 20, 8}}, - {m68k_op_addq_32_aw , 0xf1ff, 0x50b8, { 24, 24, 8}}, - {m68k_op_addq_32_al , 0xf1ff, 0x50b9, { 28, 28, 8}}, - {m68k_op_subq_8_pi7 , 0xf1ff, 0x511f, { 12, 12, 8}}, - {m68k_op_subq_8_pd7 , 0xf1ff, 0x5127, { 14, 14, 9}}, - {m68k_op_subq_8_aw , 0xf1ff, 0x5138, { 16, 16, 8}}, - {m68k_op_subq_8_al , 0xf1ff, 0x5139, { 20, 20, 8}}, - {m68k_op_subq_16_aw , 0xf1ff, 0x5178, { 16, 16, 8}}, - {m68k_op_subq_16_al , 0xf1ff, 0x5179, { 20, 20, 8}}, - {m68k_op_subq_32_aw , 0xf1ff, 0x51b8, { 24, 24, 8}}, - {m68k_op_subq_32_al , 0xf1ff, 0x51b9, { 28, 28, 8}}, - {m68k_op_or_8_er_pi7 , 0xf1ff, 0x801f, { 8, 8, 6}}, - {m68k_op_or_8_er_pd7 , 0xf1ff, 0x8027, { 10, 10, 7}}, - {m68k_op_or_8_er_aw , 0xf1ff, 0x8038, { 12, 12, 6}}, - {m68k_op_or_8_er_al , 0xf1ff, 0x8039, { 16, 16, 6}}, - {m68k_op_or_8_er_pcdi , 0xf1ff, 0x803a, { 12, 12, 7}}, - {m68k_op_or_8_er_pcix , 0xf1ff, 0x803b, { 14, 14, 9}}, - {m68k_op_or_8_er_i , 0xf1ff, 0x803c, { 10, 8, 4}}, - {m68k_op_or_16_er_aw , 0xf1ff, 0x8078, { 12, 12, 6}}, - {m68k_op_or_16_er_al , 0xf1ff, 0x8079, { 16, 16, 6}}, - {m68k_op_or_16_er_pcdi , 0xf1ff, 0x807a, { 12, 12, 7}}, - {m68k_op_or_16_er_pcix , 0xf1ff, 0x807b, { 14, 14, 9}}, - {m68k_op_or_16_er_i , 0xf1ff, 0x807c, { 10, 8, 4}}, - {m68k_op_or_32_er_aw , 0xf1ff, 0x80b8, { 18, 18, 6}}, - {m68k_op_or_32_er_al , 0xf1ff, 0x80b9, { 22, 22, 6}}, - {m68k_op_or_32_er_pcdi , 0xf1ff, 0x80ba, { 18, 18, 7}}, - {m68k_op_or_32_er_pcix , 0xf1ff, 0x80bb, { 20, 20, 9}}, - {m68k_op_or_32_er_i , 0xf1ff, 0x80bc, { 16, 14, 6}}, - {m68k_op_divu_16_aw , 0xf1ff, 0x80f8, {148, 116, 48}}, - {m68k_op_divu_16_al , 0xf1ff, 0x80f9, {152, 120, 48}}, - {m68k_op_divu_16_pcdi , 0xf1ff, 0x80fa, {148, 116, 49}}, - {m68k_op_divu_16_pcix , 0xf1ff, 0x80fb, {150, 118, 51}}, - {m68k_op_divu_16_i , 0xf1ff, 0x80fc, {144, 112, 46}}, - {m68k_op_sbcd_8_mm_ay7 , 0xf1ff, 0x810f, { 18, 18, 16}}, - {m68k_op_or_8_re_pi7 , 0xf1ff, 0x811f, { 12, 12, 8}}, - {m68k_op_or_8_re_pd7 , 0xf1ff, 0x8127, { 14, 14, 9}}, - {m68k_op_or_8_re_aw , 0xf1ff, 0x8138, { 16, 16, 8}}, - {m68k_op_or_8_re_al , 0xf1ff, 0x8139, { 20, 20, 8}}, - {m68k_op_pack_16_mm_ay7 , 0xf1ff, 0x814f, { 0, 0, 13}}, - {m68k_op_or_16_re_aw , 0xf1ff, 0x8178, { 16, 16, 8}}, - {m68k_op_or_16_re_al , 0xf1ff, 0x8179, { 20, 20, 8}}, - {m68k_op_unpk_16_mm_ay7 , 0xf1ff, 0x818f, { 0, 0, 13}}, - {m68k_op_or_32_re_aw , 0xf1ff, 0x81b8, { 24, 24, 8}}, - {m68k_op_or_32_re_al , 0xf1ff, 0x81b9, { 28, 28, 8}}, - {m68k_op_divs_16_aw , 0xf1ff, 0x81f8, {166, 130, 60}}, - {m68k_op_divs_16_al , 0xf1ff, 0x81f9, {170, 134, 60}}, - {m68k_op_divs_16_pcdi , 0xf1ff, 0x81fa, {166, 130, 61}}, - {m68k_op_divs_16_pcix , 0xf1ff, 0x81fb, {168, 132, 63}}, - {m68k_op_divs_16_i , 0xf1ff, 0x81fc, {162, 126, 58}}, - {m68k_op_sub_8_er_pi7 , 0xf1ff, 0x901f, { 8, 8, 6}}, - {m68k_op_sub_8_er_pd7 , 0xf1ff, 0x9027, { 10, 10, 7}}, - {m68k_op_sub_8_er_aw , 0xf1ff, 0x9038, { 12, 12, 6}}, - {m68k_op_sub_8_er_al , 0xf1ff, 0x9039, { 16, 16, 6}}, - {m68k_op_sub_8_er_pcdi , 0xf1ff, 0x903a, { 12, 12, 7}}, - {m68k_op_sub_8_er_pcix , 0xf1ff, 0x903b, { 14, 14, 9}}, - {m68k_op_sub_8_er_i , 0xf1ff, 0x903c, { 10, 8, 4}}, - {m68k_op_sub_16_er_aw , 0xf1ff, 0x9078, { 12, 12, 6}}, - {m68k_op_sub_16_er_al , 0xf1ff, 0x9079, { 16, 16, 6}}, - {m68k_op_sub_16_er_pcdi , 0xf1ff, 0x907a, { 12, 12, 7}}, - {m68k_op_sub_16_er_pcix , 0xf1ff, 0x907b, { 14, 14, 9}}, - {m68k_op_sub_16_er_i , 0xf1ff, 0x907c, { 10, 8, 4}}, - {m68k_op_sub_32_er_aw , 0xf1ff, 0x90b8, { 18, 18, 6}}, - {m68k_op_sub_32_er_al , 0xf1ff, 0x90b9, { 22, 22, 6}}, - {m68k_op_sub_32_er_pcdi , 0xf1ff, 0x90ba, { 18, 18, 7}}, - {m68k_op_sub_32_er_pcix , 0xf1ff, 0x90bb, { 20, 20, 9}}, - {m68k_op_sub_32_er_i , 0xf1ff, 0x90bc, { 16, 14, 6}}, - {m68k_op_suba_16_aw , 0xf1ff, 0x90f8, { 16, 16, 6}}, - {m68k_op_suba_16_al , 0xf1ff, 0x90f9, { 20, 20, 6}}, - {m68k_op_suba_16_pcdi , 0xf1ff, 0x90fa, { 16, 16, 7}}, - {m68k_op_suba_16_pcix , 0xf1ff, 0x90fb, { 18, 18, 9}}, - {m68k_op_suba_16_i , 0xf1ff, 0x90fc, { 14, 12, 4}}, - {m68k_op_subx_8_mm_ay7 , 0xf1ff, 0x910f, { 18, 18, 12}}, - {m68k_op_sub_8_re_pi7 , 0xf1ff, 0x911f, { 12, 12, 8}}, - {m68k_op_sub_8_re_pd7 , 0xf1ff, 0x9127, { 14, 14, 9}}, - {m68k_op_sub_8_re_aw , 0xf1ff, 0x9138, { 16, 16, 8}}, - {m68k_op_sub_8_re_al , 0xf1ff, 0x9139, { 20, 20, 8}}, - {m68k_op_sub_16_re_aw , 0xf1ff, 0x9178, { 16, 16, 8}}, - {m68k_op_sub_16_re_al , 0xf1ff, 0x9179, { 20, 20, 8}}, - {m68k_op_sub_32_re_aw , 0xf1ff, 0x91b8, { 24, 24, 8}}, - {m68k_op_sub_32_re_al , 0xf1ff, 0x91b9, { 28, 28, 8}}, - {m68k_op_suba_32_aw , 0xf1ff, 0x91f8, { 18, 18, 6}}, - {m68k_op_suba_32_al , 0xf1ff, 0x91f9, { 22, 22, 6}}, - {m68k_op_suba_32_pcdi , 0xf1ff, 0x91fa, { 18, 18, 7}}, - {m68k_op_suba_32_pcix , 0xf1ff, 0x91fb, { 20, 20, 9}}, - {m68k_op_suba_32_i , 0xf1ff, 0x91fc, { 16, 14, 6}}, - {m68k_op_cmp_8_pi7 , 0xf1ff, 0xb01f, { 8, 8, 6}}, - {m68k_op_cmp_8_pd7 , 0xf1ff, 0xb027, { 10, 10, 7}}, - {m68k_op_cmp_8_aw , 0xf1ff, 0xb038, { 12, 12, 6}}, - {m68k_op_cmp_8_al , 0xf1ff, 0xb039, { 16, 16, 6}}, - {m68k_op_cmp_8_pcdi , 0xf1ff, 0xb03a, { 12, 12, 7}}, - {m68k_op_cmp_8_pcix , 0xf1ff, 0xb03b, { 14, 14, 9}}, - {m68k_op_cmp_8_i , 0xf1ff, 0xb03c, { 8, 8, 4}}, - {m68k_op_cmp_16_aw , 0xf1ff, 0xb078, { 12, 12, 6}}, - {m68k_op_cmp_16_al , 0xf1ff, 0xb079, { 16, 16, 6}}, - {m68k_op_cmp_16_pcdi , 0xf1ff, 0xb07a, { 12, 12, 7}}, - {m68k_op_cmp_16_pcix , 0xf1ff, 0xb07b, { 14, 14, 9}}, - {m68k_op_cmp_16_i , 0xf1ff, 0xb07c, { 8, 8, 4}}, - {m68k_op_cmp_32_aw , 0xf1ff, 0xb0b8, { 18, 18, 6}}, - {m68k_op_cmp_32_al , 0xf1ff, 0xb0b9, { 22, 22, 6}}, - {m68k_op_cmp_32_pcdi , 0xf1ff, 0xb0ba, { 18, 18, 7}}, - {m68k_op_cmp_32_pcix , 0xf1ff, 0xb0bb, { 20, 20, 9}}, - {m68k_op_cmp_32_i , 0xf1ff, 0xb0bc, { 14, 14, 6}}, - {m68k_op_cmpa_16_aw , 0xf1ff, 0xb0f8, { 14, 14, 8}}, - {m68k_op_cmpa_16_al , 0xf1ff, 0xb0f9, { 18, 18, 8}}, - {m68k_op_cmpa_16_pcdi , 0xf1ff, 0xb0fa, { 14, 14, 9}}, - {m68k_op_cmpa_16_pcix , 0xf1ff, 0xb0fb, { 16, 16, 11}}, - {m68k_op_cmpa_16_i , 0xf1ff, 0xb0fc, { 10, 10, 6}}, - {m68k_op_cmpm_8_ay7 , 0xf1ff, 0xb10f, { 12, 12, 9}}, - {m68k_op_eor_8_pi7 , 0xf1ff, 0xb11f, { 12, 12, 8}}, - {m68k_op_eor_8_pd7 , 0xf1ff, 0xb127, { 14, 14, 9}}, - {m68k_op_eor_8_aw , 0xf1ff, 0xb138, { 16, 16, 8}}, - {m68k_op_eor_8_al , 0xf1ff, 0xb139, { 20, 20, 8}}, - {m68k_op_eor_16_aw , 0xf1ff, 0xb178, { 16, 16, 8}}, - {m68k_op_eor_16_al , 0xf1ff, 0xb179, { 20, 20, 8}}, - {m68k_op_eor_32_aw , 0xf1ff, 0xb1b8, { 24, 24, 8}}, - {m68k_op_eor_32_al , 0xf1ff, 0xb1b9, { 28, 28, 8}}, - {m68k_op_cmpa_32_aw , 0xf1ff, 0xb1f8, { 18, 18, 8}}, - {m68k_op_cmpa_32_al , 0xf1ff, 0xb1f9, { 22, 22, 8}}, - {m68k_op_cmpa_32_pcdi , 0xf1ff, 0xb1fa, { 18, 18, 9}}, - {m68k_op_cmpa_32_pcix , 0xf1ff, 0xb1fb, { 20, 20, 11}}, - {m68k_op_cmpa_32_i , 0xf1ff, 0xb1fc, { 14, 14, 8}}, - {m68k_op_and_8_er_pi7 , 0xf1ff, 0xc01f, { 8, 8, 6}}, - {m68k_op_and_8_er_pd7 , 0xf1ff, 0xc027, { 10, 10, 7}}, - {m68k_op_and_8_er_aw , 0xf1ff, 0xc038, { 12, 12, 6}}, - {m68k_op_and_8_er_al , 0xf1ff, 0xc039, { 16, 16, 6}}, - {m68k_op_and_8_er_pcdi , 0xf1ff, 0xc03a, { 12, 12, 7}}, - {m68k_op_and_8_er_pcix , 0xf1ff, 0xc03b, { 14, 14, 9}}, - {m68k_op_and_8_er_i , 0xf1ff, 0xc03c, { 10, 8, 4}}, - {m68k_op_and_16_er_aw , 0xf1ff, 0xc078, { 12, 12, 6}}, - {m68k_op_and_16_er_al , 0xf1ff, 0xc079, { 16, 16, 6}}, - {m68k_op_and_16_er_pcdi , 0xf1ff, 0xc07a, { 12, 12, 7}}, - {m68k_op_and_16_er_pcix , 0xf1ff, 0xc07b, { 14, 14, 9}}, - {m68k_op_and_16_er_i , 0xf1ff, 0xc07c, { 10, 8, 4}}, - {m68k_op_and_32_er_aw , 0xf1ff, 0xc0b8, { 18, 18, 6}}, - {m68k_op_and_32_er_al , 0xf1ff, 0xc0b9, { 22, 22, 6}}, - {m68k_op_and_32_er_pcdi , 0xf1ff, 0xc0ba, { 18, 18, 7}}, - {m68k_op_and_32_er_pcix , 0xf1ff, 0xc0bb, { 20, 20, 9}}, - {m68k_op_and_32_er_i , 0xf1ff, 0xc0bc, { 16, 14, 6}}, - {m68k_op_mulu_16_aw , 0xf1ff, 0xc0f8, { 62, 38, 31}}, - {m68k_op_mulu_16_al , 0xf1ff, 0xc0f9, { 66, 42, 31}}, - {m68k_op_mulu_16_pcdi , 0xf1ff, 0xc0fa, { 62, 38, 32}}, - {m68k_op_mulu_16_pcix , 0xf1ff, 0xc0fb, { 64, 40, 34}}, - {m68k_op_mulu_16_i , 0xf1ff, 0xc0fc, { 58, 34, 29}}, - {m68k_op_abcd_8_mm_ay7 , 0xf1ff, 0xc10f, { 18, 18, 16}}, - {m68k_op_and_8_re_pi7 , 0xf1ff, 0xc11f, { 12, 12, 8}}, - {m68k_op_and_8_re_pd7 , 0xf1ff, 0xc127, { 14, 14, 9}}, - {m68k_op_and_8_re_aw , 0xf1ff, 0xc138, { 16, 16, 8}}, - {m68k_op_and_8_re_al , 0xf1ff, 0xc139, { 20, 20, 8}}, - {m68k_op_and_16_re_aw , 0xf1ff, 0xc178, { 16, 16, 8}}, - {m68k_op_and_16_re_al , 0xf1ff, 0xc179, { 20, 20, 8}}, - {m68k_op_and_32_re_aw , 0xf1ff, 0xc1b8, { 24, 24, 8}}, - {m68k_op_and_32_re_al , 0xf1ff, 0xc1b9, { 28, 28, 8}}, - {m68k_op_muls_16_aw , 0xf1ff, 0xc1f8, { 62, 40, 31}}, - {m68k_op_muls_16_al , 0xf1ff, 0xc1f9, { 66, 44, 31}}, - {m68k_op_muls_16_pcdi , 0xf1ff, 0xc1fa, { 62, 40, 32}}, - {m68k_op_muls_16_pcix , 0xf1ff, 0xc1fb, { 64, 42, 34}}, - {m68k_op_muls_16_i , 0xf1ff, 0xc1fc, { 58, 36, 29}}, - {m68k_op_add_8_er_pi7 , 0xf1ff, 0xd01f, { 8, 8, 6}}, - {m68k_op_add_8_er_pd7 , 0xf1ff, 0xd027, { 10, 10, 7}}, - {m68k_op_add_8_er_aw , 0xf1ff, 0xd038, { 12, 12, 6}}, - {m68k_op_add_8_er_al , 0xf1ff, 0xd039, { 16, 16, 6}}, - {m68k_op_add_8_er_pcdi , 0xf1ff, 0xd03a, { 12, 12, 7}}, - {m68k_op_add_8_er_pcix , 0xf1ff, 0xd03b, { 14, 14, 9}}, - {m68k_op_add_8_er_i , 0xf1ff, 0xd03c, { 10, 8, 4}}, - {m68k_op_add_16_er_aw , 0xf1ff, 0xd078, { 12, 12, 6}}, - {m68k_op_add_16_er_al , 0xf1ff, 0xd079, { 16, 16, 6}}, - {m68k_op_add_16_er_pcdi , 0xf1ff, 0xd07a, { 12, 12, 7}}, - {m68k_op_add_16_er_pcix , 0xf1ff, 0xd07b, { 14, 14, 9}}, - {m68k_op_add_16_er_i , 0xf1ff, 0xd07c, { 10, 8, 4}}, - {m68k_op_add_32_er_aw , 0xf1ff, 0xd0b8, { 18, 18, 6}}, - {m68k_op_add_32_er_al , 0xf1ff, 0xd0b9, { 22, 22, 6}}, - {m68k_op_add_32_er_pcdi , 0xf1ff, 0xd0ba, { 18, 18, 7}}, - {m68k_op_add_32_er_pcix , 0xf1ff, 0xd0bb, { 20, 20, 9}}, - {m68k_op_add_32_er_i , 0xf1ff, 0xd0bc, { 16, 14, 6}}, - {m68k_op_adda_16_aw , 0xf1ff, 0xd0f8, { 16, 16, 6}}, - {m68k_op_adda_16_al , 0xf1ff, 0xd0f9, { 20, 20, 6}}, - {m68k_op_adda_16_pcdi , 0xf1ff, 0xd0fa, { 16, 16, 7}}, - {m68k_op_adda_16_pcix , 0xf1ff, 0xd0fb, { 18, 18, 9}}, - {m68k_op_adda_16_i , 0xf1ff, 0xd0fc, { 14, 12, 4}}, - {m68k_op_addx_8_mm_ay7 , 0xf1ff, 0xd10f, { 18, 18, 12}}, - {m68k_op_add_8_re_pi7 , 0xf1ff, 0xd11f, { 12, 12, 8}}, - {m68k_op_add_8_re_pd7 , 0xf1ff, 0xd127, { 14, 14, 9}}, - {m68k_op_add_8_re_aw , 0xf1ff, 0xd138, { 16, 16, 8}}, - {m68k_op_add_8_re_al , 0xf1ff, 0xd139, { 20, 20, 8}}, - {m68k_op_add_16_re_aw , 0xf1ff, 0xd178, { 16, 16, 8}}, - {m68k_op_add_16_re_al , 0xf1ff, 0xd179, { 20, 20, 8}}, - {m68k_op_add_32_re_aw , 0xf1ff, 0xd1b8, { 24, 24, 8}}, - {m68k_op_add_32_re_al , 0xf1ff, 0xd1b9, { 28, 28, 8}}, - {m68k_op_adda_32_aw , 0xf1ff, 0xd1f8, { 18, 18, 6}}, - {m68k_op_adda_32_al , 0xf1ff, 0xd1f9, { 22, 22, 6}}, - {m68k_op_adda_32_pcdi , 0xf1ff, 0xd1fa, { 18, 18, 7}}, - {m68k_op_adda_32_pcix , 0xf1ff, 0xd1fb, { 20, 20, 9}}, - {m68k_op_adda_32_i , 0xf1ff, 0xd1fc, { 16, 14, 6}}, - {m68k_op_ori_8_d , 0xfff8, 0x0000, { 8, 8, 2}}, - {m68k_op_ori_8_ai , 0xfff8, 0x0010, { 16, 16, 8}}, - {m68k_op_ori_8_pi , 0xfff8, 0x0018, { 16, 16, 8}}, - {m68k_op_ori_8_pd , 0xfff8, 0x0020, { 18, 18, 9}}, - {m68k_op_ori_8_di , 0xfff8, 0x0028, { 20, 20, 9}}, - {m68k_op_ori_8_ix , 0xfff8, 0x0030, { 22, 22, 11}}, - {m68k_op_ori_16_d , 0xfff8, 0x0040, { 8, 8, 2}}, - {m68k_op_ori_16_ai , 0xfff8, 0x0050, { 16, 16, 8}}, - {m68k_op_ori_16_pi , 0xfff8, 0x0058, { 16, 16, 8}}, - {m68k_op_ori_16_pd , 0xfff8, 0x0060, { 18, 18, 9}}, - {m68k_op_ori_16_di , 0xfff8, 0x0068, { 20, 20, 9}}, - {m68k_op_ori_16_ix , 0xfff8, 0x0070, { 22, 22, 11}}, - {m68k_op_ori_32_d , 0xfff8, 0x0080, { 16, 14, 2}}, - {m68k_op_ori_32_ai , 0xfff8, 0x0090, { 28, 28, 8}}, - {m68k_op_ori_32_pi , 0xfff8, 0x0098, { 28, 28, 8}}, - {m68k_op_ori_32_pd , 0xfff8, 0x00a0, { 30, 30, 9}}, - {m68k_op_ori_32_di , 0xfff8, 0x00a8, { 32, 32, 9}}, - {m68k_op_ori_32_ix , 0xfff8, 0x00b0, { 34, 34, 11}}, - {m68k_op_chk2cmp2_8_ai , 0xfff8, 0x00d0, { 0, 0, 22}}, - {m68k_op_chk2cmp2_8_di , 0xfff8, 0x00e8, { 0, 0, 23}}, - {m68k_op_chk2cmp2_8_ix , 0xfff8, 0x00f0, { 0, 0, 25}}, - {m68k_op_andi_8_d , 0xfff8, 0x0200, { 8, 8, 2}}, - {m68k_op_andi_8_ai , 0xfff8, 0x0210, { 16, 16, 8}}, - {m68k_op_andi_8_pi , 0xfff8, 0x0218, { 16, 16, 8}}, - {m68k_op_andi_8_pd , 0xfff8, 0x0220, { 18, 18, 9}}, - {m68k_op_andi_8_di , 0xfff8, 0x0228, { 20, 20, 9}}, - {m68k_op_andi_8_ix , 0xfff8, 0x0230, { 22, 22, 11}}, - {m68k_op_andi_16_d , 0xfff8, 0x0240, { 8, 8, 2}}, - {m68k_op_andi_16_ai , 0xfff8, 0x0250, { 16, 16, 8}}, - {m68k_op_andi_16_pi , 0xfff8, 0x0258, { 16, 16, 8}}, - {m68k_op_andi_16_pd , 0xfff8, 0x0260, { 18, 18, 9}}, - {m68k_op_andi_16_di , 0xfff8, 0x0268, { 20, 20, 9}}, - {m68k_op_andi_16_ix , 0xfff8, 0x0270, { 22, 22, 11}}, - {m68k_op_andi_32_d , 0xfff8, 0x0280, { 14, 14, 2}}, - {m68k_op_andi_32_ai , 0xfff8, 0x0290, { 28, 28, 8}}, - {m68k_op_andi_32_pi , 0xfff8, 0x0298, { 28, 28, 8}}, - {m68k_op_andi_32_pd , 0xfff8, 0x02a0, { 30, 30, 9}}, - {m68k_op_andi_32_di , 0xfff8, 0x02a8, { 32, 32, 9}}, - {m68k_op_andi_32_ix , 0xfff8, 0x02b0, { 34, 34, 11}}, - {m68k_op_chk2cmp2_16_ai , 0xfff8, 0x02d0, { 0, 0, 22}}, - {m68k_op_chk2cmp2_16_di , 0xfff8, 0x02e8, { 0, 0, 23}}, - {m68k_op_chk2cmp2_16_ix , 0xfff8, 0x02f0, { 0, 0, 25}}, - {m68k_op_subi_8_d , 0xfff8, 0x0400, { 8, 8, 2}}, - {m68k_op_subi_8_ai , 0xfff8, 0x0410, { 16, 16, 8}}, - {m68k_op_subi_8_pi , 0xfff8, 0x0418, { 16, 16, 8}}, - {m68k_op_subi_8_pd , 0xfff8, 0x0420, { 18, 18, 9}}, - {m68k_op_subi_8_di , 0xfff8, 0x0428, { 20, 20, 9}}, - {m68k_op_subi_8_ix , 0xfff8, 0x0430, { 22, 22, 11}}, - {m68k_op_subi_16_d , 0xfff8, 0x0440, { 8, 8, 2}}, - {m68k_op_subi_16_ai , 0xfff8, 0x0450, { 16, 16, 8}}, - {m68k_op_subi_16_pi , 0xfff8, 0x0458, { 16, 16, 8}}, - {m68k_op_subi_16_pd , 0xfff8, 0x0460, { 18, 18, 9}}, - {m68k_op_subi_16_di , 0xfff8, 0x0468, { 20, 20, 9}}, - {m68k_op_subi_16_ix , 0xfff8, 0x0470, { 22, 22, 11}}, - {m68k_op_subi_32_d , 0xfff8, 0x0480, { 16, 14, 2}}, - {m68k_op_subi_32_ai , 0xfff8, 0x0490, { 28, 28, 8}}, - {m68k_op_subi_32_pi , 0xfff8, 0x0498, { 28, 28, 8}}, - {m68k_op_subi_32_pd , 0xfff8, 0x04a0, { 30, 30, 9}}, - {m68k_op_subi_32_di , 0xfff8, 0x04a8, { 32, 32, 9}}, - {m68k_op_subi_32_ix , 0xfff8, 0x04b0, { 34, 34, 11}}, - {m68k_op_chk2cmp2_32_ai , 0xfff8, 0x04d0, { 0, 0, 22}}, - {m68k_op_chk2cmp2_32_di , 0xfff8, 0x04e8, { 0, 0, 23}}, - {m68k_op_chk2cmp2_32_ix , 0xfff8, 0x04f0, { 0, 0, 25}}, - {m68k_op_addi_8_d , 0xfff8, 0x0600, { 8, 8, 2}}, - {m68k_op_addi_8_ai , 0xfff8, 0x0610, { 16, 16, 8}}, - {m68k_op_addi_8_pi , 0xfff8, 0x0618, { 16, 16, 8}}, - {m68k_op_addi_8_pd , 0xfff8, 0x0620, { 18, 18, 9}}, - {m68k_op_addi_8_di , 0xfff8, 0x0628, { 20, 20, 9}}, - {m68k_op_addi_8_ix , 0xfff8, 0x0630, { 22, 22, 11}}, - {m68k_op_addi_16_d , 0xfff8, 0x0640, { 8, 8, 2}}, - {m68k_op_addi_16_ai , 0xfff8, 0x0650, { 16, 16, 8}}, - {m68k_op_addi_16_pi , 0xfff8, 0x0658, { 16, 16, 8}}, - {m68k_op_addi_16_pd , 0xfff8, 0x0660, { 18, 18, 9}}, - {m68k_op_addi_16_di , 0xfff8, 0x0668, { 20, 20, 9}}, - {m68k_op_addi_16_ix , 0xfff8, 0x0670, { 22, 22, 11}}, - {m68k_op_addi_32_d , 0xfff8, 0x0680, { 16, 14, 2}}, - {m68k_op_addi_32_ai , 0xfff8, 0x0690, { 28, 28, 8}}, - {m68k_op_addi_32_pi , 0xfff8, 0x0698, { 28, 28, 8}}, - {m68k_op_addi_32_pd , 0xfff8, 0x06a0, { 30, 30, 9}}, - {m68k_op_addi_32_di , 0xfff8, 0x06a8, { 32, 32, 9}}, - {m68k_op_addi_32_ix , 0xfff8, 0x06b0, { 34, 34, 11}}, - {m68k_op_callm_32_ai , 0xfff8, 0x06d0, { 0, 0, 64}}, - {m68k_op_callm_32_di , 0xfff8, 0x06e8, { 0, 0, 65}}, - {m68k_op_callm_32_ix , 0xfff8, 0x06f0, { 0, 0, 67}}, - {m68k_op_btst_32_s_d , 0xfff8, 0x0800, { 10, 10, 4}}, - {m68k_op_btst_8_s_ai , 0xfff8, 0x0810, { 12, 12, 8}}, - {m68k_op_btst_8_s_pi , 0xfff8, 0x0818, { 12, 12, 8}}, - {m68k_op_btst_8_s_pd , 0xfff8, 0x0820, { 14, 14, 9}}, - {m68k_op_btst_8_s_di , 0xfff8, 0x0828, { 16, 16, 9}}, - {m68k_op_btst_8_s_ix , 0xfff8, 0x0830, { 18, 18, 11}}, - {m68k_op_bchg_32_s_d , 0xfff8, 0x0840, { 12, 12, 4}}, - {m68k_op_bchg_8_s_ai , 0xfff8, 0x0850, { 16, 16, 8}}, - {m68k_op_bchg_8_s_pi , 0xfff8, 0x0858, { 16, 16, 8}}, - {m68k_op_bchg_8_s_pd , 0xfff8, 0x0860, { 18, 18, 9}}, - {m68k_op_bchg_8_s_di , 0xfff8, 0x0868, { 20, 20, 9}}, - {m68k_op_bchg_8_s_ix , 0xfff8, 0x0870, { 22, 22, 11}}, - {m68k_op_bclr_32_s_d , 0xfff8, 0x0880, { 14, 14, 4}}, - {m68k_op_bclr_8_s_ai , 0xfff8, 0x0890, { 16, 16, 8}}, - {m68k_op_bclr_8_s_pi , 0xfff8, 0x0898, { 16, 16, 8}}, - {m68k_op_bclr_8_s_pd , 0xfff8, 0x08a0, { 18, 18, 9}}, - {m68k_op_bclr_8_s_di , 0xfff8, 0x08a8, { 20, 20, 9}}, - {m68k_op_bclr_8_s_ix , 0xfff8, 0x08b0, { 22, 22, 11}}, - {m68k_op_bset_32_s_d , 0xfff8, 0x08c0, { 12, 12, 4}}, - {m68k_op_bset_8_s_ai , 0xfff8, 0x08d0, { 16, 16, 8}}, - {m68k_op_bset_8_s_pi , 0xfff8, 0x08d8, { 16, 16, 8}}, - {m68k_op_bset_8_s_pd , 0xfff8, 0x08e0, { 18, 18, 9}}, - {m68k_op_bset_8_s_di , 0xfff8, 0x08e8, { 20, 20, 9}}, - {m68k_op_bset_8_s_ix , 0xfff8, 0x08f0, { 22, 22, 11}}, - {m68k_op_eori_8_d , 0xfff8, 0x0a00, { 8, 8, 2}}, - {m68k_op_eori_8_ai , 0xfff8, 0x0a10, { 16, 16, 8}}, - {m68k_op_eori_8_pi , 0xfff8, 0x0a18, { 16, 16, 8}}, - {m68k_op_eori_8_pd , 0xfff8, 0x0a20, { 18, 18, 9}}, - {m68k_op_eori_8_di , 0xfff8, 0x0a28, { 20, 20, 9}}, - {m68k_op_eori_8_ix , 0xfff8, 0x0a30, { 22, 22, 11}}, - {m68k_op_eori_16_d , 0xfff8, 0x0a40, { 8, 8, 2}}, - {m68k_op_eori_16_ai , 0xfff8, 0x0a50, { 16, 16, 8}}, - {m68k_op_eori_16_pi , 0xfff8, 0x0a58, { 16, 16, 8}}, - {m68k_op_eori_16_pd , 0xfff8, 0x0a60, { 18, 18, 9}}, - {m68k_op_eori_16_di , 0xfff8, 0x0a68, { 20, 20, 9}}, - {m68k_op_eori_16_ix , 0xfff8, 0x0a70, { 22, 22, 11}}, - {m68k_op_eori_32_d , 0xfff8, 0x0a80, { 16, 14, 2}}, - {m68k_op_eori_32_ai , 0xfff8, 0x0a90, { 28, 28, 8}}, - {m68k_op_eori_32_pi , 0xfff8, 0x0a98, { 28, 28, 8}}, - {m68k_op_eori_32_pd , 0xfff8, 0x0aa0, { 30, 30, 9}}, - {m68k_op_eori_32_di , 0xfff8, 0x0aa8, { 32, 32, 9}}, - {m68k_op_eori_32_ix , 0xfff8, 0x0ab0, { 34, 34, 11}}, - {m68k_op_cas_8_ai , 0xfff8, 0x0ad0, { 0, 0, 16}}, - {m68k_op_cas_8_pi , 0xfff8, 0x0ad8, { 0, 0, 16}}, - {m68k_op_cas_8_pd , 0xfff8, 0x0ae0, { 0, 0, 17}}, - {m68k_op_cas_8_di , 0xfff8, 0x0ae8, { 0, 0, 17}}, - {m68k_op_cas_8_ix , 0xfff8, 0x0af0, { 0, 0, 19}}, - {m68k_op_cmpi_8_d , 0xfff8, 0x0c00, { 8, 8, 2}}, - {m68k_op_cmpi_8_ai , 0xfff8, 0x0c10, { 12, 12, 6}}, - {m68k_op_cmpi_8_pi , 0xfff8, 0x0c18, { 12, 12, 6}}, - {m68k_op_cmpi_8_pd , 0xfff8, 0x0c20, { 14, 14, 7}}, - {m68k_op_cmpi_8_di , 0xfff8, 0x0c28, { 16, 16, 7}}, - {m68k_op_cmpi_8_ix , 0xfff8, 0x0c30, { 18, 18, 9}}, - {m68k_op_cmpi_16_d , 0xfff8, 0x0c40, { 8, 8, 2}}, - {m68k_op_cmpi_16_ai , 0xfff8, 0x0c50, { 12, 12, 6}}, - {m68k_op_cmpi_16_pi , 0xfff8, 0x0c58, { 12, 12, 6}}, - {m68k_op_cmpi_16_pd , 0xfff8, 0x0c60, { 14, 14, 7}}, - {m68k_op_cmpi_16_di , 0xfff8, 0x0c68, { 16, 16, 7}}, - {m68k_op_cmpi_16_ix , 0xfff8, 0x0c70, { 18, 18, 9}}, - {m68k_op_cmpi_32_d , 0xfff8, 0x0c80, { 14, 12, 2}}, - {m68k_op_cmpi_32_ai , 0xfff8, 0x0c90, { 20, 20, 6}}, - {m68k_op_cmpi_32_pi , 0xfff8, 0x0c98, { 20, 20, 6}}, - {m68k_op_cmpi_32_pd , 0xfff8, 0x0ca0, { 22, 22, 7}}, - {m68k_op_cmpi_32_di , 0xfff8, 0x0ca8, { 24, 24, 7}}, - {m68k_op_cmpi_32_ix , 0xfff8, 0x0cb0, { 26, 26, 9}}, - {m68k_op_cas_16_ai , 0xfff8, 0x0cd0, { 0, 0, 16}}, - {m68k_op_cas_16_pi , 0xfff8, 0x0cd8, { 0, 0, 16}}, - {m68k_op_cas_16_pd , 0xfff8, 0x0ce0, { 0, 0, 17}}, - {m68k_op_cas_16_di , 0xfff8, 0x0ce8, { 0, 0, 17}}, - {m68k_op_cas_16_ix , 0xfff8, 0x0cf0, { 0, 0, 19}}, - {m68k_op_moves_8_ai , 0xfff8, 0x0e10, { 0, 18, 9}}, - {m68k_op_moves_8_pi , 0xfff8, 0x0e18, { 0, 18, 9}}, - {m68k_op_moves_8_pd , 0xfff8, 0x0e20, { 0, 20, 10}}, - {m68k_op_moves_8_di , 0xfff8, 0x0e28, { 0, 26, 10}}, - {m68k_op_moves_8_ix , 0xfff8, 0x0e30, { 0, 30, 12}}, - {m68k_op_moves_16_ai , 0xfff8, 0x0e50, { 0, 18, 9}}, - {m68k_op_moves_16_pi , 0xfff8, 0x0e58, { 0, 18, 9}}, - {m68k_op_moves_16_pd , 0xfff8, 0x0e60, { 0, 20, 10}}, - {m68k_op_moves_16_di , 0xfff8, 0x0e68, { 0, 26, 10}}, - {m68k_op_moves_16_ix , 0xfff8, 0x0e70, { 0, 30, 12}}, - {m68k_op_moves_32_ai , 0xfff8, 0x0e90, { 0, 22, 9}}, - {m68k_op_moves_32_pi , 0xfff8, 0x0e98, { 0, 22, 9}}, - {m68k_op_moves_32_pd , 0xfff8, 0x0ea0, { 0, 28, 10}}, - {m68k_op_moves_32_di , 0xfff8, 0x0ea8, { 0, 32, 10}}, - {m68k_op_moves_32_ix , 0xfff8, 0x0eb0, { 0, 36, 12}}, - {m68k_op_cas_32_ai , 0xfff8, 0x0ed0, { 0, 0, 16}}, - {m68k_op_cas_32_pi , 0xfff8, 0x0ed8, { 0, 0, 16}}, - {m68k_op_cas_32_pd , 0xfff8, 0x0ee0, { 0, 0, 17}}, - {m68k_op_cas_32_di , 0xfff8, 0x0ee8, { 0, 0, 17}}, - {m68k_op_cas_32_ix , 0xfff8, 0x0ef0, { 0, 0, 19}}, - {m68k_op_move_8_aw_d , 0xfff8, 0x11c0, { 12, 12, 4}}, - {m68k_op_move_8_aw_ai , 0xfff8, 0x11d0, { 16, 16, 8}}, - {m68k_op_move_8_aw_pi , 0xfff8, 0x11d8, { 16, 16, 8}}, - {m68k_op_move_8_aw_pd , 0xfff8, 0x11e0, { 18, 18, 9}}, - {m68k_op_move_8_aw_di , 0xfff8, 0x11e8, { 20, 20, 9}}, - {m68k_op_move_8_aw_ix , 0xfff8, 0x11f0, { 22, 22, 11}}, - {m68k_op_move_8_al_d , 0xfff8, 0x13c0, { 16, 16, 6}}, - {m68k_op_move_8_al_ai , 0xfff8, 0x13d0, { 20, 20, 10}}, - {m68k_op_move_8_al_pi , 0xfff8, 0x13d8, { 20, 20, 10}}, - {m68k_op_move_8_al_pd , 0xfff8, 0x13e0, { 22, 22, 11}}, - {m68k_op_move_8_al_di , 0xfff8, 0x13e8, { 24, 24, 11}}, - {m68k_op_move_8_al_ix , 0xfff8, 0x13f0, { 26, 26, 13}}, - {m68k_op_move_8_pi7_d , 0xfff8, 0x1ec0, { 8, 8, 4}}, - {m68k_op_move_8_pi7_ai , 0xfff8, 0x1ed0, { 12, 12, 8}}, - {m68k_op_move_8_pi7_pi , 0xfff8, 0x1ed8, { 12, 12, 8}}, - {m68k_op_move_8_pi7_pd , 0xfff8, 0x1ee0, { 14, 14, 9}}, - {m68k_op_move_8_pi7_di , 0xfff8, 0x1ee8, { 16, 16, 9}}, - {m68k_op_move_8_pi7_ix , 0xfff8, 0x1ef0, { 18, 18, 11}}, - {m68k_op_move_8_pd7_d , 0xfff8, 0x1f00, { 8, 8, 5}}, - {m68k_op_move_8_pd7_ai , 0xfff8, 0x1f10, { 12, 12, 9}}, - {m68k_op_move_8_pd7_pi , 0xfff8, 0x1f18, { 12, 12, 9}}, - {m68k_op_move_8_pd7_pd , 0xfff8, 0x1f20, { 14, 14, 10}}, - {m68k_op_move_8_pd7_di , 0xfff8, 0x1f28, { 16, 16, 10}}, - {m68k_op_move_8_pd7_ix , 0xfff8, 0x1f30, { 18, 18, 12}}, - {m68k_op_move_32_aw_d , 0xfff8, 0x21c0, { 16, 16, 4}}, - {m68k_op_move_32_aw_a , 0xfff8, 0x21c8, { 16, 16, 4}}, - {m68k_op_move_32_aw_ai , 0xfff8, 0x21d0, { 24, 24, 8}}, - {m68k_op_move_32_aw_pi , 0xfff8, 0x21d8, { 24, 24, 8}}, - {m68k_op_move_32_aw_pd , 0xfff8, 0x21e0, { 26, 26, 9}}, - {m68k_op_move_32_aw_di , 0xfff8, 0x21e8, { 28, 28, 9}}, - {m68k_op_move_32_aw_ix , 0xfff8, 0x21f0, { 30, 30, 11}}, - {m68k_op_move_32_al_d , 0xfff8, 0x23c0, { 20, 20, 6}}, - {m68k_op_move_32_al_a , 0xfff8, 0x23c8, { 20, 20, 6}}, - {m68k_op_move_32_al_ai , 0xfff8, 0x23d0, { 28, 28, 10}}, - {m68k_op_move_32_al_pi , 0xfff8, 0x23d8, { 28, 28, 10}}, - {m68k_op_move_32_al_pd , 0xfff8, 0x23e0, { 30, 30, 11}}, - {m68k_op_move_32_al_di , 0xfff8, 0x23e8, { 32, 32, 11}}, - {m68k_op_move_32_al_ix , 0xfff8, 0x23f0, { 34, 34, 13}}, - {m68k_op_move_16_aw_d , 0xfff8, 0x31c0, { 12, 12, 4}}, - {m68k_op_move_16_aw_a , 0xfff8, 0x31c8, { 12, 12, 4}}, - {m68k_op_move_16_aw_ai , 0xfff8, 0x31d0, { 16, 16, 8}}, - {m68k_op_move_16_aw_pi , 0xfff8, 0x31d8, { 16, 16, 8}}, - {m68k_op_move_16_aw_pd , 0xfff8, 0x31e0, { 18, 18, 9}}, - {m68k_op_move_16_aw_di , 0xfff8, 0x31e8, { 20, 20, 9}}, - {m68k_op_move_16_aw_ix , 0xfff8, 0x31f0, { 22, 22, 11}}, - {m68k_op_move_16_al_d , 0xfff8, 0x33c0, { 16, 16, 6}}, - {m68k_op_move_16_al_a , 0xfff8, 0x33c8, { 16, 16, 6}}, - {m68k_op_move_16_al_ai , 0xfff8, 0x33d0, { 20, 20, 10}}, - {m68k_op_move_16_al_pi , 0xfff8, 0x33d8, { 20, 20, 10}}, - {m68k_op_move_16_al_pd , 0xfff8, 0x33e0, { 22, 22, 11}}, - {m68k_op_move_16_al_di , 0xfff8, 0x33e8, { 24, 24, 11}}, - {m68k_op_move_16_al_ix , 0xfff8, 0x33f0, { 26, 26, 13}}, - {m68k_op_negx_8_d , 0xfff8, 0x4000, { 4, 4, 2}}, - {m68k_op_negx_8_ai , 0xfff8, 0x4010, { 12, 12, 8}}, - {m68k_op_negx_8_pi , 0xfff8, 0x4018, { 12, 12, 8}}, - {m68k_op_negx_8_pd , 0xfff8, 0x4020, { 14, 14, 9}}, - {m68k_op_negx_8_di , 0xfff8, 0x4028, { 16, 16, 9}}, - {m68k_op_negx_8_ix , 0xfff8, 0x4030, { 18, 18, 11}}, - {m68k_op_negx_16_d , 0xfff8, 0x4040, { 4, 4, 2}}, - {m68k_op_negx_16_ai , 0xfff8, 0x4050, { 12, 12, 8}}, - {m68k_op_negx_16_pi , 0xfff8, 0x4058, { 12, 12, 8}}, - {m68k_op_negx_16_pd , 0xfff8, 0x4060, { 14, 14, 9}}, - {m68k_op_negx_16_di , 0xfff8, 0x4068, { 16, 16, 9}}, - {m68k_op_negx_16_ix , 0xfff8, 0x4070, { 18, 18, 11}}, - {m68k_op_negx_32_d , 0xfff8, 0x4080, { 6, 6, 2}}, - {m68k_op_negx_32_ai , 0xfff8, 0x4090, { 20, 20, 8}}, - {m68k_op_negx_32_pi , 0xfff8, 0x4098, { 20, 20, 8}}, - {m68k_op_negx_32_pd , 0xfff8, 0x40a0, { 22, 22, 9}}, - {m68k_op_negx_32_di , 0xfff8, 0x40a8, { 24, 24, 9}}, - {m68k_op_negx_32_ix , 0xfff8, 0x40b0, { 26, 26, 11}}, - {m68k_op_move_16_frs_d , 0xfff8, 0x40c0, { 6, 4, 8}}, - {m68k_op_move_16_frs_ai , 0xfff8, 0x40d0, { 12, 12, 12}}, - {m68k_op_move_16_frs_pi , 0xfff8, 0x40d8, { 12, 12, 12}}, - {m68k_op_move_16_frs_pd , 0xfff8, 0x40e0, { 14, 14, 13}}, - {m68k_op_move_16_frs_di , 0xfff8, 0x40e8, { 16, 16, 13}}, - {m68k_op_move_16_frs_ix , 0xfff8, 0x40f0, { 18, 18, 15}}, - {m68k_op_clr_8_d , 0xfff8, 0x4200, { 4, 4, 2}}, - {m68k_op_clr_8_ai , 0xfff8, 0x4210, { 12, 8, 8}}, - {m68k_op_clr_8_pi , 0xfff8, 0x4218, { 12, 8, 8}}, - {m68k_op_clr_8_pd , 0xfff8, 0x4220, { 14, 10, 9}}, - {m68k_op_clr_8_di , 0xfff8, 0x4228, { 16, 12, 9}}, - {m68k_op_clr_8_ix , 0xfff8, 0x4230, { 18, 14, 11}}, - {m68k_op_clr_16_d , 0xfff8, 0x4240, { 4, 4, 2}}, - {m68k_op_clr_16_ai , 0xfff8, 0x4250, { 12, 8, 8}}, - {m68k_op_clr_16_pi , 0xfff8, 0x4258, { 12, 8, 8}}, - {m68k_op_clr_16_pd , 0xfff8, 0x4260, { 14, 10, 9}}, - {m68k_op_clr_16_di , 0xfff8, 0x4268, { 16, 12, 9}}, - {m68k_op_clr_16_ix , 0xfff8, 0x4270, { 18, 14, 11}}, - {m68k_op_clr_32_d , 0xfff8, 0x4280, { 6, 6, 2}}, - {m68k_op_clr_32_ai , 0xfff8, 0x4290, { 20, 12, 8}}, - {m68k_op_clr_32_pi , 0xfff8, 0x4298, { 20, 12, 8}}, - {m68k_op_clr_32_pd , 0xfff8, 0x42a0, { 22, 14, 9}}, - {m68k_op_clr_32_di , 0xfff8, 0x42a8, { 24, 16, 9}}, - {m68k_op_clr_32_ix , 0xfff8, 0x42b0, { 26, 20, 11}}, - {m68k_op_move_16_frc_d , 0xfff8, 0x42c0, { 0, 4, 4}}, - {m68k_op_move_16_frc_ai , 0xfff8, 0x42d0, { 0, 12, 8}}, - {m68k_op_move_16_frc_pi , 0xfff8, 0x42d8, { 0, 12, 8}}, - {m68k_op_move_16_frc_pd , 0xfff8, 0x42e0, { 0, 14, 9}}, - {m68k_op_move_16_frc_di , 0xfff8, 0x42e8, { 0, 16, 9}}, - {m68k_op_move_16_frc_ix , 0xfff8, 0x42f0, { 0, 18, 11}}, - {m68k_op_neg_8_d , 0xfff8, 0x4400, { 4, 4, 2}}, - {m68k_op_neg_8_ai , 0xfff8, 0x4410, { 12, 12, 8}}, - {m68k_op_neg_8_pi , 0xfff8, 0x4418, { 12, 12, 8}}, - {m68k_op_neg_8_pd , 0xfff8, 0x4420, { 14, 14, 9}}, - {m68k_op_neg_8_di , 0xfff8, 0x4428, { 16, 16, 9}}, - {m68k_op_neg_8_ix , 0xfff8, 0x4430, { 18, 18, 11}}, - {m68k_op_neg_16_d , 0xfff8, 0x4440, { 4, 4, 2}}, - {m68k_op_neg_16_ai , 0xfff8, 0x4450, { 12, 12, 8}}, - {m68k_op_neg_16_pi , 0xfff8, 0x4458, { 12, 12, 8}}, - {m68k_op_neg_16_pd , 0xfff8, 0x4460, { 14, 14, 9}}, - {m68k_op_neg_16_di , 0xfff8, 0x4468, { 16, 16, 9}}, - {m68k_op_neg_16_ix , 0xfff8, 0x4470, { 18, 18, 11}}, - {m68k_op_neg_32_d , 0xfff8, 0x4480, { 6, 6, 2}}, - {m68k_op_neg_32_ai , 0xfff8, 0x4490, { 20, 20, 8}}, - {m68k_op_neg_32_pi , 0xfff8, 0x4498, { 20, 20, 8}}, - {m68k_op_neg_32_pd , 0xfff8, 0x44a0, { 22, 22, 9}}, - {m68k_op_neg_32_di , 0xfff8, 0x44a8, { 24, 24, 9}}, - {m68k_op_neg_32_ix , 0xfff8, 0x44b0, { 26, 26, 11}}, - {m68k_op_move_16_toc_d , 0xfff8, 0x44c0, { 12, 12, 4}}, - {m68k_op_move_16_toc_ai , 0xfff8, 0x44d0, { 16, 16, 8}}, - {m68k_op_move_16_toc_pi , 0xfff8, 0x44d8, { 16, 16, 8}}, - {m68k_op_move_16_toc_pd , 0xfff8, 0x44e0, { 18, 18, 9}}, - {m68k_op_move_16_toc_di , 0xfff8, 0x44e8, { 20, 20, 9}}, - {m68k_op_move_16_toc_ix , 0xfff8, 0x44f0, { 22, 22, 11}}, - {m68k_op_not_8_d , 0xfff8, 0x4600, { 4, 4, 2}}, - {m68k_op_not_8_ai , 0xfff8, 0x4610, { 12, 12, 8}}, - {m68k_op_not_8_pi , 0xfff8, 0x4618, { 12, 12, 8}}, - {m68k_op_not_8_pd , 0xfff8, 0x4620, { 14, 14, 9}}, - {m68k_op_not_8_di , 0xfff8, 0x4628, { 16, 16, 9}}, - {m68k_op_not_8_ix , 0xfff8, 0x4630, { 18, 18, 11}}, - {m68k_op_not_16_d , 0xfff8, 0x4640, { 4, 4, 2}}, - {m68k_op_not_16_ai , 0xfff8, 0x4650, { 12, 12, 8}}, - {m68k_op_not_16_pi , 0xfff8, 0x4658, { 12, 12, 8}}, - {m68k_op_not_16_pd , 0xfff8, 0x4660, { 14, 14, 9}}, - {m68k_op_not_16_di , 0xfff8, 0x4668, { 16, 16, 9}}, - {m68k_op_not_16_ix , 0xfff8, 0x4670, { 18, 18, 11}}, - {m68k_op_not_32_d , 0xfff8, 0x4680, { 6, 6, 2}}, - {m68k_op_not_32_ai , 0xfff8, 0x4690, { 20, 20, 8}}, - {m68k_op_not_32_pi , 0xfff8, 0x4698, { 20, 20, 8}}, - {m68k_op_not_32_pd , 0xfff8, 0x46a0, { 22, 22, 9}}, - {m68k_op_not_32_di , 0xfff8, 0x46a8, { 24, 24, 9}}, - {m68k_op_not_32_ix , 0xfff8, 0x46b0, { 26, 26, 11}}, - {m68k_op_move_16_tos_d , 0xfff8, 0x46c0, { 12, 12, 8}}, - {m68k_op_move_16_tos_ai , 0xfff8, 0x46d0, { 16, 16, 12}}, - {m68k_op_move_16_tos_pi , 0xfff8, 0x46d8, { 16, 16, 12}}, - {m68k_op_move_16_tos_pd , 0xfff8, 0x46e0, { 18, 18, 13}}, - {m68k_op_move_16_tos_di , 0xfff8, 0x46e8, { 20, 20, 13}}, - {m68k_op_move_16_tos_ix , 0xfff8, 0x46f0, { 22, 22, 15}}, - {m68k_op_nbcd_8_d , 0xfff8, 0x4800, { 6, 6, 6}}, - {m68k_op_link_32 , 0xfff8, 0x4808, { 0, 0, 6}}, - {m68k_op_nbcd_8_ai , 0xfff8, 0x4810, { 12, 12, 10}}, - {m68k_op_nbcd_8_pi , 0xfff8, 0x4818, { 12, 12, 10}}, - {m68k_op_nbcd_8_pd , 0xfff8, 0x4820, { 14, 14, 11}}, - {m68k_op_nbcd_8_di , 0xfff8, 0x4828, { 16, 16, 11}}, - {m68k_op_nbcd_8_ix , 0xfff8, 0x4830, { 18, 18, 13}}, - {m68k_op_swap_32 , 0xfff8, 0x4840, { 4, 4, 4}}, - {m68k_op_bkpt , 0xfff8, 0x4848, { 0, 10, 10}}, - {m68k_op_pea_32_ai , 0xfff8, 0x4850, { 10, 10, 9}}, - {m68k_op_pea_32_di , 0xfff8, 0x4868, { 16, 16, 10}}, - {m68k_op_pea_32_ix , 0xfff8, 0x4870, { 20, 20, 12}}, - {m68k_op_ext_16 , 0xfff8, 0x4880, { 4, 4, 4}}, - {m68k_op_movem_16_re_ai , 0xfff8, 0x4890, { 12, 12, 8}}, - {m68k_op_movem_16_re_pd , 0xfff8, 0x48a0, { 8, 8, 4}}, - {m68k_op_movem_16_re_di , 0xfff8, 0x48a8, { 16, 16, 9}}, - {m68k_op_movem_16_re_ix , 0xfff8, 0x48b0, { 18, 18, 11}}, - {m68k_op_ext_32 , 0xfff8, 0x48c0, { 4, 4, 4}}, - {m68k_op_movem_32_re_ai , 0xfff8, 0x48d0, { 16, 16, 8}}, - {m68k_op_movem_32_re_pd , 0xfff8, 0x48e0, { 8, 8, 4}}, - {m68k_op_movem_32_re_di , 0xfff8, 0x48e8, { 20, 20, 9}}, - {m68k_op_movem_32_re_ix , 0xfff8, 0x48f0, { 22, 22, 11}}, - {m68k_op_extb_32 , 0xfff8, 0x49c0, { 0, 0, 4}}, - {m68k_op_tst_8_d , 0xfff8, 0x4a00, { 4, 4, 2}}, - {m68k_op_tst_8_ai , 0xfff8, 0x4a10, { 8, 8, 6}}, - {m68k_op_tst_8_pi , 0xfff8, 0x4a18, { 8, 8, 6}}, - {m68k_op_tst_8_pd , 0xfff8, 0x4a20, { 10, 10, 7}}, - {m68k_op_tst_8_di , 0xfff8, 0x4a28, { 12, 12, 7}}, - {m68k_op_tst_8_ix , 0xfff8, 0x4a30, { 14, 14, 9}}, - {m68k_op_tst_16_d , 0xfff8, 0x4a40, { 4, 4, 2}}, - {m68k_op_tst_16_a , 0xfff8, 0x4a48, { 0, 0, 2}}, - {m68k_op_tst_16_ai , 0xfff8, 0x4a50, { 8, 8, 6}}, - {m68k_op_tst_16_pi , 0xfff8, 0x4a58, { 8, 8, 6}}, - {m68k_op_tst_16_pd , 0xfff8, 0x4a60, { 10, 10, 7}}, - {m68k_op_tst_16_di , 0xfff8, 0x4a68, { 12, 12, 7}}, - {m68k_op_tst_16_ix , 0xfff8, 0x4a70, { 14, 14, 9}}, - {m68k_op_tst_32_d , 0xfff8, 0x4a80, { 4, 4, 2}}, - {m68k_op_tst_32_a , 0xfff8, 0x4a88, { 0, 0, 2}}, - {m68k_op_tst_32_ai , 0xfff8, 0x4a90, { 12, 12, 6}}, - {m68k_op_tst_32_pi , 0xfff8, 0x4a98, { 12, 12, 6}}, - {m68k_op_tst_32_pd , 0xfff8, 0x4aa0, { 14, 14, 7}}, - {m68k_op_tst_32_di , 0xfff8, 0x4aa8, { 16, 16, 7}}, - {m68k_op_tst_32_ix , 0xfff8, 0x4ab0, { 18, 18, 9}}, - {m68k_op_tas_8_d , 0xfff8, 0x4ac0, { 4, 4, 4}}, - {m68k_op_tas_8_ai , 0xfff8, 0x4ad0, { 18, 18, 16}}, - {m68k_op_tas_8_pi , 0xfff8, 0x4ad8, { 18, 18, 16}}, - {m68k_op_tas_8_pd , 0xfff8, 0x4ae0, { 20, 20, 17}}, - {m68k_op_tas_8_di , 0xfff8, 0x4ae8, { 22, 22, 17}}, - {m68k_op_tas_8_ix , 0xfff8, 0x4af0, { 24, 24, 19}}, - {m68k_op_mull_32_d , 0xfff8, 0x4c00, { 0, 0, 43}}, - {m68k_op_mull_32_ai , 0xfff8, 0x4c10, { 0, 0, 47}}, - {m68k_op_mull_32_pi , 0xfff8, 0x4c18, { 0, 0, 47}}, - {m68k_op_mull_32_pd , 0xfff8, 0x4c20, { 0, 0, 48}}, - {m68k_op_mull_32_di , 0xfff8, 0x4c28, { 0, 0, 48}}, - {m68k_op_mull_32_ix , 0xfff8, 0x4c30, { 0, 0, 50}}, - {m68k_op_divl_32_d , 0xfff8, 0x4c40, { 0, 0, 84}}, - {m68k_op_divl_32_ai , 0xfff8, 0x4c50, { 0, 0, 88}}, - {m68k_op_divl_32_pi , 0xfff8, 0x4c58, { 0, 0, 88}}, - {m68k_op_divl_32_pd , 0xfff8, 0x4c60, { 0, 0, 89}}, - {m68k_op_divl_32_di , 0xfff8, 0x4c68, { 0, 0, 89}}, - {m68k_op_divl_32_ix , 0xfff8, 0x4c70, { 0, 0, 91}}, - {m68k_op_movem_16_er_ai , 0xfff8, 0x4c90, { 16, 16, 12}}, - {m68k_op_movem_16_er_pi , 0xfff8, 0x4c98, { 12, 12, 8}}, - {m68k_op_movem_16_er_di , 0xfff8, 0x4ca8, { 20, 20, 13}}, - {m68k_op_movem_16_er_ix , 0xfff8, 0x4cb0, { 22, 22, 15}}, - {m68k_op_movem_32_er_ai , 0xfff8, 0x4cd0, { 20, 20, 12}}, - {m68k_op_movem_32_er_pi , 0xfff8, 0x4cd8, { 12, 12, 8}}, - {m68k_op_movem_32_er_di , 0xfff8, 0x4ce8, { 24, 24, 13}}, - {m68k_op_movem_32_er_ix , 0xfff8, 0x4cf0, { 26, 26, 15}}, - {m68k_op_link_16 , 0xfff8, 0x4e50, { 16, 16, 5}}, - {m68k_op_unlk_32 , 0xfff8, 0x4e58, { 12, 12, 6}}, - {m68k_op_move_32_tou , 0xfff8, 0x4e60, { 4, 6, 2}}, - {m68k_op_move_32_fru , 0xfff8, 0x4e68, { 4, 6, 2}}, - {m68k_op_jsr_32_ai , 0xfff8, 0x4e90, { 16, 16, 4}}, - {m68k_op_jsr_32_di , 0xfff8, 0x4ea8, { 18, 18, 5}}, - {m68k_op_jsr_32_ix , 0xfff8, 0x4eb0, { 22, 22, 7}}, - {m68k_op_jmp_32_ai , 0xfff8, 0x4ed0, { 8, 8, 4}}, - {m68k_op_jmp_32_di , 0xfff8, 0x4ee8, { 10, 10, 5}}, - {m68k_op_jmp_32_ix , 0xfff8, 0x4ef0, { 12, 12, 7}}, - {m68k_op_st_8_d , 0xfff8, 0x50c0, { 6, 4, 4}}, - {m68k_op_dbt_16 , 0xfff8, 0x50c8, { 12, 12, 6}}, - {m68k_op_st_8_ai , 0xfff8, 0x50d0, { 12, 12, 10}}, - {m68k_op_st_8_pi , 0xfff8, 0x50d8, { 12, 12, 10}}, - {m68k_op_st_8_pd , 0xfff8, 0x50e0, { 14, 14, 11}}, - {m68k_op_st_8_di , 0xfff8, 0x50e8, { 16, 16, 11}}, - {m68k_op_st_8_ix , 0xfff8, 0x50f0, { 18, 18, 13}}, - {m68k_op_sf_8_d , 0xfff8, 0x51c0, { 4, 4, 4}}, - {m68k_op_dbf_16 , 0xfff8, 0x51c8, { 14, 14, 6}}, - {m68k_op_sf_8_ai , 0xfff8, 0x51d0, { 12, 12, 10}}, - {m68k_op_sf_8_pi , 0xfff8, 0x51d8, { 12, 12, 10}}, - {m68k_op_sf_8_pd , 0xfff8, 0x51e0, { 14, 14, 11}}, - {m68k_op_sf_8_di , 0xfff8, 0x51e8, { 16, 16, 11}}, - {m68k_op_sf_8_ix , 0xfff8, 0x51f0, { 18, 18, 13}}, - {m68k_op_shi_8_d , 0xfff8, 0x52c0, { 4, 4, 4}}, - {m68k_op_dbhi_16 , 0xfff8, 0x52c8, { 12, 12, 6}}, - {m68k_op_shi_8_ai , 0xfff8, 0x52d0, { 12, 12, 10}}, - {m68k_op_shi_8_pi , 0xfff8, 0x52d8, { 12, 12, 10}}, - {m68k_op_shi_8_pd , 0xfff8, 0x52e0, { 14, 14, 11}}, - {m68k_op_shi_8_di , 0xfff8, 0x52e8, { 16, 16, 11}}, - {m68k_op_shi_8_ix , 0xfff8, 0x52f0, { 18, 18, 13}}, - {m68k_op_sls_8_d , 0xfff8, 0x53c0, { 4, 4, 4}}, - {m68k_op_dbls_16 , 0xfff8, 0x53c8, { 12, 12, 6}}, - {m68k_op_sls_8_ai , 0xfff8, 0x53d0, { 12, 12, 10}}, - {m68k_op_sls_8_pi , 0xfff8, 0x53d8, { 12, 12, 10}}, - {m68k_op_sls_8_pd , 0xfff8, 0x53e0, { 14, 14, 11}}, - {m68k_op_sls_8_di , 0xfff8, 0x53e8, { 16, 16, 11}}, - {m68k_op_sls_8_ix , 0xfff8, 0x53f0, { 18, 18, 13}}, - {m68k_op_scc_8_d , 0xfff8, 0x54c0, { 4, 4, 4}}, - {m68k_op_dbcc_16 , 0xfff8, 0x54c8, { 12, 12, 6}}, - {m68k_op_scc_8_ai , 0xfff8, 0x54d0, { 12, 12, 10}}, - {m68k_op_scc_8_pi , 0xfff8, 0x54d8, { 12, 12, 10}}, - {m68k_op_scc_8_pd , 0xfff8, 0x54e0, { 14, 14, 11}}, - {m68k_op_scc_8_di , 0xfff8, 0x54e8, { 16, 16, 11}}, - {m68k_op_scc_8_ix , 0xfff8, 0x54f0, { 18, 18, 13}}, - {m68k_op_scs_8_d , 0xfff8, 0x55c0, { 4, 4, 4}}, - {m68k_op_dbcs_16 , 0xfff8, 0x55c8, { 12, 12, 6}}, - {m68k_op_scs_8_ai , 0xfff8, 0x55d0, { 12, 12, 10}}, - {m68k_op_scs_8_pi , 0xfff8, 0x55d8, { 12, 12, 10}}, - {m68k_op_scs_8_pd , 0xfff8, 0x55e0, { 14, 14, 11}}, - {m68k_op_scs_8_di , 0xfff8, 0x55e8, { 16, 16, 11}}, - {m68k_op_scs_8_ix , 0xfff8, 0x55f0, { 18, 18, 13}}, - {m68k_op_sne_8_d , 0xfff8, 0x56c0, { 4, 4, 4}}, - {m68k_op_dbne_16 , 0xfff8, 0x56c8, { 12, 12, 6}}, - {m68k_op_sne_8_ai , 0xfff8, 0x56d0, { 12, 12, 10}}, - {m68k_op_sne_8_pi , 0xfff8, 0x56d8, { 12, 12, 10}}, - {m68k_op_sne_8_pd , 0xfff8, 0x56e0, { 14, 14, 11}}, - {m68k_op_sne_8_di , 0xfff8, 0x56e8, { 16, 16, 11}}, - {m68k_op_sne_8_ix , 0xfff8, 0x56f0, { 18, 18, 13}}, - {m68k_op_seq_8_d , 0xfff8, 0x57c0, { 4, 4, 4}}, - {m68k_op_dbeq_16 , 0xfff8, 0x57c8, { 12, 12, 6}}, - {m68k_op_seq_8_ai , 0xfff8, 0x57d0, { 12, 12, 10}}, - {m68k_op_seq_8_pi , 0xfff8, 0x57d8, { 12, 12, 10}}, - {m68k_op_seq_8_pd , 0xfff8, 0x57e0, { 14, 14, 11}}, - {m68k_op_seq_8_di , 0xfff8, 0x57e8, { 16, 16, 11}}, - {m68k_op_seq_8_ix , 0xfff8, 0x57f0, { 18, 18, 13}}, - {m68k_op_svc_8_d , 0xfff8, 0x58c0, { 4, 4, 4}}, - {m68k_op_dbvc_16 , 0xfff8, 0x58c8, { 12, 12, 6}}, - {m68k_op_svc_8_ai , 0xfff8, 0x58d0, { 12, 12, 10}}, - {m68k_op_svc_8_pi , 0xfff8, 0x58d8, { 12, 12, 10}}, - {m68k_op_svc_8_pd , 0xfff8, 0x58e0, { 14, 14, 11}}, - {m68k_op_svc_8_di , 0xfff8, 0x58e8, { 16, 16, 11}}, - {m68k_op_svc_8_ix , 0xfff8, 0x58f0, { 18, 18, 13}}, - {m68k_op_svs_8_d , 0xfff8, 0x59c0, { 4, 4, 4}}, - {m68k_op_dbvs_16 , 0xfff8, 0x59c8, { 12, 12, 6}}, - {m68k_op_svs_8_ai , 0xfff8, 0x59d0, { 12, 12, 10}}, - {m68k_op_svs_8_pi , 0xfff8, 0x59d8, { 12, 12, 10}}, - {m68k_op_svs_8_pd , 0xfff8, 0x59e0, { 14, 14, 11}}, - {m68k_op_svs_8_di , 0xfff8, 0x59e8, { 16, 16, 11}}, - {m68k_op_svs_8_ix , 0xfff8, 0x59f0, { 18, 18, 13}}, - {m68k_op_spl_8_d , 0xfff8, 0x5ac0, { 4, 4, 4}}, - {m68k_op_dbpl_16 , 0xfff8, 0x5ac8, { 12, 12, 6}}, - {m68k_op_spl_8_ai , 0xfff8, 0x5ad0, { 12, 12, 10}}, - {m68k_op_spl_8_pi , 0xfff8, 0x5ad8, { 12, 12, 10}}, - {m68k_op_spl_8_pd , 0xfff8, 0x5ae0, { 14, 14, 11}}, - {m68k_op_spl_8_di , 0xfff8, 0x5ae8, { 16, 16, 11}}, - {m68k_op_spl_8_ix , 0xfff8, 0x5af0, { 18, 18, 13}}, - {m68k_op_smi_8_d , 0xfff8, 0x5bc0, { 4, 4, 4}}, - {m68k_op_dbmi_16 , 0xfff8, 0x5bc8, { 12, 12, 6}}, - {m68k_op_smi_8_ai , 0xfff8, 0x5bd0, { 12, 12, 10}}, - {m68k_op_smi_8_pi , 0xfff8, 0x5bd8, { 12, 12, 10}}, - {m68k_op_smi_8_pd , 0xfff8, 0x5be0, { 14, 14, 11}}, - {m68k_op_smi_8_di , 0xfff8, 0x5be8, { 16, 16, 11}}, - {m68k_op_smi_8_ix , 0xfff8, 0x5bf0, { 18, 18, 13}}, - {m68k_op_sge_8_d , 0xfff8, 0x5cc0, { 4, 4, 4}}, - {m68k_op_dbge_16 , 0xfff8, 0x5cc8, { 12, 12, 6}}, - {m68k_op_sge_8_ai , 0xfff8, 0x5cd0, { 12, 12, 10}}, - {m68k_op_sge_8_pi , 0xfff8, 0x5cd8, { 12, 12, 10}}, - {m68k_op_sge_8_pd , 0xfff8, 0x5ce0, { 14, 14, 11}}, - {m68k_op_sge_8_di , 0xfff8, 0x5ce8, { 16, 16, 11}}, - {m68k_op_sge_8_ix , 0xfff8, 0x5cf0, { 18, 18, 13}}, - {m68k_op_slt_8_d , 0xfff8, 0x5dc0, { 4, 4, 4}}, - {m68k_op_dblt_16 , 0xfff8, 0x5dc8, { 12, 12, 6}}, - {m68k_op_slt_8_ai , 0xfff8, 0x5dd0, { 12, 12, 10}}, - {m68k_op_slt_8_pi , 0xfff8, 0x5dd8, { 12, 12, 10}}, - {m68k_op_slt_8_pd , 0xfff8, 0x5de0, { 14, 14, 11}}, - {m68k_op_slt_8_di , 0xfff8, 0x5de8, { 16, 16, 11}}, - {m68k_op_slt_8_ix , 0xfff8, 0x5df0, { 18, 18, 13}}, - {m68k_op_sgt_8_d , 0xfff8, 0x5ec0, { 4, 4, 4}}, - {m68k_op_dbgt_16 , 0xfff8, 0x5ec8, { 12, 12, 6}}, - {m68k_op_sgt_8_ai , 0xfff8, 0x5ed0, { 12, 12, 10}}, - {m68k_op_sgt_8_pi , 0xfff8, 0x5ed8, { 12, 12, 10}}, - {m68k_op_sgt_8_pd , 0xfff8, 0x5ee0, { 14, 14, 11}}, - {m68k_op_sgt_8_di , 0xfff8, 0x5ee8, { 16, 16, 11}}, - {m68k_op_sgt_8_ix , 0xfff8, 0x5ef0, { 18, 18, 13}}, - {m68k_op_sle_8_d , 0xfff8, 0x5fc0, { 4, 4, 4}}, - {m68k_op_dble_16 , 0xfff8, 0x5fc8, { 12, 12, 6}}, - {m68k_op_sle_8_ai , 0xfff8, 0x5fd0, { 12, 12, 10}}, - {m68k_op_sle_8_pi , 0xfff8, 0x5fd8, { 12, 12, 10}}, - {m68k_op_sle_8_pd , 0xfff8, 0x5fe0, { 14, 14, 11}}, - {m68k_op_sle_8_di , 0xfff8, 0x5fe8, { 16, 16, 11}}, - {m68k_op_sle_8_ix , 0xfff8, 0x5ff0, { 18, 18, 13}}, - {m68k_op_sbcd_8_mm_ax7 , 0xfff8, 0x8f08, { 18, 18, 16}}, - {m68k_op_pack_16_mm_ax7 , 0xfff8, 0x8f48, { 0, 0, 13}}, - {m68k_op_unpk_16_mm_ax7 , 0xfff8, 0x8f88, { 0, 0, 13}}, - {m68k_op_subx_8_mm_ax7 , 0xfff8, 0x9f08, { 18, 18, 12}}, - {m68k_op_cmpm_8_ax7 , 0xfff8, 0xbf08, { 12, 12, 9}}, - {m68k_op_abcd_8_mm_ax7 , 0xfff8, 0xcf08, { 18, 18, 16}}, - {m68k_op_addx_8_mm_ax7 , 0xfff8, 0xdf08, { 18, 18, 12}}, - {m68k_op_asr_16_ai , 0xfff8, 0xe0d0, { 12, 12, 9}}, - {m68k_op_asr_16_pi , 0xfff8, 0xe0d8, { 12, 12, 9}}, - {m68k_op_asr_16_pd , 0xfff8, 0xe0e0, { 14, 14, 10}}, - {m68k_op_asr_16_di , 0xfff8, 0xe0e8, { 16, 16, 10}}, - {m68k_op_asr_16_ix , 0xfff8, 0xe0f0, { 18, 18, 12}}, - {m68k_op_asl_16_ai , 0xfff8, 0xe1d0, { 12, 12, 10}}, - {m68k_op_asl_16_pi , 0xfff8, 0xe1d8, { 12, 12, 10}}, - {m68k_op_asl_16_pd , 0xfff8, 0xe1e0, { 14, 14, 11}}, - {m68k_op_asl_16_di , 0xfff8, 0xe1e8, { 16, 16, 11}}, - {m68k_op_asl_16_ix , 0xfff8, 0xe1f0, { 18, 18, 13}}, - {m68k_op_lsr_16_ai , 0xfff8, 0xe2d0, { 12, 12, 9}}, - {m68k_op_lsr_16_pi , 0xfff8, 0xe2d8, { 12, 12, 9}}, - {m68k_op_lsr_16_pd , 0xfff8, 0xe2e0, { 14, 14, 10}}, - {m68k_op_lsr_16_di , 0xfff8, 0xe2e8, { 16, 16, 10}}, - {m68k_op_lsr_16_ix , 0xfff8, 0xe2f0, { 18, 18, 12}}, - {m68k_op_lsl_16_ai , 0xfff8, 0xe3d0, { 12, 12, 9}}, - {m68k_op_lsl_16_pi , 0xfff8, 0xe3d8, { 12, 12, 9}}, - {m68k_op_lsl_16_pd , 0xfff8, 0xe3e0, { 14, 14, 10}}, - {m68k_op_lsl_16_di , 0xfff8, 0xe3e8, { 16, 16, 10}}, - {m68k_op_lsl_16_ix , 0xfff8, 0xe3f0, { 18, 18, 12}}, - {m68k_op_roxr_16_ai , 0xfff8, 0xe4d0, { 12, 12, 9}}, - {m68k_op_roxr_16_pi , 0xfff8, 0xe4d8, { 12, 12, 9}}, - {m68k_op_roxr_16_pd , 0xfff8, 0xe4e0, { 14, 14, 10}}, - {m68k_op_roxr_16_di , 0xfff8, 0xe4e8, { 16, 16, 10}}, - {m68k_op_roxr_16_ix , 0xfff8, 0xe4f0, { 18, 18, 12}}, - {m68k_op_roxl_16_ai , 0xfff8, 0xe5d0, { 12, 12, 9}}, - {m68k_op_roxl_16_pi , 0xfff8, 0xe5d8, { 12, 12, 9}}, - {m68k_op_roxl_16_pd , 0xfff8, 0xe5e0, { 14, 14, 10}}, - {m68k_op_roxl_16_di , 0xfff8, 0xe5e8, { 16, 16, 10}}, - {m68k_op_roxl_16_ix , 0xfff8, 0xe5f0, { 18, 18, 12}}, - {m68k_op_ror_16_ai , 0xfff8, 0xe6d0, { 12, 12, 11}}, - {m68k_op_ror_16_pi , 0xfff8, 0xe6d8, { 12, 12, 11}}, - {m68k_op_ror_16_pd , 0xfff8, 0xe6e0, { 14, 14, 12}}, - {m68k_op_ror_16_di , 0xfff8, 0xe6e8, { 16, 16, 12}}, - {m68k_op_ror_16_ix , 0xfff8, 0xe6f0, { 18, 18, 14}}, - {m68k_op_rol_16_ai , 0xfff8, 0xe7d0, { 12, 12, 11}}, - {m68k_op_rol_16_pi , 0xfff8, 0xe7d8, { 12, 12, 11}}, - {m68k_op_rol_16_pd , 0xfff8, 0xe7e0, { 14, 14, 12}}, - {m68k_op_rol_16_di , 0xfff8, 0xe7e8, { 16, 16, 12}}, - {m68k_op_rol_16_ix , 0xfff8, 0xe7f0, { 18, 18, 14}}, - {m68k_op_bftst_32_d , 0xfff8, 0xe8c0, { 0, 0, 6}}, - {m68k_op_bftst_32_ai , 0xfff8, 0xe8d0, { 0, 0, 17}}, - {m68k_op_bftst_32_di , 0xfff8, 0xe8e8, { 0, 0, 18}}, - {m68k_op_bftst_32_ix , 0xfff8, 0xe8f0, { 0, 0, 20}}, - {m68k_op_bfextu_32_d , 0xfff8, 0xe9c0, { 0, 0, 8}}, - {m68k_op_bfextu_32_ai , 0xfff8, 0xe9d0, { 0, 0, 19}}, - {m68k_op_bfextu_32_di , 0xfff8, 0xe9e8, { 0, 0, 20}}, - {m68k_op_bfextu_32_ix , 0xfff8, 0xe9f0, { 0, 0, 22}}, - {m68k_op_bfchg_32_d , 0xfff8, 0xeac0, { 0, 0, 12}}, - {m68k_op_bfchg_32_ai , 0xfff8, 0xead0, { 0, 0, 24}}, - {m68k_op_bfchg_32_di , 0xfff8, 0xeae8, { 0, 0, 25}}, - {m68k_op_bfchg_32_ix , 0xfff8, 0xeaf0, { 0, 0, 27}}, - {m68k_op_bfexts_32_d , 0xfff8, 0xebc0, { 0, 0, 8}}, - {m68k_op_bfexts_32_ai , 0xfff8, 0xebd0, { 0, 0, 19}}, - {m68k_op_bfexts_32_di , 0xfff8, 0xebe8, { 0, 0, 20}}, - {m68k_op_bfexts_32_ix , 0xfff8, 0xebf0, { 0, 0, 22}}, - {m68k_op_bfclr_32_d , 0xfff8, 0xecc0, { 0, 0, 12}}, - {m68k_op_bfclr_32_ai , 0xfff8, 0xecd0, { 0, 0, 24}}, - {m68k_op_bfclr_32_di , 0xfff8, 0xece8, { 0, 0, 25}}, - {m68k_op_bfclr_32_ix , 0xfff8, 0xecf0, { 0, 0, 27}}, - {m68k_op_bfffo_32_d , 0xfff8, 0xedc0, { 0, 0, 18}}, - {m68k_op_bfffo_32_ai , 0xfff8, 0xedd0, { 0, 0, 32}}, - {m68k_op_bfffo_32_di , 0xfff8, 0xede8, { 0, 0, 33}}, - {m68k_op_bfffo_32_ix , 0xfff8, 0xedf0, { 0, 0, 35}}, - {m68k_op_bfset_32_d , 0xfff8, 0xeec0, { 0, 0, 12}}, - {m68k_op_bfset_32_ai , 0xfff8, 0xeed0, { 0, 0, 24}}, - {m68k_op_bfset_32_di , 0xfff8, 0xeee8, { 0, 0, 25}}, - {m68k_op_bfset_32_ix , 0xfff8, 0xeef0, { 0, 0, 27}}, - {m68k_op_bfins_32_d , 0xfff8, 0xefc0, { 0, 0, 10}}, - {m68k_op_bfins_32_ai , 0xfff8, 0xefd0, { 0, 0, 21}}, - {m68k_op_bfins_32_di , 0xfff8, 0xefe8, { 0, 0, 22}}, - {m68k_op_bfins_32_ix , 0xfff8, 0xeff0, { 0, 0, 24}}, - {m68k_op_ori_8_pi7 , 0xffff, 0x001f, { 16, 16, 8}}, - {m68k_op_ori_8_pd7 , 0xffff, 0x0027, { 18, 18, 9}}, - {m68k_op_ori_8_aw , 0xffff, 0x0038, { 20, 20, 8}}, - {m68k_op_ori_8_al , 0xffff, 0x0039, { 24, 24, 8}}, - {m68k_op_ori_16_toc , 0xffff, 0x003c, { 20, 16, 12}}, - {m68k_op_ori_16_aw , 0xffff, 0x0078, { 20, 20, 8}}, - {m68k_op_ori_16_al , 0xffff, 0x0079, { 24, 24, 8}}, - {m68k_op_ori_16_tos , 0xffff, 0x007c, { 20, 16, 12}}, - {m68k_op_ori_32_aw , 0xffff, 0x00b8, { 32, 32, 8}}, - {m68k_op_ori_32_al , 0xffff, 0x00b9, { 36, 36, 8}}, - {m68k_op_chk2cmp2_8_aw , 0xffff, 0x00f8, { 0, 0, 22}}, - {m68k_op_chk2cmp2_8_al , 0xffff, 0x00f9, { 0, 0, 22}}, - {m68k_op_chk2cmp2_8_pcdi , 0xffff, 0x00fa, { 0, 0, 23}}, - {m68k_op_chk2cmp2_8_pcix , 0xffff, 0x00fb, { 0, 0, 23}}, - {m68k_op_andi_8_pi7 , 0xffff, 0x021f, { 16, 16, 8}}, - {m68k_op_andi_8_pd7 , 0xffff, 0x0227, { 18, 18, 9}}, - {m68k_op_andi_8_aw , 0xffff, 0x0238, { 20, 20, 8}}, - {m68k_op_andi_8_al , 0xffff, 0x0239, { 24, 24, 8}}, - {m68k_op_andi_16_toc , 0xffff, 0x023c, { 20, 16, 12}}, - {m68k_op_andi_16_aw , 0xffff, 0x0278, { 20, 20, 8}}, - {m68k_op_andi_16_al , 0xffff, 0x0279, { 24, 24, 8}}, - {m68k_op_andi_16_tos , 0xffff, 0x027c, { 20, 16, 12}}, - {m68k_op_andi_32_aw , 0xffff, 0x02b8, { 32, 32, 8}}, - {m68k_op_andi_32_al , 0xffff, 0x02b9, { 36, 36, 8}}, - {m68k_op_chk2cmp2_16_aw , 0xffff, 0x02f8, { 0, 0, 22}}, - {m68k_op_chk2cmp2_16_al , 0xffff, 0x02f9, { 0, 0, 22}}, - {m68k_op_chk2cmp2_16_pcdi , 0xffff, 0x02fa, { 0, 0, 23}}, - {m68k_op_chk2cmp2_16_pcix , 0xffff, 0x02fb, { 0, 0, 23}}, - {m68k_op_subi_8_pi7 , 0xffff, 0x041f, { 16, 16, 8}}, - {m68k_op_subi_8_pd7 , 0xffff, 0x0427, { 18, 18, 9}}, - {m68k_op_subi_8_aw , 0xffff, 0x0438, { 20, 20, 8}}, - {m68k_op_subi_8_al , 0xffff, 0x0439, { 24, 24, 8}}, - {m68k_op_subi_16_aw , 0xffff, 0x0478, { 20, 20, 8}}, - {m68k_op_subi_16_al , 0xffff, 0x0479, { 24, 24, 8}}, - {m68k_op_subi_32_aw , 0xffff, 0x04b8, { 32, 32, 8}}, - {m68k_op_subi_32_al , 0xffff, 0x04b9, { 36, 36, 8}}, - {m68k_op_chk2cmp2_32_aw , 0xffff, 0x04f8, { 0, 0, 22}}, - {m68k_op_chk2cmp2_32_al , 0xffff, 0x04f9, { 0, 0, 22}}, - {m68k_op_chk2cmp2_32_pcdi , 0xffff, 0x04fa, { 0, 0, 23}}, - {m68k_op_chk2cmp2_32_pcix , 0xffff, 0x04fb, { 0, 0, 23}}, - {m68k_op_addi_8_pi7 , 0xffff, 0x061f, { 16, 16, 8}}, - {m68k_op_addi_8_pd7 , 0xffff, 0x0627, { 18, 18, 9}}, - {m68k_op_addi_8_aw , 0xffff, 0x0638, { 20, 20, 8}}, - {m68k_op_addi_8_al , 0xffff, 0x0639, { 24, 24, 8}}, - {m68k_op_addi_16_aw , 0xffff, 0x0678, { 20, 20, 8}}, - {m68k_op_addi_16_al , 0xffff, 0x0679, { 24, 24, 8}}, - {m68k_op_addi_32_aw , 0xffff, 0x06b8, { 32, 32, 8}}, - {m68k_op_addi_32_al , 0xffff, 0x06b9, { 36, 36, 8}}, - {m68k_op_callm_32_aw , 0xffff, 0x06f8, { 0, 0, 64}}, - {m68k_op_callm_32_al , 0xffff, 0x06f9, { 0, 0, 64}}, - {m68k_op_callm_32_pcdi , 0xffff, 0x06fa, { 0, 0, 65}}, - {m68k_op_callm_32_pcix , 0xffff, 0x06fb, { 0, 0, 67}}, - {m68k_op_btst_8_s_pi7 , 0xffff, 0x081f, { 12, 12, 8}}, - {m68k_op_btst_8_s_pd7 , 0xffff, 0x0827, { 14, 14, 9}}, - {m68k_op_btst_8_s_aw , 0xffff, 0x0838, { 16, 16, 8}}, - {m68k_op_btst_8_s_al , 0xffff, 0x0839, { 20, 20, 8}}, - {m68k_op_btst_8_s_pcdi , 0xffff, 0x083a, { 16, 16, 9}}, - {m68k_op_btst_8_s_pcix , 0xffff, 0x083b, { 18, 18, 11}}, - {m68k_op_bchg_8_s_pi7 , 0xffff, 0x085f, { 16, 16, 8}}, - {m68k_op_bchg_8_s_pd7 , 0xffff, 0x0867, { 18, 18, 9}}, - {m68k_op_bchg_8_s_aw , 0xffff, 0x0878, { 20, 20, 8}}, - {m68k_op_bchg_8_s_al , 0xffff, 0x0879, { 24, 24, 8}}, - {m68k_op_bclr_8_s_pi7 , 0xffff, 0x089f, { 16, 16, 8}}, - {m68k_op_bclr_8_s_pd7 , 0xffff, 0x08a7, { 18, 18, 9}}, - {m68k_op_bclr_8_s_aw , 0xffff, 0x08b8, { 20, 20, 8}}, - {m68k_op_bclr_8_s_al , 0xffff, 0x08b9, { 24, 24, 8}}, - {m68k_op_bset_8_s_pi7 , 0xffff, 0x08df, { 16, 16, 8}}, - {m68k_op_bset_8_s_pd7 , 0xffff, 0x08e7, { 18, 18, 9}}, - {m68k_op_bset_8_s_aw , 0xffff, 0x08f8, { 20, 20, 8}}, - {m68k_op_bset_8_s_al , 0xffff, 0x08f9, { 24, 24, 8}}, - {m68k_op_eori_8_pi7 , 0xffff, 0x0a1f, { 16, 16, 8}}, - {m68k_op_eori_8_pd7 , 0xffff, 0x0a27, { 18, 18, 9}}, - {m68k_op_eori_8_aw , 0xffff, 0x0a38, { 20, 20, 8}}, - {m68k_op_eori_8_al , 0xffff, 0x0a39, { 24, 24, 8}}, - {m68k_op_eori_16_toc , 0xffff, 0x0a3c, { 20, 16, 12}}, - {m68k_op_eori_16_aw , 0xffff, 0x0a78, { 20, 20, 8}}, - {m68k_op_eori_16_al , 0xffff, 0x0a79, { 24, 24, 8}}, - {m68k_op_eori_16_tos , 0xffff, 0x0a7c, { 20, 16, 12}}, - {m68k_op_eori_32_aw , 0xffff, 0x0ab8, { 32, 32, 8}}, - {m68k_op_eori_32_al , 0xffff, 0x0ab9, { 36, 36, 8}}, - {m68k_op_cas_8_pi7 , 0xffff, 0x0adf, { 0, 0, 16}}, - {m68k_op_cas_8_pd7 , 0xffff, 0x0ae7, { 0, 0, 17}}, - {m68k_op_cas_8_aw , 0xffff, 0x0af8, { 0, 0, 16}}, - {m68k_op_cas_8_al , 0xffff, 0x0af9, { 0, 0, 16}}, - {m68k_op_cmpi_8_pi7 , 0xffff, 0x0c1f, { 12, 12, 6}}, - {m68k_op_cmpi_8_pd7 , 0xffff, 0x0c27, { 14, 14, 7}}, - {m68k_op_cmpi_8_aw , 0xffff, 0x0c38, { 16, 16, 6}}, - {m68k_op_cmpi_8_al , 0xffff, 0x0c39, { 20, 20, 6}}, - {m68k_op_cmpi_8_pcdi , 0xffff, 0x0c3a, { 0, 0, 7}}, - {m68k_op_cmpi_8_pcix , 0xffff, 0x0c3b, { 0, 0, 9}}, - {m68k_op_cmpi_16_aw , 0xffff, 0x0c78, { 16, 16, 6}}, - {m68k_op_cmpi_16_al , 0xffff, 0x0c79, { 20, 20, 6}}, - {m68k_op_cmpi_16_pcdi , 0xffff, 0x0c7a, { 0, 0, 7}}, - {m68k_op_cmpi_16_pcix , 0xffff, 0x0c7b, { 0, 0, 9}}, - {m68k_op_cmpi_32_aw , 0xffff, 0x0cb8, { 24, 24, 6}}, - {m68k_op_cmpi_32_al , 0xffff, 0x0cb9, { 28, 28, 6}}, - {m68k_op_cmpi_32_pcdi , 0xffff, 0x0cba, { 0, 0, 7}}, - {m68k_op_cmpi_32_pcix , 0xffff, 0x0cbb, { 0, 0, 9}}, - {m68k_op_cas_16_aw , 0xffff, 0x0cf8, { 0, 0, 16}}, - {m68k_op_cas_16_al , 0xffff, 0x0cf9, { 0, 0, 16}}, - {m68k_op_cas2_16 , 0xffff, 0x0cfc, { 0, 0, 12}}, - {m68k_op_moves_8_pi7 , 0xffff, 0x0e1f, { 0, 18, 9}}, - {m68k_op_moves_8_pd7 , 0xffff, 0x0e27, { 0, 20, 10}}, - {m68k_op_moves_8_aw , 0xffff, 0x0e38, { 0, 26, 9}}, - {m68k_op_moves_8_al , 0xffff, 0x0e39, { 0, 30, 9}}, - {m68k_op_moves_16_aw , 0xffff, 0x0e78, { 0, 26, 9}}, - {m68k_op_moves_16_al , 0xffff, 0x0e79, { 0, 30, 9}}, - {m68k_op_moves_32_aw , 0xffff, 0x0eb8, { 0, 32, 9}}, - {m68k_op_moves_32_al , 0xffff, 0x0eb9, { 0, 36, 9}}, - {m68k_op_cas_32_aw , 0xffff, 0x0ef8, { 0, 0, 16}}, - {m68k_op_cas_32_al , 0xffff, 0x0ef9, { 0, 0, 16}}, - {m68k_op_cas2_32 , 0xffff, 0x0efc, { 0, 0, 12}}, - {m68k_op_move_8_aw_pi7 , 0xffff, 0x11df, { 16, 16, 8}}, - {m68k_op_move_8_aw_pd7 , 0xffff, 0x11e7, { 18, 18, 9}}, - {m68k_op_move_8_aw_aw , 0xffff, 0x11f8, { 20, 20, 8}}, - {m68k_op_move_8_aw_al , 0xffff, 0x11f9, { 24, 24, 8}}, - {m68k_op_move_8_aw_pcdi , 0xffff, 0x11fa, { 20, 20, 9}}, - {m68k_op_move_8_aw_pcix , 0xffff, 0x11fb, { 22, 22, 11}}, - {m68k_op_move_8_aw_i , 0xffff, 0x11fc, { 16, 16, 6}}, - {m68k_op_move_8_al_pi7 , 0xffff, 0x13df, { 20, 20, 10}}, - {m68k_op_move_8_al_pd7 , 0xffff, 0x13e7, { 22, 22, 11}}, - {m68k_op_move_8_al_aw , 0xffff, 0x13f8, { 24, 24, 10}}, - {m68k_op_move_8_al_al , 0xffff, 0x13f9, { 28, 28, 10}}, - {m68k_op_move_8_al_pcdi , 0xffff, 0x13fa, { 24, 24, 11}}, - {m68k_op_move_8_al_pcix , 0xffff, 0x13fb, { 26, 26, 13}}, - {m68k_op_move_8_al_i , 0xffff, 0x13fc, { 20, 20, 8}}, - {m68k_op_move_8_pi7_pi7 , 0xffff, 0x1edf, { 12, 12, 8}}, - {m68k_op_move_8_pi7_pd7 , 0xffff, 0x1ee7, { 14, 14, 9}}, - {m68k_op_move_8_pi7_aw , 0xffff, 0x1ef8, { 16, 16, 8}}, - {m68k_op_move_8_pi7_al , 0xffff, 0x1ef9, { 20, 20, 8}}, - {m68k_op_move_8_pi7_pcdi , 0xffff, 0x1efa, { 16, 16, 9}}, - {m68k_op_move_8_pi7_pcix , 0xffff, 0x1efb, { 18, 18, 11}}, - {m68k_op_move_8_pi7_i , 0xffff, 0x1efc, { 12, 12, 6}}, - {m68k_op_move_8_pd7_pi7 , 0xffff, 0x1f1f, { 12, 12, 9}}, - {m68k_op_move_8_pd7_pd7 , 0xffff, 0x1f27, { 14, 14, 10}}, - {m68k_op_move_8_pd7_aw , 0xffff, 0x1f38, { 16, 16, 9}}, - {m68k_op_move_8_pd7_al , 0xffff, 0x1f39, { 20, 20, 9}}, - {m68k_op_move_8_pd7_pcdi , 0xffff, 0x1f3a, { 16, 16, 10}}, - {m68k_op_move_8_pd7_pcix , 0xffff, 0x1f3b, { 18, 18, 12}}, - {m68k_op_move_8_pd7_i , 0xffff, 0x1f3c, { 12, 12, 7}}, - {m68k_op_move_32_aw_aw , 0xffff, 0x21f8, { 28, 28, 8}}, - {m68k_op_move_32_aw_al , 0xffff, 0x21f9, { 32, 32, 8}}, - {m68k_op_move_32_aw_pcdi , 0xffff, 0x21fa, { 28, 28, 9}}, - {m68k_op_move_32_aw_pcix , 0xffff, 0x21fb, { 30, 30, 11}}, - {m68k_op_move_32_aw_i , 0xffff, 0x21fc, { 24, 24, 8}}, - {m68k_op_move_32_al_aw , 0xffff, 0x23f8, { 32, 32, 10}}, - {m68k_op_move_32_al_al , 0xffff, 0x23f9, { 36, 36, 10}}, - {m68k_op_move_32_al_pcdi , 0xffff, 0x23fa, { 32, 32, 11}}, - {m68k_op_move_32_al_pcix , 0xffff, 0x23fb, { 34, 34, 13}}, - {m68k_op_move_32_al_i , 0xffff, 0x23fc, { 28, 28, 10}}, - {m68k_op_move_16_aw_aw , 0xffff, 0x31f8, { 20, 20, 8}}, - {m68k_op_move_16_aw_al , 0xffff, 0x31f9, { 24, 24, 8}}, - {m68k_op_move_16_aw_pcdi , 0xffff, 0x31fa, { 20, 20, 9}}, - {m68k_op_move_16_aw_pcix , 0xffff, 0x31fb, { 22, 22, 11}}, - {m68k_op_move_16_aw_i , 0xffff, 0x31fc, { 16, 16, 6}}, - {m68k_op_move_16_al_aw , 0xffff, 0x33f8, { 24, 24, 10}}, - {m68k_op_move_16_al_al , 0xffff, 0x33f9, { 28, 28, 10}}, - {m68k_op_move_16_al_pcdi , 0xffff, 0x33fa, { 24, 24, 11}}, - {m68k_op_move_16_al_pcix , 0xffff, 0x33fb, { 26, 26, 13}}, - {m68k_op_move_16_al_i , 0xffff, 0x33fc, { 20, 20, 8}}, - {m68k_op_negx_8_pi7 , 0xffff, 0x401f, { 12, 12, 8}}, - {m68k_op_negx_8_pd7 , 0xffff, 0x4027, { 14, 14, 9}}, - {m68k_op_negx_8_aw , 0xffff, 0x4038, { 16, 16, 8}}, - {m68k_op_negx_8_al , 0xffff, 0x4039, { 20, 20, 8}}, - {m68k_op_negx_16_aw , 0xffff, 0x4078, { 16, 16, 8}}, - {m68k_op_negx_16_al , 0xffff, 0x4079, { 20, 20, 8}}, - {m68k_op_negx_32_aw , 0xffff, 0x40b8, { 24, 24, 8}}, - {m68k_op_negx_32_al , 0xffff, 0x40b9, { 28, 28, 8}}, - {m68k_op_move_16_frs_aw , 0xffff, 0x40f8, { 16, 16, 12}}, - {m68k_op_move_16_frs_al , 0xffff, 0x40f9, { 20, 20, 12}}, - {m68k_op_clr_8_pi7 , 0xffff, 0x421f, { 12, 8, 8}}, - {m68k_op_clr_8_pd7 , 0xffff, 0x4227, { 14, 10, 9}}, - {m68k_op_clr_8_aw , 0xffff, 0x4238, { 16, 12, 8}}, - {m68k_op_clr_8_al , 0xffff, 0x4239, { 20, 14, 8}}, - {m68k_op_clr_16_aw , 0xffff, 0x4278, { 16, 12, 8}}, - {m68k_op_clr_16_al , 0xffff, 0x4279, { 20, 14, 8}}, - {m68k_op_clr_32_aw , 0xffff, 0x42b8, { 24, 16, 8}}, - {m68k_op_clr_32_al , 0xffff, 0x42b9, { 28, 20, 8}}, - {m68k_op_move_16_frc_aw , 0xffff, 0x42f8, { 0, 16, 8}}, - {m68k_op_move_16_frc_al , 0xffff, 0x42f9, { 0, 20, 8}}, - {m68k_op_neg_8_pi7 , 0xffff, 0x441f, { 12, 12, 8}}, - {m68k_op_neg_8_pd7 , 0xffff, 0x4427, { 14, 14, 9}}, - {m68k_op_neg_8_aw , 0xffff, 0x4438, { 16, 16, 8}}, - {m68k_op_neg_8_al , 0xffff, 0x4439, { 20, 20, 8}}, - {m68k_op_neg_16_aw , 0xffff, 0x4478, { 16, 16, 8}}, - {m68k_op_neg_16_al , 0xffff, 0x4479, { 20, 20, 8}}, - {m68k_op_neg_32_aw , 0xffff, 0x44b8, { 24, 24, 8}}, - {m68k_op_neg_32_al , 0xffff, 0x44b9, { 28, 28, 8}}, - {m68k_op_move_16_toc_aw , 0xffff, 0x44f8, { 20, 20, 8}}, - {m68k_op_move_16_toc_al , 0xffff, 0x44f9, { 24, 24, 8}}, - {m68k_op_move_16_toc_pcdi , 0xffff, 0x44fa, { 20, 20, 9}}, - {m68k_op_move_16_toc_pcix , 0xffff, 0x44fb, { 22, 22, 11}}, - {m68k_op_move_16_toc_i , 0xffff, 0x44fc, { 16, 16, 6}}, - {m68k_op_not_8_pi7 , 0xffff, 0x461f, { 12, 12, 8}}, - {m68k_op_not_8_pd7 , 0xffff, 0x4627, { 14, 14, 9}}, - {m68k_op_not_8_aw , 0xffff, 0x4638, { 16, 16, 8}}, - {m68k_op_not_8_al , 0xffff, 0x4639, { 20, 20, 8}}, - {m68k_op_not_16_aw , 0xffff, 0x4678, { 16, 16, 8}}, - {m68k_op_not_16_al , 0xffff, 0x4679, { 20, 20, 8}}, - {m68k_op_not_32_aw , 0xffff, 0x46b8, { 24, 24, 8}}, - {m68k_op_not_32_al , 0xffff, 0x46b9, { 28, 28, 8}}, - {m68k_op_move_16_tos_aw , 0xffff, 0x46f8, { 20, 20, 12}}, - {m68k_op_move_16_tos_al , 0xffff, 0x46f9, { 24, 24, 12}}, - {m68k_op_move_16_tos_pcdi , 0xffff, 0x46fa, { 20, 20, 13}}, - {m68k_op_move_16_tos_pcix , 0xffff, 0x46fb, { 22, 22, 15}}, - {m68k_op_move_16_tos_i , 0xffff, 0x46fc, { 16, 16, 10}}, - {m68k_op_link_32_a7 , 0xffff, 0x480f, { 0, 0, 6}}, - {m68k_op_nbcd_8_pi7 , 0xffff, 0x481f, { 12, 12, 10}}, - {m68k_op_nbcd_8_pd7 , 0xffff, 0x4827, { 14, 14, 11}}, - {m68k_op_nbcd_8_aw , 0xffff, 0x4838, { 16, 16, 10}}, - {m68k_op_nbcd_8_al , 0xffff, 0x4839, { 20, 20, 10}}, - {m68k_op_pea_32_aw , 0xffff, 0x4878, { 16, 16, 9}}, - {m68k_op_pea_32_al , 0xffff, 0x4879, { 20, 20, 9}}, - {m68k_op_pea_32_pcdi , 0xffff, 0x487a, { 16, 16, 10}}, - {m68k_op_pea_32_pcix , 0xffff, 0x487b, { 20, 20, 12}}, - {m68k_op_movem_16_re_aw , 0xffff, 0x48b8, { 16, 16, 8}}, - {m68k_op_movem_16_re_al , 0xffff, 0x48b9, { 20, 20, 8}}, - {m68k_op_movem_32_re_aw , 0xffff, 0x48f8, { 20, 20, 8}}, - {m68k_op_movem_32_re_al , 0xffff, 0x48f9, { 24, 24, 8}}, - {m68k_op_tst_8_pi7 , 0xffff, 0x4a1f, { 8, 8, 6}}, - {m68k_op_tst_8_pd7 , 0xffff, 0x4a27, { 10, 10, 7}}, - {m68k_op_tst_8_aw , 0xffff, 0x4a38, { 12, 12, 6}}, - {m68k_op_tst_8_al , 0xffff, 0x4a39, { 16, 16, 6}}, - {m68k_op_tst_8_pcdi , 0xffff, 0x4a3a, { 0, 0, 7}}, - {m68k_op_tst_8_pcix , 0xffff, 0x4a3b, { 0, 0, 9}}, - {m68k_op_tst_8_i , 0xffff, 0x4a3c, { 0, 0, 6}}, - {m68k_op_tst_16_aw , 0xffff, 0x4a78, { 12, 12, 6}}, - {m68k_op_tst_16_al , 0xffff, 0x4a79, { 16, 16, 6}}, - {m68k_op_tst_16_pcdi , 0xffff, 0x4a7a, { 0, 0, 7}}, - {m68k_op_tst_16_pcix , 0xffff, 0x4a7b, { 0, 0, 9}}, - {m68k_op_tst_16_i , 0xffff, 0x4a7c, { 0, 0, 6}}, - {m68k_op_tst_32_aw , 0xffff, 0x4ab8, { 16, 16, 6}}, - {m68k_op_tst_32_al , 0xffff, 0x4ab9, { 20, 20, 6}}, - {m68k_op_tst_32_pcdi , 0xffff, 0x4aba, { 0, 0, 7}}, - {m68k_op_tst_32_pcix , 0xffff, 0x4abb, { 0, 0, 9}}, - {m68k_op_tst_32_i , 0xffff, 0x4abc, { 0, 0, 6}}, - {m68k_op_tas_8_pi7 , 0xffff, 0x4adf, { 18, 18, 16}}, - {m68k_op_tas_8_pd7 , 0xffff, 0x4ae7, { 20, 20, 17}}, - {m68k_op_tas_8_aw , 0xffff, 0x4af8, { 22, 22, 16}}, - {m68k_op_tas_8_al , 0xffff, 0x4af9, { 26, 26, 16}}, - {m68k_op_illegal , 0xffff, 0x4afc, { 4, 4, 4}}, - {m68k_op_mull_32_aw , 0xffff, 0x4c38, { 0, 0, 47}}, - {m68k_op_mull_32_al , 0xffff, 0x4c39, { 0, 0, 47}}, - {m68k_op_mull_32_pcdi , 0xffff, 0x4c3a, { 0, 0, 48}}, - {m68k_op_mull_32_pcix , 0xffff, 0x4c3b, { 0, 0, 50}}, - {m68k_op_mull_32_i , 0xffff, 0x4c3c, { 0, 0, 47}}, - {m68k_op_divl_32_aw , 0xffff, 0x4c78, { 0, 0, 88}}, - {m68k_op_divl_32_al , 0xffff, 0x4c79, { 0, 0, 88}}, - {m68k_op_divl_32_pcdi , 0xffff, 0x4c7a, { 0, 0, 89}}, - {m68k_op_divl_32_pcix , 0xffff, 0x4c7b, { 0, 0, 91}}, - {m68k_op_divl_32_i , 0xffff, 0x4c7c, { 0, 0, 88}}, - {m68k_op_movem_16_er_aw , 0xffff, 0x4cb8, { 20, 20, 12}}, - {m68k_op_movem_16_er_al , 0xffff, 0x4cb9, { 24, 24, 12}}, - {m68k_op_movem_16_er_pcdi , 0xffff, 0x4cba, { 16, 16, 9}}, - {m68k_op_movem_16_er_pcix , 0xffff, 0x4cbb, { 18, 18, 11}}, - {m68k_op_movem_32_er_aw , 0xffff, 0x4cf8, { 24, 24, 12}}, - {m68k_op_movem_32_er_al , 0xffff, 0x4cf9, { 28, 28, 12}}, - {m68k_op_movem_32_er_pcdi , 0xffff, 0x4cfa, { 20, 20, 9}}, - {m68k_op_movem_32_er_pcix , 0xffff, 0x4cfb, { 22, 22, 11}}, - {m68k_op_link_16_a7 , 0xffff, 0x4e57, { 16, 16, 5}}, - {m68k_op_unlk_32_a7 , 0xffff, 0x4e5f, { 12, 12, 6}}, - {m68k_op_reset , 0xffff, 0x4e70, { 0, 0, 0}}, - {m68k_op_nop , 0xffff, 0x4e71, { 4, 4, 2}}, - {m68k_op_stop , 0xffff, 0x4e72, { 4, 4, 8}}, - {m68k_op_rte_32 , 0xffff, 0x4e73, { 20, 24, 20}}, - {m68k_op_rtd_32 , 0xffff, 0x4e74, { 0, 16, 10}}, - {m68k_op_rts_32 , 0xffff, 0x4e75, { 16, 16, 10}}, - {m68k_op_trapv , 0xffff, 0x4e76, { 4, 4, 4}}, - {m68k_op_rtr_32 , 0xffff, 0x4e77, { 20, 20, 14}}, - {m68k_op_movec_32_cr , 0xffff, 0x4e7a, { 0, 12, 6}}, - {m68k_op_movec_32_rc , 0xffff, 0x4e7b, { 0, 10, 12}}, - {m68k_op_jsr_32_aw , 0xffff, 0x4eb8, { 18, 18, 4}}, - {m68k_op_jsr_32_al , 0xffff, 0x4eb9, { 20, 20, 4}}, - {m68k_op_jsr_32_pcdi , 0xffff, 0x4eba, { 18, 18, 5}}, - {m68k_op_jsr_32_pcix , 0xffff, 0x4ebb, { 22, 22, 7}}, - {m68k_op_jmp_32_aw , 0xffff, 0x4ef8, { 10, 10, 4}}, - {m68k_op_jmp_32_al , 0xffff, 0x4ef9, { 12, 12, 4}}, - {m68k_op_jmp_32_pcdi , 0xffff, 0x4efa, { 10, 10, 5}}, - {m68k_op_jmp_32_pcix , 0xffff, 0x4efb, { 14, 14, 7}}, - {m68k_op_st_8_pi7 , 0xffff, 0x50df, { 12, 12, 10}}, - {m68k_op_st_8_pd7 , 0xffff, 0x50e7, { 14, 14, 11}}, - {m68k_op_st_8_aw , 0xffff, 0x50f8, { 16, 16, 10}}, - {m68k_op_st_8_al , 0xffff, 0x50f9, { 20, 20, 10}}, - {m68k_op_trapt_16 , 0xffff, 0x50fa, { 0, 0, 6}}, - {m68k_op_trapt_32 , 0xffff, 0x50fb, { 0, 0, 8}}, - {m68k_op_trapt , 0xffff, 0x50fc, { 0, 0, 4}}, - {m68k_op_sf_8_pi7 , 0xffff, 0x51df, { 12, 12, 10}}, - {m68k_op_sf_8_pd7 , 0xffff, 0x51e7, { 14, 14, 11}}, - {m68k_op_sf_8_aw , 0xffff, 0x51f8, { 16, 16, 10}}, - {m68k_op_sf_8_al , 0xffff, 0x51f9, { 20, 20, 10}}, - {m68k_op_trapf_16 , 0xffff, 0x51fa, { 0, 0, 6}}, - {m68k_op_trapf_32 , 0xffff, 0x51fb, { 0, 0, 8}}, - {m68k_op_trapf , 0xffff, 0x51fc, { 0, 0, 4}}, - {m68k_op_shi_8_pi7 , 0xffff, 0x52df, { 12, 12, 10}}, - {m68k_op_shi_8_pd7 , 0xffff, 0x52e7, { 14, 14, 11}}, - {m68k_op_shi_8_aw , 0xffff, 0x52f8, { 16, 16, 10}}, - {m68k_op_shi_8_al , 0xffff, 0x52f9, { 20, 20, 10}}, - {m68k_op_traphi_16 , 0xffff, 0x52fa, { 0, 0, 6}}, - {m68k_op_traphi_32 , 0xffff, 0x52fb, { 0, 0, 8}}, - {m68k_op_traphi , 0xffff, 0x52fc, { 0, 0, 4}}, - {m68k_op_sls_8_pi7 , 0xffff, 0x53df, { 12, 12, 10}}, - {m68k_op_sls_8_pd7 , 0xffff, 0x53e7, { 14, 14, 11}}, - {m68k_op_sls_8_aw , 0xffff, 0x53f8, { 16, 16, 10}}, - {m68k_op_sls_8_al , 0xffff, 0x53f9, { 20, 20, 10}}, - {m68k_op_trapls_16 , 0xffff, 0x53fa, { 0, 0, 6}}, - {m68k_op_trapls_32 , 0xffff, 0x53fb, { 0, 0, 8}}, - {m68k_op_trapls , 0xffff, 0x53fc, { 0, 0, 4}}, - {m68k_op_scc_8_pi7 , 0xffff, 0x54df, { 12, 12, 10}}, - {m68k_op_scc_8_pd7 , 0xffff, 0x54e7, { 14, 14, 11}}, - {m68k_op_scc_8_aw , 0xffff, 0x54f8, { 16, 16, 10}}, - {m68k_op_scc_8_al , 0xffff, 0x54f9, { 20, 20, 10}}, - {m68k_op_trapcc_16 , 0xffff, 0x54fa, { 0, 0, 6}}, - {m68k_op_trapcc_32 , 0xffff, 0x54fb, { 0, 0, 8}}, - {m68k_op_trapcc , 0xffff, 0x54fc, { 0, 0, 4}}, - {m68k_op_scs_8_pi7 , 0xffff, 0x55df, { 12, 12, 10}}, - {m68k_op_scs_8_pd7 , 0xffff, 0x55e7, { 14, 14, 11}}, - {m68k_op_scs_8_aw , 0xffff, 0x55f8, { 16, 16, 10}}, - {m68k_op_scs_8_al , 0xffff, 0x55f9, { 20, 20, 10}}, - {m68k_op_trapcs_16 , 0xffff, 0x55fa, { 0, 0, 6}}, - {m68k_op_trapcs_32 , 0xffff, 0x55fb, { 0, 0, 8}}, - {m68k_op_trapcs , 0xffff, 0x55fc, { 0, 0, 4}}, - {m68k_op_sne_8_pi7 , 0xffff, 0x56df, { 12, 12, 10}}, - {m68k_op_sne_8_pd7 , 0xffff, 0x56e7, { 14, 14, 11}}, - {m68k_op_sne_8_aw , 0xffff, 0x56f8, { 16, 16, 10}}, - {m68k_op_sne_8_al , 0xffff, 0x56f9, { 20, 20, 10}}, - {m68k_op_trapne_16 , 0xffff, 0x56fa, { 0, 0, 6}}, - {m68k_op_trapne_32 , 0xffff, 0x56fb, { 0, 0, 8}}, - {m68k_op_trapne , 0xffff, 0x56fc, { 0, 0, 4}}, - {m68k_op_seq_8_pi7 , 0xffff, 0x57df, { 12, 12, 10}}, - {m68k_op_seq_8_pd7 , 0xffff, 0x57e7, { 14, 14, 11}}, - {m68k_op_seq_8_aw , 0xffff, 0x57f8, { 16, 16, 10}}, - {m68k_op_seq_8_al , 0xffff, 0x57f9, { 20, 20, 10}}, - {m68k_op_trapeq_16 , 0xffff, 0x57fa, { 0, 0, 6}}, - {m68k_op_trapeq_32 , 0xffff, 0x57fb, { 0, 0, 8}}, - {m68k_op_trapeq , 0xffff, 0x57fc, { 0, 0, 4}}, - {m68k_op_svc_8_pi7 , 0xffff, 0x58df, { 12, 12, 10}}, - {m68k_op_svc_8_pd7 , 0xffff, 0x58e7, { 14, 14, 11}}, - {m68k_op_svc_8_aw , 0xffff, 0x58f8, { 16, 16, 10}}, - {m68k_op_svc_8_al , 0xffff, 0x58f9, { 20, 20, 10}}, - {m68k_op_trapvc_16 , 0xffff, 0x58fa, { 0, 0, 6}}, - {m68k_op_trapvc_32 , 0xffff, 0x58fb, { 0, 0, 8}}, - {m68k_op_trapvc , 0xffff, 0x58fc, { 0, 0, 4}}, - {m68k_op_svs_8_pi7 , 0xffff, 0x59df, { 12, 12, 10}}, - {m68k_op_svs_8_pd7 , 0xffff, 0x59e7, { 14, 14, 11}}, - {m68k_op_svs_8_aw , 0xffff, 0x59f8, { 16, 16, 10}}, - {m68k_op_svs_8_al , 0xffff, 0x59f9, { 20, 20, 10}}, - {m68k_op_trapvs_16 , 0xffff, 0x59fa, { 0, 0, 6}}, - {m68k_op_trapvs_32 , 0xffff, 0x59fb, { 0, 0, 8}}, - {m68k_op_trapvs , 0xffff, 0x59fc, { 0, 0, 4}}, - {m68k_op_spl_8_pi7 , 0xffff, 0x5adf, { 12, 12, 10}}, - {m68k_op_spl_8_pd7 , 0xffff, 0x5ae7, { 14, 14, 11}}, - {m68k_op_spl_8_aw , 0xffff, 0x5af8, { 16, 16, 10}}, - {m68k_op_spl_8_al , 0xffff, 0x5af9, { 20, 20, 10}}, - {m68k_op_trappl_16 , 0xffff, 0x5afa, { 0, 0, 6}}, - {m68k_op_trappl_32 , 0xffff, 0x5afb, { 0, 0, 8}}, - {m68k_op_trappl , 0xffff, 0x5afc, { 0, 0, 4}}, - {m68k_op_smi_8_pi7 , 0xffff, 0x5bdf, { 12, 12, 10}}, - {m68k_op_smi_8_pd7 , 0xffff, 0x5be7, { 14, 14, 11}}, - {m68k_op_smi_8_aw , 0xffff, 0x5bf8, { 16, 16, 10}}, - {m68k_op_smi_8_al , 0xffff, 0x5bf9, { 20, 20, 10}}, - {m68k_op_trapmi_16 , 0xffff, 0x5bfa, { 0, 0, 6}}, - {m68k_op_trapmi_32 , 0xffff, 0x5bfb, { 0, 0, 8}}, - {m68k_op_trapmi , 0xffff, 0x5bfc, { 0, 0, 4}}, - {m68k_op_sge_8_pi7 , 0xffff, 0x5cdf, { 12, 12, 10}}, - {m68k_op_sge_8_pd7 , 0xffff, 0x5ce7, { 14, 14, 11}}, - {m68k_op_sge_8_aw , 0xffff, 0x5cf8, { 16, 16, 10}}, - {m68k_op_sge_8_al , 0xffff, 0x5cf9, { 20, 20, 10}}, - {m68k_op_trapge_16 , 0xffff, 0x5cfa, { 0, 0, 6}}, - {m68k_op_trapge_32 , 0xffff, 0x5cfb, { 0, 0, 8}}, - {m68k_op_trapge , 0xffff, 0x5cfc, { 0, 0, 4}}, - {m68k_op_slt_8_pi7 , 0xffff, 0x5ddf, { 12, 12, 10}}, - {m68k_op_slt_8_pd7 , 0xffff, 0x5de7, { 14, 14, 11}}, - {m68k_op_slt_8_aw , 0xffff, 0x5df8, { 16, 16, 10}}, - {m68k_op_slt_8_al , 0xffff, 0x5df9, { 20, 20, 10}}, - {m68k_op_traplt_16 , 0xffff, 0x5dfa, { 0, 0, 6}}, - {m68k_op_traplt_32 , 0xffff, 0x5dfb, { 0, 0, 8}}, - {m68k_op_traplt , 0xffff, 0x5dfc, { 0, 0, 4}}, - {m68k_op_sgt_8_pi7 , 0xffff, 0x5edf, { 12, 12, 10}}, - {m68k_op_sgt_8_pd7 , 0xffff, 0x5ee7, { 14, 14, 11}}, - {m68k_op_sgt_8_aw , 0xffff, 0x5ef8, { 16, 16, 10}}, - {m68k_op_sgt_8_al , 0xffff, 0x5ef9, { 20, 20, 10}}, - {m68k_op_trapgt_16 , 0xffff, 0x5efa, { 0, 0, 6}}, - {m68k_op_trapgt_32 , 0xffff, 0x5efb, { 0, 0, 8}}, - {m68k_op_trapgt , 0xffff, 0x5efc, { 0, 0, 4}}, - {m68k_op_sle_8_pi7 , 0xffff, 0x5fdf, { 12, 12, 10}}, - {m68k_op_sle_8_pd7 , 0xffff, 0x5fe7, { 14, 14, 11}}, - {m68k_op_sle_8_aw , 0xffff, 0x5ff8, { 16, 16, 10}}, - {m68k_op_sle_8_al , 0xffff, 0x5ff9, { 20, 20, 10}}, - {m68k_op_traple_16 , 0xffff, 0x5ffa, { 0, 0, 6}}, - {m68k_op_traple_32 , 0xffff, 0x5ffb, { 0, 0, 8}}, - {m68k_op_traple , 0xffff, 0x5ffc, { 0, 0, 4}}, - {m68k_op_bra_16 , 0xffff, 0x6000, { 10, 10, 10}}, - {m68k_op_bra_32 , 0xffff, 0x60ff, { 0, 0, 10}}, - {m68k_op_bsr_16 , 0xffff, 0x6100, { 18, 18, 7}}, - {m68k_op_bsr_32 , 0xffff, 0x61ff, { 0, 0, 7}}, - {m68k_op_bhi_16 , 0xffff, 0x6200, { 10, 10, 6}}, - {m68k_op_bhi_32 , 0xffff, 0x62ff, { 0, 0, 6}}, - {m68k_op_bls_16 , 0xffff, 0x6300, { 10, 10, 6}}, - {m68k_op_bls_32 , 0xffff, 0x63ff, { 0, 0, 6}}, - {m68k_op_bcc_16 , 0xffff, 0x6400, { 10, 10, 6}}, - {m68k_op_bcc_32 , 0xffff, 0x64ff, { 0, 0, 6}}, - {m68k_op_bcs_16 , 0xffff, 0x6500, { 10, 10, 6}}, - {m68k_op_bcs_32 , 0xffff, 0x65ff, { 0, 0, 6}}, - {m68k_op_bne_16 , 0xffff, 0x6600, { 10, 10, 6}}, - {m68k_op_bne_32 , 0xffff, 0x66ff, { 0, 0, 6}}, - {m68k_op_beq_16 , 0xffff, 0x6700, { 10, 10, 6}}, - {m68k_op_beq_32 , 0xffff, 0x67ff, { 0, 0, 6}}, - {m68k_op_bvc_16 , 0xffff, 0x6800, { 10, 10, 6}}, - {m68k_op_bvc_32 , 0xffff, 0x68ff, { 0, 0, 6}}, - {m68k_op_bvs_16 , 0xffff, 0x6900, { 10, 10, 6}}, - {m68k_op_bvs_32 , 0xffff, 0x69ff, { 0, 0, 6}}, - {m68k_op_bpl_16 , 0xffff, 0x6a00, { 10, 10, 6}}, - {m68k_op_bpl_32 , 0xffff, 0x6aff, { 0, 0, 6}}, - {m68k_op_bmi_16 , 0xffff, 0x6b00, { 10, 10, 6}}, - {m68k_op_bmi_32 , 0xffff, 0x6bff, { 0, 0, 6}}, - {m68k_op_bge_16 , 0xffff, 0x6c00, { 10, 10, 6}}, - {m68k_op_bge_32 , 0xffff, 0x6cff, { 0, 0, 6}}, - {m68k_op_blt_16 , 0xffff, 0x6d00, { 10, 10, 6}}, - {m68k_op_blt_32 , 0xffff, 0x6dff, { 0, 0, 6}}, - {m68k_op_bgt_16 , 0xffff, 0x6e00, { 10, 10, 6}}, - {m68k_op_bgt_32 , 0xffff, 0x6eff, { 0, 0, 6}}, - {m68k_op_ble_16 , 0xffff, 0x6f00, { 10, 10, 6}}, - {m68k_op_ble_32 , 0xffff, 0x6fff, { 0, 0, 6}}, - {m68k_op_sbcd_8_mm_axy7 , 0xffff, 0x8f0f, { 18, 18, 16}}, - {m68k_op_pack_16_mm_axy7 , 0xffff, 0x8f4f, { 0, 0, 13}}, - {m68k_op_unpk_16_mm_axy7 , 0xffff, 0x8f8f, { 0, 0, 13}}, - {m68k_op_subx_8_mm_axy7 , 0xffff, 0x9f0f, { 18, 18, 12}}, - {m68k_op_cmpm_8_axy7 , 0xffff, 0xbf0f, { 12, 12, 9}}, - {m68k_op_abcd_8_mm_axy7 , 0xffff, 0xcf0f, { 18, 18, 16}}, - {m68k_op_addx_8_mm_axy7 , 0xffff, 0xdf0f, { 18, 18, 12}}, - {m68k_op_asr_16_aw , 0xffff, 0xe0f8, { 16, 16, 9}}, - {m68k_op_asr_16_al , 0xffff, 0xe0f9, { 20, 20, 9}}, - {m68k_op_asl_16_aw , 0xffff, 0xe1f8, { 16, 16, 10}}, - {m68k_op_asl_16_al , 0xffff, 0xe1f9, { 20, 20, 10}}, - {m68k_op_lsr_16_aw , 0xffff, 0xe2f8, { 16, 16, 9}}, - {m68k_op_lsr_16_al , 0xffff, 0xe2f9, { 20, 20, 9}}, - {m68k_op_lsl_16_aw , 0xffff, 0xe3f8, { 16, 16, 9}}, - {m68k_op_lsl_16_al , 0xffff, 0xe3f9, { 20, 20, 9}}, - {m68k_op_roxr_16_aw , 0xffff, 0xe4f8, { 16, 16, 9}}, - {m68k_op_roxr_16_al , 0xffff, 0xe4f9, { 20, 20, 9}}, - {m68k_op_roxl_16_aw , 0xffff, 0xe5f8, { 16, 16, 9}}, - {m68k_op_roxl_16_al , 0xffff, 0xe5f9, { 20, 20, 9}}, - {m68k_op_ror_16_aw , 0xffff, 0xe6f8, { 16, 16, 11}}, - {m68k_op_ror_16_al , 0xffff, 0xe6f9, { 20, 20, 11}}, - {m68k_op_rol_16_aw , 0xffff, 0xe7f8, { 16, 16, 11}}, - {m68k_op_rol_16_al , 0xffff, 0xe7f9, { 20, 20, 11}}, - {m68k_op_bftst_32_aw , 0xffff, 0xe8f8, { 0, 0, 17}}, - {m68k_op_bftst_32_al , 0xffff, 0xe8f9, { 0, 0, 17}}, - {m68k_op_bftst_32_pcdi , 0xffff, 0xe8fa, { 0, 0, 18}}, - {m68k_op_bftst_32_pcix , 0xffff, 0xe8fb, { 0, 0, 20}}, - {m68k_op_bfextu_32_aw , 0xffff, 0xe9f8, { 0, 0, 19}}, - {m68k_op_bfextu_32_al , 0xffff, 0xe9f9, { 0, 0, 19}}, - {m68k_op_bfextu_32_pcdi , 0xffff, 0xe9fa, { 0, 0, 20}}, - {m68k_op_bfextu_32_pcix , 0xffff, 0xe9fb, { 0, 0, 22}}, - {m68k_op_bfchg_32_aw , 0xffff, 0xeaf8, { 0, 0, 24}}, - {m68k_op_bfchg_32_al , 0xffff, 0xeaf9, { 0, 0, 24}}, - {m68k_op_bfexts_32_aw , 0xffff, 0xebf8, { 0, 0, 19}}, - {m68k_op_bfexts_32_al , 0xffff, 0xebf9, { 0, 0, 19}}, - {m68k_op_bfexts_32_pcdi , 0xffff, 0xebfa, { 0, 0, 20}}, - {m68k_op_bfexts_32_pcix , 0xffff, 0xebfb, { 0, 0, 22}}, - {m68k_op_bfclr_32_aw , 0xffff, 0xecf8, { 0, 0, 24}}, - {m68k_op_bfclr_32_al , 0xffff, 0xecf9, { 0, 0, 24}}, - {m68k_op_bfffo_32_aw , 0xffff, 0xedf8, { 0, 0, 32}}, - {m68k_op_bfffo_32_al , 0xffff, 0xedf9, { 0, 0, 32}}, - {m68k_op_bfffo_32_pcdi , 0xffff, 0xedfa, { 0, 0, 33}}, - {m68k_op_bfffo_32_pcix , 0xffff, 0xedfb, { 0, 0, 35}}, - {m68k_op_bfset_32_aw , 0xffff, 0xeef8, { 0, 0, 24}}, - {m68k_op_bfset_32_al , 0xffff, 0xeef9, { 0, 0, 24}}, - {m68k_op_bfins_32_aw , 0xffff, 0xeff8, { 0, 0, 21}}, - {m68k_op_bfins_32_al , 0xffff, 0xeff9, { 0, 0, 21}}, - {0, 0, 0, {0, 0, 0}} -}; - - -/* Build the opcode handler jump table */ -void m68ki_build_opcode_table(void) -{ - opcode_handler_struct *ostruct; - int instr; - int i; - int j; - int k; - - for(i = 0; i < 0x10000; i++) - { - /* default to illegal */ - m68ki_instruction_jump_table[i] = m68k_op_illegal; - for(k=0;kmask != 0xff00) - { - for(i = 0;i < 0x10000;i++) - { - if((i & ostruct->mask) == ostruct->match) - { - m68ki_instruction_jump_table[i] = ostruct->opcode_handler; - for(k=0;kcycles[k]; - } - } - ostruct++; - } - while(ostruct->mask == 0xff00) - { - for(i = 0;i <= 0xff;i++) - { - m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler; - for(k=0;kmatch | i] = ostruct->cycles[k]; - } - ostruct++; - } - while(ostruct->mask == 0xf1f8) - { - for(i = 0;i < 8;i++) - { - for(j = 0;j < 8;j++) - { - instr = ostruct->match | (i << 9) | j; - m68ki_instruction_jump_table[instr] = ostruct->opcode_handler; - for(k=0;kcycles[k]; - if((instr & 0xf000) == 0xe000 && (!(instr & 0x20))) - m68ki_cycles[0][instr] = m68ki_cycles[1][instr] = ostruct->cycles[k] + ((((j-1)&7)+1)<<1); - } - } - ostruct++; - } - while(ostruct->mask == 0xfff0) - { - for(i = 0;i <= 0x0f;i++) - { - m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler; - for(k=0;kmatch | i] = ostruct->cycles[k]; - } - ostruct++; - } - while(ostruct->mask == 0xf1ff) - { - for(i = 0;i <= 0x07;i++) - { - m68ki_instruction_jump_table[ostruct->match | (i << 9)] = ostruct->opcode_handler; - for(k=0;kmatch | (i << 9)] = ostruct->cycles[k]; - } - ostruct++; - } - while(ostruct->mask == 0xfff8) - { - for(i = 0;i <= 0x07;i++) - { - m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler; - for(k=0;kmatch | i] = ostruct->cycles[k]; - } - ostruct++; - } - while(ostruct->mask == 0xffff) - { - m68ki_instruction_jump_table[ostruct->match] = ostruct->opcode_handler; - for(k=0;kmatch] = ostruct->cycles[k]; - ostruct++; - } -} - - -/* ======================================================================== */ -/* ============================== END OF FILE ============================= */ -/* ======================================================================== */ - - diff --git a/Frameworks/AudioOverload/aosdk/eng_ssf/m68kops.h b/Frameworks/AudioOverload/aosdk/eng_ssf/m68kops.h deleted file mode 100644 index 8524d2fe6..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_ssf/m68kops.h +++ /dev/null @@ -1,1984 +0,0 @@ -#ifndef M68KOPS__HEADER -#define M68KOPS__HEADER - -/* ======================================================================== */ -/* ============================ OPCODE HANDLERS =========================== */ -/* ======================================================================== */ - - -void m68k_op_1010(void); -void m68k_op_1111(void); -void m68k_op_abcd_8_rr(void); -void m68k_op_abcd_8_mm_ax7(void); -void m68k_op_abcd_8_mm_ay7(void); -void m68k_op_abcd_8_mm_axy7(void); -void m68k_op_abcd_8_mm(void); -void m68k_op_add_8_er_d(void); -void m68k_op_add_8_er_ai(void); -void m68k_op_add_8_er_pi(void); -void m68k_op_add_8_er_pi7(void); -void m68k_op_add_8_er_pd(void); -void m68k_op_add_8_er_pd7(void); -void m68k_op_add_8_er_di(void); -void m68k_op_add_8_er_ix(void); -void m68k_op_add_8_er_aw(void); -void m68k_op_add_8_er_al(void); -void m68k_op_add_8_er_pcdi(void); -void m68k_op_add_8_er_pcix(void); -void m68k_op_add_8_er_i(void); -void m68k_op_add_16_er_d(void); -void m68k_op_add_16_er_a(void); -void m68k_op_add_16_er_ai(void); -void m68k_op_add_16_er_pi(void); -void m68k_op_add_16_er_pd(void); -void m68k_op_add_16_er_di(void); -void m68k_op_add_16_er_ix(void); -void m68k_op_add_16_er_aw(void); -void m68k_op_add_16_er_al(void); -void m68k_op_add_16_er_pcdi(void); -void m68k_op_add_16_er_pcix(void); -void m68k_op_add_16_er_i(void); -void m68k_op_add_32_er_d(void); -void m68k_op_add_32_er_a(void); -void m68k_op_add_32_er_ai(void); -void m68k_op_add_32_er_pi(void); -void m68k_op_add_32_er_pd(void); -void m68k_op_add_32_er_di(void); -void m68k_op_add_32_er_ix(void); -void m68k_op_add_32_er_aw(void); -void m68k_op_add_32_er_al(void); -void m68k_op_add_32_er_pcdi(void); -void m68k_op_add_32_er_pcix(void); -void m68k_op_add_32_er_i(void); -void m68k_op_add_8_re_ai(void); -void m68k_op_add_8_re_pi(void); -void m68k_op_add_8_re_pi7(void); -void m68k_op_add_8_re_pd(void); -void m68k_op_add_8_re_pd7(void); -void m68k_op_add_8_re_di(void); -void m68k_op_add_8_re_ix(void); -void m68k_op_add_8_re_aw(void); -void m68k_op_add_8_re_al(void); -void m68k_op_add_16_re_ai(void); -void m68k_op_add_16_re_pi(void); -void m68k_op_add_16_re_pd(void); -void m68k_op_add_16_re_di(void); -void m68k_op_add_16_re_ix(void); -void m68k_op_add_16_re_aw(void); -void m68k_op_add_16_re_al(void); -void m68k_op_add_32_re_ai(void); -void m68k_op_add_32_re_pi(void); -void m68k_op_add_32_re_pd(void); -void m68k_op_add_32_re_di(void); -void m68k_op_add_32_re_ix(void); -void m68k_op_add_32_re_aw(void); -void m68k_op_add_32_re_al(void); -void m68k_op_adda_16_d(void); -void m68k_op_adda_16_a(void); -void m68k_op_adda_16_ai(void); -void m68k_op_adda_16_pi(void); -void m68k_op_adda_16_pd(void); -void m68k_op_adda_16_di(void); -void m68k_op_adda_16_ix(void); -void m68k_op_adda_16_aw(void); -void m68k_op_adda_16_al(void); -void m68k_op_adda_16_pcdi(void); -void m68k_op_adda_16_pcix(void); -void m68k_op_adda_16_i(void); -void m68k_op_adda_32_d(void); -void m68k_op_adda_32_a(void); -void m68k_op_adda_32_ai(void); -void m68k_op_adda_32_pi(void); -void m68k_op_adda_32_pd(void); -void m68k_op_adda_32_di(void); -void m68k_op_adda_32_ix(void); -void m68k_op_adda_32_aw(void); -void m68k_op_adda_32_al(void); -void m68k_op_adda_32_pcdi(void); -void m68k_op_adda_32_pcix(void); -void m68k_op_adda_32_i(void); -void m68k_op_addi_8_d(void); -void m68k_op_addi_8_ai(void); -void m68k_op_addi_8_pi(void); -void m68k_op_addi_8_pi7(void); -void m68k_op_addi_8_pd(void); -void m68k_op_addi_8_pd7(void); -void m68k_op_addi_8_di(void); -void m68k_op_addi_8_ix(void); -void m68k_op_addi_8_aw(void); -void m68k_op_addi_8_al(void); -void m68k_op_addi_16_d(void); -void m68k_op_addi_16_ai(void); -void m68k_op_addi_16_pi(void); -void m68k_op_addi_16_pd(void); -void m68k_op_addi_16_di(void); -void m68k_op_addi_16_ix(void); -void m68k_op_addi_16_aw(void); -void m68k_op_addi_16_al(void); -void m68k_op_addi_32_d(void); -void m68k_op_addi_32_ai(void); -void m68k_op_addi_32_pi(void); -void m68k_op_addi_32_pd(void); -void m68k_op_addi_32_di(void); -void m68k_op_addi_32_ix(void); -void m68k_op_addi_32_aw(void); -void m68k_op_addi_32_al(void); -void m68k_op_addq_8_d(void); -void m68k_op_addq_8_ai(void); -void m68k_op_addq_8_pi(void); -void m68k_op_addq_8_pi7(void); -void m68k_op_addq_8_pd(void); -void m68k_op_addq_8_pd7(void); -void m68k_op_addq_8_di(void); -void m68k_op_addq_8_ix(void); -void m68k_op_addq_8_aw(void); -void m68k_op_addq_8_al(void); -void m68k_op_addq_16_d(void); -void m68k_op_addq_16_a(void); -void m68k_op_addq_16_ai(void); -void m68k_op_addq_16_pi(void); -void m68k_op_addq_16_pd(void); -void m68k_op_addq_16_di(void); -void m68k_op_addq_16_ix(void); -void m68k_op_addq_16_aw(void); -void m68k_op_addq_16_al(void); -void m68k_op_addq_32_d(void); -void m68k_op_addq_32_a(void); -void m68k_op_addq_32_ai(void); -void m68k_op_addq_32_pi(void); -void m68k_op_addq_32_pd(void); -void m68k_op_addq_32_di(void); -void m68k_op_addq_32_ix(void); -void m68k_op_addq_32_aw(void); -void m68k_op_addq_32_al(void); -void m68k_op_addx_8_rr(void); -void m68k_op_addx_16_rr(void); -void m68k_op_addx_32_rr(void); -void m68k_op_addx_8_mm_ax7(void); -void m68k_op_addx_8_mm_ay7(void); -void m68k_op_addx_8_mm_axy7(void); -void m68k_op_addx_8_mm(void); -void m68k_op_addx_16_mm(void); -void m68k_op_addx_32_mm(void); -void m68k_op_and_8_er_d(void); -void m68k_op_and_8_er_ai(void); -void m68k_op_and_8_er_pi(void); -void m68k_op_and_8_er_pi7(void); -void m68k_op_and_8_er_pd(void); -void m68k_op_and_8_er_pd7(void); -void m68k_op_and_8_er_di(void); -void m68k_op_and_8_er_ix(void); -void m68k_op_and_8_er_aw(void); -void m68k_op_and_8_er_al(void); -void m68k_op_and_8_er_pcdi(void); -void m68k_op_and_8_er_pcix(void); -void m68k_op_and_8_er_i(void); -void m68k_op_and_16_er_d(void); -void m68k_op_and_16_er_ai(void); -void m68k_op_and_16_er_pi(void); -void m68k_op_and_16_er_pd(void); -void m68k_op_and_16_er_di(void); -void m68k_op_and_16_er_ix(void); -void m68k_op_and_16_er_aw(void); -void m68k_op_and_16_er_al(void); -void m68k_op_and_16_er_pcdi(void); -void m68k_op_and_16_er_pcix(void); -void m68k_op_and_16_er_i(void); -void m68k_op_and_32_er_d(void); -void m68k_op_and_32_er_ai(void); -void m68k_op_and_32_er_pi(void); -void m68k_op_and_32_er_pd(void); -void m68k_op_and_32_er_di(void); -void m68k_op_and_32_er_ix(void); -void m68k_op_and_32_er_aw(void); -void m68k_op_and_32_er_al(void); -void m68k_op_and_32_er_pcdi(void); -void m68k_op_and_32_er_pcix(void); -void m68k_op_and_32_er_i(void); -void m68k_op_and_8_re_ai(void); -void m68k_op_and_8_re_pi(void); -void m68k_op_and_8_re_pi7(void); -void m68k_op_and_8_re_pd(void); -void m68k_op_and_8_re_pd7(void); -void m68k_op_and_8_re_di(void); -void m68k_op_and_8_re_ix(void); -void m68k_op_and_8_re_aw(void); -void m68k_op_and_8_re_al(void); -void m68k_op_and_16_re_ai(void); -void m68k_op_and_16_re_pi(void); -void m68k_op_and_16_re_pd(void); -void m68k_op_and_16_re_di(void); -void m68k_op_and_16_re_ix(void); -void m68k_op_and_16_re_aw(void); -void m68k_op_and_16_re_al(void); -void m68k_op_and_32_re_ai(void); -void m68k_op_and_32_re_pi(void); -void m68k_op_and_32_re_pd(void); -void m68k_op_and_32_re_di(void); -void m68k_op_and_32_re_ix(void); -void m68k_op_and_32_re_aw(void); -void m68k_op_and_32_re_al(void); -void m68k_op_andi_8_d(void); -void m68k_op_andi_8_ai(void); -void m68k_op_andi_8_pi(void); -void m68k_op_andi_8_pi7(void); -void m68k_op_andi_8_pd(void); -void m68k_op_andi_8_pd7(void); -void m68k_op_andi_8_di(void); -void m68k_op_andi_8_ix(void); -void m68k_op_andi_8_aw(void); -void m68k_op_andi_8_al(void); -void m68k_op_andi_16_d(void); -void m68k_op_andi_16_ai(void); -void m68k_op_andi_16_pi(void); -void m68k_op_andi_16_pd(void); -void m68k_op_andi_16_di(void); -void m68k_op_andi_16_ix(void); -void m68k_op_andi_16_aw(void); -void m68k_op_andi_16_al(void); -void m68k_op_andi_32_d(void); -void m68k_op_andi_32_ai(void); -void m68k_op_andi_32_pi(void); -void m68k_op_andi_32_pd(void); -void m68k_op_andi_32_di(void); -void m68k_op_andi_32_ix(void); -void m68k_op_andi_32_aw(void); -void m68k_op_andi_32_al(void); -void m68k_op_andi_16_toc(void); -void m68k_op_andi_16_tos(void); -void m68k_op_asr_8_s(void); -void m68k_op_asr_16_s(void); -void m68k_op_asr_32_s(void); -void m68k_op_asr_8_r(void); -void m68k_op_asr_16_r(void); -void m68k_op_asr_32_r(void); -void m68k_op_asr_16_ai(void); -void m68k_op_asr_16_pi(void); -void m68k_op_asr_16_pd(void); -void m68k_op_asr_16_di(void); -void m68k_op_asr_16_ix(void); -void m68k_op_asr_16_aw(void); -void m68k_op_asr_16_al(void); -void m68k_op_asl_8_s(void); -void m68k_op_asl_16_s(void); -void m68k_op_asl_32_s(void); -void m68k_op_asl_8_r(void); -void m68k_op_asl_16_r(void); -void m68k_op_asl_32_r(void); -void m68k_op_asl_16_ai(void); -void m68k_op_asl_16_pi(void); -void m68k_op_asl_16_pd(void); -void m68k_op_asl_16_di(void); -void m68k_op_asl_16_ix(void); -void m68k_op_asl_16_aw(void); -void m68k_op_asl_16_al(void); -void m68k_op_bhi_8(void); -void m68k_op_bls_8(void); -void m68k_op_bcc_8(void); -void m68k_op_bcs_8(void); -void m68k_op_bne_8(void); -void m68k_op_beq_8(void); -void m68k_op_bvc_8(void); -void m68k_op_bvs_8(void); -void m68k_op_bpl_8(void); -void m68k_op_bmi_8(void); -void m68k_op_bge_8(void); -void m68k_op_blt_8(void); -void m68k_op_bgt_8(void); -void m68k_op_ble_8(void); -void m68k_op_bhi_16(void); -void m68k_op_bls_16(void); -void m68k_op_bcc_16(void); -void m68k_op_bcs_16(void); -void m68k_op_bne_16(void); -void m68k_op_beq_16(void); -void m68k_op_bvc_16(void); -void m68k_op_bvs_16(void); -void m68k_op_bpl_16(void); -void m68k_op_bmi_16(void); -void m68k_op_bge_16(void); -void m68k_op_blt_16(void); -void m68k_op_bgt_16(void); -void m68k_op_ble_16(void); -void m68k_op_bhi_32(void); -void m68k_op_bls_32(void); -void m68k_op_bcc_32(void); -void m68k_op_bcs_32(void); -void m68k_op_bne_32(void); -void m68k_op_beq_32(void); -void m68k_op_bvc_32(void); -void m68k_op_bvs_32(void); -void m68k_op_bpl_32(void); -void m68k_op_bmi_32(void); -void m68k_op_bge_32(void); -void m68k_op_blt_32(void); -void m68k_op_bgt_32(void); -void m68k_op_ble_32(void); -void m68k_op_bchg_32_r_d(void); -void m68k_op_bchg_8_r_ai(void); -void m68k_op_bchg_8_r_pi(void); -void m68k_op_bchg_8_r_pi7(void); -void m68k_op_bchg_8_r_pd(void); -void m68k_op_bchg_8_r_pd7(void); -void m68k_op_bchg_8_r_di(void); -void m68k_op_bchg_8_r_ix(void); -void m68k_op_bchg_8_r_aw(void); -void m68k_op_bchg_8_r_al(void); -void m68k_op_bchg_32_s_d(void); -void m68k_op_bchg_8_s_ai(void); -void m68k_op_bchg_8_s_pi(void); -void m68k_op_bchg_8_s_pi7(void); -void m68k_op_bchg_8_s_pd(void); -void m68k_op_bchg_8_s_pd7(void); -void m68k_op_bchg_8_s_di(void); -void m68k_op_bchg_8_s_ix(void); -void m68k_op_bchg_8_s_aw(void); -void m68k_op_bchg_8_s_al(void); -void m68k_op_bclr_32_r_d(void); -void m68k_op_bclr_8_r_ai(void); -void m68k_op_bclr_8_r_pi(void); -void m68k_op_bclr_8_r_pi7(void); -void m68k_op_bclr_8_r_pd(void); -void m68k_op_bclr_8_r_pd7(void); -void m68k_op_bclr_8_r_di(void); -void m68k_op_bclr_8_r_ix(void); -void m68k_op_bclr_8_r_aw(void); -void m68k_op_bclr_8_r_al(void); -void m68k_op_bclr_32_s_d(void); -void m68k_op_bclr_8_s_ai(void); -void m68k_op_bclr_8_s_pi(void); -void m68k_op_bclr_8_s_pi7(void); -void m68k_op_bclr_8_s_pd(void); -void m68k_op_bclr_8_s_pd7(void); -void m68k_op_bclr_8_s_di(void); -void m68k_op_bclr_8_s_ix(void); -void m68k_op_bclr_8_s_aw(void); -void m68k_op_bclr_8_s_al(void); -void m68k_op_bfchg_32_d(void); -void m68k_op_bfchg_32_ai(void); -void m68k_op_bfchg_32_di(void); -void m68k_op_bfchg_32_ix(void); -void m68k_op_bfchg_32_aw(void); -void m68k_op_bfchg_32_al(void); -void m68k_op_bfclr_32_d(void); -void m68k_op_bfclr_32_ai(void); -void m68k_op_bfclr_32_di(void); -void m68k_op_bfclr_32_ix(void); -void m68k_op_bfclr_32_aw(void); -void m68k_op_bfclr_32_al(void); -void m68k_op_bfexts_32_d(void); -void m68k_op_bfexts_32_ai(void); -void m68k_op_bfexts_32_di(void); -void m68k_op_bfexts_32_ix(void); -void m68k_op_bfexts_32_aw(void); -void m68k_op_bfexts_32_al(void); -void m68k_op_bfexts_32_pcdi(void); -void m68k_op_bfexts_32_pcix(void); -void m68k_op_bfextu_32_d(void); -void m68k_op_bfextu_32_ai(void); -void m68k_op_bfextu_32_di(void); -void m68k_op_bfextu_32_ix(void); -void m68k_op_bfextu_32_aw(void); -void m68k_op_bfextu_32_al(void); -void m68k_op_bfextu_32_pcdi(void); -void m68k_op_bfextu_32_pcix(void); -void m68k_op_bfffo_32_d(void); -void m68k_op_bfffo_32_ai(void); -void m68k_op_bfffo_32_di(void); -void m68k_op_bfffo_32_ix(void); -void m68k_op_bfffo_32_aw(void); -void m68k_op_bfffo_32_al(void); -void m68k_op_bfffo_32_pcdi(void); -void m68k_op_bfffo_32_pcix(void); -void m68k_op_bfins_32_d(void); -void m68k_op_bfins_32_ai(void); -void m68k_op_bfins_32_di(void); -void m68k_op_bfins_32_ix(void); -void m68k_op_bfins_32_aw(void); -void m68k_op_bfins_32_al(void); -void m68k_op_bfset_32_d(void); -void m68k_op_bfset_32_ai(void); -void m68k_op_bfset_32_di(void); -void m68k_op_bfset_32_ix(void); -void m68k_op_bfset_32_aw(void); -void m68k_op_bfset_32_al(void); -void m68k_op_bftst_32_d(void); -void m68k_op_bftst_32_ai(void); -void m68k_op_bftst_32_di(void); -void m68k_op_bftst_32_ix(void); -void m68k_op_bftst_32_aw(void); -void m68k_op_bftst_32_al(void); -void m68k_op_bftst_32_pcdi(void); -void m68k_op_bftst_32_pcix(void); -void m68k_op_bkpt(void); -void m68k_op_bra_8(void); -void m68k_op_bra_16(void); -void m68k_op_bra_32(void); -void m68k_op_bset_32_r_d(void); -void m68k_op_bset_8_r_ai(void); -void m68k_op_bset_8_r_pi(void); -void m68k_op_bset_8_r_pi7(void); -void m68k_op_bset_8_r_pd(void); -void m68k_op_bset_8_r_pd7(void); -void m68k_op_bset_8_r_di(void); -void m68k_op_bset_8_r_ix(void); -void m68k_op_bset_8_r_aw(void); -void m68k_op_bset_8_r_al(void); -void m68k_op_bset_32_s_d(void); -void m68k_op_bset_8_s_ai(void); -void m68k_op_bset_8_s_pi(void); -void m68k_op_bset_8_s_pi7(void); -void m68k_op_bset_8_s_pd(void); -void m68k_op_bset_8_s_pd7(void); -void m68k_op_bset_8_s_di(void); -void m68k_op_bset_8_s_ix(void); -void m68k_op_bset_8_s_aw(void); -void m68k_op_bset_8_s_al(void); -void m68k_op_bsr_8(void); -void m68k_op_bsr_16(void); -void m68k_op_bsr_32(void); -void m68k_op_btst_32_r_d(void); -void m68k_op_btst_8_r_ai(void); -void m68k_op_btst_8_r_pi(void); -void m68k_op_btst_8_r_pi7(void); -void m68k_op_btst_8_r_pd(void); -void m68k_op_btst_8_r_pd7(void); -void m68k_op_btst_8_r_di(void); -void m68k_op_btst_8_r_ix(void); -void m68k_op_btst_8_r_aw(void); -void m68k_op_btst_8_r_al(void); -void m68k_op_btst_8_r_pcdi(void); -void m68k_op_btst_8_r_pcix(void); -void m68k_op_btst_8_r_i(void); -void m68k_op_btst_32_s_d(void); -void m68k_op_btst_8_s_ai(void); -void m68k_op_btst_8_s_pi(void); -void m68k_op_btst_8_s_pi7(void); -void m68k_op_btst_8_s_pd(void); -void m68k_op_btst_8_s_pd7(void); -void m68k_op_btst_8_s_di(void); -void m68k_op_btst_8_s_ix(void); -void m68k_op_btst_8_s_aw(void); -void m68k_op_btst_8_s_al(void); -void m68k_op_btst_8_s_pcdi(void); -void m68k_op_btst_8_s_pcix(void); -void m68k_op_callm_32_ai(void); -void m68k_op_callm_32_di(void); -void m68k_op_callm_32_ix(void); -void m68k_op_callm_32_aw(void); -void m68k_op_callm_32_al(void); -void m68k_op_callm_32_pcdi(void); -void m68k_op_callm_32_pcix(void); -void m68k_op_cas_8_ai(void); -void m68k_op_cas_8_pi(void); -void m68k_op_cas_8_pi7(void); -void m68k_op_cas_8_pd(void); -void m68k_op_cas_8_pd7(void); -void m68k_op_cas_8_di(void); -void m68k_op_cas_8_ix(void); -void m68k_op_cas_8_aw(void); -void m68k_op_cas_8_al(void); -void m68k_op_cas_16_ai(void); -void m68k_op_cas_16_pi(void); -void m68k_op_cas_16_pd(void); -void m68k_op_cas_16_di(void); -void m68k_op_cas_16_ix(void); -void m68k_op_cas_16_aw(void); -void m68k_op_cas_16_al(void); -void m68k_op_cas_32_ai(void); -void m68k_op_cas_32_pi(void); -void m68k_op_cas_32_pd(void); -void m68k_op_cas_32_di(void); -void m68k_op_cas_32_ix(void); -void m68k_op_cas_32_aw(void); -void m68k_op_cas_32_al(void); -void m68k_op_cas2_16(void); -void m68k_op_cas2_32(void); -void m68k_op_chk_16_d(void); -void m68k_op_chk_16_ai(void); -void m68k_op_chk_16_pi(void); -void m68k_op_chk_16_pd(void); -void m68k_op_chk_16_di(void); -void m68k_op_chk_16_ix(void); -void m68k_op_chk_16_aw(void); -void m68k_op_chk_16_al(void); -void m68k_op_chk_16_pcdi(void); -void m68k_op_chk_16_pcix(void); -void m68k_op_chk_16_i(void); -void m68k_op_chk_32_d(void); -void m68k_op_chk_32_ai(void); -void m68k_op_chk_32_pi(void); -void m68k_op_chk_32_pd(void); -void m68k_op_chk_32_di(void); -void m68k_op_chk_32_ix(void); -void m68k_op_chk_32_aw(void); -void m68k_op_chk_32_al(void); -void m68k_op_chk_32_pcdi(void); -void m68k_op_chk_32_pcix(void); -void m68k_op_chk_32_i(void); -void m68k_op_chk2cmp2_8_pcdi(void); -void m68k_op_chk2cmp2_8_pcix(void); -void m68k_op_chk2cmp2_8_ai(void); -void m68k_op_chk2cmp2_8_di(void); -void m68k_op_chk2cmp2_8_ix(void); -void m68k_op_chk2cmp2_8_aw(void); -void m68k_op_chk2cmp2_8_al(void); -void m68k_op_chk2cmp2_16_pcdi(void); -void m68k_op_chk2cmp2_16_pcix(void); -void m68k_op_chk2cmp2_16_ai(void); -void m68k_op_chk2cmp2_16_di(void); -void m68k_op_chk2cmp2_16_ix(void); -void m68k_op_chk2cmp2_16_aw(void); -void m68k_op_chk2cmp2_16_al(void); -void m68k_op_chk2cmp2_32_pcdi(void); -void m68k_op_chk2cmp2_32_pcix(void); -void m68k_op_chk2cmp2_32_ai(void); -void m68k_op_chk2cmp2_32_di(void); -void m68k_op_chk2cmp2_32_ix(void); -void m68k_op_chk2cmp2_32_aw(void); -void m68k_op_chk2cmp2_32_al(void); -void m68k_op_clr_8_d(void); -void m68k_op_clr_8_ai(void); -void m68k_op_clr_8_pi(void); -void m68k_op_clr_8_pi7(void); -void m68k_op_clr_8_pd(void); -void m68k_op_clr_8_pd7(void); -void m68k_op_clr_8_di(void); -void m68k_op_clr_8_ix(void); -void m68k_op_clr_8_aw(void); -void m68k_op_clr_8_al(void); -void m68k_op_clr_16_d(void); -void m68k_op_clr_16_ai(void); -void m68k_op_clr_16_pi(void); -void m68k_op_clr_16_pd(void); -void m68k_op_clr_16_di(void); -void m68k_op_clr_16_ix(void); -void m68k_op_clr_16_aw(void); -void m68k_op_clr_16_al(void); -void m68k_op_clr_32_d(void); -void m68k_op_clr_32_ai(void); -void m68k_op_clr_32_pi(void); -void m68k_op_clr_32_pd(void); -void m68k_op_clr_32_di(void); -void m68k_op_clr_32_ix(void); -void m68k_op_clr_32_aw(void); -void m68k_op_clr_32_al(void); -void m68k_op_cmp_8_d(void); -void m68k_op_cmp_8_ai(void); -void m68k_op_cmp_8_pi(void); -void m68k_op_cmp_8_pi7(void); -void m68k_op_cmp_8_pd(void); -void m68k_op_cmp_8_pd7(void); -void m68k_op_cmp_8_di(void); -void m68k_op_cmp_8_ix(void); -void m68k_op_cmp_8_aw(void); -void m68k_op_cmp_8_al(void); -void m68k_op_cmp_8_pcdi(void); -void m68k_op_cmp_8_pcix(void); -void m68k_op_cmp_8_i(void); -void m68k_op_cmp_16_d(void); -void m68k_op_cmp_16_a(void); -void m68k_op_cmp_16_ai(void); -void m68k_op_cmp_16_pi(void); -void m68k_op_cmp_16_pd(void); -void m68k_op_cmp_16_di(void); -void m68k_op_cmp_16_ix(void); -void m68k_op_cmp_16_aw(void); -void m68k_op_cmp_16_al(void); -void m68k_op_cmp_16_pcdi(void); -void m68k_op_cmp_16_pcix(void); -void m68k_op_cmp_16_i(void); -void m68k_op_cmp_32_d(void); -void m68k_op_cmp_32_a(void); -void m68k_op_cmp_32_ai(void); -void m68k_op_cmp_32_pi(void); -void m68k_op_cmp_32_pd(void); -void m68k_op_cmp_32_di(void); -void m68k_op_cmp_32_ix(void); -void m68k_op_cmp_32_aw(void); -void m68k_op_cmp_32_al(void); -void m68k_op_cmp_32_pcdi(void); -void m68k_op_cmp_32_pcix(void); -void m68k_op_cmp_32_i(void); -void m68k_op_cmpa_16_d(void); -void m68k_op_cmpa_16_a(void); -void m68k_op_cmpa_16_ai(void); -void m68k_op_cmpa_16_pi(void); -void m68k_op_cmpa_16_pd(void); -void m68k_op_cmpa_16_di(void); -void m68k_op_cmpa_16_ix(void); -void m68k_op_cmpa_16_aw(void); -void m68k_op_cmpa_16_al(void); -void m68k_op_cmpa_16_pcdi(void); -void m68k_op_cmpa_16_pcix(void); -void m68k_op_cmpa_16_i(void); -void m68k_op_cmpa_32_d(void); -void m68k_op_cmpa_32_a(void); -void m68k_op_cmpa_32_ai(void); -void m68k_op_cmpa_32_pi(void); -void m68k_op_cmpa_32_pd(void); -void m68k_op_cmpa_32_di(void); -void m68k_op_cmpa_32_ix(void); -void m68k_op_cmpa_32_aw(void); -void m68k_op_cmpa_32_al(void); -void m68k_op_cmpa_32_pcdi(void); -void m68k_op_cmpa_32_pcix(void); -void m68k_op_cmpa_32_i(void); -void m68k_op_cmpi_8_d(void); -void m68k_op_cmpi_8_ai(void); -void m68k_op_cmpi_8_pi(void); -void m68k_op_cmpi_8_pi7(void); -void m68k_op_cmpi_8_pd(void); -void m68k_op_cmpi_8_pd7(void); -void m68k_op_cmpi_8_di(void); -void m68k_op_cmpi_8_ix(void); -void m68k_op_cmpi_8_aw(void); -void m68k_op_cmpi_8_al(void); -void m68k_op_cmpi_8_pcdi(void); -void m68k_op_cmpi_8_pcix(void); -void m68k_op_cmpi_16_d(void); -void m68k_op_cmpi_16_ai(void); -void m68k_op_cmpi_16_pi(void); -void m68k_op_cmpi_16_pd(void); -void m68k_op_cmpi_16_di(void); -void m68k_op_cmpi_16_ix(void); -void m68k_op_cmpi_16_aw(void); -void m68k_op_cmpi_16_al(void); -void m68k_op_cmpi_16_pcdi(void); -void m68k_op_cmpi_16_pcix(void); -void m68k_op_cmpi_32_d(void); -void m68k_op_cmpi_32_ai(void); -void m68k_op_cmpi_32_pi(void); -void m68k_op_cmpi_32_pd(void); -void m68k_op_cmpi_32_di(void); -void m68k_op_cmpi_32_ix(void); -void m68k_op_cmpi_32_aw(void); -void m68k_op_cmpi_32_al(void); -void m68k_op_cmpi_32_pcdi(void); -void m68k_op_cmpi_32_pcix(void); -void m68k_op_cmpm_8_ax7(void); -void m68k_op_cmpm_8_ay7(void); -void m68k_op_cmpm_8_axy7(void); -void m68k_op_cmpm_8(void); -void m68k_op_cmpm_16(void); -void m68k_op_cmpm_32(void); -void m68k_op_cpbcc_32(void); -void m68k_op_cpdbcc_32(void); -void m68k_op_cpgen_32(void); -void m68k_op_cpscc_32(void); -void m68k_op_cptrapcc_32(void); -void m68k_op_dbt_16(void); -void m68k_op_dbf_16(void); -void m68k_op_dbhi_16(void); -void m68k_op_dbls_16(void); -void m68k_op_dbcc_16(void); -void m68k_op_dbcs_16(void); -void m68k_op_dbne_16(void); -void m68k_op_dbeq_16(void); -void m68k_op_dbvc_16(void); -void m68k_op_dbvs_16(void); -void m68k_op_dbpl_16(void); -void m68k_op_dbmi_16(void); -void m68k_op_dbge_16(void); -void m68k_op_dblt_16(void); -void m68k_op_dbgt_16(void); -void m68k_op_dble_16(void); -void m68k_op_divs_16_d(void); -void m68k_op_divs_16_ai(void); -void m68k_op_divs_16_pi(void); -void m68k_op_divs_16_pd(void); -void m68k_op_divs_16_di(void); -void m68k_op_divs_16_ix(void); -void m68k_op_divs_16_aw(void); -void m68k_op_divs_16_al(void); -void m68k_op_divs_16_pcdi(void); -void m68k_op_divs_16_pcix(void); -void m68k_op_divs_16_i(void); -void m68k_op_divu_16_d(void); -void m68k_op_divu_16_ai(void); -void m68k_op_divu_16_pi(void); -void m68k_op_divu_16_pd(void); -void m68k_op_divu_16_di(void); -void m68k_op_divu_16_ix(void); -void m68k_op_divu_16_aw(void); -void m68k_op_divu_16_al(void); -void m68k_op_divu_16_pcdi(void); -void m68k_op_divu_16_pcix(void); -void m68k_op_divu_16_i(void); -void m68k_op_divl_32_d(void); -void m68k_op_divl_32_ai(void); -void m68k_op_divl_32_pi(void); -void m68k_op_divl_32_pd(void); -void m68k_op_divl_32_di(void); -void m68k_op_divl_32_ix(void); -void m68k_op_divl_32_aw(void); -void m68k_op_divl_32_al(void); -void m68k_op_divl_32_pcdi(void); -void m68k_op_divl_32_pcix(void); -void m68k_op_divl_32_i(void); -void m68k_op_eor_8_d(void); -void m68k_op_eor_8_ai(void); -void m68k_op_eor_8_pi(void); -void m68k_op_eor_8_pi7(void); -void m68k_op_eor_8_pd(void); -void m68k_op_eor_8_pd7(void); -void m68k_op_eor_8_di(void); -void m68k_op_eor_8_ix(void); -void m68k_op_eor_8_aw(void); -void m68k_op_eor_8_al(void); -void m68k_op_eor_16_d(void); -void m68k_op_eor_16_ai(void); -void m68k_op_eor_16_pi(void); -void m68k_op_eor_16_pd(void); -void m68k_op_eor_16_di(void); -void m68k_op_eor_16_ix(void); -void m68k_op_eor_16_aw(void); -void m68k_op_eor_16_al(void); -void m68k_op_eor_32_d(void); -void m68k_op_eor_32_ai(void); -void m68k_op_eor_32_pi(void); -void m68k_op_eor_32_pd(void); -void m68k_op_eor_32_di(void); -void m68k_op_eor_32_ix(void); -void m68k_op_eor_32_aw(void); -void m68k_op_eor_32_al(void); -void m68k_op_eori_8_d(void); -void m68k_op_eori_8_ai(void); -void m68k_op_eori_8_pi(void); -void m68k_op_eori_8_pi7(void); -void m68k_op_eori_8_pd(void); -void m68k_op_eori_8_pd7(void); -void m68k_op_eori_8_di(void); -void m68k_op_eori_8_ix(void); -void m68k_op_eori_8_aw(void); -void m68k_op_eori_8_al(void); -void m68k_op_eori_16_d(void); -void m68k_op_eori_16_ai(void); -void m68k_op_eori_16_pi(void); -void m68k_op_eori_16_pd(void); -void m68k_op_eori_16_di(void); -void m68k_op_eori_16_ix(void); -void m68k_op_eori_16_aw(void); -void m68k_op_eori_16_al(void); -void m68k_op_eori_32_d(void); -void m68k_op_eori_32_ai(void); -void m68k_op_eori_32_pi(void); -void m68k_op_eori_32_pd(void); -void m68k_op_eori_32_di(void); -void m68k_op_eori_32_ix(void); -void m68k_op_eori_32_aw(void); -void m68k_op_eori_32_al(void); -void m68k_op_eori_16_toc(void); -void m68k_op_eori_16_tos(void); -void m68k_op_exg_32_dd(void); -void m68k_op_exg_32_aa(void); -void m68k_op_exg_32_da(void); -void m68k_op_ext_16(void); -void m68k_op_ext_32(void); -void m68k_op_extb_32(void); -void m68k_op_illegal(void); -void m68k_op_jmp_32_ai(void); -void m68k_op_jmp_32_di(void); -void m68k_op_jmp_32_ix(void); -void m68k_op_jmp_32_aw(void); -void m68k_op_jmp_32_al(void); -void m68k_op_jmp_32_pcdi(void); -void m68k_op_jmp_32_pcix(void); -void m68k_op_jsr_32_ai(void); -void m68k_op_jsr_32_di(void); -void m68k_op_jsr_32_ix(void); -void m68k_op_jsr_32_aw(void); -void m68k_op_jsr_32_al(void); -void m68k_op_jsr_32_pcdi(void); -void m68k_op_jsr_32_pcix(void); -void m68k_op_lea_32_ai(void); -void m68k_op_lea_32_di(void); -void m68k_op_lea_32_ix(void); -void m68k_op_lea_32_aw(void); -void m68k_op_lea_32_al(void); -void m68k_op_lea_32_pcdi(void); -void m68k_op_lea_32_pcix(void); -void m68k_op_link_16_a7(void); -void m68k_op_link_16(void); -void m68k_op_link_32_a7(void); -void m68k_op_link_32(void); -void m68k_op_lsr_8_s(void); -void m68k_op_lsr_16_s(void); -void m68k_op_lsr_32_s(void); -void m68k_op_lsr_8_r(void); -void m68k_op_lsr_16_r(void); -void m68k_op_lsr_32_r(void); -void m68k_op_lsr_16_ai(void); -void m68k_op_lsr_16_pi(void); -void m68k_op_lsr_16_pd(void); -void m68k_op_lsr_16_di(void); -void m68k_op_lsr_16_ix(void); -void m68k_op_lsr_16_aw(void); -void m68k_op_lsr_16_al(void); -void m68k_op_lsl_8_s(void); -void m68k_op_lsl_16_s(void); -void m68k_op_lsl_32_s(void); -void m68k_op_lsl_8_r(void); -void m68k_op_lsl_16_r(void); -void m68k_op_lsl_32_r(void); -void m68k_op_lsl_16_ai(void); -void m68k_op_lsl_16_pi(void); -void m68k_op_lsl_16_pd(void); -void m68k_op_lsl_16_di(void); -void m68k_op_lsl_16_ix(void); -void m68k_op_lsl_16_aw(void); -void m68k_op_lsl_16_al(void); -void m68k_op_move_8_d_d(void); -void m68k_op_move_8_d_ai(void); -void m68k_op_move_8_d_pi(void); -void m68k_op_move_8_d_pi7(void); -void m68k_op_move_8_d_pd(void); -void m68k_op_move_8_d_pd7(void); -void m68k_op_move_8_d_di(void); -void m68k_op_move_8_d_ix(void); -void m68k_op_move_8_d_aw(void); -void m68k_op_move_8_d_al(void); -void m68k_op_move_8_d_pcdi(void); -void m68k_op_move_8_d_pcix(void); -void m68k_op_move_8_d_i(void); -void m68k_op_move_8_ai_d(void); -void m68k_op_move_8_ai_ai(void); -void m68k_op_move_8_ai_pi(void); -void m68k_op_move_8_ai_pi7(void); -void m68k_op_move_8_ai_pd(void); -void m68k_op_move_8_ai_pd7(void); -void m68k_op_move_8_ai_di(void); -void m68k_op_move_8_ai_ix(void); -void m68k_op_move_8_ai_aw(void); -void m68k_op_move_8_ai_al(void); -void m68k_op_move_8_ai_pcdi(void); -void m68k_op_move_8_ai_pcix(void); -void m68k_op_move_8_ai_i(void); -void m68k_op_move_8_pi7_d(void); -void m68k_op_move_8_pi_d(void); -void m68k_op_move_8_pi7_ai(void); -void m68k_op_move_8_pi7_pi(void); -void m68k_op_move_8_pi7_pi7(void); -void m68k_op_move_8_pi7_pd(void); -void m68k_op_move_8_pi7_pd7(void); -void m68k_op_move_8_pi7_di(void); -void m68k_op_move_8_pi7_ix(void); -void m68k_op_move_8_pi7_aw(void); -void m68k_op_move_8_pi7_al(void); -void m68k_op_move_8_pi7_pcdi(void); -void m68k_op_move_8_pi7_pcix(void); -void m68k_op_move_8_pi7_i(void); -void m68k_op_move_8_pi_ai(void); -void m68k_op_move_8_pi_pi(void); -void m68k_op_move_8_pi_pi7(void); -void m68k_op_move_8_pi_pd(void); -void m68k_op_move_8_pi_pd7(void); -void m68k_op_move_8_pi_di(void); -void m68k_op_move_8_pi_ix(void); -void m68k_op_move_8_pi_aw(void); -void m68k_op_move_8_pi_al(void); -void m68k_op_move_8_pi_pcdi(void); -void m68k_op_move_8_pi_pcix(void); -void m68k_op_move_8_pi_i(void); -void m68k_op_move_8_pd7_d(void); -void m68k_op_move_8_pd_d(void); -void m68k_op_move_8_pd7_ai(void); -void m68k_op_move_8_pd7_pi(void); -void m68k_op_move_8_pd7_pi7(void); -void m68k_op_move_8_pd7_pd(void); -void m68k_op_move_8_pd7_pd7(void); -void m68k_op_move_8_pd7_di(void); -void m68k_op_move_8_pd7_ix(void); -void m68k_op_move_8_pd7_aw(void); -void m68k_op_move_8_pd7_al(void); -void m68k_op_move_8_pd7_pcdi(void); -void m68k_op_move_8_pd7_pcix(void); -void m68k_op_move_8_pd7_i(void); -void m68k_op_move_8_pd_ai(void); -void m68k_op_move_8_pd_pi(void); -void m68k_op_move_8_pd_pi7(void); -void m68k_op_move_8_pd_pd(void); -void m68k_op_move_8_pd_pd7(void); -void m68k_op_move_8_pd_di(void); -void m68k_op_move_8_pd_ix(void); -void m68k_op_move_8_pd_aw(void); -void m68k_op_move_8_pd_al(void); -void m68k_op_move_8_pd_pcdi(void); -void m68k_op_move_8_pd_pcix(void); -void m68k_op_move_8_pd_i(void); -void m68k_op_move_8_di_d(void); -void m68k_op_move_8_di_ai(void); -void m68k_op_move_8_di_pi(void); -void m68k_op_move_8_di_pi7(void); -void m68k_op_move_8_di_pd(void); -void m68k_op_move_8_di_pd7(void); -void m68k_op_move_8_di_di(void); -void m68k_op_move_8_di_ix(void); -void m68k_op_move_8_di_aw(void); -void m68k_op_move_8_di_al(void); -void m68k_op_move_8_di_pcdi(void); -void m68k_op_move_8_di_pcix(void); -void m68k_op_move_8_di_i(void); -void m68k_op_move_8_ix_d(void); -void m68k_op_move_8_ix_ai(void); -void m68k_op_move_8_ix_pi(void); -void m68k_op_move_8_ix_pi7(void); -void m68k_op_move_8_ix_pd(void); -void m68k_op_move_8_ix_pd7(void); -void m68k_op_move_8_ix_di(void); -void m68k_op_move_8_ix_ix(void); -void m68k_op_move_8_ix_aw(void); -void m68k_op_move_8_ix_al(void); -void m68k_op_move_8_ix_pcdi(void); -void m68k_op_move_8_ix_pcix(void); -void m68k_op_move_8_ix_i(void); -void m68k_op_move_8_aw_d(void); -void m68k_op_move_8_aw_ai(void); -void m68k_op_move_8_aw_pi(void); -void m68k_op_move_8_aw_pi7(void); -void m68k_op_move_8_aw_pd(void); -void m68k_op_move_8_aw_pd7(void); -void m68k_op_move_8_aw_di(void); -void m68k_op_move_8_aw_ix(void); -void m68k_op_move_8_aw_aw(void); -void m68k_op_move_8_aw_al(void); -void m68k_op_move_8_aw_pcdi(void); -void m68k_op_move_8_aw_pcix(void); -void m68k_op_move_8_aw_i(void); -void m68k_op_move_8_al_d(void); -void m68k_op_move_8_al_ai(void); -void m68k_op_move_8_al_pi(void); -void m68k_op_move_8_al_pi7(void); -void m68k_op_move_8_al_pd(void); -void m68k_op_move_8_al_pd7(void); -void m68k_op_move_8_al_di(void); -void m68k_op_move_8_al_ix(void); -void m68k_op_move_8_al_aw(void); -void m68k_op_move_8_al_al(void); -void m68k_op_move_8_al_pcdi(void); -void m68k_op_move_8_al_pcix(void); -void m68k_op_move_8_al_i(void); -void m68k_op_move_16_d_d(void); -void m68k_op_move_16_d_a(void); -void m68k_op_move_16_d_ai(void); -void m68k_op_move_16_d_pi(void); -void m68k_op_move_16_d_pd(void); -void m68k_op_move_16_d_di(void); -void m68k_op_move_16_d_ix(void); -void m68k_op_move_16_d_aw(void); -void m68k_op_move_16_d_al(void); -void m68k_op_move_16_d_pcdi(void); -void m68k_op_move_16_d_pcix(void); -void m68k_op_move_16_d_i(void); -void m68k_op_move_16_ai_d(void); -void m68k_op_move_16_ai_a(void); -void m68k_op_move_16_ai_ai(void); -void m68k_op_move_16_ai_pi(void); -void m68k_op_move_16_ai_pd(void); -void m68k_op_move_16_ai_di(void); -void m68k_op_move_16_ai_ix(void); -void m68k_op_move_16_ai_aw(void); -void m68k_op_move_16_ai_al(void); -void m68k_op_move_16_ai_pcdi(void); -void m68k_op_move_16_ai_pcix(void); -void m68k_op_move_16_ai_i(void); -void m68k_op_move_16_pi_d(void); -void m68k_op_move_16_pi_a(void); -void m68k_op_move_16_pi_ai(void); -void m68k_op_move_16_pi_pi(void); -void m68k_op_move_16_pi_pd(void); -void m68k_op_move_16_pi_di(void); -void m68k_op_move_16_pi_ix(void); -void m68k_op_move_16_pi_aw(void); -void m68k_op_move_16_pi_al(void); -void m68k_op_move_16_pi_pcdi(void); -void m68k_op_move_16_pi_pcix(void); -void m68k_op_move_16_pi_i(void); -void m68k_op_move_16_pd_d(void); -void m68k_op_move_16_pd_a(void); -void m68k_op_move_16_pd_ai(void); -void m68k_op_move_16_pd_pi(void); -void m68k_op_move_16_pd_pd(void); -void m68k_op_move_16_pd_di(void); -void m68k_op_move_16_pd_ix(void); -void m68k_op_move_16_pd_aw(void); -void m68k_op_move_16_pd_al(void); -void m68k_op_move_16_pd_pcdi(void); -void m68k_op_move_16_pd_pcix(void); -void m68k_op_move_16_pd_i(void); -void m68k_op_move_16_di_d(void); -void m68k_op_move_16_di_a(void); -void m68k_op_move_16_di_ai(void); -void m68k_op_move_16_di_pi(void); -void m68k_op_move_16_di_pd(void); -void m68k_op_move_16_di_di(void); -void m68k_op_move_16_di_ix(void); -void m68k_op_move_16_di_aw(void); -void m68k_op_move_16_di_al(void); -void m68k_op_move_16_di_pcdi(void); -void m68k_op_move_16_di_pcix(void); -void m68k_op_move_16_di_i(void); -void m68k_op_move_16_ix_d(void); -void m68k_op_move_16_ix_a(void); -void m68k_op_move_16_ix_ai(void); -void m68k_op_move_16_ix_pi(void); -void m68k_op_move_16_ix_pd(void); -void m68k_op_move_16_ix_di(void); -void m68k_op_move_16_ix_ix(void); -void m68k_op_move_16_ix_aw(void); -void m68k_op_move_16_ix_al(void); -void m68k_op_move_16_ix_pcdi(void); -void m68k_op_move_16_ix_pcix(void); -void m68k_op_move_16_ix_i(void); -void m68k_op_move_16_aw_d(void); -void m68k_op_move_16_aw_a(void); -void m68k_op_move_16_aw_ai(void); -void m68k_op_move_16_aw_pi(void); -void m68k_op_move_16_aw_pd(void); -void m68k_op_move_16_aw_di(void); -void m68k_op_move_16_aw_ix(void); -void m68k_op_move_16_aw_aw(void); -void m68k_op_move_16_aw_al(void); -void m68k_op_move_16_aw_pcdi(void); -void m68k_op_move_16_aw_pcix(void); -void m68k_op_move_16_aw_i(void); -void m68k_op_move_16_al_d(void); -void m68k_op_move_16_al_a(void); -void m68k_op_move_16_al_ai(void); -void m68k_op_move_16_al_pi(void); -void m68k_op_move_16_al_pd(void); -void m68k_op_move_16_al_di(void); -void m68k_op_move_16_al_ix(void); -void m68k_op_move_16_al_aw(void); -void m68k_op_move_16_al_al(void); -void m68k_op_move_16_al_pcdi(void); -void m68k_op_move_16_al_pcix(void); -void m68k_op_move_16_al_i(void); -void m68k_op_move_32_d_d(void); -void m68k_op_move_32_d_a(void); -void m68k_op_move_32_d_ai(void); -void m68k_op_move_32_d_pi(void); -void m68k_op_move_32_d_pd(void); -void m68k_op_move_32_d_di(void); -void m68k_op_move_32_d_ix(void); -void m68k_op_move_32_d_aw(void); -void m68k_op_move_32_d_al(void); -void m68k_op_move_32_d_pcdi(void); -void m68k_op_move_32_d_pcix(void); -void m68k_op_move_32_d_i(void); -void m68k_op_move_32_ai_d(void); -void m68k_op_move_32_ai_a(void); -void m68k_op_move_32_ai_ai(void); -void m68k_op_move_32_ai_pi(void); -void m68k_op_move_32_ai_pd(void); -void m68k_op_move_32_ai_di(void); -void m68k_op_move_32_ai_ix(void); -void m68k_op_move_32_ai_aw(void); -void m68k_op_move_32_ai_al(void); -void m68k_op_move_32_ai_pcdi(void); -void m68k_op_move_32_ai_pcix(void); -void m68k_op_move_32_ai_i(void); -void m68k_op_move_32_pi_d(void); -void m68k_op_move_32_pi_a(void); -void m68k_op_move_32_pi_ai(void); -void m68k_op_move_32_pi_pi(void); -void m68k_op_move_32_pi_pd(void); -void m68k_op_move_32_pi_di(void); -void m68k_op_move_32_pi_ix(void); -void m68k_op_move_32_pi_aw(void); -void m68k_op_move_32_pi_al(void); -void m68k_op_move_32_pi_pcdi(void); -void m68k_op_move_32_pi_pcix(void); -void m68k_op_move_32_pi_i(void); -void m68k_op_move_32_pd_d(void); -void m68k_op_move_32_pd_a(void); -void m68k_op_move_32_pd_ai(void); -void m68k_op_move_32_pd_pi(void); -void m68k_op_move_32_pd_pd(void); -void m68k_op_move_32_pd_di(void); -void m68k_op_move_32_pd_ix(void); -void m68k_op_move_32_pd_aw(void); -void m68k_op_move_32_pd_al(void); -void m68k_op_move_32_pd_pcdi(void); -void m68k_op_move_32_pd_pcix(void); -void m68k_op_move_32_pd_i(void); -void m68k_op_move_32_di_d(void); -void m68k_op_move_32_di_a(void); -void m68k_op_move_32_di_ai(void); -void m68k_op_move_32_di_pi(void); -void m68k_op_move_32_di_pd(void); -void m68k_op_move_32_di_di(void); -void m68k_op_move_32_di_ix(void); -void m68k_op_move_32_di_aw(void); -void m68k_op_move_32_di_al(void); -void m68k_op_move_32_di_pcdi(void); -void m68k_op_move_32_di_pcix(void); -void m68k_op_move_32_di_i(void); -void m68k_op_move_32_ix_d(void); -void m68k_op_move_32_ix_a(void); -void m68k_op_move_32_ix_ai(void); -void m68k_op_move_32_ix_pi(void); -void m68k_op_move_32_ix_pd(void); -void m68k_op_move_32_ix_di(void); -void m68k_op_move_32_ix_ix(void); -void m68k_op_move_32_ix_aw(void); -void m68k_op_move_32_ix_al(void); -void m68k_op_move_32_ix_pcdi(void); -void m68k_op_move_32_ix_pcix(void); -void m68k_op_move_32_ix_i(void); -void m68k_op_move_32_aw_d(void); -void m68k_op_move_32_aw_a(void); -void m68k_op_move_32_aw_ai(void); -void m68k_op_move_32_aw_pi(void); -void m68k_op_move_32_aw_pd(void); -void m68k_op_move_32_aw_di(void); -void m68k_op_move_32_aw_ix(void); -void m68k_op_move_32_aw_aw(void); -void m68k_op_move_32_aw_al(void); -void m68k_op_move_32_aw_pcdi(void); -void m68k_op_move_32_aw_pcix(void); -void m68k_op_move_32_aw_i(void); -void m68k_op_move_32_al_d(void); -void m68k_op_move_32_al_a(void); -void m68k_op_move_32_al_ai(void); -void m68k_op_move_32_al_pi(void); -void m68k_op_move_32_al_pd(void); -void m68k_op_move_32_al_di(void); -void m68k_op_move_32_al_ix(void); -void m68k_op_move_32_al_aw(void); -void m68k_op_move_32_al_al(void); -void m68k_op_move_32_al_pcdi(void); -void m68k_op_move_32_al_pcix(void); -void m68k_op_move_32_al_i(void); -void m68k_op_movea_16_d(void); -void m68k_op_movea_16_a(void); -void m68k_op_movea_16_ai(void); -void m68k_op_movea_16_pi(void); -void m68k_op_movea_16_pd(void); -void m68k_op_movea_16_di(void); -void m68k_op_movea_16_ix(void); -void m68k_op_movea_16_aw(void); -void m68k_op_movea_16_al(void); -void m68k_op_movea_16_pcdi(void); -void m68k_op_movea_16_pcix(void); -void m68k_op_movea_16_i(void); -void m68k_op_movea_32_d(void); -void m68k_op_movea_32_a(void); -void m68k_op_movea_32_ai(void); -void m68k_op_movea_32_pi(void); -void m68k_op_movea_32_pd(void); -void m68k_op_movea_32_di(void); -void m68k_op_movea_32_ix(void); -void m68k_op_movea_32_aw(void); -void m68k_op_movea_32_al(void); -void m68k_op_movea_32_pcdi(void); -void m68k_op_movea_32_pcix(void); -void m68k_op_movea_32_i(void); -void m68k_op_move_16_frc_d(void); -void m68k_op_move_16_frc_ai(void); -void m68k_op_move_16_frc_pi(void); -void m68k_op_move_16_frc_pd(void); -void m68k_op_move_16_frc_di(void); -void m68k_op_move_16_frc_ix(void); -void m68k_op_move_16_frc_aw(void); -void m68k_op_move_16_frc_al(void); -void m68k_op_move_16_toc_d(void); -void m68k_op_move_16_toc_ai(void); -void m68k_op_move_16_toc_pi(void); -void m68k_op_move_16_toc_pd(void); -void m68k_op_move_16_toc_di(void); -void m68k_op_move_16_toc_ix(void); -void m68k_op_move_16_toc_aw(void); -void m68k_op_move_16_toc_al(void); -void m68k_op_move_16_toc_pcdi(void); -void m68k_op_move_16_toc_pcix(void); -void m68k_op_move_16_toc_i(void); -void m68k_op_move_16_frs_d(void); -void m68k_op_move_16_frs_ai(void); -void m68k_op_move_16_frs_pi(void); -void m68k_op_move_16_frs_pd(void); -void m68k_op_move_16_frs_di(void); -void m68k_op_move_16_frs_ix(void); -void m68k_op_move_16_frs_aw(void); -void m68k_op_move_16_frs_al(void); -void m68k_op_move_16_tos_d(void); -void m68k_op_move_16_tos_ai(void); -void m68k_op_move_16_tos_pi(void); -void m68k_op_move_16_tos_pd(void); -void m68k_op_move_16_tos_di(void); -void m68k_op_move_16_tos_ix(void); -void m68k_op_move_16_tos_aw(void); -void m68k_op_move_16_tos_al(void); -void m68k_op_move_16_tos_pcdi(void); -void m68k_op_move_16_tos_pcix(void); -void m68k_op_move_16_tos_i(void); -void m68k_op_move_32_fru(void); -void m68k_op_move_32_tou(void); -void m68k_op_movec_32_cr(void); -void m68k_op_movec_32_rc(void); -void m68k_op_movem_16_re_pd(void); -void m68k_op_movem_16_re_ai(void); -void m68k_op_movem_16_re_di(void); -void m68k_op_movem_16_re_ix(void); -void m68k_op_movem_16_re_aw(void); -void m68k_op_movem_16_re_al(void); -void m68k_op_movem_32_re_pd(void); -void m68k_op_movem_32_re_ai(void); -void m68k_op_movem_32_re_di(void); -void m68k_op_movem_32_re_ix(void); -void m68k_op_movem_32_re_aw(void); -void m68k_op_movem_32_re_al(void); -void m68k_op_movem_16_er_pi(void); -void m68k_op_movem_16_er_pcdi(void); -void m68k_op_movem_16_er_pcix(void); -void m68k_op_movem_16_er_ai(void); -void m68k_op_movem_16_er_di(void); -void m68k_op_movem_16_er_ix(void); -void m68k_op_movem_16_er_aw(void); -void m68k_op_movem_16_er_al(void); -void m68k_op_movem_32_er_pi(void); -void m68k_op_movem_32_er_pcdi(void); -void m68k_op_movem_32_er_pcix(void); -void m68k_op_movem_32_er_ai(void); -void m68k_op_movem_32_er_di(void); -void m68k_op_movem_32_er_ix(void); -void m68k_op_movem_32_er_aw(void); -void m68k_op_movem_32_er_al(void); -void m68k_op_movep_16_re(void); -void m68k_op_movep_32_re(void); -void m68k_op_movep_16_er(void); -void m68k_op_movep_32_er(void); -void m68k_op_moves_8_ai(void); -void m68k_op_moves_8_pi(void); -void m68k_op_moves_8_pi7(void); -void m68k_op_moves_8_pd(void); -void m68k_op_moves_8_pd7(void); -void m68k_op_moves_8_di(void); -void m68k_op_moves_8_ix(void); -void m68k_op_moves_8_aw(void); -void m68k_op_moves_8_al(void); -void m68k_op_moves_16_ai(void); -void m68k_op_moves_16_pi(void); -void m68k_op_moves_16_pd(void); -void m68k_op_moves_16_di(void); -void m68k_op_moves_16_ix(void); -void m68k_op_moves_16_aw(void); -void m68k_op_moves_16_al(void); -void m68k_op_moves_32_ai(void); -void m68k_op_moves_32_pi(void); -void m68k_op_moves_32_pd(void); -void m68k_op_moves_32_di(void); -void m68k_op_moves_32_ix(void); -void m68k_op_moves_32_aw(void); -void m68k_op_moves_32_al(void); -void m68k_op_moveq_32(void); -void m68k_op_muls_16_d(void); -void m68k_op_muls_16_ai(void); -void m68k_op_muls_16_pi(void); -void m68k_op_muls_16_pd(void); -void m68k_op_muls_16_di(void); -void m68k_op_muls_16_ix(void); -void m68k_op_muls_16_aw(void); -void m68k_op_muls_16_al(void); -void m68k_op_muls_16_pcdi(void); -void m68k_op_muls_16_pcix(void); -void m68k_op_muls_16_i(void); -void m68k_op_mulu_16_d(void); -void m68k_op_mulu_16_ai(void); -void m68k_op_mulu_16_pi(void); -void m68k_op_mulu_16_pd(void); -void m68k_op_mulu_16_di(void); -void m68k_op_mulu_16_ix(void); -void m68k_op_mulu_16_aw(void); -void m68k_op_mulu_16_al(void); -void m68k_op_mulu_16_pcdi(void); -void m68k_op_mulu_16_pcix(void); -void m68k_op_mulu_16_i(void); -void m68k_op_mull_32_d(void); -void m68k_op_mull_32_ai(void); -void m68k_op_mull_32_pi(void); -void m68k_op_mull_32_pd(void); -void m68k_op_mull_32_di(void); -void m68k_op_mull_32_ix(void); -void m68k_op_mull_32_aw(void); -void m68k_op_mull_32_al(void); -void m68k_op_mull_32_pcdi(void); -void m68k_op_mull_32_pcix(void); -void m68k_op_mull_32_i(void); -void m68k_op_nbcd_8_d(void); -void m68k_op_nbcd_8_ai(void); -void m68k_op_nbcd_8_pi(void); -void m68k_op_nbcd_8_pi7(void); -void m68k_op_nbcd_8_pd(void); -void m68k_op_nbcd_8_pd7(void); -void m68k_op_nbcd_8_di(void); -void m68k_op_nbcd_8_ix(void); -void m68k_op_nbcd_8_aw(void); -void m68k_op_nbcd_8_al(void); -void m68k_op_neg_8_d(void); -void m68k_op_neg_8_ai(void); -void m68k_op_neg_8_pi(void); -void m68k_op_neg_8_pi7(void); -void m68k_op_neg_8_pd(void); -void m68k_op_neg_8_pd7(void); -void m68k_op_neg_8_di(void); -void m68k_op_neg_8_ix(void); -void m68k_op_neg_8_aw(void); -void m68k_op_neg_8_al(void); -void m68k_op_neg_16_d(void); -void m68k_op_neg_16_ai(void); -void m68k_op_neg_16_pi(void); -void m68k_op_neg_16_pd(void); -void m68k_op_neg_16_di(void); -void m68k_op_neg_16_ix(void); -void m68k_op_neg_16_aw(void); -void m68k_op_neg_16_al(void); -void m68k_op_neg_32_d(void); -void m68k_op_neg_32_ai(void); -void m68k_op_neg_32_pi(void); -void m68k_op_neg_32_pd(void); -void m68k_op_neg_32_di(void); -void m68k_op_neg_32_ix(void); -void m68k_op_neg_32_aw(void); -void m68k_op_neg_32_al(void); -void m68k_op_negx_8_d(void); -void m68k_op_negx_8_ai(void); -void m68k_op_negx_8_pi(void); -void m68k_op_negx_8_pi7(void); -void m68k_op_negx_8_pd(void); -void m68k_op_negx_8_pd7(void); -void m68k_op_negx_8_di(void); -void m68k_op_negx_8_ix(void); -void m68k_op_negx_8_aw(void); -void m68k_op_negx_8_al(void); -void m68k_op_negx_16_d(void); -void m68k_op_negx_16_ai(void); -void m68k_op_negx_16_pi(void); -void m68k_op_negx_16_pd(void); -void m68k_op_negx_16_di(void); -void m68k_op_negx_16_ix(void); -void m68k_op_negx_16_aw(void); -void m68k_op_negx_16_al(void); -void m68k_op_negx_32_d(void); -void m68k_op_negx_32_ai(void); -void m68k_op_negx_32_pi(void); -void m68k_op_negx_32_pd(void); -void m68k_op_negx_32_di(void); -void m68k_op_negx_32_ix(void); -void m68k_op_negx_32_aw(void); -void m68k_op_negx_32_al(void); -void m68k_op_nop(void); -void m68k_op_not_8_d(void); -void m68k_op_not_8_ai(void); -void m68k_op_not_8_pi(void); -void m68k_op_not_8_pi7(void); -void m68k_op_not_8_pd(void); -void m68k_op_not_8_pd7(void); -void m68k_op_not_8_di(void); -void m68k_op_not_8_ix(void); -void m68k_op_not_8_aw(void); -void m68k_op_not_8_al(void); -void m68k_op_not_16_d(void); -void m68k_op_not_16_ai(void); -void m68k_op_not_16_pi(void); -void m68k_op_not_16_pd(void); -void m68k_op_not_16_di(void); -void m68k_op_not_16_ix(void); -void m68k_op_not_16_aw(void); -void m68k_op_not_16_al(void); -void m68k_op_not_32_d(void); -void m68k_op_not_32_ai(void); -void m68k_op_not_32_pi(void); -void m68k_op_not_32_pd(void); -void m68k_op_not_32_di(void); -void m68k_op_not_32_ix(void); -void m68k_op_not_32_aw(void); -void m68k_op_not_32_al(void); -void m68k_op_or_8_er_d(void); -void m68k_op_or_8_er_ai(void); -void m68k_op_or_8_er_pi(void); -void m68k_op_or_8_er_pi7(void); -void m68k_op_or_8_er_pd(void); -void m68k_op_or_8_er_pd7(void); -void m68k_op_or_8_er_di(void); -void m68k_op_or_8_er_ix(void); -void m68k_op_or_8_er_aw(void); -void m68k_op_or_8_er_al(void); -void m68k_op_or_8_er_pcdi(void); -void m68k_op_or_8_er_pcix(void); -void m68k_op_or_8_er_i(void); -void m68k_op_or_16_er_d(void); -void m68k_op_or_16_er_ai(void); -void m68k_op_or_16_er_pi(void); -void m68k_op_or_16_er_pd(void); -void m68k_op_or_16_er_di(void); -void m68k_op_or_16_er_ix(void); -void m68k_op_or_16_er_aw(void); -void m68k_op_or_16_er_al(void); -void m68k_op_or_16_er_pcdi(void); -void m68k_op_or_16_er_pcix(void); -void m68k_op_or_16_er_i(void); -void m68k_op_or_32_er_d(void); -void m68k_op_or_32_er_ai(void); -void m68k_op_or_32_er_pi(void); -void m68k_op_or_32_er_pd(void); -void m68k_op_or_32_er_di(void); -void m68k_op_or_32_er_ix(void); -void m68k_op_or_32_er_aw(void); -void m68k_op_or_32_er_al(void); -void m68k_op_or_32_er_pcdi(void); -void m68k_op_or_32_er_pcix(void); -void m68k_op_or_32_er_i(void); -void m68k_op_or_8_re_ai(void); -void m68k_op_or_8_re_pi(void); -void m68k_op_or_8_re_pi7(void); -void m68k_op_or_8_re_pd(void); -void m68k_op_or_8_re_pd7(void); -void m68k_op_or_8_re_di(void); -void m68k_op_or_8_re_ix(void); -void m68k_op_or_8_re_aw(void); -void m68k_op_or_8_re_al(void); -void m68k_op_or_16_re_ai(void); -void m68k_op_or_16_re_pi(void); -void m68k_op_or_16_re_pd(void); -void m68k_op_or_16_re_di(void); -void m68k_op_or_16_re_ix(void); -void m68k_op_or_16_re_aw(void); -void m68k_op_or_16_re_al(void); -void m68k_op_or_32_re_ai(void); -void m68k_op_or_32_re_pi(void); -void m68k_op_or_32_re_pd(void); -void m68k_op_or_32_re_di(void); -void m68k_op_or_32_re_ix(void); -void m68k_op_or_32_re_aw(void); -void m68k_op_or_32_re_al(void); -void m68k_op_ori_8_d(void); -void m68k_op_ori_8_ai(void); -void m68k_op_ori_8_pi(void); -void m68k_op_ori_8_pi7(void); -void m68k_op_ori_8_pd(void); -void m68k_op_ori_8_pd7(void); -void m68k_op_ori_8_di(void); -void m68k_op_ori_8_ix(void); -void m68k_op_ori_8_aw(void); -void m68k_op_ori_8_al(void); -void m68k_op_ori_16_d(void); -void m68k_op_ori_16_ai(void); -void m68k_op_ori_16_pi(void); -void m68k_op_ori_16_pd(void); -void m68k_op_ori_16_di(void); -void m68k_op_ori_16_ix(void); -void m68k_op_ori_16_aw(void); -void m68k_op_ori_16_al(void); -void m68k_op_ori_32_d(void); -void m68k_op_ori_32_ai(void); -void m68k_op_ori_32_pi(void); -void m68k_op_ori_32_pd(void); -void m68k_op_ori_32_di(void); -void m68k_op_ori_32_ix(void); -void m68k_op_ori_32_aw(void); -void m68k_op_ori_32_al(void); -void m68k_op_ori_16_toc(void); -void m68k_op_ori_16_tos(void); -void m68k_op_pack_16_rr(void); -void m68k_op_pack_16_mm_ax7(void); -void m68k_op_pack_16_mm_ay7(void); -void m68k_op_pack_16_mm_axy7(void); -void m68k_op_pack_16_mm(void); -void m68k_op_pea_32_ai(void); -void m68k_op_pea_32_di(void); -void m68k_op_pea_32_ix(void); -void m68k_op_pea_32_aw(void); -void m68k_op_pea_32_al(void); -void m68k_op_pea_32_pcdi(void); -void m68k_op_pea_32_pcix(void); -void m68k_op_reset(void); -void m68k_op_ror_8_s(void); -void m68k_op_ror_16_s(void); -void m68k_op_ror_32_s(void); -void m68k_op_ror_8_r(void); -void m68k_op_ror_16_r(void); -void m68k_op_ror_32_r(void); -void m68k_op_ror_16_ai(void); -void m68k_op_ror_16_pi(void); -void m68k_op_ror_16_pd(void); -void m68k_op_ror_16_di(void); -void m68k_op_ror_16_ix(void); -void m68k_op_ror_16_aw(void); -void m68k_op_ror_16_al(void); -void m68k_op_rol_8_s(void); -void m68k_op_rol_16_s(void); -void m68k_op_rol_32_s(void); -void m68k_op_rol_8_r(void); -void m68k_op_rol_16_r(void); -void m68k_op_rol_32_r(void); -void m68k_op_rol_16_ai(void); -void m68k_op_rol_16_pi(void); -void m68k_op_rol_16_pd(void); -void m68k_op_rol_16_di(void); -void m68k_op_rol_16_ix(void); -void m68k_op_rol_16_aw(void); -void m68k_op_rol_16_al(void); -void m68k_op_roxr_8_s(void); -void m68k_op_roxr_16_s(void); -void m68k_op_roxr_32_s(void); -void m68k_op_roxr_8_r(void); -void m68k_op_roxr_16_r(void); -void m68k_op_roxr_32_r(void); -void m68k_op_roxr_16_ai(void); -void m68k_op_roxr_16_pi(void); -void m68k_op_roxr_16_pd(void); -void m68k_op_roxr_16_di(void); -void m68k_op_roxr_16_ix(void); -void m68k_op_roxr_16_aw(void); -void m68k_op_roxr_16_al(void); -void m68k_op_roxl_8_s(void); -void m68k_op_roxl_16_s(void); -void m68k_op_roxl_32_s(void); -void m68k_op_roxl_8_r(void); -void m68k_op_roxl_16_r(void); -void m68k_op_roxl_32_r(void); -void m68k_op_roxl_16_ai(void); -void m68k_op_roxl_16_pi(void); -void m68k_op_roxl_16_pd(void); -void m68k_op_roxl_16_di(void); -void m68k_op_roxl_16_ix(void); -void m68k_op_roxl_16_aw(void); -void m68k_op_roxl_16_al(void); -void m68k_op_rtd_32(void); -void m68k_op_rte_32(void); -void m68k_op_rtm_32(void); -void m68k_op_rtr_32(void); -void m68k_op_rts_32(void); -void m68k_op_sbcd_8_rr(void); -void m68k_op_sbcd_8_mm_ax7(void); -void m68k_op_sbcd_8_mm_ay7(void); -void m68k_op_sbcd_8_mm_axy7(void); -void m68k_op_sbcd_8_mm(void); -void m68k_op_st_8_d(void); -void m68k_op_st_8_ai(void); -void m68k_op_st_8_pi(void); -void m68k_op_st_8_pi7(void); -void m68k_op_st_8_pd(void); -void m68k_op_st_8_pd7(void); -void m68k_op_st_8_di(void); -void m68k_op_st_8_ix(void); -void m68k_op_st_8_aw(void); -void m68k_op_st_8_al(void); -void m68k_op_sf_8_d(void); -void m68k_op_sf_8_ai(void); -void m68k_op_sf_8_pi(void); -void m68k_op_sf_8_pi7(void); -void m68k_op_sf_8_pd(void); -void m68k_op_sf_8_pd7(void); -void m68k_op_sf_8_di(void); -void m68k_op_sf_8_ix(void); -void m68k_op_sf_8_aw(void); -void m68k_op_sf_8_al(void); -void m68k_op_shi_8_d(void); -void m68k_op_sls_8_d(void); -void m68k_op_scc_8_d(void); -void m68k_op_scs_8_d(void); -void m68k_op_sne_8_d(void); -void m68k_op_seq_8_d(void); -void m68k_op_svc_8_d(void); -void m68k_op_svs_8_d(void); -void m68k_op_spl_8_d(void); -void m68k_op_smi_8_d(void); -void m68k_op_sge_8_d(void); -void m68k_op_slt_8_d(void); -void m68k_op_sgt_8_d(void); -void m68k_op_sle_8_d(void); -void m68k_op_shi_8_ai(void); -void m68k_op_shi_8_pi(void); -void m68k_op_shi_8_pi7(void); -void m68k_op_shi_8_pd(void); -void m68k_op_shi_8_pd7(void); -void m68k_op_shi_8_di(void); -void m68k_op_shi_8_ix(void); -void m68k_op_shi_8_aw(void); -void m68k_op_shi_8_al(void); -void m68k_op_sls_8_ai(void); -void m68k_op_sls_8_pi(void); -void m68k_op_sls_8_pi7(void); -void m68k_op_sls_8_pd(void); -void m68k_op_sls_8_pd7(void); -void m68k_op_sls_8_di(void); -void m68k_op_sls_8_ix(void); -void m68k_op_sls_8_aw(void); -void m68k_op_sls_8_al(void); -void m68k_op_scc_8_ai(void); -void m68k_op_scc_8_pi(void); -void m68k_op_scc_8_pi7(void); -void m68k_op_scc_8_pd(void); -void m68k_op_scc_8_pd7(void); -void m68k_op_scc_8_di(void); -void m68k_op_scc_8_ix(void); -void m68k_op_scc_8_aw(void); -void m68k_op_scc_8_al(void); -void m68k_op_scs_8_ai(void); -void m68k_op_scs_8_pi(void); -void m68k_op_scs_8_pi7(void); -void m68k_op_scs_8_pd(void); -void m68k_op_scs_8_pd7(void); -void m68k_op_scs_8_di(void); -void m68k_op_scs_8_ix(void); -void m68k_op_scs_8_aw(void); -void m68k_op_scs_8_al(void); -void m68k_op_sne_8_ai(void); -void m68k_op_sne_8_pi(void); -void m68k_op_sne_8_pi7(void); -void m68k_op_sne_8_pd(void); -void m68k_op_sne_8_pd7(void); -void m68k_op_sne_8_di(void); -void m68k_op_sne_8_ix(void); -void m68k_op_sne_8_aw(void); -void m68k_op_sne_8_al(void); -void m68k_op_seq_8_ai(void); -void m68k_op_seq_8_pi(void); -void m68k_op_seq_8_pi7(void); -void m68k_op_seq_8_pd(void); -void m68k_op_seq_8_pd7(void); -void m68k_op_seq_8_di(void); -void m68k_op_seq_8_ix(void); -void m68k_op_seq_8_aw(void); -void m68k_op_seq_8_al(void); -void m68k_op_svc_8_ai(void); -void m68k_op_svc_8_pi(void); -void m68k_op_svc_8_pi7(void); -void m68k_op_svc_8_pd(void); -void m68k_op_svc_8_pd7(void); -void m68k_op_svc_8_di(void); -void m68k_op_svc_8_ix(void); -void m68k_op_svc_8_aw(void); -void m68k_op_svc_8_al(void); -void m68k_op_svs_8_ai(void); -void m68k_op_svs_8_pi(void); -void m68k_op_svs_8_pi7(void); -void m68k_op_svs_8_pd(void); -void m68k_op_svs_8_pd7(void); -void m68k_op_svs_8_di(void); -void m68k_op_svs_8_ix(void); -void m68k_op_svs_8_aw(void); -void m68k_op_svs_8_al(void); -void m68k_op_spl_8_ai(void); -void m68k_op_spl_8_pi(void); -void m68k_op_spl_8_pi7(void); -void m68k_op_spl_8_pd(void); -void m68k_op_spl_8_pd7(void); -void m68k_op_spl_8_di(void); -void m68k_op_spl_8_ix(void); -void m68k_op_spl_8_aw(void); -void m68k_op_spl_8_al(void); -void m68k_op_smi_8_ai(void); -void m68k_op_smi_8_pi(void); -void m68k_op_smi_8_pi7(void); -void m68k_op_smi_8_pd(void); -void m68k_op_smi_8_pd7(void); -void m68k_op_smi_8_di(void); -void m68k_op_smi_8_ix(void); -void m68k_op_smi_8_aw(void); -void m68k_op_smi_8_al(void); -void m68k_op_sge_8_ai(void); -void m68k_op_sge_8_pi(void); -void m68k_op_sge_8_pi7(void); -void m68k_op_sge_8_pd(void); -void m68k_op_sge_8_pd7(void); -void m68k_op_sge_8_di(void); -void m68k_op_sge_8_ix(void); -void m68k_op_sge_8_aw(void); -void m68k_op_sge_8_al(void); -void m68k_op_slt_8_ai(void); -void m68k_op_slt_8_pi(void); -void m68k_op_slt_8_pi7(void); -void m68k_op_slt_8_pd(void); -void m68k_op_slt_8_pd7(void); -void m68k_op_slt_8_di(void); -void m68k_op_slt_8_ix(void); -void m68k_op_slt_8_aw(void); -void m68k_op_slt_8_al(void); -void m68k_op_sgt_8_ai(void); -void m68k_op_sgt_8_pi(void); -void m68k_op_sgt_8_pi7(void); -void m68k_op_sgt_8_pd(void); -void m68k_op_sgt_8_pd7(void); -void m68k_op_sgt_8_di(void); -void m68k_op_sgt_8_ix(void); -void m68k_op_sgt_8_aw(void); -void m68k_op_sgt_8_al(void); -void m68k_op_sle_8_ai(void); -void m68k_op_sle_8_pi(void); -void m68k_op_sle_8_pi7(void); -void m68k_op_sle_8_pd(void); -void m68k_op_sle_8_pd7(void); -void m68k_op_sle_8_di(void); -void m68k_op_sle_8_ix(void); -void m68k_op_sle_8_aw(void); -void m68k_op_sle_8_al(void); -void m68k_op_stop(void); -void m68k_op_sub_8_er_d(void); -void m68k_op_sub_8_er_ai(void); -void m68k_op_sub_8_er_pi(void); -void m68k_op_sub_8_er_pi7(void); -void m68k_op_sub_8_er_pd(void); -void m68k_op_sub_8_er_pd7(void); -void m68k_op_sub_8_er_di(void); -void m68k_op_sub_8_er_ix(void); -void m68k_op_sub_8_er_aw(void); -void m68k_op_sub_8_er_al(void); -void m68k_op_sub_8_er_pcdi(void); -void m68k_op_sub_8_er_pcix(void); -void m68k_op_sub_8_er_i(void); -void m68k_op_sub_16_er_d(void); -void m68k_op_sub_16_er_a(void); -void m68k_op_sub_16_er_ai(void); -void m68k_op_sub_16_er_pi(void); -void m68k_op_sub_16_er_pd(void); -void m68k_op_sub_16_er_di(void); -void m68k_op_sub_16_er_ix(void); -void m68k_op_sub_16_er_aw(void); -void m68k_op_sub_16_er_al(void); -void m68k_op_sub_16_er_pcdi(void); -void m68k_op_sub_16_er_pcix(void); -void m68k_op_sub_16_er_i(void); -void m68k_op_sub_32_er_d(void); -void m68k_op_sub_32_er_a(void); -void m68k_op_sub_32_er_ai(void); -void m68k_op_sub_32_er_pi(void); -void m68k_op_sub_32_er_pd(void); -void m68k_op_sub_32_er_di(void); -void m68k_op_sub_32_er_ix(void); -void m68k_op_sub_32_er_aw(void); -void m68k_op_sub_32_er_al(void); -void m68k_op_sub_32_er_pcdi(void); -void m68k_op_sub_32_er_pcix(void); -void m68k_op_sub_32_er_i(void); -void m68k_op_sub_8_re_ai(void); -void m68k_op_sub_8_re_pi(void); -void m68k_op_sub_8_re_pi7(void); -void m68k_op_sub_8_re_pd(void); -void m68k_op_sub_8_re_pd7(void); -void m68k_op_sub_8_re_di(void); -void m68k_op_sub_8_re_ix(void); -void m68k_op_sub_8_re_aw(void); -void m68k_op_sub_8_re_al(void); -void m68k_op_sub_16_re_ai(void); -void m68k_op_sub_16_re_pi(void); -void m68k_op_sub_16_re_pd(void); -void m68k_op_sub_16_re_di(void); -void m68k_op_sub_16_re_ix(void); -void m68k_op_sub_16_re_aw(void); -void m68k_op_sub_16_re_al(void); -void m68k_op_sub_32_re_ai(void); -void m68k_op_sub_32_re_pi(void); -void m68k_op_sub_32_re_pd(void); -void m68k_op_sub_32_re_di(void); -void m68k_op_sub_32_re_ix(void); -void m68k_op_sub_32_re_aw(void); -void m68k_op_sub_32_re_al(void); -void m68k_op_suba_16_d(void); -void m68k_op_suba_16_a(void); -void m68k_op_suba_16_ai(void); -void m68k_op_suba_16_pi(void); -void m68k_op_suba_16_pd(void); -void m68k_op_suba_16_di(void); -void m68k_op_suba_16_ix(void); -void m68k_op_suba_16_aw(void); -void m68k_op_suba_16_al(void); -void m68k_op_suba_16_pcdi(void); -void m68k_op_suba_16_pcix(void); -void m68k_op_suba_16_i(void); -void m68k_op_suba_32_d(void); -void m68k_op_suba_32_a(void); -void m68k_op_suba_32_ai(void); -void m68k_op_suba_32_pi(void); -void m68k_op_suba_32_pd(void); -void m68k_op_suba_32_di(void); -void m68k_op_suba_32_ix(void); -void m68k_op_suba_32_aw(void); -void m68k_op_suba_32_al(void); -void m68k_op_suba_32_pcdi(void); -void m68k_op_suba_32_pcix(void); -void m68k_op_suba_32_i(void); -void m68k_op_subi_8_d(void); -void m68k_op_subi_8_ai(void); -void m68k_op_subi_8_pi(void); -void m68k_op_subi_8_pi7(void); -void m68k_op_subi_8_pd(void); -void m68k_op_subi_8_pd7(void); -void m68k_op_subi_8_di(void); -void m68k_op_subi_8_ix(void); -void m68k_op_subi_8_aw(void); -void m68k_op_subi_8_al(void); -void m68k_op_subi_16_d(void); -void m68k_op_subi_16_ai(void); -void m68k_op_subi_16_pi(void); -void m68k_op_subi_16_pd(void); -void m68k_op_subi_16_di(void); -void m68k_op_subi_16_ix(void); -void m68k_op_subi_16_aw(void); -void m68k_op_subi_16_al(void); -void m68k_op_subi_32_d(void); -void m68k_op_subi_32_ai(void); -void m68k_op_subi_32_pi(void); -void m68k_op_subi_32_pd(void); -void m68k_op_subi_32_di(void); -void m68k_op_subi_32_ix(void); -void m68k_op_subi_32_aw(void); -void m68k_op_subi_32_al(void); -void m68k_op_subq_8_d(void); -void m68k_op_subq_8_ai(void); -void m68k_op_subq_8_pi(void); -void m68k_op_subq_8_pi7(void); -void m68k_op_subq_8_pd(void); -void m68k_op_subq_8_pd7(void); -void m68k_op_subq_8_di(void); -void m68k_op_subq_8_ix(void); -void m68k_op_subq_8_aw(void); -void m68k_op_subq_8_al(void); -void m68k_op_subq_16_d(void); -void m68k_op_subq_16_a(void); -void m68k_op_subq_16_ai(void); -void m68k_op_subq_16_pi(void); -void m68k_op_subq_16_pd(void); -void m68k_op_subq_16_di(void); -void m68k_op_subq_16_ix(void); -void m68k_op_subq_16_aw(void); -void m68k_op_subq_16_al(void); -void m68k_op_subq_32_d(void); -void m68k_op_subq_32_a(void); -void m68k_op_subq_32_ai(void); -void m68k_op_subq_32_pi(void); -void m68k_op_subq_32_pd(void); -void m68k_op_subq_32_di(void); -void m68k_op_subq_32_ix(void); -void m68k_op_subq_32_aw(void); -void m68k_op_subq_32_al(void); -void m68k_op_subx_8_rr(void); -void m68k_op_subx_16_rr(void); -void m68k_op_subx_32_rr(void); -void m68k_op_subx_8_mm_ax7(void); -void m68k_op_subx_8_mm_ay7(void); -void m68k_op_subx_8_mm_axy7(void); -void m68k_op_subx_8_mm(void); -void m68k_op_subx_16_mm(void); -void m68k_op_subx_32_mm(void); -void m68k_op_swap_32(void); -void m68k_op_tas_8_d(void); -void m68k_op_tas_8_ai(void); -void m68k_op_tas_8_pi(void); -void m68k_op_tas_8_pi7(void); -void m68k_op_tas_8_pd(void); -void m68k_op_tas_8_pd7(void); -void m68k_op_tas_8_di(void); -void m68k_op_tas_8_ix(void); -void m68k_op_tas_8_aw(void); -void m68k_op_tas_8_al(void); -void m68k_op_trap(void); -void m68k_op_trapt(void); -void m68k_op_trapt_16(void); -void m68k_op_trapt_32(void); -void m68k_op_trapf(void); -void m68k_op_trapf_16(void); -void m68k_op_trapf_32(void); -void m68k_op_traphi(void); -void m68k_op_trapls(void); -void m68k_op_trapcc(void); -void m68k_op_trapcs(void); -void m68k_op_trapne(void); -void m68k_op_trapeq(void); -void m68k_op_trapvc(void); -void m68k_op_trapvs(void); -void m68k_op_trappl(void); -void m68k_op_trapmi(void); -void m68k_op_trapge(void); -void m68k_op_traplt(void); -void m68k_op_trapgt(void); -void m68k_op_traple(void); -void m68k_op_traphi_16(void); -void m68k_op_trapls_16(void); -void m68k_op_trapcc_16(void); -void m68k_op_trapcs_16(void); -void m68k_op_trapne_16(void); -void m68k_op_trapeq_16(void); -void m68k_op_trapvc_16(void); -void m68k_op_trapvs_16(void); -void m68k_op_trappl_16(void); -void m68k_op_trapmi_16(void); -void m68k_op_trapge_16(void); -void m68k_op_traplt_16(void); -void m68k_op_trapgt_16(void); -void m68k_op_traple_16(void); -void m68k_op_traphi_32(void); -void m68k_op_trapls_32(void); -void m68k_op_trapcc_32(void); -void m68k_op_trapcs_32(void); -void m68k_op_trapne_32(void); -void m68k_op_trapeq_32(void); -void m68k_op_trapvc_32(void); -void m68k_op_trapvs_32(void); -void m68k_op_trappl_32(void); -void m68k_op_trapmi_32(void); -void m68k_op_trapge_32(void); -void m68k_op_traplt_32(void); -void m68k_op_trapgt_32(void); -void m68k_op_traple_32(void); -void m68k_op_trapv(void); -void m68k_op_tst_8_d(void); -void m68k_op_tst_8_ai(void); -void m68k_op_tst_8_pi(void); -void m68k_op_tst_8_pi7(void); -void m68k_op_tst_8_pd(void); -void m68k_op_tst_8_pd7(void); -void m68k_op_tst_8_di(void); -void m68k_op_tst_8_ix(void); -void m68k_op_tst_8_aw(void); -void m68k_op_tst_8_al(void); -void m68k_op_tst_8_pcdi(void); -void m68k_op_tst_8_pcix(void); -void m68k_op_tst_8_i(void); -void m68k_op_tst_16_d(void); -void m68k_op_tst_16_a(void); -void m68k_op_tst_16_ai(void); -void m68k_op_tst_16_pi(void); -void m68k_op_tst_16_pd(void); -void m68k_op_tst_16_di(void); -void m68k_op_tst_16_ix(void); -void m68k_op_tst_16_aw(void); -void m68k_op_tst_16_al(void); -void m68k_op_tst_16_pcdi(void); -void m68k_op_tst_16_pcix(void); -void m68k_op_tst_16_i(void); -void m68k_op_tst_32_d(void); -void m68k_op_tst_32_a(void); -void m68k_op_tst_32_ai(void); -void m68k_op_tst_32_pi(void); -void m68k_op_tst_32_pd(void); -void m68k_op_tst_32_di(void); -void m68k_op_tst_32_ix(void); -void m68k_op_tst_32_aw(void); -void m68k_op_tst_32_al(void); -void m68k_op_tst_32_pcdi(void); -void m68k_op_tst_32_pcix(void); -void m68k_op_tst_32_i(void); -void m68k_op_unlk_32_a7(void); -void m68k_op_unlk_32(void); -void m68k_op_unpk_16_rr(void); -void m68k_op_unpk_16_mm_ax7(void); -void m68k_op_unpk_16_mm_ay7(void); -void m68k_op_unpk_16_mm_axy7(void); -void m68k_op_unpk_16_mm(void); -/* Build the opcode handler table */ -void m68ki_build_opcode_table(void); - -extern void (*m68ki_instruction_jump_table[0x10000])(void); /* opcode handler jump table */ -extern unsigned char m68ki_cycles[][0x10000]; - - -/* ======================================================================== */ -/* ============================== END OF FILE ============================= */ -/* ======================================================================== */ - -#endif /* M68KOPS__HEADER */ - - diff --git a/Frameworks/AudioOverload/aosdk/eng_ssf/sat_hw.c b/Frameworks/AudioOverload/aosdk/eng_ssf/sat_hw.c deleted file mode 100644 index bc8805493..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_ssf/sat_hw.c +++ /dev/null @@ -1,170 +0,0 @@ -/* - sat_hw.c - Saturn sound hardware glue/emulation/whatever - - supported: main RAM (512 KB) - SCSP + timers - MC68000 CPU - - Copyright (c) 2007, R. Belmont and Richard Bannister. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - * Neither the names of R. Belmont and Richard Bannister nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#include - -#include "ao.h" -#include "scsp.h" -#include "sat_hw.h" -#include "m68k.h" - -uint8 sat_ram[512*1024]; - -static void scsp_irq(int irq) -{ - if (irq > 0) - { - m68k_set_irq(irq); - } -} - -#define MIXER_PAN_LEFT 1 -#define MIXER_PAN_RIGHT 2 -#define MIXER(level,pan) ((level & 0xff) | ((pan & 0x03) << 8)) -#define YM3012_VOL(LVol,LPan,RVol,RPan) (MIXER(LVol,LPan)|(MIXER(RVol,RPan) << 16)) - -static struct SCSPinterface scsp_interface = -{ - 1, - { sat_ram, }, - { YM3012_VOL(100, MIXER_PAN_LEFT, 100, MIXER_PAN_RIGHT) }, - { scsp_irq, }, -}; - -void sat_hw_init(void) -{ - m68k_init(); - m68k_set_cpu_type(M68K_CPU_TYPE_68000); - m68k_pulse_reset(); - - scsp_interface.region[0] = sat_ram; - scsp_start(&scsp_interface); -} - -/* M68k memory handlers */ - -unsigned int m68k_read_memory_8(unsigned int address) -{ - if (address < (512*1024)) - return sat_ram[address^1]; - - if (address >= 0x100000 && address < 0x100c00) - { - int foo = SCSP_0_r((address - 0x100000)/2, 0); - - if (address & 1) - return foo & 0xff; - else - return foo>>8; - } - - printf("R8 @ %x\n", address); - return 0; -} - -unsigned int m68k_read_memory_16(unsigned int address) -{ - if (address < (512*1024)) - { - return mem_readword_swap((unsigned short *)(sat_ram+address)); - } - - if (address >= 0x100000 && address < 0x100c00) - return SCSP_0_r((address-0x100000)/2, 0); - - printf("R16 @ %x\n", address); - return 0; -} - -unsigned int m68k_read_memory_32(unsigned int address) -{ - if (address < 0x80000) - { - return sat_ram[address+2] | sat_ram[address+3]<<8 | sat_ram[address]<<16 | sat_ram[address+1]<<24; - } - - printf("R32 @ %x\n", address); - return 0; -} - -void m68k_write_memory_8(unsigned int address, unsigned int data) -{ - if (address < 0x80000) - { - sat_ram[address^1] = data; - return; - } - - if (address >= 0x100000 && address < 0x100c00) - { - address -= 0x100000; - if (address & 1) - SCSP_0_w(address>>1, data, 0xff00); - else - SCSP_0_w(address>>1, data<<8, 0x00ff); - return; - } -} - -void m68k_write_memory_16(unsigned int address, unsigned int data) -{ - if (address < 0x80000) - { - sat_ram[address+1] = (data>>8)&0xff; - sat_ram[address] = data&0xff; - return; - } - - if (address >= 0x100000 && address < 0x100c00) - { - SCSP_0_w((address-0x100000)>>1, data, 0x0000); - return; - } -} - -void m68k_write_memory_32(unsigned int address, unsigned int data) -{ - if (address < 0x80000) - { - sat_ram[address+1] = (data>>24)&0xff; - sat_ram[address] = (data>>16)&0xff; - sat_ram[address+3] = (data>>8)&0xff; - sat_ram[address+2] = data&0xff; - return; - } - - if (address >= 0x100000 && address < 0x100c00) - { - address -= 0x100000; - SCSP_0_w(address>>1, data>>16, 0x0000); - SCSP_0_w((address>>1)+1, data&0xffff, 0x0000); - return; - } -} diff --git a/Frameworks/AudioOverload/aosdk/eng_ssf/sat_hw.h b/Frameworks/AudioOverload/aosdk/eng_ssf/sat_hw.h deleted file mode 100644 index 1f275842f..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_ssf/sat_hw.h +++ /dev/null @@ -1,35 +0,0 @@ -#ifndef _SAT_HW_H_ -#define _SAT_HW_H_ - -extern uint8 sat_ram[512*1024]; - -void sat_hw_init(void); - -#if !LSB_FIRST -static unsigned short INLINE mem_readword_swap(unsigned short *addr) -{ - return ((*addr&0x00ff)<<8)|((*addr&0xff00)>>8); -} - -static void INLINE mem_writeword_swap(unsigned short *addr, unsigned short value) -{ - *addr = ((value&0x00ff)<<8)|((value&0xff00)>>8); -} -#else // big endian -static unsigned short INLINE mem_readword_swap(unsigned short *addr) -{ - unsigned long retval; - - retval = *addr; - - return retval; -} - -static void INLINE mem_writeword_swap(unsigned short *addr, unsigned short value) -{ - *addr = value; -} -#endif - - -#endif diff --git a/Frameworks/AudioOverload/aosdk/eng_ssf/scsp.c b/Frameworks/AudioOverload/aosdk/eng_ssf/scsp.c deleted file mode 100644 index f1e695301..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_ssf/scsp.c +++ /dev/null @@ -1,1276 +0,0 @@ -/* - Sega/Yamaha YMF292-F (SCSP = Saturn Custom Sound Processor) emulation - By ElSemi - MAME/M1 conversion and cleanup by R. Belmont - Additional code and bugfixes by kingshriek - - This chip has 32 voices. Each voice can play a sample or be part of - an FM construct. Unlike traditional Yamaha FM chips, the base waveform - for the FM still comes from the wavetable RAM. - - ChangeLog: - * November 25, 2003 (ES) Fixed buggy timers and envelope overflows. - (RB) Improved sample rates other than 44100, multiple - chips now works properly. - * December 02, 2003 (ES) Added DISDL register support, improves mix. - * April 28, 2004 (ES) Corrected envelope rates, added key-rate scaling, - added ringbuffer support. - * January 8, 2005 (RB) Added ability to specify region offset for RAM. - * January 26, 2007 (ES) Added on-board DSP capability - * December 16, 2007 (kingshriek) Many EG bug fixes, implemented effects mixer, - implemented FM. -*/ - -#include -#include -#include "ao.h" -#include "cpuintrf.h" -#include "scsp.h" -#include "scspdsp.h" -#include "sat_hw.h" - -#define ICLIP16(x) (x<-32768)?-32768:((x>32767)?32767:x) - -#define SHIFT 12 -#define FIX(v) ((UINT32) ((float) (1<udata.data[0x0]>>0x0)&0x1000) -#define KEYONB(slot) ((slot->udata.data[0x0]>>0x0)&0x0800) -#define SBCTL(slot) ((slot->udata.data[0x0]>>0x9)&0x0003) -#define SSCTL(slot) ((slot->udata.data[0x0]>>0x7)&0x0003) -#define LPCTL(slot) ((slot->udata.data[0x0]>>0x5)&0x0003) -#define PCM8B(slot) ((slot->udata.data[0x0]>>0x0)&0x0010) - -#define SA(slot) (((slot->udata.data[0x0]&0xF)<<16)|(slot->udata.data[0x1])) - -#define LSA(slot) (slot->udata.data[0x2]) - -#define LEA(slot) (slot->udata.data[0x3]) - -#define D2R(slot) ((slot->udata.data[0x4]>>0xB)&0x001F) -#define D1R(slot) ((slot->udata.data[0x4]>>0x6)&0x001F) -#define EGHOLD(slot) ((slot->udata.data[0x4]>>0x0)&0x0020) -#define AR(slot) ((slot->udata.data[0x4]>>0x0)&0x001F) - -#define LPSLNK(slot) ((slot->udata.data[0x5]>>0x0)&0x4000) -#define KRS(slot) ((slot->udata.data[0x5]>>0xA)&0x000F) -#define DL(slot) ((slot->udata.data[0x5]>>0x5)&0x001F) -#define RR(slot) ((slot->udata.data[0x5]>>0x0)&0x001F) - -#define STWINH(slot) ((slot->udata.data[0x6]>>0x0)&0x0200) -#define SDIR(slot) ((slot->udata.data[0x6]>>0x0)&0x0100) -#define TL(slot) ((slot->udata.data[0x6]>>0x0)&0x00FF) - -#define MDL(slot) ((slot->udata.data[0x7]>>0xC)&0x000F) -#define MDXSL(slot) ((slot->udata.data[0x7]>>0x6)&0x003F) -#define MDYSL(slot) ((slot->udata.data[0x7]>>0x0)&0x003F) - -#define OCT(slot) ((slot->udata.data[0x8]>>0xB)&0x000F) -#define FNS(slot) ((slot->udata.data[0x8]>>0x0)&0x03FF) - -#define LFORE(slot) ((slot->udata.data[0x9]>>0x0)&0x8000) -#define LFOF(slot) ((slot->udata.data[0x9]>>0xA)&0x001F) -#define PLFOWS(slot) ((slot->udata.data[0x9]>>0x8)&0x0003) -#define PLFOS(slot) ((slot->udata.data[0x9]>>0x5)&0x0007) -#define ALFOWS(slot) ((slot->udata.data[0x9]>>0x3)&0x0003) -#define ALFOS(slot) ((slot->udata.data[0x9]>>0x0)&0x0007) - -#define ISEL(slot) ((slot->udata.data[0xA]>>0x3)&0x000F) -#define IMXL(slot) ((slot->udata.data[0xA]>>0x0)&0x0007) - -#define DISDL(slot) ((slot->udata.data[0xB]>>0xD)&0x0007) -#define DIPAN(slot) ((slot->udata.data[0xB]>>0x8)&0x001F) -#define EFSDL(slot) ((slot->udata.data[0xB]>>0x5)&0x0007) -#define EFPAN(slot) ((slot->udata.data[0xB]>>0x0)&0x001F) - -//Envelope times in ms -static const double ARTimes[64]={100000/*infinity*/,100000/*infinity*/,8100.0,6900.0,6000.0,4800.0,4000.0,3400.0,3000.0,2400.0,2000.0,1700.0,1500.0, - 1200.0,1000.0,860.0,760.0,600.0,500.0,430.0,380.0,300.0,250.0,220.0,190.0,150.0,130.0,110.0,95.0, - 76.0,63.0,55.0,47.0,38.0,31.0,27.0,24.0,19.0,15.0,13.0,12.0,9.4,7.9,6.8,6.0,4.7,3.8,3.4,3.0,2.4, - 2.0,1.8,1.6,1.3,1.1,0.93,0.85,0.65,0.53,0.44,0.40,0.35,0.0,0.0}; -static const double DRTimes[64]={100000/*infinity*/,100000/*infinity*/,118200.0,101300.0,88600.0,70900.0,59100.0,50700.0,44300.0,35500.0,29600.0,25300.0,22200.0,17700.0, - 14800.0,12700.0,11100.0,8900.0,7400.0,6300.0,5500.0,4400.0,3700.0,3200.0,2800.0,2200.0,1800.0,1600.0,1400.0,1100.0, - 920.0,790.0,690.0,550.0,460.0,390.0,340.0,270.0,230.0,200.0,170.0,140.0,110.0,98.0,85.0,68.0,57.0,49.0,43.0,34.0, - 28.0,25.0,22.0,18.0,14.0,12.0,11.0,8.5,7.1,6.1,5.4,4.3,3.6,3.1}; -static UINT32 FNS_Table[0x400]; -static INT32 EG_TABLE[0x400]; - -typedef enum {ATTACK,DECAY1,DECAY2,RELEASE} _STATE; -struct _EG -{ - int volume; // - _STATE state; - int step; - //step vals - int AR; //Attack - int D1R; //Decay1 - int D2R; //Decay2 - int RR; //Release - - int DL; //Decay level - UINT8 EGHOLD; - UINT8 LPLINK; -}; - -struct _SLOT -{ - union - { - UINT16 data[0x10]; //only 0x1a bytes used - UINT8 datab[0x20]; - } udata; - UINT8 active; //this slot is currently playing - UINT8 *base; //samples base address - UINT32 cur_addr; //current play address (24.8) - UINT32 nxt_addr; //next play address - UINT32 step; //pitch step (24.8) - UINT8 Backwards; //the wave is playing backwards - struct _EG EG; //Envelope - struct _LFO PLFO; //Phase LFO - struct _LFO ALFO; //Amplitude LFO - int slot; - signed short Prev; //Previous sample (for interpolation) -}; - - -#define MEM4B(scsp) ((scsp->udata.data[0]>>0x0)&0x0200) -#define DAC18B(scsp) ((scsp->udata.data[0]>>0x0)&0x0100) -#define MVOL(scsp) ((scsp->udata.data[0]>>0x0)&0x000F) -#define RBL(scsp) ((scsp->udata.data[1]>>0x7)&0x0003) -#define RBP(scsp) ((scsp->udata.data[1]>>0x0)&0x003F) -#define MOFULL(scsp) ((scsp->udata.data[2]>>0x0)&0x1000) -#define MOEMPTY(scsp) ((scsp->udata.data[2]>>0x0)&0x0800) -#define MIOVF(scsp) ((scsp->udata.data[2]>>0x0)&0x0400) -#define MIFULL(scsp) ((scsp->udata.data[2]>>0x0)&0x0200) -#define MIEMPTY(scsp) ((scsp->udata.data[2]>>0x0)&0x0100) - -#define SCILV0(scsp) ((scsp->udata.data[0x24/2]>>0x0)&0xff) -#define SCILV1(scsp) ((scsp->udata.data[0x26/2]>>0x0)&0xff) -#define SCILV2(scsp) ((scsp->udata.data[0x28/2]>>0x0)&0xff) - -#define SCIEX0 0 -#define SCIEX1 1 -#define SCIEX2 2 -#define SCIMID 3 -#define SCIDMA 4 -#define SCIIRQ 5 -#define SCITMA 6 -#define SCITMB 7 - -#define USEDSP - -struct _SCSP -{ - union - { - UINT16 data[0x30/2]; - UINT8 datab[0x30]; - } udata; - struct _SLOT Slots[32]; - signed short RINGBUF[64]; - unsigned char BUFPTR; -#if FM_DELAY - signed short DELAYBUF[FM_DELAY]; - unsigned char DELAYPTR; -#endif - unsigned char *SCSPRAM; - UINT32 SCSPRAM_LENGTH; - char Master; - void (*Int68kCB)(int irq); - - INT32 *buffertmpl, *buffertmpr; - - UINT32 IrqTimA; - UINT32 IrqTimBC; - UINT32 IrqMidi; - - UINT8 MidiOutW,MidiOutR; - UINT8 MidiStack[16]; - UINT8 MidiW,MidiR; - - int LPANTABLE[0x10000]; - int RPANTABLE[0x10000]; - - int TimPris[3]; - int TimCnt[3]; - - // DMA stuff - UINT32 scsp_dmea; - UINT16 scsp_drga; - UINT16 scsp_dtlg; - - int ARTABLE[64], DRTABLE[64]; - - struct _SCSPDSP DSP; -}; - -static struct _SCSP *AllocedSCSP; - -static void dma_scsp(struct _SCSP *SCSP); /*SCSP DMA transfer function*/ -#define scsp_dgate scsp_regs[0x16/2] & 0x4000 -#define scsp_ddir scsp_regs[0x16/2] & 0x2000 -#define scsp_dexe scsp_regs[0x16/2] & 0x1000 -#define dma_transfer_end ((scsp_regs[0x24/2] & 0x10)>>4)|(((scsp_regs[0x26/2] & 0x10)>>4)<<1)|(((scsp_regs[0x28/2] & 0x10)>>4)<<2) - -static const float SDLT[8]={-1000000.0,-36.0,-30.0,-24.0,-18.0,-12.0,-6.0,0.0}; - -static INT16 *bufferl; -static INT16 *bufferr; - -static int length; - -static signed short *RBUFDST; //this points to where the sample will be stored in the RingBuf - -static unsigned char DecodeSCI(struct _SCSP *SCSP,unsigned char irq) -{ - unsigned char SCI=0; - unsigned char v; - v=(SCILV0((SCSP))&(1<udata.data[0x22/2]; - if (reset & 0x40) - SCSP->Int68kCB(-SCSP->IrqTimA); - if (reset & 0x180) - SCSP->Int68kCB(-SCSP->IrqTimBC); -} - -static void CheckPendingIRQ(struct _SCSP *SCSP) -{ - UINT32 pend=SCSP->udata.data[0x20/2]; - UINT32 en=SCSP->udata.data[0x1e/2]; - if(SCSP->MidiW!=SCSP->MidiR) - { - SCSP->Int68kCB(SCSP->IrqMidi); - return; - } - if(!pend) - return; - if(pend&0x40) - if(en&0x40) - { - SCSP->Int68kCB(SCSP->IrqTimA); - return; - } - if(pend&0x80) - if(en&0x80) - { - SCSP->Int68kCB(SCSP->IrqTimBC); - return; - } - if(pend&0x100) - if(en&0x100) - { - SCSP->Int68kCB(SCSP->IrqTimBC); - return; - } - - SCSP->Int68kCB(0); -} - -static int Get_AR(struct _SCSP *SCSP,int base,int R) -{ - int Rate=base+(R<<1); - if(Rate>63) Rate=63; - if(Rate<0) Rate=0; - return SCSP->ARTABLE[Rate]; -} - -static int Get_DR(struct _SCSP *SCSP,int base,int R) -{ - int Rate=base+(R<<1); - if(Rate>63) Rate=63; - if(Rate<0) Rate=0; - return SCSP->DRTABLE[Rate]; -} - -static int Get_RR(struct _SCSP *SCSP,int base,int R) -{ - int Rate=base+(R<<1); - if(Rate>63) Rate=63; - if(Rate<0) Rate=0; - return SCSP->DRTABLE[Rate]; -} - -static void Compute_EG(struct _SCSP *SCSP,struct _SLOT *slot) -{ - int octave=OCT(slot); - int rate; - if(octave&8) octave=octave-16; - if(KRS(slot)!=0xf) - rate=octave+2*KRS(slot)+((FNS(slot)>>9)&1); - else - rate=0; //rate=((FNS(slot)>>9)&1); - - slot->EG.volume=0x17F<EG.AR=Get_AR(SCSP,rate,AR(slot)); - slot->EG.D1R=Get_DR(SCSP,rate,D1R(slot)); - slot->EG.D2R=Get_DR(SCSP,rate,D2R(slot)); - slot->EG.RR=Get_RR(SCSP,rate,RR(slot)); - slot->EG.DL=0x1f-DL(slot); - slot->EG.EGHOLD=EGHOLD(slot); -} - -static void SCSP_StopSlot(struct _SLOT *slot,int keyoff); - -static int EG_Update(struct _SLOT *slot) -{ - switch(slot->EG.state) - { - case ATTACK: - slot->EG.volume+=slot->EG.AR; - if(slot->EG.volume>=(0x3ff<EG.state=DECAY1; - if(slot->EG.D1R>=(1024<EG.state=DECAY2; - } - slot->EG.volume=0x3ff<EG.EGHOLD) - return 0x3ff<<(SHIFT-10); - break; - case DECAY1: - slot->EG.volume-=slot->EG.D1R; - if(slot->EG.volume<=0) - slot->EG.volume=0; - if(slot->EG.volume>>(EG_SHIFT+5)<=slot->EG.DL) - slot->EG.state=DECAY2; - break; - case DECAY2: - if(D2R(slot)==0) - return (slot->EG.volume>>EG_SHIFT)<<(SHIFT-10); - slot->EG.volume-=slot->EG.D2R; - if(slot->EG.volume<=0) - slot->EG.volume=0; - - break; - case RELEASE: - slot->EG.volume-=slot->EG.RR; - if(slot->EG.volume<=0) - { - slot->EG.volume=0; - SCSP_StopSlot(slot,0); - //slot->EG.volume=0x17F<EG.state=ATTACK; - } - break; - default: - return 1<EG.volume>>EG_SHIFT)<<(SHIFT-10); -} - -static UINT32 SCSP_Step(struct _SLOT *slot) -{ - int octave=OCT(slot); - UINT64 Fn; - - Fn=(FNS_Table[FNS(slot)]); //24.8 - if(octave&8) - Fn>>=(16-octave); - else - Fn<<=octave; - - return Fn/(44100); -} - - -static void Compute_LFO(struct _SLOT *slot) -{ - if(PLFOS(slot)!=0) - LFO_ComputeStep(&(slot->PLFO),LFOF(slot),PLFOWS(slot),PLFOS(slot),0); - if(ALFOS(slot)!=0) - LFO_ComputeStep(&(slot->ALFO),LFOF(slot),ALFOWS(slot),ALFOS(slot),1); -} - -static void SCSP_StartSlot(struct _SCSP *SCSP, struct _SLOT *slot) -{ - UINT32 start_offset; - slot->active=1; - slot->Backwards=0; - slot->cur_addr=0; slot->nxt_addr=1<base=SCSP->SCSPRAM + start_offset; - slot->step=SCSP_Step(slot); - Compute_EG(SCSP,slot); - slot->EG.state=ATTACK; - slot->EG.volume=0x17F<Prev=0; - Compute_LFO(slot); - -// printf("StartSlot: SA %x PCM8B %x LPCTL %x ALFOS %x STWINH %x TL %x EFSDL %x\n", SA(slot), PCM8B(slot), LPCTL(slot), ALFOS(slot), STWINH(slot), TL(slot), EFSDL(slot)); -// printf(" AR %x D1R %x D2R %x RR %x DL %x KRS %x EGHOLD %x LPSLNK %x\n", AR(slot), D1R(slot), D2R(slot), RR(slot), DL(slot), KRS(slot), EGHOLD(slot), LPSLNK(slot)); -} - -static void SCSP_StopSlot(struct _SLOT *slot,int keyoff) -{ - if(keyoff /*&& slot->EG.state!=RELEASE*/) - { - slot->EG.state=RELEASE; - } - else - { - slot->active=0; - } - slot->udata.data[0]&=~0x800; -} - -#define log_base_2(n) (log((float) n)/log((float) 2)) - -static void SCSP_Init(struct _SCSP *SCSP, const struct SCSPinterface *intf) -{ - int i=0; - - SCSP->IrqTimA = SCSP->IrqTimBC = SCSP->IrqMidi = 0; - SCSP->MidiR=SCSP->MidiW=0; - SCSP->MidiOutR=SCSP->MidiOutW=0; - - // get SCSP RAM - { - memset(SCSP,0,sizeof(*SCSP)); - - if (!i) - { - SCSP->Master=1; - } - else - { - SCSP->Master=0; - } - - if (intf->region) - { - SCSP->SCSPRAM = &sat_ram[0]; //(unsigned char *)intf->region; - SCSP->SCSPRAM_LENGTH = 512*1024; - SCSP->DSP.SCSPRAM = (UINT16 *)SCSP->SCSPRAM; - SCSP->DSP.SCSPRAM_LENGTH = (512*1024)/2; -// SCSP->SCSPRAM += intf->roffset; - } - } - - for(i=0;i<0x400;++i) - { - float fcent=(double) 1200.0*log_base_2((double)(((double) 1024.0+(double)i)/(double)1024.0)); - fcent=(double) 44100.0*pow(2.0,fcent/1200.0); - FNS_Table[i]=(float) (1<>0x0)&0xff; - int iPAN=(i>>0x8)&0x1f; - int iSDL=(i>>0xD)&0x07; - float TL=1.0; - float SegaDB=0; - float fSDL=1.0; - float PAN=1.0; - float LPAN,RPAN; - - if(iTL&0x01) SegaDB-=0.4; - if(iTL&0x02) SegaDB-=0.8; - if(iTL&0x04) SegaDB-=1.5; - if(iTL&0x08) SegaDB-=3; - if(iTL&0x10) SegaDB-=6; - if(iTL&0x20) SegaDB-=12; - if(iTL&0x40) SegaDB-=24; - if(iTL&0x80) SegaDB-=48; - - TL=pow(10.0,SegaDB/20.0); - - SegaDB=0; - if(iPAN&0x1) SegaDB-=3; - if(iPAN&0x2) SegaDB-=6; - if(iPAN&0x4) SegaDB-=12; - if(iPAN&0x8) SegaDB-=24; - - if((iPAN&0xf)==0xf) PAN=0.0; - else PAN=pow(10.0,SegaDB/20.0); - - if(iPAN<0x10) - { - LPAN=PAN; - RPAN=1.0; - } - else - { - RPAN=PAN; - LPAN=1.0; - } - - if(iSDL) - fSDL=pow(10.0,(SDLT[iSDL])/20.0); - else - fSDL=0.0; - - SCSP->LPANTABLE[i]=FIX((4.0*LPAN*TL*fSDL)); - SCSP->RPANTABLE[i]=FIX((4.0*RPAN*TL*fSDL)); - } - - SCSP->ARTABLE[0]=SCSP->DRTABLE[0]=0; //Infinite time - SCSP->ARTABLE[1]=SCSP->DRTABLE[1]=0; //Infinite time - for(i=2;i<64;++i) - { - double t,step,scale; - t=ARTimes[i]; //In ms - if(t!=0.0) - { - step=(1023*1000.0)/((float) 44100.0f*t); - scale=(double) (1<ARTABLE[i]=(int) (step*scale); - } - else - SCSP->ARTABLE[i]=1024<DRTABLE[i]=(int) (step*scale); - } - - // make sure all the slots are off - for(i=0;i<32;++i) - { - SCSP->Slots[i].slot=i; - SCSP->Slots[i].active=0; - SCSP->Slots[i].base=NULL; - } - - LFO_Init(); - SCSP->buffertmpl=(signed int*) malloc(44100*sizeof(signed int)); - SCSP->buffertmpr=(signed int*) malloc(44100*sizeof(signed int)); - memset(SCSP->buffertmpl,0,44100*sizeof(signed int)); - memset(SCSP->buffertmpr,0,44100*sizeof(signed int)); - - // no "pend" - SCSP[0].udata.data[0x20/2] = 0; - //SCSP[1].udata.data[0x20/2] = 0; - SCSP->TimCnt[0] = 0xffff; - SCSP->TimCnt[1] = 0xffff; - SCSP->TimCnt[2] = 0xffff; -} - -static void SCSP_UpdateSlotReg(struct _SCSP *SCSP,int s,int r) -{ - struct _SLOT *slot=SCSP->Slots+s; - int sl; - switch(r&0x3f) - { - case 0: - case 1: - if(KEYONEX(slot)) - { - for(sl=0;sl<32;++sl) - { - struct _SLOT *s2=SCSP->Slots+sl; - { - if(KEYONB(s2) && s2->EG.state==RELEASE/*&& !s2->active*/) - { - SCSP_StartSlot(SCSP, s2); - } - if(!KEYONB(s2) /*&& s2->active*/) - { - SCSP_StopSlot(s2,1); - } - } - } - slot->udata.data[0]&=~0x1000; - } - break; - case 0x10: - case 0x11: - slot->step=SCSP_Step(slot); - break; - case 0xA: - case 0xB: - slot->EG.RR=Get_RR(SCSP,0,RR(slot)); - slot->EG.DL=0x1f-DL(slot); - break; - case 0x12: - case 0x13: - Compute_LFO(slot); - break; - } -} - -static void SCSP_UpdateReg(struct _SCSP *SCSP, int reg) -{ - switch(reg&0x3f) - { - case 0x2: - case 0x3: - { - unsigned int v=RBL(SCSP); - SCSP->DSP.RBP=RBP(SCSP); - if(v==0) - SCSP->DSP.RBL=8*1024; - else if(v==1) - SCSP->DSP.RBL=16*1024; - if(v==2) - SCSP->DSP.RBL=32*1024; - if(v==3) - SCSP->DSP.RBL=64*1024; - } - break; - case 0x6: - case 0x7: - SCSP_MidiIn(0, SCSP->udata.data[0x6/2]&0xff, 0); - break; - case 0x12: - case 0x13: - case 0x14: - case 0x15: - case 0x16: - case 0x17: - break; - case 0x18: - case 0x19: - if(SCSP->Master) - { - SCSP->TimPris[0]=1<<((SCSP->udata.data[0x18/2]>>8)&0x7); - SCSP->TimCnt[0]=(SCSP->udata.data[0x18/2]&0xff)<<8; - } - break; - case 0x1a: - case 0x1b: - if(SCSP->Master) - { - SCSP->TimPris[1]=1<<((SCSP->udata.data[0x1A/2]>>8)&0x7); - SCSP->TimCnt[1]=(SCSP->udata.data[0x1A/2]&0xff)<<8; - } - break; - case 0x1C: - case 0x1D: - if(SCSP->Master) - { - SCSP->TimPris[2]=1<<((SCSP->udata.data[0x1C/2]>>8)&0x7); - SCSP->TimCnt[2]=(SCSP->udata.data[0x1C/2]&0xff)<<8; - } - break; - case 0x22: //SCIRE - case 0x23: - - if(SCSP->Master) - { - SCSP->udata.data[0x20/2]&=~SCSP->udata.data[0x22/2]; - ResetInterrupts(SCSP); - - // behavior from real hardware: if you SCIRE a timer that's expired, - // it'll immediately pop up again. ask Sakura Taisen on the Saturn... - if (SCSP->TimCnt[0] >= 0xff00) - { - SCSP->udata.data[0x20/2] |= 0x40; - } - if (SCSP->TimCnt[1] >= 0xff00) - { - SCSP->udata.data[0x20/2] |= 0x80; - } - if (SCSP->TimCnt[2] >= 0xff00) - { - SCSP->udata.data[0x20/2] |= 0x100; - } - } - break; - case 0x24: - case 0x25: - case 0x26: - case 0x27: - case 0x28: - case 0x29: - if(SCSP->Master) - { - SCSP->IrqTimA=DecodeSCI(SCSP,SCITMA); - SCSP->IrqTimBC=DecodeSCI(SCSP,SCITMB); - SCSP->IrqMidi=DecodeSCI(SCSP,SCIMID); - } - break; - } -} - -static void SCSP_UpdateSlotRegR(struct _SCSP *SCSP, int slot,int reg) -{ - -} - -static void SCSP_UpdateRegR(struct _SCSP *SCSP, int reg) -{ - switch(reg&0x3f) - { - case 4: - case 5: - { - unsigned short v=SCSP->udata.data[0x5/2]; - v&=0xff00; - v|=SCSP->MidiStack[SCSP->MidiR]; - SCSP->Int68kCB(0); // cancel the IRQ - if(SCSP->MidiR!=SCSP->MidiW) - { - ++SCSP->MidiR; - SCSP->MidiR&=15; - } - SCSP->udata.data[0x5/2]=v; - } - break; - case 8: - case 9: - { - unsigned char slot=SCSP->udata.data[0x8/2]>>11; - unsigned int CA=SCSP->Slots[slot&0x1f].cur_addr>>(SHIFT+12); - SCSP->udata.data[0x8/2]&=~(0x780); - SCSP->udata.data[0x8/2]|=CA<<7; - } - break; - } -} - -static void SCSP_w16(struct _SCSP *SCSP,unsigned int addr,unsigned short val) -{ - addr&=0xffff; - if(addr<0x400) - { - int slot=addr/0x20; - addr&=0x1f; - *((unsigned short *) (SCSP->Slots[slot].udata.datab+(addr))) = val; - SCSP_UpdateSlotReg(SCSP,slot,addr&0x1f); - } - else if(addr<0x600) - { - if (addr < 0x430) - { - *((unsigned short *) (SCSP->udata.datab+((addr&0x3f)))) = val; - SCSP_UpdateReg(SCSP, addr&0x3f); - } - } - else if(addr<0x700) - SCSP->RINGBUF[(addr-0x600)/2]=val; - else - { - //DSP - if(addr<0x780) //COEF - *((unsigned short *) (SCSP->DSP.COEF+(addr-0x700)/2))=val; - else if(addr<0x800) - *((unsigned short *) (SCSP->DSP.MADRS+(addr-0x780)/2))=val; - else if(addr<0xC00) - *((unsigned short *) (SCSP->DSP.MPRO+(addr-0x800)/2))=val; - - if(addr==0xBF0) - { -// printf("DSP start\n"); - SCSPDSP_Start(&SCSP->DSP); - } - } -} - -static unsigned short SCSP_r16(struct _SCSP *SCSP, unsigned int addr) -{ - unsigned short v=0; - addr&=0xffff; - if(addr<0x400) - { - int slot=addr/0x20; - addr&=0x1f; - SCSP_UpdateSlotRegR(SCSP, slot,addr&0x1f); - v=*((unsigned short *) (SCSP->Slots[slot].udata.datab+(addr))); - } - else if(addr<0x600) - { - if (addr < 0x430) - { - SCSP_UpdateRegR(SCSP, addr&0x3f); - v= *((unsigned short *) (SCSP->udata.datab+((addr&0x3f)))); - } - } - else if(addr<0x700) - v=SCSP->RINGBUF[(addr-0x600)/2]; - return v; -} - - -#define REVSIGN(v) ((~v)+1) - -void SCSP_TimersAddTicks(struct _SCSP *SCSP, int ticks) -{ - if(SCSP->TimCnt[0]<=0xff00) - { - SCSP->TimCnt[0] += ticks << (8-((SCSP->udata.data[0x18/2]>>8)&0x7)); - if (SCSP->TimCnt[0] > 0xFF00) - { - SCSP->TimCnt[0] = 0xFFFF; - SCSP->udata.data[0x20/2]|=0x40; - } - SCSP->udata.data[0x18/2]&=0xff00; - SCSP->udata.data[0x18/2]|=SCSP->TimCnt[0]>>8; - } - - if(SCSP->TimCnt[1]<=0xff00) - { - SCSP->TimCnt[1] += ticks << (8-((SCSP->udata.data[0x1a/2]>>8)&0x7)); - if (SCSP->TimCnt[1] > 0xFF00) - { - SCSP->TimCnt[1] = 0xFFFF; - SCSP->udata.data[0x20/2]|=0x80; - } - SCSP->udata.data[0x1a/2]&=0xff00; - SCSP->udata.data[0x1a/2]|=SCSP->TimCnt[1]>>8; - } - - if(SCSP->TimCnt[2]<=0xff00) - { - SCSP->TimCnt[2] += ticks << (8-((SCSP->udata.data[0x1c/2]>>8)&0x7)); - if (SCSP->TimCnt[2] > 0xFF00) - { - SCSP->TimCnt[2] = 0xFFFF; - SCSP->udata.data[0x20/2]|=0x100; - } - SCSP->udata.data[0x1c/2]&=0xff00; - SCSP->udata.data[0x1c/2]|=SCSP->TimCnt[2]>>8; - } -} - -static INLINE INT32 SCSP_UpdateSlot(struct _SCSP *SCSP, struct _SLOT *slot) -{ - INT32 sample; - int step=slot->step; - UINT32 addr1,addr2,addr_select; // current and next sample addresses - UINT32 *addr[2] = {&addr1, &addr2}; // used for linear interpolation - UINT32 *slot_addr[2] = {&(slot->cur_addr), &(slot->nxt_addr)}; // - - if(SSCTL(slot)!=0) //no FM or noise yet - return 0; - - if(PLFOS(slot)!=0) - { - step=step*PLFO_Step(&(slot->PLFO)); - step>>=SHIFT; - } - - if(PCM8B(slot)) - { - addr1=slot->cur_addr>>SHIFT; - addr2=slot->nxt_addr>>SHIFT; - } - else - { - addr1=(slot->cur_addr>>(SHIFT-1))&0x7fffe; - addr2=(slot->nxt_addr>>(SHIFT-1))&0x7fffe; - } - - if(MDL(slot)!=0 || MDXSL(slot)!=0 || MDYSL(slot)!=0) - { - INT32 smp=(SCSP->RINGBUF[(SCSP->BUFPTR+MDXSL(slot))&63]+SCSP->RINGBUF[(SCSP->BUFPTR+MDYSL(slot))&63])/2; - - smp<<=0xA; // associate cycle with 1024 - smp>>=0x1A-MDL(slot); // ex. for MDL=0xF, sample range corresponds to +/- 64 pi (32=2^5 cycles) so shift by 11 (16-5 == 0x1A-0xF) - if(!PCM8B(slot)) smp<<=1; - - addr1+=smp; addr2+=smp; - } - - if(PCM8B(slot)) //8 bit signed - { - INT8 *p1=(signed char *) (SCSP->SCSPRAM+(((SA(slot)+addr1)^1)&0x7FFFF)); - INT8 *p2=(signed char *) (SCSP->SCSPRAM+(((SA(slot)+addr2)^1)&0x7FFFF)); - //sample=(p[0])<<8; - INT32 s; - INT32 fpart=slot->cur_addr&((1<>SHIFT); - } - else //16 bit signed (endianness?) - { - INT16 *p1=(signed short *) (SCSP->SCSPRAM+((SA(slot)+addr1)&0x7FFFE)); - INT16 *p2=(signed short *) (SCSP->SCSPRAM+((SA(slot)+addr2)&0x7FFFE)); - //sample=LE16(p[0]); - INT32 s; - INT32 fpart=slot->cur_addr&((1<>SHIFT); - } - - if(SBCTL(slot)&0x1) - sample ^= 0x7FFF; - if(SBCTL(slot)&0x2) - sample = (INT16)(sample^0x8000); - - if(slot->Backwards) - slot->cur_addr-=step; - else - slot->cur_addr+=step; - slot->nxt_addr=slot->cur_addr+(1<cur_addr>>SHIFT; - addr2=slot->nxt_addr>>SHIFT; - - if(addr1>=LSA(slot) && !(slot->Backwards)) - { - if(LPSLNK(slot) && slot->EG.state==ATTACK) - slot->EG.state = DECAY1; - } - - for (addr_select=0;addr_select<2;addr_select++) - { - INT32 rem_addr; - switch(LPCTL(slot)) - { - case 0: //no loop - if(*addr[addr_select]>=LSA(slot) && *addr[addr_select]>=LEA(slot)) - { - //slot->active=0; - SCSP_StopSlot(slot,0); - } - break; - case 1: //normal loop - if(*addr[addr_select]>=LEA(slot)) - { - rem_addr = *slot_addr[addr_select] - (LEA(slot)<=LSA(slot)) && !(slot->Backwards)) - { - rem_addr = *slot_addr[addr_select] - (LSA(slot)<Backwards=1; - } - else if((*addr[addr_select]Backwards) - { - rem_addr = (LSA(slot)<=LEA(slot)) //reached end, reverse till start - { - rem_addr = *slot_addr[addr_select] - (LEA(slot)<Backwards=1; - } - else if((*addr[addr_select]Backwards)//reached start or negative - { - rem_addr = (LSA(slot)<Backwards=0; - } - break; - } - } - - if(ALFOS(slot)!=0) - { - sample=sample*ALFO_Step(&(slot->ALFO)); - sample>>=SHIFT; - } - - if(slot->EG.state==ATTACK) - sample=(sample*EG_Update(slot))>>SHIFT; - else - sample=(sample*EG_TABLE[EG_Update(slot)>>(SHIFT-10)])>>SHIFT; - - if(!STWINH(slot)) - { - unsigned short Enc=((TL(slot))<<0x0)|(0x7<<0xd); - *RBUFDST=(sample*SCSP->LPANTABLE[Enc])>>(SHIFT+1); - } - - return sample; -} - -static void SCSP_DoMasterSamples(struct _SCSP *SCSP, int nsamples) -{ - INT16 *bufr,*bufl; - int sl, s, i; - - bufr=bufferr; - bufl=bufferl; - - for(s=0;sDELAYBUF+SCSP->DELAYPTR; -#else - RBUFDST=SCSP->RINGBUF+SCSP->BUFPTR; -#endif - if(SCSP->Slots[sl].active) - { - struct _SLOT *slot=SCSP->Slots+sl; - unsigned short Enc; - signed int sample; - - sample=SCSP_UpdateSlot(SCSP, slot); - - Enc=((TL(slot))<<0x0)|((IMXL(slot))<<0xd); - SCSPDSP_SetSample(&SCSP->DSP,(sample*SCSP->LPANTABLE[Enc])>>(SHIFT-2),ISEL(slot),IMXL(slot)); - Enc=((TL(slot))<<0x0)|((DIPAN(slot))<<0x8)|((DISDL(slot))<<0xd); - { - smpl+=(sample*SCSP->LPANTABLE[Enc])>>SHIFT; - smpr+=(sample*SCSP->RPANTABLE[Enc])>>SHIFT; - } - } - -#if FM_DELAY - SCSP->RINGBUF[(SCSP->BUFPTR+64-(FM_DELAY-1))&63] = SCSP->DELAYBUF[(SCSP->DELAYPTR+FM_DELAY-(FM_DELAY-1))%FM_DELAY]; -#endif - ++SCSP->BUFPTR; - SCSP->BUFPTR&=63; -#if FM_DELAY - ++SCSP->DELAYPTR; - if(SCSP->DELAYPTR>FM_DELAY-1) SCSP->DELAYPTR=0; -#endif - } - - SCSPDSP_Step(&SCSP->DSP); - - for(i=0;i<16;++i) - { - struct _SLOT *slot=SCSP->Slots+i; - if(EFSDL(slot)) - { - unsigned short Enc=((EFPAN(slot))<<0x8)|((EFSDL(slot))<<0xd); - smpl+=(SCSP->DSP.EFREG[i]*SCSP->LPANTABLE[Enc])>>SHIFT; - smpr+=(SCSP->DSP.EFREG[i]*SCSP->RPANTABLE[Enc])>>SHIFT; - } - } - - *bufl++ = ICLIP16(smpl>>2); - *bufr++ = ICLIP16(smpr>>2); - - SCSP_TimersAddTicks(SCSP, 1); - CheckPendingIRQ(SCSP); - } - -} - -static void dma_scsp(struct _SCSP *SCSP) -{ - static UINT16 tmp_dma[3], *scsp_regs; - - scsp_regs = (UINT16 *)SCSP->udata.datab; - - printf("SCSP: DMA transfer START\n" - "DMEA: %04x DRGA: %04x DTLG: %04x\n" - "DGATE: %d DDIR: %d\n",SCSP->scsp_dmea,SCSP->scsp_drga,SCSP->scsp_dtlg,scsp_dgate ? 1 : 0,scsp_ddir ? 1 : 0); - - /* Copy the dma values in a temp storage for resuming later * - * (DMA *can't* overwrite his parameters). */ - if(!(scsp_ddir)) - { - tmp_dma[0] = scsp_regs[0x12/2]; - tmp_dma[1] = scsp_regs[0x14/2]; - tmp_dma[2] = scsp_regs[0x16/2]; - } - - if(scsp_ddir) - { - for(;SCSP->scsp_dtlg > 0;SCSP->scsp_dtlg-=2) - { -// program_write_word(SCSP->scsp_dmea, program_read_word(0x100000|SCSP->scsp_drga)); - SCSP->scsp_dmea+=2; - SCSP->scsp_drga+=2; - } - } - else - { - for(;SCSP->scsp_dtlg > 0;SCSP->scsp_dtlg-=2) - { -// program_write_word(0x100000|SCSP->scsp_drga,program_read_word(SCSP->scsp_dmea)); - SCSP->scsp_dmea+=2; - SCSP->scsp_drga+=2; - } - } - - /*Resume the values*/ - if(!(scsp_ddir)) - { - scsp_regs[0x12/2] = tmp_dma[0]; - scsp_regs[0x14/2] = tmp_dma[1]; - scsp_regs[0x16/2] = tmp_dma[2]; - } - - /*Job done,request a dma end irq*/ -// if(scsp_regs[0x1e/2] & 0x10) -// cpunum_set_input_line(2,dma_transfer_end,HOLD_LINE); -} - -int SCSP_IRQCB(void *param) -{ - CheckPendingIRQ(param); - return -1; -} - -void SCSP_Update(void *param, INT16 **inputs, INT16 **buf, int samples) -{ - struct _SCSP *SCSP = AllocedSCSP; - bufferl = buf[0]; - bufferr = buf[1]; - length = samples; - SCSP_DoMasterSamples(SCSP, samples); -} - -void *scsp_start(const void *config) -{ - const struct SCSPinterface *intf; - - struct _SCSP *SCSP; - - SCSP = malloc(sizeof(*SCSP)); - memset(SCSP, 0, sizeof(*SCSP)); - - intf = config; - - // init the emulation - SCSP_Init(SCSP, intf); - - // set up the IRQ callbacks - { - SCSP->Int68kCB = intf->irq_callback[0]; - -// SCSP->stream = stream_create(0, 2, 44100, SCSP, SCSP_Update); - } - - AllocedSCSP = SCSP; - - return SCSP; -} - -void scsp_stop(void) -{ - free(AllocedSCSP->buffertmpl); - free(AllocedSCSP->buffertmpr); - - free(AllocedSCSP); -} - - -void SCSP_set_ram_base(int which, void *base) -{ - struct _SCSP *SCSP = AllocedSCSP; - if (SCSP) - { - SCSP->SCSPRAM = base; - SCSP->DSP.SCSPRAM = base; - } -} - - -READ16_HANDLER( SCSP_0_r ) -{ - struct _SCSP *SCSP = AllocedSCSP; - - return SCSP_r16(SCSP, offset*2); -} - -extern UINT32* stv_scu; - -WRITE16_HANDLER( SCSP_0_w ) -{ - struct _SCSP *SCSP = AllocedSCSP; - UINT16 tmp, *scsp_regs; - - tmp = SCSP_r16(SCSP, offset*2); - COMBINE_DATA(&tmp); - SCSP_w16(SCSP,offset*2, tmp); - - scsp_regs = (UINT16 *)SCSP->udata.datab; - - switch(offset*2) - { - // check DMA - case 0x412: - /*DMEA [15:1]*/ - /*Sound memory address*/ - SCSP->scsp_dmea = (((scsp_regs[0x14/2] & 0xf000)>>12)*0x10000) | (scsp_regs[0x12/2] & 0xfffe); - break; - case 0x414: - /*DMEA [19:16]*/ - SCSP->scsp_dmea = (((scsp_regs[0x14/2] & 0xf000)>>12)*0x10000) | (scsp_regs[0x12/2] & 0xfffe); - /*DRGA [11:1]*/ - /*Register memory address*/ - SCSP->scsp_drga = scsp_regs[0x14/2] & 0x0ffe; - break; - case 0x416: - /*DGATE[14]*/ - /*DDIR[13]*/ - /*if 0 sound_mem -> reg*/ - /*if 1 sound_mem <- reg*/ - /*DEXE[12]*/ - /*starting bit*/ - /*DTLG[11:1]*/ - /*size of transfer*/ - SCSP->scsp_dtlg = scsp_regs[0x16/2] & 0x0ffe; - if(scsp_dexe) - { - dma_scsp(SCSP); - scsp_regs[0x16/2]^=0x1000;//disable starting bit - } - break; - //check main cpu IRQ - case 0x42a: -#if 0 - if(stv_scu && !(stv_scu[40] & 0x40) /*&& scsp_regs[0x42c/2] & 0x20*/)/*Main CPU allow sound irq*/ - { - cpunum_set_input_line_and_vector(0, 9, HOLD_LINE , 0x46); - logerror("SCSP: Main CPU interrupt\n"); - } -#endif - break; - case 0x42c: - break; - case 0x42e: - break; - } -} - -WRITE16_HANDLER( SCSP_MidiIn ) -{ - struct _SCSP *SCSP = AllocedSCSP; - SCSP->MidiStack[SCSP->MidiW++]=data; - SCSP->MidiW &= 15; -} - -READ16_HANDLER( SCSP_MidiOutR ) -{ - struct _SCSP *SCSP = AllocedSCSP; - unsigned char val; - - val=SCSP->MidiStack[SCSP->MidiR++]; - SCSP->MidiR&=7; - return val; -} - diff --git a/Frameworks/AudioOverload/aosdk/eng_ssf/scsp.h b/Frameworks/AudioOverload/aosdk/eng_ssf/scsp.h deleted file mode 100644 index 56c82f713..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_ssf/scsp.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - - SCSP (YMF292-F) header -*/ - -#ifndef _SCSP_H_ -#define _SCSP_H_ - -#define MAX_SCSP (2) - -#define COMBINE_DATA(varptr) (*(varptr) = (*(varptr) & mem_mask) | (data & ~mem_mask)) - -// convert AO types -typedef int8 data8_t; -typedef int16 data16_t; -typedef int32 data32_t; -typedef int offs_t; - -struct SCSPinterface -{ - int num; - void *region[MAX_SCSP]; - int mixing_level[MAX_SCSP]; /* volume */ - void (*irq_callback[MAX_SCSP])(int state); /* irq callback */ -}; - -void *scsp_start(const void *config); -void scsp_stop(void); - -void SCSP_Update(void *param, INT16 **inputs, INT16 **buf, int samples); - -#define READ16_HANDLER(name) data16_t name(offs_t offset, data16_t mem_mask) -#define WRITE16_HANDLER(name) void name(offs_t offset, data16_t data, data16_t mem_mask) - -// SCSP register access -READ16_HANDLER( SCSP_0_r ); -WRITE16_HANDLER( SCSP_0_w ); -READ16_HANDLER( SCSP_1_r ); -WRITE16_HANDLER( SCSP_1_w ); - -// MIDI I/O access (used for comms on Model 2/3) -WRITE16_HANDLER( SCSP_MidiIn ); -READ16_HANDLER( SCSP_MidiOutR ); - -#endif diff --git a/Frameworks/AudioOverload/aosdk/eng_ssf/scspdsp.c b/Frameworks/AudioOverload/aosdk/eng_ssf/scspdsp.c deleted file mode 100644 index 8c08dd729..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_ssf/scspdsp.c +++ /dev/null @@ -1,349 +0,0 @@ -#include -#include -#include "ao.h" -#include "cpuintrf.h" -#include "scsp.h" -#include "scspdsp.h" - -static UINT16 PACK(INT32 val) -{ - UINT32 temp; - int sign,exponent,k; - - sign = (val >> 23) & 0x1; - temp = (val ^ (val << 1)) & 0xFFFFFF; - exponent = 0; - for (k=0; k<12; k++) - { - if (temp & 0x800000) - break; - temp <<= 1; - exponent += 1; - } - if (exponent < 12) - val = (val << exponent) & 0x3FFFFF; - else - val <<= 11; - val >>= 11; - val |= sign << 15; - val |= exponent << 11; - - return (UINT16)val; -} - -static INT32 UNPACK(UINT16 val) -{ - int sign,exponent,mantissa; - INT32 uval; - - sign = (val >> 15) & 0x1; - exponent = (val >> 11) & 0xF; - mantissa = val & 0x7FF; - uval = mantissa << 11; - if (exponent > 11) - exponent = 11; - else - uval |= (sign ^ 1) << 22; - uval |= sign << 23; - uval <<= 8; - uval >>= 8; - uval >>= exponent; - - return uval; -} - -void SCSPDSP_Init(struct _SCSPDSP *DSP) -{ - memset(DSP,0,sizeof(struct _SCSPDSP)); - DSP->RBL=0x8000; - DSP->Stopped=1; -} - -void SCSPDSP_Step(struct _SCSPDSP *DSP) -{ - INT32 ACC=0; //26 bit - INT32 SHIFTED=0; //24 bit - INT32 X=0; //24 bit - INT32 Y=0; //13 bit - INT32 B=0; //26 bit - INT32 INPUTS=0; //24 bit - INT32 MEMVAL=0; - INT32 FRC_REG=0; //13 bit - INT32 Y_REG=0; //24 bit - UINT32 ADDR=0; - UINT32 ADRS_REG=0; //13 bit - int step; - - if(DSP->Stopped) - return; - - memset(DSP->EFREG,0,2*16); -#if 0 - int dump=0; - FILE *f=NULL; - if(dump) - f=fopen("dsp.txt","wt"); -#endif - for(step=0;stepLastStep;++step) - { - UINT16 *IPtr=DSP->MPRO+step*4; - -// if(IPtr[0]==0 && IPtr[1]==0 && IPtr[2]==0 && IPtr[3]==0) -// break; - - UINT32 TRA=(IPtr[0]>>8)&0x7F; - UINT32 TWT=(IPtr[0]>>7)&0x01; - UINT32 TWA=(IPtr[0]>>0)&0x7F; - - UINT32 XSEL=(IPtr[1]>>15)&0x01; - UINT32 YSEL=(IPtr[1]>>13)&0x03; - UINT32 IRA=(IPtr[1]>>6)&0x3F; - UINT32 IWT=(IPtr[1]>>5)&0x01; - UINT32 IWA=(IPtr[1]>>0)&0x1F; - - UINT32 TABLE=(IPtr[2]>>15)&0x01; - UINT32 MWT=(IPtr[2]>>14)&0x01; - UINT32 MRD=(IPtr[2]>>13)&0x01; - UINT32 EWT=(IPtr[2]>>12)&0x01; - UINT32 EWA=(IPtr[2]>>8)&0x0F; - UINT32 ADRL=(IPtr[2]>>7)&0x01; - UINT32 FRCL=(IPtr[2]>>6)&0x01; - UINT32 SHIFT=(IPtr[2]>>4)&0x03; - UINT32 YRL=(IPtr[2]>>3)&0x01; - UINT32 NEGB=(IPtr[2]>>2)&0x01; - UINT32 ZERO=(IPtr[2]>>1)&0x01; - UINT32 BSEL=(IPtr[2]>>0)&0x01; - - UINT32 NOFL=(IPtr[3]>>15)&1; //???? - UINT32 COEF=(IPtr[3]>>9)&0x3f; - - UINT32 MASA=(IPtr[3]>>2)&0x1f; //??? - UINT32 ADREB=(IPtr[3]>>1)&0x1; - UINT32 NXADR=(IPtr[3]>>0)&0x1; - - INT64 v; - - //operations are done at 24 bit precision -#if 0 - if(MASA) - int a=1; - if(NOFL) - int a=1; - -// int dump=0; - - if(f) - { -#define DUMP(v) fprintf(f," " #v ": %04X",v); - - fprintf(f,"%d: ",step); - DUMP(ACC); - DUMP(SHIFTED); - DUMP(X); - DUMP(Y); - DUMP(B); - DUMP(INPUTS); - DUMP(MEMVAL); - DUMP(FRC_REG); - DUMP(Y_REG); - DUMP(ADDR); - DUMP(ADRS_REG); - fprintf(f,"\n"); - } -#endif - //INPUTS RW - assert(IRA<0x32); - if(IRA<=0x1f) - INPUTS=DSP->MEMS[IRA]; - else if(IRA<=0x2F) - INPUTS=DSP->MIXS[IRA-0x20]<<4; //MIXS is 20 bit - else if(IRA<=0x31) - INPUTS=0; - - INPUTS<<=8; - INPUTS>>=8; - //if(INPUTS&0x00800000) - // INPUTS|=0xFF000000; - - if(IWT) - { - DSP->MEMS[IWA]=MEMVAL; //MEMVAL was selected in previous MRD - if(IRA==IWA) - INPUTS=MEMVAL; - } - - //Operand sel - //B - if(!ZERO) - { - if(BSEL) - B=ACC; - else - { - B=DSP->TEMP[(TRA+DSP->DEC)&0x7F]; - B<<=8; - B>>=8; - //if(B&0x00800000) - // B|=0xFF000000; //Sign extend - } - if(NEGB) - B=0-B; - } - else - B=0; - - //X - if(XSEL) - X=INPUTS; - else - { - X=DSP->TEMP[(TRA+DSP->DEC)&0x7F]; - X<<=8; - X>>=8; - //if(X&0x00800000) - // X|=0xFF000000; - } - - //Y - if(YSEL==0) - Y=FRC_REG; - else if(YSEL==1) - Y=DSP->COEF[COEF]>>3; //COEF is 16 bits - else if(YSEL==2) - Y=(Y_REG>>11)&0x1FFF; - else if(YSEL==3) - Y=(Y_REG>>4)&0x0FFF; - - if(YRL) - Y_REG=INPUTS; - - //Shifter - if(SHIFT==0) - { - SHIFTED=ACC; - if(SHIFTED>0x007FFFFF) - SHIFTED=0x007FFFFF; - if(SHIFTED<(-0x00800000)) - SHIFTED=-0x00800000; - } - else if(SHIFT==1) - { - SHIFTED=ACC*2; - if(SHIFTED>0x007FFFFF) - SHIFTED=0x007FFFFF; - if(SHIFTED<(-0x00800000)) - SHIFTED=-0x00800000; - } - else if(SHIFT==2) - { - SHIFTED=ACC*2; - SHIFTED<<=8; - SHIFTED>>=8; - //SHIFTED&=0x00FFFFFF; - //if(SHIFTED&0x00800000) - // SHIFTED|=0xFF000000; - } - else if(SHIFT==3) - { - SHIFTED=ACC; - SHIFTED<<=8; - SHIFTED>>=8; - //SHIFTED&=0x00FFFFFF; - //if(SHIFTED&0x00800000) - // SHIFTED|=0xFF000000; - } - - //ACCUM - Y<<=19; - Y>>=19; - //if(Y&0x1000) - // Y|=0xFFFFF000; - - v=(((INT64) X*(INT64) Y)>>12); - ACC=(int) v+B; - - if(TWT) - DSP->TEMP[(TWA+DSP->DEC)&0x7F]=SHIFTED; - - if(FRCL) - { - if(SHIFT==3) - FRC_REG=SHIFTED&0x0FFF; - else - FRC_REG=(SHIFTED>>11)&0x1FFF; - } - - if(MRD || MWT) - //if(0) - { - ADDR=DSP->MADRS[MASA]; - if(!TABLE) - ADDR+=DSP->DEC; - if(ADREB) - ADDR+=ADRS_REG&0x0FFF; - if(NXADR) - ADDR++; - if(!TABLE) - ADDR&=DSP->RBL-1; - else - ADDR&=0xFFFF; - //ADDR<<=1; - //ADDR+=DSP->RBP<<13; - //MEMVAL=DSP->SCSPRAM[ADDR>>1]; - ADDR+=DSP->RBP<<12; - if(MRD && (step&1)) //memory only allowed on odd? DoA inserts NOPs on even - { - if(NOFL) - MEMVAL=DSP->SCSPRAM[ADDR]<<8; - else - MEMVAL=UNPACK(DSP->SCSPRAM[ADDR]); - } - if(MWT && (step&1)) - { - if(NOFL) - DSP->SCSPRAM[ADDR]=SHIFTED>>8; - else - DSP->SCSPRAM[ADDR]=PACK(SHIFTED); - } - } - - if(ADRL) - { - if(SHIFT==3) - ADRS_REG=(SHIFTED>>12)&0xFFF; - else - ADRS_REG=(INPUTS>>16); - } - - if(EWT) - DSP->EFREG[EWA]+=SHIFTED>>8; - - } - --DSP->DEC; - memset(DSP->MIXS,0,4*16); -// if(f) -// fclose(f); -} - -void SCSPDSP_SetSample(struct _SCSPDSP *DSP,INT32 sample,int SEL,int MXL) -{ - //DSP->MIXS[SEL]+=sample<<(MXL+1)/*7*/; - DSP->MIXS[SEL]+=sample; -// if(MXL) -// int a=1; -} - -void SCSPDSP_Start(struct _SCSPDSP *DSP) -{ - int i; - DSP->Stopped=0; - for(i=127;i>=0;--i) - { - UINT16 *IPtr=DSP->MPRO+i*4; - - if(IPtr[0]!=0 || IPtr[1]!=0 || IPtr[2]!=0 || IPtr[3]!=0) - break; - } - DSP->LastStep=i+1; - -} diff --git a/Frameworks/AudioOverload/aosdk/eng_ssf/scspdsp.h b/Frameworks/AudioOverload/aosdk/eng_ssf/scspdsp.h deleted file mode 100644 index 481f93af0..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_ssf/scspdsp.h +++ /dev/null @@ -1,37 +0,0 @@ -#ifndef SCSPDSP_H -#define SCSPDSP_H - -//the DSP Context -struct _SCSPDSP -{ -//Config - UINT16 *SCSPRAM; - UINT32 SCSPRAM_LENGTH; - UINT32 RBP; //Ring buf pointer - UINT32 RBL; //Delay ram (Ring buffer) size in words - -//context - - INT16 COEF[64]; //16 bit signed - UINT16 MADRS[32]; //offsets (in words), 16 bit - UINT16 MPRO[128*4]; //128 steps 64 bit - INT32 TEMP[128]; //TEMP regs,24 bit signed - INT32 MEMS[32]; //MEMS regs,24 bit signed - UINT32 DEC; - -//input - INT32 MIXS[16]; //MIXS, 24 bit signed - INT16 EXTS[2]; //External inputs (CDDA) 16 bit signed - -//output - INT16 EFREG[16]; //EFREG, 16 bit signed - - int Stopped; - int LastStep; -}; - -void SCSPDSP_Init(struct _SCSPDSP *DSP); -void SCSPDSP_SetSample(struct _SCSPDSP *DSP, INT32 sample, INT32 SEL, INT32 MXL); -void SCSPDSP_Step(struct _SCSPDSP *DSP); -void SCSPDSP_Start(struct _SCSPDSP *DSP); -#endif diff --git a/Frameworks/AudioOverload/aosdk/eng_ssf/scsplfo.c b/Frameworks/AudioOverload/aosdk/eng_ssf/scsplfo.c deleted file mode 100644 index 0a8281c1f..000000000 --- a/Frameworks/AudioOverload/aosdk/eng_ssf/scsplfo.c +++ /dev/null @@ -1,157 +0,0 @@ -/* - SCSP LFO handling - - Part of the SCSP (YMF292-F) emulator package. - (not compiled directly, #included from scsp.c) - - By ElSemi - MAME/M1 conversion and cleanup by R. Belmont -*/ - -#define LFO_SHIFT 8 - -struct _LFO -{ - unsigned short phase; - UINT32 phase_step; - int *table; - int *scale; -}; - -#define LFIX(v) ((unsigned int) ((float) (1<phase+=LFO->phase_step; -#if LFO_SHIFT!=8 - LFO->phase&=(1<<(LFO_SHIFT+8))-1; -#endif - p=LFO->table[LFO->phase>>LFO_SHIFT]; - p=LFO->scale[p+128]; - return p<<(SHIFT-LFO_SHIFT); -} - -static signed int INLINE ALFO_Step(struct _LFO *LFO) -{ - int p; - LFO->phase+=LFO->phase_step; -#if LFO_SHIFT!=8 - LFO->phase&=(1<<(LFO_SHIFT+8))-1; -#endif - p=LFO->table[LFO->phase>>LFO_SHIFT]; - p=LFO->scale[p]; - return p<<(SHIFT-LFO_SHIFT); -} - -void LFO_ComputeStep(struct _LFO *LFO,UINT32 LFOF,UINT32 LFOWS,UINT32 LFOS,int ALFO) -{ - float step=(float) LFOFreq[LFOF]*256.0/(float)44100.0; - LFO->phase_step=(unsigned int) ((float) (1<table=ALFO_SAW; break; - case 1: LFO->table=ALFO_SQR; break; - case 2: LFO->table=ALFO_TRI; break; - case 3: LFO->table=ALFO_NOI; break; - } - LFO->scale=ASCALES[LFOS]; - } - else - { - switch(LFOWS) - { - case 0: LFO->table=PLFO_SAW; break; - case 1: LFO->table=PLFO_SQR; break; - case 2: LFO->table=PLFO_TRI; break; - case 3: LFO->table=PLFO_NOI; break; - } - LFO->scale=PSCALES[LFOS]; - } -} diff --git a/Frameworks/AudioOverload/aosdk/file.c b/Frameworks/AudioOverload/aosdk/file.c deleted file mode 100644 index 9180ad82a..000000000 --- a/Frameworks/AudioOverload/aosdk/file.c +++ /dev/null @@ -1,98 +0,0 @@ -/* - - Audio Overload SDK - - Copyright (c) 2007, R. Belmont and Richard Bannister. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - * Neither the names of R. Belmont and Richard Bannister nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#include -#include -#include - -#include "ao.h" - -// local variables - -void (*m1sdr_Callback)(unsigned long dwNumSamples, signed short *data); - -int nDSoundSegLen = 0; - -static INT16 samples[44100*2]; -static FILE *fout = NULL; - -// set # of samples per update - -void m1sdr_SetSamplesPerTick(UINT32 spf) -{ -} - -// m1sdr_Update - timer callback routine: runs sequencer and mixes sound - -void m1sdr_Update(void) -{ - if (m1sdr_Callback) - { - printf("Requesting %i\n", nDSoundSegLen); - m1sdr_Callback(nDSoundSegLen, (INT16 *)samples); - } -} -// checks the play position to see if we should trigger another update - -void m1sdr_TimeCheck(void) -{ - m1sdr_Update(); - fwrite(samples, nDSoundSegLen*4, 1, fout); -} - -// m1sdr_Init - inits the output device and our global state - -INT16 m1sdr_Init(int sample_rate) -{ - nDSoundSegLen = 350; // ;sample_rate/60; - memset(samples, 0, 44100*4); // zero out samples - m1sdr_Callback = NULL; - - fout = fopen("output.raw", "wb"); -} - -void m1sdr_Exit(void) -{ - fclose(fout); -} - -void m1sdr_SetCallback(void *fn) -{ - if (fn == (void *)NULL) - { - printf("ERROR: NULL CALLBACK!\n"); - } - -// printf("m1sdr_SetCallback: aok!\n"); - m1sdr_Callback = (void (*)(unsigned long, signed short *))fn; -} - -void m1sdr_PlayStart(void) -{ -} - - diff --git a/Frameworks/AudioOverload/aosdk/license.txt b/Frameworks/AudioOverload/aosdk/license.txt deleted file mode 100644 index b700befa8..000000000 --- a/Frameworks/AudioOverload/aosdk/license.txt +++ /dev/null @@ -1,236 +0,0 @@ -Here is a list of the licenses each file in this package are under, and their text. - -The upshot is this: if you create anything from this SDK and include any MAME licensed components -(which are an integral part of each engine supplied) you must distribute the source code to your -derivative program. - - -===================================================================================== - -BSD license: - -Copyright (c) 2007-2009, R. Belmont and Richard Bannister. - -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. -* Neither the names of R. Belmont and Richard Bannister nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR -CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -===================================================================================== - -MAME license: - -Copyright (c) 1997-2008, Nicola Salmoria and the MAME team -All rights reserved. - -Redistribution and use of this code or any derivative works are permitted provided that the following conditions are met: - - * Redistributions may not be sold, nor may they be used in a commercial product or activity. - * Redistributions that are modified from the original source must include the complete source code, including the source code for all components used by a binary built from the modified sources. However, as a special exception, the source code distributed need not include anything that is normally distributed (in either source or binary form) with the major components (compiler, kernel, and so on) of the operating system on which the executable runs, unless that component itself accompanies the executable. - * Redistributions must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -===================================================================================== - -GPL license: - -Too long to include here. - -See eng_psf/peops/License.txt or eng_psf/peops2/License.txt for the complete text. - -While legally combining GPL with BSD and MAME licensed software is unclear, Pete Bernert -will probably be OK with anything you do as long as you distribute the source for your -AOSDK based creations. - -===================================================================================== - -ZLIB license: - -/* zlib.h -- interface of the 'zlib' general purpose compression library - version 1.2.2, October 3rd, 2004 - - Copyright (C) 1995-2004 Jean-loup Gailly and Mark Adler - - This software is provided 'as-is', without any express or implied - warranty. In no event will the authors be held liable for any damages - arising from the use of this software. - - Permission is granted to anyone to use this software for any purpose, - including commercial applications, and to alter it and redistribute it - freely, subject to the following restrictions: - - 1. The origin of this software must not be misrepresented; you must not - claim that you wrote the original software. If you use this software - in a product, an acknowledgment in the product documentation would be - appreciated but is not required. - 2. Altered source versions must be plainly marked as such, and must not be - misrepresented as being the original software. - 3. This notice may not be removed or altered from any source distribution. - - Jean-loup Gailly jloup@gzip.org - Mark Adler madler@alumni.caltech.edu - -*/ - -===================================================================================== - -List of files and their licenses: - -ao.h BSD -corlett.c BSD -corlett.h BSD -cpuintrf.h BSD -dsnd.c BSD -eng_protos.h BSD -main.c BSD -Makefile BSD -mem.h BSD -osd_cpu.h MAME -oss.c BSD -oss.h BSD - -eng_dsf: - -aica.c MAME -aica.h MAME -aicadsp.c MAME -aicadsp.h MAME -aicalfo.c MAME -arm7.c MAME -arm7.h MAME -arm7i.c MAME -arm7i.h MAME -arm7memil.c MAME -eng_dsf.c BSD -dc_hw.c BSD -dc_hw.h BSD - -eng_qsf: - -eng_qsf.c BSD -kabuki.c MAME -qsound.c MAME -qsound.h MAME -z80.c MAME -z80dasm.c MAME -z80dasm.h MAME -z80.h MAME - -eng_ssf: - -eng_ssf.c BSD -m68kconf.h MAME -m68kcpu.c MAME -m68kcpu.h MAME -m68k.h MAME -m68k_in.c MAME -m68kmake.c MAME -m68kmame.h MAME -m68kopac.c MAME -m68kopdm.c MAME -m68kopnz.c MAME -m68kops.c MAME -m68kops.h MAME -sat_hw.c BSD -sat_hw.h BSD -scsp.c MAME -scspdsp.c MAME -scspdsp.h MAME -scsp.h MAME -scsplfo.c MAME - -eng_psf: - -eng_psf2.c BSD -eng_psf.c BSD -eng_spu.c BSD -psx_hw.c BSD -psx.c MAME -psx.h MAME -cpuintrf.h MAME -mamemem.h MAME - -eng_psf/peops: - -adsr.c GPL -adsr.h GPL -dma.c GPL -dma.h GPL -externals.h GPL -gauss_i.h GPL -registers.c GPL -registers.h GPL -regs.h GPL -reverb.c GPL -spu.c GPL -spu.h GPL -stdafx.h GPL - - -eng_psf/peops2: - -adsr.c GPL -adsr.h GPL -dma.c GPL -dma.h GPL -externals.h GPL -gauss_i.h GPL -psemuxa.h GPL -registers.c GPL -registers.h GPL -regs.h GPL -reverb.c GPL -reverb.h GPL -spu.c GPL -spu.h GPL -stdafx.h GPL -xa.c GPL - - - -zlib: - -adler32.c ZLIB -compress.c ZLIB -crc32.c ZLIB -crc32.h ZLIB -crypt.h ZLIB -deflate.c ZLIB -deflate.h ZLIB -gzio.c ZLIB -infback.c ZLIB -inffast.c ZLIB -inffast.h ZLIB -inffixed.h ZLIB -inflate.c ZLIB -inflate.h ZLIB -inftrees.c ZLIB -inftrees.h ZLIB -ioapi.c ZLIB -ioapi.h ZLIB -trees.c ZLIB -trees.h ZLIB -uncompr.c ZLIB -unzip.c ZLIB -unzip.h ZLIB -zconf.h ZLIB -zlib.h ZLIB -zutil.c ZLIB -zutil.h ZLIB - diff --git a/Frameworks/AudioOverload/aosdk/main.c b/Frameworks/AudioOverload/aosdk/main.c deleted file mode 100644 index 2382c5154..000000000 --- a/Frameworks/AudioOverload/aosdk/main.c +++ /dev/null @@ -1,195 +0,0 @@ -/* - Audio Overload SDK - main driver. for demonstration only, not user friendly! - - Copyright (c) 2007-2009 R. Belmont and Richard Bannister. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - * Neither the names of R. Belmont and Richard Bannister nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#include -#include -#include - -#include "ao.h" -#include "eng_protos.h" - -/* file types */ -static uint32 type; - -static struct -{ - uint32 sig; - char *name; - int32 (*start)(uint8 *, uint32); - int32 (*gen)(int16 *, uint32); - int32 (*stop)(void); - int32 (*command)(int32, int32); - uint32 rate; - int32 (*fillinfo)(ao_display_info *); -} types[] = { - { 0x50534641, "Capcom QSound (.qsf)", qsf_start, qsf_gen, qsf_stop, qsf_command, 60, qsf_fill_info }, - { 0x50534611, "Sega Saturn (.ssf)", ssf_start, ssf_gen, ssf_stop, ssf_command, 60, ssf_fill_info }, - { 0x50534601, "Sony PlayStation (.psf)", psf_start, psf_gen, psf_stop, psf_command, 60, psf_fill_info }, - { 0x53505500, "Sony PlayStation (.spu)", spu_start, spu_gen, spu_stop, spu_command, 60, spu_fill_info }, - { 0x50534602, "Sony PlayStation 2 (.psf2)", psf2_start, psf2_gen, psf2_stop, psf2_command, 60, psf2_fill_info }, - { 0x50534612, "Sega Dreamcast (.dsf)", dsf_start, dsf_gen, dsf_stop, dsf_command, 60, dsf_fill_info }, - - { 0xffffffff, "", NULL, NULL, NULL, NULL, 0, NULL } -}; - -/* redirect stubs to interface the Z80 core to the QSF engine */ -uint8 memory_read(uint16 addr) -{ - return qsf_memory_read(addr); -} - -uint8 memory_readop(uint16 addr) -{ - return memory_read(addr); -} - -uint8 memory_readport(uint16 addr) -{ - return qsf_memory_readport(addr); -} - -void memory_write(uint16 addr, uint8 byte) -{ - qsf_memory_write(addr, byte); -} - -void memory_writeport(uint16 addr, uint8 byte) -{ - qsf_memory_writeport(addr, byte); -} - - -static int (*ao_get_lib_callback)(char *filename, uint8 **buffer, uint64 *length) = NULL; - -// ao_get_lib: called to load secondary files -int ao_get_lib(char *filename, uint8 **buffer, uint64 *length) -{ - return (*ao_get_lib_callback)(filename, buffer, length); -} - -void ao_set_get_lib_callback(int (*callback)(char *filename, uint8 **buffer, uint64 *length)) { - ao_get_lib_callback = callback; -} - - -/* -int main(int argv, char *argc[]) -{ - FILE *file; - uint8 *buffer; - uint32 size, filesig; - - printf("AOSDK test program v1.0 by R. Belmont [AOSDK release 1.4.8]\nCopyright (c) 2007-2009 R. Belmont and Richard Bannister - please read license.txt for license details\n\n"); - - // check if an argument was given - if (argv < 2) - { - printf("Error: must specify a filename!\n"); - return -1; - } - - file = fopen(argc[1], "rb"); - - if (!file) - { - printf("ERROR: could not open file %s\n", argc[1]); - return -1; - } - - // get the length of the file by seeking to the end then reading the current position - fseek(file, 0, SEEK_END); - size = ftell(file); - // reset the pointer - fseek(file, 0, SEEK_SET); - - buffer = malloc(size); - - if (!buffer) - { - fclose(file); - printf("ERROR: could not allocate %d bytes of memory\n", size); - return -1; - } - - // read the file - fread(buffer, size, 1, file); - fclose(file); - - // now try to identify the file - type = 0; - filesig = buffer[0]<<24 | buffer[1]<<16 | buffer[2]<<8 | buffer[3]; - while (types[type].sig != 0xffffffff) - { - if (filesig == types[type].sig) - { - break; - } - else - { - type++; - } - } - - // now did we identify it above or just fall through? - if (types[type].sig != 0xffffffff) - { - printf("File identified as %s\n", types[type].name); - } - else - { - printf("ERROR: File is unknown, signature bytes are %02x %02x %02x %02x\n", buffer[0], buffer[1], buffer[2], buffer[3]); - free(buffer); - return -1; - } - - if ((*types[type].start)(buffer, size) != AO_SUCCESS) - { - free(buffer); - printf("ERROR: Engine rejected file!\n"); - return -1; - } - - m1sdr_Init(44100); - m1sdr_SetCallback(do_frame); - m1sdr_PlayStart(); - - printf("\n\nPlaying. Press CTRL-C to stop.\n"); - - while (1) - { - m1sdr_TimeCheck(); - } - - free(buffer); - - return 1; -} -*/ - -// stub for MAME stuff -int change_pc(int foo) -{ -} diff --git a/Frameworks/AudioOverload/aosdk/main_original.c b/Frameworks/AudioOverload/aosdk/main_original.c deleted file mode 100644 index 2a8ef5855..000000000 --- a/Frameworks/AudioOverload/aosdk/main_original.c +++ /dev/null @@ -1,220 +0,0 @@ -/* - Audio Overload SDK - main driver. for demonstration only, not user friendly! - - Copyright (c) 2007-2009 R. Belmont and Richard Bannister. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - * Neither the names of R. Belmont and Richard Bannister nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#include -#include -#include - -#include "ao.h" -#include "eng_protos.h" - -/* file types */ -static uint32 type; - -static struct -{ - uint32 sig; - char *name; - int32 (*start)(uint8 *, uint32); - int32 (*gen)(int16 *, uint32); - int32 (*stop)(void); - int32 (*command)(int32, int32); - uint32 rate; - int32 (*fillinfo)(ao_display_info *); -} types[] = { - { 0x50534641, "Capcom QSound (.qsf)", qsf_start, qsf_gen, qsf_stop, qsf_command, 60, qsf_fill_info }, - { 0x50534611, "Sega Saturn (.ssf)", ssf_start, ssf_gen, ssf_stop, ssf_command, 60, ssf_fill_info }, - { 0x50534601, "Sony PlayStation (.psf)", psf_start, psf_gen, psf_stop, psf_command, 60, psf_fill_info }, - { 0x53505500, "Sony PlayStation (.spu)", spu_start, spu_gen, spu_stop, spu_command, 60, spu_fill_info }, - { 0x50534602, "Sony PlayStation 2 (.psf2)", psf2_start, psf2_gen, psf2_stop, psf2_command, 60, psf2_fill_info }, - { 0x50534612, "Sega Dreamcast (.dsf)", dsf_start, dsf_gen, dsf_stop, dsf_command, 60, dsf_fill_info }, - - { 0xffffffff, "", NULL, NULL, NULL, NULL, 0, NULL } -}; - -/* redirect stubs to interface the Z80 core to the QSF engine */ -uint8 memory_read(uint16 addr) -{ - return qsf_memory_read(addr); -} - -uint8 memory_readop(uint16 addr) -{ - return memory_read(addr); -} - -uint8 memory_readport(uint16 addr) -{ - return qsf_memory_readport(addr); -} - -void memory_write(uint16 addr, uint8 byte) -{ - qsf_memory_write(addr, byte); -} - -void memory_writeport(uint16 addr, uint8 byte) -{ - qsf_memory_writeport(addr, byte); -} - -/* ao_get_lib: called to load secondary files */ -int ao_get_lib(char *filename, uint8 **buffer, uint64 *length) -{ - uint8 *filebuf; - uint32 size; - FILE *auxfile; - - auxfile = fopen(filename, "rb"); - if (!auxfile) - { - printf("Unable to find auxiliary file %s\n", filename); - return AO_FAIL; - } - - fseek(auxfile, 0, SEEK_END); - size = ftell(auxfile); - fseek(auxfile, 0, SEEK_SET); - - filebuf = malloc(size); - - if (!filebuf) - { - fclose(auxfile); - printf("ERROR: could not allocate %d bytes of memory\n", size); - return AO_FAIL; - } - - fread(filebuf, size, 1, auxfile); - fclose(auxfile); - - *buffer = filebuf; - *length = (uint64)size; - - return AO_SUCCESS; -} - -static void do_frame(uint32 size, int16 *buffer) -{ - (*types[type].gen)(buffer, size); -} - -int main(int argv, char *argc[]) -{ - FILE *file; - uint8 *buffer; - uint32 size, filesig; - - printf("AOSDK test program v1.0 by R. Belmont [AOSDK release 1.4.8]\nCopyright (c) 2007-2009 R. Belmont and Richard Bannister - please read license.txt for license details\n\n"); - - // check if an argument was given - if (argv < 2) - { - printf("Error: must specify a filename!\n"); - return -1; - } - - file = fopen(argc[1], "rb"); - - if (!file) - { - printf("ERROR: could not open file %s\n", argc[1]); - return -1; - } - - // get the length of the file by seeking to the end then reading the current position - fseek(file, 0, SEEK_END); - size = ftell(file); - // reset the pointer - fseek(file, 0, SEEK_SET); - - buffer = malloc(size); - - if (!buffer) - { - fclose(file); - printf("ERROR: could not allocate %d bytes of memory\n", size); - return -1; - } - - // read the file - fread(buffer, size, 1, file); - fclose(file); - - // now try to identify the file - type = 0; - filesig = buffer[0]<<24 | buffer[1]<<16 | buffer[2]<<8 | buffer[3]; - while (types[type].sig != 0xffffffff) - { - if (filesig == types[type].sig) - { - break; - } - else - { - type++; - } - } - - // now did we identify it above or just fall through? - if (types[type].sig != 0xffffffff) - { - printf("File identified as %s\n", types[type].name); - } - else - { - printf("ERROR: File is unknown, signature bytes are %02x %02x %02x %02x\n", buffer[0], buffer[1], buffer[2], buffer[3]); - free(buffer); - return -1; - } - - if ((*types[type].start)(buffer, size) != AO_SUCCESS) - { - free(buffer); - printf("ERROR: Engine rejected file!\n"); - return -1; - } - - m1sdr_Init(44100); - m1sdr_SetCallback(do_frame); - m1sdr_PlayStart(); - - printf("\n\nPlaying. Press CTRL-C to stop.\n"); - - while (1) - { - m1sdr_TimeCheck(); - } - - free(buffer); - - return 1; -} - -// stub for MAME stuff -int change_pc(int foo) -{ -} diff --git a/Frameworks/AudioOverload/aosdk/mem.h b/Frameworks/AudioOverload/aosdk/mem.h deleted file mode 100644 index 8fac19880..000000000 --- a/Frameworks/AudioOverload/aosdk/mem.h +++ /dev/null @@ -1,22 +0,0 @@ -// -// Audio Overload -// Emulated music player -// -// (C) 2000-2008 Richard F. Bannister -// - -// mem.h - -uint8 memory_read(uint16 addr); -uint8 memory_readop(uint16 addr); -uint8 memory_readport(uint16 addr); -void memory_write(uint16 addr, uint8 byte); -void memory_writeport(uint16 addr, uint8 byte); - -uint8 dc_read8(uint32 addr); -uint16 dc_read16(uint32 addr); -uint32 dc_read32(uint32 addr); -void dc_write8(uint32 addr, uint8 byte); -void dc_write16(uint32 addr, uint16 word); -void dc_write32(uint32 addr, uint32 dword); - diff --git a/Frameworks/AudioOverload/aosdk/osd_cpu.h b/Frameworks/AudioOverload/aosdk/osd_cpu.h deleted file mode 100644 index da74a0d42..000000000 --- a/Frameworks/AudioOverload/aosdk/osd_cpu.h +++ /dev/null @@ -1,70 +0,0 @@ -/******************************************************************************* -* * -* Define size independent data types and operations. * -* * -* The following types must be supported by all platforms: * -* * -* UINT8 - Unsigned 8-bit Integer INT8 - Signed 8-bit integer * -* UINT16 - Unsigned 16-bit Integer INT16 - Signed 16-bit integer * -* UINT32 - Unsigned 32-bit Integer INT32 - Signed 32-bit integer * -* UINT64 - Unsigned 64-bit Integer INT64 - Signed 64-bit integer * -* * -* * -* The macro names for the artithmatic operations are composed as follows: * -* * -* XXX_R_A_B, where XXX - 3 letter operation code (ADD, SUB, etc.) * -* R - The type of the result * -* A - The type of operand 1 * -* B - The type of operand 2 (if binary operation) * -* * -* Each type is one of: U8,8,U16,16,U32,32,U64,64 * -* * -*******************************************************************************/ - - -#ifndef OSD_CPU_H -#define OSD_CPU_H - -#include "ao.h" - -/* Combine two 32-bit integers into a 64-bit integer */ -#define COMBINE_64_32_32(A,B) ((((UINT64)(A))<<32) | (UINT32)(B)) -#define COMBINE_U64_U32_U32(A,B) COMBINE_64_32_32(A,B) - -/* Return upper 32 bits of a 64-bit integer */ -#define HI32_32_64(A) (((UINT64)(A)) >> 32) -#define HI32_U32_U64(A) HI32_32_64(A) - -/* Return lower 32 bits of a 64-bit integer */ -#define LO32_32_64(A) ((A) & 0xffffffff) -#define LO32_U32_U64(A) LO32_32_64(A) - -#define DIV_64_64_32(A,B) ((A)/(B)) -#define DIV_U64_U64_U32(A,B) ((A)/(UINT32)(B)) - -#define MOD_32_64_32(A,B) ((A)%(B)) -#define MOD_U32_U64_U32(A,B) ((A)%(UINT32)(B)) - -#define MUL_64_32_32(A,B) ((A)*(INT64)(B)) -#define MUL_U64_U32_U32(A,B) ((A)*(UINT64)(UINT32)(B)) - - -/****************************************************************************** - * Union of UINT8, UINT16 and UINT32 in native endianess of the target - * This is used to access bytes and words in a machine independent manner. - * The upper bytes h2 and h3 normally contain zero (16 bit CPU cores) - * thus PAIR.d can be used to pass arguments to the memory system - * which expects 'int' really. - ******************************************************************************/ -typedef union { -#if LSB_FIRST - struct { UINT8 l,h,h2,h3; } b; - struct { UINT16 l,h; } w; -#else - struct { UINT8 h3,h2,h,l; } b; - struct { UINT16 h,l; } w; -#endif - UINT32 d; -} PAIR; - -#endif /* defined OSD_CPU_H */ diff --git a/Frameworks/AudioOverload/aosdk/oss.c b/Frameworks/AudioOverload/aosdk/oss.c deleted file mode 100644 index a85a2eaa6..000000000 --- a/Frameworks/AudioOverload/aosdk/oss.c +++ /dev/null @@ -1,290 +0,0 @@ -/* - - Audio Overload SDK - - Copyright (c) 2007, R. Belmont and Richard Bannister. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - * Neither the names of R. Belmont and Richard Bannister nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF - LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "ao.h" -#include "oss.h" - -#define LOG_WAVE (0) -#define VALGRIND (0) - -#define NUM_FRAGS_BROKEN (8) -#define NUM_FRAGS_NORMAL (4) -static INT32 num_frags; -#define OSS_FRAGMENT (0x000D | (num_frags<<16)); // 16k fragments (2 * 2^14). - -// local variables - -void (*m1sdr_Callback)(unsigned long dwNumSamples, signed short *data); -unsigned long cbUserData; - -static int hw_present; - -static INT32 is_broken_driver; -int nDSoundSegLen = 0; -int oss_nw = 0; - -int audiofd; -#if LOG_WAVE -FILE *logfil; -#endif - -static int playtime = 0; - -static INT16 samples[44100*2]; - - -// set # of samples per update - -void m1sdr_SetSamplesPerTick(UINT32 spf) -{ - nDSoundSegLen = spf; -} - -// m1sdr_Update - timer callback routine: runs sequencer and mixes sound - -void m1sdr_Update(void) -{ - if (!hw_present) return; - - if (m1sdr_Callback) - { - m1sdr_Callback(nDSoundSegLen, (INT16 *)samples); - } -} -// checks the play position to see if we should trigger another update - -void m1sdr_TimeCheck(void) -{ -#if VALGRIND - m1sdr_Update(); -#else - audio_buf_info info; - - ioctl(audiofd, SNDCTL_DSP_GETOSPACE, &info); - - if (oss_nw) - { - int err; - - m1sdr_Update(); - playtime++; - - // output the generated samples - err = write(audiofd, samples, nDSoundSegLen * 4); - if (err == -1) - { - perror("write\n"); - } - - #if LOG_WAVE - fwrite(samples, nDSoundSegLen*4, 1, logfil); - #endif - } - else - { - while (info.bytes >= (nDSoundSegLen * 4)) - { - m1sdr_Update(); - playtime++; - - // output the generated samples - write(audiofd, samples, nDSoundSegLen * 4); - - #if LOG_WAVE - fwrite(samples, nDSoundSegLen*4, 1, logfil); - #endif - - ioctl(audiofd, SNDCTL_DSP_GETOSPACE, &info); - } - } - - usleep(50); -#endif -} - -// m1sdr_Init - inits the output device and our global state - -INT16 m1sdr_Init(int sample_rate) -{ - int format, stereo, rate, fsize; - - hw_present = 0; - - nDSoundSegLen = sample_rate / 60; - - memset(samples, 0, 44100*4); // zero out samples - - m1sdr_Callback = NULL; - - audiofd = open("/dev/dsp", O_WRONLY, 0); - if (audiofd == -1) - { - perror("/dev/dsp"); - - audiofd = open("/dev/dsp1", O_WRONLY, 0); - - if (audiofd == -1) - { - perror("/dev/dsp1"); - return(0); - } - } - - // reset things - ioctl(audiofd, SNDCTL_DSP_RESET, 0); - - is_broken_driver = 0; - num_frags = NUM_FRAGS_NORMAL; - - // set the buffer size we want - fsize = OSS_FRAGMENT; - if (ioctl(audiofd, SNDCTL_DSP_SETFRAGMENT, &fsize) == - 1) - { - perror("SNDCTL_DSP_SETFRAGMENT"); - return(0); - } - - // set 16-bit output - format = AFMT_S16_NE; // 16 bit signed "native"-endian - if (ioctl(audiofd, SNDCTL_DSP_SETFMT, &format) == - 1) - { - perror("SNDCTL_DSP_SETFMT"); - return(0); - } - - // now set stereo - stereo = 1; - if (ioctl(audiofd, SNDCTL_DSP_STEREO, &stereo) == - 1) - { - perror("SNDCTL_DSP_STEREO"); - return(0); - } - - // and the sample rate - rate = sample_rate; - if (ioctl(audiofd, SNDCTL_DSP_SPEED, &rate) == - 1) - { - perror("SNDCTL_DSP_SPEED"); - return(0); - } - - // and make sure that did what we wanted - ioctl(audiofd, SNDCTL_DSP_GETBLKSIZE, &fsize); - //printf("Fragment size: %d\n", fsize); - - hw_present = 1; - -#if LOG_WAVE - logfil = fopen("log.bin", "wb"); -#endif - - return (1); -} - -void m1sdr_Exit(void) -{ - if (!hw_present) return; - - close(audiofd); -#if LOG_WAVE - fclose(logfil); -#endif -} - -void m1sdr_SetCallback(void *fn) -{ - if (fn == (void *)NULL) - { - printf("ERROR: NULL CALLBACK!\n"); - } - -// printf("m1sdr_SetCallback: aok!\n"); - m1sdr_Callback = (void (*)(unsigned long, signed short *))fn; -} - -INT16 m1sdr_IsThere(void) -{ - audiofd = open("/dev/dsp", O_WRONLY, 0); - - if (audiofd == -1) - { - printf("Error accessing soundcard, sound will be disabled\n"); - hw_present = 0; - return(0); - } - - close(audiofd); - hw_present = 1; - return (1); -} - -INT32 m1sdr_HwPresent(void) -{ - return hw_present; -} - -// unused stubs for this driver, but the Win32 driver needs them -void m1sdr_PlayStart(void) -{ - playtime = 0; -} - -void m1sdr_PlayStop(void) -{ -} - -void m1sdr_FlushAudio(void) -{ - memset(samples, 0, nDSoundSegLen * 4); - write(audiofd, samples, nDSoundSegLen * 4); - write(audiofd, samples, nDSoundSegLen * 4); -} - -void m1sdr_SetNoWait(int nw) -{ - oss_nw = nw; -} - -short *m1sdr_GetSamples(void) -{ - return samples; -} - -int m1sdr_GetPlayTime(void) -{ - return playtime; -} - diff --git a/Frameworks/AudioOverload/aosdk/oss.h b/Frameworks/AudioOverload/aosdk/oss.h deleted file mode 100644 index 3a46a4ed6..000000000 --- a/Frameworks/AudioOverload/aosdk/oss.h +++ /dev/null @@ -1,27 +0,0 @@ -#ifndef _OSS_H_ -#define _OSS_H_ - -extern int audiofd; -extern void (*m1sdr_Callback)(unsigned long dwUser, signed short *smp); -extern unsigned long cbUserData; - -// function protos - -void m1sdr_Update(void); -INT16 m1sdr_Init(int sample_rate); -void m1sdr_Exit(void); -void m1sdr_PlayStart(void); -void m1sdr_PlayStop(void); -INT16 m1sdr_IsThere(void); -void m1sdr_TimeCheck(void); -void m1sdr_SetSamplesPerTick(UINT32 spf); -void m1sdr_SetHz(UINT32 hz); -void m1sdr_SetCallback(void *fn); -void m1sdr_SetCPUHog(int hog); -INT32 m1sdr_HwPresent(void); -void m1sdr_FlushAudio(void); -void m1sdr_Pause(int); -void m1sdr_SetNoWait(int nw); -short *m1sdr_GetSamples(void); -int m1sdr_GetPlayTime(void); -#endif diff --git a/Frameworks/AudioOverload/aosdk/readme.txt b/Frameworks/AudioOverload/aosdk/readme.txt deleted file mode 100644 index 26fcbcb1a..000000000 --- a/Frameworks/AudioOverload/aosdk/readme.txt +++ /dev/null @@ -1,81 +0,0 @@ -Audio Overload SDK - Development Release 1.4.8 February 15, 2009 - -Copyright (c) 2007-2009 R. Belmont and Richard Bannister. -All rights reserved. -========================================================= - -Please refer to license.txt for the specific licensing details of this software. - -This SDK opens up some of the music file format engines developed for the Audio Overload project. -You may use this code to play the formats on systems we don't support or inside of applications -other than AO. - -Configurables in the makefile: - -- Uncomment the line that defines LONG_IS_64BIT for compilation on 64-bit Linux, *BSD, and other operating -systems using the AMD64 recommended ABI (not 64-bit Windows). - -- Change LSB_FIRST=1 to =0 for big-endian platforms. - -New in Release 1.4.8 -- Guard against invalid data sometimes created by makessf.py (fixes crashing Pebble Beach ST-V rips) - - -Entry points of an AO engine are as follows: - -int32 XXX_start(uint8 *, uint32) - -This function attempts to recognize and load a file of a specific type. It is assumed external code has -already checked the file's signature in cases where that's possible. The first parameter is a pointer to -the entire file in memory, and the second is the length of the file. The return value is AO_SUCCESS if -the engine properly loaded the file and AO_FAIL if it didn't. - - -int32 XXX_gen(int16 *, uint32) - -This function actually plays the song and generates signed 16-bit stereo samples at 44100 Hz. The first -parameter is a pointer to a buffer in which to place the samples (stereo interleaved), and the second is -the number of stereo samples to generate (so the output buffer size must be (number of samples) * 2 * 2 -bytes in length). - - -int32 XXX_stop(void) - -This function ceases playback and cleans up the engine. You must call _start again after this to play more -music. - - -int32 XXX_command(int32, int32) - -For some engines, this allows you to send commands while a song is playing. The first parameter is the -command (these are defined in ao.h), the second is the parameter. These commands are as follows: - -COMMAND_PREV (parameter ignored) - for file formats which have more than one song in a file (NSF), this -moves back one song. - -COMMAND_NEXT (parameter ignored) - for file formats which have more than one song in a file (NSF), this -moves forward one song. - -COMMAND_RESTART (parameter ignored) - Restarts the current song from the beginning. Not supported by -all engines. - -COMMAND_HAS_PREV (parameter ignored) - for file formats which have more than one song in a file (NSF), -this checks if moving backwards from the current song is a valid operation. (Returns AO_FAIL if not) - -COMMAND_HAS_NEXT (parameter ignored) - for file formats which have more than one song in a file (NSF), -this checks if moving forward from the current song is a valid operation. (Returns AO_FAIL if not) - -COMMAND_GET_MIN (parameter ignored) - for file formats which have more than one song in a file (NSF), -this returns the lowest valid song number. - -COMMAND_GET_MAX (parameter ignored) - for file formats which have more than one song in a file (NSF), -this returns the highest valid song number. - -COMAND_JUMP - for file formats which have more than one song in a file (NSF), this command jumps directly -to a specific song number, which is passed in as the parameter. - - -int32 XXX_fillinfo(ao_display_info *) - -This function fills out the ao_display_info struct (see ao.h for details) with information about the currently -playing song. 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CFBundleVersion - 1.0 + 1 + NSHumanReadableCopyright + Copyright © 2013 Christopher Snowhill. All rights reserved. NSPrincipalClass diff --git a/Frameworks/HighlyAdvanced/HighlyAdvanced/en.lproj/InfoPlist.strings b/Frameworks/HighlyAdvanced/HighlyAdvanced/en.lproj/InfoPlist.strings new file mode 100644 index 000000000..477b28ff8 --- /dev/null +++ b/Frameworks/HighlyAdvanced/HighlyAdvanced/en.lproj/InfoPlist.strings @@ -0,0 +1,2 @@ +/* Localized versions of Info.plist keys */ + diff --git a/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/License.txt b/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/License.txt new file mode 100644 index 000000000..8969d279c --- /dev/null +++ b/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/License.txt @@ -0,0 +1,28 @@ +Copyright for all files in trunk/src excluding gb_apu +or when stated otherwise in the source file: + VisualBoyAdvance - Nintendo Gameboy/GameboyAdvance (TM) emulator + Copyright (C) 1999-2003 Forgotten + Copyright (C) 2004-2006 Forgotten and the VBA development team + +Copyright for the modifications to the files mentioned above: + VisualBoyAdvance-M GB/GBA emulator + Copyright (C) 2007-2008 VBA-M development team + + +All files excluding gb_apu, modified files from zlib +or when stated otherwise in the source file +are distributed under the GNU GPL v2: + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or(at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software Foundation, +Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. diff --git a/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/apu/Blip_Buffer.cpp b/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/apu/Blip_Buffer.cpp new file mode 100644 index 000000000..ea5860c51 --- /dev/null +++ b/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/apu/Blip_Buffer.cpp @@ -0,0 +1,469 @@ +// Blip_Buffer 0.4.1. http://www.slack.net/~ant/ + +#include +#include +#include +#include +#include + +#include "Blip_Buffer.h" + +/* Copyright (C) 2003-2007 Shay Green. This module is free software; you +can redistribute it and/or modify it under the terms of the GNU Lesser +General Public License as published by the Free Software Foundation; either +version 2.1 of the License, or (at your option) any later version. This +module is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more +details. You should have received a copy of the GNU Lesser General Public +License along with this module; if not, write to the Free Software Foundation, +Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ + +// TODO: use scoped for variables in treble_eq() + +#ifdef BLARGG_ENABLE_OPTIMIZER + #include BLARGG_ENABLE_OPTIMIZER +#endif + +namespace GBA { + +int const silent_buf_size = 1; // size used for Silent_Blip_Buffer + +Blip_Buffer::Blip_Buffer() +{ + factor_ = LONG_MAX; + buffer_ = 0; + buffer_size_ = 0; + sample_rate_ = 0; + bass_shift_ = 0; + clock_rate_ = 0; + bass_freq_ = 16; + length_ = 0; + + // assumptions code makes about implementation-defined features + #ifndef NDEBUG + // right shift of negative value preserves sign + buf_t_ i = -0x7FFFFFFE; + assert( (i >> 1) == -0x3FFFFFFF ); + + // casting to short truncates to 16 bits and sign-extends + i = 0x18000; + assert( (short) i == -0x8000 ); + #endif + + clear(); +} + +Blip_Buffer::~Blip_Buffer() +{ + if ( buffer_size_ != silent_buf_size ) + free( buffer_ ); +} + +Silent_Blip_Buffer::Silent_Blip_Buffer() +{ + factor_ = 0; + buffer_ = buf; + buffer_size_ = silent_buf_size; + clear(); +} + +void Blip_Buffer::clear( int entire_buffer ) +{ + offset_ = 0; + reader_accum_ = 0; + modified_ = 0; + if ( buffer_ ) + { + long count = (entire_buffer ? buffer_size_ : samples_avail()); + memset( buffer_, 0, (count + blip_buffer_extra_) * sizeof (buf_t_) ); + } +} + +Blip_Buffer::blargg_err_t Blip_Buffer::set_sample_rate( long new_rate, int msec ) +{ + if ( buffer_size_ == silent_buf_size ) + { + assert( 0 ); + return "Internal (tried to resize Silent_Blip_Buffer)"; + } + + // start with maximum length that resampled time can represent + long new_size = (ULONG_MAX >> BLIP_BUFFER_ACCURACY) - blip_buffer_extra_ - 64; + if ( msec != blip_max_length ) + { + long s = (new_rate * (msec + 1) + 999) / 1000; + if ( s < new_size ) + new_size = s; + else + assert( 0 ); // fails if requested buffer length exceeds limit + } + + if ( buffer_size_ != new_size ) + { + void* p = realloc( buffer_, (new_size + blip_buffer_extra_) * sizeof *buffer_ ); + if ( !p ) + return "Out of memory"; + buffer_ = (buf_t_*) p; + } + + buffer_size_ = new_size; + assert( buffer_size_ != silent_buf_size ); // size should never happen to match this + + // update things based on the sample rate + sample_rate_ = new_rate; + length_ = new_size * 1000 / new_rate - 1; + if ( msec ) + assert( length_ == msec ); // ensure length is same as that passed in + + // update these since they depend on sample rate + if ( clock_rate_ ) + clock_rate( clock_rate_ ); + bass_freq( bass_freq_ ); + + clear(); + + return 0; // success +} + +blip_resampled_time_t Blip_Buffer::clock_rate_factor( long rate ) const +{ + double ratio = (double) sample_rate_ / rate; + blip_long factor = (blip_long) floor( ratio * (1L << BLIP_BUFFER_ACCURACY) + 0.5 ); + assert( factor > 0 || !sample_rate_ ); // fails if clock/output ratio is too large + return (blip_resampled_time_t) factor; +} + +void Blip_Buffer::bass_freq( int freq ) +{ + bass_freq_ = freq; + int shift = 31; + if ( freq > 0 ) + { + shift = 13; + long f = (freq << 16) / sample_rate_; + while ( (f >>= 1) && --shift ) { } + } + bass_shift_ = shift; +} + +void Blip_Buffer::end_frame( blip_time_t t ) +{ + offset_ += t * factor_; + assert( samples_avail() <= (long) buffer_size_ ); // fails if time is past end of buffer +} + +long Blip_Buffer::count_samples( blip_time_t t ) const +{ + blip_resampled_time_t last_sample = resampled_time( t ) >> BLIP_BUFFER_ACCURACY; + blip_resampled_time_t first_sample = offset_ >> BLIP_BUFFER_ACCURACY; + return long (last_sample - first_sample); +} + +blip_time_t Blip_Buffer::count_clocks( long count ) const +{ + if ( !factor_ ) + { + assert( 0 ); // sample rate and clock rates must be set first + return 0; + } + + if ( count > buffer_size_ ) + count = buffer_size_; + blip_resampled_time_t time = (blip_resampled_time_t) count << BLIP_BUFFER_ACCURACY; + return (blip_time_t) ((time - offset_ + factor_ - 1) / factor_); +} + +void Blip_Buffer::remove_samples( long count ) +{ + if ( count ) + { + remove_silence( count ); + + // copy remaining samples to beginning and clear old samples + long remain = samples_avail() + blip_buffer_extra_; + memmove( buffer_, buffer_ + count, remain * sizeof *buffer_ ); + memset( buffer_ + remain, 0, count * sizeof *buffer_ ); + } +} + +// Blip_Synth_ + +Blip_Synth_Fast_::Blip_Synth_Fast_() +{ + buf = 0; + last_amp = 0; + delta_factor = 0; +} + +void Blip_Synth_Fast_::volume_unit( double new_unit ) +{ + delta_factor = int (new_unit * (1L << blip_sample_bits) + 0.5); +} + +#if !BLIP_BUFFER_FAST + +Blip_Synth_::Blip_Synth_( short* p, int w ) : + impulses( p ), + width( w ) +{ + volume_unit_ = 0.0; + kernel_unit = 0; + buf = 0; + last_amp = 0; + delta_factor = 0; +} + +#undef PI +#define PI 3.1415926535897932384626433832795029 + +static void gen_sinc( float* out, int count, double oversample, double treble, double cutoff ) +{ + if ( cutoff >= 0.999 ) + cutoff = 0.999; + + if ( treble < -300.0 ) + treble = -300.0; + if ( treble > 5.0 ) + treble = 5.0; + + double const maxh = 4096.0; + double const rolloff = pow( 10.0, 1.0 / (maxh * 20.0) * treble / (1.0 - cutoff) ); + double const pow_a_n = pow( rolloff, maxh - maxh * cutoff ); + double const to_angle = PI / 2 / maxh / oversample; + for ( int i = 0; i < count; i++ ) + { + double angle = ((i - count) * 2 + 1) * to_angle; + double c = rolloff * cos( (maxh - 1.0) * angle ) - cos( maxh * angle ); + double cos_nc_angle = cos( maxh * cutoff * angle ); + double cos_nc1_angle = cos( (maxh * cutoff - 1.0) * angle ); + double cos_angle = cos( angle ); + + c = c * pow_a_n - rolloff * cos_nc1_angle + cos_nc_angle; + double d = 1.0 + rolloff * (rolloff - cos_angle - cos_angle); + double b = 2.0 - cos_angle - cos_angle; + double a = 1.0 - cos_angle - cos_nc_angle + cos_nc1_angle; + + out [i] = (float) ((a * d + c * b) / (b * d)); // a / b + c / d + } +} + +void blip_eq_t::generate( float* out, int count ) const +{ + // lower cutoff freq for narrow kernels with their wider transition band + // (8 points->1.49, 16 points->1.15) + double oversample = blip_res * 2.25 / count + 0.85; + double half_rate = sample_rate * 0.5; + if ( cutoff_freq ) + oversample = half_rate / cutoff_freq; + double cutoff = rolloff_freq * oversample / half_rate; + + gen_sinc( out, count, blip_res * oversample, treble, cutoff ); + + // apply (half of) hamming window + double to_fraction = PI / (count - 1); + for ( int i = count; i--; ) + out [i] *= 0.54f - 0.46f * (float) cos( i * to_fraction ); +} + +void Blip_Synth_::adjust_impulse() +{ + // sum pairs for each phase and add error correction to end of first half + int const size = impulses_size(); + for ( int p = blip_res; p-- >= blip_res / 2; ) + { + int p2 = blip_res - 2 - p; + long error = kernel_unit; + for ( int i = 1; i < size; i += blip_res ) + { + error -= impulses [i + p ]; + error -= impulses [i + p2]; + } + if ( p == p2 ) + error /= 2; // phase = 0.5 impulse uses same half for both sides + impulses [size - blip_res + p] += (short) error; + //printf( "error: %ld\n", error ); + } + + //for ( int i = blip_res; i--; printf( "\n" ) ) + // for ( int j = 0; j < width / 2; j++ ) + // printf( "%5ld,", impulses [j * blip_res + i + 1] ); +} + +void Blip_Synth_::treble_eq( blip_eq_t const& eq ) +{ + float fimpulse [blip_res / 2 * (blip_widest_impulse_ - 1) + blip_res * 2]; + + int const half_size = blip_res / 2 * (width - 1); + eq.generate( &fimpulse [blip_res], half_size ); + + int i; + + // need mirror slightly past center for calculation + for ( i = blip_res; i--; ) + fimpulse [blip_res + half_size + i] = fimpulse [blip_res + half_size - 1 - i]; + + // starts at 0 + for ( i = 0; i < blip_res; i++ ) + fimpulse [i] = 0.0f; + + // find rescale factor + double total = 0.0; + for ( i = 0; i < half_size; i++ ) + total += fimpulse [blip_res + i]; + + //double const base_unit = 44800.0 - 128 * 18; // allows treble up to +0 dB + //double const base_unit = 37888.0; // allows treble to +5 dB + double const base_unit = 32768.0; // necessary for blip_unscaled to work + double rescale = base_unit / 2 / total; + kernel_unit = (long) base_unit; + + // integrate, first difference, rescale, convert to int + double sum = 0.0; + double next = 0.0; + int const size = this->impulses_size(); + for ( i = 0; i < size; i++ ) + { + impulses [i] = (short) (int) floor( (next - sum) * rescale + 0.5 ); + sum += fimpulse [i]; + next += fimpulse [i + blip_res]; + } + adjust_impulse(); + + // volume might require rescaling + double vol = volume_unit_; + if ( vol ) + { + volume_unit_ = 0.0; + volume_unit( vol ); + } +} + +void Blip_Synth_::volume_unit( double new_unit ) +{ + if ( new_unit != volume_unit_ ) + { + // use default eq if it hasn't been set yet + if ( !kernel_unit ) + treble_eq( -8.0 ); + + volume_unit_ = new_unit; + double factor = new_unit * (1L << blip_sample_bits) / kernel_unit; + + if ( factor > 0.0 ) + { + int shift = 0; + + // if unit is really small, might need to attenuate kernel + while ( factor < 2.0 ) + { + shift++; + factor *= 2.0; + } + + if ( shift ) + { + kernel_unit >>= shift; + assert( kernel_unit > 0 ); // fails if volume unit is too low + + // keep values positive to avoid round-towards-zero of sign-preserving + // right shift for negative values + long offset = 0x8000 + (1 << (shift - 1)); + long offset2 = 0x8000 >> shift; + for ( int i = impulses_size(); i--; ) + impulses [i] = (short) (int) (((impulses [i] + offset) >> shift) - offset2); + adjust_impulse(); + } + } + delta_factor = (int) floor( factor + 0.5 ); + //printf( "delta_factor: %d, kernel_unit: %d\n", delta_factor, kernel_unit ); + } +} +#endif + +long Blip_Buffer::read_samples( blip_sample_t* out_, long max_samples, int stereo ) +{ + long count = samples_avail(); + if ( count > max_samples ) + count = max_samples; + + if ( count ) + { + int const bass = BLIP_READER_BASS( *this ); + BLIP_READER_BEGIN( reader, *this ); + BLIP_READER_ADJ_( reader, count ); + blip_sample_t* BLIP_RESTRICT out = out_ + count; + blip_long offset = (blip_long) -count; + + if ( !stereo ) + { + do + { + blip_long s = BLIP_READER_READ( reader ); + BLIP_READER_NEXT_IDX_( reader, bass, offset ); + BLIP_CLAMP( s, s ); + out [offset] = (blip_sample_t) s; + } + while ( ++offset ); + } + else + { + do + { + blip_long s = BLIP_READER_READ( reader ); + BLIP_READER_NEXT_IDX_( reader, bass, offset ); + BLIP_CLAMP( s, s ); + out [offset * 2] = (blip_sample_t) s; + } + while ( ++offset ); + } + + BLIP_READER_END( reader, *this ); + + remove_samples( count ); + } + return count; +} + +void Blip_Buffer::mix_samples( blip_sample_t const* in, long count ) +{ + if ( buffer_size_ == silent_buf_size ) + { + assert( 0 ); + return; + } + + buf_t_* out = buffer_ + (offset_ >> BLIP_BUFFER_ACCURACY) + blip_widest_impulse_ / 2; + + int const sample_shift = blip_sample_bits - 16; + int prev = 0; + while ( count-- ) + { + blip_long s = (blip_long) *in++ << sample_shift; + *out += s - prev; + prev = s; + ++out; + } + *out -= prev; +} + +blip_ulong const subsample_mask = (1L << BLIP_BUFFER_ACCURACY) - 1; + +void Blip_Buffer::save_state( blip_buffer_state_t* out ) +{ + assert( samples_avail() == 0 ); + out->offset_ = offset_; + out->reader_accum_ = reader_accum_; + memcpy( out->buf, &buffer_ [offset_ >> BLIP_BUFFER_ACCURACY], sizeof out->buf ); +} + +void Blip_Buffer::load_state( blip_buffer_state_t const& in ) +{ + clear( false ); + + offset_ = in.offset_; + reader_accum_ = in.reader_accum_; + memcpy( buffer_, in.buf, sizeof in.buf ); +} + +} diff --git a/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/apu/Blip_Buffer.h b/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/apu/Blip_Buffer.h new file mode 100644 index 000000000..73648d853 --- /dev/null +++ b/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/apu/Blip_Buffer.h @@ -0,0 +1,560 @@ +// Band-limited sound synthesis buffer + +// Blip_Buffer 0.4.1 +#ifndef BLIP_BUFFER_H +#define BLIP_BUFFER_H + + // internal + #include + #if INT_MAX < 0x7FFFFFFF || LONG_MAX == 0x7FFFFFFF + typedef long blip_long; + typedef unsigned long blip_ulong; + #else + typedef int blip_long; + typedef unsigned blip_ulong; + #endif + +namespace GBA { + +// Time unit at source clock rate +typedef blip_long blip_time_t; + +// Output samples are 16-bit signed, with a range of -32768 to 32767 +typedef short blip_sample_t; +enum { blip_sample_max = 32767 }; + +struct blip_buffer_state_t; + +class Blip_Buffer { +public: + typedef const char* blargg_err_t; + + // Sets output sample rate and buffer length in milliseconds (1/1000 sec, defaults + // to 1/4 second) and clears buffer. If there isn't enough memory, leaves buffer + // untouched and returns "Out of memory", otherwise returns NULL. + blargg_err_t set_sample_rate( long samples_per_sec, int msec_length = 1000 / 4 ); + + // Sets number of source time units per second + void clock_rate( long clocks_per_sec ); + + // Ends current time frame of specified duration and makes its samples available + // (along with any still-unread samples) for reading with read_samples(). Begins + // a new time frame at the end of the current frame. + void end_frame( blip_time_t time ); + + // Reads at most 'max_samples' out of buffer into 'dest', removing them from + // the buffer. Returns number of samples actually read and removed. If stereo is + // true, increments 'dest' one extra time after writing each sample, to allow + // easy interleving of two channels into a stereo output buffer. + long read_samples( blip_sample_t* dest, long max_samples, int stereo = 0 ); + +// Additional features + + // Removes all available samples and clear buffer to silence. If 'entire_buffer' is + // false, just clears out any samples waiting rather than the entire buffer. + void clear( int entire_buffer = 1 ); + + // Number of samples available for reading with read_samples() + long samples_avail() const; + + // Removes 'count' samples from those waiting to be read + void remove_samples( long count ); + + // Sets frequency high-pass filter frequency, where higher values reduce bass more + void bass_freq( int frequency ); + + // Current output sample rate + long sample_rate() const; + + // Length of buffer in milliseconds + int length() const; + + // Number of source time units per second + long clock_rate() const; + +// Experimental features + + // Saves state, including high-pass filter and tails of last deltas. + // All samples must have been read from buffer before calling this. + void save_state( blip_buffer_state_t* out ); + + // Loads state. State must have been saved from Blip_Buffer with same + // settings during same run of program. States can NOT be stored on disk. + // Clears buffer before loading state. + void load_state( blip_buffer_state_t const& in ); + + // Number of samples delay from synthesis to samples read out + int output_latency() const; + + // Counts number of clocks needed until 'count' samples will be available. + // If buffer can't even hold 'count' samples, returns number of clocks until + // buffer becomes full. + blip_time_t count_clocks( long count ) const; + + // Number of raw samples that can be mixed within frame of specified duration. + long count_samples( blip_time_t duration ) const; + + // Mixes in 'count' samples from 'buf_in' + void mix_samples( blip_sample_t const* buf_in, long count ); + + + // Signals that sound has been added to buffer. Could be done automatically in + // Blip_Synth, but that would affect performance more, as you can arrange that + // this is called only once per time frame rather than for every delta. + void set_modified() { modified_ = this; } + + // not documented yet + blip_ulong unsettled() const; + Blip_Buffer* clear_modified() { Blip_Buffer* b = modified_; modified_ = 0; return b; } + void remove_silence( long count ); + typedef blip_ulong blip_resampled_time_t; + blip_resampled_time_t resampled_duration( int t ) const { return t * factor_; } + blip_resampled_time_t resampled_time( blip_time_t t ) const { return t * factor_ + offset_; } + blip_resampled_time_t clock_rate_factor( long clock_rate ) const; +public: + Blip_Buffer(); + ~Blip_Buffer(); + + // Deprecated + typedef blip_resampled_time_t resampled_time_t; + blargg_err_t sample_rate( long r ) { return set_sample_rate( r ); } + blargg_err_t sample_rate( long r, int msec ) { return set_sample_rate( r, msec ); } +private: + // noncopyable + Blip_Buffer( const Blip_Buffer& ); + Blip_Buffer& operator = ( const Blip_Buffer& ); +public: + typedef blip_long buf_t_; + blip_ulong factor_; + blip_resampled_time_t offset_; + buf_t_* buffer_; + blip_long buffer_size_; + blip_long reader_accum_; + int bass_shift_; +private: + long sample_rate_; + long clock_rate_; + int bass_freq_; + int length_; + Blip_Buffer* modified_; // non-zero = true (more optimal than using bool, heh) + friend class Blip_Reader; +}; + +#ifdef HAVE_CONFIG_H + #include "config.h" +#endif + +// Number of bits in resample ratio fraction. Higher values give a more accurate ratio +// but reduce maximum buffer size. +#ifndef BLIP_BUFFER_ACCURACY + #define BLIP_BUFFER_ACCURACY 16 +#endif + +// Number bits in phase offset. Fewer than 6 bits (64 phase offsets) results in +// noticeable broadband noise when synthesizing high frequency square waves. +// Affects size of Blip_Synth objects since they store the waveform directly. +#ifndef BLIP_PHASE_BITS + #if BLIP_BUFFER_FAST + #define BLIP_PHASE_BITS 8 + #else + #define BLIP_PHASE_BITS 6 + #endif +#endif + + // Internal + typedef blip_ulong blip_resampled_time_t; + int const blip_widest_impulse_ = 16; + int const blip_buffer_extra_ = blip_widest_impulse_ + 2; + int const blip_res = 1 << BLIP_PHASE_BITS; + class blip_eq_t; + + class Blip_Synth_Fast_ { + public: + Blip_Buffer* buf; + int last_amp; + int delta_factor; + + void volume_unit( double ); + Blip_Synth_Fast_(); + void treble_eq( blip_eq_t const& ) { } + }; + + class Blip_Synth_ { + public: + Blip_Buffer* buf; + int last_amp; + int delta_factor; + + void volume_unit( double ); + Blip_Synth_( short* impulses, int width ); + void treble_eq( blip_eq_t const& ); + private: + double volume_unit_; + short* const impulses; + int const width; + blip_long kernel_unit; + int impulses_size() const { return blip_res / 2 * width + 1; } + void adjust_impulse(); + }; + +// Quality level, better = slower. In general, use blip_good_quality. +const int blip_med_quality = 8; +const int blip_good_quality = 12; +const int blip_high_quality = 16; + +// Range specifies the greatest expected change in amplitude. Calculate it +// by finding the difference between the maximum and minimum expected +// amplitudes (max - min). +template +class Blip_Synth { +public: + // Sets overall volume of waveform + void volume( double v ) { impl.volume_unit( v * (1.0 / (range < 0 ? -range : range)) ); } + + // Configures low-pass filter (see blip_buffer.txt) + void treble_eq( blip_eq_t const& eq ) { impl.treble_eq( eq ); } + + // Gets/sets Blip_Buffer used for output + Blip_Buffer* output() const { return impl.buf; } + void output( Blip_Buffer* b ) { impl.buf = b; impl.last_amp = 0; } + + // Updates amplitude of waveform at given time. Using this requires a separate + // Blip_Synth for each waveform. + void update( blip_time_t time, int amplitude ); + +// Low-level interface + + // Adds an amplitude transition of specified delta, optionally into specified buffer + // rather than the one set with output(). Delta can be positive or negative. + // The actual change in amplitude is delta * (volume / range) + void offset( blip_time_t, int delta, Blip_Buffer* ) const; + void offset( blip_time_t t, int delta ) const { offset( t, delta, impl.buf ); } + + // Works directly in terms of fractional output samples. Contact author for more info. + void offset_resampled( blip_resampled_time_t, int delta, Blip_Buffer* ) const; + + // Same as offset(), except code is inlined for higher performance + void offset_inline( blip_time_t t, int delta, Blip_Buffer* buf ) const { + offset_resampled( t * buf->factor_ + buf->offset_, delta, buf ); + } + void offset_inline( blip_time_t t, int delta ) const { + offset_resampled( t * impl.buf->factor_ + impl.buf->offset_, delta, impl.buf ); + } + +private: +#if BLIP_BUFFER_FAST + Blip_Synth_Fast_ impl; +#else + Blip_Synth_ impl; + typedef short imp_t; + imp_t impulses [blip_res * (quality / 2) + 1]; +public: + Blip_Synth() : impl( impulses, quality ) { } +#endif +}; + +// Low-pass equalization parameters +class blip_eq_t { +public: + // Logarithmic rolloff to treble dB at half sampling rate. Negative values reduce + // treble, small positive values (0 to 5.0) increase treble. + blip_eq_t( double treble_db = 0 ); + + // See blip_buffer.txt + blip_eq_t( double treble, long rolloff_freq, long sample_rate, long cutoff_freq = 0 ); + +private: + double treble; + long rolloff_freq; + long sample_rate; + long cutoff_freq; + void generate( float* out, int count ) const; + friend class Blip_Synth_; +}; + +int const blip_sample_bits = 30; + +// Dummy Blip_Buffer to direct sound output to, for easy muting without +// having to stop sound code. +class Silent_Blip_Buffer : public Blip_Buffer { + buf_t_ buf [blip_buffer_extra_ + 1]; +public: + // The following cannot be used (an assertion will fail if attempted): + blargg_err_t set_sample_rate( long samples_per_sec, int msec_length ); + blip_time_t count_clocks( long count ) const; + void mix_samples( blip_sample_t const* buf, long count ); + + Silent_Blip_Buffer(); +}; + + #if __GNUC__ >= 3 || _MSC_VER >= 1400 + #define BLIP_RESTRICT __restrict + #else + #define BLIP_RESTRICT + #endif + +// Optimized reading from Blip_Buffer, for use in custom sample output + +// Begins reading from buffer. Name should be unique to the current block. +#define BLIP_READER_BEGIN( name, blip_buffer ) \ + const Blip_Buffer::buf_t_* BLIP_RESTRICT name##_reader_buf = (blip_buffer).buffer_;\ + blip_long name##_reader_accum = (blip_buffer).reader_accum_ + +// Gets value to pass to BLIP_READER_NEXT() +#define BLIP_READER_BASS( blip_buffer ) ((blip_buffer).bass_shift_) + +// Constant value to use instead of BLIP_READER_BASS(), for slightly more optimal +// code at the cost of having no bass control +int const blip_reader_default_bass = 9; + +// Current sample +#define BLIP_READER_READ( name ) (name##_reader_accum >> (blip_sample_bits - 16)) + +// Current raw sample in full internal resolution +#define BLIP_READER_READ_RAW( name ) (name##_reader_accum) + +// Advances to next sample +#define BLIP_READER_NEXT( name, bass ) \ + (void) (name##_reader_accum += *name##_reader_buf++ - (name##_reader_accum >> (bass))) + +// Ends reading samples from buffer. The number of samples read must now be removed +// using Blip_Buffer::remove_samples(). +#define BLIP_READER_END( name, blip_buffer ) \ + (void) ((blip_buffer).reader_accum_ = name##_reader_accum) + + +// experimental +#define BLIP_READER_ADJ_( name, offset ) (name##_reader_buf += offset) + +blip_long const blip_reader_idx_factor = sizeof (Blip_Buffer::buf_t_); + +#define BLIP_READER_NEXT_IDX_( name, bass, idx ) {\ + name##_reader_accum -= name##_reader_accum >> (bass);\ + name##_reader_accum += name##_reader_buf [(idx)];\ +} + +#define BLIP_READER_NEXT_RAW_IDX_( name, bass, idx ) {\ + name##_reader_accum -= name##_reader_accum >> (bass);\ + name##_reader_accum +=\ + *(Blip_Buffer::buf_t_ const*) ((char const*) name##_reader_buf + (idx));\ +} + +// Compatibility with older version +const long blip_unscaled = 65535; +const int blip_low_quality = blip_med_quality; +const int blip_best_quality = blip_high_quality; + +// Deprecated; use BLIP_READER macros as follows: +// Blip_Reader r; r.begin( buf ); -> BLIP_READER_BEGIN( r, buf ); +// int bass = r.begin( buf ) -> BLIP_READER_BEGIN( r, buf ); int bass = BLIP_READER_BASS( buf ); +// r.read() -> BLIP_READER_READ( r ) +// r.read_raw() -> BLIP_READER_READ_RAW( r ) +// r.next( bass ) -> BLIP_READER_NEXT( r, bass ) +// r.next() -> BLIP_READER_NEXT( r, blip_reader_default_bass ) +// r.end( buf ) -> BLIP_READER_END( r, buf ) +class Blip_Reader { +public: + int begin( Blip_Buffer& ); + blip_long read() const { return accum >> (blip_sample_bits - 16); } + blip_long read_raw() const { return accum; } + void next( int bass_shift = 9 ) { accum += *buf++ - (accum >> bass_shift); } + void end( Blip_Buffer& b ) { b.reader_accum_ = accum; } +private: + const Blip_Buffer::buf_t_* buf; + blip_long accum; +}; + +#if defined (_M_IX86) || defined (_M_IA64) || defined (__i486__) || \ + defined (__x86_64__) || defined (__ia64__) || defined (__i386__) + #define BLIP_CLAMP_( in ) in < -0x8000 || 0x7FFF < in +#else + #define BLIP_CLAMP_( in ) (blip_sample_t) in != in +#endif + +// Clamp sample to blip_sample_t range +#define BLIP_CLAMP( sample, out )\ + { if ( BLIP_CLAMP_( (sample) ) ) (out) = ((sample) >> 24) ^ 0x7FFF; } + +struct blip_buffer_state_t +{ + blip_resampled_time_t offset_; + blip_long reader_accum_; + blip_long buf [blip_buffer_extra_]; +}; + +// End of public interface + +#ifndef assert + #include +#endif + +template +inline void Blip_Synth::offset_resampled( blip_resampled_time_t time, + int delta, Blip_Buffer* blip_buf ) const +{ + // If this assertion fails, it means that an attempt was made to add a delta + // at a negative time or past the end of the buffer. + assert( (blip_long) (time >> BLIP_BUFFER_ACCURACY) < blip_buf->buffer_size_ ); + + delta *= impl.delta_factor; + blip_long* BLIP_RESTRICT buf = blip_buf->buffer_ + (time >> BLIP_BUFFER_ACCURACY); + int phase = (int) (time >> (BLIP_BUFFER_ACCURACY - BLIP_PHASE_BITS) & (blip_res - 1)); + +#if BLIP_BUFFER_FAST + blip_long left = buf [0] + delta; + + // Kind of crappy, but doing shift after multiply results in overflow. + // Alternate way of delaying multiply by delta_factor results in worse + // sub-sample resolution. + blip_long right = (delta >> BLIP_PHASE_BITS) * phase; + left -= right; + right += buf [1]; + + buf [0] = left; + buf [1] = right; +#else + + int const fwd = (blip_widest_impulse_ - quality) / 2; + int const rev = fwd + quality - 2; + int const mid = quality / 2 - 1; + + imp_t const* BLIP_RESTRICT imp = impulses + blip_res - phase; + + #if defined (_M_IX86) || defined (_M_IA64) || defined (__i486__) || \ + defined (__x86_64__) || defined (__ia64__) || defined (__i386__) + + // this straight forward version gave in better code on GCC for x86 + + #define ADD_IMP( out, in ) \ + buf [out] += (blip_long) imp [blip_res * (in)] * delta + + #define BLIP_FWD( i ) {\ + ADD_IMP( fwd + i, i );\ + ADD_IMP( fwd + 1 + i, i + 1 );\ + } + #define BLIP_REV( r ) {\ + ADD_IMP( rev - r, r + 1 );\ + ADD_IMP( rev + 1 - r, r );\ + } + + BLIP_FWD( 0 ) + if ( quality > 8 ) BLIP_FWD( 2 ) + if ( quality > 12 ) BLIP_FWD( 4 ) + { + ADD_IMP( fwd + mid - 1, mid - 1 ); + ADD_IMP( fwd + mid , mid ); + imp = impulses + phase; + } + if ( quality > 12 ) BLIP_REV( 6 ) + if ( quality > 8 ) BLIP_REV( 4 ) + BLIP_REV( 2 ) + + ADD_IMP( rev , 1 ); + ADD_IMP( rev + 1, 0 ); + + #undef ADD_IMP + + #else + + // for RISC processors, help compiler by reading ahead of writes + + #define BLIP_FWD( i ) {\ + blip_long t0 = i0 * delta + buf [fwd + i];\ + blip_long t1 = imp [blip_res * (i + 1)] * delta + buf [fwd + 1 + i];\ + i0 = imp [blip_res * (i + 2)];\ + buf [fwd + i] = t0;\ + buf [fwd + 1 + i] = t1;\ + } + #define BLIP_REV( r ) {\ + blip_long t0 = i0 * delta + buf [rev - r];\ + blip_long t1 = imp [blip_res * r] * delta + buf [rev + 1 - r];\ + i0 = imp [blip_res * (r - 1)];\ + buf [rev - r] = t0;\ + buf [rev + 1 - r] = t1;\ + } + + blip_long i0 = *imp; + BLIP_FWD( 0 ) + if ( quality > 8 ) BLIP_FWD( 2 ) + if ( quality > 12 ) BLIP_FWD( 4 ) + { + blip_long t0 = i0 * delta + buf [fwd + mid - 1]; + blip_long t1 = imp [blip_res * mid] * delta + buf [fwd + mid ]; + imp = impulses + phase; + i0 = imp [blip_res * mid]; + buf [fwd + mid - 1] = t0; + buf [fwd + mid ] = t1; + } + if ( quality > 12 ) BLIP_REV( 6 ) + if ( quality > 8 ) BLIP_REV( 4 ) + BLIP_REV( 2 ) + + blip_long t0 = i0 * delta + buf [rev ]; + blip_long t1 = *imp * delta + buf [rev + 1]; + buf [rev ] = t0; + buf [rev + 1] = t1; + #endif + +#endif +} + +#undef BLIP_FWD +#undef BLIP_REV + +template +#if BLIP_BUFFER_FAST + inline +#endif +void Blip_Synth::offset( blip_time_t t, int delta, Blip_Buffer* buf ) const +{ + offset_resampled( t * buf->factor_ + buf->offset_, delta, buf ); +} + +template +#if BLIP_BUFFER_FAST + inline +#endif +void Blip_Synth::update( blip_time_t t, int amp ) +{ + int delta = amp - impl.last_amp; + impl.last_amp = amp; + offset_resampled( t * impl.buf->factor_ + impl.buf->offset_, delta, impl.buf ); +} + +inline blip_eq_t::blip_eq_t( double t ) : + treble( t ), rolloff_freq( 0 ), sample_rate( 44100 ), cutoff_freq( 0 ) { } +inline blip_eq_t::blip_eq_t( double t, long rf, long sr, long cf ) : + treble( t ), rolloff_freq( rf ), sample_rate( sr ), cutoff_freq( cf ) { } + +inline int Blip_Buffer::length() const { return length_; } +inline long Blip_Buffer::samples_avail() const { return (long) (offset_ >> BLIP_BUFFER_ACCURACY); } +inline long Blip_Buffer::sample_rate() const { return sample_rate_; } +inline int Blip_Buffer::output_latency() const { return blip_widest_impulse_ / 2; } +inline long Blip_Buffer::clock_rate() const { return clock_rate_; } +inline void Blip_Buffer::clock_rate( long cps ) { factor_ = clock_rate_factor( clock_rate_ = cps ); } + +inline int Blip_Reader::begin( Blip_Buffer& blip_buf ) +{ + buf = blip_buf.buffer_; + accum = blip_buf.reader_accum_; + return blip_buf.bass_shift_; +} + +inline void Blip_Buffer::remove_silence( long count ) +{ + // fails if you try to remove more samples than available + assert( count <= samples_avail() ); + offset_ -= (blip_resampled_time_t) count << BLIP_BUFFER_ACCURACY; +} + +inline blip_ulong Blip_Buffer::unsettled() const +{ + return reader_accum_ >> (blip_sample_bits - 16); +} + +int const blip_max_length = 0; +int const blip_default_length = 250; // 1/4 second + +} + +#endif diff --git a/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/apu/Effects_Buffer.cpp b/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/apu/Effects_Buffer.cpp new file mode 100644 index 000000000..cbe7bf96d --- /dev/null +++ b/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/apu/Effects_Buffer.cpp @@ -0,0 +1,646 @@ +// Game_Music_Emu $vers. http://www.slack.net/~ant/ + +#include "Effects_Buffer.h" + +#include + +/* Copyright (C) 2006-2007 Shay Green. This module is free software; you +can redistribute it and/or modify it under the terms of the GNU Lesser +General Public License as published by the Free Software Foundation; either +version 2.1 of the License, or (at your option) any later version. This +module is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more +details. You should have received a copy of the GNU Lesser General Public +License along with this module; if not, write to the Free Software Foundation, +Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ + +#include "blargg_source.h" + +namespace GBA { + +int const fixed_shift = 12; +#define TO_FIXED( f ) fixed_t ((f) * ((fixed_t) 1 << fixed_shift)) +#define FROM_FIXED( f ) ((f) >> fixed_shift) + +int const max_read = 2560; // determines minimum delay + +Effects_Buffer::Effects_Buffer( int max_bufs, long echo_size_ ) : Multi_Buffer( stereo ) +{ + echo_size = max( long(max_read * (long) stereo), long(echo_size_ & ~1) ); + clock_rate_ = 0; + bass_freq_ = 90; + bufs = 0; + bufs_size = 0; + bufs_max = max( max_bufs, (int) extra_chans ); + no_echo = true; + no_effects = true; + + // defaults + config_.enabled = false; + config_.delay [0] = 120; + config_.delay [1] = 122; + config_.feedback = 0.2f; + config_.treble = 0.4f; + + static float const sep = 0.8f; + config_.side_chans [0].pan = -sep; + config_.side_chans [1].pan = +sep; + config_.side_chans [0].vol = 1.0f; + config_.side_chans [1].vol = 1.0f; + + memset( &s, 0, sizeof s ); + clear(); +} + +Effects_Buffer::~Effects_Buffer() +{ + delete_bufs(); +} + +// avoid using new [] +blargg_err_t Effects_Buffer::new_bufs( int size ) +{ + bufs = (buf_t*) malloc( size * sizeof *bufs ); + CHECK_ALLOC( bufs ); + for ( int i = 0; i < size; i++ ) + new (bufs + i) buf_t; + bufs_size = size; + return 0; +} + +void Effects_Buffer::delete_bufs() +{ + if ( bufs ) + { + for ( int i = bufs_size; --i >= 0; ) + bufs [i].~buf_t(); + free( bufs ); + bufs = 0; + } + bufs_size = 0; +} + +blargg_err_t Effects_Buffer::set_sample_rate( long rate, int msec ) +{ + // extra to allow farther past-the-end pointers + mixer.samples_read = 0; + RETURN_ERR( echo.resize( echo_size + stereo ) ); + return Multi_Buffer::set_sample_rate( rate, msec ); +} + +void Effects_Buffer::clock_rate( long rate ) +{ + clock_rate_ = rate; + for ( int i = bufs_size; --i >= 0; ) + bufs [i].clock_rate( clock_rate_ ); +} + +void Effects_Buffer::bass_freq( int freq ) +{ + bass_freq_ = freq; + for ( int i = bufs_size; --i >= 0; ) + bufs [i].bass_freq( bass_freq_ ); +} + +blargg_err_t Effects_Buffer::set_channel_count( int count, int const* types ) +{ + RETURN_ERR( Multi_Buffer::set_channel_count( count, types ) ); + + delete_bufs(); + + mixer.samples_read = 0; + + RETURN_ERR( chans.resize( count + extra_chans ) ); + + RETURN_ERR( new_bufs( min( bufs_max, count + extra_chans ) ) ); + + { + for ( int i = bufs_size; --i >= 0; ) + RETURN_ERR( bufs [i].set_sample_rate( sample_rate(), length() ) ); + } + + { + for ( int i = chans.size(); --i >= 0; ) + { + chan_t& ch = chans [i]; + ch.cfg.vol = 1.0f; + ch.cfg.pan = 0.0f; + ch.cfg.surround = false; + ch.cfg.echo = false; + } + } + // side channels with echo + chans [2].cfg.echo = true; + chans [3].cfg.echo = true; + + clock_rate( clock_rate_ ); + bass_freq( bass_freq_ ); + apply_config(); + clear(); + + return 0; +} + +void Effects_Buffer::clear_echo() +{ + if ( echo.size() ) + memset( echo.begin(), 0, echo.size() * sizeof echo [0] ); +} + +void Effects_Buffer::clear() +{ + echo_pos = 0; + s.low_pass [0] = 0; + s.low_pass [1] = 0; + mixer.samples_read = 0; + + for ( int i = bufs_size; --i >= 0; ) + bufs [i].clear(); + clear_echo(); +} + +Effects_Buffer::channel_t Effects_Buffer::channel( int i ) +{ + i += extra_chans; + require( extra_chans <= i && i < (int) chans.size() ); + return chans [i].channel; +} + + +// Configuration + +// 3 wave positions with/without surround, 2 multi (one with same config as wave) +int const simple_bufs = 3 * 2 + 2 - 1; + +Simple_Effects_Buffer::Simple_Effects_Buffer() : + Effects_Buffer( extra_chans + simple_bufs, 18 * 1024L ) +{ + config_.echo = 0.20f; + config_.stereo = 0.20f; + config_.surround = true; + config_.enabled = false; +} + +void Simple_Effects_Buffer::apply_config() +{ + Effects_Buffer::config_t& c = Effects_Buffer::config(); + + c.enabled = config_.enabled; + if ( c.enabled ) + { + c.delay [0] = 120; + c.delay [1] = 122; + c.feedback = config_.echo * 0.7f; + c.treble = 0.6f - 0.3f * config_.echo; + + float sep = config_.stereo + 0.80f; + if ( sep > 1.0f ) + sep = 1.0f; + + c.side_chans [0].pan = -sep; + c.side_chans [1].pan = +sep; + + for ( int i = channel_count(); --i >= 0; ) + { + chan_config_t& ch = Effects_Buffer::chan_config( i ); + + ch.pan = 0.0f; + ch.surround = config_.surround; + ch.echo = false; + + int const type = (channel_types() ? channel_types() [i] : 0); + if ( !(type & noise_type) ) + { + int index = (type & type_index_mask) % 6 - 3; + if ( index < 0 ) + { + index += 3; + ch.surround = false; + ch.echo = true; + } + if ( index >= 1 ) + { + ch.pan = config_.stereo; + if ( index == 1 ) + ch.pan = -ch.pan; + } + } + else if ( type & 1 ) + { + ch.surround = false; + } + } + } + + Effects_Buffer::apply_config(); +} + +int Effects_Buffer::min_delay() const +{ + require( sample_rate() ); + return max_read * 1000L / sample_rate(); +} + +int Effects_Buffer::max_delay() const +{ + require( sample_rate() ); + return (echo_size / stereo - max_read) * 1000L / sample_rate(); +} + +void Effects_Buffer::apply_config() +{ + int i; + + if ( !bufs_size ) + return; + + s.treble = TO_FIXED( config_.treble ); + + bool echo_dirty = false; + + fixed_t old_feedback = s.feedback; + s.feedback = TO_FIXED( config_.feedback ); + if ( !old_feedback && s.feedback ) + echo_dirty = true; + + // delays + for ( i = stereo; --i >= 0; ) + { + long delay = config_.delay [i] * sample_rate() / 1000 * stereo; + delay = max( delay, long (max_read * stereo) ); + delay = min( delay, long (echo_size - max_read * stereo) ); + if ( s.delay [i] != delay ) + { + s.delay [i] = delay; + echo_dirty = true; + } + } + + // side channels + for ( i = 2; --i >= 0; ) + { + chans [i+2].cfg.vol = chans [i].cfg.vol = config_.side_chans [i].vol * 0.5f; + chans [i+2].cfg.pan = chans [i].cfg.pan = config_.side_chans [i].pan; + } + + // convert volumes + for ( i = chans.size(); --i >= 0; ) + { + chan_t& ch = chans [i]; + ch.vol [0] = TO_FIXED( ch.cfg.vol - ch.cfg.vol * ch.cfg.pan ); + ch.vol [1] = TO_FIXED( ch.cfg.vol + ch.cfg.vol * ch.cfg.pan ); + if ( ch.cfg.surround ) + ch.vol [0] = -ch.vol [0]; + } + + assign_buffers(); + + // set side channels + for ( i = chans.size(); --i >= 0; ) + { + chan_t& ch = chans [i]; + ch.channel.left = chans [ch.cfg.echo*2 ].channel.center; + ch.channel.right = chans [ch.cfg.echo*2+1].channel.center; + } + + bool old_echo = !no_echo && !no_effects; + + // determine whether effects and echo are needed at all + no_effects = true; + no_echo = true; + for ( i = chans.size(); --i >= extra_chans; ) + { + chan_t& ch = chans [i]; + if ( ch.cfg.echo && s.feedback ) + no_echo = false; + + if ( ch.vol [0] != TO_FIXED( 1 ) || ch.vol [1] != TO_FIXED( 1 ) ) + no_effects = false; + } + if ( !no_echo ) + no_effects = false; + + if ( chans [0].vol [0] != TO_FIXED( 1 ) || + chans [0].vol [1] != TO_FIXED( 0 ) || + chans [1].vol [0] != TO_FIXED( 0 ) || + chans [1].vol [1] != TO_FIXED( 1 ) ) + no_effects = false; + + if ( !config_.enabled ) + no_effects = true; + + if ( no_effects ) + { + for ( i = chans.size(); --i >= 0; ) + { + chan_t& ch = chans [i]; + ch.channel.center = &bufs [2]; + ch.channel.left = &bufs [0]; + ch.channel.right = &bufs [1]; + } + } + + mixer.bufs [0] = &bufs [0]; + mixer.bufs [1] = &bufs [1]; + mixer.bufs [2] = &bufs [2]; + + if ( echo_dirty || (!old_echo && (!no_echo && !no_effects)) ) + clear_echo(); + + channels_changed(); +} + +void Effects_Buffer::assign_buffers() +{ + // assign channels to buffers + int buf_count = 0; + for ( int i = 0; i < (int) chans.size(); i++ ) + { + // put second two side channels at end to give priority to main channels + // in case closest matching is necessary + int x = i; + if ( i > 1 ) + x += 2; + if ( x >= (int) chans.size() ) + x -= (chans.size() - 2); + chan_t& ch = chans [x]; + + int b = 0; + for ( ; b < buf_count; b++ ) + { + if ( ch.vol [0] == bufs [b].vol [0] && + ch.vol [1] == bufs [b].vol [1] && + (ch.cfg.echo == bufs [b].echo || !s.feedback) ) + break; + } + + if ( b >= buf_count ) + { + if ( buf_count < bufs_max ) + { + bufs [b].vol [0] = ch.vol [0]; + bufs [b].vol [1] = ch.vol [1]; + bufs [b].echo = ch.cfg.echo; + buf_count++; + } + else + { + // TODO: this is a mess, needs refinement + dprintf( "Effects_Buffer ran out of buffers; using closest match\n" ); + b = 0; + fixed_t best_dist = TO_FIXED( 8 ); + for ( int h = buf_count; --h >= 0; ) + { + #define CALC_LEVELS( vols, sum, diff, surround ) \ + fixed_t sum, diff;\ + bool surround = false;\ + {\ + fixed_t vol_0 = vols [0];\ + if ( vol_0 < 0 ) vol_0 = -vol_0, surround = true;\ + fixed_t vol_1 = vols [1];\ + if ( vol_1 < 0 ) vol_1 = -vol_1, surround = true;\ + sum = vol_0 + vol_1;\ + diff = vol_0 - vol_1;\ + } + CALC_LEVELS( ch.vol, ch_sum, ch_diff, ch_surround ); + CALC_LEVELS( bufs [h].vol, buf_sum, buf_diff, buf_surround ); + + fixed_t dist = abs( ch_sum - buf_sum ) + abs( ch_diff - buf_diff ); + + if ( ch_surround != buf_surround ) + dist += TO_FIXED( 1 ) / 2; + + if ( s.feedback && ch.cfg.echo != bufs [h].echo ) + dist += TO_FIXED( 1 ) / 2; + + if ( best_dist > dist ) + { + best_dist = dist; + b = h; + } + } + } + } + + //dprintf( "ch %d->buf %d\n", x, b ); + ch.channel.center = &bufs [b]; + } +} + + +// Mixing + +void Effects_Buffer::end_frame( blip_time_t time ) +{ + for ( int i = bufs_size; --i >= 0; ) + bufs [i].end_frame( time ); +} + +long Effects_Buffer::read_samples( blip_sample_t* out, long out_size ) +{ + out_size = min( out_size, samples_avail() ); + + int pair_count = int (out_size >> 1); + require( pair_count * stereo == out_size ); // must read an even number of samples + if ( pair_count ) + { + if ( no_effects ) + { + mixer.read_pairs( out, pair_count ); + } + else + { + int pairs_remain = pair_count; + do + { + // mix at most max_read pairs at a time + int count = max_read; + if ( count > pairs_remain ) + count = pairs_remain; + + if ( no_echo ) + { + // optimization: clear echo here to keep mix_effects() a leaf function + echo_pos = 0; + memset( echo.begin(), 0, count * stereo * sizeof echo [0] ); + } + mix_effects( out, count ); + + blargg_long new_echo_pos = echo_pos + count * stereo; + if ( new_echo_pos >= echo_size ) + new_echo_pos -= echo_size; + echo_pos = new_echo_pos; + assert( echo_pos < echo_size ); + + out += count * stereo; + mixer.samples_read += count; + pairs_remain -= count; + } + while ( pairs_remain ); + } + + if ( samples_avail() <= 0 || immediate_removal() ) + { + for ( int i = bufs_size; --i >= 0; ) + { + buf_t& b = bufs [i]; + // TODO: might miss non-silence settling since it checks END of last read + if ( b.non_silent() ) + b.remove_samples( mixer.samples_read ); + else + b.remove_silence( mixer.samples_read ); + } + mixer.samples_read = 0; + } + } + return out_size; +} + +void Effects_Buffer::mix_effects( blip_sample_t* out_, int pair_count ) +{ + typedef fixed_t stereo_fixed_t [stereo]; + + // add channels with echo, do echo, add channels without echo, then convert to 16-bit and output + int echo_phase = 1; + do + { + // mix any modified buffers + { + buf_t* buf = bufs; + int bufs_remain = bufs_size; + do + { + if ( buf->non_silent() && ( buf->echo == !!echo_phase ) ) + { + stereo_fixed_t* BLIP_RESTRICT out = (stereo_fixed_t*) &echo [echo_pos]; + int const bass = BLIP_READER_BASS( *buf ); + BLIP_READER_BEGIN( in, *buf ); + BLIP_READER_ADJ_( in, mixer.samples_read ); + fixed_t const vol_0 = buf->vol [0]; + fixed_t const vol_1 = buf->vol [1]; + + int count = unsigned (echo_size - echo_pos) / stereo; + int remain = pair_count; + if ( count > remain ) + count = remain; + do + { + remain -= count; + BLIP_READER_ADJ_( in, count ); + + out += count; + int offset = -count; + do + { + fixed_t s = BLIP_READER_READ( in ); + BLIP_READER_NEXT_IDX_( in, bass, offset ); + + out [offset] [0] += s * vol_0; + out [offset] [1] += s * vol_1; + } + while ( ++offset ); + + out = (stereo_fixed_t*) echo.begin(); + count = remain; + } + while ( remain ); + + BLIP_READER_END( in, *buf ); + } + buf++; + } + while ( --bufs_remain ); + } + + // add echo + if ( echo_phase && !no_echo ) + { + fixed_t const feedback = s.feedback; + fixed_t const treble = s.treble; + + int i = 1; + do + { + fixed_t low_pass = s.low_pass [i]; + + fixed_t* echo_end = &echo [echo_size + i]; + fixed_t const* BLIP_RESTRICT in_pos = &echo [echo_pos + i]; + blargg_long out_offset = echo_pos + i + s.delay [i]; + if ( out_offset >= echo_size ) + out_offset -= echo_size; + assert( out_offset < echo_size ); + fixed_t* BLIP_RESTRICT out_pos = &echo [out_offset]; + + // break into up to three chunks to avoid having to handle wrap-around + // in middle of core loop + int remain = pair_count; + do + { + fixed_t const* pos = in_pos; + if ( pos < out_pos ) + pos = out_pos; + int count = blargg_ulong ((char*) echo_end - (char const*) pos) / + unsigned (stereo * sizeof (fixed_t)); + if ( count > remain ) + count = remain; + remain -= count; + + in_pos += count * stereo; + out_pos += count * stereo; + int offset = -count; + do + { + low_pass += FROM_FIXED( in_pos [offset * stereo] - low_pass ) * treble; + out_pos [offset * stereo] = FROM_FIXED( low_pass ) * feedback; + } + while ( ++offset ); + + if ( in_pos >= echo_end ) in_pos -= echo_size; + if ( out_pos >= echo_end ) out_pos -= echo_size; + } + while ( remain ); + + s.low_pass [i] = low_pass; + } + while ( --i >= 0 ); + } + } + while ( --echo_phase >= 0 ); + + // clamp to 16 bits + { + stereo_fixed_t const* BLIP_RESTRICT in = (stereo_fixed_t*) &echo [echo_pos]; + typedef blip_sample_t stereo_blip_sample_t [stereo]; + stereo_blip_sample_t* BLIP_RESTRICT out = (stereo_blip_sample_t*) out_; + int count = unsigned (echo_size - echo_pos) / (unsigned) stereo; + int remain = pair_count; + if ( count > remain ) + count = remain; + do + { + remain -= count; + in += count; + out += count; + int offset = -count; + do + { + fixed_t in_0 = FROM_FIXED( in [offset] [0] ); + fixed_t in_1 = FROM_FIXED( in [offset] [1] ); + + BLIP_CLAMP( in_0, in_0 ); + out [offset] [0] = (blip_sample_t) in_0; + + BLIP_CLAMP( in_1, in_1 ); + out [offset] [1] = (blip_sample_t) in_1; + } + while ( ++offset ); + + in = (stereo_fixed_t*) echo.begin(); + count = remain; + } + while ( remain ); + } +} + +} diff --git a/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/apu/Effects_Buffer.h b/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/apu/Effects_Buffer.h new file mode 100644 index 000000000..e8458f654 --- /dev/null +++ b/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/apu/Effects_Buffer.h @@ -0,0 +1,147 @@ +// Multi-channel effects buffer with echo and individual panning for each channel + +// Game_Music_Emu $vers +#ifndef EFFECTS_BUFFER_H +#define EFFECTS_BUFFER_H + +#include "Multi_Buffer.h" + +// See Simple_Effects_Buffer (below) for a simpler interface + +namespace GBA { + +class Effects_Buffer : public Multi_Buffer { +public: + // To reduce memory usage, fewer buffers can be used (with a best-fit + // approach if there are too few), and maximum echo delay can be reduced + Effects_Buffer( int max_bufs = 32, long echo_size = 24 * 1024L ); + + struct pan_vol_t + { + float vol; // 0.0 = silent, 0.5 = half volume, 1.0 = normal + float pan; // -1.0 = left, 0.0 = center, +1.0 = right + }; + + // Global configuration + struct config_t + { + bool enabled; // false = disable all effects + + // Current sound is echoed at adjustable left/right delay, + // with reduced treble and volume (feedback). + float treble; // 1.0 = full treble, 0.1 = very little, 0.0 = silent + int delay [2]; // left, right delays (msec) + float feedback; // 0.0 = no echo, 0.5 = each echo half previous, 1.0 = cacophony + pan_vol_t side_chans [2]; // left and right side channel volume and pan + }; + config_t& config() { return config_; } + + // Limits of delay (msec) + int min_delay() const; + int max_delay() const; + + // Per-channel configuration. Two or more channels with matching parameters are + // optimized to internally use the same buffer. + struct chan_config_t : pan_vol_t + { + // (inherited from pan_vol_t) + //float vol; // these only affect center channel + //float pan; + bool surround; // if true, negates left volume to put sound in back + bool echo; // false = channel doesn't have any echo + }; + chan_config_t& chan_config( int i ) { return chans [i + extra_chans].cfg; } + + // Apply any changes made to config() and chan_config() + virtual void apply_config(); + +public: + ~Effects_Buffer(); + blargg_err_t set_sample_rate( long samples_per_sec, int msec = blip_default_length ); + blargg_err_t set_channel_count( int, int const* = 0 ); + void clock_rate( long ); + void bass_freq( int ); + void clear(); + channel_t channel( int ); + void end_frame( blip_time_t ); + long read_samples( blip_sample_t*, long ); + long samples_avail() const { return (bufs [0].samples_avail() - mixer.samples_read) * 2; } + enum { stereo = 2 }; + typedef blargg_long fixed_t; +protected: + enum { extra_chans = stereo * stereo }; +private: + config_t config_; + long clock_rate_; + int bass_freq_; + + blargg_long echo_size; + + struct chan_t + { + fixed_t vol [stereo]; + chan_config_t cfg; + channel_t channel; + }; + blargg_vector chans; + + struct buf_t : Tracked_Blip_Buffer + { + fixed_t vol [stereo]; + bool echo; + + void* operator new ( size_t, void* p ) { return p; } + void operator delete ( void* ) { } + + ~buf_t() { } + }; + buf_t* bufs; + int bufs_size; + int bufs_max; // bufs_size <= bufs_max, to limit memory usage + Stereo_Mixer mixer; + + struct { + long delay [stereo]; + fixed_t treble; + fixed_t feedback; + fixed_t low_pass [stereo]; + } s; + + blargg_vector echo; + blargg_long echo_pos; + + bool no_effects; + bool no_echo; + + void assign_buffers(); + void clear_echo(); + void mix_effects( blip_sample_t* out, int pair_count ); + blargg_err_t new_bufs( int size ); + void delete_bufs(); +}; + +// Simpler interface and lower memory usage +class Simple_Effects_Buffer : public Effects_Buffer { +public: + struct config_t + { + bool enabled; // false = disable all effects + float echo; // 0.0 = none, 1.0 = lots + float stereo; // 0.0 = channels in center, 1.0 = channels on left/right + bool surround; // true = put some channels in back + }; + config_t& config() { return config_; } + + // Apply any changes made to config() + void apply_config(); + +public: + Simple_Effects_Buffer(); +private: + config_t config_; + void chan_config(); // hide +}; + +} + +#endif diff --git a/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/apu/Gb_Apu.cpp b/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/apu/Gb_Apu.cpp new file mode 100644 index 000000000..0fadfba14 --- /dev/null +++ b/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/apu/Gb_Apu.cpp @@ -0,0 +1,408 @@ +// Gb_Snd_Emu 0.2.0. http://www.slack.net/~ant/ + +#include "Gb_Apu.h" + +/* Copyright (C) 2003-2007 Shay Green. This module is free software; you +can redistribute it and/or modify it under the terms of the GNU Lesser +General Public License as published by the Free Software Foundation; either +version 2.1 of the License, or (at your option) any later version. This +module is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more +details. You should have received a copy of the GNU Lesser General Public +License along with this module; if not, write to the Free Software Foundation, +Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ + +#include "blargg_source.h" + +namespace GBA { + +unsigned const vol_reg = 0xFF24; +unsigned const stereo_reg = 0xFF25; +unsigned const status_reg = 0xFF26; +unsigned const wave_ram = 0xFF30; + +int const power_mask = 0x80; + +void Gb_Apu::treble_eq( blip_eq_t const& eq ) +{ + good_synth.treble_eq( eq ); + med_synth .treble_eq( eq ); +} + +inline int Gb_Apu::calc_output( int osc ) const +{ + int bits = regs [stereo_reg - start_addr] >> osc; + return (bits >> 3 & 2) | (bits & 1); +} + +void Gb_Apu::set_output( Blip_Buffer* center, Blip_Buffer* left, Blip_Buffer* right, int osc ) +{ + // Must be silent (all NULL), mono (left and right NULL), or stereo (none NULL) + require( !center || (center && !left && !right) || (center && left && right) ); + require( (unsigned) osc <= osc_count ); // fails if you pass invalid osc index + + if ( !center || !left || !right ) + { + left = center; + right = center; + } + + int i = (unsigned) osc % osc_count; + do + { + Gb_Osc& o = *oscs [i]; + o.outputs [1] = right; + o.outputs [2] = left; + o.outputs [3] = center; + o.output = o.outputs [calc_output( i )]; + } + while ( ++i < osc ); +} + +void Gb_Apu::synth_volume( int iv ) +{ + double v = volume_ * 0.60 / osc_count / 15 /*steps*/ / 8 /*master vol range*/ * iv; + good_synth.volume( v ); + med_synth .volume( v ); +} + +void Gb_Apu::apply_volume() +{ + // TODO: Doesn't handle differing left and right volumes (panning). + // Not worth the complexity. + int data = regs [vol_reg - start_addr]; + int left = data >> 4 & 7; + int right = data & 7; + //if ( data & 0x88 ) dprintf( "Vin: %02X\n", data & 0x88 ); + //if ( left != right ) dprintf( "l: %d r: %d\n", left, right ); + synth_volume( max( left, right ) + 1 ); +} + +void Gb_Apu::volume( double v ) +{ + if ( volume_ != v ) + { + volume_ = v; + apply_volume(); + } +} + +void Gb_Apu::reset_regs() +{ + for ( int i = 0; i < 0x20; i++ ) + regs [i] = 0; + + square1.reset(); + square2.reset(); + wave .reset(); + noise .reset(); + + apply_volume(); +} + +void Gb_Apu::reset_lengths() +{ + square1.length_ctr = 64; + square2.length_ctr = 64; + wave .length_ctr = 256; + noise .length_ctr = 64; +} + +void Gb_Apu::reduce_clicks( bool reduce ) +{ + reduce_clicks_ = reduce; + + // Click reduction makes DAC off generate same output as volume 0 + int dac_off_amp = 0; + if ( reduce && wave.mode != mode_agb ) // AGB already eliminates clicks + dac_off_amp = -Gb_Osc::dac_bias; + + for ( int i = 0; i < osc_count; i++ ) + oscs [i]->dac_off_amp = dac_off_amp; + + // AGB always eliminates clicks on wave channel using same method + if ( wave.mode == mode_agb ) + wave.dac_off_amp = -Gb_Osc::dac_bias; +} + +void Gb_Apu::reset( mode_t mode, bool agb_wave ) +{ + // Hardware mode + if ( agb_wave ) + mode = mode_agb; // using AGB wave features implies AGB hardware + wave.agb_mask = agb_wave ? 0xFF : 0; + for ( int i = 0; i < osc_count; i++ ) + oscs [i]->mode = mode; + reduce_clicks( reduce_clicks_ ); + + // Reset state + frame_time = 0; + last_time = 0; + frame_phase = 0; + + reset_regs(); + reset_lengths(); + + // Load initial wave RAM + static byte const initial_wave [2] [16] = { + {0x84,0x40,0x43,0xAA,0x2D,0x78,0x92,0x3C,0x60,0x59,0x59,0xB0,0x34,0xB8,0x2E,0xDA}, + {0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF}, + }; + for ( int b = 2; --b >= 0; ) + { + // Init both banks (does nothing if not in AGB mode) + // TODO: verify that this works + write_register( 0, 0xFF1A, b * 0x40 ); + for ( unsigned i = 0; i < sizeof initial_wave [0]; i++ ) + write_register( 0, i + wave_ram, initial_wave [(mode != mode_dmg)] [i] ); + } +} + +void Gb_Apu::set_tempo( double t ) +{ + frame_period = 4194304 / 512; // 512 Hz + if ( t != 1.0 ) + frame_period = blip_time_t (frame_period / t); +} + +Gb_Apu::Gb_Apu() +{ + wave.wave_ram = ®s [wave_ram - start_addr]; + + oscs [0] = &square1; + oscs [1] = &square2; + oscs [2] = &wave; + oscs [3] = &noise; + + for ( int i = osc_count; --i >= 0; ) + { + Gb_Osc& o = *oscs [i]; + o.regs = ®s [i * 5]; + o.output = 0; + o.outputs [0] = 0; + o.outputs [1] = 0; + o.outputs [2] = 0; + o.outputs [3] = 0; + o.good_synth = &good_synth; + o.med_synth = &med_synth; + } + + reduce_clicks_ = false; + set_tempo( 1.0 ); + volume_ = 1.0; + reset(); +} + +void Gb_Apu::run_until_( blip_time_t end_time ) +{ + while ( true ) + { + // run oscillators + blip_time_t time = end_time; + if ( time > frame_time ) + time = frame_time; + + square1.run( last_time, time ); + square2.run( last_time, time ); + wave .run( last_time, time ); + noise .run( last_time, time ); + last_time = time; + + if ( time == end_time ) + break; + + // run frame sequencer + frame_time += frame_period * Gb_Osc::clk_mul; + switch ( frame_phase++ ) + { + case 2: + case 6: + // 128 Hz + square1.clock_sweep(); + case 0: + case 4: + // 256 Hz + square1.clock_length(); + square2.clock_length(); + wave .clock_length(); + noise .clock_length(); + break; + + case 7: + // 64 Hz + frame_phase = 0; + square1.clock_envelope(); + square2.clock_envelope(); + noise .clock_envelope(); + } + } +} + +inline void Gb_Apu::run_until( blip_time_t time ) +{ + require( time >= last_time ); // end_time must not be before previous time + if ( time > last_time ) + run_until_( time ); +} + +void Gb_Apu::end_frame( blip_time_t end_time ) +{ + if ( end_time > last_time ) + run_until( end_time ); + + frame_time -= end_time; + assert( frame_time >= 0 ); + + last_time -= end_time; + assert( last_time >= 0 ); +} + +void Gb_Apu::silence_osc( Gb_Osc& o ) +{ + int delta = -o.last_amp; + if ( delta ) + { + o.last_amp = 0; + if ( o.output ) + { + o.output->set_modified(); + med_synth.offset( last_time, delta, o.output ); + } + } +} + +void Gb_Apu::apply_stereo() +{ + for ( int i = osc_count; --i >= 0; ) + { + Gb_Osc& o = *oscs [i]; + Blip_Buffer* out = o.outputs [calc_output( i )]; + if ( o.output != out ) + { + silence_osc( o ); + o.output = out; + } + } +} + +void Gb_Apu::write_register( blip_time_t time, unsigned addr, int data ) +{ + require( (unsigned) data < 0x100 ); + + int reg = addr - start_addr; + if ( (unsigned) reg >= register_count ) + { + require( false ); + return; + } + + if ( addr < status_reg && !(regs [status_reg - start_addr] & power_mask) ) + { + // Power is off + + // length counters can only be written in DMG mode + if ( wave.mode != mode_dmg || (reg != 1 && reg != 5+1 && reg != 10+1 && reg != 15+1) ) + return; + + if ( reg < 10 ) + data &= 0x3F; // clear square duty + } + + run_until( time ); + + if ( addr >= wave_ram ) + { + wave.write( addr, data ); + } + else + { + int old_data = regs [reg]; + regs [reg] = data; + + if ( addr < vol_reg ) + { + // Oscillator + write_osc( reg / 5, reg, old_data, data ); + } + else if ( addr == vol_reg && data != old_data ) + { + // Master volume + for ( int i = osc_count; --i >= 0; ) + silence_osc( *oscs [i] ); + + apply_volume(); + } + else if ( addr == stereo_reg ) + { + // Stereo panning + apply_stereo(); + } + else if ( addr == status_reg && (data ^ old_data) & power_mask ) + { + // Power control + frame_phase = 0; + for ( int i = osc_count; --i >= 0; ) + silence_osc( *oscs [i] ); + + reset_regs(); + if ( wave.mode != mode_dmg ) + reset_lengths(); + + regs [status_reg - start_addr] = data; + } + } +} + +int Gb_Apu::read_register( blip_time_t time, unsigned addr ) +{ + run_until( time ); + + int reg = addr - start_addr; + if ( (unsigned) reg >= register_count ) + { + require( false ); + return 0; + } + + if ( addr >= wave_ram ) + return wave.read( addr ); + + // Value read back has some bits always set + static byte const masks [] = { + 0x80,0x3F,0x00,0xFF,0xBF, + 0xFF,0x3F,0x00,0xFF,0xBF, + 0x7F,0xFF,0x9F,0xFF,0xBF, + 0xFF,0xFF,0x00,0x00,0xBF, + 0x00,0x00,0x70, + 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF + }; + int mask = masks [reg]; + if ( wave.agb_mask && (reg == 10 || reg == 12) ) + mask = 0x1F; // extra implemented bits in wave regs on AGB + int data = regs [reg] | mask; + + // Status register + if ( addr == status_reg ) + { + data &= 0xF0; + data |= (int) square1.enabled << 0; + data |= (int) square2.enabled << 1; + data |= (int) wave .enabled << 2; + data |= (int) noise .enabled << 3; + } + + return data; +} + +int Gb_Apu::read_status() +{ + int data = 0; + data |= (int) square1.enabled << 0; + data |= (int) square2.enabled << 1; + data |= (int) wave .enabled << 2; + data |= (int) noise .enabled << 3; + return data; +} + +} diff --git a/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/apu/Gb_Apu.h b/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/apu/Gb_Apu.h new file mode 100644 index 000000000..c807a023b --- /dev/null +++ b/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/apu/Gb_Apu.h @@ -0,0 +1,186 @@ +// Nintendo Game Boy sound hardware emulator with save state support + +// Gb_Snd_Emu 0.2.0 +#ifndef GB_APU_H +#define GB_APU_H + +#include "Gb_Oscs.h" + +namespace GBA { + +struct gb_apu_state_t; + +class Gb_Apu { +public: +// Basics + + // Clock rate that sound hardware runs at. + enum { clock_rate = 4194304 * GB_APU_OVERCLOCK }; + + // Sets buffer(s) to generate sound into. If left and right are NULL, output is mono. + // If all are NULL, no output is generated but other emulation still runs. + // If chan is specified, only that channel's output is changed, otherwise all are. + enum { osc_count = 4 }; // 0: Square 1, 1: Square 2, 2: Wave, 3: Noise + void set_output( Blip_Buffer* center, Blip_Buffer* left = NULL, Blip_Buffer* right = NULL, + int chan = osc_count ); + + // Resets hardware to initial power on state BEFORE boot ROM runs. Mode selects + // sound hardware. Additional AGB wave features are enabled separately. + enum mode_t { + mode_dmg, // Game Boy monochrome + mode_cgb, // Game Boy Color + mode_agb // Game Boy Advance + }; + void reset( mode_t mode = mode_cgb, bool agb_wave = false ); + + // Reads and writes must be within the start_addr to end_addr range, inclusive. + // Addresses outside this range are not mapped to the sound hardware. + enum { start_addr = 0xFF10 }; + enum { end_addr = 0xFF3F }; + enum { register_count = end_addr - start_addr + 1 }; + + // Times are specified as the number of clocks since the beginning of the + // current time frame. + + // Emulates CPU write of data to addr at specified time. + void write_register( blip_time_t time, unsigned addr, int data ); + + // Emulates CPU read from addr at specified time. + int read_register( blip_time_t time, unsigned addr ); + + // Emulates sound hardware up to specified time, ends current time frame, then + // starts a new frame at time 0. + void end_frame( blip_time_t frame_length ); + +// Sound adjustments + + // Sets overall volume, where 1.0 is normal. + void volume( double ); + + // If true, reduces clicking by disabling DAC biasing. Note that this reduces + // emulation accuracy, since the clicks are authentic. + void reduce_clicks( bool reduce = true ); + + // Sets treble equalization. + void treble_eq( blip_eq_t const& ); + + // Treble and bass values for various hardware. + enum { + speaker_treble = -47, // speaker on system + speaker_bass = 2000, + dmg_treble = 0, // headphones on each system + dmg_bass = 30, + cgb_treble = 0, + cgb_bass = 300, // CGB has much less bass + agb_treble = 0, + agb_bass = 30 + }; + + // Sets frame sequencer rate, where 1.0 is normal. Meant for adjusting the + // tempo in a game music player. + void set_tempo( double ); + +// Save states + + // Saves full emulation state to state_out. Data format is portable and + // includes some extra space to avoid expansion in case more state needs + // to be stored in the future. + void save_state( gb_apu_state_t* state_out ); + + // Loads state. You should call reset() BEFORE this. + blargg_err_t load_state( gb_apu_state_t const& in ); + +public: + Gb_Apu(); + +private: + // noncopyable + Gb_Apu( const Gb_Apu& ); + Gb_Apu& operator = ( const Gb_Apu& ); + + Gb_Osc* oscs [osc_count]; + blip_time_t last_time; // time sound emulator has been run to + blip_time_t frame_period; // clocks between each frame sequencer step + double volume_; + bool reduce_clicks_; + + Gb_Sweep_Square square1; + Gb_Square square2; + Gb_Wave wave; + Gb_Noise noise; + blip_time_t frame_time; // time of next frame sequencer action + int frame_phase; // phase of next frame sequencer step + enum { regs_size = register_count + 0x10 }; + BOOST::uint8_t regs [regs_size];// last values written to registers + + // large objects after everything else + Gb_Osc::Good_Synth good_synth; + Gb_Osc::Med_Synth med_synth; + + void reset_lengths(); + void reset_regs(); + int calc_output( int osc ) const; + void apply_stereo(); + void apply_volume(); + void synth_volume( int ); + void run_until_( blip_time_t ); + void run_until( blip_time_t ); + void silence_osc( Gb_Osc& ); + void write_osc( int index, int reg, int old_data, int data ); + const char* save_load( gb_apu_state_t*, bool save ); + void save_load2( gb_apu_state_t*, bool save ); + friend class Gb_Apu_Tester; + +#ifdef VIOGSF_REMOVED +#else +public: + int read_status(); +#endif +}; + +// Format of save state. Should be stable across versions of the library, +// with earlier versions properly opening later save states. Includes some +// room for expansion so the state size shouldn't increase. +struct gb_apu_state_t +{ +#if GB_APU_CUSTOM_STATE + // Values stored as plain int so your code can read/write them easily. + // Structure can NOT be written to disk, since format is not portable. + typedef int val_t; +#else + // Values written in portable little-endian format, allowing structure + // to be written directly to disk. + typedef unsigned char val_t [4]; +#endif + + enum { format0 = 0x50414247 }; + + val_t format; // format of all following data + val_t version; // later versions just add fields to end + + unsigned char regs [0x40]; + val_t frame_time; + val_t frame_phase; + + val_t sweep_freq; + val_t sweep_delay; + val_t sweep_enabled; + val_t sweep_neg; + val_t noise_divider; + val_t wave_buf; + + val_t delay [4]; + val_t length_ctr [4]; + val_t phase [4]; + val_t enabled [4]; + + val_t env_delay [3]; + val_t env_volume [3]; + val_t env_enabled [3]; + + val_t unused [13]; // for future expansion +}; + +} + +#endif diff --git a/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/apu/Gb_Oscs.cpp b/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/apu/Gb_Oscs.cpp new file mode 100644 index 000000000..1f0763d25 --- /dev/null +++ b/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/apu/Gb_Oscs.cpp @@ -0,0 +1,669 @@ +// Gb_Snd_Emu 0.2.0. http://www.slack.net/~ant/ + +#include "Gb_Apu.h" + +/* Copyright (C) 2003-2007 Shay Green. This module is free software; you +can redistribute it and/or modify it under the terms of the GNU Lesser +General Public License as published by the Free Software Foundation; either +version 2.1 of the License, or (at your option) any later version. This +module is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more +details. You should have received a copy of the GNU Lesser General Public +License along with this module; if not, write to the Free Software Foundation, +Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ + +#include "blargg_source.h" + +namespace GBA { + +bool const cgb_02 = false; // enables bug in early CGB units that causes problems in some games +bool const cgb_05 = false; // enables CGB-05 zombie behavior + +int const trigger_mask = 0x80; +int const length_enabled = 0x40; + +void Gb_Osc::reset() +{ + output = 0; + last_amp = 0; + delay = 0; + phase = 0; + enabled = false; +} + +inline void Gb_Osc::update_amp( blip_time_t time, int new_amp ) +{ + output->set_modified(); + int delta = new_amp - last_amp; + if ( delta ) + { + last_amp = new_amp; + med_synth->offset( time, delta, output ); + } +} + +// Units + +void Gb_Osc::clock_length() +{ + if ( (regs [4] & length_enabled) && length_ctr ) + { + if ( --length_ctr <= 0 ) + enabled = false; + } +} + +inline int Gb_Env::reload_env_timer() +{ + int raw = regs [2] & 7; + env_delay = (raw ? raw : 8); + return raw; +} + +void Gb_Env::clock_envelope() +{ + if ( env_enabled && --env_delay <= 0 && reload_env_timer() ) + { + int v = volume + (regs [2] & 0x08 ? +1 : -1); + if ( 0 <= v && v <= 15 ) + volume = v; + else + env_enabled = false; + } +} + +inline void Gb_Sweep_Square::reload_sweep_timer() +{ + sweep_delay = (regs [0] & period_mask) >> 4; + if ( !sweep_delay ) + sweep_delay = 8; +} + +void Gb_Sweep_Square::calc_sweep( bool update ) +{ + int const shift = regs [0] & shift_mask; + int const delta = sweep_freq >> shift; + sweep_neg = (regs [0] & 0x08) != 0; + int const freq = sweep_freq + (sweep_neg ? -delta : delta); + + if ( freq > 0x7FF ) + { + enabled = false; + } + else if ( shift && update ) + { + sweep_freq = freq; + + regs [3] = freq & 0xFF; + regs [4] = (regs [4] & ~0x07) | (freq >> 8 & 0x07); + } +} + +void Gb_Sweep_Square::clock_sweep() +{ + if ( --sweep_delay <= 0 ) + { + reload_sweep_timer(); + if ( sweep_enabled && (regs [0] & period_mask) ) + { + calc_sweep( true ); + calc_sweep( false ); + } + } +} + +int Gb_Wave::access( unsigned addr ) const +{ + if ( enabled && mode != Gb_Apu::mode_agb ) + { + addr = phase & (bank_size - 1); + if ( mode == Gb_Apu::mode_dmg ) + { + addr++; + if ( delay > clk_mul ) + return -1; // can only access within narrow time window while playing + } + addr >>= 1; + } + return addr & 0x0F; +} + +// write_register + +int Gb_Osc::write_trig( int frame_phase, int max_len, int old_data ) +{ + int data = regs [4]; + + if ( (frame_phase & 1) && !(old_data & length_enabled) && length_ctr ) + { + if ( (data & length_enabled) || cgb_02 ) + length_ctr--; + } + + if ( data & trigger_mask ) + { + enabled = true; + if ( !length_ctr ) + { + length_ctr = max_len; + if ( (frame_phase & 1) && (data & length_enabled) ) + length_ctr--; + } + } + + if ( !length_ctr ) + enabled = false; + + return data & trigger_mask; +} + +inline void Gb_Env::zombie_volume( int old, int data ) +{ + int v = volume; + if ( mode == Gb_Apu::mode_agb || cgb_05 ) + { + // CGB-05 behavior, very close to AGB behavior as well + if ( (old ^ data) & 8 ) + { + if ( !(old & 8) ) + { + v++; + if ( old & 7 ) + v++; + } + + v = 16 - v; + } + else if ( (old & 0x0F) == 8 ) + { + v++; + } + } + else + { + // CGB-04&02 behavior, very close to MGB behavior as well + if ( !(old & 7) && env_enabled ) + v++; + else if ( !(old & 8) ) + v += 2; + + if ( (old ^ data) & 8 ) + v = 16 - v; + } + volume = v & 0x0F; +} + +bool Gb_Env::write_register( int frame_phase, int reg, int old, int data ) +{ + int const max_len = 64; + + switch ( reg ) + { + case 1: + length_ctr = max_len - (data & (max_len - 1)); + break; + + case 2: + if ( !dac_enabled() ) + enabled = false; + + zombie_volume( old, data ); + + if ( (data & 7) && env_delay == 8 ) + { + env_delay = 1; + clock_envelope(); // TODO: really happens at next length clock + } + break; + + case 4: + if ( write_trig( frame_phase, max_len, old ) ) + { + volume = regs [2] >> 4; + reload_env_timer(); + env_enabled = true; + if ( frame_phase == 7 ) + env_delay++; + if ( !dac_enabled() ) + enabled = false; + return true; + } + } + return false; +} + +bool Gb_Square::write_register( int frame_phase, int reg, int old_data, int data ) +{ + bool result = Gb_Env::write_register( frame_phase, reg, old_data, data ); + if ( result ) + delay = (delay & (4 * clk_mul - 1)) + period(); + return result; +} + +inline void Gb_Noise::write_register( int frame_phase, int reg, int old_data, int data ) +{ + if ( Gb_Env::write_register( frame_phase, reg, old_data, data ) ) + { + phase = 0x7FFF; + delay += 8 * clk_mul; + } +} + +inline void Gb_Sweep_Square::write_register( int frame_phase, int reg, int old_data, int data ) +{ + if ( reg == 0 && sweep_enabled && sweep_neg && !(data & 0x08) ) + enabled = false; // sweep negate disabled after used + + if ( Gb_Square::write_register( frame_phase, reg, old_data, data ) ) + { + sweep_freq = frequency(); + sweep_neg = false; + reload_sweep_timer(); + sweep_enabled = (regs [0] & (period_mask | shift_mask)) != 0; + if ( regs [0] & shift_mask ) + calc_sweep( false ); + } +} + +void Gb_Wave::corrupt_wave() +{ + int pos = ((phase + 1) & (bank_size - 1)) >> 1; + if ( pos < 4 ) + wave_ram [0] = wave_ram [pos]; + else + for ( int i = 4; --i >= 0; ) + wave_ram [i] = wave_ram [(pos & ~3) + i]; +} + +inline void Gb_Wave::write_register( int frame_phase, int reg, int old_data, int data ) +{ + int const max_len = 256; + + switch ( reg ) + { + case 0: + if ( !dac_enabled() ) + enabled = false; + break; + + case 1: + length_ctr = max_len - data; + break; + + case 4: + bool was_enabled = enabled; + if ( write_trig( frame_phase, max_len, old_data ) ) + { + if ( !dac_enabled() ) + enabled = false; + else if ( mode == Gb_Apu::mode_dmg && was_enabled && + (unsigned) (delay - 2 * clk_mul) < 2 * clk_mul ) + corrupt_wave(); + + phase = 0; + delay = period() + 6 * clk_mul; + } + } +} + +void Gb_Apu::write_osc( int index, int reg, int old_data, int data ) +{ + reg -= index * 5; + switch ( index ) + { + case 0: square1.write_register( frame_phase, reg, old_data, data ); break; + case 1: square2.write_register( frame_phase, reg, old_data, data ); break; + case 2: wave .write_register( frame_phase, reg, old_data, data ); break; + case 3: noise .write_register( frame_phase, reg, old_data, data ); break; + } +} + +// Synthesis + +void Gb_Square::run( blip_time_t time, blip_time_t end_time ) +{ + // Calc duty and phase + static byte const duty_offsets [4] = { 1, 1, 3, 7 }; + static byte const duties [4] = { 1, 2, 4, 6 }; + int const duty_code = regs [1] >> 6; + int duty_offset = duty_offsets [duty_code]; + int duty = duties [duty_code]; + if ( mode == Gb_Apu::mode_agb ) + { + // AGB uses inverted duty + duty_offset -= duty; + duty = 8 - duty; + } + int ph = (this->phase + duty_offset) & 7; + + // Determine what will be generated + int vol = 0; + Blip_Buffer* const out = this->output; + if ( out ) + { + int amp = dac_off_amp; + if ( dac_enabled() ) + { + if ( enabled ) + vol = this->volume; + + amp = -dac_bias; + if ( mode == Gb_Apu::mode_agb ) + amp = -(vol >> 1); + + // Play inaudible frequencies as constant amplitude + if ( frequency() >= 0x7FA && delay < 32 * clk_mul ) + { + amp += (vol * duty) >> 3; + vol = 0; + } + + if ( ph < duty ) + { + amp += vol; + vol = -vol; + } + } + update_amp( time, amp ); + } + + // Generate wave + time += delay; + if ( time < end_time ) + { + int const per = this->period(); + if ( !vol ) + { + // Maintain phase when not playing + int count = (end_time - time + per - 1) / per; + ph += count; // will be masked below + time += (blip_time_t) count * per; + } + else + { + // Output amplitude transitions + int delta = vol; + do + { + ph = (ph + 1) & 7; + if ( ph == 0 || ph == duty ) + { + good_synth->offset_inline( time, delta, out ); + delta = -delta; + } + time += per; + } + while ( time < end_time ); + + if ( delta != vol ) + last_amp -= delta; + } + this->phase = (ph - duty_offset) & 7; + } + delay = time - end_time; +} + +// Quickly runs LFSR for a large number of clocks. For use when noise is generating +// no sound. +static unsigned run_lfsr( unsigned s, unsigned mask, int count ) +{ + bool const optimized = true; // set to false to use only unoptimized loop in middle + + // optimization used in several places: + // ((s & (1 << b)) << n) ^ ((s & (1 << b)) << (n + 1)) = (s & (1 << b)) * (3 << n) + + if ( mask == 0x4000 && optimized ) + { + if ( count >= 32767 ) + count %= 32767; + + // Convert from Fibonacci to Galois configuration, + // shifted left 1 bit + s ^= (s & 1) * 0x8000; + + // Each iteration is equivalent to clocking LFSR 255 times + while ( (count -= 255) > 0 ) + s ^= ((s & 0xE) << 12) ^ ((s & 0xE) << 11) ^ (s >> 3); + count += 255; + + // Each iteration is equivalent to clocking LFSR 15 times + // (interesting similarity to single clocking below) + while ( (count -= 15) > 0 ) + s ^= ((s & 2) * (3 << 13)) ^ (s >> 1); + count += 15; + + // Remaining singles + while ( --count >= 0 ) + s = ((s & 2) * (3 << 13)) ^ (s >> 1); + + // Convert back to Fibonacci configuration + s &= 0x7FFF; + } + else if ( count < 8 || !optimized ) + { + // won't fully replace upper 8 bits, so have to do the unoptimized way + while ( --count >= 0 ) + s = (s >> 1 | mask) ^ (mask & -((s - 1) & 2)); + } + else + { + if ( count > 127 ) + { + count %= 127; + if ( !count ) + count = 127; // must run at least once + } + + // Need to keep one extra bit of history + s = s << 1 & 0xFF; + + // Convert from Fibonacci to Galois configuration, + // shifted left 2 bits + s ^= (s & 2) * 0x80; + + // Each iteration is equivalent to clocking LFSR 7 times + // (interesting similarity to single clocking below) + while ( (count -= 7) > 0 ) + s ^= ((s & 4) * (3 << 5)) ^ (s >> 1); + count += 7; + + // Remaining singles + while ( --count >= 0 ) + s = ((s & 4) * (3 << 5)) ^ (s >> 1); + + // Convert back to Fibonacci configuration and + // repeat last 8 bits above significant 7 + s = (s << 7 & 0x7F80) | (s >> 1 & 0x7F); + } + + return s; +} + +void Gb_Noise::run( blip_time_t time, blip_time_t end_time ) +{ + // Determine what will be generated + int vol = 0; + Blip_Buffer* const out = this->output; + if ( out ) + { + int amp = dac_off_amp; + if ( dac_enabled() ) + { + if ( enabled ) + vol = this->volume; + + amp = -dac_bias; + if ( mode == Gb_Apu::mode_agb ) + amp = -(vol >> 1); + + if ( !(phase & 1) ) + { + amp += vol; + vol = -vol; + } + } + + // AGB negates final output + if ( mode == Gb_Apu::mode_agb ) + { + vol = -vol; + amp = -amp; + } + + update_amp( time, amp ); + } + + // Run timer and calculate time of next LFSR clock + static byte const period1s [8] = { 1, 2, 4, 6, 8, 10, 12, 14 }; + int const period1 = period1s [regs [3] & 7] * clk_mul; + { + int extra = (end_time - time) - delay; + int const per2 = this->period2(); + time += delay + ((divider ^ (per2 >> 1)) & (per2 - 1)) * period1; + + int count = (extra < 0 ? 0 : (extra + period1 - 1) / period1); + divider = (divider - count) & period2_mask; + delay = count * period1 - extra; + } + + // Generate wave + if ( time < end_time ) + { + unsigned const mask = this->lfsr_mask(); + unsigned bits = this->phase; + + int per = period2( period1 * 8 ); + if ( period2_index() >= 0xE ) + { + time = end_time; + } + else if ( !vol ) + { + // Maintain phase when not playing + int count = (end_time - time + per - 1) / per; + time += (blip_time_t) count * per; + bits = run_lfsr( bits, ~mask, count ); + } + else + { + // Output amplitude transitions + int delta = -vol; + do + { + unsigned changed = bits + 1; + bits = bits >> 1 & mask; + if ( changed & 2 ) + { + bits |= ~mask; + delta = -delta; + med_synth->offset_inline( time, delta, out ); + } + time += per; + } + while ( time < end_time ); + + if ( delta == vol ) + last_amp += delta; + } + this->phase = bits; + } +} + +void Gb_Wave::run( blip_time_t time, blip_time_t end_time ) +{ + // Calc volume + static byte const volumes [8] = { 0, 4, 2, 1, 3, 3, 3, 3 }; + int const volume_shift = 2; + int const volume_idx = regs [2] >> 5 & (agb_mask | 3); // 2 bits on DMG/CGB, 3 on AGB + int const volume_mul = volumes [volume_idx]; + + // Determine what will be generated + int playing = false; + Blip_Buffer* const out = this->output; + if ( out ) + { + int amp = dac_off_amp; + if ( dac_enabled() ) + { + // Play inaudible frequencies as constant amplitude + amp = 8 << 4; // really depends on average of all samples in wave + + // if delay is larger, constant amplitude won't start yet + if ( frequency() <= 0x7FB || delay > 15 * clk_mul ) + { + if ( volume_mul ) + playing = (int) enabled; + + amp = (sample_buf << (phase << 2 & 4) & 0xF0) * playing; + } + + amp = ((amp * volume_mul) >> (volume_shift + 4)) - dac_bias; + } + update_amp( time, amp ); + } + + // Generate wave + time += delay; + if ( time < end_time ) + { + byte const* wave = this->wave_ram; + + // wave size and bank + int const size20_mask = 0x20; + int const flags = regs [0] & agb_mask; + int const wave_mask = (flags & size20_mask) | 0x1F; + int swap_banks = 0; + if ( flags & bank40_mask ) + { + swap_banks = flags & size20_mask; + wave += bank_size/2 - (swap_banks >> 1); + } + + int ph = this->phase ^ swap_banks; + ph = (ph + 1) & wave_mask; // pre-advance + + int const per = this->period(); + if ( !playing ) + { + // Maintain phase when not playing + int count = (end_time - time + per - 1) / per; + ph += count; // will be masked below + time += (blip_time_t) count * per; + } + else + { + // Output amplitude transitions + int lamp = this->last_amp + dac_bias; + do + { + // Extract nybble + int nybble = wave [ph >> 1] << (ph << 2 & 4) & 0xF0; + ph = (ph + 1) & wave_mask; + + // Scale by volume + int amp = (nybble * volume_mul) >> (volume_shift + 4); + + int delta = amp - lamp; + if ( delta ) + { + lamp = amp; + med_synth->offset_inline( time, delta, out ); + } + time += per; + } + while ( time < end_time ); + this->last_amp = lamp - dac_bias; + } + ph = (ph - 1) & wave_mask; // undo pre-advance and mask position + + // Keep track of last byte read + if ( enabled ) + sample_buf = wave [ph >> 1]; + + this->phase = ph ^ swap_banks; // undo swapped banks + } + delay = time - end_time; +} + +} diff --git a/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/apu/Gb_Oscs.h b/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/apu/Gb_Oscs.h new file mode 100644 index 000000000..4f8080025 --- /dev/null +++ b/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/apu/Gb_Oscs.h @@ -0,0 +1,194 @@ +// Private oscillators used by Gb_Apu + +// Gb_Snd_Emu 0.2.0 +#ifndef GB_OSCS_H +#define GB_OSCS_H + +#include "blargg_common.h" +#include "Blip_Buffer.h" + +#ifndef GB_APU_OVERCLOCK + #define GB_APU_OVERCLOCK 1 +#endif + +#if GB_APU_OVERCLOCK & (GB_APU_OVERCLOCK - 1) + #error "GB_APU_OVERCLOCK must be a power of 2" +#endif + +namespace GBA { + +class Gb_Osc { +protected: + + // 11-bit frequency in NRx3 and NRx4 + int frequency() const { return (regs [4] & 7) * 0x100 + regs [3]; } + + void update_amp( blip_time_t, int new_amp ); + int write_trig( int frame_phase, int max_len, int old_data ); +public: + + enum { clk_mul = GB_APU_OVERCLOCK }; + enum { dac_bias = 7 }; + + Blip_Buffer* outputs [4];// NULL, right, left, center + Blip_Buffer* output; // where to output sound + BOOST::uint8_t* regs; // osc's 5 registers + int mode; // mode_dmg, mode_cgb, mode_agb + int dac_off_amp;// amplitude when DAC is off + int last_amp; // current amplitude in Blip_Buffer + typedef Blip_Synth Good_Synth; + typedef Blip_Synth Med_Synth; + Good_Synth const* good_synth; + Med_Synth const* med_synth; + + int delay; // clocks until frequency timer expires + int length_ctr; // length counter + unsigned phase; // waveform phase (or equivalent) + bool enabled; // internal enabled flag + + void clock_length(); + void reset(); +}; + +class Gb_Env : public Gb_Osc { +public: + int env_delay; + int volume; + bool env_enabled; + + void clock_envelope(); + bool write_register( int frame_phase, int reg, int old_data, int data ); + + void reset() + { + env_delay = 0; + volume = 0; + Gb_Osc::reset(); + } +protected: + // Non-zero if DAC is enabled + int dac_enabled() const { return regs [2] & 0xF8; } +private: + void zombie_volume( int old, int data ); + int reload_env_timer(); +}; + +class Gb_Square : public Gb_Env { +public: + bool write_register( int frame_phase, int reg, int old_data, int data ); + void run( blip_time_t, blip_time_t ); + + void reset() + { + Gb_Env::reset(); + delay = 0x40000000; // TODO: something less hacky (never clocked until first trigger) + } +private: + // Frequency timer period + int period() const { return (2048 - frequency()) * (4 * clk_mul); } +}; + +class Gb_Sweep_Square : public Gb_Square { +public: + int sweep_freq; + int sweep_delay; + bool sweep_enabled; + bool sweep_neg; + + void clock_sweep(); + void write_register( int frame_phase, int reg, int old_data, int data ); + + void reset() + { + sweep_freq = 0; + sweep_delay = 0; + sweep_enabled = false; + sweep_neg = false; + Gb_Square::reset(); + } +private: + enum { period_mask = 0x70 }; + enum { shift_mask = 0x07 }; + + void calc_sweep( bool update ); + void reload_sweep_timer(); +}; + +class Gb_Noise : public Gb_Env { +public: + + int divider; // noise has more complex frequency divider setup + + void run( blip_time_t, blip_time_t ); + void write_register( int frame_phase, int reg, int old_data, int data ); + + void reset() + { + divider = 0; + Gb_Env::reset(); + delay = 4 * clk_mul; // TODO: remove? + } +private: + enum { period2_mask = 0x1FFFF }; + + int period2_index() const { return regs [3] >> 4; } + int period2( int base = 8 ) const { return base << period2_index(); } + unsigned lfsr_mask() const { return (regs [3] & 0x08) ? ~0x4040 : ~0x4000; } +}; + +class Gb_Wave : public Gb_Osc { +public: + int sample_buf; // last wave RAM byte read (hardware has this as well) + + void write_register( int frame_phase, int reg, int old_data, int data ); + void run( blip_time_t, blip_time_t ); + + // Reads/writes wave RAM + int read( unsigned addr ) const; + void write( unsigned addr, int data ); + + void reset() + { + sample_buf = 0; + Gb_Osc::reset(); + } + +private: + enum { bank40_mask = 0x40 }; + enum { bank_size = 32 }; + + int agb_mask; // 0xFF if AGB features enabled, 0 otherwise + BOOST::uint8_t* wave_ram; // 32 bytes (64 nybbles), stored in APU + + friend class Gb_Apu; + + // Frequency timer period + int period() const { return (2048 - frequency()) * (2 * clk_mul); } + + // Non-zero if DAC is enabled + int dac_enabled() const { return regs [0] & 0x80; } + + void corrupt_wave(); + + BOOST::uint8_t* wave_bank() const { return &wave_ram [(~regs [0] & bank40_mask) >> 2 & agb_mask]; } + + // Wave index that would be accessed, or -1 if no access would occur + int access( unsigned addr ) const; +}; + +inline int Gb_Wave::read( unsigned addr ) const +{ + int index = access( addr ); + return (index < 0 ? 0xFF : wave_bank() [index]); +} + +inline void Gb_Wave::write( unsigned addr, int data ) +{ + int index = access( addr ); + if ( index >= 0 ) + wave_bank() [index] = data;; +} + +} + +#endif diff --git a/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/apu/Multi_Buffer.cpp b/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/apu/Multi_Buffer.cpp new file mode 100644 index 000000000..dfbf0771c --- /dev/null +++ b/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/apu/Multi_Buffer.cpp @@ -0,0 +1,285 @@ +// Blip_Buffer 0.4.1. http://www.slack.net/~ant/ + +#include "Multi_Buffer.h" + +/* Copyright (C) 2003-2007 Shay Green. This module is free software; you +can redistribute it and/or modify it under the terms of the GNU Lesser +General Public License as published by the Free Software Foundation; either +version 2.1 of the License, or (at your option) any later version. This +module is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more +details. You should have received a copy of the GNU Lesser General Public +License along with this module; if not, write to the Free Software Foundation, +Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ + +#include "blargg_source.h" + +namespace GBA { + +#ifdef BLARGG_ENABLE_OPTIMIZER + #include BLARGG_ENABLE_OPTIMIZER +#endif + +Multi_Buffer::Multi_Buffer( int spf ) : samples_per_frame_( spf ) +{ + length_ = 0; + sample_rate_ = 0; + channels_changed_count_ = 1; + channel_types_ = 0; + channel_count_ = 0; + immediate_removal_ = true; +} + +Multi_Buffer::channel_t Multi_Buffer::channel( int /*index*/ ) +{ + static channel_t const ch = { 0, 0, 0 }; + return ch; +} + +// Silent_Buffer + +Silent_Buffer::Silent_Buffer() : Multi_Buffer( 1 ) // 0 channels would probably confuse +{ + // TODO: better to use empty Blip_Buffer so caller never has to check for NULL? + chan.left = 0; + chan.center = 0; + chan.right = 0; +} + +// Mono_Buffer + +Mono_Buffer::Mono_Buffer() : Multi_Buffer( 1 ) +{ + chan.center = &buf; + chan.left = &buf; + chan.right = &buf; +} + +Mono_Buffer::~Mono_Buffer() { } + +blargg_err_t Mono_Buffer::set_sample_rate( long rate, int msec ) +{ + RETURN_ERR( buf.set_sample_rate( rate, msec ) ); + return Multi_Buffer::set_sample_rate( buf.sample_rate(), buf.length() ); +} + + +// Tracked_Blip_Buffer + +Tracked_Blip_Buffer::Tracked_Blip_Buffer() +{ + last_non_silence = 0; +} + +void Tracked_Blip_Buffer::clear() +{ + last_non_silence = 0; + Blip_Buffer::clear(); +} + +void Tracked_Blip_Buffer::end_frame( blip_time_t t ) +{ + Blip_Buffer::end_frame( t ); + if ( clear_modified() ) + last_non_silence = samples_avail() + blip_buffer_extra_; +} + +blip_ulong Tracked_Blip_Buffer::non_silent() const +{ + return last_non_silence | unsettled(); +} + +inline void Tracked_Blip_Buffer::remove_( long n ) +{ + if ( (last_non_silence -= n) < 0 ) + last_non_silence = 0; +} + +void Tracked_Blip_Buffer::remove_silence( long n ) +{ + remove_( n ); + Blip_Buffer::remove_silence( n ); +} + +void Tracked_Blip_Buffer::remove_samples( long n ) +{ + remove_( n ); + Blip_Buffer::remove_samples( n ); +} + +void Tracked_Blip_Buffer::remove_all_samples() +{ + long avail = samples_avail(); + if ( !non_silent() ) + remove_silence( avail ); + else + remove_samples( avail ); +} + +long Tracked_Blip_Buffer::read_samples( blip_sample_t* out, long count ) +{ + count = Blip_Buffer::read_samples( out, count ); + remove_( count ); + return count; +} + +// Stereo_Buffer + +int const stereo = 2; + +Stereo_Buffer::Stereo_Buffer() : Multi_Buffer( 2 ) +{ + chan.center = mixer.bufs [2] = &bufs [2]; + chan.left = mixer.bufs [0] = &bufs [0]; + chan.right = mixer.bufs [1] = &bufs [1]; + mixer.samples_read = 0; +} + +Stereo_Buffer::~Stereo_Buffer() { } + +blargg_err_t Stereo_Buffer::set_sample_rate( long rate, int msec ) +{ + mixer.samples_read = 0; + for ( int i = bufs_size; --i >= 0; ) + RETURN_ERR( bufs [i].set_sample_rate( rate, msec ) ); + return Multi_Buffer::set_sample_rate( bufs [0].sample_rate(), bufs [0].length() ); +} + +void Stereo_Buffer::clock_rate( long rate ) +{ + for ( int i = bufs_size; --i >= 0; ) + bufs [i].clock_rate( rate ); +} + +void Stereo_Buffer::bass_freq( int bass ) +{ + for ( int i = bufs_size; --i >= 0; ) + bufs [i].bass_freq( bass ); +} + +void Stereo_Buffer::clear() +{ + mixer.samples_read = 0; + for ( int i = bufs_size; --i >= 0; ) + bufs [i].clear(); +} + +void Stereo_Buffer::end_frame( blip_time_t time ) +{ + for ( int i = bufs_size; --i >= 0; ) + bufs [i].end_frame( time ); +} + +long Stereo_Buffer::read_samples( blip_sample_t* out, long out_size ) +{ + require( (out_size & 1) == 0 ); // must read an even number of samples + out_size = min( out_size, samples_avail() ); + + int pair_count = int (out_size >> 1); + if ( pair_count ) + { + mixer.read_pairs( out, pair_count ); + + if ( samples_avail() <= 0 || immediate_removal() ) + { + for ( int i = bufs_size; --i >= 0; ) + { + buf_t& b = bufs [i]; + // TODO: might miss non-silence settling since it checks END of last read + if ( !b.non_silent() ) + b.remove_silence( mixer.samples_read ); + else + b.remove_samples( mixer.samples_read ); + } + mixer.samples_read = 0; + } + } + return out_size; +} + + +// Stereo_Mixer + +// mixers use a single index value to improve performance on register-challenged processors +// offset goes from negative to zero + +void Stereo_Mixer::read_pairs( blip_sample_t* out, int count ) +{ + // TODO: if caller never marks buffers as modified, uses mono + // except that buffer isn't cleared, so caller can encounter + // subtle problems and not realize the cause. + samples_read += count; + if ( bufs [0]->non_silent() | bufs [1]->non_silent() ) + mix_stereo( out, count ); + else + mix_mono( out, count ); +} + +void Stereo_Mixer::mix_mono( blip_sample_t* out_, int count ) +{ + int const bass = BLIP_READER_BASS( *bufs [2] ); + BLIP_READER_BEGIN( center, *bufs [2] ); + BLIP_READER_ADJ_( center, samples_read ); + + typedef blip_sample_t stereo_blip_sample_t [stereo]; + stereo_blip_sample_t* BLIP_RESTRICT out = (stereo_blip_sample_t*) out_ + count; + int offset = -count; + do + { + blargg_long s = BLIP_READER_READ( center ); + BLIP_READER_NEXT_IDX_( center, bass, offset ); + BLIP_CLAMP( s, s ); + + out [offset] [0] = (blip_sample_t) s; + out [offset] [1] = (blip_sample_t) s; + } + while ( ++offset ); + + BLIP_READER_END( center, *bufs [2] ); +} + +void Stereo_Mixer::mix_stereo( blip_sample_t* out_, int count ) +{ + blip_sample_t* BLIP_RESTRICT out = out_ + count * stereo; + + // do left + center and right + center separately to reduce register load + Tracked_Blip_Buffer* const* buf = &bufs [2]; + while ( true ) // loop runs twice + { + --buf; + --out; + + int const bass = BLIP_READER_BASS( *bufs [2] ); + BLIP_READER_BEGIN( side, **buf ); + BLIP_READER_BEGIN( center, *bufs [2] ); + + BLIP_READER_ADJ_( side, samples_read ); + BLIP_READER_ADJ_( center, samples_read ); + + int offset = -count; + do + { + blargg_long s = BLIP_READER_READ_RAW( center ) + BLIP_READER_READ_RAW( side ); + s >>= blip_sample_bits - 16; + BLIP_READER_NEXT_IDX_( side, bass, offset ); + BLIP_READER_NEXT_IDX_( center, bass, offset ); + BLIP_CLAMP( s, s ); + + ++offset; // before write since out is decremented to slightly before end + out [offset * stereo] = (blip_sample_t) s; + } + while ( offset ); + + BLIP_READER_END( side, **buf ); + + if ( buf != bufs ) + continue; + + // only end center once + BLIP_READER_END( center, *bufs [2] ); + break; + } +} + +} diff --git a/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/apu/Multi_Buffer.h b/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/apu/Multi_Buffer.h new file mode 100644 index 000000000..0a347f157 --- /dev/null +++ b/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/apu/Multi_Buffer.h @@ -0,0 +1,209 @@ +// Multi-channel sound buffer interface, and basic mono and stereo buffers + +// Blip_Buffer 0.4.1 +#ifndef MULTI_BUFFER_H +#define MULTI_BUFFER_H + +#include "blargg_common.h" +#include "Blip_Buffer.h" + +namespace GBA { + +// Interface to one or more Blip_Buffers mapped to one or more channels +// consisting of left, center, and right buffers. +class Multi_Buffer { +public: + Multi_Buffer( int samples_per_frame ); + virtual ~Multi_Buffer() { } + + // Sets the number of channels available and optionally their types + // (type information used by Effects_Buffer) + enum { type_index_mask = 0xFF }; + enum { wave_type = 0x100, noise_type = 0x200, mixed_type = wave_type | noise_type }; + virtual blargg_err_t set_channel_count( int, int const* types = 0 ); + int channel_count() const { return channel_count_; } + + // Gets indexed channel, from 0 to channel count - 1 + struct channel_t { + Blip_Buffer* center; + Blip_Buffer* left; + Blip_Buffer* right; + }; + virtual channel_t channel( int index ) BLARGG_PURE( ; ) + + // See Blip_Buffer.h + virtual blargg_err_t set_sample_rate( long rate, int msec = blip_default_length ) BLARGG_PURE( ; ) + virtual void clock_rate( long ) BLARGG_PURE( { } ) + virtual void bass_freq( int ) BLARGG_PURE( { } ) + virtual void clear() BLARGG_PURE( { } ) + long sample_rate() const; + + // Length of buffer, in milliseconds + int length() const; + + // See Blip_Buffer.h + virtual void end_frame( blip_time_t ) BLARGG_PURE( { } ) + + // Number of samples per output frame (1 = mono, 2 = stereo) + int samples_per_frame() const; + + // Count of changes to channel configuration. Incremented whenever + // a change is made to any of the Blip_Buffers for any channel. + unsigned channels_changed_count() { return channels_changed_count_; } + + // See Blip_Buffer.h + virtual long read_samples( blip_sample_t*, long ) BLARGG_PURE( { return 0; } ) + virtual long samples_avail() const BLARGG_PURE( { return 0; } ) + +public: + BLARGG_DISABLE_NOTHROW + void disable_immediate_removal() { immediate_removal_ = false; } +protected: + bool immediate_removal() const { return immediate_removal_; } + int const* channel_types() const { return channel_types_; } + void channels_changed() { channels_changed_count_++; } +private: + // noncopyable + Multi_Buffer( const Multi_Buffer& ); + Multi_Buffer& operator = ( const Multi_Buffer& ); + + unsigned channels_changed_count_; + long sample_rate_; + int length_; + int channel_count_; + int const samples_per_frame_; + int const* channel_types_; + bool immediate_removal_; +}; + +// Uses a single buffer and outputs mono samples. +class Mono_Buffer : public Multi_Buffer { + Blip_Buffer buf; + channel_t chan; +public: + // Buffer used for all channels + Blip_Buffer* center() { return &buf; } + +public: + Mono_Buffer(); + ~Mono_Buffer(); + blargg_err_t set_sample_rate( long rate, int msec = blip_default_length ); + void clock_rate( long rate ) { buf.clock_rate( rate ); } + void bass_freq( int freq ) { buf.bass_freq( freq ); } + void clear() { buf.clear(); } + long samples_avail() const { return buf.samples_avail(); } + long read_samples( blip_sample_t* p, long s ) { return buf.read_samples( p, s ); } + channel_t channel( int ) { return chan; } + void end_frame( blip_time_t t ) { buf.end_frame( t ); } +}; + + class Tracked_Blip_Buffer : public Blip_Buffer { + public: + // Non-zero if buffer still has non-silent samples in it. Requires that you call + // set_modified() appropriately. + blip_ulong non_silent() const; + + // remove_samples( samples_avail() ) + void remove_all_samples(); + + public: + BLARGG_DISABLE_NOTHROW + + long read_samples( blip_sample_t*, long ); + void remove_silence( long ); + void remove_samples( long ); + Tracked_Blip_Buffer(); + void clear(); + void end_frame( blip_time_t ); + private: + blip_long last_non_silence; + void remove_( long ); + }; + + class Stereo_Mixer { + public: + Tracked_Blip_Buffer* bufs [3]; + blargg_long samples_read; + + Stereo_Mixer() : samples_read( 0 ) { } + void read_pairs( blip_sample_t* out, int count ); + private: + void mix_mono ( blip_sample_t* out, int pair_count ); + void mix_stereo( blip_sample_t* out, int pair_count ); + }; + +// Uses three buffers (one for center) and outputs stereo sample pairs. +class Stereo_Buffer : public Multi_Buffer { +public: + + // Buffers used for all channels + Blip_Buffer* center() { return &bufs [2]; } + Blip_Buffer* left() { return &bufs [0]; } + Blip_Buffer* right() { return &bufs [1]; } + +public: + Stereo_Buffer(); + ~Stereo_Buffer(); + blargg_err_t set_sample_rate( long, int msec = blip_default_length ); + void clock_rate( long ); + void bass_freq( int ); + void clear(); + channel_t channel( int ) { return chan; } + void end_frame( blip_time_t ); + + long samples_avail() const { return (bufs [0].samples_avail() - mixer.samples_read) * 2; } + long read_samples( blip_sample_t*, long ); + +private: + enum { bufs_size = 3 }; + typedef Tracked_Blip_Buffer buf_t; + buf_t bufs [bufs_size]; + Stereo_Mixer mixer; + channel_t chan; + long samples_avail_; +}; + +// Silent_Buffer generates no samples, useful where no sound is wanted +class Silent_Buffer : public Multi_Buffer { + channel_t chan; +public: + Silent_Buffer(); + blargg_err_t set_sample_rate( long rate, int msec = blip_default_length ); + void clock_rate( long ) { } + void bass_freq( int ) { } + void clear() { } + channel_t channel( int ) { return chan; } + void end_frame( blip_time_t ) { } + long samples_avail() const { return 0; } + long read_samples( blip_sample_t*, long ) { return 0; } +}; + + +inline blargg_err_t Multi_Buffer::set_sample_rate( long rate, int msec ) +{ + sample_rate_ = rate; + length_ = msec; + return 0; +} + +inline blargg_err_t Silent_Buffer::set_sample_rate( long rate, int msec ) +{ + return Multi_Buffer::set_sample_rate( rate, msec ); +} + +inline int Multi_Buffer::samples_per_frame() const { return samples_per_frame_; } + +inline long Multi_Buffer::sample_rate() const { return sample_rate_; } + +inline int Multi_Buffer::length() const { return length_; } + +inline blargg_err_t Multi_Buffer::set_channel_count( int n, int const* types ) +{ + channel_count_ = n; + channel_types_ = types; + return 0; +} + +} + +#endif diff --git a/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/apu/blargg_common.h b/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/apu/blargg_common.h new file mode 100644 index 000000000..1203d3878 --- /dev/null +++ b/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/apu/blargg_common.h @@ -0,0 +1,206 @@ +// Sets up common environment for Shay Green's libraries. +// To change configuration options, modify blargg_config.h, not this file. + +// Gb_Snd_Emu 0.2.0 +#ifndef BLARGG_COMMON_H +#define BLARGG_COMMON_H + +#include +#include +#include +#include + +#undef BLARGG_COMMON_H +// allow blargg_config.h to #include blargg_common.h +#include "blargg_config.h" +#ifndef BLARGG_COMMON_H +#define BLARGG_COMMON_H + +// BLARGG_RESTRICT: equivalent to restrict, where supported +#if __GNUC__ >= 3 || _MSC_VER >= 1100 + #define BLARGG_RESTRICT __restrict +#else + #define BLARGG_RESTRICT +#endif + +// STATIC_CAST(T,expr): Used in place of static_cast (expr) +// CONST_CAST( T,expr): Used in place of const_cast (expr) +#ifndef STATIC_CAST + #if __GNUC__ >= 4 + #define STATIC_CAST(T,expr) static_cast (expr) + #define CONST_CAST( T,expr) const_cast (expr) + #else + #define STATIC_CAST(T,expr) ((T) (expr)) + #define CONST_CAST( T,expr) ((T) (expr)) + #endif +#endif + +// blargg_err_t (0 on success, otherwise error string) +#ifndef blargg_err_t + typedef const char* blargg_err_t; +#endif + +// blargg_vector - very lightweight vector of POD types (no constructor/destructor) +template +class blargg_vector { + T* begin_; + size_t size_; +public: + blargg_vector() : begin_( 0 ), size_( 0 ) { } + ~blargg_vector() { free( begin_ ); } + size_t size() const { return size_; } + T* begin() const { return begin_; } + T* end() const { return begin_ + size_; } + blargg_err_t resize( size_t n ) + { + // TODO: blargg_common.cpp to hold this as an outline function, ugh + void* p = realloc( begin_, n * sizeof (T) ); + if ( p ) + begin_ = (T*) p; + else if ( n > size_ ) // realloc failure only a problem if expanding + return "Out of memory"; + size_ = n; + return 0; + } + void clear() { void* p = begin_; begin_ = 0; size_ = 0; free( p ); } + T& operator [] ( size_t n ) const + { + assert( n <= size_ ); // <= to allow past-the-end value + return begin_ [n]; + } +}; + +#ifndef BLARGG_DISABLE_NOTHROW + // throw spec mandatory in ISO C++ if operator new can return NULL + #if __cplusplus >= 199711 || __GNUC__ >= 3 + #define BLARGG_THROWS( spec ) throw spec + #else + #define BLARGG_THROWS( spec ) + #endif + #define BLARGG_DISABLE_NOTHROW \ + void* operator new ( size_t s ) BLARGG_THROWS(()) { return malloc( s ); }\ + void operator delete ( void* p ) { free( p ); } + #define BLARGG_NEW new +#else + #include + #define BLARGG_NEW new (std::nothrow) +#endif + +// BLARGG_4CHAR('a','b','c','d') = 'abcd' (four character integer constant) +#define BLARGG_4CHAR( a, b, c, d ) \ + ((a&0xFF)*0x1000000 + (b&0xFF)*0x10000 + (c&0xFF)*0x100 + (d&0xFF)) + +// BOOST_STATIC_ASSERT( expr ): Generates compile error if expr is 0. +#ifndef BOOST_STATIC_ASSERT + #ifdef _MSC_VER + // MSVC6 (_MSC_VER < 1300) fails for use of __LINE__ when /Zl is specified + #define BOOST_STATIC_ASSERT( expr ) \ + void blargg_failed_( int (*arg) [2 / (int) !!(expr) - 1] ) + #else + // Some other compilers fail when declaring same function multiple times in class, + // so differentiate them by line + #define BOOST_STATIC_ASSERT( expr ) \ + void blargg_failed_( int (*arg) [2 / !!(expr) - 1] [__LINE__] ) + #endif +#endif + +// BLARGG_COMPILER_HAS_BOOL: If 0, provides bool support for old compiler. If 1, +// compiler is assumed to support bool. If undefined, availability is determined. +#ifndef BLARGG_COMPILER_HAS_BOOL + #if defined (__MWERKS__) + #if !__option(bool) + #define BLARGG_COMPILER_HAS_BOOL 0 + #endif + #elif defined (_MSC_VER) + #if _MSC_VER < 1100 + #define BLARGG_COMPILER_HAS_BOOL 0 + #endif + #elif defined (__GNUC__) + // supports bool + #elif __cplusplus < 199711 + #define BLARGG_COMPILER_HAS_BOOL 0 + #endif +#endif +#if defined (BLARGG_COMPILER_HAS_BOOL) && !BLARGG_COMPILER_HAS_BOOL + // If you get errors here, modify your blargg_config.h file + typedef int bool; + const bool true = 1; + const bool false = 0; +#endif + +// blargg_long/blargg_ulong = at least 32 bits, int if it's big enough + +#if INT_MAX < 0x7FFFFFFF || LONG_MAX == 0x7FFFFFFF + typedef long blargg_long; +#else + typedef int blargg_long; +#endif + +#if UINT_MAX < 0xFFFFFFFF || ULONG_MAX == 0xFFFFFFFF + typedef unsigned long blargg_ulong; +#else + typedef unsigned blargg_ulong; +#endif + +// BOOST::int8_t etc. + +// HAVE_STDINT_H: If defined, use for int8_t etc. +#if defined (HAVE_STDINT_H) + #include + #define BOOST + +// HAVE_INTTYPES_H: If defined, use for int8_t etc. +#elif defined (HAVE_INTTYPES_H) + #include + #define BOOST + +#else + struct BOOST + { + #if UCHAR_MAX == 0xFF && SCHAR_MAX == 0x7F + typedef signed char int8_t; + typedef unsigned char uint8_t; + #else + // No suitable 8-bit type available + typedef struct see_blargg_common_h int8_t; + typedef struct see_blargg_common_h uint8_t; + #endif + + #if USHRT_MAX == 0xFFFF + typedef short int16_t; + typedef unsigned short uint16_t; + #else + // No suitable 16-bit type available + typedef struct see_blargg_common_h int16_t; + typedef struct see_blargg_common_h uint16_t; + #endif + + #if ULONG_MAX == 0xFFFFFFFF + typedef long int32_t; + typedef unsigned long uint32_t; + #elif UINT_MAX == 0xFFFFFFFF + typedef int int32_t; + typedef unsigned int uint32_t; + #else + // No suitable 32-bit type available + typedef struct see_blargg_common_h int32_t; + typedef struct see_blargg_common_h uint32_t; + #endif + }; +#endif + +#if __GNUC__ >= 3 + #define BLARGG_DEPRECATED __attribute__ ((deprecated)) +#else + #define BLARGG_DEPRECATED +#endif + +// Use in place of "= 0;" for a pure virtual, since these cause calls to std C++ lib. +// During development, BLARGG_PURE( x ) expands to = 0; +// virtual int func() BLARGG_PURE( { return 0; } ) +#ifndef BLARGG_PURE + #define BLARGG_PURE( def ) def +#endif + +#endif +#endif diff --git a/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/apu/blargg_config.h b/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/apu/blargg_config.h new file mode 100644 index 000000000..961e04532 --- /dev/null +++ b/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/apu/blargg_config.h @@ -0,0 +1,33 @@ +// $package user configuration file. Don't replace when updating library. + +#ifndef BLARGG_CONFIG_H +#define BLARGG_CONFIG_H + +// Uncomment to have Gb_Apu run at 4x normal clock rate (16777216 Hz), useful in +// a Game Boy Advance emulator. +#define GB_APU_OVERCLOCK 4 + +#define GB_APU_CUSTOM_STATE 1 + +// Uncomment to enable platform-specific (and possibly non-portable) optimizations. +//#define BLARGG_NONPORTABLE 1 + +// Uncomment if automatic byte-order determination doesn't work +//#define BLARGG_BIG_ENDIAN 1 + +// Uncomment to use zlib for transparent decompression of gzipped files +//#define HAVE_ZLIB_H + +// Uncomment if you get errors in the bool section of blargg_common.h +//#define BLARGG_COMPILER_HAS_BOOL 1 + +// Uncomment to disable out-of-memory exceptions +//#include +//#define BLARGG_NEW new (std::nothrow) + +// Use standard config.h if present +#ifdef HAVE_CONFIG_H + #include "config.h" +#endif + +#endif diff --git a/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/apu/blargg_source.h b/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/apu/blargg_source.h new file mode 100644 index 000000000..ddef37d61 --- /dev/null +++ b/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/apu/blargg_source.h @@ -0,0 +1,92 @@ +/* Included at the beginning of library source files, AFTER all other #include lines. +Sets up helpful macros and services used in my source code. Since this is only "active" +in my source code, I don't have to worry about polluting the global namespace with +unprefixed names. */ + +// Gb_Snd_Emu 0.2.0 +#ifndef BLARGG_SOURCE_H +#define BLARGG_SOURCE_H + +// The following four macros are for debugging only. Some or all might be defined +// to do nothing, depending on the circumstances. Described is what happens when +// a particular macro is defined to do something. When defined to do nothing, the +// macros do NOT evaluate their argument(s). + +// If expr is false, prints file and line number, then aborts program. Meant for +// checking internal state and consistency. A failed assertion indicates a bug +// in MY code. +// +// void assert( bool expr ); +#include + +// If expr is false, prints file and line number, then aborts program. Meant for +// checking caller-supplied parameters and operations that are outside the control +// of the module. A failed requirement probably indicates a bug in YOUR code. +// +// void require( bool expr ); +#undef require +#define require( expr ) assert( expr ) + +// Like printf() except output goes to debugging console/file. +// +// void dprintf( const char* format, ... ); +static inline void blargg_dprintf_( const char*, ... ) { } +#undef dprintf +#define dprintf (1) ? (void) 0 : blargg_dprintf_ + +// If expr is false, prints file and line number to debug console/log, then +// continues execution normally. Meant for flagging potential problems or things +// that should be looked into, but that aren't serious problems. +// +// void check( bool expr ); +#undef check +#define check( expr ) ((void) 0) + +// If expr yields non-NULL error string, returns it from current function, +// otherwise continues normally. +#undef RETURN_ERR +#define RETURN_ERR( expr ) do { \ + blargg_err_t blargg_return_err_ = (expr); \ + if ( blargg_return_err_ ) return blargg_return_err_; \ + } while ( 0 ) + +// If ptr is NULL, returns "Out of memory" error string, otherwise continues normally. +#undef CHECK_ALLOC +#define CHECK_ALLOC( ptr ) do { if ( (ptr) == 0 ) return "Out of memory"; } while ( 0 ) + +// The usual min/max functions for built-in types. +// +// template T min( T x, T y ) { return x < y ? x : y; } +// template T max( T x, T y ) { return x > y ? x : y; } +#define BLARGG_DEF_MIN_MAX( type ) \ + static inline type blargg_min( type x, type y ) { if ( y < x ) x = y; return x; }\ + static inline type blargg_max( type x, type y ) { if ( x < y ) x = y; return x; } + +BLARGG_DEF_MIN_MAX( int ) +BLARGG_DEF_MIN_MAX( unsigned ) +BLARGG_DEF_MIN_MAX( long ) +BLARGG_DEF_MIN_MAX( unsigned long ) +BLARGG_DEF_MIN_MAX( float ) +BLARGG_DEF_MIN_MAX( double ) + +#undef min +#define min blargg_min + +#undef max +#define max blargg_max + +// typedef unsigned char byte; +typedef unsigned char blargg_byte; +#undef byte +#define byte blargg_byte + +// deprecated +#define BLARGG_CHECK_ALLOC CHECK_ALLOC +#define BLARGG_RETURN_ERR RETURN_ERR + +// BLARGG_SOURCE_BEGIN: If defined, #included, allowing redefition of dprintf and check +#ifdef BLARGG_SOURCE_BEGIN + #include BLARGG_SOURCE_BEGIN +#endif + +#endif diff --git a/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/common/Port.h b/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/common/Port.h new file mode 100644 index 000000000..081ead62e --- /dev/null +++ b/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/common/Port.h @@ -0,0 +1,56 @@ +#ifndef PORT_H +#define PORT_H + +// swaps a 16-bit value +static inline u16 swap16(u16 v) +{ + return (v<<8)|(v>>8); +} + +// swaps a 32-bit value +static inline u32 swap32(u32 v) +{ + return (v<<24)|((v<<8)&0xff0000)|((v>>8)&0xff00)|(v>>24); +} + +#ifdef WORDS_BIGENDIAN +#if defined(__GNUC__) && defined(__ppc__) + +#define READ16LE(base) \ + ({ unsigned short lhbrxResult; \ + __asm__ ("lhbrx %0, 0, %1" : "=r" (lhbrxResult) : "r" (base) : "memory"); \ + lhbrxResult; }) + +#define READ32LE(base) \ + ({ unsigned long lwbrxResult; \ + __asm__ ("lwbrx %0, 0, %1" : "=r" (lwbrxResult) : "r" (base) : "memory"); \ + lwbrxResult; }) + +#define WRITE16LE(base, value) \ + __asm__ ("sthbrx %0, 0, %1" : : "r" (value), "r" (base) : "memory") + +#define WRITE32LE(base, value) \ + __asm__ ("stwbrx %0, 0, %1" : : "r" (value), "r" (base) : "memory") + +#else +#define READ16LE(x) \ + swap16(*((u16 *)(x))) +#define READ32LE(x) \ + swap32(*((u32 *)(x))) +#define WRITE16LE(x,v) \ + *((u16 *)x) = swap16((v)) +#define WRITE32LE(x,v) \ + *((u32 *)x) = swap32((v)) +#endif +#else +#define READ16LE(x) \ + *((u16 *)x) +#define READ32LE(x) \ + *((u32 *)x) +#define WRITE16LE(x,v) \ + *((u16 *)x) = (v) +#define WRITE32LE(x,v) \ + *((u32 *)x) = (v) +#endif + +#endif // PORT_H diff --git a/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/common/Types.h b/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/common/Types.h new file mode 100644 index 000000000..8433576dc --- /dev/null +++ b/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/common/Types.h @@ -0,0 +1,33 @@ +// VisualBoyAdvance - Nintendo Gameboy/GameboyAdvance (TM) emulator. +// Copyright (C) 2008 VBA-M development team + +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2, or(at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software Foundation, +// Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +#ifndef __VBA_TYPES_H__ +#define __VBA_TYPES_H__ + +#include + +typedef uint8_t u8; +typedef uint16_t u16; +typedef uint32_t u32; +typedef uint64_t u64; + +typedef int8_t s8; +typedef int16_t s16; +typedef int32_t s32; +typedef int64_t s64; + +#endif // __VBA_TYPES_H__ diff --git a/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/gba/GBA-arm.cpp b/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/gba/GBA-arm.cpp new file mode 100644 index 000000000..37930b9fd --- /dev/null +++ b/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/gba/GBA-arm.cpp @@ -0,0 +1,2275 @@ +#include +#include +#include +#include +#include + +#include "GBA.h" +#include "GBAcpu.h" +#include "GBAinline.h" +#include "Globals.h" + +#include "Sound.h" +#include "bios.h" +#include "../common/Types.h" + +#ifdef _MSC_VER + // Disable "empty statement" warnings + #pragma warning(disable: 4390) + // Visual C's inline assembler treats "offset" as a reserved word, so we + // tell it otherwise. If you want to use it, write "OFFSET" in capitals. + #define offset offset_ +#endif + +/////////////////////////////////////////////////////////////////////////// + +static INSN_REGPARM void armUnknownInsn(GBASystem *gba, u32 opcode) +{ + CPUUndefinedException(gba); +} + +// Common macros ////////////////////////////////////////////////////////// + +#define CONSOLE_OUTPUT(a,b) /* nothing */ + +#define NEG(i) ((i) >> 31) +#define POS(i) ((~(i)) >> 31) + +// The following macros are used for optimization; any not defined for a +// particular compiler/CPU combination default to the C core versions. +// +// ALU_INIT_C: Used at the beginning of ALU instructions (AND/EOR/...). +// (ALU_INIT_NC) Can consist of variable declarations, like the C core, +// or the start of a continued assembly block, like the +// x86-optimized version. The _C version is used when the +// carry flag from the shift operation is needed (logical +// operations that set condition codes, like ANDS); the +// _NC version is used when the carry result is ignored. +// VALUE_XXX: Retrieve the second operand's value for an ALU instruction. +// The _C and _NC versions are used the same way as ALU_INIT. +// OP_XXX: ALU operations. XXX is the instruction name. +// ALU_FINISH: Appended to all ALU instructions. Usually empty, but if +// ALU_INIT started a block ALU_FINISH can be used to end it +// (as with the asm(...) statement in the x86 core). +// SETCOND_NONE: Used in multiply instructions in place of SETCOND_MUL +// when the condition codes are not set. Usually empty. +// SETCOND_MUL: Used in multiply instructions to set the condition codes. +// ROR_IMM_MSR: Used to rotate the immediate operand for MSR. +// ROR_OFFSET: Used to rotate the `offset' parameter for LDR and STR +// instructions. +// RRX_OFFSET: Used to rotate (RRX) the `offset' parameter for LDR and +// STR instructions. + +// C core + +#define C_SETCOND_LOGICAL \ + gba->N_FLAG = ((s32)res < 0) ? true : false; \ + gba->Z_FLAG = (res == 0) ? true : false; \ + gba->C_FLAG = C_OUT; +#define C_SETCOND_ADD \ + gba->N_FLAG = ((s32)res < 0) ? true : false; \ + gba->Z_FLAG = (res == 0) ? true : false; \ + gba->V_FLAG = ((NEG(lhs) & NEG(rhs) & POS(res)) | \ + (POS(lhs) & POS(rhs) & NEG(res))) ? true : false;\ + gba->C_FLAG = ((NEG(lhs) & NEG(rhs)) | \ + (NEG(lhs) & POS(res)) | \ + (NEG(rhs) & POS(res))) ? true : false; +#define C_SETCOND_SUB \ + gba->N_FLAG = ((s32)res < 0) ? true : false; \ + gba->Z_FLAG = (res == 0) ? true : false; \ + gba->V_FLAG = ((NEG(lhs) & POS(rhs) & POS(res)) | \ + (POS(lhs) & NEG(rhs) & NEG(res))) ? true : false;\ + gba->C_FLAG = ((NEG(lhs) & POS(rhs)) | \ + (NEG(lhs) & POS(res)) | \ + (POS(rhs) & POS(res))) ? true : false; + +#ifndef ALU_INIT_C + #define ALU_INIT_C \ + int dest = (opcode>>12) & 15; \ + bool C_OUT = gba->C_FLAG; \ + u32 value; +#endif +// OP Rd,Rb,Rm LSL # +#ifndef VALUE_LSL_IMM_C + #define VALUE_LSL_IMM_C \ + unsigned int shift = (opcode >> 7) & 0x1F; \ + if (LIKELY(!shift)) { /* LSL #0 most common? */ \ + value = gba->reg[opcode & 0x0F].I; \ + } else { \ + u32 v = gba->reg[opcode & 0x0F].I; \ + C_OUT = (v >> (32 - shift)) & 1 ? true : false; \ + value = v << shift; \ + } +#endif +// OP Rd,Rb,Rm LSL Rs +#ifndef VALUE_LSL_REG_C + #define VALUE_LSL_REG_C \ + unsigned int shift = gba->reg[(opcode >> 8)&15].B.B0; \ + unsigned int rm = gba->reg[opcode & 0x0F].I; \ + if(opcode & 0x0F == 15) { \ + rm += 4; \ + } \ + if (LIKELY(shift)) { \ + if (shift == 32) { \ + value = 0; \ + C_OUT = (rm & 1 ? true : false); \ + } else if (LIKELY(shift < 32)) { \ + C_OUT = (rm >> (32 - shift)) & 1 ? true : false;\ + value = rm << shift; \ + } else { \ + value = 0; \ + C_OUT = false; \ + } \ + } else { \ + value = rm; \ + } +#endif +// OP Rd,Rb,Rm LSR # +#ifndef VALUE_LSR_IMM_C + #define VALUE_LSR_IMM_C \ + unsigned int shift = (opcode >> 7) & 0x1F; \ + if (LIKELY(shift)) { \ + u32 v = gba->reg[opcode & 0x0F].I; \ + C_OUT = (v >> (shift - 1)) & 1 ? true : false; \ + value = v >> shift; \ + } else { \ + value = 0; \ + C_OUT = (gba->reg[opcode & 0x0F].I & 0x80000000) ? true : false;\ + } +#endif +// OP Rd,Rb,Rm LSR Rs +#ifndef VALUE_LSR_REG_C + #define VALUE_LSR_REG_C \ + unsigned int shift = gba->reg[(opcode >> 8)&15].B.B0; \ + unsigned int rm = gba->reg[opcode & 0x0F].I; \ + if(opcode & 0x0F == 15) { \ + rm += 4; \ + } \ + if (LIKELY(shift)) { \ + if (shift == 32) { \ + value = 0; \ + C_OUT = (rm & 0x80000000 ? true : false); \ + } else if (LIKELY(shift < 32)) { \ + C_OUT = (rm >> (shift - 1)) & 1 ? true : false;\ + value = rm >> shift; \ + } else { \ + value = 0; \ + C_OUT = false; \ + } \ + } else { \ + value = rm; \ + } +#endif +// OP Rd,Rb,Rm ASR # +#ifndef VALUE_ASR_IMM_C + #define VALUE_ASR_IMM_C \ + unsigned int shift = (opcode >> 7) & 0x1F; \ + if (LIKELY(shift)) { \ + /* VC++ BUG: u32 v; (s32)v>>n is optimized to shr! */ \ + s32 v = gba->reg[opcode & 0x0F].I; \ + C_OUT = (v >> (int)(shift - 1)) & 1 ? true : false;\ + value = v >> (int)shift; \ + } else { \ + if (gba->reg[opcode & 0x0F].I & 0x80000000) { \ + value = 0xFFFFFFFF; \ + C_OUT = true; \ + } else { \ + value = 0; \ + C_OUT = false; \ + } \ + } +#endif +// OP Rd,Rb,Rm ASR Rs +#ifndef VALUE_ASR_REG_C + #define VALUE_ASR_REG_C \ + unsigned int shift = gba->reg[(opcode >> 8)&15].B.B0; \ + s32 rm = gba->reg[opcode & 0x0F].I; \ + if(opcode & 0x0F == 15) { \ + rm += 4; \ + } \ + if (LIKELY(shift < 32)) { \ + if (LIKELY(shift)) { \ + C_OUT = (rm >> (int)(shift - 1)) & 1 ? true : false;\ + value = rm >> (int)shift; \ + } else { \ + value = rm; \ + } \ + } else { \ + if (rm & 0x80000000) { \ + value = 0xFFFFFFFF; \ + C_OUT = true; \ + } else { \ + value = 0; \ + C_OUT = false; \ + } \ + } +#endif +// OP Rd,Rb,Rm ROR # +#ifndef VALUE_ROR_IMM_C + #define VALUE_ROR_IMM_C \ + unsigned int shift = (opcode >> 7) & 0x1F; \ + if (LIKELY(shift)) { \ + u32 v = gba->reg[opcode & 0x0F].I; \ + C_OUT = (v >> (shift - 1)) & 1 ? true : false; \ + value = ((v << (32 - shift)) | \ + (v >> shift)); \ + } else { \ + u32 v = gba->reg[opcode & 0x0F].I; \ + C_OUT = (v & 1) ? true : false; \ + value = ((v >> 1) | \ + (gba->C_FLAG << 31)); \ + } +#endif +// OP Rd,Rb,Rm ROR Rs +#ifndef VALUE_ROR_REG_C + #define VALUE_ROR_REG_C \ + unsigned int shift = gba->reg[(opcode >> 8)&15].B.B0; \ + unsigned int rm = gba->reg[opcode & 0x0F].I; \ + if(opcode & 0x0F == 15) { \ + rm += 4; \ + } \ + if (LIKELY(shift & 0x1F)) { \ + C_OUT = (rm >> (shift - 1)) & 1 ? true : false; \ + value = ((rm << (32 - shift)) | \ + (rm >> shift)); \ + } else { \ + value = rm; \ + if (shift) \ + C_OUT = (value & 0x80000000 ? true : false);\ + } +#endif +// OP Rd,Rb,# ROR # +#ifndef VALUE_IMM_C + #define VALUE_IMM_C \ + int shift = (opcode & 0xF00) >> 7; \ + if (UNLIKELY(shift)) { \ + u32 v = opcode & 0xFF; \ + C_OUT = (v >> (shift - 1)) & 1 ? true : false; \ + value = ((v << (32 - shift)) | \ + (v >> shift)); \ + } else { \ + value = opcode & 0xFF; \ + } +#endif + +// Make the non-carry versions default to the carry versions +// (this is fine for C--the compiler will optimize the dead code out) +#ifndef ALU_INIT_NC + #define ALU_INIT_NC ALU_INIT_C +#endif +#ifndef VALUE_LSL_IMM_NC + #define VALUE_LSL_IMM_NC VALUE_LSL_IMM_C +#endif +#ifndef VALUE_LSL_REG_NC + #define VALUE_LSL_REG_NC VALUE_LSL_REG_C +#endif +#ifndef VALUE_LSR_IMM_NC + #define VALUE_LSR_IMM_NC VALUE_LSR_IMM_C +#endif +#ifndef VALUE_LSR_REG_NC + #define VALUE_LSR_REG_NC VALUE_LSR_REG_C +#endif +#ifndef VALUE_ASR_IMM_NC + #define VALUE_ASR_IMM_NC VALUE_ASR_IMM_C +#endif +#ifndef VALUE_ASR_REG_NC + #define VALUE_ASR_REG_NC VALUE_ASR_REG_C +#endif +#ifndef VALUE_ROR_IMM_NC + #define VALUE_ROR_IMM_NC VALUE_ROR_IMM_C +#endif +#ifndef VALUE_ROR_REG_NC + #define VALUE_ROR_REG_NC VALUE_ROR_REG_C +#endif +#ifndef VALUE_IMM_NC + #define VALUE_IMM_NC VALUE_IMM_C +#endif + +#define C_CHECK_PC(SETCOND) if (LIKELY(dest != 15)) { SETCOND } +#ifndef OP_AND + #define OP_AND \ + u32 res = gba->reg[(opcode>>16)&15].I & value; \ + gba->reg[dest].I = res; +#endif +#ifndef OP_ANDS + #define OP_ANDS OP_AND C_CHECK_PC(C_SETCOND_LOGICAL) +#endif +#ifndef OP_EOR + #define OP_EOR \ + u32 res = gba->reg[(opcode>>16)&15].I ^ value; \ + gba->reg[dest].I = res; +#endif +#ifndef OP_EORS + #define OP_EORS OP_EOR C_CHECK_PC(C_SETCOND_LOGICAL) +#endif +#ifndef OP_SUB + #define OP_SUB \ + u32 lhs = gba->reg[(opcode>>16)&15].I; \ + u32 rhs = value; \ + u32 res = lhs - rhs; \ + gba->reg[dest].I = res; +#endif +#ifndef OP_SUBS + #define OP_SUBS OP_SUB C_CHECK_PC(C_SETCOND_SUB) +#endif +#ifndef OP_RSB + #define OP_RSB \ + u32 lhs = gba->reg[(opcode>>16)&15].I; \ + u32 rhs = value; \ + u32 res = rhs - lhs; \ + gba->reg[dest].I = res; +#endif +#ifndef OP_RSBS + #define OP_RSBS OP_RSB C_CHECK_PC(C_SETCOND_SUB) +#endif +#ifndef OP_ADD + #define OP_ADD \ + u32 lhs = gba->reg[(opcode>>16)&15].I; \ + u32 rhs = value; \ + u32 res = lhs + rhs; \ + gba->reg[dest].I = res; +#endif +#ifndef OP_ADDS + #define OP_ADDS OP_ADD C_CHECK_PC(C_SETCOND_ADD) +#endif +#ifndef OP_ADC + #define OP_ADC \ + u32 lhs = gba->reg[(opcode>>16)&15].I; \ + u32 rhs = value; \ + u32 res = lhs + rhs + (u32)gba->C_FLAG; \ + gba->reg[dest].I = res; +#endif +#ifndef OP_ADCS + #define OP_ADCS OP_ADC C_CHECK_PC(C_SETCOND_ADD) +#endif +#ifndef OP_SBC + #define OP_SBC \ + u32 lhs = gba->reg[(opcode>>16)&15].I; \ + u32 rhs = value; \ + u32 res = lhs - rhs - !((u32)gba->C_FLAG); \ + gba->reg[dest].I = res; +#endif +#ifndef OP_SBCS + #define OP_SBCS OP_SBC C_CHECK_PC(C_SETCOND_SUB) +#endif +#ifndef OP_RSC + #define OP_RSC \ + u32 lhs = gba->reg[(opcode>>16)&15].I; \ + u32 rhs = value; \ + u32 res = rhs - lhs - !((u32)gba->C_FLAG); \ + gba->reg[dest].I = res; +#endif +#ifndef OP_RSCS + #define OP_RSCS OP_RSC C_CHECK_PC(C_SETCOND_SUB) +#endif +#ifndef OP_TST + #define OP_TST \ + u32 res = gba->reg[(opcode >> 16) & 0x0F].I & value; \ + C_SETCOND_LOGICAL; +#endif +#ifndef OP_TEQ + #define OP_TEQ \ + u32 res = gba->reg[(opcode >> 16) & 0x0F].I ^ value; \ + C_SETCOND_LOGICAL; +#endif +#ifndef OP_CMP + #define OP_CMP \ + u32 lhs = gba->reg[(opcode>>16)&15].I; \ + u32 rhs = value; \ + u32 res = lhs - rhs; \ + C_SETCOND_SUB; +#endif +#ifndef OP_CMN + #define OP_CMN \ + u32 lhs = gba->reg[(opcode>>16)&15].I; \ + u32 rhs = value; \ + u32 res = lhs + rhs; \ + C_SETCOND_ADD; +#endif +#ifndef OP_ORR + #define OP_ORR \ + u32 res = gba->reg[(opcode >> 16) & 0x0F].I | value; \ + gba->reg[dest].I = res; +#endif +#ifndef OP_ORRS + #define OP_ORRS OP_ORR C_CHECK_PC(C_SETCOND_LOGICAL) +#endif +#ifndef OP_MOV + #define OP_MOV \ + u32 res = value; \ + gba->reg[dest].I = res; +#endif +#ifndef OP_MOVS + #define OP_MOVS OP_MOV C_CHECK_PC(C_SETCOND_LOGICAL) +#endif +#ifndef OP_BIC + #define OP_BIC \ + u32 res = gba->reg[(opcode >> 16) & 0x0F].I & (~value); \ + gba->reg[dest].I = res; +#endif +#ifndef OP_BICS + #define OP_BICS OP_BIC C_CHECK_PC(C_SETCOND_LOGICAL) +#endif +#ifndef OP_MVN + #define OP_MVN \ + u32 res = ~value; \ + gba->reg[dest].I = res; +#endif +#ifndef OP_MVNS + #define OP_MVNS OP_MVN C_CHECK_PC(C_SETCOND_LOGICAL) +#endif + +#ifndef SETCOND_NONE + #define SETCOND_NONE /*nothing*/ +#endif +#ifndef SETCOND_MUL + #define SETCOND_MUL \ + gba->N_FLAG = ((s32)gba->reg[dest].I < 0) ? true : false; \ + gba->Z_FLAG = gba->reg[dest].I ? false : true; +#endif +#ifndef SETCOND_MULL + #define SETCOND_MULL \ + gba->N_FLAG = (gba->reg[dest].I & 0x80000000) ? true : false;\ + gba->Z_FLAG = gba->reg[dest].I || gba->reg[acc].I ? false : true; +#endif + +#ifndef ALU_FINISH + #define ALU_FINISH /*nothing*/ +#endif + +#ifndef ROR_IMM_MSR + #define ROR_IMM_MSR \ + u32 v = opcode & 0xff; \ + value = ((v << (32 - shift)) | (v >> shift)); +#endif +#ifndef ROR_OFFSET + #define ROR_OFFSET \ + offset = ((offset << (32 - shift)) | (offset >> shift)); +#endif +#ifndef RRX_OFFSET + #define RRX_OFFSET \ + offset = ((offset >> 1) | ((int)gba->C_FLAG << 31)); +#endif + +// ALU ops (except multiply) ////////////////////////////////////////////// + +// ALU_INIT: init code (ALU_INIT_C or ALU_INIT_NC) +// GETVALUE: load value and shift/rotate (VALUE_XXX) +// OP: ALU operation (OP_XXX) +// MODECHANGE: MODECHANGE_NO or MODECHANGE_YES +// ISREGSHIFT: 1 for insns of the form ...,Rn LSL/etc Rs; 0 otherwise +// ALU_INIT, GETVALUE, OP, and ALU_FINISH are concatenated in order. +#define ALU_INSN(ALU_INIT, GETVALUE, OP, MODECHANGE, ISREGSHIFT) \ + ALU_INIT GETVALUE OP ALU_FINISH; \ + if (LIKELY((opcode & 0x0000F000) != 0x0000F000)) { \ + gba->clockTicks = 1 + ISREGSHIFT \ + + codeTicksAccessSeq32(gba, gba->armNextPC); \ + } else { \ + MODECHANGE; \ + if (gba->armState) { \ + gba->reg[15].I &= 0xFFFFFFFC; \ + gba->armNextPC = gba->reg[15].I; \ + gba->reg[15].I += 4; \ + ARM_PREFETCH; \ + } else { \ + gba->reg[15].I &= 0xFFFFFFFE; \ + gba->armNextPC = gba->reg[15].I; \ + gba->reg[15].I += 2; \ + THUMB_PREFETCH; \ + } \ + gba->clockTicks = 3 + ISREGSHIFT \ + + codeTicksAccess32(gba, gba->armNextPC) \ + + codeTicksAccessSeq32(gba, gba->armNextPC) \ + + codeTicksAccessSeq32(gba, gba->armNextPC); \ + } + +#define MODECHANGE_NO /*nothing*/ +#define MODECHANGE_YES CPUSwitchMode(gba, gba->reg[17].I & 0x1f, false); + +#define DEFINE_ALU_INSN_C(CODE1, CODE2, OP, MODECHANGE) \ + static INSN_REGPARM void arm##CODE1##0(GBASystem *gba, u32 opcode) { ALU_INSN(ALU_INIT_C, VALUE_LSL_IMM_C, OP_##OP, MODECHANGE_##MODECHANGE, 0); }\ + static INSN_REGPARM void arm##CODE1##1(GBASystem *gba, u32 opcode) { ALU_INSN(ALU_INIT_C, VALUE_LSL_REG_C, OP_##OP, MODECHANGE_##MODECHANGE, 1); }\ + static INSN_REGPARM void arm##CODE1##2(GBASystem *gba, u32 opcode) { ALU_INSN(ALU_INIT_C, VALUE_LSR_IMM_C, OP_##OP, MODECHANGE_##MODECHANGE, 0); }\ + static INSN_REGPARM void arm##CODE1##3(GBASystem *gba, u32 opcode) { ALU_INSN(ALU_INIT_C, VALUE_LSR_REG_C, OP_##OP, MODECHANGE_##MODECHANGE, 1); }\ + static INSN_REGPARM void arm##CODE1##4(GBASystem *gba, u32 opcode) { ALU_INSN(ALU_INIT_C, VALUE_ASR_IMM_C, OP_##OP, MODECHANGE_##MODECHANGE, 0); }\ + static INSN_REGPARM void arm##CODE1##5(GBASystem *gba, u32 opcode) { ALU_INSN(ALU_INIT_C, VALUE_ASR_REG_C, OP_##OP, MODECHANGE_##MODECHANGE, 1); }\ + static INSN_REGPARM void arm##CODE1##6(GBASystem *gba, u32 opcode) { ALU_INSN(ALU_INIT_C, VALUE_ROR_IMM_C, OP_##OP, MODECHANGE_##MODECHANGE, 0); }\ + static INSN_REGPARM void arm##CODE1##7(GBASystem *gba, u32 opcode) { ALU_INSN(ALU_INIT_C, VALUE_ROR_REG_C, OP_##OP, MODECHANGE_##MODECHANGE, 1); }\ + static INSN_REGPARM void arm##CODE2##0(GBASystem *gba, u32 opcode) { ALU_INSN(ALU_INIT_C, VALUE_IMM_C, OP_##OP, MODECHANGE_##MODECHANGE, 0); } +#define DEFINE_ALU_INSN_NC(CODE1, CODE2, OP, MODECHANGE) \ + static INSN_REGPARM void arm##CODE1##0(GBASystem *gba, u32 opcode) { ALU_INSN(ALU_INIT_NC, VALUE_LSL_IMM_NC, OP_##OP, MODECHANGE_##MODECHANGE, 0); }\ + static INSN_REGPARM void arm##CODE1##1(GBASystem *gba, u32 opcode) { ALU_INSN(ALU_INIT_NC, VALUE_LSL_REG_NC, OP_##OP, MODECHANGE_##MODECHANGE, 1); }\ + static INSN_REGPARM void arm##CODE1##2(GBASystem *gba, u32 opcode) { ALU_INSN(ALU_INIT_NC, VALUE_LSR_IMM_NC, OP_##OP, MODECHANGE_##MODECHANGE, 0); }\ + static INSN_REGPARM void arm##CODE1##3(GBASystem *gba, u32 opcode) { ALU_INSN(ALU_INIT_NC, VALUE_LSR_REG_NC, OP_##OP, MODECHANGE_##MODECHANGE, 1); }\ + static INSN_REGPARM void arm##CODE1##4(GBASystem *gba, u32 opcode) { ALU_INSN(ALU_INIT_NC, VALUE_ASR_IMM_NC, OP_##OP, MODECHANGE_##MODECHANGE, 0); }\ + static INSN_REGPARM void arm##CODE1##5(GBASystem *gba, u32 opcode) { ALU_INSN(ALU_INIT_NC, VALUE_ASR_REG_NC, OP_##OP, MODECHANGE_##MODECHANGE, 1); }\ + static INSN_REGPARM void arm##CODE1##6(GBASystem *gba, u32 opcode) { ALU_INSN(ALU_INIT_NC, VALUE_ROR_IMM_NC, OP_##OP, MODECHANGE_##MODECHANGE, 0); }\ + static INSN_REGPARM void arm##CODE1##7(GBASystem *gba, u32 opcode) { ALU_INSN(ALU_INIT_NC, VALUE_ROR_REG_NC, OP_##OP, MODECHANGE_##MODECHANGE, 1); }\ + static INSN_REGPARM void arm##CODE2##0(GBASystem *gba, u32 opcode) { ALU_INSN(ALU_INIT_NC, VALUE_IMM_NC, OP_##OP, MODECHANGE_##MODECHANGE, 0); } + +// AND +DEFINE_ALU_INSN_NC(00, 20, AND, NO) +// ANDS +DEFINE_ALU_INSN_C (01, 21, ANDS, YES) + +// EOR +DEFINE_ALU_INSN_NC(02, 22, EOR, NO) +// EORS +DEFINE_ALU_INSN_C (03, 23, EORS, YES) + +// SUB +DEFINE_ALU_INSN_NC(04, 24, SUB, NO) +// SUBS +DEFINE_ALU_INSN_NC(05, 25, SUBS, YES) + +// RSB +DEFINE_ALU_INSN_NC(06, 26, RSB, NO) +// RSBS +DEFINE_ALU_INSN_NC(07, 27, RSBS, YES) + +// ADD +DEFINE_ALU_INSN_NC(08, 28, ADD, NO) +// ADDS +DEFINE_ALU_INSN_NC(09, 29, ADDS, YES) + +// ADC +DEFINE_ALU_INSN_NC(0A, 2A, ADC, NO) +// ADCS +DEFINE_ALU_INSN_NC(0B, 2B, ADCS, YES) + +// SBC +DEFINE_ALU_INSN_NC(0C, 2C, SBC, NO) +// SBCS +DEFINE_ALU_INSN_NC(0D, 2D, SBCS, YES) + +// RSC +DEFINE_ALU_INSN_NC(0E, 2E, RSC, NO) +// RSCS +DEFINE_ALU_INSN_NC(0F, 2F, RSCS, YES) + +// TST +DEFINE_ALU_INSN_C (11, 31, TST, NO) + +// TEQ +DEFINE_ALU_INSN_C (13, 33, TEQ, NO) + +// CMP +DEFINE_ALU_INSN_NC(15, 35, CMP, NO) + +// CMN +DEFINE_ALU_INSN_NC(17, 37, CMN, NO) + +// ORR +DEFINE_ALU_INSN_NC(18, 38, ORR, NO) +// ORRS +DEFINE_ALU_INSN_C (19, 39, ORRS, YES) + +// MOV +DEFINE_ALU_INSN_NC(1A, 3A, MOV, NO) +// MOVS +DEFINE_ALU_INSN_C (1B, 3B, MOVS, YES) + +// BIC +DEFINE_ALU_INSN_NC(1C, 3C, BIC, NO) +// BICS +DEFINE_ALU_INSN_C (1D, 3D, BICS, YES) + +// MVN +DEFINE_ALU_INSN_NC(1E, 3E, MVN, NO) +// MVNS +DEFINE_ALU_INSN_C (1F, 3F, MVNS, YES) + +// Multiply instructions ////////////////////////////////////////////////// + +// OP: OP_MUL, OP_MLA etc. +// SETCOND: SETCOND_NONE, SETCOND_MUL, or SETCOND_MULL +// CYCLES: base cycle count (1, 2, or 3) +#define MUL_INSN(OP, SETCOND, CYCLES) \ + int mult = (opcode & 0x0F); \ + u32 rs = gba->reg[(opcode >> 8) & 0x0F].I; \ + int acc = (opcode >> 12) & 0x0F; /* or destLo */ \ + int dest = (opcode >> 16) & 0x0F; /* or destHi */ \ + OP; \ + SETCOND; \ + if ((s32)rs < 0) \ + rs = ~rs; \ + if ((rs & 0xFFFFFF00) == 0) \ + gba->clockTicks += 0; \ + else if ((rs & 0xFFFF0000) == 0) \ + gba->clockTicks += 1; \ + else if ((rs & 0xFF000000) == 0) \ + gba->clockTicks += 2; \ + else \ + gba->clockTicks += 3; \ + if (gba->busPrefetchCount == 0) \ + gba->busPrefetchCount = ((gba->busPrefetchCount+1)<clockTicks) - 1; \ + gba->clockTicks += 1 + codeTicksAccess32(gba, gba->armNextPC); + +#define OP_MUL \ + gba->reg[dest].I = gba->reg[mult].I * rs; +#define OP_MLA \ + gba->reg[dest].I = gba->reg[mult].I * rs + gba->reg[acc].I; +#define OP_MULL(SIGN) \ + SIGN##64 res = (SIGN##64)(SIGN##32)gba->reg[mult].I \ + * (SIGN##64)(SIGN##32)rs; \ + gba->reg[acc].I = (u32)res; \ + gba->reg[dest].I = (u32)(res >> 32); +#define OP_MLAL(SIGN) \ + SIGN##64 res = ((SIGN##64)gba->reg[dest].I<<32 | gba->reg[acc].I)\ + + ((SIGN##64)(SIGN##32)gba->reg[mult].I \ + * (SIGN##64)(SIGN##32)rs); \ + gba->reg[acc].I = (u32)res; \ + gba->reg[dest].I = (u32)(res >> 32); +#define OP_UMULL OP_MULL(u) +#define OP_UMLAL OP_MLAL(u) +#define OP_SMULL OP_MULL(s) +#define OP_SMLAL OP_MLAL(s) + +// MUL Rd, Rm, Rs +static INSN_REGPARM void arm009(GBASystem *gba, u32 opcode) { MUL_INSN(OP_MUL, SETCOND_NONE, 1); } +// MULS Rd, Rm, Rs +static INSN_REGPARM void arm019(GBASystem *gba, u32 opcode) { MUL_INSN(OP_MUL, SETCOND_MUL, 1); } + +// MLA Rd, Rm, Rs, Rn +static INSN_REGPARM void arm029(GBASystem *gba, u32 opcode) { MUL_INSN(OP_MLA, SETCOND_NONE, 2); } +// MLAS Rd, Rm, Rs, Rn +static INSN_REGPARM void arm039(GBASystem *gba, u32 opcode) { MUL_INSN(OP_MLA, SETCOND_MUL, 2); } + +// UMULL RdLo, RdHi, Rn, Rs +static INSN_REGPARM void arm089(GBASystem *gba, u32 opcode) { MUL_INSN(OP_UMULL, SETCOND_NONE, 2); } +// UMULLS RdLo, RdHi, Rn, Rs +static INSN_REGPARM void arm099(GBASystem *gba, u32 opcode) { MUL_INSN(OP_UMULL, SETCOND_MULL, 2); } + +// UMLAL RdLo, RdHi, Rn, Rs +static INSN_REGPARM void arm0A9(GBASystem *gba, u32 opcode) { MUL_INSN(OP_UMLAL, SETCOND_NONE, 3); } +// UMLALS RdLo, RdHi, Rn, Rs +static INSN_REGPARM void arm0B9(GBASystem *gba, u32 opcode) { MUL_INSN(OP_UMLAL, SETCOND_MULL, 3); } + +// SMULL RdLo, RdHi, Rm, Rs +static INSN_REGPARM void arm0C9(GBASystem *gba, u32 opcode) { MUL_INSN(OP_SMULL, SETCOND_NONE, 2); } +// SMULLS RdLo, RdHi, Rm, Rs +static INSN_REGPARM void arm0D9(GBASystem *gba, u32 opcode) { MUL_INSN(OP_SMULL, SETCOND_MULL, 2); } + +// SMLAL RdLo, RdHi, Rm, Rs +static INSN_REGPARM void arm0E9(GBASystem *gba, u32 opcode) { MUL_INSN(OP_SMLAL, SETCOND_NONE, 3); } +// SMLALS RdLo, RdHi, Rm, Rs +static INSN_REGPARM void arm0F9(GBASystem *gba, u32 opcode) { MUL_INSN(OP_SMLAL, SETCOND_MULL, 3); } + +// Misc instructions ////////////////////////////////////////////////////// + +// SWP Rd, Rm, [Rn] +static INSN_REGPARM void arm109(GBASystem *gba, u32 opcode) +{ + u32 address = gba->reg[(opcode >> 16) & 15].I; + u32 temp = CPUReadMemory(gba, address); + CPUWriteMemory(gba, address, gba->reg[opcode&15].I); + gba->reg[(opcode >> 12) & 15].I = temp; + gba->clockTicks = 4 + dataTicksAccess32(gba, address) + dataTicksAccess32(gba, address) + + codeTicksAccess32(gba, gba->armNextPC); +} + +// SWPB Rd, Rm, [Rn] +static INSN_REGPARM void arm149(GBASystem *gba, u32 opcode) +{ + u32 address = gba->reg[(opcode >> 16) & 15].I; + u32 temp = CPUReadByte(gba, address); + CPUWriteByte(gba, address, gba->reg[opcode&15].B.B0); + gba->reg[(opcode>>12)&15].I = temp; + gba->clockTicks = 4 + dataTicksAccess32(gba, address) + dataTicksAccess32(gba, address) + + codeTicksAccess32(gba, gba->armNextPC); +} + +// MRS Rd, CPSR +static INSN_REGPARM void arm100(GBASystem *gba, u32 opcode) +{ + if (LIKELY((opcode & 0x0FFF0FFF) == 0x010F0000)) { + CPUUpdateCPSR(gba); + gba->reg[(opcode >> 12) & 0x0F].I = gba->reg[16].I; + } else { + armUnknownInsn(gba, opcode); + } +} + +// MRS Rd, SPSR +static INSN_REGPARM void arm140(GBASystem *gba, u32 opcode) +{ + if (LIKELY((opcode & 0x0FFF0FFF) == 0x014F0000)) { + gba->reg[(opcode >> 12) & 0x0F].I = gba->reg[17].I; + } else { + armUnknownInsn(gba, opcode); + } +} + +// MSR CPSR_fields, Rm +static INSN_REGPARM void arm120(GBASystem *gba, u32 opcode) +{ + if (LIKELY((opcode & 0x0FF0FFF0) == 0x0120F000)) { + CPUUpdateCPSR(gba); + u32 value = gba->reg[opcode & 15].I; + u32 newValue = gba->reg[16].I; + if (gba->armMode > 0x10) { + if (opcode & 0x00010000) + newValue = (newValue & 0xFFFFFF00) | (value & 0x000000FF); + if (opcode & 0x00020000) + newValue = (newValue & 0xFFFF00FF) | (value & 0x0000FF00); + if (opcode & 0x00040000) + newValue = (newValue & 0xFF00FFFF) | (value & 0x00FF0000); + } + if (opcode & 0x00080000) + newValue = (newValue & 0x00FFFFFF) | (value & 0xFF000000); + newValue |= 0x10; + CPUSwitchMode(gba, newValue & 0x1F, false); + gba->reg[16].I = newValue; + CPUUpdateFlags(gba); + if (!gba->armState) { // this should not be allowed, but it seems to work + THUMB_PREFETCH; + gba->reg[15].I = gba->armNextPC + 2; + } + } else { + armUnknownInsn(gba, opcode); + } +} + +// MSR SPSR_fields, Rm +static INSN_REGPARM void arm160(GBASystem *gba, u32 opcode) +{ + if (LIKELY((opcode & 0x0FF0FFF0) == 0x0160F000)) { + u32 value = gba->reg[opcode & 15].I; + if (gba->armMode > 0x10 && gba->armMode < 0x1F) { + if (opcode & 0x00010000) + gba->reg[17].I = (gba->reg[17].I & 0xFFFFFF00) | (value & 0x000000FF); + if (opcode & 0x00020000) + gba->reg[17].I = (gba->reg[17].I & 0xFFFF00FF) | (value & 0x0000FF00); + if (opcode & 0x00040000) + gba->reg[17].I = (gba->reg[17].I & 0xFF00FFFF) | (value & 0x00FF0000); + if (opcode & 0x00080000) + gba->reg[17].I = (gba->reg[17].I & 0x00FFFFFF) | (value & 0xFF000000); + } + } else { + armUnknownInsn(gba, opcode); + } +} + +// MSR CPSR_fields, # +static INSN_REGPARM void arm320(GBASystem *gba, u32 opcode) +{ + if (LIKELY((opcode & 0x0FF0F000) == 0x0320F000)) { + CPUUpdateCPSR(gba); + u32 value = opcode & 0xFF; + int shift = (opcode & 0xF00) >> 7; + if (shift) { + ROR_IMM_MSR; + } + u32 newValue = gba->reg[16].I; + if (gba->armMode > 0x10) { + if (opcode & 0x00010000) + newValue = (newValue & 0xFFFFFF00) | (value & 0x000000FF); + if (opcode & 0x00020000) + newValue = (newValue & 0xFFFF00FF) | (value & 0x0000FF00); + if (opcode & 0x00040000) + newValue = (newValue & 0xFF00FFFF) | (value & 0x00FF0000); + } + if (opcode & 0x00080000) + newValue = (newValue & 0x00FFFFFF) | (value & 0xFF000000); + + newValue |= 0x10; + + CPUSwitchMode(gba, newValue & 0x1F, false); + gba->reg[16].I = newValue; + CPUUpdateFlags(gba); + if (!gba->armState) { // this should not be allowed, but it seems to work + THUMB_PREFETCH; + gba->reg[15].I = gba->armNextPC + 2; + } + } else { + armUnknownInsn(gba, opcode); + } +} + +// MSR SPSR_fields, # +static INSN_REGPARM void arm360(GBASystem *gba, u32 opcode) +{ + if (LIKELY((opcode & 0x0FF0F000) == 0x0360F000)) { + if (gba->armMode > 0x10 && gba->armMode < 0x1F) { + u32 value = opcode & 0xFF; + int shift = (opcode & 0xF00) >> 7; + if (shift) { + ROR_IMM_MSR; + } + if (opcode & 0x00010000) + gba->reg[17].I = (gba->reg[17].I & 0xFFFFFF00) | (value & 0x000000FF); + if (opcode & 0x00020000) + gba->reg[17].I = (gba->reg[17].I & 0xFFFF00FF) | (value & 0x0000FF00); + if (opcode & 0x00040000) + gba->reg[17].I = (gba->reg[17].I & 0xFF00FFFF) | (value & 0x00FF0000); + if (opcode & 0x00080000) + gba->reg[17].I = (gba->reg[17].I & 0x00FFFFFF) | (value & 0xFF000000); + } + } else { + armUnknownInsn(gba, opcode); + } +} + +// BX Rm +static INSN_REGPARM void arm121(GBASystem *gba, u32 opcode) +{ + if (LIKELY((opcode & 0x0FFFFFF0) == 0x012FFF10)) { + int base = opcode & 0x0F; + gba->busPrefetchCount = 0; + gba->armState = gba->reg[base].I & 1 ? false : true; + if (gba->armState) { + gba->reg[15].I = gba->reg[base].I & 0xFFFFFFFC; + gba->armNextPC = gba->reg[15].I; + gba->reg[15].I += 4; + ARM_PREFETCH; + gba->clockTicks = 3 + codeTicksAccessSeq32(gba, gba->armNextPC) + + codeTicksAccessSeq32(gba, gba->armNextPC) + + codeTicksAccess32(gba, gba->armNextPC); + } else { + gba->reg[15].I = gba->reg[base].I & 0xFFFFFFFE; + gba->armNextPC = gba->reg[15].I; + gba->reg[15].I += 2; + THUMB_PREFETCH; + gba->clockTicks = 3 + codeTicksAccessSeq16(gba, gba->armNextPC) + + codeTicksAccessSeq16(gba, gba->armNextPC) + + codeTicksAccess16(gba, gba->armNextPC); + } + } else { + armUnknownInsn(gba, opcode); + } +} + +// Load/store ///////////////////////////////////////////////////////////// + +#define OFFSET_IMM \ + int offset = opcode & 0xFFF; +#define OFFSET_IMM8 \ + int offset = ((opcode & 0x0F) | ((opcode>>4) & 0xF0)); +#define OFFSET_REG \ + int offset = gba->reg[opcode & 15].I; +#define OFFSET_LSL \ + int offset = gba->reg[opcode & 15].I << ((opcode>>7) & 31); +#define OFFSET_LSR \ + int shift = (opcode >> 7) & 31; \ + int offset = shift ? gba->reg[opcode & 15].I >> shift : 0; +#define OFFSET_ASR \ + int shift = (opcode >> 7) & 31; \ + int offset; \ + if (shift) \ + offset = (int)((s32)gba->reg[opcode & 15].I >> shift);\ + else if (gba->reg[opcode & 15].I & 0x80000000) \ + offset = 0xFFFFFFFF; \ + else \ + offset = 0; +#define OFFSET_ROR \ + int shift = (opcode >> 7) & 31; \ + u32 offset = gba->reg[opcode & 15].I; \ + if (shift) { \ + ROR_OFFSET; \ + } else { \ + RRX_OFFSET; \ + } + +#define ADDRESS_POST (gba->reg[base].I) +#define ADDRESS_PREDEC (gba->reg[base].I - offset) +#define ADDRESS_PREINC (gba->reg[base].I + offset) + +#define OP_STR CPUWriteMemory(gba, address, gba->reg[dest].I) +#define OP_STRH CPUWriteHalfWord(gba, address, gba->reg[dest].W.W0) +#define OP_STRB CPUWriteByte(gba, address, gba->reg[dest].B.B0) +#define OP_LDR gba->reg[dest].I = CPUReadMemory(gba, address) +#define OP_LDRH gba->reg[dest].I = CPUReadHalfWord(gba, address) +#define OP_LDRB gba->reg[dest].I = CPUReadByte(gba, address) +#define OP_LDRSH gba->reg[dest].I = (s16)CPUReadHalfWordSigned(gba, address) +#define OP_LDRSB gba->reg[dest].I = (s8)CPUReadByte(gba, address) + +#define WRITEBACK_NONE /*nothing*/ +#define WRITEBACK_PRE gba->reg[base].I = address +#define WRITEBACK_POSTDEC gba->reg[base].I = address - offset +#define WRITEBACK_POSTINC gba->reg[base].I = address + offset + +#define LDRSTR_INIT(CALC_OFFSET, CALC_ADDRESS) \ + if (gba->busPrefetchCount == 0) \ + gba->busPrefetch = gba->busPrefetchEnable; \ + int dest = (opcode >> 12) & 15; \ + int base = (opcode >> 16) & 15; \ + CALC_OFFSET; \ + u32 address = CALC_ADDRESS; + +#define STR(CALC_OFFSET, CALC_ADDRESS, STORE_DATA, WRITEBACK1, WRITEBACK2, SIZE) \ + LDRSTR_INIT(CALC_OFFSET, CALC_ADDRESS); \ + WRITEBACK1; \ + STORE_DATA; \ + WRITEBACK2; \ + gba->clockTicks = 2 + dataTicksAccess##SIZE(gba, address) \ + + codeTicksAccess32(gba, gba->armNextPC); +#define LDR(CALC_OFFSET, CALC_ADDRESS, LOAD_DATA, WRITEBACK, SIZE) \ + LDRSTR_INIT(CALC_OFFSET, CALC_ADDRESS); \ + LOAD_DATA; \ + if (dest != base) \ + { \ + WRITEBACK; \ + } \ + gba->clockTicks = 0; \ + if (dest == 15) { \ + gba->reg[15].I &= 0xFFFFFFFC; \ + gba->armNextPC = gba->reg[15].I; \ + gba->reg[15].I += 4; \ + ARM_PREFETCH; \ + gba->clockTicks += 2 + dataTicksAccessSeq32(gba, address) \ + + dataTicksAccessSeq32(gba, address);\ + } \ + gba->clockTicks += 3 + dataTicksAccess##SIZE(gba, address) \ + + codeTicksAccess32(gba, gba->armNextPC); +#define STR_POSTDEC(CALC_OFFSET, STORE_DATA, SIZE) \ + STR(CALC_OFFSET, ADDRESS_POST, STORE_DATA, WRITEBACK_NONE, WRITEBACK_POSTDEC, SIZE) +#define STR_POSTINC(CALC_OFFSET, STORE_DATA, SIZE) \ + STR(CALC_OFFSET, ADDRESS_POST, STORE_DATA, WRITEBACK_NONE, WRITEBACK_POSTINC, SIZE) +#define STR_PREDEC(CALC_OFFSET, STORE_DATA, SIZE) \ + STR(CALC_OFFSET, ADDRESS_PREDEC, STORE_DATA, WRITEBACK_NONE, WRITEBACK_NONE, SIZE) +#define STR_PREDEC_WB(CALC_OFFSET, STORE_DATA, SIZE) \ + STR(CALC_OFFSET, ADDRESS_PREDEC, STORE_DATA, WRITEBACK_PRE, WRITEBACK_NONE, SIZE) +#define STR_PREINC(CALC_OFFSET, STORE_DATA, SIZE) \ + STR(CALC_OFFSET, ADDRESS_PREINC, STORE_DATA, WRITEBACK_NONE, WRITEBACK_NONE, SIZE) +#define STR_PREINC_WB(CALC_OFFSET, STORE_DATA, SIZE) \ + STR(CALC_OFFSET, ADDRESS_PREINC, STORE_DATA, WRITEBACK_PRE, WRITEBACK_NONE, SIZE) +#define LDR_POSTDEC(CALC_OFFSET, LOAD_DATA, SIZE) \ + LDR(CALC_OFFSET, ADDRESS_POST, LOAD_DATA, WRITEBACK_POSTDEC, SIZE) +#define LDR_POSTINC(CALC_OFFSET, LOAD_DATA, SIZE) \ + LDR(CALC_OFFSET, ADDRESS_POST, LOAD_DATA, WRITEBACK_POSTINC, SIZE) +#define LDR_PREDEC(CALC_OFFSET, LOAD_DATA, SIZE) \ + LDR(CALC_OFFSET, ADDRESS_PREDEC, LOAD_DATA, WRITEBACK_NONE, SIZE) +#define LDR_PREDEC_WB(CALC_OFFSET, LOAD_DATA, SIZE) \ + LDR(CALC_OFFSET, ADDRESS_PREDEC, LOAD_DATA, WRITEBACK_PRE, SIZE) +#define LDR_PREINC(CALC_OFFSET, LOAD_DATA, SIZE) \ + LDR(CALC_OFFSET, ADDRESS_PREINC, LOAD_DATA, WRITEBACK_NONE, SIZE) +#define LDR_PREINC_WB(CALC_OFFSET, LOAD_DATA, SIZE) \ + LDR(CALC_OFFSET, ADDRESS_PREINC, LOAD_DATA, WRITEBACK_PRE, SIZE) + +// STRH Rd, [Rn], -Rm +static INSN_REGPARM void arm00B(GBASystem *gba, u32 opcode) { STR_POSTDEC(OFFSET_REG, OP_STRH, 16); } +// STRH Rd, [Rn], #-offset +static INSN_REGPARM void arm04B(GBASystem *gba, u32 opcode) { STR_POSTDEC(OFFSET_IMM8, OP_STRH, 16); } +// STRH Rd, [Rn], Rm +static INSN_REGPARM void arm08B(GBASystem *gba, u32 opcode) { STR_POSTINC(OFFSET_REG, OP_STRH, 16); } +// STRH Rd, [Rn], #offset +static INSN_REGPARM void arm0CB(GBASystem *gba, u32 opcode) { STR_POSTINC(OFFSET_IMM8, OP_STRH, 16); } +// STRH Rd, [Rn, -Rm] +static INSN_REGPARM void arm10B(GBASystem *gba, u32 opcode) { STR_PREDEC(OFFSET_REG, OP_STRH, 16); } +// STRH Rd, [Rn, -Rm]! +static INSN_REGPARM void arm12B(GBASystem *gba, u32 opcode) { STR_PREDEC_WB(OFFSET_REG, OP_STRH, 16); } +// STRH Rd, [Rn, -#offset] +static INSN_REGPARM void arm14B(GBASystem *gba, u32 opcode) { STR_PREDEC(OFFSET_IMM8, OP_STRH, 16); } +// STRH Rd, [Rn, -#offset]! +static INSN_REGPARM void arm16B(GBASystem *gba, u32 opcode) { STR_PREDEC_WB(OFFSET_IMM8, OP_STRH, 16); } +// STRH Rd, [Rn, Rm] +static INSN_REGPARM void arm18B(GBASystem *gba, u32 opcode) { STR_PREINC(OFFSET_REG, OP_STRH, 16); } +// STRH Rd, [Rn, Rm]! +static INSN_REGPARM void arm1AB(GBASystem *gba, u32 opcode) { STR_PREINC_WB(OFFSET_REG, OP_STRH, 16); } +// STRH Rd, [Rn, #offset] +static INSN_REGPARM void arm1CB(GBASystem *gba, u32 opcode) { STR_PREINC(OFFSET_IMM8, OP_STRH, 16); } +// STRH Rd, [Rn, #offset]! +static INSN_REGPARM void arm1EB(GBASystem *gba, u32 opcode) { STR_PREINC_WB(OFFSET_IMM8, OP_STRH, 16); } + +// LDRH Rd, [Rn], -Rm +static INSN_REGPARM void arm01B(GBASystem *gba, u32 opcode) { LDR_POSTDEC(OFFSET_REG, OP_LDRH, 16); } +// LDRH Rd, [Rn], #-offset +static INSN_REGPARM void arm05B(GBASystem *gba, u32 opcode) { LDR_POSTDEC(OFFSET_IMM8, OP_LDRH, 16); } +// LDRH Rd, [Rn], Rm +static INSN_REGPARM void arm09B(GBASystem *gba, u32 opcode) { LDR_POSTINC(OFFSET_REG, OP_LDRH, 16); } +// LDRH Rd, [Rn], #offset +static INSN_REGPARM void arm0DB(GBASystem *gba, u32 opcode) { LDR_POSTINC(OFFSET_IMM8, OP_LDRH, 16); } +// LDRH Rd, [Rn, -Rm] +static INSN_REGPARM void arm11B(GBASystem *gba, u32 opcode) { LDR_PREDEC(OFFSET_REG, OP_LDRH, 16); } +// LDRH Rd, [Rn, -Rm]! +static INSN_REGPARM void arm13B(GBASystem *gba, u32 opcode) { LDR_PREDEC_WB(OFFSET_REG, OP_LDRH, 16); } +// LDRH Rd, [Rn, -#offset] +static INSN_REGPARM void arm15B(GBASystem *gba, u32 opcode) { LDR_PREDEC(OFFSET_IMM8, OP_LDRH, 16); } +// LDRH Rd, [Rn, -#offset]! +static INSN_REGPARM void arm17B(GBASystem *gba, u32 opcode) { LDR_PREDEC_WB(OFFSET_IMM8, OP_LDRH, 16); } +// LDRH Rd, [Rn, Rm] +static INSN_REGPARM void arm19B(GBASystem *gba, u32 opcode) { LDR_PREINC(OFFSET_REG, OP_LDRH, 16); } +// LDRH Rd, [Rn, Rm]! +static INSN_REGPARM void arm1BB(GBASystem *gba, u32 opcode) { LDR_PREINC_WB(OFFSET_REG, OP_LDRH, 16); } +// LDRH Rd, [Rn, #offset] +static INSN_REGPARM void arm1DB(GBASystem *gba, u32 opcode) { LDR_PREINC(OFFSET_IMM8, OP_LDRH, 16); } +// LDRH Rd, [Rn, #offset]! +static INSN_REGPARM void arm1FB(GBASystem *gba, u32 opcode) { LDR_PREINC_WB(OFFSET_IMM8, OP_LDRH, 16); } + +// LDRSB Rd, [Rn], -Rm +static INSN_REGPARM void arm01D(GBASystem *gba, u32 opcode) { LDR_POSTDEC(OFFSET_REG, OP_LDRSB, 16); } +// LDRSB Rd, [Rn], #-offset +static INSN_REGPARM void arm05D(GBASystem *gba, u32 opcode) { LDR_POSTDEC(OFFSET_IMM8, OP_LDRSB, 16); } +// LDRSB Rd, [Rn], Rm +static INSN_REGPARM void arm09D(GBASystem *gba, u32 opcode) { LDR_POSTINC(OFFSET_REG, OP_LDRSB, 16); } +// LDRSB Rd, [Rn], #offset +static INSN_REGPARM void arm0DD(GBASystem *gba, u32 opcode) { LDR_POSTINC(OFFSET_IMM8, OP_LDRSB, 16); } +// LDRSB Rd, [Rn, -Rm] +static INSN_REGPARM void arm11D(GBASystem *gba, u32 opcode) { LDR_PREDEC(OFFSET_REG, OP_LDRSB, 16); } +// LDRSB Rd, [Rn, -Rm]! +static INSN_REGPARM void arm13D(GBASystem *gba, u32 opcode) { LDR_PREDEC_WB(OFFSET_REG, OP_LDRSB, 16); } +// LDRSB Rd, [Rn, -#offset] +static INSN_REGPARM void arm15D(GBASystem *gba, u32 opcode) { LDR_PREDEC(OFFSET_IMM8, OP_LDRSB, 16); } +// LDRSB Rd, [Rn, -#offset]! +static INSN_REGPARM void arm17D(GBASystem *gba, u32 opcode) { LDR_PREDEC_WB(OFFSET_IMM8, OP_LDRSB, 16); } +// LDRSB Rd, [Rn, Rm] +static INSN_REGPARM void arm19D(GBASystem *gba, u32 opcode) { LDR_PREINC(OFFSET_REG, OP_LDRSB, 16); } +// LDRSB Rd, [Rn, Rm]! +static INSN_REGPARM void arm1BD(GBASystem *gba, u32 opcode) { LDR_PREINC_WB(OFFSET_REG, OP_LDRSB, 16); } +// LDRSB Rd, [Rn, #offset] +static INSN_REGPARM void arm1DD(GBASystem *gba, u32 opcode) { LDR_PREINC(OFFSET_IMM8, OP_LDRSB, 16); } +// LDRSB Rd, [Rn, #offset]! +static INSN_REGPARM void arm1FD(GBASystem *gba, u32 opcode) { LDR_PREINC_WB(OFFSET_IMM8, OP_LDRSB, 16); } + +// LDRSH Rd, [Rn], -Rm +static INSN_REGPARM void arm01F(GBASystem *gba, u32 opcode) { LDR_POSTDEC(OFFSET_REG, OP_LDRSH, 16); } +// LDRSH Rd, [Rn], #-offset +static INSN_REGPARM void arm05F(GBASystem *gba, u32 opcode) { LDR_POSTDEC(OFFSET_IMM8, OP_LDRSH, 16); } +// LDRSH Rd, [Rn], Rm +static INSN_REGPARM void arm09F(GBASystem *gba, u32 opcode) { LDR_POSTINC(OFFSET_REG, OP_LDRSH, 16); } +// LDRSH Rd, [Rn], #offset +static INSN_REGPARM void arm0DF(GBASystem *gba, u32 opcode) { LDR_POSTINC(OFFSET_IMM8, OP_LDRSH, 16); } +// LDRSH Rd, [Rn, -Rm] +static INSN_REGPARM void arm11F(GBASystem *gba, u32 opcode) { LDR_PREDEC(OFFSET_REG, OP_LDRSH, 16); } +// LDRSH Rd, [Rn, -Rm]! +static INSN_REGPARM void arm13F(GBASystem *gba, u32 opcode) { LDR_PREDEC_WB(OFFSET_REG, OP_LDRSH, 16); } +// LDRSH Rd, [Rn, -#offset] +static INSN_REGPARM void arm15F(GBASystem *gba, u32 opcode) { LDR_PREDEC(OFFSET_IMM8, OP_LDRSH, 16); } +// LDRSH Rd, [Rn, -#offset]! +static INSN_REGPARM void arm17F(GBASystem *gba, u32 opcode) { LDR_PREDEC_WB(OFFSET_IMM8, OP_LDRSH, 16); } +// LDRSH Rd, [Rn, Rm] +static INSN_REGPARM void arm19F(GBASystem *gba, u32 opcode) { LDR_PREINC(OFFSET_REG, OP_LDRSH, 16); } +// LDRSH Rd, [Rn, Rm]! +static INSN_REGPARM void arm1BF(GBASystem *gba, u32 opcode) { LDR_PREINC_WB(OFFSET_REG, OP_LDRSH, 16); } +// LDRSH Rd, [Rn, #offset] +static INSN_REGPARM void arm1DF(GBASystem *gba, u32 opcode) { LDR_PREINC(OFFSET_IMM8, OP_LDRSH, 16); } +// LDRSH Rd, [Rn, #offset]! +static INSN_REGPARM void arm1FF(GBASystem *gba, u32 opcode) { LDR_PREINC_WB(OFFSET_IMM8, OP_LDRSH, 16); } + +// STR[T] Rd, [Rn], -# +// Note: STR and STRT do the same thing on the GBA (likewise for LDR/LDRT etc) +static INSN_REGPARM void arm400(GBASystem *gba, u32 opcode) { STR_POSTDEC(OFFSET_IMM, OP_STR, 32); } +// LDR[T] Rd, [Rn], -# +static INSN_REGPARM void arm410(GBASystem *gba, u32 opcode) { LDR_POSTDEC(OFFSET_IMM, OP_LDR, 32); } +// STRB[T] Rd, [Rn], -# +static INSN_REGPARM void arm440(GBASystem *gba, u32 opcode) { STR_POSTDEC(OFFSET_IMM, OP_STRB, 16); } +// LDRB[T] Rd, [Rn], -# +static INSN_REGPARM void arm450(GBASystem *gba, u32 opcode) { LDR_POSTDEC(OFFSET_IMM, OP_LDRB, 16); } +// STR[T] Rd, [Rn], # +static INSN_REGPARM void arm480(GBASystem *gba, u32 opcode) { STR_POSTINC(OFFSET_IMM, OP_STR, 32); } +// LDR Rd, [Rn], # +static INSN_REGPARM void arm490(GBASystem *gba, u32 opcode) { LDR_POSTINC(OFFSET_IMM, OP_LDR, 32); } +// STRB[T] Rd, [Rn], # +static INSN_REGPARM void arm4C0(GBASystem *gba, u32 opcode) { STR_POSTINC(OFFSET_IMM, OP_STRB, 16); } +// LDRB[T] Rd, [Rn], # +static INSN_REGPARM void arm4D0(GBASystem *gba, u32 opcode) { LDR_POSTINC(OFFSET_IMM, OP_LDRB, 16); } +// STR Rd, [Rn, -#] +static INSN_REGPARM void arm500(GBASystem *gba, u32 opcode) { STR_PREDEC(OFFSET_IMM, OP_STR, 32); } +// LDR Rd, [Rn, -#] +static INSN_REGPARM void arm510(GBASystem *gba, u32 opcode) { LDR_PREDEC(OFFSET_IMM, OP_LDR, 32); } +// STR Rd, [Rn, -#]! +static INSN_REGPARM void arm520(GBASystem *gba, u32 opcode) { STR_PREDEC_WB(OFFSET_IMM, OP_STR, 32); } +// LDR Rd, [Rn, -#]! +static INSN_REGPARM void arm530(GBASystem *gba, u32 opcode) { LDR_PREDEC_WB(OFFSET_IMM, OP_LDR, 32); } +// STRB Rd, [Rn, -#] +static INSN_REGPARM void arm540(GBASystem *gba, u32 opcode) { STR_PREDEC(OFFSET_IMM, OP_STRB, 16); } +// LDRB Rd, [Rn, -#] +static INSN_REGPARM void arm550(GBASystem *gba, u32 opcode) { LDR_PREDEC(OFFSET_IMM, OP_LDRB, 16); } +// STRB Rd, [Rn, -#]! +static INSN_REGPARM void arm560(GBASystem *gba, u32 opcode) { STR_PREDEC_WB(OFFSET_IMM, OP_STRB, 16); } +// LDRB Rd, [Rn, -#]! +static INSN_REGPARM void arm570(GBASystem *gba, u32 opcode) { LDR_PREDEC_WB(OFFSET_IMM, OP_LDRB, 16); } +// STR Rd, [Rn, #] +static INSN_REGPARM void arm580(GBASystem *gba, u32 opcode) { STR_PREINC(OFFSET_IMM, OP_STR, 32); } +// LDR Rd, [Rn, #] +static INSN_REGPARM void arm590(GBASystem *gba, u32 opcode) { LDR_PREINC(OFFSET_IMM, OP_LDR, 32); } +// STR Rd, [Rn, #]! +static INSN_REGPARM void arm5A0(GBASystem *gba, u32 opcode) { STR_PREINC_WB(OFFSET_IMM, OP_STR, 32); } +// LDR Rd, [Rn, #]! +static INSN_REGPARM void arm5B0(GBASystem *gba, u32 opcode) { LDR_PREINC_WB(OFFSET_IMM, OP_LDR, 32); } +// STRB Rd, [Rn, #] +static INSN_REGPARM void arm5C0(GBASystem *gba, u32 opcode) { STR_PREINC(OFFSET_IMM, OP_STRB, 16); } +// LDRB Rd, [Rn, #] +static INSN_REGPARM void arm5D0(GBASystem *gba, u32 opcode) { LDR_PREINC(OFFSET_IMM, OP_LDRB, 16); } +// STRB Rd, [Rn, #]! +static INSN_REGPARM void arm5E0(GBASystem *gba, u32 opcode) { STR_PREINC_WB(OFFSET_IMM, OP_STRB, 16); } +// LDRB Rd, [Rn, #]! +static INSN_REGPARM void arm5F0(GBASystem *gba, u32 opcode) { LDR_PREINC_WB(OFFSET_IMM, OP_LDRB, 16); } + +// STR[T] Rd, [Rn], -Rm, LSL # +static INSN_REGPARM void arm600(GBASystem *gba, u32 opcode) { STR_POSTDEC(OFFSET_LSL, OP_STR, 32); } +// STR[T] Rd, [Rn], -Rm, LSR # +static INSN_REGPARM void arm602(GBASystem *gba, u32 opcode) { STR_POSTDEC(OFFSET_LSR, OP_STR, 32); } +// STR[T] Rd, [Rn], -Rm, ASR # +static INSN_REGPARM void arm604(GBASystem *gba, u32 opcode) { STR_POSTDEC(OFFSET_ASR, OP_STR, 32); } +// STR[T] Rd, [Rn], -Rm, ROR # +static INSN_REGPARM void arm606(GBASystem *gba, u32 opcode) { STR_POSTDEC(OFFSET_ROR, OP_STR, 32); } +// LDR[T] Rd, [Rn], -Rm, LSL # +static INSN_REGPARM void arm610(GBASystem *gba, u32 opcode) { LDR_POSTDEC(OFFSET_LSL, OP_LDR, 32); } +// LDR[T] Rd, [Rn], -Rm, LSR # +static INSN_REGPARM void arm612(GBASystem *gba, u32 opcode) { LDR_POSTDEC(OFFSET_LSR, OP_LDR, 32); } +// LDR[T] Rd, [Rn], -Rm, ASR # +static INSN_REGPARM void arm614(GBASystem *gba, u32 opcode) { LDR_POSTDEC(OFFSET_ASR, OP_LDR, 32); } +// LDR[T] Rd, [Rn], -Rm, ROR # +static INSN_REGPARM void arm616(GBASystem *gba, u32 opcode) { LDR_POSTDEC(OFFSET_ROR, OP_LDR, 32); } +// STRB[T] Rd, [Rn], -Rm, LSL # +static INSN_REGPARM void arm640(GBASystem *gba, u32 opcode) { STR_POSTDEC(OFFSET_LSL, OP_STRB, 16); } +// STRB[T] Rd, [Rn], -Rm, LSR # +static INSN_REGPARM void arm642(GBASystem *gba, u32 opcode) { STR_POSTDEC(OFFSET_LSR, OP_STRB, 16); } +// STRB[T] Rd, [Rn], -Rm, ASR # +static INSN_REGPARM void arm644(GBASystem *gba, u32 opcode) { STR_POSTDEC(OFFSET_ASR, OP_STRB, 16); } +// STRB[T] Rd, [Rn], -Rm, ROR # +static INSN_REGPARM void arm646(GBASystem *gba, u32 opcode) { STR_POSTDEC(OFFSET_ROR, OP_STRB, 16); } +// LDRB[T] Rd, [Rn], -Rm, LSL # +static INSN_REGPARM void arm650(GBASystem *gba, u32 opcode) { LDR_POSTDEC(OFFSET_LSL, OP_LDRB, 16); } +// LDRB[T] Rd, [Rn], -Rm, LSR # +static INSN_REGPARM void arm652(GBASystem *gba, u32 opcode) { LDR_POSTDEC(OFFSET_LSR, OP_LDRB, 16); } +// LDRB[T] Rd, [Rn], -Rm, ASR # +static INSN_REGPARM void arm654(GBASystem *gba, u32 opcode) { LDR_POSTDEC(OFFSET_ASR, OP_LDRB, 16); } +// LDRB Rd, [Rn], -Rm, ROR # +static INSN_REGPARM void arm656(GBASystem *gba, u32 opcode) { LDR_POSTDEC(OFFSET_ROR, OP_LDRB, 16); } +// STR[T] Rd, [Rn], Rm, LSL # +static INSN_REGPARM void arm680(GBASystem *gba, u32 opcode) { STR_POSTINC(OFFSET_LSL, OP_STR, 32); } +// STR[T] Rd, [Rn], Rm, LSR # +static INSN_REGPARM void arm682(GBASystem *gba, u32 opcode) { STR_POSTINC(OFFSET_LSR, OP_STR, 32); } +// STR[T] Rd, [Rn], Rm, ASR # +static INSN_REGPARM void arm684(GBASystem *gba, u32 opcode) { STR_POSTINC(OFFSET_ASR, OP_STR, 32); } +// STR[T] Rd, [Rn], Rm, ROR # +static INSN_REGPARM void arm686(GBASystem *gba, u32 opcode) { STR_POSTINC(OFFSET_ROR, OP_STR, 32); } +// LDR[T] Rd, [Rn], Rm, LSL # +static INSN_REGPARM void arm690(GBASystem *gba, u32 opcode) { LDR_POSTINC(OFFSET_LSL, OP_LDR, 32); } +// LDR[T] Rd, [Rn], Rm, LSR # +static INSN_REGPARM void arm692(GBASystem *gba, u32 opcode) { LDR_POSTINC(OFFSET_LSR, OP_LDR, 32); } +// LDR[T] Rd, [Rn], Rm, ASR # +static INSN_REGPARM void arm694(GBASystem *gba, u32 opcode) { LDR_POSTINC(OFFSET_ASR, OP_LDR, 32); } +// LDR[T] Rd, [Rn], Rm, ROR # +static INSN_REGPARM void arm696(GBASystem *gba, u32 opcode) { LDR_POSTINC(OFFSET_ROR, OP_LDR, 32); } +// STRB[T] Rd, [Rn], Rm, LSL # +static INSN_REGPARM void arm6C0(GBASystem *gba, u32 opcode) { STR_POSTINC(OFFSET_LSL, OP_STRB, 16); } +// STRB[T] Rd, [Rn], Rm, LSR # +static INSN_REGPARM void arm6C2(GBASystem *gba, u32 opcode) { STR_POSTINC(OFFSET_LSR, OP_STRB, 16); } +// STRB[T] Rd, [Rn], Rm, ASR # +static INSN_REGPARM void arm6C4(GBASystem *gba, u32 opcode) { STR_POSTINC(OFFSET_ASR, OP_STRB, 16); } +// STRB[T] Rd, [Rn], Rm, ROR # +static INSN_REGPARM void arm6C6(GBASystem *gba, u32 opcode) { STR_POSTINC(OFFSET_ROR, OP_STRB, 16); } +// LDRB[T] Rd, [Rn], Rm, LSL # +static INSN_REGPARM void arm6D0(GBASystem *gba, u32 opcode) { LDR_POSTINC(OFFSET_LSL, OP_LDRB, 16); } +// LDRB[T] Rd, [Rn], Rm, LSR # +static INSN_REGPARM void arm6D2(GBASystem *gba, u32 opcode) { LDR_POSTINC(OFFSET_LSR, OP_LDRB, 16); } +// LDRB[T] Rd, [Rn], Rm, ASR # +static INSN_REGPARM void arm6D4(GBASystem *gba, u32 opcode) { LDR_POSTINC(OFFSET_ASR, OP_LDRB, 16); } +// LDRB[T] Rd, [Rn], Rm, ROR # +static INSN_REGPARM void arm6D6(GBASystem *gba, u32 opcode) { LDR_POSTINC(OFFSET_ROR, OP_LDRB, 16); } +// STR Rd, [Rn, -Rm, LSL #] +static INSN_REGPARM void arm700(GBASystem *gba, u32 opcode) { STR_PREDEC(OFFSET_LSL, OP_STR, 32); } +// STR Rd, [Rn, -Rm, LSR #] +static INSN_REGPARM void arm702(GBASystem *gba, u32 opcode) { STR_PREDEC(OFFSET_LSR, OP_STR, 32); } +// STR Rd, [Rn, -Rm, ASR #] +static INSN_REGPARM void arm704(GBASystem *gba, u32 opcode) { STR_PREDEC(OFFSET_ASR, OP_STR, 32); } +// STR Rd, [Rn, -Rm, ROR #] +static INSN_REGPARM void arm706(GBASystem *gba, u32 opcode) { STR_PREDEC(OFFSET_ROR, OP_STR, 32); } +// LDR Rd, [Rn, -Rm, LSL #] +static INSN_REGPARM void arm710(GBASystem *gba, u32 opcode) { LDR_PREDEC(OFFSET_LSL, OP_LDR, 32); } +// LDR Rd, [Rn, -Rm, LSR #] +static INSN_REGPARM void arm712(GBASystem *gba, u32 opcode) { LDR_PREDEC(OFFSET_LSR, OP_LDR, 32); } +// LDR Rd, [Rn, -Rm, ASR #] +static INSN_REGPARM void arm714(GBASystem *gba, u32 opcode) { LDR_PREDEC(OFFSET_ASR, OP_LDR, 32); } +// LDR Rd, [Rn, -Rm, ROR #] +static INSN_REGPARM void arm716(GBASystem *gba, u32 opcode) { LDR_PREDEC(OFFSET_ROR, OP_LDR, 32); } +// STR Rd, [Rn, -Rm, LSL #]! +static INSN_REGPARM void arm720(GBASystem *gba, u32 opcode) { STR_PREDEC_WB(OFFSET_LSL, OP_STR, 32); } +// STR Rd, [Rn, -Rm, LSR #]! +static INSN_REGPARM void arm722(GBASystem *gba, u32 opcode) { STR_PREDEC_WB(OFFSET_LSR, OP_STR, 32); } +// STR Rd, [Rn, -Rm, ASR #]! +static INSN_REGPARM void arm724(GBASystem *gba, u32 opcode) { STR_PREDEC_WB(OFFSET_ASR, OP_STR, 32); } +// STR Rd, [Rn, -Rm, ROR #]! +static INSN_REGPARM void arm726(GBASystem *gba, u32 opcode) { STR_PREDEC_WB(OFFSET_ROR, OP_STR, 32); } +// LDR Rd, [Rn, -Rm, LSL #]! +static INSN_REGPARM void arm730(GBASystem *gba, u32 opcode) { LDR_PREDEC_WB(OFFSET_LSL, OP_LDR, 32); } +// LDR Rd, [Rn, -Rm, LSR #]! +static INSN_REGPARM void arm732(GBASystem *gba, u32 opcode) { LDR_PREDEC_WB(OFFSET_LSR, OP_LDR, 32); } +// LDR Rd, [Rn, -Rm, ASR #]! +static INSN_REGPARM void arm734(GBASystem *gba, u32 opcode) { LDR_PREDEC_WB(OFFSET_ASR, OP_LDR, 32); } +// LDR Rd, [Rn, -Rm, ROR #]! +static INSN_REGPARM void arm736(GBASystem *gba, u32 opcode) { LDR_PREDEC_WB(OFFSET_ROR, OP_LDR, 32); } +// STRB Rd, [Rn, -Rm, LSL #] +static INSN_REGPARM void arm740(GBASystem *gba, u32 opcode) { STR_PREDEC(OFFSET_LSL, OP_STRB, 16); } +// STRB Rd, [Rn, -Rm, LSR #] +static INSN_REGPARM void arm742(GBASystem *gba, u32 opcode) { STR_PREDEC(OFFSET_LSR, OP_STRB, 16); } +// STRB Rd, [Rn, -Rm, ASR #] +static INSN_REGPARM void arm744(GBASystem *gba, u32 opcode) { STR_PREDEC(OFFSET_ASR, OP_STRB, 16); } +// STRB Rd, [Rn, -Rm, ROR #] +static INSN_REGPARM void arm746(GBASystem *gba, u32 opcode) { STR_PREDEC(OFFSET_ROR, OP_STRB, 16); } +// LDRB Rd, [Rn, -Rm, LSL #] +static INSN_REGPARM void arm750(GBASystem *gba, u32 opcode) { LDR_PREDEC(OFFSET_LSL, OP_LDRB, 16); } +// LDRB Rd, [Rn, -Rm, LSR #] +static INSN_REGPARM void arm752(GBASystem *gba, u32 opcode) { LDR_PREDEC(OFFSET_LSR, OP_LDRB, 16); } +// LDRB Rd, [Rn, -Rm, ASR #] +static INSN_REGPARM void arm754(GBASystem *gba, u32 opcode) { LDR_PREDEC(OFFSET_ASR, OP_LDRB, 16); } +// LDRB Rd, [Rn, -Rm, ROR #] +static INSN_REGPARM void arm756(GBASystem *gba, u32 opcode) { LDR_PREDEC(OFFSET_ROR, OP_LDRB, 16); } +// STRB Rd, [Rn, -Rm, LSL #]! +static INSN_REGPARM void arm760(GBASystem *gba, u32 opcode) { STR_PREDEC_WB(OFFSET_LSL, OP_STRB, 16); } +// STRB Rd, [Rn, -Rm, LSR #]! +static INSN_REGPARM void arm762(GBASystem *gba, u32 opcode) { STR_PREDEC_WB(OFFSET_LSR, OP_STRB, 16); } +// STRB Rd, [Rn, -Rm, ASR #]! +static INSN_REGPARM void arm764(GBASystem *gba, u32 opcode) { STR_PREDEC_WB(OFFSET_ASR, OP_STRB, 16); } +// STRB Rd, [Rn, -Rm, ROR #]! +static INSN_REGPARM void arm766(GBASystem *gba, u32 opcode) { STR_PREDEC_WB(OFFSET_ROR, OP_STRB, 16); } +// LDRB Rd, [Rn, -Rm, LSL #]! +static INSN_REGPARM void arm770(GBASystem *gba, u32 opcode) { LDR_PREDEC_WB(OFFSET_LSL, OP_LDRB, 16); } +// LDRB Rd, [Rn, -Rm, LSR #]! +static INSN_REGPARM void arm772(GBASystem *gba, u32 opcode) { LDR_PREDEC_WB(OFFSET_LSR, OP_LDRB, 16); } +// LDRB Rd, [Rn, -Rm, ASR #]! +static INSN_REGPARM void arm774(GBASystem *gba, u32 opcode) { LDR_PREDEC_WB(OFFSET_ASR, OP_LDRB, 16); } +// LDRB Rd, [Rn, -Rm, ROR #]! +static INSN_REGPARM void arm776(GBASystem *gba, u32 opcode) { LDR_PREDEC_WB(OFFSET_ROR, OP_LDRB, 16); } +// STR Rd, [Rn, Rm, LSL #] +static INSN_REGPARM void arm780(GBASystem *gba, u32 opcode) { STR_PREINC(OFFSET_LSL, OP_STR, 32); } +// STR Rd, [Rn, Rm, LSR #] +static INSN_REGPARM void arm782(GBASystem *gba, u32 opcode) { STR_PREINC(OFFSET_LSR, OP_STR, 32); } +// STR Rd, [Rn, Rm, ASR #] +static INSN_REGPARM void arm784(GBASystem *gba, u32 opcode) { STR_PREINC(OFFSET_ASR, OP_STR, 32); } +// STR Rd, [Rn, Rm, ROR #] +static INSN_REGPARM void arm786(GBASystem *gba, u32 opcode) { STR_PREINC(OFFSET_ROR, OP_STR, 32); } +// LDR Rd, [Rn, Rm, LSL #] +static INSN_REGPARM void arm790(GBASystem *gba, u32 opcode) { LDR_PREINC(OFFSET_LSL, OP_LDR, 32); } +// LDR Rd, [Rn, Rm, LSR #] +static INSN_REGPARM void arm792(GBASystem *gba, u32 opcode) { LDR_PREINC(OFFSET_LSR, OP_LDR, 32); } +// LDR Rd, [Rn, Rm, ASR #] +static INSN_REGPARM void arm794(GBASystem *gba, u32 opcode) { LDR_PREINC(OFFSET_ASR, OP_LDR, 32); } +// LDR Rd, [Rn, Rm, ROR #] +static INSN_REGPARM void arm796(GBASystem *gba, u32 opcode) { LDR_PREINC(OFFSET_ROR, OP_LDR, 32); } +// STR Rd, [Rn, Rm, LSL #]! +static INSN_REGPARM void arm7A0(GBASystem *gba, u32 opcode) { STR_PREINC_WB(OFFSET_LSL, OP_STR, 32); } +// STR Rd, [Rn, Rm, LSR #]! +static INSN_REGPARM void arm7A2(GBASystem *gba, u32 opcode) { STR_PREINC_WB(OFFSET_LSR, OP_STR, 32); } +// STR Rd, [Rn, Rm, ASR #]! +static INSN_REGPARM void arm7A4(GBASystem *gba, u32 opcode) { STR_PREINC_WB(OFFSET_ASR, OP_STR, 32); } +// STR Rd, [Rn, Rm, ROR #]! +static INSN_REGPARM void arm7A6(GBASystem *gba, u32 opcode) { STR_PREINC_WB(OFFSET_ROR, OP_STR, 32); } +// LDR Rd, [Rn, Rm, LSL #]! +static INSN_REGPARM void arm7B0(GBASystem *gba, u32 opcode) { LDR_PREINC_WB(OFFSET_LSL, OP_LDR, 32); } +// LDR Rd, [Rn, Rm, LSR #]! +static INSN_REGPARM void arm7B2(GBASystem *gba, u32 opcode) { LDR_PREINC_WB(OFFSET_LSR, OP_LDR, 32); } +// LDR Rd, [Rn, Rm, ASR #]! +static INSN_REGPARM void arm7B4(GBASystem *gba, u32 opcode) { LDR_PREINC_WB(OFFSET_ASR, OP_LDR, 32); } +// LDR Rd, [Rn, Rm, ROR #]! +static INSN_REGPARM void arm7B6(GBASystem *gba, u32 opcode) { LDR_PREINC_WB(OFFSET_ROR, OP_LDR, 32); } +// STRB Rd, [Rn, Rm, LSL #] +static INSN_REGPARM void arm7C0(GBASystem *gba, u32 opcode) { STR_PREINC(OFFSET_LSL, OP_STRB, 16); } +// STRB Rd, [Rn, Rm, LSR #] +static INSN_REGPARM void arm7C2(GBASystem *gba, u32 opcode) { STR_PREINC(OFFSET_LSR, OP_STRB, 16); } +// STRB Rd, [Rn, Rm, ASR #] +static INSN_REGPARM void arm7C4(GBASystem *gba, u32 opcode) { STR_PREINC(OFFSET_ASR, OP_STRB, 16); } +// STRB Rd, [Rn, Rm, ROR #] +static INSN_REGPARM void arm7C6(GBASystem *gba, u32 opcode) { STR_PREINC(OFFSET_ROR, OP_STRB, 16); } +// LDRB Rd, [Rn, Rm, LSL #] +static INSN_REGPARM void arm7D0(GBASystem *gba, u32 opcode) { LDR_PREINC(OFFSET_LSL, OP_LDRB, 16); } +// LDRB Rd, [Rn, Rm, LSR #] +static INSN_REGPARM void arm7D2(GBASystem *gba, u32 opcode) { LDR_PREINC(OFFSET_LSR, OP_LDRB, 16); } +// LDRB Rd, [Rn, Rm, ASR #] +static INSN_REGPARM void arm7D4(GBASystem *gba, u32 opcode) { LDR_PREINC(OFFSET_ASR, OP_LDRB, 16); } +// LDRB Rd, [Rn, Rm, ROR #] +static INSN_REGPARM void arm7D6(GBASystem *gba, u32 opcode) { LDR_PREINC(OFFSET_ROR, OP_LDRB, 16); } +// STRB Rd, [Rn, Rm, LSL #]! +static INSN_REGPARM void arm7E0(GBASystem *gba, u32 opcode) { STR_PREINC_WB(OFFSET_LSL, OP_STRB, 16); } +// STRB Rd, [Rn, Rm, LSR #]! +static INSN_REGPARM void arm7E2(GBASystem *gba, u32 opcode) { STR_PREINC_WB(OFFSET_LSR, OP_STRB, 16); } +// STRB Rd, [Rn, Rm, ASR #]! +static INSN_REGPARM void arm7E4(GBASystem *gba, u32 opcode) { STR_PREINC_WB(OFFSET_ASR, OP_STRB, 16); } +// STRB Rd, [Rn, Rm, ROR #]! +static INSN_REGPARM void arm7E6(GBASystem *gba, u32 opcode) { STR_PREINC_WB(OFFSET_ROR, OP_STRB, 16); } +// LDRB Rd, [Rn, Rm, LSL #]! +static INSN_REGPARM void arm7F0(GBASystem *gba, u32 opcode) { LDR_PREINC_WB(OFFSET_LSL, OP_LDRB, 16); } +// LDRB Rd, [Rn, Rm, LSR #]! +static INSN_REGPARM void arm7F2(GBASystem *gba, u32 opcode) { LDR_PREINC_WB(OFFSET_LSR, OP_LDRB, 16); } +// LDRB Rd, [Rn, Rm, ASR #]! +static INSN_REGPARM void arm7F4(GBASystem *gba, u32 opcode) { LDR_PREINC_WB(OFFSET_ASR, OP_LDRB, 16); } +// LDRB Rd, [Rn, Rm, ROR #]! +static INSN_REGPARM void arm7F6(GBASystem *gba, u32 opcode) { LDR_PREINC_WB(OFFSET_ROR, OP_LDRB, 16); } + +// STM/LDM //////////////////////////////////////////////////////////////// + +#define STM_REG(bit,num) \ + if (opcode & (1U<<(bit))) { \ + CPUWriteMemory(gba, address, gba->reg[(num)].I); \ + if (!count) { \ + gba->clockTicks += 1 + dataTicksAccess32(gba, address);\ + } else { \ + gba->clockTicks += 1 + dataTicksAccessSeq32(gba, address);\ + } \ + count++; \ + address += 4; \ + } +#define STMW_REG(bit,num) \ + if (opcode & (1U<<(bit))) { \ + CPUWriteMemory(gba, address, gba->reg[(num)].I); \ + if (!count) { \ + gba->clockTicks += 1 + dataTicksAccess32(gba, address);\ + } else { \ + gba->clockTicks += 1 + dataTicksAccessSeq32(gba, address);\ + } \ + gba->reg[base].I = temp; \ + count++; \ + address += 4; \ + } +#define LDM_REG(bit,num) \ + if (opcode & (1U<<(bit))) { \ + gba->reg[(num)].I = CPUReadMemory(gba, address); \ + if (!count) { \ + gba->clockTicks += 1 + dataTicksAccess32(gba, address);\ + } else { \ + gba->clockTicks += 1 + dataTicksAccessSeq32(gba, address);\ + } \ + count++; \ + address += 4; \ + } +#define STM_LOW(STORE_REG) \ + STORE_REG(0, 0); \ + STORE_REG(1, 1); \ + STORE_REG(2, 2); \ + STORE_REG(3, 3); \ + STORE_REG(4, 4); \ + STORE_REG(5, 5); \ + STORE_REG(6, 6); \ + STORE_REG(7, 7); +#define STM_HIGH(STORE_REG) \ + STORE_REG(8, 8); \ + STORE_REG(9, 9); \ + STORE_REG(10, 10); \ + STORE_REG(11, 11); \ + STORE_REG(12, 12); \ + STORE_REG(13, 13); \ + STORE_REG(14, 14); +#define STM_HIGH_2(STORE_REG) \ + if (gba->armMode == 0x11) { \ + STORE_REG(8, R8_FIQ); \ + STORE_REG(9, R9_FIQ); \ + STORE_REG(10, R10_FIQ); \ + STORE_REG(11, R11_FIQ); \ + STORE_REG(12, R12_FIQ); \ + } else { \ + STORE_REG(8, 8); \ + STORE_REG(9, 9); \ + STORE_REG(10, 10); \ + STORE_REG(11, 11); \ + STORE_REG(12, 12); \ + } \ + if (gba->armMode != 0x10 && gba->armMode != 0x1F) { \ + STORE_REG(13, R13_USR); \ + STORE_REG(14, R14_USR); \ + } else { \ + STORE_REG(13, 13); \ + STORE_REG(14, 14); \ + } +#define STM_PC \ + if (opcode & (1U<<15)) { \ + CPUWriteMemory(gba, address, gba->reg[15].I+4); \ + if (!count) { \ + gba->clockTicks += 1 + dataTicksAccess32(gba, address);\ + } else { \ + gba->clockTicks += 1 + dataTicksAccessSeq32(gba, address);\ + } \ + count++; \ + } +#define STMW_PC \ + if (opcode & (1U<<15)) { \ + CPUWriteMemory(gba, address, gba->reg[15].I+4); \ + if (!count) { \ + gba->clockTicks += 1 + dataTicksAccess32(gba, address);\ + } else { \ + gba->clockTicks += 1 + dataTicksAccessSeq32(gba, address);\ + } \ + gba->reg[base].I = temp; \ + count++; \ + } +#define LDM_LOW \ + LDM_REG(0, 0); \ + LDM_REG(1, 1); \ + LDM_REG(2, 2); \ + LDM_REG(3, 3); \ + LDM_REG(4, 4); \ + LDM_REG(5, 5); \ + LDM_REG(6, 6); \ + LDM_REG(7, 7); +#define LDM_HIGH \ + LDM_REG(8, 8); \ + LDM_REG(9, 9); \ + LDM_REG(10, 10); \ + LDM_REG(11, 11); \ + LDM_REG(12, 12); \ + LDM_REG(13, 13); \ + LDM_REG(14, 14); +#define LDM_HIGH_2 \ + if (gba->armMode == 0x11) { \ + LDM_REG(8, R8_FIQ); \ + LDM_REG(9, R9_FIQ); \ + LDM_REG(10, R10_FIQ); \ + LDM_REG(11, R11_FIQ); \ + LDM_REG(12, R12_FIQ); \ + } else { \ + LDM_REG(8, 8); \ + LDM_REG(9, 9); \ + LDM_REG(10, 10); \ + LDM_REG(11, 11); \ + LDM_REG(12, 12); \ + } \ + if (gba->armMode != 0x10 && gba->armMode != 0x1F) { \ + LDM_REG(13, R13_USR); \ + LDM_REG(14, R14_USR); \ + } else { \ + LDM_REG(13, 13); \ + LDM_REG(14, 14); \ + } +#define STM_ALL \ + STM_LOW(STM_REG); \ + STM_HIGH(STM_REG); \ + STM_PC; +#define STMW_ALL \ + STM_LOW(STMW_REG); \ + STM_HIGH(STMW_REG); \ + STMW_PC; +#define LDM_ALL \ + LDM_LOW; \ + LDM_HIGH; \ + if (opcode & (1U<<15)) { \ + gba->reg[15].I = CPUReadMemory(gba, address); \ + if (!count) { \ + gba->clockTicks += 1 + dataTicksAccess32(gba, address);\ + } else { \ + gba->clockTicks += 1 + dataTicksAccessSeq32(gba, address);\ + } \ + count++; \ + } \ + if (opcode & (1U<<15)) { \ + gba->armNextPC = gba->reg[15].I; \ + gba->reg[15].I += 4; \ + ARM_PREFETCH; \ + gba->clockTicks += 1 + codeTicksAccessSeq32(gba, gba->armNextPC);\ + } +#define STM_ALL_2 \ + STM_LOW(STM_REG); \ + STM_HIGH_2(STM_REG); \ + STM_PC; +#define STMW_ALL_2 \ + STM_LOW(STMW_REG); \ + STM_HIGH_2(STMW_REG); \ + STMW_PC; +#define LDM_ALL_2 \ + LDM_LOW; \ + if (opcode & (1U<<15)) { \ + LDM_HIGH; \ + gba->reg[15].I = CPUReadMemory(gba, address); \ + if (!count) { \ + gba->clockTicks += 1 + dataTicksAccess32(gba, address); \ + } else { \ + gba->clockTicks += 1 + dataTicksAccessSeq32(gba, address); \ + } \ + count++; \ + } else { \ + LDM_HIGH_2; \ + } +#define LDM_ALL_2B \ + if (opcode & (1U<<15)) { \ + CPUSwitchMode(gba, gba->reg[17].I & 0x1F, false); \ + if (gba->armState) { \ + gba->armNextPC = gba->reg[15].I & 0xFFFFFFFC; \ + gba->reg[15].I = gba->armNextPC + 4; \ + ARM_PREFETCH; \ + } else { \ + gba->armNextPC = gba->reg[15].I & 0xFFFFFFFE; \ + gba->reg[15].I = gba->armNextPC + 2; \ + THUMB_PREFETCH; \ + } \ + gba->clockTicks += 1 + codeTicksAccessSeq32(gba, gba->armNextPC);\ + } + + +// STMDA Rn, {Rlist} +static INSN_REGPARM void arm800(GBASystem *gba, u32 opcode) +{ + if (gba->busPrefetchCount == 0) + gba->busPrefetch = gba->busPrefetchEnable; + int base = (opcode & 0x000F0000) >> 16; + u32 temp = gba->reg[base].I - + 4 * (gba->cpuBitsSet[opcode & 255] + gba->cpuBitsSet[(opcode >> 8) & 255]); + u32 address = (temp + 4) & 0xFFFFFFFC; + int count = 0; + STM_ALL; + gba->clockTicks += 1 + codeTicksAccess32(gba, gba->armNextPC); +} + +// LDMDA Rn, {Rlist} +static INSN_REGPARM void arm810(GBASystem *gba, u32 opcode) +{ + if (gba->busPrefetchCount == 0) + gba->busPrefetch = gba->busPrefetchEnable; + int base = (opcode & 0x000F0000) >> 16; + u32 temp = gba->reg[base].I - + 4 * (gba->cpuBitsSet[opcode & 255] + gba->cpuBitsSet[(opcode >> 8) & 255]); + u32 address = (temp + 4) & 0xFFFFFFFC; + int count = 0; + LDM_ALL; + gba->clockTicks += 2 + codeTicksAccess32(gba, gba->armNextPC); +} + +// STMDA Rn!, {Rlist} +static INSN_REGPARM void arm820(GBASystem *gba, u32 opcode) +{ + if (gba->busPrefetchCount == 0) + gba->busPrefetch = gba->busPrefetchEnable; + int base = (opcode & 0x000F0000) >> 16; + u32 temp = gba->reg[base].I - + 4 * (gba->cpuBitsSet[opcode & 255] + gba->cpuBitsSet[(opcode >> 8) & 255]); + u32 address = (temp+4) & 0xFFFFFFFC; + int count = 0; + STMW_ALL; + gba->clockTicks += 1 + codeTicksAccess32(gba, gba->armNextPC); +} + +// LDMDA Rn!, {Rlist} +static INSN_REGPARM void arm830(GBASystem *gba, u32 opcode) +{ + if (gba->busPrefetchCount == 0) + gba->busPrefetch = gba->busPrefetchEnable; + int base = (opcode & 0x000F0000) >> 16; + u32 temp = gba->reg[base].I - + 4 * (gba->cpuBitsSet[opcode & 255] + gba->cpuBitsSet[(opcode >> 8) & 255]); + u32 address = (temp + 4) & 0xFFFFFFFC; + int count = 0; + LDM_ALL; + gba->clockTicks += 2 + codeTicksAccess32(gba, gba->armNextPC); + if (!(opcode & (1U << base))) + gba->reg[base].I = temp; +} + +// STMDA Rn, {Rlist}^ +static INSN_REGPARM void arm840(GBASystem *gba, u32 opcode) +{ + if (gba->busPrefetchCount == 0) + gba->busPrefetch = gba->busPrefetchEnable; + int base = (opcode & 0x000F0000) >> 16; + u32 temp = gba->reg[base].I - + 4 * (gba->cpuBitsSet[opcode & 255] + gba->cpuBitsSet[(opcode >> 8) & 255]); + u32 address = (temp+4) & 0xFFFFFFFC; + int count = 0; + STM_ALL_2; + gba->clockTicks += 1 + codeTicksAccess32(gba, gba->armNextPC); +} + +// LDMDA Rn, {Rlist}^ +static INSN_REGPARM void arm850(GBASystem *gba, u32 opcode) +{ + if (gba->busPrefetchCount == 0) + gba->busPrefetch = gba->busPrefetchEnable; + int base = (opcode & 0x000F0000) >> 16; + u32 temp = gba->reg[base].I - + 4 * (gba->cpuBitsSet[opcode & 255] + gba->cpuBitsSet[(opcode >> 8) & 255]); + u32 address = (temp + 4) & 0xFFFFFFFC; + int count = 0; + LDM_ALL_2; + LDM_ALL_2B; + gba->clockTicks += 2 + codeTicksAccess32(gba, gba->armNextPC); +} + +// STMDA Rn!, {Rlist}^ +static INSN_REGPARM void arm860(GBASystem *gba, u32 opcode) +{ + if (gba->busPrefetchCount == 0) + gba->busPrefetch = gba->busPrefetchEnable; + int base = (opcode & 0x000F0000) >> 16; + u32 temp = gba->reg[base].I - + 4 * (gba->cpuBitsSet[opcode & 255] + gba->cpuBitsSet[(opcode >> 8) & 255]); + u32 address = (temp+4) & 0xFFFFFFFC; + int count = 0; + STMW_ALL_2; + gba->clockTicks += 1 + codeTicksAccess32(gba, gba->armNextPC); +} + +// LDMDA Rn!, {Rlist}^ +static INSN_REGPARM void arm870(GBASystem *gba, u32 opcode) +{ + if (gba->busPrefetchCount == 0) + gba->busPrefetch = gba->busPrefetchEnable; + int base = (opcode & 0x000F0000) >> 16; + u32 temp = gba->reg[base].I - + 4 * (gba->cpuBitsSet[opcode & 255] + gba->cpuBitsSet[(opcode >> 8) & 255]); + u32 address = (temp + 4) & 0xFFFFFFFC; + int count = 0; + LDM_ALL_2; + if (!(opcode & (1U << base))) + gba->reg[base].I = temp; + LDM_ALL_2B; + gba->clockTicks += 2 + codeTicksAccess32(gba, gba->armNextPC); +} + +// STMIA Rn, {Rlist} +static INSN_REGPARM void arm880(GBASystem *gba, u32 opcode) +{ + if (gba->busPrefetchCount == 0) + gba->busPrefetch = gba->busPrefetchEnable; + int base = (opcode & 0x000F0000) >> 16; + u32 address = gba->reg[base].I & 0xFFFFFFFC; + int count = 0; + STM_ALL; + gba->clockTicks += 1 + codeTicksAccess32(gba, gba->armNextPC); +} + +// LDMIA Rn, {Rlist} +static INSN_REGPARM void arm890(GBASystem *gba, u32 opcode) +{ + if (gba->busPrefetchCount == 0) + gba->busPrefetch = gba->busPrefetchEnable; + int base = (opcode & 0x000F0000) >> 16; + u32 address = gba->reg[base].I & 0xFFFFFFFC; + int count = 0; + LDM_ALL; + gba->clockTicks += 2 + codeTicksAccess32(gba, gba->armNextPC); +} + +// STMIA Rn!, {Rlist} +static INSN_REGPARM void arm8A0(GBASystem *gba, u32 opcode) +{ + if (gba->busPrefetchCount == 0) + gba->busPrefetch = gba->busPrefetchEnable; + int base = (opcode & 0x000F0000) >> 16; + u32 address = gba->reg[base].I & 0xFFFFFFFC; + int count = 0; + u32 temp = gba->reg[base].I + + 4 * (gba->cpuBitsSet[opcode & 0xFF] + gba->cpuBitsSet[(opcode >> 8) & 255]); + STMW_ALL; + gba->clockTicks += 1 + codeTicksAccess32(gba, gba->armNextPC); +} + +// LDMIA Rn!, {Rlist} +static INSN_REGPARM void arm8B0(GBASystem *gba, u32 opcode) +{ + if (gba->busPrefetchCount == 0) + gba->busPrefetch = gba->busPrefetchEnable; + int base = (opcode & 0x000F0000) >> 16; + u32 temp = gba->reg[base].I + + 4 * (gba->cpuBitsSet[opcode & 255] + gba->cpuBitsSet[(opcode >> 8) & 255]); + u32 address = gba->reg[base].I & 0xFFFFFFFC; + int count = 0; + LDM_ALL; + gba->clockTicks += 2 + codeTicksAccess32(gba, gba->armNextPC); + if (!(opcode & (1U << base))) + gba->reg[base].I = temp; +} + +// STMIA Rn, {Rlist}^ +static INSN_REGPARM void arm8C0(GBASystem *gba, u32 opcode) +{ + if (gba->busPrefetchCount == 0) + gba->busPrefetch = gba->busPrefetchEnable; + int base = (opcode & 0x000F0000) >> 16; + u32 address = gba->reg[base].I & 0xFFFFFFFC; + int count = 0; + STM_ALL_2; + gba->clockTicks += 1 + codeTicksAccess32(gba, gba->armNextPC); +} + +// LDMIA Rn, {Rlist}^ +static INSN_REGPARM void arm8D0(GBASystem *gba, u32 opcode) +{ + if (gba->busPrefetchCount == 0) + gba->busPrefetch = gba->busPrefetchEnable; + int base = (opcode & 0x000F0000) >> 16; + u32 address = gba->reg[base].I & 0xFFFFFFFC; + int count = 0; + LDM_ALL_2; + LDM_ALL_2B; + gba->clockTicks += 2 + codeTicksAccess32(gba, gba->armNextPC); +} + +// STMIA Rn!, {Rlist}^ +static INSN_REGPARM void arm8E0(GBASystem *gba, u32 opcode) +{ + if (gba->busPrefetchCount == 0) + gba->busPrefetch = gba->busPrefetchEnable; + int base = (opcode & 0x000F0000) >> 16; + u32 address = gba->reg[base].I & 0xFFFFFFFC; + int count = 0; + u32 temp = gba->reg[base].I + + 4 * (gba->cpuBitsSet[opcode & 0xFF] + gba->cpuBitsSet[(opcode >> 8) & 255]); + STMW_ALL_2; + gba->clockTicks += 1 + codeTicksAccess32(gba, gba->armNextPC); +} + +// LDMIA Rn!, {Rlist}^ +static INSN_REGPARM void arm8F0(GBASystem *gba, u32 opcode) +{ + if (gba->busPrefetchCount == 0) + gba->busPrefetch = gba->busPrefetchEnable; + int base = (opcode & 0x000F0000) >> 16; + u32 temp = gba->reg[base].I + + 4 * (gba->cpuBitsSet[opcode & 255] + gba->cpuBitsSet[(opcode >> 8) & 255]); + u32 address = gba->reg[base].I & 0xFFFFFFFC; + int count = 0; + LDM_ALL_2; + if (!(opcode & (1U << base))) + gba->reg[base].I = temp; + LDM_ALL_2B; + gba->clockTicks += 2 + codeTicksAccess32(gba, gba->armNextPC); +} + +// STMDB Rn, {Rlist} +static INSN_REGPARM void arm900(GBASystem *gba, u32 opcode) +{ + if (gba->busPrefetchCount == 0) + gba->busPrefetch = gba->busPrefetchEnable; + int base = (opcode & 0x000F0000) >> 16; + u32 temp = gba->reg[base].I - + 4 * (gba->cpuBitsSet[opcode & 255] + gba->cpuBitsSet[(opcode >> 8) & 255]); + u32 address = temp & 0xFFFFFFFC; + int count = 0; + STM_ALL; + gba->clockTicks += 1 + codeTicksAccess32(gba, gba->armNextPC); +} + +// LDMDB Rn, {Rlist} +static INSN_REGPARM void arm910(GBASystem *gba, u32 opcode) +{ + if (gba->busPrefetchCount == 0) + gba->busPrefetch = gba->busPrefetchEnable; + int base = (opcode & 0x000F0000) >> 16; + u32 temp = gba->reg[base].I - + 4 * (gba->cpuBitsSet[opcode & 255] + gba->cpuBitsSet[(opcode >> 8) & 255]); + u32 address = temp & 0xFFFFFFFC; + int count = 0; + LDM_ALL; + gba->clockTicks += 2 + codeTicksAccess32(gba, gba->armNextPC); +} + +// STMDB Rn!, {Rlist} +static INSN_REGPARM void arm920(GBASystem *gba, u32 opcode) +{ + if (gba->busPrefetchCount == 0) + gba->busPrefetch = gba->busPrefetchEnable; + int base = (opcode & 0x000F0000) >> 16; + u32 temp = gba->reg[base].I - + 4 * (gba->cpuBitsSet[opcode & 255] + gba->cpuBitsSet[(opcode >> 8) & 255]); + u32 address = temp & 0xFFFFFFFC; + int count = 0; + STMW_ALL; + gba->clockTicks += 1 + codeTicksAccess32(gba, gba->armNextPC); +} + +// LDMDB Rn!, {Rlist} +static INSN_REGPARM void arm930(GBASystem *gba, u32 opcode) +{ + if (gba->busPrefetchCount == 0) + gba->busPrefetch = gba->busPrefetchEnable; + int base = (opcode & 0x000F0000) >> 16; + u32 temp = gba->reg[base].I - + 4 * (gba->cpuBitsSet[opcode & 255] + gba->cpuBitsSet[(opcode >> 8) & 255]); + u32 address = temp & 0xFFFFFFFC; + int count = 0; + LDM_ALL; + gba->clockTicks += 2 + codeTicksAccess32(gba, gba->armNextPC); + if (!(opcode & (1U << base))) + gba->reg[base].I = temp; +} + +// STMDB Rn, {Rlist}^ +static INSN_REGPARM void arm940(GBASystem *gba, u32 opcode) +{ + if (gba->busPrefetchCount == 0) + gba->busPrefetch = gba->busPrefetchEnable; + int base = (opcode & 0x000F0000) >> 16; + u32 temp = gba->reg[base].I - + 4 * (gba->cpuBitsSet[opcode & 255] + gba->cpuBitsSet[(opcode >> 8) & 255]); + u32 address = temp & 0xFFFFFFFC; + int count = 0; + STM_ALL_2; + gba->clockTicks += 1 + codeTicksAccess32(gba, gba->armNextPC); +} + +// LDMDB Rn, {Rlist}^ +static INSN_REGPARM void arm950(GBASystem *gba, u32 opcode) +{ + if (gba->busPrefetchCount == 0) + gba->busPrefetch = gba->busPrefetchEnable; + int base = (opcode & 0x000F0000) >> 16; + u32 temp = gba->reg[base].I - + 4 * (gba->cpuBitsSet[opcode & 255] + gba->cpuBitsSet[(opcode >> 8) & 255]); + u32 address = temp & 0xFFFFFFFC; + int count = 0; + LDM_ALL_2; + LDM_ALL_2B; + gba->clockTicks += 2 + codeTicksAccess32(gba, gba->armNextPC); +} + +// STMDB Rn!, {Rlist}^ +static INSN_REGPARM void arm960(GBASystem *gba, u32 opcode) +{ + if (gba->busPrefetchCount == 0) + gba->busPrefetch = gba->busPrefetchEnable; + int base = (opcode & 0x000F0000) >> 16; + u32 temp = gba->reg[base].I - + 4 * (gba->cpuBitsSet[opcode & 255] + gba->cpuBitsSet[(opcode >> 8) & 255]); + u32 address = temp & 0xFFFFFFFC; + int count = 0; + STMW_ALL_2; + gba->clockTicks += 1 + codeTicksAccess32(gba, gba->armNextPC); +} + +// LDMDB Rn!, {Rlist}^ +static INSN_REGPARM void arm970(GBASystem *gba, u32 opcode) +{ + if (gba->busPrefetchCount == 0) + gba->busPrefetch = gba->busPrefetchEnable; + int base = (opcode & 0x000F0000) >> 16; + u32 temp = gba->reg[base].I - + 4 * (gba->cpuBitsSet[opcode & 255] + gba->cpuBitsSet[(opcode >> 8) & 255]); + u32 address = temp & 0xFFFFFFFC; + int count = 0; + LDM_ALL_2; + if (!(opcode & (1U << base))) + gba->reg[base].I = temp; + LDM_ALL_2B; + gba->clockTicks += 2 + codeTicksAccess32(gba, gba->armNextPC); +} + +// STMIB Rn, {Rlist} +static INSN_REGPARM void arm980(GBASystem *gba, u32 opcode) +{ + if (gba->busPrefetchCount == 0) + gba->busPrefetch = gba->busPrefetchEnable; + int base = (opcode & 0x000F0000) >> 16; + u32 address = (gba->reg[base].I+4) & 0xFFFFFFFC; + int count = 0; + STM_ALL; + gba->clockTicks += 1 + codeTicksAccess32(gba, gba->armNextPC); +} + +// LDMIB Rn, {Rlist} +static INSN_REGPARM void arm990(GBASystem *gba, u32 opcode) +{ + if (gba->busPrefetchCount == 0) + gba->busPrefetch = gba->busPrefetchEnable; + int base = (opcode & 0x000F0000) >> 16; + u32 address = (gba->reg[base].I+4) & 0xFFFFFFFC; + int count = 0; + LDM_ALL; + gba->clockTicks += 2 + codeTicksAccess32(gba, gba->armNextPC); +} + +// STMIB Rn!, {Rlist} +static INSN_REGPARM void arm9A0(GBASystem *gba, u32 opcode) +{ + if (gba->busPrefetchCount == 0) + gba->busPrefetch = gba->busPrefetchEnable; + int base = (opcode & 0x000F0000) >> 16; + u32 address = (gba->reg[base].I+4) & 0xFFFFFFFC; + int count = 0; + u32 temp = gba->reg[base].I + + 4 * (gba->cpuBitsSet[opcode & 0xFF] + gba->cpuBitsSet[(opcode >> 8) & 255]); + STMW_ALL; + gba->clockTicks += 1 + codeTicksAccess32(gba, gba->armNextPC); +} + +// LDMIB Rn!, {Rlist} +static INSN_REGPARM void arm9B0(GBASystem *gba, u32 opcode) +{ + if (gba->busPrefetchCount == 0) + gba->busPrefetch = gba->busPrefetchEnable; + int base = (opcode & 0x000F0000) >> 16; + u32 temp = gba->reg[base].I + + 4 * (gba->cpuBitsSet[opcode & 255] + gba->cpuBitsSet[(opcode >> 8) & 255]); + u32 address = (gba->reg[base].I+4) & 0xFFFFFFFC; + int count = 0; + LDM_ALL; + gba->clockTicks += 2 + codeTicksAccess32(gba, gba->armNextPC); + if (!(opcode & (1U << base))) + gba->reg[base].I = temp; +} + +// STMIB Rn, {Rlist}^ +static INSN_REGPARM void arm9C0(GBASystem *gba, u32 opcode) +{ + if (gba->busPrefetchCount == 0) + gba->busPrefetch = gba->busPrefetchEnable; + int base = (opcode & 0x000F0000) >> 16; + u32 address = (gba->reg[base].I+4) & 0xFFFFFFFC; + int count = 0; + STM_ALL_2; + gba->clockTicks += 1 + codeTicksAccess32(gba, gba->armNextPC); +} + +// LDMIB Rn, {Rlist}^ +static INSN_REGPARM void arm9D0(GBASystem *gba, u32 opcode) +{ + if (gba->busPrefetchCount == 0) + gba->busPrefetch = gba->busPrefetchEnable; + int base = (opcode & 0x000F0000) >> 16; + u32 address = (gba->reg[base].I+4) & 0xFFFFFFFC; + int count = 0; + LDM_ALL_2; + LDM_ALL_2B; + gba->clockTicks += 2 + codeTicksAccess32(gba, gba->armNextPC); +} + +// STMIB Rn!, {Rlist}^ +static INSN_REGPARM void arm9E0(GBASystem *gba, u32 opcode) +{ + if (gba->busPrefetchCount == 0) + gba->busPrefetch = gba->busPrefetchEnable; + int base = (opcode & 0x000F0000) >> 16; + u32 address = (gba->reg[base].I+4) & 0xFFFFFFFC; + int count = 0; + u32 temp = gba->reg[base].I + + 4 * (gba->cpuBitsSet[opcode & 0xFF] + gba->cpuBitsSet[(opcode >> 8) & 255]); + STMW_ALL_2; + gba->clockTicks += 1 + codeTicksAccess32(gba, gba->armNextPC); +} + +// LDMIB Rn!, {Rlist}^ +static INSN_REGPARM void arm9F0(GBASystem *gba, u32 opcode) +{ + if (gba->busPrefetchCount == 0) + gba->busPrefetch = gba->busPrefetchEnable; + int base = (opcode & 0x000F0000) >> 16; + u32 temp = gba->reg[base].I + + 4 * (gba->cpuBitsSet[opcode & 255] + gba->cpuBitsSet[(opcode >> 8) & 255]); + u32 address = (gba->reg[base].I+4) & 0xFFFFFFFC; + int count = 0; + LDM_ALL_2; + if (!(opcode & (1U << base))) + gba->reg[base].I = temp; + LDM_ALL_2B; + gba->clockTicks += 2 + codeTicksAccess32(gba, gba->armNextPC); +} + +// B/BL/SWI and (unimplemented) coproc support //////////////////////////// + +// B +static INSN_REGPARM void armA00(GBASystem *gba, u32 opcode) +{ + int offset = opcode & 0x00FFFFFF; + if (offset & 0x00800000) + offset |= 0xFF000000; // negative offset + gba->reg[15].I += offset<<2; + gba->armNextPC = gba->reg[15].I; + gba->reg[15].I += 4; + ARM_PREFETCH; + gba->clockTicks = codeTicksAccessSeq32(gba, gba->armNextPC) + 1; + gba->clockTicks += 2 + codeTicksAccess32(gba, gba->armNextPC) + + codeTicksAccessSeq32(gba, gba->armNextPC); + gba->busPrefetchCount = 0; +} + +// BL +static INSN_REGPARM void armB00(GBASystem *gba, u32 opcode) +{ + int offset = opcode & 0x00FFFFFF; + if (offset & 0x00800000) + offset |= 0xFF000000; // negative offset + gba->reg[14].I = gba->reg[15].I - 4; + gba->reg[15].I += offset<<2; + gba->armNextPC = gba->reg[15].I; + gba->reg[15].I += 4; + ARM_PREFETCH; + gba->clockTicks = codeTicksAccessSeq32(gba, gba->armNextPC) + 1; + gba->clockTicks += 2 + codeTicksAccess32(gba, gba->armNextPC) + + codeTicksAccessSeq32(gba, gba->armNextPC); + gba->busPrefetchCount = 0; +} + + +#define armE01 armUnknownInsn + + +// SWI +static INSN_REGPARM void armF00(GBASystem *gba, u32 opcode) +{ + gba->clockTicks = codeTicksAccessSeq32(gba, gba->armNextPC) + 1; + gba->clockTicks += 2 + codeTicksAccess32(gba, gba->armNextPC) + + codeTicksAccessSeq32(gba, gba->armNextPC); + gba->busPrefetchCount = 0; + CPUSoftwareInterrupt(gba, opcode & 0x00FFFFFF); +} + +// Instruction table ////////////////////////////////////////////////////// + +typedef INSN_REGPARM void (*insnfunc_t)(GBASystem *, u32 opcode); +#define REP16(insn) \ + insn,insn,insn,insn,insn,insn,insn,insn,\ + insn,insn,insn,insn,insn,insn,insn,insn +#define REP256(insn) \ + REP16(insn),REP16(insn),REP16(insn),REP16(insn),\ + REP16(insn),REP16(insn),REP16(insn),REP16(insn),\ + REP16(insn),REP16(insn),REP16(insn),REP16(insn),\ + REP16(insn),REP16(insn),REP16(insn),REP16(insn) +#define arm_UI armUnknownInsn +#define arm_BP armUnknownInsn +static insnfunc_t armInsnTable[4096] = { + arm000,arm001,arm002,arm003,arm004,arm005,arm006,arm007, // 000 + arm000,arm009,arm002,arm00B,arm004,arm_UI,arm006,arm_UI, // 008 + arm010,arm011,arm012,arm013,arm014,arm015,arm016,arm017, // 010 + arm010,arm019,arm012,arm01B,arm014,arm01D,arm016,arm01F, // 018 + arm020,arm021,arm022,arm023,arm024,arm025,arm026,arm027, // 020 + arm020,arm029,arm022,arm_UI,arm024,arm_UI,arm026,arm_UI, // 028 + arm030,arm031,arm032,arm033,arm034,arm035,arm036,arm037, // 030 + arm030,arm039,arm032,arm_UI,arm034,arm01D,arm036,arm01F, // 038 + arm040,arm041,arm042,arm043,arm044,arm045,arm046,arm047, // 040 + arm040,arm_UI,arm042,arm04B,arm044,arm_UI,arm046,arm_UI, // 048 + arm050,arm051,arm052,arm053,arm054,arm055,arm056,arm057, // 050 + arm050,arm_UI,arm052,arm05B,arm054,arm05D,arm056,arm05F, // 058 + arm060,arm061,arm062,arm063,arm064,arm065,arm066,arm067, // 060 + arm060,arm_UI,arm062,arm_UI,arm064,arm_UI,arm066,arm_UI, // 068 + arm070,arm071,arm072,arm073,arm074,arm075,arm076,arm077, // 070 + arm070,arm_UI,arm072,arm_UI,arm074,arm05D,arm076,arm05F, // 078 + arm080,arm081,arm082,arm083,arm084,arm085,arm086,arm087, // 080 + arm080,arm089,arm082,arm08B,arm084,arm_UI,arm086,arm_UI, // 088 + arm090,arm091,arm092,arm093,arm094,arm095,arm096,arm097, // 090 + arm090,arm099,arm092,arm09B,arm094,arm09D,arm096,arm09F, // 098 + arm0A0,arm0A1,arm0A2,arm0A3,arm0A4,arm0A5,arm0A6,arm0A7, // 0A0 + arm0A0,arm0A9,arm0A2,arm_UI,arm0A4,arm_UI,arm0A6,arm_UI, // 0A8 + arm0B0,arm0B1,arm0B2,arm0B3,arm0B4,arm0B5,arm0B6,arm0B7, // 0B0 + arm0B0,arm0B9,arm0B2,arm_UI,arm0B4,arm09D,arm0B6,arm09F, // 0B8 + arm0C0,arm0C1,arm0C2,arm0C3,arm0C4,arm0C5,arm0C6,arm0C7, // 0C0 + arm0C0,arm0C9,arm0C2,arm0CB,arm0C4,arm_UI,arm0C6,arm_UI, // 0C8 + arm0D0,arm0D1,arm0D2,arm0D3,arm0D4,arm0D5,arm0D6,arm0D7, // 0D0 + arm0D0,arm0D9,arm0D2,arm0DB,arm0D4,arm0DD,arm0D6,arm0DF, // 0D8 + arm0E0,arm0E1,arm0E2,arm0E3,arm0E4,arm0E5,arm0E6,arm0E7, // 0E0 + arm0E0,arm0E9,arm0E2,arm_UI,arm0E4,arm_UI,arm0E6,arm_UI, // 0E8 + arm0F0,arm0F1,arm0F2,arm0F3,arm0F4,arm0F5,arm0F6,arm0F7, // 0F0 + arm0F0,arm0F9,arm0F2,arm_UI,arm0F4,arm0DD,arm0F6,arm0DF, // 0F8 + + arm100,arm_UI,arm_UI,arm_UI,arm_UI,arm_UI,arm_UI,arm_UI, // 100 + arm_UI,arm109,arm_UI,arm10B,arm_UI,arm_UI,arm_UI,arm_UI, // 108 + arm110,arm111,arm112,arm113,arm114,arm115,arm116,arm117, // 110 + arm110,arm_UI,arm112,arm11B,arm114,arm11D,arm116,arm11F, // 118 + arm120,arm121,arm_UI,arm_UI,arm_UI,arm_UI,arm_UI,arm_BP, // 120 + arm_UI,arm_UI,arm_UI,arm12B,arm_UI,arm_UI,arm_UI,arm_UI, // 128 + arm130,arm131,arm132,arm133,arm134,arm135,arm136,arm137, // 130 + arm130,arm_UI,arm132,arm13B,arm134,arm13D,arm136,arm13F, // 138 + arm140,arm_UI,arm_UI,arm_UI,arm_UI,arm_UI,arm_UI,arm_UI, // 140 + arm_UI,arm149,arm_UI,arm14B,arm_UI,arm_UI,arm_UI,arm_UI, // 148 + arm150,arm151,arm152,arm153,arm154,arm155,arm156,arm157, // 150 + arm150,arm_UI,arm152,arm15B,arm154,arm15D,arm156,arm15F, // 158 + arm160,arm_UI,arm_UI,arm_UI,arm_UI,arm_UI,arm_UI,arm_UI, // 160 + arm_UI,arm_UI,arm_UI,arm16B,arm_UI,arm_UI,arm_UI,arm_UI, // 168 + arm170,arm171,arm172,arm173,arm174,arm175,arm176,arm177, // 170 + arm170,arm_UI,arm172,arm17B,arm174,arm17D,arm176,arm17F, // 178 + arm180,arm181,arm182,arm183,arm184,arm185,arm186,arm187, // 180 + arm180,arm_UI,arm182,arm18B,arm184,arm_UI,arm186,arm_UI, // 188 + arm190,arm191,arm192,arm193,arm194,arm195,arm196,arm197, // 190 + arm190,arm_UI,arm192,arm19B,arm194,arm19D,arm196,arm19F, // 198 + arm1A0,arm1A1,arm1A2,arm1A3,arm1A4,arm1A5,arm1A6,arm1A7, // 1A0 + arm1A0,arm_UI,arm1A2,arm1AB,arm1A4,arm_UI,arm1A6,arm_UI, // 1A8 + arm1B0,arm1B1,arm1B2,arm1B3,arm1B4,arm1B5,arm1B6,arm1B7, // 1B0 + arm1B0,arm_UI,arm1B2,arm1BB,arm1B4,arm1BD,arm1B6,arm1BF, // 1B8 + arm1C0,arm1C1,arm1C2,arm1C3,arm1C4,arm1C5,arm1C6,arm1C7, // 1C0 + arm1C0,arm_UI,arm1C2,arm1CB,arm1C4,arm_UI,arm1C6,arm_UI, // 1C8 + arm1D0,arm1D1,arm1D2,arm1D3,arm1D4,arm1D5,arm1D6,arm1D7, // 1D0 + arm1D0,arm_UI,arm1D2,arm1DB,arm1D4,arm1DD,arm1D6,arm1DF, // 1D8 + arm1E0,arm1E1,arm1E2,arm1E3,arm1E4,arm1E5,arm1E6,arm1E7, // 1E0 + arm1E0,arm_UI,arm1E2,arm1EB,arm1E4,arm_UI,arm1E6,arm_UI, // 1E8 + arm1F0,arm1F1,arm1F2,arm1F3,arm1F4,arm1F5,arm1F6,arm1F7, // 1F0 + arm1F0,arm_UI,arm1F2,arm1FB,arm1F4,arm1FD,arm1F6,arm1FF, // 1F8 + + REP16(arm200),REP16(arm210),REP16(arm220),REP16(arm230), // 200 + REP16(arm240),REP16(arm250),REP16(arm260),REP16(arm270), // 240 + REP16(arm280),REP16(arm290),REP16(arm2A0),REP16(arm2B0), // 280 + REP16(arm2C0),REP16(arm2D0),REP16(arm2E0),REP16(arm2F0), // 2C0 + REP16(arm_UI),REP16(arm310),REP16(arm320),REP16(arm330), // 300 + REP16(arm_UI),REP16(arm350),REP16(arm360),REP16(arm370), // 340 + REP16(arm380),REP16(arm390),REP16(arm3A0),REP16(arm3B0), // 380 + REP16(arm3C0),REP16(arm3D0),REP16(arm3E0),REP16(arm3F0), // 3C0 + + REP16(arm400),REP16(arm410),REP16(arm400),REP16(arm410), // 400 + REP16(arm440),REP16(arm450),REP16(arm440),REP16(arm450), // 440 + REP16(arm480),REP16(arm490),REP16(arm480),REP16(arm490), // 480 + REP16(arm4C0),REP16(arm4D0),REP16(arm4C0),REP16(arm4D0), // 4C0 + REP16(arm500),REP16(arm510),REP16(arm520),REP16(arm530), // 500 + REP16(arm540),REP16(arm550),REP16(arm560),REP16(arm570), // 540 + REP16(arm580),REP16(arm590),REP16(arm5A0),REP16(arm5B0), // 580 + REP16(arm5C0),REP16(arm5D0),REP16(arm5E0),REP16(arm5F0), // 5C0 + + arm600,arm_UI,arm602,arm_UI,arm604,arm_UI,arm606,arm_UI, // 600 + arm600,arm_UI,arm602,arm_UI,arm604,arm_UI,arm606,arm_UI, // 608 + arm610,arm_UI,arm612,arm_UI,arm614,arm_UI,arm616,arm_UI, // 610 + arm610,arm_UI,arm612,arm_UI,arm614,arm_UI,arm616,arm_UI, // 618 + arm600,arm_UI,arm602,arm_UI,arm604,arm_UI,arm606,arm_UI, // 620 + arm600,arm_UI,arm602,arm_UI,arm604,arm_UI,arm606,arm_UI, // 628 + arm610,arm_UI,arm612,arm_UI,arm614,arm_UI,arm616,arm_UI, // 630 + arm610,arm_UI,arm612,arm_UI,arm614,arm_UI,arm616,arm_UI, // 638 + arm640,arm_UI,arm642,arm_UI,arm644,arm_UI,arm646,arm_UI, // 640 + arm640,arm_UI,arm642,arm_UI,arm644,arm_UI,arm646,arm_UI, // 648 + arm650,arm_UI,arm652,arm_UI,arm654,arm_UI,arm656,arm_UI, // 650 + arm650,arm_UI,arm652,arm_UI,arm654,arm_UI,arm656,arm_UI, // 658 + arm640,arm_UI,arm642,arm_UI,arm644,arm_UI,arm646,arm_UI, // 660 + arm640,arm_UI,arm642,arm_UI,arm644,arm_UI,arm646,arm_UI, // 668 + arm650,arm_UI,arm652,arm_UI,arm654,arm_UI,arm656,arm_UI, // 670 + arm650,arm_UI,arm652,arm_UI,arm654,arm_UI,arm656,arm_UI, // 678 + arm680,arm_UI,arm682,arm_UI,arm684,arm_UI,arm686,arm_UI, // 680 + arm680,arm_UI,arm682,arm_UI,arm684,arm_UI,arm686,arm_UI, // 688 + arm690,arm_UI,arm692,arm_UI,arm694,arm_UI,arm696,arm_UI, // 690 + arm690,arm_UI,arm692,arm_UI,arm694,arm_UI,arm696,arm_UI, // 698 + arm680,arm_UI,arm682,arm_UI,arm684,arm_UI,arm686,arm_UI, // 6A0 + arm680,arm_UI,arm682,arm_UI,arm684,arm_UI,arm686,arm_UI, // 6A8 + arm690,arm_UI,arm692,arm_UI,arm694,arm_UI,arm696,arm_UI, // 6B0 + arm690,arm_UI,arm692,arm_UI,arm694,arm_UI,arm696,arm_UI, // 6B8 + arm6C0,arm_UI,arm6C2,arm_UI,arm6C4,arm_UI,arm6C6,arm_UI, // 6C0 + arm6C0,arm_UI,arm6C2,arm_UI,arm6C4,arm_UI,arm6C6,arm_UI, // 6C8 + arm6D0,arm_UI,arm6D2,arm_UI,arm6D4,arm_UI,arm6D6,arm_UI, // 6D0 + arm6D0,arm_UI,arm6D2,arm_UI,arm6D4,arm_UI,arm6D6,arm_UI, // 6D8 + arm6C0,arm_UI,arm6C2,arm_UI,arm6C4,arm_UI,arm6C6,arm_UI, // 6E0 + arm6C0,arm_UI,arm6C2,arm_UI,arm6C4,arm_UI,arm6C6,arm_UI, // 6E8 + arm6D0,arm_UI,arm6D2,arm_UI,arm6D4,arm_UI,arm6D6,arm_UI, // 6F0 + arm6D0,arm_UI,arm6D2,arm_UI,arm6D4,arm_UI,arm6D6,arm_UI, // 6F8 + + arm700,arm_UI,arm702,arm_UI,arm704,arm_UI,arm706,arm_UI, // 700 + arm700,arm_UI,arm702,arm_UI,arm704,arm_UI,arm706,arm_UI, // 708 + arm710,arm_UI,arm712,arm_UI,arm714,arm_UI,arm716,arm_UI, // 710 + arm710,arm_UI,arm712,arm_UI,arm714,arm_UI,arm716,arm_UI, // 718 + arm720,arm_UI,arm722,arm_UI,arm724,arm_UI,arm726,arm_UI, // 720 + arm720,arm_UI,arm722,arm_UI,arm724,arm_UI,arm726,arm_UI, // 728 + arm730,arm_UI,arm732,arm_UI,arm734,arm_UI,arm736,arm_UI, // 730 + arm730,arm_UI,arm732,arm_UI,arm734,arm_UI,arm736,arm_UI, // 738 + arm740,arm_UI,arm742,arm_UI,arm744,arm_UI,arm746,arm_UI, // 740 + arm740,arm_UI,arm742,arm_UI,arm744,arm_UI,arm746,arm_UI, // 748 + arm750,arm_UI,arm752,arm_UI,arm754,arm_UI,arm756,arm_UI, // 750 + arm750,arm_UI,arm752,arm_UI,arm754,arm_UI,arm756,arm_UI, // 758 + arm760,arm_UI,arm762,arm_UI,arm764,arm_UI,arm766,arm_UI, // 760 + arm760,arm_UI,arm762,arm_UI,arm764,arm_UI,arm766,arm_UI, // 768 + arm770,arm_UI,arm772,arm_UI,arm774,arm_UI,arm776,arm_UI, // 770 + arm770,arm_UI,arm772,arm_UI,arm774,arm_UI,arm776,arm_UI, // 778 + arm780,arm_UI,arm782,arm_UI,arm784,arm_UI,arm786,arm_UI, // 780 + arm780,arm_UI,arm782,arm_UI,arm784,arm_UI,arm786,arm_UI, // 788 + arm790,arm_UI,arm792,arm_UI,arm794,arm_UI,arm796,arm_UI, // 790 + arm790,arm_UI,arm792,arm_UI,arm794,arm_UI,arm796,arm_UI, // 798 + arm7A0,arm_UI,arm7A2,arm_UI,arm7A4,arm_UI,arm7A6,arm_UI, // 7A0 + arm7A0,arm_UI,arm7A2,arm_UI,arm7A4,arm_UI,arm7A6,arm_UI, // 7A8 + arm7B0,arm_UI,arm7B2,arm_UI,arm7B4,arm_UI,arm7B6,arm_UI, // 7B0 + arm7B0,arm_UI,arm7B2,arm_UI,arm7B4,arm_UI,arm7B6,arm_UI, // 7B8 + arm7C0,arm_UI,arm7C2,arm_UI,arm7C4,arm_UI,arm7C6,arm_UI, // 7C0 + arm7C0,arm_UI,arm7C2,arm_UI,arm7C4,arm_UI,arm7C6,arm_UI, // 7C8 + arm7D0,arm_UI,arm7D2,arm_UI,arm7D4,arm_UI,arm7D6,arm_UI, // 7D0 + arm7D0,arm_UI,arm7D2,arm_UI,arm7D4,arm_UI,arm7D6,arm_UI, // 7D8 + arm7E0,arm_UI,arm7E2,arm_UI,arm7E4,arm_UI,arm7E6,arm_UI, // 7E0 + arm7E0,arm_UI,arm7E2,arm_UI,arm7E4,arm_UI,arm7E6,arm_UI, // 7E8 + arm7F0,arm_UI,arm7F2,arm_UI,arm7F4,arm_UI,arm7F6,arm_UI, // 7F0 + arm7F0,arm_UI,arm7F2,arm_UI,arm7F4,arm_UI,arm7F6,arm_BP, // 7F8 + + REP16(arm800),REP16(arm810),REP16(arm820),REP16(arm830), // 800 + REP16(arm840),REP16(arm850),REP16(arm860),REP16(arm870), // 840 + REP16(arm880),REP16(arm890),REP16(arm8A0),REP16(arm8B0), // 880 + REP16(arm8C0),REP16(arm8D0),REP16(arm8E0),REP16(arm8F0), // 8C0 + REP16(arm900),REP16(arm910),REP16(arm920),REP16(arm930), // 900 + REP16(arm940),REP16(arm950),REP16(arm960),REP16(arm970), // 940 + REP16(arm980),REP16(arm990),REP16(arm9A0),REP16(arm9B0), // 980 + REP16(arm9C0),REP16(arm9D0),REP16(arm9E0),REP16(arm9F0), // 9C0 + + REP256(armA00), // A00 + REP256(armB00), // B00 + REP256(arm_UI), // C00 + REP256(arm_UI), // D00 + + arm_UI,armE01,arm_UI,armE01,arm_UI,armE01,arm_UI,armE01, // E00 + arm_UI,armE01,arm_UI,armE01,arm_UI,armE01,arm_UI,armE01, // E08 + arm_UI,armE01,arm_UI,armE01,arm_UI,armE01,arm_UI,armE01, // E10 + arm_UI,armE01,arm_UI,armE01,arm_UI,armE01,arm_UI,armE01, // E18 + REP16(arm_UI), // E20 + REP16(arm_UI), // E30 + REP16(arm_UI),REP16(arm_UI),REP16(arm_UI),REP16(arm_UI), // E40 + REP16(arm_UI),REP16(arm_UI),REP16(arm_UI),REP16(arm_UI), // E80 + REP16(arm_UI),REP16(arm_UI),REP16(arm_UI),REP16(arm_UI), // EC0 + + REP256(armF00), // F00 +}; + +// Wrapper routine (execution loop) /////////////////////////////////////// + +int armExecute(GBASystem *gba) +{ + do { + if ((gba->armNextPC & 0x0803FFFF) == 0x08020000) + gba->busPrefetchCount = 0x100; + + u32 opcode = gba->cpuPrefetch[0]; + gba->cpuPrefetch[0] = gba->cpuPrefetch[1]; + + gba->busPrefetch = false; + if (gba->busPrefetchCount & 0xFFFFFE00) + gba->busPrefetchCount = 0x100 | (gba->busPrefetchCount & 0xFF); + + gba->clockTicks = 0; + int oldArmNextPC = gba->armNextPC; + + gba->armNextPC = gba->reg[15].I; + gba->reg[15].I += 4; + ARM_PREFETCH_NEXT; + + int cond = opcode >> 28; + bool cond_res = true; + if (UNLIKELY(cond != 0x0E)) { // most opcodes are AL (always) + switch(cond) { + case 0x00: // EQ + cond_res = gba->Z_FLAG; + break; + case 0x01: // NE + cond_res = !gba->Z_FLAG; + break; + case 0x02: // CS + cond_res = gba->C_FLAG; + break; + case 0x03: // CC + cond_res = !gba->C_FLAG; + break; + case 0x04: // MI + cond_res = gba->N_FLAG; + break; + case 0x05: // PL + cond_res = !gba->N_FLAG; + break; + case 0x06: // VS + cond_res = gba->V_FLAG; + break; + case 0x07: // VC + cond_res = !gba->V_FLAG; + break; + case 0x08: // HI + cond_res = gba->C_FLAG && !gba->Z_FLAG; + break; + case 0x09: // LS + cond_res = !gba->C_FLAG || gba->Z_FLAG; + break; + case 0x0A: // GE + cond_res = gba->N_FLAG == gba->V_FLAG; + break; + case 0x0B: // LT + cond_res = gba->N_FLAG != gba->V_FLAG; + break; + case 0x0C: // GT + cond_res = !gba->Z_FLAG &&(gba->N_FLAG == gba->V_FLAG); + break; + case 0x0D: // LE + cond_res = gba->Z_FLAG || (gba->N_FLAG != gba->V_FLAG); + break; + case 0x0E: // AL (impossible, checked above) + cond_res = true; + break; + case 0x0F: + default: + // ??? + cond_res = false; + break; + } + } + + if (cond_res) + (*armInsnTable[((opcode>>16)&0xFF0) | ((opcode>>4)&0x0F)])(gba, opcode); + if (gba->clockTicks < 0) + return 0; + if (gba->clockTicks == 0) + gba->clockTicks = 1 + codeTicksAccessSeq32(gba, oldArmNextPC); + gba->cpuTotalTicks += gba->clockTicks; + + } while (gba->cpuTotalTickscpuNextEvent && gba->armState && !gba->holdState && !gba->SWITicks); + + return 1; +} diff --git a/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/gba/GBA-thumb.cpp b/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/gba/GBA-thumb.cpp new file mode 100644 index 000000000..73a88372c --- /dev/null +++ b/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/gba/GBA-thumb.cpp @@ -0,0 +1,1623 @@ +#include +#include +#include +#include +#include + +#include "GBA.h" +#include "GBAcpu.h" +#include "GBAinline.h" +#include "Globals.h" + +#include "Sound.h" +#include "bios.h" +#include "../common/Types.h" + +#ifdef _MSC_VER +#define snprintf _snprintf +#endif + +/////////////////////////////////////////////////////////////////////////// + +static INSN_REGPARM void thumbUnknownInsn(GBASystem *gba, u32 opcode) +{ + CPUUndefinedException(gba); +} + +// Common macros ////////////////////////////////////////////////////////// + +#define THUMB_CONSOLE_OUTPUT(a,b) +#define UPDATE_OLDREG + +#define NEG(i) ((i) >> 31) +#define POS(i) ((~(i)) >> 31) + +// C core +#ifndef ADDCARRY + #define ADDCARRY(a, b, c) \ + gba->C_FLAG = ((NEG(a) & NEG(b)) |\ + (NEG(a) & POS(c)) |\ + (NEG(b) & POS(c))) ? true : false; +#endif +#ifndef ADDOVERFLOW + #define ADDOVERFLOW(a, b, c) \ + gba->V_FLAG = ((NEG(a) & NEG(b) & POS(c)) |\ + (POS(a) & POS(b) & NEG(c))) ? true : false; +#endif +#ifndef SUBCARRY + #define SUBCARRY(a, b, c) \ + gba->C_FLAG = ((NEG(a) & POS(b)) |\ + (NEG(a) & POS(c)) |\ + (POS(b) & POS(c))) ? true : false; +#endif +#ifndef SUBOVERFLOW + #define SUBOVERFLOW(a, b, c)\ + gba->V_FLAG = ((NEG(a) & POS(b) & POS(c)) |\ + (POS(a) & NEG(b) & NEG(c))) ? true : false; +#endif +#ifndef ADD_RD_RS_RN + #define ADD_RD_RS_RN(N) \ + {\ + u32 lhs = gba->reg[source].I;\ + u32 rhs = gba->reg[N].I;\ + u32 res = lhs + rhs;\ + gba->reg[dest].I = res;\ + gba->Z_FLAG = (res == 0) ? true : false;\ + gba->N_FLAG = NEG(res) ? true : false;\ + ADDCARRY(lhs, rhs, res);\ + ADDOVERFLOW(lhs, rhs, res);\ + } +#endif +#ifndef ADD_RD_RS_O3 + #define ADD_RD_RS_O3(N) \ + {\ + u32 lhs = gba->reg[source].I;\ + u32 rhs = N;\ + u32 res = lhs + rhs;\ + gba->reg[dest].I = res;\ + gba->Z_FLAG = (res == 0) ? true : false;\ + gba->N_FLAG = NEG(res) ? true : false;\ + ADDCARRY(lhs, rhs, res);\ + ADDOVERFLOW(lhs, rhs, res);\ + } +#endif +#ifndef ADD_RD_RS_O3_0 +# define ADD_RD_RS_O3_0 ADD_RD_RS_O3 +#endif +#ifndef ADD_RN_O8 + #define ADD_RN_O8(d) \ + {\ + u32 lhs = gba->reg[(d)].I;\ + u32 rhs = (opcode & 255);\ + u32 res = lhs + rhs;\ + gba->reg[(d)].I = res;\ + gba->Z_FLAG = (res == 0) ? true : false;\ + gba->N_FLAG = NEG(res) ? true : false;\ + ADDCARRY(lhs, rhs, res);\ + ADDOVERFLOW(lhs, rhs, res);\ + } +#endif +#ifndef CMN_RD_RS + #define CMN_RD_RS \ + {\ + u32 lhs = gba->reg[dest].I;\ + u32 rhs = value;\ + u32 res = lhs + rhs;\ + gba->Z_FLAG = (res == 0) ? true : false;\ + gba->N_FLAG = NEG(res) ? true : false;\ + ADDCARRY(lhs, rhs, res);\ + ADDOVERFLOW(lhs, rhs, res);\ + } +#endif +#ifndef ADC_RD_RS + #define ADC_RD_RS \ + {\ + u32 lhs = gba->reg[dest].I;\ + u32 rhs = value;\ + u32 res = lhs + rhs + (u32)gba->C_FLAG;\ + gba->reg[dest].I = res;\ + gba->Z_FLAG = (res == 0) ? true : false;\ + gba->N_FLAG = NEG(res) ? true : false;\ + ADDCARRY(lhs, rhs, res);\ + ADDOVERFLOW(lhs, rhs, res);\ + } +#endif +#ifndef SUB_RD_RS_RN + #define SUB_RD_RS_RN(N) \ + {\ + u32 lhs = gba->reg[source].I;\ + u32 rhs = gba->reg[N].I;\ + u32 res = lhs - rhs;\ + gba->reg[dest].I = res;\ + gba->Z_FLAG = (res == 0) ? true : false;\ + gba->N_FLAG = NEG(res) ? true : false;\ + SUBCARRY(lhs, rhs, res);\ + SUBOVERFLOW(lhs, rhs, res);\ + } +#endif +#ifndef SUB_RD_RS_O3 + #define SUB_RD_RS_O3(N) \ + {\ + u32 lhs = gba->reg[source].I;\ + u32 rhs = N;\ + u32 res = lhs - rhs;\ + gba->reg[dest].I = res;\ + gba->Z_FLAG = (res == 0) ? true : false;\ + gba->N_FLAG = NEG(res) ? true : false;\ + SUBCARRY(lhs, rhs, res);\ + SUBOVERFLOW(lhs, rhs, res);\ + } +#endif +#ifndef SUB_RD_RS_O3_0 +# define SUB_RD_RS_O3_0 SUB_RD_RS_O3 +#endif +#ifndef SUB_RN_O8 + #define SUB_RN_O8(d) \ + {\ + u32 lhs = gba->reg[(d)].I;\ + u32 rhs = (opcode & 255);\ + u32 res = lhs - rhs;\ + gba->reg[(d)].I = res;\ + gba->Z_FLAG = (res == 0) ? true : false;\ + gba->N_FLAG = NEG(res) ? true : false;\ + SUBCARRY(lhs, rhs, res);\ + SUBOVERFLOW(lhs, rhs, res);\ + } +#endif +#ifndef MOV_RN_O8 + #define MOV_RN_O8(d) \ + {\ + gba->reg[d].I = opcode & 255;\ + gba->N_FLAG = false;\ + gba->Z_FLAG = (gba->reg[d].I ? false : true);\ + } +#endif +#ifndef CMP_RN_O8 + #define CMP_RN_O8(d) \ + {\ + u32 lhs = gba->reg[(d)].I;\ + u32 rhs = (opcode & 255);\ + u32 res = lhs - rhs;\ + gba->Z_FLAG = (res == 0) ? true : false;\ + gba->N_FLAG = NEG(res) ? true : false;\ + SUBCARRY(lhs, rhs, res);\ + SUBOVERFLOW(lhs, rhs, res);\ + } +#endif +#ifndef SBC_RD_RS + #define SBC_RD_RS \ + {\ + u32 lhs = gba->reg[dest].I;\ + u32 rhs = value;\ + u32 res = lhs - rhs - !((u32)gba->C_FLAG);\ + gba->reg[dest].I = res;\ + gba->Z_FLAG = (res == 0) ? true : false;\ + gba->N_FLAG = NEG(res) ? true : false;\ + SUBCARRY(lhs, rhs, res);\ + SUBOVERFLOW(lhs, rhs, res);\ + } +#endif +#ifndef LSL_RD_RM_I5 + #define LSL_RD_RM_I5 \ + {\ + gba->C_FLAG = (gba->reg[source].I >> (32 - shift)) & 1 ? true : false;\ + value = gba->reg[source].I << shift;\ + } +#endif +#ifndef LSL_RD_RS + #define LSL_RD_RS \ + {\ + gba->C_FLAG = (gba->reg[dest].I >> (32 - value)) & 1 ? true : false;\ + value = gba->reg[dest].I << value;\ + } +#endif +#ifndef LSR_RD_RM_I5 + #define LSR_RD_RM_I5 \ + {\ + gba->C_FLAG = (gba->reg[source].I >> (shift - 1)) & 1 ? true : false;\ + value = gba->reg[source].I >> shift;\ + } +#endif +#ifndef LSR_RD_RS + #define LSR_RD_RS \ + {\ + gba->C_FLAG = (gba->reg[dest].I >> (value - 1)) & 1 ? true : false;\ + value = gba->reg[dest].I >> value;\ + } +#endif +#ifndef ASR_RD_RM_I5 + #define ASR_RD_RM_I5 \ + {\ + gba->C_FLAG = ((s32)gba->reg[source].I >> (int)(shift - 1)) & 1 ? true : false;\ + value = (s32)gba->reg[source].I >> (int)shift;\ + } +#endif +#ifndef ASR_RD_RS + #define ASR_RD_RS \ + {\ + gba->C_FLAG = ((s32)gba->reg[dest].I >> (int)(value - 1)) & 1 ? true : false;\ + value = (s32)gba->reg[dest].I >> (int)value;\ + } +#endif +#ifndef ROR_RD_RS + #define ROR_RD_RS \ + {\ + gba->C_FLAG = (gba->reg[dest].I >> (value - 1)) & 1 ? true : false;\ + value = ((gba->reg[dest].I << (32 - value)) |\ + (gba->reg[dest].I >> value));\ + } +#endif +#ifndef NEG_RD_RS + #define NEG_RD_RS \ + {\ + u32 lhs = gba->reg[source].I;\ + u32 rhs = 0;\ + u32 res = rhs - lhs;\ + gba->reg[dest].I = res;\ + gba->Z_FLAG = (res == 0) ? true : false;\ + gba->N_FLAG = NEG(res) ? true : false;\ + SUBCARRY(rhs, lhs, res);\ + SUBOVERFLOW(rhs, lhs, res);\ + } +#endif +#ifndef CMP_RD_RS + #define CMP_RD_RS \ + {\ + u32 lhs = gba->reg[dest].I;\ + u32 rhs = value;\ + u32 res = lhs - rhs;\ + gba->Z_FLAG = (res == 0) ? true : false;\ + gba->N_FLAG = NEG(res) ? true : false;\ + SUBCARRY(lhs, rhs, res);\ + SUBOVERFLOW(lhs, rhs, res);\ + } +#endif +#ifndef IMM5_INSN + #define IMM5_INSN(OP,N) \ + int dest = opcode & 0x07;\ + int source = (opcode >> 3) & 0x07;\ + u32 value;\ + OP(N);\ + gba->reg[dest].I = value;\ + gba->N_FLAG = (value & 0x80000000 ? true : false);\ + gba->Z_FLAG = (value ? false : true); + #define IMM5_INSN_0(OP) \ + int dest = opcode & 0x07;\ + int source = (opcode >> 3) & 0x07;\ + u32 value;\ + OP;\ + gba->reg[dest].I = value;\ + gba->N_FLAG = (value & 0x80000000 ? true : false);\ + gba->Z_FLAG = (value ? false : true); + #define IMM5_LSL(N) \ + int shift = N;\ + LSL_RD_RM_I5; + #define IMM5_LSL_0 \ + value = gba->reg[source].I; + #define IMM5_LSR(N) \ + int shift = N;\ + LSR_RD_RM_I5; + #define IMM5_LSR_0 \ + gba->C_FLAG = gba->reg[source].I & 0x80000000 ? true : false;\ + value = 0; + #define IMM5_ASR(N) \ + int shift = N;\ + ASR_RD_RM_I5; + #define IMM5_ASR_0 \ + if(gba->reg[source].I & 0x80000000) {\ + value = 0xFFFFFFFF;\ + gba->C_FLAG = true;\ + } else {\ + value = 0;\ + gba->C_FLAG = false;\ + } +#endif +#ifndef THREEARG_INSN + #define THREEARG_INSN(OP,N) \ + int dest = opcode & 0x07; \ + int source = (opcode >> 3) & 0x07; \ + OP(N); +#endif + +// Shift instructions ///////////////////////////////////////////////////// + +#define DEFINE_IMM5_INSN(OP,BASE) \ + static INSN_REGPARM void thumb##BASE##_00(GBASystem *gba, u32 opcode) { IMM5_INSN_0(OP##_0); } \ + static INSN_REGPARM void thumb##BASE##_01(GBASystem *gba, u32 opcode) { IMM5_INSN(OP, 1); } \ + static INSN_REGPARM void thumb##BASE##_02(GBASystem *gba, u32 opcode) { IMM5_INSN(OP, 2); } \ + static INSN_REGPARM void thumb##BASE##_03(GBASystem *gba, u32 opcode) { IMM5_INSN(OP, 3); } \ + static INSN_REGPARM void thumb##BASE##_04(GBASystem *gba, u32 opcode) { IMM5_INSN(OP, 4); } \ + static INSN_REGPARM void thumb##BASE##_05(GBASystem *gba, u32 opcode) { IMM5_INSN(OP, 5); } \ + static INSN_REGPARM void thumb##BASE##_06(GBASystem *gba, u32 opcode) { IMM5_INSN(OP, 6); } \ + static INSN_REGPARM void thumb##BASE##_07(GBASystem *gba, u32 opcode) { IMM5_INSN(OP, 7); } \ + static INSN_REGPARM void thumb##BASE##_08(GBASystem *gba, u32 opcode) { IMM5_INSN(OP, 8); } \ + static INSN_REGPARM void thumb##BASE##_09(GBASystem *gba, u32 opcode) { IMM5_INSN(OP, 9); } \ + static INSN_REGPARM void thumb##BASE##_0A(GBASystem *gba, u32 opcode) { IMM5_INSN(OP,10); } \ + static INSN_REGPARM void thumb##BASE##_0B(GBASystem *gba, u32 opcode) { IMM5_INSN(OP,11); } \ + static INSN_REGPARM void thumb##BASE##_0C(GBASystem *gba, u32 opcode) { IMM5_INSN(OP,12); } \ + static INSN_REGPARM void thumb##BASE##_0D(GBASystem *gba, u32 opcode) { IMM5_INSN(OP,13); } \ + static INSN_REGPARM void thumb##BASE##_0E(GBASystem *gba, u32 opcode) { IMM5_INSN(OP,14); } \ + static INSN_REGPARM void thumb##BASE##_0F(GBASystem *gba, u32 opcode) { IMM5_INSN(OP,15); } \ + static INSN_REGPARM void thumb##BASE##_10(GBASystem *gba, u32 opcode) { IMM5_INSN(OP,16); } \ + static INSN_REGPARM void thumb##BASE##_11(GBASystem *gba, u32 opcode) { IMM5_INSN(OP,17); } \ + static INSN_REGPARM void thumb##BASE##_12(GBASystem *gba, u32 opcode) { IMM5_INSN(OP,18); } \ + static INSN_REGPARM void thumb##BASE##_13(GBASystem *gba, u32 opcode) { IMM5_INSN(OP,19); } \ + static INSN_REGPARM void thumb##BASE##_14(GBASystem *gba, u32 opcode) { IMM5_INSN(OP,20); } \ + static INSN_REGPARM void thumb##BASE##_15(GBASystem *gba, u32 opcode) { IMM5_INSN(OP,21); } \ + static INSN_REGPARM void thumb##BASE##_16(GBASystem *gba, u32 opcode) { IMM5_INSN(OP,22); } \ + static INSN_REGPARM void thumb##BASE##_17(GBASystem *gba, u32 opcode) { IMM5_INSN(OP,23); } \ + static INSN_REGPARM void thumb##BASE##_18(GBASystem *gba, u32 opcode) { IMM5_INSN(OP,24); } \ + static INSN_REGPARM void thumb##BASE##_19(GBASystem *gba, u32 opcode) { IMM5_INSN(OP,25); } \ + static INSN_REGPARM void thumb##BASE##_1A(GBASystem *gba, u32 opcode) { IMM5_INSN(OP,26); } \ + static INSN_REGPARM void thumb##BASE##_1B(GBASystem *gba, u32 opcode) { IMM5_INSN(OP,27); } \ + static INSN_REGPARM void thumb##BASE##_1C(GBASystem *gba, u32 opcode) { IMM5_INSN(OP,28); } \ + static INSN_REGPARM void thumb##BASE##_1D(GBASystem *gba, u32 opcode) { IMM5_INSN(OP,29); } \ + static INSN_REGPARM void thumb##BASE##_1E(GBASystem *gba, u32 opcode) { IMM5_INSN(OP,30); } \ + static INSN_REGPARM void thumb##BASE##_1F(GBASystem *gba, u32 opcode) { IMM5_INSN(OP,31); } + +// LSL Rd, Rm, #Imm 5 +DEFINE_IMM5_INSN(IMM5_LSL,00) +// LSR Rd, Rm, #Imm 5 +DEFINE_IMM5_INSN(IMM5_LSR,08) +// ASR Rd, Rm, #Imm 5 +DEFINE_IMM5_INSN(IMM5_ASR,10) + +// 3-argument ADD/SUB ///////////////////////////////////////////////////// + +#define DEFINE_REG3_INSN(OP,BASE) \ + static INSN_REGPARM void thumb##BASE##_0(GBASystem *gba, u32 opcode) { THREEARG_INSN(OP,0); } \ + static INSN_REGPARM void thumb##BASE##_1(GBASystem *gba, u32 opcode) { THREEARG_INSN(OP,1); } \ + static INSN_REGPARM void thumb##BASE##_2(GBASystem *gba, u32 opcode) { THREEARG_INSN(OP,2); } \ + static INSN_REGPARM void thumb##BASE##_3(GBASystem *gba, u32 opcode) { THREEARG_INSN(OP,3); } \ + static INSN_REGPARM void thumb##BASE##_4(GBASystem *gba, u32 opcode) { THREEARG_INSN(OP,4); } \ + static INSN_REGPARM void thumb##BASE##_5(GBASystem *gba, u32 opcode) { THREEARG_INSN(OP,5); } \ + static INSN_REGPARM void thumb##BASE##_6(GBASystem *gba, u32 opcode) { THREEARG_INSN(OP,6); } \ + static INSN_REGPARM void thumb##BASE##_7(GBASystem *gba, u32 opcode) { THREEARG_INSN(OP,7); } + +#define DEFINE_IMM3_INSN(OP,BASE) \ + static INSN_REGPARM void thumb##BASE##_0(GBASystem *gba, u32 opcode) { THREEARG_INSN(OP##_0,0); } \ + static INSN_REGPARM void thumb##BASE##_1(GBASystem *gba, u32 opcode) { THREEARG_INSN(OP,1); } \ + static INSN_REGPARM void thumb##BASE##_2(GBASystem *gba, u32 opcode) { THREEARG_INSN(OP,2); } \ + static INSN_REGPARM void thumb##BASE##_3(GBASystem *gba, u32 opcode) { THREEARG_INSN(OP,3); } \ + static INSN_REGPARM void thumb##BASE##_4(GBASystem *gba, u32 opcode) { THREEARG_INSN(OP,4); } \ + static INSN_REGPARM void thumb##BASE##_5(GBASystem *gba, u32 opcode) { THREEARG_INSN(OP,5); } \ + static INSN_REGPARM void thumb##BASE##_6(GBASystem *gba, u32 opcode) { THREEARG_INSN(OP,6); } \ + static INSN_REGPARM void thumb##BASE##_7(GBASystem *gba, u32 opcode) { THREEARG_INSN(OP,7); } + +// ADD Rd, Rs, Rn +DEFINE_REG3_INSN(ADD_RD_RS_RN,18) +// SUB Rd, Rs, Rn +DEFINE_REG3_INSN(SUB_RD_RS_RN,1A) +// ADD Rd, Rs, #Offset3 +DEFINE_IMM3_INSN(ADD_RD_RS_O3,1C) +// SUB Rd, Rs, #Offset3 +DEFINE_IMM3_INSN(SUB_RD_RS_O3,1E) + +// MOV/CMP/ADD/SUB immediate ////////////////////////////////////////////// + +// MOV R0, #Offset8 +static INSN_REGPARM void thumb20(GBASystem *gba, u32 opcode) { MOV_RN_O8(0); } +// MOV R1, #Offset8 +static INSN_REGPARM void thumb21(GBASystem *gba, u32 opcode) { MOV_RN_O8(1); } +// MOV R2, #Offset8 +static INSN_REGPARM void thumb22(GBASystem *gba, u32 opcode) { MOV_RN_O8(2); } +// MOV R3, #Offset8 +static INSN_REGPARM void thumb23(GBASystem *gba, u32 opcode) { MOV_RN_O8(3); } +// MOV R4, #Offset8 +static INSN_REGPARM void thumb24(GBASystem *gba, u32 opcode) { MOV_RN_O8(4); } +// MOV R5, #Offset8 +static INSN_REGPARM void thumb25(GBASystem *gba, u32 opcode) { MOV_RN_O8(5); } +// MOV R6, #Offset8 +static INSN_REGPARM void thumb26(GBASystem *gba, u32 opcode) { MOV_RN_O8(6); } +// MOV R7, #Offset8 +static INSN_REGPARM void thumb27(GBASystem *gba, u32 opcode) { MOV_RN_O8(7); } + +// CMP R0, #Offset8 +static INSN_REGPARM void thumb28(GBASystem *gba, u32 opcode) { CMP_RN_O8(0); } +// CMP R1, #Offset8 +static INSN_REGPARM void thumb29(GBASystem *gba, u32 opcode) { CMP_RN_O8(1); } +// CMP R2, #Offset8 +static INSN_REGPARM void thumb2A(GBASystem *gba, u32 opcode) { CMP_RN_O8(2); } +// CMP R3, #Offset8 +static INSN_REGPARM void thumb2B(GBASystem *gba, u32 opcode) { CMP_RN_O8(3); } +// CMP R4, #Offset8 +static INSN_REGPARM void thumb2C(GBASystem *gba, u32 opcode) { CMP_RN_O8(4); } +// CMP R5, #Offset8 +static INSN_REGPARM void thumb2D(GBASystem *gba, u32 opcode) { CMP_RN_O8(5); } +// CMP R6, #Offset8 +static INSN_REGPARM void thumb2E(GBASystem *gba, u32 opcode) { CMP_RN_O8(6); } +// CMP R7, #Offset8 +static INSN_REGPARM void thumb2F(GBASystem *gba, u32 opcode) { CMP_RN_O8(7); } + +// ADD R0,#Offset8 +static INSN_REGPARM void thumb30(GBASystem *gba, u32 opcode) { ADD_RN_O8(0); } +// ADD R1,#Offset8 +static INSN_REGPARM void thumb31(GBASystem *gba, u32 opcode) { ADD_RN_O8(1); } +// ADD R2,#Offset8 +static INSN_REGPARM void thumb32(GBASystem *gba, u32 opcode) { ADD_RN_O8(2); } +// ADD R3,#Offset8 +static INSN_REGPARM void thumb33(GBASystem *gba, u32 opcode) { ADD_RN_O8(3); } +// ADD R4,#Offset8 +static INSN_REGPARM void thumb34(GBASystem *gba, u32 opcode) { ADD_RN_O8(4); } +// ADD R5,#Offset8 +static INSN_REGPARM void thumb35(GBASystem *gba, u32 opcode) { ADD_RN_O8(5); } +// ADD R6,#Offset8 +static INSN_REGPARM void thumb36(GBASystem *gba, u32 opcode) { ADD_RN_O8(6); } +// ADD R7,#Offset8 +static INSN_REGPARM void thumb37(GBASystem *gba, u32 opcode) { ADD_RN_O8(7); } + +// SUB R0,#Offset8 +static INSN_REGPARM void thumb38(GBASystem *gba, u32 opcode) { SUB_RN_O8(0); } +// SUB R1,#Offset8 +static INSN_REGPARM void thumb39(GBASystem *gba, u32 opcode) { SUB_RN_O8(1); } +// SUB R2,#Offset8 +static INSN_REGPARM void thumb3A(GBASystem *gba, u32 opcode) { SUB_RN_O8(2); } +// SUB R3,#Offset8 +static INSN_REGPARM void thumb3B(GBASystem *gba, u32 opcode) { SUB_RN_O8(3); } +// SUB R4,#Offset8 +static INSN_REGPARM void thumb3C(GBASystem *gba, u32 opcode) { SUB_RN_O8(4); } +// SUB R5,#Offset8 +static INSN_REGPARM void thumb3D(GBASystem *gba, u32 opcode) { SUB_RN_O8(5); } +// SUB R6,#Offset8 +static INSN_REGPARM void thumb3E(GBASystem *gba, u32 opcode) { SUB_RN_O8(6); } +// SUB R7,#Offset8 +static INSN_REGPARM void thumb3F(GBASystem *gba, u32 opcode) { SUB_RN_O8(7); } + +// ALU operations ///////////////////////////////////////////////////////// + +// AND Rd, Rs +static INSN_REGPARM void thumb40_0(GBASystem *gba, u32 opcode) +{ + int dest = opcode & 7; + gba->reg[dest].I &= gba->reg[(opcode >> 3)&7].I; + gba->N_FLAG = gba->reg[dest].I & 0x80000000 ? true : false; + gba->Z_FLAG = gba->reg[dest].I ? false : true; + THUMB_CONSOLE_OUTPUT(NULL, reg[2].I); +} + +// EOR Rd, Rs +static INSN_REGPARM void thumb40_1(GBASystem *gba, u32 opcode) +{ + int dest = opcode & 7; + gba->reg[dest].I ^= gba->reg[(opcode >> 3)&7].I; + gba->N_FLAG = gba->reg[dest].I & 0x80000000 ? true : false; + gba->Z_FLAG = gba->reg[dest].I ? false : true; +} + +// LSL Rd, Rs +static INSN_REGPARM void thumb40_2(GBASystem *gba, u32 opcode) +{ + int dest = opcode & 7; + u32 value = gba->reg[(opcode >> 3)&7].B.B0; + if(value) { + if(value == 32) { + value = 0; + gba->C_FLAG = (gba->reg[dest].I & 1 ? true : false); + } else if(value < 32) { + LSL_RD_RS; + } else { + value = 0; + gba->C_FLAG = false; + } + gba->reg[dest].I = value; + } + gba->N_FLAG = gba->reg[dest].I & 0x80000000 ? true : false; + gba->Z_FLAG = gba->reg[dest].I ? false : true; + gba->clockTicks = codeTicksAccess16(gba, gba->armNextPC)+2; +} + +// LSR Rd, Rs +static INSN_REGPARM void thumb40_3(GBASystem *gba, u32 opcode) +{ + int dest = opcode & 7; + u32 value = gba->reg[(opcode >> 3)&7].B.B0; + if(value) { + if(value == 32) { + value = 0; + gba->C_FLAG = (gba->reg[dest].I & 0x80000000 ? true : false); + } else if(value < 32) { + LSR_RD_RS; + } else { + value = 0; + gba->C_FLAG = false; + } + gba->reg[dest].I = value; + } + gba->N_FLAG = gba->reg[dest].I & 0x80000000 ? true : false; + gba->Z_FLAG = gba->reg[dest].I ? false : true; + gba->clockTicks = codeTicksAccess16(gba, gba->armNextPC)+2; +} + +// ASR Rd, Rs +static INSN_REGPARM void thumb41_0(GBASystem *gba, u32 opcode) +{ + int dest = opcode & 7; + u32 value = gba->reg[(opcode >> 3)&7].B.B0; + if(value) { + if(value < 32) { + ASR_RD_RS; + gba->reg[dest].I = value; + } else { + if(gba->reg[dest].I & 0x80000000){ + gba->reg[dest].I = 0xFFFFFFFF; + gba->C_FLAG = true; + } else { + gba->reg[dest].I = 0x00000000; + gba->C_FLAG = false; + } + } + } + gba->N_FLAG = gba->reg[dest].I & 0x80000000 ? true : false; + gba->Z_FLAG = gba->reg[dest].I ? false : true; + gba->clockTicks = codeTicksAccess16(gba, gba->armNextPC)+2; +} + +// ADC Rd, Rs +static INSN_REGPARM void thumb41_1(GBASystem *gba, u32 opcode) +{ + int dest = opcode & 0x07; + u32 value = gba->reg[(opcode >> 3)&7].I; + ADC_RD_RS; +} + +// SBC Rd, Rs +static INSN_REGPARM void thumb41_2(GBASystem *gba, u32 opcode) +{ + int dest = opcode & 0x07; + u32 value = gba->reg[(opcode >> 3)&7].I; + SBC_RD_RS; +} + +// ROR Rd, Rs +static INSN_REGPARM void thumb41_3(GBASystem *gba, u32 opcode) +{ + int dest = opcode & 7; + u32 value = gba->reg[(opcode >> 3)&7].B.B0; + + if(value) { + value = value & 0x1f; + if(value == 0) { + gba->C_FLAG = (gba->reg[dest].I & 0x80000000 ? true : false); + } else { + ROR_RD_RS; + gba->reg[dest].I = value; + } + } + gba->clockTicks = codeTicksAccess16(gba, gba->armNextPC)+2; + gba->N_FLAG = gba->reg[dest].I & 0x80000000 ? true : false; + gba->Z_FLAG = gba->reg[dest].I ? false : true; +} + +// TST Rd, Rs +static INSN_REGPARM void thumb42_0(GBASystem *gba, u32 opcode) +{ + u32 value = gba->reg[opcode & 7].I & gba->reg[(opcode >> 3) & 7].I; + gba->N_FLAG = value & 0x80000000 ? true : false; + gba->Z_FLAG = value ? false : true; +} + +// NEG Rd, Rs +static INSN_REGPARM void thumb42_1(GBASystem *gba, u32 opcode) +{ + int dest = opcode & 7; + int source = (opcode >> 3) & 7; + NEG_RD_RS; +} + +// CMP Rd, Rs +static INSN_REGPARM void thumb42_2(GBASystem *gba, u32 opcode) +{ + int dest = opcode & 7; + u32 value = gba->reg[(opcode >> 3)&7].I; + CMP_RD_RS; +} + +// CMN Rd, Rs +static INSN_REGPARM void thumb42_3(GBASystem *gba, u32 opcode) +{ + int dest = opcode & 7; + u32 value = gba->reg[(opcode >> 3)&7].I; + CMN_RD_RS; +} + +// ORR Rd, Rs +static INSN_REGPARM void thumb43_0(GBASystem *gba, u32 opcode) +{ + int dest = opcode & 7; + gba->reg[dest].I |= gba->reg[(opcode >> 3) & 7].I; + gba->Z_FLAG = gba->reg[dest].I ? false : true; + gba->N_FLAG = gba->reg[dest].I & 0x80000000 ? true : false; +} + +// MUL Rd, Rs +static INSN_REGPARM void thumb43_1(GBASystem *gba, u32 opcode) +{ + gba->clockTicks = 1; + int dest = opcode & 7; + u32 rm = gba->reg[dest].I; + gba->reg[dest].I = gba->reg[(opcode >> 3) & 7].I * rm; + if (((s32)rm) < 0) + rm = ~rm; + if ((rm & 0xFFFFFF00) == 0) + gba->clockTicks += 0; + else if ((rm & 0xFFFF0000) == 0) + gba->clockTicks += 1; + else if ((rm & 0xFF000000) == 0) + gba->clockTicks += 2; + else + gba->clockTicks += 3; + gba->busPrefetchCount = (gba->busPrefetchCount<clockTicks) | (0xFF>>(8-gba->clockTicks)); + gba->clockTicks += codeTicksAccess16(gba, gba->armNextPC) + 1; + gba->Z_FLAG = gba->reg[dest].I ? false : true; + gba->N_FLAG = gba->reg[dest].I & 0x80000000 ? true : false; +} + +// BIC Rd, Rs +static INSN_REGPARM void thumb43_2(GBASystem *gba, u32 opcode) +{ + int dest = opcode & 7; + gba->reg[dest].I &= (~gba->reg[(opcode >> 3) & 7].I); + gba->Z_FLAG = gba->reg[dest].I ? false : true; + gba->N_FLAG = gba->reg[dest].I & 0x80000000 ? true : false; +} + +// MVN Rd, Rs +static INSN_REGPARM void thumb43_3(GBASystem *gba, u32 opcode) +{ + int dest = opcode & 7; + gba->reg[dest].I = ~gba->reg[(opcode >> 3) & 7].I; + gba->Z_FLAG = gba->reg[dest].I ? false : true; + gba->N_FLAG = gba->reg[dest].I & 0x80000000 ? true : false; +} + +// High-register instructions and BX ////////////////////////////////////// + +// ADD Rd, Hs +static INSN_REGPARM void thumb44_1(GBASystem *gba, u32 opcode) +{ + gba->reg[opcode&7].I += gba->reg[((opcode>>3)&7)+8].I; +} + +// ADD Hd, Rs +static INSN_REGPARM void thumb44_2(GBASystem *gba, u32 opcode) +{ + gba->reg[(opcode&7)+8].I += gba->reg[(opcode>>3)&7].I; + if((opcode&7) == 7) { + gba->reg[15].I &= 0xFFFFFFFE; + gba->armNextPC = gba->reg[15].I; + gba->reg[15].I += 2; + THUMB_PREFETCH; + gba->clockTicks = codeTicksAccessSeq16(gba, gba->armNextPC)*2 + + codeTicksAccess16(gba, gba->armNextPC) + 3; + } +} + +// ADD Hd, Hs +static INSN_REGPARM void thumb44_3(GBASystem *gba, u32 opcode) +{ + gba->reg[(opcode&7)+8].I += gba->reg[((opcode>>3)&7)+8].I; + if((opcode&7) == 7) { + gba->reg[15].I &= 0xFFFFFFFE; + gba->armNextPC = gba->reg[15].I; + gba->reg[15].I += 2; + THUMB_PREFETCH; + gba->clockTicks = codeTicksAccessSeq16(gba, gba->armNextPC)*2 + + codeTicksAccess16(gba, gba->armNextPC) + 3; + } +} + +// CMP Rd, Hs +static INSN_REGPARM void thumb45_1(GBASystem *gba, u32 opcode) +{ + int dest = opcode & 7; + u32 value = gba->reg[((opcode>>3)&7)+8].I; + CMP_RD_RS; +} + +// CMP Hd, Rs +static INSN_REGPARM void thumb45_2(GBASystem *gba, u32 opcode) +{ + int dest = (opcode & 7) + 8; + u32 value = gba->reg[(opcode>>3)&7].I; + CMP_RD_RS; +} + +// CMP Hd, Hs +static INSN_REGPARM void thumb45_3(GBASystem *gba, u32 opcode) +{ + int dest = (opcode & 7) + 8; + u32 value = gba->reg[((opcode>>3)&7)+8].I; + CMP_RD_RS; +} + +// MOV Rd, Hs +static INSN_REGPARM void thumb46_1(GBASystem *gba, u32 opcode) +{ + gba->reg[opcode&7].I = gba->reg[((opcode>>3)&7)+8].I; +} + +// MOV Hd, Rs +static INSN_REGPARM void thumb46_2(GBASystem *gba, u32 opcode) +{ + gba->reg[(opcode&7)+8].I = gba->reg[(opcode>>3)&7].I; + if((opcode&7) == 7) { + UPDATE_OLDREG; + gba->reg[15].I &= 0xFFFFFFFE; + gba->armNextPC = gba->reg[15].I; + gba->reg[15].I += 2; + THUMB_PREFETCH; + gba->clockTicks = codeTicksAccessSeq16(gba, gba->armNextPC)*2 + + codeTicksAccess16(gba, gba->armNextPC) + 3; + } +} + +// MOV Hd, Hs +static INSN_REGPARM void thumb46_3(GBASystem *gba, u32 opcode) +{ + gba->reg[(opcode&7)+8].I = gba->reg[((opcode>>3)&7)+8].I; + if((opcode&7) == 7) { + UPDATE_OLDREG; + gba->reg[15].I &= 0xFFFFFFFE; + gba->armNextPC = gba->reg[15].I; + gba->reg[15].I += 2; + THUMB_PREFETCH; + gba->clockTicks = codeTicksAccessSeq16(gba, gba->armNextPC)*2 + + codeTicksAccess16(gba, gba->armNextPC) + 3; + } +} + + +// BX Rs +static INSN_REGPARM void thumb47(GBASystem *gba, u32 opcode) +{ + int base = (opcode >> 3) & 15; + gba->busPrefetchCount=0; + UPDATE_OLDREG; + gba->reg[15].I = gba->reg[base].I; + if(gba->reg[base].I & 1) { + gba->armState = false; + gba->reg[15].I &= 0xFFFFFFFE; + gba->armNextPC = gba->reg[15].I; + gba->reg[15].I += 2; + THUMB_PREFETCH; + gba->clockTicks = codeTicksAccessSeq16(gba, gba->armNextPC) + + codeTicksAccessSeq16(gba, gba->armNextPC) + codeTicksAccess16(gba, gba->armNextPC) + 3; + } else { + gba->armState = true; + gba->reg[15].I &= 0xFFFFFFFC; + gba->armNextPC = gba->reg[15].I; + gba->reg[15].I += 4; + ARM_PREFETCH; + gba->clockTicks = codeTicksAccessSeq32(gba, gba->armNextPC) + + codeTicksAccessSeq32(gba, gba->armNextPC) + codeTicksAccess32(gba, gba->armNextPC) + 3; + } +} + +// Load/store instructions //////////////////////////////////////////////// + +// LDR R0~R7,[PC, #Imm] +static INSN_REGPARM void thumb48(GBASystem *gba, u32 opcode) +{ + u8 regist = (opcode >> 8) & 7; + if (gba->busPrefetchCount == 0) + gba->busPrefetch = gba->busPrefetchEnable; + u32 address = (gba->reg[15].I & 0xFFFFFFFC) + ((opcode & 0xFF) << 2); + gba->reg[regist].I = CPUReadMemoryQuick(gba, address); + gba->busPrefetchCount=0; + gba->clockTicks = 3 + dataTicksAccess32(gba, address) + codeTicksAccess16(gba, gba->armNextPC); +} + +// STR Rd, [Rs, Rn] +static INSN_REGPARM void thumb50(GBASystem *gba, u32 opcode) +{ + if (gba->busPrefetchCount == 0) + gba->busPrefetch = gba->busPrefetchEnable; + u32 address = gba->reg[(opcode>>3)&7].I + gba->reg[(opcode>>6)&7].I; + CPUWriteMemory(gba, address, gba->reg[opcode & 7].I); + gba->clockTicks = dataTicksAccess32(gba, address) + codeTicksAccess16(gba, gba->armNextPC) + 2; +} + +// STRH Rd, [Rs, Rn] +static INSN_REGPARM void thumb52(GBASystem *gba, u32 opcode) +{ + if (gba->busPrefetchCount == 0) + gba->busPrefetch = gba->busPrefetchEnable; + u32 address = gba->reg[(opcode>>3)&7].I + gba->reg[(opcode>>6)&7].I; + CPUWriteHalfWord(gba, address, gba->reg[opcode&7].W.W0); + gba->clockTicks = dataTicksAccess16(gba, address) + codeTicksAccess16(gba, gba->armNextPC) + 2; +} + +// STRB Rd, [Rs, Rn] +static INSN_REGPARM void thumb54(GBASystem *gba, u32 opcode) +{ + if (gba->busPrefetchCount == 0) + gba->busPrefetch = gba->busPrefetchEnable; + u32 address = gba->reg[(opcode>>3)&7].I + gba->reg[(opcode >>6)&7].I; + CPUWriteByte(gba, address, gba->reg[opcode & 7].B.B0); + gba->clockTicks = dataTicksAccess16(gba, address) + codeTicksAccess16(gba, gba->armNextPC) + 2; +} + +// LDSB Rd, [Rs, Rn] +static INSN_REGPARM void thumb56(GBASystem *gba, u32 opcode) +{ + if (gba->busPrefetchCount == 0) + gba->busPrefetch = gba->busPrefetchEnable; + u32 address = gba->reg[(opcode>>3)&7].I + gba->reg[(opcode>>6)&7].I; + gba->reg[opcode&7].I = (s8)CPUReadByte(gba, address); + gba->clockTicks = 3 + dataTicksAccess16(gba, address) + codeTicksAccess16(gba, gba->armNextPC); +} + +// LDR Rd, [Rs, Rn] +static INSN_REGPARM void thumb58(GBASystem *gba, u32 opcode) +{ + if (gba->busPrefetchCount == 0) + gba->busPrefetch = gba->busPrefetchEnable; + u32 address = gba->reg[(opcode>>3)&7].I + gba->reg[(opcode>>6)&7].I; + gba->reg[opcode&7].I = CPUReadMemory(gba, address); + gba->clockTicks = 3 + dataTicksAccess32(gba, address) + codeTicksAccess16(gba, gba->armNextPC); +} + +// LDRH Rd, [Rs, Rn] +static INSN_REGPARM void thumb5A(GBASystem *gba, u32 opcode) +{ + if (gba->busPrefetchCount == 0) + gba->busPrefetch = gba->busPrefetchEnable; + u32 address = gba->reg[(opcode>>3)&7].I + gba->reg[(opcode>>6)&7].I; + gba->reg[opcode&7].I = CPUReadHalfWord(gba, address); + gba->clockTicks = 3 + dataTicksAccess32(gba, address) + codeTicksAccess16(gba, gba->armNextPC); +} + +// LDRB Rd, [Rs, Rn] +static INSN_REGPARM void thumb5C(GBASystem *gba, u32 opcode) +{ + if (gba->busPrefetchCount == 0) + gba->busPrefetch = gba->busPrefetchEnable; + u32 address = gba->reg[(opcode>>3)&7].I + gba->reg[(opcode>>6)&7].I; + gba->reg[opcode&7].I = CPUReadByte(gba, address); + gba->clockTicks = 3 + dataTicksAccess16(gba, address) + codeTicksAccess16(gba, gba->armNextPC); +} + +// LDSH Rd, [Rs, Rn] +static INSN_REGPARM void thumb5E(GBASystem *gba, u32 opcode) +{ + if (gba->busPrefetchCount == 0) + gba->busPrefetch = gba->busPrefetchEnable; + u32 address = gba->reg[(opcode>>3)&7].I + gba->reg[(opcode>>6)&7].I; + gba->reg[opcode&7].I = (s16)CPUReadHalfWordSigned(gba, address); + gba->clockTicks = 3 + dataTicksAccess16(gba, address) + codeTicksAccess16(gba, gba->armNextPC); +} + +// STR Rd, [Rs, #Imm] +static INSN_REGPARM void thumb60(GBASystem *gba, u32 opcode) +{ + if (gba->busPrefetchCount == 0) + gba->busPrefetch = gba->busPrefetchEnable; + u32 address = gba->reg[(opcode>>3)&7].I + (((opcode>>6)&31)<<2); + CPUWriteMemory(gba, address, gba->reg[opcode&7].I); + gba->clockTicks = dataTicksAccess32(gba, address) + codeTicksAccess16(gba, gba->armNextPC) + 2; +} + +// LDR Rd, [Rs, #Imm] +static INSN_REGPARM void thumb68(GBASystem *gba, u32 opcode) +{ + if (gba->busPrefetchCount == 0) + gba->busPrefetch = gba->busPrefetchEnable; + u32 address = gba->reg[(opcode>>3)&7].I + (((opcode>>6)&31)<<2); + gba->reg[opcode&7].I = CPUReadMemory(gba, address); + gba->clockTicks = 3 + dataTicksAccess32(gba, address) + codeTicksAccess16(gba, gba->armNextPC); +} + +// STRB Rd, [Rs, #Imm] +static INSN_REGPARM void thumb70(GBASystem *gba, u32 opcode) +{ + if (gba->busPrefetchCount == 0) + gba->busPrefetch = gba->busPrefetchEnable; + u32 address = gba->reg[(opcode>>3)&7].I + (((opcode>>6)&31)); + CPUWriteByte(gba, address, gba->reg[opcode&7].B.B0); + gba->clockTicks = dataTicksAccess16(gba, address) + codeTicksAccess16(gba, gba->armNextPC) + 2; +} + +// LDRB Rd, [Rs, #Imm] +static INSN_REGPARM void thumb78(GBASystem *gba, u32 opcode) +{ + if (gba->busPrefetchCount == 0) + gba->busPrefetch = gba->busPrefetchEnable; + u32 address = gba->reg[(opcode>>3)&7].I + (((opcode>>6)&31)); + gba->reg[opcode&7].I = CPUReadByte(gba, address); + gba->clockTicks = 3 + dataTicksAccess16(gba, address) + codeTicksAccess16(gba, gba->armNextPC); +} + +// STRH Rd, [Rs, #Imm] +static INSN_REGPARM void thumb80(GBASystem *gba, u32 opcode) +{ + if (gba->busPrefetchCount == 0) + gba->busPrefetch = gba->busPrefetchEnable; + u32 address = gba->reg[(opcode>>3)&7].I + (((opcode>>6)&31)<<1); + CPUWriteHalfWord(gba, address, gba->reg[opcode&7].W.W0); + gba->clockTicks = dataTicksAccess16(gba, address) + codeTicksAccess16(gba, gba->armNextPC) + 2; +} + +// LDRH Rd, [Rs, #Imm] +static INSN_REGPARM void thumb88(GBASystem *gba, u32 opcode) +{ + if (gba->busPrefetchCount == 0) + gba->busPrefetch = gba->busPrefetchEnable; + u32 address = gba->reg[(opcode>>3)&7].I + (((opcode>>6)&31)<<1); + gba->reg[opcode&7].I = CPUReadHalfWord(gba, address); + gba->clockTicks = 3 + dataTicksAccess16(gba, address) + codeTicksAccess16(gba, gba->armNextPC); +} + +// STR R0~R7, [SP, #Imm] +static INSN_REGPARM void thumb90(GBASystem *gba, u32 opcode) +{ + u8 regist = (opcode >> 8) & 7; + if (gba->busPrefetchCount == 0) + gba->busPrefetch = gba->busPrefetchEnable; + u32 address = gba->reg[13].I + ((opcode&255)<<2); + CPUWriteMemory(gba, address, gba->reg[regist].I); + gba->clockTicks = dataTicksAccess32(gba, address) + codeTicksAccess16(gba, gba->armNextPC) + 2; +} + +// LDR R0~R7, [SP, #Imm] +static INSN_REGPARM void thumb98(GBASystem *gba, u32 opcode) +{ + u8 regist = (opcode >> 8) & 7; + if (gba->busPrefetchCount == 0) + gba->busPrefetch = gba->busPrefetchEnable; + u32 address = gba->reg[13].I + ((opcode&255)<<2); + gba->reg[regist].I = CPUReadMemoryQuick(gba, address); + gba->clockTicks = 3 + dataTicksAccess32(gba, address) + codeTicksAccess16(gba, gba->armNextPC); +} + +// PC/stack-related /////////////////////////////////////////////////////// + +// ADD R0~R7, PC, Imm +static INSN_REGPARM void thumbA0(GBASystem *gba, u32 opcode) +{ + u8 regist = (opcode >> 8) & 7; + gba->reg[regist].I = (gba->reg[15].I & 0xFFFFFFFC) + ((opcode&255)<<2); +} + +// ADD R0~R7, SP, Imm +static INSN_REGPARM void thumbA8(GBASystem *gba, u32 opcode) +{ + u8 regist = (opcode >> 8) & 7; + gba->reg[regist].I = gba->reg[13].I + ((opcode&255)<<2); +} + +// ADD SP, Imm +static INSN_REGPARM void thumbB0(GBASystem *gba, u32 opcode) +{ + int offset = (opcode & 127) << 2; + if(opcode & 0x80) + offset = -offset; + gba->reg[13].I += offset; +} + +// Push and pop /////////////////////////////////////////////////////////// + +#define PUSH_REG(val, r) \ + if (opcode & (val)) { \ + CPUWriteMemory(gba, address, gba->reg[(r)].I); \ + if (!count) { \ + gba->clockTicks += 1 + dataTicksAccess32(gba, address); \ + } else { \ + gba->clockTicks += 1 + dataTicksAccessSeq32(gba, address); \ + } \ + count++; \ + address += 4; \ + } + +#define POP_REG(val, r) \ + if (opcode & (val)) { \ + gba->reg[(r)].I = CPUReadMemory(gba, address); \ + if (!count) { \ + gba->clockTicks += 1 + dataTicksAccess32(gba, address); \ + } else { \ + gba->clockTicks += 1 + dataTicksAccessSeq32(gba, address); \ + } \ + count++; \ + address += 4; \ + } + +// PUSH {Rlist} +static INSN_REGPARM void thumbB4(GBASystem *gba, u32 opcode) +{ + if (gba->busPrefetchCount == 0) + gba->busPrefetch = gba->busPrefetchEnable; + int count = 0; + u32 temp = gba->reg[13].I - 4 * gba->cpuBitsSet[opcode & 0xff]; + u32 address = temp & 0xFFFFFFFC; + PUSH_REG(1, 0); + PUSH_REG(2, 1); + PUSH_REG(4, 2); + PUSH_REG(8, 3); + PUSH_REG(16, 4); + PUSH_REG(32, 5); + PUSH_REG(64, 6); + PUSH_REG(128, 7); + gba->clockTicks += 1 + codeTicksAccess16(gba, gba->armNextPC); + gba->reg[13].I = temp; +} + +// PUSH {Rlist, LR} +static INSN_REGPARM void thumbB5(GBASystem *gba, u32 opcode) +{ + if (gba->busPrefetchCount == 0) + gba->busPrefetch = gba->busPrefetchEnable; + int count = 0; + u32 temp = gba->reg[13].I - 4 - 4 * gba->cpuBitsSet[opcode & 0xff]; + u32 address = temp & 0xFFFFFFFC; + PUSH_REG(1, 0); + PUSH_REG(2, 1); + PUSH_REG(4, 2); + PUSH_REG(8, 3); + PUSH_REG(16, 4); + PUSH_REG(32, 5); + PUSH_REG(64, 6); + PUSH_REG(128, 7); + PUSH_REG(256, 14); + gba->clockTicks += 1 + codeTicksAccess16(gba, gba->armNextPC); + gba->reg[13].I = temp; +} + +// POP {Rlist} +static INSN_REGPARM void thumbBC(GBASystem *gba, u32 opcode) +{ + if (gba->busPrefetchCount == 0) + gba->busPrefetch = gba->busPrefetchEnable; + int count = 0; + u32 address = gba->reg[13].I & 0xFFFFFFFC; + u32 temp = gba->reg[13].I + 4*gba->cpuBitsSet[opcode & 0xFF]; + POP_REG(1, 0); + POP_REG(2, 1); + POP_REG(4, 2); + POP_REG(8, 3); + POP_REG(16, 4); + POP_REG(32, 5); + POP_REG(64, 6); + POP_REG(128, 7); + gba->reg[13].I = temp; + gba->clockTicks = 2 + codeTicksAccess16(gba, gba->armNextPC); +} + +// POP {Rlist, PC} +static INSN_REGPARM void thumbBD(GBASystem *gba, u32 opcode) +{ + if (gba->busPrefetchCount == 0) + gba->busPrefetch = gba->busPrefetchEnable; + int count = 0; + u32 address = gba->reg[13].I & 0xFFFFFFFC; + u32 temp = gba->reg[13].I + 4 + 4*gba->cpuBitsSet[opcode & 0xFF]; + POP_REG(1, 0); + POP_REG(2, 1); + POP_REG(4, 2); + POP_REG(8, 3); + POP_REG(16, 4); + POP_REG(32, 5); + POP_REG(64, 6); + POP_REG(128, 7); + gba->reg[15].I = (CPUReadMemory(gba, address) & 0xFFFFFFFE); + if (!count) { + gba->clockTicks += 1 + dataTicksAccess32(gba, address); + } else { + gba->clockTicks += 1 + dataTicksAccessSeq32(gba, address); + } + count++; + gba->armNextPC = gba->reg[15].I; + gba->reg[15].I += 2; + gba->reg[13].I = temp; + THUMB_PREFETCH; + gba->busPrefetchCount = 0; + gba->clockTicks += 3 + codeTicksAccess16(gba, gba->armNextPC) + codeTicksAccess16(gba, gba->armNextPC); +} + +// Load/store multiple //////////////////////////////////////////////////// + +#define THUMB_STM_REG(val,r,b) \ + if(opcode & (val)) { \ + CPUWriteMemory(gba, address, gba->reg[(r)].I); \ + gba->reg[(b)].I = temp; \ + if (!count) { \ + gba->clockTicks += 1 + dataTicksAccess32(gba, address); \ + } else { \ + gba->clockTicks += 1 + dataTicksAccessSeq32(gba, address); \ + } \ + count++; \ + address += 4; \ + } + +#define THUMB_LDM_REG(val,r) \ + if(opcode & (val)) { \ + gba->reg[(r)].I = CPUReadMemory(gba, address); \ + if (!count) { \ + gba->clockTicks += 1 + dataTicksAccess32(gba, address); \ + } else { \ + gba->clockTicks += 1 + dataTicksAccessSeq32(gba, address); \ + } \ + count++; \ + address += 4; \ + } + +// STM R0~7!, {Rlist} +static INSN_REGPARM void thumbC0(GBASystem *gba, u32 opcode) +{ + u8 regist = (opcode >> 8) & 7; + if (gba->busPrefetchCount == 0) + gba->busPrefetch = gba->busPrefetchEnable; + u32 address = gba->reg[regist].I & 0xFFFFFFFC; + u32 temp = gba->reg[regist].I + 4*gba->cpuBitsSet[opcode & 0xff]; + int count = 0; + // store + THUMB_STM_REG(1, 0, regist); + THUMB_STM_REG(2, 1, regist); + THUMB_STM_REG(4, 2, regist); + THUMB_STM_REG(8, 3, regist); + THUMB_STM_REG(16, 4, regist); + THUMB_STM_REG(32, 5, regist); + THUMB_STM_REG(64, 6, regist); + THUMB_STM_REG(128, 7, regist); + gba->clockTicks = 1 + codeTicksAccess16(gba, gba->armNextPC); +} + +// LDM R0~R7!, {Rlist} +static INSN_REGPARM void thumbC8(GBASystem *gba, u32 opcode) +{ + u8 regist = (opcode >> 8) & 7; + if (gba->busPrefetchCount == 0) + gba->busPrefetch = gba->busPrefetchEnable; + u32 address = gba->reg[regist].I & 0xFFFFFFFC; + u32 temp = gba->reg[regist].I + 4*gba->cpuBitsSet[opcode & 0xFF]; + int count = 0; + // load + THUMB_LDM_REG(1, 0); + THUMB_LDM_REG(2, 1); + THUMB_LDM_REG(4, 2); + THUMB_LDM_REG(8, 3); + THUMB_LDM_REG(16, 4); + THUMB_LDM_REG(32, 5); + THUMB_LDM_REG(64, 6); + THUMB_LDM_REG(128, 7); + gba->clockTicks = 2 + codeTicksAccess16(gba, gba->armNextPC); + if(!(opcode & (1<reg[regist].I = temp; +} + +// Conditional branches /////////////////////////////////////////////////// + +// BEQ offset +static INSN_REGPARM void thumbD0(GBASystem *gba, u32 opcode) +{ + UPDATE_OLDREG; + if(gba->Z_FLAG) { + gba->reg[15].I += ((s8)(opcode & 0xFF)) << 1; + gba->armNextPC = gba->reg[15].I; + gba->reg[15].I += 2; + THUMB_PREFETCH; + gba->clockTicks = codeTicksAccessSeq16(gba, gba->armNextPC) + codeTicksAccessSeq16(gba, gba->armNextPC) + + codeTicksAccess16(gba, gba->armNextPC)+3; + gba->busPrefetchCount=0; + } +} + +// BNE offset +static INSN_REGPARM void thumbD1(GBASystem *gba, u32 opcode) +{ + UPDATE_OLDREG; + if(!gba->Z_FLAG) { + gba->reg[15].I += ((s8)(opcode & 0xFF)) << 1; + gba->armNextPC = gba->reg[15].I; + gba->reg[15].I += 2; + THUMB_PREFETCH; + gba->clockTicks = codeTicksAccessSeq16(gba, gba->armNextPC) + codeTicksAccessSeq16(gba, gba->armNextPC) + + codeTicksAccess16(gba, gba->armNextPC)+3; + gba->busPrefetchCount=0; + } +} + +// BCS offset +static INSN_REGPARM void thumbD2(GBASystem *gba, u32 opcode) +{ + UPDATE_OLDREG; + if(gba->C_FLAG) { + gba->reg[15].I += ((s8)(opcode & 0xFF)) << 1; + gba->armNextPC = gba->reg[15].I; + gba->reg[15].I += 2; + THUMB_PREFETCH; + gba->clockTicks = codeTicksAccessSeq16(gba, gba->armNextPC) + codeTicksAccessSeq16(gba, gba->armNextPC) + + codeTicksAccess16(gba, gba->armNextPC)+3; + gba->busPrefetchCount=0; + } +} + +// BCC offset +static INSN_REGPARM void thumbD3(GBASystem *gba, u32 opcode) +{ + UPDATE_OLDREG; + if(!gba->C_FLAG) { + gba->reg[15].I += ((s8)(opcode & 0xFF)) << 1; + gba->armNextPC = gba->reg[15].I; + gba->reg[15].I += 2; + THUMB_PREFETCH; + gba->clockTicks = codeTicksAccessSeq16(gba, gba->armNextPC) + codeTicksAccessSeq16(gba, gba->armNextPC) + + codeTicksAccess16(gba, gba->armNextPC)+3; + gba->busPrefetchCount=0; + } +} + +// BMI offset +static INSN_REGPARM void thumbD4(GBASystem *gba, u32 opcode) +{ + UPDATE_OLDREG; + if(gba->N_FLAG) { + gba->reg[15].I += ((s8)(opcode & 0xFF)) << 1; + gba->armNextPC = gba->reg[15].I; + gba->reg[15].I += 2; + THUMB_PREFETCH; + gba->clockTicks = codeTicksAccessSeq16(gba, gba->armNextPC) + codeTicksAccessSeq16(gba, gba->armNextPC) + + codeTicksAccess16(gba, gba->armNextPC)+3; + gba->busPrefetchCount=0; + } +} + +// BPL offset +static INSN_REGPARM void thumbD5(GBASystem *gba, u32 opcode) +{ + UPDATE_OLDREG; + if(!gba->N_FLAG) { + gba->reg[15].I += ((s8)(opcode & 0xFF)) << 1; + gba->armNextPC = gba->reg[15].I; + gba->reg[15].I += 2; + THUMB_PREFETCH; + gba->clockTicks = codeTicksAccessSeq16(gba, gba->armNextPC) + codeTicksAccessSeq16(gba, gba->armNextPC) + + codeTicksAccess16(gba, gba->armNextPC)+3; + gba->busPrefetchCount=0; + } +} + +// BVS offset +static INSN_REGPARM void thumbD6(GBASystem *gba, u32 opcode) +{ + UPDATE_OLDREG; + if(gba->V_FLAG) { + gba->reg[15].I += ((s8)(opcode & 0xFF)) << 1; + gba->armNextPC = gba->reg[15].I; + gba->reg[15].I += 2; + THUMB_PREFETCH; + gba->clockTicks = codeTicksAccessSeq16(gba, gba->armNextPC) + codeTicksAccessSeq16(gba, gba->armNextPC) + + codeTicksAccess16(gba, gba->armNextPC)+3; + gba->busPrefetchCount=0; + } +} + +// BVC offset +static INSN_REGPARM void thumbD7(GBASystem *gba, u32 opcode) +{ + UPDATE_OLDREG; + if(!gba->V_FLAG) { + gba->reg[15].I += ((s8)(opcode & 0xFF)) << 1; + gba->armNextPC = gba->reg[15].I; + gba->reg[15].I += 2; + THUMB_PREFETCH; + gba->clockTicks = codeTicksAccessSeq16(gba, gba->armNextPC) + codeTicksAccessSeq16(gba, gba->armNextPC) + + codeTicksAccess16(gba, gba->armNextPC)+3; + gba->busPrefetchCount=0; + } +} + +// BHI offset +static INSN_REGPARM void thumbD8(GBASystem *gba, u32 opcode) +{ + UPDATE_OLDREG; + if(gba->C_FLAG && !gba->Z_FLAG) { + gba->reg[15].I += ((s8)(opcode & 0xFF)) << 1; + gba->armNextPC = gba->reg[15].I; + gba->reg[15].I += 2; + THUMB_PREFETCH; + gba->clockTicks = codeTicksAccessSeq16(gba, gba->armNextPC) + codeTicksAccessSeq16(gba, gba->armNextPC) + + codeTicksAccess16(gba, gba->armNextPC)+3; + gba->busPrefetchCount=0; + } +} + +// BLS offset +static INSN_REGPARM void thumbD9(GBASystem *gba, u32 opcode) +{ + UPDATE_OLDREG; + if(!gba->C_FLAG || gba->Z_FLAG) { + gba->reg[15].I += ((s8)(opcode & 0xFF)) << 1; + gba->armNextPC = gba->reg[15].I; + gba->reg[15].I += 2; + THUMB_PREFETCH; + gba->clockTicks = codeTicksAccessSeq16(gba, gba->armNextPC) + codeTicksAccessSeq16(gba, gba->armNextPC) + + codeTicksAccess16(gba, gba->armNextPC)+3; + gba->busPrefetchCount=0; + } +} + +// BGE offset +static INSN_REGPARM void thumbDA(GBASystem *gba, u32 opcode) +{ + UPDATE_OLDREG; + if(gba->N_FLAG == gba->V_FLAG) { + gba->reg[15].I += ((s8)(opcode & 0xFF)) << 1; + gba->armNextPC = gba->reg[15].I; + gba->reg[15].I += 2; + THUMB_PREFETCH; + gba->clockTicks = codeTicksAccessSeq16(gba, gba->armNextPC) + codeTicksAccessSeq16(gba, gba->armNextPC) + + codeTicksAccess16(gba, gba->armNextPC)+3; + gba->busPrefetchCount=0; + } +} + +// BLT offset +static INSN_REGPARM void thumbDB(GBASystem *gba, u32 opcode) +{ + UPDATE_OLDREG; + if(gba->N_FLAG != gba->V_FLAG) { + gba->reg[15].I += ((s8)(opcode & 0xFF)) << 1; + gba->armNextPC = gba->reg[15].I; + gba->reg[15].I += 2; + THUMB_PREFETCH; + gba->clockTicks = codeTicksAccessSeq16(gba, gba->armNextPC) + codeTicksAccessSeq16(gba, gba->armNextPC) + + codeTicksAccess16(gba, gba->armNextPC)+3; + gba->busPrefetchCount=0; + } +} + +// BGT offset +static INSN_REGPARM void thumbDC(GBASystem *gba, u32 opcode) +{ + UPDATE_OLDREG; + if(!gba->Z_FLAG && (gba->N_FLAG == gba->V_FLAG)) { + gba->reg[15].I += ((s8)(opcode & 0xFF)) << 1; + gba->armNextPC = gba->reg[15].I; + gba->reg[15].I += 2; + THUMB_PREFETCH; + gba->clockTicks = codeTicksAccessSeq16(gba, gba->armNextPC) + codeTicksAccessSeq16(gba, gba->armNextPC) + + codeTicksAccess16(gba, gba->armNextPC)+3; + gba->busPrefetchCount=0; + } +} + +// BLE offset +static INSN_REGPARM void thumbDD(GBASystem *gba, u32 opcode) +{ + UPDATE_OLDREG; + if(gba->Z_FLAG || (gba->N_FLAG != gba->V_FLAG)) { + gba->reg[15].I += ((s8)(opcode & 0xFF)) << 1; + gba->armNextPC = gba->reg[15].I; + gba->reg[15].I += 2; + THUMB_PREFETCH; + gba->clockTicks = codeTicksAccessSeq16(gba, gba->armNextPC) + codeTicksAccessSeq16(gba, gba->armNextPC) + + codeTicksAccess16(gba, gba->armNextPC)+3; + gba->busPrefetchCount=0; + } +} + +// SWI, B, BL ///////////////////////////////////////////////////////////// + +// SWI #comment +static INSN_REGPARM void thumbDF(GBASystem *gba, u32 opcode) +{ + u32 address = 0; + gba->clockTicks = codeTicksAccessSeq16(gba, address) + codeTicksAccessSeq16(gba, address) + + codeTicksAccess16(gba, address)+3; + gba->busPrefetchCount=0; + CPUSoftwareInterrupt(gba, opcode & 0xFF); +} + +// B offset +static INSN_REGPARM void thumbE0(GBASystem *gba, u32 opcode) +{ + int offset = (opcode & 0x3FF) << 1; + if(opcode & 0x0400) + offset |= 0xFFFFF800; + gba->reg[15].I += offset; + gba->armNextPC = gba->reg[15].I; + gba->reg[15].I += 2; + THUMB_PREFETCH; + gba->clockTicks = codeTicksAccessSeq16(gba, gba->armNextPC) + codeTicksAccessSeq16(gba, gba->armNextPC) + + codeTicksAccess16(gba, gba->armNextPC) + 3; + gba->busPrefetchCount=0; +} + +// BLL #offset (forward) +static INSN_REGPARM void thumbF0(GBASystem *gba, u32 opcode) +{ + int offset = (opcode & 0x7FF); + gba->reg[14].I = gba->reg[15].I + (offset << 12); + gba->clockTicks = codeTicksAccessSeq16(gba, gba->armNextPC) + 1; +} + +// BLL #offset (backward) +static INSN_REGPARM void thumbF4(GBASystem *gba, u32 opcode) +{ + int offset = (opcode & 0x7FF); + gba->reg[14].I = gba->reg[15].I + ((offset << 12) | 0xFF800000); + gba->clockTicks = codeTicksAccessSeq16(gba, gba->armNextPC) + 1; +} + +// BLH #offset +static INSN_REGPARM void thumbF8(GBASystem *gba, u32 opcode) +{ + int offset = (opcode & 0x7FF); + u32 temp = gba->reg[15].I-2; + gba->reg[15].I = (gba->reg[14].I + (offset<<1))&0xFFFFFFFE; + gba->armNextPC = gba->reg[15].I; + gba->reg[15].I += 2; + gba->reg[14].I = temp|1; + THUMB_PREFETCH; + gba->clockTicks = codeTicksAccessSeq16(gba, gba->armNextPC) + + codeTicksAccess16(gba, gba->armNextPC) + codeTicksAccessSeq16(gba, gba->armNextPC) + 3; + gba->busPrefetchCount = 0; +} + +// Instruction table ////////////////////////////////////////////////////// + +typedef INSN_REGPARM void (*insnfunc_t)(GBASystem *gba, u32 opcode); +#define thumbUI thumbUnknownInsn +#define thumbBP thumbUnknownInsn +static insnfunc_t thumbInsnTable[1024] = { + thumb00_00,thumb00_01,thumb00_02,thumb00_03,thumb00_04,thumb00_05,thumb00_06,thumb00_07, // 00 + thumb00_08,thumb00_09,thumb00_0A,thumb00_0B,thumb00_0C,thumb00_0D,thumb00_0E,thumb00_0F, + thumb00_10,thumb00_11,thumb00_12,thumb00_13,thumb00_14,thumb00_15,thumb00_16,thumb00_17, + thumb00_18,thumb00_19,thumb00_1A,thumb00_1B,thumb00_1C,thumb00_1D,thumb00_1E,thumb00_1F, + thumb08_00,thumb08_01,thumb08_02,thumb08_03,thumb08_04,thumb08_05,thumb08_06,thumb08_07, // 08 + thumb08_08,thumb08_09,thumb08_0A,thumb08_0B,thumb08_0C,thumb08_0D,thumb08_0E,thumb08_0F, + thumb08_10,thumb08_11,thumb08_12,thumb08_13,thumb08_14,thumb08_15,thumb08_16,thumb08_17, + thumb08_18,thumb08_19,thumb08_1A,thumb08_1B,thumb08_1C,thumb08_1D,thumb08_1E,thumb08_1F, + thumb10_00,thumb10_01,thumb10_02,thumb10_03,thumb10_04,thumb10_05,thumb10_06,thumb10_07, // 10 + thumb10_08,thumb10_09,thumb10_0A,thumb10_0B,thumb10_0C,thumb10_0D,thumb10_0E,thumb10_0F, + thumb10_10,thumb10_11,thumb10_12,thumb10_13,thumb10_14,thumb10_15,thumb10_16,thumb10_17, + thumb10_18,thumb10_19,thumb10_1A,thumb10_1B,thumb10_1C,thumb10_1D,thumb10_1E,thumb10_1F, + thumb18_0,thumb18_1,thumb18_2,thumb18_3,thumb18_4,thumb18_5,thumb18_6,thumb18_7, // 18 + thumb1A_0,thumb1A_1,thumb1A_2,thumb1A_3,thumb1A_4,thumb1A_5,thumb1A_6,thumb1A_7, + thumb1C_0,thumb1C_1,thumb1C_2,thumb1C_3,thumb1C_4,thumb1C_5,thumb1C_6,thumb1C_7, + thumb1E_0,thumb1E_1,thumb1E_2,thumb1E_3,thumb1E_4,thumb1E_5,thumb1E_6,thumb1E_7, + thumb20,thumb20,thumb20,thumb20,thumb21,thumb21,thumb21,thumb21, // 20 + thumb22,thumb22,thumb22,thumb22,thumb23,thumb23,thumb23,thumb23, + thumb24,thumb24,thumb24,thumb24,thumb25,thumb25,thumb25,thumb25, + thumb26,thumb26,thumb26,thumb26,thumb27,thumb27,thumb27,thumb27, + thumb28,thumb28,thumb28,thumb28,thumb29,thumb29,thumb29,thumb29, // 28 + thumb2A,thumb2A,thumb2A,thumb2A,thumb2B,thumb2B,thumb2B,thumb2B, + thumb2C,thumb2C,thumb2C,thumb2C,thumb2D,thumb2D,thumb2D,thumb2D, + thumb2E,thumb2E,thumb2E,thumb2E,thumb2F,thumb2F,thumb2F,thumb2F, + thumb30,thumb30,thumb30,thumb30,thumb31,thumb31,thumb31,thumb31, // 30 + thumb32,thumb32,thumb32,thumb32,thumb33,thumb33,thumb33,thumb33, + thumb34,thumb34,thumb34,thumb34,thumb35,thumb35,thumb35,thumb35, + thumb36,thumb36,thumb36,thumb36,thumb37,thumb37,thumb37,thumb37, + thumb38,thumb38,thumb38,thumb38,thumb39,thumb39,thumb39,thumb39, // 38 + thumb3A,thumb3A,thumb3A,thumb3A,thumb3B,thumb3B,thumb3B,thumb3B, + thumb3C,thumb3C,thumb3C,thumb3C,thumb3D,thumb3D,thumb3D,thumb3D, + thumb3E,thumb3E,thumb3E,thumb3E,thumb3F,thumb3F,thumb3F,thumb3F, + thumb40_0,thumb40_1,thumb40_2,thumb40_3,thumb41_0,thumb41_1,thumb41_2,thumb41_3, // 40 + thumb42_0,thumb42_1,thumb42_2,thumb42_3,thumb43_0,thumb43_1,thumb43_2,thumb43_3, + thumbUI,thumb44_1,thumb44_2,thumb44_3,thumbUI,thumb45_1,thumb45_2,thumb45_3, + thumbUI,thumb46_1,thumb46_2,thumb46_3,thumb47,thumb47,thumbUI,thumbUI, + thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,thumb48, // 48 + thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,thumb48, + thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,thumb48, + thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,thumb48,thumb48, + thumb50,thumb50,thumb50,thumb50,thumb50,thumb50,thumb50,thumb50, // 50 + thumb52,thumb52,thumb52,thumb52,thumb52,thumb52,thumb52,thumb52, + thumb54,thumb54,thumb54,thumb54,thumb54,thumb54,thumb54,thumb54, + thumb56,thumb56,thumb56,thumb56,thumb56,thumb56,thumb56,thumb56, + thumb58,thumb58,thumb58,thumb58,thumb58,thumb58,thumb58,thumb58, // 58 + thumb5A,thumb5A,thumb5A,thumb5A,thumb5A,thumb5A,thumb5A,thumb5A, + thumb5C,thumb5C,thumb5C,thumb5C,thumb5C,thumb5C,thumb5C,thumb5C, + thumb5E,thumb5E,thumb5E,thumb5E,thumb5E,thumb5E,thumb5E,thumb5E, + thumb60,thumb60,thumb60,thumb60,thumb60,thumb60,thumb60,thumb60, // 60 + thumb60,thumb60,thumb60,thumb60,thumb60,thumb60,thumb60,thumb60, + thumb60,thumb60,thumb60,thumb60,thumb60,thumb60,thumb60,thumb60, + thumb60,thumb60,thumb60,thumb60,thumb60,thumb60,thumb60,thumb60, + thumb68,thumb68,thumb68,thumb68,thumb68,thumb68,thumb68,thumb68, // 68 + thumb68,thumb68,thumb68,thumb68,thumb68,thumb68,thumb68,thumb68, + thumb68,thumb68,thumb68,thumb68,thumb68,thumb68,thumb68,thumb68, + thumb68,thumb68,thumb68,thumb68,thumb68,thumb68,thumb68,thumb68, + thumb70,thumb70,thumb70,thumb70,thumb70,thumb70,thumb70,thumb70, // 70 + thumb70,thumb70,thumb70,thumb70,thumb70,thumb70,thumb70,thumb70, + thumb70,thumb70,thumb70,thumb70,thumb70,thumb70,thumb70,thumb70, + thumb70,thumb70,thumb70,thumb70,thumb70,thumb70,thumb70,thumb70, + thumb78,thumb78,thumb78,thumb78,thumb78,thumb78,thumb78,thumb78, // 78 + thumb78,thumb78,thumb78,thumb78,thumb78,thumb78,thumb78,thumb78, + thumb78,thumb78,thumb78,thumb78,thumb78,thumb78,thumb78,thumb78, + thumb78,thumb78,thumb78,thumb78,thumb78,thumb78,thumb78,thumb78, + thumb80,thumb80,thumb80,thumb80,thumb80,thumb80,thumb80,thumb80, // 80 + thumb80,thumb80,thumb80,thumb80,thumb80,thumb80,thumb80,thumb80, + thumb80,thumb80,thumb80,thumb80,thumb80,thumb80,thumb80,thumb80, + thumb80,thumb80,thumb80,thumb80,thumb80,thumb80,thumb80,thumb80, + thumb88,thumb88,thumb88,thumb88,thumb88,thumb88,thumb88,thumb88, // 88 + thumb88,thumb88,thumb88,thumb88,thumb88,thumb88,thumb88,thumb88, + thumb88,thumb88,thumb88,thumb88,thumb88,thumb88,thumb88,thumb88, + thumb88,thumb88,thumb88,thumb88,thumb88,thumb88,thumb88,thumb88, + thumb90,thumb90,thumb90,thumb90,thumb90,thumb90,thumb90,thumb90, // 90 + thumb90,thumb90,thumb90,thumb90,thumb90,thumb90,thumb90,thumb90, + thumb90,thumb90,thumb90,thumb90,thumb90,thumb90,thumb90,thumb90, + thumb90,thumb90,thumb90,thumb90,thumb90,thumb90,thumb90,thumb90, + thumb98,thumb98,thumb98,thumb98,thumb98,thumb98,thumb98,thumb98, // 98 + thumb98,thumb98,thumb98,thumb98,thumb98,thumb98,thumb98,thumb98, + thumb98,thumb98,thumb98,thumb98,thumb98,thumb98,thumb98,thumb98, + thumb98,thumb98,thumb98,thumb98,thumb98,thumb98,thumb98,thumb98, + thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,thumbA0, // A0 + thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,thumbA0, + thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,thumbA0, + thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,thumbA0,thumbA0, + thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,thumbA8, // A8 + thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,thumbA8, + thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,thumbA8, + thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,thumbA8,thumbA8, + thumbB0,thumbB0,thumbB0,thumbB0,thumbUI,thumbUI,thumbUI,thumbUI, // B0 + thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI, + thumbB4,thumbB4,thumbB4,thumbB4,thumbB5,thumbB5,thumbB5,thumbB5, + thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI, + thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI, // B8 + thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI, + thumbBC,thumbBC,thumbBC,thumbBC,thumbBD,thumbBD,thumbBD,thumbBD, + thumbBP,thumbBP,thumbBP,thumbBP,thumbUI,thumbUI,thumbUI,thumbUI, + thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,thumbC0, // C0 + thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,thumbC0, + thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,thumbC0, + thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,thumbC0,thumbC0, + thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,thumbC8, // C8 + thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,thumbC8, + thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,thumbC8, + thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,thumbC8,thumbC8, + thumbD0,thumbD0,thumbD0,thumbD0,thumbD1,thumbD1,thumbD1,thumbD1, // D0 + thumbD2,thumbD2,thumbD2,thumbD2,thumbD3,thumbD3,thumbD3,thumbD3, + thumbD4,thumbD4,thumbD4,thumbD4,thumbD5,thumbD5,thumbD5,thumbD5, + thumbD6,thumbD6,thumbD6,thumbD6,thumbD7,thumbD7,thumbD7,thumbD7, + thumbD8,thumbD8,thumbD8,thumbD8,thumbD9,thumbD9,thumbD9,thumbD9, // D8 + thumbDA,thumbDA,thumbDA,thumbDA,thumbDB,thumbDB,thumbDB,thumbDB, + thumbDC,thumbDC,thumbDC,thumbDC,thumbDD,thumbDD,thumbDD,thumbDD, + thumbUI,thumbUI,thumbUI,thumbUI,thumbDF,thumbDF,thumbDF,thumbDF, + thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,thumbE0, // E0 + thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,thumbE0, + thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,thumbE0, + thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,thumbE0,thumbE0, + thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI, // E8 + thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI, + thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI, + thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI,thumbUI, + thumbF0,thumbF0,thumbF0,thumbF0,thumbF0,thumbF0,thumbF0,thumbF0, // F0 + thumbF0,thumbF0,thumbF0,thumbF0,thumbF0,thumbF0,thumbF0,thumbF0, + thumbF4,thumbF4,thumbF4,thumbF4,thumbF4,thumbF4,thumbF4,thumbF4, + thumbF4,thumbF4,thumbF4,thumbF4,thumbF4,thumbF4,thumbF4,thumbF4, + thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8, // F8 + thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8, + thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8, + thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8,thumbF8, +}; + +// Wrapper routine (execution loop) /////////////////////////////////////// + +int thumbExecute(GBASystem *gba) +{ + do { + //if ((armNextPC & 0x0803FFFF) == 0x08020000) + // gba->busPrefetchCount=0x100; + + u32 opcode = gba->cpuPrefetch[0]; + gba->cpuPrefetch[0] = gba->cpuPrefetch[1]; + + gba->busPrefetch = false; + if (gba->busPrefetchCount & 0xFFFFFF00) + gba->busPrefetchCount = 0x100 | (gba->busPrefetchCount & 0xFF); + gba->clockTicks = 0; + u32 oldArmNextPC = gba->armNextPC; + + gba->armNextPC = gba->reg[15].I; + gba->reg[15].I += 2; + THUMB_PREFETCH_NEXT; + + (*thumbInsnTable[opcode>>6])(gba, opcode); + + if (gba->clockTicks < 0) + return 0; + if (gba->clockTicks==0) + gba->clockTicks = codeTicksAccessSeq16(gba, oldArmNextPC) + 1; + gba->cpuTotalTicks += gba->clockTicks; + + } while (gba->cpuTotalTicks < gba->cpuNextEvent && !gba->armState && !gba->holdState && !gba->SWITicks); + return 1; +} diff --git a/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/gba/GBA.cpp b/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/gba/GBA.cpp new file mode 100644 index 000000000..6807d9e23 --- /dev/null +++ b/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/gba/GBA.cpp @@ -0,0 +1,2500 @@ +#include +#include +#include +#include +#include +#include "GBA.h" +#include "GBAcpu.h" +#include "GBAinline.h" +#include "Globals.h" + +#include "Sound.h" +#include "bios.h" + +GBASystem::GBASystem() +{ + N_FLAG = false; + C_FLAG = false; + Z_FLAG = false; + V_FLAG = false; + armState = true; + armIrqEnable = true; + armNextPC = 0x00000000; + armMode = 0x1f; + stop = 0x08000568; + saveType = 0; + useBios = false; + skipBios = false; + frameSkip = 1; + speedup = false; + synchronize = true; + cpuDisableSfx = false; + cpuIsMultiBoot = false; + parseDebug = true; + layerSettings = 0xff00; + layerEnable = 0xff00; + speedHack = false; + cpuSaveType = 0; + cheatsEnabled = true; + mirroringEnable = false; + skipSaveGameBattery = false; + skipSaveGameCheats = false; + + bios = 0; + rom = 0; + internalRAM = 0; + workRAM = 0; + paletteRAM = 0; + vram = 0; + oam = 0; + ioMem = 0; + + customBackdropColor = -1; + + DISPCNT = 0x0080; + DISPSTAT = 0x0000; + VCOUNT = 0x0000; + BG0CNT = 0x0000; + BG1CNT = 0x0000; + BG2CNT = 0x0000; + BG3CNT = 0x0000; + BG0HOFS = 0x0000; + BG0VOFS = 0x0000; + BG1HOFS = 0x0000; + BG1VOFS = 0x0000; + BG2HOFS = 0x0000; + BG2VOFS = 0x0000; + BG3HOFS = 0x0000; + BG3VOFS = 0x0000; + BG2PA = 0x0100; + BG2PB = 0x0000; + BG2PC = 0x0000; + BG2PD = 0x0100; + BG2X_L = 0x0000; + BG2X_H = 0x0000; + BG2Y_L = 0x0000; + BG2Y_H = 0x0000; + BG3PA = 0x0100; + BG3PB = 0x0000; + BG3PC = 0x0000; + BG3PD = 0x0100; + BG3X_L = 0x0000; + BG3X_H = 0x0000; + BG3Y_L = 0x0000; + BG3Y_H = 0x0000; + WIN0H = 0x0000; + WIN1H = 0x0000; + WIN0V = 0x0000; + WIN1V = 0x0000; + WININ = 0x0000; + WINOUT = 0x0000; + MOSAIC = 0x0000; + BLDMOD = 0x0000; + COLEV = 0x0000; + COLY = 0x0000; + DM0SAD_L = 0x0000; + DM0SAD_H = 0x0000; + DM0DAD_L = 0x0000; + DM0DAD_H = 0x0000; + DM0CNT_L = 0x0000; + DM0CNT_H = 0x0000; + DM1SAD_L = 0x0000; + DM1SAD_H = 0x0000; + DM1DAD_L = 0x0000; + DM1DAD_H = 0x0000; + DM1CNT_L = 0x0000; + DM1CNT_H = 0x0000; + DM2SAD_L = 0x0000; + DM2SAD_H = 0x0000; + DM2DAD_L = 0x0000; + DM2DAD_H = 0x0000; + DM2CNT_L = 0x0000; + DM2CNT_H = 0x0000; + DM3SAD_L = 0x0000; + DM3SAD_H = 0x0000; + DM3DAD_L = 0x0000; + DM3DAD_H = 0x0000; + DM3CNT_L = 0x0000; + DM3CNT_H = 0x0000; + TM0D = 0x0000; + TM0CNT = 0x0000; + TM1D = 0x0000; + TM1CNT = 0x0000; + TM2D = 0x0000; + TM2CNT = 0x0000; + TM3D = 0x0000; + TM3CNT = 0x0000; + P1 = 0xFFFF; + IE = 0x0000; + IF = 0x0000; + IME = 0x0000; + + gfxBG2Changed = 0; + gfxBG3Changed = 0; + eepromInUse = 0; + + SWITicks = 0; + IRQTicks = 0; + + mastercode = 0; + layerEnableDelay = 0; + busPrefetch = false; + busPrefetchEnable = false; + busPrefetchCount = 0; + cpuDmaTicksToUpdate = 0; + cpuDmaCount = 0; + cpuDmaHack = false; + cpuDmaLast = 0; + dummyAddress = 0; + + cpuBreakLoop = false; + cpuNextEvent = 0; + + gbaSaveType = 0; // used to remember the save type on reset + intState = false; + stopState = false; + holdState = false; + holdType = 0; + cpuSramEnabled = true; + cpuFlashEnabled = true; + cpuEEPROMEnabled = true; + cpuEEPROMSensorEnabled = false; + + cpuTotalTicks = 0; + + lcdTicks = (useBios && !skipBios) ? 1008 : 208; + timerOnOffDelay = 0; + timer0Value = 0; + timer0On = false; + timer0Ticks = 0; + timer0Reload = 0; + timer0ClockReload = 0; + timer1Value = 0; + timer1On = false; + timer1Ticks = 0; + timer1Reload = 0; + timer1ClockReload = 0; + timer2Value = 0; + timer2On = false; + timer2Ticks = 0; + timer2Reload = 0; + timer2ClockReload = 0; + timer3Value = 0; + timer3On = false; + timer3Ticks = 0; + timer3Reload = 0; + timer3ClockReload = 0; + dma0Source = 0; + dma0Dest = 0; + dma1Source = 0; + dma1Dest = 0; + dma2Source = 0; + dma2Dest = 0; + dma3Source = 0; + dma3Dest = 0; + fxOn = false; + windowOn = false; + frameCount = 0; + lastTime = 0; + count = 0; + + capture = 0; + capturePrevious = 0; + captureNumber = 0; + + static const u8 init_memoryWait[16] = + { 0, 0, 2, 0, 0, 0, 0, 0, 4, 4, 4, 4, 4, 4, 4, 0 }; + memcpy(memoryWait, init_memoryWait, sizeof(memoryWait)); + static const u8 init_memoryWait32[16] = + { 0, 0, 5, 0, 0, 1, 1, 0, 7, 7, 9, 9, 13, 13, 4, 0 }; + memcpy(memoryWait32, init_memoryWait32, sizeof(memoryWait32)); + static const u8 init_memoryWaitSeq[16] = + { 0, 0, 2, 0, 0, 0, 0, 0, 2, 2, 4, 4, 8, 8, 4, 0 }; + memcpy(memoryWaitSeq, init_memoryWaitSeq, sizeof(memoryWaitSeq)); + static const u8 init_memoryWaitSeq32[16] = + { 0, 0, 5, 0, 0, 1, 1, 0, 5, 5, 9, 9, 17, 17, 4, 0 }; + memcpy(memoryWaitSeq32, init_memoryWaitSeq32, sizeof(memoryWaitSeq32)); + + #ifdef WORDS_BIGENDIAN + cpuBiosSwapped = false; + #endif + + romSize = 0x2000000; + + soundDeclicking = true; + + soundSampleRate = 44100; + soundInterpolation = true; + soundPaused = true; + soundFiltering = 0.5f; + SOUND_CLOCK_TICKS = SOUND_CLOCK_TICKS_; + soundTicks = SOUND_CLOCK_TICKS_; + + soundVolume = 1.0f; + soundEnableFlag = 0x3ff; // emulator channels enabled + soundFiltering_ = -1; + soundVolume_ = -1; + + gb_apu = 0; + stereo_buffer = 0; +} + +const int TIMER_TICKS[4] = { + 0, + 6, + 8, + 10 +}; + +const u32 objTilesAddress [3] = {0x010000, 0x014000, 0x014000}; +const u8 gamepakRamWaitState[4] = { 4, 3, 2, 8 }; +const u8 gamepakWaitState[4] = { 4, 3, 2, 8 }; +const u8 gamepakWaitState0[2] = { 2, 1 }; +const u8 gamepakWaitState1[2] = { 4, 1 }; +const u8 gamepakWaitState2[2] = { 8, 1 }; +const bool isInRom [16]= + { false, false, false, false, false, false, false, false, + true, true, true, true, true, true, false, false }; + +const u32 myROM[] = { +0xEA000006, +0xEA000093, +0xEA000006, +0x00000000, +0x00000000, +0x00000000, +0xEA000088, +0x00000000, +0xE3A00302, +0xE1A0F000, +0xE92D5800, +0xE55EC002, +0xE28FB03C, +0xE79BC10C, +0xE14FB000, +0xE92D0800, +0xE20BB080, +0xE38BB01F, +0xE129F00B, +0xE92D4004, +0xE1A0E00F, +0xE12FFF1C, +0xE8BD4004, +0xE3A0C0D3, +0xE129F00C, +0xE8BD0800, +0xE169F00B, +0xE8BD5800, +0xE1B0F00E, +0x0000009C, +0x0000009C, +0x0000009C, +0x0000009C, +0x000001F8, +0x000001F0, +0x000000AC, +0x000000A0, +0x000000FC, +0x00000168, +0xE12FFF1E, +0xE1A03000, +0xE1A00001, +0xE1A01003, +0xE2113102, +0x42611000, +0xE033C040, +0x22600000, +0xE1B02001, +0xE15200A0, +0x91A02082, +0x3AFFFFFC, +0xE1500002, +0xE0A33003, +0x20400002, +0xE1320001, +0x11A020A2, +0x1AFFFFF9, +0xE1A01000, +0xE1A00003, +0xE1B0C08C, +0x22600000, +0x42611000, +0xE12FFF1E, +0xE92D0010, +0xE1A0C000, +0xE3A01001, +0xE1500001, +0x81A000A0, +0x81A01081, +0x8AFFFFFB, +0xE1A0000C, +0xE1A04001, +0xE3A03000, +0xE1A02001, +0xE15200A0, +0x91A02082, +0x3AFFFFFC, +0xE1500002, +0xE0A33003, +0x20400002, +0xE1320001, +0x11A020A2, +0x1AFFFFF9, +0xE0811003, +0xE1B010A1, +0xE1510004, +0x3AFFFFEE, +0xE1A00004, +0xE8BD0010, +0xE12FFF1E, +0xE0010090, +0xE1A01741, +0xE2611000, +0xE3A030A9, +0xE0030391, +0xE1A03743, +0xE2833E39, +0xE0030391, +0xE1A03743, +0xE2833C09, +0xE283301C, +0xE0030391, +0xE1A03743, +0xE2833C0F, +0xE28330B6, +0xE0030391, +0xE1A03743, +0xE2833C16, +0xE28330AA, +0xE0030391, +0xE1A03743, +0xE2833A02, +0xE2833081, +0xE0030391, +0xE1A03743, +0xE2833C36, +0xE2833051, +0xE0030391, +0xE1A03743, +0xE2833CA2, +0xE28330F9, +0xE0000093, +0xE1A00840, +0xE12FFF1E, +0xE3A00001, +0xE3A01001, +0xE92D4010, +0xE3A03000, +0xE3A04001, +0xE3500000, +0x1B000004, +0xE5CC3301, +0xEB000002, +0x0AFFFFFC, +0xE8BD4010, +0xE12FFF1E, +0xE3A0C301, +0xE5CC3208, +0xE15C20B8, +0xE0110002, +0x10222000, +0x114C20B8, +0xE5CC4208, +0xE12FFF1E, +0xE92D500F, +0xE3A00301, +0xE1A0E00F, +0xE510F004, +0xE8BD500F, +0xE25EF004, +0xE59FD044, +0xE92D5000, +0xE14FC000, +0xE10FE000, +0xE92D5000, +0xE3A0C302, +0xE5DCE09C, +0xE35E00A5, +0x1A000004, +0x05DCE0B4, +0x021EE080, +0xE28FE004, +0x159FF018, +0x059FF018, +0xE59FD018, +0xE8BD5000, +0xE169F00C, +0xE8BD5000, +0xE25EF004, +0x03007FF0, +0x09FE2000, +0x09FFC000, +0x03007FE0 +}; + +inline int CPUUpdateTicks(GBASystem * gba) +{ + int cpuLoopTicks = gba->lcdTicks; + + if(gba->soundTicks < cpuLoopTicks) + cpuLoopTicks = gba->soundTicks; + + if(gba->timer0On && (gba->timer0Ticks < cpuLoopTicks)) { + cpuLoopTicks = gba->timer0Ticks; + } + if(gba->timer1On && !(gba->TM1CNT & 4) && (gba->timer1Ticks < cpuLoopTicks)) { + cpuLoopTicks = gba->timer1Ticks; + } + if(gba->timer2On && !(gba->TM2CNT & 4) && (gba->timer2Ticks < cpuLoopTicks)) { + cpuLoopTicks = gba->timer2Ticks; + } + if(gba->timer3On && !(gba->TM3CNT & 4) && (gba->timer3Ticks < cpuLoopTicks)) { + cpuLoopTicks = gba->timer3Ticks; + } + + if (gba->SWITicks) { + if (gba->SWITicks < cpuLoopTicks) + cpuLoopTicks = gba->SWITicks; + } + + if (gba->IRQTicks) { + if (gba->IRQTicks < cpuLoopTicks) + cpuLoopTicks = gba->IRQTicks; + } + + return cpuLoopTicks; +} + +void CPUCleanUp(GBASystem * gba) +{ + if(gba->rom != NULL) { + free(gba->rom); + gba->rom = NULL; + } + + if(gba->vram != NULL) { + free(gba->vram); + gba->vram = NULL; + } + + if(gba->paletteRAM != NULL) { + free(gba->paletteRAM); + gba->paletteRAM = NULL; + } + + if(gba->internalRAM != NULL) { + free(gba->internalRAM); + gba->internalRAM = NULL; + } + + if(gba->workRAM != NULL) { + free(gba->workRAM); + gba->workRAM = NULL; + } + + if(gba->bios != NULL) { + free(gba->bios); + gba->bios = NULL; + } + + if(gba->oam != NULL) { + free(gba->oam); + gba->oam = NULL; + } + + if(gba->ioMem != NULL) { + free(gba->ioMem); + gba->ioMem = NULL; + } +} + +int CPULoadRom(GBASystem *gba, const void *rom, u32 size) +{ + gba->romSize = 0x2000000; + if(gba->rom != NULL) { + CPUCleanUp(gba); + } + + gba->rom = (u8 *)malloc(0x2000000); + if(gba->rom == NULL) { + return 0; + } + gba->workRAM = (u8 *)calloc(1, 0x40000); + if(gba->workRAM == NULL) { + return 0; + } + + if (gba->cpuIsMultiBoot) + { + if ( size > 0x40000 ) size = 0x40000; + memcpy( gba->workRAM, rom, size ); + gba->romSize = size; + } + else + { + if ( size > 0x2000000 ) size = 0x2000000; + memcpy( gba->rom, rom, size ); + gba->romSize = size; + } + + u16 *temp = (u16 *)(gba->rom+((gba->romSize+1)&~1)); + int i; + for(i = (gba->romSize+1)&~1; i < 0x2000000; i+=2) { + WRITE16LE(temp, (i >> 1) & 0xFFFF); + temp++; + } + + gba->bios = (u8 *)calloc(1,0x4000); + if(gba->bios == NULL) { + CPUCleanUp(gba); + return 0; + } + gba->internalRAM = (u8 *)calloc(1,0x8000); + if(gba->internalRAM == NULL) { + CPUCleanUp(gba); + return 0; + } + gba->paletteRAM = (u8 *)calloc(1,0x400); + if(gba->paletteRAM == NULL) { + CPUCleanUp(gba); + return 0; + } + gba->vram = (u8 *)calloc(1, 0x20000); + if(gba->vram == NULL) { + CPUCleanUp(gba); + return 0; + } + gba->oam = (u8 *)calloc(1, 0x400); + if(gba->oam == NULL) { + CPUCleanUp(gba); + return 0; + } + gba->ioMem = (u8 *)calloc(1, 0x400); + if(gba->ioMem == NULL) { + CPUCleanUp(gba); + return 0; + } + + return gba->romSize; +} + +void doMirroring (GBASystem *gba, bool b) +{ + u32 mirroredRomSize = (((gba->romSize)>>20) & 0x3F)<<20; + u32 mirroredRomAddress = gba->romSize; + if ((mirroredRomSize <=0x800000) && (b)) + { + mirroredRomAddress = mirroredRomSize; + if (mirroredRomSize==0) + mirroredRomSize=0x100000; + while (mirroredRomAddress<0x01000000) + { + memcpy ((u16 *)(gba->rom+mirroredRomAddress), (u16 *)(gba->rom), mirroredRomSize); + mirroredRomAddress+=mirroredRomSize; + } + } +} + +void CPUUpdateCPSR(GBASystem *gba) +{ + u32 CPSR = gba->reg[16].I & 0x40; + if(gba->N_FLAG) + CPSR |= 0x80000000; + if(gba->Z_FLAG) + CPSR |= 0x40000000; + if(gba->C_FLAG) + CPSR |= 0x20000000; + if(gba->V_FLAG) + CPSR |= 0x10000000; + if(!gba->armState) + CPSR |= 0x00000020; + if(!gba->armIrqEnable) + CPSR |= 0x80; + CPSR |= (gba->armMode & 0x1F); + gba->reg[16].I = CPSR; +} + +void CPUUpdateFlags(GBASystem *gba, bool breakLoop) +{ + u32 CPSR = gba->reg[16].I; + + gba->N_FLAG = (CPSR & 0x80000000) ? true: false; + gba->Z_FLAG = (CPSR & 0x40000000) ? true: false; + gba->C_FLAG = (CPSR & 0x20000000) ? true: false; + gba->V_FLAG = (CPSR & 0x10000000) ? true: false; + gba->armState = (CPSR & 0x20) ? false : true; + gba->armIrqEnable = (CPSR & 0x80) ? false : true; + if(breakLoop) { + if (gba->armIrqEnable && (gba->IF & gba->IE) && (gba->IME & 1)) + gba->cpuNextEvent = gba->cpuTotalTicks; + } +} + +void CPUUpdateFlags(GBASystem *gba) +{ + CPUUpdateFlags(gba, true); +} + +#ifdef WORDS_BIGENDIAN +static void CPUSwap(volatile u32 *a, volatile u32 *b) +{ + volatile u32 c = *b; + *b = *a; + *a = c; +} +#else +static void CPUSwap(u32 *a, u32 *b) +{ + u32 c = *b; + *b = *a; + *a = c; +} +#endif + +void CPUSwitchMode(GBASystem *gba, int mode, bool saveState, bool breakLoop) +{ + // if(armMode == mode) + // return; + + CPUUpdateCPSR(gba); + + switch(gba->armMode) { + case 0x10: + case 0x1F: + gba->reg[R13_USR].I = gba->reg[13].I; + gba->reg[R14_USR].I = gba->reg[14].I; + gba->reg[17].I = gba->reg[16].I; + break; + case 0x11: + CPUSwap(&gba->reg[R8_FIQ].I, &gba->reg[8].I); + CPUSwap(&gba->reg[R9_FIQ].I, &gba->reg[9].I); + CPUSwap(&gba->reg[R10_FIQ].I, &gba->reg[10].I); + CPUSwap(&gba->reg[R11_FIQ].I, &gba->reg[11].I); + CPUSwap(&gba->reg[R12_FIQ].I, &gba->reg[12].I); + gba->reg[R13_FIQ].I = gba->reg[13].I; + gba->reg[R14_FIQ].I = gba->reg[14].I; + gba->reg[SPSR_FIQ].I = gba->reg[17].I; + break; + case 0x12: + gba->reg[R13_IRQ].I = gba->reg[13].I; + gba->reg[R14_IRQ].I = gba->reg[14].I; + gba->reg[SPSR_IRQ].I = gba->reg[17].I; + break; + case 0x13: + gba->reg[R13_SVC].I = gba->reg[13].I; + gba->reg[R14_SVC].I = gba->reg[14].I; + gba->reg[SPSR_SVC].I = gba->reg[17].I; + break; + case 0x17: + gba->reg[R13_ABT].I = gba->reg[13].I; + gba->reg[R14_ABT].I = gba->reg[14].I; + gba->reg[SPSR_ABT].I = gba->reg[17].I; + break; + case 0x1b: + gba->reg[R13_UND].I = gba->reg[13].I; + gba->reg[R14_UND].I = gba->reg[14].I; + gba->reg[SPSR_UND].I = gba->reg[17].I; + break; + } + + u32 CPSR = gba->reg[16].I; + u32 SPSR = gba->reg[17].I; + + switch(mode) { + case 0x10: + case 0x1F: + gba->reg[13].I = gba->reg[R13_USR].I; + gba->reg[14].I = gba->reg[R14_USR].I; + gba->reg[16].I = SPSR; + break; + case 0x11: + CPUSwap(&gba->reg[8].I, &gba->reg[R8_FIQ].I); + CPUSwap(&gba->reg[9].I, &gba->reg[R9_FIQ].I); + CPUSwap(&gba->reg[10].I, &gba->reg[R10_FIQ].I); + CPUSwap(&gba->reg[11].I, &gba->reg[R11_FIQ].I); + CPUSwap(&gba->reg[12].I, &gba->reg[R12_FIQ].I); + gba->reg[13].I = gba->reg[R13_FIQ].I; + gba->reg[14].I = gba->reg[R14_FIQ].I; + if(saveState) + gba->reg[17].I = CPSR; + else + gba->reg[17].I = gba->reg[SPSR_FIQ].I; + break; + case 0x12: + gba->reg[13].I = gba->reg[R13_IRQ].I; + gba->reg[14].I = gba->reg[R14_IRQ].I; + gba->reg[16].I = SPSR; + if(saveState) + gba->reg[17].I = CPSR; + else + gba->reg[17].I = gba->reg[SPSR_IRQ].I; + break; + case 0x13: + gba->reg[13].I = gba->reg[R13_SVC].I; + gba->reg[14].I = gba->reg[R14_SVC].I; + gba->reg[16].I = SPSR; + if(saveState) + gba->reg[17].I = CPSR; + else + gba->reg[17].I = gba->reg[SPSR_SVC].I; + break; + case 0x17: + gba->reg[13].I = gba->reg[R13_ABT].I; + gba->reg[14].I = gba->reg[R14_ABT].I; + gba->reg[16].I = SPSR; + if(saveState) + gba->reg[17].I = CPSR; + else + gba->reg[17].I = gba->reg[SPSR_ABT].I; + break; + case 0x1b: + gba->reg[13].I = gba->reg[R13_UND].I; + gba->reg[14].I = gba->reg[R14_UND].I; + gba->reg[16].I = SPSR; + if(saveState) + gba->reg[17].I = CPSR; + else + gba->reg[17].I = gba->reg[SPSR_UND].I; + break; + default: + break; + } + gba->armMode = mode; + CPUUpdateFlags(gba, breakLoop); + CPUUpdateCPSR(gba); +} + +void CPUSwitchMode(GBASystem *gba, int mode, bool saveState) +{ + CPUSwitchMode(gba, mode, saveState, true); +} + +void CPUUndefinedException(GBASystem *gba) +{ + u32 PC = gba->reg[15].I; + bool savedArmState = gba->armState; + CPUSwitchMode(gba, 0x1b, true, false); + gba->reg[14].I = PC - (savedArmState ? 4 : 2); + gba->reg[15].I = 0x04; + gba->armState = true; + gba->armIrqEnable = false; + gba->armNextPC = 0x04; + ARM_PREFETCH; + gba->reg[15].I += 4; +} + +void CPUSoftwareInterrupt(GBASystem *gba) +{ + u32 PC = gba->reg[15].I; + bool savedArmState = gba->armState; + CPUSwitchMode(gba, 0x13, true, false); + gba->reg[14].I = PC - (savedArmState ? 4 : 2); + gba->reg[15].I = 0x08; + gba->armState = true; + gba->armIrqEnable = false; + gba->armNextPC = 0x08; + ARM_PREFETCH; + gba->reg[15].I += 4; +} + +void CPUSoftwareInterrupt(GBASystem *gba, int comment) +{ + if(gba->armState) comment >>= 16; + if(comment == 0xfa) { + return; + } + if(gba->useBios) { + CPUSoftwareInterrupt(gba); + return; + } + switch(comment) { + case 0x00: + BIOS_SoftReset(gba); + ARM_PREFETCH; + break; + case 0x01: + BIOS_RegisterRamReset(gba); + break; + case 0x02: + gba->holdState = true; + gba->holdType = -1; + gba->cpuNextEvent = gba->cpuTotalTicks; + break; + case 0x03: + gba->holdState = true; + gba->holdType = -1; + gba->stopState = true; + gba->cpuNextEvent = gba->cpuTotalTicks; + break; + case 0x04: + CPUSoftwareInterrupt(gba); + break; + case 0x05: + CPUSoftwareInterrupt(gba); + break; + case 0x06: + CPUSoftwareInterrupt(gba); + break; + case 0x07: + CPUSoftwareInterrupt(gba); + break; + case 0x08: + BIOS_Sqrt(gba); + break; + case 0x09: + BIOS_ArcTan(gba); + break; + case 0x0A: + BIOS_ArcTan2(gba); + break; + case 0x0B: + { + int len = (gba->reg[2].I & 0x1FFFFF) >>1; + if (!(((gba->reg[0].I & 0xe000000) == 0) || + ((gba->reg[0].I + len) & 0xe000000) == 0)) + { + if ((gba->reg[2].I >> 24) & 1) + { + if ((gba->reg[2].I >> 26) & 1) + gba->SWITicks = (7 + gba->memoryWait32[(gba->reg[1].I>>24) & 0xF]) * (len>>1); + else + gba->SWITicks = (8 + gba->memoryWait[(gba->reg[1].I>>24) & 0xF]) * (len); + } + else + { + if ((gba->reg[2].I >> 26) & 1) + gba->SWITicks = (10 + gba->memoryWait32[(gba->reg[0].I>>24) & 0xF] + + gba->memoryWait32[(gba->reg[1].I>>24) & 0xF]) * (len>>1); + else + gba->SWITicks = (11 + gba->memoryWait[(gba->reg[0].I>>24) & 0xF] + + gba->memoryWait[(gba->reg[1].I>>24) & 0xF]) * len; + } + } + } + BIOS_CpuSet(gba); + break; + case 0x0C: + { + int len = (gba->reg[2].I & 0x1FFFFF) >>5; + if (!(((gba->reg[0].I & 0xe000000) == 0) || + ((gba->reg[0].I + len) & 0xe000000) == 0)) + { + if ((gba->reg[2].I >> 24) & 1) + gba->SWITicks = (6 + gba->memoryWait32[(gba->reg[1].I>>24) & 0xF] + + 7 * (gba->memoryWaitSeq32[(gba->reg[1].I>>24) & 0xF] + 1)) * len; + else + gba->SWITicks = (9 + gba->memoryWait32[(gba->reg[0].I>>24) & 0xF] + + gba->memoryWait32[(gba->reg[1].I>>24) & 0xF] + + 7 * (gba->memoryWaitSeq32[(gba->reg[0].I>>24) & 0xF] + + gba->memoryWaitSeq32[(gba->reg[1].I>>24) & 0xF] + 2)) * len; + } + } + BIOS_CpuFastSet(gba); + break; + case 0x0D: + BIOS_GetBiosChecksum(gba); + break; + case 0x0E: + BIOS_BgAffineSet(gba); + break; + case 0x0F: + BIOS_ObjAffineSet(gba); + break; + case 0x10: + { + int len = CPUReadHalfWord(gba, gba->reg[2].I); + if (!(((gba->reg[0].I & 0xe000000) == 0) || + ((gba->reg[0].I + len) & 0xe000000) == 0)) + gba->SWITicks = (32 + gba->memoryWait[(gba->reg[0].I>>24) & 0xF]) * len; + } + BIOS_BitUnPack(gba); + break; + case 0x11: + { + u32 len = CPUReadMemory(gba, gba->reg[0].I) >> 8; + if(!(((gba->reg[0].I & 0xe000000) == 0) || + ((gba->reg[0].I + (len & 0x1fffff)) & 0xe000000) == 0)) + gba->SWITicks = (9 + gba->memoryWait[(gba->reg[1].I>>24) & 0xF]) * len; + } + BIOS_LZ77UnCompWram(gba); + break; + case 0x12: + { + u32 len = CPUReadMemory(gba, gba->reg[0].I) >> 8; + if(!(((gba->reg[0].I & 0xe000000) == 0) || + ((gba->reg[0].I + (len & 0x1fffff)) & 0xe000000) == 0)) + gba->SWITicks = (19 + gba->memoryWait[(gba->reg[1].I>>24) & 0xF]) * len; + } + BIOS_LZ77UnCompVram(gba); + break; + case 0x13: + { + u32 len = CPUReadMemory(gba, gba->reg[0].I) >> 8; + if(!(((gba->reg[0].I & 0xe000000) == 0) || + ((gba->reg[0].I + (len & 0x1fffff)) & 0xe000000) == 0)) + gba->SWITicks = (29 + (gba->memoryWait[(gba->reg[0].I>>24) & 0xF]<<1)) * len; + } + BIOS_HuffUnComp(gba); + break; + case 0x14: + { + u32 len = CPUReadMemory(gba, gba->reg[0].I) >> 8; + if(!(((gba->reg[0].I & 0xe000000) == 0) || + ((gba->reg[0].I + (len & 0x1fffff)) & 0xe000000) == 0)) + gba->SWITicks = (11 + gba->memoryWait[(gba->reg[0].I>>24) & 0xF] + + gba->memoryWait[(gba->reg[1].I>>24) & 0xF]) * len; + } + BIOS_RLUnCompWram(gba); + break; + case 0x15: + { + u32 len = CPUReadMemory(gba, gba->reg[0].I) >> 9; + if(!(((gba->reg[0].I & 0xe000000) == 0) || + ((gba->reg[0].I + (len & 0x1fffff)) & 0xe000000) == 0)) + gba->SWITicks = (34 + (gba->memoryWait[(gba->reg[0].I>>24) & 0xF] << 1) + + gba->memoryWait[(gba->reg[1].I>>24) & 0xF]) * len; + } + BIOS_RLUnCompVram(gba); + break; + case 0x16: + { + u32 len = CPUReadMemory(gba, gba->reg[0].I) >> 8; + if(!(((gba->reg[0].I & 0xe000000) == 0) || + ((gba->reg[0].I + (len & 0x1fffff)) & 0xe000000) == 0)) + gba->SWITicks = (13 + gba->memoryWait[(gba->reg[0].I>>24) & 0xF] + + gba->memoryWait[(gba->reg[1].I>>24) & 0xF]) * len; + } + BIOS_Diff8bitUnFilterWram(gba); + break; + case 0x17: + { + u32 len = CPUReadMemory(gba, gba->reg[0].I) >> 9; + if(!(((gba->reg[0].I & 0xe000000) == 0) || + ((gba->reg[0].I + (len & 0x1fffff)) & 0xe000000) == 0)) + gba->SWITicks = (39 + (gba->memoryWait[(gba->reg[0].I>>24) & 0xF]<<1) + + gba->memoryWait[(gba->reg[1].I>>24) & 0xF]) * len; + } + BIOS_Diff8bitUnFilterVram(gba); + break; + case 0x18: + { + u32 len = CPUReadMemory(gba, gba->reg[0].I) >> 9; + if(!(((gba->reg[0].I & 0xe000000) == 0) || + ((gba->reg[0].I + (len & 0x1fffff)) & 0xe000000) == 0)) + gba->SWITicks = (13 + gba->memoryWait[(gba->reg[0].I>>24) & 0xF] + + gba->memoryWait[(gba->reg[1].I>>24) & 0xF]) * len; + } + BIOS_Diff16bitUnFilter(gba); + break; + case 0x19: + if(gba->reg[0].I) + soundPause(gba); + else + soundResume(gba); + break; + case 0x1F: + BIOS_MidiKey2Freq(gba); + break; + case 0x2A: + BIOS_SndDriverJmpTableCopy(gba); + default: + break; + } +} + +void CPUCompareVCOUNT(GBASystem *gba) +{ + if(gba->VCOUNT == (gba->DISPSTAT >> 8)) { + gba->DISPSTAT |= 4; + UPDATE_REG(0x04, gba->DISPSTAT); + + if(gba->DISPSTAT & 0x20) { + gba->IF |= 4; + UPDATE_REG(0x202, gba->IF); + } + } else { + gba->DISPSTAT &= 0xFFFB; + UPDATE_REG(0x4, gba->DISPSTAT); + } + if (gba->layerEnableDelay>0) + { + gba->layerEnableDelay--; + if (gba->layerEnableDelay==1) + gba->layerEnable = gba->layerSettings & gba->DISPCNT; + } + +} + +void doDMA(GBASystem *gba, u32 &s, u32 &d, u32 si, u32 di, u32 c, int transfer32) +{ + int sm = s >> 24; + int dm = d >> 24; + int sw = 0; + int dw = 0; + int sc = c; + + gba->cpuDmaCount = c; + // This is done to get the correct waitstates. + if (sm>15) + sm=15; + if (dm>15) + dm=15; + + //if ((sm>=0x05) && (sm<=0x07) || (dm>=0x05) && (dm <=0x07)) + // blank = (((DISPSTAT | ((DISPSTAT>>1)&1))==1) ? true : false); + + if(transfer32) { + s &= 0xFFFFFFFC; + if(s < 0x02000000 && (gba->reg[15].I >> 24)) { + while(c != 0) { + CPUWriteMemory(gba, d, 0); + d += di; + c--; + } + } else { + while(c != 0) { + gba->cpuDmaLast = CPUReadMemory(gba, s); + CPUWriteMemory(gba, d, gba->cpuDmaLast); + d += di; + s += si; + c--; + } + } + } else { + s &= 0xFFFFFFFE; + si = (int)si >> 1; + di = (int)di >> 1; + if(s < 0x02000000 && (gba->reg[15].I >> 24)) { + while(c != 0) { + CPUWriteHalfWord(gba, d, 0); + d += di; + c--; + } + } else { + while(c != 0) { + gba->cpuDmaLast = CPUReadHalfWord(gba, s); + CPUWriteHalfWord(gba, d, gba->cpuDmaLast); + gba->cpuDmaLast |= (gba->cpuDmaLast<<16); + d += di; + s += si; + c--; + } + } + } + + gba->cpuDmaCount = 0; + + int totalTicks = 0; + + if(transfer32) { + sw =1+gba->memoryWaitSeq32[sm & 15]; + dw =1+gba->memoryWaitSeq32[dm & 15]; + totalTicks = (sw+dw)*(sc-1) + 6 + gba->memoryWait32[sm & 15] + + gba->memoryWaitSeq32[dm & 15]; + } + else + { + sw = 1+gba->memoryWaitSeq[sm & 15]; + dw = 1+gba->memoryWaitSeq[dm & 15]; + totalTicks = (sw+dw)*(sc-1) + 6 + gba->memoryWait[sm & 15] + + gba->memoryWaitSeq[dm & 15]; + } + + gba->cpuDmaTicksToUpdate += totalTicks; + +} + +void CPUCheckDMA(GBASystem *gba, int reason, int dmamask) +{ + // DMA 0 + if((gba->DM0CNT_H & 0x8000) && (dmamask & 1)) { + if(((gba->DM0CNT_H >> 12) & 3) == reason) { + u32 sourceIncrement = 4; + u32 destIncrement = 4; + switch((gba->DM0CNT_H >> 7) & 3) { + case 0: + break; + case 1: + sourceIncrement = (u32)-4; + break; + case 2: + sourceIncrement = 0; + break; + } + switch((gba->DM0CNT_H >> 5) & 3) { + case 0: + break; + case 1: + destIncrement = (u32)-4; + break; + case 2: + destIncrement = 0; + break; + } + doDMA(gba, gba->dma0Source, gba->dma0Dest, sourceIncrement, destIncrement, + gba->DM0CNT_L ? gba->DM0CNT_L : 0x4000, + gba->DM0CNT_H & 0x0400); + gba->cpuDmaHack = true; + + if(gba->DM0CNT_H & 0x4000) { + gba->IF |= 0x0100; + UPDATE_REG(0x202, gba->IF); + gba->cpuNextEvent = gba->cpuTotalTicks; + } + + if(((gba->DM0CNT_H >> 5) & 3) == 3) { + gba->dma0Dest = gba->DM0DAD_L | (gba->DM0DAD_H << 16); + } + + if(!(gba->DM0CNT_H & 0x0200) || (reason == 0)) { + gba->DM0CNT_H &= 0x7FFF; + UPDATE_REG(0xBA, gba->DM0CNT_H); + } + } + } + + // DMA 1 + if((gba->DM1CNT_H & 0x8000) && (dmamask & 2)) { + if(((gba->DM1CNT_H >> 12) & 3) == reason) { + u32 sourceIncrement = 4; + u32 destIncrement = 4; + switch((gba->DM1CNT_H >> 7) & 3) { + case 0: + break; + case 1: + sourceIncrement = (u32)-4; + break; + case 2: + sourceIncrement = 0; + break; + } + switch((gba->DM1CNT_H >> 5) & 3) { + case 0: + break; + case 1: + destIncrement = (u32)-4; + break; + case 2: + destIncrement = 0; + break; + } + if(reason == 3) { + doDMA(gba, gba->dma1Source, gba->dma1Dest, sourceIncrement, 0, 4, + 0x0400); + } else { + doDMA(gba, gba->dma1Source, gba->dma1Dest, sourceIncrement, destIncrement, + gba->DM1CNT_L ? gba->DM1CNT_L : 0x4000, + gba->DM1CNT_H & 0x0400); + } + gba->cpuDmaHack = true; + + if(gba->DM1CNT_H & 0x4000) { + gba->IF |= 0x0200; + UPDATE_REG(0x202, gba->IF); + gba->cpuNextEvent = gba->cpuTotalTicks; + } + + if(((gba->DM1CNT_H >> 5) & 3) == 3) { + gba->dma1Dest = gba->DM1DAD_L | (gba->DM1DAD_H << 16); + } + + if(!(gba->DM1CNT_H & 0x0200) || (reason == 0)) { + gba->DM1CNT_H &= 0x7FFF; + UPDATE_REG(0xC6, gba->DM1CNT_H); + } + } + } + + // DMA 2 + if((gba->DM2CNT_H & 0x8000) && (dmamask & 4)) { + if(((gba->DM2CNT_H >> 12) & 3) == reason) { + u32 sourceIncrement = 4; + u32 destIncrement = 4; + switch((gba->DM2CNT_H >> 7) & 3) { + case 0: + break; + case 1: + sourceIncrement = (u32)-4; + break; + case 2: + sourceIncrement = 0; + break; + } + switch((gba->DM2CNT_H >> 5) & 3) { + case 0: + break; + case 1: + destIncrement = (u32)-4; + break; + case 2: + destIncrement = 0; + break; + } + if(reason == 3) { + doDMA(gba, gba->dma2Source, gba->dma2Dest, sourceIncrement, 0, 4, + 0x0400); + } else { + doDMA(gba, gba->dma2Source, gba->dma2Dest, sourceIncrement, destIncrement, + gba->DM2CNT_L ? gba->DM2CNT_L : 0x4000, + gba->DM2CNT_H & 0x0400); + } + gba->cpuDmaHack = true; + + if(gba->DM2CNT_H & 0x4000) { + gba->IF |= 0x0400; + UPDATE_REG(0x202, gba->IF); + gba->cpuNextEvent = gba->cpuTotalTicks; + } + + if(((gba->DM2CNT_H >> 5) & 3) == 3) { + gba->dma2Dest = gba->DM2DAD_L | (gba->DM2DAD_H << 16); + } + + if(!(gba->DM2CNT_H & 0x0200) || (reason == 0)) { + gba->DM2CNT_H &= 0x7FFF; + UPDATE_REG(0xD2, gba->DM2CNT_H); + } + } + } + + // DMA 3 + if((gba->DM3CNT_H & 0x8000) && (dmamask & 8)) { + if(((gba->DM3CNT_H >> 12) & 3) == reason) { + u32 sourceIncrement = 4; + u32 destIncrement = 4; + switch((gba->DM3CNT_H >> 7) & 3) { + case 0: + break; + case 1: + sourceIncrement = (u32)-4; + break; + case 2: + sourceIncrement = 0; + break; + } + switch((gba->DM3CNT_H >> 5) & 3) { + case 0: + break; + case 1: + destIncrement = (u32)-4; + break; + case 2: + destIncrement = 0; + break; + } + doDMA(gba, gba->dma3Source, gba->dma3Dest, sourceIncrement, destIncrement, + gba->DM3CNT_L ? gba->DM3CNT_L : 0x10000, + gba->DM3CNT_H & 0x0400); + if(gba->DM3CNT_H & 0x4000) { + gba->IF |= 0x0800; + UPDATE_REG(0x202, gba->IF); + gba->cpuNextEvent = gba->cpuTotalTicks; + } + + if(((gba->DM3CNT_H >> 5) & 3) == 3) { + gba->dma3Dest = gba->DM3DAD_L | (gba->DM3DAD_H << 16); + } + + if(!(gba->DM3CNT_H & 0x0200) || (reason == 0)) { + gba->DM3CNT_H &= 0x7FFF; + UPDATE_REG(0xDE, gba->DM3CNT_H); + } + } + } +} + +void CPUUpdateRegister(GBASystem *gba, u32 address, u16 value) +{ + switch(address) + { + case 0x00: + { // we need to place the following code in { } because we declare & initialize variables in a case statement + if((value & 7) > 5) { + // display modes above 0-5 are prohibited + gba->DISPCNT = (value & 7); + } + bool change = (0 != ((gba->DISPCNT ^ value) & 0x80)); + bool changeBG = (0 != ((gba->DISPCNT ^ value) & 0x0F00)); + u16 changeBGon = ((~gba->DISPCNT) & value) & 0x0F00; // these layers are being activated + + gba->DISPCNT = (value & 0xFFF7); // bit 3 can only be accessed by the BIOS to enable GBC mode + UPDATE_REG(0x00, gba->DISPCNT); + + if(changeBGon) { + gba->layerEnableDelay = 4; + gba->layerEnable = gba->layerSettings & value & (~changeBGon); + } else { + gba->layerEnable = gba->layerSettings & value; + // CPUUpdateTicks(); + } + + gba->windowOn = (gba->layerEnable & 0x6000) ? true : false; + if(change && !((value & 0x80))) { + if(!(gba->DISPSTAT & 1)) { + gba->lcdTicks = 1008; + // VCOUNT = 0; + // UPDATE_REG(0x06, VCOUNT); + gba->DISPSTAT &= 0xFFFC; + UPDATE_REG(0x04, gba->DISPSTAT); + CPUCompareVCOUNT(gba); + } + // (*renderLine)(); + } + // we only care about changes in BG0-BG3 + if(changeBG) { + } + break; + } + case 0x04: + gba->DISPSTAT = (value & 0xFF38) | (gba->DISPSTAT & 7); + UPDATE_REG(0x04, gba->DISPSTAT); + break; + case 0x06: + // not writable + break; + case 0x08: + gba->BG0CNT = (value & 0xDFCF); + UPDATE_REG(0x08, gba->BG0CNT); + break; + case 0x0A: + gba->BG1CNT = (value & 0xDFCF); + UPDATE_REG(0x0A, gba->BG1CNT); + break; + case 0x0C: + gba->BG2CNT = (value & 0xFFCF); + UPDATE_REG(0x0C, gba->BG2CNT); + break; + case 0x0E: + gba->BG3CNT = (value & 0xFFCF); + UPDATE_REG(0x0E, gba->BG3CNT); + break; + case 0x10: + gba->BG0HOFS = value & 511; + UPDATE_REG(0x10, gba->BG0HOFS); + break; + case 0x12: + gba->BG0VOFS = value & 511; + UPDATE_REG(0x12, gba->BG0VOFS); + break; + case 0x14: + gba->BG1HOFS = value & 511; + UPDATE_REG(0x14, gba->BG1HOFS); + break; + case 0x16: + gba->BG1VOFS = value & 511; + UPDATE_REG(0x16, gba->BG1VOFS); + break; + case 0x18: + gba->BG2HOFS = value & 511; + UPDATE_REG(0x18, gba->BG2HOFS); + break; + case 0x1A: + gba->BG2VOFS = value & 511; + UPDATE_REG(0x1A, gba->BG2VOFS); + break; + case 0x1C: + gba->BG3HOFS = value & 511; + UPDATE_REG(0x1C, gba->BG3HOFS); + break; + case 0x1E: + gba->BG3VOFS = value & 511; + UPDATE_REG(0x1E, gba->BG3VOFS); + break; + case 0x20: + gba->BG2PA = value; + UPDATE_REG(0x20, gba->BG2PA); + break; + case 0x22: + gba->BG2PB = value; + UPDATE_REG(0x22, gba->BG2PB); + break; + case 0x24: + gba->BG2PC = value; + UPDATE_REG(0x24, gba->BG2PC); + break; + case 0x26: + gba->BG2PD = value; + UPDATE_REG(0x26, gba->BG2PD); + break; + case 0x28: + gba->BG2X_L = value; + UPDATE_REG(0x28, gba->BG2X_L); + gba->gfxBG2Changed |= 1; + break; + case 0x2A: + gba->BG2X_H = (value & 0xFFF); + UPDATE_REG(0x2A, gba->BG2X_H); + gba->gfxBG2Changed |= 1; + break; + case 0x2C: + gba->BG2Y_L = value; + UPDATE_REG(0x2C, gba->BG2Y_L); + gba->gfxBG2Changed |= 2; + break; + case 0x2E: + gba->BG2Y_H = value & 0xFFF; + UPDATE_REG(0x2E, gba->BG2Y_H); + gba->gfxBG2Changed |= 2; + break; + case 0x30: + gba->BG3PA = value; + UPDATE_REG(0x30, gba->BG3PA); + break; + case 0x32: + gba->BG3PB = value; + UPDATE_REG(0x32, gba->BG3PB); + break; + case 0x34: + gba->BG3PC = value; + UPDATE_REG(0x34, gba->BG3PC); + break; + case 0x36: + gba->BG3PD = value; + UPDATE_REG(0x36, gba->BG3PD); + break; + case 0x38: + gba->BG3X_L = value; + UPDATE_REG(0x38, gba->BG3X_L); + gba->gfxBG3Changed |= 1; + break; + case 0x3A: + gba->BG3X_H = value & 0xFFF; + UPDATE_REG(0x3A, gba->BG3X_H); + gba->gfxBG3Changed |= 1; + break; + case 0x3C: + gba->BG3Y_L = value; + UPDATE_REG(0x3C, gba->BG3Y_L); + gba->gfxBG3Changed |= 2; + break; + case 0x3E: + gba->BG3Y_H = value & 0xFFF; + UPDATE_REG(0x3E, gba->BG3Y_H); + gba->gfxBG3Changed |= 2; + break; + case 0x40: + gba->WIN0H = value; + UPDATE_REG(0x40, gba->WIN0H); + break; + case 0x42: + gba->WIN1H = value; + UPDATE_REG(0x42, gba->WIN1H); + break; + case 0x44: + gba->WIN0V = value; + UPDATE_REG(0x44, gba->WIN0V); + break; + case 0x46: + gba->WIN1V = value; + UPDATE_REG(0x46, gba->WIN1V); + break; + case 0x48: + gba->WININ = value & 0x3F3F; + UPDATE_REG(0x48, gba->WININ); + break; + case 0x4A: + gba->WINOUT = value & 0x3F3F; + UPDATE_REG(0x4A, gba->WINOUT); + break; + case 0x4C: + gba->MOSAIC = value; + UPDATE_REG(0x4C, gba->MOSAIC); + break; + case 0x50: + gba->BLDMOD = value & 0x3FFF; + UPDATE_REG(0x50, gba->BLDMOD); + gba->fxOn = ((gba->BLDMOD>>6)&3) != 0; + break; + case 0x52: + gba->COLEV = value & 0x1F1F; + UPDATE_REG(0x52, gba->COLEV); + break; + case 0x54: + gba->COLY = value & 0x1F; + UPDATE_REG(0x54, gba->COLY); + break; + case 0x60: + case 0x62: + case 0x64: + case 0x68: + case 0x6c: + case 0x70: + case 0x72: + case 0x74: + case 0x78: + case 0x7c: + case 0x80: + case 0x84: + soundEvent(gba, address&0xFF, (u8)(value & 0xFF)); + soundEvent(gba, (address&0xFF)+1, (u8)(value>>8)); + break; + case 0x82: + case 0x88: + case 0xa0: + case 0xa2: + case 0xa4: + case 0xa6: + case 0x90: + case 0x92: + case 0x94: + case 0x96: + case 0x98: + case 0x9a: + case 0x9c: + case 0x9e: + soundEvent(gba, address&0xFF, value); + break; + case 0xB0: + gba->DM0SAD_L = value; + UPDATE_REG(0xB0, gba->DM0SAD_L); + break; + case 0xB2: + gba->DM0SAD_H = value & 0x07FF; + UPDATE_REG(0xB2, gba->DM0SAD_H); + break; + case 0xB4: + gba->DM0DAD_L = value; + UPDATE_REG(0xB4, gba->DM0DAD_L); + break; + case 0xB6: + gba->DM0DAD_H = value & 0x07FF; + UPDATE_REG(0xB6, gba->DM0DAD_H); + break; + case 0xB8: + gba->DM0CNT_L = value & 0x3FFF; + UPDATE_REG(0xB8, 0); + break; + case 0xBA: + { + bool start = ((gba->DM0CNT_H ^ value) & 0x8000) ? true : false; + value &= 0xF7E0; + + gba->DM0CNT_H = value; + UPDATE_REG(0xBA, gba->DM0CNT_H); + + if(start && (value & 0x8000)) { + gba->dma0Source = gba->DM0SAD_L | (gba->DM0SAD_H << 16); + gba->dma0Dest = gba->DM0DAD_L | (gba->DM0DAD_H << 16); + CPUCheckDMA(gba, 0, 1); + } + } + break; + case 0xBC: + gba->DM1SAD_L = value; + UPDATE_REG(0xBC, gba->DM1SAD_L); + break; + case 0xBE: + gba->DM1SAD_H = value & 0x0FFF; + UPDATE_REG(0xBE, gba->DM1SAD_H); + break; + case 0xC0: + gba->DM1DAD_L = value; + UPDATE_REG(0xC0, gba->DM1DAD_L); + break; + case 0xC2: + gba->DM1DAD_H = value & 0x07FF; + UPDATE_REG(0xC2, gba->DM1DAD_H); + break; + case 0xC4: + gba->DM1CNT_L = value & 0x3FFF; + UPDATE_REG(0xC4, 0); + break; + case 0xC6: + { + bool start = ((gba->DM1CNT_H ^ value) & 0x8000) ? true : false; + value &= 0xF7E0; + + gba->DM1CNT_H = value; + UPDATE_REG(0xC6, gba->DM1CNT_H); + + if(start && (value & 0x8000)) { + gba->dma1Source = gba->DM1SAD_L | (gba->DM1SAD_H << 16); + gba->dma1Dest = gba->DM1DAD_L | (gba->DM1DAD_H << 16); + CPUCheckDMA(gba, 0, 2); + } + } + break; + case 0xC8: + gba->DM2SAD_L = value; + UPDATE_REG(0xC8, gba->DM2SAD_L); + break; + case 0xCA: + gba->DM2SAD_H = value & 0x0FFF; + UPDATE_REG(0xCA, gba->DM2SAD_H); + break; + case 0xCC: + gba->DM2DAD_L = value; + UPDATE_REG(0xCC, gba->DM2DAD_L); + break; + case 0xCE: + gba->DM2DAD_H = value & 0x07FF; + UPDATE_REG(0xCE, gba->DM2DAD_H); + break; + case 0xD0: + gba->DM2CNT_L = value & 0x3FFF; + UPDATE_REG(0xD0, 0); + break; + case 0xD2: + { + bool start = ((gba->DM2CNT_H ^ value) & 0x8000) ? true : false; + + value &= 0xF7E0; + + gba->DM2CNT_H = value; + UPDATE_REG(0xD2, gba->DM2CNT_H); + + if(start && (value & 0x8000)) { + gba->dma2Source = gba->DM2SAD_L | (gba->DM2SAD_H << 16); + gba->dma2Dest = gba->DM2DAD_L | (gba->DM2DAD_H << 16); + + CPUCheckDMA(gba, 0, 4); + } + } + break; + case 0xD4: + gba->DM3SAD_L = value; + UPDATE_REG(0xD4, gba->DM3SAD_L); + break; + case 0xD6: + gba->DM3SAD_H = value & 0x0FFF; + UPDATE_REG(0xD6, gba->DM3SAD_H); + break; + case 0xD8: + gba->DM3DAD_L = value; + UPDATE_REG(0xD8, gba->DM3DAD_L); + break; + case 0xDA: + gba->DM3DAD_H = value & 0x0FFF; + UPDATE_REG(0xDA, gba->DM3DAD_H); + break; + case 0xDC: + gba->DM3CNT_L = value; + UPDATE_REG(0xDC, 0); + break; + case 0xDE: + { + bool start = ((gba->DM3CNT_H ^ value) & 0x8000) ? true : false; + + value &= 0xFFE0; + + gba->DM3CNT_H = value; + UPDATE_REG(0xDE, gba->DM3CNT_H); + + if(start && (value & 0x8000)) { + gba->dma3Source = gba->DM3SAD_L | (gba->DM3SAD_H << 16); + gba->dma3Dest = gba->DM3DAD_L | (gba->DM3DAD_H << 16); + CPUCheckDMA(gba, 0, 8); + } + } + break; + case 0x100: + gba->timer0Reload = value; + break; + case 0x102: + gba->timer0Value = value; + gba->timerOnOffDelay|=1; + gba->cpuNextEvent = gba->cpuTotalTicks; + break; + case 0x104: + gba->timer1Reload = value; + break; + case 0x106: + gba->timer1Value = value; + gba->timerOnOffDelay|=2; + gba->cpuNextEvent = gba->cpuTotalTicks; + break; + case 0x108: + gba->timer2Reload = value; + break; + case 0x10A: + gba->timer2Value = value; + gba->timerOnOffDelay|=4; + gba->cpuNextEvent = gba->cpuTotalTicks; + break; + case 0x10C: + gba->timer3Reload = value; + break; + case 0x10E: + gba->timer3Value = value; + gba->timerOnOffDelay|=8; + gba->cpuNextEvent = gba->cpuTotalTicks; + break; + + case 0x130: + gba->P1 |= (value & 0x3FF); + UPDATE_REG(0x130, gba->P1); + break; + + case 0x132: + UPDATE_REG(0x132, value & 0xC3FF); + break; + + case 0x200: + gba->IE = value & 0x3FFF; + UPDATE_REG(0x200, gba->IE); + if ((gba->IME & 1) && (gba->IF & gba->IE) && gba->armIrqEnable) + gba->cpuNextEvent = gba->cpuTotalTicks; + break; + case 0x202: + gba->IF ^= (value & gba->IF); + UPDATE_REG(0x202, gba->IF); + break; + case 0x204: + { + gba->memoryWait[0x0e] = gba->memoryWaitSeq[0x0e] = gamepakRamWaitState[value & 3]; + + if(!gba->speedHack) { + gba->memoryWait[0x08] = gba->memoryWait[0x09] = gamepakWaitState[(value >> 2) & 3]; + gba->memoryWaitSeq[0x08] = gba->memoryWaitSeq[0x09] = + gamepakWaitState0[(value >> 4) & 1]; + + gba->memoryWait[0x0a] = gba->memoryWait[0x0b] = gamepakWaitState[(value >> 5) & 3]; + gba->memoryWaitSeq[0x0a] = gba->memoryWaitSeq[0x0b] = + gamepakWaitState1[(value >> 7) & 1]; + + gba->memoryWait[0x0c] = gba->memoryWait[0x0d] = gamepakWaitState[(value >> 8) & 3]; + gba->memoryWaitSeq[0x0c] = gba->memoryWaitSeq[0x0d] = + gamepakWaitState2[(value >> 10) & 1]; + } else { + gba->memoryWait[0x08] = gba->memoryWait[0x09] = 3; + gba->memoryWaitSeq[0x08] = gba->memoryWaitSeq[0x09] = 1; + + gba->memoryWait[0x0a] = gba->memoryWait[0x0b] = 3; + gba->memoryWaitSeq[0x0a] = gba->memoryWaitSeq[0x0b] = 1; + + gba->memoryWait[0x0c] = gba->memoryWait[0x0d] = 3; + gba->memoryWaitSeq[0x0c] = gba->memoryWaitSeq[0x0d] = 1; + } + + for(int i = 8; i < 15; i++) { + gba->memoryWait32[i] = gba->memoryWait[i] + gba->memoryWaitSeq[i] + 1; + gba->memoryWaitSeq32[i] = gba->memoryWaitSeq[i]*2 + 1; + } + + if((value & 0x4000) == 0x4000) { + gba->busPrefetchEnable = true; + gba->busPrefetch = false; + gba->busPrefetchCount = 0; + } else { + gba->busPrefetchEnable = false; + gba->busPrefetch = false; + gba->busPrefetchCount = 0; + } + UPDATE_REG(0x204, value & 0x7FFF); + + } + break; + case 0x208: + gba->IME = value & 1; + UPDATE_REG(0x208, gba->IME); + if ((gba->IME & 1) && (gba->IF & gba->IE) && gba->armIrqEnable) + gba->cpuNextEvent = gba->cpuTotalTicks; + break; + case 0x300: + if(value != 0) + value &= 0xFFFE; + UPDATE_REG(0x300, value); + break; + default: + UPDATE_REG(address&0x3FE, value); + break; + } +} + +void applyTimer (GBASystem *gba) +{ + if (gba->timerOnOffDelay & 1) + { + gba->timer0ClockReload = TIMER_TICKS[gba->timer0Value & 3]; + if(!gba->timer0On && (gba->timer0Value & 0x80)) { + // reload the counter + gba->TM0D = gba->timer0Reload; + gba->timer0Ticks = (0x10000 - gba->TM0D) << gba->timer0ClockReload; + UPDATE_REG(0x100, gba->TM0D); + } + gba->timer0On = gba->timer0Value & 0x80 ? true : false; + gba->TM0CNT = gba->timer0Value & 0xC7; + UPDATE_REG(0x102, gba->TM0CNT); + // CPUUpdateTicks(); + } + if (gba->timerOnOffDelay & 2) + { + gba->timer1ClockReload = TIMER_TICKS[gba->timer1Value & 3]; + if(!gba->timer1On && (gba->timer1Value & 0x80)) { + // reload the counter + gba->TM1D = gba->timer1Reload; + gba->timer1Ticks = (0x10000 - gba->TM1D) << gba->timer1ClockReload; + UPDATE_REG(0x104, gba->TM1D); + } + gba->timer1On = gba->timer1Value & 0x80 ? true : false; + gba->TM1CNT = gba->timer1Value & 0xC7; + UPDATE_REG(0x106, gba->TM1CNT); + } + if (gba->timerOnOffDelay & 4) + { + gba->timer2ClockReload = TIMER_TICKS[gba->timer2Value & 3]; + if(!gba->timer2On && (gba->timer2Value & 0x80)) { + // reload the counter + gba->TM2D = gba->timer2Reload; + gba->timer2Ticks = (0x10000 - gba->TM2D) << gba->timer2ClockReload; + UPDATE_REG(0x108, gba->TM2D); + } + gba->timer2On = gba->timer2Value & 0x80 ? true : false; + gba->TM2CNT = gba->timer2Value & 0xC7; + UPDATE_REG(0x10A, gba->TM2CNT); + } + if (gba->timerOnOffDelay & 8) + { + gba->timer3ClockReload = TIMER_TICKS[gba->timer3Value & 3]; + if(!gba->timer3On && (gba->timer3Value & 0x80)) { + // reload the counter + gba->TM3D = gba->timer3Reload; + gba->timer3Ticks = (0x10000 - gba->TM3D) << gba->timer3ClockReload; + UPDATE_REG(0x10C, gba->TM3D); + } + gba->timer3On = gba->timer3Value & 0x80 ? true : false; + gba->TM3CNT = gba->timer3Value & 0xC7; + UPDATE_REG(0x10E, gba->TM3CNT); + } + gba->cpuNextEvent = CPUUpdateTicks(gba); + gba->timerOnOffDelay = 0; +} + +void CPUInit(GBASystem *gba) +{ + gba->gbaSaveType = 0; + gba->eepromInUse = 0; + gba->saveType = 0; + gba->useBios = false; + + if(!gba->useBios) { + memcpy(gba->bios, myROM, sizeof(myROM)); + } + + int i = 0; + + gba->biosProtected[0] = 0x00; + gba->biosProtected[1] = 0xf0; + gba->biosProtected[2] = 0x29; + gba->biosProtected[3] = 0xe1; + + for(i = 0; i < 256; i++) { + int count = 0; + int j; + for(j = 0; j < 8; j++) + if(i & (1 << j)) + count++; + gba->cpuBitsSet[i] = count; + + for(j = 0; j < 8; j++) + if(i & (1 << j)) + break; + gba->cpuLowestBitSet[i] = j; + } + + for(i = 0; i < 0x400; i++) + gba->ioReadable[i] = true; + for(i = 0x10; i < 0x48; i++) + gba->ioReadable[i] = false; + for(i = 0x4c; i < 0x50; i++) + gba->ioReadable[i] = false; + for(i = 0x54; i < 0x60; i++) + gba->ioReadable[i] = false; + for(i = 0x8c; i < 0x90; i++) + gba->ioReadable[i] = false; + for(i = 0xa0; i < 0xb8; i++) + gba->ioReadable[i] = false; + for(i = 0xbc; i < 0xc4; i++) + gba->ioReadable[i] = false; + for(i = 0xc8; i < 0xd0; i++) + gba->ioReadable[i] = false; + for(i = 0xd4; i < 0xdc; i++) + gba->ioReadable[i] = false; + for(i = 0xe0; i < 0x100; i++) + gba->ioReadable[i] = false; + for(i = 0x110; i < 0x120; i++) + gba->ioReadable[i] = false; + for(i = 0x12c; i < 0x130; i++) + gba->ioReadable[i] = false; + for(i = 0x138; i < 0x140; i++) + gba->ioReadable[i] = false; + for(i = 0x144; i < 0x150; i++) + gba->ioReadable[i] = false; + for(i = 0x15c; i < 0x200; i++) + gba->ioReadable[i] = false; + for(i = 0x20c; i < 0x300; i++) + gba->ioReadable[i] = false; + for(i = 0x304; i < 0x400; i++) + gba->ioReadable[i] = false; + + if(gba->romSize < 0x1fe2000) { + *((u16 *)&gba->rom[0x1fe209c]) = 0xdffa; // SWI 0xFA + *((u16 *)&gba->rom[0x1fe209e]) = 0x4770; // BX LR + } else { + } +} + +void CPUReset(GBASystem *gba) +{ + // clean registers + memset(&gba->reg[0], 0, sizeof(gba->reg)); + // clean OAM + memset(gba->oam, 0, 0x400); + // clean palette + memset(gba->paletteRAM, 0, 0x400); + // clean vram + memset(gba->vram, 0, 0x20000); + // clean io memory + memset(gba->ioMem, 0, 0x400); + + gba->DISPCNT = 0x0080; + gba->DISPSTAT = 0x0000; + gba->VCOUNT = (gba->useBios && !gba->skipBios) ? 0 :0x007E; + gba->BG0CNT = 0x0000; + gba->BG1CNT = 0x0000; + gba->BG2CNT = 0x0000; + gba->BG3CNT = 0x0000; + gba->BG0HOFS = 0x0000; + gba->BG0VOFS = 0x0000; + gba->BG1HOFS = 0x0000; + gba->BG1VOFS = 0x0000; + gba->BG2HOFS = 0x0000; + gba->BG2VOFS = 0x0000; + gba->BG3HOFS = 0x0000; + gba->BG3VOFS = 0x0000; + gba->BG2PA = 0x0100; + gba->BG2PB = 0x0000; + gba->BG2PC = 0x0000; + gba->BG2PD = 0x0100; + gba->BG2X_L = 0x0000; + gba->BG2X_H = 0x0000; + gba->BG2Y_L = 0x0000; + gba->BG2Y_H = 0x0000; + gba->BG3PA = 0x0100; + gba->BG3PB = 0x0000; + gba->BG3PC = 0x0000; + gba->BG3PD = 0x0100; + gba->BG3X_L = 0x0000; + gba->BG3X_H = 0x0000; + gba->BG3Y_L = 0x0000; + gba->BG3Y_H = 0x0000; + gba->WIN0H = 0x0000; + gba->WIN1H = 0x0000; + gba->WIN0V = 0x0000; + gba->WIN1V = 0x0000; + gba->WININ = 0x0000; + gba->WINOUT = 0x0000; + gba->MOSAIC = 0x0000; + gba->BLDMOD = 0x0000; + gba->COLEV = 0x0000; + gba->COLY = 0x0000; + gba->DM0SAD_L = 0x0000; + gba->DM0SAD_H = 0x0000; + gba->DM0DAD_L = 0x0000; + gba->DM0DAD_H = 0x0000; + gba->DM0CNT_L = 0x0000; + gba->DM0CNT_H = 0x0000; + gba->DM1SAD_L = 0x0000; + gba->DM1SAD_H = 0x0000; + gba->DM1DAD_L = 0x0000; + gba->DM1DAD_H = 0x0000; + gba->DM1CNT_L = 0x0000; + gba->DM1CNT_H = 0x0000; + gba->DM2SAD_L = 0x0000; + gba->DM2SAD_H = 0x0000; + gba->DM2DAD_L = 0x0000; + gba->DM2DAD_H = 0x0000; + gba->DM2CNT_L = 0x0000; + gba->DM2CNT_H = 0x0000; + gba->DM3SAD_L = 0x0000; + gba->DM3SAD_H = 0x0000; + gba->DM3DAD_L = 0x0000; + gba->DM3DAD_H = 0x0000; + gba->DM3CNT_L = 0x0000; + gba->DM3CNT_H = 0x0000; + gba->TM0D = 0x0000; + gba->TM0CNT = 0x0000; + gba->TM1D = 0x0000; + gba->TM1CNT = 0x0000; + gba->TM2D = 0x0000; + gba->TM2CNT = 0x0000; + gba->TM3D = 0x0000; + gba->TM3CNT = 0x0000; + gba->P1 = 0x03FF; + gba->IE = 0x0000; + gba->IF = 0x0000; + gba->IME = 0x0000; + + gba->armMode = 0x1F; + + if(gba->cpuIsMultiBoot) { + gba->reg[13].I = 0x03007F00; + gba->reg[15].I = 0x02000000; + gba->reg[16].I = 0x00000000; + gba->reg[R13_IRQ].I = 0x03007FA0; + gba->reg[R13_SVC].I = 0x03007FE0; + gba->armIrqEnable = true; + } else { + if(gba->useBios && !gba->skipBios) { + gba->reg[15].I = 0x00000000; + gba->armMode = 0x13; + gba->armIrqEnable = false; + } else { + gba->reg[13].I = 0x03007F00; + gba->reg[15].I = 0x08000000; + gba->reg[16].I = 0x00000000; + gba->reg[R13_IRQ].I = 0x03007FA0; + gba->reg[R13_SVC].I = 0x03007FE0; + gba->armIrqEnable = true; + } + } + gba->armState = true; + gba->C_FLAG = gba->V_FLAG = gba->N_FLAG = gba->Z_FLAG = false; + UPDATE_REG(0x00, gba->DISPCNT); + UPDATE_REG(0x06, gba->VCOUNT); + UPDATE_REG(0x20, gba->BG2PA); + UPDATE_REG(0x26, gba->BG2PD); + UPDATE_REG(0x30, gba->BG3PA); + UPDATE_REG(0x36, gba->BG3PD); + UPDATE_REG(0x130, gba->P1); + UPDATE_REG(0x88, 0x200); + + // disable FIQ + gba->reg[16].I |= 0x40; + + CPUUpdateCPSR(gba); + + gba->armNextPC = gba->reg[15].I; + gba->reg[15].I += 4; + + // reset internal state + gba->holdState = false; + gba->holdType = 0; + + gba->biosProtected[0] = 0x00; + gba->biosProtected[1] = 0xf0; + gba->biosProtected[2] = 0x29; + gba->biosProtected[3] = 0xe1; + + gba->lcdTicks = (gba->useBios && !gba->skipBios) ? 1008 : 208; + gba->timer0On = false; + gba->timer0Ticks = 0; + gba->timer0Reload = 0; + gba->timer0ClockReload = 0; + gba->timer1On = false; + gba->timer1Ticks = 0; + gba->timer1Reload = 0; + gba->timer1ClockReload = 0; + gba->timer2On = false; + gba->timer2Ticks = 0; + gba->timer2Reload = 0; + gba->timer2ClockReload = 0; + gba->timer3On = false; + gba->timer3Ticks = 0; + gba->timer3Reload = 0; + gba->timer3ClockReload = 0; + gba->dma0Source = 0; + gba->dma0Dest = 0; + gba->dma1Source = 0; + gba->dma1Dest = 0; + gba->dma2Source = 0; + gba->dma2Dest = 0; + gba->dma3Source = 0; + gba->dma3Dest = 0; + gba->fxOn = false; + gba->windowOn = false; + gba->frameCount = 0; + gba->saveType = 0; + gba->layerEnable = gba->DISPCNT & gba->layerSettings; + + for(int i = 0; i < 256; i++) { + gba->map[i].address = (u8 *)&gba->dummyAddress; + gba->map[i].mask = 0; + } + + gba->map[0].address = gba->bios; + gba->map[0].mask = 0x3FFF; + gba->map[2].address = gba->workRAM; + gba->map[2].mask = 0x3FFFF; + gba->map[3].address = gba->internalRAM; + gba->map[3].mask = 0x7FFF; + gba->map[4].address = gba->ioMem; + gba->map[4].mask = 0x3FF; + gba->map[5].address = gba->paletteRAM; + gba->map[5].mask = 0x3FF; + gba->map[6].address = gba->vram; + gba->map[6].mask = 0x1FFFF; + gba->map[7].address = gba->oam; + gba->map[7].mask = 0x3FF; + gba->map[8].address = gba->rom; + gba->map[8].mask = 0x1FFFFFF; + gba->map[9].address = gba->rom; + gba->map[9].mask = 0x1FFFFFF; + gba->map[10].address = gba->rom; + gba->map[10].mask = 0x1FFFFFF; + gba->map[12].address = gba->rom; + gba->map[12].mask = 0x1FFFFFF; + soundReset(gba); + + // make sure registers are correctly initialized if not using BIOS + if(!gba->useBios) { + if(gba->cpuIsMultiBoot) + BIOS_RegisterRamReset(gba, 0xfe); + else + BIOS_RegisterRamReset(gba, 0xff); + } else { + if(gba->cpuIsMultiBoot) + BIOS_RegisterRamReset(gba, 0xfe); + } + + ARM_PREFETCH; + + gba->cpuDmaHack = false; + + gba->SWITicks = 0; +} + +void CPUInterrupt(GBASystem *gba) +{ + u32 PC = gba->reg[15].I; + bool savedState = gba->armState; + CPUSwitchMode(gba, 0x12, true, false); + gba->reg[14].I = PC; + if(!savedState) + gba->reg[14].I += 2; + gba->reg[15].I = 0x18; + gba->armState = true; + gba->armIrqEnable = false; + + gba->armNextPC = gba->reg[15].I; + gba->reg[15].I += 4; + ARM_PREFETCH; + + // if(!holdState) + gba->biosProtected[0] = 0x02; + gba->biosProtected[1] = 0xc0; + gba->biosProtected[2] = 0x5e; + gba->biosProtected[3] = 0xe5; +} + +void CPULoop(GBASystem *gba, int ticks) +{ + int clockTicks; + int timerOverflow = 0; + // variable used by the CPU core + gba->cpuTotalTicks = 0; + + gba->cpuBreakLoop = false; + gba->cpuNextEvent = CPUUpdateTicks(gba); + if(gba->cpuNextEvent > ticks) + gba->cpuNextEvent = ticks; + + + for(;;) { + if(!gba->holdState && !gba->SWITicks) { + if(gba->armState) { + if (!armExecute(gba)) + return; + } else { + if (!thumbExecute(gba)) + return; + } + clockTicks = 0; + } else + clockTicks = CPUUpdateTicks(gba); + + gba->cpuTotalTicks += clockTicks; + + + if(gba->cpuTotalTicks >= gba->cpuNextEvent) { + int remainingTicks = gba->cpuTotalTicks - gba->cpuNextEvent; + + if (gba->SWITicks) + { + gba->SWITicks-=clockTicks; + if (gba->SWITicks<0) + gba->SWITicks = 0; + } + + clockTicks = gba->cpuNextEvent; + gba->cpuTotalTicks = 0; + gba->cpuDmaHack = false; + + updateLoop: + + if (gba->IRQTicks) + { + gba->IRQTicks -= clockTicks; + if (gba->IRQTicks<0) + gba->IRQTicks = 0; + } + + gba->lcdTicks -= clockTicks; + + + if(gba->lcdTicks <= 0) { + if(gba->DISPSTAT & 1) { // V-BLANK + // if in V-Blank mode, keep computing... + if(gba->DISPSTAT & 2) { + gba->lcdTicks += 1008; + gba->VCOUNT++; + UPDATE_REG(0x06, gba->VCOUNT); + gba->DISPSTAT &= 0xFFFD; + UPDATE_REG(0x04, gba->DISPSTAT); + CPUCompareVCOUNT(gba); + } else { + gba->lcdTicks += 224; + gba->DISPSTAT |= 2; + UPDATE_REG(0x04, gba->DISPSTAT); + if(gba->DISPSTAT & 16) { + gba->IF |= 2; + UPDATE_REG(0x202, gba->IF); + } + } + + if(gba->VCOUNT >= 228) { //Reaching last line + gba->DISPSTAT &= 0xFFFC; + UPDATE_REG(0x04, gba->DISPSTAT); + gba->VCOUNT = 0; + UPDATE_REG(0x06, gba->VCOUNT); + CPUCompareVCOUNT(gba); + } + } else { + if(gba->DISPSTAT & 2) { + // if in H-Blank, leave it and move to drawing mode + gba->VCOUNT++; + UPDATE_REG(0x06, gba->VCOUNT); + + gba->lcdTicks += 1008; + gba->DISPSTAT &= 0xFFFD; + if(gba->VCOUNT == 160) { + gba->count++; + if(gba->count == 60) { + gba->count = 0; + } + + gba->DISPSTAT |= 1; + gba->DISPSTAT &= 0xFFFD; + UPDATE_REG(0x04, gba->DISPSTAT); + if(gba->DISPSTAT & 0x0008) { + gba->IF |= 1; + UPDATE_REG(0x202, gba->IF); + } + CPUCheckDMA(gba, 1, 0x0f); + gba->frameCount++; + } + + UPDATE_REG(0x04, gba->DISPSTAT); + CPUCompareVCOUNT(gba); + + } else { + // entering H-Blank + gba->DISPSTAT |= 2; + UPDATE_REG(0x04, gba->DISPSTAT); + gba->lcdTicks += 224; + CPUCheckDMA(gba, 2, 0x0f); + if(gba->DISPSTAT & 16) { + gba->IF |= 2; + UPDATE_REG(0x202, gba->IF); + } + } + } + } + + // we shouldn't be doing sound in stop state, but we loose synchronization + // if sound is disabled, so in stop state, soundTick will just produce + // mute sound + gba->soundTicks -= clockTicks; + if(gba->soundTicks <= 0) { + psoundTickfn(gba); + gba->soundTicks += gba->SOUND_CLOCK_TICKS; + } + + if(!gba->stopState) { + if(gba->timer0On) { + gba->timer0Ticks -= clockTicks; + if(gba->timer0Ticks <= 0) { + gba->timer0Ticks += (0x10000 - gba->timer0Reload) << gba->timer0ClockReload; + timerOverflow |= 1; + soundTimerOverflow(gba, 0); + if(gba->TM0CNT & 0x40) { + gba->IF |= 0x08; + UPDATE_REG(0x202, gba->IF); + } + } + gba->TM0D = 0xFFFF - (gba->timer0Ticks >> gba->timer0ClockReload); + UPDATE_REG(0x100, gba->TM0D); + } + + if(gba->timer1On) { + if(gba->TM1CNT & 4) { + if(timerOverflow & 1) { + gba->TM1D++; + if(gba->TM1D == 0) { + gba->TM1D += gba->timer1Reload; + timerOverflow |= 2; + soundTimerOverflow(gba, 1); + if(gba->TM1CNT & 0x40) { + gba->IF |= 0x10; + UPDATE_REG(0x202, gba->IF); + } + } + UPDATE_REG(0x104, gba->TM1D); + } + } else { + gba->timer1Ticks -= clockTicks; + if(gba->timer1Ticks <= 0) { + gba->timer1Ticks += (0x10000 - gba->timer1Reload) << gba->timer1ClockReload; + timerOverflow |= 2; + soundTimerOverflow(gba, 1); + if(gba->TM1CNT & 0x40) { + gba->IF |= 0x10; + UPDATE_REG(0x202, gba->IF); + } + } + gba->TM1D = 0xFFFF - (gba->timer1Ticks >> gba->timer1ClockReload); + UPDATE_REG(0x104, gba->TM1D); + } + } + + if(gba->timer2On) { + if(gba->TM2CNT & 4) { + if(timerOverflow & 2) { + gba->TM2D++; + if(gba->TM2D == 0) { + gba->TM2D += gba->timer2Reload; + timerOverflow |= 4; + if(gba->TM2CNT & 0x40) { + gba->IF |= 0x20; + UPDATE_REG(0x202, gba->IF); + } + } + UPDATE_REG(0x108, gba->TM2D); + } + } else { + gba->timer2Ticks -= clockTicks; + if(gba->timer2Ticks <= 0) { + gba->timer2Ticks += (0x10000 - gba->timer2Reload) << gba->timer2ClockReload; + timerOverflow |= 4; + if(gba->TM2CNT & 0x40) { + gba->IF |= 0x20; + UPDATE_REG(0x202, gba->IF); + } + } + gba->TM2D = 0xFFFF - (gba->timer2Ticks >> gba->timer2ClockReload); + UPDATE_REG(0x108, gba->TM2D); + } + } + + if(gba->timer3On) { + if(gba->TM3CNT & 4) { + if(timerOverflow & 4) { + gba->TM3D++; + if(gba->TM3D == 0) { + gba->TM3D += gba->timer3Reload; + if(gba->TM3CNT & 0x40) { + gba->IF |= 0x40; + UPDATE_REG(0x202, gba->IF); + } + } + UPDATE_REG(0x10C, gba->TM3D); + } + } else { + gba->timer3Ticks -= clockTicks; + if(gba->timer3Ticks <= 0) { + gba->timer3Ticks += (0x10000 - gba->timer3Reload) << gba->timer3ClockReload; + if(gba->TM3CNT & 0x40) { + gba->IF |= 0x40; + UPDATE_REG(0x202, gba->IF); + } + } + gba->TM3D = 0xFFFF - (gba->timer3Ticks >> gba->timer3ClockReload); + UPDATE_REG(0x10C, gba->TM3D); + } + } + } + + timerOverflow = 0; + + + + ticks -= clockTicks; + + gba->cpuNextEvent = CPUUpdateTicks(gba); + + if(gba->cpuDmaTicksToUpdate > 0) { + if(gba->cpuDmaTicksToUpdate > gba->cpuNextEvent) + clockTicks = gba->cpuNextEvent; + else + clockTicks = gba->cpuDmaTicksToUpdate; + gba->cpuDmaTicksToUpdate -= clockTicks; + if(gba->cpuDmaTicksToUpdate < 0) + gba->cpuDmaTicksToUpdate = 0; + gba->cpuDmaHack = true; + goto updateLoop; + } + + if(gba->IF && (gba->IME & 1) && gba->armIrqEnable) { + int res = gba->IF & gba->IE; + if(gba->stopState) + res &= 0x3080; + if(res) { + if (gba->intState) + { + if (!gba->IRQTicks) + { + CPUInterrupt(gba); + gba->intState = false; + gba->holdState = false; + gba->stopState = false; + gba->holdType = 0; + } + } + else + { + if (!gba->holdState) + { + gba->intState = true; + gba->IRQTicks=7; + if (gba->cpuNextEvent> gba->IRQTicks) + gba->cpuNextEvent = gba->IRQTicks; + } + else + { + CPUInterrupt(gba); + gba->holdState = false; + gba->stopState = false; + gba->holdType = 0; + } + } + + // Stops the SWI Ticks emulation if an IRQ is executed + //(to avoid problems with nested IRQ/SWI) + if (gba->SWITicks) + gba->SWITicks = 0; + } + } + + if(remainingTicks > 0) { + if(remainingTicks > gba->cpuNextEvent) + clockTicks = gba->cpuNextEvent; + else + clockTicks = remainingTicks; + remainingTicks -= clockTicks; + if(remainingTicks < 0) + remainingTicks = 0; + goto updateLoop; + } + + if (gba->timerOnOffDelay) + applyTimer(gba); + + if(gba->cpuNextEvent > ticks) + gba->cpuNextEvent = ticks; + + if(ticks <= 0 || gba->cpuBreakLoop) + break; + + } + } +} diff --git a/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/gba/GBA.h b/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/gba/GBA.h new file mode 100644 index 000000000..d701de752 --- /dev/null +++ b/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/gba/GBA.h @@ -0,0 +1,407 @@ +#ifndef GBA_H +#define GBA_H + +#ifdef EMU_COMPILE +#include "../common/Types.h" + +#include "Sound.h" + +#include "../apu/Gb_Apu.h" +#include "../apu/Multi_Buffer.h" +#else +#include + +#include + +#include +#include +#endif + +#define SAVE_GAME_VERSION_1 1 +#define SAVE_GAME_VERSION_2 2 +#define SAVE_GAME_VERSION_3 3 +#define SAVE_GAME_VERSION_4 4 +#define SAVE_GAME_VERSION_5 5 +#define SAVE_GAME_VERSION_6 6 +#define SAVE_GAME_VERSION_7 7 +#define SAVE_GAME_VERSION_8 8 +#define SAVE_GAME_VERSION_9 9 +#define SAVE_GAME_VERSION_10 10 +#define SAVE_GAME_VERSION SAVE_GAME_VERSION_10 + +typedef struct { + u8 *address; + u32 mask; +} memoryMap; + +typedef union { + struct { +#ifdef WORDS_BIGENDIAN + u8 B3; + u8 B2; + u8 B1; + u8 B0; +#else + u8 B0; + u8 B1; + u8 B2; + u8 B3; +#endif + } B; + struct { +#ifdef WORDS_BIGENDIAN + u16 W1; + u16 W0; +#else + u16 W0; + u16 W1; +#endif + } W; +#ifdef WORDS_BIGENDIAN + volatile u32 I; +#else + u32 I; +#endif +} reg_pair; + +struct GBASystem; + +class Gba_Pcm { +public: + void init(GBASystem *); + void apply_control( int idx ); + void update( int dac ); + void end_frame( GBA::blip_time_t ); + +private: + GBASystem* gba; + GBA::Blip_Buffer* output; + GBA::blip_time_t last_time; + int last_amp; + int shift; +}; + +class Gba_Pcm_Fifo { +public: + int which; + Gba_Pcm pcm; + + void init(GBASystem *); + void write_control( int data ); + void write_fifo( int data ); + void timer_overflowed( int which_timer ); + + // public only so save state routines can access it + GBASystem* gba; + int readIndex; + int count; + int writeIndex; + u8 fifo [32]; + int dac; +private: + + int timer; + bool enabled; +}; + +// Callback class, passed the audio data from the emulator +struct GBASoundOut +{ + virtual ~GBASoundOut() { } + // Receives signed 16-bit stereo audio and a byte count + virtual void write(const void * samples, unsigned bytes) = 0; +}; + +struct GBASystem +{ + reg_pair reg[45]; + memoryMap map[256]; + bool ioReadable[0x400]; + + bool N_FLAG; + bool C_FLAG; + bool Z_FLAG; + bool V_FLAG; + bool armState; + bool armIrqEnable; + u32 armNextPC; + int armMode; + u32 stop; + int saveType; + bool useBios; + bool skipBios; + int frameSkip; + bool speedup; + bool synchronize; + bool cpuDisableSfx; + bool cpuIsMultiBoot; + bool parseDebug; + int layerSettings; + int layerEnable; + bool speedHack; + int cpuSaveType; + bool cheatsEnabled; + bool mirroringEnable; + bool skipSaveGameBattery; + bool skipSaveGameCheats; + + u8 *bios; + u8 *rom; + u8 *internalRAM; + u8 *workRAM; + u8 *paletteRAM; + u8 *vram; + u8 *oam; + u8 *ioMem; + + int customBackdropColor; + + u16 DISPCNT; + u16 DISPSTAT; + u16 VCOUNT; + u16 BG0CNT; + u16 BG1CNT; + u16 BG2CNT; + u16 BG3CNT; + u16 BG0HOFS; + u16 BG0VOFS; + u16 BG1HOFS; + u16 BG1VOFS; + u16 BG2HOFS; + u16 BG2VOFS; + u16 BG3HOFS; + u16 BG3VOFS; + u16 BG2PA; + u16 BG2PB; + u16 BG2PC; + u16 BG2PD; + u16 BG2X_L; + u16 BG2X_H; + u16 BG2Y_L; + u16 BG2Y_H; + u16 BG3PA; + u16 BG3PB; + u16 BG3PC; + u16 BG3PD; + u16 BG3X_L; + u16 BG3X_H; + u16 BG3Y_L; + u16 BG3Y_H; + u16 WIN0H; + u16 WIN1H; + u16 WIN0V; + u16 WIN1V; + u16 WININ; + u16 WINOUT; + u16 MOSAIC; + u16 BLDMOD; + u16 COLEV; + u16 COLY; + u16 DM0SAD_L; + u16 DM0SAD_H; + u16 DM0DAD_L; + u16 DM0DAD_H; + u16 DM0CNT_L; + u16 DM0CNT_H; + u16 DM1SAD_L; + u16 DM1SAD_H; + u16 DM1DAD_L; + u16 DM1DAD_H; + u16 DM1CNT_L; + u16 DM1CNT_H; + u16 DM2SAD_L; + u16 DM2SAD_H; + u16 DM2DAD_L; + u16 DM2DAD_H; + u16 DM2CNT_L; + u16 DM2CNT_H; + u16 DM3SAD_L; + u16 DM3SAD_H; + u16 DM3DAD_L; + u16 DM3DAD_H; + u16 DM3CNT_L; + u16 DM3CNT_H; + u16 TM0D; + u16 TM0CNT; + u16 TM1D; + u16 TM1CNT; + u16 TM2D; + u16 TM2CNT; + u16 TM3D; + u16 TM3CNT; + u16 P1; + u16 IE; + u16 IF; + u16 IME; + + int gfxBG2Changed; + int gfxBG3Changed; + int eepromInUse; + + int emulating; + + int SWITicks; + int IRQTicks; + + u32 mastercode; + int layerEnableDelay; + bool busPrefetch; + bool busPrefetchEnable; + u32 busPrefetchCount; + int cpuDmaTicksToUpdate; + int cpuDmaCount; + bool cpuDmaHack; + u32 cpuDmaLast; + int dummyAddress; + + bool cpuBreakLoop; + int cpuNextEvent; + + int clockTicks; + + int gbaSaveType; + bool intState; + bool stopState; + bool holdState; + int holdType; + bool cpuSramEnabled; + bool cpuFlashEnabled; + bool cpuEEPROMEnabled; + bool cpuEEPROMSensorEnabled; + + u32 cpuPrefetch[2]; + + int cpuTotalTicks; + + int lcdTicks; + u8 timerOnOffDelay; + u16 timer0Value; + bool timer0On; + int timer0Ticks; + int timer0Reload; + int timer0ClockReload; + u16 timer1Value; + bool timer1On; + int timer1Ticks; + int timer1Reload; + int timer1ClockReload; + u16 timer2Value; + bool timer2On; + int timer2Ticks; + int timer2Reload; + int timer2ClockReload; + u16 timer3Value; + bool timer3On; + int timer3Ticks; + int timer3Reload; + int timer3ClockReload; + u32 dma0Source; + u32 dma0Dest; + u32 dma1Source; + u32 dma1Dest; + u32 dma2Source; + u32 dma2Dest; + u32 dma3Source; + u32 dma3Dest; + + bool fxOn; + bool windowOn; + int frameCount; + + char buffer[1024]; + + u32 lastTime; + int count; + + int capture; + int capturePrevious; + int captureNumber; + + u8 memoryWait[16]; + u8 memoryWait32[16]; + u8 memoryWaitSeq[16]; + u8 memoryWaitSeq32[16]; + + u8 biosProtected[4]; + + #ifdef WORDS_BIGENDIAN + bool cpuBiosSwapped; + #endif + + int romSize; + + u8 cpuBitsSet[256]; + u8 cpuLowestBitSet[256]; + + // Sound settings + bool soundDeclicking; + bool soundInterpolation; // 1 if PCM should have low-pass filtering + float soundFiltering; // 0.0 = none, 1.0 = max + long soundSampleRate; + + u16 soundFinalWave [1600]; + bool soundPaused; + + enum { SOUND_CLOCK_TICKS_ = 167772 }; // 1/100 second + + int SOUND_CLOCK_TICKS; + int soundTicks; + + float soundVolume; + int soundEnableFlag; + float soundFiltering_; + float soundVolume_; + + GBASoundOut * output; + + Gba_Pcm_Fifo pcm [2]; + GBA::Gb_Apu* gb_apu; + GBA::Stereo_Buffer* stereo_buffer; + + GBA::Blip_Synth pcm_synth [3]; // 32 kHz, 16 kHz, 8 kHz + + GBASystem(); +}; + +extern void CPUCleanUp(GBASystem *); +extern void CPUUpdateRender(GBASystem *); +extern void CPUUpdateRenderBuffers(GBASystem *, bool); +extern int CPULoadRom(GBASystem *, const void *, u32); +extern void doMirroring(GBASystem *, bool); +extern void CPUUpdateRegister(GBASystem *, u32, u16); +extern void applyTimer (GBASystem *); +extern void CPUInit(GBASystem *); +extern void CPUReset(GBASystem *); +extern void CPULoop(GBASystem *, int); +extern void CPUCheckDMA(GBASystem *, int,int); + +#define R13_IRQ 18 +#define R14_IRQ 19 +#define SPSR_IRQ 20 +#define R13_USR 26 +#define R14_USR 27 +#define R13_SVC 28 +#define R14_SVC 29 +#define SPSR_SVC 30 +#define R13_ABT 31 +#define R14_ABT 32 +#define SPSR_ABT 33 +#define R13_UND 34 +#define R14_UND 35 +#define SPSR_UND 36 +#define R8_FIQ 37 +#define R9_FIQ 38 +#define R10_FIQ 39 +#define R11_FIQ 40 +#define R12_FIQ 41 +#define R13_FIQ 42 +#define R14_FIQ 43 +#define SPSR_FIQ 44 + +#ifdef EMU_COMPILE +#include "Globals.h" +#else +#include +#endif + +#endif // GBA_H diff --git a/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/gba/GBAcpu.h b/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/gba/GBAcpu.h new file mode 100644 index 000000000..5f3cf5c08 --- /dev/null +++ b/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/gba/GBAcpu.h @@ -0,0 +1,256 @@ +#ifndef GBACPU_H +#define GBACPU_H + +struct GBASystem; + +extern int armExecute(GBASystem *); +extern int thumbExecute(GBASystem *); + +#ifdef __GNUC__ +# define INSN_REGPARM __attribute__((regparm(2))) +# define LIKELY(x) __builtin_expect(!!(x),1) +# define UNLIKELY(x) __builtin_expect(!!(x),0) +#else +# define INSN_REGPARM /*nothing*/ +# define LIKELY(x) (x) +# define UNLIKELY(x) (x) +#endif + +#define UPDATE_REG(address, value)\ + {\ + WRITE16LE(((u16 *)&gba->ioMem[address]),value);\ + }\ + +#define ARM_PREFETCH \ + {\ + gba->cpuPrefetch[0] = CPUReadMemoryQuick(gba, gba->armNextPC);\ + gba->cpuPrefetch[1] = CPUReadMemoryQuick(gba, gba->armNextPC+4);\ + } + +#define THUMB_PREFETCH \ + {\ + gba->cpuPrefetch[0] = CPUReadHalfWordQuick(gba, gba->armNextPC);\ + gba->cpuPrefetch[1] = CPUReadHalfWordQuick(gba, gba->armNextPC+2);\ + } + +#define ARM_PREFETCH_NEXT \ + gba->cpuPrefetch[1] = CPUReadMemoryQuick(gba, gba->armNextPC+4); + +#define THUMB_PREFETCH_NEXT\ + gba->cpuPrefetch[1] = CPUReadHalfWordQuick(gba, gba->armNextPC+2); + + +extern void CPUSwitchMode(GBASystem *, int mode, bool saveState, bool breakLoop); +extern void CPUSwitchMode(GBASystem *, int mode, bool saveState); +extern void CPUUpdateCPSR(GBASystem *); +extern void CPUUpdateFlags(GBASystem *, bool breakLoop); +extern void CPUUpdateFlags(GBASystem *); +extern void CPUUndefinedException(GBASystem *); +extern void CPUSoftwareInterrupt(GBASystem *); +extern void CPUSoftwareInterrupt(GBASystem *, int comment); + + +// Waitstates when accessing data +inline int dataTicksAccess16(GBASystem *gba, u32 address) // DATA 8/16bits NON SEQ +{ + int addr = (address>>24)&15; + int value = gba->memoryWait[addr]; + + if ((addr>=0x08) || (addr < 0x02)) + { + gba->busPrefetchCount=0; + gba->busPrefetch=false; + } + else if (gba->busPrefetch) + { + int waitState = value; + if (!waitState) + waitState = 1; + gba->busPrefetchCount = ((gba->busPrefetchCount+1)<>24)&15; + int value = gba->memoryWait32[addr]; + + if ((addr>=0x08) || (addr < 0x02)) + { + gba->busPrefetchCount=0; + gba->busPrefetch=false; + } + else if (gba->busPrefetch) + { + int waitState = value; + if (!waitState) + waitState = 1; + gba->busPrefetchCount = ((gba->busPrefetchCount+1)<>24)&15; + int value = gba->memoryWaitSeq[addr]; + + if ((addr>=0x08) || (addr < 0x02)) + { + gba->busPrefetchCount=0; + gba->busPrefetch=false; + } + else if (gba->busPrefetch) + { + int waitState = value; + if (!waitState) + waitState = 1; + gba->busPrefetchCount = ((gba->busPrefetchCount+1)<>24)&15; + int value = gba->memoryWaitSeq32[addr]; + + if ((addr>=0x08) || (addr < 0x02)) + { + gba->busPrefetchCount=0; + gba->busPrefetch=false; + } + else if (gba->busPrefetch) + { + int waitState = value; + if (!waitState) + waitState = 1; + gba->busPrefetchCount = ((gba->busPrefetchCount+1)<>24)&15; + + if ((addr>=0x08) && (addr<=0x0D)) + { + if (gba->busPrefetchCount&0x1) + { + if (gba->busPrefetchCount&0x2) + { + gba->busPrefetchCount = ((gba->busPrefetchCount&0xFF)>>2) | (gba->busPrefetchCount&0xFFFFFF00); + return 0; + } + gba->busPrefetchCount = ((gba->busPrefetchCount&0xFF)>>1) | (gba->busPrefetchCount&0xFFFFFF00); + return gba->memoryWaitSeq[addr]-1; + } + else + { + gba->busPrefetchCount=0; + return gba->memoryWait[addr]; + } + } + else + { + gba->busPrefetchCount = 0; + return gba->memoryWait[addr]; + } +} + +inline int codeTicksAccess32(GBASystem *gba, u32 address) // ARM NON SEQ +{ + int addr = (address>>24)&15; + + if ((addr>=0x08) && (addr<=0x0D)) + { + if (gba->busPrefetchCount&0x1) + { + if (gba->busPrefetchCount&0x2) + { + gba->busPrefetchCount = ((gba->busPrefetchCount&0xFF)>>2) | (gba->busPrefetchCount&0xFFFFFF00); + return 0; + } + gba->busPrefetchCount = ((gba->busPrefetchCount&0xFF)>>1) | (gba->busPrefetchCount&0xFFFFFF00); + return gba->memoryWaitSeq[addr] - 1; + } + else + { + gba->busPrefetchCount = 0; + return gba->memoryWait32[addr]; + } + } + else + { + gba->busPrefetchCount = 0; + return gba->memoryWait32[addr]; + } +} + +inline int codeTicksAccessSeq16(GBASystem *gba, u32 address) // THUMB SEQ +{ + int addr = (address>>24)&15; + + if ((addr>=0x08) && (addr<=0x0D)) + { + if (gba->busPrefetchCount&0x1) + { + gba->busPrefetchCount = ((gba->busPrefetchCount&0xFF)>>1) | (gba->busPrefetchCount&0xFFFFFF00); + return 0; + } + else + if (gba->busPrefetchCount>0xFF) + { + gba->busPrefetchCount=0; + return gba->memoryWait[addr]; + } + else + return gba->memoryWaitSeq[addr]; + } + else + { + gba->busPrefetchCount = 0; + return gba->memoryWaitSeq[addr]; + } +} + +inline int codeTicksAccessSeq32(GBASystem *gba, u32 address) // ARM SEQ +{ + int addr = (address>>24)&15; + + if ((addr>=0x08) && (addr<=0x0D)) + { + if (gba->busPrefetchCount&0x1) + { + if (gba->busPrefetchCount&0x2) + { + gba->busPrefetchCount = ((gba->busPrefetchCount&0xFF)>>2) | (gba->busPrefetchCount&0xFFFFFF00); + return 0; + } + gba->busPrefetchCount = ((gba->busPrefetchCount&0xFF)>>1) | (gba->busPrefetchCount&0xFFFFFF00); + return gba->memoryWaitSeq[addr]; + } + else + if (gba->busPrefetchCount>0xFF) + { + gba->busPrefetchCount=0; + return gba->memoryWait32[addr]; + } + else + return gba->memoryWaitSeq32[addr]; + } + else + { + return gba->memoryWaitSeq32[addr]; + } +} + +#endif // GBACPU_H diff --git a/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/gba/GBAinline.h b/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/gba/GBAinline.h new file mode 100644 index 000000000..495c5a6a7 --- /dev/null +++ b/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/gba/GBAinline.h @@ -0,0 +1,494 @@ +#ifndef GBAINLINE_H +#define GBAINLINE_H + +#include "../common/Port.h" +#include "../common/Types.h" +#include "Sound.h" + +#define eepromRead(a) 0 +#define eepromWrite(a, v) 1 +#define flashRead(a) 0 +#define rtcRead(a) 0 +#define systemGetSensorX() 0 +#define systemGetSensorY() 0 +#define agbPrintWrite(a, v) 1 +#define rtcWrite(a, v) 1 + +extern const u32 objTilesAddress[3]; + +#define CPUReadByteQuick(gba, addr) \ + (gba)->map[(addr)>>24].address[(addr) & (gba)->map[(addr)>>24].mask] + +#define CPUReadHalfWordQuick(gba, addr) \ + READ16LE(((u16*)&(gba)->map[(addr)>>24].address[(addr) & (gba)->map[(addr)>>24].mask])) + +#define CPUReadMemoryQuick(gba, addr) \ + READ32LE(((u32*)&(gba)->map[(addr)>>24].address[(addr) & (gba)->map[(addr)>>24].mask])) + +static inline u32 CPUReadMemory(GBASystem *gba, u32 address) +{ + u32 value; + switch(address >> 24) { + case 0: + if(gba->reg[15].I >> 24) { + if(address < 0x4000) { + value = READ32LE(((u32 *)&gba->biosProtected)); + } + else goto unreadable; + } else + value = READ32LE(((u32 *)&gba->bios[address & 0x3FFC])); + break; + case 2: + value = READ32LE(((u32 *)&gba->workRAM[address & 0x3FFFC])); + break; + case 3: + value = READ32LE(((u32 *)&gba->internalRAM[address & 0x7ffC])); + break; + case 4: + if((address < 0x4000400) && gba->ioReadable[address & 0x3fc]) { + if(gba->ioReadable[(address & 0x3fc) + 2]) { + value = READ32LE(((u32 *)&gba->ioMem[address & 0x3fC])); + } else { + value = READ16LE(((u16 *)&gba->ioMem[address & 0x3fc])); + } + } + else + goto unreadable; + break; + case 5: + value = READ32LE(((u32 *)&gba->paletteRAM[address & 0x3fC])); + break; + case 6: + address = (address & 0x1fffc); + if (((gba->DISPCNT & 7) >2) && ((address & 0x1C000) == 0x18000)) + { + value = 0; + break; + } + if ((address & 0x18000) == 0x18000) + address &= 0x17fff; + value = READ32LE(((u32 *)&gba->vram[address])); + break; + case 7: + value = READ32LE(((u32 *)&gba->oam[address & 0x3FC])); + break; + case 8: + case 9: + case 10: + case 11: + case 12: + value = READ32LE(((u32 *)&gba->rom[address&0x1FFFFFC])); + break; + case 13: + if(gba->cpuEEPROMEnabled) + // no need to swap this + return eepromRead(address); + goto unreadable; + case 14: + if(gba->cpuFlashEnabled | gba->cpuSramEnabled) + // no need to swap this + return flashRead(address); + // default + default: +unreadable: + + if(gba->cpuDmaHack) { + value = gba->cpuDmaLast; + } else { + if(gba->armState) { + value = CPUReadMemoryQuick(gba, gba->reg[15].I); + } else { + value = CPUReadHalfWordQuick(gba, gba->reg[15].I) | + CPUReadHalfWordQuick(gba, gba->reg[15].I) << 16; + } + } + } + + if(address & 3) { + int shift = (address & 3) << 3; + value = (value >> shift) | (value << (32 - shift)); + } + return value; +} + +extern const u32 myROM[]; + +static inline u32 CPUReadHalfWord(GBASystem *gba, u32 address) +{ + u32 value; + + switch(address >> 24) { + case 0: + if (gba->reg[15].I >> 24) { + if(address < 0x4000) { + value = READ16LE(((u16 *)&gba->biosProtected[address&2])); + } else goto unreadable; + } else + value = READ16LE(((u16 *)&gba->bios[address & 0x3FFE])); + break; + case 2: + value = READ16LE(((u16 *)&gba->workRAM[address & 0x3FFFE])); + break; + case 3: + value = READ16LE(((u16 *)&gba->internalRAM[address & 0x7ffe])); + break; + case 4: + if((address < 0x4000400) && gba->ioReadable[address & 0x3fe]) + { + value = READ16LE(((u16 *)&gba->ioMem[address & 0x3fe])); + if (((address & 0x3fe)>0xFF) && ((address & 0x3fe)<0x10E)) + { + if (((address & 0x3fe) == 0x100) && gba->timer0On) + value = 0xFFFF - ((gba->timer0Ticks-gba->cpuTotalTicks) >> gba->timer0ClockReload); + else + if (((address & 0x3fe) == 0x104) && gba->timer1On && !(gba->TM1CNT & 4)) + value = 0xFFFF - ((gba->timer1Ticks-gba->cpuTotalTicks) >> gba->timer1ClockReload); + else + if (((address & 0x3fe) == 0x108) && gba->timer2On && !(gba->TM2CNT & 4)) + value = 0xFFFF - ((gba->timer2Ticks-gba->cpuTotalTicks) >> gba->timer2ClockReload); + else + if (((address & 0x3fe) == 0x10C) && gba->timer3On && !(gba->TM3CNT & 4)) + value = 0xFFFF - ((gba->timer3Ticks-gba->cpuTotalTicks) >> gba->timer3ClockReload); + } + } + else goto unreadable; + break; + case 5: + value = READ16LE(((u16 *)&gba->paletteRAM[address & 0x3fe])); + break; + case 6: + address = (address & 0x1fffe); + if (((gba->DISPCNT & 7) >2) && ((address & 0x1C000) == 0x18000)) + { + value = 0; + break; + } + if ((address & 0x18000) == 0x18000) + address &= 0x17fff; + value = READ16LE(((u16 *)&gba->vram[address])); + break; + case 7: + value = READ16LE(((u16 *)&gba->oam[address & 0x3fe])); + break; + case 8: + case 9: + case 10: + case 11: + case 12: + if(address == 0x80000c4 || address == 0x80000c6 || address == 0x80000c8) + value = rtcRead(address); + else + value = READ16LE(((u16 *)&gba->rom[address & 0x1FFFFFE])); + break; + case 13: + if(gba->cpuEEPROMEnabled) + // no need to swap this + return eepromRead(address); + goto unreadable; + case 14: + if(gba->cpuFlashEnabled | gba->cpuSramEnabled) + // no need to swap this + return flashRead(address); + // default + default: +unreadable: + if(gba->cpuDmaHack) { + value = gba->cpuDmaLast & 0xFFFF; + } else { + if(gba->armState) { + value = CPUReadHalfWordQuick(gba, gba->reg[15].I + (address & 2)); + } else { + value = CPUReadHalfWordQuick(gba, gba->reg[15].I); + } + } + break; + } + + if(address & 1) { + value = (value >> 8) | (value << 24); + } + + return value; +} + +static inline u16 CPUReadHalfWordSigned(GBASystem *gba, u32 address) +{ + u16 value = CPUReadHalfWord(gba, address); + if((address & 1)) + value = (s8)value; + return value; +} + +static inline u8 CPUReadByte(GBASystem *gba, u32 address) +{ + switch(address >> 24) { + case 0: + if (gba->reg[15].I >> 24) { + if(address < 0x4000) { + return gba->biosProtected[address & 3]; + } else goto unreadable; + } + return gba->bios[address & 0x3FFF]; + case 2: + return gba->workRAM[address & 0x3FFFF]; + case 3: + return gba->internalRAM[address & 0x7fff]; + case 4: + if((address < 0x4000400) && gba->ioReadable[address & 0x3ff]) + return gba->ioMem[address & 0x3ff]; + else goto unreadable; + case 5: + return gba->paletteRAM[address & 0x3ff]; + case 6: + address = (address & 0x1ffff); + if (((gba->DISPCNT & 7) >2) && ((address & 0x1C000) == 0x18000)) + return 0; + if ((address & 0x18000) == 0x18000) + address &= 0x17fff; + return gba->vram[address]; + case 7: + return gba->oam[address & 0x3ff]; + case 8: + case 9: + case 10: + case 11: + case 12: + return gba->rom[address & 0x1FFFFFF]; + case 13: + if(gba->cpuEEPROMEnabled) + return eepromRead(address); + goto unreadable; + case 14: + if(gba->cpuSramEnabled | gba->cpuFlashEnabled) + return flashRead(address); + if(gba->cpuEEPROMSensorEnabled) { + switch(address & 0x00008f00) { + case 0x8200: + return systemGetSensorX() & 255; + case 0x8300: + return (systemGetSensorX() >> 8)|0x80; + case 0x8400: + return systemGetSensorY() & 255; + case 0x8500: + return systemGetSensorY() >> 8; + } + } + // default + default: +unreadable: + if(gba->cpuDmaHack) { + return gba->cpuDmaLast & 0xFF; + } else { + if(gba->armState) { + return CPUReadByteQuick(gba, gba->reg[15].I+(address & 3)); + } else { + return CPUReadByteQuick(gba, gba->reg[15].I+(address & 1)); + } + } + break; + } +} + +static inline void CPUWriteMemory(GBASystem *gba, u32 address, u32 value) +{ + switch(address >> 24) { + case 0x02: + WRITE32LE(((u32 *)&gba->workRAM[address & 0x3FFFC]), value); + break; + case 0x03: + WRITE32LE(((u32 *)&gba->internalRAM[address & 0x7ffC]), value); + break; + case 0x04: + if(address < 0x4000400) { + CPUUpdateRegister(gba, (address & 0x3FC), value & 0xFFFF); + CPUUpdateRegister(gba, (address & 0x3FC) + 2, (value >> 16)); + } else goto unwritable; + break; + case 0x05: + WRITE32LE(((u32 *)&gba->paletteRAM[address & 0x3FC]), value); + break; + case 0x06: + address = (address & 0x1fffc); + if (((gba->DISPCNT & 7) >2) && ((address & 0x1C000) == 0x18000)) + return; + if ((address & 0x18000) == 0x18000) + address &= 0x17fff; + + WRITE32LE(((u32 *)&gba->vram[address]), value); + break; + case 0x07: + WRITE32LE(((u32 *)&gba->oam[address & 0x3fc]), value); + break; + case 0x0D: + if(gba->cpuEEPROMEnabled) { + eepromWrite(address, value); + break; + } + goto unwritable; + case 0x0E: + // default + default: +unwritable: + break; + } +} + +static inline void CPUWriteHalfWord(GBASystem *gba, u32 address, u16 value) +{ + switch(address >> 24) { + case 2: + WRITE16LE(((u16 *)&gba->workRAM[address & 0x3FFFE]),value); + break; + case 3: + WRITE16LE(((u16 *)&gba->internalRAM[address & 0x7ffe]), value); + break; + case 4: + if(address < 0x4000400) + CPUUpdateRegister(gba, address & 0x3fe, value); + else goto unwritable; + break; + case 5: + WRITE16LE(((u16 *)&gba->paletteRAM[address & 0x3fe]), value); + break; + case 6: + address = (address & 0x1fffe); + if (((gba->DISPCNT & 7) >2) && ((address & 0x1C000) == 0x18000)) + return; + if ((address & 0x18000) == 0x18000) + address &= 0x17fff; + WRITE16LE(((u16 *)&gba->vram[address]), value); + break; + case 7: + WRITE16LE(((u16 *)&gba->oam[address & 0x3fe]), value); + break; + case 8: + case 9: + if(address == 0x80000c4 || address == 0x80000c6 || address == 0x80000c8) { + if(!rtcWrite(address, value)) + goto unwritable; + } else if(!agbPrintWrite(address, value)) goto unwritable; + break; + case 13: + if(gba->cpuEEPROMEnabled) { + eepromWrite(address, (u8)value); + break; + } + goto unwritable; + case 14: + goto unwritable; + default: +unwritable: + break; + } +} + +static inline void CPUWriteByte(GBASystem *gba, u32 address, u8 b) +{ + switch(address >> 24) { + case 2: + gba->workRAM[address & 0x3FFFF] = b; + break; + case 3: + gba->internalRAM[address & 0x7fff] = b; + break; + case 4: + if(address < 0x4000400) { + switch(address & 0x3FF) { + case 0x60: + case 0x61: + case 0x62: + case 0x63: + case 0x64: + case 0x65: + case 0x68: + case 0x69: + case 0x6c: + case 0x6d: + case 0x70: + case 0x71: + case 0x72: + case 0x73: + case 0x74: + case 0x75: + case 0x78: + case 0x79: + case 0x7c: + case 0x7d: + case 0x80: + case 0x81: + case 0x84: + case 0x85: + case 0x90: + case 0x91: + case 0x92: + case 0x93: + case 0x94: + case 0x95: + case 0x96: + case 0x97: + case 0x98: + case 0x99: + case 0x9a: + case 0x9b: + case 0x9c: + case 0x9d: + case 0x9e: + case 0x9f: + soundEvent(gba, address&0xFF, b); + break; + case 0x301: // HALTCNT, undocumented + if(b == 0x80) + gba->stopState = true; + gba->holdState = 1; + gba->holdType = -1; + gba->cpuNextEvent = gba->cpuTotalTicks; + break; + default: // every other register + u32 lowerBits = address & 0x3fe; + if(address & 1) { + CPUUpdateRegister(gba, lowerBits, (READ16LE(&gba->ioMem[lowerBits]) & 0x00FF) | (b << 8)); + } else { + CPUUpdateRegister(gba, lowerBits, (READ16LE(&gba->ioMem[lowerBits]) & 0xFF00) | b); + } + } + break; + } else goto unwritable; + break; + case 5: + // no need to switch + *((u16 *)&gba->paletteRAM[address & 0x3FE]) = (b << 8) | b; + break; + case 6: + address = (address & 0x1fffe); + if (((gba->DISPCNT & 7) >2) && ((address & 0x1C000) == 0x18000)) + return; + if ((address & 0x18000) == 0x18000) + address &= 0x17fff; + + // no need to switch + // byte writes to OBJ VRAM are ignored + if ((address) < objTilesAddress[((gba->DISPCNT&7)+1)>>2]) + { + *((u16 *)&gba->vram[address]) = (b << 8) | b; + } + break; + case 7: + // no need to switch + // byte writes to OAM are ignored + // *((u16 *)&oam[address & 0x3FE]) = (b << 8) | b; + break; + case 13: + if(gba->cpuEEPROMEnabled) { + eepromWrite(address, b); + break; + } + goto unwritable; + case 14: + // default + default: +unwritable: + break; + } +} + +#endif // GBAINLINE_H diff --git a/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/gba/Globals.h b/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/gba/Globals.h new file mode 100644 index 000000000..593e4927c --- /dev/null +++ b/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/gba/Globals.h @@ -0,0 +1,24 @@ +#ifndef GLOBALS_H +#define GLOBALS_H + +#ifdef EMU_COMPILE +#include "../common/Types.h" +#include "GBA.h" +#else +#include +#include +#endif + +#define VERBOSE_SWI 1 +#define VERBOSE_UNALIGNED_MEMORY 2 +#define VERBOSE_ILLEGAL_WRITE 4 +#define VERBOSE_ILLEGAL_READ 8 +#define VERBOSE_DMA0 16 +#define VERBOSE_DMA1 32 +#define VERBOSE_DMA2 64 +#define VERBOSE_DMA3 128 +#define VERBOSE_UNDEFINED 256 +#define VERBOSE_AGBPRINT 512 +#define VERBOSE_SOUNDOUTPUT 1024 + +#endif // GLOBALS_H diff --git a/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/gba/Sound.cpp b/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/gba/Sound.cpp new file mode 100644 index 000000000..6e3c2d6f1 --- /dev/null +++ b/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/gba/Sound.cpp @@ -0,0 +1,505 @@ +#include + +#include "Sound.h" + +#include "GBA.h" +#include "Globals.h" + +#include "../common/Port.h" + +#include "../apu/Gb_Apu.h" +#include "../apu/Multi_Buffer.h" + +#define NR10 0x60 +#define NR11 0x62 +#define NR12 0x63 +#define NR13 0x64 +#define NR14 0x65 +#define NR21 0x68 +#define NR22 0x69 +#define NR23 0x6c +#define NR24 0x6d +#define NR30 0x70 +#define NR31 0x72 +#define NR32 0x73 +#define NR33 0x74 +#define NR34 0x75 +#define NR41 0x78 +#define NR42 0x79 +#define NR43 0x7c +#define NR44 0x7d +#define NR50 0x80 +#define NR51 0x81 +#define NR52 0x84 + +static inline GBA::blip_time_t blip_time(GBASystem *gba) +{ + return gba->SOUND_CLOCK_TICKS - gba->soundTicks; +} + +void Gba_Pcm::init(GBASystem *gba) +{ + this->gba = gba; + output = 0; + last_time = 0; + last_amp = 0; + shift = 0; +} + +void Gba_Pcm::apply_control( int idx ) +{ + shift = ~gba->ioMem [SGCNT0_H] >> (2 + idx) & 1; + + int ch = 0; + if ( (gba->soundEnableFlag >> idx & 0x100) && (gba->ioMem [NR52] & 0x80) ) + ch = gba->ioMem [SGCNT0_H+1] >> (idx * 4) & 3; + + GBA::Blip_Buffer* out = 0; + switch ( ch ) + { + case 1: out = gba->stereo_buffer->right(); break; + case 2: out = gba->stereo_buffer->left(); break; + case 3: out = gba->stereo_buffer->center(); break; + } + + if ( output != out ) + { + if ( output ) + { + output->set_modified(); + gba->pcm_synth [0].offset( blip_time(gba), -last_amp, output ); + } + last_amp = 0; + output = out; + } +} + +void Gba_Pcm::end_frame( GBA::blip_time_t time ) +{ + last_time -= time; + if ( last_time < -2048 ) + last_time = -2048; + + if ( output ) + output->set_modified(); +} + +void Gba_Pcm::update( int dac ) +{ + if ( output ) + { + GBA::blip_time_t time = blip_time(gba); + + dac = (s8) dac >> shift; + int delta = dac - last_amp; + if ( delta ) + { + last_amp = dac; + + int filter = 0; + if ( gba->soundInterpolation ) + { + // base filtering on how long since last sample was output + int period = time - last_time; + + int idx = (unsigned) period / 512; + if ( idx >= 3 ) + idx = 3; + + static int const filters [4] = { 0, 0, 1, 2 }; + filter = filters [idx]; + } + + gba->pcm_synth [filter].offset( time, delta, output ); + } + last_time = time; + } +} + +void Gba_Pcm_Fifo::init(GBASystem *gba) +{ + this->gba = gba; + pcm.init(gba); +} + +void Gba_Pcm_Fifo::timer_overflowed( int which_timer ) +{ + if ( which_timer == timer && enabled ) + { + if ( count <= 16 ) + { + // Need to fill FIFO + CPUCheckDMA( gba, 3, which ? 4 : 2 ); + if ( count <= 16 ) + { + // Not filled by DMA, so fill with 16 bytes of silence + int reg = which ? FIFOB_L : FIFOA_L; + for ( int n = 4; n--; ) + { + soundEvent(gba, reg , (u16)0); + soundEvent(gba, reg+2, (u16)0); + } + } + } + + // Read next sample from FIFO + count--; + dac = fifo [readIndex]; + readIndex = (readIndex + 1) & 31; + pcm.update( dac ); + } +} + +void Gba_Pcm_Fifo::write_control( int data ) +{ + enabled = (data & 0x0300) ? true : false; + timer = (data & 0x0400) ? 1 : 0; + + if ( data & 0x0800 ) + { + // Reset + writeIndex = 0; + readIndex = 0; + count = 0; + dac = 0; + memset( fifo, 0, sizeof fifo ); + } + + pcm.apply_control( which ); + pcm.update( dac ); +} + +void Gba_Pcm_Fifo::write_fifo( int data ) +{ + fifo [writeIndex ] = data & 0xFF; + fifo [writeIndex+1] = data >> 8; + count += 2; + writeIndex = (writeIndex + 2) & 31; +} + +static void apply_control(GBASystem *gba) +{ + gba->pcm [0].pcm.apply_control( 0 ); + gba->pcm [1].pcm.apply_control( 1 ); +} + +static int gba_to_gb_sound( int addr ) +{ + static const int table [0x40] = + { + 0xFF10, 0,0xFF11,0xFF12,0xFF13,0xFF14, 0, 0, + 0xFF16,0xFF17, 0, 0,0xFF18,0xFF19, 0, 0, + 0xFF1A, 0,0xFF1B,0xFF1C,0xFF1D,0xFF1E, 0, 0, + 0xFF20,0xFF21, 0, 0,0xFF22,0xFF23, 0, 0, + 0xFF24,0xFF25, 0, 0,0xFF26, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0xFF30,0xFF31,0xFF32,0xFF33,0xFF34,0xFF35,0xFF36,0xFF37, + 0xFF38,0xFF39,0xFF3A,0xFF3B,0xFF3C,0xFF3D,0xFF3E,0xFF3F, + }; + if ( addr >= 0x60 && addr < 0xA0 ) + return table [addr - 0x60]; + return 0; +} + +void soundEvent(GBASystem *gba, u32 address, u8 data) +{ + int gb_addr = gba_to_gb_sound( address ); + if ( gb_addr ) + { + gba->ioMem[address] = data; + gba->gb_apu->write_register( blip_time(gba), gb_addr, data ); + + if ( address == NR52 ) + apply_control(gba); + } + + gba->ioMem[NR52] = (gba->ioMem[NR52] & 0x80) | (gba->gb_apu->read_status() & 0x7f); + + // TODO: what about byte writes to SGCNT0_H etc.? +} + +static void apply_volume( GBASystem *gba, bool apu_only = false ) +{ + if ( !apu_only ) + gba->soundVolume_ = gba->soundVolume; + + if ( gba->gb_apu ) + { + static float const apu_vols [4] = { 0.25, 0.5, 1, 0.25 }; + gba->gb_apu->volume( gba->soundVolume_ * apu_vols [gba->ioMem [SGCNT0_H] & 3] ); + } + + if ( !apu_only ) + { + for ( int i = 0; i < 3; i++ ) + gba->pcm_synth [i].volume( 0.66 / 256 * gba->soundVolume_ ); + } +} + +static void write_SGCNT0_H( GBASystem *gba, int data ) +{ + WRITE16LE( &gba->ioMem [SGCNT0_H], data & 0x770F ); + gba->pcm [0].write_control( data ); + gba->pcm [1].write_control( data >> 4 ); + apply_volume( gba, true ); +} + +void soundEvent(GBASystem *gba, u32 address, u16 data) +{ + switch ( address ) + { + case SGCNT0_H: + write_SGCNT0_H( gba, data ); + break; + + case FIFOA_L: + case FIFOA_H: + gba->pcm [0].write_fifo( data ); + WRITE16LE( &gba->ioMem[address], data ); + break; + + case FIFOB_L: + case FIFOB_H: + gba->pcm [1].write_fifo( data ); + WRITE16LE( &gba->ioMem[address], data ); + break; + + case 0x88: + data &= 0xC3FF; + WRITE16LE( &gba->ioMem[address], data ); + break; + + default: + soundEvent( gba, address & ~1, (u8) (data ) ); // even + soundEvent( gba, address | 1, (u8) (data >> 8) ); // odd + break; + } +} + +void soundTimerOverflow(GBASystem *gba, int timer) +{ + gba->pcm [0].timer_overflowed( timer ); + gba->pcm [1].timer_overflowed( timer ); +} + +static void end_frame( GBASystem *gba, GBA::blip_time_t time ) +{ + gba->pcm [0].pcm.end_frame( time ); + gba->pcm [1].pcm.end_frame( time ); + + gba->gb_apu ->end_frame( time ); + gba->stereo_buffer->end_frame( time ); +} + +void flush_samples(GBASystem *gba, GBA::Multi_Buffer * buffer) +{ + // We want to write the data frame by frame to support legacy audio drivers + // that don't use the length parameter of the write method. + // TODO: Update the Win32 audio drivers (DS, OAL, XA2), and flush all the + // samples at once to help reducing the audio delay on all platforms. + int soundBufferLen = ( gba->soundSampleRate / 60 ) * 4; + + // soundBufferLen should have a whole number of sample pairs + assert( soundBufferLen % (2 * sizeof *gba->soundFinalWave) == 0 ); + + // number of samples in output buffer + int const out_buf_size = soundBufferLen / sizeof *gba->soundFinalWave; + + while ( buffer->samples_avail() ) + { + long samples_read = buffer->read_samples( (GBA::blip_sample_t*) gba->soundFinalWave, out_buf_size ); + if(gba->soundPaused) + soundResume(gba); + + gba->output->write(gba->soundFinalWave, samples_read * sizeof *gba->soundFinalWave); + } +} + +static void apply_filtering(GBASystem *gba) +{ + gba->soundFiltering_ = gba->soundFiltering; + + int const base_freq = (int) (32768 - gba->soundFiltering_ * 16384); + int const nyquist = gba->stereo_buffer->sample_rate() / 2; + + for ( int i = 0; i < 3; i++ ) + { + int cutoff = base_freq >> i; + if ( cutoff > nyquist ) + cutoff = nyquist; + gba->pcm_synth [i].treble_eq( GBA::blip_eq_t( 0, 0, gba->stereo_buffer->sample_rate(), cutoff ) ); + } +} + +void psoundTickfn(GBASystem *gba) +{ + if ( gba->gb_apu && gba->stereo_buffer ) + { + // Run sound hardware to present + end_frame( gba, gba->SOUND_CLOCK_TICKS ); + + flush_samples( gba, gba->stereo_buffer ); + + if ( gba->soundFiltering_ != gba->soundFiltering ) + apply_filtering(gba); + + if ( gba->soundVolume_ != gba->soundVolume ) + apply_volume(gba); + } +} + +static void apply_muting(GBASystem *gba) +{ + if ( !gba->stereo_buffer || !gba->ioMem ) + return; + + // PCM + apply_control(gba); + + if ( gba->gb_apu ) + { + // APU + for ( int i = 0; i < 4; i++ ) + { + if ( gba->soundEnableFlag >> i & 1 ) + gba->gb_apu->set_output( gba->stereo_buffer->center(), + gba->stereo_buffer->left(), gba->stereo_buffer->right(), i ); + else + gba->gb_apu->set_output( 0, 0, 0, i ); + } + } +} + +static void reset_apu(GBASystem *gba) +{ + if (gba->gb_apu) + { + gba->gb_apu->reduce_clicks(gba->soundDeclicking); + gba->gb_apu->reset( gba->gb_apu->mode_agb, true ); + } + + if ( gba->stereo_buffer ) + gba->stereo_buffer->clear(); + + gba->soundTicks = gba->SOUND_CLOCK_TICKS; +} + +static void remake_stereo_buffer(GBASystem *gba) +{ + if ( !gba->ioMem ) + return; + + // Clears pointers kept to old stereo_buffer + gba->pcm [0].init(gba); + gba->pcm [1].init(gba); + + // Stereo_Buffer + if (gba->stereo_buffer) + { + delete gba->stereo_buffer; + gba->stereo_buffer = 0; + } + + gba->stereo_buffer = new GBA::Stereo_Buffer; // TODO: handle out of memory + gba->stereo_buffer->set_sample_rate( gba->soundSampleRate ); // TODO: handle out of memory + gba->stereo_buffer->clock_rate( gba->gb_apu->clock_rate ); + + // PCM + gba->pcm [0].which = 0; + gba->pcm [1].which = 1; + apply_filtering(gba); + + // APU + if ( !gba->gb_apu ) + { + gba->gb_apu = new GBA::Gb_Apu; // TODO: handle out of memory + reset_apu(gba); + } + + apply_muting(gba); + apply_volume(gba); +} + +void soundShutdown(GBASystem *gba) +{ + // APU + if ( !gba->gb_apu ) + { + delete gba->gb_apu; + gba->gb_apu = 0; + } + + // Stereo_Buffer + if (gba->stereo_buffer) + { + delete gba->stereo_buffer; + gba->stereo_buffer = 0; + } +} + +void soundPause(GBASystem *gba) +{ + gba->soundPaused = true; +} + +void soundResume(GBASystem *gba) +{ + gba->soundPaused = false; +} + +void soundSetVolume( GBASystem *gba, float volume ) +{ + gba->soundVolume = volume; +} + +float soundGetVolume(GBASystem *gba) +{ + return gba->soundVolume; +} + +void soundSetEnable(GBASystem *gba, int channels) +{ + gba->soundEnableFlag = channels; + apply_muting(gba); +} + +int soundGetEnable(GBASystem *gba) +{ + return (gba->soundEnableFlag & 0x30f); +} + +void soundReset(GBASystem *gba) +{ + remake_stereo_buffer(gba); + reset_apu(gba); + + gba->soundPaused = true; + gba->SOUND_CLOCK_TICKS = GBASystem::SOUND_CLOCK_TICKS_; + gba->soundTicks = GBASystem::SOUND_CLOCK_TICKS_; + + soundEvent( gba, NR52, (u8) 0x80 ); +} + +bool soundInit(GBASystem *gba, GBASoundOut *out) +{ + gba->soundPaused = true; + gba->output = out; + return true; +} + +long soundGetSampleRate(GBASystem *gba) +{ + return gba->soundSampleRate; +} + +void soundSetSampleRate(GBASystem *gba, long sampleRate) +{ + if ( gba->soundSampleRate != sampleRate ) + { + { + gba->soundSampleRate = sampleRate; + } + + remake_stereo_buffer(gba); + } +} diff --git a/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/gba/Sound.h b/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/gba/Sound.h new file mode 100644 index 000000000..dff2b0ec1 --- /dev/null +++ b/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/gba/Sound.h @@ -0,0 +1,77 @@ +#ifndef SOUND_H +#define SOUND_H + +// Sound emulation setup/options and GBA sound emulation + +#ifdef EMU_COMPILE +#include "../common/Types.h" +#else +#include +#endif + +struct GBASystem; + +struct GBASoundOut; + +// Initializes sound and returns true if successful. Sets sound quality to +// current value in soundQuality global. +bool soundInit(GBASystem *, GBASoundOut *); + +// sets the Sound throttle +void soundSetThrottle(GBASystem *, unsigned short throttle); + +// Manages sound volume, where 1.0 is normal +void soundSetVolume( GBASystem *, float ); +float soundGetVolume(GBASystem *); + +// Manages muting bitmask. The bits control the following channels: +// 0x001 Pulse 1 +// 0x002 Pulse 2 +// 0x004 Wave +// 0x008 Noise +// 0x100 PCM 1 +// 0x200 PCM 2 +void soundSetEnable( GBASystem *, int mask ); +int soundGetEnable( GBASystem * ); + +// Pauses/resumes system sound output +void soundPause( GBASystem * ); +void soundResume( GBASystem * ); + +// Cleans up sound. Afterwards, soundInit() can be called again. +void soundShutdown( GBASystem * ); + +//// GBA sound options + +long soundGetSampleRate( GBASystem * ); +void soundSetSampleRate( GBASystem *, long sampleRate ); + + + +//// GBA sound emulation + +// GBA sound registers +#define SGCNT0_H 0x82 +#define FIFOA_L 0xa0 +#define FIFOA_H 0xa2 +#define FIFOB_L 0xa4 +#define FIFOB_H 0xa6 + +// Resets emulated sound hardware +void soundReset(GBASystem *); + +// Emulates write to sound hardware +void soundEvent( GBASystem *, u32 addr, u8 data ); +void soundEvent( GBASystem *, u32 addr, u16 data ); // TODO: error-prone to overload like this + +// Notifies emulator that a timer has overflowed +void soundTimerOverflow( GBASystem *, int which ); + +// Notifies emulator that SOUND_CLOCK_TICKS clocks have passed +void psoundTickfn(GBASystem *); + +namespace GBA { class Multi_Buffer; } + +void flush_samples(GBASystem *, GBA::Multi_Buffer * buffer); + +#endif // SOUND_H diff --git a/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/gba/bios.cpp b/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/gba/bios.cpp new file mode 100644 index 000000000..a30714376 --- /dev/null +++ b/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/gba/bios.cpp @@ -0,0 +1,934 @@ +#include +#include +#include + +#include "GBA.h" +#include "bios.h" +#include "GBAinline.h" +#include "Globals.h" + +static const s16 sineTable[256] = { + (s16)0x0000, (s16)0x0192, (s16)0x0323, (s16)0x04B5, (s16)0x0645, (s16)0x07D5, (s16)0x0964, (s16)0x0AF1, + (s16)0x0C7C, (s16)0x0E05, (s16)0x0F8C, (s16)0x1111, (s16)0x1294, (s16)0x1413, (s16)0x158F, (s16)0x1708, + (s16)0x187D, (s16)0x19EF, (s16)0x1B5D, (s16)0x1CC6, (s16)0x1E2B, (s16)0x1F8B, (s16)0x20E7, (s16)0x223D, + (s16)0x238E, (s16)0x24DA, (s16)0x261F, (s16)0x275F, (s16)0x2899, (s16)0x29CD, (s16)0x2AFA, (s16)0x2C21, + (s16)0x2D41, (s16)0x2E5A, (s16)0x2F6B, (s16)0x3076, (s16)0x3179, (s16)0x3274, (s16)0x3367, (s16)0x3453, + (s16)0x3536, (s16)0x3612, (s16)0x36E5, (s16)0x37AF, (s16)0x3871, (s16)0x392A, (s16)0x39DA, (s16)0x3A82, + (s16)0x3B20, (s16)0x3BB6, (s16)0x3C42, (s16)0x3CC5, (s16)0x3D3E, (s16)0x3DAE, (s16)0x3E14, (s16)0x3E71, + (s16)0x3EC5, (s16)0x3F0E, (s16)0x3F4E, (s16)0x3F84, (s16)0x3FB1, (s16)0x3FD3, (s16)0x3FEC, (s16)0x3FFB, + (s16)0x4000, (s16)0x3FFB, (s16)0x3FEC, (s16)0x3FD3, (s16)0x3FB1, (s16)0x3F84, (s16)0x3F4E, (s16)0x3F0E, + (s16)0x3EC5, (s16)0x3E71, (s16)0x3E14, (s16)0x3DAE, (s16)0x3D3E, (s16)0x3CC5, (s16)0x3C42, (s16)0x3BB6, + (s16)0x3B20, (s16)0x3A82, (s16)0x39DA, (s16)0x392A, (s16)0x3871, (s16)0x37AF, (s16)0x36E5, (s16)0x3612, + (s16)0x3536, (s16)0x3453, (s16)0x3367, (s16)0x3274, (s16)0x3179, (s16)0x3076, (s16)0x2F6B, (s16)0x2E5A, + (s16)0x2D41, (s16)0x2C21, (s16)0x2AFA, (s16)0x29CD, (s16)0x2899, (s16)0x275F, (s16)0x261F, (s16)0x24DA, + (s16)0x238E, (s16)0x223D, (s16)0x20E7, (s16)0x1F8B, (s16)0x1E2B, (s16)0x1CC6, (s16)0x1B5D, (s16)0x19EF, + (s16)0x187D, (s16)0x1708, (s16)0x158F, (s16)0x1413, (s16)0x1294, (s16)0x1111, (s16)0x0F8C, (s16)0x0E05, + (s16)0x0C7C, (s16)0x0AF1, (s16)0x0964, (s16)0x07D5, (s16)0x0645, (s16)0x04B5, (s16)0x0323, (s16)0x0192, + (s16)0x0000, (s16)0xFE6E, (s16)0xFCDD, (s16)0xFB4B, (s16)0xF9BB, (s16)0xF82B, (s16)0xF69C, (s16)0xF50F, + (s16)0xF384, (s16)0xF1FB, (s16)0xF074, (s16)0xEEEF, (s16)0xED6C, (s16)0xEBED, (s16)0xEA71, (s16)0xE8F8, + (s16)0xE783, (s16)0xE611, (s16)0xE4A3, (s16)0xE33A, (s16)0xE1D5, (s16)0xE075, (s16)0xDF19, (s16)0xDDC3, + (s16)0xDC72, (s16)0xDB26, (s16)0xD9E1, (s16)0xD8A1, (s16)0xD767, (s16)0xD633, (s16)0xD506, (s16)0xD3DF, + (s16)0xD2BF, (s16)0xD1A6, (s16)0xD095, (s16)0xCF8A, (s16)0xCE87, (s16)0xCD8C, (s16)0xCC99, (s16)0xCBAD, + (s16)0xCACA, (s16)0xC9EE, (s16)0xC91B, (s16)0xC851, (s16)0xC78F, (s16)0xC6D6, (s16)0xC626, (s16)0xC57E, + (s16)0xC4E0, (s16)0xC44A, (s16)0xC3BE, (s16)0xC33B, (s16)0xC2C2, (s16)0xC252, (s16)0xC1EC, (s16)0xC18F, + (s16)0xC13B, (s16)0xC0F2, (s16)0xC0B2, (s16)0xC07C, (s16)0xC04F, (s16)0xC02D, (s16)0xC014, (s16)0xC005, + (s16)0xC000, (s16)0xC005, (s16)0xC014, (s16)0xC02D, (s16)0xC04F, (s16)0xC07C, (s16)0xC0B2, (s16)0xC0F2, + (s16)0xC13B, (s16)0xC18F, (s16)0xC1EC, (s16)0xC252, (s16)0xC2C2, (s16)0xC33B, (s16)0xC3BE, (s16)0xC44A, + (s16)0xC4E0, (s16)0xC57E, (s16)0xC626, (s16)0xC6D6, (s16)0xC78F, (s16)0xC851, (s16)0xC91B, (s16)0xC9EE, + (s16)0xCACA, (s16)0xCBAD, (s16)0xCC99, (s16)0xCD8C, (s16)0xCE87, (s16)0xCF8A, (s16)0xD095, (s16)0xD1A6, + (s16)0xD2BF, (s16)0xD3DF, (s16)0xD506, (s16)0xD633, (s16)0xD767, (s16)0xD8A1, (s16)0xD9E1, (s16)0xDB26, + (s16)0xDC72, (s16)0xDDC3, (s16)0xDF19, (s16)0xE075, (s16)0xE1D5, (s16)0xE33A, (s16)0xE4A3, (s16)0xE611, + (s16)0xE783, (s16)0xE8F8, (s16)0xEA71, (s16)0xEBED, (s16)0xED6C, (s16)0xEEEF, (s16)0xF074, (s16)0xF1FB, + (s16)0xF384, (s16)0xF50F, (s16)0xF69C, (s16)0xF82B, (s16)0xF9BB, (s16)0xFB4B, (s16)0xFCDD, (s16)0xFE6E +}; + +void BIOS_ArcTan(GBASystem *gba) +{ + s32 a = -(((s32)(gba->reg[0].I*gba->reg[0].I)) >> 14); + s32 b = ((0xA9 * a) >> 14) + 0x390; + b = ((b * a) >> 14) + 0x91C; + b = ((b * a) >> 14) + 0xFB6; + b = ((b * a) >> 14) + 0x16AA; + b = ((b * a) >> 14) + 0x2081; + b = ((b * a) >> 14) + 0x3651; + b = ((b * a) >> 14) + 0xA2F9; + a = ((s32)gba->reg[0].I * b) >> 16; + gba->reg[0].I = a; +} + +void BIOS_ArcTan2(GBASystem *gba) +{ + s32 x = gba->reg[0].I; + s32 y = gba->reg[1].I; + u32 res = 0; + if (y == 0) { + res = ((x>>16) & 0x8000); + } else { + if (x == 0) { + res = ((y>>16) & 0x8000) + 0x4000; + } else { + if ((abs(x) > abs(y)) || ((abs(x) == abs(y)) && (!((x<0) && (y<0))))) { + gba->reg[1].I = x; + gba->reg[0].I = y << 14; + BIOS_Div(gba); + BIOS_ArcTan(gba); + if (x < 0) + res = 0x8000 + gba->reg[0].I; + else + res = (((y>>16) & 0x8000)<<1) + gba->reg[0].I; + } else { + gba->reg[0].I = x << 14; + BIOS_Div(gba); + BIOS_ArcTan(gba); + res = (0x4000 + ((y>>16) & 0x8000)) - gba->reg[0].I; + } + } + } + gba->reg[0].I = res; +} + +void BIOS_BitUnPack(GBASystem *gba) +{ + u32 source = gba->reg[0].I; + u32 dest = gba->reg[1].I; + u32 header = gba->reg[2].I; + + int len = CPUReadHalfWord(gba, header); + // check address + if(((source & 0xe000000) == 0) || + ((source + len) & 0xe000000) == 0) + return; + + int bits = CPUReadByte(gba, header+2); + int revbits = 8 - bits; + // u32 value = 0; + u32 base = CPUReadMemory(gba, header+4); + bool addBase = (base & 0x80000000) ? true : false; + base &= 0x7fffffff; + int dataSize = CPUReadByte(gba, header+3); + + int data = 0; + int bitwritecount = 0; + while(1) { + len -= 1; + if(len < 0) + break; + int mask = 0xff >> revbits; + u8 b = CPUReadByte(gba, source); + source++; + int bitcount = 0; + while(1) { + if(bitcount >= 8) + break; + u32 d = b & mask; + u32 temp = d >> bitcount; + if(d || addBase) { + temp += base; + } + data |= temp << bitwritecount; + bitwritecount += dataSize; + if(bitwritecount >= 32) { + CPUWriteMemory(gba, dest, data); + dest += 4; + data = 0; + bitwritecount = 0; + } + mask <<= bits; + bitcount += bits; + } + } +} + +void BIOS_GetBiosChecksum(GBASystem *gba) +{ + gba->reg[0].I=0xBAAE187F; +} + +void BIOS_BgAffineSet(GBASystem *gba) +{ + u32 src = gba->reg[0].I; + u32 dest = gba->reg[1].I; + int num = gba->reg[2].I; + + for(int i = 0; i < num; i++) { + s32 cx = CPUReadMemory(gba, src); + src+=4; + s32 cy = CPUReadMemory(gba, src); + src+=4; + s16 dispx = CPUReadHalfWord(gba, src); + src+=2; + s16 dispy = CPUReadHalfWord(gba, src); + src+=2; + s16 rx = CPUReadHalfWord(gba, src); + src+=2; + s16 ry = CPUReadHalfWord(gba, src); + src+=2; + u16 theta = CPUReadHalfWord(gba, src)>>8; + src+=4; // keep structure alignment + s32 a = sineTable[(theta+0x40)&255]; + s32 b = sineTable[theta]; + + s16 dx = (rx * a)>>14; + s16 dmx = (rx * b)>>14; + s16 dy = (ry * b)>>14; + s16 dmy = (ry * a)>>14; + + CPUWriteHalfWord(gba, dest, dx); + dest += 2; + CPUWriteHalfWord(gba, dest, -dmx); + dest += 2; + CPUWriteHalfWord(gba, dest, dy); + dest += 2; + CPUWriteHalfWord(gba, dest, dmy); + dest += 2; + + s32 startx = cx - dx * dispx + dmx * dispy; + s32 starty = cy - dy * dispx - dmy * dispy; + + CPUWriteMemory(gba, dest, startx); + dest += 4; + CPUWriteMemory(gba, dest, starty); + dest += 4; + } +} + +void BIOS_CpuSet(GBASystem *gba) +{ + u32 source = gba->reg[0].I; + u32 dest = gba->reg[1].I; + u32 cnt = gba->reg[2].I; + + if(((source & 0xe000000) == 0) || + ((source + (((cnt << 11)>>9) & 0x1fffff)) & 0xe000000) == 0) + return; + + int count = cnt & 0x1FFFFF; + + // 32-bit ? + if((cnt >> 26) & 1) { + // needed for 32-bit mode! + source &= 0xFFFFFFFC; + dest &= 0xFFFFFFFC; + // fill ? + if((cnt >> 24) & 1) { + u32 value = (source>0x0EFFFFFF ? 0x1CAD1CAD : CPUReadMemory(gba, source)); + while(count) { + CPUWriteMemory(gba, dest, value); + dest += 4; + count--; + } + } else { + // copy + while(count) { + CPUWriteMemory(gba, dest, (source>0x0EFFFFFF ? 0x1CAD1CAD : CPUReadMemory(gba, source))); + source += 4; + dest += 4; + count--; + } + } + } else { + // 16-bit fill? + if((cnt >> 24) & 1) { + u16 value = (source>0x0EFFFFFF ? 0x1CAD : CPUReadHalfWord(gba, source)); + while(count) { + CPUWriteHalfWord(gba, dest, value); + dest += 2; + count--; + } + } else { + // copy + while(count) { + CPUWriteHalfWord(gba, dest, (source>0x0EFFFFFF ? 0x1CAD : CPUReadHalfWord(gba, source))); + source += 2; + dest += 2; + count--; + } + } + } +} + +void BIOS_CpuFastSet(GBASystem *gba) +{ + u32 source = gba->reg[0].I; + u32 dest = gba->reg[1].I; + u32 cnt = gba->reg[2].I; + + if(((source & 0xe000000) == 0) || + ((source + (((cnt << 11)>>9) & 0x1fffff)) & 0xe000000) == 0) + return; + + // needed for 32-bit mode! + source &= 0xFFFFFFFC; + dest &= 0xFFFFFFFC; + + int count = cnt & 0x1FFFFF; + + // fill? + if((cnt >> 24) & 1) { + while(count > 0) { + // BIOS always transfers 32 bytes at a time + u32 value = (source>0x0EFFFFFF ? 0xBAFFFFFB : CPUReadMemory(gba, source)); + for(int i = 0; i < 8; i++) { + CPUWriteMemory(gba, dest, value); + dest += 4; + } + count -= 8; + } + } else { + // copy + while(count > 0) { + // BIOS always transfers 32 bytes at a time + for(int i = 0; i < 8; i++) { + CPUWriteMemory(gba, dest, (source>0x0EFFFFFF ? 0xBAFFFFFB :CPUReadMemory(gba, source))); + source += 4; + dest += 4; + } + count -= 8; + } + } +} + +void BIOS_Diff8bitUnFilterWram(GBASystem *gba) +{ + u32 source = gba->reg[0].I; + u32 dest = gba->reg[1].I; + + u32 header = CPUReadMemory(gba, source); + source += 4; + + if(((source & 0xe000000) == 0) || + (((source + ((header >> 8) & 0x1fffff)) & 0xe000000) == 0)) + return; + + int len = header >> 8; + + u8 data = CPUReadByte(gba, source++); + CPUWriteByte(gba, dest++, data); + len--; + + while(len > 0) { + u8 diff = CPUReadByte(gba, source++); + data += diff; + CPUWriteByte(gba, dest++, data); + len--; + } +} + +void BIOS_Diff8bitUnFilterVram(GBASystem *gba) +{ + u32 source = gba->reg[0].I; + u32 dest = gba->reg[1].I; + + u32 header = CPUReadMemory(gba, source); + source += 4; + + if(((source & 0xe000000) == 0) || + ((source + ((header >> 8) & 0x1fffff)) & 0xe000000) == 0) + return; + + int len = header >> 8; + + u8 data = CPUReadByte(gba, source++); + u16 writeData = data; + int shift = 8; + int bytes = 1; + + while(len >= 2) { + u8 diff = CPUReadByte(gba, source++); + data += diff; + writeData |= (data << shift); + bytes++; + shift += 8; + if(bytes == 2) { + CPUWriteHalfWord(gba, dest, writeData); + dest += 2; + len -= 2; + bytes = 0; + writeData = 0; + shift = 0; + } + } +} + +void BIOS_Diff16bitUnFilter(GBASystem *gba) +{ + u32 source = gba->reg[0].I; + u32 dest = gba->reg[1].I; + + u32 header = CPUReadMemory(gba, source); + source += 4; + + if(((source & 0xe000000) == 0) || + ((source + ((header >> 8) & 0x1fffff)) & 0xe000000) == 0) + return; + + int len = header >> 8; + + u16 data = CPUReadHalfWord(gba, source); + source += 2; + CPUWriteHalfWord(gba, dest, data); + dest += 2; + len -= 2; + + while(len >= 2) { + u16 diff = CPUReadHalfWord(gba, source); + source += 2; + data += diff; + CPUWriteHalfWord(gba, dest, data); + dest += 2; + len -= 2; + } +} + +void BIOS_Div(GBASystem *gba) +{ + int number = gba->reg[0].I; + int denom = gba->reg[1].I; + + if(denom != 0) { + gba->reg[0].I = number / denom; + gba->reg[1].I = number % denom; + s32 temp = (s32)gba->reg[0].I; + gba->reg[3].I = temp < 0 ? (u32)-temp : (u32)temp; + } +} + +void BIOS_DivARM(GBASystem *gba) +{ + u32 temp = gba->reg[0].I; + gba->reg[0].I = gba->reg[1].I; + gba->reg[1].I = temp; + BIOS_Div(gba); +} + +void BIOS_HuffUnComp(GBASystem *gba) +{ + u32 source = gba->reg[0].I; + u32 dest = gba->reg[1].I; + + u32 header = CPUReadMemory(gba, source); + source += 4; + + if(((source & 0xe000000) == 0) || + ((source + ((header >> 8) & 0x1fffff)) & 0xe000000) == 0) + return; + + u8 treeSize = CPUReadByte(gba, source++); + + u32 treeStart = source; + + source += ((treeSize+1)<<1)-1; // minus because we already skipped one byte + + int len = header >> 8; + + u32 mask = 0x80000000; + u32 data = CPUReadMemory(gba, source); + source += 4; + + int pos = 0; + u8 rootNode = CPUReadByte(gba, treeStart); + u8 currentNode = rootNode; + bool writeData = false; + int byteShift = 0; + int byteCount = 0; + u32 writeValue = 0; + + if((header & 0x0F) == 8) { + while(len > 0) { + // take left + if(pos == 0) + pos++; + else + pos += (((currentNode & 0x3F)+1)<<1); + + if(data & mask) { + // right + if(currentNode & 0x40) + writeData = true; + currentNode = CPUReadByte(gba, treeStart+pos+1); + } else { + // left + if(currentNode & 0x80) + writeData = true; + currentNode = CPUReadByte(gba, treeStart+pos); + } + + if(writeData) { + writeValue |= (currentNode << byteShift); + byteCount++; + byteShift += 8; + + pos = 0; + currentNode = rootNode; + writeData = false; + + if(byteCount == 4) { + byteCount = 0; + byteShift = 0; + CPUWriteMemory(gba, dest, writeValue); + writeValue = 0; + dest += 4; + len -= 4; + } + } + mask >>= 1; + if(mask == 0) { + mask = 0x80000000; + data = CPUReadMemory(gba, source); + source += 4; + } + } + } else { + int halfLen = 0; + int value = 0; + while(len > 0) { + // take left + if(pos == 0) + pos++; + else + pos += (((currentNode & 0x3F)+1)<<1); + + if((data & mask)) { + // right + if(currentNode & 0x40) + writeData = true; + currentNode = CPUReadByte(gba, treeStart+pos+1); + } else { + // left + if(currentNode & 0x80) + writeData = true; + currentNode = CPUReadByte(gba, treeStart+pos); + } + + if(writeData) { + if(halfLen == 0) + value |= currentNode; + else + value |= (currentNode<<4); + + halfLen += 4; + if(halfLen == 8) { + writeValue |= (value << byteShift); + byteCount++; + byteShift += 8; + + halfLen = 0; + value = 0; + + if(byteCount == 4) { + byteCount = 0; + byteShift = 0; + CPUWriteMemory(gba, dest, writeValue); + dest += 4; + writeValue = 0; + len -= 4; + } + } + pos = 0; + currentNode = rootNode; + writeData = false; + } + mask >>= 1; + if(mask == 0) { + mask = 0x80000000; + data = CPUReadMemory(gba, source); + source += 4; + } + } + } +} + +void BIOS_LZ77UnCompVram(GBASystem *gba) +{ + u32 source = gba->reg[0].I; + u32 dest = gba->reg[1].I; + + u32 header = CPUReadMemory(gba, source); + source += 4; + + if(((source & 0xe000000) == 0) || + ((source + ((header >> 8) & 0x1fffff)) & 0xe000000) == 0) + return; + + int byteCount = 0; + int byteShift = 0; + u32 writeValue = 0; + + int len = header >> 8; + + while(len > 0) { + u8 d = CPUReadByte(gba, source++); + + if(d) { + for(int i = 0; i < 8; i++) { + if(d & 0x80) { + u16 data = CPUReadByte(gba, source++) << 8; + data |= CPUReadByte(gba, source++); + int length = (data >> 12) + 3; + int offset = (data & 0x0FFF); + u32 windowOffset = dest + byteCount - offset - 1; + for(int i2 = 0; i2 < length; i2++) { + writeValue |= (CPUReadByte(gba, windowOffset++) << byteShift); + byteShift += 8; + byteCount++; + + if(byteCount == 2) { + CPUWriteHalfWord(gba, dest, writeValue); + dest += 2; + byteCount = 0; + byteShift = 0; + writeValue = 0; + } + len--; + if(len == 0) + return; + } + } else { + writeValue |= (CPUReadByte(gba, source++) << byteShift); + byteShift += 8; + byteCount++; + if(byteCount == 2) { + CPUWriteHalfWord(gba, dest, writeValue); + dest += 2; + byteCount = 0; + byteShift = 0; + writeValue = 0; + } + len--; + if(len == 0) + return; + } + d <<= 1; + } + } else { + for(int i = 0; i < 8; i++) { + writeValue |= (CPUReadByte(gba, source++) << byteShift); + byteShift += 8; + byteCount++; + if(byteCount == 2) { + CPUWriteHalfWord(gba, dest, writeValue); + dest += 2; + byteShift = 0; + byteCount = 0; + writeValue = 0; + } + len--; + if(len == 0) + return; + } + } + } +} + +void BIOS_LZ77UnCompWram(GBASystem *gba) +{ + u32 source = gba->reg[0].I; + u32 dest = gba->reg[1].I; + + u32 header = CPUReadMemory(gba, source); + source += 4; + + if(((source & 0xe000000) == 0) || + ((source + ((header >> 8) & 0x1fffff)) & 0xe000000) == 0) + return; + + int len = header >> 8; + + while(len > 0) { + u8 d = CPUReadByte(gba, source++); + + if(d) { + for(int i = 0; i < 8; i++) { + if(d & 0x80) { + u16 data = CPUReadByte(gba, source++) << 8; + data |= CPUReadByte(gba, source++); + int length = (data >> 12) + 3; + int offset = (data & 0x0FFF); + u32 windowOffset = dest - offset - 1; + for(int i2 = 0; i2 < length; i2++) { + CPUWriteByte(gba, dest++, CPUReadByte(gba, windowOffset++)); + len--; + if(len == 0) + return; + } + } else { + CPUWriteByte(gba, dest++, CPUReadByte(gba, source++)); + len--; + if(len == 0) + return; + } + d <<= 1; + } + } else { + for(int i = 0; i < 8; i++) { + CPUWriteByte(gba, dest++, CPUReadByte(gba, source++)); + len--; + if(len == 0) + return; + } + } + } +} + +void BIOS_ObjAffineSet(GBASystem *gba) +{ + u32 src = gba->reg[0].I; + u32 dest = gba->reg[1].I; + int num = gba->reg[2].I; + int offset = gba->reg[3].I; + + for(int i = 0; i < num; i++) { + s16 rx = CPUReadHalfWord(gba, src); + src+=2; + s16 ry = CPUReadHalfWord(gba, src); + src+=2; + u16 theta = CPUReadHalfWord(gba, src)>>8; + src+=4; // keep structure alignment + + s32 a = (s32)sineTable[(theta+0x40)&255]; + s32 b = (s32)sineTable[theta]; + + s16 dx = ((s32)rx * a)>>14; + s16 dmx = ((s32)rx * b)>>14; + s16 dy = ((s32)ry * b)>>14; + s16 dmy = ((s32)ry * a)>>14; + + CPUWriteHalfWord(gba, dest, dx); + dest += offset; + CPUWriteHalfWord(gba, dest, -dmx); + dest += offset; + CPUWriteHalfWord(gba, dest, dy); + dest += offset; + CPUWriteHalfWord(gba, dest, dmy); + dest += offset; + } +} + +void BIOS_RegisterRamReset(GBASystem *gba, u32 flags) +{ + // no need to trace here. this is only called directly from GBA.cpp + // to emulate bios initialization + + CPUUpdateRegister(gba, 0x0, 0x80); + + if(flags) { + if(flags & 0x01) { + // clear work RAM + memset(gba->workRAM, 0, 0x40000); + } + if(flags & 0x02) { + // clear internal RAM + memset(gba->internalRAM, 0, 0x7e00); // don't clear 0x7e00-0x7fff + } + if(flags & 0x04) { + // clear palette RAM + memset(gba->paletteRAM, 0, 0x400); + } + if(flags & 0x08) { + // clear VRAM + memset(gba->vram, 0, 0x18000); + } + if(flags & 0x10) { + // clean OAM + memset(gba->oam, 0, 0x400); + } + + if(flags & 0x80) { + int i; + for(i = 0; i < 0x10; i++) + CPUUpdateRegister(gba, 0x200+i*2, 0); + + for(i = 0; i < 0xF; i++) + CPUUpdateRegister(gba, 0x4+i*2, 0); + + for(i = 0; i < 0x20; i++) + CPUUpdateRegister(gba, 0x20+i*2, 0); + + for(i = 0; i < 0x18; i++) + CPUUpdateRegister(gba, 0xb0+i*2, 0); + + CPUUpdateRegister(gba, 0x130, 0); + CPUUpdateRegister(gba, 0x20, 0x100); + CPUUpdateRegister(gba, 0x30, 0x100); + CPUUpdateRegister(gba, 0x26, 0x100); + CPUUpdateRegister(gba, 0x36, 0x100); + } + + if(flags & 0x20) { + int i; + for(i = 0; i < 8; i++) + CPUUpdateRegister(gba, 0x110+i*2, 0); + CPUUpdateRegister(gba, 0x134, 0x8000); + for(i = 0; i < 7; i++) + CPUUpdateRegister(gba, 0x140+i*2, 0); + } + + if(flags & 0x40) { + int i; + CPUWriteByte(gba, 0x4000084, 0); + CPUWriteByte(gba, 0x4000084, 0x80); + CPUWriteMemory(gba, 0x4000080, 0x880e0000); + CPUUpdateRegister(gba, 0x88, CPUReadHalfWord(gba, 0x4000088)&0x3ff); + CPUWriteByte(gba, 0x4000070, 0x70); + for(i = 0; i < 8; i++) + CPUUpdateRegister(gba, 0x90+i*2, 0); + CPUWriteByte(gba, 0x4000070, 0); + for(i = 0; i < 8; i++) + CPUUpdateRegister(gba, 0x90+i*2, 0); + CPUWriteByte(gba, 0x4000084, 0); + } + } +} + +void BIOS_RegisterRamReset(GBASystem *gba) +{ + BIOS_RegisterRamReset(gba, gba->reg[0].I); +} + +void BIOS_RLUnCompVram(GBASystem *gba) +{ + u32 source = gba->reg[0].I; + u32 dest = gba->reg[1].I; + + u32 header = CPUReadMemory(gba, source & 0xFFFFFFFC); + source += 4; + + if(((source & 0xe000000) == 0) || + ((source + ((header >> 8) & 0x1fffff)) & 0xe000000) == 0) + return; + + int len = header >> 8; + int byteCount = 0; + int byteShift = 0; + u32 writeValue = 0; + + while(len > 0) { + u8 d = CPUReadByte(gba, source++); + int l = d & 0x7F; + if(d & 0x80) { + u8 data = CPUReadByte(gba, source++); + l += 3; + for(int i = 0;i < l; i++) { + writeValue |= (data << byteShift); + byteShift += 8; + byteCount++; + + if(byteCount == 2) { + CPUWriteHalfWord(gba, dest, writeValue); + dest += 2; + byteCount = 0; + byteShift = 0; + writeValue = 0; + } + len--; + if(len == 0) + return; + } + } else { + l++; + for(int i = 0; i < l; i++) { + writeValue |= (CPUReadByte(gba, source++) << byteShift); + byteShift += 8; + byteCount++; + if(byteCount == 2) { + CPUWriteHalfWord(gba, dest, writeValue); + dest += 2; + byteCount = 0; + byteShift = 0; + writeValue = 0; + } + len--; + if(len == 0) + return; + } + } + } +} + +void BIOS_RLUnCompWram(GBASystem *gba) +{ + u32 source = gba->reg[0].I; + u32 dest = gba->reg[1].I; + + u32 header = CPUReadMemory(gba, source & 0xFFFFFFFC); + source += 4; + + if(((source & 0xe000000) == 0) || + ((source + ((header >> 8) & 0x1fffff)) & 0xe000000) == 0) + return; + + int len = header >> 8; + + while(len > 0) { + u8 d = CPUReadByte(gba, source++); + int l = d & 0x7F; + if(d & 0x80) { + u8 data = CPUReadByte(gba, source++); + l += 3; + for(int i = 0;i < l; i++) { + CPUWriteByte(gba, dest++, data); + len--; + if(len == 0) + return; + } + } else { + l++; + for(int i = 0; i < l; i++) { + CPUWriteByte(gba, dest++, CPUReadByte(gba, source++)); + len--; + if(len == 0) + return; + } + } + } +} + +void BIOS_SoftReset(GBASystem *gba) +{ + gba->armState = true; + gba->armMode = 0x1F; + gba->armIrqEnable = false; + gba->C_FLAG = gba->V_FLAG = gba->N_FLAG = gba->Z_FLAG = false; + gba->reg[13].I = 0x03007F00; + gba->reg[14].I = 0x00000000; + gba->reg[16].I = 0x00000000; + gba->reg[R13_IRQ].I = 0x03007FA0; + gba->reg[R14_IRQ].I = 0x00000000; + gba->reg[SPSR_IRQ].I = 0x00000000; + gba->reg[R13_SVC].I = 0x03007FE0; + gba->reg[R14_SVC].I = 0x00000000; + gba->reg[SPSR_SVC].I = 0x00000000; + u8 b = gba->internalRAM[0x7ffa]; + + memset(&gba->internalRAM[0x7e00], 0, 0x200); + + if(b) { + gba->armNextPC = 0x02000000; + gba->reg[15].I = 0x02000004; + } else { + gba->armNextPC = 0x08000000; + gba->reg[15].I = 0x08000004; + } +} + +void BIOS_Sqrt(GBASystem *gba) +{ + gba->reg[0].I = (u32)sqrt((double)gba->reg[0].I); +} + +void BIOS_MidiKey2Freq(GBASystem *gba) +{ + int freq = CPUReadMemory(gba, gba->reg[0].I+4); + double tmp; + tmp = ((double)(180 - gba->reg[1].I)) - ((double)gba->reg[2].I / 256.f); + tmp = pow((double)2.f, tmp / 12.f); + gba->reg[0].I = (int)((double)freq / tmp); +} + +void BIOS_SndDriverJmpTableCopy(GBASystem *gba) +{ + for(int i = 0; i < 0x24; i++) { + CPUWriteMemory(gba, gba->reg[0].I, 0x9c); + gba->reg[0].I += 4; + } +} diff --git a/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/gba/bios.h b/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/gba/bios.h new file mode 100644 index 000000000..60f784023 --- /dev/null +++ b/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/gba/bios.h @@ -0,0 +1,29 @@ +#ifndef BIOS_H +#define BIOS_H + +extern void BIOS_ArcTan(GBASystem *); +extern void BIOS_ArcTan2(GBASystem *); +extern void BIOS_BitUnPack(GBASystem *); +extern void BIOS_GetBiosChecksum(GBASystem *); +extern void BIOS_BgAffineSet(GBASystem *); +extern void BIOS_CpuSet(GBASystem *); +extern void BIOS_CpuFastSet(GBASystem *); +extern void BIOS_Diff8bitUnFilterWram(GBASystem *); +extern void BIOS_Diff8bitUnFilterVram(GBASystem *); +extern void BIOS_Diff16bitUnFilter(GBASystem *); +extern void BIOS_Div(GBASystem *); +extern void BIOS_DivARM(GBASystem *); +extern void BIOS_HuffUnComp(GBASystem *); +extern void BIOS_LZ77UnCompVram(GBASystem *); +extern void BIOS_LZ77UnCompWram(GBASystem *); +extern void BIOS_ObjAffineSet(GBASystem *); +extern void BIOS_RegisterRamReset(GBASystem *); +extern void BIOS_RegisterRamReset(GBASystem *, u32); +extern void BIOS_RLUnCompVram(GBASystem *); +extern void BIOS_RLUnCompWram(GBASystem *); +extern void BIOS_SoftReset(GBASystem *); +extern void BIOS_Sqrt(GBASystem *); +extern void BIOS_MidiKey2Freq(GBASystem *); +extern void BIOS_SndDriverJmpTableCopy(GBASystem *); + +#endif // BIOS_H diff --git a/Frameworks/AudioOverload/aosdk/eng_psf/peops2/License.txt b/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/gpl.txt similarity index 83% rename from Frameworks/AudioOverload/aosdk/eng_psf/peops2/License.txt rename to Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/gpl.txt index e51338c2c..074594074 100644 --- a/Frameworks/AudioOverload/aosdk/eng_psf/peops2/License.txt +++ b/Frameworks/HighlyAdvanced/HighlyAdvanced/vbam/gpl.txt @@ -1,10 +1,8 @@ -######################################################################### - GNU GENERAL PUBLIC LICENSE Version 2, June 1991 Copyright (C) 1989, 1991 Free Software Foundation, Inc. - 675 Mass Ave, Cambridge, MA 02139, USA + 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA Everyone is permitted to copy and distribute verbatim copies of this license document, but changing it is not allowed. @@ -57,7 +55,7 @@ patent must be licensed for everyone's free use or not licensed at all. The precise terms and conditions for copying, distribution and modification follow. - + GNU GENERAL PUBLIC LICENSE TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION @@ -112,7 +110,7 @@ above, provided that you also meet all of these conditions: License. (Exception: if the Program itself is interactive but does not normally print such an announcement, your work based on the Program is not required to print an announcement.) - + These requirements apply to the modified work as a whole. If identifiable sections of that work are not derived from the Program, and can be reasonably considered independent and separate works in @@ -170,7 +168,7 @@ access to copy from a designated place, then offering equivalent access to copy the source code from the same place counts as distribution of the source code, even though third parties are not compelled to copy the source along with the object code. - + 4. You may not copy, modify, sublicense, or distribute the Program except as expressly provided under this License. Any attempt otherwise to copy, modify, sublicense or distribute the Program is @@ -227,7 +225,7 @@ impose that choice. This section is intended to make thoroughly clear what is believed to be a consequence of the rest of this License. - + 8. If the distribution and/or use of the Program is restricted in certain countries either by patents or by copyrighted interfaces, the original copyright holder who places the Program under this License @@ -280,3 +278,63 @@ PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. END OF TERMS AND CONDITIONS + + How to Apply These Terms to Your New Programs + + If you develop a new program, and you want it to be of the greatest +possible use to the public, the best way to achieve this is to make it +free software which everyone can redistribute and change under these terms. + + To do so, attach the following notices to the program. It is safest +to attach them to the start of each source file to most effectively +convey the exclusion of warranty; and each file should have at least +the "copyright" line and a pointer to where the full notice is found. + + + Copyright (C) + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this +when it starts in an interactive mode: + + Gnomovision version 69, Copyright (C) year name of author + Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + , 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Library General +Public License instead of this License. \ No newline at end of file diff --git a/Frameworks/HighlyExperimental/HighlyExperimental.xcodeproj/project.pbxproj b/Frameworks/HighlyExperimental/HighlyExperimental.xcodeproj/project.pbxproj new file mode 100644 index 000000000..1c9508435 --- /dev/null +++ b/Frameworks/HighlyExperimental/HighlyExperimental.xcodeproj/project.pbxproj @@ -0,0 +1,389 @@ +// !$*UTF8*$! +{ + archiveVersion = 1; + classes = { + }; + objectVersion = 46; + objects = { + +/* Begin PBXBuildFile section */ + 8360EF1E17F92C91005208A4 /* InfoPlist.strings in Resources */ = {isa = PBXBuildFile; fileRef = 8360EF1C17F92C91005208A4 /* InfoPlist.strings */; }; + 8360EF5A17F92DB0005208A4 /* bios.c in Sources */ = {isa = PBXBuildFile; fileRef = 8360EF4717F92DB0005208A4 /* bios.c */; }; + 8360EF5B17F92DB0005208A4 /* bios.h in Headers */ = {isa = PBXBuildFile; fileRef = 8360EF4817F92DB0005208A4 /* bios.h */; settings = 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8360EF0F17F92C91005208A4 + + primary + + + 8360EF2617F92C91005208A4 + + primary + + + + + diff --git a/Frameworks/HighlyExperimental/HighlyExperimental/Core/.gitignore b/Frameworks/HighlyExperimental/HighlyExperimental/Core/.gitignore new file mode 100644 index 000000000..32cff875e --- /dev/null +++ b/Frameworks/HighlyExperimental/HighlyExperimental/Core/.gitignore @@ -0,0 +1,3 @@ +*.user +Debug +Release \ No newline at end of file diff --git a/Frameworks/HighlyExperimental/HighlyExperimental/Core/Core.pro b/Frameworks/HighlyExperimental/HighlyExperimental/Core/Core.pro new file mode 100644 index 000000000..2320d08b3 --- /dev/null +++ b/Frameworks/HighlyExperimental/HighlyExperimental/Core/Core.pro @@ -0,0 +1,54 @@ +#------------------------------------------------- +# +# Project created by QtCreator 2012-12-26T20:57:48 +# +#------------------------------------------------- + +QT -= core gui + +TARGET = PSXCore +TEMPLATE = lib +CONFIG += staticlib + +DEFINES += EMU_COMPILE EMU_LITTLE_ENDIAN HAVE_STDINT_H + +SOURCES += \ + psx.c \ + ioptimer.c \ + iop.c \ + bios.c \ + r3000dis.c \ + r3000asm.c \ + r3000.c \ + vfs.c \ + spucore.c \ + spu.c \ + mkhebios.c + +HEADERS += \ + ioptimer.h \ + iop.h \ + emuconfig.h \ + bios.h \ + psx.h \ + r3000asm.h \ + r3000.h \ + vfs.h \ + spucore.h \ + spu.h \ + r3000dis.h \ + mkhebios.h \ + mkhebios_overlays.h \ + mkhebios_scripts.h +unix:!symbian { + maemo5 { + target.path = /opt/usr/lib + } else { + target.path = /usr/lib + } + INSTALLS += target +} + +OTHER_FILES += \ + Readme.txt \ + r3000predict.txt diff --git a/Frameworks/HighlyExperimental/HighlyExperimental/Core/PSXCore.vcxproj b/Frameworks/HighlyExperimental/HighlyExperimental/Core/PSXCore.vcxproj new file mode 100644 index 000000000..978230fbd --- /dev/null +++ b/Frameworks/HighlyExperimental/HighlyExperimental/Core/PSXCore.vcxproj @@ -0,0 +1,142 @@ + + + + + Debug + Win32 + + + Release + Win32 + + + + {D578378A-A579-461A-A4E8-BA2C548B12A7} + + + + + + + + + + + + StaticLibrary + Unicode + v100 + + + StaticLibrary + Unicode + true + v100 + + + + + + + + + + + + + + + <_ProjectFileVersion>10.0.21006.1 + AllRules.ruleset + + + AllRules.ruleset + + + + + + MaxSpeed + AnySuitable + true + Speed + true + WIN32;NDEBUG;_LIB;EMU_COMPILE;EMU_LITTLE_ENDIAN;%(PreprocessorDefinitions) + true + MultiThreaded + false + true + Fast + .\Release/PSXCore.pch + .\Release/ + .\Release/ + .\Release/ + Level3 + true + FastCall + + + NDEBUG;%(PreprocessorDefinitions) + 0x0409 + + + true + + + + + Disabled + OnlyExplicitInline + WIN32;_DEBUG;_LIB;EMU_COMPILE;EMU_LITTLE_ENDIAN;%(PreprocessorDefinitions) + EnableFastChecks + MultiThreadedDebug + .\Debug/PSXCore.pch + .\Debug/ + .\Debug/ + .\Debug/ + Level3 + true + ProgramDatabase + FastCall + + + _DEBUG;%(PreprocessorDefinitions) + 0x0409 + + + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/Frameworks/HighlyExperimental/HighlyExperimental/Core/PSXCore.vcxproj.filters b/Frameworks/HighlyExperimental/HighlyExperimental/Core/PSXCore.vcxproj.filters new file mode 100644 index 000000000..f0574b4e0 --- /dev/null +++ b/Frameworks/HighlyExperimental/HighlyExperimental/Core/PSXCore.vcxproj.filters @@ -0,0 +1,92 @@ + + + + + {01bc00bc-020b-4814-b54f-ac49730e2d00} + h;hpp;hxx;hm;inl + + + {17290422-dd57-475a-a6e4-acc55635519c} + cpp;c;cxx;rc;def;r;odl;idl;hpj;bat + + + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + \ No newline at end of file diff --git a/Frameworks/HighlyExperimental/HighlyExperimental/Core/Readme.txt b/Frameworks/HighlyExperimental/HighlyExperimental/Core/Readme.txt new file mode 100644 index 000000000..287228b76 --- /dev/null +++ b/Frameworks/HighlyExperimental/HighlyExperimental/Core/Readme.txt @@ -0,0 +1,51 @@ +PSX emulation core - PS1/PS2 + +This core emulates the PS2 IOP, which can conveniently be dropped into PS1 +compatibility mode to play PS1 sound as well. + +The unfortunate dirty secret here is that Sony BIOS is used. Originally this +was the plain 512K SCPH1001 image we all know and love. But when PS2 support +was added, starting with core version 0007 (HE 1.08), a new technique was used. +A PS2 BIOS image (5.0 North American) is stripped module-by-module to just the +necessary code for sound playing, plus PS1 compatibility (TBIN/SBIN). The +result is about 350K smaller when compressed. + +Making this stuff 100% legal (via IOP kernel and PS1 BIOS HLE) is on the to-do +list. + + +mkhebios - This directory contains the tools for generating the new-style PS2 + BIOS images. + +he - Source code for HE IOP module. This is the code that handles "hefile:" + requests. Compiled into an .IRX file and then included in the mkhebios + process. + + +SHTest - A system for testing the emulation core for byte order / alignment + issues, by compiling it to a sh-arm-elf target and then running it in a simple + emulator. Slow, but effective. + + +bios.c - when compiled, contains the BIOS image. Also includes some environment + variable-like stuff (can be set in mkhebios). + +iop.c - IOP emulation (mostly just glue between other modules) + +ioptimer.c - IOP timers (root counters), both the 16-bit PS1 style and 32-bit + PS2 style. + +psx.c - top-level PS1/PS2 emulation. + +r3000.c - R3000 core. all C, all slow (though with the wait loop detection, + this hasn't been a big deal). + +r3000asm.c - R3000 quick assembler as used in PSFLab. + +r3000dis.c - R3000 disassembler (also as used in PSFLab). + +spu.c - SPU1 or SPU2 emulation. + +spucore.c - Emulates one SPU core (24 channels). PS2 has a pair of these. + +vfs.c - Virtual PSF2 filesystem stuff. diff --git a/Frameworks/HighlyExperimental/HighlyExperimental/Core/bios.c b/Frameworks/HighlyExperimental/HighlyExperimental/Core/bios.c new file mode 100644 index 000000000..ecf1ab9f7 --- /dev/null +++ b/Frameworks/HighlyExperimental/HighlyExperimental/Core/bios.c @@ -0,0 +1,126 @@ +///////////////////////////////////////////////////////////////////////////// +// +// bios - Holds BIOS image and can retrieve environment data +// +///////////////////////////////////////////////////////////////////////////// + +#ifndef EMU_COMPILE +#error "Hi I forgot to set EMU_COMPILE" +#endif + +#include "bios.h" + +///////////////////////////////////////////////////////////////////////////// + +static uint8 *image = {0}; +static uint32 image_size = 0; + +uint8* EMU_CALL bios_get_image_native(void) { return image; } +uint32 EMU_CALL bios_get_imagesize(void) { return image_size; } + +///////////////////////////////////////////////////////////////////////////// +// +// Static init +// +void EMU_CALL bios_set_image(uint8 *_image, uint32 _size) { +#ifdef EMU_BIG_ENDIAN + uint32 i; + for (i = 0; i < _size; i += 4) { + uint8 a = _image[i + 0]; + uint8 b = _image[i + 1]; + _image[i + 0] = _image[i + 3]; + _image[i + 1] = _image[i + 2]; + _image[i + 2] = b; + _image[i + 3] = a; + } +#endif + image = _image; + image_size = _size; +} + +///////////////////////////////////////////////////////////////////////////// +// +// Find environment variables +// Returns nonzero on error +// +sint32 EMU_CALL bios_getenv( + const char *name, + char *dest, + sint32 dest_l +) { + uint8 *romnative = bios_get_image_native(); + uint8 whole_env_area[129]; + uint8 *env; + uint8 *banner = "Highly Experimental"; + sint32 banner_l = strlen(banner); + sint32 name_l = strlen(name); + sint32 i; + + for(i = 0; i < 128; i++) { + sint32 byteofs = 0x80 + (i ^ (EMU_ENDIAN_XOR(3))); + whole_env_area[i] = romnative[byteofs]; + } + whole_env_area[128] = 0; + + env = whole_env_area; + + if(!dest_l) return 1; + if(memcmp(env, banner, banner_l)) return 1; + env += banner_l; + + for(;;) { + sint32 isquote = 0; + uint8 *varnamestart; + uint8 *varnameend; + uint8 *varvalstart; + uint8 *varvalend; + sint32 varnamelen; + sint32 varvallen; + // find a variable name + for(;; env++) { uint8 c = *env; if(!c) return 1; if(c != ' ') break; } + varnamestart = env; + // find where it ends + for(;; env++) { uint8 c = *env; if(!c) return 1; if(c == '=') break; } + varnameend = env; + // eat trailing spaces + while( + (varnameend > varnamestart) && + (varnameend[-1] == ' ') + ) varnameend--; + // skip equals sign + env++; + // compute length + varnamelen = varnameend - varnamestart; + // find the value + for(;; env++) { uint8 c = *env; if(!c) return 1; if(c != ' ') break; } + varvalstart = env; + // if it's a quote, handle it as such + if(*env == '\"') { varvalstart++; env++; isquote = 1; } + // seek to the end of the value + for(;; env++) { + uint8 c = *env; + if(!c) break; + if(isquote && c == '\"') break; + if((!isquote) && c == ' ') break; + } + varvalend = env; + // skip trailing quote if it's there + if(isquote && *env == '\"') env++; + // compute length + varvallen = varvalend - varvalstart; + + // now, if this is the variable name we want... + if(varnamelen == name_l && !memcmp(varnamestart, name, name_l)) { + // return it in the destination buffer + if(varvallen > (dest_l - 1)) varvallen = (dest_l - 1); + if(varvallen) memcpy(dest, varvalstart, varvallen); + dest[varvallen] = 0; + return 0; + } + + } + + return 1; +} + +///////////////////////////////////////////////////////////////////////////// diff --git a/Frameworks/HighlyExperimental/HighlyExperimental/Core/bios.h b/Frameworks/HighlyExperimental/HighlyExperimental/Core/bios.h new file mode 100644 index 000000000..5ed45f026 --- /dev/null +++ b/Frameworks/HighlyExperimental/HighlyExperimental/Core/bios.h @@ -0,0 +1,35 @@ +///////////////////////////////////////////////////////////////////////////// +// +// bios - Holds BIOS image and can retrieve environment data +// +///////////////////////////////////////////////////////////////////////////// + +#ifndef __PSX_BIOS_H__ +#define __PSX_BIOS_H__ + +#include "emuconfig.h" + +#ifdef __cplusplus +extern "C" { +#endif + +uint8* EMU_CALL bios_get_image_native(void); +uint32 EMU_CALL bios_get_imagesize(void); + +void EMU_CALL bios_set_image(uint8 *, uint32); + +/* +** Find environment variables +** Returns nonzero on error +*/ +sint32 EMU_CALL bios_getenv( + const char *name, + char *dest, + sint32 dest_l +); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Frameworks/HighlyExperimental/HighlyExperimental/Core/emuconfig.h b/Frameworks/HighlyExperimental/HighlyExperimental/Core/emuconfig.h new file mode 100644 index 000000000..57d06eeef --- /dev/null +++ b/Frameworks/HighlyExperimental/HighlyExperimental/Core/emuconfig.h @@ -0,0 +1,101 @@ +///////////////////////////////////////////////////////////////////////////// +// +// Configuration for emulation libraries +// +///////////////////////////////////////////////////////////////////////////// + +#ifndef __EMUCONFIG_H__ +#define __EMUCONFIG_H__ + +///////////////////////////////////////////////////////////////////////////// + +#include +#include +#include +#include + +///////////////////////////////////////////////////////////////////////////// +// +// One of these has to be defined when compiling the library. +// Shouldn't be necessary for using it. +// +#if defined(EMU_COMPILE) && !defined(EMU_BIG_ENDIAN) && !defined(EMU_LITTLE_ENDIAN) +#error "Hi I forgot to set EMU_x_ENDIAN" +#endif +#if defined(EMU_COMPILE) && defined(EMU_BIG_ENDIAN) && defined(EMU_LITTLE_ENDIAN) +#error "Both byte orders should not be defined" +#endif + +///////////////////////////////////////////////////////////////////////////// +// +// WIN32 native project definitions +// +///////////////////////////////////////////////////////////////////////////// +#if defined(WIN32) && !defined(__GNUC__) + +#define EMU_CALL __fastcall +#define EMU_CALL_ __cdecl +#define EMU_INLINE __inline + +#define uint8 unsigned char +#define uint16 unsigned short +#define uint32 unsigned int +#define uint64 unsigned __int64 +#define sint8 signed char +#define sint16 signed short +#define sint32 signed int +#define sint64 signed __int64 + +///////////////////////////////////////////////////////////////////////////// +// +// LINUX / other platform definitions +// +///////////////////////////////////////////////////////////////////////////// +#else + +//#if defined(__GNUC__) && defined(__i386__) +//#define EMU_CALL __attribute__((__regparm__(2))) +//#else +#define EMU_CALL +//#endif + +#define EMU_CALL_ +#define EMU_INLINE __inline + +#ifdef HAVE_STDINT_H +#include +#define uint8 uint8_t +#define uint16 uint16_t +#define uint32 uint32_t +#define uint64 uint64_t +#define sint8 int8_t +#define sint16 int16_t +#define sint32 int32_t +#define sint64 int64_t +#else +#define uint8 unsigned char +#define uint16 unsigned short +#define uint32 unsigned int +#define uint64 unsigned long long +#define sint8 signed char +#define sint16 signed short +#define sint32 signed int +#define sint64 signed long long +#endif + +#endif + +#ifdef EMU_BIG_ENDIAN +#define EMU_ENDIAN_XOR_L2H(x) (x) +#define EMU_ENDIAN_XOR_B2H(x) (0) +#else +#define EMU_ENDIAN_XOR_L2H(x) (0) +#define EMU_ENDIAN_XOR_B2H(x) (x) +#endif + +// deprecated +#define EMU_ENDIAN_XOR(x) EMU_ENDIAN_XOR_L2H(x) + +///////////////////////////////////////////////////////////////////////////// + +#endif diff --git a/Frameworks/HighlyExperimental/HighlyExperimental/Core/iop.c b/Frameworks/HighlyExperimental/HighlyExperimental/Core/iop.c new file mode 100644 index 000000000..df32958ee --- /dev/null +++ b/Frameworks/HighlyExperimental/HighlyExperimental/Core/iop.c @@ -0,0 +1,1205 @@ +///////////////////////////////////////////////////////////////////////////// +// +// iop - PS2 IOP emulation; can also do PS1 via compatibility mode +// +///////////////////////////////////////////////////////////////////////////// + +#ifndef EMU_COMPILE +#error "Hi I forgot to set EMU_COMPILE" +#endif + +#include "iop.h" + +#include "psx.h" +#include "ioptimer.h" +#include "r3000.h" +#include "spu.h" +#include "bios.h" + +//#include + +///////////////////////////////////////////////////////////////////////////// +// +// Simulate DMA delay for harsh compat mode +// +#define DMA_SPU_CYCLES_PER_HALFWORD (8) + +///////////////////////////////////////////////////////////////////////////// +// +// Static information +// +sint32 EMU_CALL iop_init(void) { + return 0; +} + +//////////////////////////////////////////////////////////////////////////////// +/* +** State information +*/ + +// +// names from INTRMAN.H +// +#define IOP_INT_VBLANK (1<<0) +#define IOP_INT_GM (1<<1) +#define IOP_INT_CDROM (1<<2) +#define IOP_INT_DMA (1<<3) +#define IOP_INT_RTC0 (1<<4) +#define IOP_INT_RTC1 (1<<5) +#define IOP_INT_RTC2 (1<<6) +#define IOP_INT_SIO0 (1<<7) +#define IOP_INT_SIO1 (1<<8) +#define IOP_INT_SPU (1<<9) +#define IOP_INT_PIO (1<<10) +#define IOP_INT_EVBLANK (1<<11) +#define IOP_INT_DVD (1<<12) +#define IOP_INT_PCMCIA (1<<13) +#define IOP_INT_RTC3 (1<<14) +#define IOP_INT_RTC4 (1<<15) +#define IOP_INT_RTC5 (1<<16) +#define IOP_INT_SIO2 (1<<17) +#define IOP_INT_HTR0 (1<<18) +#define IOP_INT_HTR1 (1<<19) +#define IOP_INT_HTR2 (1<<20) +#define IOP_INT_HTR3 (1<<21) +#define IOP_INT_USB (1<<22) +#define IOP_INT_EXTR (1<<23) +#define IOP_INT_FWRE (1<<24) +#define IOP_INT_FDMA (1<<25) + +struct IOP_INTR { + uint32 en; + uint32 signaled; + uint8 is_masked; +}; + +struct IOP_DMA_CHAN { + uint32 MADR; + uint32 BCR; + uint32 CHCR; + uint64 cycles_until_interrupt; +}; + +struct IOP_DMA { + struct IOP_DMA_CHAN chan[7]; + uint32 DPCR; + uint32 DICR; +}; + +struct IOP_EVENT { + uint64 time; + uint32 type; + char *fmt; // Always points into constant static data. safe. + uint32 arg[4]; +}; + +#define IOP_MAX_EVENTS (16) + +struct IOP_STATE { + struct IOP_STATE *myself; // Pointer used to check location invariance + + uint8 version; + uint32 offset_to_map_load; + uint32 offset_to_map_store; + uint32 offset_to_ioptimer; + uint32 offset_to_r3000; + uint32 offset_to_spu; + uint32 ram[0x200000/4]; + uint32 scratch[0x400/4]; + uint64 odometer; +// struct IOP_INTR intr[2]; + struct IOP_INTR intr; + struct IOP_DMA dma[2]; + sint16 *sound_buffer; // TEMPORARY pointer. safe. + uint32 sound_buffer_samples_free; + uint32 sound_cycles_pending; + uint32 sound_cycles_until_interrupt; + struct IOP_EVENT event[IOP_MAX_EVENTS]; + uint32 event_write_index; + uint32 event_count; + uint32 event_mask; + uint8 *audit_map; // Externally-registered pointer. safe. + uint32 audit_bytes_used; + uint8 compat_level; + uint8 quitflag; + uint8 fatalflag; + uint32 cycles_per_sample; + void *psx_state; // TEMPORARY pointer. safe. +}; + +#define IOPSTATE ((struct IOP_STATE*)(state)) +#define MAPLOAD ((void*)(((char*)(state))+(IOPSTATE->offset_to_map_load))) +#define MAPSTORE ((void*)(((char*)(state))+(IOPSTATE->offset_to_map_store))) +#define IOPTIMERSTATE ((void*)(((char*)(state))+(IOPSTATE->offset_to_ioptimer))) +#define R3000STATE ((void*)(((char*)(state))+(IOPSTATE->offset_to_r3000))) +#define SPUSTATE ((void*)(((char*)(state))+(IOPSTATE->offset_to_spu))) + +extern const uint32 iop_map_load_entries; +extern const uint32 iop_map_store_entries; + +uint32 EMU_CALL iop_get_state_size(int version) { + uint32 size = 0; + if(version != 2) { version = 1; } + size += sizeof(struct IOP_STATE); + size += sizeof(struct R3000_MEMORY_MAP) * iop_map_load_entries; + size += sizeof(struct R3000_MEMORY_MAP) * iop_map_store_entries; + size += ioptimer_get_state_size(); + size += r3000_get_state_size(); + size += spu_get_state_size(version); + return size; +} + +#define PSXRAM_BYTE_NATIVE ((uint8*)(IOPSTATE->ram)) +#define BIOS_BYTE_NATIVE ((uint8*)(bios_rom_native)) +#define SCRATCH_BYTE_NATIVE ((uint8*)(IOPSTATE->scratch)) + +static void EMU_CALL recompute_memory_maps(struct IOP_STATE *state); +static void EMU_CALL iop_advance(void *state, uint32 elapse); + +void EMU_CALL iop_clear_state(void *state, int version) { + uint32 offset; + if(version != 2) { version = 1; } + /* Clear local struct */ + memset(state, 0, sizeof(struct IOP_STATE)); + /* Set version */ + IOPSTATE->version = version; + /* Set up offsets */ + offset = sizeof(struct IOP_STATE); + IOPSTATE->offset_to_map_load = offset; offset += sizeof(struct R3000_MEMORY_MAP) * iop_map_load_entries; + IOPSTATE->offset_to_map_store = offset; offset += sizeof(struct R3000_MEMORY_MAP) * iop_map_store_entries; + IOPSTATE->offset_to_ioptimer = offset; offset += ioptimer_get_state_size(); + IOPSTATE->offset_to_r3000 = offset; offset += r3000_get_state_size(); + IOPSTATE->offset_to_spu = offset; offset += spu_get_state_size(version); + // + // Set other variables + // + IOPSTATE->cycles_per_sample = 768; + // + // Take care of substructures: memory map, R3000 state, SPU state + // + recompute_memory_maps(IOPSTATE); + + ioptimer_clear_state(IOPTIMERSTATE); + // default to NTSC / 60Hz + iop_set_refresh(IOPSTATE, 60); + + r3000_clear_state(R3000STATE); + r3000_set_prid(R3000STATE, (version == 1) ? 0x02 : 0x10); + + r3000_set_advance_callback(R3000STATE, iop_advance, IOPSTATE); + r3000_set_memory_maps(R3000STATE, MAPLOAD, MAPSTORE); + + spu_clear_state(SPUSTATE, version); + + // Done +} + +///////////////////////////////////////////////////////////////////////////// +// +// Set the screen refresh rate in Hz (50 or 60 for PAL or NTSC) +// Only 50 or 60 are valid; other values will be ignored +// +void EMU_CALL iop_set_refresh(void *state, uint32 refresh) { + if(refresh == 50 || refresh == 60) { + ioptimer_set_rates(IOPTIMERSTATE, + (IOPSTATE->version == 1) ? 33868800 : 36864000, + (IOPSTATE->version == 1) ? 429 : 858, + (refresh == 60) ? 262 : 312, + (refresh == 60) ? 224 : 240, + refresh + ); + } +} + +//////////////////////////////////////////////////////////////////////////////// +// +// Location invariance handlers +// + +// +// Recompute all internally-kept pointers +// +static void EMU_CALL location_recompute(struct IOP_STATE *state) { + recompute_memory_maps(state); + r3000_set_advance_callback(R3000STATE, iop_advance, IOPSTATE); + r3000_set_memory_maps(R3000STATE, MAPLOAD, MAPSTORE); + state->myself = state; +} + +// +// Check to see if this structure has moved, and if so, recompute +// +// This is currently ONLY done on iop_execute +// +static EMU_INLINE void EMU_CALL location_check(struct IOP_STATE *state) { + if(state->myself == state) return; + location_recompute(state); +} + +//////////////////////////////////////////////////////////////////////////////// +// +// Obtain substates +// +// These require no location checks as the substates are obtained via +// relative offsets +// +void* EMU_CALL iop_get_r3000_state(void *state) { return R3000STATE; } +void* EMU_CALL iop_get_spu_state (void *state) { return SPUSTATE ; } + +//////////////////////////////////////////////////////////////////////////////// +/* +** Register a map for auditing purposes +** (must contain 1 byte for every RAM byte) +** +** Pass NULL to disable auditing. +*/ +void EMU_CALL iop_register_map_for_auditing(void *state, uint8 *map) { + IOPSTATE->audit_map = map; + IOPSTATE->audit_bytes_used = 0; + recompute_memory_maps(IOPSTATE); +} + +/* +** Auditing functions +*/ +static EMU_INLINE void EMU_CALL audit(struct IOP_STATE *state, uint32 address, uint32 length, uint8 t) { + for(; length; length--, address++) { + if(!(state->audit_map[address & 0x1FFFFF])) { + if(t == IOP_AUDIT_READ) { state->audit_bytes_used++; } + state->audit_map[address & 0x1FFFFF] = t; + } + } +} + +uint32 EMU_CALL iop_get_bytes_used_in_audit(void *state) { + // No location check required + return IOPSTATE->audit_bytes_used; +} + +/* +** R3000 memory map callbacks for auditing +*/ +static uint32 EMU_CALL audit_lw(void *state, uint32 a, uint32 mask) { + +//PSXTRACE3("audit_lw(%08X,%08X,%08X)\n",state,a,mask); + + a &= 0x1FFFFC; + if((mask & 0x000000FF) && (!(IOPSTATE->audit_map[a+0]))) { IOPSTATE->audit_map[a+0] = IOP_AUDIT_READ; IOPSTATE->audit_bytes_used++; } + if((mask & 0x0000FF00) && (!(IOPSTATE->audit_map[a+1]))) { IOPSTATE->audit_map[a+1] = IOP_AUDIT_READ; IOPSTATE->audit_bytes_used++; } + if((mask & 0x00FF0000) && (!(IOPSTATE->audit_map[a+2]))) { IOPSTATE->audit_map[a+2] = IOP_AUDIT_READ; IOPSTATE->audit_bytes_used++; } + if((mask & 0xFF000000) && (!(IOPSTATE->audit_map[a+3]))) { IOPSTATE->audit_map[a+3] = IOP_AUDIT_READ; IOPSTATE->audit_bytes_used++; } + return (*((uint32*)((PSXRAM_BYTE_NATIVE)+a))) & mask; +} + +static void EMU_CALL audit_sw(void *state, uint32 a, uint32 d, uint32 mask) { + +//PSXTRACE3("audit_sw(state,%08X,%08X,%08X)\n",a,d,mask); + + a &= 0x1FFFFC; + if((mask & 0x000000FF) && (!(IOPSTATE->audit_map[a+0]))) IOPSTATE->audit_map[a+0] = IOP_AUDIT_WRITE; + if((mask & 0x0000FF00) && (!(IOPSTATE->audit_map[a+1]))) IOPSTATE->audit_map[a+1] = IOP_AUDIT_WRITE; + if((mask & 0x00FF0000) && (!(IOPSTATE->audit_map[a+2]))) IOPSTATE->audit_map[a+2] = IOP_AUDIT_WRITE; + if((mask & 0xFF000000) && (!(IOPSTATE->audit_map[a+3]))) IOPSTATE->audit_map[a+3] = IOP_AUDIT_WRITE; + (*((uint32*)((PSXRAM_BYTE_NATIVE)+a))) &= (~mask); + (*((uint32*)((PSXRAM_BYTE_NATIVE)+a))) |= (d & mask); +} + +//////////////////////////////////////////////////////////////////////////////// +// +// Event handling +// +// None of this needs location checking. +// +static void EMU_CALL event( + struct IOP_STATE *state, + uint32 type, + char *fmt, + uint32 arg0, + uint32 arg1, + uint32 arg2, + uint32 arg3 +) { + if(state->event_mask & (1 << type)) { + struct IOP_EVENT *ev = state->event + state->event_write_index; + state->event_write_index++; + if(state->event_write_index >= IOP_MAX_EVENTS) { state->event_write_index = 0; } + if(state->event_count < IOP_MAX_EVENTS) { state->event_count++; } + /* + ** Copy event info + */ + ev->time = state->odometer; + ev->type = type; + ev->fmt = fmt; + ev->arg[0] = arg0; + ev->arg[1] = arg1; + ev->arg[2] = arg2; + ev->arg[3] = arg3; + } +} + +void EMU_CALL iop_clear_events(void *state) { + IOPSTATE->event_count = 0; +} + +uint32 EMU_CALL iop_get_event_count(void *state) { + return IOPSTATE->event_count; +} + +void EMU_CALL iop_get_event(void *state, uint64 *time, uint32 *type, char **fmt, uint32 *arg) { + struct IOP_EVENT *ev; + if(!IOPSTATE->event_count) return; + ev = IOPSTATE->event + (((IOPSTATE->event_write_index + IOP_MAX_EVENTS) - IOPSTATE->event_count) % IOP_MAX_EVENTS); + if(time) *time = ev->time; + if(type) *type = ev->type; + if(fmt) *fmt = ev->fmt; + if(arg) { + arg[0] = ev->arg[0]; + arg[1] = ev->arg[1]; + arg[2] = ev->arg[2]; + arg[3] = ev->arg[3]; + } +} + +void EMU_CALL iop_dismiss_event(void *state) { + if(IOPSTATE->event_count) { IOPSTATE->event_count--; } +} + +///////////////////////////////////////////////////////////////////////////// +// +// misc register load +// +static uint32 EMU_CALL misc_lw(struct IOP_STATE *state, uint32 a, uint32 mask) { + uint32 d = 0; + switch(a & 0x1FFFFFFC) { + case 0x1F801450: + if(state->version == 1) { d = 0x0000008; } + else { d = 0x0000000; } + break; + } + event(state, IOP_EVENT_REG_LOAD, "Misc. load (%08X,%08X)=%08X", a, mask, d, 0); + return d; +} + +//////////////////////////////////////////////////////////////////////////////// +/* +** Interrupt controller +*/ + +/* +** Update the CPU-side interrupt pending flag +*/ +static void EMU_CALL intr_update_ip(struct IOP_STATE *state) { + uint32 ip = 0; + if( + (!(state->intr.is_masked)) && + ((state->intr.signaled & state->intr.en) != 0) + ) { ip |= 0x4; } + r3000_setinterrupt(R3000STATE, ip); +} + +/* +** Signal an interrupt (hardware-side interrupt bits are used) +*/ +static void EMU_CALL intr_signal(struct IOP_STATE *state, uint32 i) { + + event(state, IOP_EVENT_INTR_SIGNAL, "Interrupt %X signaled", i, 0, 0, 0); + + if(!(state->intr.signaled & i)) { + state->intr.signaled |= i; + intr_update_ip(state); + } +} + +/* +** INTR register load +*/ +static uint32 EMU_CALL intr_lw(struct IOP_STATE *state, uint32 a, uint32 mask) { + uint32 d = 0; + + switch(a & 0x7C) { + case 0x70: d = state->intr.signaled; break; + case 0x74: d = state->intr.en; break; + case 0x78: + d = (state->intr.is_masked) ? 0 : 1; + state->intr.is_masked = 1; + intr_update_ip(state); + break; + } + +//end: + d &= mask; + event(state, IOP_EVENT_REG_LOAD, "INTR load (%08X,%08X)=%08X", a, mask, d, 0); + return d; +} + +/* +** INTR register store +*/ +static void EMU_CALL intr_sw(struct IOP_STATE *state, uint32 a, uint32 d, uint32 mask) { + + event(state, IOP_EVENT_REG_STORE, "INTR store (%08X,%08X,%08X)", a, d, mask, 0); + + switch(a & 0x7C) { + case 0x70: + // Acknowledge + state->intr.signaled &= (d | (~mask)); + intr_update_ip(state); + break; + case 0x74: + // Change enable bits + state->intr.en = (state->intr.en & (~mask)) | (d & mask); + intr_update_ip(state); + break; + case 0x78: + // Mask/unmask + state->intr.is_masked = (d ^ 1) & 1; + intr_update_ip(state); + break; + } + +} + +//////////////////////////////////////////////////////////////////////////////// +/* +** DMA +*/ + +/* +** Signal completion on a DMA channel +*/ +static void EMU_CALL dma_signal_completion(struct IOP_STATE *state, uint32 chan) { + uint32 core = chan / 7; + chan %= 7; + + /* Reset transfer busy bit */ + state->dma[core].chan[chan].CHCR &= (~0x01000000); + + /* TODO: see how the core affects the int numbers */ + + if(state->dma[core].DICR & (0x00010000 << (chan))) { + state->dma[core].DICR |= (0x01000000 << (chan)); + intr_signal(state, IOP_INT_DMA); + } +} + +/* +** Initiate a DMA transfer +*/ +static void EMU_CALL dma_transfer(struct IOP_STATE *state, uint32 core, uint32 chan) { + uint32 realchan = 7 * core + chan; + uint32 mem_address = (state->dma[core].chan[chan].MADR ); + uint32 blocksize = (state->dma[core].chan[chan].BCR >> 0) & 0xFFFF; + uint32 blockcount = (state->dma[core].chan[chan].BCR >> 16) & 0xFFFF; + int is_writing = (state->dma[core].chan[chan].CHCR >> 0) & 1; + int is_continuous = (state->dma[core].chan[chan].CHCR >> 9) & 1; + int is_linked = (state->dma[core].chan[chan].CHCR >> 10) & 1; + uint32 len = blocksize * 4 * blockcount; +// uint32 i; + uint64 cycles_delay = 0; + + event(state, IOP_EVENT_DMA_TRANSFER, + is_writing ? + "DMA ch.%d write (%08X, %08X)" : + "DMA ch.%d read (%08X, %08X)", + realchan, mem_address, len, 0 + ); + + mem_address &= 0x1FFFFC; + if(!len) return; + + /* + ** Remember to audit! + ** TODO: audit linking: SPU with IOP etc. + */ + if(state->audit_map) { + audit(state, mem_address, len, is_writing ? IOP_AUDIT_READ : IOP_AUDIT_WRITE); + } + + switch(realchan) { + case 4: // SPU CORE0 + spu_dma(SPUSTATE, 0, PSXRAM_BYTE_NATIVE, mem_address & 0x1FFFFC, 0x1FFFFC, len, is_writing); + cycles_delay = DMA_SPU_CYCLES_PER_HALFWORD * (len / 2); + break; + case 7: // SPU CORE1 + spu_dma(SPUSTATE, 1, PSXRAM_BYTE_NATIVE, mem_address & 0x1FFFFC, 0x1FFFFC, len, is_writing); + cycles_delay = DMA_SPU_CYCLES_PER_HALFWORD * (len / 2); + break; + case 10: // SIF + break; + } + + /* + ** Behavior here depends on compat level + */ + switch(state->compat_level) { + case IOP_COMPAT_FRIENDLY: + /* Interrupt immediately */ + dma_signal_completion(state, realchan); + break; + case IOP_COMPAT_HARSH: + /* Schedule interrupt for later */ + if(!cycles_delay) { cycles_delay = 1; } + state->dma[core].chan[chan].cycles_until_interrupt = cycles_delay; + break; + default: + /* Default behavior: friendly, interrupt immediately */ + dma_signal_completion(state, realchan); + break; + } + +} + +/* +** DMA register load +*/ +static uint32 EMU_CALL dma_lw(struct IOP_STATE *state, uint32 core, uint32 a, uint32 mask) { + uint32 d = 0; + struct IOP_DMA *dma; + uint8 chan; + + dma = &(state->dma[core]); + chan = (a >> 4) & 7; + if(chan == 7) { + switch(a & 0xC) { + case 0x0: d = dma->DPCR; break; + case 0x4: d = dma->DICR; break; + case 0x8: d = 0; break; // sometimes this is blocked until it's 0 + } + } + +//end: + d &= mask; + event(state, IOP_EVENT_REG_LOAD, "DMA%d load (%08X,%08X)=%08X", core, a, mask, d); + return d; +} + +static uint32 EMU_CALL dma0_lw(struct IOP_STATE *state, uint32 a, uint32 mask) { return dma_lw(state, 0, a, mask); } +static uint32 EMU_CALL dma1_lw(struct IOP_STATE *state, uint32 a, uint32 mask) { return dma_lw(state, 1, a, mask); } + +/* +** DMA register store +*/ +static void EMU_CALL dma_sw(struct IOP_STATE *state, uint32 core, uint32 a, uint32 d, uint32 mask) { + struct IOP_DMA *dma; + uint8 chan; + + event(state, IOP_EVENT_REG_STORE, "DMA%d store (%08X,%08X,%08X)", core, a, d, mask); + + dma = &(state->dma[core]); + chan = (a >> 4) & 7; + if(chan == 7) { + switch(a & 0xC) { + case 0x0: dma->DPCR = (dma->DPCR & (~mask)) | (d & mask); break; + case 0x4: + if(mask & 0xFF000000) { dma->DICR &= ((~d) & 0xFF000000); } + if(mask & 0x00FF0000) { dma->DICR |= (( d) & 0x00FF0000); } + break; + case 0x8: // sometimes 0 is stored here + break; + } + } else { + switch(a & 0xC) { + case 0x0: dma->chan[chan].MADR = (dma->chan[chan].MADR & (~mask)) | (d & mask); break; + case 0x4: dma->chan[chan].BCR = (dma->chan[chan].BCR & (~mask)) | (d & mask); break; + case 0x8: + dma->chan[chan].CHCR = (dma->chan[chan].CHCR & (~mask)) | (d & mask); + /* Transfer being initiated */ + if(d & mask & 0x01000000) dma_transfer(state, core, chan); + break; + } + } + +} + +static void EMU_CALL dma0_sw(struct IOP_STATE *state, uint32 a, uint32 d, uint32 mask) { dma_sw(state, 0, a, d, mask); } +static void EMU_CALL dma1_sw(struct IOP_STATE *state, uint32 a, uint32 d, uint32 mask) { dma_sw(state, 1, a, d, mask); } + +//////////////////////////////////////////////////////////////////////////////// +/* +** Timers +*/ + +static uint32 EMU_CALL timer_lw(struct IOP_STATE *state, uint32 a, uint32 mask) { + uint32 d = 0; + event(state, IOP_EVENT_REG_LOAD, "Timer load (%08X,%08X)=%08X", a, mask, d, 0); + d = ioptimer_lw(IOPTIMERSTATE, a, mask); + return d & mask; +} + +static void EMU_CALL timer_sw(struct IOP_STATE *state, uint32 a, uint32 d, uint32 mask) { + event(state, IOP_EVENT_REG_STORE, "Timer store (%08X,%08X,%08X)", a, d, mask, 0); + ioptimer_sw(IOPTIMERSTATE, a, d, mask); +} + +//////////////////////////////////////////////////////////////////////////////// +/* +** SPU: Forward read/write/advance calls to the SPU code +*/ + +static void EMU_CALL flush_sound(struct IOP_STATE *state) { + uint32 samples_needed = state->sound_cycles_pending / (state->cycles_per_sample); + if(samples_needed > state->sound_buffer_samples_free) { + samples_needed = state->sound_buffer_samples_free; + } + if(!samples_needed) return; + + spu_render(SPUSTATE, state->sound_buffer, samples_needed); + + if(state->sound_buffer) state->sound_buffer += 2 * samples_needed; + state->sound_buffer_samples_free -= samples_needed; + state->sound_cycles_pending -= (state->cycles_per_sample) * samples_needed; +} + +/* +** Register loads/stores +*/ + +static uint32 EMU_CALL iop_spu_lw(void *state, uint32 a, uint32 mask) { + uint32 d = 0; + flush_sound(IOPSTATE); + if(mask & 0x0000FFFF) d |= ((((uint32)(spu_lh(SPUSTATE, (a&(~3))+0))) & 0xFFFF) << 0); + if(mask & 0xFFFF0000) d |= ((((uint32)(spu_lh(SPUSTATE, (a&(~3))+2))) & 0xFFFF) << 16); +//end: + d &= mask; + event(state, IOP_EVENT_REG_LOAD, "SPU load (%08X,%08X)=%08X", a, mask, d, 0); + return d; +} + +static void EMU_CALL iop_spu_sw(void *state, uint32 a, uint32 d, uint32 mask) { + event(state, IOP_EVENT_REG_STORE, "SPU store (%08X,%08X,%08X)", a, d, mask, 0); + flush_sound(IOPSTATE); + if(mask & 0x0000FFFF) spu_sh(SPUSTATE, (a&(~3))+0, d >> 0); + if(mask & 0xFFFF0000) spu_sh(SPUSTATE, (a&(~3))+2, d >> 16); +} + +static uint32 EMU_CALL iop_spu2_lw(void *state, uint32 a, uint32 mask) { + uint32 d = 0; + if(IOPSTATE->version == 2) { + flush_sound(IOPSTATE); + if(mask & 0x0000FFFF) d |= ((((uint32)(spu_lh(SPUSTATE, (a&(~3))+0))) & 0xFFFF) << 0); + if(mask & 0xFFFF0000) d |= ((((uint32)(spu_lh(SPUSTATE, (a&(~3))+2))) & 0xFFFF) << 16); + } +//end: + d &= mask; + event(state, IOP_EVENT_REG_LOAD, "SPU2 load (%08X,%08X)=%08X", a, mask, d, 0); + return d; +} + +static void EMU_CALL iop_spu2_sw(void *state, uint32 a, uint32 d, uint32 mask) { + event(state, IOP_EVENT_REG_STORE, "SPU2 store (%08X,%08X,%08X)", a, d, mask, 0); + if(IOPSTATE->version == 2) { + flush_sound(IOPSTATE); + if(mask & 0x0000FFFF) spu_sh(SPUSTATE, (a&(~3))+0, d >> 0); + if(mask & 0xFFFF0000) spu_sh(SPUSTATE, (a&(~3))+2, d >> 16); + } +} + +///////////////////////////////////////////////////////////////////////////// +// +// SIF register load +// +static uint32 EMU_CALL sif_lw(struct IOP_STATE *state, uint32 a, uint32 mask) { + uint32 d = 0; + switch(a & 0x7C) { + case 0x20: d = 0x00010000; break; + case 0x60: d = 0x1D000060; break; + } + d &= mask; + event(state, IOP_EVENT_REG_LOAD, "SIF load (%08X,%08X)=%08X", a, mask, d, 0); + return d; +} + +// +// SIF register store +// +static void EMU_CALL sif_sw(struct IOP_STATE *state, uint32 a, uint32 d, uint32 mask) { + + event(state, IOP_EVENT_REG_STORE, "SIF store (%08X,%08X,%08X)", a, d, mask, 0); + + switch(a & 0x7C) { + case 0x30: // seems to be a command of some kind + //dma_signal_completion(state, 10); + break; + case 0x60: + break; + } + +} + +//////////////////////////////////////////////////////////////////////////////// +/* +** hefile emucall +*/ + +static void EMU_CALL iop_emucall_sw(void *state, uint32 a, uint32 d, uint32 mask) { + sint32 type; + sint32 emufd; + sint32 ofs; + sint32 arg1; + sint32 arg2; + sint32 r; + if(mask != 0xFFFFFFFF) return; + if(d & 3) return; + type = *((sint32*)((PSXRAM_BYTE_NATIVE)+((d+(4*( 0 )))&0x1FFFFC))); + emufd = *((sint32*)((PSXRAM_BYTE_NATIVE)+((d+(4*( 1 )))&0x1FFFFC))); + ofs = *((sint32*)((PSXRAM_BYTE_NATIVE)+((d+(4*( 2 )))&0x1FFFFC))); + arg1 = *((sint32*)((PSXRAM_BYTE_NATIVE)+((d+(4*( 3 )))&0x1FFFFC))); + arg2 = *((sint32*)((PSXRAM_BYTE_NATIVE)+((d+(4*( 4 )))&0x1FFFFC))); + + // + // Log an event + // + switch(type) { + case 0: event(IOPSTATE, IOP_EVENT_VIRTUAL_IO, "Virtual console output(0x%X, 0x%X)", ofs, arg1, 0, 0); break; + case 1: event(IOPSTATE, IOP_EVENT_VIRTUAL_IO, "Virtual quit", 0, 0, 0, 0); break; + case 3: event(IOPSTATE, IOP_EVENT_VIRTUAL_IO, "Virtual open(%d, 0x%X, 0x%X, 0x%X)", emufd, ofs, arg1, arg2); break; + case 4: event(IOPSTATE, IOP_EVENT_VIRTUAL_IO, "Virtual close(%d)", emufd, 0, 0, 0); break; + case 5: event(IOPSTATE, IOP_EVENT_VIRTUAL_IO, "Virtual read(%d, 0x%X, 0x%X)", emufd, ofs, arg1, 0); break; + case 6: event(IOPSTATE, IOP_EVENT_VIRTUAL_IO, "Virtual write(%d, 0x%X, 0x%X)", emufd, ofs, arg1, 0); break; + case 7: event(IOPSTATE, IOP_EVENT_VIRTUAL_IO, "Virtual lseek(%d, 0x%X, 0x%X)", emufd, arg1, arg2, 0); break; + default: event(IOPSTATE, IOP_EVENT_VIRTUAL_IO, "Virtual unknown event(0x%X, 0x%X, 0x%X, 0x%X)", emufd, ofs, arg1, arg2); break; + } + + switch(type) { + case 1: // HEFILE_PSX_QUIT +//MessageBox(NULL,"qfset",NULL,MB_OK); + IOPSTATE->quitflag = 1; + r3000_break(R3000STATE); + r = 0; + break; + default: + r = psx_emucall( + IOPSTATE->psx_state, + PSXRAM_BYTE_NATIVE, + 0x200000, + type, emufd, ofs, arg1, arg2 + ); + // + // Special case: fatal error if return value is -5 + // + if(r == -5) { + IOPSTATE->fatalflag = 1; + r3000_break(R3000STATE); + } + break; + } + *((sint32*)((PSXRAM_BYTE_NATIVE)+((d+(4*( 0 )))&0x1FFFFC))) = r; +} + +//////////////////////////////////////////////////////////////////////////////// +/* +** Invalid-address catchers +*/ + +static uint32 EMU_CALL catcher_lw(void *state, uint32 a, uint32 mask) { + uint32 d = 0; + event(state, IOP_EVENT_REG_LOAD, "Catcher load (%08X,%08X)", a, mask, d, 0); + return d; +} + +static void EMU_CALL catcher_sw(void *state, uint32 a, uint32 d, uint32 mask) { + event(state, IOP_EVENT_REG_STORE, "Catcher store (%08X,%08X,%08X)", a, d, mask, 0); +} + +//////////////////////////////////////////////////////////////////////////////// +/* +** Advance hardware activity by the given cycle count +*/ +static void EMU_CALL iop_advance(void *state, uint32 elapse) { + sint32 core, i; //, r; + uint32 intr; + if(!elapse) return; + // + // Check timers + // + intr = ioptimer_advance(IOPTIMERSTATE, elapse); + if(intr) intr_signal(IOPSTATE, intr); + /* + ** Check DMA counters + */ + for(core = 0; core < 2; core++) { + for(i = 0; i < 7; i++) { + uint64 u = IOPSTATE->dma[core].chan[i].cycles_until_interrupt; + if(!u) continue; + if(u > elapse) { + u -= elapse; + } else { + u = 0; + dma_signal_completion(IOPSTATE, core * 7 + i); + } + IOPSTATE->dma[core].chan[i].cycles_until_interrupt = u; + } + } + /* + ** Check SPU IRQ + */ + if(elapse >= IOPSTATE->sound_cycles_until_interrupt) intr_signal(IOPSTATE, 0x200); + /* + ** Update pending sound cycles + */ + IOPSTATE->sound_cycles_pending += elapse; + /* + ** Update odometer + */ + IOPSTATE->odometer += ((uint64)elapse); +} + +//////////////////////////////////////////////////////////////////////////////// +/* +** Determine how many cycles until the next interrupt +** +** This is then used as an upper bound for how many cycles can be executed +** before checking for futher interrupts +*/ +static uint32 EMU_CALL cycles_until_next_interrupt(struct IOP_STATE *state, uint32 min) { + uint32 cyc; + uint32 core, i; //, r; + // + // Timers + // + cyc = ioptimer_cycles_until_interrupt(IOPTIMERSTATE); + if(cyc < min) min = cyc; + // + // DMA + // + for(core = 0; core < 2; core++) { + for(i = 0; i < 7; i++) { + uint64 u = state->dma[core].chan[i].cycles_until_interrupt; + if(!u) continue; + if(u < ((uint64)min)) { min = (uint32)u; } + } + } + // + // SPU + // + state->sound_cycles_until_interrupt = cyc = spu_cycles_until_interrupt(SPUSTATE, (min + 767) / 768); + if(cyc < min) min = cyc; + + if(min < 1) min = 1; + return min; +} + +//////////////////////////////////////////////////////////////////////////////// +/* +** Static memory map structures +*/ + +#define STATEOFS(thetype,thefield) ((void*)(&(((struct thetype*)0)->thefield))) + +// +// Note that the first two entries here MUST both be state offsets. +// +static const struct R3000_MEMORY_MAP iop_map_load[] = { + { 0x00000000, 0x007FFFFF, { 0x001FFFFF, R3000_MAP_TYPE_POINTER , STATEOFS(IOP_STATE, ram ) } }, + { 0x1F800000, 0x1F800FFF, { 0x000003FF, R3000_MAP_TYPE_POINTER , STATEOFS(IOP_STATE, scratch) } }, + { 0x1FC00000, 0x1FFFFFFF, { 0x00000000, R3000_MAP_TYPE_POINTER , NULL } }, + + { 0x1D000000, 0x1D00007F, { 0x1FFFFFFF, R3000_MAP_TYPE_CALLBACK, sif_lw } }, + { 0x1F801000, 0x1F80107F, { 0x1FFFFFFF, R3000_MAP_TYPE_CALLBACK, intr_lw } }, + { 0x1F801080, 0x1F8010FF, { 0x1FFFFFFF, R3000_MAP_TYPE_CALLBACK, dma0_lw } }, + { 0x1F801100, 0x1F80112F, { 0x1FFFFFFF, R3000_MAP_TYPE_CALLBACK, timer_lw } }, + { 0x1F801400, 0x1F80147F, { 0x1FFFFFFF, R3000_MAP_TYPE_CALLBACK, misc_lw } }, + { 0x1F801480, 0x1F8014AF, { 0x1FFFFFFF, R3000_MAP_TYPE_CALLBACK, timer_lw } }, + { 0x1F801500, 0x1F80157F, { 0x1FFFFFFF, R3000_MAP_TYPE_CALLBACK, dma1_lw } }, + { 0x1F801C00, 0x1F801DFF, { 0x1FFFFFFF, R3000_MAP_TYPE_CALLBACK, iop_spu_lw } }, + { 0x1F900000, 0x1F9007FF, { 0x1FFFFFFF, R3000_MAP_TYPE_CALLBACK, iop_spu2_lw } }, + + { 0x00000000, 0xFFFFFFFF, { 0x1FFFFFFF, R3000_MAP_TYPE_CALLBACK, catcher_lw } } +}; + +static const struct R3000_MEMORY_MAP iop_map_store[] = { + { 0x00000000, 0x007FFFFF, { 0x001FFFFF, R3000_MAP_TYPE_POINTER , STATEOFS(IOP_STATE, ram ) } }, + { 0x1F800000, 0x1F800FFF, { 0x000003FF, R3000_MAP_TYPE_POINTER , STATEOFS(IOP_STATE, scratch) } }, + + { 0x1D000000, 0x1D00007F, { 0x1FFFFFFF, R3000_MAP_TYPE_CALLBACK, sif_sw } }, + { 0x1F801000, 0x1F80107F, { 0x1FFFFFFF, R3000_MAP_TYPE_CALLBACK, intr_sw } }, + { 0x1F801080, 0x1F8010FF, { 0x1FFFFFFF, R3000_MAP_TYPE_CALLBACK, dma0_sw } }, + { 0x1F801100, 0x1F80112F, { 0x1FFFFFFF, R3000_MAP_TYPE_CALLBACK, timer_sw } }, +//{ 0x1F801400, 0x1F80147F, { 0x1FFFFFFF, R3000_MAP_TYPE_CALLBACK, intr1_sw } }, + { 0x1F801480, 0x1F8014AF, { 0x1FFFFFFF, R3000_MAP_TYPE_CALLBACK, timer_sw } }, + { 0x1F801500, 0x1F80157F, { 0x1FFFFFFF, R3000_MAP_TYPE_CALLBACK, dma1_sw } }, + { 0x1F801C00, 0x1F801DFF, { 0x1FFFFFFF, R3000_MAP_TYPE_CALLBACK, iop_spu_sw } }, + { 0x1F900000, 0x1F9007FF, { 0x1FFFFFFF, R3000_MAP_TYPE_CALLBACK, iop_spu2_sw } }, + + { 0x1FC17120, 0x1FC17123, { 0x1FFFFFFF, R3000_MAP_TYPE_CALLBACK, iop_emucall_sw } }, + + { 0x00000000, 0xFFFFFFFF, { 0x1FFFFFFF, R3000_MAP_TYPE_CALLBACK, catcher_sw } } +}; + +#define IOP_ARRAY_ENTRIES(x) (sizeof(x)/sizeof((x)[0])) + +const uint32 iop_map_load_entries = IOP_ARRAY_ENTRIES(iop_map_load ); +const uint32 iop_map_store_entries = IOP_ARRAY_ENTRIES(iop_map_store); + +//////////////////////////////////////////////////////////////////////////////// +// +// Memory map recomputation +// +// Necessary on structure location change or audit change +// + +static void perform_state_offset(struct R3000_MEMORY_MAP *map, struct IOP_STATE *state) { + // + // It's safe to typecast this "pointer" to a uint32 since, due to + // the STATEOFS hack, it'll never be bigger than 4GB + // + uint32 o = (uint32)(map->type.p); + map->type.p = ((uint8*)state) + o; +} + +// +// Recompute the memory maps. +// PERFORMS NO REGISTRATION with the actual R3000 state. +// +static void recompute_memory_maps(struct IOP_STATE *state) { + sint32 i; + struct R3000_MEMORY_MAP *mapload = MAPLOAD; + struct R3000_MEMORY_MAP *mapstore = MAPSTORE; + // + // First, just copy from the static tables + // + memcpy(mapload , iop_map_load , sizeof(iop_map_load )); + memcpy(mapstore, iop_map_store, sizeof(iop_map_store)); + // + // Now perform state offsets on first _two_ entries in each map + // + for(i = 0; i < 2; i++) { + perform_state_offset(mapload + i, state); + perform_state_offset(mapstore + i, state); + } + // + // And importantly, set the third load entry to point to the BIOS + // + mapload[2].type.mask = bios_get_imagesize() - 1; + mapload[2].type.n = R3000_MAP_TYPE_POINTER; + mapload[2].type.p = bios_get_image_native(); + + // + // Finally, if we're auditing, we'll want to change the _first_ entry in + // each map to an audit callback + // + if(state->audit_map) { + mapload [0].type.n = R3000_MAP_TYPE_CALLBACK; + mapload [0].type.p = audit_lw; + mapstore[0].type.n = R3000_MAP_TYPE_CALLBACK; + mapstore[0].type.p = audit_sw; + } +} + +//////////////////////////////////////////////////////////////////////////////// +// +// Executes the given number of cycles or the given number of samples +// (whichever is less) +// +// Sets *sound_samples to the number of samples actually generated, +// which may be ZERO or LESS than the number requested, but never more. +// +// Return value: +// >= 0 The number of cycles actually executed, which may be ZERO, MORE, +// or LESS than the number requested +// -1 Halted successfully (only applicable to PS2 environment) +// <= -2 Unrecoverable error +// +sint32 EMU_CALL iop_execute( + void *state, + void *psx_state, + sint32 cycles, + sint16 *sound_buf, + uint32 *sound_samples, + uint32 event_mask +) { + sint32 r = 0; + sint64 cyc_upperbound; + uint64 old_odometer; + uint64 target_odometer; + + location_check(IOPSTATE); + + IOPSTATE->psx_state = psx_state; + + old_odometer = IOPSTATE->odometer; + + IOPSTATE->event_mask = event_mask; + IOPSTATE->sound_buffer = sound_buf; + IOPSTATE->sound_buffer_samples_free = *sound_samples; + // + // If the quit flag was set, do nothing + // + if(IOPSTATE->quitflag) { +//MessageBox(NULL,"qfset_on_execute",NULL,MB_OK); + return -1; + } + // + // If the fatal flag was set, return -2 + // + if(IOPSTATE->fatalflag) { return -2; } + // + // If we have a bogus cycle count, return error + // + if(cycles < 0) { return -2; } + + /* + ** Begin by flushing any pending sound data into the newly available + ** buffer, if necessary + */ + flush_sound(IOPSTATE); + /* + ** Compute an upper bound for the number of cycles that can be generated + ** while still fitting in the buffer + */ + cyc_upperbound = + ((sint64)(IOPSTATE->cycles_per_sample)) * + ((sint64)(IOPSTATE->sound_buffer_samples_free)); + if(cyc_upperbound > (IOPSTATE->sound_cycles_pending)) { + cyc_upperbound -= IOPSTATE->sound_cycles_pending; + } else { + cyc_upperbound = 0; + } + /* + ** Bound cyc_upperbound by the number of cycles requested + */ + if(cycles > 0x70000000) cycles = 0x70000000; + if(cyc_upperbound > cycles) cyc_upperbound = cycles; + /* + ** Now cyc_upperbound is the number of cycles to execute. + ** Compute the target odometer + */ + target_odometer = (IOPSTATE->odometer)+((uint64)(cyc_upperbound)); + /* + ** Execution loop + */ + for(;;) { + uint32 diff, ci; + if(IOPSTATE->odometer >= target_odometer) break; + + diff = (uint32)((target_odometer) - (IOPSTATE->odometer)); + ci = cycles_until_next_interrupt(IOPSTATE, diff); + if(diff > ci) diff = ci; + r = r3000_execute(R3000STATE, diff); + // + // On a clean quit, break with -1 + // + if(IOPSTATE->quitflag) { + r = -1; + break; + } + // + // Create an error if the fatalflag got set + // + if(IOPSTATE->fatalflag) { + IOPSTATE->fatalflag = 0; + r = -5; + } + // + // On an unrecoverable CPU error, break with -2 + // + if(r < 0) { + r = -2; + break; + } + } + /* + ** End with a final sound flush + */ + flush_sound(IOPSTATE); + /* + ** Determine how many sound samples we generated + */ + (*sound_samples) -= (IOPSTATE->sound_buffer_samples_free); + // + // If there was an error, return it + // + if(r < 0) { +//char s[100]; +//sprintf(s,"blah blah %d", r); +//MessageBox(NULL,s,NULL,MB_OK); + return r; + } + // + // Otherwise return the number of cycles we executed + // + r = (sint32)(IOPSTATE->odometer - old_odometer); + return r; +} + +//////////////////////////////////////////////////////////////////////////////// +// +// For debugger use +// +// Location checks not needed +// +uint32 EMU_CALL iop_getword(void *state, uint32 a) { a &= 0x1FFFFFFC; + if(a < 0x00800000) { return (*((uint32*)(PSXRAM_BYTE_NATIVE+(a&0x1FFFFC)))); + } else if(a >=0x1FC00000) { return (*((uint32*)(bios_get_image_native()+(a&(bios_get_imagesize()-1))))); + } else { return 0; + } +} + +void EMU_CALL iop_setword(void *state, uint32 a, uint32 d) { a &= 0x1FFFFFFC; + if(a < 0x00800000) { + (*((uint32*)(PSXRAM_BYTE_NATIVE+(a&0x1FFFFC)))) = d; + } +} + +//////////////////////////////////////////////////////////////////////////////// +// +// Timing may be nonuniform +// +// Location checks not needed +// +uint64 EMU_CALL iop_get_odometer(void *state) { + return IOPSTATE->odometer; +} + +//////////////////////////////////////////////////////////////////////////////// +// +// Compatibility level +// +// Location checks not needed +// +void EMU_CALL iop_set_compat(void *state, uint8 compat) { + IOPSTATE->compat_level = compat; +} + +//////////////////////////////////////////////////////////////////////////////// +// +// Useful for playing with the tempo. +// 768 is normal. +// Higher is faster; lower is slower. +// +// Location checks not needed +// +void EMU_CALL iop_set_cycles_per_sample(void *state, uint32 cycles_per_sample) { + if(!cycles_per_sample) cycles_per_sample = 1; + IOPSTATE->cycles_per_sample = cycles_per_sample; +} + +//////////////////////////////////////////////////////////////////////////////// +// +// Upload a section to RAM +// +// Location checks not needed +// +void EMU_CALL iop_upload_to_ram(void *state, uint32 address, const void *src, uint32 len) { + while(len) { + uint32 advance; + address &= 0x1FFFFF; + advance = 0x200000 - address; + if(advance > len) { advance = len; } +#ifdef EMU_BIG_ENDIAN + { uint32 i; + for(i = 0; i < advance; i++) { + (PSXRAM_BYTE_NATIVE)[(address+i)^(EMU_ENDIAN_XOR(3))] = ((char*)src)[i]; + } + } +#else + memcpy((PSXRAM_BYTE_NATIVE) + address, src, advance); +#endif + src = (((const char*)src) + advance); + len -= advance; + address += advance; + } + +} + +//////////////////////////////////////////////////////////////////////////////// diff --git a/Frameworks/HighlyExperimental/HighlyExperimental/Core/iop.h b/Frameworks/HighlyExperimental/HighlyExperimental/Core/iop.h new file mode 100644 index 000000000..6b15508a5 --- /dev/null +++ b/Frameworks/HighlyExperimental/HighlyExperimental/Core/iop.h @@ -0,0 +1,127 @@ +///////////////////////////////////////////////////////////////////////////// +// +// iop - PS2 IOP emulation; can also do PS1 via compatibility mode +// +///////////////////////////////////////////////////////////////////////////// + +#ifndef __PSX_IOP_H__ +#define __PSX_IOP_H__ + +#include "emuconfig.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* +** Types of events. +** +** Each event has a 64-bit cycle time, a format string and up to 4 dword args +*/ +#define IOP_EVENT_REG_STORE (0) +#define IOP_EVENT_REG_LOAD (1) +#define IOP_EVENT_INTR_SIGNAL (2) +#define IOP_EVENT_DMA_TRANSFER (3) +#define IOP_EVENT_VIRTUAL_IO (4) +#define IOP_EVENT_MAX (5) + +/* +** Types of audit markers. +*/ +#define IOP_AUDIT_UNUSED (0) +#define IOP_AUDIT_READ (1) +#define IOP_AUDIT_WRITE (2) + +/* +** Static init +*/ +sint32 EMU_CALL iop_init(void); + +/* +** State init +** version = 1 for PS1, 2 for PS2 +*/ +uint32 EMU_CALL iop_get_state_size(int version); +void EMU_CALL iop_clear_state(void *state, int version); + +/* +** Obtain substates +*/ +void* EMU_CALL iop_get_r3000_state(void *state); +void* EMU_CALL iop_get_spu_state(void *state); + +/* +** For debugger use +** These functions have no side effects +*/ +uint32 EMU_CALL iop_getword(void *state, uint32 a); +void EMU_CALL iop_setword(void *state, uint32 a, uint32 d); + +/* +** Uploads a section of data; only affects RAM +*/ +void EMU_CALL iop_upload_to_ram(void *state, uint32 address, const void *src, uint32 len); + +/* +** IOP timing may be nonuniform +*/ +uint64 EMU_CALL iop_get_odometer(void *state); + +/* +** Event handling +*/ +void EMU_CALL iop_clear_events(void *state); +uint32 EMU_CALL iop_get_event_count(void *state); +void EMU_CALL iop_get_event(void *state, uint64 *time, uint32 *type, char **fmt, uint32 *arg); +void EMU_CALL iop_dismiss_event(void *state); +void EMU_CALL iop_set_event_mask(void *state, uint64 mask); + +/* +** Register a map for auditing purposes +** (must contain 1 byte for every RAM byte) +** +** Pass NULL to disable auditing. +*/ +void EMU_CALL iop_register_map_for_auditing(void *state, uint8 *map); +uint32 EMU_CALL iop_get_bytes_used_in_audit(void *state); + +// +// Set the screen refresh rate in Hz (50 or 60 for PAL or NTSC) +// Only 50 or 60 are valid; other values will be ignored +// +void EMU_CALL iop_set_refresh(void *state, uint32 refresh); + +// +// DO NOT CALL THIS DIRECTLY. +// Call psx_execute instead. +// +sint32 EMU_CALL iop_execute( + void *state, + void *psx_state, + sint32 cycles, + sint16 *sound_buf, + uint32 *sound_samples, + uint32 event_mask +); + +/* +** Compatibility level +*/ +#define IOP_COMPAT_DEFAULT (0) +#define IOP_COMPAT_HARSH (1) +#define IOP_COMPAT_FRIENDLY (2) + +void EMU_CALL iop_set_compat(void *state, uint8 compat); + +/* +** Useful for playing with the tempo. +** 768 is normal. +** Higher is faster; lower is slower. +*/ +void EMU_CALL iop_set_cycles_per_sample(void *state, uint32 cycles_per_sample); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Frameworks/HighlyExperimental/HighlyExperimental/Core/ioptimer.c b/Frameworks/HighlyExperimental/HighlyExperimental/Core/ioptimer.c new file mode 100644 index 000000000..f71440f14 --- /dev/null +++ b/Frameworks/HighlyExperimental/HighlyExperimental/Core/ioptimer.c @@ -0,0 +1,372 @@ +///////////////////////////////////////////////////////////////////////////// +// +// ioptimer - IOP timers +// +///////////////////////////////////////////////////////////////////////////// + +#ifndef EMU_COMPILE +#error "Hi I forgot to set EMU_COMPILE" +#endif + +#include "ioptimer.h" + +///////////////////////////////////////////////////////////////////////////// +// +// Static information +// +sint32 EMU_CALL ioptimer_init(void) { return 0; } + +#define COUNTERS (6) + +#define IOP_INT_VBLANK (1<<0) +#define IOP_INT_RTC0 (1<<4) +#define IOP_INT_RTC1 (1<<5) +#define IOP_INT_RTC2 (1<<6) +#define IOP_INT_RTC3 (1<<14) +#define IOP_INT_RTC4 (1<<15) +#define IOP_INT_RTC5 (1<<16) + +static const uint32 intrflag[COUNTERS] = { + IOP_INT_RTC0, IOP_INT_RTC1, IOP_INT_RTC2, + IOP_INT_RTC3, IOP_INT_RTC4, IOP_INT_RTC5 +}; + +///////////////////////////////////////////////////////////////////////////// +// +// State information +// +#define IOPTIMERSTATE ((struct IOPTIMER_STATE*)(state)) + +struct IOPTIMER_COUNTER { + // + // quick values used in advance loop, etc. + // + uint64 counter; + uint32 delta; + uint64 target; + uint8 target_is_overflow; + // + // other values + // + uint16 mode; + uint16 status; + uint64 compare; +}; + +struct IOPTIMER_STATE { + struct IOPTIMER_COUNTER counter[COUNTERS]; + uint8 gate; + uint64 field_counter; + uint64 field_vblank; + uint64 field_total; + uint32 hz_sysclock; + uint32 hz_hline; + uint32 hz_pixel; +}; + +uint32 EMU_CALL ioptimer_get_state_size(void) { + return sizeof(struct IOPTIMER_STATE); +} + +void EMU_CALL ioptimer_clear_state(void *state) { + memset(IOPTIMERSTATE, 0, sizeof(struct IOPTIMER_STATE)); +} + +///////////////////////////////////////////////////////////////////////////// + +void EMU_CALL ioptimer_set_rates(void *state, uint32 sysclock, uint32 dots, uint32 lines, uint32 lines_visible, uint32 refresh_rate) { + IOPTIMERSTATE->hz_sysclock = sysclock; + IOPTIMERSTATE->hz_hline = lines * refresh_rate; + IOPTIMERSTATE->hz_pixel = IOPTIMERSTATE->hz_hline * dots; + + IOPTIMERSTATE->field_counter = 0; + IOPTIMERSTATE->field_vblank = ((uint64)(lines_visible)) * ((uint64)(sysclock)); + IOPTIMERSTATE->field_total = ((uint64)(lines )) * ((uint64)(sysclock)); +} + +///////////////////////////////////////////////////////////////////////////// + +static EMU_INLINE uint32 EMU_CALL cycles_until_gate(struct IOPTIMER_STATE *state) { + uint64 diff; + if(!(IOPTIMERSTATE->hz_hline)) return 0xFFFFFFFF; + if(state->field_counter < state->field_vblank) { + diff = state->field_vblank - state->field_counter; + } else { + diff = state->field_total - state->field_counter; + } + diff += (IOPTIMERSTATE->hz_hline-1); + diff /= ((uint64)(IOPTIMERSTATE->hz_hline)); + if(diff > 0xFFFFFFFF) diff = 0xFFFFFFFF; + if(diff < 1) diff = 1; + return (uint32)diff; +} + +///////////////////////////////////////////////////////////////////////////// + +uint32 EMU_CALL ioptimer_cycles_until_interrupt(void *state) { + uint32 min = cycles_until_gate(IOPTIMERSTATE); + uint32 c; + // + // counters + // + for(c = 0; c < COUNTERS; c++) { + uint64 diff; + if(!(IOPTIMERSTATE->counter[c].delta)) continue; + if(IOPTIMERSTATE->counter[c].counter >= IOPTIMERSTATE->counter[c].target) { + diff = 0; + } else { + diff = IOPTIMERSTATE->counter[c].target - IOPTIMERSTATE->counter[c].counter; + diff += (IOPTIMERSTATE->counter[c].delta-1); + diff /= ((uint64)(IOPTIMERSTATE->counter[c].delta)); + } + if(diff < ((uint64)(min))) min = (uint32)diff; + } + if(min < 1) min = 1; + return min; +} + +///////////////////////////////////////////////////////////////////////////// + +static EMU_INLINE uint32 EMU_CALL counters_advance(struct IOPTIMER_STATE *state, uint32 cycles) { + uint32 intr = 0; + uint32 c; + for(c = 0; c < COUNTERS; c++) { + struct IOPTIMER_COUNTER *ctr = IOPTIMERSTATE->counter + c;; + if(!ctr->delta) continue; + ctr->counter += ((uint64)(cycles)) * ((uint64)(ctr->delta)); + // + // timer loop handling + // + for(;;) { + // + // if we're below the given target, then good - quit. + // + if(ctr->counter < ctr->target) break; + // + // otherwise, we have a transition to make. + // + if(ctr->target_is_overflow) { + ctr->status |= 0x1000; + if(ctr->mode & 0x20) intr |= intrflag[c]; + // counter always loops on overflow (duh!) + ctr->counter -= ctr->target; + // counter now becomes the compare target + ctr->target = ((uint64)(state->hz_sysclock)) * ((uint64)(ctr->compare)); + ctr->target_is_overflow = 0; + } else { + ctr->status |= 0x800; + if(ctr->mode & 0x10) intr |= intrflag[c]; + // counter only loops on target if the appropriate bit is set + if(ctr->mode & 8) { + // no change to target, just loop counter + ctr->counter -= ctr->target; + // no target loop - proceed to overflow + } else { + if(c < 3) { + ctr->target = ((uint64)(state->hz_sysclock)) << 16; + } else { + ctr->target = ((uint64)(state->hz_sysclock)) << 32; + } + ctr->target_is_overflow = 1; + } + } + } + } + return intr; +} + +///////////////////////////////////////////////////////////////////////////// + +static void EMU_CALL counter_start(struct IOPTIMER_STATE *state, uint32 c) { + struct IOPTIMER_COUNTER *ctr = state->counter + c; + uint32 delta = state->hz_sysclock; + switch(c) { + case 0: if(ctr->mode & 0x100) { delta = state->hz_pixel; } break; + case 1: if(ctr->mode & 0x100) { delta = state->hz_hline; } break; + case 2: if(ctr->mode & 0x200) { delta /= 8; } break; + case 3: if(ctr->mode & 0x100) { delta = state->hz_hline; } break; + case 4: case 5: + switch((ctr->mode >> 13) & 3) { + case 0: delta /= 1; break; + case 1: delta /= 8; break; + case 2: delta /= 16; break; + case 3: delta /= 256; break; + } + break; + } + ctr->counter = 0; + ctr->delta = delta; + ctr->target = ((uint64)(ctr->compare)) * ((uint64)(state->hz_sysclock)); + ctr->target_is_overflow = 0; +} + +///////////////////////////////////////////////////////////////////////////// + +static void EMU_CALL counter_stop(struct IOPTIMER_STATE *state, uint32 c) { + state->counter[c].delta = 0; +} + +///////////////////////////////////////////////////////////////////////////// + +static void EMU_CALL gate_transition(struct IOPTIMER_STATE *state) { + uint32 c; + for(c = 0; c < COUNTERS; c++) { + // must be both enabled and gate-enabled + if((state->counter[c].mode & 0x41) != 0x41) continue; + switch(state->counter[c].mode & 0x6) { + case 0x0: // TM_GATE_ON_Count + if(state->gate) { counter_start(state, c); } + else { counter_stop(state, c); } + break; + case 0x2: // TM_GATE_ON_ClearStart + if(state->gate) { counter_start(state, c); } + break; + case 0x4: // TM_GATE_ON_Clear_OFF_Start + if(state->gate) { counter_stop(state, c); } + else { counter_start(state, c); } + break; + case 0x6: // TM_GATE_ON_Start + if(state->gate) { + // one-time start: disable gate bit + state->counter[c].mode &= ~1; + counter_start(state, c); + } + break; + } + } +} + +///////////////////////////////////////////////////////////////////////////// + +static EMU_INLINE uint32 EMU_CALL gate_advance(struct IOPTIMER_STATE *state, uint32 cycles) { + uint32 intr = 0; + state->field_counter += ((uint64)(cycles)) * ((uint64)(state->hz_hline)); + // + // gate overflow loop + // + for(;;) { + // + // if we're below the given target, then good - quit. + // + if(state->gate) { + if(state->field_counter < state->field_vblank) break; + // + // gate transition 1->0 + // + state->gate = 0; + gate_transition(state); + intr |= IOP_INT_VBLANK; + } else { + if(state->field_counter < state->field_total) break; + // + // gate transition 0->1 + // + state->gate = 1; + gate_transition(state); + state->field_counter -= state->field_total; + } + } + return intr; +} + +///////////////////////////////////////////////////////////////////////////// + +uint32 EMU_CALL ioptimer_advance(void *state, uint32 cycles) { + uint32 intr = 0; + uint32 cycles_left = cycles; + while(cycles_left) { + uint32 g = cycles_until_gate(IOPTIMERSTATE); + if(g > cycles_left) g = cycles_left; + intr |= counters_advance(IOPTIMERSTATE, g); + intr |= gate_advance(IOPTIMERSTATE, g); + cycles_left -= g; + } + return intr; +} + +///////////////////////////////////////////////////////////////////////////// + +static uint32 EMU_CALL which_counter(uint32 a) { + switch(a & 0xFFF0) { + case 0x1100: return 0; + case 0x1110: return 1; + case 0x1120: return 2; + case 0x1480: return 3; + case 0x1490: return 4; + case 0x14A0: return 5; + } + return 0xFFFFFFFF; +} + +///////////////////////////////////////////////////////////////////////////// + +uint32 EMU_CALL ioptimer_lw(void *state, uint32 a, uint32 mask) { + uint32 d = 0; + uint32 c = which_counter(a); + struct IOPTIMER_COUNTER *ctr; + if(c >= COUNTERS) return 0; + ctr = IOPTIMERSTATE->counter + c; + switch(a & 0xC) { + case 0x0: + if(ctr->delta) { d = (uint32)((ctr->counter) / ((uint64)(ctr->delta))); } + break; + case 0x4: + d = ctr->status; + ctr->status = 0; + break; + case 0x8: + d = (uint32)(ctr->compare); + break; + } + if(c < 3) d &= 0xFFFF; + return d & mask; +} + +///////////////////////////////////////////////////////////////////////////// + +void EMU_CALL ioptimer_sw(void *state, uint32 a, uint32 d, uint32 mask) { + uint32 c = which_counter(a); + struct IOPTIMER_COUNTER *ctr; + if(c >= COUNTERS) return; + ctr = IOPTIMERSTATE->counter + c; + d &= mask; + if(c < 3) d &= 0xFFFF; + switch(a & 0xC) { + case 0x4: + ctr->delta = 0; + ctr->mode = d; + if(d & 0x40) { + if((d & 7) != 7) { + counter_start(state, c); + } + } + break; + case 0x8: + ctr->compare = d; + if(!ctr->compare) { + if(c < 3) { + ctr->compare = 0x10000; + } else { + ctr->compare = 0x100000000; + } + } + // + // if this timer was running, recompute the target + // + if(ctr->delta) { + ctr->target = ctr->compare * ((uint64)(IOPTIMERSTATE->hz_sysclock)); + ctr->target_is_overflow = 0; + if(ctr->counter >= ctr->target) { + if(c < 3) { + ctr->target = ((uint64)(IOPTIMERSTATE->hz_sysclock)) << 16; + } else { + ctr->target = ((uint64)(IOPTIMERSTATE->hz_sysclock)) << 32; + } + ctr->target_is_overflow = 1; + } + } + break; + } +} + +///////////////////////////////////////////////////////////////////////////// diff --git a/Frameworks/HighlyExperimental/HighlyExperimental/Core/ioptimer.h b/Frameworks/HighlyExperimental/HighlyExperimental/Core/ioptimer.h new file mode 100644 index 000000000..c2ace0911 --- /dev/null +++ b/Frameworks/HighlyExperimental/HighlyExperimental/Core/ioptimer.h @@ -0,0 +1,32 @@ +///////////////////////////////////////////////////////////////////////////// +// +// ioptimer - IOP timers +// +///////////////////////////////////////////////////////////////////////////// + +#ifndef __PSX_IOPTIMER_H__ +#define __PSX_IOPTIMER_H__ + +#include "emuconfig.h" + +#ifdef __cplusplus +extern "C" { +#endif + +sint32 EMU_CALL ioptimer_init(void); +uint32 EMU_CALL ioptimer_get_state_size(void); +void EMU_CALL ioptimer_clear_state(void *state); + +void EMU_CALL ioptimer_set_rates(void *state, uint32 sysclock, uint32 dots, uint32 lines, uint32 lines_visible, uint32 refresh_rate); + +uint32 EMU_CALL ioptimer_cycles_until_interrupt(void *state); +uint32 EMU_CALL ioptimer_advance(void *state, uint32 cycles); + +uint32 EMU_CALL ioptimer_lw(void *state, uint32 a, uint32 mask); +void EMU_CALL ioptimer_sw(void *state, uint32 a, uint32 d, uint32 mask); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Frameworks/HighlyExperimental/HighlyExperimental/Core/mkhebios.c b/Frameworks/HighlyExperimental/HighlyExperimental/Core/mkhebios.c new file mode 100644 index 000000000..b97c5d144 --- /dev/null +++ b/Frameworks/HighlyExperimental/HighlyExperimental/Core/mkhebios.c @@ -0,0 +1,907 @@ +#include "mkhebios.h" + +/***************************************************************************/ + +#include +#include +#include +#include + +#ifdef _MSC_VER +#define strcasecmp _stricmp +#endif + +#if 0 +#define log_error do { fprintf(stderr, "he: error at line %u\n", __LINE__); } while(0) +#else +#define log_error +#endif + +/***************************************************************************/ + +static uint16 get16lsb(const uint8 *p) { + return (((uint16)(p[0])) << 0) | + (((uint16)(p[1])) << 8); +} + +static uint32 get32lsb(const uint8 *p) { + return (((uint32)(p[0])) << 0) | + (((uint32)(p[1])) << 8) | + (((uint32)(p[2])) << 16) | + (((uint32)(p[3])) << 24); +} + +static void put16lsb(uint8 *p, uint16 n) { + p[0] = n >> 0; + p[1] = n >> 8; +} + +static void put32lsb(uint8 *p, uint32 n) { + p[0] = n >> 0; + p[1] = n >> 8; + p[2] = n >> 16; + p[3] = n >> 24; +} + +/***************************************************************************/ + +struct MODULE { + uint8 name[11]; + uint16 code; + void *ext_data; + uint32 size; + uint32 start; +}; + +static void init_mod_fields( + struct MODULE *mod, + const char *name, + uint16 code, + uint32 start, + uint32 size +) { + memset(mod, 0, sizeof(struct MODULE)); + strncpy(mod->name, name, 10); + mod->code = code; + mod->start = start; + mod->size = size; +} + +/***************************************************************************/ + +static int read_script_file(const char *script, int (*linehandler)(void *, int, const char*), void * ctx) { + int r = 0; + char s[1000]; + int l = 0; + int linenum = 1; + for(;;) { + int c = *script++; + if(c == 10 || c == 0) { + while(l && s[l-1] == 32) l--; + s[l] = 0; + if(s[0]) { + if(linehandler(ctx, linenum, s)) { + r = 1; + break; + } + } + l = 0; + if(c == 0) { r = 0; break; } + linenum++; + continue; + } + if(c < 32) c = 32; + if(l || c > 32) { + s[l] = c; + if(l < (sizeof(s) - 1)) l++; + } + } + return r; +} + +/***************************************************************************/ +/* +** Find the ROMDIR offset within the ROM. +** Returns 0 if not found (it should never be 0 in real circumstances). +*/ +static uint32 find_romdir(uint8 *bios, uint32 bios_size) { + uint32 u; + bios_size &= ~0xF; + for(u = 0; u < bios_size; u += 0x10) { + if(!memcmp(bios + u, "RESET\0\0\0\0\0", 10)) return u; + } + return 0; +} + +/***************************************************************************/ +/* +** Returns true on success +*/ +static int find_romdir_entry( + uint8 *bios, uint32 bios_size, + uint32 romdir_start, + const uint8 *name, + uint16 *out_code, + uint32 *out_start, + uint32 *out_size +) { + uint32 ofs = 0; + bios_size &= ~0xF; + romdir_start &= ~0xF; + for(; romdir_start < bios_size; romdir_start += 0x10) { + uint8 n[11]; + uint16 c; + uint32 s; + // exhausted romdir? + if(!bios[romdir_start]) return 0; + memcpy(n, bios + romdir_start, 10); + n[10] = 0; + c = get16lsb(bios + romdir_start + 0xA); + s = get32lsb(bios + romdir_start + 0xC); + if(!strcmp(n, name)) { + if(out_code ) *out_code = c; + if(out_start) *out_start = ofs; + if(out_size ) *out_size = s; + log_error; + return 1; + } + // round up to the nearest paragraph and advance offset + // (confirmed the actual BIOS does this too) + s += 0xF; s &= ~0xF; + ofs += s; + } + return 0; +} + +/***************************************************************************/ + +struct MKHEBIOS +{ + const char * iopbtconf_script; + + struct MODULE *master_module_free_list; + int master_module_free_n; + struct MODULE *master_module_pin_list; + int master_module_pin_n; + + char *master_iopbtconf; + + uint8 *master_bios; + int master_bios_size; + + struct MODULE **rom_usage_map; + int usage_entries; + + uint8 *romdir; + uint32 romdir_size; + uint16 romdir_code; + + uint32 attempt_romdir_line; + uint32 attempt_romdir_ofs; +}; + +static struct MODULE *master_find_module(struct MKHEBIOS *state, const char *name) { + int n; + for(n = 0; n < state->master_module_pin_n; n++) { + if(!strcasecmp(state->master_module_pin_list[n].name, name)) return state->master_module_pin_list + n; + } + for(n = 0; n < state->master_module_free_n; n++) { + if(!strcasecmp(state->master_module_free_list[n].name, name)) return state->master_module_free_list + n; + } + return NULL; +} + +static struct MKHEBIOS * master_init(void) { + struct MKHEBIOS * state = ( struct MKHEBIOS * ) malloc( sizeof( struct MKHEBIOS ) ); + if ( !state ) { log_error; return NULL; } + memset( state, 0, sizeof( struct MKHEBIOS ) ); + return state; +} + +static void master_iopbtconf_append(struct MKHEBIOS *state, const char *line) { + char newline[1000]; + int l; + char *p; + + strncpy(newline, line, sizeof(newline)); + newline[sizeof(newline)-1]=0; + p = strrchr(newline,','); + if(p) *p = 0; + + if(!state->master_iopbtconf) { + state->master_iopbtconf = malloc(1); + if(!state->master_iopbtconf) return; + *state->master_iopbtconf = 0; + } + l = strlen(state->master_iopbtconf) + strlen(newline) + 1; + state->master_iopbtconf = realloc(state->master_iopbtconf, l + 1); + if(!state->master_iopbtconf) return; + p = state->master_iopbtconf; p += strlen(p); + strcpy(p, newline); p += strlen(p); + p[0] = 10; + p[1] = 0; +} + +static void master_module_free_add(struct MKHEBIOS *state, struct MODULE *mod) { + state->master_module_free_list = realloc( + state->master_module_free_list, + sizeof(struct MODULE) * (state->master_module_free_n + 1) + ); + if(!state->master_module_free_list) return; + memcpy(state->master_module_free_list + state->master_module_free_n, mod, sizeof(struct MODULE)); + state->master_module_free_n++; +} + +static void master_module_pin_add(struct MKHEBIOS *state, struct MODULE *mod) { + state->master_module_pin_list = realloc( + state->master_module_pin_list, + sizeof(struct MODULE) * (state->master_module_pin_n + 1) + ); + if(!state->master_module_pin_list) return; + memcpy(state->master_module_pin_list + state->master_module_pin_n, mod, sizeof(struct MODULE)); + state->master_module_pin_n++; +} + +/***************************************************************************/ +/* +** Returns nonzero on error +*/ +static int master_bios_modinfo( + struct MKHEBIOS *state, + const char *name, + struct MODULE *out_mod +) { + uint32 rbase; + int success; + uint16 code; + uint32 start; + uint32 size; + + rbase = find_romdir(state->master_bios, state->master_bios_size); + if(!rbase) { log_error; return 1; } + success = find_romdir_entry( + state->master_bios, state->master_bios_size, + rbase, + name, + &code, + &start, + &size + ); + if(!success) { log_error; return 1; } + if(out_mod) init_mod_fields(out_mod, name, code, start, size); + return 0; +} + +/***************************************************************************/ +/* +** ROM usage map (granularity 16 bytes) +*/ +static void rom_usage_clear(struct MKHEBIOS * state) { + state->usage_entries = state->master_bios_size / 0x10; + state->rom_usage_map = realloc( state->rom_usage_map, sizeof(struct MODULE *) * state->usage_entries ); + memset(state->rom_usage_map, 0, sizeof(struct MODULE *) * state->usage_entries); +} + +static void rom_usage_set(struct MKHEBIOS * state, uint32 ofs, uint32 size, struct MODULE *m) { + uint32 slop; +//printf("rom_usage_set(%X,%X,%X)\n",ofs,size,(uint32)m); + slop = ofs & 0xF; + size += slop; + ofs -= slop; + slop = (0x10 - (size & 0xF)) & 0xF; + size += slop; + ofs /= 0x10; + size /= 0x10; + if(ofs >= state->usage_entries) return; + if(size > state->usage_entries) size = state->usage_entries; + if((ofs + size) > state->usage_entries) size = state->usage_entries - ofs; + while(size--) state->rom_usage_map[ofs++] = m; +} + +static uint32 rom_usage_get_free_space(struct MKHEBIOS * state, uint32 ofs) { + uint32 i; + ofs /= 0x10; + i = ofs; + for(; i < state->usage_entries; i++) if(state->rom_usage_map[i]) break; + i -= ofs; + i *= 0x10; + return i; +} + +static struct MODULE *rom_usage_get_module(struct MKHEBIOS * state, uint32 ofs) { + ofs /= 0x10; + if(ofs >= state->usage_entries) return NULL; + return state->rom_usage_map[ofs]; +} + +static void rom_usage_set_all_pinned(struct MKHEBIOS * state) { + int n; + if(!state->master_module_pin_list) return; + for(n = 0; n < state->master_module_pin_n; n++) { + rom_usage_set( + state, + state->master_module_pin_list[n].start, + state->master_module_pin_list[n].size, + state->master_module_pin_list + n + ); + } +} + +/***************************************************************************/ + +static int any_unhandled_pinned_modules(struct MKHEBIOS * state) { + int n; + for(n = 0; n < state->master_module_pin_n; n++) { + if(state->master_module_pin_list[n].start >= state->attempt_romdir_ofs) { log_error; return 1; } + } + return 0; +} + +static uint32 closest_unhandled_pinned_module(struct MKHEBIOS * state) { + uint32 lowest = 0xFFFFFFFF; + int n; + for(n = 0; n < state->master_module_pin_n; n++) { + uint32 s = state->master_module_pin_list[n].start; + if(s >= state->attempt_romdir_ofs) { + if(s < lowest) lowest = s; + } + } + return lowest; +} + +static uint32 space_in_romdir(struct MKHEBIOS * state) { return state->romdir_size - state->attempt_romdir_line; } + +static int line_from_arbitrary(struct MKHEBIOS * state, const char *name, uint16 code, uint32 size) { + uint8 *p = state->romdir + state->attempt_romdir_line; + if(space_in_romdir(state) < 0x10) { log_error; return 1; } + memset (p, 0, 0x10); + strcpy (p, name); + put16lsb(p + 0xA, code); + put32lsb(p + 0xC, size); + state->attempt_romdir_line += 0x10; +//printf("new line name '%s' code %X size %X\n",name,code,size); + return 0; +} + +static int line_from_module(struct MKHEBIOS * state, struct MODULE *m) { return line_from_arbitrary(state, m->name, m->code, m->size); } +static int line_from_blank(struct MKHEBIOS * state, uint32 size) { return line_from_arbitrary(state, "-", 0, size); } +static int line_from_eod(struct MKHEBIOS * state) { return line_from_arbitrary(state, "", 0, 0); } + +static int handle_pinned(struct MKHEBIOS * state) { +//printf("handle_pinned\n"); + for(;;) { + struct MODULE *m = rom_usage_get_module(state, state->attempt_romdir_ofs); + if(!m) break; + if(line_from_module(state, m)) { log_error; return 1; } + state->attempt_romdir_ofs += (m->size + 0xF) & (~0xF); + } + return 0; +} + +static int seek_to_free(struct MKHEBIOS * state, uint32 s) { +//printf("seek_to_free(%X)\n",s); + for(;;) { + uint32 cf; + if(handle_pinned(state)) { log_error; return 1; } + cf = rom_usage_get_free_space(state, state->attempt_romdir_ofs); +//printf(" cf=%X\n",cf); + if(!cf) { log_error; return 1; } + if(cf >= s) return 0; + if(line_from_blank(state, cf)) { log_error; return 1; } + state->attempt_romdir_ofs += cf; + } + return 0; +} + +/* +** Returns nonzero on error +*/ +static int attempt_rebuild_romdir(struct MKHEBIOS * state) { + int n; + + if(!state->romdir) { log_error; return 1; } + state->romdir_size &= ~0xF; + if(!state->romdir_size) { log_error; return 1; } + + memset(state->romdir, 0, state->romdir_size); + +//printf("attempt rebuild romdir_size=0x%X\n",romdir_size); + + state->attempt_romdir_line = 0; + state->attempt_romdir_ofs = 0; + + rom_usage_clear(state); + rom_usage_set_all_pinned(state); + + if(seek_to_free(state, state->romdir_size)) { log_error; return 1; } +//printf("a l=%X ofs=%X\n",attempt_romdir_line,attempt_romdir_ofs); + + if(line_from_arbitrary(state, "ROMDIR", state->romdir_code, state->romdir_size)) { log_error; return 1; } + state->attempt_romdir_ofs += state->romdir_size; +//printf("b l=%X ofs=%X\n",attempt_romdir_line,attempt_romdir_ofs); + + for(n = 0; n < state->master_module_free_n; n++) { + uint32 size; +//printf("n%02d a l=%X ofs=%X\n",n,attempt_romdir_line,attempt_romdir_ofs); + size = state->master_module_free_list[n].size; +//printf("n%02d b l=%X ofs=%X\n",n,attempt_romdir_line,attempt_romdir_ofs); + if(seek_to_free(state, size)) { log_error; return 1; } +//printf("n%02d c l=%X ofs=%X\n",n,attempt_romdir_line,attempt_romdir_ofs); + if(line_from_module(state, state->master_module_free_list + n)) { log_error; return 1; } +//printf("n%02d d l=%X ofs=%X\n",n,attempt_romdir_line,attempt_romdir_ofs); + state->attempt_romdir_ofs += (size + 0xF) & (~0xF); +//printf("n%02d e l=%X ofs=%X\n",n,attempt_romdir_line,attempt_romdir_ofs); + } +//printf("z l=%X ofs=%X\n",attempt_romdir_line,attempt_romdir_ofs); + + // handle any higher-up pinned modules if necessary + for(;;) { + uint32 c, blank; + handle_pinned(state); + if(!(any_unhandled_pinned_modules(state))) break; + c = closest_unhandled_pinned_module(state); + blank = c - state->attempt_romdir_ofs; + if(line_from_blank(state, blank)) { log_error; return 1; } + state->attempt_romdir_ofs += blank; + } + + if(line_from_eod(state)) { log_error; return 1; } + + return 0; +} + +/***************************************************************************/ + +static int find_romdir_code(struct MKHEBIOS * state) { + struct MODULE mod; + if(master_bios_modinfo(state, "ROMDIR", &mod)) { + { log_error; return 1; } + } + state->romdir_code = mod.code; + return 0; +} + +#include "mkhebios_overlays.h" + +/***************************************************************************/ +/* +** Returns nonzero on error +** modname can also be of the form "modname,hexcode" +*/ +static int irx(struct MKHEBIOS * state, const char *modname) { + int overlay_index; + uint32 code = 0xFFFFFFFF; + char n[1000]; + int i; + char *t; + struct MODULE mod; + i = 0; + memset(&mod, 0, sizeof(struct MODULE)); + for(;;) { + char c = *modname++; + if(!c) break; + if(isspace(c)) continue; + n[i] = toupper(c); + if(i < (sizeof(n) - 1)) i++; + } + n[i] = 0; + t = strchr(n, ','); + if(t) { + *t = 0; + t++; + code = strtoul(t, NULL, 16); + code &= 0xFFFF; + } + // force name to get chopped to 10 bytes + n[10] = 0; + + goto try_file; + +try_file: + memset(&mod, 0, sizeof(struct MODULE)); + { + for (overlay_index = 0;;overlay_index++) { + if (modules_list[overlay_index].name == NULL) goto file_fail; + if (!strcasecmp(modules_list[overlay_index].name, n)) break; + } + } + strcpy(mod.name, n); + mod.size = modules_list[overlay_index].size; + mod.ext_data = malloc(mod.size); + if(!mod.ext_data) goto giveup; + memcpy(mod.ext_data, modules_list[overlay_index].data, mod.size); + goto file_ok; + +try_bios: + if(master_bios_modinfo(state, n, &mod)) goto bios_fail; + mod.ext_data = malloc(mod.size); + if(!mod.ext_data) abort(); + memcpy(mod.ext_data, state->master_bios + mod.start, mod.size); + goto bios_ok; + +file_fail: goto try_bios; +bios_fail: goto giveup; + +file_ok: goto codecheck; +bios_ok: goto codecheck; + +giveup: + { log_error; return 1; } + +codecheck: + printf(" "); + // if we're using an override code, great + if(code != 0xFFFFFFFF) { + mod.code = code; + // otherwise, try finding the BIOS code + } else { + struct MODULE tmpmod; + if(master_bios_modinfo(state, n, &tmpmod)) { + free(mod.ext_data); + { log_error; return 1; } + } + mod.code = tmpmod.code; + } + + if(mod.size < 4 || memcmp(mod.ext_data, "\x7F" "ELF", 4)) { + free(mod.ext_data); + { log_error; return 1; } + } + + master_module_free_add(state, &mod); + + return 0; +} + +/***************************************************************************/ + +static int pin(struct MKHEBIOS * state, const char *modname) { + char n[11]; + int i, l; + struct MODULE mod; + strncpy(n, modname, 10); + n[10] = 0; + l = strlen(n); + for(i = 0; i < l; i++) { n[i] = toupper(n[i]); } + + if(master_bios_modinfo(state, n, &mod)) { + { log_error; return 1; } + } + + mod.ext_data = malloc(mod.size); + if(!mod.ext_data) abort(); + memcpy(mod.ext_data, state->master_bios + mod.start, mod.size); + + master_module_pin_add(state, &mod); + + return 0; +} + +/***************************************************************************/ + +static int mkhebios_script_pin(struct MKHEBIOS * state, const char *args) { + return pin(state, args); +} + +/***************************************************************************/ + +static int mkhebios_iopbtconf_line(void *ctx, int linenum, const char *line) { + struct MKHEBIOS * state = ( struct MKHEBIOS * ) ctx; + int r; + if(!line[0]) return 0; + if(line[0] == '#') return 0; + master_iopbtconf_append(state, line); + if(!isalpha(line[0])) return 0; + r = irx(state, line); + if(r) { log_error; return 1; } + return 0; +} + +/***************************************************************************/ + +static int mkhebios_script_iopbtconf(struct MKHEBIOS * state, const char *args) { + struct MODULE mod; + + if(master_bios_modinfo(state, "IOPBTCONF", &mod)) { + { log_error; return 1; } + } + + if(read_script_file(state->iopbtconf_script, mkhebios_iopbtconf_line, state)) { log_error; return 1; } + + mod.size = strlen(state->master_iopbtconf); + mod.ext_data = malloc(mod.size); + if(!mod.ext_data) { log_error; return 1; } + memcpy(mod.ext_data, state->master_iopbtconf, mod.size); + master_module_free_add(state, &mod); + + return 0; +} + +/***************************************************************************/ + +static void rebuild_master_bios(struct MKHEBIOS *state) { + uint8 *p = state->romdir; + uint32 start = 0; + uint32 size; + uint16 code; + + memset(state->master_bios, 0, state->master_bios_size); + + for(;;) { + uint8 *srcdata = NULL; + char n[11]; +// int i; + memcpy(n, p, 10); + n[10] = 0; + if(!n[0]) break; + code = get16lsb(p + 0xA); + size = get32lsb(p + 0xC); +//printf("named module %s\n",n);fflush(stdout); + if(!strcmp(n, "-")) { + srcdata = NULL; + } else if(!strcmp(n, "ROMDIR")) { + srcdata = state->romdir; + } else { + struct MODULE *pmod = master_find_module(state, n); + if(!pmod) { return; } + srcdata = pmod->ext_data; + } + if(start >= state->master_bios_size) { return; } + if((start + size) >= state->master_bios_size) { return; } + if(srcdata) memcpy(state->master_bios + start, srcdata, size); + size += 0xF; size &= ~0xF; start += size; + p += 0x10; + } +} + +/***************************************************************************/ + +static int mkhebios_script_rebuild(struct MKHEBIOS *state, const char *args) { + uint32 romdir_size_min; + uint32 romdir_size_max; + + romdir_size_min = 0x10 * (state->master_module_free_n + state->master_module_pin_n); + romdir_size_max = 500000 & (~0xF); + + for( + state->romdir_size = romdir_size_min; + state->romdir_size <= romdir_size_max; + state->romdir_size += 0x10 + ) { + if(state->romdir) { free(state->romdir); state->romdir = NULL; } + state->romdir = malloc(state->romdir_size); + if(!state->romdir) { log_error; return 1; } + if(!attempt_rebuild_romdir(state)) break; + if(state->romdir) { free(state->romdir); state->romdir = NULL; } + } + + if(!state->romdir) { + log_error; return 1; + } + + rebuild_master_bios(state); + + return 0; +} + +/***************************************************************************/ + +static int mkhebios_script_patch(struct MKHEBIOS *state, const char *args) { + uint32 patchstart = 0; + uint8 patchfrom[1000]; + uint8 patchto[1000]; + uint32 patchfromny = 0; + uint32 patchtony = 0; + uint32 patchlen = 0; + char n[1000]; + int i = 0; + char *t = n; + for(;;) { + char c = *args++; + if(!c) break; + if(isspace(c)) continue; + n[i] = toupper(c); + if(i < (sizeof(n) - 1)) i++; + } + n[i] = 0; + t = n; + for(;;) { + int c = *t++; + if(c == ':') break; + if(c >= 'A' && c <= 'F') { c -= 'A'; c += 10; } + else if(c >= 'a' && c <= 'f') { c -= 'a'; c += 10; } + else if(c >= '0' && c <= '9') { c -= '0'; c += 0; } + else { log_error; return 1; } + patchstart <<= 4; + patchstart += c; + } +// printf("patchstart %X\n",patchstart); + + for(;;) { + int c = *t++; + if(c == ':') break; + if(c >= 'A' && c <= 'F') { c -= 'A'; c += 10; } + else if(c >= 'a' && c <= 'f') { c -= 'a'; c += 10; } + else if(c >= '0' && c <= '9') { c -= '0'; c += 0; } + else { log_error; return 1; } + patchfrom[patchfromny/2] <<= 4; + patchfrom[patchfromny/2] += c; + patchfromny++; + } + + for(;;) { + int c = *t++; + if(c == 0) break; + if(c >= 'A' && c <= 'F') { c -= 'A'; c += 10; } + else if(c >= 'a' && c <= 'f') { c -= 'a'; c += 10; } + else if(c >= '0' && c <= '9') { c -= '0'; c += 0; } + else { log_error; return 1; } + patchto[patchtony/2] <<= 4; + patchto[patchtony/2] += c; + patchtony++; + } + + if(patchfromny != patchtony) { log_error; return 1; } + patchlen = patchfromny / 2; + if(!patchlen) { log_error; return 1; } + + if(patchstart >= state->master_bios_size) { log_error; return 1; } + if((patchstart + patchlen) > state->master_bios_size) { log_error; return 1; } + + if(memcmp(state->master_bios + patchstart, patchfrom, patchlen)) { + log_error; return 1; + } + + memcpy(state->master_bios + patchstart, patchto, patchlen); + + return 0; +} + +/***************************************************************************/ + +static int mkhebios_script_asc(struct MKHEBIOS *state, const char *args) { + uint32 ascstart = 0; + + for(;;) { + int c = *args++; + if(!c) { log_error; return 1; } + if(isspace(c)) continue; + if(c == ':') break; + if(c >= 'A' && c <= 'F') { c -= 'A'; c += 10; } + else if(c >= 'a' && c <= 'f') { c -= 'a'; c += 10; } + else if(c >= '0' && c <= '9') { c -= '0'; c += 0; } + else { log_error; return 1; } + ascstart <<= 4; + ascstart += c; + } + + for(;;) { + int c = *args++; + if(!c) { log_error; return 1; } + if(isspace(c)) continue; + if(c == '\"') break; + } + + for(;;) { + int c = *args++; + if(!c) { log_error; return 1; } + if(c == '\"') break; + state->master_bios[ascstart % state->master_bios_size] = c; + ascstart++; + } + state->master_bios[ascstart % state->master_bios_size] = 0; + + return 0; +} + +/***************************************************************************/ +/* +** Returns nonzero on error +*/ +int mkhebios_script_line(void *ctx, int linenum, const char *line) { + struct MKHEBIOS *state = ( struct MKHEBIOS * ) ctx; + if(line[0] == '#') return 0; + + { int cmdlen = 0; + int ofs_to_args = 0; + while(line[cmdlen] && isalpha(line[cmdlen])) cmdlen++; + ofs_to_args = cmdlen; + while(line[ofs_to_args] && isspace(line[ofs_to_args])) ofs_to_args++; + + switch(cmdlen) { + case 3: + if(!memcmp(line, "pin", 3)) return mkhebios_script_pin(state, line + ofs_to_args); + if(!memcmp(line, "asc", 3)) return mkhebios_script_asc(state, line + ofs_to_args); + break; + case 4: + if(!memcmp(line, "load", 4)) return 0; /*mkhebios_script_load(line + ofs_to_args);*/ + if(!memcmp(line, "save", 4)) return 0; /*mkhebios_script_save(line + ofs_to_args);*/ + break; + case 5: + if(!memcmp(line, "patch", 5)) return mkhebios_script_patch(state, line + ofs_to_args); + break; + case 7: + if(!memcmp(line, "rebuild", 7)) return mkhebios_script_rebuild(state, line + ofs_to_args); + break; + /*case 8: + if(!memcmp(line, "deadbeef", 8)) return mkhebios_script_deadbeef(line + ofs_to_args); + break;*/ + case 9: + if(!memcmp(line, "iopbtconf", 9)) return mkhebios_script_iopbtconf(state, line + ofs_to_args); + break; + } + } + log_error; return 1; +} + +/***************************************************************************/ + +#include "mkhebios_scripts.h" + +void * EMU_CALL mkhebios_create( void * ps2_bios, int *size ) +{ + int rval; + + void * bios_out; + + struct MKHEBIOS * state; + + if ( *size != 0x400000 ) { log_error; return NULL; } + + state = master_init(); + if ( !state ) { log_error; return NULL; } + + state->master_bios = (uint8 *) malloc( 0x400000 ); + if ( !state->master_bios ) { + free( state ); + log_error; + return NULL; + } + + memcpy( state->master_bios, ps2_bios, 0x400000 ); + state->master_bios_size = 0x400000; + + state->iopbtconf_script = script_iopbtconf; + + rval = read_script_file( script_hebios, mkhebios_script_line, state ); + + if ( rval ) { + bios_out = NULL; + free( state->master_bios ); + log_error; + } + else { + bios_out = realloc( state->master_bios, 0x400000 / 8 ); + if ( !bios_out ) log_error; + *size = 0x400000 / 8; + } + + if ( state->master_iopbtconf ) free( state->master_iopbtconf ); + + if ( state->master_module_free_list ) { + for ( rval = 0; rval < state->master_module_free_n; rval++ ) { + free( state->master_module_free_list[ rval ].ext_data ); + } + free( state->master_module_free_list ); + } + + if ( state->master_module_pin_list ) { + for ( rval = 0; rval < state->master_module_pin_n; rval++ ) { + free( state->master_module_pin_list[ rval ].ext_data ); + } + free( state->master_module_pin_list ); + } + + if ( state->romdir ) free( state->romdir ); + + free( state ); + + return bios_out; +} + +void EMU_CALL mkhebios_delete( void * iop_bios ) +{ + free( iop_bios ); +} + +/***************************************************************************/ diff --git a/Frameworks/HighlyExperimental/HighlyExperimental/Core/mkhebios.h b/Frameworks/HighlyExperimental/HighlyExperimental/Core/mkhebios.h new file mode 100644 index 000000000..b30775283 --- /dev/null +++ b/Frameworks/HighlyExperimental/HighlyExperimental/Core/mkhebios.h @@ -0,0 +1,18 @@ +#ifndef MKHEBIOS_H +#define MKHEBIOS_H + +#include "emuconfig.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void * EMU_CALL mkhebios_create( void * ps2_bios, int *size ); + +void EMU_CALL mkhebios_delete( void * ); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Frameworks/HighlyExperimental/HighlyExperimental/Core/mkhebios_overlays.h b/Frameworks/HighlyExperimental/HighlyExperimental/Core/mkhebios_overlays.h new file mode 100644 index 000000000..523a3a16d --- /dev/null +++ b/Frameworks/HighlyExperimental/HighlyExperimental/Core/mkhebios_overlays.h @@ -0,0 +1,4388 @@ +static const uint8 module_fileio[] = { +0x7F,0x45,0x4C,0x46,0x1,0x1,0x1,0,0,0,0,0,0,0,0,0,0x80,0xFF,0x8,0,0x1,0,0,0,0,0,0,0,0x34,0,0,0, +0x4,0x2F,0,0,0x1,0,0,0,0x34,0,0x20,0,0x2,0,0x28,0,0xD,0,0xA,0,0x80,0,0,0x70,0x74,0,0,0,0,0,0,0, +0,0,0,0,0x29,0,0,0,0,0,0,0,0x4,0,0,0,0x4,0,0,0,0x1,0,0,0,0xA0,0,0,0,0,0,0,0, +0,0,0,0,0,0x2E,0,0,0x90,0x3D,0,0,0x7,0,0,0,0x10,0,0,0,0x40,0x2D,0,0,0,0,0,0,0xF0,0xAD,0,0, +0xF0,0x29,0,0,0x10,0x4,0,0,0x90,0xF,0,0,0xF,0x2,0x46,0x49,0x4C,0x45,0x49,0x4F,0x5F,0x73,0x65,0x72,0x76,0x69,0x63,0x65,0,0,0,0, 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+0x2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,}; + +static const uint8 module_ioman[] = { +0x7F,0x45,0x4C,0x46,0x1,0x1,0x1,0,0,0,0,0,0,0,0,0,0x80,0xFF,0x8,0,0x1,0,0,0,0,0,0,0,0x34,0,0,0, +0x48,0x21,0,0,0x1,0,0,0,0x34,0,0x20,0,0x2,0,0x28,0,0xC,0,0x9,0,0x80,0,0,0x70,0x74,0,0,0,0,0,0,0, +0,0,0,0,0x2A,0,0,0,0,0,0,0,0x4,0,0,0,0x4,0,0,0,0x1,0,0,0,0xA0,0,0,0,0,0,0,0, +0,0,0,0,0x50,0x20,0,0,0xE0,0x22,0,0,0x7,0,0,0,0x10,0,0,0,0x20,0x1F,0,0,0,0,0,0,0x40,0xA0,0,0, +0x60,0x1E,0,0,0xF0,0x1,0,0,0x90,0x2,0,0,0x3,0x2,0x49,0x4F,0x2F,0x46,0x69,0x6C,0x65,0x5F,0x4D,0x61,0x6E,0x61,0x67,0x65,0x72,0,0,0, +0xE8,0xFF,0xBD,0x27,0x10,0,0xB0,0xAF,0,0,0x10,0x3C,0xA0,0x1C,0x10,0x26,0x14,0,0xBF,0xAF,0x62,0x7,0,0xC,0x21,0x20,0,0x2,0x3,0,0x40,0x10, +0,0,0,0,0x2A,0,0,0x8,0x1,0,0x2,0x24,0x21,0x20,0,0x2,0x66,0x7,0,0xC,0x2,0,0x5,0x24,0,0,0x10,0x3C,0x60,0x22,0x10,0x26, +0x21,0x20,0,0x2,0,0,0x1,0x3C,0x50,0x20,0x20,0xAC,0x7C,0x7,0,0xC,0x80,0,0x5,0x24,0xE,0,0x4,0x24,0x78,0,0x3,0x26,0x70,0,0x2,0x24, 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+0x98,0x18,0,0,0x6,0,0,0,0x9C,0x18,0,0,0x4,0,0,0,0xEC,0x18,0,0,0x5,0,0,0,0xF0,0x18,0,0,0x6,0,0,0, +0x8,0x19,0,0,0x5,0,0,0,0xC,0x19,0,0,0x6,0,0,0,0x30,0x19,0,0,0x5,0,0,0,0x34,0x19,0,0,0x6,0,0,0, +0x40,0x19,0,0,0x5,0,0,0,0x44,0x19,0,0,0x6,0,0,0,0x78,0x19,0,0,0x4,0,0,0,0xB8,0x19,0,0,0x4,0,0,0, +0xC4,0x19,0,0,0x5,0,0,0,0xC8,0x19,0,0,0x6,0,0,0,0xC0,0x1F,0,0,0x2,0,0,0,0xC8,0x1F,0,0,0x2,0,0,0, +0xCC,0x1F,0,0,0x2,0,0,0,0xD0,0x1F,0,0,0x2,0,0,0,0xD4,0x1F,0,0,0x2,0,0,0,0xD8,0x1F,0,0,0x2,0,0,0, +0xDC,0x1F,0,0,0x2,0,0,0,0xE0,0x1F,0,0,0x2,0,0,0,0xE4,0x1F,0,0,0x2,0,0,0,0xE8,0x1F,0,0,0x2,0,0,0, +0xEC,0x1F,0,0,0x2,0,0,0,0xF0,0x1F,0,0,0x2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, +0,}; + +static const uint8 module_modload[] = { +0x7F,0x45,0x4C,0x46,0x1,0x1,0x1,0,0,0,0,0,0,0,0,0,0x80,0xFF,0x8,0,0x1,0,0,0,0,0,0,0,0x34,0,0,0, +0xEC,0x36,0,0,0x1,0,0,0,0x34,0,0x20,0,0x2,0,0x28,0,0xC,0,0x9,0,0x80,0,0,0x70,0x74,0,0,0,0,0,0,0, +0,0,0,0,0x2E,0,0,0,0,0,0,0,0x4,0,0,0,0x4,0,0,0,0x1,0,0,0,0xB0,0,0,0,0,0,0,0, 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+0x2,0,0,0,0x20,0x10,0,0,0x2,0,0,0,0x24,0x10,0,0,0x2,0,0,0,0x28,0x10,0,0,0x2,0,0,0,0x2C,0x10,0,0, +0x2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,}; + +static const struct +{ + const char * name; + const uint8 * data; + int size; +} +modules_list[] = +{ + { "fileio", module_fileio, sizeof(module_fileio) }, + { "he", module_he, sizeof(module_he) }, + { "ioman", module_ioman, sizeof(module_ioman) }, + { "loadcore", module_loadcore, sizeof(module_loadcore) }, + { "loadfile", module_loadfile, sizeof(module_loadfile) }, + { "modload", module_modload, sizeof(module_modload) }, + { "sifinit", module_sifinit, sizeof(module_sifinit) }, + { "stdio", module_stdio, sizeof(module_stdio) }, + { "sysclib", module_sysclib, sizeof(module_sysclib) }, + { "threadman", module_threadman, sizeof(module_threadman) }, + { "timemani", module_timemani, sizeof(module_timemani) }, + { NULL, NULL, 0 } +}; diff --git a/Frameworks/HighlyExperimental/HighlyExperimental/Core/mkhebios_scripts.h b/Frameworks/HighlyExperimental/HighlyExperimental/Core/mkhebios_scripts.h new file mode 100644 index 000000000..2466705eb --- /dev/null +++ b/Frameworks/HighlyExperimental/HighlyExperimental/Core/mkhebios_scripts.h @@ -0,0 +1,107 @@ +static const char script_hebios[] = +"#\n" +"# Script for creating hebios-50na.bin\n" +"#\n" +"\n" +"load image/ps2-50na.bin\n" +"\n" +"# Necessary to maintain block before ROMDIR\n" +"pin reset\n" +"\n" +"# Necessary fixed modules for PS1\n" +"pin tbin\n" +"pin sbin\n" +"# Necessary fixed modules for PS2\n" +"pin iopboot\n" +"# IOPBTCONF\n" +"iopbtconf he-iopbtconf.txt\n" +"# Rebuild the ROM image.\n" +"rebuild\n" +"# PS1 preboot patch\n" +"patch 52360: DC 34 F1 0F 07 00 04 24: FF FF 00 10 00 00 00 00\n" +"# PS2 preboot patch\n" +"patch 4A448: 00 00 00 00 09 F8 40 00 21 20 60 02: 21 20 60 02 FF FF 00 10 00 00 00 00\n" +"# BIOS environment\n" +"asc 80: \"Highly Experimental ps1preboot=52360 ps2preboot=4A44C\"\n" +"\n" +"save hebios-50na.bin\n"; + +static const char script_iopbtconf[] = +"#\n" +"# IOPBTCONF for Highly Experimental\n" +"#\n" +"# Note that mkhebios will strip blank lines or\n" +"# lines starting with '#' because the real BIOS\n" +"# doesn't.\n" +"#\n" +"# start at 0x800 in memory\n" +"@800\n" +"# these first two are loaded by the bios (preboot)\n" +"SYSMEM\n" +"LOADCORE\n" +"\n" +"EXCEPMAN\n" +"# seems unnecessary. does nothing if in native IOP mode\n" +"# INTRMANP\n" +"# this is probably the native IOP version\n" +"INTRMANI\n" +"\n" +"SSBUSC\n" +"DMACMAN\n" +"\n" +"# seems unnecessary. does nothing if in native IOP mode\n" +"# TIMEMANP\n" +"# this is probably the native IOP version\n" +"TIMEMANI\n" +"\n" +"SYSCLIB\n" +"HEAPLIB\n" +"\n" +"# disabled - hang\n" +"# EECONF\n" +"\n" +"THREADMAN\n" +"VBLANK\n" +"\n" +"IOMAN\n" +"# ttyhack overwrites the tty function pointer for H.E. (obsolete)\n" +"# TTYHACK,C\n" +"# modload does LoadStartModule and all that stuff\n" +"# it needs to be loaded after ioman because it uses I/O\n" +"MODLOAD\n" +"\n" +"# doesn't seem necessary.\n" +"# this does what it says - registers a \"rom:\" device in ioman\n" +"# which can read files from the BFC00000-BFFFFFFF area\n" +"# ROMDRV\n" +"\n" +"# stdio does printf, mainly. it's just a ioman write() wrapper.\n" +"STDIO\n" +"SIFMAN\n" +"IGREETING\n" +"SIFCMD\n" +"# the RebootByEE module isn't of much use without a EE\n" +"# REBOOT\n" +"LOADFILE\n" +"\n" +"# not much point to these since there is no CD/DVD emulation yet\n" +"# CDVDMAN\n" +"# CDVDFSV\n" +"\n" +"SIFINIT\n" +"FILEIO\n" +"\n" +"# this won't link because it needs cdvdman.\n" +"# probably copy protection related.\n" +"# SECRMAN\n" +"\n" +"# disabled - hang\n" +"# EESYNC\n" +"\n" +"# hefile sets up the hefile: device and runs hefile:/psf2.irx (obsolete)\n" +"# HEFILE,C\n" +"\n" +"# unified HE environment\n" +"HE,C\n" +"\n" +"# done\n"; diff --git a/Frameworks/HighlyExperimental/HighlyExperimental/Core/psx.c b/Frameworks/HighlyExperimental/HighlyExperimental/Core/psx.c new file mode 100644 index 000000000..dd4c59383 --- /dev/null +++ b/Frameworks/HighlyExperimental/HighlyExperimental/Core/psx.c @@ -0,0 +1,463 @@ +///////////////////////////////////////////////////////////////////////////// +// +// psx - Top-level emulation +// +///////////////////////////////////////////////////////////////////////////// + +#ifndef EMU_COMPILE +#error "Hi I forgot to set EMU_COMPILE" +#endif + +#include "psx.h" + +#include "r3000.h" +#include "iop.h" +#include "spu.h" +#include "bios.h" +#include "ioptimer.h" +#include "spucore.h" +#include "vfs.h" + +///////////////////////////////////////////////////////////////////////////// +// +// Static init for the whole library +// +static uint8 library_was_initialized = 0; + +static uint32 ps1preboot; +static uint32 ps2preboot; + +// +// Deliberately create a NULL dereference +// Useful for calling attention to show-stopper problems like forgetting to +// call psx_init() or compiling with the wrong byte order +// +static void psx_hang(const char *message) { + for(;;) { *((volatile char*)0) = *message; } +} + +// +// Endian check +// +static void psx_endian_check(void) { + uint32 num = 0x61626364; + // Big + if(!memcmp(&num, "abcd", 4)) { +#ifdef EMU_BIG_ENDIAN + return; +#endif + psx_hang("endian check"); + } + // Little + if(!memcmp(&num, "dcba", 4)) { +#ifndef EMU_BIG_ENDIAN + return; +#endif + psx_hang("endian check"); + } + // Don't know what! + psx_hang("endian check"); +} + +// +// Data type size check +// +static void psx_size_check(void) { + if(sizeof(uint8 ) != 1) psx_hang("size check"); + if(sizeof(uint16) != 2) psx_hang("size check"); + if(sizeof(uint32) != 4) psx_hang("size check"); + if(sizeof(uint64) != 8) psx_hang("size check"); + if(sizeof(sint8 ) != 1) psx_hang("size check"); + if(sizeof(sint16) != 2) psx_hang("size check"); + if(sizeof(sint32) != 4) psx_hang("size check"); + if(sizeof(sint64) != 8) psx_hang("size check"); +} + +static uint32 EMU_CALL getenvhex(const char *name) { + uint32 value; + char s[100]; + char *t = s; + if(bios_getenv(name, s, sizeof(s))) psx_hang("getenv failed"); + s[99] = 0; + value = 0; + for(;;) { + int c = *t++; + if(!c) break; + if(c >= 'a' && c <= 'f') { c -= 'a'; c += 10; } + else if(c >= 'A' && c <= 'F') { c -= 'A'; c += 10; } + else if(c >= '0' && c <= '9') { c -= '0'; c += 0; } + else psx_hang("invalid hex string"); + value <<= 4; + value += c; + } + return value; +} + +sint32 EMU_CALL psx_init(void) { + sint32 r; + psx_endian_check(); + psx_size_check(); + + // BIOS must be loaded first + if ( !bios_get_image_native() || !bios_get_imagesize() ) return 0; + // + // BIOS must be a power of 2, or all hell breaks loose + // + { uint32 s = bios_get_imagesize(); + if(s & (s - 1)) psx_hang("imagesize error"); + } + // + // Environment inits + // + ps1preboot = getenvhex("ps1preboot"); + ps2preboot = getenvhex("ps2preboot"); + + r = iop_init(); if(r) return r; + r = ioptimer_init(); if(r) return r; + r = r3000_init(); if(r) return r; + r = spu_init(); if(r) return r; + r = spucore_init(); if(r) return r; + r = vfs_init(); if(r) return r; + library_was_initialized = 1; + return 0; +} + +///////////////////////////////////////////////////////////////////////////// +// +// Version information +// +const char* EMU_CALL psx_getversion(void) { + static const char s[] = "PSXCore0008 (built " __DATE__ ")"; + return s; +} + +///////////////////////////////////////////////////////////////////////////// +// +// State information +// +struct PSX_STATE { + uint8 version; + uint32 offset_to_vfs; + uint32 offset_to_iop; + psx_console_out_t console_callback; + void *console_context; + uint8 console_enable; +}; + +#define PSXSTATE ((struct PSX_STATE*)(state)) +#define VFSSTATE ((void*)(((char*)(state))+(PSXSTATE->offset_to_vfs))) +#define IOPSTATE ((void*)(((char*)(state))+(PSXSTATE->offset_to_iop))) + +#define HAVE_VFS (PSXSTATE->offset_to_vfs!=0) +#define HAVE_IOP (PSXSTATE->offset_to_iop!=0) + +uint32 EMU_CALL psx_get_state_size(uint8 version) { + uint32 size = 0; + if(version != 2) version = 1; + size += sizeof(struct PSX_STATE); + size += iop_get_state_size(version); + if(version == 2) size += vfs_get_state_size(); + return size; +} + +static EMU_INLINE void EMU_CALL preboot(struct PSX_STATE *state, uint32 target_address) { + sint32 r; + for(;;) { + uint32 s = 10000; + r = iop_execute(IOPSTATE, state, 10000, NULL, &s, 0); + if(r < 0) break; + if(r3000_getreg(iop_get_r3000_state(IOPSTATE), R3000_REG_PC) == target_address) break; + } +} + +void EMU_CALL psx_clear_state(void *state, uint8 version) { + uint32 offset; + // + // If we haven't initialized, we really SHOULD have. + // + if(!library_was_initialized) psx_hang("library not initialized"); + + if(version != 2) version = 1; + // Clear local struct + memset(state, 0, sizeof(struct PSX_STATE)); + // Set local version + PSXSTATE->version = version; + // Set up offsets + offset = sizeof(struct PSX_STATE); + if(version == 2) { + PSXSTATE->offset_to_vfs = offset; offset += vfs_get_state_size(); + } + PSXSTATE->offset_to_iop = offset; offset += iop_get_state_size(version); + // Take care of VFS state + if(HAVE_VFS) vfs_clear_state(VFSSTATE); + // Take care of IOP state + if(HAVE_IOP) iop_clear_state(IOPSTATE, version); + // + // Do some final inits + // + switch(version) { + case 1: + // + // preboot for PS1 + // + preboot(PSXSTATE, 0xBFC00000 | (ps1preboot & 0x003FFFFF)); + r3000_setreg(iop_get_r3000_state(IOPSTATE), R3000_REG_PC , 0x80010000); + r3000_setreg(iop_get_r3000_state(IOPSTATE), R3000_REG_GEN+29, 0x801FFFF0); + break; + case 2: + // + // preboot for PS2 + // + preboot(PSXSTATE, 0xBFC00000 | (ps2preboot & 0x003FFFFF)); + // + // simulate jr $v0 to transfer execution to loadcore + // + r3000_setreg(iop_get_r3000_state(IOPSTATE), R3000_REG_PC, + r3000_getreg(iop_get_r3000_state(IOPSTATE), R3000_REG_GEN+2) + ); + break; + } + // Done +} + +// +// Obtain substates +// +void* EMU_CALL psx_get_iop_state(void *state) { return IOPSTATE; } + +///////////////////////////////////////////////////////////////////////////// +// +// Set readfile +// +void EMU_CALL psx_set_readfile( + void *state, + psx_readfile_t callback, + void *context +) { + if(HAVE_VFS) vfs_set_readfile(VFSSTATE, callback, context); +} + +///////////////////////////////////////////////////////////////////////////// +// +// Console +// +void EMU_CALL psx_set_console_out( + void *state, + psx_console_out_t callback, + void *context +) { + PSXSTATE->console_callback = callback; + PSXSTATE->console_context = context; +} + +void EMU_CALL psx_console_in(void *state, char c) { + +} + +///////////////////////////////////////////////////////////////////////////// + +static EMU_INLINE uint32 EMU_CALL get32lsb(uint8 *src) { + return + ((((uint32)(src[0])) & 0xFF) << 0) | + ((((uint32)(src[1])) & 0xFF) << 8) | + ((((uint32)(src[2])) & 0xFF) << 16) | + ((((uint32)(src[3])) & 0xFF) << 24); +} + +///////////////////////////////////////////////////////////////////////////// +// +// Determine if an ASCII string exists in a byte block +// +static int string_exists(const char *block, uint32 len, const char *string) { + uint32 sl = strlen(string); + uint32 i; + if(sl > len) return 0; + len = (len - sl) + 1; + for(i = 0; i < len; i++) { + if(memcmp(block + i, string, sl) == 0) return 1; + } + return 0; +} + +///////////////////////////////////////////////////////////////////////////// +// +// Upload PS-X EXE - must INCLUDE the header. +// If the header includes the strings "North America", "Japan", or "Europe", +// the appropriate refresh rate is set. +// Returns nonzero on error. +// Will return error for PS2. +// +sint32 EMU_CALL psx_upload_psxexe(void *state, void *program, uint32 size) { + uint32 init_pc; + uint32 init_sp; + uint32 text_start; + uint32 text_size; + + if(PSXSTATE->version != 1) return -1; + + if(size < 0x801) return -1; + if(memcmp(program, "PS-X EXE", 8)) return -1; + + text_start = get32lsb(((uint8*)program) + 0x18); + text_size = get32lsb(((uint8*)program) + 0x1C); + init_pc = get32lsb(((uint8*)program) + 0x10); + init_sp = get32lsb(((uint8*)program) + 0x30); + + // Try to determine the region, or leave it at the default if it's not found + if(string_exists(program, 0x800, "North America")) { psx_set_refresh(state, 60); } + else if(string_exists(program, 0x800, "Japan" )) { psx_set_refresh(state, 60); } + else if(string_exists(program, 0x800, "Europe" )) { psx_set_refresh(state, 50); } + + if(text_size > (size - 0x800)) { text_size = (size - 0x800); } + + iop_upload_to_ram(IOPSTATE, text_start, ((uint8*)program) + 0x800, text_size); + + r3000_setreg(iop_get_r3000_state(IOPSTATE), R3000_REG_PC , init_pc); + r3000_setreg(iop_get_r3000_state(IOPSTATE), R3000_REG_GEN+29, init_sp); + + return 0; +} + +///////////////////////////////////////////////////////////////////////////// +// +// Set the screen refresh rate in Hz (50 or 60 for PAL or NTSC) +// Only 50 or 60 are valid; other values will be ignored +// +void EMU_CALL psx_set_refresh(void *state, uint32 refresh) { + iop_set_refresh(IOPSTATE, refresh); +} + +///////////////////////////////////////////////////////////////////////////// +// +// Executes the given number of cycles or the given number of samples +// (whichever is less) +// +// Sets *sound_samples to the number of samples actually generated, +// which may be ZERO or LESS than the number requested, but never more. +// +// Return value: +// >= 0 The number of cycles actually executed, which may be ZERO, MORE, +// or LESS than the number requested +// -1 Halted successfully (only applicable to PS2 environment) +// <= -2 Unrecoverable error +// +sint32 EMU_CALL psx_execute( + void *state, + sint32 cycles, + sint16 *sound_buf, + uint32 *sound_samples, + uint32 event_mask +) { + return iop_execute(IOPSTATE, state, cycles, sound_buf, sound_samples, event_mask); +} + +///////////////////////////////////////////////////////////////////////////// +// +// emu virtual I/O +// +static sint32 EMU_CALL vopen(void *vfsstate, uint8 *ram_native, uint32 ram_size, sint32 ofs) { + char path[256]; + sint32 i; + for(i = 0; i < 255; i++) { + char c = ram_native[(ofs & (ram_size-1)) ^ (EMU_ENDIAN_XOR(3))]; ofs++; + if(!c) break; + path[i] = c; + } + if(!i) return -2; // ENOENT if path is empty + path[i] = 0; + i = vfs_open(vfsstate, path); + return i; +} + +static sint32 EMU_CALL vclose(void *vfsstate, sint32 emufd) { + if(emufd < 0) return -9; + return vfs_close(vfsstate, emufd); +} + +#ifdef PSX_BIG_ENDIAN +// +// This byte swapper performs NO bounds checking. Prepare accordingly. +// Also, it assumes you're only calling it if PSX_BIG_ENDIAN is defined. +// +static void EMU_CALL vreadswap(uint8 *base, uint32 ofs, uint32 len) { + uint32 slop_0 = ofs & 3; + uint32 slop_1 = (0-(ofs+len)) & 3; + uint32 start = ofs - slop_0; + uint32 end = ofs + len + slop_1; + for(; start < end; start += 4) { + uint8 a, b, c, d; + a = base[start+0]; + b = base[start+1]; + c = base[start+2]; + d = base[start+3]; + base[start+0] = d; + base[start+1] = c; + base[start+2] = b; + base[start+3] = a; + } +} +#endif + +static sint32 EMU_CALL vread(void *vfsstate, uint8 *ram_native, uint32 ram_size, sint32 emufd, sint32 ofs, sint32 len) { + sint32 r; + if(emufd < 0) return -9; + if(len < 0) return -22; + if(len >= (sint32)ram_size) return -22; + ofs &= (ram_size-1); + if((len + ofs) > (sint32)ram_size) return -22; +#ifdef PSX_BIG_ENDIAN + vreadswap(ram_native, ofs, len); +#endif + r = vfs_read(vfsstate, emufd, ram_native + ofs, len); +#ifdef PSX_BIG_ENDIAN + vreadswap(ram_native, ofs, len); +#endif + return r; +} + +static sint32 EMU_CALL vlseek(void *vfsstate, sint32 emufd, sint32 offset, sint32 whence) { + if(emufd < 0) return -9; + if(whence < 0 || whence > 2) return -22; + if(whence == 0 && offset < 0) return -22; + return vfs_lseek(vfsstate, emufd, offset, whence); +} + +///////////////////////////////////////////////////////////////////////////// +// +// hefile emucall handler +// +sint32 EMU_CALL psx_emucall( + void *state, + uint8 *ram_native, + uint32 ram_size, + sint32 type, + sint32 emufd, + sint32 ofs, + sint32 arg1, + sint32 arg2 +) { + if(type == 0) { + if(PSXSTATE->console_callback) { + sint32 i; + for(i = 0; i < arg1; i++) { + char c = ram_native[ofs & (ram_size-1)]; ofs++; + if(c == 'H') { PSXSTATE->console_enable = 1; } + if(PSXSTATE->console_enable) { + (PSXSTATE->console_callback)(PSXSTATE->console_context, c); + } + } + } + return arg1; + } + if(!(HAVE_VFS)) return -5; + switch(type) { + case 3: return vopen (VFSSTATE, ram_native, ram_size, ofs); + case 4: return vclose(VFSSTATE, emufd); + case 5: return vread (VFSSTATE, ram_native, ram_size, emufd, ofs, arg1); + case 6: return -13; // EACCES permission denied + case 7: return vlseek(VFSSTATE, emufd, arg1, arg2); + default: return -5; + } +} + +///////////////////////////////////////////////////////////////////////////// diff --git a/Frameworks/HighlyExperimental/HighlyExperimental/Core/psx.h b/Frameworks/HighlyExperimental/HighlyExperimental/Core/psx.h new file mode 100644 index 000000000..1331dcdf0 --- /dev/null +++ b/Frameworks/HighlyExperimental/HighlyExperimental/Core/psx.h @@ -0,0 +1,157 @@ +///////////////////////////////////////////////////////////////////////////// +// +// psx - Top-level emulation +// +///////////////////////////////////////////////////////////////////////////// + +#ifndef __PSX_PSX_H__ +#define __PSX_PSX_H__ + +///////////////////////////////////////////////////////////////////////////// + +#include "emuconfig.h" + +///////////////////////////////////////////////////////////////////////////// + +#ifdef __cplusplus +extern "C" { +#endif + +///////////////////////////////////////////////////////////////////////////// +// +// Static init for the whole library +// Returns nonzero on error +// +// May generate a null dereference if the library was compiled wrong, but +// that's for me to worry about. +// +sint32 EMU_CALL psx_init(void); + +///////////////////////////////////////////////////////////////////////////// +// +// Version information +// +const char* EMU_CALL psx_getversion(void); + +///////////////////////////////////////////////////////////////////////////// +// +// State init +// Version = 1 for PS1, 2 for PS2 +// +// Example of usage: +// +// void *my_psx_state = malloc(psx_get_state_size(version)); +// psx_clear_state(my_psx_state, version); +// ... +// [subsequent emu calls] +// ... +// +uint32 EMU_CALL psx_get_state_size(uint8 version); +void EMU_CALL psx_clear_state(void *state, uint8 version); + +// Obtain substates +void* EMU_CALL psx_get_iop_state(void *state); + +///////////////////////////////////////////////////////////////////////////// +// +// Upload PS-X EXE - must INCLUDE the header. +// If the header includes the strings "North America", "Japan", or "Europe", +// the appropriate refresh rate is set. +// Returns nonzero on error. +// Will return error for PS2. +// +sint32 EMU_CALL psx_upload_psxexe(void *state, void *program, uint32 size); + +///////////////////////////////////////////////////////////////////////////// +// +// Set the screen refresh rate in Hz (50 or 60 for PAL or NTSC) +// Only 50 or 60 are valid; other values will be ignored +// +void EMU_CALL psx_set_refresh(void *state, uint32 refresh); + +///////////////////////////////////////////////////////////////////////////// +// +// Executes the given number of cycles or the given number of samples +// (whichever is less) +// +// Sets *sound_samples to the number of samples actually generated, +// which may be ZERO or LESS than the number requested, but never more. +// +// Return value: +// >= 0 The number of cycles actually executed, which may be ZERO, MORE, +// or LESS than the number requested +// -1 Halted successfully (only applicable to PS2 environment) +// <= -2 Unrecoverable error +// +sint32 EMU_CALL psx_execute( + void *state, + sint32 cycles, + sint16 *sound_buf, + uint32 *sound_samples, + uint32 event_mask +); + +///////////////////////////////////////////////////////////////////////////// +// +// hefile emucall handler +// Do not call this. +// +sint32 EMU_CALL psx_emucall( + void *state, + uint8 *ram_native, + uint32 ram_size, + sint32 type, + sint32 emufd, + sint32 ofs, + sint32 arg1, + sint32 arg2 +); + +///////////////////////////////////////////////////////////////////////////// +// +// Read file callback +// +typedef sint32 (EMU_CALL * psx_readfile_t)( + void *context, + const char *path, + sint32 offset, + char *buffer, + sint32 length +); + +// +// Register a callback and context +// Pass NULL for both to disable +// +void EMU_CALL psx_set_readfile( + void *state, + psx_readfile_t callback, + void *context +); + +///////////////////////////////////////////////////////////////////////////// +// +// Console +// +typedef void (EMU_CALL * psx_console_out_t)( + void *context, + char c +); + +void EMU_CALL psx_set_console_out( + void *state, + psx_console_out_t callback, + void *context +); + +void EMU_CALL psx_console_in(void *state, char c); + +///////////////////////////////////////////////////////////////////////////// + +#ifdef __cplusplus +} +#endif + +///////////////////////////////////////////////////////////////////////////// + +#endif diff --git a/Frameworks/HighlyExperimental/HighlyExperimental/Core/r3000.c b/Frameworks/HighlyExperimental/HighlyExperimental/Core/r3000.c new file mode 100644 index 000000000..6c9faa17d --- /dev/null +++ b/Frameworks/HighlyExperimental/HighlyExperimental/Core/r3000.c @@ -0,0 +1,731 @@ +///////////////////////////////////////////////////////////////////////////// +// +// r3000 - Emulates R3000 CPU +// +///////////////////////////////////////////////////////////////////////////// + +#ifndef EMU_COMPILE +#error "Hi I forgot to set EMU_COMPILE" +#endif + +#include "r3000.h" + +///////////////////////////////////////////////////////////////////////////// +/* +** integer overflow exceptions are not taken! +** divide by zero exceptions are not taken! +*/ +///////////////////////////////////////////////////////////////////////////// + +///////////////////////////////////////////////////////////////////////////// +/* +** Divider is now hardcoded +*/ +#define DIVIDER (1) + +///////////////////////////////////////////////////////////////////////////// +/* +** Static information +*/ + +/* (none) */ + +sint32 EMU_CALL r3000_init(void) { + return 0; +} + +///////////////////////////////////////////////////////////////////////////// +/* +** State information +*/ + +#define STATE ((struct R3000_STATE*)(state)) + +#define C0_status (12) +#define C0_cause (13) +#define C0_epc (14) +#define C0_prid (15) + +struct R3000_STATE { + uint32 regs[32]; + + uint32 c0_status; + uint32 c0_cause; + uint32 c0_epc; + uint32 c0_prid; + + uint32 pc; + uint32 hi,lo; + + uint32 intpending; + + sint32 slot; + uint32 slot_target; + + sint32 cycles_remaining; + sint32 cycles_remaining_last_checkpoint; + sint32 cycles_deferred_from_break; + + /* usage statistics */ + sint32 usage_total_cycles; + sint32 usage_idle_cycles; + sint32 usage_cycles_max; + uint32 usage_last_fraction; + + uint32 cache_ctrl; + + uint32 cache_isolate; + + // + // These are REGISTERED EXTERNAL POINTERS. + // + r3000_advance_callback_t advance; + void *hwstate; + struct R3000_MEMORY_MAP *map_load; + struct R3000_MEMORY_MAP *map_store; + + // + // The following are TEMPORARY. + // There are no location invariance issues. + // + uint32 maxpc; + void *fetchbase; + uint32 fetchbox; +}; + +uint32 EMU_CALL r3000_get_state_size(void) { + return sizeof(struct R3000_STATE); +} + +void EMU_CALL r3000_clear_state(void *state) { + memset(state, 0, sizeof(struct R3000_STATE)); + STATE->c0_prid = 0x02; + STATE->pc = 0xBFC00000; + /* update statistics every 20 million cycles (may overshoot a little) */ + STATE->usage_cycles_max = 20000000; +} + +///////////////////////////////////////////////////////////////////////////// +/* +** Registration of external pointers within the state +*/ +void EMU_CALL r3000_set_memory_maps( + void *state, + struct R3000_MEMORY_MAP *map_load, + struct R3000_MEMORY_MAP *map_store +) { + STATE->map_load = map_load; + STATE->map_store = map_store; +} + +void EMU_CALL r3000_set_advance_callback( + void *state, + r3000_advance_callback_t advance, + void *hwstate +) { + STATE->advance = advance; + STATE->hwstate = hwstate; +} + +///////////////////////////////////////////////////////////////////////////// +/* +** Set the processor revision ID +*/ +void EMU_CALL r3000_set_prid(void *state, uint32 prid) { + STATE->c0_prid = prid; +} + +///////////////////////////////////////////////////////////////////////////// + +static EMU_INLINE uint32 EMU_CALL getc0(struct R3000_STATE *state, uint32 regnum) { + switch(regnum) { + case 12: return state->c0_status; + case 13: return state->c0_cause; + case 14: return state->c0_epc; + case 15: return state->c0_prid; + } + return 0; +} + +static EMU_INLINE void EMU_CALL setc0(struct R3000_STATE *state, uint32 regnum, uint32 value) { + switch(regnum) { + case 12: state->c0_status = value; break; + case 13: state->c0_cause = value; break; + case 14: state->c0_epc = value; break; + case 15: break; + } +} + +///////////////////////////////////////////////////////////////////////////// + +uint32 EMU_CALL r3000_getreg(void *state, sint32 regnum) { + if(regnum >= R3000_REG_GEN && regnum < (R3000_REG_GEN+32)) { return STATE->regs[regnum - R3000_REG_GEN]; } + if(regnum >= R3000_REG_C0 && regnum < (R3000_REG_C0+32)) { return getc0(STATE, regnum - R3000_REG_C0); } + switch(regnum) { + case R3000_REG_PC: return STATE->pc; + case R3000_REG_HI: return STATE->hi; + case R3000_REG_LO: return STATE->lo; + + case R3000_REG_CI: return STATE->cache_isolate; + + } + return 0; +} + +void EMU_CALL r3000_setreg(void *state, sint32 regnum, uint32 value) { + if(regnum >= R3000_REG_GEN && regnum < (R3000_REG_GEN+32)) { STATE->regs[regnum - R3000_REG_GEN] = value; return; } + if(regnum >= R3000_REG_C0 && regnum < (R3000_REG_C0+32)) { setc0(STATE, regnum - R3000_REG_C0, value); return; } + switch(regnum) { + case R3000_REG_PC: STATE->pc = value; return; + case R3000_REG_HI: STATE->hi = value; return; + case R3000_REG_LO: STATE->lo = value; return; + + case R3000_REG_CI: STATE->cache_isolate = value; return; + + } +} + +///////////////////////////////////////////////////////////////////////////// + +void EMU_CALL r3000_break(void *state) { + if(STATE->cycles_remaining <= 0) return; + STATE->cycles_deferred_from_break += STATE->cycles_remaining; + STATE->cycles_remaining_last_checkpoint -= STATE->cycles_remaining; + STATE->cycles_remaining = 0; +} + +void EMU_CALL r3000_setinterrupt(void *state, uint32 intpending) { + STATE->intpending = intpending; + r3000_break(state); +} + +///////////////////////////////////////////////////////////////////////////// +/* +** Memory map walker +*/ +static EMU_INLINE struct R3000_MEMORY_TYPE* EMU_CALL mmwalk(struct R3000_MEMORY_MAP *map, uint32 a) { + a &= 0x1FFFFFFF; + for(;; map++) { + uint32 x = map->x; + uint32 y = map->y; + if(a < x || a > y) continue; + return &(map->type); + } +} + +///////////////////////////////////////////////////////////////////////////// + +static EMU_INLINE void EMU_CALL exception(struct R3000_STATE *state, uint32 cause, uint32 IP) { + /* Step out of the delay slot, if we were in one */ + if(state->slot) { +// state->pc = state->slot_target & (~3); + state->pc -= 4; + state->slot = 0; + } + + /* Shift mode/interrupt bits */ + state->c0_status = + (state->c0_status & 0xFFFFFFC0) | + ((state->c0_status & 0x0F) << 2); + state->c0_epc = state->pc; + state->c0_cause = ((cause & 0xF) << 2) | ((IP & 0x3F) << 10); + /* ignore BEV for now */ + state->pc = 0x80000080; + + /* Force a recheck of the memory map */ + state->maxpc = 0; + +//printf("exception %08X %08X\n",cause,IP); +} + +///////////////////////////////////////////////////////////////////////////// + +static EMU_INLINE void EMU_CALL update_usage(void *state) { + /* + ** Update usage statistics + */ + if(STATE->usage_total_cycles >= STATE->usage_cycles_max) { + sint64 fraction; + /* + ** Bounds checking + */ + if(STATE->usage_total_cycles <= 0) { STATE->usage_total_cycles = 1; } + + if(STATE->usage_idle_cycles > STATE->usage_total_cycles) { + STATE->usage_idle_cycles = STATE->usage_total_cycles; + } else if(STATE->usage_idle_cycles < 0) { + STATE->usage_idle_cycles = 0; + } + + fraction = STATE->usage_total_cycles - STATE->usage_idle_cycles; + fraction *= ((sint64)(0x20000)); + fraction /= ((sint64)(STATE->usage_total_cycles)); + fraction++; + fraction /= 2; + if(fraction < 0x00000) fraction = 0x00000; + if(fraction > 0x10000) fraction = 0x10000; + STATE->usage_last_fraction = (uint32)fraction; + STATE->usage_total_cycles = 0; + STATE->usage_idle_cycles = 0; + } +} + +///////////////////////////////////////////////////////////////////////////// + +#define INS_S ((uint32)((instruction>>21)&0x1F)) +#define INS_T ((uint32)((instruction>>16)&0x1F)) +#define INS_D ((uint32)((instruction>>11)&0x1F)) +#define INS_H ((uint32)((instruction>>6)&0x1F)) +#define INS_I ((uint32)(instruction&0xFFFF)) + +#define SIGNED16(x) ((sint32)(((sint16)(x)))) +#define UNSIGNED16(x) ((uint32)(((uint16)(x)))) + +#define REL_I (PC+4+(((sint32)(SIGNED16(INS_I)))<<2)) +#define ABS_I ((PC&0xF0000000)|((instruction<<2)&0x0FFFFFFC)) + +#define J_REL_I {STATE->slot=2;STATE->slot_target=REL_I;} +#define J_ABS_I {STATE->slot=2;STATE->slot_target=ABS_I;} + +#define REGS (STATE->regs) +#define HI (STATE->hi) +#define LO (STATE->lo) +#define PC (STATE->pc) + +static EMU_INLINE void EMU_CALL cold_interrupt_check(struct R3000_STATE *state) { + uint32 hotint = ((STATE->intpending) & (STATE->c0_status >> 8)) & 0x3F; + if(!(STATE->c0_status & 1)) hotint = 0; + if(hotint) { exception(STATE, 0, hotint); state->cycles_remaining -= DIVIDER; } +} + +static EMU_INLINE void EMU_CALL hw_sync(struct R3000_STATE *state) { + sint32 d = state->cycles_remaining_last_checkpoint - state->cycles_remaining; + if(d > 0) { + state->advance(state->hwstate, d); + state->cycles_remaining_last_checkpoint = state->cycles_remaining; + } +} + +static EMU_INLINE void EMU_CALL renew_fetch_region(struct R3000_STATE *state) { + struct R3000_MEMORY_TYPE *t = mmwalk(state->map_load, state->pc); + if(t->n == R3000_MAP_TYPE_POINTER) { + uint32 astart = (state->pc) & (~(t->mask)); + state->maxpc = astart + ((t->mask) + 1); + state->fetchbase = ((uint8*)(t->p)) - astart; + } else { + state->maxpc = state->pc + 4; + state->fetchbase = ((uint8*)(&(state->fetchbox)))-(state->pc); + state->fetchbox = ((r3000_load_callback_t)(t->p))(state->hwstate, state->pc, 0xFFFFFFFF); + } +} + +static EMU_INLINE uint32 EMU_CALL lb(struct R3000_STATE *state, uint32 a) { + struct R3000_MEMORY_TYPE *t = mmwalk(state->map_load, a); + a &= t->mask; + if(t->n == R3000_MAP_TYPE_POINTER) { + a ^= EMU_ENDIAN_XOR(3); + return *((uint8*)(((uint8*)(t->p))+a)); + } else { + uint32 sh = (a & 3) * 8; + hw_sync(state); + a = ((r3000_load_callback_t)(t->p))(state->hwstate, a & (~3), 0xFF << sh); + a >>= sh; + return a & 0xFF; + } +} + +static EMU_INLINE uint32 EMU_CALL lh(struct R3000_STATE *state, uint32 a) { + struct R3000_MEMORY_TYPE *t = mmwalk(state->map_load, a); + a &= t->mask; + if(t->n == R3000_MAP_TYPE_POINTER) { + a ^= EMU_ENDIAN_XOR(2); + a &= (~1); + return *((uint16*)(((uint8*)(t->p))+a)); + } else { + uint32 sh = (a & 2) * 8; + hw_sync(state); + a = ((r3000_load_callback_t)(t->p))(state->hwstate, a & (~3), 0xFFFF << sh); + a >>= sh; + return a & 0xFFFF; + } +} + +static EMU_INLINE uint32 EMU_CALL lw(struct R3000_STATE *state, uint32 a) { + struct R3000_MEMORY_TYPE *t; + /* + ** HACK HACK HACK TODO fix later + */ + if(a == 0xFFFE0130) { + return state->cache_ctrl; + } + t = mmwalk(state->map_load, a); + a &= t->mask; + if(t->n == R3000_MAP_TYPE_POINTER) { + a &= (~3); + return *((uint32*)(((uint8*)(t->p))+a)); + } else { + hw_sync(state); + a = ((r3000_load_callback_t)(t->p))(state->hwstate, a & (~3), 0xFFFFFFFF); + return a; + } +} + +// +// Performs no callbacks; suitable for prediction +// +static EMU_INLINE uint32 EMU_CALL lw_noeffects(struct R3000_STATE *state, uint32 a) { + struct R3000_MEMORY_TYPE *t; + t = mmwalk(state->map_load, a); + a &= t->mask; + if(t->n == R3000_MAP_TYPE_POINTER) { + a &= (~3); + return *((uint32*)(((uint8*)(t->p))+a)); + } else { + return 0; + } +} + +static EMU_INLINE void EMU_CALL sb(struct R3000_STATE *state, uint32 a, uint32 d) { + struct R3000_MEMORY_TYPE *t = mmwalk(state->map_store, a); + a &= t->mask; + if(t->n == R3000_MAP_TYPE_POINTER) { + a ^= EMU_ENDIAN_XOR(3); + *((uint8*)(((uint8*)(t->p))+a)) = d; + } else { + uint32 sh = (a & 3) * 8; + hw_sync(state); + d &= 0xFF; + ((r3000_store_callback_t)(t->p))(state->hwstate, a & (~3), d << sh, 0xFF << sh); + } +} + +static EMU_INLINE void EMU_CALL sh(struct R3000_STATE *state, uint32 a, uint32 d) { + struct R3000_MEMORY_TYPE *t = mmwalk(state->map_store, a); + a &= t->mask; + if(t->n == R3000_MAP_TYPE_POINTER) { + a ^= EMU_ENDIAN_XOR(2); + a &= (~1); + *((uint16*)(((uint8*)(t->p))+a)) = d; + } else { + uint32 sh = (a & 2) * 8; + hw_sync(state); + d &= 0xFFFF; + ((r3000_store_callback_t)(t->p))(state->hwstate, a & (~3), d << sh, 0xFFFF << sh); + } +} + +static EMU_INLINE void EMU_CALL sw(struct R3000_STATE *state, uint32 a, uint32 d) { + struct R3000_MEMORY_TYPE *t; + /* + ** HACK HACK HACK TODO fix later + */ + if(a == 0xFFFE0130) { + state->cache_ctrl = d; + if(d >= 0x10000) { + state->cache_isolate = 0; + } else { + state->cache_isolate = 1; + } + return; + } + if(state->cache_isolate) return; + + t = mmwalk(state->map_store, a); + a &= t->mask; + a &= (~3); + if(t->n == R3000_MAP_TYPE_POINTER) { + *((uint32*)(((uint8*)(t->p))+a)) = d; + } else { + hw_sync(state); + ((r3000_store_callback_t)(t->p))(state->hwstate, a & (~3), d, 0xFFFFFFFF); + } +} + +static EMU_INLINE uint32 EMU_CALL fetch(struct R3000_STATE *state) { + if(state->pc >= state->maxpc) renew_fetch_region(state); + return *((uint32*)(((uint8*)(state->fetchbase))+(state->pc))); +} + +#define caseMINOR(a) case(a): +#define caseMAJOR(a) case(a): + +// +// Returns 0 or positive on success +// Returns negative on error +// (value is otherwise meaningless for now) +// +sint32 EMU_CALL r3000_execute(void *state, sint32 cycles) { + uint32 a, d; + uint32 instruction; + + STATE->cycles_remaining_last_checkpoint = cycles; + STATE->cycles_remaining = cycles; + STATE->cycles_deferred_from_break = 0; + + STATE->usage_total_cycles += cycles; + + PC &= (~3); + + cold_interrupt_check(STATE); + + // + // This guarantees location invariance on fetchbox/fetchbase + // + STATE->maxpc = 0; + + while(STATE->slot || STATE->cycles_remaining > 0) { + instruction = fetch(state); + if(instruction < 0x04000000) { + switch(instruction & 0x3F) { + /* MINOR */ + caseMINOR(0x00) /* sll */ if(INS_D) { REGS[INS_D] = ((uint32)(REGS[INS_T])) << INS_H; + } else { + /* idle detect */ + /* if this is a nop in a branch delay slot, and the target is the + ** previous instruction, then we are officially idle */ + if((STATE->slot) && (STATE->slot_target == (PC - 4))) { + /* steal off cycles under cycidle */ + sint32 cycidle = STATE->cycles_remaining; + if(cycidle < 0) { cycidle = 0; } + STATE->cycles_remaining -= cycidle; + STATE->usage_idle_cycles += cycidle; + + STATE->slot = 0; + PC -= 4; + STATE->maxpc = 0; + goto finishing_sync; + } + } + break; + caseMINOR(0x02) /* srl */ if(INS_D) { REGS[INS_D] = ((uint32)(REGS[INS_T])) >> INS_H; } break; + caseMINOR(0x03) /* sra */ if(INS_D) { REGS[INS_D] = ((sint32)(REGS[INS_T])) >> INS_H; } break; + caseMINOR(0x04) /* sllv */ if(INS_D) { uint32 sc=REGS[INS_S]; if(sc>=32){REGS[INS_D]=0;}else{REGS[INS_D]=REGS[INS_T]<=32){REGS[INS_D]=0;}else{REGS[INS_D]=REGS[INS_T]>>sc;} } break; + caseMINOR(0x07) /* srav */ if(INS_D) { uint32 sc=REGS[INS_S]; if(sc>=32){sc=31;} {REGS[INS_D]=(((sint32)(REGS[INS_T]))>>sc);} } break; + caseMINOR(0x08) /* jr */ if(!STATE->slot) { {STATE->slot=2;STATE->slot_target=REGS[INS_S];} } break; + caseMINOR(0x09) /* jalr */ if(!STATE->slot) { REGS[INS_D] = PC + 8;{STATE->slot=2;STATE->slot_target=REGS[INS_S];} } break; + caseMINOR(0x0C) /*syscall*/ if(!STATE->slot) { exception(STATE, 8, 0); PC -= 4; } break; + caseMINOR(0x10) /* mfhi */ if(INS_D) { REGS[INS_D] = HI; } break; + caseMINOR(0x11) /* mthi */ { HI = REGS[INS_S]; } break; + caseMINOR(0x12) /* mflo */ if(INS_D) { REGS[INS_D] = LO; } break; + caseMINOR(0x13) /* mtlo */ { LO = REGS[INS_S]; } break; + caseMINOR(0x18) /* mult */ { sint64 t = ((sint64)(((sint32)(REGS[INS_S])))) * ((sint64)(((sint32)(REGS[INS_T])))); LO = (uint32)(t); HI = (uint32)(t >> 32); } break; + caseMINOR(0x19) /* multu */ { uint64 t = ((uint64)(((uint32)(REGS[INS_S])))) * ((uint64)(((uint32)(REGS[INS_T])))); LO = (uint32)(t); HI = (uint32)(t >> 32); } break; + caseMINOR(0x1A) /* div */ if(REGS[INS_T]) { LO = ((sint32)(REGS[INS_S])) / ((sint32)(REGS[INS_T])); HI = ((sint32)(REGS[INS_S])) % ((sint32)(REGS[INS_T])); } break; + caseMINOR(0x1B) /* divu */ if(REGS[INS_T]) { LO = ((uint32)(REGS[INS_S])) / ((uint32)(REGS[INS_T])); HI = ((uint32)(REGS[INS_S])) % ((uint32)(REGS[INS_T])); } break; + caseMINOR(0x20) /* add */ if(INS_D) { REGS[INS_D] = (((uint32)(REGS[INS_S])) + ((uint32)(REGS[INS_T]))); } break; + caseMINOR(0x21) /* addu */ if(INS_D) { REGS[INS_D] = (((uint32)(REGS[INS_S])) + ((uint32)(REGS[INS_T]))); } break; + caseMINOR(0x22) /* sub */ if(INS_D) { REGS[INS_D] = (((uint32)(REGS[INS_S])) - ((uint32)(REGS[INS_T]))); } break; + caseMINOR(0x23) /* subu */ if(INS_D) { REGS[INS_D] = (((uint32)(REGS[INS_S])) - ((uint32)(REGS[INS_T]))); } break; + caseMINOR(0x24) /* and */ if(INS_D) { REGS[INS_D] = (((uint32)(REGS[INS_S])) & ((uint32)(REGS[INS_T]))); } break; + caseMINOR(0x25) /* or */ if(INS_D) { REGS[INS_D] = (((uint32)(REGS[INS_S])) | ((uint32)(REGS[INS_T]))); } break; + caseMINOR(0x26) /* xor */ if(INS_D) { REGS[INS_D] = (((uint32)(REGS[INS_S])) ^ ((uint32)(REGS[INS_T]))); } break; + caseMINOR(0x27) /* nor */ if(INS_D) { REGS[INS_D] = ~(((uint32)(REGS[INS_S])) | ((uint32)(REGS[INS_T]))); } break; + caseMINOR(0x2A) /* slt */ if(INS_D) { REGS[INS_D] = (((sint32)(REGS[INS_S])) < ((sint32)(REGS[INS_T]))); } break; + caseMINOR(0x2B) /* sltu */ if(INS_D) { REGS[INS_D] = (((uint32)(REGS[INS_S])) < ((uint32)(REGS[INS_T]))); } break; + default: goto badins; + } + } else { + switch(instruction >> 26) { + /* MAJOR */ + caseMAJOR(0x01) + switch(INS_T) { + case 0x00: /* bltz */ if(!STATE->slot) { if( ((sint32)(REGS[INS_S])) < 0) { J_REL_I; } } break; + case 0x01: /* bgez */ if(!STATE->slot) { if( ((sint32)(REGS[INS_S])) >= 0) { J_REL_I; } } break; + case 0x10: /* bltzal*/ if(!STATE->slot) { if( ((sint32)(REGS[INS_S])) < 0) { REGS[31]=PC+8; J_REL_I; } } break; + case 0x11: /* bgezal*/ if(!STATE->slot) { if( ((sint32)(REGS[INS_S])) >= 0) { REGS[31]=PC+8; J_REL_I; } } break; + default: goto badins; + } + break; + caseMAJOR(0x02) /* j */ if(!STATE->slot) { J_ABS_I; } break; + caseMAJOR(0x03) /* jal */ if(!STATE->slot) { REGS[31]=PC+8; J_ABS_I; } break; + caseMAJOR(0x04) /* beq */ if(!STATE->slot) { if(REGS[INS_S] == REGS[INS_T]) { J_REL_I; } } break; + caseMAJOR(0x05) /* bne */ if(!STATE->slot) { if(REGS[INS_S] != REGS[INS_T]) { J_REL_I; } } break; + caseMAJOR(0x06) /* blez */ if(!STATE->slot) { if( ((sint32)(REGS[INS_S])) <= 0) { J_REL_I; } } break; + caseMAJOR(0x07) /* bgtz */ if(!STATE->slot) { if( ((sint32)(REGS[INS_S])) > 0) { J_REL_I; } } break; + caseMAJOR(0x08) /* addi */ if(INS_T) { REGS[INS_T] = REGS[INS_S] + SIGNED16(INS_I); } break; + caseMAJOR(0x09) /* addiu */ if(INS_T) { REGS[INS_T] = REGS[INS_S] + SIGNED16(INS_I); } break; + caseMAJOR(0x0A) /* slti */ if(INS_T) { REGS[INS_T] = ( ((sint32)(REGS[INS_S])) < ((sint32)( ((sint32)( SIGNED16(INS_I) )) )) ); } break; + caseMAJOR(0x0B) /* sltiu */ if(INS_T) { REGS[INS_T] = ( ((uint32)(REGS[INS_S])) < ((uint32)( ((sint32)( SIGNED16(INS_I) )) )) ); } break; + caseMAJOR(0x0C) /* andi */ if(INS_T) { REGS[INS_T] = REGS[INS_S] & UNSIGNED16(INS_I); } break; + caseMAJOR(0x0D) /* ori */ if(INS_T) { REGS[INS_T] = REGS[INS_S] | UNSIGNED16(INS_I); } break; + caseMAJOR(0x0E) /* xori */ if(INS_T) { REGS[INS_T] = REGS[INS_S] ^ UNSIGNED16(INS_I); } break; + caseMAJOR(0x0F) /* lui */ if(INS_T) { REGS[INS_T] = INS_I << 16; } break; + caseMAJOR(0x10) /* cop0 */ + switch(INS_S) { + case 0x00: /* mfc0 */ if(INS_T) { REGS[INS_T] = getc0(STATE, INS_D); } break; + case 0x04: /* mtc0 */ { setc0(STATE, INS_D, REGS[INS_T]); r3000_break(state); } break; + case 0x10: /* rfe */ { + STATE->c0_status = + (STATE->c0_status & 0xFFFFFFC0) | + ((STATE->c0_status & 0x3C) >> 2) | + ((STATE->c0_status & 0x03) << 4); + r3000_break(state); } break; + default: goto badins; + } + break; + caseMAJOR(0x20) /* lb */ { a = REGS[INS_S] + SIGNED16(INS_I); d = lb(state, a); if(INS_T) { REGS[INS_T] = ((sint32)((sint8)(d))); } } break; + caseMAJOR(0x21) /* lh */ { a = REGS[INS_S] + SIGNED16(INS_I); d = lh(state, a); if(INS_T) { REGS[INS_T] = ((sint32)((sint16)(d))); } } break; + caseMAJOR(0x23) /* lw */ { a = REGS[INS_S] + SIGNED16(INS_I); d = lw(state, a); if(INS_T) { REGS[INS_T] = d; } } break; + caseMAJOR(0x24) /* lbu */ { a = REGS[INS_S] + SIGNED16(INS_I); d = lb(state, a); if(INS_T) { REGS[INS_T] = d & 0x000000FF; } } break; + caseMAJOR(0x25) /* lhu */ { a = REGS[INS_S] + SIGNED16(INS_I); d = lh(state, a); if(INS_T) { REGS[INS_T] = d & 0x0000FFFF; } } break; + caseMAJOR(0x28) /* sb */ { a = REGS[INS_S] + SIGNED16(INS_I); sb(state, a, REGS[INS_T] & 0x000000FF); } break; + caseMAJOR(0x29) /* sh */ { a = REGS[INS_S] + SIGNED16(INS_I); sh(state, a, REGS[INS_T] & 0x0000FFFF); } break; + caseMAJOR(0x2B) /* sw */ { a = REGS[INS_S] + SIGNED16(INS_I); sw(state, a, REGS[INS_T] ); } break; + + caseMAJOR(0x22) /* lwl */ + a = REGS[INS_S] + SIGNED16(INS_I); + { int bitshift; + for(bitshift = 24;; bitshift -= 8) { + REGS[INS_T] &= ~(0xFF << bitshift); + REGS[INS_T] |= (((uint32)(lb(state, a))) & 0xFF) << bitshift; + if(!(a&3))break; + a--; + } + } + REGS[0] = 0; + break; + caseMAJOR(0x26) /* lwr */ + a = REGS[INS_S] + SIGNED16(INS_I); + { int bitshift; + for(bitshift = 0;; bitshift += 8) { + REGS[INS_T] &= ~(0xFF << bitshift); + REGS[INS_T] |= (((uint32)(lb(state, a))) & 0xFF) << bitshift; + if((a&3) == 3)break; + a++; + } + } + REGS[0] = 0; + break; + caseMAJOR(0x2A) /* swl */ + a = REGS[INS_S] + SIGNED16(INS_I); + { int bitshift; + for(bitshift = 24;; bitshift -= 8) { + sb(state, a, REGS[INS_T]>>bitshift); + if(!(a&3))break; + a--; + } + } + break; + caseMAJOR(0x2E) /* swr */ + a = REGS[INS_S] + SIGNED16(INS_I); + { int bitshift; + for(bitshift = 0;; bitshift += 8) { + sb(state, a, REGS[INS_T]>>bitshift); + if((a&3) == 3)break; + a++; + } + } + break; + + default: goto badins; + } + } + + PC += 4; + + STATE->cycles_remaining -= DIVIDER; + if(STATE->slot) { + STATE->slot--; + if(!(STATE->slot)) { + PC = STATE->slot_target & (~3); + STATE->maxpc = 0; + } + } + } + +finishing_sync: + + STATE->cycles_remaining_last_checkpoint += STATE->cycles_deferred_from_break; + STATE->cycles_remaining += STATE->cycles_deferred_from_break; + STATE->cycles_deferred_from_break = 0; + STATE->usage_total_cycles -= STATE->cycles_remaining; + update_usage(state); + + hw_sync(state); + return 0; + +badins: + + STATE->cycles_remaining_last_checkpoint += STATE->cycles_deferred_from_break; + STATE->cycles_remaining += STATE->cycles_deferred_from_break; + STATE->cycles_deferred_from_break = 0; + STATE->usage_total_cycles -= STATE->cycles_remaining; + update_usage(state); + + hw_sync(state); + return -1; + +} + +///////////////////////////////////////////////////////////////////////////// +// +// Get usage statistics +// +uint32 EMU_CALL r3000_get_usage_fraction(void *state) { + return STATE->usage_last_fraction; +} + +///////////////////////////////////////////////////////////////////////////// +// +// Perform prediction of what next instruction will do +// +// first word: address of next instruction +// following words describe possible activity +// 0xxxxxxx yyyyyyyy means "read x bytes from address y" +// 1xxxxxxx yyyyyyyy means "write x bytes from address y" +// 20000000 yyyyyyyy means "jump to y" +// 30000000 yyyyyyyy means "call to y" +// 00000000 terminates the list +// max 256 bytes in prediction profile +// +#define PROFILE_READ 0x00000000 +#define PROFILE_WRITE 0x10000000 +#define PROFILE_JUMP 0x20000000 +#define PROFILE_CALL 0x30000000 + +void EMU_CALL r3000_predict(void *state, uint32 *profile) { + uint32 instruction = lw_noeffects(STATE, PC); + *profile++ = PC + 4; + if(instruction < 0x04000000) { + switch(instruction & 0x3F) { + caseMINOR(0x08) /* jr */ *profile++ = PROFILE_JUMP; *profile++ = REGS[INS_S]; break; + caseMINOR(0x09) /* jalr */ *profile++ = PROFILE_CALL; *profile++ = REGS[INS_S]; break; + } + } else { + switch(instruction >> 26) { + caseMAJOR(0x01) + switch(INS_T) { + case 0x00: /* bltz */ *profile++ = PROFILE_JUMP; *profile++ = REL_I; break; + case 0x01: /* bgez */ *profile++ = PROFILE_JUMP; *profile++ = REL_I; break; + case 0x10: /* bltzal*/ *profile++ = PROFILE_CALL; *profile++ = REL_I; break; + case 0x11: /* bgezal*/ *profile++ = PROFILE_CALL; *profile++ = REL_I; break; + } + break; + caseMAJOR(0x02) /* j */ *profile++ = PROFILE_JUMP; *profile++ = ABS_I; break; + caseMAJOR(0x03) /* jal */ *profile++ = PROFILE_CALL; *profile++ = ABS_I; break; + caseMAJOR(0x04) /* beq */ *profile++ = PROFILE_JUMP; *profile++ = REL_I; break; + caseMAJOR(0x05) /* bne */ *profile++ = PROFILE_JUMP; *profile++ = REL_I; break; + caseMAJOR(0x06) /* blez */ *profile++ = PROFILE_JUMP; *profile++ = REL_I; break; + caseMAJOR(0x07) /* bgtz */ *profile++ = PROFILE_JUMP; *profile++ = REL_I; break; + + caseMAJOR(0x20) /* lb */ *profile++ = PROFILE_READ +1; *profile++ = REGS[INS_S] + SIGNED16(INS_I); break; + caseMAJOR(0x21) /* lh */ *profile++ = PROFILE_READ +2; *profile++ = REGS[INS_S] + SIGNED16(INS_I); break; + caseMAJOR(0x23) /* lw */ *profile++ = PROFILE_READ +4; *profile++ = REGS[INS_S] + SIGNED16(INS_I); break; + caseMAJOR(0x24) /* lbu */ *profile++ = PROFILE_READ +1; *profile++ = REGS[INS_S] + SIGNED16(INS_I); break; + caseMAJOR(0x25) /* lhu */ *profile++ = PROFILE_READ +2; *profile++ = REGS[INS_S] + SIGNED16(INS_I); break; + caseMAJOR(0x28) /* sb */ *profile++ = PROFILE_WRITE+1; *profile++ = REGS[INS_S] + SIGNED16(INS_I); break; + caseMAJOR(0x29) /* sh */ *profile++ = PROFILE_WRITE+2; *profile++ = REGS[INS_S] + SIGNED16(INS_I); break; + caseMAJOR(0x2B) /* sw */ *profile++ = PROFILE_WRITE+4; *profile++ = REGS[INS_S] + SIGNED16(INS_I); break; + + // these could be done better, but this is good enough for now + caseMAJOR(0x22) /* lwl */ *profile++ = PROFILE_READ +4; *profile++ = REGS[INS_S] + SIGNED16(INS_I); break; + caseMAJOR(0x26) /* lwr */ *profile++ = PROFILE_READ +4; *profile++ = REGS[INS_S] + SIGNED16(INS_I); break; + caseMAJOR(0x2A) /* swl */ *profile++ = PROFILE_WRITE+4; *profile++ = REGS[INS_S] + SIGNED16(INS_I); break; + caseMAJOR(0x2E) /* swr */ *profile++ = PROFILE_WRITE+4; *profile++ = REGS[INS_S] + SIGNED16(INS_I); break; + } + } + *profile = 0; +} + +///////////////////////////////////////////////////////////////////////////// diff --git a/Frameworks/HighlyExperimental/HighlyExperimental/Core/r3000.h b/Frameworks/HighlyExperimental/HighlyExperimental/Core/r3000.h new file mode 100644 index 000000000..ee9efff63 --- /dev/null +++ b/Frameworks/HighlyExperimental/HighlyExperimental/Core/r3000.h @@ -0,0 +1,73 @@ +///////////////////////////////////////////////////////////////////////////// +// +// r3000 - Emulates R3000 CPU +// +///////////////////////////////////////////////////////////////////////////// + +#ifndef __PSX_R3000_H__ +#define __PSX_R3000_H__ + +#include "emuconfig.h" + +#ifdef __cplusplus +extern "C" { +#endif + +sint32 EMU_CALL r3000_init(void); +uint32 EMU_CALL r3000_get_state_size(void); +void EMU_CALL r3000_clear_state(void *state); + +typedef uint32 (EMU_CALL * r3000_load_callback_t )(void *hwstate, uint32 a, uint32 dmask); +typedef void (EMU_CALL * r3000_store_callback_t )(void *hwstate, uint32 a, uint32 d, uint32 dmask); +typedef void (EMU_CALL * r3000_advance_callback_t)(void *hwstate, uint32 cycles); + +struct R3000_MEMORY_TYPE { uint32 mask, n; void *p; }; +struct R3000_MEMORY_MAP { uint32 x, y; struct R3000_MEMORY_TYPE type; }; +#define R3000_MAP_TYPE_POINTER (0) +#define R3000_MAP_TYPE_CALLBACK (1) + +void EMU_CALL r3000_set_memory_maps( + void *state, + struct R3000_MEMORY_MAP *map_load, + struct R3000_MEMORY_MAP *map_store +); +void EMU_CALL r3000_set_advance_callback( + void *state, + r3000_advance_callback_t advance, + void *hwstate +); + +void EMU_CALL r3000_set_prid(void *state, uint32 prid); + +#define R3000_REG_GEN (0) +#define R3000_REG_C0 (32) +#define R3000_REG_PC (64) +#define R3000_REG_HI (65) +#define R3000_REG_LO (66) +#define R3000_REG_CI (67) +#define R3000_REG_MAX (68) + +uint32 EMU_CALL r3000_getreg(void *state, sint32 regnum); +void EMU_CALL r3000_setreg(void *state, sint32 regnum, uint32 value); + +void EMU_CALL r3000_setinterrupt(void *state, uint32 intpending); +void EMU_CALL r3000_break(void *state); + +// +// Returns 0 or positive on success +// Returns negative on error +// (value is otherwise meaningless for now) +// Performs all iop_advance calls according to how many cycles it actually executed +// +sint32 EMU_CALL r3000_execute(void *state, sint32 cycles); + +void EMU_CALL r3000_predict(void *state, uint32 *profile); + +/* usage statistics - 0x10000 is 100% */ +uint32 EMU_CALL r3000_get_usage_fraction(void *state); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Frameworks/HighlyExperimental/HighlyExperimental/Core/r3000asm.c b/Frameworks/HighlyExperimental/HighlyExperimental/Core/r3000asm.c new file mode 100644 index 000000000..a33e0a98b --- /dev/null +++ b/Frameworks/HighlyExperimental/HighlyExperimental/Core/r3000asm.c @@ -0,0 +1,441 @@ +///////////////////////////////////////////////////////////////////////////// +// +// r3000asm - R3000 quick assembler (no symbols, no macro instructions) +// +///////////////////////////////////////////////////////////////////////////// + +#ifndef EMU_COMPILE +#error "Hi I forgot to set EMU_COMPILE" +#endif + +#include "r3000asm.h" + +///////////////////////////////////////////////////////////////////////////// + +enum { + TOKEN_NONE, + TOKEN_REG, + TOKEN_C0REG, + TOKEN_LPAREN, + TOKEN_RPAREN, + TOKEN_COMMA, + TOKEN_NUMBER, + TOKEN_UNKNOWN +}; + +///////////////////////////////////////////////////////////////////////////// + +static int myisspace(unsigned char c) { + return (c == 9 || c == 10 || c == 13 || c == 32); +} + +static int myisdigit(unsigned char c) { + return (c >= '0' && c <= '9'); +} +static int myisalpha(unsigned char c) { + return ((c >= 'A' && c <= 'Z') || (c >= 'a' && c <= 'z')); +} + +static int myisalnum(unsigned char c) { + return (myisalpha(c) || myisdigit(c)); +} + +///////////////////////////////////////////////////////////////////////////// +// +// Returns TRUE on match +// +static int alphacompare(const char *text, const char *pattern) { + for(; *pattern; pattern++, text++) { + if(!(*text)) return 0; + if(tolower(*text) != tolower(*pattern)) return 0; + } + // The key: The trailing text must be non-alnum + if(myisalnum(*text)) return 0; + return 1; +} + +///////////////////////////////////////////////////////////////////////////// + +static const char *scan(const char *text, uint32 *token, uint32 *subtoken) { + const char *s; + *token = TOKEN_UNKNOWN; + // + // Skip opening space + // + while(*text && myisspace(*text)) text++; + s = text; + // + // Token: None + // + if(!(*s)) { + *token = TOKEN_NONE; + return text; + } + // + // Token: Register + // + if(*s == '$') { + int regnum = 0; + s++; + if(myisdigit(*s)) { + regnum = *(s++) - '0'; + if(myisdigit(*s)) { + regnum = (regnum * 10) + (*(s++) - '0'); + } + if(regnum >= 32) return text; + } else { + char a = 0; + char b = 0; + if(*s) { a = tolower(*s); s++; } + if(*s) { b = tolower(*s); s++; } + if(a=='a'&&b=='t') { regnum = 1; } + else if(a=='v'&&b=='0') { regnum = 2; } + else if(a=='v'&&b=='1') { regnum = 3; } + else if(a=='a'&&b=='0') { regnum = 4; } + else if(a=='a'&&b=='1') { regnum = 5; } + else if(a=='a'&&b=='2') { regnum = 6; } + else if(a=='a'&&b=='3') { regnum = 7; } + else if(a=='t'&&b=='0') { regnum = 8; } + else if(a=='t'&&b=='1') { regnum = 9; } + else if(a=='t'&&b=='2') { regnum = 10; } + else if(a=='t'&&b=='3') { regnum = 11; } + else if(a=='t'&&b=='4') { regnum = 12; } + else if(a=='t'&&b=='5') { regnum = 13; } + else if(a=='t'&&b=='6') { regnum = 14; } + else if(a=='t'&&b=='7') { regnum = 15; } + else if(a=='s'&&b=='0') { regnum = 16; } + else if(a=='s'&&b=='1') { regnum = 17; } + else if(a=='s'&&b=='2') { regnum = 18; } + else if(a=='s'&&b=='3') { regnum = 19; } + else if(a=='s'&&b=='4') { regnum = 20; } + else if(a=='s'&&b=='5') { regnum = 21; } + else if(a=='s'&&b=='6') { regnum = 22; } + else if(a=='s'&&b=='7') { regnum = 23; } + else if(a=='t'&&b=='8') { regnum = 24; } + else if(a=='t'&&b=='9') { regnum = 25; } + else if(a=='k'&&b=='0') { regnum = 26; } + else if(a=='k'&&b=='1') { regnum = 27; } + else if(a=='g'&&b=='p') { regnum = 28; } + else if(a=='s'&&b=='p') { regnum = 29; } + else if(a=='f'&&b=='p') { regnum = 30; } + else if(a=='r'&&b=='a') { regnum = 31; } + else { return text; } + } + *token = TOKEN_REG; + *subtoken = regnum; + return s; + } + // + // Token: C0 register + // + if(tolower(s[0]) == 'C' && s[1] == '0' && s[2] == '_') { + int regnum = 0; + s += 3; + if(myisdigit(*s)) { + regnum = *(s++) - '0'; + if(myisdigit(*s)) { + regnum = (regnum * 10) + (*(s++) - '0'); + } + if(regnum >= 32) return text; + } else { + if(alphacompare(s, "status")) { regnum = 12; } + else if(alphacompare(s, "cause" )) { regnum = 13; } + else if(alphacompare(s, "epc" )) { regnum = 14; } + else { return text; } + } + *token = TOKEN_C0REG; + *subtoken = regnum; + return s; + } + // + // Token: Various punctuation + // + switch(*s) { + case ',': s++; *token = TOKEN_COMMA ; return s; + case '(': s++; *token = TOKEN_LPAREN; return s; + case ')': s++; *token = TOKEN_RPAREN; return s; + } + // + // Token: Number + // + if(myisdigit(*s) || *s == '-') { + int bNegative = 0; + int radix = 10; + int num = 0; + if(*s == '-') { bNegative = 1; s++; } + if(*s == '0') { + s++; + if(tolower(*s) == 'x') { + radix = 16; + s++; + } else { + radix = 8; + } + } + for(;;) { + int digit = 0; + char c = *s; + if(!c) break; + if(c >= '0' && c <= '9') { digit = c - '0'; } + else if(c >= 'a' && c <= 'f') { digit = 10 + c - 'a'; } + else if(c >= 'A' && c <= 'F') { digit = 10 + c - 'A'; } + else { break; } + if(digit >= radix) return text; + num *= radix; + num += digit; + s++; + } + if(bNegative) { num = -num; } + *token = TOKEN_NUMBER; + *subtoken = num; + return s; + } + // + // Token was unknown + // + return text; +} + +///////////////////////////////////////////////////////////////////////////// + +static void replaceinsfield(uint32 *ins, int nBitPosition, int nBits, uint32 dwValue) { + uint32 dwMask = (1 << nBits) - 1; + dwValue &= dwMask; + (*ins) &= ~(dwMask << nBitPosition); + (*ins) |= (dwValue << nBitPosition); +} + +///////////////////////////////////////////////////////////////////////////// + +static const char *assemblepattern( + const char *pattern, + uint32 pc, + const char *text, + uint32 *ins +) { + uint32 token; + uint32 subtoken; + for(;;) { + char p = *pattern++; + text = scan(text, &token, &subtoken); + switch(p) { + case 0: + if(token != TOKEN_NONE) return "Expected end-of-line"; + return NULL; + case ',': + if(token != TOKEN_COMMA) return "Expected ','"; + break; + case '(': + if(token != TOKEN_LPAREN) return "Expected '('"; + break; + case ')': + if(token != TOKEN_RPAREN) return "Expected ')'"; + break; + // + // S is 21 + // T is 16 + // D is 11 + // + case 'S': + if(token != TOKEN_REG) return "Expected register name"; + replaceinsfield(ins, 21, 5, subtoken); + break; + case 'T': + if(token != TOKEN_REG) return "Expected register name"; + replaceinsfield(ins, 16, 5, subtoken); + break; + case 'D': + if(token != TOKEN_REG) return "Expected register name"; + replaceinsfield(ins, 11, 5, subtoken); + break; + // + // E = D and T + // F = D and S + // G = T and S + // + case 'E': + if(token != TOKEN_REG) return "Expected register name"; + replaceinsfield(ins, 11, 5, subtoken); + replaceinsfield(ins, 16, 5, subtoken); + break; + case 'F': + if(token != TOKEN_REG) return "Expected register name"; + replaceinsfield(ins, 11, 5, subtoken); + replaceinsfield(ins, 21, 5, subtoken); + break; + case 'G': + if(token != TOKEN_REG) return "Expected register name"; + replaceinsfield(ins, 16, 5, subtoken); + replaceinsfield(ins, 21, 5, subtoken); + break; + case 'H': + if(token != TOKEN_NUMBER) return "Expected shift constant"; + replaceinsfield(ins, 6, 5, subtoken); + break; + case 'I': + if(token != TOKEN_NUMBER) return "Expected number"; + replaceinsfield(ins, 0, 16, subtoken); + break; + case 'C': + if(token != TOKEN_C0REG) return "Expected C0 register name"; + replaceinsfield(ins, 11, 5, subtoken); + break; + case 'J': + if(token != TOKEN_NUMBER) return "Expected address"; + replaceinsfield(ins, 0, 26, subtoken>>2); + break; + case 'B': + if(token != TOKEN_NUMBER) return "Expected address"; + replaceinsfield(ins, 0, 16, (subtoken-(pc+4))>>2); + break; + } + } +} + +///////////////////////////////////////////////////////////////////////////// + +const char *assemblepatterns( + const char *patterns, + uint32 pc, + const char *text, + uint32 *ins, + uint32 insTemplate +) { + int i; + const char *complaint = NULL; + do { + char pattemp[20]; + *ins = insTemplate; + for(i = 0;; i++) { + char c = *patterns; + if(!c) break; + patterns++; + if(c == '/') break; + pattemp[i] = c; + } + pattemp[i] = 0; + complaint = assemblepattern(pattemp, pc, text, ins); + if(!complaint) break; + } while(*patterns); + return complaint; +} + +///////////////////////////////////////////////////////////////////////////// + +static const char *assemble(uint32 pc, const char *text, uint32 *ins) { + // + // Skip opening space + // + while(*text && myisspace(*text)) text++; + + // + // E = D and T + // F = D and S + // G = T and S + // + + if(alphacompare(text, "nop" )) return assemblepatterns("" , pc, text + 3, ins, 0x00); + + if(alphacompare(text, "sll" )) return assemblepatterns("E,H/D,T,H", pc, text + 3, ins, 0x00); + if(alphacompare(text, "srl" )) return assemblepatterns("E,H/D,T,H", pc, text + 3, ins, 0x02); + if(alphacompare(text, "sra" )) return assemblepatterns("E,H/D,T,H", pc, text + 3, ins, 0x03); + if(alphacompare(text, "sllv" )) return assemblepatterns("E,S/D,T,S", pc, text + 4, ins, 0x04); + if(alphacompare(text, "srlv" )) return assemblepatterns("E,S/D,T,S", pc, text + 4, ins, 0x06); + if(alphacompare(text, "srav" )) return assemblepatterns("E,S/D,T,S", pc, text + 4, ins, 0x07); + + if(alphacompare(text, "jr" )) return assemblepatterns("S" , pc, text + 2, ins, 0x08); + if(alphacompare(text, "jalr" )) return assemblepatterns("S/D,S" , pc, text + 4, ins, 0x09|(0x1F<<11)); + + if(alphacompare(text, "syscall")) return assemblepatterns("" , pc, text + 7, ins, 0x0C); + + if(alphacompare(text, "mfhi" )) return assemblepatterns("D" , pc, text + 4, ins, 0x10); + if(alphacompare(text, "mthi" )) return assemblepatterns("D" , pc, text + 4, ins, 0x11); + if(alphacompare(text, "mflo" )) return assemblepatterns("D" , pc, text + 4, ins, 0x12); + if(alphacompare(text, "mtlo" )) return assemblepatterns("D" , pc, text + 4, ins, 0x13); + + if(alphacompare(text, "mult" )) return assemblepatterns("S,T" , pc, text + 4, ins, 0x18); + if(alphacompare(text, "multu" )) return assemblepatterns("S,T" , pc, text + 5, ins, 0x19); + if(alphacompare(text, "div" )) return assemblepatterns("S,T" , pc, text + 3, ins, 0x1A); + if(alphacompare(text, "divu" )) return assemblepatterns("S,T" , pc, text + 4, ins, 0x1B); + + if(alphacompare(text, "add" )) return assemblepatterns("F,T/D,S,T", pc, text + 3, ins, 0x20); + if(alphacompare(text, "addu" )) return assemblepatterns("F,T/D,S,T", pc, text + 4, ins, 0x21); + if(alphacompare(text, "sub" )) return assemblepatterns("F,T/D,S,T", pc, text + 3, ins, 0x22); + if(alphacompare(text, "subu" )) return assemblepatterns("F,T/D,S,T", pc, text + 4, ins, 0x23); + if(alphacompare(text, "and" )) return assemblepatterns("F,T/D,S,T", pc, text + 3, ins, 0x24); + if(alphacompare(text, "or" )) return assemblepatterns("F,T/D,S,T", pc, text + 2, ins, 0x25); + if(alphacompare(text, "xor" )) return assemblepatterns("F,T/D,S,T", pc, text + 3, ins, 0x26); + if(alphacompare(text, "nor" )) return assemblepatterns("F,T/D,S,T", pc, text + 3, ins, 0x27); + + if(alphacompare(text, "slt" )) return assemblepatterns("D,S,T" , pc, text + 3, ins, 0x2A); + if(alphacompare(text, "sltu" )) return assemblepatterns("D,S,T" , pc, text + 4, ins, 0x2B); + + if(alphacompare(text, "bltz" )) return assemblepatterns("S,B" , pc, text + 4, ins, (0x01<<26)|(0x00<<16)); + if(alphacompare(text, "bgez" )) return assemblepatterns("S,B" , pc, text + 4, ins, (0x01<<26)|(0x01<<16)); + if(alphacompare(text, "bltzal" )) return assemblepatterns("S,B" , pc, text + 6, ins, (0x01<<26)|(0x10<<16)); + if(alphacompare(text, "bgezal" )) return assemblepatterns("S,B" , pc, text + 6, ins, (0x01<<26)|(0x11<<16)); + + if(alphacompare(text, "j" )) return assemblepatterns("J" , pc, text + 1, ins, (0x02<<26)); + if(alphacompare(text, "jal" )) return assemblepatterns("J" , pc, text + 3, ins, (0x03<<26)); + + if(alphacompare(text, "beq" )) return assemblepatterns("S,T,B" , pc, text + 3, ins, (0x04<<26)); + if(alphacompare(text, "bne" )) return assemblepatterns("S,T,B" , pc, text + 3, ins, (0x05<<26)); + if(alphacompare(text, "beqz" )) return assemblepatterns("S,B" , pc, text + 4, ins, (0x04<<26)); + if(alphacompare(text, "bnez" )) return assemblepatterns("S,B" , pc, text + 4, ins, (0x05<<26)); + + if(alphacompare(text, "blez" )) return assemblepatterns("S,B" , pc, text + 4, ins, (0x06<<26)); + if(alphacompare(text, "bgtz" )) return assemblepatterns("S,B" , pc, text + 4, ins, (0x07<<26)); + + if(alphacompare(text, "addi" )) return assemblepatterns("G,I/T,S,I", pc, text + 4, ins, (0x08<<26)); + if(alphacompare(text, "addiu" )) return assemblepatterns("G,I/T,S,I", pc, text + 5, ins, (0x09<<26)); + if(alphacompare(text, "slti" )) return assemblepatterns("T,S,I" , pc, text + 4, ins, (0x0A<<26)); + if(alphacompare(text, "sltiu" )) return assemblepatterns("T,S,I" , pc, text + 5, ins, (0x0B<<26)); + + if(alphacompare(text, "andi" )) return assemblepatterns("G,I/T,S,I", pc, text + 4, ins, (0x0C<<26)); + if(alphacompare(text, "ori" )) return assemblepatterns("G,I/T,S,I", pc, text + 3, ins, (0x0D<<26)); + if(alphacompare(text, "xori" )) return assemblepatterns("G,I/T,S,I", pc, text + 4, ins, (0x0E<<26)); + if(alphacompare(text, "lui" )) return assemblepatterns("T,I" , pc, text + 3, ins, (0x0F<<26)); + + if(alphacompare(text, "mfc0" )) return assemblepatterns("T,C" , pc, text + 4, ins, (0x10<<26)|(0x00<<21)); + if(alphacompare(text, "mtc0" )) return assemblepatterns("T,C" , pc, text + 4, ins, (0x10<<26)|(0x04<<21)); + if(alphacompare(text, "rfe" )) return assemblepatterns("" , pc, text + 3, ins, (0x10<<26)|(0x10<<21)); + + if(alphacompare(text, "lb" )) return assemblepatterns("T,(S)/T,I(S)", pc, text + 2, ins, (uint32)(0x20<<26)); + if(alphacompare(text, "lh" )) return assemblepatterns("T,(S)/T,I(S)", pc, text + 2, ins, (uint32)(0x21<<26)); + if(alphacompare(text, "lw" )) return assemblepatterns("T,(S)/T,I(S)", pc, text + 2, ins, (uint32)(0x23<<26)); + if(alphacompare(text, "lbu" )) return assemblepatterns("T,(S)/T,I(S)", pc, text + 3, ins, (uint32)(0x24<<26)); + if(alphacompare(text, "lhu" )) return assemblepatterns("T,(S)/T,I(S)", pc, text + 3, ins, (uint32)(0x25<<26)); + if(alphacompare(text, "sb" )) return assemblepatterns("T,(S)/T,I(S)", pc, text + 2, ins, (uint32)(0x28<<26)); + if(alphacompare(text, "sh" )) return assemblepatterns("T,(S)/T,I(S)", pc, text + 2, ins, (uint32)(0x29<<26)); + if(alphacompare(text, "sw" )) return assemblepatterns("T,(S)/T,I(S)", pc, text + 2, ins, (uint32)(0x2B<<26)); + + // + // Friendly instructions like not, move, neg, negu, li + // "li" always expands to a signed addiu - not an ori. + // + if(alphacompare(text, "move" )) return assemblepatterns("D,T" , pc, text + 4, ins, 0x21); + if(alphacompare(text, "neg" )) return assemblepatterns("E/D,T", pc, text + 3, ins, 0x22); + if(alphacompare(text, "negu" )) return assemblepatterns("E/D,T", pc, text + 4, ins, 0x23); + if(alphacompare(text, "not" )) return assemblepatterns("E/D,T", pc, text + 3, ins, 0x27); + if(alphacompare(text, "li" )) return assemblepatterns("T,I" , pc, text + 2, ins, (0x09<<26)); + + return "Unknown instuction name"; +} + +///////////////////////////////////////////////////////////////////////////// +// +// Returns negative on error (and fills the error string buffer) +// Must be 256 bytes in the error string buffer +// +sint32 EMU_CALL r3000asm(uint32 pc, const char *text, uint32 *ins, char *errorstring) { + const char *complaint = assemble(pc, text, ins); + if(complaint) { + int i; + for(i = 0; i < 255 && complaint[i]; i++) errorstring[i] = complaint[i]; + errorstring[i] = 0; + return -1; + } + return 0; +} + +///////////////////////////////////////////////////////////////////////////// diff --git a/Frameworks/HighlyExperimental/HighlyExperimental/Core/r3000asm.h b/Frameworks/HighlyExperimental/HighlyExperimental/Core/r3000asm.h new file mode 100644 index 000000000..bc0f7b87c --- /dev/null +++ b/Frameworks/HighlyExperimental/HighlyExperimental/Core/r3000asm.h @@ -0,0 +1,29 @@ +///////////////////////////////////////////////////////////////////////////// +// +// r3000asm - R3000 quick assembler (no symbols, no macro instructions) +// +///////////////////////////////////////////////////////////////////////////// + +#ifndef __PSX_R3000ASM_H__ +#define __PSX_R3000ASM_H__ + +#include "emuconfig.h" + +#ifdef __cplusplus +extern "C" { +#endif + +///////////////////////////////////////////////////////////////////////////// +// +// Returns negative on error (and fills the error string buffer) +// Must be 256 bytes in the error string buffer +// +sint32 EMU_CALL r3000asm(uint32 pc, const char *text, uint32 *ins, char *errorstring); + +///////////////////////////////////////////////////////////////////////////// + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Frameworks/HighlyExperimental/HighlyExperimental/Core/r3000dis.c b/Frameworks/HighlyExperimental/HighlyExperimental/Core/r3000dis.c new file mode 100644 index 000000000..62420899f --- /dev/null +++ b/Frameworks/HighlyExperimental/HighlyExperimental/Core/r3000dis.c @@ -0,0 +1,265 @@ +///////////////////////////////////////////////////////////////////////////// +// +// r3000dis - R3000 disassembler +// +///////////////////////////////////////////////////////////////////////////// + +#ifndef EMU_COMPILE +#error "Hi I forgot to set EMU_COMPILE" +#endif + +#include "r3000dis.h" + +///////////////////////////////////////////////////////////////////////////// + +#define INS_S (uint32)((ins>>21)&0x1F) +#define INS_T (uint32)((ins>>16)&0x1F) +#define INS_D (uint32)((ins>>11)&0x1F) +#define INS_H (uint32)((ins>>6)&0x1F) +#define INS_I (uint32)(ins&0xFFFF) + +#define SIGNED16(x) ((sint32)(((sint16)(x)))) + +#define REL_I (pc+4+(((sint32)(SIGNED16(INS_I)))<<2)) +#define ABS_I ((pc&0xF0000000)|((ins<<2)&0x0FFFFFFC)) + +#define RICH_CODE_REGISTER ('R'-64) +#define RICH_CODE_ADDRESS ('A'-64) + +///////////////////////////////////////////////////////////////////////////// +// +// Returns negative on unknown instuction +// dest must have 256 bytes available +// +sint32 EMU_CALL r3000dis(char *dest, uint32 rich, uint32 pc, uint32 ins) { + sint32 delayslot = 0; + static const char *regname[32] = { + "$0" ,"$at","$v0","$v1","$a0","$a1","$a2","$a3", + "$t0","$t1","$t2","$t3","$t4","$t5","$t6","$t7", + "$s0","$s1","$s2","$s3","$s4","$s5","$s6","$s7", + "$t8","$t9","$k0","$k1","$gp","$sp","$fp","$ra" + }; + static const char *C0regname[32] = { + "C0_0","C0_1","C0_2","C0_3","C0_4","C0_5","C0_6","C0_7", + "C0_8","C0_9","C0_10","C0_11","C0_status","C0_cause","C0_epc","C0_prid", + "C0_16","C0_17","C0_18","C0_19","C0_20","C0_21","C0_22","C0_23", + "C0_24","C0_25","C0_26","C0_27","C0_28","C0_29","C0_30","C0_31" + }; + const char *fmt; + int j, col = 0; + if(ins < 0x04000000) { + switch(ins & 0x3F) { + case 0x00: + if(!ins) fmt = "nop"; goto ok; + if(INS_D==INS_T) fmt = "sll D,H"; goto ok; + if(!INS_H) fmt = "move D,T"; goto ok; + fmt = "sll D,T,H"; goto ok; + case 0x02: + if(INS_D==INS_T) fmt = "srl D,H"; goto ok; + if(!INS_H) fmt = "move D,T"; goto ok; + fmt = "srl D,T,H"; goto ok; + case 0x03: + if(INS_D==INS_T) fmt = "sra D,H"; goto ok; + if(!INS_H) fmt = "move D,T"; goto ok; + fmt = "sra D,T,H"; goto ok; + case 0x04: + if(INS_D==INS_T) fmt = "sllv D,S"; goto ok; + if(!INS_S) fmt = "move D,T"; goto ok; + fmt = "sllv D,T,S"; goto ok; + case 0x06: + if(INS_D==INS_T) fmt = "srlv D,S"; goto ok; + if(!INS_S) fmt = "move D,T"; goto ok; + fmt = "srlv D,T,S"; goto ok; + case 0x07: + if(INS_D==INS_T) fmt = "srav D,S"; goto ok; + if(!INS_S) fmt = "move D,T"; goto ok; + fmt = "srav D,T,S"; goto ok; + case 0x08: fmt = "jr S"; goto okdelayslot; + case 0x09: + if(INS_D==31) fmt = "jalr S"; goto okdelayslot; + fmt = "jalr D,S"; goto okdelayslot; + case 0x0C: fmt = "syscall"; goto ok; + case 0x10: fmt = "mfhi D"; goto ok; + case 0x11: fmt = "mthi S"; goto ok; + case 0x12: fmt = "mflo D"; goto ok; + case 0x13: fmt = "mtlo S"; goto ok; + case 0x18: fmt = "mult S,T"; goto ok; + case 0x19: fmt = "multu S,T"; goto ok; + case 0x1A: fmt = "div S,T"; goto ok; + case 0x1B: fmt = "divu S,T"; goto ok; + case 0x20: + if(INS_D==INS_S) fmt = "add D,T"; goto ok; + if(!INS_T) fmt = "move D,S"; goto ok; + if(!INS_S) fmt = "move D,T"; goto ok; + fmt = "add D,S,T"; goto ok; + case 0x21: + if(INS_D==INS_S) fmt = "addu D,T"; goto ok; + if(!INS_T) fmt = "move D,S"; goto ok; + if(!INS_S) fmt = "move D,T"; goto ok; + fmt = "addu D,S,T"; goto ok; + case 0x22: + if(INS_D==INS_S) fmt = "sub D,T"; goto ok; + if(!INS_T) fmt = "move D,S"; goto ok; + if(!INS_S) { + if(INS_D==INS_T) fmt = "neg D"; goto ok; + fmt = "neg D,T"; goto ok; + } + fmt = "sub D,S,T"; goto ok; + case 0x23: + if(INS_D==INS_S) fmt = "subu D,T"; goto ok; + if(!INS_T) fmt = "move D,S"; goto ok; + if(!INS_S) { + if(INS_D==INS_T) fmt = "negu D"; goto ok; + fmt = "negu D,T"; goto ok; + } + fmt = "subu D,S,T"; goto ok; + case 0x24: + if(INS_D==INS_S) fmt = "and D,T"; goto ok; + fmt = "and D,S,T"; goto ok; + case 0x25: + if(INS_D==INS_S) fmt = "or D,T"; goto ok; + if(!INS_T) fmt = "move D,S"; goto ok; + fmt = "or D,S,T"; goto ok; + case 0x26: + if(INS_D==INS_S) fmt = "xor D,T"; goto ok; + if(!INS_T) fmt = "move D,S"; goto ok; + fmt = "xor D,S,T"; goto ok; + case 0x27: + if(!INS_T) { + if(INS_D==INS_S) fmt = "not D"; goto ok; + fmt = "not D,S"; goto ok; + } else if(!INS_S) { + if(INS_D==INS_T) fmt = "not D"; goto ok; + fmt = "not D,T"; goto ok; + } else { + if(INS_D==INS_S) fmt = "nor D,T"; goto ok; + fmt = "nor D,S,T"; goto ok; + } + case 0x2A: fmt = "slt D,S,T"; goto ok; + case 0x2B: fmt = "sltu D,S,T"; goto ok; + default: goto invalid; + } + } else { + switch(ins >> 26) { + case 0x01: + switch(INS_T) { + case 0x00: fmt = "bltz S,B"; goto okdelayslot; + case 0x01: fmt = "bgez S,B"; goto okdelayslot; + case 0x10: fmt = "bltzal S,B"; goto okdelayslot; + case 0x11: fmt = "bgezal S,B"; goto okdelayslot; + default: goto invalid; + } + break; + case 0x02: fmt = "j J"; goto okdelayslot; + case 0x03: fmt = "jal J"; goto okdelayslot; + case 0x04: + if(INS_S==INS_T) fmt = "b B"; goto okdelayslot; + fmt = "beq S,T,B"; goto okdelayslot; + case 0x05: fmt = "bne S,T,B"; goto okdelayslot; + case 0x06: + if(!INS_S) fmt = "b B"; goto okdelayslot; + fmt = "blez S,B"; goto okdelayslot; + case 0x07: fmt = "bgtz S,B"; goto okdelayslot; + case 0x08: + if(INS_T==INS_S) fmt = "addi T,I"; goto ok; + if(!INS_S) fmt = "li T,I"; goto ok; + if(!INS_I) fmt = "move T,S"; goto ok; + fmt = "addi T,S,I"; goto ok; + case 0x09: + if(INS_T==INS_S) fmt = "addiu T,I"; goto ok; + if(!INS_S) fmt = "li T,I"; goto ok; + if(!INS_I) fmt = "move T,S"; goto ok; + fmt = "addiu T,S,I"; goto ok; + case 0x0A: fmt = "slti T,S,I"; goto ok; + case 0x0B: fmt = "sltiu T,S,I"; goto ok; + case 0x0C: + if(INS_T==INS_S) fmt = "andi T,I"; goto ok; + fmt = "andi T,S,I"; goto ok; + case 0x0D: + if(INS_T==INS_S) fmt = "ori T,I"; goto ok; + fmt = "ori T,S,I"; goto ok; + case 0x0E: + if(INS_T==INS_S) fmt = "xori T,I"; goto ok; + fmt = "xori T,S,I"; goto ok; + case 0x0F: fmt = "lui T,I"; goto ok; + case 0x10: + switch(INS_S) { + case 0x00: fmt = "mfc0 T,CD"; goto ok; + case 0x04: fmt = "mtc0 T,CD"; goto ok; + case 0x10: fmt = "rfe"; goto ok; + default: goto invalid; + } + break; + case 0x20: + if(!INS_I) fmt = "lb T,(S)"; goto ok; + fmt = "lb T,I(S)"; goto ok; + case 0x21: + if(!INS_I) fmt = "lh T,(S)"; goto ok; + fmt = "lh T,I(S)"; goto ok; + case 0x22: + if(!INS_I) fmt = "lwl T,(S)"; goto ok; + fmt = "lwl T,I(S)"; goto ok; + case 0x23: + if(!INS_I) fmt = "lw T,(S)"; goto ok; + fmt = "lw T,I(S)"; goto ok; + case 0x24: + if(!INS_I) fmt = "lbu T,(S)"; goto ok; + fmt = "lbu T,I(S)"; goto ok; + case 0x25: + if(!INS_I) fmt = "lhu T,(S)"; goto ok; + fmt = "lhu T,I(S)"; goto ok; + case 0x26: + if(!INS_I) fmt = "lwr T,(S)"; goto ok; + fmt = "lwr T,I(S)"; goto ok; + case 0x28: + if(!INS_I) fmt = "sb T,(S)"; goto ok; + fmt = "sb T,I(S)"; goto ok; + case 0x29: + if(!INS_I) fmt = "sh T,(S)"; goto ok; + fmt = "sh T,I(S)"; goto ok; + case 0x2A: + if(!INS_I) fmt = "swl T,(S)"; goto ok; + fmt = "swl T,I(S)"; goto ok; + case 0x2B: + if(!INS_I) fmt = "sw T,(S)"; goto ok; + fmt = "sw T,I(S)"; goto ok; + case 0x2E: + if(!INS_I) fmt = "swr T,(S)"; goto ok; + fmt = "swr T,I(S)"; goto ok; + default: goto invalid; + } + } +invalid: + *dest = 0; + return -1; +okdelayslot: + delayslot = 1; +ok: + for(; *fmt; fmt++) { + switch(*fmt) { + case 'S': if(rich) dest[col++] = RICH_CODE_REGISTER; strcpy(dest+col, regname[INS_S]); while(dest[col]) col++; break; + case 'T': if(rich) dest[col++] = RICH_CODE_REGISTER; strcpy(dest+col, regname[INS_T]); while(dest[col]) col++; break; + case 'D': if(rich) dest[col++] = RICH_CODE_REGISTER; strcpy(dest+col, regname[INS_D]); while(dest[col]) col++; break; + case 'H': sprintf(dest+col, "%d", INS_H); while(dest[col]) col++; break; + case 'I': sprintf(dest+col, "0x%04X", INS_I); while(dest[col]) col++; break; + case 'B': if(rich) dest[col++] = RICH_CODE_ADDRESS; sprintf(dest+col, "0x%08X", REL_I); while(dest[col]) col++; break; + case 'J': if(rich) dest[col++] = RICH_CODE_ADDRESS; sprintf(dest+col, "0x%08X", ABS_I); while(dest[col]) col++; break; + case 'C': + fmt++; + if(rich) dest[col++] = RICH_CODE_REGISTER; + j = 0; + switch(*fmt) { + case 'D': j = INS_D; break; + } + strcpy(dest+col, C0regname[j]); while(dest[col]) col++; + break; + case ' ': while(col < 6) dest[col++] = ' '; break; + case ',': dest[col++] = ','; dest[col++] = ' '; break; + default: dest[col++] = *fmt; break; + } + } + dest[col] = 0; + return delayslot ? 1 : 0; +} + +///////////////////////////////////////////////////////////////////////////// diff --git a/Frameworks/HighlyExperimental/HighlyExperimental/Core/r3000dis.h b/Frameworks/HighlyExperimental/HighlyExperimental/Core/r3000dis.h new file mode 100644 index 000000000..4732bdef0 --- /dev/null +++ b/Frameworks/HighlyExperimental/HighlyExperimental/Core/r3000dis.h @@ -0,0 +1,32 @@ +///////////////////////////////////////////////////////////////////////////// +// +// r3000dis - R3000 disassembler +// +///////////////////////////////////////////////////////////////////////////// + +#ifndef __PSX_R3000DIS_H__ +#define __PSX_R3000DIS_H__ + +#include "emuconfig.h" + +#ifdef __cplusplus +extern "C" { +#endif + +///////////////////////////////////////////////////////////////////////////// +// +// Returns: +// 0 on success +// 1 on success + there's a delay slot too +// negative on failure +// dest must have 256 bytes available +// +sint32 EMU_CALL r3000dis(char *dest, uint32 rich, uint32 pc, uint32 ins); + +///////////////////////////////////////////////////////////////////////////// + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Frameworks/HighlyExperimental/HighlyExperimental/Core/r3000predict.txt b/Frameworks/HighlyExperimental/HighlyExperimental/Core/r3000predict.txt new file mode 100644 index 000000000..a0b48b92a --- /dev/null +++ b/Frameworks/HighlyExperimental/HighlyExperimental/Core/r3000predict.txt @@ -0,0 +1,2004 @@ +// PSFWorkArea.cpp : implementation file +// + +#include "stdafx.h" +#include "PSFLab.h" +#include "PSFWorkArea.h" + +#include "../Emu/emu.h" + +#include "CodeView.h" +#include "MemoryView.h" +#include "EventView.h" + +#include "ImportBinaryDlg.h" +#include "BreakpointsDlg.h" +#include "ExeSettingsDlg.h" +#include "RunToSpecificLineDlg.h" +#include "StateSlotDlg.h" +#include "TagDlg.h" +#include "OptimizeDlg.h" + +#include "WaveOutput.h" + +#ifdef _DEBUG +#define new DEBUG_NEW +#undef THIS_FILE +static char THIS_FILE[] = __FILE__; +#endif + +#define R3000CLASS(x) (R3000_REG_##x) + +static const int anRegisterHWID[PSFWORKAREA_REG_N] = { + R3000CLASS(GEN)+ 0, R3000CLASS(GEN)+ 1, R3000CLASS(GEN)+ 2, R3000CLASS(GEN)+ 3, + R3000CLASS(GEN)+ 4, R3000CLASS(GEN)+ 5, R3000CLASS(GEN)+ 6, R3000CLASS(GEN)+ 7, + R3000CLASS(GEN)+ 8, R3000CLASS(GEN)+ 9, R3000CLASS(GEN)+10, R3000CLASS(GEN)+11, + R3000CLASS(GEN)+12, R3000CLASS(GEN)+13, R3000CLASS(GEN)+14, R3000CLASS(GEN)+15, + R3000CLASS(GEN)+16, R3000CLASS(GEN)+17, R3000CLASS(GEN)+18, R3000CLASS(GEN)+19, + R3000CLASS(GEN)+20, R3000CLASS(GEN)+21, R3000CLASS(GEN)+22, R3000CLASS(GEN)+23, + R3000CLASS(GEN)+24, R3000CLASS(GEN)+25, R3000CLASS(GEN)+26, R3000CLASS(GEN)+27, + R3000CLASS(GEN)+28, R3000CLASS(GEN)+29, R3000CLASS(GEN)+30, R3000CLASS(GEN)+31, + + R3000CLASS(C0) + 0, R3000CLASS(C0) + 1, R3000CLASS(C0) + 2, R3000CLASS(C0) + 3, + R3000CLASS(C0) + 4, R3000CLASS(C0) + 5, R3000CLASS(C0) + 6, R3000CLASS(C0) + 7, + R3000CLASS(C0) + 8, R3000CLASS(C0) + 9, R3000CLASS(C0) +10, R3000CLASS(C0) +11, + R3000CLASS(C0) +12, R3000CLASS(C0) +13, R3000CLASS(C0) +14, R3000CLASS(C0) +15, + R3000CLASS(C0) +16, R3000CLASS(C0) +17, R3000CLASS(C0) +18, R3000CLASS(C0) +19, + R3000CLASS(C0) +20, R3000CLASS(C0) +21, R3000CLASS(C0) +22, R3000CLASS(C0) +23, + R3000CLASS(C0) +24, R3000CLASS(C0) +25, R3000CLASS(C0) +26, R3000CLASS(C0) +27, + R3000CLASS(C0) +28, R3000CLASS(C0) +29, R3000CLASS(C0) +30, R3000CLASS(C0) +31, + + R3000CLASS(PC), + R3000CLASS(HI), + R3000CLASS(LO), + + R3000CLASS(CI) +}; + +extern "C" void CPSFWorkArea__console_out( + void *context, + char c +) { + ((CPSFWorkArea*)context)->console.AddChar(c); +// char asdf[2]; +// asdf[0] = c; +// asdf[1] = 0; +// OutputDebugString(asdf); +} + +extern "C" sint32 CPSFWorkArea__readfile_cb( + void *context, + const char *path, + sint32 offset, + char *buffer, + sint32 length +) { + int r; + char fool[1000]; +//return -1; + +//sprintf(fool,"[readfile: %s(%d) %d]",path,offset,length);OutputDebugString(fool); + + + if(length < 0) return -1; + if(offset < 0) return -1; + strncpy(fool, + (LPCTSTR)( ((CPSFLabApp*)(AfxGetApp()))->m_strPSF2Path ), + +//"C:/Corlett", +//((CPSFWorkArea*)context)->m_sPSF2Path, + + sizeof(fool) + ); + fool[sizeof(fool)-1] = 0; + int l =strlen(fool); + while(l>0) { + char c=fool[l-1]; + if(c=='/'||c=='\\'||c==':'){ + fool[--l]=0; + continue; + } + break; + } + l = sizeof(fool)-strlen(fool); + strncpy(fool+strlen(fool),path,l); + fool[sizeof(fool)-1] = 0; + + + FILE *f = fopen(fool, "rb"); + if(!f) return -1; + if(!length) { int l; fseek(f,0,SEEK_END);l=ftell(f);fclose(f); return l; } + fseek(f,offset,SEEK_SET); + r = fread(buffer, 1, length, f); + fclose(f); + + + +//sprintf(fool,"(returned %d)",r);OutputDebugString(fool);OutputDebugString("\n"); + + + + return r; +} + +///////////////////////////////////////////////////////////////////////////// +// CPSFWorkArea + +IMPLEMENT_DYNCREATE(CPSFWorkArea, CDocument) + +CPSFWorkArea::CPSFWorkArea() +{ + /* + ** Initialize state pointers + */ + m_pStateDebug = NULL; + m_pStatePlay = NULL; + m_nVersion = 1; + + /* + ** Initialize thread information + */ + m_pDebugThread = NULL; + m_pPlayThread = NULL; + m_bRunning = FALSE; + m_bPlaying = FALSE; + + /* + ** Initialize saved state system + */ + memset(m_apSavedStates, 0, sizeof(m_apSavedStates)); + m_nCurrentStateSlot = 0; + + /* + ** Allocate debug state - this is always here + */ + m_pStateDebug = malloc(emu_get_state_size(m_nVersion)); + ASSERT(m_pStateDebug); + /* + ** Initialize the state just to ensure no problems + */ + emu_clear_state(m_pStateDebug, m_nVersion); + emu_set_readfile(m_pStateDebug, CPSFWorkArea__readfile_cb, this); + emu_set_console_out(m_pStateDebug, CPSFWorkArea__console_out, this); + + +// strcpy(m_sPSF2Path, + // (((CPSFLabApp*)(AfxGetApp()))->m_sPSF2Path) + // ); +} + +BOOL CPSFWorkArea::OnNewDocument() +{ + TRACE("CPSFWorkArea::OnNewDocument()\n"); + if(IsModified()) { + TRACE("Creating a new document over an existing modified one\n"); +// MessageBox(NULL,"trying to do a file new on a modified thingy\n",NULL,MB_OK); +// return FALSE; + } + + DeleteContents(); + + int nDesiredVersion = ((CPSFLabApp*)(::AfxGetApp()))->m_nNewPSFVersion; + if(m_nVersion != nDesiredVersion) { + m_nVersion = nDesiredVersion; + if(m_pStateDebug) { + free(m_pStateDebug); + m_pStateDebug = NULL; + } + m_pStateDebug = malloc(emu_get_state_size(m_nVersion)); + emu_clear_state(m_pStateDebug, m_nVersion); + emu_set_readfile(m_pStateDebug, CPSFWorkArea__readfile_cb, this); + emu_set_console_out(m_pStateDebug, CPSFWorkArea__console_out, this); + +// strcpy(m_sPSF2Path, +// (((CPSFLabApp*)(AfxGetApp()))->m_sPSF2Path) +// ); + + DeleteContents(); + } + + m_strPathName.Empty(); + SetModifiedFlag(FALSE); + + /* + ** Restart debugger + */ + DebugRestart(); + RegisterMonitor(); + + UpdateAllViews(NULL); + + return TRUE; +} + +CPSFWorkArea::~CPSFWorkArea() +{ + KillDebugThreadAndBlock(); + KillPlayThreadAndBlock(); + + ClearAllSavedStates(); + + if(m_pStateDebug) free(m_pStateDebug); + if(m_pStatePlay) free(m_pStatePlay); +} + + +BEGIN_MESSAGE_MAP(CPSFWorkArea, CDocument) + //{{AFX_MSG_MAP(CPSFWorkArea) + ON_UPDATE_COMMAND_UI(ID_DEBUG_GO, OnUpdateDebugGo) + ON_COMMAND(ID_DEBUG_GO, OnDebugGo) + ON_UPDATE_COMMAND_UI(ID_DEBUG_BREAK, OnUpdateDebugBreak) + ON_UPDATE_COMMAND_UI(ID_DEBUG_PLAY, OnUpdateDebugPlay) + ON_UPDATE_COMMAND_UI(ID_DEBUG_STOP, OnUpdateDebugStop) + ON_UPDATE_COMMAND_UI(ID_DEBUG_PAUSE, OnUpdateDebugPause) + ON_UPDATE_COMMAND_UI(ID_DEBUG_STEPINTO, OnUpdateDebugStepinto) + ON_UPDATE_COMMAND_UI(ID_DEBUG_STEPOUT, OnUpdateDebugStepout) + ON_UPDATE_COMMAND_UI(ID_DEBUG_STEPOVER, OnUpdateDebugStepover) + ON_COMMAND(ID_DEBUG_PLAY, OnDebugPlay) + ON_COMMAND(ID_DEBUG_PAUSE, OnDebugPause) + ON_COMMAND(ID_DEBUG_STOP, OnDebugStop) + ON_COMMAND(ID_DEBUG_BREAK, OnDebugBreak) + ON_UPDATE_COMMAND_UI(ID_DEBUG_RESTART, OnUpdateDebugRestart) + ON_COMMAND(ID_DEBUG_RESTART, OnDebugRestart) + ON_COMMAND(ID_DEBUG_STEPINTO, OnDebugStepinto) + ON_COMMAND(ID_DEBUG_STEPOUT, OnDebugStepout) + ON_COMMAND(ID_DEBUG_STEPOVER, OnDebugStepover) + ON_UPDATE_COMMAND_UI(ID_DEBUG_LOADSTATE, OnUpdateDebugLoadstate) + ON_COMMAND(ID_DEBUG_LOADSTATE, OnDebugLoadstate) + ON_UPDATE_COMMAND_UI(ID_DEBUG_SAVESTATE, OnUpdateDebugSavestate) + ON_COMMAND(ID_DEBUG_SAVESTATE, OnDebugSavestate) + ON_COMMAND(ID_FILE_IMPORTBINARY, OnFileImportbinary) + ON_UPDATE_COMMAND_UI(ID_FILE_IMPORTBINARY, OnUpdateFileImportbinary) + ON_UPDATE_COMMAND_UI(ID_DEBUG_RUNTOINT, OnUpdateDebugRuntoint) + ON_UPDATE_COMMAND_UI(ID_EDIT_BREAKPOINTS, OnUpdateEditBreakpoints) + ON_COMMAND(ID_EDIT_BREAKPOINTS, OnEditBreakpoints) + ON_UPDATE_COMMAND_UI(ID_EDIT_EXESETTINGS, OnUpdateEditExesettings) + ON_COMMAND(ID_EDIT_EXESETTINGS, OnEditExesettings) + ON_COMMAND(ID_DEBUG_EXECUTIONSTOPPED, OnDebugExecutionstopped) + ON_UPDATE_COMMAND_UI(ID_DEBUG_SPECIFICLINE, OnUpdateDebugSpecificline) + ON_COMMAND(ID_DEBUG_SPECIFICLINE, OnDebugSpecificline) + ON_COMMAND(ID_DEBUG_RUNTOINT, OnDebugRuntoint) + ON_COMMAND(ID_DEBUG_SELECTSLOT, OnDebugSelectslot) + ON_COMMAND(ID_EDIT_TAG, OnEditTag) + ON_COMMAND(ID_FILE_SAVEAS, OnFileSaveas) + ON_COMMAND(ID_FILE_IMPORTEXE, OnFileImportexe) + ON_UPDATE_COMMAND_UI(ID_FILE_IMPORTEXE, OnUpdateFileImportexe) + ON_COMMAND(ID_FILE_EXPORTEXE, OnFileExportexe) + ON_COMMAND(ID_FILE_FONDUE, OnFileFondue) + ON_UPDATE_COMMAND_UI(ID_EDIT_OPTIMIZE, OnUpdateEditOptimize) + ON_COMMAND(ID_EDIT_OPTIMIZE, OnEditOptimize) + ON_COMMAND(ID_FILE_EXPORTBIOSAREA, OnFileExportbiosarea) + ON_UPDATE_COMMAND_UI(ID_FILE_SAVE, OnUpdateFileSave) + ON_UPDATE_COMMAND_UI(ID_FILE_SAVEAS, OnUpdateFileSaveas) + ON_UPDATE_COMMAND_UI(ID_EDIT_TAG, OnUpdateEditTag) + ON_UPDATE_COMMAND_UI(ID_FILE_EXPORTEXE, OnUpdateFileExportexe) + //}}AFX_MSG_MAP +END_MESSAGE_MAP() + +///////////////////////////////////////////////////////////////////////////// +// CPSFWorkArea diagnostics + +#ifdef _DEBUG +void CPSFWorkArea::AssertValid() const +{ + CDocument::AssertValid(); +} + +void CPSFWorkArea::Dump(CDumpContext& dc) const +{ + CDocument::Dump(dc); +} +#endif //_DEBUG + +///////////////////////////////////////////////////////////////////////////// +// CPSFWorkArea serialization + +void CPSFWorkArea::Serialize(CArchive& ar) +{ + if (ar.IsStoring()) + { + // TODO: add storing code here + } + else + { + // TODO: add loading code here + } +} + +///////////////////////////////////////////////////////////////////////////// +// CPSFWorkArea commands + +DWORD CPSFWorkArea::PeekWord(DWORD dwAddress) const +{ + ASSERT(m_pStateDebug); + return iop_getword(emu_get_iop_state(m_pStateDebug), dwAddress); +} + +BOOL CPSFWorkArea::IsWordPatched(DWORD dwAddress) const +{ + int nEXEIndex = AddressToEXEIndex(dwAddress); + if(nEXEIndex < 0) return FALSE; + return ((m_adwPatchMap[nEXEIndex / 32] >> (nEXEIndex & 31)) & 1); +} + +DWORD CPSFWorkArea::GetPatchWord(DWORD dwAddress) const +{ + int nEXEIndex = AddressToEXEIndex(dwAddress); + if(nEXEIndex < 0) return 0; + return m_adwPatchData[nEXEIndex]; +} + +void CPSFWorkArea::SetPatchWord(DWORD dwAddress, DWORD dwValue) +{ + if(m_nVersion == 1) SetModifiedFlag(); + + /* + ** Copy the change to the current debug state too + */ + if(m_pStateDebug) { + iop_setword(emu_get_iop_state(m_pStateDebug), dwAddress, dwValue); + } + + if(m_nVersion == 1) { + int nEXEIndex = AddressToEXEIndex(dwAddress); + if(nEXEIndex >= 0) { + m_adwPatchMap[nEXEIndex / 32] |= (1 << (nEXEIndex & 31)); + m_adwPatchData[nEXEIndex] = dwValue; + } + } +} + +int CPSFWorkArea::AddressToEXEIndex(DWORD dwAddress) const +{ + dwAddress &= 0x1FFFFFFC; + if(dwAddress >= 0x1F000000) return -1; + dwAddress &= 0x1FFFFC; + if(dwAddress < 0x10000) return -1; + return (dwAddress - 0x10000) / 4; +} + +DWORD CPSFWorkArea::GetPC() const +{ + ASSERT(m_pStateDebug); + return r3000_getreg(iop_get_r3000_state(emu_get_iop_state(m_pStateDebug)), R3000CLASS(PC)); +} + +void CPSFWorkArea::DeletePatchWord(DWORD dwAddress) +{ + int nWordIndex = AddressToEXEIndex(dwAddress); + if(nWordIndex < 0) return; + // If it wasn't patched to begin with, don't do anything + if(!(m_adwPatchMap[nWordIndex / 32] & (1 << (nWordIndex & 31)))) return; + m_adwPatchMap[nWordIndex / 32] &= ~(1 << (nWordIndex & 31)); + /* + ** Copy the change to the current debug state too + */ + ASSERT(m_pStateDebug); + iop_setword(emu_get_iop_state(m_pStateDebug), dwAddress, m_adwEXEData[nWordIndex]); + SetModifiedFlag(); +} + +int CPSFWorkArea::AddressToBreakpointIndex(DWORD dwAddress) const +{ + dwAddress &= 0x1FFFFFFC; + if(dwAddress < 0x1F000000) return ((dwAddress & 0x1FFFFC) / 4); + if(dwAddress >= 0x1FC00000) return ((dwAddress & 0x7FFFC) / 4) + 0x80000; + return -1; +} + +BOOL CPSFWorkArea::IsBreakpointOnExecute(DWORD dwAddress) const +{ + int nWordIndex = AddressToBreakpointIndex(dwAddress); + if(nWordIndex < 0) return FALSE; + return (m_adwBreakpointMapExecute[nWordIndex / 32] >> (nWordIndex & 31)) & 1; +} + +void CPSFWorkArea::SetBreakpointOnExecute(DWORD dwAddress, BOOL bBreak) +{ + int nWordIndex = AddressToBreakpointIndex(dwAddress); + if(nWordIndex < 0) return; + if(bBreak) { + m_adwBreakpointMapExecute[nWordIndex / 32] |= (1 << (nWordIndex & 31)); + } else { + m_adwBreakpointMapExecute[nWordIndex / 32] &= ~(1 << (nWordIndex & 31)); + } +} + +BOOL CPSFWorkArea::IsBreakpointOnRead(DWORD dwAddress) const +{ + int nWordIndex = AddressToBreakpointIndex(dwAddress); + if(nWordIndex < 0) return FALSE; + return (m_adwBreakpointMapRead[nWordIndex / 32] >> (nWordIndex & 31)) & 1; +} + +void CPSFWorkArea::SetBreakpointOnRead(DWORD dwAddress, BOOL bBreak) +{ + int nWordIndex = AddressToBreakpointIndex(dwAddress); + if(nWordIndex < 0) return; + if(bBreak) { + m_adwBreakpointMapRead[nWordIndex / 32] |= (1 << (nWordIndex & 31)); + } else { + m_adwBreakpointMapRead[nWordIndex / 32] &= ~(1 << (nWordIndex & 31)); + } +} + +BOOL CPSFWorkArea::IsBreakpointOnWrite(DWORD dwAddress) const +{ + int nWordIndex = AddressToBreakpointIndex(dwAddress); + if(nWordIndex < 0) return FALSE; + return (m_adwBreakpointMapWrite[nWordIndex / 32] >> (nWordIndex & 31)) & 1; +} + +void CPSFWorkArea::SetBreakpointOnWrite(DWORD dwAddress, BOOL bBreak) +{ + int nWordIndex = AddressToBreakpointIndex(dwAddress); + if(nWordIndex < 0) return; + if(bBreak) { + m_adwBreakpointMapWrite[nWordIndex / 32] |= (1 << (nWordIndex & 31)); + } else { + m_adwBreakpointMapWrite[nWordIndex / 32] &= ~(1 << (nWordIndex & 31)); + } +} + +CEventLog* CPSFWorkArea::GetEventLog() +{ + return &m_eventlog; +} + +void CPSFWorkArea::OnUpdateDebugGo (CCmdUI* pCmdUI) { pCmdUI->Enable(!IsRunning()); } +void CPSFWorkArea::OnUpdateDebugRestart(CCmdUI* pCmdUI) { pCmdUI->Enable(!IsRunning()); } +void CPSFWorkArea::OnUpdateDebugBreak (CCmdUI* pCmdUI) { pCmdUI->Enable( IsRunning()); } + +void CPSFWorkArea::OnUpdateDebugStepinto (CCmdUI* pCmdUI) { pCmdUI->Enable(!IsRunning()); } +void CPSFWorkArea::OnUpdateDebugStepout (CCmdUI* pCmdUI) { pCmdUI->Enable(!IsRunning()); } +void CPSFWorkArea::OnUpdateDebugStepover (CCmdUI* pCmdUI) { pCmdUI->Enable(!IsRunning()); } + +void CPSFWorkArea::OnUpdateDebugPlay (CCmdUI* pCmdUI) { pCmdUI->Enable(!IsPlaying()); } +void CPSFWorkArea::OnUpdateDebugPause(CCmdUI* pCmdUI) { pCmdUI->Enable( IsPlaying()); } +void CPSFWorkArea::OnUpdateDebugStop (CCmdUI* pCmdUI) { pCmdUI->Enable( IsPlaying()); } + +void CPSFWorkArea::OnDebugGo() +{ + KillDebugThreadAndBlock(); + m_nDebugCommand = ID_DEBUG_GO; + StartDebugThreadAndBlock(); + UpdateAllViews(NULL); +} + + +void CPSFWorkArea::OnDebugPlay() { + PlayStart(); +} + +void CPSFWorkArea::OnDebugPause() { + if(IsPlayPaused()) { + PlayUnpause(); + } else { + PlayPause(); + } +} + +void CPSFWorkArea::OnDebugStop() +{ + PlayStop(); +} + +void CPSFWorkArea::OnDebugBreak() +{ + KillDebugThreadAndBlock(); + OnDebugExecutionstopped(); + +//FILE*f=fopen("statedump","wb"); +//if(f){ +//fwrite(m_pStateDebug,1,emu_get_state_size(2),f); +//fclose(f); +//} + +} + +void CPSFWorkArea::OnDebugRestart() +{ + KillDebugThreadAndBlock(); + DebugRestart(); + UpdateAllViews(NULL); +} + +void CPSFWorkArea::OnDebugStepinto() +{ + KillDebugThreadAndBlock(); + m_nDebugCommand = ID_DEBUG_STEPINTO; + StartDebugThreadAndBlock(); + UpdateAllViews(NULL); +} + +void CPSFWorkArea::OnDebugStepout() +{ + KillDebugThreadAndBlock(); + m_nDebugCommand = ID_DEBUG_STEPOUT; + StartDebugThreadAndBlock(); + UpdateAllViews(NULL); +} + +void CPSFWorkArea::OnDebugStepover() +{ + KillDebugThreadAndBlock(); + m_nDebugCommand = ID_DEBUG_STEPOVER; + StartDebugThreadAndBlock(); + UpdateAllViews(NULL); +} + +void CPSFWorkArea::OnUpdateDebugLoadstate(CCmdUI* pCmdUI) +{ + ASSERT(m_nCurrentStateSlot >= 0 && m_nCurrentStateSlot <= 9); + if(IsRunning()) { pCmdUI->Enable(FALSE); return; } + if(m_apSavedStates[m_nCurrentStateSlot]) { + pCmdUI->Enable(TRUE); + } else { + pCmdUI->Enable(FALSE); + } +} + +void CPSFWorkArea::OnDebugLoadstate() +{ + KillDebugThreadAndBlock(); + ASSERT(m_nCurrentStateSlot >= 0 && m_nCurrentStateSlot <= 9); + LoadDebugState(m_nCurrentStateSlot); + + CodeJumpTo(r3000_getreg(iop_get_r3000_state(emu_get_iop_state(m_pStateDebug)), R3000CLASS(PC))); + + UpdateAllViews(FALSE); +} + +void CPSFWorkArea::OnUpdateDebugSavestate(CCmdUI* pCmdUI) { pCmdUI->Enable(!IsRunning()); } + +void CPSFWorkArea::OnDebugSavestate() +{ + KillDebugThreadAndBlock(); + ASSERT(m_nCurrentStateSlot >= 0 && m_nCurrentStateSlot <= 9); + SaveDebugState(m_nCurrentStateSlot); +} + +void CPSFWorkArea::PlayStop() +{ + KillPlayThreadAndBlock(); + /* + ** Free memory used by play state + */ + if(m_pStatePlay) { + free(m_pStatePlay); + m_pStatePlay = NULL; + } +} + +void CPSFWorkArea::DebugRestart() +{ + ASSERT(m_pStateDebug); + /* + ** Initialize the state + */ + emu_clear_state(m_pStateDebug, m_nVersion); + emu_set_readfile(m_pStateDebug, CPSFWorkArea__readfile_cb, this); + emu_set_console_out(m_pStateDebug, CPSFWorkArea__console_out, this); + +// strcpy(m_sPSF2Path, +// (((CPSFLabApp*)(AfxGetApp()))->m_sPSF2Path) +// ); + + if(m_nVersion == 1) { + /* + ** Load EXE data and apply patches + */ + LoadEXEToState(m_pStateDebug); + ApplyPatchesToState(m_pStateDebug); + } + + /* + ** Update the code view with the place where we are + */ +// CodeJumpTo(m_dwEXEStartPC); + CodeJumpTo(GetPC()); + + /* + ** Clear the event log and call stack + */ + m_eventlog.Clear(); + m_callstack.Clear(); + /* + ** Reset the register change monitor + */ + RegisterMonitorReset(); +} + +CView* CPSFWorkArea::FindViewOfClass(CRuntimeClass *pClass) +{ + POSITION p = GetFirstViewPosition(); + CView *v; + for(;;) { + v = GetNextView(p); + if(!v) break; + if(v->IsKindOf(pClass)) break; + } + ASSERT(v); + return v; +} + +DWORD CPSFWorkArea::GetRegister(int nRegisterIndex) +{ + ASSERT(m_pStateDebug); + ASSERT(nRegisterIndex >= 0 && nRegisterIndex < PSFWORKAREA_REG_N); + return r3000_getreg(iop_get_r3000_state(emu_get_iop_state(m_pStateDebug)), anRegisterHWID[nRegisterIndex]); +} + +void CPSFWorkArea::RegisterMonitor() +{ + for(int i = 0; i < PSFWORKAREA_REG_N; i++) { + if(m_anRegisterChangeTimeout[i]) m_anRegisterChangeTimeout[i]--; + DWORD r = GetRegister(i); + if(r != m_adwRegisterPrevious[i]) { + m_adwRegisterPrevious[i] = r; + m_anRegisterChangeTimeout[i] = PSFWORKAREA_REGISTER_CHANGE_TIMEOUT; + } + } +} + +void CPSFWorkArea::RegisterMonitorReset() +{ + for(int i = 0; i < PSFWORKAREA_REG_N; i++) { + m_adwRegisterPrevious[i] = GetRegister(i); + m_anRegisterChangeTimeout[i] = 0; + } +} + +BOOL CPSFWorkArea::RegisterChangedRecently(int nRegisterIndex) const +{ + ASSERT(nRegisterIndex >= 0 && nRegisterIndex < PSFWORKAREA_REG_N); + return m_anRegisterChangeTimeout[nRegisterIndex] ? TRUE : FALSE; +} + +CCallStack* CPSFWorkArea::GetCallStack() +{ + return &m_callstack; +} + +BOOL CPSFWorkArea::OnOpenDocument(LPCTSTR lpszPathName) +{ + TRACE("CPSFWorkArea::OnOpenDocument(%s)\n", lpszPathName); + if(IsModified()) { + TRACE("Opening a new document over an existing modified one\n"); + } + + // can only open psf + SetVersion(1); + + TRACE("set version to %d\n", m_nVersion); + +// LPBYTE lpEXE = new BYTE[0x200000]; + + BOOL b; + + CPSF psf; + CPSXEXE exe; + + /* + ** Load the EXE into an EXE buffer which we have temporarily allocated + ** (if there's an error here, it's recoverable) + */ + b = psf.ReadFromFile(lpszPathName, CPSF::PSF_FILE_ALL, TRUE); + if(!b) { + CString s; + s.Format(_T("%s\n%s"), lpszPathName, (LPCTSTR)psf.GetLastError()); + AfxGetMainWnd()->MessageBox(s, _T("Open"), MB_OK|MB_ICONHAND); + return FALSE; + } + b = exe.ReadFromPSF(psf, TRUE); + if(!b) { + CString s; + s.Format(_T("%s\n%s"), lpszPathName, (LPCTSTR)exe.GetLastError()); + AfxGetMainWnd()->MessageBox(s, _T("Open"), MB_OK|MB_ICONHAND); + return FALSE; + } + + /* + ** Clear the document contents + */ + DeleteContents(); + SetPathName(lpszPathName); + SetModifiedFlag(FALSE); + + /* + ** "Import" the EXE + */ + ImportEXEFromBuffer( + exe.GetEXEBuffer(), + exe.GetEXESize() + ); + + /* + ** Silly reminder to myself that this hasn't been unicode-proofed yet + */ + ASSERT(sizeof(TCHAR)==1); + + /* + ** Attempt to load the tag + */ + m_tag.ReadFromPSF(psf, FALSE); + + /* + ** Restart debugger + */ + DebugRestart(); + RegisterMonitor(); + + UpdateAllViews(NULL); + + TRACE("got here, version is %d\n",m_nVersion); + + return TRUE; +} + +BOOL CPSFWorkArea::OnSaveDocument(LPCTSTR lpszPathName) +{ + TRACE("CPSFWorkArea::OnSaveDocument(%s)\n", lpszPathName); + + CWaitCursor cwc; + + /* + ** Silly reminder to myself that this hasn't been unicode-proofed yet + */ + ASSERT(sizeof(TCHAR)==1); + + /* + ** Create the EXE data + */ + CByteArray aEXE; + aEXE.SetSize(0x200000); + DWORD dwEXELength = ExportEXEToBuffer(aEXE.GetData()); + aEXE.SetSize(dwEXELength); + + /* + ** Save the EXE data and tag to a PSF file + */ + + CPSF psf; + + psf.SetVersion(0x01); + psf.SetReservedSize(0); + UINT uMethod = ((CPSFLabApp*)(::AfxGetApp()))->GetCompressionMethodNumber(); + BOOL b; + b = psf.SetProgramData(aEXE.GetData(), aEXE.GetSize(), uMethod); + if(!b) { + CString s; + s.Format(_T("%s\n%s"), lpszPathName, (LPCTSTR)psf.GetLastError()); + AfxGetMainWnd()->MessageBox(s, _T("Save"), MB_OK|MB_ICONHAND); + return FALSE; + } + m_tag.WriteToPSF(psf, FALSE); + + b = psf.WriteToFile(lpszPathName, CPSF::PSF_FILE_ALL, TRUE); + if(!b) { + CString s; + s.Format(_T("%s\n%s"), lpszPathName, (LPCTSTR)psf.GetLastError()); + AfxGetMainWnd()->MessageBox(s, _T("Save"), MB_OK|MB_ICONHAND); + return FALSE; + } + + /* + ** Success + ** Document is no longer modified + ** (and may have a new pathname now) + */ + SetPathName(lpszPathName); + SetModifiedFlag(FALSE); + + UpdateAllViews(NULL); + return TRUE; +} + +void CPSFWorkArea::ClearWorkArea() +{ + /* + ** Clear original EXE data + */ + memset(m_adwEXEData, 0, sizeof(m_adwEXEData)); + m_dwEXEStartAddress = 0x80010000; + m_dwEXEByteLength = 0; + m_dwEXEStartPC = 0x80010000; + m_dwEXEStartSP = 0x801FFFF0; + memset(m_EXEHeader, 0, 0x800); + memcpy(m_EXEHeader, "PS-X EXE", 8); + memcpy(m_EXEHeader+0x4C, "Sony Computer Entertainment Inc. for North America area", 0x37); + + /* + ** Clear patch/breakpoint info + */ + memset(m_adwPatchMap, 0, sizeof(m_adwPatchMap)); + memset(m_adwBreakpointMapRead, 0, sizeof(m_adwBreakpointMapRead)); + memset(m_adwBreakpointMapWrite, 0, sizeof(m_adwBreakpointMapWrite)); + memset(m_adwBreakpointMapExecute, 0, sizeof(m_adwBreakpointMapExecute)); + + // clear register change monitoring + memset(m_adwRegisterPrevious, 0, sizeof(m_adwRegisterPrevious)); + memset(m_anRegisterChangeTimeout, 0, sizeof(m_anRegisterChangeTimeout)); + + // clear console + console.Clear(); +} + +/***************************************************************************/ +/* +** Debugging thread / debug core +*/ +UINT AFX_CDECL CPSFWorkArea__DebugThread(LPVOID lpParam) { + CPSFWorkArea *me = (CPSFWorkArea*)lpParam; + ASSERT(me); + /* + ** Signal thread start + */ + me->m_csDebug.Lock(); + me->m_evDebug.SetEvent(); + /* + ** Initial preparations + */ + ASSERT(me->m_pStateDebug); + me->m_bDebugBreakpointReadFlag = FALSE; + me->m_bDebugBreakpointWriteFlag = FALSE; + me->m_bDebugBreakpointExecuteFlag = FALSE; + me->m_bDebugErrorFlag = FALSE; + + me->m_bDebugBreakOnWeed = TRUE; + me->m_bDebugWeedFlag = FALSE; + + /* + ** Initial call stack caching (size, top PC/SP) + */ + int nInitialCallStackSize = me->m_callstack.GetSize(); + int nCallStackSize = nInitialCallStackSize; + /* + ** Clear the hardware event buffer + */ + iop_clear_events(emu_get_iop_state(me->m_pStateDebug)); + /* + ** Debug core loop + */ + while(!me->m_dwDebugKillFlag) { + DWORD dwIns; + #define INS_S ((DWORD)((dwIns>>21)&0x1F)) + #define INS_T ((DWORD)((dwIns>>16)&0x1F)) + #define INS_D ((DWORD)((dwIns>>11)&0x1F)) + #define INS_H ((DWORD)((dwIns>>6 )&0x1F)) + #define INS_I ((DWORD)((dwIns )&0xFFFF)) + #define SIGNED16(x) ((INT32)(((SHORT)(x)))) + #define UNSIGNED16(x) (((UINT32)(x))&0xFFFF) + #define REL_I(pc) ((pc)+4+((SIGNED16(INS_I))<<2)) + #define ABS_I(pc) (((pc)&0xF0000000)|((dwIns<<2)&0x0FFFFFFC)) + + /* + ** Prepare to execute the next instruction + */ + DWORD dwBeforePC = r3000_getreg(iop_get_r3000_state(emu_get_iop_state(me->m_pStateDebug)), R3000CLASS(PC)); + /* + ** Check for possible jump/call instructions and compute the target. + ** + ** This way we'll know whether there was a call to add to the call stack + ** and be able to differentiate between jumps and exceptions. + ** + ** "The program counter changed - was this intentional?" + ** We can know this ahead of time. + */ + BOOL bPossibleJump = FALSE; + BOOL bPossibleCall = FALSE; + DWORD dwPossibleJumpTarget = 0; + dwIns = iop_getword(emu_get_iop_state(me->m_pStateDebug), dwBeforePC); + if(dwIns < 0x04000000) { + /* MINOR */ + switch(dwIns & 0x3F) { + case 0x09: /* jalr */ + if(INS_D == 31) bPossibleCall = TRUE; + /* INTENTIONAL FALL THROUGH */ + case 0x08: /* jr */ + bPossibleJump = TRUE; + dwPossibleJumpTarget = r3000_getreg(iop_get_r3000_state(emu_get_iop_state(me->m_pStateDebug)), R3000CLASS(GEN)+INS_S); + break; + } + } else { + /* MAJOR */ + switch(dwIns >> 26) { + case 0x01: /* various branch types */ + switch(INS_T) { + case 0x10: case 0x11: bPossibleCall = TRUE; + } + /* INTENTIONAL FALL THROUGH */ + case 0x04: /* beq */ + case 0x05: /* bne */ + case 0x06: /* blez */ + case 0x07: /* bgtz */ + bPossibleJump = TRUE; + dwPossibleJumpTarget = REL_I(dwBeforePC); + break; + case 0x03: /* jal */ + bPossibleCall = TRUE; + /* INTENTIONAL FALL THROUGH */ + case 0x02: /* j */ + bPossibleJump = TRUE; + dwPossibleJumpTarget = ABS_I(dwBeforePC); + break; + } + } + + /* + ** Execute the next instruction + */ + signed short samplebuffer[2*100]; + unsigned dwSoundSamples = 100; + int nExecuteError = emu_execute(me->m_pStateDebug, 1, samplebuffer, &dwSoundSamples, me->m_dwDebugEventMask); + /* + ** Handle unrecoverable errors here + ** Set the error flag and terminate directly + */ + if(nExecuteError < 0) { + me->m_bDebugErrorFlag = TRUE; + AfxGetMainWnd()->PostMessage(WM_COMMAND, ID_DEBUG_EXECUTIONSTOPPED, 0); + break; + } + + /* + ** Update the event log + */ + int c = iop_get_event_count(emu_get_iop_state(me->m_pStateDebug)); + for(; c > 0; c--) { + TCHAR s[500]; + UINT64 time; + char *fmt = "format not set(%08X,%08X,%08X,%08X)"; + UINT32 type; + UINT32 arg[4]; + iop_get_event(emu_get_iop_state(me->m_pStateDebug), &time, &type, &fmt, arg); + iop_dismiss_event(emu_get_iop_state(me->m_pStateDebug)); + int i; + TCHAR *ps = s + 19; + for(i = 19; i >= 0; i--) { + int digit = (int)(time % 10); + time /= 10; + s[i] = _T("0123456789")[digit]; + if(digit) ps = s + i; + } + s[20] = _T(':'); + s[21] = _T(' '); + s[22] = 0; + wsprintf(s + lstrlen(s), _T("(pc=0x%08X) "), dwBeforePC); + wsprintf(s + lstrlen(s), fmt, + (UINT32)(arg[0]), + (UINT32)(arg[1]), + (UINT32)(arg[2]), + (UINT32)(arg[3]) + ); + + me->m_eventlog.Add(ps); + } + + /* + ** Perform post-analysis on the instruction just executed + */ + DWORD dwPC = r3000_getreg(iop_get_r3000_state(emu_get_iop_state(me->m_pStateDebug)), R3000CLASS(PC)); + DWORD dwSP = r3000_getreg(iop_get_r3000_state(emu_get_iop_state(me->m_pStateDebug)), R3000CLASS(GEN)+29); + BOOL bException = FALSE; + if(dwPC != (dwBeforePC + 4)) { + /* + ** Check for return + */ + if(nCallStackSize) { + me->m_callstack.CheckForReturn(dwPC, dwSP); + nCallStackSize = me->m_callstack.GetSize(); + } + /* + ** Do some voodoo to see if an exception happened + */ + if(bPossibleJump && dwPC == dwPossibleJumpTarget) { + bException = FALSE; + } else { + bException = TRUE; + } + /* + ** Handle calls or exceptions + */ + if(bPossibleCall || bException) { + SCallStackEntry e; + e.bException = bException; + e.dwArg[0] = r3000_getreg(iop_get_r3000_state(emu_get_iop_state(me->m_pStateDebug)), R3000CLASS(GEN)+4); + e.dwArg[1] = r3000_getreg(iop_get_r3000_state(emu_get_iop_state(me->m_pStateDebug)), R3000CLASS(GEN)+5); + e.dwArg[2] = r3000_getreg(iop_get_r3000_state(emu_get_iop_state(me->m_pStateDebug)), R3000CLASS(GEN)+6); + e.dwArg[3] = r3000_getreg(iop_get_r3000_state(emu_get_iop_state(me->m_pStateDebug)), R3000CLASS(GEN)+7); + e.dwCause = r3000_getreg(iop_get_r3000_state(emu_get_iop_state(me->m_pStateDebug)), R3000CLASS(C0)+13); + e.dwInvokedAddress = dwPC; + e.dwReturnPC = r3000_getreg(iop_get_r3000_state(emu_get_iop_state(me->m_pStateDebug)), bException ? (R3000CLASS(C0)+14) : (R3000CLASS(GEN)+31)); + e.dwReturnSP = r3000_getreg(iop_get_r3000_state(emu_get_iop_state(me->m_pStateDebug)), R3000CLASS(GEN)+29); + me->m_callstack.Add(e); + nCallStackSize++; + } + } + + /* + ** Check for terminating conditions + */ + BOOL bTerminate = FALSE; + /* + ** Code breakpoints + */ + if(me->IsBreakpointOnExecute(dwPC)) { + me->m_bDebugBreakpointExecuteFlag = TRUE; + me->m_dwDebugBreakpointExecuteAddress = dwPC; + bTerminate = TRUE; + } + + /* Invalid PC */ + if(me->m_bDebugBreakOnWeed) { + BOOL inv = FALSE; + switch((dwPC >> 29) & 7) { + case 1: case 2: case 3: case 6: case 7: inv = TRUE; + } + DWORD t = dwPC & 0x1FFFFFFF; + if(t >= 0x00800000 && t < 0x1F000000) inv = TRUE; + if(t >= 0x1F000000 && t < 0x1FC00000) inv = TRUE; + if(inv) { + me->m_bDebugWeedFlag = TRUE; + me->m_dwDebugWeedAddress = dwPC; + bTerminate = TRUE; + } + } + + /* + ** Memory breakpoints + ** Terminate if there's a triggering load or store instruction + */ + dwIns = iop_getword(emu_get_iop_state(me->m_pStateDebug), dwPC); + DWORD dwOperandAddress; + switch(dwIns >> 26) { + case 0x20: /* lb */ + case 0x21: /* lh */ + case 0x23: /* lw */ + case 0x24: /* lbu */ + case 0x25: /* lhu */ + dwOperandAddress = r3000_getreg(iop_get_r3000_state(emu_get_iop_state(me->m_pStateDebug)), R3000CLASS(GEN)+INS_S) + SIGNED16(INS_I); + dwOperandAddress &= 0xFFFFFFFC; + if(me->IsBreakpointOnRead(dwOperandAddress)) { + me->m_bDebugBreakpointReadFlag = TRUE; + me->m_dwDebugBreakpointReadAddress = dwOperandAddress; + bTerminate = TRUE; + } + break; + case 0x28: /* sb */ + case 0x29: /* sh */ + case 0x2B: /* sw */ + dwOperandAddress = r3000_getreg(iop_get_r3000_state(emu_get_iop_state(me->m_pStateDebug)), R3000CLASS(GEN)+INS_S) + SIGNED16(INS_I); + dwOperandAddress &= 0xFFFFFFFC; + if(me->IsBreakpointOnWrite(dwOperandAddress)) { + me->m_bDebugBreakpointWriteFlag = TRUE; + me->m_dwDebugBreakpointWriteAddress = dwOperandAddress; + bTerminate = TRUE; + } + break; + } + + /* + ** Command-specific terminating conditions + */ + switch(me->m_nDebugCommand) { + /* + ** Go: Never terminate + */ + case ID_DEBUG_GO: + break; + /* + ** Step Into: Always terminate + */ + case ID_DEBUG_STEPINTO: + bTerminate = TRUE; + break; + /* + ** Step Over: Terminate if the call stack level is the same as before + */ + case ID_DEBUG_STEPOVER: + if(nCallStackSize == nInitialCallStackSize) bTerminate = TRUE; + break; + /* + ** Step Out: Terminate if the call stack level is less than before + */ + case ID_DEBUG_STEPOUT: + if(nCallStackSize < nInitialCallStackSize) bTerminate = TRUE; + break; + /* + ** Run to Cursor / Run to Specific Address: Terminate when that address is reached + */ + case ID_DEBUG_RUNTOCURSOR: + case ID_DEBUG_SPECIFICLINE: + if((dwPC & 0x1FFFFFFC) == (me->m_dwDebugRunTarget & 0x1FFFFFFC)) bTerminate = TRUE; + break; + /* + ** Run to Interrupt: Terminate if an interrupt just happened + */ + case ID_DEBUG_RUNTOINT: + if(bException) { + DWORD dwCause = r3000_getreg(iop_get_r3000_state(emu_get_iop_state(me->m_pStateDebug)), R3000CLASS(C0)+13); + /* + ** Examine Cause bits + ** 0 means hardware interrupt + */ + if(((dwCause >> 2) & 0xF) == 0x0) bTerminate = TRUE; + } + break; + /* + ** Unknown command: Just terminate + */ + default: + bTerminate = TRUE; + break; + } + + /* + ** Handle terminating conditions, if they exist + */ + if(bTerminate) { + AfxGetMainWnd()->PostMessage(WM_COMMAND, ID_DEBUG_EXECUTIONSTOPPED, 0); + break; + } + + } + + /* + ** Signal thread end; return + */ + me->m_pDebugThread = NULL; + me->m_csDebug.Unlock(); + return 0; +} + +/***************************************************************************/ +/* +** Play thread must never die until specifically told to +** (via either m_dwPlayKillFlag or a WM_APP+1 message) +*/ +UINT AFX_CDECL CPSFWorkArea__PlayThread(LPVOID lpParam) { + CPSFWorkArea *me = (CPSFWorkArea*)lpParam; + me->m_csPlay.Lock(); + me->m_evPlay.SetEvent(); + + DWORD samplebuffer[8*4096]; + CWaveOutput waveoutput; + waveoutput.Open(samplebuffer, 8, 4096, + (me->m_nVersion == 1) ? 44100 : 48000 + ); + +// OutputDebugString("PlayThread started\n"); + +// void *pFilter = filter_open(); + + int q = 0; + while(!me->m_dwPlayKillFlag) { + MSG msg; + ::GetMessage(&msg, NULL, WM_APP, WM_APP+2); + if(msg.message == WM_APP+2) { +//TRACE("pause %d\n",msg.wParam); + waveoutput.Pause(msg.wParam); + continue; + } + + if(msg.message == WM_APP+1) break; + if(msg.message != WM_APP) continue; + + short *pBuf = (short*)(msg.lParam); + int nSamples = 4096; + + int r = 0; + while(nSamples > 0) { + int n = nSamples; + r = emu_execute(me->m_pStatePlay, 0x7FFFFFFF, pBuf, (unsigned*)(&n), 0); + /* + ** On error, simply play silence + */ + if(r < 0) { + memset(pBuf, 0, sizeof(short)*2*nSamples); + n = nSamples; + } else { + /* + ** Shove it through the filter + */ +// n = filter_process(pFilter, pBuf, n); + } +//for(r=0;r<2*n;r++)pBuf[r]=((q++)%168)*10; + pBuf += 2 * n; + nSamples -= n; + } + waveoutput.BufferReady(msg.wParam); + } + +// filter_close(pFilter); + + waveoutput.Close(); + + me->m_pPlayThread = NULL; + me->m_csPlay.Unlock(); + return 0; +} + +/***************************************************************************/ + +void CPSFWorkArea::DeleteContents() +{ + KillDebugThreadAndBlock(); + KillPlayThreadAndBlock(); + ClearWorkArea(); + ClearAllSavedStates(); + m_tag.Empty(); +} + +void CPSFWorkArea::OnCloseDocument() +{ + // TODO: Add your specialized code here and/or call the base class + + CDocument::OnCloseDocument(); +} + +void CPSFWorkArea::OnFileImportbinary() +{ + CImportBinaryDlg dlgImportBinary; + + if(dlgImportBinary.DoModal() != IDOK) return; + + CString strPathName = dlgImportBinary.m_strPathName; + DWORD dwOffset = dlgImportBinary.m_dwOffset; + DWORD dwLength = dlgImportBinary.m_dwLength; + DWORD dwDestinationAddress = dlgImportBinary.m_dwDestinationAddress; + +// dwOffset &= 0xFFFFFFFC; +// dwLength &= 0xFFFFFFFC; +// dwDestinationAddress &= 0xFFFFFFFC; + + if(!dwLength) return; + if(strPathName.IsEmpty()) return; + + CString strCaption; + strCaption.LoadString(IDS_IMPORT_BINARY); + + FILE *f = fopen((LPCSTR)strPathName, "rb"); + if(!f) { + CString s; + s.Format(_T("Unable to open '%s'."), (LPCTSTR)strPathName); + AfxGetMainWnd()->MessageBox(s, (LPCTSTR)strCaption, MB_OK|MB_ICONHAND); + } + + LPBYTE lpBuffer = new BYTE[dwLength]; + memset(lpBuffer, 0, dwLength); + fseek(f, dwOffset, SEEK_SET); + fread(lpBuffer, 1, dwLength, f); + fclose(f); + + ImportBinaryFromBuffer(lpBuffer, dwDestinationAddress, dwLength); + + delete[] lpBuffer; + + SetModifiedFlag(); + UpdateAllViews(NULL); +} + +void CPSFWorkArea::OnUpdateFileImportbinary(CCmdUI* pCmdUI) { + pCmdUI->Enable( + (GetVersion() == 1) && (!IsRunning()) + ); +} + +void CPSFWorkArea::OnUpdateDebugRuntoint(CCmdUI* pCmdUI) { pCmdUI->Enable(!IsRunning()); } +void CPSFWorkArea::OnUpdateEditBreakpoints(CCmdUI* pCmdUI) { pCmdUI->Enable(!IsRunning()); } + +void CPSFWorkArea::OnEditBreakpoints() +{ + CBreakpointsDlg dlgBreakpoints; + + dlgBreakpoints.m_pWorkArea = this; + + /* + ** Quick run through the breakpoint map to add all breakpoint addresses + ** This makes the dialog's job a lot easier + */ + for(int i = 0; i < 0x5000; i++) { + DWORD dwMap = + m_adwBreakpointMapExecute[i] | + m_adwBreakpointMapRead[i] | + m_adwBreakpointMapWrite[i]; + if(dwMap) { + DWORD dwBase = BreakpointIndexToAddress(32 * i); + for(int j = 0; j < 32; j++) { + if(dwMap & (1 << j)) dlgBreakpoints.m_adwBreakpoints.Add(dwBase + 4 * j); + } + } + } + + /* + ** Dialog will handle everything from here + */ + dlgBreakpoints.DoModal(); + +} + +void CPSFWorkArea::OnUpdateEditExesettings(CCmdUI* pCmdUI) { + BOOL b = FALSE; + if((m_nVersion == 1) && (!IsRunning())) b = TRUE; + pCmdUI->Enable(b); +} + +void CPSFWorkArea::OnEditExesettings() +{ + CExeSettingsDlg dlgExeSettings; + + dlgExeSettings.m_dwPC = m_dwEXEStartPC; + dlgExeSettings.m_dwSP = m_dwEXEStartSP; + + dlgExeSettings.m_dwTextStart = m_dwEXEStartAddress; + dlgExeSettings.m_dwTextSize = m_dwEXEByteLength; + + if(dlgExeSettings.DoModal() != IDOK) return; + + m_dwEXEStartPC = dlgExeSettings.m_dwPC; + m_dwEXEStartSP = dlgExeSettings.m_dwSP; + m_dwEXEStartAddress = dlgExeSettings.m_dwTextStart; + m_dwEXEByteLength = dlgExeSettings.m_dwTextSize; + +} + +void CPSFWorkArea::PlayStart() +{ + /* + ** Kill old thread, if there was one + */ + KillPlayThreadAndBlock(); + /* + ** Allocate a play state if it doesn't already exist + */ + if(!m_pStatePlay) { + m_pStatePlay = malloc(emu_get_state_size(m_nVersion)); + } + ASSERT(m_pStatePlay); + emu_clear_state(m_pStatePlay, m_nVersion); + emu_set_readfile(m_pStatePlay, CPSFWorkArea__readfile_cb, this); + +// strcpy(m_sPSF2Path, +// (((CPSFLabApp*)(AfxGetApp()))->m_sPSF2Path) +// ); + + //emu_set_console_out(m_pStatePlay, CPSFWorkArea__console_out, this); + //spu_enable_reverb(iop_get_spu_state(emu_get_iop_state(m_pStatePlay)), 0); + /* + ** Set emulation core settings + */ + SPSFEmuSettings es; + theApp.GetEmuSettings(PSF_EMUSETTINGS_PLAY, es); + iop_set_compat(emu_get_iop_state(m_pStatePlay), es.bFriendly ? IOP_COMPAT_FRIENDLY : IOP_COMPAT_HARSH); + /* + ** Load the patched EXE into this play state + */ + if(m_nVersion == 1) { + LoadEXEToState(m_pStatePlay); + ApplyPatchesToState(m_pStatePlay); + } + /* + ** Begin unpaused! + */ + m_bPlayPaused = FALSE; + /* + ** Begin new thread + */ + StartPlayThreadAndBlock(); +} + +void CPSFWorkArea::PlayPause() { + if(m_bPlayPaused) return; + if(m_pPlayThread) m_pPlayThread->PostThreadMessage(WM_APP+2, TRUE, 0); + m_bPlayPaused = TRUE; +} + +void CPSFWorkArea::PlayUnpause() { + if(!m_bPlayPaused) return; + if(m_pPlayThread) m_pPlayThread->PostThreadMessage(WM_APP+2, FALSE, 0); + m_bPlayPaused = FALSE; +} + +void CPSFWorkArea::LoadEXEToState(void *pState) +{ + ASSERT(pState); + /* + ** Copy EXE data + */ + for(DWORD i = 0; i < 0x7C000; i++) { + iop_setword(emu_get_iop_state(pState), 0x80010000+4*i, m_adwEXEData[i]); + } + /* + ** Set the initial PC/SP + */ + r3000_setreg(iop_get_r3000_state(emu_get_iop_state(pState)), R3000CLASS(PC) , m_dwEXEStartPC); + r3000_setreg(iop_get_r3000_state(emu_get_iop_state(pState)), R3000CLASS(GEN)+29, m_dwEXEStartSP); +} + +void CPSFWorkArea::ApplyPatchesToState(void *pState) +{ + ASSERT(pState); + DWORD dwAddress; + for(dwAddress = 0x80010000; dwAddress < 0x80200000; dwAddress += 4) { + if(IsWordPatched(dwAddress)) iop_setword(emu_get_iop_state(pState), dwAddress, GetPatchWord(dwAddress)); + } +} + +/***************************************************************************/ + +void CPSFWorkArea::KillDebugThreadAndBlock() { + m_dwDebugKillFlag = 1; + m_csDebug.Lock(); m_csDebug.Unlock(); + m_bRunning = FALSE; +} + +void CPSFWorkArea::KillPlayThreadAndBlock() { + if(m_pPlayThread) m_pPlayThread->PostThreadMessage(WM_APP+1,0,0); + m_dwPlayKillFlag = 1; + m_csPlay.Lock(); m_csPlay.Unlock(); + m_bPlaying = FALSE; +} + +void CPSFWorkArea::StartDebugThreadAndBlock() { + KillDebugThreadAndBlock(); + m_evDebug.ResetEvent(); + m_dwDebugKillFlag = 0; + m_bRunning = TRUE; + /* + ** Must get app-global options here... can't really get them in the + ** debug thread itself + */ + /* + ** Event mask + */ + m_dwDebugEventMask = theApp.GetEventMask(); + /* + ** Emulation core settings + */ + SPSFEmuSettings es; + theApp.GetEmuSettings(PSF_EMUSETTINGS_DEBUG, es); + iop_set_compat(emu_get_iop_state(m_pStateDebug), es.bFriendly ? IOP_COMPAT_FRIENDLY : IOP_COMPAT_HARSH); + /* + ** Now begin the thread + */ + m_pDebugThread = AfxBeginThread(CPSFWorkArea__DebugThread, (LPVOID)this); + m_evDebug.Lock(); +} + +void CPSFWorkArea::StartPlayThreadAndBlock() { + KillPlayThreadAndBlock(); + m_evPlay.ResetEvent(); + m_dwPlayKillFlag = 0; + m_bPlaying = TRUE; + m_pPlayThread = AfxBeginThread(CPSFWorkArea__PlayThread, (LPVOID)this); + m_evPlay.Lock(); +} + +/***************************************************************************/ +/* +** This command is sent INTERNALLY when execution has stopped in the debug +** thread. +*/ +void CPSFWorkArea::OnDebugExecutionstopped() +{ + KillDebugThreadAndBlock(); + /* + ** Update views depending on what exactly happened + */ + DWORD dwPC = r3000_getreg(iop_get_r3000_state(emu_get_iop_state(m_pStateDebug)), R3000CLASS(PC)); + CodeJumpTo(dwPC); + if(m_bDebugBreakpointReadFlag ) MemoryJumpTo(m_dwDebugBreakpointReadAddress ); + if(m_bDebugBreakpointWriteFlag) MemoryJumpTo(m_dwDebugBreakpointWriteAddress); + CEventView *ev = (CEventView *)FindViewOfClass(RUNTIME_CLASS(CEventView )); + if(ev) { ev->JumpToBottom(); } + RegisterMonitor(); + UpdateAllViews(NULL); + + /* + ** Message box depending on what happened + */ + CString str, strMessage; + CString strCaption; + strCaption.LoadString(IDS_BREAKPOINT); + UINT nType = MB_OK; + if(m_bDebugErrorFlag) { + str.Format(IDS_UNRECOVERABLE_ADDRESS, dwPC); + strMessage += str; + strCaption.LoadString(IDS_ERROR); + nType = MB_OK|MB_ICONHAND; + } + if(m_bDebugBreakpointExecuteFlag) { + str.Format(IDS_BREAKPOINT_EXECUTE_ADDRESS, dwPC); + strMessage += str; + } + if(m_bDebugBreakpointReadFlag) { + str.Format(IDS_BREAKPOINT_READ_ADDRESS, m_dwDebugBreakpointReadAddress); + strMessage += str; + } + if(m_bDebugBreakpointWriteFlag) { + str.Format(IDS_BREAKPOINT_WRITE_ADDRESS, m_dwDebugBreakpointWriteAddress); + strMessage += str; + } + if(m_bDebugWeedFlag) { + str.Format(IDS_WEED_ADDRESS, m_dwDebugWeedAddress); + strMessage += str; + } + + if(!strMessage.IsEmpty()) { + AfxGetMainWnd()->MessageBox(strMessage, (LPCTSTR)strCaption, nType); + } + + // commands will re-enable themselves automatically when this returns +} + +void CPSFWorkArea::RunToAddress(DWORD dwAddress) +{ + KillDebugThreadAndBlock(); + m_nDebugCommand = ID_DEBUG_SPECIFICLINE; + m_dwDebugRunTarget = dwAddress; + StartDebugThreadAndBlock(); + UpdateAllViews(NULL); +} + +void CPSFWorkArea::OnUpdateDebugSpecificline(CCmdUI* pCmdUI) { + pCmdUI->Enable(!IsRunning()); +} + +void CPSFWorkArea::OnDebugSpecificline() { + CRunToSpecificLineDlg dlgRunToSpecificLine; + ASSERT(m_pStateDebug); + dlgRunToSpecificLine.m_dwAddress = r3000_getreg(iop_get_r3000_state(emu_get_iop_state(m_pStateDebug)), R3000CLASS(PC)); + if(dlgRunToSpecificLine.DoModal() != IDOK) return; + RunToAddress(dlgRunToSpecificLine.m_dwAddress); +} + +void CPSFWorkArea::OnDebugRuntoint() +{ + KillDebugThreadAndBlock(); + m_nDebugCommand = ID_DEBUG_RUNTOINT; + StartDebugThreadAndBlock(); + UpdateAllViews(NULL); +} + +void CPSFWorkArea::ClearAllSavedStates() +{ + int i; + for(i = 0; i < 10; i++) { + if(m_apSavedStates[i]) { + free(m_apSavedStates[i]); + m_apSavedStates[i] = 0; + } + } + m_nCurrentStateSlot = 0; +} + +void CPSFWorkArea::SaveDebugState(int nSlot) +{ + ASSERT(m_pStateDebug); + ASSERT(nSlot >= 0 && nSlot <= 9); + int nStateSize = emu_get_state_size(m_nVersion); + if(!m_apSavedStates[nSlot]) { + m_apSavedStates[nSlot] = malloc(nStateSize); + } + + memcpy(m_apSavedStates[nSlot], m_pStateDebug, nStateSize); + m_aSavedCallStacks[nSlot].CopyFrom(m_callstack); + m_aSavedEventLogs[nSlot].CopyFrom(m_eventlog); + +} + +void CPSFWorkArea::LoadDebugState(int nSlot) +{ + ASSERT(m_pStateDebug); + ASSERT(nSlot >= 0 && nSlot <= 9); + if(!m_apSavedStates[nSlot]) return; + int nStateSize = emu_get_state_size(m_nVersion); + + memcpy(m_pStateDebug, m_apSavedStates[nSlot], nStateSize); + m_callstack.CopyFrom(m_aSavedCallStacks[nSlot]); + m_eventlog.CopyFrom(m_aSavedEventLogs[nSlot]); +} + +void CPSFWorkArea::OnDebugSelectslot() +{ + CStateSlotDlg dlgStateSlot; + + dlgStateSlot.m_nSlot = m_nCurrentStateSlot; + + CString strInUse; + CString strNotInUse; + strInUse.LoadString(IDS_INUSE); + strNotInUse.LoadString(IDS_NOTINUSE); + + dlgStateSlot.m_strInUse1 = m_apSavedStates[0] ? ((LPCTSTR)strInUse) : ((LPCTSTR)strNotInUse); + dlgStateSlot.m_strInUse2 = m_apSavedStates[1] ? ((LPCTSTR)strInUse) : ((LPCTSTR)strNotInUse); + dlgStateSlot.m_strInUse3 = m_apSavedStates[2] ? ((LPCTSTR)strInUse) : ((LPCTSTR)strNotInUse); + dlgStateSlot.m_strInUse4 = m_apSavedStates[3] ? ((LPCTSTR)strInUse) : ((LPCTSTR)strNotInUse); + dlgStateSlot.m_strInUse5 = m_apSavedStates[4] ? ((LPCTSTR)strInUse) : ((LPCTSTR)strNotInUse); + dlgStateSlot.m_strInUse6 = m_apSavedStates[5] ? ((LPCTSTR)strInUse) : ((LPCTSTR)strNotInUse); + dlgStateSlot.m_strInUse7 = m_apSavedStates[6] ? ((LPCTSTR)strInUse) : ((LPCTSTR)strNotInUse); + dlgStateSlot.m_strInUse8 = m_apSavedStates[7] ? ((LPCTSTR)strInUse) : ((LPCTSTR)strNotInUse); + dlgStateSlot.m_strInUse9 = m_apSavedStates[8] ? ((LPCTSTR)strInUse) : ((LPCTSTR)strNotInUse); + dlgStateSlot.m_strInUse0 = m_apSavedStates[9] ? ((LPCTSTR)strInUse) : ((LPCTSTR)strNotInUse); + + if(dlgStateSlot.DoModal() != IDOK) return; + + m_nCurrentStateSlot = dlgStateSlot.m_nSlot; +} + +DWORD CPSFWorkArea::BreakpointIndexToAddress(int nIndex) +{ + if(nIndex < 0) return 0; + if(nIndex >= 0xA0000) return 0; + if(nIndex < 0x80000) return 0x80000000 + 4 * nIndex; + return 0xBFC00000 + 4 * (nIndex - 0x80000); +} + +void CPSFWorkArea::CodeJumpTo(DWORD dwAddress) +{ + CCodeView *cv = (CCodeView*)FindViewOfClass(RUNTIME_CLASS(CCodeView)); + if(cv) { + cv->JumpTo(dwAddress); + cv->SetFocus(); + } +} + +void CPSFWorkArea::MemoryJumpTo(DWORD dwAddress) +{ + CMemoryView *mv = (CMemoryView*)FindViewOfClass(RUNTIME_CLASS(CMemoryView)); + if(mv) { + mv->JumpTo(dwAddress); + mv->SetFocus(); + } +} + +void CPSFWorkArea::OnEditTag() +{ + CTagDlg dlgTag; + CString strTag = m_tag.GetRaw(); + dlgTag.m_strTag = strTag; + if(dlgTag.DoModal() != IDOK) return; + if(!lstrcmp((LPCTSTR)strTag, (LPCTSTR)dlgTag.m_strTag)) return; + m_tag.SetRaw(dlgTag.m_strTag); + SetModifiedFlag(); +} + +void CPSFWorkArea::ImportEXEFromBuffer(LPBYTE lpBuffer, DWORD dwLength) +{ + if(dwLength < 0x800) return; + memcpy(m_EXEHeader, lpBuffer, 0x800); + m_dwEXEStartPC = *((DWORD*)(lpBuffer+0x10)); + m_dwEXEStartSP = *((DWORD*)(lpBuffer+0x30)); + m_dwEXEStartAddress = *((DWORD*)(lpBuffer+0x18)); + m_dwEXEByteLength = *((DWORD*)(lpBuffer+0x1C)); + if(m_dwEXEByteLength > (dwLength-0x800)) m_dwEXEByteLength = (dwLength-0x800); + ImportBinaryFromBuffer(lpBuffer+0x800, m_dwEXEStartAddress, m_dwEXEByteLength); +} + +/* +** TODO +** Hi there! +** Fix me so I can load unaligned data! +*/ +void CPSFWorkArea::ImportBinaryFromBuffer(LPBYTE lpBuffer, DWORD dwAddress, DWORD dwLength) +{ + dwLength &= 0xFFFFFFFC; + for(DWORD i = 0; i < dwLength; i += 4) { + DWORD d = *((DWORD*)(lpBuffer+i)); + DWORD a = (dwAddress + i) & 0xFFFFFFFC; + DeletePatchWord(a); + int nEXEIndex = AddressToEXEIndex(a); + if(nEXEIndex >= 0) m_adwEXEData[nEXEIndex] = d; + iop_setword(emu_get_iop_state(m_pStateDebug), a, d); + } +} + +/* +** TODO +** Hi there! +** Fix me so I can export unaligned data! +*/ +void CPSFWorkArea::ExportBinaryToBuffer(LPBYTE lpBuffer, DWORD dwAddress, DWORD dwLength) +{ + dwLength &= 0xFFFFFFFC; + for(DWORD i = 0; i < dwLength; i += 4) { + DWORD a = (dwAddress & 0xFFFFFFFC) + i; + DWORD d = 0; + int nEXEIndex = AddressToEXEIndex(a); + if(nEXEIndex >= 0) d = m_adwEXEData[nEXEIndex]; + if(IsWordPatched(a)) d = GetPatchWord(a); + *((DWORD*)(lpBuffer+i)) = d; + } +} + +/* +** Buffer must have 0x200000 bytes available +*/ +DWORD CPSFWorkArea::ExportEXEToBuffer(LPBYTE lpBuffer) +{ + DWORD dwLen = m_dwEXEByteLength; + if(dwLen > 0x1F0000) dwLen = 0x1F0000; + /* + ** Write header, hooray + */ + *((DWORD*)(m_EXEHeader+0x10)) = m_dwEXEStartPC; + *((DWORD*)(m_EXEHeader+0x30)) = m_dwEXEStartSP; + *((DWORD*)(m_EXEHeader+0x18)) = m_dwEXEStartAddress; + *((DWORD*)(m_EXEHeader+0x1C)) = m_dwEXEByteLength; + memcpy(lpBuffer, m_EXEHeader, 0x800); + /* + ** Export the text section + */ + ExportBinaryToBuffer(lpBuffer + 0x800, m_dwEXEStartAddress, m_dwEXEByteLength); + /* + ** Return the total length + */ + return (0x800 + m_dwEXEByteLength); +} + +void CPSFWorkArea::OnFileSaveas() +{ + CString strFilterName; + CString strFilterExt; + + CDocTemplate *pDocTemplate = GetDocTemplate(); + ASSERT(pDocTemplate); + pDocTemplate->GetDocString(strFilterName, CDocTemplate::filterName); + pDocTemplate->GetDocString(strFilterExt , CDocTemplate::filterExt ); + + CString strFilterString = strFilterName + _T("|*") + strFilterExt + _T("||"); + + CFileDialog dlgFile( + FALSE, + (LPCTSTR)strFilterExt, + (LPCTSTR)m_strPathName, + OFN_HIDEREADONLY | OFN_OVERWRITEPROMPT, + (LPCTSTR)strFilterString + ); + + if(dlgFile.DoModal() != IDOK) return; + + CString strSaveAsPathName = dlgFile.GetPathName(); + + OnSaveDocument((LPCTSTR)strSaveAsPathName); +} + +void CPSFWorkArea::OnFileImportexe() +{ + CString strEXEFilter; + CString strAllFilter; + strEXEFilter.LoadString(IDS_FILTER_EXE); + strAllFilter.LoadString(IDS_FILTER_ALL); + CString strFilterString = strEXEFilter + _T("|") + strAllFilter + _T("||"); + CFileDialog dlgFile( + TRUE, + _T(""), + _T(""), + OFN_HIDEREADONLY | OFN_OVERWRITEPROMPT, + (LPCTSTR)strFilterString + ); + CString strTitle; + strTitle.LoadString(IDS_IMPORT_EXE); + dlgFile.m_ofn.lpstrTitle = (LPCTSTR)strTitle; + if(dlgFile.DoModal() != IDOK) return; + CString strPathName = dlgFile.GetPathName(); + + FILE *f; + f = fopen((LPCSTR)strPathName, "rb"); + if(!f) { + CString s; + s.Format(_T("Unable to open '%s'."), (LPCTSTR)strPathName); + AfxGetMainWnd()->MessageBox(s, (LPCTSTR)strTitle, MB_OK|MB_ICONHAND); + } + + fseek(f, 0, SEEK_END); + int nLength = ftell(f); + fseek(f, 0, SEEK_SET); + if(nLength < 0) nLength = 0; + + LPBYTE lpEXE = new BYTE[nLength]; + ASSERT(lpEXE); + memset(lpEXE, 0, nLength); + + fread(lpEXE, 1, nLength, f); + fclose(f); + + ImportEXEFromBuffer(lpEXE, nLength); + delete[] lpEXE; + + /* + ** Might as well restart the debugger + */ + DebugRestart(); + RegisterMonitor(); + + SetModifiedFlag(); + UpdateAllViews(NULL); +} + +void CPSFWorkArea::OnUpdateFileImportexe(CCmdUI* pCmdUI) { + pCmdUI->Enable( + (GetVersion() == 1) && (!IsRunning()) + ); +} + +void CPSFWorkArea::OnFileExportexe() +{ + CString strEXEFilter; + CString strAllFilter; + strEXEFilter.LoadString(IDS_FILTER_EXE); + strAllFilter.LoadString(IDS_FILTER_ALL); + CString strFilterString = strEXEFilter + _T("|") + strAllFilter + _T("||"); + CFileDialog dlgFile( + FALSE, + _T(""), + _T(""), + OFN_HIDEREADONLY | OFN_OVERWRITEPROMPT, + (LPCTSTR)strFilterString + ); + CString strTitle; + strTitle.LoadString(IDS_EXPORT_EXE); + dlgFile.m_ofn.lpstrTitle = (LPCTSTR)strTitle; + if(dlgFile.DoModal() != IDOK) return; + CString strPathName = dlgFile.GetPathName(); + + LPBYTE lpEXE = new BYTE[0x200000]; + ASSERT(lpEXE); + DWORD dwEXELength = ExportEXEToBuffer(lpEXE); + + FILE *f; + f = fopen((LPCSTR)strPathName, "wb"); + if(!f) { + delete[] lpEXE; + CString s; + s.Format(_T("Unable to open '%s'."), (LPCTSTR)strPathName); + AfxGetMainWnd()->MessageBox(s, (LPCTSTR)strTitle, MB_OK|MB_ICONHAND); + } + fwrite(lpEXE, 1, dwEXELength, f); + fclose(f); + + delete[] lpEXE; + +} + +void CPSFWorkArea::OnFileFondue() +{ + while(AfxGetMainWnd()->MessageBox( + _T("Please insert Disk 22 to continue"), + _T("Disk Change"), + MB_OKCANCEL|MB_ICONINFORMATION + ) != IDCANCEL); + AfxGetMainWnd()->MessageBox( + _T("Unable to load overlay for CPSFWorkArea::OnFondue()\nFile not found"), + _T("Critical Error"), + MB_OK|MB_ICONHAND + ); +} + +void CPSFWorkArea::OnUpdateEditOptimize(CCmdUI* pCmdUI) { + BOOL b = FALSE; + if((m_nVersion == 1) && (!IsRunning())) b = TRUE; + pCmdUI->Enable(b); +} + +void CPSFWorkArea::OnEditOptimize() +{ + COptimizeDlg dlg; + dlg.m_pWorkArea = this; + if(dlg.DoModal() != IDOK) return; +} + +void CPSFWorkArea::AuditCommit(CPSFAudit &audit) { + DWORD i; + DWORD last_i_read = 0; + for(i = 0x80010000; i < 0x80200000; i += 4) { + if(audit.IsWordUsed(i)) { + last_i_read = i; + } else { + SetPatchWord(i, 0); + } + } + last_i_read += 4; + last_i_read &= 0x1FFFFC; + if(last_i_read < (m_dwEXEStartAddress & 0x1FFFFC)) { + last_i_read = (m_dwEXEStartAddress & 0x1FFFFC); + } + m_dwEXEByteLength = last_i_read - (m_dwEXEStartAddress & 0x1FFFFC); + if(m_dwEXEByteLength > 0x1F0000) { m_dwEXEByteLength = 0x1F0000; } + UpdateAllViews(NULL); +} + +void CPSFWorkArea::AuditUpload(CPSFAudit &audit) { + /* + ** Copy the executable there + */ + audit.Upload(0x80010000, m_adwEXEData, 0x1F0000); + /* + ** Set the initial PC/SP + */ + audit.SetPC(m_dwEXEStartPC); + audit.SetSP(m_dwEXEStartSP); + /* + ** Apply all patches + */ + DWORD dwAddress; + for(dwAddress = 0x80010000; dwAddress < 0x80200000; dwAddress += 4) { + if(IsWordPatched(dwAddress)) { + DWORD dwData = GetPatchWord(dwAddress); + audit.Upload(dwAddress, &dwData, 4); + } + } +} + +void CPSFWorkArea::OnFileExportbiosarea() +{ + // TODO: Add your command handler code here + if(!m_pStateDebug) return; + + FILE *f = fopen("test-ram", "wb"); + if(!f) return; + + DWORD tmp; + DWORD i; + for(i = 0; i < 0x200000; i += 4) { + tmp = iop_getword(emu_get_iop_state(m_pStateDebug), 0x80000000 + i); + fwrite(&tmp, 1, 4, f); + } + + fclose(f); + +} + +void CPSFWorkArea::SetVersion(int n) +{ + if(m_nVersion == n) return; + + ((CPSFLabApp*)(AfxGetApp()))->m_nNewPSFVersion = n; + ((CPSFLabApp*)(AfxGetApp()))->m_nWorkAreaVersion = n; + + DeleteContents(); + + m_nVersion = n; + + if(m_pStateDebug) { + free(m_pStateDebug); + m_pStateDebug = NULL; + } + m_pStateDebug = malloc(emu_get_state_size(m_nVersion)); + emu_clear_state(m_pStateDebug, m_nVersion); + emu_set_readfile(m_pStateDebug, CPSFWorkArea__readfile_cb, this); + emu_set_console_out(m_pStateDebug, CPSFWorkArea__console_out, this); + +// strcpy(m_sPSF2Path, +// (((CPSFLabApp*)(AfxGetApp()))->m_sPSF2Path) +// ); + + + OnNewDocument(); +} + +int CPSFWorkArea::GetVersion() +{ + return m_nVersion; +} + +void CPSFWorkArea::OnUpdateFileSave(CCmdUI* pCmdUI) +{ + pCmdUI->Enable(GetVersion() == 1); +} + +void CPSFWorkArea::OnUpdateFileSaveas(CCmdUI* pCmdUI) +{ + pCmdUI->Enable(GetVersion() == 1); +} + +void CPSFWorkArea::OnUpdateEditTag(CCmdUI* pCmdUI) +{ + pCmdUI->Enable(GetVersion() == 1); +} + +void CPSFWorkArea::OnUpdateFileExportexe(CCmdUI* pCmdUI) +{ + pCmdUI->Enable(GetVersion() == 1); +} diff --git a/Frameworks/HighlyExperimental/HighlyExperimental/Core/spu.c b/Frameworks/HighlyExperimental/HighlyExperimental/Core/spu.c new file mode 100644 index 000000000..d860ff1de --- /dev/null +++ b/Frameworks/HighlyExperimental/HighlyExperimental/Core/spu.c @@ -0,0 +1,812 @@ +///////////////////////////////////////////////////////////////////////////// +// +// spu - Top-level SPU emulation, for SPU and SPU2 +// +///////////////////////////////////////////////////////////////////////////// + +#ifndef EMU_COMPILE +#error "Hi I forgot to set EMU_COMPILE" +#endif + +#include "spu.h" + +#include "spucore.h" + +//////////////////////////////////////////////////////////////////////////////// +/* +** Static information +*/ +sint32 EMU_CALL spu_init(void) { return 0; } + +//////////////////////////////////////////////////////////////////////////////// +/* +** State information +*/ +#define SPUSTATE ((struct SPU_STATE*)(state)) + +#define CORESTATE(n) ((void*)(((char*)(state))+(SPUSTATE->offset_to_core[(n)]))) +#define SPURAM ((void*)(((char*)(state))+(SPUSTATE->offset_to_ram))) + + +struct SPU_STATE { + uint8 version; + uint32 offset_to_ram; + uint32 offset_to_core[2]; + + /* actual plugin option */ + uint8 global_main_on; + uint8 global_effect_on; + + uint32 tsa[2]; + uint8 dma_mode[2]; + + uint8 is_on[2]; + uint8 is_audible[2]; + uint8 is_reverb_enabled[2]; + uint8 is_irq_enabled[2]; + + uint16 mystery_dma[2]; + +}; + +/* +** Get size depending on version +*/ +uint32 EMU_CALL spu_get_state_size(uint8 version) { + uint32 size = 0; + if(version != 2) { version = 1; } + size += sizeof(struct SPU_STATE); + switch(version) { + case 1: + size += spucore_get_state_size(); + size += 0x80000; + break; + case 2: + size += spucore_get_state_size() * 2; + size += 0x200000; + break; + } + return size; +} + +/* +** Initialize SPU state +*/ +void EMU_CALL spu_clear_state(void *state, uint8 version) { + uint32 offset; + if(version != 2) { version = 1; } + /* + ** Clear to zero + */ + memset(state, 0, sizeof(struct SPU_STATE)); + /* + ** Set version + */ + SPUSTATE->version = version; + /* + ** Set offsets + */ + offset = sizeof(struct SPU_STATE); + switch(version) { + case 1: + /* Both cores point to the same place (safety) */ + SPUSTATE->offset_to_core[0] = offset; + SPUSTATE->offset_to_core[1] = offset; offset += spucore_get_state_size(); + SPUSTATE->offset_to_ram = offset; + break; + case 2: + SPUSTATE->offset_to_core[0] = offset; offset += spucore_get_state_size(); + SPUSTATE->offset_to_core[1] = offset; offset += spucore_get_state_size(); + SPUSTATE->offset_to_ram = offset; + break; + } + + // + // Set local flags + // + SPUSTATE->global_main_on = 1; + SPUSTATE->global_effect_on = 1; + + /* + ** Init SPU core states / clear SPU RAM + */ + switch(version) { + case 1: + spucore_clear_state(CORESTATE(0)); + spucore_set_mem_size(CORESTATE(0), 0x80000); + memset(SPURAM, 0, 0x80000); + break; + case 2: + spucore_clear_state(CORESTATE(0)); + spucore_clear_state(CORESTATE(1)); + spucore_set_mem_size(CORESTATE(0), 0x200000); + spucore_set_mem_size(CORESTATE(1), 0x200000); + memset(SPURAM, 0, 0x200000); + break; + } + +} + +/* +** Enable/disable reverb +*/ +void EMU_CALL spu_enable_reverb(void *state, uint8 enable) { + SPUSTATE->global_effect_on = enable; +} + +void EMU_CALL spu_enable_main(void *state, uint8 enable) { + SPUSTATE->global_main_on = enable; +} + +//////////////////////////////////////////////////////////////////////////////// +/* +** Hardware register load/store +*/ + +static uint32 EMU_CALL get_tsa(struct SPU_STATE *state, uint32 core) { + return state->tsa[core]; +} + +static void EMU_CALL set_tsa(struct SPU_STATE *state, uint32 core, uint32 a, uint32 mask) { + state->tsa[core] &= ~mask; + state->tsa[core] |= a & mask; +} + +static EMU_INLINE uint16 EMU_CALL get_transfer(struct SPU_STATE *state, uint32 core) { + uint32 memmask = (state->version == 2) ? 0x001FFFFE : 0x0007FFFE; + uint16 d = *((uint16*)(((uint8*)(SPURAM)) + ((state->tsa[core]) & memmask))); + state->tsa[core] += 2; + state->tsa[core] &= memmask; + return d; +} + +static EMU_INLINE void EMU_CALL set_transfer(struct SPU_STATE *state, uint32 core, uint16 d) { + uint32 memmask = (state->version == 2) ? 0x001FFFFE : 0x0007FFFE; + *((uint16*)(((uint8*)(SPURAM)) + ((state->tsa[core]) & memmask))) = d; + state->tsa[core] += 2; + state->tsa[core] &= memmask; +} + +void EMU_CALL spu_dma(void *state, uint32 core, void *mem, uint32 mem_ofs, uint32 mem_mask, uint32 bytes, int iswrite) { + uint32 words = (bytes + 3) / 4; + mem_ofs &= (~3); + if(iswrite) { + while(words--) { + uint32 d; + mem_ofs &= mem_mask; + d = *((uint32*)(((uint8*)mem)+mem_ofs)); + set_transfer(state, core, d ); + set_transfer(state, core, d >> 16); + mem_ofs += 4; + } + } else { + while(words--) { + uint32 d; + mem_ofs &= mem_mask; + d = ((uint32)(get_transfer(state, core))) ; + d |= ((uint32)(get_transfer(state, core))) << 16; + *((uint32*)(((uint8*)mem)+mem_ofs)) = d; + mem_ofs += 4; + } + } + // complete flag? + SPUSTATE->mystery_dma[core] |= 0x80; +} + +static uint16 EMU_CALL get_mystery_dma(struct SPU_STATE *state, uint32 core) { + uint16 m = state->mystery_dma[core]; + state->mystery_dma[core] = 0; + return m; +} + +static void EMU_CALL set_mystery_dma(struct SPU_STATE *state, uint32 core, uint16 n) { +} + +static uint16 EMU_CALL get_ctrl(struct SPU_STATE *state, uint32 core) { + uint32 on = !!(spucore_getflag(CORESTATE(core), SPUREG_FLAG_ON)); + uint32 main_enable = !!(spucore_getflag(CORESTATE(core), SPUREG_FLAG_MAIN_ENABLE)); + uint32 noiseclock = spucore_getreg(CORESTATE(core), SPUREG_NOISECLOCK) & 0x3F; + uint32 reverb_enable = !!(spucore_getflag(CORESTATE(core), SPUREG_FLAG_REVERB_ENABLE)); + uint32 irq_enable = !!(spucore_getflag(CORESTATE(core), SPUREG_FLAG_IRQ_ENABLE)); + uint32 dmamode = state->dma_mode[core] & 3; + uint32 er = !!(spucore_getflag(CORESTATE(core), SPUREG_FLAG_ER)); + uint32 cr = !!(spucore_getflag(CORESTATE(core), SPUREG_FLAG_CR)); + uint32 ee = !!(spucore_getflag(CORESTATE(core), SPUREG_FLAG_EE)); + uint32 ce = !!(spucore_getflag(CORESTATE(core), SPUREG_FLAG_CE)); + return ( + (on << 15) | + (main_enable << 14) | + (noiseclock << 8) | + (reverb_enable << 7) | + (irq_enable << 6) | + (dmamode << 4) | + (er << 3) | + (cr << 2) | + (ee << 1) | + (ce << 0) + ); +} + +static void EMU_CALL set_ctrl(struct SPU_STATE *state, uint32 core, uint16 d) { + spucore_setflag(CORESTATE(core), SPUREG_FLAG_ON , !!(d & (1<<15))); + spucore_setflag(CORESTATE(core), SPUREG_FLAG_MAIN_ENABLE , !!(d & (1<<14))); + spucore_setreg (CORESTATE(core), SPUREG_NOISECLOCK, (d >> 8) & 0x3F, 0x3F); + spucore_setflag(CORESTATE(core), SPUREG_FLAG_REVERB_ENABLE, !!(d & (1<< 7))); + spucore_setflag(CORESTATE(core), SPUREG_FLAG_IRQ_ENABLE , !!(d & (1<< 6))); + state->dma_mode[core] = (d >> 4) & 3; + spucore_setflag(CORESTATE(core), SPUREG_FLAG_ER , !!(d & (1<< 3))); + spucore_setflag(CORESTATE(core), SPUREG_FLAG_CR , !!(d & (1<< 2))); + spucore_setflag(CORESTATE(core), SPUREG_FLAG_EE , !!(d & (1<< 1))); + spucore_setflag(CORESTATE(core), SPUREG_FLAG_CE , !!(d & (1<< 0))); +} + +static uint16 EMU_CALL get_mmix(struct SPU_STATE *state, uint32 core) { + uint16 d = 0; + if(spucore_getflag(CORESTATE(core), SPUREG_FLAG_MSNDL )) d |= (1<<11); + if(spucore_getflag(CORESTATE(core), SPUREG_FLAG_MSNDR )) d |= (1<<10); + if(spucore_getflag(CORESTATE(core), SPUREG_FLAG_MSNDEL)) d |= (1<< 9); + if(spucore_getflag(CORESTATE(core), SPUREG_FLAG_MSNDER)) d |= (1<< 8); + if(spucore_getflag(CORESTATE(core), SPUREG_FLAG_MINL )) d |= (1<< 7); + if(spucore_getflag(CORESTATE(core), SPUREG_FLAG_MINR )) d |= (1<< 6); + if(spucore_getflag(CORESTATE(core), SPUREG_FLAG_MINEL )) d |= (1<< 5); + if(spucore_getflag(CORESTATE(core), SPUREG_FLAG_MINER )) d |= (1<< 4); + if(spucore_getflag(CORESTATE(core), SPUREG_FLAG_SINL )) d |= (1<< 3); + if(spucore_getflag(CORESTATE(core), SPUREG_FLAG_SINR )) d |= (1<< 2); + if(spucore_getflag(CORESTATE(core), SPUREG_FLAG_SINEL )) d |= (1<< 1); + if(spucore_getflag(CORESTATE(core), SPUREG_FLAG_SINER )) d |= (1<< 0); + return d; +} + +static void EMU_CALL set_mmix(struct SPU_STATE *state, uint32 core, uint16 d) { + spucore_setflag(CORESTATE(core), SPUREG_FLAG_MSNDL , (d >> 11) & 1); + spucore_setflag(CORESTATE(core), SPUREG_FLAG_MSNDR , (d >> 10) & 1); + spucore_setflag(CORESTATE(core), SPUREG_FLAG_MSNDEL, (d >> 9) & 1); + spucore_setflag(CORESTATE(core), SPUREG_FLAG_MSNDER, (d >> 8) & 1); + spucore_setflag(CORESTATE(core), SPUREG_FLAG_MINL , (d >> 7) & 1); + spucore_setflag(CORESTATE(core), SPUREG_FLAG_MINR , (d >> 6) & 1); + spucore_setflag(CORESTATE(core), SPUREG_FLAG_MINEL , (d >> 5) & 1); + spucore_setflag(CORESTATE(core), SPUREG_FLAG_MINER , (d >> 4) & 1); + spucore_setflag(CORESTATE(core), SPUREG_FLAG_SINL , (d >> 3) & 1); + spucore_setflag(CORESTATE(core), SPUREG_FLAG_SINR , (d >> 2) & 1); + spucore_setflag(CORESTATE(core), SPUREG_FLAG_SINEL , (d >> 1) & 1); + spucore_setflag(CORESTATE(core), SPUREG_FLAG_SINER , (d >> 0) & 1); +} + +//////////////////////////////////////////////////////////////////////////////// +/* +** SPU1 register accesses: lh1/sh1 +*/ + +static uint16 EMU_CALL lh1(struct SPU_STATE *state, uint32 a) { + a &= 0x1FE; + if(a < 0x180) { + uint32 voice = a >> 4; + switch(a & 0xE) { + case 0x0: return spucore_getreg_voice(CORESTATE(0), voice, SPUREG_VOICE_VOLL ); + case 0x2: return spucore_getreg_voice(CORESTATE(0), voice, SPUREG_VOICE_VOLR ); + case 0x4: return spucore_getreg_voice(CORESTATE(0), voice, SPUREG_VOICE_PITCH); + case 0x6: return spucore_getreg_voice(CORESTATE(0), voice, SPUREG_VOICE_SSA ) >> 3; + case 0x8: return spucore_getreg_voice(CORESTATE(0), voice, SPUREG_VOICE_ADSR1); + case 0xA: return spucore_getreg_voice(CORESTATE(0), voice, SPUREG_VOICE_ADSR2); + case 0xC: return spucore_getreg_voice(CORESTATE(0), voice, SPUREG_VOICE_ENVX ); + case 0xE: return spucore_getreg_voice(CORESTATE(0), voice, SPUREG_VOICE_LSAX ) >> 3; + } + } else { + switch(a) { + case 0x180: return spucore_getreg(CORESTATE(0), SPUREG_MVOLL); + case 0x182: return spucore_getreg(CORESTATE(0), SPUREG_MVOLR); + case 0x184: return spucore_getreg(CORESTATE(0), SPUREG_EVOLL); + case 0x186: return spucore_getreg(CORESTATE(0), SPUREG_EVOLR); + case 0x188: return spucore_getreg(CORESTATE(0), SPUREG_KON); + case 0x18A: return spucore_getreg(CORESTATE(0), SPUREG_KON) >> 16; + case 0x18C: return spucore_getreg(CORESTATE(0), SPUREG_KOFF); + case 0x18E: return spucore_getreg(CORESTATE(0), SPUREG_KOFF) >> 16; + case 0x190: return spucore_getreg(CORESTATE(0), SPUREG_FM); + case 0x192: return spucore_getreg(CORESTATE(0), SPUREG_FM) >> 16; + case 0x194: return spucore_getreg(CORESTATE(0), SPUREG_NOISE); + case 0x196: return spucore_getreg(CORESTATE(0), SPUREG_NOISE) >> 16; + case 0x198: return spucore_getreg(CORESTATE(0), SPUREG_VMIXE); + case 0x19A: return spucore_getreg(CORESTATE(0), SPUREG_VMIXE) >> 16; +// case 0x19C: return spucore_getreg(CORESTATE(0), SPUREG_VMIX); +// case 0x19E: return spucore_getreg(CORESTATE(0), SPUREG_VMIX) >> 16; + case 0x19C: return 0; + case 0x19E: return 0; + case 0x1A0: return 0; + case 0x1A2: return spucore_getreg(CORESTATE(0), SPUREG_ESA) >> 3; + case 0x1A4: return spucore_getreg(CORESTATE(0), SPUREG_IRQA) >> 3; + case 0x1A6: return get_tsa (state, 0) >> 3; + case 0x1A8: return get_transfer(state, 0); + case 0x1AA: return get_ctrl (state, 0); + case 0x1AC: return 0; /* TODO: what does this reg do? */ + case 0x1AE: return 0; /* TODO: implement status bits (0 should be ok though) */ + case 0x1B0: return spucore_getreg(CORESTATE(0), SPUREG_AVOLL); + case 0x1B2: return spucore_getreg(CORESTATE(0), SPUREG_AVOLR); + case 0x1B4: return spucore_getreg(CORESTATE(0), SPUREG_BVOLL); + case 0x1B6: return spucore_getreg(CORESTATE(0), SPUREG_BVOLR); + case 0x1B8: return 0; + case 0x1BA: return 0; + case 0x1BC: return 0; + case 0x1BE: return 0; + case 0x1C0: return spucore_getreg(CORESTATE(0), SPUREG_REVERB_FB_SRC_A ) >> 3; + case 0x1C2: return spucore_getreg(CORESTATE(0), SPUREG_REVERB_FB_SRC_B ) >> 3; + case 0x1C4: return spucore_getreg(CORESTATE(0), SPUREG_REVERB_IIR_ALPHA ); + case 0x1C6: return spucore_getreg(CORESTATE(0), SPUREG_REVERB_ACC_COEF_A ); + case 0x1C8: return spucore_getreg(CORESTATE(0), SPUREG_REVERB_ACC_COEF_B ); + case 0x1CA: return spucore_getreg(CORESTATE(0), SPUREG_REVERB_ACC_COEF_C ); + case 0x1CC: return spucore_getreg(CORESTATE(0), SPUREG_REVERB_ACC_COEF_D ); + case 0x1CE: return spucore_getreg(CORESTATE(0), SPUREG_REVERB_IIR_COEF ); + case 0x1D0: return spucore_getreg(CORESTATE(0), SPUREG_REVERB_FB_ALPHA ); + case 0x1D2: return spucore_getreg(CORESTATE(0), SPUREG_REVERB_FB_X ); + case 0x1D4: return spucore_getreg(CORESTATE(0), SPUREG_REVERB_IIR_DEST_A0) >> 3; + case 0x1D6: return spucore_getreg(CORESTATE(0), SPUREG_REVERB_IIR_DEST_A1) >> 3; + case 0x1D8: return spucore_getreg(CORESTATE(0), SPUREG_REVERB_ACC_SRC_A0 ) >> 3; + case 0x1DA: return spucore_getreg(CORESTATE(0), SPUREG_REVERB_ACC_SRC_A1 ) >> 3; + case 0x1DC: return spucore_getreg(CORESTATE(0), SPUREG_REVERB_ACC_SRC_B0 ) >> 3; + case 0x1DE: return spucore_getreg(CORESTATE(0), SPUREG_REVERB_ACC_SRC_B1 ) >> 3; + case 0x1E0: return spucore_getreg(CORESTATE(0), SPUREG_REVERB_IIR_SRC_A0 ) >> 3; + case 0x1E2: return spucore_getreg(CORESTATE(0), SPUREG_REVERB_IIR_SRC_A1 ) >> 3; + case 0x1E4: return spucore_getreg(CORESTATE(0), SPUREG_REVERB_IIR_DEST_B0) >> 3; + case 0x1E6: return spucore_getreg(CORESTATE(0), SPUREG_REVERB_IIR_DEST_B1) >> 3; + case 0x1E8: return spucore_getreg(CORESTATE(0), SPUREG_REVERB_ACC_SRC_C0 ) >> 3; + case 0x1EA: return spucore_getreg(CORESTATE(0), SPUREG_REVERB_ACC_SRC_C1 ) >> 3; + case 0x1EC: return spucore_getreg(CORESTATE(0), SPUREG_REVERB_ACC_SRC_D0 ) >> 3; + case 0x1EE: return spucore_getreg(CORESTATE(0), SPUREG_REVERB_ACC_SRC_D1 ) >> 3; + case 0x1F0: return spucore_getreg(CORESTATE(0), SPUREG_REVERB_IIR_SRC_B1 ) >> 3; + case 0x1F2: return spucore_getreg(CORESTATE(0), SPUREG_REVERB_IIR_SRC_B0 ) >> 3; + case 0x1F4: return spucore_getreg(CORESTATE(0), SPUREG_REVERB_MIX_DEST_A0) >> 3; + case 0x1F6: return spucore_getreg(CORESTATE(0), SPUREG_REVERB_MIX_DEST_A1) >> 3; + case 0x1F8: return spucore_getreg(CORESTATE(0), SPUREG_REVERB_MIX_DEST_B0) >> 3; + case 0x1FA: return spucore_getreg(CORESTATE(0), SPUREG_REVERB_MIX_DEST_B1) >> 3; + case 0x1FC: return spucore_getreg(CORESTATE(0), SPUREG_REVERB_IN_COEF_L ); + case 0x1FE: return spucore_getreg(CORESTATE(0), SPUREG_REVERB_IN_COEF_R ); + } + } + return 0; +} + +static void EMU_CALL sh1(struct SPU_STATE *state, uint32 a, uint16 d) { + a &= 0x1FE; + if(a < 0x180) { + uint32 voice = a >> 4; + switch(a & 0xE) { + case 0x0: spucore_setreg_voice(CORESTATE(0), voice, SPUREG_VOICE_VOLL , d, 0xFFFF); break; + case 0x2: spucore_setreg_voice(CORESTATE(0), voice, SPUREG_VOICE_VOLR , d, 0xFFFF); break; + case 0x4: spucore_setreg_voice(CORESTATE(0), voice, SPUREG_VOICE_PITCH, d, 0xFFFF); break; + case 0x6: spucore_setreg_voice(CORESTATE(0), voice, SPUREG_VOICE_SSA , ((uint32)d) << 3, 0xFFFFFFFF); break; + case 0x8: spucore_setreg_voice(CORESTATE(0), voice, SPUREG_VOICE_ADSR1, d, 0xFFFF); break; + case 0xA: spucore_setreg_voice(CORESTATE(0), voice, SPUREG_VOICE_ADSR2, d, 0xFFFF); break; + case 0xC: spucore_setreg_voice(CORESTATE(0), voice, SPUREG_VOICE_ENVX , d, 0xFFFF); break; + case 0xE: spucore_setreg_voice(CORESTATE(0), voice, SPUREG_VOICE_LSAX , ((uint32)d) << 3, 0xFFFFFFFF); break; + } + } else { + switch(a) { + case 0x180: spucore_setreg (CORESTATE(0), SPUREG_MVOLL, d, 0xFFFF); break; + case 0x182: spucore_setreg (CORESTATE(0), SPUREG_MVOLR, d, 0xFFFF); break; + case 0x184: spucore_setreg (CORESTATE(0), SPUREG_EVOLL, d, 0xFFFF); break; + case 0x186: spucore_setreg (CORESTATE(0), SPUREG_EVOLR, d, 0xFFFF); break; + case 0x188: spucore_setreg (CORESTATE(0), SPUREG_KON , ((uint32)d) << 0, 0x0000FFFF); break; + case 0x18A: spucore_setreg (CORESTATE(0), SPUREG_KON , ((uint32)d) << 16, 0xFFFF0000); break; + case 0x18C: spucore_setreg (CORESTATE(0), SPUREG_KOFF , ((uint32)d) << 0, 0x0000FFFF); break; + case 0x18E: spucore_setreg (CORESTATE(0), SPUREG_KOFF , ((uint32)d) << 16, 0xFFFF0000); break; + case 0x190: spucore_setreg (CORESTATE(0), SPUREG_FM , ((uint32)d) << 0, 0x0000FFFF); break; + case 0x192: spucore_setreg (CORESTATE(0), SPUREG_FM , ((uint32)d) << 16, 0xFFFF0000); break; + case 0x194: spucore_setreg (CORESTATE(0), SPUREG_NOISE, ((uint32)d) << 0, 0x0000FFFF); break; + case 0x196: spucore_setreg (CORESTATE(0), SPUREG_NOISE, ((uint32)d) << 16, 0xFFFF0000); break; + case 0x198: spucore_setreg (CORESTATE(0), SPUREG_VMIXE, ((uint32)d) << 0, 0x0000FFFF); break; + case 0x19A: spucore_setreg (CORESTATE(0), SPUREG_VMIXE, ((uint32)d) << 16, 0xFFFF0000); break; +// case 0x19C: spucore_setreg (CORESTATE(0), SPUREG_VMIX , ((uint32)d) << 0, 0x0000FFFF); break; +// case 0x19E: spucore_setreg (CORESTATE(0), SPUREG_VMIX , ((uint32)d) << 16, 0xFFFF0000); break; + case 0x19C: break; + case 0x19E: break; + case 0x1A0: break; + case 0x1A2: spucore_setreg (CORESTATE(0), SPUREG_ESA , ((uint32)d) << 3, 0xFFFFFFFF); break; + case 0x1A4: spucore_setreg (CORESTATE(0), SPUREG_IRQA, ((uint32)d) << 3, 0xFFFFFFFF); break; + case 0x1A6: set_tsa (state, 0, ((uint32)d) << 3, 0xFFFFFFFF); break; + case 0x1A8: set_transfer(state, 0, d); break; + case 0x1AA: set_ctrl (state, 0, d); break; + case 0x1AC: break; /* TODO: what does this reg do? */ + case 0x1AE: break; /* TODO: implement status bits (0 should be ok though) */ + case 0x1B0: spucore_setreg (CORESTATE(0), SPUREG_AVOLL, d, 0xFFFF); break; + case 0x1B2: spucore_setreg (CORESTATE(0), SPUREG_AVOLR, d, 0xFFFF); break; + case 0x1B4: spucore_setreg (CORESTATE(0), SPUREG_BVOLL, d, 0xFFFF); break; + case 0x1B6: spucore_setreg (CORESTATE(0), SPUREG_BVOLR, d, 0xFFFF); break; + case 0x1B8: break; + case 0x1BA: break; + case 0x1BC: break; + case 0x1BE: break; + case 0x1C0: spucore_setreg(CORESTATE(0), SPUREG_REVERB_FB_SRC_A , ((uint32)d) << 3, 0xFFFFFFFF); break; + case 0x1C2: spucore_setreg(CORESTATE(0), SPUREG_REVERB_FB_SRC_B , ((uint32)d) << 3, 0xFFFFFFFF); break; + case 0x1C4: spucore_setreg(CORESTATE(0), SPUREG_REVERB_IIR_ALPHA , ((uint32)d) , 0x0000FFFF); break; + case 0x1C6: spucore_setreg(CORESTATE(0), SPUREG_REVERB_ACC_COEF_A , ((uint32)d) , 0x0000FFFF); break; + case 0x1C8: spucore_setreg(CORESTATE(0), SPUREG_REVERB_ACC_COEF_B , ((uint32)d) , 0x0000FFFF); break; + case 0x1CA: spucore_setreg(CORESTATE(0), SPUREG_REVERB_ACC_COEF_C , ((uint32)d) , 0x0000FFFF); break; + case 0x1CC: spucore_setreg(CORESTATE(0), SPUREG_REVERB_ACC_COEF_D , ((uint32)d) , 0x0000FFFF); break; + case 0x1CE: spucore_setreg(CORESTATE(0), SPUREG_REVERB_IIR_COEF , ((uint32)d) , 0x0000FFFF); break; + case 0x1D0: spucore_setreg(CORESTATE(0), SPUREG_REVERB_FB_ALPHA , ((uint32)d) , 0x0000FFFF); break; + case 0x1D2: spucore_setreg(CORESTATE(0), SPUREG_REVERB_FB_X , ((uint32)d) , 0x0000FFFF); break; + case 0x1D4: spucore_setreg(CORESTATE(0), SPUREG_REVERB_IIR_DEST_A0, ((uint32)d) << 3, 0xFFFFFFFF); break; + case 0x1D6: spucore_setreg(CORESTATE(0), SPUREG_REVERB_IIR_DEST_A1, ((uint32)d) << 3, 0xFFFFFFFF); break; + case 0x1D8: spucore_setreg(CORESTATE(0), SPUREG_REVERB_ACC_SRC_A0 , ((uint32)d) << 3, 0xFFFFFFFF); break; + case 0x1DA: spucore_setreg(CORESTATE(0), SPUREG_REVERB_ACC_SRC_A1 , ((uint32)d) << 3, 0xFFFFFFFF); break; + case 0x1DC: spucore_setreg(CORESTATE(0), SPUREG_REVERB_ACC_SRC_B0 , ((uint32)d) << 3, 0xFFFFFFFF); break; + case 0x1DE: spucore_setreg(CORESTATE(0), SPUREG_REVERB_ACC_SRC_B1 , ((uint32)d) << 3, 0xFFFFFFFF); break; + case 0x1E0: spucore_setreg(CORESTATE(0), SPUREG_REVERB_IIR_SRC_A0 , ((uint32)d) << 3, 0xFFFFFFFF); break; + case 0x1E2: spucore_setreg(CORESTATE(0), SPUREG_REVERB_IIR_SRC_A1 , ((uint32)d) << 3, 0xFFFFFFFF); break; + case 0x1E4: spucore_setreg(CORESTATE(0), SPUREG_REVERB_IIR_DEST_B0, ((uint32)d) << 3, 0xFFFFFFFF); break; + case 0x1E6: spucore_setreg(CORESTATE(0), SPUREG_REVERB_IIR_DEST_B1, ((uint32)d) << 3, 0xFFFFFFFF); break; + case 0x1E8: spucore_setreg(CORESTATE(0), SPUREG_REVERB_ACC_SRC_C0 , ((uint32)d) << 3, 0xFFFFFFFF); break; + case 0x1EA: spucore_setreg(CORESTATE(0), SPUREG_REVERB_ACC_SRC_C1 , ((uint32)d) << 3, 0xFFFFFFFF); break; + case 0x1EC: spucore_setreg(CORESTATE(0), SPUREG_REVERB_ACC_SRC_D0 , ((uint32)d) << 3, 0xFFFFFFFF); break; + case 0x1EE: spucore_setreg(CORESTATE(0), SPUREG_REVERB_ACC_SRC_D1 , ((uint32)d) << 3, 0xFFFFFFFF); break; + case 0x1F0: spucore_setreg(CORESTATE(0), SPUREG_REVERB_IIR_SRC_B1 , ((uint32)d) << 3, 0xFFFFFFFF); break; + case 0x1F2: spucore_setreg(CORESTATE(0), SPUREG_REVERB_IIR_SRC_B0 , ((uint32)d) << 3, 0xFFFFFFFF); break; + case 0x1F4: spucore_setreg(CORESTATE(0), SPUREG_REVERB_MIX_DEST_A0, ((uint32)d) << 3, 0xFFFFFFFF); break; + case 0x1F6: spucore_setreg(CORESTATE(0), SPUREG_REVERB_MIX_DEST_A1, ((uint32)d) << 3, 0xFFFFFFFF); break; + case 0x1F8: spucore_setreg(CORESTATE(0), SPUREG_REVERB_MIX_DEST_B0, ((uint32)d) << 3, 0xFFFFFFFF); break; + case 0x1FA: spucore_setreg(CORESTATE(0), SPUREG_REVERB_MIX_DEST_B1, ((uint32)d) << 3, 0xFFFFFFFF); break; + case 0x1FC: spucore_setreg(CORESTATE(0), SPUREG_REVERB_IN_COEF_L , ((uint32)d) , 0x0000FFFF); break; + case 0x1FE: spucore_setreg(CORESTATE(0), SPUREG_REVERB_IN_COEF_R , ((uint32)d) , 0x0000FFFF); break; + } + } +} + +//////////////////////////////////////////////////////////////////////////////// +/* +** SPU2 register accesses: lh2/sh2 +*/ + +/* +** Returns "normalized to core0" address +** Also sets *core to 0 or 1 +*/ +static EMU_INLINE uint32 EMU_CALL spu2_reg_addr_normal(uint32 a, uint32 *core) { + a &= 0x7FE; + if(a < 0x400) { *core = 0; return a; } + if(a < 0x760) { *core = 1; return a-0x400; } + if(a < 0x788) { *core = 0; return a; } + if(a < 0x7B0) { *core = 1; return a-0x28; } + *core = 0; return a; +} + +static uint16 EMU_CALL lh2(struct SPU_STATE *state, uint32 a) { + uint32 core = 0; a = spu2_reg_addr_normal(a, &core); + if(a < 0x180) { + uint32 voice = a >> 4; + switch(a & 0xE) { + case 0x0: return spucore_getreg_voice(CORESTATE(core), voice, SPUREG_VOICE_VOLL ); + case 0x2: return spucore_getreg_voice(CORESTATE(core), voice, SPUREG_VOICE_VOLR ); + case 0x4: return spucore_getreg_voice(CORESTATE(core), voice, SPUREG_VOICE_PITCH); + case 0x6: return spucore_getreg_voice(CORESTATE(core), voice, SPUREG_VOICE_ADSR1); + case 0x8: return spucore_getreg_voice(CORESTATE(core), voice, SPUREG_VOICE_ADSR2); + case 0xA: return spucore_getreg_voice(CORESTATE(core), voice, SPUREG_VOICE_ENVX ); + case 0xC: return spucore_getreg_voice(CORESTATE(core), voice, SPUREG_VOICE_VOLXL); + case 0xE: return spucore_getreg_voice(CORESTATE(core), voice, SPUREG_VOICE_VOLXR); + } + } else if(a < 0x1C0) { + switch(a) { + case 0x180: return spucore_getreg(CORESTATE(core), SPUREG_FM); + case 0x182: return spucore_getreg(CORESTATE(core), SPUREG_FM) >> 16; + case 0x184: return spucore_getreg(CORESTATE(core), SPUREG_NOISE); + case 0x186: return spucore_getreg(CORESTATE(core), SPUREG_NOISE) >> 16; + case 0x188: return spucore_getreg(CORESTATE(core), SPUREG_VMIXL); + case 0x18A: return spucore_getreg(CORESTATE(core), SPUREG_VMIXL) >> 16; + case 0x18C: return spucore_getreg(CORESTATE(core), SPUREG_VMIXEL); + case 0x18E: return spucore_getreg(CORESTATE(core), SPUREG_VMIXEL) >> 16; + case 0x190: return spucore_getreg(CORESTATE(core), SPUREG_VMIXR); + case 0x192: return spucore_getreg(CORESTATE(core), SPUREG_VMIXR) >> 16; + case 0x194: return spucore_getreg(CORESTATE(core), SPUREG_VMIXER); + case 0x196: return spucore_getreg(CORESTATE(core), SPUREG_VMIXER) >> 16; + case 0x198: return get_mmix(state, core); + case 0x19A: return get_ctrl(state, core); + case 0x19C: return spucore_getreg(CORESTATE(core), SPUREG_IRQA) >> 17; + case 0x19E: return spucore_getreg(CORESTATE(core), SPUREG_IRQA) >> 1; + case 0x1A0: return spucore_getreg(CORESTATE(core), SPUREG_KON); + case 0x1A2: return spucore_getreg(CORESTATE(core), SPUREG_KON) >> 16; + case 0x1A4: return spucore_getreg(CORESTATE(core), SPUREG_KOFF); + case 0x1A6: return spucore_getreg(CORESTATE(core), SPUREG_KOFF) >> 16; + case 0x1A8: return get_tsa(state, core) >> 17; + case 0x1AA: return get_tsa(state, core) >> 1; + case 0x1AC: return get_transfer(state, core); + case 0x1AE: return 0; // do not know what this is yet but it may be important + case 0x1B0: return 0; // do not know what this is yet but it may be important + case 0x1B2: return 0; + case 0x1B4: return 0; + case 0x1B6: return 0; + case 0x1B8: return 0; + case 0x1BA: return 0; + case 0x1BC: return 0; + case 0x1BE: return 0; + } + } else if(a < 0x2E0) { + uint32 voice = (a-0x1C0)/12; + switch((a-0x1C0)%12) { + case 0x0: return spucore_getreg_voice(CORESTATE(core), voice, SPUREG_VOICE_SSA ) >> 17; + case 0x2: return spucore_getreg_voice(CORESTATE(core), voice, SPUREG_VOICE_SSA ) >> 1; + case 0x4: return spucore_getreg_voice(CORESTATE(core), voice, SPUREG_VOICE_LSAX) >> 17; + case 0x6: return spucore_getreg_voice(CORESTATE(core), voice, SPUREG_VOICE_LSAX) >> 1; + case 0x8: return spucore_getreg_voice(CORESTATE(core), voice, SPUREG_VOICE_NAX ) >> 17; + case 0xA: return spucore_getreg_voice(CORESTATE(core), voice, SPUREG_VOICE_NAX ) >> 1; + } + } else { + switch(a) { + case 0x2E0: return spucore_getreg(CORESTATE(core), SPUREG_ESA) >> 17; + case 0x2E2: return spucore_getreg(CORESTATE(core), SPUREG_ESA) >> 1; + case 0x2E4: return spucore_getreg(CORESTATE(core), SPUREG_REVERB_FB_SRC_A ) >> 17; + case 0x2E6: return spucore_getreg(CORESTATE(core), SPUREG_REVERB_FB_SRC_A ) >> 1; + case 0x2E8: return spucore_getreg(CORESTATE(core), SPUREG_REVERB_FB_SRC_B ) >> 17; + case 0x2EA: return spucore_getreg(CORESTATE(core), SPUREG_REVERB_FB_SRC_B ) >> 1; + case 0x2EC: return spucore_getreg(CORESTATE(core), SPUREG_REVERB_IIR_DEST_A0) >> 17; + case 0x2EE: return spucore_getreg(CORESTATE(core), SPUREG_REVERB_IIR_DEST_A0) >> 1; + case 0x2F0: return spucore_getreg(CORESTATE(core), SPUREG_REVERB_IIR_DEST_A1) >> 17; + case 0x2F2: return spucore_getreg(CORESTATE(core), SPUREG_REVERB_IIR_DEST_A1) >> 1; + case 0x2F4: return spucore_getreg(CORESTATE(core), SPUREG_REVERB_ACC_SRC_A0 ) >> 17; + case 0x2F6: return spucore_getreg(CORESTATE(core), SPUREG_REVERB_ACC_SRC_A0 ) >> 1; + case 0x2F8: return spucore_getreg(CORESTATE(core), SPUREG_REVERB_ACC_SRC_A1 ) >> 17; + case 0x2FA: return spucore_getreg(CORESTATE(core), SPUREG_REVERB_ACC_SRC_A1 ) >> 1; + case 0x2FC: return spucore_getreg(CORESTATE(core), SPUREG_REVERB_ACC_SRC_B0 ) >> 17; + case 0x2FE: return spucore_getreg(CORESTATE(core), SPUREG_REVERB_ACC_SRC_B0 ) >> 1; + case 0x300: return spucore_getreg(CORESTATE(core), SPUREG_REVERB_ACC_SRC_B1 ) >> 17; + case 0x302: return spucore_getreg(CORESTATE(core), SPUREG_REVERB_ACC_SRC_B1 ) >> 1; + case 0x304: return spucore_getreg(CORESTATE(core), SPUREG_REVERB_IIR_SRC_A0 ) >> 17; + case 0x306: return spucore_getreg(CORESTATE(core), SPUREG_REVERB_IIR_SRC_A0 ) >> 1; + case 0x308: return spucore_getreg(CORESTATE(core), SPUREG_REVERB_IIR_SRC_A1 ) >> 17; + case 0x30A: return spucore_getreg(CORESTATE(core), SPUREG_REVERB_IIR_SRC_A1 ) >> 1; + case 0x30C: return spucore_getreg(CORESTATE(core), SPUREG_REVERB_IIR_DEST_B0) >> 17; + case 0x30E: return spucore_getreg(CORESTATE(core), SPUREG_REVERB_IIR_DEST_B0) >> 1; + case 0x310: return spucore_getreg(CORESTATE(core), SPUREG_REVERB_IIR_DEST_B1) >> 17; + case 0x312: return spucore_getreg(CORESTATE(core), SPUREG_REVERB_IIR_DEST_B1) >> 1; + case 0x314: return spucore_getreg(CORESTATE(core), SPUREG_REVERB_ACC_SRC_C0 ) >> 17; + case 0x316: return spucore_getreg(CORESTATE(core), SPUREG_REVERB_ACC_SRC_C0 ) >> 1; + case 0x318: return spucore_getreg(CORESTATE(core), SPUREG_REVERB_ACC_SRC_C1 ) >> 17; + case 0x31A: return spucore_getreg(CORESTATE(core), SPUREG_REVERB_ACC_SRC_C1 ) >> 1; + case 0x31C: return spucore_getreg(CORESTATE(core), SPUREG_REVERB_ACC_SRC_D0 ) >> 17; + case 0x31E: return spucore_getreg(CORESTATE(core), SPUREG_REVERB_ACC_SRC_D0 ) >> 1; + case 0x320: return spucore_getreg(CORESTATE(core), SPUREG_REVERB_ACC_SRC_D1 ) >> 17; + case 0x322: return spucore_getreg(CORESTATE(core), SPUREG_REVERB_ACC_SRC_D1 ) >> 1; + case 0x324: return spucore_getreg(CORESTATE(core), SPUREG_REVERB_IIR_SRC_B1 ) >> 17; + case 0x326: return spucore_getreg(CORESTATE(core), SPUREG_REVERB_IIR_SRC_B1 ) >> 1; + case 0x328: return spucore_getreg(CORESTATE(core), SPUREG_REVERB_IIR_SRC_B0 ) >> 17; + case 0x32A: return spucore_getreg(CORESTATE(core), SPUREG_REVERB_IIR_SRC_B0 ) >> 1; + case 0x32C: return spucore_getreg(CORESTATE(core), SPUREG_REVERB_MIX_DEST_A0) >> 17; + case 0x32E: return spucore_getreg(CORESTATE(core), SPUREG_REVERB_MIX_DEST_A0) >> 1; + case 0x330: return spucore_getreg(CORESTATE(core), SPUREG_REVERB_MIX_DEST_A1) >> 17; + case 0x332: return spucore_getreg(CORESTATE(core), SPUREG_REVERB_MIX_DEST_A1) >> 1; + case 0x334: return spucore_getreg(CORESTATE(core), SPUREG_REVERB_MIX_DEST_B0) >> 17; + case 0x336: return spucore_getreg(CORESTATE(core), SPUREG_REVERB_MIX_DEST_B0) >> 1; + case 0x338: return spucore_getreg(CORESTATE(core), SPUREG_REVERB_MIX_DEST_B1) >> 17; + case 0x33A: return spucore_getreg(CORESTATE(core), SPUREG_REVERB_MIX_DEST_B1) >> 1; + case 0x33C: return spucore_getreg(CORESTATE(core), SPUREG_EEA) >> 17; + case 0x33E: return spucore_getreg(CORESTATE(core), SPUREG_EEA) >> 1; + case 0x340: return spucore_getreg(CORESTATE(core), SPUREG_EAX) >> 17; + case 0x342: return spucore_getreg(CORESTATE(core), SPUREG_EAX) >> 1; + case 0x344: return get_mystery_dma(state, core); + case 0x760: return spucore_getreg(CORESTATE(core), SPUREG_MVOLL); + case 0x762: return spucore_getreg(CORESTATE(core), SPUREG_MVOLR); + case 0x764: return spucore_getreg(CORESTATE(core), SPUREG_EVOLL); + case 0x766: return spucore_getreg(CORESTATE(core), SPUREG_EVOLR); + case 0x768: return spucore_getreg(CORESTATE(core), SPUREG_AVOLL); + case 0x76A: return spucore_getreg(CORESTATE(core), SPUREG_AVOLR); + case 0x76C: return spucore_getreg(CORESTATE(core), SPUREG_BVOLL); + case 0x76E: return spucore_getreg(CORESTATE(core), SPUREG_BVOLR); + case 0x770: return spucore_getreg(CORESTATE(core), SPUREG_MVOLXL); + case 0x772: return spucore_getreg(CORESTATE(core), SPUREG_MVOLXR); + case 0x774: return spucore_getreg(CORESTATE(core), SPUREG_REVERB_IIR_ALPHA ); + case 0x776: return spucore_getreg(CORESTATE(core), SPUREG_REVERB_ACC_COEF_A); + case 0x778: return spucore_getreg(CORESTATE(core), SPUREG_REVERB_ACC_COEF_B); + case 0x77A: return spucore_getreg(CORESTATE(core), SPUREG_REVERB_ACC_COEF_C); + case 0x77C: return spucore_getreg(CORESTATE(core), SPUREG_REVERB_ACC_COEF_D); + case 0x77E: return spucore_getreg(CORESTATE(core), SPUREG_REVERB_IIR_COEF ); + case 0x780: return spucore_getreg(CORESTATE(core), SPUREG_REVERB_FB_ALPHA ); + case 0x782: return spucore_getreg(CORESTATE(core), SPUREG_REVERB_FB_X ); + case 0x784: return spucore_getreg(CORESTATE(core), SPUREG_REVERB_IN_COEF_L ); + case 0x786: return spucore_getreg(CORESTATE(core), SPUREG_REVERB_IN_COEF_R ); + } + } + return 0; +} + +static void EMU_CALL sh2(struct SPU_STATE *state, uint32 a, uint16 d) { + uint32 core = 0; a = spu2_reg_addr_normal(a, &core); + if(a < 0x180) { + uint32 voice = a >> 4; + switch(a & 0xE) { + case 0x0: spucore_setreg_voice(CORESTATE(core), voice, SPUREG_VOICE_VOLL , d, 0xFFFF); break; + case 0x2: spucore_setreg_voice(CORESTATE(core), voice, SPUREG_VOICE_VOLR , d, 0xFFFF); break; + case 0x4: spucore_setreg_voice(CORESTATE(core), voice, SPUREG_VOICE_PITCH, d, 0xFFFF); break; + case 0x6: spucore_setreg_voice(CORESTATE(core), voice, SPUREG_VOICE_ADSR1, d, 0xFFFF); break; + case 0x8: spucore_setreg_voice(CORESTATE(core), voice, SPUREG_VOICE_ADSR2, d, 0xFFFF); break; + case 0xA: break; /* ENVX is read-only */ + case 0xC: break; /* VOLXL is read-only */ + case 0xE: break; /* VOLXR is read-only */ + } + } else if(a < 0x1C0) { + switch(a) { + case 0x180: spucore_setreg(CORESTATE(core), SPUREG_FM , ((uint32)d) , 0x0000FFFF); break; + case 0x182: spucore_setreg(CORESTATE(core), SPUREG_FM , ((uint32)d) << 16, 0xFFFF0000); break; + case 0x184: spucore_setreg(CORESTATE(core), SPUREG_NOISE , ((uint32)d) , 0x0000FFFF); break; + case 0x186: spucore_setreg(CORESTATE(core), SPUREG_NOISE , ((uint32)d) << 16, 0xFFFF0000); break; + case 0x188: spucore_setreg(CORESTATE(core), SPUREG_VMIXL , ((uint32)d) , 0x0000FFFF); break; + case 0x18A: spucore_setreg(CORESTATE(core), SPUREG_VMIXL , ((uint32)d) << 16, 0xFFFF0000); break; + case 0x18C: spucore_setreg(CORESTATE(core), SPUREG_VMIXEL, ((uint32)d) , 0x0000FFFF); break; + case 0x18E: spucore_setreg(CORESTATE(core), SPUREG_VMIXEL, ((uint32)d) << 16, 0xFFFF0000); break; + case 0x190: spucore_setreg(CORESTATE(core), SPUREG_VMIXR , ((uint32)d) , 0x0000FFFF); break; + case 0x192: spucore_setreg(CORESTATE(core), SPUREG_VMIXR , ((uint32)d) << 16, 0xFFFF0000); break; + case 0x194: spucore_setreg(CORESTATE(core), SPUREG_VMIXER, ((uint32)d) , 0x0000FFFF); break; + case 0x196: spucore_setreg(CORESTATE(core), SPUREG_VMIXER, ((uint32)d) << 16, 0xFFFF0000); break; + case 0x198: set_mmix(state, core, d); break; + case 0x19A: set_ctrl(state, core, d); break; + case 0x19C: spucore_setreg(CORESTATE(core), SPUREG_IRQA, ((uint32)d) << 17, 0xFFFE0000); break; + case 0x19E: spucore_setreg(CORESTATE(core), SPUREG_IRQA, ((uint32)d) << 1 , 0x0001FFFF); break; + case 0x1A0: spucore_setreg(CORESTATE(core), SPUREG_KON , ((uint32)d) , 0x0000FFFF); break; + case 0x1A2: spucore_setreg(CORESTATE(core), SPUREG_KON , ((uint32)d) << 16, 0xFFFF0000); break; + case 0x1A4: spucore_setreg(CORESTATE(core), SPUREG_KOFF, ((uint32)d) , 0x0000FFFF); break; + case 0x1A6: spucore_setreg(CORESTATE(core), SPUREG_KOFF, ((uint32)d) << 16, 0xFFFF0000); break; + case 0x1A8: set_tsa(state, core, ((uint32)d) << 17, 0xFFFE0000); break; + case 0x1AA: set_tsa(state, core, ((uint32)d) << 1 , 0x0001FFFF); break; + case 0x1AC: set_transfer(state, core, d); break; + case 0x1AE: break; // do not know what this is yet but it may be important + case 0x1B0: break; // do not know what this is yet but it may be important + case 0x1B2: break; + case 0x1B4: break; + case 0x1B6: break; + case 0x1B8: break; + case 0x1BA: break; + case 0x1BC: break; + case 0x1BE: break; + } + } else if(a < 0x2E0) { + uint32 voice = (a-0x1C0)/12; + switch((a-0x1C0)%12) { + case 0x0: spucore_setreg_voice(CORESTATE(core), voice, SPUREG_VOICE_SSA , ((uint32)d) << 17, 0xFFFE0000); break; + case 0x2: spucore_setreg_voice(CORESTATE(core), voice, SPUREG_VOICE_SSA , ((uint32)d) << 1 , 0x0001FFFF); break; + case 0x4: spucore_setreg_voice(CORESTATE(core), voice, SPUREG_VOICE_LSAX, ((uint32)d) << 17, 0xFFFE0000); break; + case 0x6: spucore_setreg_voice(CORESTATE(core), voice, SPUREG_VOICE_LSAX, ((uint32)d) << 1 , 0x0001FFFF); break; + case 0x8: break; /* NAX is read-only */ + case 0xA: break; /* NAX is read-only */ + } + } else { + switch(a) { + case 0x2E0: spucore_setreg(CORESTATE(core), SPUREG_ESA , ((uint32)d) << 17, 0xFFFE0000); break; + case 0x2E2: spucore_setreg(CORESTATE(core), SPUREG_ESA , ((uint32)d) << 1 , 0x0001FFFF); break; + case 0x2E4: spucore_setreg(CORESTATE(core), SPUREG_REVERB_FB_SRC_A , ((uint32)d) << 17, 0xFFFE0000); break; + case 0x2E6: spucore_setreg(CORESTATE(core), SPUREG_REVERB_FB_SRC_A , ((uint32)d) << 1 , 0x0001FFFF); break; + case 0x2E8: spucore_setreg(CORESTATE(core), SPUREG_REVERB_FB_SRC_B , ((uint32)d) << 17, 0xFFFE0000); break; + case 0x2EA: spucore_setreg(CORESTATE(core), SPUREG_REVERB_FB_SRC_B , ((uint32)d) << 1 , 0x0001FFFF); break; + case 0x2EC: spucore_setreg(CORESTATE(core), SPUREG_REVERB_IIR_DEST_A0, ((uint32)d) << 17, 0xFFFE0000); break; + case 0x2EE: spucore_setreg(CORESTATE(core), SPUREG_REVERB_IIR_DEST_A0, ((uint32)d) << 1 , 0x0001FFFF); break; + case 0x2F0: spucore_setreg(CORESTATE(core), SPUREG_REVERB_IIR_DEST_A1, ((uint32)d) << 17, 0xFFFE0000); break; + case 0x2F2: spucore_setreg(CORESTATE(core), SPUREG_REVERB_IIR_DEST_A1, ((uint32)d) << 1 , 0x0001FFFF); break; + case 0x2F4: spucore_setreg(CORESTATE(core), SPUREG_REVERB_ACC_SRC_A0 , ((uint32)d) << 17, 0xFFFE0000); break; + case 0x2F6: spucore_setreg(CORESTATE(core), SPUREG_REVERB_ACC_SRC_A0 , ((uint32)d) << 1 , 0x0001FFFF); break; + case 0x2F8: spucore_setreg(CORESTATE(core), SPUREG_REVERB_ACC_SRC_A1 , ((uint32)d) << 17, 0xFFFE0000); break; + case 0x2FA: spucore_setreg(CORESTATE(core), SPUREG_REVERB_ACC_SRC_A1 , ((uint32)d) << 1 , 0x0001FFFF); break; + case 0x2FC: spucore_setreg(CORESTATE(core), SPUREG_REVERB_ACC_SRC_B0 , ((uint32)d) << 17, 0xFFFE0000); break; + case 0x2FE: spucore_setreg(CORESTATE(core), SPUREG_REVERB_ACC_SRC_B0 , ((uint32)d) << 1 , 0x0001FFFF); break; + case 0x300: spucore_setreg(CORESTATE(core), SPUREG_REVERB_ACC_SRC_B1 , ((uint32)d) << 17, 0xFFFE0000); break; + case 0x302: spucore_setreg(CORESTATE(core), SPUREG_REVERB_ACC_SRC_B1 , ((uint32)d) << 1 , 0x0001FFFF); break; + case 0x304: spucore_setreg(CORESTATE(core), SPUREG_REVERB_IIR_SRC_A0 , ((uint32)d) << 17, 0xFFFE0000); break; + case 0x306: spucore_setreg(CORESTATE(core), SPUREG_REVERB_IIR_SRC_A0 , ((uint32)d) << 1 , 0x0001FFFF); break; + case 0x308: spucore_setreg(CORESTATE(core), SPUREG_REVERB_IIR_SRC_A1 , ((uint32)d) << 17, 0xFFFE0000); break; + case 0x30A: spucore_setreg(CORESTATE(core), SPUREG_REVERB_IIR_SRC_A1 , ((uint32)d) << 1 , 0x0001FFFF); break; + case 0x30C: spucore_setreg(CORESTATE(core), SPUREG_REVERB_IIR_DEST_B0, ((uint32)d) << 17, 0xFFFE0000); break; + case 0x30E: spucore_setreg(CORESTATE(core), SPUREG_REVERB_IIR_DEST_B0, ((uint32)d) << 1 , 0x0001FFFF); break; + case 0x310: spucore_setreg(CORESTATE(core), SPUREG_REVERB_IIR_DEST_B1, ((uint32)d) << 17, 0xFFFE0000); break; + case 0x312: spucore_setreg(CORESTATE(core), SPUREG_REVERB_IIR_DEST_B1, ((uint32)d) << 1 , 0x0001FFFF); break; + case 0x314: spucore_setreg(CORESTATE(core), SPUREG_REVERB_ACC_SRC_C0 , ((uint32)d) << 17, 0xFFFE0000); break; + case 0x316: spucore_setreg(CORESTATE(core), SPUREG_REVERB_ACC_SRC_C0 , ((uint32)d) << 1 , 0x0001FFFF); break; + case 0x318: spucore_setreg(CORESTATE(core), SPUREG_REVERB_ACC_SRC_C1 , ((uint32)d) << 17, 0xFFFE0000); break; + case 0x31A: spucore_setreg(CORESTATE(core), SPUREG_REVERB_ACC_SRC_C1 , ((uint32)d) << 1 , 0x0001FFFF); break; + case 0x31C: spucore_setreg(CORESTATE(core), SPUREG_REVERB_ACC_SRC_D0 , ((uint32)d) << 17, 0xFFFE0000); break; + case 0x31E: spucore_setreg(CORESTATE(core), SPUREG_REVERB_ACC_SRC_D0 , ((uint32)d) << 1 , 0x0001FFFF); break; + case 0x320: spucore_setreg(CORESTATE(core), SPUREG_REVERB_ACC_SRC_D1 , ((uint32)d) << 17, 0xFFFE0000); break; + case 0x322: spucore_setreg(CORESTATE(core), SPUREG_REVERB_ACC_SRC_D1 , ((uint32)d) << 1 , 0x0001FFFF); break; + case 0x324: spucore_setreg(CORESTATE(core), SPUREG_REVERB_IIR_SRC_B1 , ((uint32)d) << 17, 0xFFFE0000); break; + case 0x326: spucore_setreg(CORESTATE(core), SPUREG_REVERB_IIR_SRC_B1 , ((uint32)d) << 1 , 0x0001FFFF); break; + case 0x328: spucore_setreg(CORESTATE(core), SPUREG_REVERB_IIR_SRC_B0 , ((uint32)d) << 17, 0xFFFE0000); break; + case 0x32A: spucore_setreg(CORESTATE(core), SPUREG_REVERB_IIR_SRC_B0 , ((uint32)d) << 1 , 0x0001FFFF); break; + case 0x32C: spucore_setreg(CORESTATE(core), SPUREG_REVERB_MIX_DEST_A0, ((uint32)d) << 17, 0xFFFE0000); break; + case 0x32E: spucore_setreg(CORESTATE(core), SPUREG_REVERB_MIX_DEST_A0, ((uint32)d) << 1 , 0x0001FFFF); break; + case 0x330: spucore_setreg(CORESTATE(core), SPUREG_REVERB_MIX_DEST_A1, ((uint32)d) << 17, 0xFFFE0000); break; + case 0x332: spucore_setreg(CORESTATE(core), SPUREG_REVERB_MIX_DEST_A1, ((uint32)d) << 1 , 0x0001FFFF); break; + case 0x334: spucore_setreg(CORESTATE(core), SPUREG_REVERB_MIX_DEST_B0, ((uint32)d) << 17, 0xFFFE0000); break; + case 0x336: spucore_setreg(CORESTATE(core), SPUREG_REVERB_MIX_DEST_B0, ((uint32)d) << 1 , 0x0001FFFF); break; + case 0x338: spucore_setreg(CORESTATE(core), SPUREG_REVERB_MIX_DEST_B1, ((uint32)d) << 17, 0xFFFE0000); break; + case 0x33A: spucore_setreg(CORESTATE(core), SPUREG_REVERB_MIX_DEST_B1, ((uint32)d) << 1 , 0x0001FFFF); break; + case 0x33C: spucore_setreg(CORESTATE(core), SPUREG_EEA , ((uint32)d) << 17, 0xFFFE0000); break; + case 0x33E: spucore_setreg(CORESTATE(core), SPUREG_EEA , ((uint32)d) << 1 , 0x0001FFFF); break; + case 0x340: spucore_setreg(CORESTATE(core), SPUREG_EAX , ((uint32)d) << 17, 0xFFFE0000); break; + case 0x342: spucore_setreg(CORESTATE(core), SPUREG_EAX , ((uint32)d) << 1 , 0x0001FFFF); break; + case 0x344: set_mystery_dma(state, core, d); break; + case 0x760: spucore_setreg(CORESTATE(core), SPUREG_MVOLL, d, 0xFFFF); break; + case 0x762: spucore_setreg(CORESTATE(core), SPUREG_MVOLR, d, 0xFFFF); break; + case 0x764: spucore_setreg(CORESTATE(core), SPUREG_EVOLL, d, 0xFFFF); break; + case 0x766: spucore_setreg(CORESTATE(core), SPUREG_EVOLR, d, 0xFFFF); break; + case 0x768: spucore_setreg(CORESTATE(core), SPUREG_AVOLL, d, 0xFFFF); break; + case 0x76A: spucore_setreg(CORESTATE(core), SPUREG_AVOLR, d, 0xFFFF); break; + case 0x76C: spucore_setreg(CORESTATE(core), SPUREG_BVOLL, d, 0xFFFF); break; + case 0x76E: spucore_setreg(CORESTATE(core), SPUREG_BVOLR, d, 0xFFFF); break; + case 0x770: break; /* MVOLXL is read-only */ + case 0x772: break; /* MVOLXR is read-only */ + case 0x774: spucore_setreg(CORESTATE(core), SPUREG_REVERB_IIR_ALPHA , d, 0xFFFF); break; + case 0x776: spucore_setreg(CORESTATE(core), SPUREG_REVERB_ACC_COEF_A, d, 0xFFFF); break; + case 0x778: spucore_setreg(CORESTATE(core), SPUREG_REVERB_ACC_COEF_B, d, 0xFFFF); break; + case 0x77A: spucore_setreg(CORESTATE(core), SPUREG_REVERB_ACC_COEF_C, d, 0xFFFF); break; + case 0x77C: spucore_setreg(CORESTATE(core), SPUREG_REVERB_ACC_COEF_D, d, 0xFFFF); break; + case 0x77E: spucore_setreg(CORESTATE(core), SPUREG_REVERB_IIR_COEF , d, 0xFFFF); break; + case 0x780: spucore_setreg(CORESTATE(core), SPUREG_REVERB_FB_ALPHA , d, 0xFFFF); break; + case 0x782: spucore_setreg(CORESTATE(core), SPUREG_REVERB_FB_X , d, 0xFFFF); break; + case 0x784: spucore_setreg(CORESTATE(core), SPUREG_REVERB_IN_COEF_L , d, 0xFFFF); break; + case 0x786: spucore_setreg(CORESTATE(core), SPUREG_REVERB_IN_COEF_R , d, 0xFFFF); break; + } + } +} + +//////////////////////////////////////////////////////////////////////////////// +/* +** Externally-accessible lh/sh +*/ + +uint16 EMU_CALL spu_lh(void *state, uint32 a) { + a &= 0x1FFFFFFE; + if(a >= 0x1F801C00 && a <= 0x1F801DFF) { + return lh1(SPUSTATE, a); + } else if(a >= 0x1F900000 && a <= 0x1F9007FF) { + if(SPUSTATE->version == 2) return lh2(SPUSTATE, a); + } + return 0; +} + +void EMU_CALL spu_sh(void *state, uint32 a, uint16 d) { + a &= 0x1FFFFFFE; + if(a >= 0x1F801C00 && a <= 0x1F801DFF) { + sh1(SPUSTATE, a, d); + } else if(a >= 0x1F900000 && a <= 0x1F9007FF) { + if(SPUSTATE->version == 2) sh2(SPUSTATE, a, d); + } +} + +//////////////////////////////////////////////////////////////////////////////// + +void EMU_CALL spu_render(void *state, sint16 *buf, uint32 samples) { + + uint8 mainout = SPUSTATE->global_main_on; + uint8 effectout = SPUSTATE->global_effect_on; +// mainout = 0; + if(SPUSTATE->version == 1) { + spucore_render(CORESTATE(0), SPURAM, buf, NULL, samples, mainout, effectout); + } else { + spucore_render(CORESTATE(0), SPURAM, buf, NULL, samples, mainout, effectout); + spucore_render(CORESTATE(1), SPURAM, buf, buf , samples, mainout, effectout); +// spucore_render(CORESTATE(1), SPURAM, buf, NULL, samples); + } +} + +//////////////////////////////////////////////////////////////////////////////// + +void EMU_CALL spu_render_ext(void *state, sint16 *buf, sint16 *ext, uint32 samples) { + + uint8 mainout = SPUSTATE->global_main_on; + uint8 effectout = SPUSTATE->global_effect_on; +// mainout = 0; + if(SPUSTATE->version == 1) { + spucore_render(CORESTATE(0), SPURAM, buf, ext, samples, mainout, effectout); + } else { + spucore_render(CORESTATE(0), SPURAM, buf, ext, samples, mainout, effectout); + spucore_render(CORESTATE(1), SPURAM, buf, buf, samples, mainout, effectout); +// spucore_render(CORESTATE(1), SPURAM, buf, NULL, samples); + } +} + +//////////////////////////////////////////////////////////////////////////////// + +uint32 EMU_CALL spu_cycles_until_interrupt(void *state, uint32 samples) { + if(SPUSTATE->version == 1) { + return spucore_cycles_until_interrupt(CORESTATE(0), SPURAM, samples); + } else { + uint32 cycles1 = spucore_cycles_until_interrupt(CORESTATE(0), SPURAM, samples); + uint32 cycles2 = spucore_cycles_until_interrupt(CORESTATE(1), SPURAM, samples); + return cycles1 < cycles2 ? cycles1 : cycles2; + } +} + +//////////////////////////////////////////////////////////////////////////////// diff --git a/Frameworks/HighlyExperimental/HighlyExperimental/Core/spu.h b/Frameworks/HighlyExperimental/HighlyExperimental/Core/spu.h new file mode 100644 index 000000000..1eb014e98 --- /dev/null +++ b/Frameworks/HighlyExperimental/HighlyExperimental/Core/spu.h @@ -0,0 +1,40 @@ +///////////////////////////////////////////////////////////////////////////// +// +// spu - Top-level SPU emulation, for SPU and SPU2 +// +///////////////////////////////////////////////////////////////////////////// + +#ifndef __PSX_SPU_H__ +#define __PSX_SPU_H__ + +#include "emuconfig.h" + +#ifdef __cplusplus +extern "C" { +#endif + +sint32 EMU_CALL spu_init(void); +/* version = 1 for PS1, 2 for PS2 */ +uint32 EMU_CALL spu_get_state_size(uint8 version); +void EMU_CALL spu_clear_state(void *state, uint8 version); + +void EMU_CALL spu_render (void *state, sint16 *buf, uint32 samples); +void EMU_CALL spu_render_ext(void *state, sint16 *buf, sint16 *ext, uint32 samples); +uint16 EMU_CALL spu_lh(void *state, uint32 a); +void EMU_CALL spu_sh(void *state, uint32 a, uint16 d); + +void EMU_CALL spu_dma(void *state, uint32 core, void *mem, uint32 mem_ofs, uint32 mem_mask, uint32 bytes, int iswrite); + +uint32 EMU_CALL spu_cycles_until_interrupt(void *state, uint32 samples); + +/* +** Enable/disable main or reverb +*/ +void EMU_CALL spu_enable_main(void *state, uint8 enable); +void EMU_CALL spu_enable_reverb(void *state, uint8 enable); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Frameworks/HighlyExperimental/HighlyExperimental/Core/spucore.c b/Frameworks/HighlyExperimental/HighlyExperimental/Core/spucore.c new file mode 100644 index 000000000..d076bf683 --- /dev/null +++ b/Frameworks/HighlyExperimental/HighlyExperimental/Core/spucore.c @@ -0,0 +1,2127 @@ +///////////////////////////////////////////////////////////////////////////// +// +// spucore - Emulates a single SPU CORE +// +///////////////////////////////////////////////////////////////////////////// + +#ifndef EMU_COMPILE +#error "Hi I forgot to set EMU_COMPILE" +#endif + +#include "spucore.h" + +//////////////////////////////////////////////////////////////////////////////// +/* +** Key-on defer +** +** Bit of a hack I did to stop the clicking in Final Fantasy Tactics +** If there's a key-on while the envelope is still active, the key-on is +** deferred by this many samples while the existing channel is microramped +** down to zero (works best if it's a power of 2) +*/ + +//#define KEYON_DEFER_SAMPLES (64) +#define KEYON_DEFER_SAMPLES (64) + +// +// Render max samples +// +#define RENDERMAX (200) + +//////////////////////////////////////////////////////////////////////////////// +/* +** Static information +*/ +static const sint16 gauss_shuffled_reverse_table[1024] = { + 0x12c7, 0x59b3, 0x1307, 0xffff, 0x1288, 0x59b2, 0x1347, 0xffff, 0x1249, 0x59b0, 0x1388, 0xffff, 0x120b, 0x59ad, 0x13c9, 0xffff, + 0x11cd, 0x59a9, 0x140b, 0xffff, 0x118f, 0x59a4, 0x144d, 0xffff, 0x1153, 0x599e, 0x1490, 0xffff, 0x1116, 0x5997, 0x14d4, 0xffff, + 0x10db, 0x598f, 0x1517, 0xffff, 0x109f, 0x5986, 0x155c, 0xffff, 0x1065, 0x597c, 0x15a0, 0xffff, 0x102a, 0x5971, 0x15e6, 0xffff, + 0x0ff1, 0x5965, 0x162c, 0xffff, 0x0fb7, 0x5958, 0x1672, 0xffff, 0x0f7f, 0x5949, 0x16b9, 0xffff, 0x0f46, 0x593a, 0x1700, 0xffff, + 0x0f0f, 0x592a, 0x1747, 0x0000, 0x0ed7, 0x5919, 0x1790, 0x0000, 0x0ea1, 0x5907, 0x17d8, 0x0000, 0x0e6b, 0x58f4, 0x1821, 0x0000, + 0x0e35, 0x58e0, 0x186b, 0x0000, 0x0e00, 0x58cb, 0x18b5, 0x0000, 0x0dcb, 0x58b5, 0x1900, 0x0000, 0x0d97, 0x589e, 0x194b, 0x0001, + 0x0d63, 0x5886, 0x1996, 0x0001, 0x0d30, 0x586d, 0x19e2, 0x0001, 0x0cfd, 0x5853, 0x1a2e, 0x0001, 0x0ccb, 0x5838, 0x1a7b, 0x0002, + 0x0c99, 0x581c, 0x1ac8, 0x0002, 0x0c68, 0x57ff, 0x1b16, 0x0002, 0x0c38, 0x57e2, 0x1b64, 0x0003, 0x0c07, 0x57c3, 0x1bb3, 0x0003, + 0x0bd8, 0x57a3, 0x1c02, 0x0003, 0x0ba9, 0x5782, 0x1c51, 0x0004, 0x0b7a, 0x5761, 0x1ca1, 0x0004, 0x0b4c, 0x573e, 0x1cf1, 0x0005, + 0x0b1e, 0x571b, 0x1d42, 0x0005, 0x0af1, 0x56f6, 0x1d93, 0x0006, 0x0ac4, 0x56d1, 0x1de5, 0x0007, 0x0a98, 0x56ab, 0x1e37, 0x0007, + 0x0a6c, 0x5684, 0x1e89, 0x0008, 0x0a40, 0x565b, 0x1edc, 0x0009, 0x0a16, 0x5632, 0x1f2f, 0x0009, 0x09eb, 0x5609, 0x1f82, 0x000a, + 0x09c1, 0x55de, 0x1fd6, 0x000b, 0x0998, 0x55b2, 0x202a, 0x000c, 0x096f, 0x5585, 0x207f, 0x000d, 0x0946, 0x5558, 0x20d4, 0x000e, + 0x091e, 0x5529, 0x2129, 0x000f, 0x08f7, 0x54fa, 0x217f, 0x0010, 0x08d0, 0x54ca, 0x21d5, 0x0011, 0x08a9, 0x5499, 0x222c, 0x0012, + 0x0883, 0x5467, 0x2282, 0x0013, 0x085d, 0x5434, 0x22da, 0x0015, 0x0838, 0x5401, 0x2331, 0x0016, 0x0813, 0x53cc, 0x2389, 0x0018, + 0x07ef, 0x5397, 0x23e1, 0x0019, 0x07cb, 0x5361, 0x2439, 0x001b, 0x07a7, 0x532a, 0x2492, 0x001c, 0x0784, 0x52f3, 0x24eb, 0x001e, + 0x0762, 0x52ba, 0x2545, 0x0020, 0x0740, 0x5281, 0x259e, 0x0021, 0x071e, 0x5247, 0x25f8, 0x0023, 0x06fd, 0x520c, 0x2653, 0x0025, + 0x06dc, 0x51d0, 0x26ad, 0x0027, 0x06bb, 0x5194, 0x2708, 0x0029, 0x069b, 0x5156, 0x2763, 0x002c, 0x067c, 0x5118, 0x27be, 0x002e, + 0x065c, 0x50da, 0x281a, 0x0030, 0x063e, 0x509a, 0x2876, 0x0033, 0x061f, 0x505a, 0x28d2, 0x0035, 0x0601, 0x5019, 0x292e, 0x0038, + 0x05e4, 0x4fd7, 0x298b, 0x003a, 0x05c7, 0x4f95, 0x29e7, 0x003d, 0x05aa, 0x4f52, 0x2a44, 0x0040, 0x058e, 0x4f0e, 0x2aa1, 0x0043, + 0x0572, 0x4ec9, 0x2aff, 0x0046, 0x0556, 0x4e84, 0x2b5c, 0x0049, 0x053b, 0x4e3e, 0x2bba, 0x004d, 0x0520, 0x4df7, 0x2c18, 0x0050, + 0x0506, 0x4db0, 0x2c76, 0x0054, 0x04ec, 0x4d68, 0x2cd4, 0x0057, 0x04d2, 0x4d20, 0x2d33, 0x005b, 0x04b9, 0x4cd7, 0x2d91, 0x005f, + 0x04a0, 0x4c8d, 0x2df0, 0x0063, 0x0488, 0x4c42, 0x2e4f, 0x0067, 0x0470, 0x4bf7, 0x2eae, 0x006b, 0x0458, 0x4bac, 0x2f0d, 0x006f, + 0x0441, 0x4b5f, 0x2f6c, 0x0074, 0x042a, 0x4b13, 0x2fcc, 0x0078, 0x0413, 0x4ac5, 0x302b, 0x007d, 0x03fc, 0x4a77, 0x308b, 0x0082, + 0x03e7, 0x4a29, 0x30ea, 0x0087, 0x03d1, 0x49d9, 0x314a, 0x008c, 0x03bc, 0x498a, 0x31aa, 0x0091, 0x03a7, 0x493a, 0x3209, 0x0096, + 0x0392, 0x48e9, 0x3269, 0x009c, 0x037e, 0x4898, 0x32c9, 0x00a1, 0x036a, 0x4846, 0x3329, 0x00a7, 0x0356, 0x47f4, 0x3389, 0x00ad, + 0x0343, 0x47a1, 0x33e9, 0x00b3, 0x0330, 0x474e, 0x3449, 0x00ba, 0x031d, 0x46fa, 0x34a9, 0x00c0, 0x030b, 0x46a6, 0x3509, 0x00c7, + 0x02f9, 0x4651, 0x3569, 0x00cd, 0x02e7, 0x45fc, 0x35c9, 0x00d4, 0x02d6, 0x45a6, 0x3629, 0x00db, 0x02c4, 0x4550, 0x3689, 0x00e3, + 0x02b4, 0x44fa, 0x36e8, 0x00ea, 0x02a3, 0x44a3, 0x3748, 0x00f2, 0x0293, 0x444c, 0x37a8, 0x00fa, 0x0283, 0x43f4, 0x3807, 0x0101, + 0x0273, 0x439c, 0x3867, 0x010a, 0x0264, 0x4344, 0x38c6, 0x0112, 0x0255, 0x42eb, 0x3926, 0x011b, 0x0246, 0x4292, 0x3985, 0x0123, + 0x0237, 0x4239, 0x39e4, 0x012c, 0x0229, 0x41df, 0x3a43, 0x0135, 0x021b, 0x4185, 0x3aa2, 0x013f, 0x020d, 0x412a, 0x3b00, 0x0148, + 0x0200, 0x40d0, 0x3b5f, 0x0152, 0x01f2, 0x4074, 0x3bbd, 0x015c, 0x01e5, 0x4019, 0x3c1b, 0x0166, 0x01d9, 0x3fbd, 0x3c79, 0x0171, + 0x01cc, 0x3f62, 0x3cd7, 0x017b, 0x01c0, 0x3f05, 0x3d35, 0x0186, 0x01b4, 0x3ea9, 0x3d92, 0x0191, 0x01a8, 0x3e4c, 0x3def, 0x019c, + 0x019c, 0x3def, 0x3e4c, 0x01a8, 0x0191, 0x3d92, 0x3ea9, 0x01b4, 0x0186, 0x3d35, 0x3f05, 0x01c0, 0x017b, 0x3cd7, 0x3f62, 0x01cc, + 0x0171, 0x3c79, 0x3fbd, 0x01d9, 0x0166, 0x3c1b, 0x4019, 0x01e5, 0x015c, 0x3bbd, 0x4074, 0x01f2, 0x0152, 0x3b5f, 0x40d0, 0x0200, + 0x0148, 0x3b00, 0x412a, 0x020d, 0x013f, 0x3aa2, 0x4185, 0x021b, 0x0135, 0x3a43, 0x41df, 0x0229, 0x012c, 0x39e4, 0x4239, 0x0237, + 0x0123, 0x3985, 0x4292, 0x0246, 0x011b, 0x3926, 0x42eb, 0x0255, 0x0112, 0x38c6, 0x4344, 0x0264, 0x010a, 0x3867, 0x439c, 0x0273, + 0x0101, 0x3807, 0x43f4, 0x0283, 0x00fa, 0x37a8, 0x444c, 0x0293, 0x00f2, 0x3748, 0x44a3, 0x02a3, 0x00ea, 0x36e8, 0x44fa, 0x02b4, + 0x00e3, 0x3689, 0x4550, 0x02c4, 0x00db, 0x3629, 0x45a6, 0x02d6, 0x00d4, 0x35c9, 0x45fc, 0x02e7, 0x00cd, 0x3569, 0x4651, 0x02f9, + 0x00c7, 0x3509, 0x46a6, 0x030b, 0x00c0, 0x34a9, 0x46fa, 0x031d, 0x00ba, 0x3449, 0x474e, 0x0330, 0x00b3, 0x33e9, 0x47a1, 0x0343, + 0x00ad, 0x3389, 0x47f4, 0x0356, 0x00a7, 0x3329, 0x4846, 0x036a, 0x00a1, 0x32c9, 0x4898, 0x037e, 0x009c, 0x3269, 0x48e9, 0x0392, + 0x0096, 0x3209, 0x493a, 0x03a7, 0x0091, 0x31aa, 0x498a, 0x03bc, 0x008c, 0x314a, 0x49d9, 0x03d1, 0x0087, 0x30ea, 0x4a29, 0x03e7, + 0x0082, 0x308b, 0x4a77, 0x03fc, 0x007d, 0x302b, 0x4ac5, 0x0413, 0x0078, 0x2fcc, 0x4b13, 0x042a, 0x0074, 0x2f6c, 0x4b5f, 0x0441, + 0x006f, 0x2f0d, 0x4bac, 0x0458, 0x006b, 0x2eae, 0x4bf7, 0x0470, 0x0067, 0x2e4f, 0x4c42, 0x0488, 0x0063, 0x2df0, 0x4c8d, 0x04a0, + 0x005f, 0x2d91, 0x4cd7, 0x04b9, 0x005b, 0x2d33, 0x4d20, 0x04d2, 0x0057, 0x2cd4, 0x4d68, 0x04ec, 0x0054, 0x2c76, 0x4db0, 0x0506, + 0x0050, 0x2c18, 0x4df7, 0x0520, 0x004d, 0x2bba, 0x4e3e, 0x053b, 0x0049, 0x2b5c, 0x4e84, 0x0556, 0x0046, 0x2aff, 0x4ec9, 0x0572, + 0x0043, 0x2aa1, 0x4f0e, 0x058e, 0x0040, 0x2a44, 0x4f52, 0x05aa, 0x003d, 0x29e7, 0x4f95, 0x05c7, 0x003a, 0x298b, 0x4fd7, 0x05e4, + 0x0038, 0x292e, 0x5019, 0x0601, 0x0035, 0x28d2, 0x505a, 0x061f, 0x0033, 0x2876, 0x509a, 0x063e, 0x0030, 0x281a, 0x50da, 0x065c, + 0x002e, 0x27be, 0x5118, 0x067c, 0x002c, 0x2763, 0x5156, 0x069b, 0x0029, 0x2708, 0x5194, 0x06bb, 0x0027, 0x26ad, 0x51d0, 0x06dc, + 0x0025, 0x2653, 0x520c, 0x06fd, 0x0023, 0x25f8, 0x5247, 0x071e, 0x0021, 0x259e, 0x5281, 0x0740, 0x0020, 0x2545, 0x52ba, 0x0762, + 0x001e, 0x24eb, 0x52f3, 0x0784, 0x001c, 0x2492, 0x532a, 0x07a7, 0x001b, 0x2439, 0x5361, 0x07cb, 0x0019, 0x23e1, 0x5397, 0x07ef, + 0x0018, 0x2389, 0x53cc, 0x0813, 0x0016, 0x2331, 0x5401, 0x0838, 0x0015, 0x22da, 0x5434, 0x085d, 0x0013, 0x2282, 0x5467, 0x0883, + 0x0012, 0x222c, 0x5499, 0x08a9, 0x0011, 0x21d5, 0x54ca, 0x08d0, 0x0010, 0x217f, 0x54fa, 0x08f7, 0x000f, 0x2129, 0x5529, 0x091e, + 0x000e, 0x20d4, 0x5558, 0x0946, 0x000d, 0x207f, 0x5585, 0x096f, 0x000c, 0x202a, 0x55b2, 0x0998, 0x000b, 0x1fd6, 0x55de, 0x09c1, + 0x000a, 0x1f82, 0x5609, 0x09eb, 0x0009, 0x1f2f, 0x5632, 0x0a16, 0x0009, 0x1edc, 0x565b, 0x0a40, 0x0008, 0x1e89, 0x5684, 0x0a6c, + 0x0007, 0x1e37, 0x56ab, 0x0a98, 0x0007, 0x1de5, 0x56d1, 0x0ac4, 0x0006, 0x1d93, 0x56f6, 0x0af1, 0x0005, 0x1d42, 0x571b, 0x0b1e, + 0x0005, 0x1cf1, 0x573e, 0x0b4c, 0x0004, 0x1ca1, 0x5761, 0x0b7a, 0x0004, 0x1c51, 0x5782, 0x0ba9, 0x0003, 0x1c02, 0x57a3, 0x0bd8, + 0x0003, 0x1bb3, 0x57c3, 0x0c07, 0x0003, 0x1b64, 0x57e2, 0x0c38, 0x0002, 0x1b16, 0x57ff, 0x0c68, 0x0002, 0x1ac8, 0x581c, 0x0c99, + 0x0002, 0x1a7b, 0x5838, 0x0ccb, 0x0001, 0x1a2e, 0x5853, 0x0cfd, 0x0001, 0x19e2, 0x586d, 0x0d30, 0x0001, 0x1996, 0x5886, 0x0d63, + 0x0001, 0x194b, 0x589e, 0x0d97, 0x0000, 0x1900, 0x58b5, 0x0dcb, 0x0000, 0x18b5, 0x58cb, 0x0e00, 0x0000, 0x186b, 0x58e0, 0x0e35, + 0x0000, 0x1821, 0x58f4, 0x0e6b, 0x0000, 0x17d8, 0x5907, 0x0ea1, 0x0000, 0x1790, 0x5919, 0x0ed7, 0x0000, 0x1747, 0x592a, 0x0f0f, + 0xffff, 0x1700, 0x593a, 0x0f46, 0xffff, 0x16b9, 0x5949, 0x0f7f, 0xffff, 0x1672, 0x5958, 0x0fb7, 0xffff, 0x162c, 0x5965, 0x0ff1, + 0xffff, 0x15e6, 0x5971, 0x102a, 0xffff, 0x15a0, 0x597c, 0x1065, 0xffff, 0x155c, 0x5986, 0x109f, 0xffff, 0x1517, 0x598f, 0x10db, + 0xffff, 0x14d4, 0x5997, 0x1116, 0xffff, 0x1490, 0x599e, 0x1153, 0xffff, 0x144d, 0x59a4, 0x118f, 0xffff, 0x140b, 0x59a9, 0x11cd, + 0xffff, 0x13c9, 0x59ad, 0x120b, 0xffff, 0x1388, 0x59b0, 0x1249, 0xffff, 0x1347, 0x59b2, 0x1288, 0xffff, 0x1307, 0x59b3, 0x12c7, +}; + +static sint32 ratelogtable[32+128]; + +/* +// v1.10 coefs - normalized from v1.04 +static const sint32 reverb_lowpass_coefs[8] = { + (int)((-0.036346113709214548)*(2048.0)), + (int)(( 0.044484956332843419)*(2048.0)), + (int)(( 0.183815456609675380)*(2048.0)), + (int)(( 0.308045700766695740)*(2048.0)), + (int)(( 0.308045700766695740)*(2048.0)), + (int)(( 0.183815456609675380)*(2048.0)), + (int)(( 0.044484956332843419)*(2048.0)), + (int)((-0.036346113709214548)*(2048.0)) +}; +*/ + +/* +// test coefs - ganked from LAME's blackman function +// (11-point filter, but only a few points were nonzero) +static const sint32 reverb_new_lowpass_coefs[3] = { + (int)((-0.02134438446523164)*(2048.0)), +// skip one + (int)(( 0.27085135668587779)*(2048.0)), + (int)(( 0.50098605555870768)*(2048.0)) +// rest are symmetrical +}; +*/ + +// PS1 reverb downsampling coefficients(as best as I could extract them at the moment, some of the even(non-zero/non-16384) ones *might* be off by 1. +// ------------- +#if 1 +static const sint32 reverb_psx_lowpass_coefs[11] = { + -1, +// 0, + 2, +// 0, + -10, +// 0, + 35, +// 0, + -103, +// 0, + 266, +// 0, + -616, +// 0, + 1332, +// 0, +-2960, +// 0, +10246, +16384 +}; +#else +static const sint32 reverb_psx_lowpass_coefs[48] = { + -1, + 0, + 2, + 0, + -10, + 0, + 35, + 0, + -103, + 0, + 266, + 0, + -616, + 0, + 1332, + 0, +-2960, + 0, +10246, +16384, +10246, + 0, +-2960, + 0, + 1332, + 0, + -616, + 0, + 266, + 0, + -103, + 0, + 35, + 0, + -10, + 0, + 2, + 0, + -1, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, +}; +#endif + + +static const int noisetable[] = { + 1, 0, 0, 1, 0, 1, 1, 0, + 1, 0, 0, 1, 0, 1, 1, 0, + 1, 0, 0, 1, 0, 1, 1, 0, + 1, 0, 0, 1, 0, 1, 1, 0, + 0, 1, 1, 0, 1, 0, 0, 1, + 0, 1, 1, 0, 1, 0, 0, 1, + 0, 1, 1, 0, 1, 0, 0, 1, + 0, 1, 1, 0, 1, 0, 0, 1 +}; + +/* +** Static init +*/ +sint32 EMU_CALL spucore_init(void) { + sint32 i; + + memset(ratelogtable, 0, sizeof(ratelogtable)); + ratelogtable[32-8] = 1; + ratelogtable[32-7] = 1; + ratelogtable[32-6] = 1; + ratelogtable[32-5] = 1; + ratelogtable[32-4] = 2; + ratelogtable[32-3] = 2; + ratelogtable[32-2] = 3; + ratelogtable[32-1] = 3; + ratelogtable[32+0] = 4; + ratelogtable[32+1] = 5; + ratelogtable[32+2] = 6; + ratelogtable[32+3] = 7; + for(i = 4; i < 128; i++) { + uint32 n = 2*ratelogtable[32+i-4]; + if(n > 0x20000000) n = 0x20000000; + ratelogtable[32+i] = n; + } + + return 0; +} + +//////////////////////////////////////////////////////////////////////////////// +/* +** State information +*/ +#define SPUCORESTATE ((struct SPUCORE_STATE*)(state)) + +#define SAMPLE_STATE_OFF (0) +#define SAMPLE_STATE_ENDING (1) +#define SAMPLE_STATE_ON (2) + +struct SPUCORE_SAMPLE { + uint8 state; + uint8 array_cleared; + sint32 array[32]; + uint32 phase; + + uint32 block_addr; + uint32 start_block_addr; + //uint32 start_loop_block_addr; + uint32 loop_block_addr; +}; + +#define ENVELOPE_STATE_OFF (0) +#define ENVELOPE_STATE_ATTACK (1) +#define ENVELOPE_STATE_DECAY (2) +#define ENVELOPE_STATE_SUSTAIN (3) +#define ENVELOPE_STATE_RELEASE (4) + +struct SPUCORE_ENVELOPE { + uint32 reg_ad; + uint32 reg_sr; + sint32 level; + sint32 delta; + int state; + sint32 cachemax; +}; + +//////////////////////////////////////////////////////////////////////////////// +/* +** Volumes with increase/decrease modes +*/ +struct SPUCORE_VOLUME { + uint16 mode; + sint32 level; +}; + +static EMU_INLINE void EMU_CALL volume_setmode(struct SPUCORE_VOLUME *vol, uint16 mode) { + vol->mode = mode; + if(mode & 0x8000) { + } else { + vol->level = mode; + vol->level <<= 17; + vol->level >>= 1; + } +} + +static EMU_INLINE uint16 EMU_CALL volume_getmode(struct SPUCORE_VOLUME *vol) { + return vol->mode; +} + +static EMU_INLINE sint32 EMU_CALL volume_getlevel(struct SPUCORE_VOLUME *vol) { + return (vol->level) >> 15; +} + +//////////////////////////////////////////////////////////////////////////////// + +struct SPUCORE_CHAN { + struct SPUCORE_VOLUME vol[2]; + uint32 voice_pitch; + struct SPUCORE_SAMPLE sample; + struct SPUCORE_ENVELOPE env; + int samples_until_pending_keyon; +}; + +/* +** Reverb resample state +*/ +struct SPUCORE_REVERB_RESAMPLER { + sint32 in_queue_l[64]; + sint32 in_queue_r[64]; + sint32 out_queue_l[16]; + sint32 out_queue_r[16]; + int queue_index; +}; + +struct SPUCORE_REVERB { + uint32 FB_SRC_A ; + uint32 FB_SRC_B ; + uint16 IIR_ALPHA ; + uint16 ACC_COEF_A ; + uint16 ACC_COEF_B ; + uint16 ACC_COEF_C ; + uint16 ACC_COEF_D ; + uint16 IIR_COEF ; + uint16 FB_ALPHA ; + uint16 FB_X ; + uint32 IIR_DEST_A0; + uint32 IIR_DEST_A1; + uint32 ACC_SRC_A0 ; + uint32 ACC_SRC_A1 ; + uint32 ACC_SRC_B0 ; + uint32 ACC_SRC_B1 ; + uint32 IIR_SRC_A0 ; + uint32 IIR_SRC_A1 ; + uint32 IIR_DEST_B0; + uint32 IIR_DEST_B1; + uint32 ACC_SRC_C0 ; + uint32 ACC_SRC_C1 ; + uint32 ACC_SRC_D0 ; + uint32 ACC_SRC_D1 ; + uint32 IIR_SRC_B1 ; + uint32 IIR_SRC_B0 ; + uint32 MIX_DEST_A0; + uint32 MIX_DEST_A1; + uint32 MIX_DEST_B0; + uint32 MIX_DEST_B1; + uint16 IN_COEF_L ; + uint16 IN_COEF_R ; + + uint32 start_address; + uint32 end_address; + + sint32 current_address; + + sint32 safe_start_address; + sint32 safe_end_address; + sint32 safe_size; + + struct SPUCORE_REVERB_RESAMPLER resampler; +}; + +struct SPUCORE_STATE { + uint32 flags; + sint32 memsize; + struct SPUCORE_CHAN chan[24]; + struct SPUCORE_REVERB reverb; + struct SPUCORE_VOLUME mvol[2]; + sint16 evol[2]; + sint16 avol[2]; + sint16 bvol[2]; + uint32 kon; + uint32 koff; + uint32 fm; + uint32 noise; + uint32 vmix[2]; + uint32 vmixe[2]; + uint32 irq_address; + uint32 noiseclock; + uint32 noisecounter; + sint32 noiseval; + uint32 irq_decoder_clock; + uint32 irq_triggered_cycle; +}; + +struct SPUCORE_IRQ_STATE { + uint32 offset; + uint32 triggered_cycle; +}; + +uint32 EMU_CALL spucore_get_state_size(void) { + return(sizeof(struct SPUCORE_STATE)); +} + +/* +** Initialize SPU CORE state +*/ +void EMU_CALL spucore_clear_state(void *state) { + /* + ** Clear to zero + */ + memset(state, 0, sizeof(struct SPUCORE_STATE)); + /* + ** Set other defaults + */ + SPUCORESTATE->memsize = 0x80000; + spucore_setreg(state, SPUREG_EEA, 0x7FFFF, 0xFFFFFFFF); + spucore_setreg(state, SPUREG_VMIX, 0x00FFFFFF, 0xFFFFFFFF); + spucore_setflag(state, SPUREG_FLAG_MSNDL , 1); + spucore_setflag(state, SPUREG_FLAG_MSNDR , 1); + spucore_setflag(state, SPUREG_FLAG_MSNDEL, 1); + spucore_setflag(state, SPUREG_FLAG_MSNDER, 1); + spucore_setflag(state, SPUREG_FLAG_SINL, 1); + spucore_setflag(state, SPUREG_FLAG_SINR, 1); + SPUCORESTATE->irq_triggered_cycle = 0xFFFFFFFF; +} + +void EMU_CALL spucore_set_mem_size(void *state, uint32 size) { + SPUCORESTATE->memsize = (sint32)size; + spucore_setreg(state, SPUREG_EEA, size-1, 0xFFFFFFFF); +} + +//////////////////////////////////////////////////////////////////////////////// + +static void EMU_CALL make_safe_reverb_addresses(struct SPUCORE_STATE *state) { + struct SPUCORE_REVERB *r = &(state->reverb); + sint32 sa = r->start_address; + sint32 ea = r->end_address; + +//EMUTRACE2("[sa,ea=%X,%X]\n",sa,ea); + + ea += 0x20000; + ea &= (~0x1FFFF); + sa &= (~1); + + if(ea > state->memsize) ea = state->memsize; + if(ea < 0x20000) ea = 0x20000; + if(sa > ea) { + sa &= 0x1FFFE; + sa += ea; + sa -= 0x20000; + } + + r->safe_start_address = sa; + r->safe_end_address = ea; + r->safe_size = ea-sa; + + r->current_address &= (~1); + if( + (r->current_address < r->safe_start_address) || + (r->current_address >= r->safe_end_address) + ) { + r->current_address = r->safe_start_address; + } +} + +//////////////////////////////////////////////////////////////////////////////// +/* +** ADPCM sample decoding +*/ +/* +#define SPUCORE_PREDICT_SKEL(prednum,coef1,coef2) \ +static void EMU_CALL spucore_predict_##prednum(uint8 *src, sint32 *dest, uint32 shift) { \ + uint32 i; \ + sint32 p_a = dest[-2]; \ + sint32 p_b = dest[-1]; \ + shift += 16; \ + for(i = 0; i < 14; i++) { \ + sint32 a = src[i^(EMU_ENDIAN_XOR(1))]; \ + sint32 b = (a&0xF0)<<24; \ + a = a << 28; b >>= shift; a >>= shift; \ + a += ( ( ((coef1)*p_b) + ((coef2)*p_a) )+32)>>6; \ + if(a > 32767) { a = 32767; } if(a < (-32768)) { a = (-32768); } \ + *dest++ = a; \ + b += ( ( ((coef1)* a ) + ((coef2)*p_b) )+32)>>6; \ + if(b > 32767) { b = 32767; } if(b < (-32768)) { b = (-32768); } \ + *dest++ = b; \ + p_a = a; p_b = b; \ + } \ +} +*/ + +#define SPUCORE_PREDICT_SKEL(prednum,coef1,coef2) \ +static void EMU_CALL spucore_predict_##prednum(uint16 *src, sint32 *dest, uint32 shift) { \ + uint32 i; \ + sint32 p_a = dest[-2]; \ + sint32 p_b = dest[-1]; \ + shift += 16; \ + for(i = 0; i < 7; i++) { \ + sint32 a = *src++; \ + sint32 b = (a&0x00F0)<<24; \ + sint32 c = (a&0x0F00)<<20; \ + sint32 d = (a&0xF000)<<16; \ + a <<= 28; \ + a >>= shift; \ + b >>= shift; \ + c >>= shift; \ + d >>= shift; \ + a += ( ( ((coef1)*p_b) + ((coef2)*p_a) )+32)>>6; \ + if(a > 32767) { a = 32767; } if(a < (-32768)) { a = (-32768); } \ + *dest++ = a; \ + b += ( ( ((coef1)* a ) + ((coef2)*p_b) )+32)>>6; \ + if(b > 32767) { b = 32767; } if(b < (-32768)) { b = (-32768); } \ + *dest++ = b; \ + c += ( ( ((coef1)* b ) + ((coef2)* a ) )+32)>>6; \ + if(b > 32767) { b = 32767; } if(b < (-32768)) { b = (-32768); } \ + *dest++ = c; \ + d += ( ( ((coef1)* c ) + ((coef2)* b ) )+32)>>6; \ + if(b > 32767) { b = 32767; } if(b < (-32768)) { b = (-32768); } \ + *dest++ = d; \ + p_a = c; p_b = d; \ + } \ +} + +SPUCORE_PREDICT_SKEL(0,0,0) +SPUCORE_PREDICT_SKEL(1,60,0) +SPUCORE_PREDICT_SKEL(2,115,-52) +SPUCORE_PREDICT_SKEL(3,98,-55) +SPUCORE_PREDICT_SKEL(4,122,-60) + +typedef void (EMU_CALL * spucore_predict_callback_t)(uint16*, sint32*, uint32); + +static spucore_predict_callback_t spucore_predict[8] = { + spucore_predict_0, spucore_predict_1, spucore_predict_2, spucore_predict_3, + spucore_predict_4, spucore_predict_1, spucore_predict_2, spucore_predict_3 +}; + +static void EMU_CALL decode_sample_block( + uint16 *ram, + uint32 memmax, + struct SPUCORE_SAMPLE *sample, + int skip +) { +// uint32 i; + if(sample->state != SAMPLE_STATE_ON) { + if(!sample->array_cleared) { + memset(sample->array, 0, sizeof(sample->array)); + sample->array_cleared = 1; + } + sample->state = SAMPLE_STATE_OFF; + } else { + /* temporary hack to avoid memory problems */ + sample->block_addr &= (memmax-1); + if((sample->block_addr + 0x10) > memmax) sample->block_addr -= 0x10; + ram += sample->block_addr >> 1; + /* decode */ + if(skip) { + if(!sample->array_cleared) { + memset(sample->array, 0, sizeof(sample->array)); + sample->array_cleared = 1; + } + } else { + sample->array[0] = sample->array[28]; + sample->array[1] = sample->array[29]; + sample->array[2] = sample->array[30]; + sample->array[3] = sample->array[31]; + (spucore_predict[(ram[0]>>4)&7])( + ram + 1, + sample->array + 4, + ram[0] & 0xF + ); + } + /* set loop start address if necessary */ + if(ram[0]&0x0400) { + sample->loop_block_addr = sample->block_addr; + } + /* sample end? */ + if(ram[0]&0x0100) { + /* loop? */ + if(ram[0]&0x0200) { + sample->block_addr = sample->loop_block_addr; + /* no loop, just end */ + } else { + sample->state = SAMPLE_STATE_ENDING; + } + } else { + /* advance to next block */ + sample->block_addr += 16; + } + } +} + +//////////////////////////////////////////////////////////////////////////////// +// +// Returns the number of samples actually generated +// If dest is null, it means "fast forward" - don't render anything +// +// +// output of resampler() is guaranteed clipped, as long as the output of +// decode_sample_block() is +// +static uint32 EMU_CALL resampler( + uint16 *ram, + uint32 memmax, + struct SPUCORE_SAMPLE *sample, + sint32 *dest, + uint32 n, + uint32 phase_inc, + struct SPUCORE_IRQ_STATE *irq_state +) { + uint32 irq_triggered_cycle = 0xFFFFFFFF; + uint32 s; + uint32 ph; //, phl; + ph = sample->phase; + if(!dest) { + ph += phase_inc * n; + s = 0; + while(ph >= 0x1C000) { + if(sample->state == SAMPLE_STATE_OFF) break; + if(irq_state && irq_state->offset - sample->block_addr < 16 && irq_triggered_cycle == 0xFFFFFFFF) { + irq_triggered_cycle = s; + } + decode_sample_block(ram, memmax, sample, 1); + s += phase_inc * 28; + ph -= 0x1C000; + } + s = n; + } else { + uint32 t = 0; + for(s = 0; s < n; s++) { + sint32 *source_signal; + sint16 *mygauss; + sint32 sum; + if(ph >= 0x1C000) { + if(sample->state == SAMPLE_STATE_OFF) break; + if(irq_state && irq_state->offset - sample->block_addr < 16 && irq_triggered_cycle == 0xFFFFFFFF) { + irq_triggered_cycle = t; + } + decode_sample_block(ram, memmax, sample, 0); + ph -= 0x1C000; + } + source_signal = sample->array + (ph >> 12); + mygauss = (sint16*) (((uint8*)gauss_shuffled_reverse_table) + ((ph & 0xFF0) >> 1)); + + { sum = + (source_signal[0] * mygauss[0]) + + (source_signal[1] * mygauss[1]) + + (source_signal[2] * mygauss[2]) + + (source_signal[3] * mygauss[3]); + } + sum >>= 15; + + *dest++ = sum; + ph += phase_inc; + t += phase_inc; + } + } + + if(irq_state && irq_triggered_cycle != 0xFFFFFFFF) { + irq_triggered_cycle = (irq_triggered_cycle * 768) >> 12; + if(irq_triggered_cycle < irq_state->triggered_cycle) irq_state->triggered_cycle = irq_triggered_cycle; + } + + sample->phase = ph; + + return s; +} + +//////////////////////////////////////////////////////////////////////////////// + +static uint32 EMU_CALL resampler_modulated( + uint16 *ram, + uint32 memmax, + struct SPUCORE_SAMPLE *sample, + sint32 *dest, + uint32 n, + uint32 phase_inc, + sint32 *fmbuf, + struct SPUCORE_IRQ_STATE *irq_state +) { + uint32 irq_triggered_cycle = 0xFFFFFFFF; + uint32 s, t = 0; + uint32 ph; //, phl; + uint32 pimod; + ph = sample->phase; + if(!dest) { + for(s = 0; s < n; s++) { + pimod = ((*fmbuf++ + 32768) * phase_inc) / 32768; + if(pimod > 0x3FFF) pimod = 0x3FFF; + else if(pimod < 1) pimod = 1; + ph += pimod; + while(ph >= 0x1C000) { + if(sample->state == SAMPLE_STATE_OFF) break; + if(irq_state && irq_state->offset - sample->block_addr < 16 && irq_triggered_cycle == 0xFFFFFFFF) { + irq_triggered_cycle = t; + } + decode_sample_block(ram, memmax, sample, 1); + ph -= 0x1C000; + } + t += pimod; + } + } else { + for(s = 0; s < n; s++) { + sint32 *source_signal; + sint16 *mygauss; + sint32 sum; + if(ph >= 0x1C000) { + if(sample->state == SAMPLE_STATE_OFF) break; + if(irq_state && irq_state->offset - sample->block_addr < 16 && irq_triggered_cycle == 0xFFFFFFFF) { + irq_triggered_cycle = t; + } + decode_sample_block(ram, memmax, sample, 0); + ph -= 0x1C000; + } + source_signal = sample->array + (ph >> 12); + mygauss = (sint16*) (((uint8*)gauss_shuffled_reverse_table) + ((ph & 0xFF0) >> 1)); + + { sum = + (source_signal[0] * mygauss[0]) + + (source_signal[1] * mygauss[1]) + + (source_signal[2] * mygauss[2]) + + (source_signal[3] * mygauss[3]); + } + sum >>= 15; + + *dest++ = sum; + pimod = ((*fmbuf++ + 32768) * phase_inc) / 32768; + if(pimod > 0x3FFF) pimod = 0x3FFF; + else if(pimod < 1) pimod = 1; + ph += pimod; + t += pimod; + } + } + + if(irq_state && irq_triggered_cycle != 0xFFFFFFFF) { + irq_triggered_cycle = (irq_triggered_cycle * 768) >> 12; + if(irq_triggered_cycle < irq_state->triggered_cycle) irq_state->triggered_cycle = irq_triggered_cycle; + } + + sample->phase = ph; + + return s; +} + +//////////////////////////////////////////////////////////////////////////////// + +#define MY_AM (((env->reg_ad)>>15)&0x01) +#define MY_AR (((env->reg_ad)>> 8)&0x7F) +#define MY_DR (((env->reg_ad)>> 4)&0x0F) +#define MY_SL (((env->reg_ad)>> 0)&0x0F) +#define MY_SM (((env->reg_sr)>>15)&0x01) +#define MY_SD (((env->reg_sr)>>14)&0x01) +#define MY_SR (((env->reg_sr)>> 6)&0x7F) +#define MY_RM (((env->reg_sr)>> 5)&0x01) +#define MY_RR (((env->reg_sr)>> 0)&0x1F) + +/* +** - Sets the current envelope slope +** - Returns the max number of samples that can be processed at the current +** slope +*/ +static EMU_INLINE sint32 EMU_CALL envelope_do(struct SPUCORE_ENVELOPE *env) { + sint32 target = 0; + /* + ** Clip envelope value in case it wrapped around + */ + switch(((env->level) >> 30) & 3) { + case 2: env->level = 0x7FFFFFFF; break; + case 3: env->level = 0x00000000; break; + } + switch(env->state) { + case ENVELOPE_STATE_ATTACK : goto attack; + case ENVELOPE_STATE_DECAY : goto decay; + case ENVELOPE_STATE_SUSTAIN: goto sustain; + case ENVELOPE_STATE_RELEASE: goto release; + default: + env->state = ENVELOPE_STATE_OFF; + env->level = 0; + env->delta = 0; + return 1; + } +attack: + if(env->level == 0x7FFFFFFF) { + env->state = ENVELOPE_STATE_DECAY; + goto decay; + } + /* log */ + if(MY_AM) { + if(env->level < 0x60000000) { + target = 0x60000000; + env->delta = ratelogtable[32+(MY_AR^0x7F)-0x10]; + } else { + target = 0x7FFFFFFF; + env->delta = ratelogtable[32+(MY_AR^0x7F)-0x18]; + } + /* linear */ + } else { + target = 0x7FFFFFFF; + env->delta = ratelogtable[32+(MY_AR^0x7F)-0x10]; + } + goto domax; + +decay: + if((((env->level)>>27)&0xF) <= ((sint32)(MY_SL))) { + env->state = ENVELOPE_STATE_SUSTAIN; + goto sustain; + } + target = env->level & (~0x07FFFFFF); + switch(((env->level)>>28)&0x7) { + case 0: env->delta = -ratelogtable[32+(4*(MY_DR^0x1F))-0x18+0]; break; + case 1: env->delta = -ratelogtable[32+(4*(MY_DR^0x1F))-0x18+4]; break; + case 2: env->delta = -ratelogtable[32+(4*(MY_DR^0x1F))-0x18+6]; break; + case 3: env->delta = -ratelogtable[32+(4*(MY_DR^0x1F))-0x18+8]; break; + case 4: env->delta = -ratelogtable[32+(4*(MY_DR^0x1F))-0x18+9]; break; + case 5: env->delta = -ratelogtable[32+(4*(MY_DR^0x1F))-0x18+10]; break; + case 6: env->delta = -ratelogtable[32+(4*(MY_DR^0x1F))-0x18+11]; break; + case 7: env->delta = -ratelogtable[32+(4*(MY_DR^0x1F))-0x18+12]; break; + } + goto domax; + +sustain: + if(!MY_SD) { + if(env->level == 0x7FFFFFFF) { + env->delta = 0; + return 0x7FFFFFFF; + } + /* log */ + if(MY_SM) { + if(env->level < 0x60000000) { + target = 0x60000000; + env->delta = ratelogtable[32+(MY_SR^0x7F)-0x10]; + } else { + target = 0x7FFFFFFF; + env->delta = ratelogtable[32+(MY_SR^0x7F)-0x18]; + } + /* linear */ + } else { + target = 0x7FFFFFFF; + env->delta = ratelogtable[32+(MY_SR^0x7F)-0x10]; + } + } else { + if(env->level == 0x00000000) { + env->delta = 0; + return 0x7FFFFFFF; + } + /* log */ + if(MY_SM) { + target = ((env->level)&(~0x0FFFFFFF)); + switch(((env->level)>>28)&0x7) { + case 0: env->delta = -ratelogtable[32+(MY_SR^0x7F)-0x1B+0]; break; + case 1: env->delta = -ratelogtable[32+(MY_SR^0x7F)-0x1B+4]; break; + case 2: env->delta = -ratelogtable[32+(MY_SR^0x7F)-0x1B+6]; break; + case 3: env->delta = -ratelogtable[32+(MY_SR^0x7F)-0x1B+8]; break; + case 4: env->delta = -ratelogtable[32+(MY_SR^0x7F)-0x1B+9]; break; + case 5: env->delta = -ratelogtable[32+(MY_SR^0x7F)-0x1B+10]; break; + case 6: env->delta = -ratelogtable[32+(MY_SR^0x7F)-0x1B+11]; break; + case 7: env->delta = -ratelogtable[32+(MY_SR^0x7F)-0x1B+12]; break; + } + /* linear */ + } else { + target = 0x00000000; + env->delta = -ratelogtable[32+(MY_SR^0x7F)-0x0F]; + } + } + goto domax; + +release: + if(env->level == 0) { + env->delta = 0; + env->state = ENVELOPE_STATE_OFF; + return 1; + } + /* log */ + if(MY_RM) { + target = ((env->level) & (~0x0FFFFFFF)); + switch(((env->level)>>28)&0x7) { + case 0: env->delta = -ratelogtable[32+(4*(MY_RR^0x1F))-0x18+0]; break; + case 1: env->delta = -ratelogtable[32+(4*(MY_RR^0x1F))-0x18+4]; break; + case 2: env->delta = -ratelogtable[32+(4*(MY_RR^0x1F))-0x18+6]; break; + case 3: env->delta = -ratelogtable[32+(4*(MY_RR^0x1F))-0x18+8]; break; + case 4: env->delta = -ratelogtable[32+(4*(MY_RR^0x1F))-0x18+9]; break; + case 5: env->delta = -ratelogtable[32+(4*(MY_RR^0x1F))-0x18+10]; break; + case 6: env->delta = -ratelogtable[32+(4*(MY_RR^0x1F))-0x18+11]; break; + case 7: env->delta = -ratelogtable[32+(4*(MY_RR^0x1F))-0x18+12]; break; + } + /* linear */ + } else { + target = 0; + env->delta = -ratelogtable[32+(4*(MY_RR^0x1F))-0x0C]; + } + goto domax; + +domax: + { sint32 max; + if(env->delta) { + max = (target - (env->level)) / (env->delta); + } else { + max = 0x7FFFFFFF; + } + max--; + if(max < 1) max = 1; + return max; + } +} + +//////////////////////////////////////////////////////////////////////////////// + +static void EMU_CALL envelope_prime(struct SPUCORE_ENVELOPE *env) { +// if(env->state != ENVELOPE_STATE_OFF) { +//if(env->state!=ENVELOPE_STATE_RELEASE){ +// OutputDebugString("envelope re-prime\n"); +//} +// } + +//EMUTRACE2("[eprime %04X %04X]",env->reg_ad_x,env->reg_sr_x); + + env->level = 1; + env->state = ENVELOPE_STATE_ATTACK; + env->delta = 1; + + env->cachemax = 0; +} + +static void EMU_CALL envelope_release(struct SPUCORE_ENVELOPE *env) { + if(env->state != ENVELOPE_STATE_OFF) { + env->state = ENVELOPE_STATE_RELEASE; + } + env->cachemax = 0; +} + +//////////////////////////////////////////////////////////////////////////////// + +static void EMU_CALL sample_prime(struct SPUCORE_SAMPLE *sample) { + sample->state = SAMPLE_STATE_ON; + memset(sample->array, 0, sizeof(sample->array)); + sample->array_cleared = 1; + sample->phase = 0x1C000; // ensure it grabs the first block right away +//EMUTRACE2("[sprime %08X %08X]", sample->start_block_addr, sample->start_loop_block_addr); + + sample->block_addr = sample->start_block_addr; + //sample->loop_block_addr = sample->start_loop_block_addr; +} + +//////////////////////////////////////////////////////////////////////////////// + +static void EMU_CALL voice_on(struct SPUCORE_CHAN *c) { + + // FOR DEBUGGING PURPOSES ONLY. +// if(c->sample.state == SAMPLE_STATE_ON)return; +// if(c->env.state != ENVELOPE_STATE_OFF)return; + /* + ** Defer if already on + */ + if(c->env.state != ENVELOPE_STATE_OFF) { + //EMUTRACE0("alreadyon:"); + if(!(c->samples_until_pending_keyon)) { + //EMUTRACE0("defer"); + c->samples_until_pending_keyon = KEYON_DEFER_SAMPLES; + } else { + //EMUTRACE0("was already deferred"); + } + } else { +// EMUTRACE0("prime"); + sample_prime(&(c->sample)); + envelope_prime(&(c->env)); + } +// EMUTRACE0("\n"); +} + +static void EMU_CALL voice_off(struct SPUCORE_CHAN *c) { + //EMUTRACE0("release"); + envelope_release(&(c->env)); + //EMUTRACE0("\n"); +} + +//////////////////////////////////////////////////////////////////////////////// + +static void EMU_CALL voices_on(struct SPUCORE_STATE *state, uint32 bits) { + int a; + for(a = 0; a < 24; a++) { + if(bits & 1) { + +// EMUTRACE1("voiceon %2d:",a); + +//EMUTRACE2("[vol %08X %08X]",state->chan[a].vol[0].level,state->chan[a].vol[1].level); +//EMUTRACE2("[mvol %08X %08X]",state->mvol[0].level,state->mvol[1].level); +////EMUTRACE2("[avol %08X %08X]",state->avol[0],state->avol[1]); +//EMUTRACE2("[evol %08X %08X]",state->evol[0],state->evol[1]); + +// sint32 extvol_l = ((sint16)(state->avol[0])); +// sint32 extvol_r = ((sint16)(state->avol[1])); + + voice_on(state->chan + a); + } + bits >>= 1; + } +} + +static void EMU_CALL voices_off(struct SPUCORE_STATE *state, uint32 bits) { + int a; + for(a = 0; a < 24; a++) { + if(bits & 1) { + //EMUTRACE1("voiceoff %2d:",a); + voice_off(state->chan + a); + } + bits >>= 1; + } +} + +//////////////////////////////////////////////////////////////////////////////// +/* +** - Scales samples in a buffer using an envelope +** - Returns the actual number of samples modified +** +** All UNMODIFIED samples must then be discarded +** (they're supposed to be zero) +*/ +static int EMU_CALL enveloper( + struct SPUCORE_ENVELOPE *env, + sint32 *buf, + int samples +) { + int i = 0; + while(i < samples) { + sint32 e, d, max; + if(env->state == ENVELOPE_STATE_OFF) break; + max = env->cachemax; + if(!max) { + max = envelope_do(env); + env->cachemax = max; + } + e = env->level; + d = env->delta; + if(max < 1) max = 1; + if(max > (samples - i)) { max = samples - i; } + env->cachemax -= max; + if(!buf) { + i += max; + e += max * d; + } else { + while(max--) { + sint32 b = buf[i]; + b *= (e >> 16); + b >>= 15; + buf[i] = b; + e += d; + i++; + } + } + env->level = e; + env->delta = d; + } + return i; +} + +//////////////////////////////////////////////////////////////////////////////// +// +// - Calls the resampler and enveloper +// - Returns the number of samples actually generated +// (can be 0 if the channel is silent) +// +// If buf is null, it means "fast forward" - don't render anything +// +// +// output of render_channel_raw() is guaranteed clipped as long as +// resampler() and enveloper() are also +// +static int EMU_CALL render_channel_raw( + uint16 *ram, + uint32 memmax, + struct SPUCORE_CHAN *c, + sint32 *buf, + sint32 *fmbuf, + sint32 *nbuf, + int samples, + struct SPUCORE_IRQ_STATE *irq_state +) { + int r = samples; + /* If the envelope is dead, don't bother anyway */ + if((c->env.state) == ENVELOPE_STATE_OFF) return 0; + /* Do resampling */ + if (fmbuf) r = resampler_modulated(ram, memmax, &(c->sample), buf, r, c->voice_pitch, fmbuf, irq_state); + else r = resampler(ram, memmax, &(c->sample), buf, r, c->voice_pitch, irq_state); + if(nbuf) { + r = samples; + if(buf) memcpy(buf, nbuf, 4 * r); + } + /* Do enveloping */ + r = enveloper(&(c->env), buf, r); + /* If we were cut short by _either_, then the envelope state must be set + ** to OFF */ + if(r < samples) c->env.state = ENVELOPE_STATE_OFF; + return r; +} + +// +// This is the new render_channel which processes deferred key-ons +// +// +// output of render_channel_mono() is guaranteed clipped as long as +// render_channel_raw() is also +// +static int EMU_CALL render_channel_mono( + uint16 *ram, + uint32 memmax, + struct SPUCORE_CHAN *c, + sint32 *buf, + sint32 *fmbuf, + sint32 *nbuf, + sint32 samples, + struct SPUCORE_IRQ_STATE *irq_state +) { + sint32 n; + sint32 r, r2; + sint32 defer_remaining; + struct SPUCORE_IRQ_STATE spare_state; + +//top: + n = c->samples_until_pending_keyon; + + if(!n) { + return render_channel_raw(ram, memmax, c, buf, fmbuf, nbuf, samples, irq_state); + } + + // + // Don't defer key-on if fast-forwarding + // this caused a STUCK-NOTE BUG. should not use. + // +// if(!buf) { +// c->samples_until_pending_keyon = 0; +// goto top; +// } + + if(n > samples) { n = samples; } + + /* + ** r = how many samples we actually will process + */ + r = render_channel_raw(ram, memmax, c, buf, fmbuf, nbuf, n, irq_state); + + defer_remaining = c->samples_until_pending_keyon; + if(buf) { + sint32 i; + for(i = 0; i < r; i++) { + (*buf) = ((*buf)*defer_remaining) / KEYON_DEFER_SAMPLES; + buf++; + defer_remaining--; + } + } else { + defer_remaining -= r; + } + if(fmbuf) fmbuf += r; + if(nbuf) nbuf += r; + /* + ** if render_channel_raw got cut short, then we're done anyway. + */ + if(r < n) defer_remaining = 0; + + c->samples_until_pending_keyon = defer_remaining; + /* + ** Process the key-on if necessary + */ + if(!defer_remaining) { + sample_prime(&(c->sample)); + envelope_prime(&(c->env)); + } + + /* + ** we already handled r samples + */ + samples -= r; + + /* + ** if there are any remaining samples to render, do them here + */ + r2 = 0; + if(samples) { + struct SPUCORE_IRQ_STATE *s = NULL; + if(irq_state) { + s = &spare_state; + spare_state.offset = irq_state->offset; + } + r2 = render_channel_raw(ram, memmax, c, buf, fmbuf, nbuf, samples, s); + if(irq_state && irq_state->triggered_cycle == 0xFFFFFFFF && spare_state.triggered_cycle != 0xFFFFFFFF) irq_state->triggered_cycle = spare_state.triggered_cycle + r * 768; + } + + return r + r2; + +} + +//////////////////////////////////////////////////////////////////////////////// +// +// Generates a buffer worth of noise data, ganked from Eternal SPU +// + +static void EMU_CALL render_noise( + struct SPUCORE_STATE *state, + sint32 *buf, + sint32 samples +) { + int n; + uint32 noisecounter = state->noisecounter; + sint32 noiseval = state->noiseval; + uint32 noiseinc = (uint16)(0x8000 >> (state->noiseclock << 6)); + for(n = 0; n < samples; n++) { + noisecounter += noiseinc; + noiseval += noisecounter + noisecounter + noisetable[(noisecounter >> 10) & 63]; + if (noiseval < -32767) noiseval = -32767; + else if (noiseval > 32767) noiseval = 32767; + if (buf) *buf++ = noiseval; + } + state->noisecounter = noisecounter; + state->noiseval = noiseval; +} + +//////////////////////////////////////////////////////////////////////////////// + +#define MAKE_SINT32_COEF(x) ((sint32)((sint16)(state->reverb.x))) +#define MAKE_REVERB_OFFSET(x) (state->reverb.x) +#define NORMALIZE_REVERB_OFFSET(x) {while(x>=state->reverb.safe_end_address){x-=state->reverb.safe_size;}while(xreverb.safe_start_address){x+=state->reverb.safe_size;}} + +#define RAM_PCM_SAMPLE(x) (*((sint16*)(((uint8*)ram) + (x)))) +#define RAM_SINT32_SAMPLE(x) ((sint32)(RAM_PCM_SAMPLE(x))) +/* +** Multiplying -32768 by -32768 and scaling by 15 bits is not safe +** (the sign would get flipped) +** so we should clip to -32767 instead +*/ +#define CLIP_PCM_1(x) {if(x>32767){x=32767;}else if(x<(-32767)){x=(-32767);}} +#define CLIP_PCM_2(a,b) {CLIP_PCM_1(a);CLIP_PCM_1(b);} +#define CLIP_PCM_4(a,b,c,d) {CLIP_PCM_1(a);CLIP_PCM_1(b);CLIP_PCM_1(c);CLIP_PCM_1(d);} + +//#define CLIP_PCMDBL_1(x) {if(x>(32767*2)){x=(32767*2);}else if(x<(-(32767*2))){x=(-(32767*2));}} +//#define CLIP_PCMDBL_2(a,b) {CLIP_PCMDBL_1(a);CLIP_PCMDBL_1(b);} +//#define CLIP_PCMDBL_4(a,b,c,d) {CLIP_PCMDBL_1(a);CLIP_PCMDBL_1(b);CLIP_PCMDBL_1(c);CLIP_PCMDBL_1(d);} + +//////////////////////////////////////////////////////////////////////////////// +/* +** 22KHz reverb steady state step +*/ +static void EMU_CALL reverb_steadystate22(struct SPUCORE_STATE *state, uint16 *ram, sint32 input_l, sint32 input_r) { + /* + ** Current reverb offset + */ + sint32 current = state->reverb.current_address; + /* + ** Reverb registers + */ + sint32 fb_src_a = MAKE_REVERB_OFFSET(FB_SRC_A); + sint32 fb_src_b = MAKE_REVERB_OFFSET(FB_SRC_B); + sint32 iir_alpha = MAKE_SINT32_COEF(IIR_ALPHA); + sint32 acc_coef_a = MAKE_SINT32_COEF(ACC_COEF_A); + sint32 acc_coef_b = MAKE_SINT32_COEF(ACC_COEF_B); + sint32 acc_coef_c = MAKE_SINT32_COEF(ACC_COEF_C); + sint32 acc_coef_d = MAKE_SINT32_COEF(ACC_COEF_D); + sint32 iir_coef = MAKE_SINT32_COEF(IIR_COEF); + sint32 fb_alpha = MAKE_SINT32_COEF(FB_ALPHA); + sint32 fb_x = MAKE_SINT32_COEF(FB_X); + sint32 iir_dest_a0 = MAKE_REVERB_OFFSET(IIR_DEST_A0); + sint32 iir_dest_a1 = MAKE_REVERB_OFFSET(IIR_DEST_A1); + sint32 acc_src_a0 = MAKE_REVERB_OFFSET(ACC_SRC_A0); + sint32 acc_src_a1 = MAKE_REVERB_OFFSET(ACC_SRC_A1); + sint32 acc_src_b0 = MAKE_REVERB_OFFSET(ACC_SRC_B0); + sint32 acc_src_b1 = MAKE_REVERB_OFFSET(ACC_SRC_B1); + sint32 iir_src_a0 = MAKE_REVERB_OFFSET(IIR_SRC_A0); + sint32 iir_src_a1 = MAKE_REVERB_OFFSET(IIR_SRC_A1); + sint32 iir_dest_b0 = MAKE_REVERB_OFFSET(IIR_DEST_B0); + sint32 iir_dest_b1 = MAKE_REVERB_OFFSET(IIR_DEST_B1); + sint32 acc_src_c0 = MAKE_REVERB_OFFSET(ACC_SRC_C0); + sint32 acc_src_c1 = MAKE_REVERB_OFFSET(ACC_SRC_C1); + sint32 acc_src_d0 = MAKE_REVERB_OFFSET(ACC_SRC_D0); + sint32 acc_src_d1 = MAKE_REVERB_OFFSET(ACC_SRC_D1); + sint32 iir_src_b1 = MAKE_REVERB_OFFSET(IIR_SRC_B1); + sint32 iir_src_b0 = MAKE_REVERB_OFFSET(IIR_SRC_B0); + sint32 mix_dest_a0 = MAKE_REVERB_OFFSET(MIX_DEST_A0); + sint32 mix_dest_a1 = MAKE_REVERB_OFFSET(MIX_DEST_A1); + sint32 mix_dest_b0 = MAKE_REVERB_OFFSET(MIX_DEST_B0); + sint32 mix_dest_b1 = MAKE_REVERB_OFFSET(MIX_DEST_B1); + sint32 in_coef_l = MAKE_SINT32_COEF(IN_COEF_L); + sint32 in_coef_r = MAKE_SINT32_COEF(IN_COEF_R); + /* + ** Alternate buffer positions + */ + sint32 fb_src_a0; + sint32 fb_src_a1; + sint32 fb_src_b0; + sint32 fb_src_b1; + sint32 iir_dest_a0_plus; + sint32 iir_dest_a1_plus; + sint32 iir_dest_b0_plus; + sint32 iir_dest_b1_plus; + /* + ** Intermediate results + */ + sint32 acc0; + sint32 acc1; + sint32 iir_input_a0; + sint32 iir_input_a1; + sint32 iir_input_b0; + sint32 iir_input_b1; + sint32 iir_a0; + sint32 iir_a1; + sint32 iir_b0; + sint32 iir_b1; + sint32 fb_a0; + sint32 fb_a1; + sint32 fb_b0; + sint32 fb_b1; + sint32 mix_a0; + sint32 mix_a1; + sint32 mix_b0; + sint32 mix_b1; + + /* + ** Offsets + */ + mix_dest_a0 += current; NORMALIZE_REVERB_OFFSET(mix_dest_a0); + mix_dest_a1 += current; NORMALIZE_REVERB_OFFSET(mix_dest_a1); + mix_dest_b0 += current; NORMALIZE_REVERB_OFFSET(mix_dest_b0); + mix_dest_b1 += current; NORMALIZE_REVERB_OFFSET(mix_dest_b1); + fb_src_a0 = mix_dest_a0 - fb_src_a; NORMALIZE_REVERB_OFFSET(fb_src_a0); + fb_src_a1 = mix_dest_a1 - fb_src_a; NORMALIZE_REVERB_OFFSET(fb_src_a1); + fb_src_b0 = mix_dest_b0 - fb_src_b; NORMALIZE_REVERB_OFFSET(fb_src_b0); + fb_src_b1 = mix_dest_b1 - fb_src_b; NORMALIZE_REVERB_OFFSET(fb_src_b1); + acc_src_a0 += current; NORMALIZE_REVERB_OFFSET(acc_src_a0); + acc_src_a1 += current; NORMALIZE_REVERB_OFFSET(acc_src_a1); + acc_src_b0 += current; NORMALIZE_REVERB_OFFSET(acc_src_b0); + acc_src_b1 += current; NORMALIZE_REVERB_OFFSET(acc_src_b1); + acc_src_c0 += current; NORMALIZE_REVERB_OFFSET(acc_src_c0); + acc_src_c1 += current; NORMALIZE_REVERB_OFFSET(acc_src_c1); + acc_src_d0 += current; NORMALIZE_REVERB_OFFSET(acc_src_d0); + acc_src_d1 += current; NORMALIZE_REVERB_OFFSET(acc_src_d1); + iir_src_a0 += current; NORMALIZE_REVERB_OFFSET(iir_src_a0); + iir_src_a1 += current; NORMALIZE_REVERB_OFFSET(iir_src_a1); + iir_src_b0 += current; NORMALIZE_REVERB_OFFSET(iir_src_b0); + iir_src_b1 += current; NORMALIZE_REVERB_OFFSET(iir_src_b1); + iir_dest_a0 += current; NORMALIZE_REVERB_OFFSET(iir_dest_a0); + iir_dest_a1 += current; NORMALIZE_REVERB_OFFSET(iir_dest_a1); + iir_dest_b0 += current; NORMALIZE_REVERB_OFFSET(iir_dest_b0); + iir_dest_b1 += current; NORMALIZE_REVERB_OFFSET(iir_dest_b1); + iir_dest_a0_plus = iir_dest_a0 + 2; NORMALIZE_REVERB_OFFSET(iir_dest_a0_plus); + iir_dest_a1_plus = iir_dest_a1 + 2; NORMALIZE_REVERB_OFFSET(iir_dest_a1_plus); + iir_dest_b0_plus = iir_dest_b0 + 2; NORMALIZE_REVERB_OFFSET(iir_dest_b0_plus); + iir_dest_b1_plus = iir_dest_b1 + 2; NORMALIZE_REVERB_OFFSET(iir_dest_b1_plus); + + /* + ** IIR + */ + CLIP_PCM_2(input_l,input_r); + input_l *= in_coef_l; + input_r *= in_coef_r; +#define OPPOSITE_IIR_ALPHA (32768-iir_alpha) + iir_input_a0 = ((RAM_SINT32_SAMPLE(iir_src_a0) * iir_coef) + input_l) >> 15; + iir_input_a1 = ((RAM_SINT32_SAMPLE(iir_src_a1) * iir_coef) + input_r) >> 15; + iir_input_b0 = ((RAM_SINT32_SAMPLE(iir_src_b0) * iir_coef) + input_l) >> 15; + iir_input_b1 = ((RAM_SINT32_SAMPLE(iir_src_b1) * iir_coef) + input_r) >> 15; + CLIP_PCM_4(iir_input_a0,iir_input_a1,iir_input_b0,iir_input_b1); + iir_a0 = ((iir_input_a0 * iir_alpha) + (RAM_SINT32_SAMPLE(iir_dest_a0) * (OPPOSITE_IIR_ALPHA))) >> 15; + iir_a1 = ((iir_input_a1 * iir_alpha) + (RAM_SINT32_SAMPLE(iir_dest_a1) * (OPPOSITE_IIR_ALPHA))) >> 15; + iir_b0 = ((iir_input_b0 * iir_alpha) + (RAM_SINT32_SAMPLE(iir_dest_b0) * (OPPOSITE_IIR_ALPHA))) >> 15; + iir_b1 = ((iir_input_b1 * iir_alpha) + (RAM_SINT32_SAMPLE(iir_dest_b1) * (OPPOSITE_IIR_ALPHA))) >> 15; + CLIP_PCM_4(iir_a0,iir_a1,iir_b0,iir_b1); + + RAM_PCM_SAMPLE(iir_dest_a0_plus) = iir_a0; + RAM_PCM_SAMPLE(iir_dest_a1_plus) = iir_a1; + RAM_PCM_SAMPLE(iir_dest_b0_plus) = iir_b0; + RAM_PCM_SAMPLE(iir_dest_b1_plus) = iir_b1; + + /* + ** Accumulators + */ + acc0 = + ((RAM_SINT32_SAMPLE(acc_src_a0) * acc_coef_a) >> 15) + + ((RAM_SINT32_SAMPLE(acc_src_b0) * acc_coef_b) >> 15) + + ((RAM_SINT32_SAMPLE(acc_src_c0) * acc_coef_c) >> 15) + + ((RAM_SINT32_SAMPLE(acc_src_d0) * acc_coef_d) >> 15); + acc1 = + ((RAM_SINT32_SAMPLE(acc_src_a1) * acc_coef_a) >> 15) + + ((RAM_SINT32_SAMPLE(acc_src_b1) * acc_coef_b) >> 15) + + ((RAM_SINT32_SAMPLE(acc_src_c1) * acc_coef_c) >> 15) + + ((RAM_SINT32_SAMPLE(acc_src_d1) * acc_coef_d) >> 15); + CLIP_PCM_2(acc0,acc1); + + /* + ** Feedback + */ + fb_a0 = RAM_SINT32_SAMPLE(fb_src_a0); + fb_a1 = RAM_SINT32_SAMPLE(fb_src_a1); + fb_b0 = RAM_SINT32_SAMPLE(fb_src_b0); + fb_b1 = RAM_SINT32_SAMPLE(fb_src_b1); + + mix_a0 = acc0 - ((fb_a0*fb_alpha)>>15); + mix_a1 = acc1 - ((fb_a1*fb_alpha)>>15); + mix_b0 = fb_alpha*acc0; + mix_b1 = fb_alpha*acc1; + fb_alpha = ((sint32)((sint16)(((sint16)fb_alpha)^0x8000))); + mix_b0 -= fb_a0*fb_alpha; + mix_b1 -= fb_a1*fb_alpha; + mix_b0 -= fb_b0*fb_x; + mix_b1 -= fb_b1*fb_x; + mix_b0>>=15; + mix_b1>>=15; + + CLIP_PCM_4(mix_a0,mix_a1,mix_b0,mix_b1); + RAM_PCM_SAMPLE(mix_dest_a0) = mix_a0; + RAM_PCM_SAMPLE(mix_dest_a1) = mix_a1; + RAM_PCM_SAMPLE(mix_dest_b0) = mix_b0; + RAM_PCM_SAMPLE(mix_dest_b1) = mix_b1; + +} + +//////////////////////////////////////////////////////////////////////////////// +/* +** 22KHz reverb engine +*/ +static void EMU_CALL reverb_engine22(struct SPUCORE_STATE *state, uint16 *ram, sint32 *l, sint32 *r) { + sint32 input_l = *l; + sint32 input_r = *r; + sint32 output_l; + sint32 output_r; + sint32 mix_dest_a0 = state->reverb.current_address + MAKE_REVERB_OFFSET(MIX_DEST_A0); + sint32 mix_dest_a1 = state->reverb.current_address + MAKE_REVERB_OFFSET(MIX_DEST_A1); + sint32 mix_dest_b0 = state->reverb.current_address + MAKE_REVERB_OFFSET(MIX_DEST_B0); + sint32 mix_dest_b1 = state->reverb.current_address + MAKE_REVERB_OFFSET(MIX_DEST_B1); + NORMALIZE_REVERB_OFFSET(mix_dest_a0); + NORMALIZE_REVERB_OFFSET(mix_dest_a1); + NORMALIZE_REVERB_OFFSET(mix_dest_b0); + NORMALIZE_REVERB_OFFSET(mix_dest_b1); + + /* + ** (Scale these down for now - avoids some clipping) + */ + input_l *= 2; + input_r *= 2; + input_l /= 3; + input_r /= 3; + + /* + ** Execute steady state step if necessary + */ + if(state->flags & SPUREG_FLAG_REVERB_ENABLE) { + reverb_steadystate22(state, ram, input_l, input_r); + } + + /* + ** Retrieve wet out L/R + ** (pretty certain this is done AFTER the steady state step) + */ + { + int al = RAM_SINT32_SAMPLE(mix_dest_a0); + int ar = RAM_SINT32_SAMPLE(mix_dest_a1); + int bl = RAM_SINT32_SAMPLE(mix_dest_b0); + int br = RAM_SINT32_SAMPLE(mix_dest_b1); + + output_l = al + bl; + output_r = ar + br; + } + + *l = output_l; + *r = output_r; + + /* + ** Advance reverb buffer position + */ + state->reverb.current_address += 2; + if(state->reverb.current_address >= state->reverb.safe_end_address) { + state->reverb.current_address = state->reverb.safe_start_address; + } +} + +//////////////////////////////////////////////////////////////////////////////// + +static void EMU_CALL reverb_process(struct SPUCORE_STATE *state, uint16 *ram, sint32 *buf, int samples) { + int n; + int q = state->reverb.resampler.queue_index; + /* + ** Sample loop + */ + while(samples--) { + /* + ** Get an input sample + */ + sint32 l = buf[0]; + sint32 r = buf[1]; + /* + ** Put it in the input queue + */ + state->reverb.resampler.in_queue_l[q & 63] = l; + state->reverb.resampler.in_queue_r[q & 63] = r; + /* + ** If we're ready to create another output sample... + */ + if(q & 1) { + /* + ** Lowpass/downsample + */ +#if 1 + l = + (state->reverb.resampler.in_queue_l[(q - 38) & 63]) * reverb_psx_lowpass_coefs[0] + + (state->reverb.resampler.in_queue_l[(q - 36) & 63]) * reverb_psx_lowpass_coefs[1] + + (state->reverb.resampler.in_queue_l[(q - 34) & 63]) * reverb_psx_lowpass_coefs[2] + + (state->reverb.resampler.in_queue_l[(q - 32) & 63]) * reverb_psx_lowpass_coefs[3] + + (state->reverb.resampler.in_queue_l[(q - 30) & 63]) * reverb_psx_lowpass_coefs[4] + + (state->reverb.resampler.in_queue_l[(q - 28) & 63]) * reverb_psx_lowpass_coefs[5] + + (state->reverb.resampler.in_queue_l[(q - 26) & 63]) * reverb_psx_lowpass_coefs[6] + + (state->reverb.resampler.in_queue_l[(q - 24) & 63]) * reverb_psx_lowpass_coefs[7] + + (state->reverb.resampler.in_queue_l[(q - 22) & 63]) * reverb_psx_lowpass_coefs[8] + + (state->reverb.resampler.in_queue_l[(q - 20) & 63]) * reverb_psx_lowpass_coefs[9] + + (state->reverb.resampler.in_queue_l[(q - 19) & 63]) * reverb_psx_lowpass_coefs[10] + + (state->reverb.resampler.in_queue_l[(q - 18) & 63]) * reverb_psx_lowpass_coefs[9] + + (state->reverb.resampler.in_queue_l[(q - 16) & 63]) * reverb_psx_lowpass_coefs[8] + + (state->reverb.resampler.in_queue_l[(q - 14) & 63]) * reverb_psx_lowpass_coefs[7] + + (state->reverb.resampler.in_queue_l[(q - 12) & 63]) * reverb_psx_lowpass_coefs[6] + + (state->reverb.resampler.in_queue_l[(q - 10) & 63]) * reverb_psx_lowpass_coefs[5] + + (state->reverb.resampler.in_queue_l[(q - 8) & 63]) * reverb_psx_lowpass_coefs[4] + + (state->reverb.resampler.in_queue_l[(q - 6) & 63]) * reverb_psx_lowpass_coefs[3] + + (state->reverb.resampler.in_queue_l[(q - 4) & 63]) * reverb_psx_lowpass_coefs[2] + + (state->reverb.resampler.in_queue_l[(q - 2) & 63]) * reverb_psx_lowpass_coefs[1] + + (state->reverb.resampler.in_queue_l[(q - 0) & 63]) * reverb_psx_lowpass_coefs[0]; + r = + (state->reverb.resampler.in_queue_r[(q - 38) & 63]) * reverb_psx_lowpass_coefs[0] + + (state->reverb.resampler.in_queue_r[(q - 36) & 63]) * reverb_psx_lowpass_coefs[1] + + (state->reverb.resampler.in_queue_r[(q - 34) & 63]) * reverb_psx_lowpass_coefs[2] + + (state->reverb.resampler.in_queue_r[(q - 32) & 63]) * reverb_psx_lowpass_coefs[3] + + (state->reverb.resampler.in_queue_r[(q - 30) & 63]) * reverb_psx_lowpass_coefs[4] + + (state->reverb.resampler.in_queue_r[(q - 28) & 63]) * reverb_psx_lowpass_coefs[5] + + (state->reverb.resampler.in_queue_r[(q - 26) & 63]) * reverb_psx_lowpass_coefs[6] + + (state->reverb.resampler.in_queue_r[(q - 24) & 63]) * reverb_psx_lowpass_coefs[7] + + (state->reverb.resampler.in_queue_r[(q - 22) & 63]) * reverb_psx_lowpass_coefs[8] + + (state->reverb.resampler.in_queue_r[(q - 20) & 63]) * reverb_psx_lowpass_coefs[9] + + (state->reverb.resampler.in_queue_r[(q - 19) & 63]) * reverb_psx_lowpass_coefs[10] + + (state->reverb.resampler.in_queue_r[(q - 18) & 63]) * reverb_psx_lowpass_coefs[9] + + (state->reverb.resampler.in_queue_r[(q - 16) & 63]) * reverb_psx_lowpass_coefs[8] + + (state->reverb.resampler.in_queue_r[(q - 14) & 63]) * reverb_psx_lowpass_coefs[7] + + (state->reverb.resampler.in_queue_r[(q - 12) & 63]) * reverb_psx_lowpass_coefs[6] + + (state->reverb.resampler.in_queue_r[(q - 10) & 63]) * reverb_psx_lowpass_coefs[5] + + (state->reverb.resampler.in_queue_r[(q - 8) & 63]) * reverb_psx_lowpass_coefs[4] + + (state->reverb.resampler.in_queue_r[(q - 6) & 63]) * reverb_psx_lowpass_coefs[3] + + (state->reverb.resampler.in_queue_r[(q - 4) & 63]) * reverb_psx_lowpass_coefs[2] + + (state->reverb.resampler.in_queue_r[(q - 2) & 63]) * reverb_psx_lowpass_coefs[1] + + (state->reverb.resampler.in_queue_r[(q - 0) & 63]) * reverb_psx_lowpass_coefs[0]; +#else + l = 0; + r = 0; + + for (n = 47; n >= 0; n -= 8) { + l += + (state->reverb.resampler.in_queue_l[(q - n + 0) & 63]) * reverb_psx_lowpass_coefs[n - 0] + + (state->reverb.resampler.in_queue_l[(q - n + 1) & 63]) * reverb_psx_lowpass_coefs[n - 1] + + (state->reverb.resampler.in_queue_l[(q - n + 2) & 63]) * reverb_psx_lowpass_coefs[n - 2] + + (state->reverb.resampler.in_queue_l[(q - n + 3) & 63]) * reverb_psx_lowpass_coefs[n - 3] + + (state->reverb.resampler.in_queue_l[(q - n + 4) & 63]) * reverb_psx_lowpass_coefs[n - 4] + + (state->reverb.resampler.in_queue_l[(q - n + 5) & 63]) * reverb_psx_lowpass_coefs[n - 5] + + (state->reverb.resampler.in_queue_l[(q - n + 6) & 63]) * reverb_psx_lowpass_coefs[n - 6] + + (state->reverb.resampler.in_queue_l[(q - n + 7) & 63]) * reverb_psx_lowpass_coefs[n - 7]; + r += + (state->reverb.resampler.in_queue_r[(q - n + 0) & 63]) * reverb_psx_lowpass_coefs[n - 0] + + (state->reverb.resampler.in_queue_r[(q - n + 1) & 63]) * reverb_psx_lowpass_coefs[n - 1] + + (state->reverb.resampler.in_queue_r[(q - n + 2) & 63]) * reverb_psx_lowpass_coefs[n - 2] + + (state->reverb.resampler.in_queue_r[(q - n + 3) & 63]) * reverb_psx_lowpass_coefs[n - 3] + + (state->reverb.resampler.in_queue_r[(q - n + 4) & 63]) * reverb_psx_lowpass_coefs[n - 4] + + (state->reverb.resampler.in_queue_r[(q - n + 5) & 63]) * reverb_psx_lowpass_coefs[n - 5] + + (state->reverb.resampler.in_queue_r[(q - n + 6) & 63]) * reverb_psx_lowpass_coefs[n - 6] + + (state->reverb.resampler.in_queue_r[(q - n + 7) & 63]) * reverb_psx_lowpass_coefs[n - 7]; + } +#endif + + l >>= 15; + r >>= 15; + +/* + l = + (state->reverb.resampler.in_queue_l[(q - 6) & 7]) * reverb_new_lowpass_coefs[0] + + (state->reverb.resampler.in_queue_l[(q - 4) & 7]) * reverb_new_lowpass_coefs[1] + + (state->reverb.resampler.in_queue_l[(q - 3) & 7]) * reverb_new_lowpass_coefs[2] + + (state->reverb.resampler.in_queue_l[(q - 2) & 7]) * reverb_new_lowpass_coefs[1] + + (state->reverb.resampler.in_queue_l[(q - 0) & 7]) * reverb_new_lowpass_coefs[0]; + l >>= 11; + r = + (state->reverb.resampler.in_queue_r[(q - 6) & 7]) * reverb_new_lowpass_coefs[0] + + (state->reverb.resampler.in_queue_r[(q - 4) & 7]) * reverb_new_lowpass_coefs[1] + + (state->reverb.resampler.in_queue_r[(q - 3) & 7]) * reverb_new_lowpass_coefs[2] + + (state->reverb.resampler.in_queue_r[(q - 2) & 7]) * reverb_new_lowpass_coefs[1] + + (state->reverb.resampler.in_queue_r[(q - 0) & 7]) * reverb_new_lowpass_coefs[0]; + r >>= 11; +*/ +//l = state->reverb.resampler.in_queue_l[q & 7]; +//r = state->reverb.resampler.in_queue_r[q & 7]; + + /* + ** Run the reverb engine + */ + reverb_engine22(state, ram, &l, &r); + /* + ** Put the new stuff into the output queue + */ + state->reverb.resampler.out_queue_l[q & 15] = l; + state->reverb.resampler.out_queue_r[q & 15] = r; + } + /* + ** Upsample + */ + /* + ** Upsample using the same technique as for ADPCM samples + ** (may or may not be right, sounds okay though) + */ +#define gauss_table_0x000 gauss_shuffled_reverse_table[0x200] +#define gauss_table_0x100 gauss_shuffled_reverse_table[0x201] +#define gauss_table_0x200 gauss_shuffled_reverse_table[0x202] +#define gauss_table_0x300 gauss_shuffled_reverse_table[0x203] +#define gauss_table_0x080 gauss_shuffled_reverse_table[0x000] +#define gauss_table_0x180 gauss_shuffled_reverse_table[0x001] +#define gauss_table_0x280 gauss_shuffled_reverse_table[0x002] +#define gauss_table_0x380 gauss_shuffled_reverse_table[0x003] + if(q & 1) { + l = + (state->reverb.resampler.out_queue_l[(q - 6) & 15]) * gauss_table_0x080 + + (state->reverb.resampler.out_queue_l[(q - 4) & 15]) * gauss_table_0x180 + + (state->reverb.resampler.out_queue_l[(q - 2) & 15]) * gauss_table_0x280 + + (state->reverb.resampler.out_queue_l[(q - 0) & 15]) * gauss_table_0x380; + l >>= 15; + r = + (state->reverb.resampler.out_queue_r[(q - 6) & 15]) * gauss_table_0x080 + + (state->reverb.resampler.out_queue_r[(q - 4) & 15]) * gauss_table_0x180 + + (state->reverb.resampler.out_queue_r[(q - 2) & 15]) * gauss_table_0x280 + + (state->reverb.resampler.out_queue_r[(q - 0) & 15]) * gauss_table_0x380; + r >>= 15; + } else { + l = + (state->reverb.resampler.out_queue_l[(q - 7) & 15]) * gauss_table_0x000 + + (state->reverb.resampler.out_queue_l[(q - 5) & 15]) * gauss_table_0x100 + + (state->reverb.resampler.out_queue_l[(q - 3) & 15]) * gauss_table_0x200 + + (state->reverb.resampler.out_queue_l[(q - 1) & 15]) * gauss_table_0x300; + l >>= 15; + r = + (state->reverb.resampler.out_queue_r[(q - 7) & 15]) * gauss_table_0x000 + + (state->reverb.resampler.out_queue_r[(q - 5) & 15]) * gauss_table_0x100 + + (state->reverb.resampler.out_queue_r[(q - 3) & 15]) * gauss_table_0x200 + + (state->reverb.resampler.out_queue_r[(q - 1) & 15]) * gauss_table_0x300; + r >>= 15; + } + /* + ** Advance queue position, write output, all that good stuff + */ + q++; + buf[0] = l; + buf[1] = r; + buf += 2; + } + state->reverb.resampler.queue_index = q; +} + +//////////////////////////////////////////////////////////////////////////////// + +//int spucore_frq[RENDERMAX]; + +/* +** Renderer +*/ +static void EMU_CALL render(struct SPUCORE_STATE *state, uint16 *ram, sint16 *buf, sint16 *extinput, sint32 samples, uint8 mainout, uint8 effectout) { + uint32 chanbit; + uint32 maskmain_l; + uint32 maskmain_r; + uint32 maskverb_l; + uint32 maskverb_r; + uint32 masknoise; + uint32 maskfm; + sint32 ibuf [ RENDERMAX]; + sint32 ibufmix[2*RENDERMAX]; + sint32 ibufrvb[2*RENDERMAX]; + sint32 ibufn [ RENDERMAX]; + sint32 ibuffm [ RENDERMAX]; + int ch, i; + sint32 m_v_l; + sint32 m_v_r; + sint32 r_v_l; + sint32 r_v_r; + struct SPUCORE_IRQ_STATE irq_state; + struct SPUCORE_IRQ_STATE *irq_state_ptr; + + //spucore_frq[samples]++; + + irq_state_ptr = NULL; + irq_state.triggered_cycle = 0xFFFFFFFF; + if (state->flags & SPUREG_FLAG_IRQ_ENABLE) { + if (state->memsize == 0x80000 && state->irq_address < 0x1000) { + uint32 irq_address_masked = state->irq_address & 0x3FF; + uint32 irq_sample_offset = irq_address_masked - state->irq_decoder_clock; + if(irq_sample_offset > 0x3FF) irq_sample_offset += 0x400; + if (irq_sample_offset < (uint32)samples) { + irq_state.triggered_cycle = irq_sample_offset * 768; + } + } else { + irq_state_ptr = &irq_state; + irq_state.offset = state->irq_address; + } + } + + state->irq_decoder_clock = (state->irq_decoder_clock + samples) & 0x3FF; + + memset(ibufmix, 0, 8 * samples); + if(effectout) { + memset(ibufrvb, 0, 8 * samples); + } + + maskmain_l = 0; + maskmain_r = 0; + maskverb_l = 0; + maskverb_r = 0; + if(state->flags & SPUREG_FLAG_MSNDL) maskmain_l = state->vmix[0] & 0xFFFFFF; + if(state->flags & SPUREG_FLAG_MSNDR) maskmain_r = state->vmix[1] & 0xFFFFFF; + if(effectout) { + if(state->flags & SPUREG_FLAG_MSNDEL) maskverb_l = state->vmixe[0] & 0xFFFFFF; + if(state->flags & SPUREG_FLAG_MSNDER) maskverb_r = state->vmixe[1] & 0xFFFFFF; + } + masknoise = state->noise; + render_noise(state, masknoise ? ibufn : NULL, samples); + maskfm = state->fm & 0xFFFFFE; + + if(!mainout) { maskmain_l = 0; maskmain_r = 0; } + + for(ch = 0, chanbit = 1; ch < 24; ch++, chanbit <<= 1) { + int r; + sint32 v_l, v_r; + uint32 main_l = chanbit & maskmain_l; + uint32 main_r = chanbit & maskmain_r; + uint32 verb_l = chanbit & maskverb_l; + uint32 verb_r = chanbit & maskverb_r; + sint32 *b = buf ? ibuf : NULL; + sint32 *fm = (chanbit & maskfm) ? ibuffm : NULL; + sint32 *noise = (chanbit & masknoise) ? ibufn : NULL; + if(!(main_l | main_r | verb_l | verb_r)) b = NULL; + r = render_channel_mono( + ram, state->memsize, state->chan + ch, b, fm, noise, samples, irq_state_ptr + ); + if(!b) { + memset(ibuffm, 0, 4 * samples); + continue; + } + memcpy(ibuffm, ibuf, 4 * r); + if(r < samples) memset(ibuffm + r, 0, 4 * (samples-r)); + v_l = volume_getlevel(state->chan[ch].vol+0); + v_r = volume_getlevel(state->chan[ch].vol+1); + for(i = 0; i < r; i++) { + sint32 q_l = (v_l * ibuf[i]) >> 16; + sint32 q_r = (v_r * ibuf[i]) >> 16; + if(main_l) ibufmix[2*i+0] += q_l; + if(main_r) ibufmix[2*i+1] += q_r; + if(verb_l) ibufrvb[2*i+0] += q_l; + if(verb_r) ibufrvb[2*i+1] += q_r; + } + } + + state->irq_triggered_cycle = irq_state.triggered_cycle; + + if(!buf) return; + + /* + ** Mix in external input, if it exists + */ + if(extinput) { + sint32 extvol_l = ((sint16)(state->avol[0])); + sint32 extvol_r = ((sint16)(state->avol[1])); + if(extvol_l == -0x8000) extvol_l = -0x7FFF; + if(extvol_r == -0x8000) extvol_r = -0x7FFF; + for(i = 0; i < samples; i++) { + sint32 sin_l = extinput[2*i+0]; + sint32 sin_r = extinput[2*i+1]; + sin_l *= extvol_l; + sin_r *= extvol_r; + sin_l >>= 15; + sin_r >>= 15; + if(state->flags & SPUREG_FLAG_SINL ) ibufmix[2*i+0] += sin_l; + if(state->flags & SPUREG_FLAG_SINR ) ibufmix[2*i+1] += sin_r; + if(state->flags & SPUREG_FLAG_SINEL) ibufrvb[2*i+0] += sin_l; + if(state->flags & SPUREG_FLAG_SINER) ibufrvb[2*i+1] += sin_r; + } + } + + /* + ** Do reverb + ** This handles both writing into the buffer and retrieving + ** values out of it, resampling to/from 22KHz, etc. + */ + if(effectout) { + reverb_process(state, ram, ibufrvb, samples); + } + /* + ** + */ + m_v_l = volume_getlevel(state->mvol+0); + m_v_r = volume_getlevel(state->mvol+1); + r_v_l = ((sint16)(state->evol[0])); + r_v_r = ((sint16)(state->evol[1])); + + if(!effectout) { + for(i = 0; i < samples; i++) { + sint64 q_l = ibufmix[2*i+0]; + sint64 q_r = ibufmix[2*i+1]; + q_l *= (sint64)m_v_l; + q_r *= (sint64)m_v_r; + q_l >>= 15; + q_r >>= 15; + CLIP_PCM_2(q_l,q_r); + *buf++ = (sint16)q_l; + *buf++ = (sint16)q_r; + } + } else { + for(i = 0; i < samples; i++) { + sint64 q_l = ibufmix[2*i+0]; + sint64 q_r = ibufmix[2*i+1]; + sint64 r_l = ibufrvb[2*i+0]; + sint64 r_r = ibufrvb[2*i+1]; + q_l *= (sint64)m_v_l; + q_r *= (sint64)m_v_r; + r_l *= (sint64)r_v_l; + r_r *= (sint64)r_v_r; + q_l >>= 15; + q_r >>= 15; + r_l >>= 15; + r_r >>= 15; + q_l += r_l; + q_r += r_r; + CLIP_PCM_2(q_l, q_r); + *buf++ = (sint16)q_l; + *buf++ = (sint16)q_r; + } + } +} + +//////////////////////////////////////////////////////////////////////////////// +/* +** Externally-accessible renderer +*/ +void EMU_CALL spucore_render(void *state, uint16 *ram, sint16 *buf, sint16 *extinput, uint32 samples, uint8 mainout, uint8 effectout) { + while(samples > RENDERMAX) { + samples -= RENDERMAX; + render(SPUCORESTATE, ram, buf, extinput, RENDERMAX, mainout, effectout); + if(buf ) buf += 2 * RENDERMAX; + if(extinput) extinput += 2 * RENDERMAX; + } + if(samples) render(SPUCORESTATE, ram, buf, extinput, samples, mainout, effectout); +} + +//////////////////////////////////////////////////////////////////////////////// +/* +** Flag get/set +*/ + +int EMU_CALL spucore_getflag(void *state, uint32 n) { + return !!(SPUCORESTATE->flags & n); +} + +void EMU_CALL spucore_setflag(void *state, uint32 n, int value) { + if(value) { + SPUCORESTATE->flags |= n; + } else { + SPUCORESTATE->flags &= ~n; + } +} + +//////////////////////////////////////////////////////////////////////////////// +/* +** Register get/set +*/ + +uint32 EMU_CALL spucore_getreg(void *state, uint32 n) { + switch(n) { + case SPUREG_MVOLL: return volume_getmode (SPUCORESTATE->mvol+0) & 0x0000FFFF; + case SPUREG_MVOLR: return volume_getmode (SPUCORESTATE->mvol+1) & 0x0000FFFF; + case SPUREG_MVOLXL: return volume_getlevel(SPUCORESTATE->mvol+0) & 0x0000FFFF; + case SPUREG_MVOLXR: return volume_getlevel(SPUCORESTATE->mvol+1) & 0x0000FFFF; + case SPUREG_EVOLL: return SPUCORESTATE->evol[0] & 0x0000FFFF; + case SPUREG_EVOLR: return SPUCORESTATE->evol[1] & 0x0000FFFF; + case SPUREG_AVOLL: return SPUCORESTATE->avol[0] & 0x0000FFFF; + case SPUREG_AVOLR: return SPUCORESTATE->avol[1] & 0x0000FFFF; + case SPUREG_BVOLL: return SPUCORESTATE->bvol[0] & 0x0000FFFF; + case SPUREG_BVOLR: return SPUCORESTATE->bvol[1] & 0x0000FFFF; + case SPUREG_KON: return SPUCORESTATE->kon & 0x00FFFFFF; + case SPUREG_KOFF: return SPUCORESTATE->koff & 0x00FFFFFF; + case SPUREG_FM: return SPUCORESTATE->fm & 0x00FFFFFF; + case SPUREG_NOISE: return SPUCORESTATE->noise & 0x00FFFFFF; + case SPUREG_VMIXE: return (SPUCORESTATE->vmixe[0] | SPUCORESTATE->vmixe[1]) & 0xFFFFFF; + case SPUREG_VMIX: return (SPUCORESTATE->vmix[0] | SPUCORESTATE->vmix[1] ) & 0xFFFFFF; + case SPUREG_VMIXEL: return SPUCORESTATE->vmixe[0] & 0x00FFFFFF; + case SPUREG_VMIXER: return SPUCORESTATE->vmixe[1] & 0x00FFFFFF; + case SPUREG_VMIXL: return SPUCORESTATE->vmix[0] & 0x00FFFFFF; + case SPUREG_VMIXR: return SPUCORESTATE->vmix[1] & 0x00FFFFFF; + case SPUREG_ESA: return SPUCORESTATE->reverb.start_address; + case SPUREG_EEA: return SPUCORESTATE->reverb.end_address; + case SPUREG_EAX: return SPUCORESTATE->reverb.current_address; + case SPUREG_IRQA: return SPUCORESTATE->irq_address; + case SPUREG_NOISECLOCK: return SPUCORESTATE->noiseclock; +#define SPUCORE_REVERB_GET(x) case SPUREG_REVERB_##x:return SPUCORESTATE->reverb.x; + SPUCORE_REVERB_GET(FB_SRC_A) + SPUCORE_REVERB_GET(FB_SRC_B) + SPUCORE_REVERB_GET(IIR_ALPHA) + SPUCORE_REVERB_GET(ACC_COEF_A) + SPUCORE_REVERB_GET(ACC_COEF_B) + SPUCORE_REVERB_GET(ACC_COEF_C) + SPUCORE_REVERB_GET(ACC_COEF_D) + SPUCORE_REVERB_GET(IIR_COEF) + SPUCORE_REVERB_GET(FB_ALPHA) + SPUCORE_REVERB_GET(FB_X) + SPUCORE_REVERB_GET(IIR_DEST_A0) + SPUCORE_REVERB_GET(IIR_DEST_A1) + SPUCORE_REVERB_GET(ACC_SRC_A0) + SPUCORE_REVERB_GET(ACC_SRC_A1) + SPUCORE_REVERB_GET(ACC_SRC_B0) + SPUCORE_REVERB_GET(ACC_SRC_B1) + SPUCORE_REVERB_GET(IIR_SRC_A0) + SPUCORE_REVERB_GET(IIR_SRC_A1) + SPUCORE_REVERB_GET(IIR_DEST_B0) + SPUCORE_REVERB_GET(IIR_DEST_B1) + SPUCORE_REVERB_GET(ACC_SRC_C0) + SPUCORE_REVERB_GET(ACC_SRC_C1) + SPUCORE_REVERB_GET(ACC_SRC_D0) + SPUCORE_REVERB_GET(ACC_SRC_D1) + SPUCORE_REVERB_GET(IIR_SRC_B1) + SPUCORE_REVERB_GET(IIR_SRC_B0) + SPUCORE_REVERB_GET(MIX_DEST_A0) + SPUCORE_REVERB_GET(MIX_DEST_A1) + SPUCORE_REVERB_GET(MIX_DEST_B0) + SPUCORE_REVERB_GET(MIX_DEST_B1) + SPUCORE_REVERB_GET(IN_COEF_L) + SPUCORE_REVERB_GET(IN_COEF_R) + } + return 0; +} + +void EMU_CALL spucore_setreg(void *state, uint32 n, uint32 value, uint32 mask) { + value &= mask; + switch(n) { + /* TODO: the increase/decrease modes, etc. */ + case SPUREG_MVOLL: volume_setmode(SPUCORESTATE->mvol+0, value); break; + case SPUREG_MVOLR: volume_setmode(SPUCORESTATE->mvol+1, value); break; + case SPUREG_EVOLL: SPUCORESTATE->evol[0] = value; break; + case SPUREG_EVOLR: SPUCORESTATE->evol[1] = value; break; + case SPUREG_AVOLL: SPUCORESTATE->avol[0] = value; break; + case SPUREG_AVOLR: SPUCORESTATE->avol[1] = value; break; + case SPUREG_BVOLL: SPUCORESTATE->bvol[0] = value; break; + case SPUREG_BVOLR: SPUCORESTATE->bvol[1] = value; break; + + case SPUREG_KON: + SPUCORESTATE->kon &= ~mask; + SPUCORESTATE->kon |= value; + voices_on(state, value); + break; + case SPUREG_KOFF: + SPUCORESTATE->koff &= ~mask; + SPUCORESTATE->koff |= value; + voices_off(state, value); + break; + + case SPUREG_FM: + SPUCORESTATE->fm &= ~mask; + SPUCORESTATE->fm |= value; + break; + case SPUREG_NOISE: + SPUCORESTATE->noise &= ~mask; + SPUCORESTATE->noise |= value; + break; + case SPUREG_VMIXE: + SPUCORESTATE->vmixe[0] &= ~mask; + SPUCORESTATE->vmixe[0] |= value; + SPUCORESTATE->vmixe[1] &= ~mask; + SPUCORESTATE->vmixe[1] |= value; + break; + case SPUREG_VMIX: + SPUCORESTATE->vmix[0] &= ~mask; + SPUCORESTATE->vmix[0] |= value; + SPUCORESTATE->vmix[1] &= ~mask; + SPUCORESTATE->vmix[1] |= value; + break; + case SPUREG_VMIXEL: + SPUCORESTATE->vmixe[0] &= ~mask; + SPUCORESTATE->vmixe[0] |= value; + break; + case SPUREG_VMIXER: + SPUCORESTATE->vmixe[1] &= ~mask; + SPUCORESTATE->vmixe[1] |= value; + break; + case SPUREG_VMIXL: + SPUCORESTATE->vmix[0] &= ~mask; + SPUCORESTATE->vmix[0] |= value; + break; + case SPUREG_VMIXR: + SPUCORESTATE->vmix[1] &= ~mask; + SPUCORESTATE->vmix[1] |= value; + break; + + case SPUREG_ESA: + SPUCORESTATE->reverb.start_address &= ~mask; + SPUCORESTATE->reverb.start_address |= value; + make_safe_reverb_addresses(state); + SPUCORESTATE->reverb.current_address = SPUCORESTATE->reverb.safe_start_address; + break; + case SPUREG_EEA: + SPUCORESTATE->reverb.end_address &= ~mask; + SPUCORESTATE->reverb.end_address |= value; + make_safe_reverb_addresses(state); + break; + case SPUREG_IRQA: + /* TODO: actual implementation of IRQs */ + SPUCORESTATE->irq_address &= ~mask; + SPUCORESTATE->irq_address |= value; + break; + case SPUREG_NOISECLOCK: + SPUCORESTATE->noiseclock = value & 0x3F; + break; + +#define SPUCORE_REVERB_SET(x) case SPUREG_REVERB_##x:SPUCORESTATE->reverb.x&=(~mask);SPUCORESTATE->reverb.x|=value;break; + SPUCORE_REVERB_SET(FB_SRC_A) + SPUCORE_REVERB_SET(FB_SRC_B) + SPUCORE_REVERB_SET(IIR_ALPHA) + SPUCORE_REVERB_SET(ACC_COEF_A) + SPUCORE_REVERB_SET(ACC_COEF_B) + SPUCORE_REVERB_SET(ACC_COEF_C) + SPUCORE_REVERB_SET(ACC_COEF_D) + SPUCORE_REVERB_SET(IIR_COEF) + SPUCORE_REVERB_SET(FB_ALPHA) + SPUCORE_REVERB_SET(FB_X) + SPUCORE_REVERB_SET(IIR_DEST_A0) + SPUCORE_REVERB_SET(IIR_DEST_A1) + SPUCORE_REVERB_SET(ACC_SRC_A0) + SPUCORE_REVERB_SET(ACC_SRC_A1) + SPUCORE_REVERB_SET(ACC_SRC_B0) + SPUCORE_REVERB_SET(ACC_SRC_B1) + SPUCORE_REVERB_SET(IIR_SRC_A0) + SPUCORE_REVERB_SET(IIR_SRC_A1) + SPUCORE_REVERB_SET(IIR_DEST_B0) + SPUCORE_REVERB_SET(IIR_DEST_B1) + SPUCORE_REVERB_SET(ACC_SRC_C0) + SPUCORE_REVERB_SET(ACC_SRC_C1) + SPUCORE_REVERB_SET(ACC_SRC_D0) + SPUCORE_REVERB_SET(ACC_SRC_D1) + SPUCORE_REVERB_SET(IIR_SRC_B1) + SPUCORE_REVERB_SET(IIR_SRC_B0) + SPUCORE_REVERB_SET(MIX_DEST_A0) + SPUCORE_REVERB_SET(MIX_DEST_A1) + SPUCORE_REVERB_SET(MIX_DEST_B0) + SPUCORE_REVERB_SET(MIX_DEST_B1) + SPUCORE_REVERB_SET(IN_COEF_L) + SPUCORE_REVERB_SET(IN_COEF_R) + } +} + +//////////////////////////////////////////////////////////////////////////////// +/* +** Voice register get/set +*/ + +uint32 EMU_CALL spucore_getreg_voice(void *state, uint32 voice, uint32 n) { + switch(n) { + case SPUREG_VOICE_VOLL : return volume_getmode(SPUCORESTATE->chan[voice].vol+0); + case SPUREG_VOICE_VOLR : return volume_getmode(SPUCORESTATE->chan[voice].vol+1); + case SPUREG_VOICE_VOLXL: return volume_getlevel(SPUCORESTATE->chan[voice].vol+0); + case SPUREG_VOICE_VOLXR: return volume_getlevel(SPUCORESTATE->chan[voice].vol+1); + case SPUREG_VOICE_PITCH: return SPUCORESTATE->chan[voice].voice_pitch; + case SPUREG_VOICE_ADSR1: return SPUCORESTATE->chan[voice].env.reg_ad; + case SPUREG_VOICE_ADSR2: return SPUCORESTATE->chan[voice].env.reg_sr; + case SPUREG_VOICE_ENVX : + if(SPUCORESTATE->chan[voice].env.state == ENVELOPE_STATE_OFF) return 0; + return (SPUCORESTATE->chan[voice].env.level) >> 16; + case SPUREG_VOICE_SSA : return SPUCORESTATE->chan[voice].sample.start_block_addr; + case SPUREG_VOICE_LSAX : return SPUCORESTATE->chan[voice].sample.loop_block_addr; + case SPUREG_VOICE_NAX : return SPUCORESTATE->chan[voice].sample.block_addr; + } + return 0; +} + +void EMU_CALL spucore_setreg_voice(void *state, uint32 voice, uint32 n, uint32 value, uint32 mask) { + value &= mask; + switch(n) { + /* TODO: the increase/decrease modes */ + case SPUREG_VOICE_VOLL : volume_setmode(SPUCORESTATE->chan[voice].vol+0, value); break; + case SPUREG_VOICE_VOLR : volume_setmode(SPUCORESTATE->chan[voice].vol+1, value); break; + case SPUREG_VOICE_PITCH: SPUCORESTATE->chan[voice].voice_pitch = value; break; + case SPUREG_VOICE_ADSR1: SPUCORESTATE->chan[voice].env.reg_ad = value; SPUCORESTATE->chan[voice].env.cachemax = envelope_do(&SPUCORESTATE->chan[voice].env); break; + case SPUREG_VOICE_ADSR2: SPUCORESTATE->chan[voice].env.reg_sr = value; SPUCORESTATE->chan[voice].env.cachemax = envelope_do(&SPUCORESTATE->chan[voice].env); break; + + case SPUREG_VOICE_SSA: + SPUCORESTATE->chan[voice].sample.start_block_addr &= ~mask; + SPUCORESTATE->chan[voice].sample.start_block_addr |= value; + break; + case SPUREG_VOICE_LSAX: + SPUCORESTATE->chan[voice].sample.loop_block_addr &= ~mask; + SPUCORESTATE->chan[voice].sample.loop_block_addr |= value; + break; + } +} + +//////////////////////////////////////////////////////////////////////////////// +/* +** IRQ checking +*/ +uint32 EMU_CALL spucore_cycles_until_interrupt(void *state, uint16 *ram, uint32 samples) { + uint32 r; + void *backup; + + if (!(SPUCORESTATE->flags & SPUREG_FLAG_IRQ_ENABLE)) return 0xFFFFFFFF; + + backup = malloc(spucore_get_state_size()); + if (!backup) return 0xFFFFFFFF; + memcpy(backup, state, spucore_get_state_size()); + state = backup; + SPUCORESTATE->irq_triggered_cycle = 0xFFFFFFFF; + r = 0; + while(samples > RENDERMAX) { + samples -= RENDERMAX; + render(SPUCORESTATE, ram, NULL, NULL, RENDERMAX, 0, 0); + if (SPUCORESTATE->irq_triggered_cycle != 0xFFFFFFFF) break; + r += RENDERMAX * 768; + } + if(samples && SPUCORESTATE->irq_triggered_cycle == 0xFFFFFFFF) render(SPUCORESTATE, ram, NULL, NULL, samples, 0, 0); + r = (SPUCORESTATE->irq_triggered_cycle == 0xFFFFFFFF) ? 0xFFFFFFFF : SPUCORESTATE->irq_triggered_cycle + r; + free(backup); + return r; +} + +//////////////////////////////////////////////////////////////////////////////// diff --git a/Frameworks/HighlyExperimental/HighlyExperimental/Core/spucore.h b/Frameworks/HighlyExperimental/HighlyExperimental/Core/spucore.h new file mode 100644 index 000000000..64747e4ee --- /dev/null +++ b/Frameworks/HighlyExperimental/HighlyExperimental/Core/spucore.h @@ -0,0 +1,148 @@ +///////////////////////////////////////////////////////////////////////////// +// +// spucore - Emulates a single SPU CORE +// +///////////////////////////////////////////////////////////////////////////// + +#ifndef __PSX_SPUCORE_H__ +#define __PSX_SPUCORE_H__ + +#include "emuconfig.h" + +#ifdef __cplusplus +extern "C" { +#endif + +sint32 EMU_CALL spucore_init(void); +uint32 EMU_CALL spucore_get_state_size(void); +void EMU_CALL spucore_clear_state(void *state); + +void EMU_CALL spucore_set_mem_size(void *state, uint32 size); + +void EMU_CALL spucore_render(void *state, uint16 *ram, sint16 *buf, sint16 *extinput, uint32 samples, uint8 mainout, uint8 effectout); + +uint32 EMU_CALL spucore_getreg (void *state, uint32 n); +void EMU_CALL spucore_setreg (void *state, uint32 n, uint32 value, uint32 mask); +uint32 EMU_CALL spucore_getreg_voice(void *state, uint32 voice, uint32 n); +void EMU_CALL spucore_setreg_voice(void *state, uint32 voice, uint32 n, uint32 value, uint32 mask); +int EMU_CALL spucore_getflag (void *state, uint32 n); +void EMU_CALL spucore_setflag (void *state, uint32 n, int value); + +uint32 EMU_CALL spucore_cycles_until_interrupt(void *state, uint16 *ram, uint32 samples); + +/* +** Register definitions +*/ + +/* Flags */ + +#define SPUREG_FLAG_ON (1<<19) +#define SPUREG_FLAG_MAIN_ENABLE (1<<18) +#define SPUREG_FLAG_REVERB_ENABLE (1<<17) +#define SPUREG_FLAG_IRQ_ENABLE (1<<16) + +#define SPUREG_FLAG_ER (1<<15) +#define SPUREG_FLAG_CR (1<<14) +#define SPUREG_FLAG_EE (1<<13) +#define SPUREG_FLAG_CE (1<<12) + +#define SPUREG_FLAG_MSNDL (1<<11) +#define SPUREG_FLAG_MSNDR (1<<10) +#define SPUREG_FLAG_MSNDEL (1<< 9) +#define SPUREG_FLAG_MSNDER (1<< 8) +#define SPUREG_FLAG_MINL (1<< 7) +#define SPUREG_FLAG_MINR (1<< 6) +#define SPUREG_FLAG_MINEL (1<< 5) +#define SPUREG_FLAG_MINER (1<< 4) +#define SPUREG_FLAG_SINL (1<< 3) +#define SPUREG_FLAG_SINR (1<< 2) +#define SPUREG_FLAG_SINEL (1<< 1) +#define SPUREG_FLAG_SINER (1<< 0) + +/* Voice registers */ + +enum { + SPUREG_VOICE_VOLL, + SPUREG_VOICE_VOLR, + SPUREG_VOICE_VOLXL, + SPUREG_VOICE_VOLXR, + SPUREG_VOICE_PITCH, + SPUREG_VOICE_SSA, + SPUREG_VOICE_ADSR1, + SPUREG_VOICE_ADSR2, + SPUREG_VOICE_ENVX, + SPUREG_VOICE_LSAX, + SPUREG_VOICE_NAX +}; + +/* Main registers */ + +enum { + SPUREG_MVOLL, + SPUREG_MVOLR, + SPUREG_MVOLXL, + SPUREG_MVOLXR, + SPUREG_EVOLL, + SPUREG_EVOLR, + SPUREG_AVOLL, + SPUREG_AVOLR, + SPUREG_BVOLL, + SPUREG_BVOLR, + SPUREG_KON, + SPUREG_KOFF, + SPUREG_FM, + SPUREG_NOISE, + SPUREG_VMIXE, + SPUREG_VMIX, + SPUREG_VMIXEL, + SPUREG_VMIXER, + SPUREG_VMIXL, + SPUREG_VMIXR, + SPUREG_ESA, + SPUREG_EEA, + SPUREG_EAX, + SPUREG_IRQA, + + SPUREG_NOISECLOCK, + + SPUREG_REVERB_FB_SRC_A, + SPUREG_REVERB_FB_SRC_B, + SPUREG_REVERB_IIR_ALPHA, + SPUREG_REVERB_ACC_COEF_A, + SPUREG_REVERB_ACC_COEF_B, + SPUREG_REVERB_ACC_COEF_C, + SPUREG_REVERB_ACC_COEF_D, + SPUREG_REVERB_IIR_COEF, + SPUREG_REVERB_FB_ALPHA, + SPUREG_REVERB_FB_X, + SPUREG_REVERB_IIR_DEST_A0, + SPUREG_REVERB_IIR_DEST_A1, + SPUREG_REVERB_ACC_SRC_A0, + SPUREG_REVERB_ACC_SRC_A1, + SPUREG_REVERB_ACC_SRC_B0, + SPUREG_REVERB_ACC_SRC_B1, + SPUREG_REVERB_IIR_SRC_A0, + SPUREG_REVERB_IIR_SRC_A1, + SPUREG_REVERB_IIR_DEST_B0, + SPUREG_REVERB_IIR_DEST_B1, + SPUREG_REVERB_ACC_SRC_C0, + SPUREG_REVERB_ACC_SRC_C1, + SPUREG_REVERB_ACC_SRC_D0, + SPUREG_REVERB_ACC_SRC_D1, + SPUREG_REVERB_IIR_SRC_B1, + SPUREG_REVERB_IIR_SRC_B0, + SPUREG_REVERB_MIX_DEST_A0, + SPUREG_REVERB_MIX_DEST_A1, + SPUREG_REVERB_MIX_DEST_B0, + SPUREG_REVERB_MIX_DEST_B1, + SPUREG_REVERB_IN_COEF_L, + SPUREG_REVERB_IN_COEF_R + +}; + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Frameworks/HighlyExperimental/HighlyExperimental/Core/vfs.c b/Frameworks/HighlyExperimental/HighlyExperimental/Core/vfs.c new file mode 100644 index 000000000..a49139eb0 --- /dev/null +++ b/Frameworks/HighlyExperimental/HighlyExperimental/Core/vfs.c @@ -0,0 +1,158 @@ +///////////////////////////////////////////////////////////////////////////// +// +// vfs - Virtual filesystem management +// +///////////////////////////////////////////////////////////////////////////// + +#ifndef EMU_COMPILE +#error "Hi I forgot to set EMU_COMPILE" +#endif + +#include "vfs.h" + +///////////////////////////////////////////////////////////////////////////// +// +// Static information +// + +sint32 EMU_CALL vfs_init(void) { return 0; } + +///////////////////////////////////////////////////////////////////////////// +// +// State information +// +#define VFS_MAXPATH (250) +#define VFS_MAXOPENFILES (32) + +struct VFS_STATE { + psx_readfile_t readfile_cb; + void *readfile_context; + + sint32 ofs[VFS_MAXOPENFILES]; + sint32 length[VFS_MAXOPENFILES]; + char path[VFS_MAXOPENFILES][VFS_MAXPATH]; +}; + +#define VFSSTATE ((struct VFS_STATE*)(state)) + +uint32 EMU_CALL vfs_get_state_size(void) { + return sizeof(struct VFS_STATE); +} + +void EMU_CALL vfs_clear_state(void *state) { + memset(VFSSTATE, 0, sizeof(struct VFS_STATE)); +} + +void EMU_CALL vfs_set_readfile(void *state, psx_readfile_t readfile, void *context) { + VFSSTATE->readfile_cb = readfile; + VFSSTATE->readfile_context = context; +} + +///////////////////////////////////////////////////////////////////////////// +// +// check if the given fd is valid +// +static sint32 EMU_CALL isvalidfd(struct VFS_STATE *state, sint32 fd) { + if(fd < 0 || fd >= VFS_MAXOPENFILES) return 0; + if(state->path[fd][0] == 0) return 0; + return 1; +} + +///////////////////////////////////////////////////////////////////////////// +// +// open +// +sint32 EMU_CALL vfs_open(void *state, const char *path) { + sint32 l; + sint32 fd; + char tempbuf[4]; + if(!(VFSSTATE->readfile_cb)) return -5; // EIO if no callback was set + if(!path) return -22; // EINVAL if this was NULL for some reason + if(!path[0]) return -2; // ENOENT if the path is empty + l = (VFSSTATE->readfile_cb)( + VFSSTATE->readfile_context, + path, + 0, + tempbuf, + 0 + ); + if(l < -1) return -5; // EIO for fatal errors + if(l == -1) return -2; // ENOENT for not found + // Otherwise, find a free fd and keep it + for(fd = 0; fd < VFS_MAXOPENFILES; fd++) { + if(VFSSTATE->path[fd][0] == 0) break; + } + if(fd >= VFS_MAXOPENFILES) return -24; // EMFILE too many open files + VFSSTATE->ofs[fd] = 0; + VFSSTATE->length[fd] = l; + strncpy(VFSSTATE->path[fd], path, VFS_MAXPATH); + VFSSTATE->path[fd][VFS_MAXPATH-1] = 0; + return fd; +} + +///////////////////////////////////////////////////////////////////////////// +// +// close +// +sint32 EMU_CALL vfs_close(void *state, sint32 fd) { + if(!(VFSSTATE->readfile_cb)) return -5; // EIO if no callback was set + if(!isvalidfd(VFSSTATE, fd)) return -9; // EBADF + VFSSTATE->path[fd][0] = 0; + return 0; +} + +///////////////////////////////////////////////////////////////////////////// +// +// read +// +sint32 EMU_CALL vfs_read(void *state, sint32 fd, char *buffer, sint32 length) { + sint32 r; + if(!(VFSSTATE->readfile_cb)) return -5; // EIO if no callback was set + if(!isvalidfd(VFSSTATE, fd)) return -9; // EBADF + // if length is 0, just return 0 + if(!length) return 0; + // if we're past end-of-file, return 0 + if(VFSSTATE->ofs[fd] >= VFSSTATE->length[fd]) return 0; + // make sure we don't read past the end + { sint32 remain = VFSSTATE->length[fd] - VFSSTATE->ofs[fd]; + if(length > remain) length = remain; + } + // attempt actual read + r = (VFSSTATE->readfile_cb)( + VFSSTATE->readfile_context, + VFSSTATE->path[fd], + VFSSTATE->ofs[fd], + buffer, + length + ); + if(r < -1) return -5; // EIO for fatal errors + if(r == -1) return -2; // ENOENT for not found - weird, but should work + VFSSTATE->ofs[fd] += r; + return r; +} + +///////////////////////////////////////////////////////////////////////////// +// +// lseek +// +sint32 EMU_CALL vfs_lseek(void *state, sint32 fd, sint32 offset, sint32 whence) { + if(!(VFSSTATE->readfile_cb)) return -5; // EIO if no callback was set + if(!isvalidfd(VFSSTATE, fd)) return -9; // EBADF + switch(whence) { + case 0: // SEEK_SET + break; + case 1: // SEEK_CUR + offset += VFSSTATE->ofs[fd]; + break; + case 2: // SEEK_END + offset += VFSSTATE->length[fd]; + break; + default: + return -22; // EINVAL if whence isn't right + } + if(offset < 0) return -22; // EINVAL if offset ends up negative + VFSSTATE->ofs[fd] = offset; + return offset; +} + +///////////////////////////////////////////////////////////////////////////// diff --git a/Frameworks/HighlyExperimental/HighlyExperimental/Core/vfs.h b/Frameworks/HighlyExperimental/HighlyExperimental/Core/vfs.h new file mode 100644 index 000000000..0ab6a50e1 --- /dev/null +++ b/Frameworks/HighlyExperimental/HighlyExperimental/Core/vfs.h @@ -0,0 +1,34 @@ +///////////////////////////////////////////////////////////////////////////// +// +// vfs - Virtual filesystem management +// +///////////////////////////////////////////////////////////////////////////// + +#ifndef __PSX_VFS_H__ +#define __PSX_VFS_H__ + +#include "emuconfig.h" + +#include "psx.h" + +#ifdef __cplusplus +extern "C" { +#endif + +sint32 EMU_CALL vfs_init(void); + +uint32 EMU_CALL vfs_get_state_size(void); +void EMU_CALL vfs_clear_state(void *state); + +void EMU_CALL vfs_set_readfile(void *state, psx_readfile_t readfile, void *context); + +sint32 EMU_CALL vfs_open (void *state, const char *path); +sint32 EMU_CALL vfs_close(void *state, sint32 fd); +sint32 EMU_CALL vfs_read (void *state, sint32 fd, char *buffer, sint32 length); +sint32 EMU_CALL vfs_lseek(void *state, sint32 fd, sint32 offset, sint32 whence); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Frameworks/HighlyExperimental/HighlyExperimental/HighlyExperimental-Info.plist b/Frameworks/HighlyExperimental/HighlyExperimental/HighlyExperimental-Info.plist new file mode 100644 index 000000000..02c2a8310 --- /dev/null +++ b/Frameworks/HighlyExperimental/HighlyExperimental/HighlyExperimental-Info.plist @@ -0,0 +1,30 @@ + + + + + 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+ + + + + + + + diff --git a/Frameworks/HighlyQuixotic/HighlyQuixotic.xcodeproj/xcuserdata/Chris.xcuserdatad/xcschemes/xcschememanagement.plist b/Frameworks/HighlyQuixotic/HighlyQuixotic.xcodeproj/xcuserdata/Chris.xcuserdatad/xcschemes/xcschememanagement.plist new file mode 100644 index 000000000..654d6cfa9 --- /dev/null +++ b/Frameworks/HighlyQuixotic/HighlyQuixotic.xcodeproj/xcuserdata/Chris.xcuserdatad/xcschemes/xcschememanagement.plist @@ -0,0 +1,27 @@ + + + + + SchemeUserState + + HighlyQuixotic.xcscheme + + orderHint + 37 + + + SuppressBuildableAutocreation + + 834378DD17F96E2600584396 + + primary + + + 834378F417F96E2600584396 + + primary + + + + + diff --git a/Frameworks/HighlyQuixotic/HighlyQuixotic/Core/.gitignore b/Frameworks/HighlyQuixotic/HighlyQuixotic/Core/.gitignore new file mode 100644 index 000000000..32cff875e --- /dev/null +++ b/Frameworks/HighlyQuixotic/HighlyQuixotic/Core/.gitignore @@ -0,0 +1,3 @@ +*.user +Debug +Release \ No newline at end of file diff --git a/Frameworks/HighlyQuixotic/HighlyQuixotic/Core/Core.pro b/Frameworks/HighlyQuixotic/HighlyQuixotic/Core/Core.pro new file mode 100644 index 000000000..4a8af65e4 --- /dev/null +++ b/Frameworks/HighlyQuixotic/HighlyQuixotic/Core/Core.pro @@ -0,0 +1,40 @@ +#------------------------------------------------- +# +# Project created by QtCreator 2012-12-26T20:57:48 +# +#------------------------------------------------- + +QT -= core gui + +TARGET = QSoundCore +TEMPLATE = lib +CONFIG += staticlib + +DEFINES += EMU_COMPILE EMU_LITTLE_ENDIAN HAVE_STDINT_H + +SOURCES += \ + qsound.c \ + qmix.c \ + kabuki.c \ + z80.c + +HEADERS += \ + qsound.h \ + qmix.h \ + kabuki.h \ + emuconfig.h \ + z80.h +unix:!symbian { + maemo5 { + target.path = /opt/usr/lib + } else { + target.path = /usr/lib + } + INSTALLS += target +} + +OTHER_FILES += \ + COPYING.txt \ + Readme.txt \ + m68k/m68k_in.c \ + m68k/m68kmake.c diff --git a/Frameworks/HighlyQuixotic/HighlyQuixotic/Core/QCore.vcxproj b/Frameworks/HighlyQuixotic/HighlyQuixotic/Core/QCore.vcxproj new file mode 100644 index 000000000..609a1da0b --- /dev/null +++ b/Frameworks/HighlyQuixotic/HighlyQuixotic/Core/QCore.vcxproj @@ -0,0 +1,125 @@ + + + + + Debug + Win32 + + + Release + Win32 + + + + {AC325F7F-7898-4810-88F2-8E0C04125A77} + + + + + + + + + + + + StaticLibrary + Unicode + v100 + + + StaticLibrary + Unicode + true + v100 + + + + + + + + + + + + + + + <_ProjectFileVersion>10.0.21006.1 + AllRules.ruleset + + + AllRules.ruleset + + + + + + MaxSpeed + AnySuitable + true + Speed + true + WIN32;NDEBUG;_LIB;EMU_COMPILE;EMU_LITTLE_ENDIAN;%(PreprocessorDefinitions) + true + MultiThreaded + false + true + .\Release/QCore.pch + .\Release/ + .\Release/ + .\Release/ + Level3 + true + FastCall + + + NDEBUG;%(PreprocessorDefinitions) + 0x0409 + + + true + + + + + Disabled + OnlyExplicitInline + WIN32;_DEBUG;_LIB;EMU_COMPILE;EMU_LITTLE_ENDIAN;%(PreprocessorDefinitions) + EnableFastChecks + MultiThreadedDebug + .\Debug/QCore.pch + .\Debug/ + .\Debug/ + .\Debug/ + Level3 + true + ProgramDatabase + FastCall + + + _DEBUG;%(PreprocessorDefinitions) + 0x0409 + + + true + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/Frameworks/HighlyQuixotic/HighlyQuixotic/Core/QCore.vcxproj.filters b/Frameworks/HighlyQuixotic/HighlyQuixotic/Core/QCore.vcxproj.filters new file mode 100644 index 000000000..2e453a055 --- /dev/null +++ b/Frameworks/HighlyQuixotic/HighlyQuixotic/Core/QCore.vcxproj.filters @@ -0,0 +1,44 @@ + + + + + {baa3dd43-4bab-4d0c-a4f8-a22442c85402} + h;hpp;hxx;hm;inl + + + {e522c574-c4ae-4ee1-b48b-d71847133a8d} + cpp;c;cxx;rc;def;r;odl;idl;hpj;bat + + + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + \ No newline at end of file diff --git a/Frameworks/HighlyQuixotic/HighlyQuixotic/Core/Readme.txt b/Frameworks/HighlyQuixotic/HighlyQuixotic/Core/Readme.txt new file mode 100644 index 000000000..089ef2179 --- /dev/null +++ b/Frameworks/HighlyQuixotic/HighlyQuixotic/Core/Readme.txt @@ -0,0 +1,17 @@ +QSound core for Highly Quixotic + + +Another dirty secret (gasp), the Z80 core is based on the one from MAME. +Of course it required extensive modification to make it work outside MAMEland. + +Opcodes have a separate map so that we can stick a Kabuki-decrypted mirror +underneath the first 32K and execute opcodes from that. + + +kabuki.c - Kabuki decryption code. + +qmix.c - QSound mixer code. Most of the sound emulation happens here. + +qsound.c - top-level QSound system emulation. + +z80.c - Z80 core. diff --git a/Frameworks/HighlyQuixotic/HighlyQuixotic/Core/emuconfig.h b/Frameworks/HighlyQuixotic/HighlyQuixotic/Core/emuconfig.h new file mode 100644 index 000000000..57d06eeef --- /dev/null +++ b/Frameworks/HighlyQuixotic/HighlyQuixotic/Core/emuconfig.h @@ -0,0 +1,101 @@ +///////////////////////////////////////////////////////////////////////////// +// +// Configuration for emulation libraries +// +///////////////////////////////////////////////////////////////////////////// + +#ifndef __EMUCONFIG_H__ +#define __EMUCONFIG_H__ + +///////////////////////////////////////////////////////////////////////////// + +#include +#include +#include +#include + +///////////////////////////////////////////////////////////////////////////// +// +// One of these has to be defined when compiling the library. +// Shouldn't be necessary for using it. +// +#if defined(EMU_COMPILE) && !defined(EMU_BIG_ENDIAN) && !defined(EMU_LITTLE_ENDIAN) +#error "Hi I forgot to set EMU_x_ENDIAN" +#endif +#if defined(EMU_COMPILE) && defined(EMU_BIG_ENDIAN) && defined(EMU_LITTLE_ENDIAN) +#error "Both byte orders should not be defined" +#endif + +///////////////////////////////////////////////////////////////////////////// +// +// WIN32 native project definitions +// +///////////////////////////////////////////////////////////////////////////// +#if defined(WIN32) && !defined(__GNUC__) + +#define EMU_CALL __fastcall +#define EMU_CALL_ __cdecl +#define EMU_INLINE __inline + +#define uint8 unsigned char +#define uint16 unsigned short +#define uint32 unsigned int +#define uint64 unsigned __int64 +#define sint8 signed char +#define sint16 signed short +#define sint32 signed int +#define sint64 signed __int64 + +///////////////////////////////////////////////////////////////////////////// +// +// LINUX / other platform definitions +// +///////////////////////////////////////////////////////////////////////////// +#else + +//#if defined(__GNUC__) && defined(__i386__) +//#define EMU_CALL __attribute__((__regparm__(2))) +//#else +#define EMU_CALL +//#endif + +#define EMU_CALL_ +#define EMU_INLINE __inline + +#ifdef HAVE_STDINT_H +#include +#define uint8 uint8_t +#define uint16 uint16_t +#define uint32 uint32_t +#define uint64 uint64_t +#define sint8 int8_t +#define sint16 int16_t +#define sint32 int32_t +#define sint64 int64_t +#else +#define uint8 unsigned char +#define uint16 unsigned short +#define uint32 unsigned int +#define uint64 unsigned long long +#define sint8 signed char +#define sint16 signed short +#define sint32 signed int +#define sint64 signed long long +#endif + +#endif + +#ifdef EMU_BIG_ENDIAN +#define EMU_ENDIAN_XOR_L2H(x) (x) +#define EMU_ENDIAN_XOR_B2H(x) (0) +#else +#define EMU_ENDIAN_XOR_L2H(x) (0) +#define EMU_ENDIAN_XOR_B2H(x) (x) +#endif + +// deprecated +#define EMU_ENDIAN_XOR(x) EMU_ENDIAN_XOR_L2H(x) + +///////////////////////////////////////////////////////////////////////////// + +#endif diff --git a/Frameworks/HighlyQuixotic/HighlyQuixotic/Core/kabuki.c b/Frameworks/HighlyQuixotic/HighlyQuixotic/Core/kabuki.c new file mode 100644 index 000000000..d27f5e9d9 --- /dev/null +++ b/Frameworks/HighlyQuixotic/HighlyQuixotic/Core/kabuki.c @@ -0,0 +1,95 @@ +///////////////////////////////////////////////////////////////////////////// +// +// kabuki - Kabuki decryption +// +///////////////////////////////////////////////////////////////////////////// + +#ifndef EMU_COMPILE +#error "Hi I forgot to set EMU_COMPILE" +#endif + +#include "kabuki.h" + +///////////////////////////////////////////////////////////////////////////// + +static EMU_INLINE uint8 bitswap1(uint8 src, uint16 key, uint8 select) { + if (select & (1 << ((key >> 0) & 7))) + src = (src & 0xFC) | ((src & 0x01) << 1) | ((src & 0x02) >> 1); + if (select & (1 << ((key >> 4) & 7))) + src = (src & 0xF3) | ((src & 0x04) << 1) | ((src & 0x08) >> 1); + if (select & (1 << ((key >> 8) & 7))) + src = (src & 0xCF) | ((src & 0x10) << 1) | ((src & 0x20) >> 1); + if (select & (1 << ((key >>12) & 7))) + src = (src & 0x3F) | ((src & 0x40) << 1) | ((src & 0x80) >> 1); + return src; +} + +static EMU_INLINE uint8 bitswap2(uint8 src, uint16 key, uint8 select) { + if (select & (1 << ((key >>12) & 7))) + src = (src & 0xFC) | ((src & 0x01) << 1) | ((src & 0x02) >> 1); + if (select & (1 << ((key >> 8) & 7))) + src = (src & 0xF3) | ((src & 0x04) << 1) | ((src & 0x08) >> 1); + if (select & (1 << ((key >> 4) & 7))) + src = (src & 0xCF) | ((src & 0x10) << 1) | ((src & 0x20) >> 1); + if (select & (1 << ((key >> 0) & 7))) + src = (src & 0x3F) | ((src & 0x40) << 1) | ((src & 0x80) >> 1); + return src; +} + +static EMU_INLINE uint8 bytedecode( + uint8 src, + uint32 swap_key1, + uint32 swap_key2, + uint8 xor_key, + uint16 select +) { + src = bitswap1(src, swap_key1 & 0xFFFF, select & 0xFF); + src = ((src & 0x7F) << 1) | ((src & 0x80) >> 7); + src = bitswap2(src, swap_key1 >> 16 , select & 0xFF); + src ^= xor_key; + src = ((src & 0x7F) << 1) | ((src & 0x80) >> 7); + src = bitswap2(src, swap_key2 & 0xFFFF, select >> 8 ); + src = ((src & 0x7F) << 1) | ((src & 0x80) >> 7); + src = bitswap1(src, swap_key2 >> 16 , select >> 8 ); + return src; +} + +///////////////////////////////////////////////////////////////////////////// + +void EMU_CALL kabuki_decode( + uint8 *src, + uint8 *dest_op, + uint8 *dest_data, + uint16 len, + uint32 swap_key1, + uint32 swap_key2, + uint16 addr_key, + uint8 xor_key +) { + // 32K limit + if(len > 0x8000) len = 0x8000; + // if the swap keys are zero, that means no decryption + if((!swap_key1) && (!swap_key2)) { + if(len) { + memcpy(dest_op , src, len); + memcpy(dest_data, src, len); + } + // otherwise, decrypt + } else { + uint16 a, select; + for(a = 0; a < len; a++) { + // decode opcodes + select = a + addr_key; + dest_op [a] = bytedecode(src[a], swap_key1, swap_key2, xor_key, select); + // decode data + select = (a ^ 0x1FC0) + addr_key + 1; + dest_data[a] = bytedecode(src[a], swap_key1, swap_key2, xor_key, select); + } + } + if(len < 0x8000) { + memset(dest_op + len, 0xFF, 0x8000 - len); + memset(dest_data + len, 0xFF, 0x8000 - len); + } +} + +///////////////////////////////////////////////////////////////////////////// diff --git a/Frameworks/HighlyQuixotic/HighlyQuixotic/Core/kabuki.h b/Frameworks/HighlyQuixotic/HighlyQuixotic/Core/kabuki.h new file mode 100644 index 000000000..ab6f401ff --- /dev/null +++ b/Frameworks/HighlyQuixotic/HighlyQuixotic/Core/kabuki.h @@ -0,0 +1,31 @@ +///////////////////////////////////////////////////////////////////////////// +// +// kabuki - Kabuki decryption +// +///////////////////////////////////////////////////////////////////////////// + +#ifndef __Q_KABUKI_H__ +#define __Q_KABUKI_H__ + +#include "emuconfig.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void EMU_CALL kabuki_decode( + uint8 *src, + uint8 *dest_op, + uint8 *dest_data, + uint16 len, + uint32 swap_key1, + uint32 swap_key2, + uint16 addr_key, + uint8 xor_key +); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Frameworks/HighlyQuixotic/HighlyQuixotic/Core/qmix.c b/Frameworks/HighlyQuixotic/HighlyQuixotic/Core/qmix.c new file mode 100644 index 000000000..f7a1b8674 --- /dev/null +++ b/Frameworks/HighlyQuixotic/HighlyQuixotic/Core/qmix.c @@ -0,0 +1,466 @@ +///////////////////////////////////////////////////////////////////////////// +// +// qmix - QSound mixer +// +///////////////////////////////////////////////////////////////////////////// + +#ifndef EMU_COMPILE +#error "Hi I forgot to set EMU_COMPILE" +#endif + +#include "qmix.h" + +///////////////////////////////////////////////////////////////////////////// + +#define ANTICLICK_TIME (64) +#define ANTICLICK_THRESHHOLD (32) + +///////////////////////////////////////////////////////////////////////////// + +#define RENDERMAX (200) + +///////////////////////////////////////////////////////////////////////////// + +static const sint32 gauss_shuffled_reverse_table[1024] = { + 366,1305, 374, 0, 362,1304, 378, 0, 358,1304, 381, 0, 354,1304, 385, 0, 351,1304, 389, 0, 347,1304, 393, 0, 343,1303, 397, 0, 339,1303, 401, 0, + 336,1303, 405, 0, 332,1302, 410, 0, 328,1302, 414, 0, 325,1301, 418, 0, 321,1300, 422, 0, 318,1300, 426, 0, 314,1299, 430, 0, 311,1298, 434, 0, + 307,1297, 439, 1, 304,1297, 443, 1, 300,1296, 447, 1, 297,1295, 451, 1, 293,1294, 456, 1, 290,1293, 460, 1, 286,1292, 464, 1, 283,1291, 469, 1, + 280,1290, 473, 1, 276,1288, 477, 1, 273,1287, 482, 1, 270,1286, 486, 2, 267,1284, 491, 2, 263,1283, 495, 2, 260,1282, 499, 2, 257,1280, 504, 2, + 254,1279, 508, 2, 251,1277, 513, 2, 248,1275, 517, 3, 245,1274, 522, 3, 242,1272, 527, 3, 239,1270, 531, 3, 236,1269, 536, 3, 233,1267, 540, 4, + 230,1265, 545, 4, 227,1263, 550, 4, 224,1261, 554, 4, 221,1259, 559, 4, 218,1257, 563, 5, 215,1255, 568, 5, 212,1253, 573, 5, 210,1251, 577, 5, + 207,1248, 582, 6, 204,1246, 587, 6, 201,1244, 592, 6, 199,1241, 596, 6, 196,1239, 601, 7, 193,1237, 606, 7, 191,1234, 611, 7, 188,1232, 615, 8, + 186,1229, 620, 8, 183,1227, 625, 8, 180,1224, 630, 9, 178,1221, 635, 9, 175,1219, 640, 9, 173,1216, 644, 10, 171,1213, 649, 10, 168,1210, 654, 10, + 166,1207, 659, 11, 163,1205, 664, 11, 161,1202, 669, 11, 159,1199, 674, 12, 156,1196, 678, 12, 154,1193, 683, 13, 152,1190, 688, 13, 150,1186, 693, 14, + 147,1183, 698, 14, 145,1180, 703, 15, 143,1177, 708, 15, 141,1174, 713, 15, 139,1170, 718, 16, 137,1167, 723, 16, 134,1164, 728, 17, 132,1160, 732, 17, + 130,1157, 737, 18, 128,1153, 742, 19, 126,1150, 747, 19, 124,1146, 752, 20, 122,1143, 757, 20, 120,1139, 762, 21, 118,1136, 767, 21, 117,1132, 772, 22, + 115,1128, 777, 23, 113,1125, 782, 23, 111,1121, 787, 24, 109,1117, 792, 24, 107,1113, 797, 25, 106,1109, 802, 26, 104,1106, 806, 27, 102,1102, 811, 27, + 100,1098, 816, 28, 99,1094, 821, 29, 97,1090, 826, 29, 95,1086, 831, 30, 94,1082, 836, 31, 92,1078, 841, 32, 90,1074, 846, 32, 89,1070, 851, 33, + 87,1066, 855, 34, 86,1061, 860, 35, 84,1057, 865, 36, 83,1053, 870, 36, 81,1049, 875, 37, 80,1045, 880, 38, 78,1040, 884, 39, 77,1036, 889, 40, + 76,1032, 894, 41, 74,1027, 899, 42, 73,1023, 904, 43, 71,1019, 908, 44, 70,1014, 913, 45, 69,1010, 918, 46, 67,1005, 923, 47, 66,1001, 927, 48, + 65, 997, 932, 49, 64, 992, 937, 50, 62, 988, 941, 51, 61, 983, 946, 52, 60, 978, 951, 53, 59, 974, 955, 54, 58, 969, 960, 55, 56, 965, 965, 56, + 55, 960, 969, 58, 54, 955, 974, 59, 53, 951, 978, 60, 52, 946, 983, 61, 51, 941, 988, 62, 50, 937, 992, 64, 49, 932, 997, 65, 48, 927,1001, 66, + 47, 923,1005, 67, 46, 918,1010, 69, 45, 913,1014, 70, 44, 908,1019, 71, 43, 904,1023, 73, 42, 899,1027, 74, 41, 894,1032, 76, 40, 889,1036, 77, + 39, 884,1040, 78, 38, 880,1045, 80, 37, 875,1049, 81, 36, 870,1053, 83, 36, 865,1057, 84, 35, 860,1061, 86, 34, 855,1066, 87, 33, 851,1070, 89, + 32, 846,1074, 90, 32, 841,1078, 92, 31, 836,1082, 94, 30, 831,1086, 95, 29, 826,1090, 97, 29, 821,1094, 99, 28, 816,1098, 100, 27, 811,1102, 102, + 27, 806,1106, 104, 26, 802,1109, 106, 25, 797,1113, 107, 24, 792,1117, 109, 24, 787,1121, 111, 23, 782,1125, 113, 23, 777,1128, 115, 22, 772,1132, 117, + 21, 767,1136, 118, 21, 762,1139, 120, 20, 757,1143, 122, 20, 752,1146, 124, 19, 747,1150, 126, 19, 742,1153, 128, 18, 737,1157, 130, 17, 732,1160, 132, + 17, 728,1164, 134, 16, 723,1167, 137, 16, 718,1170, 139, 15, 713,1174, 141, 15, 708,1177, 143, 15, 703,1180, 145, 14, 698,1183, 147, 14, 693,1186, 150, + 13, 688,1190, 152, 13, 683,1193, 154, 12, 678,1196, 156, 12, 674,1199, 159, 11, 669,1202, 161, 11, 664,1205, 163, 11, 659,1207, 166, 10, 654,1210, 168, + 10, 649,1213, 171, 10, 644,1216, 173, 9, 640,1219, 175, 9, 635,1221, 178, 9, 630,1224, 180, 8, 625,1227, 183, 8, 620,1229, 186, 8, 615,1232, 188, + 7, 611,1234, 191, 7, 606,1237, 193, 7, 601,1239, 196, 6, 596,1241, 199, 6, 592,1244, 201, 6, 587,1246, 204, 6, 582,1248, 207, 5, 577,1251, 210, + 5, 573,1253, 212, 5, 568,1255, 215, 5, 563,1257, 218, 4, 559,1259, 221, 4, 554,1261, 224, 4, 550,1263, 227, 4, 545,1265, 230, 4, 540,1267, 233, + 3, 536,1269, 236, 3, 531,1270, 239, 3, 527,1272, 242, 3, 522,1274, 245, 3, 517,1275, 248, 2, 513,1277, 251, 2, 508,1279, 254, 2, 504,1280, 257, + 2, 499,1282, 260, 2, 495,1283, 263, 2, 491,1284, 267, 2, 486,1286, 270, 1, 482,1287, 273, 1, 477,1288, 276, 1, 473,1290, 280, 1, 469,1291, 283, + 1, 464,1292, 286, 1, 460,1293, 290, 1, 456,1294, 293, 1, 451,1295, 297, 1, 447,1296, 300, 1, 443,1297, 304, 1, 439,1297, 307, 0, 434,1298, 311, + 0, 430,1299, 314, 0, 426,1300, 318, 0, 422,1300, 321, 0, 418,1301, 325, 0, 414,1302, 328, 0, 410,1302, 332, 0, 405,1303, 336, 0, 401,1303, 339, + 0, 397,1303, 343, 0, 393,1304, 347, 0, 389,1304, 351, 0, 385,1304, 354, 0, 381,1304, 358, 0, 378,1304, 362, 0, 374,1305, 366, 0, 370,1305, 370, +}; + +static const sint32 pan_table[33] = { + 0, 724,1024,1254,1448,1619,1774,1916, +2048,2172,2290,2401,2508,2611,2709,2804, +2896,2985,3072,3156,3238,3318,3396,3473, +3547,3620,3692,3762,3831,3899,3966,4031, +4096}; + +///////////////////////////////////////////////////////////////////////////// +// +// Static information +// +sint32 EMU_CALL qmix_init(void) { return 0; } + +///////////////////////////////////////////////////////////////////////////// +// +// State information +// +#define QMIXSTATE ((struct QMIX_STATE*)(state)) + +struct QMIX_CHAN { + uint32 on; + uint32 startbank; + uint32 startaddr; + uint32 curbank; + uint32 curaddr; + uint32 startloop; + uint32 startend; + uint32 curloop; + uint32 curend; + uint32 phase; + uint32 pitch; + uint32 vol; + uint32 pan; + sint32 current_mix_l; + sint32 current_mix_r; + sint32 sample[4]; + sint32 sample_last_l; + sint32 sample_last_r; + sint32 sample_anticlick_l; + sint32 sample_anticlick_r; + sint32 sample_anticlick_remaining_l; + sint32 sample_anticlick_remaining_r; +}; + +///////////////////////////////////////////////////////////////////////////// + +static EMU_INLINE void get_anticlicked_samples( + struct QMIX_CHAN *chan, sint32 *l, sint32 *r +) { + sint32 out, remain; + remain = chan->sample_anticlick_remaining_l; + if(remain) { + sint32 diff = chan->sample_last_l - chan->sample_anticlick_l; + if(diff < 0) { diff = -diff; } + if(diff < ANTICLICK_THRESHHOLD) { + out = chan->sample_last_l; + chan->sample_anticlick_remaining_l = 0; + } else { + out = ( + chan->sample_last_l * (ANTICLICK_TIME-remain) + + chan->sample_anticlick_l * (remain) + ) / ANTICLICK_TIME; + chan->sample_anticlick_remaining_l--; + } + } else { + out = chan->sample_last_l; + } + *l = out; + + remain = chan->sample_anticlick_remaining_r; + if(remain) { + sint32 diff = chan->sample_last_r - chan->sample_anticlick_r; + if(diff < 0) { diff = -diff; } + if(diff < ANTICLICK_THRESHHOLD) { + out = chan->sample_last_r; + chan->sample_anticlick_remaining_r = 0; + } else { + out = ( + chan->sample_last_r * (ANTICLICK_TIME-remain) + + chan->sample_anticlick_r * (remain) + ) / ANTICLICK_TIME; + chan->sample_anticlick_remaining_r--; + } + } else { + out = chan->sample_last_r; + } + *r = out; + +} + +///////////////////////////////////////////////////////////////////////////// + +static EMU_INLINE void anticlick(struct QMIX_CHAN *chan) { + sint32 l, r; + get_anticlicked_samples(chan, &l, &r); + chan->sample_anticlick_l = l; + chan->sample_anticlick_r = r; + chan->sample_anticlick_remaining_l = ANTICLICK_TIME; + chan->sample_anticlick_remaining_r = ANTICLICK_TIME; +} + +///////////////////////////////////////////////////////////////////////////// + +struct QMIX_STATE { + uint8 *sample_rom; + uint32 sample_rom_size; + uint32 pitchscaler; + struct QMIX_CHAN chan[16]; + sint32 last_in_l; + sint32 last_in_r; + sint32 last_out_l; + sint32 last_out_r; + sint32 acc_l; + sint32 acc_r; +}; + +uint32 EMU_CALL qmix_get_state_size(void) { + return sizeof(struct QMIX_STATE); +} + +void EMU_CALL qmix_clear_state(void *state) { + memset(state, 0, sizeof(struct QMIX_STATE)); + + +} + +void EMU_CALL qmix_set_sample_rom(void *state, void *rom, uint32 size) { + QMIXSTATE->sample_rom = rom; + QMIXSTATE->sample_rom_size = size; +} + +///////////////////////////////////////////////////////////////////////////// + +static EMU_INLINE void chan_advance( + struct QMIX_STATE *state, + struct QMIX_CHAN *chan +) { + uint32 rom_addr = chan->curbank + chan->curaddr; + if(rom_addr >= state->sample_rom_size) rom_addr = 0; + chan->sample[0] = chan->sample[1]; + chan->sample[1] = chan->sample[2]; + chan->sample[2] = chan->sample[3]; + chan->sample[3] = (sint32)((sint8)(state->sample_rom[rom_addr])); + chan->curaddr++; +// FIXME: MAME thinks this is >=, but is it > ? + if(chan->curaddr >= chan->curend) { +// if(!chan->curloop) { +// chan->on = 0; +// chan->curaddr--; +// } else { + chan->curaddr = chan->curend - chan->curloop; +// chan->curaddr -= 1 + chan->curloop; +// } + } + chan->curaddr &= 0xFFFF; +} + +///////////////////////////////////////////////////////////////////////////// + +static EMU_INLINE sint32 chan_get_resampled( + struct QMIX_STATE *state, + struct QMIX_CHAN *chan +) { + sint32 sum; + sint32 phase = chan->phase & 0xFFF; + +// sum = chan->sample[2]; +// sum <<= 8; + + const sint32 *gauss = (sint32*) + (((sint8*)gauss_shuffled_reverse_table) + (phase & 0x0FF0)); + sum = chan->sample[0] * gauss[0]; + sum += chan->sample[1] * gauss[1]; + sum += chan->sample[2] * gauss[2]; + sum += chan->sample[3] * gauss[3]; + sum /= 8; + +// sum = chan->sample[1] * (0x1000-phase); +// sum += chan->sample[2] * ( phase); +// sum >>= 4; + + chan->phase += chan->pitch; + while(chan->phase >= 0x1000) { + chan_advance(state, chan); + chan->phase -= 0x1000; + } + + return sum; +} + +static EMU_INLINE void chan_get_stereo_anticlicked( + struct QMIX_STATE *state, + struct QMIX_CHAN *chan, + sint32 *l, + sint32 *r +) { + if(!chan->on) { + chan->sample_last_l = 0; + chan->sample_last_r = 0; + } else { + sint32 out = chan_get_resampled(state, chan); + chan->sample_last_l = (out * chan->current_mix_l) / 0x8000; + chan->sample_last_r = (out * chan->current_mix_r) / 0x8000; + // if we suddenly keyed off, perform an anticlick here + if(!chan->on) { anticlick(chan); } + } + get_anticlicked_samples(chan, l, r); +} + +///////////////////////////////////////////////////////////////////////////// + +static void recalc_mix(struct QMIX_CHAN *chan) { + sint32 realpan = (chan->pan & 0x3F) - 0x10; + sint32 realvol = chan->vol & 0xFFFF; + if(realpan < 0x00) realpan = 0x00; + if(realpan > 0x20) realpan = 0x20; + +// chan->current_mix_l = realvol << 3; +// chan->current_mix_r = realvol << 3; +// if(realpan < 0x10) { +// chan->current_mix_r *= realpan; +// chan->current_mix_r >>= 4; +// } +// if(realpan > 0x10) { +// chan->current_mix_l *= (0x20-realpan); +// chan->current_mix_l >>= 4; +// } + +// chan->current_mix_l = ((0x20-realpan) * realvol) >> 1; +// chan->current_mix_r = (( realpan) * realvol) >> 1; + + chan->current_mix_l = (realvol * pan_table[0x20-realpan]) / 0x2000; + chan->current_mix_r = (realvol * pan_table[ realpan]) / 0x2000; + + // perform anticlick + //anticlick(chan); +} + +///////////////////////////////////////////////////////////////////////////// +// +// Command handling +// +//#include + +void EMU_CALL qmix_command(void *state, uint8 cmd, uint16 data) { + struct QMIX_CHAN *chan; + uint32 ch = 0; + uint32 reg = 99; +//printf("qmix command 0x%02X:0x%04X\n",cmd,data); + if(cmd < 0x80) { + reg = cmd & 7; + ch = cmd >> 3; + } else if(cmd < 0x90) { + reg = 8; + ch = cmd - 0x80; + } else if(cmd >= 0xBA && cmd < 0xCA) { + reg = 9; + ch = cmd - 0xBA; + } else { + reg = 99; + ch = 0; + } + chan = QMIXSTATE->chan + ch; + switch(reg) { + case 0: // bank + ch = (ch+1) & 0xF; chan = QMIXSTATE->chan + ch; + //printf("qmix: bank ch%X = %04X\n",ch,data); + chan->startbank = (((uint32)data) & 0x7F) << 16; + break; + case 1: // start + //printf("qmix: start ch%X = %04X\n",ch,data); + chan->startaddr = ((uint32)data) & 0xFFFF; + break; + case 2: // pitch + //printf("qmix: pitch ch%X = %04X\n",ch,data); + chan->pitch = (((uint32)(data & 0xFFFF)) * QMIXSTATE->pitchscaler) / 0x10000; + if (chan->pitch == 0) { + chan->on = 0; + anticlick(chan); + } + break; + case 3: // unknown + //printf("qmix: unknown reg3 ch%X = %04X\n",ch,data); + break; + case 4: // loop start + //printf("qmix: loop ch%X = %04X\n",ch,data); + chan->startloop = data; + break; + case 5: // end + //printf("qmix: end ch%X = %04X\n",ch,data); + chan->startend = data; + break; + case 6: // volume + //printf("qmix: vol ch%X = %04X\n",ch,data); +//printf("volume=%04X\n",data); +// if(!data) { +// chan->on = 0; +// } else { +// chan->on = 1; +// chan->address = chan->start; +// chan->phase = 0; +// } + if(data == 0) { + chan->on = 0; + anticlick(chan); + } else if (chan->on == 0) { + chan->on = 1; + chan->curbank = chan->startbank; + chan->curaddr = chan->startaddr; + chan->curloop = chan->startloop; + chan->curend = chan->startend; + chan->phase = 0; + chan->sample[0] = 0; + chan->sample[1] = 0; + chan->sample[2] = 0; + chan->sample[3] = 0; + anticlick(chan); + } + + chan->vol = data; + recalc_mix(chan); + break; + case 7: // unknown + //printf("qmix: unknown reg7 ch%X = %04X\n",ch,data); + break; + case 8: // pan (0x110-0x130) + //printf("qmix: pan ch%X = %04X\n",ch,data); +//printf("pan=%04X\n",data); + chan->pan = data; + recalc_mix(chan); + break; + case 9: // ADSR? + //printf("qmix: unknown reg9 ch%X = %04X\n",ch,data); + break; + default: + //printf("qmix: unknown reg %02X = %04X\n",cmd,data); + break; + } +} + +///////////////////////////////////////////////////////////////////////////// +// +// Rendering +// +static void render( + struct QMIX_STATE *state, + sint16 *buf, + uint32 samples +) { + sint32 buf_l[RENDERMAX]; + sint32 buf_r[RENDERMAX]; + sint32 l, r; + uint32 s; + int ch; + memset(buf_l, 0, 4 * samples); + memset(buf_r, 0, 4 * samples); + for(ch = 0; ch < 16; ch++) { + struct QMIX_CHAN *chan = state->chan + ch; + for(s = 0; s < samples; s++) { + chan_get_stereo_anticlicked(state, chan, &l, &r); + buf_l[s] += l; + buf_r[s] += r; + } + } + if(!buf) return; + for(s = 0; s < samples; s++) { + sint32 diff_l = buf_l[s] - state->last_in_l; + sint32 diff_r = buf_r[s] - state->last_in_r; + state->last_in_l = buf_l[s]; + state->last_in_r = buf_r[s]; + l = ((state->last_out_l * 255) / 256) + diff_l; + r = ((state->last_out_r * 255) / 256) + diff_r; + state->last_out_l = l; + state->last_out_r = r; +// l /= 2; +// r /= 2; + l *= 8; + r *= 8; + if(l > ( 32767)) l = ( 32767); + if(l < (-32768)) l = (-32768); + if(r > ( 32767)) r = ( 32767); + if(r < (-32768)) r = (-32768); + *buf++ = l; + *buf++ = r; + } +} + +///////////////////////////////////////////////////////////////////////////// + +void EMU_CALL qmix_render(void *state, sint16 *buf, uint32 samples) { +//printf("qmix render %u samples\n",samples); + for(; samples >= RENDERMAX; samples -= RENDERMAX) { + render(QMIXSTATE, buf, RENDERMAX); + if(buf) buf += 2 * RENDERMAX; + } + if(samples) { + render(QMIXSTATE, buf, samples); + } +} + +///////////////////////////////////////////////////////////////////////////// + +void EMU_CALL qmix_set_sample_rate(void *state, uint32 rate) { + if(rate < 1) rate = 1; + QMIXSTATE->pitchscaler = (65536 * 24000) / rate; +} + +///////////////////////////////////////////////////////////////////////////// diff --git a/Frameworks/HighlyQuixotic/HighlyQuixotic/Core/qmix.h b/Frameworks/HighlyQuixotic/HighlyQuixotic/Core/qmix.h new file mode 100644 index 000000000..3d03f484b --- /dev/null +++ b/Frameworks/HighlyQuixotic/HighlyQuixotic/Core/qmix.h @@ -0,0 +1,29 @@ +///////////////////////////////////////////////////////////////////////////// +// +// qmix - QSound mixer +// +///////////////////////////////////////////////////////////////////////////// + +#ifndef __Q_QMIX_H__ +#define __Q_QMIX_H__ + +#include "emuconfig.h" + +#ifdef __cplusplus +extern "C" { +#endif + +sint32 EMU_CALL qmix_init(void); +uint32 EMU_CALL qmix_get_state_size(void); +void EMU_CALL qmix_clear_state(void *state); + +void EMU_CALL qmix_set_sample_rate(void *state, uint32 rate); +void EMU_CALL qmix_set_sample_rom(void *state, void *rom, uint32 size); +void EMU_CALL qmix_command(void *state, uint8 cmd, uint16 data); +void EMU_CALL qmix_render(void *state, sint16 *buf, uint32 samples); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Frameworks/HighlyQuixotic/HighlyQuixotic/Core/qsound.c b/Frameworks/HighlyQuixotic/HighlyQuixotic/Core/qsound.c new file mode 100644 index 000000000..c10818722 --- /dev/null +++ b/Frameworks/HighlyQuixotic/HighlyQuixotic/Core/qsound.c @@ -0,0 +1,631 @@ +///////////////////////////////////////////////////////////////////////////// +// +// qsound - QSound emulation +// +///////////////////////////////////////////////////////////////////////////// + +#ifndef EMU_COMPILE +#error "Hi I forgot to set EMU_COMPILE" +#endif + +#include "qsound.h" + +#include "z80.h" +#include "kabuki.h" +#include "qmix.h" + +///////////////////////////////////////////////////////////////////////////// +// +// Static information +// +static uint8 safe_rom_area[4] = {0,0,0,0}; + +///////////////////////////////////////////////////////////////////////////// +// +// Static init for the whole library +// +static uint8 library_was_initialized = 0; + +// +// Deliberately create a NULL dereference +// Useful for calling attention to show-stopper problems like forgetting to +// call qsound_init() or compiling with the wrong byte order +// +static void qsound_hang(const char *message) { + for(;;) { *((volatile char*)0) = *message; } +} + +// +// Endian check +// +static void qsound_endian_check(void) { + uint32 num = 0x61626364; + // Big + if(!memcmp(&num, "abcd", 4)) { +#ifdef EMU_BIG_ENDIAN + return; +#endif + qsound_hang("endian check"); + } + // Little + if(!memcmp(&num, "dcba", 4)) { +#ifndef EMU_BIG_ENDIAN + return; +#endif + qsound_hang("endian check"); + } + // Don't know what! + qsound_hang("endian check"); +} + +// +// Data type size check +// +static void qsound_size_check(void) { + if(sizeof(uint8 ) != 1) qsound_hang("size check"); + if(sizeof(uint16) != 2) qsound_hang("size check"); + if(sizeof(uint32) != 4) qsound_hang("size check"); + if(sizeof(uint64) != 8) qsound_hang("size check"); + if(sizeof(sint8 ) != 1) qsound_hang("size check"); + if(sizeof(sint16) != 2) qsound_hang("size check"); + if(sizeof(sint32) != 4) qsound_hang("size check"); + if(sizeof(sint64) != 8) qsound_hang("size check"); +} + +sint32 EMU_CALL qsound_init(void) { + sint32 r; + qsound_endian_check(); + qsound_size_check(); + r = z80_init(); if(r) return r; + r = qmix_init(); if(r) return r; + library_was_initialized = 1; + return 0; +} + +///////////////////////////////////////////////////////////////////////////// +// +// Version information +// +const char* EMU_CALL qsound_getversion(void) { + static const char s[] = "QCore0001a (built " __DATE__ ")"; + return s; +} + +///////////////////////////////////////////////////////////////////////////// +// +// State information +// +struct QSOUND_STATE { + struct Z80_MEMORY_MAP *map_op; + struct Z80_MEMORY_MAP *map_read; + struct Z80_MEMORY_MAP *map_write; + void *z80_state; + void *qmix_state; + sint16 *sound_buffer; // TEMPORARY pointer. safe. + uint32 sound_buffer_samples_free; + uint32 sound_cycles_pending; + uint16 qsound_data_latch; + uint8 fatalflag; + uint8 dummy0; + uint32 bank_ofs; + uint32 cycles_until_irq; + uint32 cycles_per_irq; + uint32 cycles_per_sample; + uint64 odometer; + uint8 ramC[0x1000]; + uint8 ramF[0x1000]; + uint8 *z80_rom; + uint32 z80_rom_size; + uint32 kabuki_swap_key1; + uint32 kabuki_swap_key2; + uint16 kabuki_addr_key; + uint8 kabuki_xor_key; + uint8 kabuki_op [0x8000]; + uint8 kabuki_data[0x8000]; +}; + +#define QSOUNDSTATE ((struct QSOUND_STATE*)(state)) +#define Z80STATE (QSOUNDSTATE->z80_state) +#define QMIXSTATE (QSOUNDSTATE->qmix_state) + +extern const uint32 qsound_map_op_entries; +extern const uint32 qsound_map_read_entries; +extern const uint32 qsound_map_write_entries; + +/* +void EMU_CALL qsound_write_ram_C(void *state, uint16 addr, uint8 data) { + QSOUNDSTATE->ramC[addr & 0xFFF] = data; +} +void EMU_CALL qsound_write_ram_F(void *state, uint16 addr, uint8 data) { + QSOUNDSTATE->ramF[addr & 0xFFF] = data; +} +*/ + +uint32 EMU_CALL qsound_get_state_size(void) { + uint32 size = 0; + size += sizeof(struct QSOUND_STATE); + size += sizeof(struct Z80_MEMORY_MAP) * qsound_map_op_entries; + size += sizeof(struct Z80_MEMORY_MAP) * qsound_map_read_entries; + size += sizeof(struct Z80_MEMORY_MAP) * qsound_map_write_entries; + size += z80_get_state_size(); + size += qmix_get_state_size(); + return size; +} + +static void EMU_CALL recompute_memory_maps(struct QSOUND_STATE *state); +static void EMU_CALL qsound_advance(void *state, uint32 elapse); + +static struct Z80_MEMORY_MAP qsound_map_in [1]; +static struct Z80_MEMORY_MAP qsound_map_out[1]; + +void EMU_CALL qsound_set_rates( + void *state, + uint32 z80, + uint32 irq, + uint32 sample +) { + QSOUNDSTATE->cycles_per_irq = (z80 + (irq /2)) / irq ; + QSOUNDSTATE->cycles_per_sample = (z80 + (sample/2)) / sample; + qmix_set_sample_rate(QMIXSTATE, sample); +} + +void EMU_CALL qsound_clear_state(void *state) { + uint32 offset; + // Clear local struct + memset(state, 0, sizeof(struct QSOUND_STATE)); + // Set up sub-pointers + offset = sizeof(struct QSOUND_STATE); + QSOUNDSTATE->map_op = (void*)(((char*)state)+offset); offset += sizeof(struct Z80_MEMORY_MAP) * qsound_map_op_entries; + QSOUNDSTATE->map_read = (void*)(((char*)state)+offset); offset += sizeof(struct Z80_MEMORY_MAP) * qsound_map_read_entries; + QSOUNDSTATE->map_write = (void*)(((char*)state)+offset); offset += sizeof(struct Z80_MEMORY_MAP) * qsound_map_write_entries; + QSOUNDSTATE->z80_state = (void*)(((char*)state)+offset); offset += z80_get_state_size(); + QSOUNDSTATE->qmix_state = (void*)(((char*)state)+offset); offset += qmix_get_state_size(); + // + // Set other variables + // + QSOUNDSTATE->bank_ofs = 0x8000; + // + // Take care of substructures: memory maps, Z80 state, mixer state + // + recompute_memory_maps(QSOUNDSTATE); + + z80_clear_state(Z80STATE); + z80_set_advance_callback(Z80STATE, qsound_advance, QSOUNDSTATE); + z80_set_memory_maps( + Z80STATE, + QSOUNDSTATE->map_op, + QSOUNDSTATE->map_read, + QSOUNDSTATE->map_write, + qsound_map_in, + qsound_map_out + ); + + qmix_clear_state(QMIXSTATE); + + // Set rates + qsound_set_rates(QSOUNDSTATE, 8000000, 250, 44100); + QSOUNDSTATE->cycles_until_irq = QSOUNDSTATE->cycles_per_irq; + + // Done +} + +///////////////////////////////////////////////////////////////////////////// +// +// Obtain substates +// +void* EMU_CALL qsound_get_r3000_state(void *state) { return Z80STATE; } +void* EMU_CALL qsound_get_qmix_state (void *state) { return QMIXSTATE; } + +///////////////////////////////////////////////////////////////////////////// + +uint16 EMU_CALL qsound_getpc(void *state) { return z80_getpc(Z80STATE); } + +///////////////////////////////////////////////////////////////////////////// +// +// Signal an interrupt +// +static void EMU_CALL irq_signal(struct QSOUND_STATE *state) { + z80_setirq(Z80STATE, 1, 0x00); +} + +///////////////////////////////////////////////////////////////////////////// +// +// Bank switching +// +static void set_memory_map_rom_area( + struct Z80_MEMORY_MAP *map, + uint8 *rom, + sint32 rom_size +) { + if(rom_size < 1) { rom = safe_rom_area; rom_size = 4; } + if(rom_size > ((map->type.mask)+1)) rom_size = ((map->type.mask)+1); + map->y = map->x + (rom_size-1); + map->type.p = rom; +} + +/* +static void recompute_fixed_rom_areas(struct QSOUND_STATE *state) { + set_memory_map_rom_area( + state->map_op, + state->op_rom, + state->op_rom_size + ); + set_memory_map_rom_area( + state->map_read, + state->data_rom, + state->data_rom_size + ); +} +*/ + +static void recompute_banked_rom_areas(struct QSOUND_STATE *state) { + set_memory_map_rom_area( + state->map_op + 1, + state->z80_rom + state->bank_ofs, + state->z80_rom_size - state->bank_ofs + ); + set_memory_map_rom_area( + state->map_read + 1, + state->z80_rom + state->bank_ofs, + state->z80_rom_size - state->bank_ofs + ); +} + +static void EMU_CALL qsound_banksw_w(void *state, uint16 a, uint8 d) { + QSOUNDSTATE->bank_ofs = 0x8000 + 0x4000 * ((uint32)(d&0xF)); + recompute_banked_rom_areas(QSOUNDSTATE); + // just in case we're executing from the banked area + // (for CPS1/2 this is exquisitely unlikely) + z80_break(Z80STATE); +} + +///////////////////////////////////////////////////////////////////////////// +// +// QMIX: Forward read/write/advance calls to the QSound mixer +// + +static void EMU_CALL flush_sound(struct QSOUND_STATE *state) { + uint32 samples_needed = state->sound_cycles_pending / (state->cycles_per_sample); + if(samples_needed > state->sound_buffer_samples_free) { + samples_needed = state->sound_buffer_samples_free; + } + if(!samples_needed) return; + + qmix_render(QMIXSTATE, state->sound_buffer, samples_needed); + + if(state->sound_buffer) state->sound_buffer += 2 * samples_needed; + state->sound_buffer_samples_free -= samples_needed; + state->sound_cycles_pending -= (state->cycles_per_sample) * samples_needed; +} + +// +// Register reads/writes +// +static uint8 EMU_CALL qsound_status_r(void *state, uint16 a) { + return 0x80; +} + +static void EMU_CALL qsound_data_h_w(void *state, uint16 a, uint8 d) { + QSOUNDSTATE->qsound_data_latch = + (QSOUNDSTATE->qsound_data_latch & 0x00FF) | + (((uint32)d) << 8); +} + +static void EMU_CALL qsound_data_l_w(void *state, uint16 a, uint8 d) { + QSOUNDSTATE->qsound_data_latch = + (QSOUNDSTATE->qsound_data_latch & 0xFF00) | + ((uint32)d); +} + +static void EMU_CALL qsound_cmd_w(void *state, uint16 a, uint8 d) { + flush_sound(QSOUNDSTATE); + qmix_command(QMIXSTATE, d, QSOUNDSTATE->qsound_data_latch); +} + +///////////////////////////////////////////////////////////////////////////// +// +// Invalid-address catchers +// +static uint8 EMU_CALL catcher_read(void *state, uint16 a) { return 0; } +static void EMU_CALL catcher_write(void *state, uint16 a, uint8 d) { } + +///////////////////////////////////////////////////////////////////////////// +// +// Advance hardware activity by the given cycle count +// +static void EMU_CALL qsound_advance(void *state, uint32 elapse) { + if(!elapse) return; + // + // Check timers + // + if(QSOUNDSTATE->cycles_until_irq <= elapse) { + QSOUNDSTATE->cycles_until_irq += QSOUNDSTATE->cycles_per_irq; + irq_signal(QSOUNDSTATE); + } + QSOUNDSTATE->cycles_until_irq -= elapse; + // + // Update pending sound cycles + // + QSOUNDSTATE->sound_cycles_pending += elapse; + // + // Update odometer + // + QSOUNDSTATE->odometer += ((uint64)elapse); +} + +///////////////////////////////////////////////////////////////////////////// +// +// Determine how many cycles until the next interrupt +// +// This is then used as an upper bound for how many cycles can be executed +// before checking for futher interrupts +// +static uint32 EMU_CALL cycles_until_next_interrupt( + struct QSOUND_STATE *state +) { + uint32 cyc, min = 0xFFFFFFFF; + // + // Timers + // + cyc = state->cycles_until_irq; + if(cyc < min) min = cyc; + + if(min < 1) min = 1; + return min; +} + +///////////////////////////////////////////////////////////////////////////// +// +// Memory map structures +// +#define STATEOFS(thetype,thefield) ((void*)(&(((struct thetype*)0)->thefield))) + +static struct Z80_MEMORY_MAP qsound_map_op[] = { + { 0x0000, 0x7FFF, { 0x7FFF, Z80_MAP_TYPE_POINTER , STATEOFS(QSOUND_STATE,kabuki_op) } }, + { 0x8000, 0xBFFF, { 0x3FFF, Z80_MAP_TYPE_POINTER , NULL } }, + { 0xC000, 0xCFFF, { 0x0FFF, Z80_MAP_TYPE_POINTER , STATEOFS(QSOUND_STATE,ramC) } }, + { 0xF000, 0xFFFF, { 0x0FFF, Z80_MAP_TYPE_POINTER , STATEOFS(QSOUND_STATE,ramF) } }, + { 0x0000, 0xFFFF, { 0xFFFF, Z80_MAP_TYPE_CALLBACK, catcher_read } } +}; + +static struct Z80_MEMORY_MAP qsound_map_read[] = { + { 0x0000, 0x7FFF, { 0x7FFF, Z80_MAP_TYPE_POINTER , STATEOFS(QSOUND_STATE,kabuki_data) } }, + { 0x8000, 0xBFFF, { 0x3FFF, Z80_MAP_TYPE_POINTER , NULL } }, + { 0xC000, 0xCFFF, { 0x0FFF, Z80_MAP_TYPE_POINTER , STATEOFS(QSOUND_STATE,ramC) } }, + { 0xF000, 0xFFFF, { 0x0FFF, Z80_MAP_TYPE_POINTER , STATEOFS(QSOUND_STATE,ramF) } }, + { 0xD007, 0xD007, { 0x0000, Z80_MAP_TYPE_CALLBACK, qsound_status_r } }, + { 0x0000, 0xFFFF, { 0xFFFF, Z80_MAP_TYPE_CALLBACK, catcher_read } } +}; + +static struct Z80_MEMORY_MAP qsound_map_write[] = { + { 0xC000, 0xCFFF, { 0x0FFF, Z80_MAP_TYPE_POINTER , STATEOFS(QSOUND_STATE,ramC) } }, + { 0xF000, 0xFFFF, { 0x0FFF, Z80_MAP_TYPE_POINTER , STATEOFS(QSOUND_STATE,ramF) } }, + { 0xD000, 0xD000, { 0x0000, Z80_MAP_TYPE_CALLBACK, qsound_data_h_w } }, + { 0xD001, 0xD001, { 0x0000, Z80_MAP_TYPE_CALLBACK, qsound_data_l_w } }, + { 0xD002, 0xD002, { 0x0000, Z80_MAP_TYPE_CALLBACK, qsound_cmd_w } }, + { 0xD003, 0xD003, { 0x0000, Z80_MAP_TYPE_CALLBACK, qsound_banksw_w } }, + { 0x0000, 0xFFFF, { 0xFFFF, Z80_MAP_TYPE_CALLBACK, catcher_write } } +}; + +static struct Z80_MEMORY_MAP qsound_map_in [1] = { + { 0x0000, 0xFFFF, { 0xFFFF, Z80_MAP_TYPE_CALLBACK, catcher_read } } +}; + +static struct Z80_MEMORY_MAP qsound_map_out[1] = { + { 0x0000, 0xFFFF, { 0xFFFF, Z80_MAP_TYPE_CALLBACK, catcher_write } } +}; + +#define QSOUND_ARRAY_ENTRIES(x) (sizeof(x)/sizeof((x)[0])) + +const uint32 qsound_map_op_entries = QSOUND_ARRAY_ENTRIES(qsound_map_op ); +const uint32 qsound_map_read_entries = QSOUND_ARRAY_ENTRIES(qsound_map_read ); +const uint32 qsound_map_write_entries = QSOUND_ARRAY_ENTRIES(qsound_map_write); + +///////////////////////////////////////////////////////////////////////////// +// +// Memory map recomputation +// +static void perform_state_offset( + struct Z80_MEMORY_MAP *map, + struct QSOUND_STATE *state +) { + // + // It's safe to typecast this "pointer" to a uint32 since, due to + // the STATEOFS hack, it'll never be bigger than 4GB + // + uint32 o = (uint32)(map->type.p); + map->type.p = ((uint8*)state) + o; +} + +static void perform_nonnull_state_offsets( + struct QSOUND_STATE *state, + struct Z80_MEMORY_MAP *map, + uint32 entries +) { + uint32 i; + for(i = 0; i < entries; i++) { + if( + (map[i].type.n == Z80_MAP_TYPE_POINTER) && + (map[i].type.p) + ) { + perform_state_offset(map + i, state); + } + } +} + +// +// Recompute the memory maps. +// PERFORMS NO REGISTRATION with the actual R3000 state. +// +static void recompute_memory_maps(struct QSOUND_STATE *state) { + // + // First, just copy from the static tables + // + memcpy(state->map_op , qsound_map_op , sizeof(qsound_map_op )); + memcpy(state->map_read , qsound_map_read , sizeof(qsound_map_read )); + memcpy(state->map_write, qsound_map_write, sizeof(qsound_map_write)); + // + // Now perform state offsets on all non-NULL pointers + // + perform_nonnull_state_offsets(state, state->map_op , qsound_map_op_entries ); + perform_nonnull_state_offsets(state, state->map_read , qsound_map_read_entries ); + perform_nonnull_state_offsets(state, state->map_write, qsound_map_write_entries); + // + // Now take care of ROM areas + // +// recompute_fixed_rom_areas (state); + recompute_banked_rom_areas(state); +} + +///////////////////////////////////////////////////////////////////////////// +// +// Executes the given number of cycles or the given number of samples +// (whichever is less) +// +// Sets *sound_samples to the number of samples actually generated, +// which may be ZERO or LESS than the number requested, but never more. +// +// Return value: +// >= 0 The number of cycles actually executed, which may be ZERO, MORE, +// or LESS than the number requested +// < 0 Unrecoverable error +// +sint32 EMU_CALL qsound_execute( + void *state, + sint32 cycles, + sint16 *sound_buf, + uint32 *sound_samples +) { + sint32 r = 0; + sint64 cyc_upperbound; + uint64 old_odometer; + uint64 target_odometer; + + old_odometer = QSOUNDSTATE->odometer; + + QSOUNDSTATE->sound_buffer = sound_buf; + QSOUNDSTATE->sound_buffer_samples_free = *sound_samples; + // + // If the fatal flag was set, return -2 + // + if(QSOUNDSTATE->fatalflag) { return -1; } + // + // If we have a bogus cycle count, return error + // + if(cycles < 0) { return -1; } + + /* + ** Begin by flushing any pending sound data into the newly available + ** buffer, if necessary + */ + flush_sound(QSOUNDSTATE); + /* + ** Compute an upper bound for the number of cycles that can be generated + ** while still fitting in the buffer + */ + cyc_upperbound = + ((sint64)(QSOUNDSTATE->cycles_per_sample)) * + ((sint64)(QSOUNDSTATE->sound_buffer_samples_free)); + if(cyc_upperbound > (QSOUNDSTATE->sound_cycles_pending)) { + cyc_upperbound -= QSOUNDSTATE->sound_cycles_pending; + } else { + cyc_upperbound = 0; + } + /* + ** Bound cyc_upperbound by the number of cycles requested + */ + if(cycles > 0x70000000) cycles = 0x70000000; + if(cyc_upperbound > cycles) cyc_upperbound = cycles; + /* + ** Now cyc_upperbound is the number of cycles to execute. + ** Compute the target odometer + */ + target_odometer = (QSOUNDSTATE->odometer)+((uint64)(cyc_upperbound)); + /* + ** Execution loop + */ + for(;;) { + uint32 diff, ci; + if(QSOUNDSTATE->odometer >= target_odometer) break; + + diff = (uint32)((target_odometer) - (QSOUNDSTATE->odometer)); + ci = cycles_until_next_interrupt(QSOUNDSTATE); + if(diff > ci) diff = ci; + r = z80_execute(Z80STATE, diff); + // Create an error if necessary + if(r < 0 || QSOUNDSTATE->fatalflag) { r = -1; break; } + } + // + // End with a final sound flush + // + flush_sound(QSOUNDSTATE); + /* + ** Determine how many sound samples we generated + */ + (*sound_samples) -= (QSOUNDSTATE->sound_buffer_samples_free); + // + // If there was an error, return it + // + if(r < 0) { +//char s[100]; +//sprintf(s,"blah blah %d", r); +//MessageBox(NULL,s,NULL,MB_OK); + return r; + } + // + // Otherwise return the number of cycles we executed + // + r = QSOUNDSTATE->odometer - old_odometer; + return r; +} + +///////////////////////////////////////////////////////////////////////////// + +uint64 EMU_CALL qsound_get_odometer(void *state) { + return QSOUNDSTATE->odometer; +} + +///////////////////////////////////////////////////////////////////////////// + +static void recompute_kabuki_rom(struct QSOUND_STATE *state) { + uint32 len = state->z80_rom_size; + if(len > 0x8000) len = 0x8000; + kabuki_decode( + state->z80_rom, + state->kabuki_op, + state->kabuki_data, + len, + state->kabuki_swap_key1, + state->kabuki_swap_key2, + state->kabuki_addr_key, + state->kabuki_xor_key + ); +} + +///////////////////////////////////////////////////////////////////////////// + +void EMU_CALL qsound_set_z80_rom(void *state, void *rom, uint32 size) { + QSOUNDSTATE->z80_rom = rom; + QSOUNDSTATE->z80_rom_size = size; + recompute_kabuki_rom(QSOUNDSTATE); + recompute_memory_maps(QSOUNDSTATE); +} + +void EMU_CALL qsound_set_kabuki_key(void *state, + uint32 swap_key1, + uint32 swap_key2, + uint16 addr_key, + uint8 xor_key +) { + QSOUNDSTATE->kabuki_swap_key1 = swap_key1; + QSOUNDSTATE->kabuki_swap_key2 = swap_key2; + QSOUNDSTATE->kabuki_addr_key = addr_key; + QSOUNDSTATE->kabuki_xor_key = xor_key; + recompute_kabuki_rom(QSOUNDSTATE); +} + +void EMU_CALL qsound_set_sample_rom(void *state, void *rom, uint32 size) { + qmix_set_sample_rom(QMIXSTATE, rom, size); +} + +///////////////////////////////////////////////////////////////////////////// diff --git a/Frameworks/HighlyQuixotic/HighlyQuixotic/Core/qsound.h b/Frameworks/HighlyQuixotic/HighlyQuixotic/Core/qsound.h new file mode 100644 index 000000000..4a9d17555 --- /dev/null +++ b/Frameworks/HighlyQuixotic/HighlyQuixotic/Core/qsound.h @@ -0,0 +1,65 @@ +///////////////////////////////////////////////////////////////////////////// +// +// qsound - QSound emulation +// +///////////////////////////////////////////////////////////////////////////// + +#ifndef __Q_QSOUND_H__ +#define __Q_QSOUND_H__ + +#include "emuconfig.h" + +#ifdef __cplusplus +extern "C" { +#endif + +const char* EMU_CALL qsound_getversion(void); + +sint32 EMU_CALL qsound_init(void); +uint32 EMU_CALL qsound_get_state_size(void); +void EMU_CALL qsound_clear_state(void *state); + +// +// Obtain substates +// +void* EMU_CALL qsound_get_z80_state (void *state); +void* EMU_CALL qsound_get_qmix_state(void *state); + +uint16 EMU_CALL qsound_getpc(void *state); + +// +// Set ROM pointers, etc. +// +void EMU_CALL qsound_set_sample_rom(void *state, void *rom, uint32 size); +void EMU_CALL qsound_set_z80_rom(void *state, void *rom, uint32 size); +void EMU_CALL qsound_set_kabuki_key(void *state, + uint32 swap_key1, uint32 swap_key2, uint16 addr_key, uint8 xor_key +); + +void EMU_CALL qsound_set_rates( + void *state, + uint32 z80, + uint32 irq, + uint32 sample +); + +uint64 EMU_CALL qsound_get_odometer(void *state); + +// +// Executes +// Returns: +// >= 0: success (the number of cycles actually executed) +// -1: error +// +sint32 EMU_CALL qsound_execute( + void *state, + sint32 cycles, + sint16 *sound_buf, + uint32 *sound_samples +); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Frameworks/HighlyQuixotic/HighlyQuixotic/Core/z80.c b/Frameworks/HighlyQuixotic/HighlyQuixotic/Core/z80.c new file mode 100644 index 000000000..0dc2ed367 --- /dev/null +++ b/Frameworks/HighlyQuixotic/HighlyQuixotic/Core/z80.c @@ -0,0 +1,3076 @@ +///////////////////////////////////////////////////////////////////////////// +// +// z80 - Emulates Z80 CPU +// +///////////////////////////////////////////////////////////////////////////// + +#ifndef EMU_COMPILE +#error "Hi I forgot to set EMU_COMPILE" +#endif + +#include "z80.h" + +// no 'conversion from _blah_ possible loss of data' warnings +#pragma warning (disable: 4244) + +//#define TESTZ80 + +///////////////////////////////////////////////////////////////////////////// +// +// Static information +// +static const uint8 cycletable_normal[0x100] = { + 4,10, 7, 6, 4, 4, 7, 4, 4,11, 7, 6, 4, 4, 7, 4, + 8,10, 7, 6, 4, 4, 7, 4,12,11, 7, 6, 4, 4, 7, 4, + 7,10,16, 6, 4, 4, 7, 4, 7,11,16, 6, 4, 4, 7, 4, + 7,10,13, 6,11,11,10, 4, 7,11,13, 6, 4, 4, 7, 4, + 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4, + 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4, + 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4, + 7, 7, 7, 7, 7, 7, 4, 7, 4, 4, 4, 4, 4, 4, 7, 4, + 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4, + 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4, + 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4, + 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4, + 5,10,10,10,10,11, 7,11, 5,10,10, 0,10,17, 7,11, + 5,10,10,11,10,11, 7,11, 5, 4,10,11,10, 0, 7,11, + 5,10,10,19,10,11, 7,11, 5, 4,10, 4,10, 0, 7,11, + 5,10,10, 4,10,11, 7,11, 5, 6,10, 4,10, 0, 7,11}; + +static const uint8 cycletable_cb[0x100] = { + 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8, + 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8, + 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8, + 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8, + 8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8, + 8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8, + 8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8, + 8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8, + 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8, + 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8, + 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8, + 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8, + 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8, + 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8, + 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8, + 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8}; + +static const uint8 cycletable_ed[0x100] = { + 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, + 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, + 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, + 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, +12,12,15,20, 8, 8, 8, 9,12,12,15,20, 8, 8, 8, 9, +12,12,15,20, 8, 8, 8, 9,12,12,15,20, 8, 8, 8, 9, +12,12,15,20, 8, 8, 8,18,12,12,15,20, 8, 8, 8,18, +12,12,15,20, 8, 8, 8, 8,12,12,15,20, 8, 8, 8, 8, + 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, + 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, +16,16,16,16, 8, 8, 8, 8,16,16,16,16, 8, 8, 8, 8, +16,16,16,16, 8, 8, 8, 8,16,16,16,16, 8, 8, 8, 8, + 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, + 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, + 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, + 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8}; + +static const uint8 cycletable_xy[0x100] = { + 4, 4, 4, 4, 4, 4, 4, 4, 4,15, 4, 4, 4, 4, 4, 4, + 4, 4, 4, 4, 4, 4, 4, 4, 4,15, 4, 4, 4, 4, 4, 4, + 4,14,20,10, 9, 9, 9, 4, 4,15,20,10, 9, 9, 9, 4, + 4, 4, 4, 4,23,23,19, 4, 4,15, 4, 4, 4, 4, 4, 4, + 4, 4, 4, 4, 9, 9,19, 4, 4, 4, 4, 4, 9, 9,19, 4, + 4, 4, 4, 4, 9, 9,19, 4, 4, 4, 4, 4, 9, 9,19, 4, + 9, 9, 9, 9, 9, 9,19, 9, 9, 9, 9, 9, 9, 9,19, 9, +19,19,19,19,19,19, 4,19, 4, 4, 4, 4, 9, 9,19, 4, + 4, 4, 4, 4, 9, 9,19, 4, 4, 4, 4, 4, 9, 9,19, 4, + 4, 4, 4, 4, 9, 9,19, 4, 4, 4, 4, 4, 9, 9,19, 4, + 4, 4, 4, 4, 9, 9,19, 4, 4, 4, 4, 4, 9, 9,19, 4, + 4, 4, 4, 4, 9, 9,19, 4, 4, 4, 4, 4, 9, 9,19, 4, + 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 4, 4, 4, 4, + 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, + 4,14, 4,23, 4,15, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4, + 4, 4, 4, 4, 4, 4, 4, 4, 4,10, 4, 4, 4, 4, 4, 4}; + +#define cycletable_dd cycletable_xy +#define cycletable_fd cycletable_xy + +static const uint8 cycletable_xycb[0x100] = { +23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23, +23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23, +23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23, +23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23, +20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20, +20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20, +20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20, +20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20, +23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23, +23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23, +23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23, +23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23, +23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23, +23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23, +23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23, +23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23}; + +// extra cycles if jr/jp/call taken and 'interrupt latency' on rst 0-7 +static const uint8 cycletable_ex[0x100] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // DJNZ + 5, 0, 0, 0, 0, 0, 0, 0, 5, 0, 0, 0, 0, 0, 0, 0, // JR NZ/JR Z + 5, 0, 0, 0, 0, 0, 0, 0, 5, 0, 0, 0, 0, 0, 0, 0, // JR NC/JR C + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 5, 5, 5, 5, 0, 0, 0, 0, 5, 5, 5, 5, 0, 0, 0, 0, // LDIR/CPIR/INIR/OTIR LDDR/CPDR/INDR/OTDR + 6, 0, 0, 0, 7, 0, 0, 2, 6, 0, 0, 0, 7, 0, 0, 2, + 6, 0, 0, 0, 7, 0, 0, 2, 6, 0, 0, 0, 7, 0, 0, 2, + 6, 0, 0, 0, 7, 0, 0, 2, 6, 0, 0, 0, 7, 0, 0, 2, + 6, 0, 0, 0, 7, 0, 0, 2, 6, 0, 0, 0, 7, 0, 0, 2}; + +static uint8 SZ [0x100]; +static uint8 SZP [0x100]; +static uint8 SZHV_inc[0x100]; +static uint8 SZHV_dec[0x100]; + +#define CF (0x01) +#define NF (0x02) +#define PF (0x04) +#define VF (PF) +#define XF (0x08) +#define HF (0x10) +#define YF (0x20) +#define ZF (0x40) +#define SF (0x80) + +// +// Init: mainly just initialize the flag lookup tables +// +sint32 z80_init(void) { + uint32 i; + for (i = 0; i < 256; i++) { + uint32 nbits = 0; + if(i & 0x01) { nbits++; } + if(i & 0x02) { nbits++; } + if(i & 0x04) { nbits++; } + if(i & 0x08) { nbits++; } + if(i & 0x10) { nbits++; } + if(i & 0x20) { nbits++; } + if(i & 0x40) { nbits++; } + if(i & 0x80) { nbits++; } + SZ[i] = i ? i & SF : ZF; + SZ[i] |= (i & (YF | XF)); /* undocumented flag bits 5+3 */ + SZP[i] = SZ[i] | ((nbits & 1) ? 0 : PF); + SZHV_inc[i] = SZ[i]; + if(i == 0x80) { SZHV_inc[i] |= VF; } + if((i & 0x0F) == 0x00) { SZHV_inc[i] |= HF; } + SZHV_dec[i] = SZ[i] | NF; + if(i == 0x7F) { SZHV_dec[i] |= VF; } + if((i & 0x0F) == 0x0F) { SZHV_dec[i] |= HF; } + } + +//printf("z80 init\n"); + return 0; +} + +///////////////////////////////////////////////////////////////////////////// +// +// State information +// +struct Z80_STATE { + uint16 af; + uint16 bc; + uint16 de; + uint16 hl; + uint16 pc; + uint16 sp; + uint16 ix; + uint16 iy; + uint16 af2; + uint16 bc2; + uint16 de2; + uint16 hl2; + uint8 r; + uint8 r2; + uint8 i; + uint8 irq_vector; + uint32 imflags; // nmistate,intstate,halt,badins,iff2,iff1,im(1-0) + +#define IMFLAGS_NMISTATE (0x80) +#define IMFLAGS_IRQSTATE (0x40) +#define IMFLAGS_HALT (0x20) +#define IMFLAGS_BADINS (0x10) +#define IMFLAGS_IFF2 (0x08) +#define IMFLAGS_IFF1 (0x04) +#define IMFLAGS_IM (0x03) + + sint32 cycles_remaining; + sint32 cycles_remaining_last_checkpoint; + sint32 cycles_deferred_from_break; + + // + // These are REGISTERED EXTERNAL POINTERS. + // + z80_advance_callback_t advance; + void *hwstate; + struct Z80_MEMORY_MAP *map_op; + struct Z80_MEMORY_MAP *map_read; + struct Z80_MEMORY_MAP *map_write; + struct Z80_MEMORY_MAP *map_in; + struct Z80_MEMORY_MAP *map_out; +}; + +#define STATE ((struct Z80_STATE*)(state)) + +///////////////////////////////////////////////////////////////////////////// +// +// TESTZ80 stuff +// +#ifdef TESTZ80 + +#define MAXRW (256) + +static uint8 testz80_irq = 0; + +static uint32 testz80_numrw = 0; +static uint32 testz80_subrw = 0; +static uint8 testz80_rwtype[MAXRW]; +static uint16 testz80_rwaddr[MAXRW]; +static uint8 testz80_rwdata[MAXRW]; +#define TESTZ80_TYPE_READ (0x00) +#define TESTZ80_TYPE_WRITE (0x01) +#define TESTZ80_TYPE_IN (0x02) +#define TESTZ80_TYPE_OUT (0x03) + +static struct Z80_STATE *testz80_state = 0; + +static const char *testz80_typestr[4] = { "R","W","I","O" }; + +static void testz80_setstate(struct Z80_STATE *mainstate) { + testz80_state = mainstate; +} + +static void testz80_newins(void) { + testz80_numrw = 0; + testz80_subrw = 0; + testz80_irq = 0; +} + +static void testz80_logrw(uint8 t, uint16 a, uint8 d) { + if(testz80_numrw >= MAXRW) { *((volatile char*)0) = 0; } + testz80_rwtype[testz80_numrw] = t; + testz80_rwaddr[testz80_numrw] = a; + testz80_rwdata[testz80_numrw] = d; + testz80_numrw++; +} + +static void testz80_logread (uint16 a, uint8 d) { testz80_logrw(TESTZ80_TYPE_READ , a, d); } +static void testz80_logwrite(uint16 a, uint8 d) { testz80_logrw(TESTZ80_TYPE_WRITE, a, d); } +static void testz80_login (uint16 a, uint8 d) { testz80_logrw(TESTZ80_TYPE_IN , a, d); } +static void testz80_logout (uint16 a, uint8 d) { testz80_logrw(TESTZ80_TYPE_OUT , a, d); } + +uint16 testz80_getsub_af(void); +uint16 testz80_getsub_bc(void); +uint16 testz80_getsub_de(void); +uint16 testz80_getsub_hl(void); +uint16 testz80_getsub_pc(void); +uint16 testz80_getsub_sp(void); +uint16 testz80_getsub_ix(void); +uint16 testz80_getsub_iy(void); +uint16 testz80_getsub_af2(void); +uint16 testz80_getsub_bc2(void); +uint16 testz80_getsub_de2(void); +uint16 testz80_getsub_hl2(void); + +static void testz80_dumprw(char *s) { + uint32 i; + for(i = 0; i < testz80_numrw; i++) { + sprintf(s+strlen(s), "[%s] 0x%04X,0x%02X %s\n", + (testz80_typestr[testz80_rwtype[i]&3]), + testz80_rwaddr[i], + testz80_rwdata[i], + (testz80_subrw == i) ? "<--subrw" : "" + ); + } + if((testz80_numrw > 0) && (testz80_subrw >= i)) { + sprintf(s+strlen(s), "<--subrw\n"); + } +} + +static void testz80_dumpregs(char *s) { + sprintf(s+strlen(s), "regs (main) (sub)\n"); + sprintf(s+strlen(s), "af = %04X %04X\n", testz80_state->af , testz80_getsub_af ()); + sprintf(s+strlen(s), "bc = %04X %04X\n", testz80_state->bc , testz80_getsub_bc ()); + sprintf(s+strlen(s), "de = %04X %04X\n", testz80_state->de , testz80_getsub_de ()); + sprintf(s+strlen(s), "hl = %04X %04X\n", testz80_state->hl , testz80_getsub_hl ()); + sprintf(s+strlen(s), "pc = %04X %04X\n", testz80_state->pc , testz80_getsub_pc ()); + sprintf(s+strlen(s), "sp = %04X %04X\n", testz80_state->sp , testz80_getsub_sp ()); + sprintf(s+strlen(s), "ix = %04X %04X\n", testz80_state->ix , testz80_getsub_ix ()); + sprintf(s+strlen(s), "iy = %04X %04X\n", testz80_state->iy , testz80_getsub_iy ()); + sprintf(s+strlen(s), "af2 = %04X %04X\n", testz80_state->af2, testz80_getsub_af2()); + sprintf(s+strlen(s), "bc2 = %04X %04X\n", testz80_state->bc2, testz80_getsub_bc2()); + sprintf(s+strlen(s), "de2 = %04X %04X\n", testz80_state->de2, testz80_getsub_de2()); + sprintf(s+strlen(s), "hl2 = %04X %04X\n", testz80_state->hl2, testz80_getsub_hl2()); +} + +//#include + +static void testz80_errorout(const char *name) { + char s[10000]; + uint32 i; + strcpy(s, name); + strcat(s,"\n"); + testz80_dumprw(s); + testz80_dumpregs(s); + +{ FILE *f=fopen("C:\\corlett\\testz80.out","wt"); +fprintf(f,s); +fclose(f); +exit(1); +} +// MessageBox(NULL,s,"testz80 error",MB_OK); +} + +static void testz80_rwmismatch1(const char *name, uint16 a) { + char s[100]; sprintf(s, "mismatch sub %s(0x%04X)", name, a); testz80_errorout(s); +} + +static void testz80_rwmismatch2(const char *name, uint16 a, uint8 d) { + char s[100]; sprintf(s, "mismatch sub %s(0x%04X,0x%02X)", name, a, d); testz80_errorout(s); +} + +static void testz80_compareregs(void) { + if(testz80_state->af != testz80_getsub_af ()) testz80_errorout("af mismatch"); + if(testz80_state->bc != testz80_getsub_bc ()) testz80_errorout("bc mismatch"); + if(testz80_state->de != testz80_getsub_de ()) testz80_errorout("de mismatch"); + if(testz80_state->hl != testz80_getsub_hl ()) testz80_errorout("hl mismatch"); + if(testz80_state->pc != testz80_getsub_pc ()) testz80_errorout("pc mismatch"); + if(testz80_state->sp != testz80_getsub_sp ()) testz80_errorout("sp mismatch"); + if(testz80_state->ix != testz80_getsub_ix ()) testz80_errorout("ix mismatch"); + if(testz80_state->iy != testz80_getsub_iy ()) testz80_errorout("iy mismatch"); + if(testz80_state->af2 != testz80_getsub_af2()) testz80_errorout("af2 mismatch"); + if(testz80_state->bc2 != testz80_getsub_bc2()) testz80_errorout("bc2 mismatch"); + if(testz80_state->de2 != testz80_getsub_de2()) testz80_errorout("de2 mismatch"); + if(testz80_state->hl2 != testz80_getsub_hl2()) testz80_errorout("hl2 mismatch"); + if(testz80_numrw != testz80_subrw) testz80_errorout("rw count mismatch"); +} + +uint8 testz80_subread(uint16 a) { + if( + (testz80_subrw >= testz80_numrw) || + (testz80_rwtype[testz80_subrw] != TESTZ80_TYPE_READ) || + (testz80_rwaddr[testz80_subrw] != a) + ) { + testz80_rwmismatch1("read", a); + } + testz80_subrw++; + return testz80_rwdata[testz80_subrw - 1]; +} + +uint8 testz80_subin(uint16 a) { + if( + (testz80_subrw >= testz80_numrw) || + (testz80_rwtype[testz80_subrw] != TESTZ80_TYPE_IN) || + (testz80_rwaddr[testz80_subrw] != a) + ) { + testz80_rwmismatch1("in", a); + } + testz80_subrw++; + return testz80_rwdata[testz80_subrw - 1]; +} + +void testz80_subwrite(uint16 a, uint8 d) { + if( + (testz80_subrw >= testz80_numrw) || + (testz80_rwtype[testz80_subrw] != TESTZ80_TYPE_WRITE) || + (testz80_rwaddr[testz80_subrw] != a) || + (testz80_rwdata[testz80_subrw] != d) + ) { + testz80_rwmismatch2("write", a, d); + } + testz80_subrw++; +} + +void testz80_subout(uint16 a, uint8 d) { + if( + (testz80_subrw >= testz80_numrw) || + (testz80_rwtype[testz80_subrw] != TESTZ80_TYPE_OUT) || + (testz80_rwaddr[testz80_subrw] != a) || + (testz80_rwdata[testz80_subrw] != d) + ) { + testz80_rwmismatch2("out", a, d); + } + testz80_subrw++; +} + +void testz80_subexec(void); +void testz80_subinit(void); +void testz80_subrst38h(void); + +#endif + +///////////////////////////////////////////////////////////////////////////// + +#define OFS_LO (0^(EMU_ENDIAN_XOR_L2H(1))) +#define OFS_HI (1^(EMU_ENDIAN_XOR_L2H(1))) + +#define _AF (STATE->af) +#define _BC (STATE->bc) +#define _DE (STATE->de) +#define _HL (STATE->hl) +#define _PC (STATE->pc) +#define _SP (STATE->sp) +#define _IX (STATE->ix) +#define _IY (STATE->iy) + +#define _A (((uint8*)(&(STATE->af)))[OFS_HI]) +#define _F (((uint8*)(&(STATE->af)))[OFS_LO]) +#define _B (((uint8*)(&(STATE->bc)))[OFS_HI]) +#define _C (((uint8*)(&(STATE->bc)))[OFS_LO]) +#define _D (((uint8*)(&(STATE->de)))[OFS_HI]) +#define _E (((uint8*)(&(STATE->de)))[OFS_LO]) +#define _H (((uint8*)(&(STATE->hl)))[OFS_HI]) +#define _L (((uint8*)(&(STATE->hl)))[OFS_LO]) +#define _HX (((uint8*)(&(STATE->ix)))[OFS_HI]) +#define _LX (((uint8*)(&(STATE->ix)))[OFS_LO]) +#define _HY (((uint8*)(&(STATE->iy)))[OFS_HI]) +#define _LY (((uint8*)(&(STATE->iy)))[OFS_LO]) + +#define _R (STATE->r) +#define _I (STATE->i) +#define _R2 (STATE->r2) + +///////////////////////////////////////////////////////////////////////////// + +uint32 EMU_CALL z80_get_state_size(void) { + return sizeof(struct Z80_STATE); +} + +void EMU_CALL z80_clear_state(void *state) { + memset(state, 0, sizeof(struct Z80_STATE)); + _IX = 0xFFFF; + _IY = 0xFFFF; + _F = ZF; +#ifdef TESTZ80 +testz80_subinit(); +testz80_setstate(state); +#endif +} + +///////////////////////////////////////////////////////////////////////////// + +void EMU_CALL z80_set_memory_maps( + void *state, + struct Z80_MEMORY_MAP *map_op, + struct Z80_MEMORY_MAP *map_read, + struct Z80_MEMORY_MAP *map_write, + struct Z80_MEMORY_MAP *map_in, + struct Z80_MEMORY_MAP *map_out +) { + STATE->map_op = map_op; + STATE->map_read = map_read; + STATE->map_write = map_write; + STATE->map_in = map_in; + STATE->map_out = map_out; +} + +///////////////////////////////////////////////////////////////////////////// + +void EMU_CALL z80_set_advance_callback( + void *state, + z80_advance_callback_t advance, + void *hwstate +) { + STATE->advance = advance; + STATE->hwstate = hwstate; +} + +///////////////////////////////////////////////////////////////////////////// + +uint16 EMU_CALL z80_getpc(void *state) { return _PC; } + +///////////////////////////////////////////////////////////////////////////// + +void EMU_CALL z80_break(void *state) { + if(STATE->cycles_remaining <= 0) return; + STATE->cycles_deferred_from_break += STATE->cycles_remaining; + STATE->cycles_remaining_last_checkpoint -= STATE->cycles_remaining; + STATE->cycles_remaining = 0; +} + +///////////////////////////////////////////////////////////////////////////// + +void EMU_CALL z80_setirq(void *state, uint8 irq, uint8 vector) { + if(!irq) { + STATE->imflags &= ~(IMFLAGS_IRQSTATE); + } else { + STATE->imflags |= IMFLAGS_IRQSTATE; + STATE->irq_vector = vector; + } + z80_break(state); +} + +void EMU_CALL z80_setnmi(void *state, uint8 nmi) { + if(!nmi) { + STATE->imflags &= ~(IMFLAGS_NMISTATE); + } else { + STATE->imflags |= IMFLAGS_NMISTATE; + } + z80_break(state); +} + +///////////////////////////////////////////////////////////////////////////// + +static EMU_INLINE struct Z80_MEMORY_TYPE* mmwalk( + struct Z80_MEMORY_MAP *map, + uint16 a +) { + for(;; map++) { + if(a < (map->x) || a > (map->y)) continue; + return &(map->type); + } +} + +static EMU_INLINE void hw_sync(struct Z80_STATE *state) { + sint32 d = state->cycles_remaining_last_checkpoint - state->cycles_remaining; + if(d > 0) { + state->advance(state->hwstate, d); + state->cycles_remaining_last_checkpoint = state->cycles_remaining; + } +} + +static EMU_INLINE uint8 map_readb( + struct Z80_STATE *state, + struct Z80_MEMORY_MAP *map, + uint16 a +) { + struct Z80_MEMORY_TYPE *t = mmwalk(map, a); + a &= t->mask; + if(t->n == Z80_MAP_TYPE_POINTER) { + return *((uint8*)(((uint8*)(t->p))+a)); + } else { + hw_sync(state); + return ((z80_read_callback_t)(t->p))(state->hwstate, a); + } +} + +static EMU_INLINE void map_writeb( + struct Z80_STATE *state, + struct Z80_MEMORY_MAP *map, + uint16 a, + uint8 d +) { + struct Z80_MEMORY_TYPE *t = mmwalk(map, a); + a &= t->mask; + if(t->n == Z80_MAP_TYPE_POINTER) { + *((uint8*)(((uint8*)(t->p))+a)) = d; + } else { + hw_sync(state); + ((z80_write_callback_t)(t->p))(state->hwstate, a, d); + } +} + +///////////////////////////////////////////////////////////////////////////// + +static EMU_INLINE uint8 z80_opb(struct Z80_STATE *state, uint16 a) { + uint8 d; +//printf("z80 op byte %04X", a); fflush(stdout); + d = map_readb(state, state->map_op, a); +//printf(" = %02X\n", d); fflush(stdout); +#ifdef TESTZ80 +testz80_logread(a, d); +#endif + return d; +} +static EMU_INLINE uint8 z80_readb(struct Z80_STATE *state, uint16 a) { + uint8 d; +//printf("z80 read byte %04X", a); fflush(stdout); + d = map_readb(state, state->map_read, a); +//printf(" = %02X\n", d); fflush(stdout); +#ifdef TESTZ80 +testz80_logread(a, d); +#endif + return d; +} +static EMU_INLINE void z80_writeb(struct Z80_STATE *state, uint16 a, uint8 d) { +//printf("z80 write byte %04X = %02X\n", a, d); fflush(stdout); + map_writeb(state, state->map_write, a, d); +#ifdef TESTZ80 +testz80_logwrite(a, d); +#endif +} +static EMU_INLINE uint8 z80_inb(struct Z80_STATE *state, uint16 a) { + uint8 d; + d = map_readb(state, state->map_in, a); +#ifdef TESTZ80 +testz80_login(a, d); +#endif + return d; +} +static EMU_INLINE void z80_outb(struct Z80_STATE *state, uint16 a, uint8 d) { + map_writeb(state, state->map_out, a, d); +#ifdef TESTZ80 +testz80_logout(a, d); +#endif +} + +///////////////////////////////////////////////////////////////////////////// + +static EMU_INLINE uint16 z80_readw(struct Z80_STATE *state, uint16 a) { + uint16 t; + t = ((uint32)(z80_readb(state, a ))); + t |= ((uint32)(z80_readb(state, a+1))) << 8; + return t; +} +static EMU_INLINE void z80_writew(struct Z80_STATE *state, uint16 a, uint16 d) { + z80_writeb(state, a , (uint8)(d )); + z80_writeb(state, a+1, (uint8)(d>>8)); +} + +///////////////////////////////////////////////////////////////////////////// + +static EMU_INLINE uint8 z80_ropb(struct Z80_STATE *state) { + uint16 t = _PC; _PC++; return z80_opb(state, t); +} + +static EMU_INLINE uint8 z80_readpcb(struct Z80_STATE *state) { + uint16 t = _PC; _PC++; return z80_readb(state, t); +} + +static EMU_INLINE uint16 z80_readpcw(struct Z80_STATE *state) { + uint16 t = _PC; _PC+=2; return z80_readw(state, t); +} + +///////////////////////////////////////////////////////////////////////////// + +#define RM(a) z80_readb(state,a) +#define RM16(a) z80_readw(state,a) +#define WM(a,d) z80_writeb(state,a,d) +#define WM16(a,d) z80_writew(state,a,d) +#define ARG() z80_readpcb(state) +#define ARG16() z80_readpcw(state) +#define ROP() z80_ropb(STATE) +#define Z80IN(a) z80_inb(state,a) +#define Z80OUT(a,d) z80_outb(state,a,d) + +///////////////////////////////////////////////////////////////////////////// + +#define CC(table,op) do{STATE->cycles_remaining-=cycletable_##table[(op)];}while(0) + +///////////////////////////////////////////////////////////////////////////// + +#define EXEC(type,op) do{ \ + uint8 t=(op); \ + z80_exec_##type(state,t); \ + CC(type,t); \ +}while(0) + +#define EXEC_EA(type,op,ea) do{ \ + uint8 t=(op); \ + z80_exec_ea_##type(state,t,ea); \ + CC(type,t); \ +}while(0) + +///////////////////////////////////////////////////////////////////////////// + +static EMU_INLINE uint16 op_pop(struct Z80_STATE *state) { + uint16 t = RM16(_SP); _SP += 2; return t; +} +#define POP() op_pop(state) + +#define PUSH(x) do{ uint16 t=(x); _SP -= 1; WM(_SP, (t>>8)); _SP -= 1; WM(_SP, (t)); }while(0) + +///////////////////////////////////////////////////////////////////////////// + +static EMU_INLINE void checkinterrupts(struct Z80_STATE *state) { + // IRQ + if( + (state->imflags & IMFLAGS_IRQSTATE) && + (state->imflags & IMFLAGS_IFF1) + ) { +#ifdef TESTZ80 +testz80_irq = 1; +#endif + if(state->imflags & IMFLAGS_HALT) { _PC++; } + // auto-acknowledge interrupts. TODO: is this right? + state->imflags &= ~(IMFLAGS_HALT | IMFLAGS_IFF1 | IMFLAGS_IRQSTATE); + PUSH( _PC ); +//printf("z80 interrupt(mode=%d)\n",state->imflags & IMFLAGS_IM);fflush(stdout); + switch(state->imflags & IMFLAGS_IM) { + case 0: + _PC = state->irq_vector & 0x38; + CC(normal,0xFF); + break; + case 1: + _PC = 0x38; + CC(normal,0xFF); + break; + case 2: + _PC = RM16( + (((uint32)(state->irq_vector)) ) | + (((uint32)(state->i )) << 8) + ); + CC(normal,0xCD); + break; + } + } + // NMI + if(state->imflags & IMFLAGS_NMISTATE) { + if(state->imflags & IMFLAGS_HALT) { _PC++; } + state->imflags &= ~(IMFLAGS_HALT | IMFLAGS_IFF1 | IMFLAGS_NMISTATE); + PUSH( _PC ); + _PC = 0x0066; + CC(normal,0xFF); + } +} + +///////////////////////////////////////////////////////////////////////////// +// +// TODO: perhaps there's some latency after EI before interrupts really are +// enabled +// +#define EI do{state->imflags|= (IMFLAGS_IFF1|IMFLAGS_IFF2);checkinterrupts(state);}while(0) +#define DI do{state->imflags&=~(IMFLAGS_IFF1|IMFLAGS_IFF2);}while(0) +#define IM(x) do{state->imflags&=~(IMFLAGS_IM);state->imflags|=(x);}while(0) + +#define RETN do{ \ + _PC = POP(); \ + if(state->imflags & IMFLAGS_IFF2) { \ + state->imflags |= IMFLAGS_IFF1; \ + checkinterrupts(state); \ + } else { \ + state->imflags &= ~(IMFLAGS_IFF1); \ + } \ +}while(0) + +#define RETI do{ \ + _PC = POP(); \ + if(state->imflags & IMFLAGS_IFF2) { \ + state->imflags |= IMFLAGS_IFF1; \ + checkinterrupts(state); \ + } else { \ + state->imflags &= ~(IMFLAGS_IFF1); \ + } \ +}while(0) + +///////////////////////////////////////////////////////////////////////////// + +static EMU_INLINE uint8 op_inc(struct Z80_STATE *state, uint8 value) { + uint8 res = value + 1; + _F = (_F & CF) | SZHV_inc[res]; + return res; +} +#define INC(d) op_inc(state,d) + +static EMU_INLINE uint8 op_dec(struct Z80_STATE *state, uint8 value) { + uint8 res = value - 1; + _F = (_F & CF) | SZHV_dec[res]; + return res; +} +#define DEC(d) op_dec(state,d) + +#define RLCA do{ \ + _A = (_A << 1) | (_A >> 7); \ + _F = (_F & (SF | ZF | PF)) | (_A & (YF | XF | CF)); \ +}while(0) + +#define RRCA do{ \ + _F = (_F & (SF | ZF | PF)) | (_A & CF); \ + _A = (_A >> 1) | (_A << 7); \ + _F |= (_A & (YF | XF) ); \ +}while(0) + +#define RLA do{ \ + uint8 res = (_A << 1) | (_F & CF); \ + uint8 c = (_A & 0x80) ? CF : 0; \ + _F = (_F & (SF | ZF | PF)) | c | (res & (YF | XF)); \ + _A = res; \ +}while(0) + +#define RRA do{ \ + uint8 res = (_A >> 1) | (_F << 7); \ + uint8 c = (_A & 0x01) ? CF : 0; \ + _F = (_F & (SF | ZF | PF)) | c | (res & (YF | XF)); \ + _A = res; \ +}while(0) + +#define RRD do{ \ + uint8 n = RM(_HL); \ + WM( _HL, (n >> 4) | (_A << 4) ); \ + _A = (_A & 0xf0) | (n & 0x0f); \ + _F = (_F & CF) | SZP[_A]; \ +}while(0) + +#define RLD do{ \ + uint8 n = RM(_HL); \ + WM( _HL, (n << 4) | (_A & 0x0f) ); \ + _A = (_A & 0xf0) | (n >> 4); \ + _F = (_F & CF) | SZP[_A]; \ +}while(0) + +#define ADD(value) do{ \ + uint32 val = (value); \ + uint32 res = ((uint32)_A) + val; \ + _F = SZ[(uint8)res] | ((res >> 8) & CF) | \ + ((_A ^ res ^ val) & HF) | \ + (((val ^ _A ^ 0x80) & (val ^ res) & 0x80) >> 5); \ + _A = (uint8)res; \ +}while(0) + +#define ADC(value) do{ \ + uint32 val = (value); \ + uint32 res = ((uint32)_A) + val + ((uint32)(_F & CF)); \ + _F = SZ[res & 0xff] | ((res >> 8) & CF) | \ + ((_A ^ res ^ val) & HF) | \ + (((val ^ _A ^ 0x80) & (val ^ res) & 0x80) >> 5); \ + _A = res; \ +}while(0) + +#define SUB(value) do{ \ + uint32 val = (value); \ + uint32 res = ((uint32)_A) - val; \ + _F = SZ[res & 0xff] | ((res >> 8) & CF) | NF | \ + ((_A ^ res ^ val) & HF) | \ + (((val ^ _A) & (_A ^ res) & 0x80) >> 5); \ + _A = res; \ +}while(0) + +#define SBC(value) do{ \ + uint32 val = (value); \ + uint32 res = ((uint32)_A) - val - ((uint32)(_F & CF)); \ + _F = SZ[res & 0xff] | ((res >> 8) & CF) | NF | \ + ((_A ^ res ^ val) & HF) | \ + (((val ^ _A) & (_A ^ res) & 0x80) >> 5); \ + _A = res; \ +}while(0) + +#define NEG do{ \ + uint8 value = _A; \ + _A = 0; \ + SUB(value); \ +}while(0) + +#define DAA do{ \ + uint8 cf, nf, hf, lo, hi, diff; \ + cf = _F & CF; \ + nf = _F & NF; \ + hf = _F & HF; \ + lo = _A & 15; \ + hi = _A / 16; \ + \ + if (cf) \ + { \ + diff = (lo <= 9 && !hf) ? 0x60 : 0x66; \ + } \ + else \ + { \ + if (lo >= 10) \ + { \ + diff = hi <= 8 ? 0x06 : 0x66; \ + } \ + else \ + { \ + if (hi >= 10) \ + { \ + diff = hf ? 0x66 : 0x60; \ + } \ + else \ + { \ + diff = hf ? 0x06 : 0x00; \ + } \ + } \ + } \ + if (nf) _A -= diff; \ + else _A += diff; \ + \ + _F = SZP[_A] | (_F & NF); \ + if (cf || (lo <= 9 ? hi >= 10 : hi >= 9)) _F |= CF; \ + if (nf ? hf && lo <= 5 : lo >= 10) _F |= HF; \ +}while(0) + +#define AND(value) do{ _A &= (value); _F = SZP[_A] | HF; }while(0) +#define OR(value) do{ _A |= (value); _F = SZP[_A]; }while(0) +#define XOR(value) do{ _A ^= (value); _F = SZP[_A]; }while(0) + +#define CP(value) do{ \ + uint32 val = (value); \ + uint32 res = ((uint32)_A) - val; \ + _F = (SZ[res & 0xff] & (SF | ZF)) | \ + (val & (YF | XF)) | ((res >> 8) & CF) | NF | \ + ((_A ^ res ^ val) & HF) | \ + ((((val ^ _A) & (_A ^ res)) >> 5) & VF); \ +}while(0) + +#define EX_AF do{uint16 t=state->af;state->af=state->af2;state->af2=t;}while(0) +#define EX_DE_HL do{uint16 t=state->de;state->de=state->hl ;state->hl =t;}while(0) +#define EXX do{ uint16 t; \ + t=state->bc;state->bc=state->bc2;state->bc2=t; \ + t=state->de;state->de=state->de2;state->de2=t; \ + t=state->hl;state->hl=state->hl2;state->hl2=t; \ +}while(0) + +static EMU_INLINE uint16 op_exsp16(struct Z80_STATE *state,uint16 x) { + uint16 t = RM16(_SP); WM16(_SP,x); return t; +} +#define EXSP16(x) op_exsp16(state,x) + +#define ADD16(DR,SR) do{ \ + uint32 res = ((uint32)(DR))+((uint32)(SR)); \ + _F = (_F & (SF | ZF | VF)) | \ + (((DR ^ res ^ SR) >> 8) & HF) | \ + ((res >> 16) & CF) | ((res >> 8) & (YF | XF)); \ + DR = res; \ +}while(0) + +#define ADC16(Reg) do{ \ + uint32 res = \ + ((uint32)(_HL)) + \ + ((uint32)(Reg)) + \ + ((uint32)(_F & CF)); \ + _F = (((_HL ^ res ^ Reg) >> 8) & HF) | \ + ((res >> 16) & CF) | \ + ((res >> 8) & (SF | YF | XF)) | \ + ((res & 0xFFFF) ? 0 : ZF) | \ + (((Reg ^ _HL ^ 0x8000) & (Reg ^ res) & 0x8000) >> 13); \ + _HL = res; \ +}while(0) + +#define SBC16(Reg) do{ \ + uint32 res = \ + ((uint32)(_HL)) - \ + ((uint32)(Reg)) - \ + ((uint32)(_F & CF)); \ +/* printf("SBC HL=%04X," #Reg "=%04X-F=%02X -> %08X\n",_HL,Reg,_F,res); */ \ + _F = (((_HL ^ res ^ Reg) >> 8) & HF) | NF | \ + ((res >> 16) & CF) | \ + ((res >> 8) & (SF | YF | XF)) | \ + ((res & 0xFFFF) ? 0 : ZF) | \ + (((Reg ^ _HL) & (_HL ^ res) &0x8000) >> 13); \ +/* printf("_F=%02X\n",_F); */ \ + _HL = res; \ +}while(0) + +static EMU_INLINE uint8 op_rlc(struct Z80_STATE *state, uint8 value) { + uint32 res = value; + uint32 c = (res & 0x80) ? CF : 0; + res = ((res << 1) | (res >> 7)) & 0xff; + _F = SZP[res] | c; + return res; +} +#define RLC(d) op_rlc(state,d) + +static EMU_INLINE uint8 op_rrc(struct Z80_STATE *state, uint8 value) { + uint32 res = value; + uint32 c = (res & 0x01) ? CF : 0; + res = ((res >> 1) | (res << 7)) & 0xff; + _F = SZP[res] | c; + return res; +} +#define RRC(d) op_rrc(state,d) + +static EMU_INLINE uint8 op_rl(struct Z80_STATE *state, uint8 value) { + uint32 res = value; + uint32 c = (res & 0x80) ? CF : 0; + res = ((res << 1) | (_F & CF)) & 0xff; + _F = SZP[res] | c; + return res; +} +#define RL(d) op_rl(state,d) + +static EMU_INLINE uint8 op_rr(struct Z80_STATE *state, uint8 value) { + uint32 res = value; + uint32 c = (res & 0x01) ? CF : 0; + res = ((res >> 1) | (_F << 7)) & 0xff; + _F = SZP[res] | c; + return res; +} +#define RR(d) op_rr(state,d) + +static EMU_INLINE uint8 op_sla(struct Z80_STATE *state, uint8 value) { + uint32 res = value; + uint32 c = (res & 0x80) ? CF : 0; + res = (res << 1) & 0xff; + _F = SZP[res] | c; + return res; +} +#define SLA(d) op_sla(state,d) + +static EMU_INLINE uint8 op_sra(struct Z80_STATE *state, uint8 value) { + uint32 res = value; + uint32 c = (res & 0x01) ? CF : 0; + res = ((res >> 1) | (res & 0x80)) & 0xff; + _F = SZP[res] | c; + return res; +} +#define SRA(d) op_sra(state,d) + +static EMU_INLINE uint8 op_sll(struct Z80_STATE *state, uint8 value) { + uint32 res = value; + uint32 c = (res & 0x80) ? CF : 0; + res = ((res << 1) | 0x01) & 0xff; + _F = SZP[res] | c; + return res; +} +#define SLL(d) op_sll(state,d) + +static EMU_INLINE uint8 op_srl(struct Z80_STATE *state, uint8 value) { + uint32 res = value; + uint32 c = (res & 0x01) ? CF : 0; + res = (res >> 1) & 0xff; + _F = SZP[res] | c; + return res; +} +#define SRL(d) op_srl(state,d) + +#define BIT(bit,reg) do{ _F = (_F & CF) | HF | SZP[(reg) & (1<<(bit))]; }while(0) +//#define BIT(bit,reg) do{ _F = (_F & CF) | HF | SZP[(reg) & (1<<(bit))]; _F&=~(YF|XF);_F|=(reg)&(YF|XF);}while(0) +#define BIT_XY(bit,reg) do{ _F = (_F & CF) | HF | (SZP[(reg) & (1<<(bit))] & ~(YF|XF)) | ((EA>>8) & (YF|XF)); }while(0) + +static EMU_INLINE uint8 RES(uint8 bit, uint8 value) { return value & ~(1<%04X)\n",_HL,_DE); */ \ + _F &= SF | ZF | CF; \ + io += _A; \ + if(io & 0x02) _F |= YF; /* bit 1 -> flag 5 */ \ + if(io & 0x08) _F |= XF; /* bit 3 -> flag 3 */ \ + _HL++; _DE++; _BC--; \ + if( _BC ) _F |= VF; \ +}while(0) + +#define CPI do{ \ + uint8 val = RM(_HL); \ + uint8 res = _A - val; \ + _HL++; _BC--; \ + _F = (_F & CF) | (SZ[res] & ~(YF|XF)) | ((_A ^ val ^ res) & HF) | NF; \ + if( _F & HF ) res -= 1; \ + if(res & 0x02) _F |= YF; /* bit 1 -> flag 5 */ \ + if(res & 0x08) _F |= XF; /* bit 3 -> flag 3 */ \ + if( _BC ) _F |= VF; \ +}while(0) + +#define INI do{ \ + uint32 t; \ + uint8 io = Z80IN(_BC); \ + _B--; \ + WM( _HL, io ); \ + _HL++; \ + _F = SZ[_B]; \ + t = (uint32)((_C + 1) & 0xff) + (uint32)io; \ + if( io & SF ) _F |= NF; \ + if( t & 0x100 ) _F |= HF | CF; \ + _F |= SZP[(uint8)(t & 0x07) ^ _B] & PF; \ +}while(0) + +#define OUTI do{ \ + uint32 t; \ + uint8 io = RM(_HL); \ + _B--; \ + Z80OUT( _BC, io ); \ + _HL++; \ + _F = SZ[_B]; \ + t = (uint32)_L + (uint32)io; \ + if( io & SF ) _F |= NF; \ + if( t & 0x100 ) _F |= HF | CF; \ + _F |= SZP[(uint8)(t & 0x07) ^ _B] & PF; \ +}while(0) + +#define LDD do{ \ + uint8 io = RM(_HL); \ + WM( _DE, io ); \ + _F &= SF | ZF | CF; \ + if( (_A + io) & 0x02 ) _F |= YF; /* bit 1 -> flag 5 */ \ + if( (_A + io) & 0x08 ) _F |= XF; /* bit 3 -> flag 3 */ \ + _HL--; _DE--; _BC--; \ + if( _BC ) _F |= VF; \ +}while(0) + +#define CPD do{ \ + uint8 val = RM(_HL); \ + uint8 res = _A - val; \ + _HL--; _BC--; \ + _F = (_F & CF) | (SZ[res] & ~(YF|XF)) | ((_A ^ val ^ res) & HF) | NF; \ + if( _F & HF ) res -= 1; \ + if( res & 0x02 ) _F |= YF; /* bit 1 -> flag 5 */ \ + if( res & 0x08 ) _F |= XF; /* bit 3 -> flag 3 */ \ + if( _BC ) _F |= VF; \ +}while(0) + +#define IND do{ \ + uint32 t; \ + uint8 io = Z80IN(_BC); \ + _B--; \ + WM( _HL, io ); \ + _HL--; \ + _F = SZ[_B]; \ + t = ((uint32)(_C - 1) & 0xff) + (uint32)io; \ + if( io & SF ) _F |= NF; \ + if( t & 0x100 ) _F |= HF | CF; \ + _F |= SZP[(uint8)(t & 0x07) ^ _B] & PF; \ +}while(0) + +#define OUTD do{ \ + uint32 t; \ + uint8 io = RM(_HL); \ + _B--; \ + Z80OUT( _BC, io ); \ + _HL--; \ + _F = SZ[_B]; \ + t = (uint32)_L + (uint32)io; \ + if( io & SF ) _F |= NF; \ + if( t & 0x100 ) _F |= HF | CF; \ + _F |= SZP[(uint8)(t & 0x07) ^ _B] & PF; \ +}while(0) + +#define LDIR do{ \ + LDI; \ + if( _BC ) { \ + _PC -= 2; \ + CC(ex,0xb0); \ + } \ +}while(0) + +#define CPIR do{ \ + CPI; \ + if( _BC && !(_F & ZF) ) { \ + _PC -= 2; \ + CC(ex,0xb1); \ + } \ +}while(0) + +#define INIR do{ \ + INI; \ + if( _B ) { \ + _PC -= 2; \ + CC(ex,0xb2); \ + } \ +}while(0) + +#define OTIR do{ \ + OUTI; \ + if( _B ) { \ + _PC -= 2; \ + CC(ex,0xb3); \ + } \ +}while(0) + +#define LDDR do{ \ + LDD; \ + if( _BC ) { \ + _PC -= 2; \ + CC(ex,0xb8); \ + } \ +}while(0) + +#define CPDR do{ \ + CPD; \ + if( _BC && !(_F & ZF) ) { \ + _PC -= 2; \ + CC(ex,0xb9); \ + } \ +}while(0) + +#define INDR do{ \ + IND; \ + if( _B ) { \ + _PC -= 2; \ + CC(ex,0xba); \ + } \ +}while(0) + +#define OTDR do{ \ + OUTD; \ + if( _B ) { \ + _PC -= 2; \ + CC(ex,0xbb); \ + } \ +}while(0) + +///////////////////////////////////////////////////////////////////////////// + +#define EAX do{EA=((uint32)((uint16)(_IX+((sint8)ARG()))));}while(0) +#define EAY do{EA=((uint32)((uint16)(_IY+((sint8)ARG()))));}while(0) + +#define JP do{_PC=ARG16();}while(0) +#define JP_COND(cond) do{if(cond){JP;}else{_PC+=2;}}while(0) + +#define JR do{sint16 o=((sint16)((sint8)(ARG())));_PC+=o;}while(0) +#define JR_COND(cond,op) do{if(cond){JR;CC(ex,op);}else{_PC+=1;}}while(0) + +#define CALL do{ uint16 t=ARG16(); PUSH(_PC); _PC = t; }while(0) +#define CALL_COND(cond,op) do{if(cond){CALL;CC(ex,op);}else{_PC+=2;}}while(0) + +#define RST(addr) do{ PUSH( _PC ); _PC = (addr); }while(0) + +#define RET_COND(cond,op) do{if(cond){_PC=POP();CC(ex,op);}}while(0) + +#define LD_R_A do{ \ + _R = _A; \ + _R2 = _A & 0x80; /* keep bit 7 of R */ \ +}while(0) + +#define LD_A_R do{ \ + _A = (_R & 0x7f) | _R2; \ + _F = (_F & CF) | SZ[_A]; \ + if(state->imflags & IMFLAGS_IFF2) _F |= (1<<2); \ +}while(0) + +#define LD_I_A do{ \ + _I = _A; \ +}while(0) + +#define LD_A_I do{ \ + _A = _I; \ + _F = (_F & CF) | SZ[_A]; \ + if(state->imflags & IMFLAGS_IFF2) _F |= (1<<2); \ +}while(0) + +///////////////////////////////////////////////////////////////////////////// + +#define illegal_1() do{ state->imflags = IMFLAGS_BADINS; z80_break(state); }while(0) +#define illegal_2() do{ state->imflags = IMFLAGS_BADINS; z80_break(state); }while(0) + +#define HALT do{ \ + state->imflags |= IMFLAGS_HALT; \ + state->cycles_remaining = 0; \ +}while(0) + +///////////////////////////////////////////////////////////////////////////// + +static EMU_INLINE void z80_exec_cb(struct Z80_STATE *state, uint8 op) { + +//printf("PC=%04X exec cb %02X\n",_PC, op);fflush(stdout); + + switch(op) { + case /*CB*/0x00: _B = RLC(_B); break; // RLC B + case /*CB*/0x01: _C = RLC(_C); break; // RLC C + case /*CB*/0x02: _D = RLC(_D); break; // RLC D + case /*CB*/0x03: _E = RLC(_E); break; // RLC E + case /*CB*/0x04: _H = RLC(_H); break; // RLC H + case /*CB*/0x05: _L = RLC(_L); break; // RLC L + case /*CB*/0x06: WM( _HL, RLC(RM(_HL)) ); break; // RLC (HL) + case /*CB*/0x07: _A = RLC(_A); break; // RLC A + + case /*CB*/0x08: _B = RRC(_B); break; // RRC B + case /*CB*/0x09: _C = RRC(_C); break; // RRC C + case /*CB*/0x0a: _D = RRC(_D); break; // RRC D + case /*CB*/0x0b: _E = RRC(_E); break; // RRC E + case /*CB*/0x0c: _H = RRC(_H); break; // RRC H + case /*CB*/0x0d: _L = RRC(_L); break; // RRC L + case /*CB*/0x0e: WM( _HL, RRC(RM(_HL)) ); break; // RRC (HL) + case /*CB*/0x0f: _A = RRC(_A); break; // RRC A + + case /*CB*/0x10: _B = RL(_B); break; // RL B + case /*CB*/0x11: _C = RL(_C); break; // RL C + case /*CB*/0x12: _D = RL(_D); break; // RL D + case /*CB*/0x13: _E = RL(_E); break; // RL E + case /*CB*/0x14: _H = RL(_H); break; // RL H + case /*CB*/0x15: _L = RL(_L); break; // RL L + case /*CB*/0x16: WM( _HL, RL(RM(_HL)) ); break; // RL (HL) + case /*CB*/0x17: _A = RL(_A); break; // RL A + + case /*CB*/0x18: _B = RR(_B); break; // RR B + case /*CB*/0x19: _C = RR(_C); break; // RR C + case /*CB*/0x1a: _D = RR(_D); break; // RR D + case /*CB*/0x1b: _E = RR(_E); break; // RR E + case /*CB*/0x1c: _H = RR(_H); break; // RR H + case /*CB*/0x1d: _L = RR(_L); break; // RR L + case /*CB*/0x1e: WM( _HL, RR(RM(_HL)) ); break; // RR (HL) + case /*CB*/0x1f: _A = RR(_A); break; // RR A + + case /*CB*/0x20: _B = SLA(_B); break; // SLA B + case /*CB*/0x21: _C = SLA(_C); break; // SLA C + case /*CB*/0x22: _D = SLA(_D); break; // SLA D + case /*CB*/0x23: _E = SLA(_E); break; // SLA E + case /*CB*/0x24: _H = SLA(_H); break; // SLA H + case /*CB*/0x25: _L = SLA(_L); break; // SLA L + case /*CB*/0x26: WM( _HL, SLA(RM(_HL)) ); break; // SLA (HL) + case /*CB*/0x27: _A = SLA(_A); break; // SLA A + + case /*CB*/0x28: _B = SRA(_B); break; // SRA B + case /*CB*/0x29: _C = SRA(_C); break; // SRA C + case /*CB*/0x2a: _D = SRA(_D); break; // SRA D + case /*CB*/0x2b: _E = SRA(_E); break; // SRA E + case /*CB*/0x2c: _H = SRA(_H); break; // SRA H + case /*CB*/0x2d: _L = SRA(_L); break; // SRA L + case /*CB*/0x2e: WM( _HL, SRA(RM(_HL)) ); break; // SRA (HL) + case /*CB*/0x2f: _A = SRA(_A); break; // SRA A + + case /*CB*/0x30: _B = SLL(_B); break; // SLL B + case /*CB*/0x31: _C = SLL(_C); break; // SLL C + case /*CB*/0x32: _D = SLL(_D); break; // SLL D + case /*CB*/0x33: _E = SLL(_E); break; // SLL E + case /*CB*/0x34: _H = SLL(_H); break; // SLL H + case /*CB*/0x35: _L = SLL(_L); break; // SLL L + case /*CB*/0x36: WM( _HL, SLL(RM(_HL)) ); break; // SLL (HL) + case /*CB*/0x37: _A = SLL(_A); break; // SLL A + + case /*CB*/0x38: _B = SRL(_B); break; // SRL B + case /*CB*/0x39: _C = SRL(_C); break; // SRL C + case /*CB*/0x3a: _D = SRL(_D); break; // SRL D + case /*CB*/0x3b: _E = SRL(_E); break; // SRL E + case /*CB*/0x3c: _H = SRL(_H); break; // SRL H + case /*CB*/0x3d: _L = SRL(_L); break; // SRL L + case /*CB*/0x3e: WM( _HL, SRL(RM(_HL)) ); break; // SRL (HL) + case /*CB*/0x3f: _A = SRL(_A); break; // SRL A + + case /*CB*/0x40: BIT(0,_B); break; // BIT 0,B + case /*CB*/0x41: BIT(0,_C); break; // BIT 0,C + case /*CB*/0x42: BIT(0,_D); break; // BIT 0,D + case /*CB*/0x43: BIT(0,_E); break; // BIT 0,E + case /*CB*/0x44: BIT(0,_H); break; // BIT 0,H + case /*CB*/0x45: BIT(0,_L); break; // BIT 0,L + case /*CB*/0x46: BIT(0,RM(_HL)); break; // BIT 0,(HL) + case /*CB*/0x47: BIT(0,_A); break; // BIT 0,A + + case /*CB*/0x48: BIT(1,_B); break; // BIT 1,B + case /*CB*/0x49: BIT(1,_C); break; // BIT 1,C + case /*CB*/0x4a: BIT(1,_D); break; // BIT 1,D + case /*CB*/0x4b: BIT(1,_E); break; // BIT 1,E + case /*CB*/0x4c: BIT(1,_H); break; // BIT 1,H + case /*CB*/0x4d: BIT(1,_L); break; // BIT 1,L + case /*CB*/0x4e: BIT(1,RM(_HL)); break; // BIT 1,(HL) + case /*CB*/0x4f: BIT(1,_A); break; // BIT 1,A + + case /*CB*/0x50: BIT(2,_B); break; // BIT 2,B + case /*CB*/0x51: BIT(2,_C); break; // BIT 2,C + case /*CB*/0x52: BIT(2,_D); break; // BIT 2,D + case /*CB*/0x53: BIT(2,_E); break; // BIT 2,E + case /*CB*/0x54: BIT(2,_H); break; // BIT 2,H + case /*CB*/0x55: BIT(2,_L); break; // BIT 2,L + case /*CB*/0x56: BIT(2,RM(_HL)); break; // BIT 2,(HL) + case /*CB*/0x57: BIT(2,_A); break; // BIT 2,A + + case /*CB*/0x58: BIT(3,_B); break; // BIT 3,B + case /*CB*/0x59: BIT(3,_C); break; // BIT 3,C + case /*CB*/0x5a: BIT(3,_D); break; // BIT 3,D + case /*CB*/0x5b: BIT(3,_E); break; // BIT 3,E + case /*CB*/0x5c: BIT(3,_H); break; // BIT 3,H + case /*CB*/0x5d: BIT(3,_L); break; // BIT 3,L + case /*CB*/0x5e: BIT(3,RM(_HL)); break; // BIT 3,(HL) + case /*CB*/0x5f: BIT(3,_A); break; // BIT 3,A + + case /*CB*/0x60: BIT(4,_B); break; // BIT 4,B + case /*CB*/0x61: BIT(4,_C); break; // BIT 4,C + case /*CB*/0x62: BIT(4,_D); break; // BIT 4,D + case /*CB*/0x63: BIT(4,_E); break; // BIT 4,E + case /*CB*/0x64: BIT(4,_H); break; // BIT 4,H + case /*CB*/0x65: BIT(4,_L); break; // BIT 4,L + case /*CB*/0x66: BIT(4,RM(_HL)); break; // BIT 4,(HL) + case /*CB*/0x67: BIT(4,_A); break; // BIT 4,A + + case /*CB*/0x68: BIT(5,_B); break; // BIT 5,B + case /*CB*/0x69: BIT(5,_C); break; // BIT 5,C + case /*CB*/0x6a: BIT(5,_D); break; // BIT 5,D + case /*CB*/0x6b: BIT(5,_E); break; // BIT 5,E + case /*CB*/0x6c: BIT(5,_H); break; // BIT 5,H + case /*CB*/0x6d: BIT(5,_L); break; // BIT 5,L + case /*CB*/0x6e: BIT(5,RM(_HL)); break; // BIT 5,(HL) + case /*CB*/0x6f: BIT(5,_A); break; // BIT 5,A + + case /*CB*/0x70: BIT(6,_B); break; // BIT 6,B + case /*CB*/0x71: BIT(6,_C); break; // BIT 6,C + case /*CB*/0x72: BIT(6,_D); break; // BIT 6,D + case /*CB*/0x73: BIT(6,_E); break; // BIT 6,E + case /*CB*/0x74: BIT(6,_H); break; // BIT 6,H + case /*CB*/0x75: BIT(6,_L); break; // BIT 6,L + case /*CB*/0x76: BIT(6,RM(_HL)); break; // BIT 6,(HL) + case /*CB*/0x77: BIT(6,_A); break; // BIT 6,A + + case /*CB*/0x78: BIT(7,_B); break; // BIT 7,B + case /*CB*/0x79: BIT(7,_C); break; // BIT 7,C + case /*CB*/0x7a: BIT(7,_D); break; // BIT 7,D + case /*CB*/0x7b: BIT(7,_E); break; // BIT 7,E + case /*CB*/0x7c: BIT(7,_H); break; // BIT 7,H + case /*CB*/0x7d: BIT(7,_L); break; // BIT 7,L + case /*CB*/0x7e: BIT(7,RM(_HL)); break; // BIT 7,(HL) + case /*CB*/0x7f: BIT(7,_A); break; // BIT 7,A + + case /*CB*/0x80: _B = RES(0,_B); break; // RES 0,B + case /*CB*/0x81: _C = RES(0,_C); break; // RES 0,C + case /*CB*/0x82: _D = RES(0,_D); break; // RES 0,D + case /*CB*/0x83: _E = RES(0,_E); break; // RES 0,E + case /*CB*/0x84: _H = RES(0,_H); break; // RES 0,H + case /*CB*/0x85: _L = RES(0,_L); break; // RES 0,L + case /*CB*/0x86: WM( _HL, RES(0,RM(_HL)) ); break; // RES 0,(HL) + case /*CB*/0x87: _A = RES(0,_A); break; // RES 0,A + + case /*CB*/0x88: _B = RES(1,_B); break; // RES 1,B + case /*CB*/0x89: _C = RES(1,_C); break; // RES 1,C + case /*CB*/0x8a: _D = RES(1,_D); break; // RES 1,D + case /*CB*/0x8b: _E = RES(1,_E); break; // RES 1,E + case /*CB*/0x8c: _H = RES(1,_H); break; // RES 1,H + case /*CB*/0x8d: _L = RES(1,_L); break; // RES 1,L + case /*CB*/0x8e: WM( _HL, RES(1,RM(_HL)) ); break; // RES 1,(HL) + case /*CB*/0x8f: _A = RES(1,_A); break; // RES 1,A + + case /*CB*/0x90: _B = RES(2,_B); break; // RES 2,B + case /*CB*/0x91: _C = RES(2,_C); break; // RES 2,C + case /*CB*/0x92: _D = RES(2,_D); break; // RES 2,D + case /*CB*/0x93: _E = RES(2,_E); break; // RES 2,E + case /*CB*/0x94: _H = RES(2,_H); break; // RES 2,H + case /*CB*/0x95: _L = RES(2,_L); break; // RES 2,L + case /*CB*/0x96: WM( _HL, RES(2,RM(_HL)) ); break; // RES 2,(HL) + case /*CB*/0x97: _A = RES(2,_A); break; // RES 2,A + + case /*CB*/0x98: _B = RES(3,_B); break; // RES 3,B + case /*CB*/0x99: _C = RES(3,_C); break; // RES 3,C + case /*CB*/0x9a: _D = RES(3,_D); break; // RES 3,D + case /*CB*/0x9b: _E = RES(3,_E); break; // RES 3,E + case /*CB*/0x9c: _H = RES(3,_H); break; // RES 3,H + case /*CB*/0x9d: _L = RES(3,_L); break; // RES 3,L + case /*CB*/0x9e: WM( _HL, RES(3,RM(_HL)) ); break; // RES 3,(HL) + case /*CB*/0x9f: _A = RES(3,_A); break; // RES 3,A + + case /*CB*/0xa0: _B = RES(4,_B); break; // RES 4,B + case /*CB*/0xa1: _C = RES(4,_C); break; // RES 4,C + case /*CB*/0xa2: _D = RES(4,_D); break; // RES 4,D + case /*CB*/0xa3: _E = RES(4,_E); break; // RES 4,E + case /*CB*/0xa4: _H = RES(4,_H); break; // RES 4,H + case /*CB*/0xa5: _L = RES(4,_L); break; // RES 4,L + case /*CB*/0xa6: WM( _HL, RES(4,RM(_HL)) ); break; // RES 4,(HL) + case /*CB*/0xa7: _A = RES(4,_A); break; // RES 4,A + + case /*CB*/0xa8: _B = RES(5,_B); break; // RES 5,B + case /*CB*/0xa9: _C = RES(5,_C); break; // RES 5,C + case /*CB*/0xaa: _D = RES(5,_D); break; // RES 5,D + case /*CB*/0xab: _E = RES(5,_E); break; // RES 5,E + case /*CB*/0xac: _H = RES(5,_H); break; // RES 5,H + case /*CB*/0xad: _L = RES(5,_L); break; // RES 5,L + case /*CB*/0xae: WM( _HL, RES(5,RM(_HL)) ); break; // RES 5,(HL) + case /*CB*/0xaf: _A = RES(5,_A); break; // RES 5,A + + case /*CB*/0xb0: _B = RES(6,_B); break; // RES 6,B + case /*CB*/0xb1: _C = RES(6,_C); break; // RES 6,C + case /*CB*/0xb2: _D = RES(6,_D); break; // RES 6,D + case /*CB*/0xb3: _E = RES(6,_E); break; // RES 6,E + case /*CB*/0xb4: _H = RES(6,_H); break; // RES 6,H + case /*CB*/0xb5: _L = RES(6,_L); break; // RES 6,L + case /*CB*/0xb6: WM( _HL, RES(6,RM(_HL)) ); break; // RES 6,(HL) + case /*CB*/0xb7: _A = RES(6,_A); break; // RES 6,A + + case /*CB*/0xb8: _B = RES(7,_B); break; // RES 7,B + case /*CB*/0xb9: _C = RES(7,_C); break; // RES 7,C + case /*CB*/0xba: _D = RES(7,_D); break; // RES 7,D + case /*CB*/0xbb: _E = RES(7,_E); break; // RES 7,E + case /*CB*/0xbc: _H = RES(7,_H); break; // RES 7,H + case /*CB*/0xbd: _L = RES(7,_L); break; // RES 7,L + case /*CB*/0xbe: WM( _HL, RES(7,RM(_HL)) ); break; // RES 7,(HL) + case /*CB*/0xbf: _A = RES(7,_A); break; // RES 7,A + + case /*CB*/0xc0: _B = SET(0,_B); break; // SET 0,B + case /*CB*/0xc1: _C = SET(0,_C); break; // SET 0,C + case /*CB*/0xc2: _D = SET(0,_D); break; // SET 0,D + case /*CB*/0xc3: _E = SET(0,_E); break; // SET 0,E + case /*CB*/0xc4: _H = SET(0,_H); break; // SET 0,H + case /*CB*/0xc5: _L = SET(0,_L); break; // SET 0,L + case /*CB*/0xc6: WM( _HL, SET(0,RM(_HL)) ); break; // SET 0,(HL) + case /*CB*/0xc7: _A = SET(0,_A); break; // SET 0,A + + case /*CB*/0xc8: _B = SET(1,_B); break; // SET 1,B + case /*CB*/0xc9: _C = SET(1,_C); break; // SET 1,C + case /*CB*/0xca: _D = SET(1,_D); break; // SET 1,D + case /*CB*/0xcb: _E = SET(1,_E); break; // SET 1,E + case /*CB*/0xcc: _H = SET(1,_H); break; // SET 1,H + case /*CB*/0xcd: _L = SET(1,_L); break; // SET 1,L + case /*CB*/0xce: WM( _HL, SET(1,RM(_HL)) ); break; // SET 1,(HL) + case /*CB*/0xcf: _A = SET(1,_A); break; // SET 1,A + + case /*CB*/0xd0: _B = SET(2,_B); break; // SET 2,B + case /*CB*/0xd1: _C = SET(2,_C); break; // SET 2,C + case /*CB*/0xd2: _D = SET(2,_D); break; // SET 2,D + case /*CB*/0xd3: _E = SET(2,_E); break; // SET 2,E + case /*CB*/0xd4: _H = SET(2,_H); break; // SET 2,H + case /*CB*/0xd5: _L = SET(2,_L); break; // SET 2,L + case /*CB*/0xd6: WM( _HL, SET(2,RM(_HL)) ); break; // SET 2,(HL) + case /*CB*/0xd7: _A = SET(2,_A); break; // SET 2,A + + case /*CB*/0xd8: _B = SET(3,_B); break; // SET 3,B + case /*CB*/0xd9: _C = SET(3,_C); break; // SET 3,C + case /*CB*/0xda: _D = SET(3,_D); break; // SET 3,D + case /*CB*/0xdb: _E = SET(3,_E); break; // SET 3,E + case /*CB*/0xdc: _H = SET(3,_H); break; // SET 3,H + case /*CB*/0xdd: _L = SET(3,_L); break; // SET 3,L + case /*CB*/0xde: WM( _HL, SET(3,RM(_HL)) ); break; // SET 3,(HL) + case /*CB*/0xdf: _A = SET(3,_A); break; // SET 3,A + + case /*CB*/0xe0: _B = SET(4,_B); break; // SET 4,B + case /*CB*/0xe1: _C = SET(4,_C); break; // SET 4,C + case /*CB*/0xe2: _D = SET(4,_D); break; // SET 4,D + case /*CB*/0xe3: _E = SET(4,_E); break; // SET 4,E + case /*CB*/0xe4: _H = SET(4,_H); break; // SET 4,H + case /*CB*/0xe5: _L = SET(4,_L); break; // SET 4,L + case /*CB*/0xe6: WM( _HL, SET(4,RM(_HL)) ); break; // SET 4,(HL) + case /*CB*/0xe7: _A = SET(4,_A); break; // SET 4,A + + case /*CB*/0xe8: _B = SET(5,_B); break; // SET 5,B + case /*CB*/0xe9: _C = SET(5,_C); break; // SET 5,C + case /*CB*/0xea: _D = SET(5,_D); break; // SET 5,D + case /*CB*/0xeb: _E = SET(5,_E); break; // SET 5,E + case /*CB*/0xec: _H = SET(5,_H); break; // SET 5,H + case /*CB*/0xed: _L = SET(5,_L); break; // SET 5,L + case /*CB*/0xee: WM( _HL, SET(5,RM(_HL)) ); break; // SET 5,(HL) + case /*CB*/0xef: _A = SET(5,_A); break; // SET 5,A + + case /*CB*/0xf0: _B = SET(6,_B); break; // SET 6,B + case /*CB*/0xf1: _C = SET(6,_C); break; // SET 6,C + case /*CB*/0xf2: _D = SET(6,_D); break; // SET 6,D + case /*CB*/0xf3: _E = SET(6,_E); break; // SET 6,E + case /*CB*/0xf4: _H = SET(6,_H); break; // SET 6,H + case /*CB*/0xf5: _L = SET(6,_L); break; // SET 6,L + case /*CB*/0xf6: WM( _HL, SET(6,RM(_HL)) ); break; // SET 6,(HL) + case /*CB*/0xf7: _A = SET(6,_A); break; // SET 6,A + + case /*CB*/0xf8: _B = SET(7,_B); break; // SET 7,B + case /*CB*/0xf9: _C = SET(7,_C); break; // SET 7,C + case /*CB*/0xfa: _D = SET(7,_D); break; // SET 7,D + case /*CB*/0xfb: _E = SET(7,_E); break; // SET 7,E + case /*CB*/0xfc: _H = SET(7,_H); break; // SET 7,H + case /*CB*/0xfd: _L = SET(7,_L); break; // SET 7,L + case /*CB*/0xfe: WM( _HL, SET(7,RM(_HL)) ); break; // SET 7,(HL) + case /*CB*/0xff: _A = SET(7,_A); break; // SET 7,A + } +} + +///////////////////////////////////////////////////////////////////////////// + +static EMU_INLINE void z80_exec_ea_xycb( + struct Z80_STATE *state, uint8 op, uint16 EA +) { + +//printf("PC=%04X exec xycb %02X\n",_PC, op);fflush(stdout); + + switch(op) { + case /*xycb*/0x00: _B = RLC( RM(EA) ); WM( EA,_B ); break; // RLC B=(XY+o) + case /*xycb*/0x01: _C = RLC( RM(EA) ); WM( EA,_C ); break; // RLC C=(XY+o) + case /*xycb*/0x02: _D = RLC( RM(EA) ); WM( EA,_D ); break; // RLC D=(XY+o) + case /*xycb*/0x03: _E = RLC( RM(EA) ); WM( EA,_E ); break; // RLC E=(XY+o) + case /*xycb*/0x04: _H = RLC( RM(EA) ); WM( EA,_H ); break; // RLC H=(XY+o) + case /*xycb*/0x05: _L = RLC( RM(EA) ); WM( EA,_L ); break; // RLC L=(XY+o) + case /*xycb*/0x06: WM( EA, RLC( RM(EA) ) ); break; // RLC (XY+o) + case /*xycb*/0x07: _A = RLC( RM(EA) ); WM( EA,_A ); break; // RLC A=(XY+o) + + case /*xycb*/0x08: _B = RRC( RM(EA) ); WM( EA,_B ); break; // RRC B=(XY+o) + case /*xycb*/0x09: _C = RRC( RM(EA) ); WM( EA,_C ); break; // RRC C=(XY+o) + case /*xycb*/0x0a: _D = RRC( RM(EA) ); WM( EA,_D ); break; // RRC D=(XY+o) + case /*xycb*/0x0b: _E = RRC( RM(EA) ); WM( EA,_E ); break; // RRC E=(XY+o) + case /*xycb*/0x0c: _H = RRC( RM(EA) ); WM( EA,_H ); break; // RRC H=(XY+o) + case /*xycb*/0x0d: _L = RRC( RM(EA) ); WM( EA,_L ); break; // RRC L=(XY+o) + case /*xycb*/0x0e: WM( EA,RRC( RM(EA) ) ); break; // RRC (XY+o) + case /*xycb*/0x0f: _A = RRC( RM(EA) ); WM( EA,_A ); break; // RRC A=(XY+o) + + case /*xycb*/0x10: _B = RL( RM(EA) ); WM( EA,_B ); break; // RL B=(XY+o) + case /*xycb*/0x11: _C = RL( RM(EA) ); WM( EA,_C ); break; // RL C=(XY+o) + case /*xycb*/0x12: _D = RL( RM(EA) ); WM( EA,_D ); break; // RL D=(XY+o) + case /*xycb*/0x13: _E = RL( RM(EA) ); WM( EA,_E ); break; // RL E=(XY+o) + case /*xycb*/0x14: _H = RL( RM(EA) ); WM( EA,_H ); break; // RL H=(XY+o) + case /*xycb*/0x15: _L = RL( RM(EA) ); WM( EA,_L ); break; // RL L=(XY+o) + case /*xycb*/0x16: WM( EA,RL( RM(EA) ) ); break; // RL (XY+o) + case /*xycb*/0x17: _A = RL( RM(EA) ); WM( EA,_A ); break; // RL A=(XY+o) + + case /*xycb*/0x18: _B = RR( RM(EA) ); WM( EA,_B ); break; // RR B=(XY+o) + case /*xycb*/0x19: _C = RR( RM(EA) ); WM( EA,_C ); break; // RR C=(XY+o) + case /*xycb*/0x1a: _D = RR( RM(EA) ); WM( EA,_D ); break; // RR D=(XY+o) + case /*xycb*/0x1b: _E = RR( RM(EA) ); WM( EA,_E ); break; // RR E=(XY+o) + case /*xycb*/0x1c: _H = RR( RM(EA) ); WM( EA,_H ); break; // RR H=(XY+o) + case /*xycb*/0x1d: _L = RR( RM(EA) ); WM( EA,_L ); break; // RR L=(XY+o) + case /*xycb*/0x1e: WM( EA,RR( RM(EA) ) ); break; // RR (XY+o) + case /*xycb*/0x1f: _A = RR( RM(EA) ); WM( EA,_A ); break; // RR A=(XY+o) + + case /*xycb*/0x20: _B = SLA( RM(EA) ); WM( EA,_B ); break; // SLA B=(XY+o) + case /*xycb*/0x21: _C = SLA( RM(EA) ); WM( EA,_C ); break; // SLA C=(XY+o) + case /*xycb*/0x22: _D = SLA( RM(EA) ); WM( EA,_D ); break; // SLA D=(XY+o) + case /*xycb*/0x23: _E = SLA( RM(EA) ); WM( EA,_E ); break; // SLA E=(XY+o) + case /*xycb*/0x24: _H = SLA( RM(EA) ); WM( EA,_H ); break; // SLA H=(XY+o) + case /*xycb*/0x25: _L = SLA( RM(EA) ); WM( EA,_L ); break; // SLA L=(XY+o) + case /*xycb*/0x26: WM( EA,SLA( RM(EA) ) ); break; // SLA (XY+o) + case /*xycb*/0x27: _A = SLA( RM(EA) ); WM( EA,_A ); break; // SLA A=(XY+o) + + case /*xycb*/0x28: _B = SRA( RM(EA) ); WM( EA,_B ); break; // SRA B=(XY+o) + case /*xycb*/0x29: _C = SRA( RM(EA) ); WM( EA,_C ); break; // SRA C=(XY+o) + case /*xycb*/0x2a: _D = SRA( RM(EA) ); WM( EA,_D ); break; // SRA D=(XY+o) + case /*xycb*/0x2b: _E = SRA( RM(EA) ); WM( EA,_E ); break; // SRA E=(XY+o) + case /*xycb*/0x2c: _H = SRA( RM(EA) ); WM( EA,_H ); break; // SRA H=(XY+o) + case /*xycb*/0x2d: _L = SRA( RM(EA) ); WM( EA,_L ); break; // SRA L=(XY+o) + case /*xycb*/0x2e: WM( EA,SRA( RM(EA) ) ); break; // SRA (XY+o) + case /*xycb*/0x2f: _A = SRA( RM(EA) ); WM( EA,_A ); break; // SRA A=(XY+o) + + case /*xycb*/0x30: _B = SLL( RM(EA) ); WM( EA,_B ); break; // SLL B=(XY+o) + case /*xycb*/0x31: _C = SLL( RM(EA) ); WM( EA,_C ); break; // SLL C=(XY+o) + case /*xycb*/0x32: _D = SLL( RM(EA) ); WM( EA,_D ); break; // SLL D=(XY+o) + case /*xycb*/0x33: _E = SLL( RM(EA) ); WM( EA,_E ); break; // SLL E=(XY+o) + case /*xycb*/0x34: _H = SLL( RM(EA) ); WM( EA,_H ); break; // SLL H=(XY+o) + case /*xycb*/0x35: _L = SLL( RM(EA) ); WM( EA,_L ); break; // SLL L=(XY+o) + case /*xycb*/0x36: WM( EA,SLL( RM(EA) ) ); break; // SLL (XY+o) + case /*xycb*/0x37: _A = SLL( RM(EA) ); WM( EA,_A ); break; // SLL A=(XY+o) + + case /*xycb*/0x38: _B = SRL( RM(EA) ); WM( EA,_B ); break; // SRL B=(XY+o) + case /*xycb*/0x39: _C = SRL( RM(EA) ); WM( EA,_C ); break; // SRL C=(XY+o) + case /*xycb*/0x3a: _D = SRL( RM(EA) ); WM( EA,_D ); break; // SRL D=(XY+o) + case /*xycb*/0x3b: _E = SRL( RM(EA) ); WM( EA,_E ); break; // SRL E=(XY+o) + case /*xycb*/0x3c: _H = SRL( RM(EA) ); WM( EA,_H ); break; // SRL H=(XY+o) + case /*xycb*/0x3d: _L = SRL( RM(EA) ); WM( EA,_L ); break; // SRL L=(XY+o) + case /*xycb*/0x3e: WM( EA,SRL( RM(EA) ) ); break; // SRL (XY+o) + case /*xycb*/0x3f: _A = SRL( RM(EA) ); WM( EA,_A ); break; // SRL A=(XY+o) + + case /*xycb*/0x40: BIT_XY(0,RM(EA)); break; // BIT 0,B=(XY+o) + case /*xycb*/0x41: BIT_XY(0,RM(EA)); break; // BIT 0,C=(XY+o) + case /*xycb*/0x42: BIT_XY(0,RM(EA)); break; // BIT 0,D=(XY+o) + case /*xycb*/0x43: BIT_XY(0,RM(EA)); break; // BIT 0,E=(XY+o) + case /*xycb*/0x44: BIT_XY(0,RM(EA)); break; // BIT 0,H=(XY+o) + case /*xycb*/0x45: BIT_XY(0,RM(EA)); break; // BIT 0,L=(XY+o) + case /*xycb*/0x46: BIT_XY(0,RM(EA)); break; // BIT 0,(XY+o) + case /*xycb*/0x47: BIT_XY(0,RM(EA)); break; // BIT 0,A=(XY+o) + + case /*xycb*/0x48: BIT_XY(1,RM(EA)); break; // BIT 1,B=(XY+o) + case /*xycb*/0x49: BIT_XY(1,RM(EA)); break; // BIT 1,C=(XY+o) + case /*xycb*/0x4a: BIT_XY(1,RM(EA)); break; // BIT 1,D=(XY+o) + case /*xycb*/0x4b: BIT_XY(1,RM(EA)); break; // BIT 1,E=(XY+o) + case /*xycb*/0x4c: BIT_XY(1,RM(EA)); break; // BIT 1,H=(XY+o) + case /*xycb*/0x4d: BIT_XY(1,RM(EA)); break; // BIT 1,L=(XY+o) + case /*xycb*/0x4e: BIT_XY(1,RM(EA)); break; // BIT 1,(XY+o) + case /*xycb*/0x4f: BIT_XY(1,RM(EA)); break; // BIT 1,A=(XY+o) + + case /*xycb*/0x50: BIT_XY(2,RM(EA)); break; // BIT 2,B=(XY+o) + case /*xycb*/0x51: BIT_XY(2,RM(EA)); break; // BIT 2,C=(XY+o) + case /*xycb*/0x52: BIT_XY(2,RM(EA)); break; // BIT 2,D=(XY+o) + case /*xycb*/0x53: BIT_XY(2,RM(EA)); break; // BIT 2,E=(XY+o) + case /*xycb*/0x54: BIT_XY(2,RM(EA)); break; // BIT 2,H=(XY+o) + case /*xycb*/0x55: BIT_XY(2,RM(EA)); break; // BIT 2,L=(XY+o) + case /*xycb*/0x56: BIT_XY(2,RM(EA)); break; // BIT 2,(XY+o) + case /*xycb*/0x57: BIT_XY(2,RM(EA)); break; // BIT 2,A=(XY+o) + + case /*xycb*/0x58: BIT_XY(3,RM(EA)); break; // BIT 3,B=(XY+o) + case /*xycb*/0x59: BIT_XY(3,RM(EA)); break; // BIT 3,C=(XY+o) + case /*xycb*/0x5a: BIT_XY(3,RM(EA)); break; // BIT 3,D=(XY+o) + case /*xycb*/0x5b: BIT_XY(3,RM(EA)); break; // BIT 3,E=(XY+o) + case /*xycb*/0x5c: BIT_XY(3,RM(EA)); break; // BIT 3,H=(XY+o) + case /*xycb*/0x5d: BIT_XY(3,RM(EA)); break; // BIT 3,L=(XY+o) + case /*xycb*/0x5e: BIT_XY(3,RM(EA)); break; // BIT 3,(XY+o) + case /*xycb*/0x5f: BIT_XY(3,RM(EA)); break; // BIT 3,A=(XY+o) + + case /*xycb*/0x60: BIT_XY(4,RM(EA)); break; // BIT 4,B=(XY+o) + case /*xycb*/0x61: BIT_XY(4,RM(EA)); break; // BIT 4,C=(XY+o) + case /*xycb*/0x62: BIT_XY(4,RM(EA)); break; // BIT 4,D=(XY+o) + case /*xycb*/0x63: BIT_XY(4,RM(EA)); break; // BIT 4,E=(XY+o) + case /*xycb*/0x64: BIT_XY(4,RM(EA)); break; // BIT 4,H=(XY+o) + case /*xycb*/0x65: BIT_XY(4,RM(EA)); break; // BIT 4,L=(XY+o) + case /*xycb*/0x66: BIT_XY(4,RM(EA)); break; // BIT 4,(XY+o) + case /*xycb*/0x67: BIT_XY(4,RM(EA)); break; // BIT 4,A=(XY+o) + + case /*xycb*/0x68: BIT_XY(5,RM(EA)); break; // BIT 5,B=(XY+o) + case /*xycb*/0x69: BIT_XY(5,RM(EA)); break; // BIT 5,C=(XY+o) + case /*xycb*/0x6a: BIT_XY(5,RM(EA)); break; // BIT 5,D=(XY+o) + case /*xycb*/0x6b: BIT_XY(5,RM(EA)); break; // BIT 5,E=(XY+o) + case /*xycb*/0x6c: BIT_XY(5,RM(EA)); break; // BIT 5,H=(XY+o) + case /*xycb*/0x6d: BIT_XY(5,RM(EA)); break; // BIT 5,L=(XY+o) + case /*xycb*/0x6e: BIT_XY(5,RM(EA)); break; // BIT 5,(XY+o) + case /*xycb*/0x6f: BIT_XY(5,RM(EA)); break; // BIT 5,A=(XY+o) + + case /*xycb*/0x70: BIT_XY(6,RM(EA)); break; // BIT 6,B=(XY+o) + case /*xycb*/0x71: BIT_XY(6,RM(EA)); break; // BIT 6,C=(XY+o) + case /*xycb*/0x72: BIT_XY(6,RM(EA)); break; // BIT 6,D=(XY+o) + case /*xycb*/0x73: BIT_XY(6,RM(EA)); break; // BIT 6,E=(XY+o) + case /*xycb*/0x74: BIT_XY(6,RM(EA)); break; // BIT 6,H=(XY+o) + case /*xycb*/0x75: BIT_XY(6,RM(EA)); break; // BIT 6,L=(XY+o) + case /*xycb*/0x76: BIT_XY(6,RM(EA)); break; // BIT 6,(XY+o) + case /*xycb*/0x77: BIT_XY(6,RM(EA)); break; // BIT 6,A=(XY+o) + + case /*xycb*/0x78: BIT_XY(7,RM(EA)); break; // BIT 7,B=(XY+o) + case /*xycb*/0x79: BIT_XY(7,RM(EA)); break; // BIT 7,C=(XY+o) + case /*xycb*/0x7a: BIT_XY(7,RM(EA)); break; // BIT 7,D=(XY+o) + case /*xycb*/0x7b: BIT_XY(7,RM(EA)); break; // BIT 7,E=(XY+o) + case /*xycb*/0x7c: BIT_XY(7,RM(EA)); break; // BIT 7,H=(XY+o) + case /*xycb*/0x7d: BIT_XY(7,RM(EA)); break; // BIT 7,L=(XY+o) + case /*xycb*/0x7e: BIT_XY(7,RM(EA)); break; // BIT 7,(XY+o) + case /*xycb*/0x7f: BIT_XY(7,RM(EA)); break; // BIT 7,A=(XY+o) + + case /*xycb*/0x80: _B = RES(0, RM(EA) ); WM( EA,_B ); break; // RES 0,B=(XY+o) + case /*xycb*/0x81: _C = RES(0, RM(EA) ); WM( EA,_C ); break; // RES 0,C=(XY+o) + case /*xycb*/0x82: _D = RES(0, RM(EA) ); WM( EA,_D ); break; // RES 0,D=(XY+o) + case /*xycb*/0x83: _E = RES(0, RM(EA) ); WM( EA,_E ); break; // RES 0,E=(XY+o) + case /*xycb*/0x84: _H = RES(0, RM(EA) ); WM( EA,_H ); break; // RES 0,H=(XY+o) + case /*xycb*/0x85: _L = RES(0, RM(EA) ); WM( EA,_L ); break; // RES 0,L=(XY+o) + case /*xycb*/0x86: WM( EA, RES(0,RM(EA)) ); break; // RES 0,(XY+o) + case /*xycb*/0x87: _A = RES(0, RM(EA) ); WM( EA,_A ); break; // RES 0,A=(XY+o) + + case /*xycb*/0x88: _B = RES(1, RM(EA) ); WM( EA,_B ); break; // RES 1,B=(XY+o) + case /*xycb*/0x89: _C = RES(1, RM(EA) ); WM( EA,_C ); break; // RES 1,C=(XY+o) + case /*xycb*/0x8a: _D = RES(1, RM(EA) ); WM( EA,_D ); break; // RES 1,D=(XY+o) + case /*xycb*/0x8b: _E = RES(1, RM(EA) ); WM( EA,_E ); break; // RES 1,E=(XY+o) + case /*xycb*/0x8c: _H = RES(1, RM(EA) ); WM( EA,_H ); break; // RES 1,H=(XY+o) + case /*xycb*/0x8d: _L = RES(1, RM(EA) ); WM( EA,_L ); break; // RES 1,L=(XY+o) + case /*xycb*/0x8e: WM( EA, RES(1,RM(EA)) ); break; // RES 1,(XY+o) + case /*xycb*/0x8f: _A = RES(1, RM(EA) ); WM( EA,_A ); break; // RES 1,A=(XY+o) + + case /*xycb*/0x90: _B = RES(2, RM(EA) ); WM( EA,_B ); break; // RES 2,B=(XY+o) + case /*xycb*/0x91: _C = RES(2, RM(EA) ); WM( EA,_C ); break; // RES 2,C=(XY+o) + case /*xycb*/0x92: _D = RES(2, RM(EA) ); WM( EA,_D ); break; // RES 2,D=(XY+o) + case /*xycb*/0x93: _E = RES(2, RM(EA) ); WM( EA,_E ); break; // RES 2,E=(XY+o) + case /*xycb*/0x94: _H = RES(2, RM(EA) ); WM( EA,_H ); break; // RES 2,H=(XY+o) + case /*xycb*/0x95: _L = RES(2, RM(EA) ); WM( EA,_L ); break; // RES 2,L=(XY+o) + case /*xycb*/0x96: WM( EA, RES(2,RM(EA)) ); break; // RES 2,(XY+o) + case /*xycb*/0x97: _A = RES(2, RM(EA) ); WM( EA,_A ); break; // RES 2,A=(XY+o) + + case /*xycb*/0x98: _B = RES(3, RM(EA) ); WM( EA,_B ); break; // RES 3,B=(XY+o) + case /*xycb*/0x99: _C = RES(3, RM(EA) ); WM( EA,_C ); break; // RES 3,C=(XY+o) + case /*xycb*/0x9a: _D = RES(3, RM(EA) ); WM( EA,_D ); break; // RES 3,D=(XY+o) + case /*xycb*/0x9b: _E = RES(3, RM(EA) ); WM( EA,_E ); break; // RES 3,E=(XY+o) + case /*xycb*/0x9c: _H = RES(3, RM(EA) ); WM( EA,_H ); break; // RES 3,H=(XY+o) + case /*xycb*/0x9d: _L = RES(3, RM(EA) ); WM( EA,_L ); break; // RES 3,L=(XY+o) + case /*xycb*/0x9e: WM( EA, RES(3,RM(EA)) ); break; // RES 3,(XY+o) + case /*xycb*/0x9f: _A = RES(3, RM(EA) ); WM( EA,_A ); break; // RES 3,A=(XY+o) + + case /*xycb*/0xa0: _B = RES(4, RM(EA) ); WM( EA,_B ); break; // RES 4,B=(XY+o) + case /*xycb*/0xa1: _C = RES(4, RM(EA) ); WM( EA,_C ); break; // RES 4,C=(XY+o) + case /*xycb*/0xa2: _D = RES(4, RM(EA) ); WM( EA,_D ); break; // RES 4,D=(XY+o) + case /*xycb*/0xa3: _E = RES(4, RM(EA) ); WM( EA,_E ); break; // RES 4,E=(XY+o) + case /*xycb*/0xa4: _H = RES(4, RM(EA) ); WM( EA,_H ); break; // RES 4,H=(XY+o) + case /*xycb*/0xa5: _L = RES(4, RM(EA) ); WM( EA,_L ); break; // RES 4,L=(XY+o) + case /*xycb*/0xa6: WM( EA, RES(4,RM(EA)) ); break; // RES 4,(XY+o) + case /*xycb*/0xa7: _A = RES(4, RM(EA) ); WM( EA,_A ); break; // RES 4,A=(XY+o) + + case /*xycb*/0xa8: _B = RES(5, RM(EA) ); WM( EA,_B ); break; // RES 5,B=(XY+o) + case /*xycb*/0xa9: _C = RES(5, RM(EA) ); WM( EA,_C ); break; // RES 5,C=(XY+o) + case /*xycb*/0xaa: _D = RES(5, RM(EA) ); WM( EA,_D ); break; // RES 5,D=(XY+o) + case /*xycb*/0xab: _E = RES(5, RM(EA) ); WM( EA,_E ); break; // RES 5,E=(XY+o) + case /*xycb*/0xac: _H = RES(5, RM(EA) ); WM( EA,_H ); break; // RES 5,H=(XY+o) + case /*xycb*/0xad: _L = RES(5, RM(EA) ); WM( EA,_L ); break; // RES 5,L=(XY+o) + case /*xycb*/0xae: WM( EA, RES(5,RM(EA)) ); break; // RES 5,(XY+o) + case /*xycb*/0xaf: _A = RES(5, RM(EA) ); WM( EA,_A ); break; // RES 5,A=(XY+o) + + case /*xycb*/0xb0: _B = RES(6, RM(EA) ); WM( EA,_B ); break; // RES 6,B=(XY+o) + case /*xycb*/0xb1: _C = RES(6, RM(EA) ); WM( EA,_C ); break; // RES 6,C=(XY+o) + case /*xycb*/0xb2: _D = RES(6, RM(EA) ); WM( EA,_D ); break; // RES 6,D=(XY+o) + case /*xycb*/0xb3: _E = RES(6, RM(EA) ); WM( EA,_E ); break; // RES 6,E=(XY+o) + case /*xycb*/0xb4: _H = RES(6, RM(EA) ); WM( EA,_H ); break; // RES 6,H=(XY+o) + case /*xycb*/0xb5: _L = RES(6, RM(EA) ); WM( EA,_L ); break; // RES 6,L=(XY+o) + case /*xycb*/0xb6: WM( EA, RES(6,RM(EA)) ); break; // RES 6,(XY+o) + case /*xycb*/0xb7: _A = RES(6, RM(EA) ); WM( EA,_A ); break; // RES 6,A=(XY+o) + + case /*xycb*/0xb8: _B = RES(7, RM(EA) ); WM( EA,_B ); break; // RES 7,B=(XY+o) + case /*xycb*/0xb9: _C = RES(7, RM(EA) ); WM( EA,_C ); break; // RES 7,C=(XY+o) + case /*xycb*/0xba: _D = RES(7, RM(EA) ); WM( EA,_D ); break; // RES 7,D=(XY+o) + case /*xycb*/0xbb: _E = RES(7, RM(EA) ); WM( EA,_E ); break; // RES 7,E=(XY+o) + case /*xycb*/0xbc: _H = RES(7, RM(EA) ); WM( EA,_H ); break; // RES 7,H=(XY+o) + case /*xycb*/0xbd: _L = RES(7, RM(EA) ); WM( EA,_L ); break; // RES 7,L=(XY+o) + case /*xycb*/0xbe: WM( EA, RES(7,RM(EA)) ); break; // RES 7,(XY+o) + case /*xycb*/0xbf: _A = RES(7, RM(EA) ); WM( EA,_A ); break; // RES 7,A=(XY+o) + + case /*xycb*/0xc0: _B = SET(0, RM(EA) ); WM( EA,_B ); break; // SET 0,B=(XY+o) + case /*xycb*/0xc1: _C = SET(0, RM(EA) ); WM( EA,_C ); break; // SET 0,C=(XY+o) + case /*xycb*/0xc2: _D = SET(0, RM(EA) ); WM( EA,_D ); break; // SET 0,D=(XY+o) + case /*xycb*/0xc3: _E = SET(0, RM(EA) ); WM( EA,_E ); break; // SET 0,E=(XY+o) + case /*xycb*/0xc4: _H = SET(0, RM(EA) ); WM( EA,_H ); break; // SET 0,H=(XY+o) + case /*xycb*/0xc5: _L = SET(0, RM(EA) ); WM( EA,_L ); break; // SET 0,L=(XY+o) + case /*xycb*/0xc6: WM( EA, SET(0,RM(EA)) ); break; // SET 0,(XY+o) + case /*xycb*/0xc7: _A = SET(0, RM(EA) ); WM( EA,_A ); break; // SET 0,A=(XY+o) + + case /*xycb*/0xc8: _B = SET(1, RM(EA) ); WM( EA,_B ); break; // SET 1,B=(XY+o) + case /*xycb*/0xc9: _C = SET(1, RM(EA) ); WM( EA,_C ); break; // SET 1,C=(XY+o) + case /*xycb*/0xca: _D = SET(1, RM(EA) ); WM( EA,_D ); break; // SET 1,D=(XY+o) + case /*xycb*/0xcb: _E = SET(1, RM(EA) ); WM( EA,_E ); break; // SET 1,E=(XY+o) + case /*xycb*/0xcc: _H = SET(1, RM(EA) ); WM( EA,_H ); break; // SET 1,H=(XY+o) + case /*xycb*/0xcd: _L = SET(1, RM(EA) ); WM( EA,_L ); break; // SET 1,L=(XY+o) + case /*xycb*/0xce: WM( EA, SET(1,RM(EA)) ); break; // SET 1,(XY+o) + case /*xycb*/0xcf: _A = SET(1, RM(EA) ); WM( EA,_A ); break; // SET 1,A=(XY+o) + + case /*xycb*/0xd0: _B = SET(2, RM(EA) ); WM( EA,_B ); break; // SET 2,B=(XY+o) + case /*xycb*/0xd1: _C = SET(2, RM(EA) ); WM( EA,_C ); break; // SET 2,C=(XY+o) + case /*xycb*/0xd2: _D = SET(2, RM(EA) ); WM( EA,_D ); break; // SET 2,D=(XY+o) + case /*xycb*/0xd3: _E = SET(2, RM(EA) ); WM( EA,_E ); break; // SET 2,E=(XY+o) + case /*xycb*/0xd4: _H = SET(2, RM(EA) ); WM( EA,_H ); break; // SET 2,H=(XY+o) + case /*xycb*/0xd5: _L = SET(2, RM(EA) ); WM( EA,_L ); break; // SET 2,L=(XY+o) + case /*xycb*/0xd6: WM( EA, SET(2,RM(EA)) ); break; // SET 2,(XY+o) + case /*xycb*/0xd7: _A = SET(2, RM(EA) ); WM( EA,_A ); break; // SET 2,A=(XY+o) + + case /*xycb*/0xd8: _B = SET(3, RM(EA) ); WM( EA,_B ); break; // SET 3,B=(XY+o) + case /*xycb*/0xd9: _C = SET(3, RM(EA) ); WM( EA,_C ); break; // SET 3,C=(XY+o) + case /*xycb*/0xda: _D = SET(3, RM(EA) ); WM( EA,_D ); break; // SET 3,D=(XY+o) + case /*xycb*/0xdb: _E = SET(3, RM(EA) ); WM( EA,_E ); break; // SET 3,E=(XY+o) + case /*xycb*/0xdc: _H = SET(3, RM(EA) ); WM( EA,_H ); break; // SET 3,H=(XY+o) + case /*xycb*/0xdd: _L = SET(3, RM(EA) ); WM( EA,_L ); break; // SET 3,L=(XY+o) + case /*xycb*/0xde: WM( EA, SET(3,RM(EA)) ); break; // SET 3,(XY+o) + case /*xycb*/0xdf: _A = SET(3, RM(EA) ); WM( EA,_A ); break; // SET 3,A=(XY+o) + + case /*xycb*/0xe0: _B = SET(4, RM(EA) ); WM( EA,_B ); break; // SET 4,B=(XY+o) + case /*xycb*/0xe1: _C = SET(4, RM(EA) ); WM( EA,_C ); break; // SET 4,C=(XY+o) + case /*xycb*/0xe2: _D = SET(4, RM(EA) ); WM( EA,_D ); break; // SET 4,D=(XY+o) + case /*xycb*/0xe3: _E = SET(4, RM(EA) ); WM( EA,_E ); break; // SET 4,E=(XY+o) + case /*xycb*/0xe4: _H = SET(4, RM(EA) ); WM( EA,_H ); break; // SET 4,H=(XY+o) + case /*xycb*/0xe5: _L = SET(4, RM(EA) ); WM( EA,_L ); break; // SET 4,L=(XY+o) + case /*xycb*/0xe6: WM( EA, SET(4,RM(EA)) ); break; // SET 4,(XY+o) + case /*xycb*/0xe7: _A = SET(4, RM(EA) ); WM( EA,_A ); break; // SET 4,A=(XY+o) + + case /*xycb*/0xe8: _B = SET(5, RM(EA) ); WM( EA,_B ); break; // SET 5,B=(XY+o) + case /*xycb*/0xe9: _C = SET(5, RM(EA) ); WM( EA,_C ); break; // SET 5,C=(XY+o) + case /*xycb*/0xea: _D = SET(5, RM(EA) ); WM( EA,_D ); break; // SET 5,D=(XY+o) + case /*xycb*/0xeb: _E = SET(5, RM(EA) ); WM( EA,_E ); break; // SET 5,E=(XY+o) + case /*xycb*/0xec: _H = SET(5, RM(EA) ); WM( EA,_H ); break; // SET 5,H=(XY+o) + case /*xycb*/0xed: _L = SET(5, RM(EA) ); WM( EA,_L ); break; // SET 5,L=(XY+o) + case /*xycb*/0xee: WM( EA, SET(5,RM(EA)) ); break; // SET 5,(XY+o) + case /*xycb*/0xef: _A = SET(5, RM(EA) ); WM( EA,_A ); break; // SET 5,A=(XY+o) + + case /*xycb*/0xf0: _B = SET(6, RM(EA) ); WM( EA,_B ); break; // SET 6,B=(XY+o) + case /*xycb*/0xf1: _C = SET(6, RM(EA) ); WM( EA,_C ); break; // SET 6,C=(XY+o) + case /*xycb*/0xf2: _D = SET(6, RM(EA) ); WM( EA,_D ); break; // SET 6,D=(XY+o) + case /*xycb*/0xf3: _E = SET(6, RM(EA) ); WM( EA,_E ); break; // SET 6,E=(XY+o) + case /*xycb*/0xf4: _H = SET(6, RM(EA) ); WM( EA,_H ); break; // SET 6,H=(XY+o) + case /*xycb*/0xf5: _L = SET(6, RM(EA) ); WM( EA,_L ); break; // SET 6,L=(XY+o) + case /*xycb*/0xf6: WM( EA, SET(6,RM(EA)) ); break; // SET 6,(XY+o) + case /*xycb*/0xf7: _A = SET(6, RM(EA) ); WM( EA,_A ); break; // SET 6,A=(XY+o) + + case /*xycb*/0xf8: _B = SET(7, RM(EA) ); WM( EA,_B ); break; // SET 7,B=(XY+o) + case /*xycb*/0xf9: _C = SET(7, RM(EA) ); WM( EA,_C ); break; // SET 7,C=(XY+o) + case /*xycb*/0xfa: _D = SET(7, RM(EA) ); WM( EA,_D ); break; // SET 7,D=(XY+o) + case /*xycb*/0xfb: _E = SET(7, RM(EA) ); WM( EA,_E ); break; // SET 7,E=(XY+o) + case /*xycb*/0xfc: _H = SET(7, RM(EA) ); WM( EA,_H ); break; // SET 7,H=(XY+o) + case /*xycb*/0xfd: _L = SET(7, RM(EA) ); WM( EA,_L ); break; // SET 7,L=(XY+o) + case /*xycb*/0xfe: WM( EA, SET(7,RM(EA)) ); break; // SET 7,(XY+o) + case /*xycb*/0xff: _A = SET(7, RM(EA) ); WM( EA,_A ); break; // SET 7,A=(XY+o) + } +} + +///////////////////////////////////////////////////////////////////////////// + +static EMU_INLINE void z80_exec_dd(struct Z80_STATE *state, uint8 op) { + uint16 EA; + +//printf("PC=%04X exec dd %02X\n",_PC, op);fflush(stdout); + + switch(op) { + case /*DD*/0x00: illegal_1(); /*op_00();*/ break; // DB DD + case /*DD*/0x01: illegal_1(); /*op_01();*/ break; // DB DD + case /*DD*/0x02: illegal_1(); /*op_02();*/ break; // DB DD + case /*DD*/0x03: illegal_1(); /*op_03();*/ break; // DB DD + case /*DD*/0x04: illegal_1(); /*op_04();*/ break; // DB DD + case /*DD*/0x05: illegal_1(); /*op_05();*/ break; // DB DD + case /*DD*/0x06: illegal_1(); /*op_06();*/ break; // DB DD + case /*DD*/0x07: illegal_1(); /*op_07();*/ break; // DB DD + + case /*DD*/0x08: illegal_1(); /*op_08();*/ break; // DB DD + case /*DD*/0x09: _R++; ADD16(_IX,_BC); break; // ADD IX,BC + case /*DD*/0x0a: illegal_1(); /*op_0a();*/ break; // DB DD + case /*DD*/0x0b: illegal_1(); /*op_0b();*/ break; // DB DD + case /*DD*/0x0c: illegal_1(); /*op_0c();*/ break; // DB DD + case /*DD*/0x0d: illegal_1(); /*op_0d();*/ break; // DB DD + case /*DD*/0x0e: illegal_1(); /*op_0e();*/ break; // DB DD + case /*DD*/0x0f: illegal_1(); /*op_0f();*/ break; // DB DD + + case /*DD*/0x10: illegal_1(); /*op_10();*/ break; // DB DD + case /*DD*/0x11: illegal_1(); /*op_11();*/ break; // DB DD + case /*DD*/0x12: illegal_1(); /*op_12();*/ break; // DB DD + case /*DD*/0x13: illegal_1(); /*op_13();*/ break; // DB DD + case /*DD*/0x14: illegal_1(); /*op_14();*/ break; // DB DD + case /*DD*/0x15: illegal_1(); /*op_15();*/ break; // DB DD + case /*DD*/0x16: illegal_1(); /*op_16();*/ break; // DB DD + case /*DD*/0x17: illegal_1(); /*op_17();*/ break; // DB DD + + case /*DD*/0x18: illegal_1(); /*op_18();*/ break; // DB DD + case /*DD*/0x19: _R++; ADD16(_IX,_DE); break; // ADD IX,DE + case /*DD*/0x1a: illegal_1(); /*op_1a();*/ break; // DB DD + case /*DD*/0x1b: illegal_1(); /*op_1b();*/ break; // DB DD + case /*DD*/0x1c: illegal_1(); /*op_1c();*/ break; // DB DD + case /*DD*/0x1d: illegal_1(); /*op_1d();*/ break; // DB DD + case /*DD*/0x1e: illegal_1(); /*op_1e();*/ break; // DB DD + case /*DD*/0x1f: illegal_1(); /*op_1f();*/ break; // DB DD + + case /*DD*/0x20: illegal_1(); /*op_20();*/ break; // DB DD + case /*DD*/0x21: _R++; _IX = ARG16(); break; // LD IX,w + case /*DD*/0x22: _R++; WM16( ARG16(), _IX ); break; // LD (w),IX + case /*DD*/0x23: _R++; _IX++; break; // INC IX + case /*DD*/0x24: _R++; _HX = INC(_HX); break; // INC HX + case /*DD*/0x25: _R++; _HX = DEC(_HX); break; // DEC HX + case /*DD*/0x26: _R++; _HX = ARG(); break; // LD HX,n + case /*DD*/0x27: illegal_1(); /*op_27();*/ break; // DB DD + + case /*DD*/0x28: illegal_1(); /*op_28();*/ break; // DB DD + case /*DD*/0x29: _R++; ADD16(_IX,_IX); break; // ADD IX,IX + case /*DD*/0x2a: _R++; _IX = RM16( ARG16() ); break; // LD IX,(w) + case /*DD*/0x2b: _R++; _IX--; break; // DEC IX + case /*DD*/0x2c: _R++; _LX = INC(_LX); break; // INC LX + case /*DD*/0x2d: _R++; _LX = DEC(_LX); break; // DEC LX + case /*DD*/0x2e: _R++; _LX = ARG(); break; // LD LX,n + case /*DD*/0x2f: illegal_1(); /*op_2f();*/ break; // DB DD + + case /*DD*/0x30: illegal_1(); /*op_30();*/ break; // DB DD + case /*DD*/0x31: illegal_1(); /*op_31();*/ break; // DB DD + case /*DD*/0x32: illegal_1(); /*op_32();*/ break; // DB DD + case /*DD*/0x33: illegal_1(); /*op_33();*/ break; // DB DD + case /*DD*/0x34: _R++; EAX; WM( EA, INC(RM(EA)) ); break; // INC (IX+o) + case /*DD*/0x35: _R++; EAX; WM( EA, DEC(RM(EA)) ); break; // DEC (IX+o) + case /*DD*/0x36: _R++; EAX; WM( EA, ARG() ); break; // LD (IX+o),n + case /*DD*/0x37: illegal_1(); /*op_37();*/ break; // DB DD + + case /*DD*/0x38: illegal_1(); /*op_38();*/ break; // DB DD + case /*DD*/0x39: _R++; ADD16(_IX,_SP); break; // ADD IX,SP + case /*DD*/0x3a: illegal_1(); /*op_3a();*/ break; // DB DD + case /*DD*/0x3b: illegal_1(); /*op_3b();*/ break; // DB DD + case /*DD*/0x3c: illegal_1(); /*op_3c();*/ break; // DB DD + case /*DD*/0x3d: illegal_1(); /*op_3d();*/ break; // DB DD + case /*DD*/0x3e: illegal_1(); /*op_3e();*/ break; // DB DD + case /*DD*/0x3f: illegal_1(); /*op_3f();*/ break; // DB DD + + case /*DD*/0x40: illegal_1(); /*op_40();*/ break; // DB DD + case /*DD*/0x41: illegal_1(); /*op_41();*/ break; // DB DD + case /*DD*/0x42: illegal_1(); /*op_42();*/ break; // DB DD + case /*DD*/0x43: illegal_1(); /*op_43();*/ break; // DB DD + case /*DD*/0x44: _R++; _B = _HX; break; // LD B,HX + case /*DD*/0x45: _R++; _B = _LX; break; // LD B,LX + case /*DD*/0x46: _R++; EAX; _B = RM(EA); break; // LD B,(IX+o) + case /*DD*/0x47: illegal_1(); /*op_47();*/ break; // DB DD + + case /*DD*/0x48: illegal_1(); /*op_48();*/ break; // DB DD + case /*DD*/0x49: illegal_1(); /*op_49();*/ break; // DB DD + case /*DD*/0x4a: illegal_1(); /*op_4a();*/ break; // DB DD + case /*DD*/0x4b: illegal_1(); /*op_4b();*/ break; // DB DD + case /*DD*/0x4c: _R++; _C = _HX; break; // LD C,HX + case /*DD*/0x4d: _R++; _C = _LX; break; // LD C,LX + case /*DD*/0x4e: _R++; EAX; _C = RM(EA); break; // LD C,(IX+o) + case /*DD*/0x4f: illegal_1(); /*op_4f();*/ break; // DB DD + + case /*DD*/0x50: illegal_1(); /*op_50();*/ break; // DB DD + case /*DD*/0x51: illegal_1(); /*op_51();*/ break; // DB DD + case /*DD*/0x52: illegal_1(); /*op_52();*/ break; // DB DD + case /*DD*/0x53: illegal_1(); /*op_53();*/ break; // DB DD + case /*DD*/0x54: _R++; _D = _HX; break; // LD D,HX + case /*DD*/0x55: _R++; _D = _LX; break; // LD D,LX + case /*DD*/0x56: _R++; EAX; _D = RM(EA); break; // LD D,(IX+o) + case /*DD*/0x57: illegal_1(); /*op_57();*/ break; // DB DD + + case /*DD*/0x58: illegal_1(); /*op_58();*/ break; // DB DD + case /*DD*/0x59: illegal_1(); /*op_59();*/ break; // DB DD + case /*DD*/0x5a: illegal_1(); /*op_5a();*/ break; // DB DD + case /*DD*/0x5b: illegal_1(); /*op_5b();*/ break; // DB DD + case /*DD*/0x5c: _R++; _E = _HX; break; // LD E,HX + case /*DD*/0x5d: _R++; _E = _LX; break; // LD E,LX + case /*DD*/0x5e: _R++; EAX; _E = RM(EA); break; // LD E,(IX+o) + case /*DD*/0x5f: illegal_1(); /*op_5f();*/ break; // DB DD + + case /*DD*/0x60: _R++; _HX = _B; break; // LD HX,B + case /*DD*/0x61: _R++; _HX = _C; break; // LD HX,C + case /*DD*/0x62: _R++; _HX = _D; break; // LD HX,D + case /*DD*/0x63: _R++; _HX = _E; break; // LD HX,E + case /*DD*/0x64: break; // LD HX,HX + case /*DD*/0x65: _R++; _HX = _LX; break; // LD HX,LX + case /*DD*/0x66: _R++; EAX; _H = RM(EA); break; // LD H,(IX+o) + case /*DD*/0x67: _R++; _HX = _A; break; // LD HX,A + + case /*DD*/0x68: _R++; _LX = _B; break; // LD LX,B + case /*DD*/0x69: _R++; _LX = _C; break; // LD LX,C + case /*DD*/0x6a: _R++; _LX = _D; break; // LD LX,D + case /*DD*/0x6b: _R++; _LX = _E; break; // LD LX,E + case /*DD*/0x6c: _R++; _LX = _HX; break; // LD LX,HX + case /*DD*/0x6d: break; // LD LX,LX + case /*DD*/0x6e: _R++; EAX; _L = RM(EA); break; // LD L,(IX+o) + case /*DD*/0x6f: _R++; _LX = _A; break; // LD LX,A + + case /*DD*/0x70: _R++; EAX; WM( EA, _B ); break; // LD (IX+o),B + case /*DD*/0x71: _R++; EAX; WM( EA, _C ); break; // LD (IX+o),C + case /*DD*/0x72: _R++; EAX; WM( EA, _D ); break; // LD (IX+o),D + case /*DD*/0x73: _R++; EAX; WM( EA, _E ); break; // LD (IX+o),E + case /*DD*/0x74: _R++; EAX; WM( EA, _H ); break; // LD (IX+o),H + case /*DD*/0x75: _R++; EAX; WM( EA, _L ); break; // LD (IX+o),L + case /*DD*/0x76: illegal_1(); /*op_76();*/ break; // DB DD + case /*DD*/0x77: _R++; EAX; WM( EA, _A ); break; // LD (IX+o),A + + case /*DD*/0x78: illegal_1(); /*op_78();*/ break; // DB DD + case /*DD*/0x79: illegal_1(); /*op_79();*/ break; // DB DD + case /*DD*/0x7a: illegal_1(); /*op_7a();*/ break; // DB DD + case /*DD*/0x7b: illegal_1(); /*op_7b();*/ break; // DB DD + case /*DD*/0x7c: _R++; _A = _HX; break; // LD A,HX + case /*DD*/0x7d: _R++; _A = _LX; break; // LD A,LX + case /*DD*/0x7e: _R++; EAX; _A = RM(EA); break; // LD A,(IX+o) + case /*DD*/0x7f: illegal_1(); /*op_7f();*/ break; // DB DD + + case /*DD*/0x80: illegal_1(); /*op_80();*/ break; // DB DD + case /*DD*/0x81: illegal_1(); /*op_81();*/ break; // DB DD + case /*DD*/0x82: illegal_1(); /*op_82();*/ break; // DB DD + case /*DD*/0x83: illegal_1(); /*op_83();*/ break; // DB DD + case /*DD*/0x84: _R++; ADD(_HX); break; // ADD A,HX + case /*DD*/0x85: _R++; ADD(_LX); break; // ADD A,LX + case /*DD*/0x86: _R++; EAX; ADD(RM(EA)); break; // ADD A,(IX+o) + case /*DD*/0x87: illegal_1(); /*op_87();*/ break; // DB DD + + case /*DD*/0x88: illegal_1(); /*op_88();*/ break; // DB DD + case /*DD*/0x89: illegal_1(); /*op_89();*/ break; // DB DD + case /*DD*/0x8a: illegal_1(); /*op_8a();*/ break; // DB DD + case /*DD*/0x8b: illegal_1(); /*op_8b();*/ break; // DB DD + case /*DD*/0x8c: _R++; ADC(_HX); break; // ADC A,HX + case /*DD*/0x8d: _R++; ADC(_LX); break; // ADC A,LX + case /*DD*/0x8e: _R++; EAX; ADC(RM(EA)); break; // ADC A,(IX+o) + case /*DD*/0x8f: illegal_1(); /*op_8f();*/ break; // DB DD + + case /*DD*/0x90: illegal_1(); /*op_90();*/ break; // DB DD + case /*DD*/0x91: illegal_1(); /*op_91();*/ break; // DB DD + case /*DD*/0x92: illegal_1(); /*op_92();*/ break; // DB DD + case /*DD*/0x93: illegal_1(); /*op_93();*/ break; // DB DD + case /*DD*/0x94: _R++; SUB(_HX); break; // SUB HX + case /*DD*/0x95: _R++; SUB(_LX); break; // SUB LX + case /*DD*/0x96: _R++; EAX; SUB(RM(EA)); break; // SUB (IX+o) + case /*DD*/0x97: illegal_1(); /*op_97();*/ break; // DB DD + + case /*DD*/0x98: illegal_1(); /*op_98();*/ break; // DB DD + case /*DD*/0x99: illegal_1(); /*op_99();*/ break; // DB DD + case /*DD*/0x9a: illegal_1(); /*op_9a();*/ break; // DB DD + case /*DD*/0x9b: illegal_1(); /*op_9b();*/ break; // DB DD + case /*DD*/0x9c: _R++; SBC(_HX); break; // SBC A,HX + case /*DD*/0x9d: _R++; SBC(_LX); break; // SBC A,LX + case /*DD*/0x9e: _R++; EAX; SBC(RM(EA)); break; // SBC A,(IX+o) + case /*DD*/0x9f: illegal_1(); /*op_9f();*/ break; // DB DD + + case /*DD*/0xa0: illegal_1(); /*op_a0();*/ break; // DB DD + case /*DD*/0xa1: illegal_1(); /*op_a1();*/ break; // DB DD + case /*DD*/0xa2: illegal_1(); /*op_a2();*/ break; // DB DD + case /*DD*/0xa3: illegal_1(); /*op_a3();*/ break; // DB DD + case /*DD*/0xa4: _R++; AND(_HX); break; // AND HX + case /*DD*/0xa5: _R++; AND(_LX); break; // AND LX + case /*DD*/0xa6: _R++; EAX; AND(RM(EA)); break; // AND (IX+o) + case /*DD*/0xa7: illegal_1(); /*op_a7();*/ break; // DB DD + + case /*DD*/0xa8: illegal_1(); /*op_a8();*/ break; // DB DD + case /*DD*/0xa9: illegal_1(); /*op_a9();*/ break; // DB DD + case /*DD*/0xaa: illegal_1(); /*op_aa();*/ break; // DB DD + case /*DD*/0xab: illegal_1(); /*op_ab();*/ break; // DB DD + case /*DD*/0xac: _R++; XOR(_HX); break; // XOR HX + case /*DD*/0xad: _R++; XOR(_LX); break; // XOR LX + case /*DD*/0xae: _R++; EAX; XOR(RM(EA)); break; // XOR (IX+o) + case /*DD*/0xaf: illegal_1(); /*op_af();*/ break; // DB DD + + case /*DD*/0xb0: illegal_1(); /*op_b0();*/ break; // DB DD + case /*DD*/0xb1: illegal_1(); /*op_b1();*/ break; // DB DD + case /*DD*/0xb2: illegal_1(); /*op_b2();*/ break; // DB DD + case /*DD*/0xb3: illegal_1(); /*op_b3();*/ break; // DB DD + case /*DD*/0xb4: _R++; OR(_HX); break; // OR HX + case /*DD*/0xb5: _R++; OR(_LX); break; // OR LX + case /*DD*/0xb6: _R++; EAX; OR(RM(EA)); break; // OR (IX+o) + case /*DD*/0xb7: illegal_1(); /*op_b7();*/ break; // DB DD + + case /*DD*/0xb8: illegal_1(); /*op_b8();*/ break; // DB DD + case /*DD*/0xb9: illegal_1(); /*op_b9();*/ break; // DB DD + case /*DD*/0xba: illegal_1(); /*op_ba();*/ break; // DB DD + case /*DD*/0xbb: illegal_1(); /*op_bb();*/ break; // DB DD + case /*DD*/0xbc: _R++; CP(_HX); break; // CP HX + case /*DD*/0xbd: _R++; CP(_LX); break; // CP LX + case /*DD*/0xbe: _R++; EAX; CP(RM(EA)); break; // CP (IX+o) + case /*DD*/0xbf: illegal_1(); /*op_bf();*/ break; // DB DD + + case /*DD*/0xc0: illegal_1(); /*op_c0();*/ break; // DB DD + case /*DD*/0xc1: illegal_1(); /*op_c1();*/ break; // DB DD + case /*DD*/0xc2: illegal_1(); /*op_c2();*/ break; // DB DD + case /*DD*/0xc3: illegal_1(); /*op_c3();*/ break; // DB DD + case /*DD*/0xc4: illegal_1(); /*op_c4();*/ break; // DB DD + case /*DD*/0xc5: illegal_1(); /*op_c5();*/ break; // DB DD + case /*DD*/0xc6: illegal_1(); /*op_c6();*/ break; // DB DD + case /*DD*/0xc7: illegal_1(); /*op_c7();*/ break; // DB DD + + case /*DD*/0xc8: illegal_1(); /*op_c8();*/ break; // DB DD + case /*DD*/0xc9: illegal_1(); /*op_c9();*/ break; // DB DD + case /*DD*/0xca: illegal_1(); /*op_ca();*/ break; // DB DD +// pretty sure this is supposed to be ARG() + case /*DD*/0xcb: _R++; EAX; EXEC_EA(xycb,ARG(),EA); break; // ** DD CB xx + case /*DD*/0xcc: illegal_1(); /*op_cc();*/ break; // DB DD + case /*DD*/0xcd: illegal_1(); /*op_cd();*/ break; // DB DD + case /*DD*/0xce: illegal_1(); /*op_ce();*/ break; // DB DD + case /*DD*/0xcf: illegal_1(); /*op_cf();*/ break; // DB DD + + case /*DD*/0xd0: illegal_1(); /*op_d0();*/ break; // DB DD + case /*DD*/0xd1: illegal_1(); /*op_d1();*/ break; // DB DD + case /*DD*/0xd2: illegal_1(); /*op_d2();*/ break; // DB DD + case /*DD*/0xd3: illegal_1(); /*op_d3();*/ break; // DB DD + case /*DD*/0xd4: illegal_1(); /*op_d4();*/ break; // DB DD + case /*DD*/0xd5: illegal_1(); /*op_d5();*/ break; // DB DD + case /*DD*/0xd6: illegal_1(); /*op_d6();*/ break; // DB DD + case /*DD*/0xd7: illegal_1(); /*op_d7();*/ break; // DB DD + + case /*DD*/0xd8: illegal_1(); /*op_d8();*/ break; // DB DD + case /*DD*/0xd9: illegal_1(); /*op_d9();*/ break; // DB DD + case /*DD*/0xda: illegal_1(); /*op_da();*/ break; // DB DD + case /*DD*/0xdb: illegal_1(); /*op_db();*/ break; // DB DD + case /*DD*/0xdc: illegal_1(); /*op_dc();*/ break; // DB DD + case /*DD*/0xdd: illegal_1(); /*op_dd();*/ break; // DB DD + case /*DD*/0xde: illegal_1(); /*op_de();*/ break; // DB DD + case /*DD*/0xdf: illegal_1(); /*op_df();*/ break; // DB DD + + case /*DD*/0xe0: illegal_1(); /*op_e0();*/ break; // DB DD + case /*DD*/0xe1: _R++; _IX = POP(); break; // POP IX + case /*DD*/0xe2: illegal_1(); /*op_e2();*/ break; // DB DD + case /*DD*/0xe3: _R++; _IX = EXSP16(_IX); break; // EX (SP),IX + case /*DD*/0xe4: illegal_1(); /*op_e4();*/ break; // DB DD + case /*DD*/0xe5: _R++; PUSH( _IX ); break; // PUSH IX + case /*DD*/0xe6: illegal_1(); /*op_e6();*/ break; // DB DD + case /*DD*/0xe7: illegal_1(); /*op_e7();*/ break; // DB DD + + case /*DD*/0xe8: illegal_1(); /*op_e8();*/ break; // DB DD + case /*DD*/0xe9: _R++; _PC = _IX; break; // JP (IX) + case /*DD*/0xea: illegal_1(); /*op_ea();*/ break; // DB DD + case /*DD*/0xeb: illegal_1(); /*op_eb();*/ break; // DB DD + case /*DD*/0xec: illegal_1(); /*op_ec();*/ break; // DB DD + case /*DD*/0xed: illegal_1(); /*op_ed();*/ break; // DB DD + case /*DD*/0xee: illegal_1(); /*op_ee();*/ break; // DB DD + case /*DD*/0xef: illegal_1(); /*op_ef();*/ break; // DB DD + + case /*DD*/0xf0: illegal_1(); /*op_f0();*/ break; // DB DD + case /*DD*/0xf1: illegal_1(); /*op_f1();*/ break; // DB DD + case /*DD*/0xf2: illegal_1(); /*op_f2();*/ break; // DB DD + case /*DD*/0xf3: illegal_1(); /*op_f3();*/ break; // DB DD + case /*DD*/0xf4: illegal_1(); /*op_f4();*/ break; // DB DD + case /*DD*/0xf5: illegal_1(); /*op_f5();*/ break; // DB DD + case /*DD*/0xf6: illegal_1(); /*op_f6();*/ break; // DB DD + case /*DD*/0xf7: illegal_1(); /*op_f7();*/ break; // DB DD + + case /*DD*/0xf8: illegal_1(); /*op_f8();*/ break; // DB DD + case /*DD*/0xf9: _R++; _SP = _IX; break; // LD SP,IX + case /*DD*/0xfa: illegal_1(); /*op_fa();*/ break; // DB DD + case /*DD*/0xfb: illegal_1(); /*op_fb();*/ break; // DB DD + case /*DD*/0xfc: illegal_1(); /*op_fc();*/ break; // DB DD + case /*DD*/0xfd: illegal_1(); /*op_fd();*/ break; // DB DD + case /*DD*/0xfe: illegal_1(); /*op_fe();*/ break; // DB DD + case /*DD*/0xff: illegal_1(); /*op_ff();*/ break; // DB DD + } +} + +///////////////////////////////////////////////////////////////////////////// + +static EMU_INLINE void z80_exec_ed(struct Z80_STATE *state, uint8 op) { + +//printf("PC=%04X exec ed %02X\n",_PC, op);fflush(stdout); + + switch(op) { + case /*ED*/0x00: illegal_2(); break; // DB ED + case /*ED*/0x01: illegal_2(); break; // DB ED + case /*ED*/0x02: illegal_2(); break; // DB ED + case /*ED*/0x03: illegal_2(); break; // DB ED + case /*ED*/0x04: illegal_2(); break; // DB ED + case /*ED*/0x05: illegal_2(); break; // DB ED + case /*ED*/0x06: illegal_2(); break; // DB ED + case /*ED*/0x07: illegal_2(); break; // DB ED + + case /*ED*/0x08: illegal_2(); break; // DB ED + case /*ED*/0x09: illegal_2(); break; // DB ED + case /*ED*/0x0a: illegal_2(); break; // DB ED + case /*ED*/0x0b: illegal_2(); break; // DB ED + case /*ED*/0x0c: illegal_2(); break; // DB ED + case /*ED*/0x0d: illegal_2(); break; // DB ED + case /*ED*/0x0e: illegal_2(); break; // DB ED + case /*ED*/0x0f: illegal_2(); break; // DB ED + + case /*ED*/0x10: illegal_2(); break; // DB ED + case /*ED*/0x11: illegal_2(); break; // DB ED + case /*ED*/0x12: illegal_2(); break; // DB ED + case /*ED*/0x13: illegal_2(); break; // DB ED + case /*ED*/0x14: illegal_2(); break; // DB ED + case /*ED*/0x15: illegal_2(); break; // DB ED + case /*ED*/0x16: illegal_2(); break; // DB ED + case /*ED*/0x17: illegal_2(); break; // DB ED + + case /*ED*/0x18: illegal_2(); break; // DB ED + case /*ED*/0x19: illegal_2(); break; // DB ED + case /*ED*/0x1a: illegal_2(); break; // DB ED + case /*ED*/0x1b: illegal_2(); break; // DB ED + case /*ED*/0x1c: illegal_2(); break; // DB ED + case /*ED*/0x1d: illegal_2(); break; // DB ED + case /*ED*/0x1e: illegal_2(); break; // DB ED + case /*ED*/0x1f: illegal_2(); break; // DB ED + + case /*ED*/0x20: illegal_2(); break; // DB ED + case /*ED*/0x21: illegal_2(); break; // DB ED + case /*ED*/0x22: illegal_2(); break; // DB ED + case /*ED*/0x23: illegal_2(); break; // DB ED + case /*ED*/0x24: illegal_2(); break; // DB ED + case /*ED*/0x25: illegal_2(); break; // DB ED + case /*ED*/0x26: illegal_2(); break; // DB ED + case /*ED*/0x27: illegal_2(); break; // DB ED + + case /*ED*/0x28: illegal_2(); break; // DB ED + case /*ED*/0x29: illegal_2(); break; // DB ED + case /*ED*/0x2a: illegal_2(); break; // DB ED + case /*ED*/0x2b: illegal_2(); break; // DB ED + case /*ED*/0x2c: illegal_2(); break; // DB ED + case /*ED*/0x2d: illegal_2(); break; // DB ED + case /*ED*/0x2e: illegal_2(); break; // DB ED + case /*ED*/0x2f: illegal_2(); break; // DB ED + + case /*ED*/0x30: illegal_2(); break; // DB ED + case /*ED*/0x31: illegal_2(); break; // DB ED + case /*ED*/0x32: illegal_2(); break; // DB ED + case /*ED*/0x33: illegal_2(); break; // DB ED + case /*ED*/0x34: illegal_2(); break; // DB ED + case /*ED*/0x35: illegal_2(); break; // DB ED + case /*ED*/0x36: illegal_2(); break; // DB ED + case /*ED*/0x37: illegal_2(); break; // DB ED + + case /*ED*/0x38: illegal_2(); break; // DB ED + case /*ED*/0x39: illegal_2(); break; // DB ED + case /*ED*/0x3a: illegal_2(); break; // DB ED + case /*ED*/0x3b: illegal_2(); break; // DB ED + case /*ED*/0x3c: illegal_2(); break; // DB ED + case /*ED*/0x3d: illegal_2(); break; // DB ED + case /*ED*/0x3e: illegal_2(); break; // DB ED + case /*ED*/0x3f: illegal_2(); break; // DB ED + + case /*ED*/0x40: _B = Z80IN(_BC); _F = (_F & CF) | SZP[_B]; break; // IN B,(C) + case /*ED*/0x41: Z80OUT(_BC,_B); break; // OUT (C),B + case /*ED*/0x42: SBC16( _BC ); break; // SBC HL,BC + case /*ED*/0x43: WM16( ARG16(), _BC ); break; // LD (w),BC + case /*ED*/0x44: NEG; break; // NEG + case /*ED*/0x45: RETN; break; // RETN; + case /*ED*/0x46: IM(0); break; // IM 0 + case /*ED*/0x47: LD_I_A; break; // LD I,A + + case /*ED*/0x48: _C = Z80IN(_BC); _F = (_F & CF) | SZP[_C]; break; // IN C,(C) + case /*ED*/0x49: Z80OUT(_BC,_C); break; // OUT (C),C + case /*ED*/0x4a: ADC16( _BC ); break; // ADC HL,BC + case /*ED*/0x4b: _BC = RM16( ARG16() ); break; // LD BC,(w) + case /*ED*/0x4c: NEG; break; // NEG + case /*ED*/0x4d: RETI; break; // RETI + case /*ED*/0x4e: IM(0); break; // IM 0 + case /*ED*/0x4f: LD_R_A; break; // LD R,A + + case /*ED*/0x50: _D = Z80IN(_BC); _F = (_F & CF) | SZP[_D]; break; // IN D,(C) + case /*ED*/0x51: Z80OUT(_BC,_D); break; // OUT (C),D + case /*ED*/0x52: SBC16( _DE ); break; // SBC HL,DE + case /*ED*/0x53: WM16( ARG16(), _DE ); break; // LD (w),DE + case /*ED*/0x54: NEG; break; // NEG + case /*ED*/0x55: RETN; break; // RETN; + case /*ED*/0x56: IM(1); break; // IM 1 + case /*ED*/0x57: LD_A_I; break; // LD A,I + + case /*ED*/0x58: _E = Z80IN(_BC); _F = (_F & CF) | SZP[_E]; break; // IN E,(C) + case /*ED*/0x59: Z80OUT(_BC,_E); break; // OUT (C),E + case /*ED*/0x5a: ADC16( _DE ); break; // ADC HL,DE + case /*ED*/0x5b: _DE = RM16( ARG16() ); break; // LD DE,(w) + case /*ED*/0x5c: NEG; break; // NEG + case /*ED*/0x5d: RETI; break; // RETI + case /*ED*/0x5e: IM(2); break; // IM 2 + case /*ED*/0x5f: LD_A_R; break; // LD A,R + + case /*ED*/0x60: _H = Z80IN(_BC); _F = (_F & CF) | SZP[_H]; break; // IN H,(C) + case /*ED*/0x61: Z80OUT(_BC,_H); break; // OUT (C),H + case /*ED*/0x62: SBC16( _HL ); break; // SBC HL,HL + case /*ED*/0x63: WM16( ARG16(), _HL ); break; // LD (w),HL + case /*ED*/0x64: NEG; break; // NEG + case /*ED*/0x65: RETN; break; // RETN; + case /*ED*/0x66: IM (0); break; // IM 0 + case /*ED*/0x67: RRD; break; // RRD (HL) + + case /*ED*/0x68: _L = Z80IN(_BC); _F = (_F & CF) | SZP[_L]; break; // IN L,(C) + case /*ED*/0x69: Z80OUT(_BC,_L); break; // OUT (C),L + case /*ED*/0x6a: ADC16( _HL ); break; // ADC HL,HL + case /*ED*/0x6b: _HL = RM16( ARG16() ); break; // LD HL,(w) + case /*ED*/0x6c: NEG; break; // NEG + case /*ED*/0x6d: RETI; break; // RETI + case /*ED*/0x6e: IM(0); break; // IM 0 + case /*ED*/0x6f: RLD; break; // RLD (HL) + + case /*ED*/0x70: _F = (_F & CF) | SZP[Z80IN(_BC)]; break; // IN 0,(C) + case /*ED*/0x71: Z80OUT(_BC,0); break; // OUT (C),0 + case /*ED*/0x72: SBC16( _SP ); break; // SBC HL,SP + case /*ED*/0x73: WM16( ARG16(), _SP ); break; // LD (w),SP + case /*ED*/0x74: NEG; break; // NEG + case /*ED*/0x75: RETN; break; // RETN; + case /*ED*/0x76: IM(1); break; // IM 1 + case /*ED*/0x77: illegal_2(); break; // DB ED,77 + + case /*ED*/0x78: _A = Z80IN(_BC); _F = (_F & CF) | SZP[_A]; break; // IN E,(C) + case /*ED*/0x79: Z80OUT(_BC,_A); break; // OUT (C),E + case /*ED*/0x7a: ADC16( _SP ); break; // ADC HL,SP + case /*ED*/0x7b: _SP = RM16( ARG16() ); break; // LD SP,(w) + case /*ED*/0x7c: NEG; break; // NEG + case /*ED*/0x7d: RETI; break; // RETI + case /*ED*/0x7e: IM(2); break; // IM 2 + case /*ED*/0x7f: illegal_2(); break; // DB ED,7F + + case /*ED*/0x80: illegal_2(); break; // DB ED + case /*ED*/0x81: illegal_2(); break; // DB ED + case /*ED*/0x82: illegal_2(); break; // DB ED + case /*ED*/0x83: illegal_2(); break; // DB ED + case /*ED*/0x84: illegal_2(); break; // DB ED + case /*ED*/0x85: illegal_2(); break; // DB ED + case /*ED*/0x86: illegal_2(); break; // DB ED + case /*ED*/0x87: illegal_2(); break; // DB ED + + case /*ED*/0x88: illegal_2(); break; // DB ED + case /*ED*/0x89: illegal_2(); break; // DB ED + case /*ED*/0x8a: illegal_2(); break; // DB ED + case /*ED*/0x8b: illegal_2(); break; // DB ED + case /*ED*/0x8c: illegal_2(); break; // DB ED + case /*ED*/0x8d: illegal_2(); break; // DB ED + case /*ED*/0x8e: illegal_2(); break; // DB ED + case /*ED*/0x8f: illegal_2(); break; // DB ED + + case /*ED*/0x90: illegal_2(); break; // DB ED + case /*ED*/0x91: illegal_2(); break; // DB ED + case /*ED*/0x92: illegal_2(); break; // DB ED + case /*ED*/0x93: illegal_2(); break; // DB ED + case /*ED*/0x94: illegal_2(); break; // DB ED + case /*ED*/0x95: illegal_2(); break; // DB ED + case /*ED*/0x96: illegal_2(); break; // DB ED + case /*ED*/0x97: illegal_2(); break; // DB ED + + case /*ED*/0x98: illegal_2(); break; // DB ED + case /*ED*/0x99: illegal_2(); break; // DB ED + case /*ED*/0x9a: illegal_2(); break; // DB ED + case /*ED*/0x9b: illegal_2(); break; // DB ED + case /*ED*/0x9c: illegal_2(); break; // DB ED + case /*ED*/0x9d: illegal_2(); break; // DB ED + case /*ED*/0x9e: illegal_2(); break; // DB ED + case /*ED*/0x9f: illegal_2(); break; // DB ED + + case /*ED*/0xa0: LDI; break; // LDI + case /*ED*/0xa1: CPI; break; // CPI + case /*ED*/0xa2: INI; break; // INI + case /*ED*/0xa3: OUTI; break; // OUTI + case /*ED*/0xa4: illegal_2(); break; // DB ED + case /*ED*/0xa5: illegal_2(); break; // DB ED + case /*ED*/0xa6: illegal_2(); break; // DB ED + case /*ED*/0xa7: illegal_2(); break; // DB ED + + case /*ED*/0xa8: LDD; break; // LDD + case /*ED*/0xa9: CPD; break; // CPD + case /*ED*/0xaa: IND; break; // IND + case /*ED*/0xab: OUTD; break; // OUTD + case /*ED*/0xac: illegal_2(); break; // DB ED + case /*ED*/0xad: illegal_2(); break; // DB ED + case /*ED*/0xae: illegal_2(); break; // DB ED + case /*ED*/0xaf: illegal_2(); break; // DB ED + + case /*ED*/0xb0: LDIR; break; // LDIR + case /*ED*/0xb1: CPIR; break; // CPIR + case /*ED*/0xb2: INIR; break; // INIR + case /*ED*/0xb3: OTIR; break; // OTIR + case /*ED*/0xb4: illegal_2(); break; // DB ED + case /*ED*/0xb5: illegal_2(); break; // DB ED + case /*ED*/0xb6: illegal_2(); break; // DB ED + case /*ED*/0xb7: illegal_2(); break; // DB ED + + case /*ED*/0xb8: LDDR; break; // LDDR + case /*ED*/0xb9: CPDR; break; // CPDR + case /*ED*/0xba: INDR; break; // INDR + case /*ED*/0xbb: OTDR; break; // OTDR + case /*ED*/0xbc: illegal_2(); break; // DB ED + case /*ED*/0xbd: illegal_2(); break; // DB ED + case /*ED*/0xbe: illegal_2(); break; // DB ED + case /*ED*/0xbf: illegal_2(); break; // DB ED + + case /*ED*/0xc0: illegal_2(); break; // DB ED + case /*ED*/0xc1: illegal_2(); break; // DB ED + case /*ED*/0xc2: illegal_2(); break; // DB ED + case /*ED*/0xc3: illegal_2(); break; // DB ED + case /*ED*/0xc4: illegal_2(); break; // DB ED + case /*ED*/0xc5: illegal_2(); break; // DB ED + case /*ED*/0xc6: illegal_2(); break; // DB ED + case /*ED*/0xc7: illegal_2(); break; // DB ED + + case /*ED*/0xc8: illegal_2(); break; // DB ED + case /*ED*/0xc9: illegal_2(); break; // DB ED + case /*ED*/0xca: illegal_2(); break; // DB ED + case /*ED*/0xcb: illegal_2(); break; // DB ED + case /*ED*/0xcc: illegal_2(); break; // DB ED + case /*ED*/0xcd: illegal_2(); break; // DB ED + case /*ED*/0xce: illegal_2(); break; // DB ED + case /*ED*/0xcf: illegal_2(); break; // DB ED + + case /*ED*/0xd0: illegal_2(); break; // DB ED + case /*ED*/0xd1: illegal_2(); break; // DB ED + case /*ED*/0xd2: illegal_2(); break; // DB ED + case /*ED*/0xd3: illegal_2(); break; // DB ED + case /*ED*/0xd4: illegal_2(); break; // DB ED + case /*ED*/0xd5: illegal_2(); break; // DB ED + case /*ED*/0xd6: illegal_2(); break; // DB ED + case /*ED*/0xd7: illegal_2(); break; // DB ED + + case /*ED*/0xd8: illegal_2(); break; // DB ED + case /*ED*/0xd9: illegal_2(); break; // DB ED + case /*ED*/0xda: illegal_2(); break; // DB ED + case /*ED*/0xdb: illegal_2(); break; // DB ED + case /*ED*/0xdc: illegal_2(); break; // DB ED + case /*ED*/0xdd: illegal_2(); break; // DB ED + case /*ED*/0xde: illegal_2(); break; // DB ED + case /*ED*/0xdf: illegal_2(); break; // DB ED + + case /*ED*/0xe0: illegal_2(); break; // DB ED + case /*ED*/0xe1: illegal_2(); break; // DB ED + case /*ED*/0xe2: illegal_2(); break; // DB ED + case /*ED*/0xe3: illegal_2(); break; // DB ED + case /*ED*/0xe4: illegal_2(); break; // DB ED + case /*ED*/0xe5: illegal_2(); break; // DB ED + case /*ED*/0xe6: illegal_2(); break; // DB ED + case /*ED*/0xe7: illegal_2(); break; // DB ED + + case /*ED*/0xe8: illegal_2(); break; // DB ED + case /*ED*/0xe9: illegal_2(); break; // DB ED + case /*ED*/0xea: illegal_2(); break; // DB ED + case /*ED*/0xeb: illegal_2(); break; // DB ED + case /*ED*/0xec: illegal_2(); break; // DB ED + case /*ED*/0xed: illegal_2(); break; // DB ED + case /*ED*/0xee: illegal_2(); break; // DB ED + case /*ED*/0xef: illegal_2(); break; // DB ED + + case /*ED*/0xf0: illegal_2(); break; // DB ED + case /*ED*/0xf1: illegal_2(); break; // DB ED + case /*ED*/0xf2: illegal_2(); break; // DB ED + case /*ED*/0xf3: illegal_2(); break; // DB ED + case /*ED*/0xf4: illegal_2(); break; // DB ED + case /*ED*/0xf5: illegal_2(); break; // DB ED + case /*ED*/0xf6: illegal_2(); break; // DB ED + case /*ED*/0xf7: illegal_2(); break; // DB ED + + case /*ED*/0xf8: illegal_2(); break; // DB ED + case /*ED*/0xf9: illegal_2(); break; // DB ED + case /*ED*/0xfa: illegal_2(); break; // DB ED + case /*ED*/0xfb: illegal_2(); break; // DB ED + case /*ED*/0xfc: illegal_2(); break; // DB ED + case /*ED*/0xfd: illegal_2(); break; // DB ED + case /*ED*/0xfe: illegal_2(); break; // DB ED + case /*ED*/0xff: illegal_2(); break; // DB ED + } +} + +///////////////////////////////////////////////////////////////////////////// + +static EMU_INLINE void z80_exec_fd(struct Z80_STATE *state, uint8 op) { + uint16 EA; + +//printf("PC=%04X exec fd %02X\n",_PC, op);fflush(stdout); + + switch(op) { + case /*FD*/0x00: illegal_1(); /*op_00();*/ break; // DB FD + case /*FD*/0x01: illegal_1(); /*op_01();*/ break; // DB FD + case /*FD*/0x02: illegal_1(); /*op_02();*/ break; // DB FD + case /*FD*/0x03: illegal_1(); /*op_03();*/ break; // DB FD + case /*FD*/0x04: illegal_1(); /*op_04();*/ break; // DB FD + case /*FD*/0x05: illegal_1(); /*op_05();*/ break; // DB FD + case /*FD*/0x06: illegal_1(); /*op_06();*/ break; // DB FD + case /*FD*/0x07: illegal_1(); /*op_07();*/ break; // DB FD + + case /*FD*/0x08: illegal_1(); /*op_08();*/ break; // DB FD + case /*FD*/0x09: _R++; ADD16(_IY,_BC); break; // ADD IY,BC + case /*FD*/0x0a: illegal_1(); /*op_0a();*/ break; // DB FD + case /*FD*/0x0b: illegal_1(); /*op_0b();*/ break; // DB FD + case /*FD*/0x0c: illegal_1(); /*op_0c();*/ break; // DB FD + case /*FD*/0x0d: illegal_1(); /*op_0d();*/ break; // DB FD + case /*FD*/0x0e: illegal_1(); /*op_0e();*/ break; // DB FD + case /*FD*/0x0f: illegal_1(); /*op_0f();*/ break; // DB FD + + case /*FD*/0x10: illegal_1(); /*op_10();*/ break; // DB FD + case /*FD*/0x11: illegal_1(); /*op_11();*/ break; // DB FD + case /*FD*/0x12: illegal_1(); /*op_12();*/ break; // DB FD + case /*FD*/0x13: illegal_1(); /*op_13();*/ break; // DB FD + case /*FD*/0x14: illegal_1(); /*op_14();*/ break; // DB FD + case /*FD*/0x15: illegal_1(); /*op_15();*/ break; // DB FD + case /*FD*/0x16: illegal_1(); /*op_16();*/ break; // DB FD + case /*FD*/0x17: illegal_1(); /*op_17();*/ break; // DB FD + + case /*FD*/0x18: illegal_1(); /*op_18();*/ break; // DB FD + case /*FD*/0x19: _R++; ADD16(_IY,_DE); break; // ADD IY,DE + case /*FD*/0x1a: illegal_1(); /*op_1a();*/ break; // DB FD + case /*FD*/0x1b: illegal_1(); /*op_1b();*/ break; // DB FD + case /*FD*/0x1c: illegal_1(); /*op_1c();*/ break; // DB FD + case /*FD*/0x1d: illegal_1(); /*op_1d();*/ break; // DB FD + case /*FD*/0x1e: illegal_1(); /*op_1e();*/ break; // DB FD + case /*FD*/0x1f: illegal_1(); /*op_1f();*/ break; // DB FD + + case /*FD*/0x20: illegal_1(); /*op_20();*/ break; // DB FD + case /*FD*/0x21: _R++; _IY = ARG16(); break; // LD IY,w + case /*FD*/0x22: _R++; WM16( ARG16(), _IY ); break; // LD (w),IY + case /*FD*/0x23: _R++; _IY++; break; // INC IY + case /*FD*/0x24: _R++; _HY = INC(_HY); break; // INC HY + case /*FD*/0x25: _R++; _HY = DEC(_HY); break; // DEC HY + case /*FD*/0x26: _R++; _HY = ARG(); break; // LD HY,n + case /*FD*/0x27: illegal_1(); /*op_27();*/ break; // DB FD + + case /*FD*/0x28: illegal_1(); /*op_28();*/ break; // DB FD + case /*FD*/0x29: _R++; ADD16(_IY,_IY); break; // ADD IY,IY + case /*FD*/0x2a: _R++; _IY = RM16( ARG16() ); break; // LD IY,(w) + case /*FD*/0x2b: _R++; _IY--; break; // DEC IY + case /*FD*/0x2c: _R++; _LY = INC(_LY); break; // INC LY + case /*FD*/0x2d: _R++; _LY = DEC(_LY); break; // DEC LY + case /*FD*/0x2e: _R++; _LY = ARG(); break; // LD LY,n + case /*FD*/0x2f: illegal_1(); /*op_2f();*/ break; // DB FD + + case /*FD*/0x30: illegal_1(); /*op_30();*/ break; // DB FD + case /*FD*/0x31: illegal_1(); /*op_31();*/ break; // DB FD + case /*FD*/0x32: illegal_1(); /*op_32();*/ break; // DB FD + case /*FD*/0x33: illegal_1(); /*op_33();*/ break; // DB FD + case /*FD*/0x34: _R++; EAY; WM( EA, INC(RM(EA)) ); break; // INC (IY+o) + case /*FD*/0x35: _R++; EAY; WM( EA, DEC(RM(EA)) ); break; // DEC (IY+o) + case /*FD*/0x36: _R++; EAY; WM( EA, ARG() ); break; // LD (IY+o),n + case /*FD*/0x37: illegal_1(); /*op_37();*/ break; // DB FD + + case /*FD*/0x38: illegal_1(); /*op_38();*/ break; // DB FD + case /*FD*/0x39: _R++; ADD16(_IY,_SP); break; // ADD IY,SP + case /*FD*/0x3a: illegal_1(); /*op_3a();*/ break; // DB FD + case /*FD*/0x3b: illegal_1(); /*op_3b();*/ break; // DB FD + case /*FD*/0x3c: illegal_1(); /*op_3c();*/ break; // DB FD + case /*FD*/0x3d: illegal_1(); /*op_3d();*/ break; // DB FD + case /*FD*/0x3e: illegal_1(); /*op_3e();*/ break; // DB FD + case /*FD*/0x3f: illegal_1(); /*op_3f();*/ break; // DB FD + + case /*FD*/0x40: illegal_1(); /*op_40();*/ break; // DB FD + case /*FD*/0x41: illegal_1(); /*op_41();*/ break; // DB FD + case /*FD*/0x42: illegal_1(); /*op_42();*/ break; // DB FD + case /*FD*/0x43: illegal_1(); /*op_43();*/ break; // DB FD + case /*FD*/0x44: _R++; _B = _HY; break; // LD B,HY + case /*FD*/0x45: _R++; _B = _LY; break; // LD B,LY + case /*FD*/0x46: _R++; EAY; _B = RM(EA); break; // LD B,(IY+o) + case /*FD*/0x47: illegal_1(); /*op_47();*/ break; // DB FD + + case /*FD*/0x48: illegal_1(); /*op_48();*/ break; // DB FD + case /*FD*/0x49: illegal_1(); /*op_49();*/ break; // DB FD + case /*FD*/0x4a: illegal_1(); /*op_4a();*/ break; // DB FD + case /*FD*/0x4b: illegal_1(); /*op_4b();*/ break; // DB FD + case /*FD*/0x4c: _R++; _C = _HY; break; // LD C,HY + case /*FD*/0x4d: _R++; _C = _LY; break; // LD C,LY + case /*FD*/0x4e: _R++; EAY; _C = RM(EA); break; // LD C,(IY+o) + case /*FD*/0x4f: illegal_1(); /*op_4f();*/ break; // DB FD + + case /*FD*/0x50: illegal_1(); /*op_50();*/ break; // DB FD + case /*FD*/0x51: illegal_1(); /*op_51();*/ break; // DB FD + case /*FD*/0x52: illegal_1(); /*op_52();*/ break; // DB FD + case /*FD*/0x53: illegal_1(); /*op_53();*/ break; // DB FD + case /*FD*/0x54: _R++; _D = _HY; break; // LD D,HY + case /*FD*/0x55: _R++; _D = _LY; break; // LD D,LY + case /*FD*/0x56: _R++; EAY; _D = RM(EA); break; // LD D,(IY+o) + case /*FD*/0x57: illegal_1(); /*op_57();*/ break; // DB FD + + case /*FD*/0x58: illegal_1(); /*op_58();*/ break; // DB FD + case /*FD*/0x59: illegal_1(); /*op_59();*/ break; // DB FD + case /*FD*/0x5a: illegal_1(); /*op_5a();*/ break; // DB FD + case /*FD*/0x5b: illegal_1(); /*op_5b();*/ break; // DB FD + case /*FD*/0x5c: _R++; _E = _HY; break; // LD E,HY + case /*FD*/0x5d: _R++; _E = _LY; break; // LD E,LY + case /*FD*/0x5e: _R++; EAY; _E = RM(EA); break; // LD E,(IY+o) + case /*FD*/0x5f: illegal_1(); /*op_5f();*/ break; // DB FD + + case /*FD*/0x60: _R++; _HY = _B; break; // LD HY,B + case /*FD*/0x61: _R++; _HY = _C; break; // LD HY,C + case /*FD*/0x62: _R++; _HY = _D; break; // LD HY,D + case /*FD*/0x63: _R++; _HY = _E; break; // LD HY,E + case /*FD*/0x64: _R++; break; // LD HY,HY + case /*FD*/0x65: _R++; _HY = _LY; break; // LD HY,LY + case /*FD*/0x66: _R++; EAY; _H = RM(EA); break; // LD H,(IY+o) + case /*FD*/0x67: _R++; _HY = _A; break; // LD HY,A + + case /*FD*/0x68: _R++; _LY = _B; break; // LD LY,B + case /*FD*/0x69: _R++; _LY = _C; break; // LD LY,C + case /*FD*/0x6a: _R++; _LY = _D; break; // LD LY,D + case /*FD*/0x6b: _R++; _LY = _E; break; // LD LY,E + case /*FD*/0x6c: _R++; _LY = _HY; break; // LD LY,HY + case /*FD*/0x6d: _R++; break; // LD LY,LY + case /*FD*/0x6e: _R++; EAY; _L = RM(EA); break; // LD L,(IY+o) + case /*FD*/0x6f: _R++; _LY = _A; break; // LD LY,A + + case /*FD*/0x70: _R++; EAY; WM( EA, _B ); break; // LD (IY+o),B + case /*FD*/0x71: _R++; EAY; WM( EA, _C ); break; // LD (IY+o),C + case /*FD*/0x72: _R++; EAY; WM( EA, _D ); break; // LD (IY+o),D + case /*FD*/0x73: _R++; EAY; WM( EA, _E ); break; // LD (IY+o),E + case /*FD*/0x74: _R++; EAY; WM( EA, _H ); break; // LD (IY+o),H + case /*FD*/0x75: _R++; EAY; WM( EA, _L ); break; // LD (IY+o),L + case /*FD*/0x76: illegal_1(); /*op_76();*/ break; // DB FD + case /*FD*/0x77: _R++; EAY; WM( EA, _A ); break; // LD (IY+o),A + + case /*FD*/0x78: illegal_1(); /*op_78();*/ break; // DB FD + case /*FD*/0x79: illegal_1(); /*op_79();*/ break; // DB FD + case /*FD*/0x7a: illegal_1(); /*op_7a();*/ break; // DB FD + case /*FD*/0x7b: illegal_1(); /*op_7b();*/ break; // DB FD + case /*FD*/0x7c: _R++; _A = _HY; break; // LD A,HY + case /*FD*/0x7d: _R++; _A = _LY; break; // LD A,LY + case /*FD*/0x7e: _R++; EAY; _A = RM(EA); break; // LD A,(IY+o) + case /*FD*/0x7f: illegal_1(); /*op_7f();*/ break; // DB FD + + case /*FD*/0x80: illegal_1(); /*op_80();*/ break; // DB FD + case /*FD*/0x81: illegal_1(); /*op_81();*/ break; // DB FD + case /*FD*/0x82: illegal_1(); /*op_82();*/ break; // DB FD + case /*FD*/0x83: illegal_1(); /*op_83();*/ break; // DB FD + case /*FD*/0x84: _R++; ADD(_HY); break; // ADD A,HY + case /*FD*/0x85: _R++; ADD(_LY); break; // ADD A,LY + case /*FD*/0x86: _R++; EAY; ADD(RM(EA)); break; // ADD A,(IY+o) + case /*FD*/0x87: illegal_1(); /*op_87();*/ break; // DB FD + + case /*FD*/0x88: illegal_1(); /*op_88();*/ break; // DB FD + case /*FD*/0x89: illegal_1(); /*op_89();*/ break; // DB FD + case /*FD*/0x8a: illegal_1(); /*op_8a();*/ break; // DB FD + case /*FD*/0x8b: illegal_1(); /*op_8b();*/ break; // DB FD + case /*FD*/0x8c: _R++; ADC(_HY); break; // ADC A,HY + case /*FD*/0x8d: _R++; ADC(_LY); break; // ADC A,LY + case /*FD*/0x8e: _R++; EAY; ADC(RM(EA)); break; // ADC A,(IY+o) + case /*FD*/0x8f: illegal_1(); /*op_8f();*/ break; // DB FD + + case /*FD*/0x90: illegal_1(); /*op_90();*/ break; // DB FD + case /*FD*/0x91: illegal_1(); /*op_91();*/ break; // DB FD + case /*FD*/0x92: illegal_1(); /*op_92();*/ break; // DB FD + case /*FD*/0x93: illegal_1(); /*op_93();*/ break; // DB FD + case /*FD*/0x94: _R++; SUB(_HY); break; // SUB HY + case /*FD*/0x95: _R++; SUB(_LY); break; // SUB LY + case /*FD*/0x96: _R++; EAY; SUB(RM(EA)); break; // SUB (IY+o) + case /*FD*/0x97: illegal_1(); /*op_97();*/ break; // DB FD + + case /*FD*/0x98: illegal_1(); /*op_98();*/ break; // DB FD + case /*FD*/0x99: illegal_1(); /*op_99();*/ break; // DB FD + case /*FD*/0x9a: illegal_1(); /*op_9a();*/ break; // DB FD + case /*FD*/0x9b: illegal_1(); /*op_9b();*/ break; // DB FD + case /*FD*/0x9c: _R++; SBC(_HY); break; // SBC A,HY + case /*FD*/0x9d: _R++; SBC(_LY); break; // SBC A,LY + case /*FD*/0x9e: _R++; EAY; SBC(RM(EA)); break; // SBC A,(IY+o) + case /*FD*/0x9f: illegal_1(); /*op_9f();*/ break; // DB FD + + case /*FD*/0xa0: illegal_1(); /*op_a0();*/ break; // DB FD + case /*FD*/0xa1: illegal_1(); /*op_a1();*/ break; // DB FD + case /*FD*/0xa2: illegal_1(); /*op_a2();*/ break; // DB FD + case /*FD*/0xa3: illegal_1(); /*op_a3();*/ break; // DB FD + case /*FD*/0xa4: _R++; AND(_HY); break; // AND HY + case /*FD*/0xa5: _R++; AND(_LY); break; // AND LY + case /*FD*/0xa6: _R++; EAY; AND(RM(EA)); break; // AND (IY+o) + case /*FD*/0xa7: illegal_1(); /*op_a7();*/ break; // DB FD + + case /*FD*/0xa8: illegal_1(); /*op_a8();*/ break; // DB FD + case /*FD*/0xa9: illegal_1(); /*op_a9();*/ break; // DB FD + case /*FD*/0xaa: illegal_1(); /*op_aa();*/ break; // DB FD + case /*FD*/0xab: illegal_1(); /*op_ab();*/ break; // DB FD + case /*FD*/0xac: _R++; XOR(_HY); break; // XOR HY + case /*FD*/0xad: _R++; XOR(_LY); break; // XOR LY + case /*FD*/0xae: _R++; EAY; XOR(RM(EA)); break; // XOR (IY+o) + case /*FD*/0xaf: illegal_1(); /*op_af();*/ break; // DB FD + + case /*FD*/0xb0: illegal_1(); /*op_b0();*/ break; // DB FD + case /*FD*/0xb1: illegal_1(); /*op_b1();*/ break; // DB FD + case /*FD*/0xb2: illegal_1(); /*op_b2();*/ break; // DB FD + case /*FD*/0xb3: illegal_1(); /*op_b3();*/ break; // DB FD + case /*FD*/0xb4: _R++; OR(_HY); break; // OR HY + case /*FD*/0xb5: _R++; OR(_LY); break; // OR LY + case /*FD*/0xb6: _R++; EAY; OR(RM(EA)); break; // OR (IY+o) + case /*FD*/0xb7: illegal_1(); /*op_b7();*/ break; // DB FD + + case /*FD*/0xb8: illegal_1(); /*op_b8();*/ break; // DB FD + case /*FD*/0xb9: illegal_1(); /*op_b9();*/ break; // DB FD + case /*FD*/0xba: illegal_1(); /*op_ba();*/ break; // DB FD + case /*FD*/0xbb: illegal_1(); /*op_bb();*/ break; // DB FD + case /*FD*/0xbc: _R++; CP(_HY); break; // CP HY + case /*FD*/0xbd: _R++; CP(_LY); break; // CP LY + case /*FD*/0xbe: _R++; EAY; CP(RM(EA)); break; // CP (IY+o) + case /*FD*/0xbf: illegal_1(); /*op_bf();*/ break; // DB FD + + case /*FD*/0xc0: illegal_1(); /*op_c0();*/ break; // DB FD + case /*FD*/0xc1: illegal_1(); /*op_c1();*/ break; // DB FD + case /*FD*/0xc2: illegal_1(); /*op_c2();*/ break; // DB FD + case /*FD*/0xc3: illegal_1(); /*op_c3();*/ break; // DB FD + case /*FD*/0xc4: illegal_1(); /*op_c4();*/ break; // DB FD + case /*FD*/0xc5: illegal_1(); /*op_c5();*/ break; // DB FD + case /*FD*/0xc6: illegal_1(); /*op_c6();*/ break; // DB FD + case /*FD*/0xc7: illegal_1(); /*op_c7();*/ break; // DB FD + + case /*FD*/0xc8: illegal_1(); /*op_c8();*/ break; // DB FD + case /*FD*/0xc9: illegal_1(); /*op_c9();*/ break; // DB FD + case /*FD*/0xca: illegal_1(); /*op_ca();*/ break; // DB FD +// pretty sure this is supposed to be ARG + case /*FD*/0xcb: _R++; EAY; EXEC_EA(xycb,ARG(),EA); break; // ** FD CB xx + case /*FD*/0xcc: illegal_1(); /*op_cc();*/ break; // DB FD + case /*FD*/0xcd: illegal_1(); /*op_cd();*/ break; // DB FD + case /*FD*/0xce: illegal_1(); /*op_ce();*/ break; // DB FD + case /*FD*/0xcf: illegal_1(); /*op_cf();*/ break; // DB FD + + case /*FD*/0xd0: illegal_1(); /*op_d0();*/ break; // DB FD + case /*FD*/0xd1: illegal_1(); /*op_d1();*/ break; // DB FD + case /*FD*/0xd2: illegal_1(); /*op_d2();*/ break; // DB FD + case /*FD*/0xd3: illegal_1(); /*op_d3();*/ break; // DB FD + case /*FD*/0xd4: illegal_1(); /*op_d4();*/ break; // DB FD + case /*FD*/0xd5: illegal_1(); /*op_d5();*/ break; // DB FD + case /*FD*/0xd6: illegal_1(); /*op_d6();*/ break; // DB FD + case /*FD*/0xd7: illegal_1(); /*op_d7();*/ break; // DB FD + + case /*FD*/0xd8: illegal_1(); /*op_d8();*/ break; // DB FD + case /*FD*/0xd9: illegal_1(); /*op_d9();*/ break; // DB FD + case /*FD*/0xda: illegal_1(); /*op_da();*/ break; // DB FD + case /*FD*/0xdb: illegal_1(); /*op_db();*/ break; // DB FD + case /*FD*/0xdc: illegal_1(); /*op_dc();*/ break; // DB FD + case /*FD*/0xdd: illegal_1(); /*op_dd();*/ break; // DB FD + case /*FD*/0xde: illegal_1(); /*op_de();*/ break; // DB FD + case /*FD*/0xdf: illegal_1(); /*op_df();*/ break; // DB FD + + case /*FD*/0xe0: illegal_1(); /*op_e0();*/ break; // DB FD + case /*FD*/0xe1: _R++; _IY = POP(); break; // POP IY + case /*FD*/0xe2: illegal_1(); /*op_e2();*/ break; // DB FD + case /*FD*/0xe3: _R++; _IY = EXSP16(_IY); break; // EX (SP),IY + case /*FD*/0xe4: illegal_1(); /*op_e4();*/ break; // DB FD + case /*FD*/0xe5: _R++; PUSH( _IY ); break; // PUSH IY + case /*FD*/0xe6: illegal_1(); /*op_e6();*/ break; // DB FD + case /*FD*/0xe7: illegal_1(); /*op_e7();*/ break; // DB FD + + case /*FD*/0xe8: illegal_1(); /*op_e8();*/ break; // DB FD + case /*FD*/0xe9: _R++; _PC = _IY; break; // JP (IY) + case /*FD*/0xea: illegal_1(); /*op_ea();*/ break; // DB FD + case /*FD*/0xeb: illegal_1(); /*op_eb();*/ break; // DB FD + case /*FD*/0xec: illegal_1(); /*op_ec();*/ break; // DB FD + case /*FD*/0xed: illegal_1(); /*op_ed();*/ break; // DB FD + case /*FD*/0xee: illegal_1(); /*op_ee();*/ break; // DB FD + case /*FD*/0xef: illegal_1(); /*op_ef();*/ break; // DB FD + + case /*FD*/0xf0: illegal_1(); /*op_f0();*/ break; // DB FD + case /*FD*/0xf1: illegal_1(); /*op_f1();*/ break; // DB FD + case /*FD*/0xf2: illegal_1(); /*op_f2();*/ break; // DB FD + case /*FD*/0xf3: illegal_1(); /*op_f3();*/ break; // DB FD + case /*FD*/0xf4: illegal_1(); /*op_f4();*/ break; // DB FD + case /*FD*/0xf5: illegal_1(); /*op_f5();*/ break; // DB FD + case /*FD*/0xf6: illegal_1(); /*op_f6();*/ break; // DB FD + case /*FD*/0xf7: illegal_1(); /*op_f7();*/ break; // DB FD + + case /*FD*/0xf8: illegal_1(); /*op_f8();*/ break; // DB FD + case /*FD*/0xf9: _R++; _SP = _IY; break; // LD SP,IY + case /*FD*/0xfa: illegal_1(); /*op_fa();*/ break; // DB FD + case /*FD*/0xfb: illegal_1(); /*op_fb();*/ break; // DB FD + case /*FD*/0xfc: illegal_1(); /*op_fc();*/ break; // DB FD + case /*FD*/0xfd: illegal_1(); /*op_fd();*/ break; // DB FD + case /*FD*/0xfe: illegal_1(); /*op_fe();*/ break; // DB FD + case /*FD*/0xff: illegal_1(); /*op_ff();*/ break; // DB FD + } +} + +///////////////////////////////////////////////////////////////////////////// + +static EMU_INLINE void z80_exec_normal(struct Z80_STATE *state, uint8 op) { + +//printf("PC=%04X exec normal %02X\n",_PC, op);fflush(stdout); + + switch(op) { + case /*op*/0x00: break; // NOP + case /*op*/0x01: _BC = ARG16(); break; // LD BC,w + case /*op*/0x02: WM(_BC, _A); break; // LD (BC),A + case /*op*/0x03: _BC++; break; // INC BC + case /*op*/0x04: _B = INC(_B); break; // INC B + case /*op*/0x05: _B = DEC(_B); break; // DEC B + case /*op*/0x06: _B = ARG(); break; // LD B,n + case /*op*/0x07: RLCA; break; // RLCA + + case /*op*/0x08: EX_AF; break; // EX AF,AF' + case /*op*/0x09: ADD16(_HL,_BC); break; // ADD HL,BC + case /*op*/0x0A: _A = RM(_BC); break; // LD A,(BC) + case /*op*/0x0B: _BC--; break; // DEC BC + case /*op*/0x0C: _C = INC(_C); break; // INC C + case /*op*/0x0D: _C = DEC(_C); break; // DEC C + case /*op*/0x0E: _C = ARG(); break; // LD C,n + case /*op*/0x0F: RRCA; break; // RRCA + + case /*op*/0x10: _B--; JR_COND( _B, 0x10 ); break; // DJNZ o + case /*op*/0x11: _DE = ARG16(); break; // LD DE,w + case /*op*/0x12: WM( _DE, _A ); break; // LD (DE),A + case /*op*/0x13: _DE++; break; // INC DE + case /*op*/0x14: _D = INC(_D); break; // INC D + case /*op*/0x15: _D = DEC(_D); break; // DEC D + case /*op*/0x16: _D = ARG(); break; // LD D,n + case /*op*/0x17: RLA; break; // RLA + + case /*op*/0x18: JR; break; // JR o + case /*op*/0x19: ADD16(_HL,_DE); break; // ADD HL,DE + case /*op*/0x1A: _A = RM(_DE); break; // LD A,(DE) + case /*op*/0x1B: _DE--; break; // DEC DE + case /*op*/0x1C: _E = INC(_E); break; // INC E + case /*op*/0x1D: _E = DEC(_E); break; // DEC E + case /*op*/0x1E: _E = ARG(); break; // LD E,n + case /*op*/0x1F: RRA; break; // RRA + + case /*op*/0x20: JR_COND( !(_F & ZF), 0x20 ); break; // JR NZ,o + case /*op*/0x21: _HL = ARG16(); break; // LD HL,w + case /*op*/0x22: WM16( ARG16(), _HL ); break; // LD (w),HL + case /*op*/0x23: _HL++; break; // INC HL + case /*op*/0x24: _H = INC(_H); break; // INC H + case /*op*/0x25: _H = DEC(_H); break; // DEC H + case /*op*/0x26: _H = ARG(); break; // LD H,n + case /*op*/0x27: DAA; break; // DAA + + case /*op*/0x28: JR_COND( _F & ZF, 0x28 ); break; // JR Z,o + case /*op*/0x29: ADD16(_HL,_HL); break; // ADD HL,HL + case /*op*/0x2A: _HL = RM16( ARG16() ); break; // LD HL,(w) + case /*op*/0x2B: _HL--; break; // DEC HL + case /*op*/0x2C: _L = INC(_L); break; // INC L + case /*op*/0x2D: _L = DEC(_L); break; // DEC L + case /*op*/0x2E: _L = ARG(); break; // LD L,n + case /*op*/0x2F: _A ^= 0xff; _F = (_F&(SF|ZF|PF|CF))|HF|NF|(_A&(YF|XF)); break; // CPL + + case /*op*/0x30: JR_COND( !(_F & CF), 0x30 ); break; // JR NC,o + case /*op*/0x31: _SP = ARG16(); break; // LD SP,w + case /*op*/0x32: WM( ARG16(), _A ); break; // LD (w),A + case /*op*/0x33: _SP++; break; // INC SP + case /*op*/0x34: WM( _HL, INC(RM(_HL)) ); break; // INC (HL) + case /*op*/0x35: WM( _HL, DEC(RM(_HL)) ); break; // DEC (HL) + case /*op*/0x36: WM( _HL, ARG() ); break; // LD (HL),n + case /*op*/0x37: _F = (_F & (SF|ZF|PF)) | CF | (_A & (YF|XF)); break; // SCF + + case /*op*/0x38: JR_COND( _F & CF, 0x38 ); break; // JR C,o + case /*op*/0x39: ADD16(_HL,_SP); break; // ADD HL,SP + case /*op*/0x3A: _A = RM( ARG16() ); break; // LD A,(w) + case /*op*/0x3B: _SP--; break; // DEC SP + case /*op*/0x3C: _A = INC(_A); break; // INC A + case /*op*/0x3D: _A = DEC(_A); break; // DEC A + case /*op*/0x3E: _A = ARG(); break; // LD A,n + case /*op*/0x3F: _F = ((_F&(SF|ZF|PF|CF))|((_F&CF)<<4)|(_A&(YF|XF)))^CF; break; // CCF + + case /*op*/0x40: break; // LD B,B + case /*op*/0x41: _B = _C; break; // LD B,C + case /*op*/0x42: _B = _D; break; // LD B,D + case /*op*/0x43: _B = _E; break; // LD B,E + case /*op*/0x44: _B = _H; break; // LD B,H + case /*op*/0x45: _B = _L; break; // LD B,L + case /*op*/0x46: _B = RM(_HL); break; // LD B,(HL) + case /*op*/0x47: _B = _A; break; // LD B,A + + case /*op*/0x48: _C = _B; break; // LD C,B + case /*op*/0x49: break; // LD C,C + case /*op*/0x4A: _C = _D; break; // LD C,D + case /*op*/0x4B: _C = _E; break; // LD C,E + case /*op*/0x4C: _C = _H; break; // LD C,H + case /*op*/0x4D: _C = _L; break; // LD C,L + case /*op*/0x4E: _C = RM(_HL); break; // LD C,(HL) + case /*op*/0x4F: _C = _A; break; // LD C,A + + case /*op*/0x50: _D = _B; break; // LD D,B + case /*op*/0x51: _D = _C; break; // LD D,C + case /*op*/0x52: break; // LD D,D + case /*op*/0x53: _D = _E; break; // LD D,E + case /*op*/0x54: _D = _H; break; // LD D,H + case /*op*/0x55: _D = _L; break; // LD D,L + case /*op*/0x56: _D = RM(_HL); break; // LD D,(HL) + case /*op*/0x57: _D = _A; break; // LD D,A + + case /*op*/0x58: _E = _B; break; // LD E,B + case /*op*/0x59: _E = _C; break; // LD E,C + case /*op*/0x5A: _E = _D; break; // LD E,D + case /*op*/0x5B: break; // LD E,E + case /*op*/0x5C: _E = _H; break; // LD E,H + case /*op*/0x5D: _E = _L; break; // LD E,L + case /*op*/0x5E: _E = RM(_HL); break; // LD E,(HL) + case /*op*/0x5F: _E = _A; break; // LD E,A + + case /*op*/0x60: _H = _B; break; // LD H,B + case /*op*/0x61: _H = _C; break; // LD H,C + case /*op*/0x62: _H = _D; break; // LD H,D + case /*op*/0x63: _H = _E; break; // LD H,E + case /*op*/0x64: break; // LD H,H + case /*op*/0x65: _H = _L; break; // LD H,L + case /*op*/0x66: _H = RM(_HL); break; // LD H,(HL) + case /*op*/0x67: _H = _A; break; // LD H,A + + case /*op*/0x68: _L = _B; break; // LD L,B + case /*op*/0x69: _L = _C; break; // LD L,C + case /*op*/0x6A: _L = _D; break; // LD L,D + case /*op*/0x6B: _L = _E; break; // LD L,E + case /*op*/0x6C: _L = _H; break; // LD L,H + case /*op*/0x6D: break; // LD L,L + case /*op*/0x6E: _L = RM(_HL); break; // LD L,(HL) + case /*op*/0x6F: _L = _A; break; // LD L,A + + case /*op*/0x70: WM( _HL, _B ); break; // LD (HL),B + case /*op*/0x71: WM( _HL, _C ); break; // LD (HL),C + case /*op*/0x72: WM( _HL, _D ); break; // LD (HL),D + case /*op*/0x73: WM( _HL, _E ); break; // LD (HL),E + case /*op*/0x74: WM( _HL, _H ); break; // LD (HL),H + case /*op*/0x75: WM( _HL, _L ); break; // LD (HL),L + case /*op*/0x76: HALT; break; // HALT + case /*op*/0x77: WM( _HL, _A ); break; // LD (HL),A + + case /*op*/0x78: _A = _B; break; // LD A,B + case /*op*/0x79: _A = _C; break; // LD A,C + case /*op*/0x7A: _A = _D; break; // LD A,D + case /*op*/0x7B: _A = _E; break; // LD A,E + case /*op*/0x7C: _A = _H; break; // LD A,H + case /*op*/0x7D: _A = _L; break; // LD A,L + case /*op*/0x7E: _A = RM(_HL); break; // LD A,(HL) + case /*op*/0x7F: break; // LD A,A + + case /*op*/0x80: ADD(_B); break; // ADD A,B + case /*op*/0x81: ADD(_C); break; // ADD A,C + case /*op*/0x82: ADD(_D); break; // ADD A,D + case /*op*/0x83: ADD(_E); break; // ADD A,E + case /*op*/0x84: ADD(_H); break; // ADD A,H + case /*op*/0x85: ADD(_L); break; // ADD A,L + case /*op*/0x86: ADD(RM(_HL)); break; // ADD A,(HL) + case /*op*/0x87: ADD(_A); break; // ADD A,A + + case /*op*/0x88: ADC(_B); break; // ADC A,B + case /*op*/0x89: ADC(_C); break; // ADC A,C + case /*op*/0x8A: ADC(_D); break; // ADC A,D + case /*op*/0x8B: ADC(_E); break; // ADC A,E + case /*op*/0x8C: ADC(_H); break; // ADC A,H + case /*op*/0x8D: ADC(_L); break; // ADC A,L + case /*op*/0x8E: ADC(RM(_HL)); break; // ADC A,(HL) + case /*op*/0x8F: ADC(_A); break; // ADC A,A + + case /*op*/0x90: SUB(_B); break; // SUB B + case /*op*/0x91: SUB(_C); break; // SUB C + case /*op*/0x92: SUB(_D); break; // SUB D + case /*op*/0x93: SUB(_E); break; // SUB E + case /*op*/0x94: SUB(_H); break; // SUB H + case /*op*/0x95: SUB(_L); break; // SUB L + case /*op*/0x96: SUB(RM(_HL)); break; // SUB (HL) + case /*op*/0x97: SUB(_A); break; // SUB A + + case /*op*/0x98: SBC(_B); break; // SBC A,B + case /*op*/0x99: SBC(_C); break; // SBC A,C + case /*op*/0x9A: SBC(_D); break; // SBC A,D + case /*op*/0x9B: SBC(_E); break; // SBC A,E + case /*op*/0x9C: SBC(_H); break; // SBC A,H + case /*op*/0x9D: SBC(_L); break; // SBC A,L + case /*op*/0x9E: SBC(RM(_HL)); break; // SBC A,(HL) + case /*op*/0x9F: SBC(_A); break; // SBC A,A + + case /*op*/0xA0: AND(_B); break; // AND B + case /*op*/0xA1: AND(_C); break; // AND C + case /*op*/0xA2: AND(_D); break; // AND D + case /*op*/0xA3: AND(_E); break; // AND E + case /*op*/0xA4: AND(_H); break; // AND H + case /*op*/0xA5: AND(_L); break; // AND L + case /*op*/0xA6: AND(RM(_HL)); break; // AND (HL) + case /*op*/0xA7: AND(_A); break; // AND A + + case /*op*/0xA8: XOR(_B); break; // XOR B + case /*op*/0xA9: XOR(_C); break; // XOR C + case /*op*/0xAA: XOR(_D); break; // XOR D + case /*op*/0xAB: XOR(_E); break; // XOR E + case /*op*/0xAC: XOR(_H); break; // XOR H + case /*op*/0xAD: XOR(_L); break; // XOR L + case /*op*/0xAE: XOR(RM(_HL)); break; // XOR (HL) + case /*op*/0xAF: XOR(_A); break; // XOR A + + case /*op*/0xB0: OR(_B); break; // OR B + case /*op*/0xB1: OR(_C); break; // OR C + case /*op*/0xB2: OR(_D); break; // OR D + case /*op*/0xB3: OR(_E); break; // OR E + case /*op*/0xB4: OR(_H); break; // OR H + case /*op*/0xB5: OR(_L); break; // OR L + case /*op*/0xB6: OR(RM(_HL)); break; // OR (HL) + case /*op*/0xB7: OR(_A); break; // OR A + + case /*op*/0xB8: CP(_B); break; // CP B + case /*op*/0xB9: CP(_C); break; // CP C + case /*op*/0xBA: CP(_D); break; // CP D + case /*op*/0xBB: CP(_E); break; // CP E + case /*op*/0xBC: CP(_H); break; // CP H + case /*op*/0xBD: CP(_L); break; // CP L + case /*op*/0xBE: CP(RM(_HL)); break; // CP (HL) + case /*op*/0xBF: CP(_A); break; // CP A + + case /*op*/0xC0: RET_COND( !(_F & ZF), 0xc0 ); break; // RET NZ + case /*op*/0xC1: _BC = POP(); break; // POP BC + case /*op*/0xC2: JP_COND( !(_F & ZF) ); break; // JP NZ,a + case /*op*/0xC3: JP; break; // JP a + case /*op*/0xC4: CALL_COND( !(_F & ZF), 0xc4 ); break; // CALL NZ,a + case /*op*/0xC5: PUSH( _BC ); break; // PUSH BC + case /*op*/0xC6: ADD(ARG()); break; // ADD A,n + case /*op*/0xC7: RST(0x00); break; // RST 0 + + case /*op*/0xC8: RET_COND( _F & ZF, 0xc8 ); break; // RET Z + case /*op*/0xC9: _PC = POP(); break; // RET + case /*op*/0xCA: JP_COND( _F & ZF ); break; // JP Z,a + case /*op*/0xCB: _R++; EXEC(cb,ROP()); break; // **** CB xx + case /*op*/0xCC: CALL_COND( _F & ZF, 0xcc ); break; // CALL Z,a + case /*op*/0xCD: CALL; break; // CALL a + case /*op*/0xCE: ADC(ARG()); break; // ADC A,n + case /*op*/0xCF: RST(0x08); break; // RST 1 + + case /*op*/0xD0: RET_COND( !(_F & CF), 0xd0 ); break; // RET NC + case /*op*/0xD1: _DE = POP(); break; // POP DE + case /*op*/0xD2: JP_COND( !(_F & CF) ); break; // JP NC,a + case /*op*/0xD3: Z80OUT( ARG() | (_A << 8), _A ); break; // OUT (n),A + case /*op*/0xD4: CALL_COND( !(_F & CF), 0xd4 ); break; // CALL NC,a + case /*op*/0xD5: PUSH( _DE ); break; // PUSH DE + case /*op*/0xD6: SUB(ARG()); break; // SUB n + case /*op*/0xD7: RST(0x10); break; // RST 2 + + case /*op*/0xD8: RET_COND( _F & CF, 0xd8 ); break; // RET C + case /*op*/0xD9: EXX; break; // EXX + case /*op*/0xDA: JP_COND( _F & CF ); break; // JP C,a + case /*op*/0xDB: _A = Z80IN( ARG() | (_A << 8) ); break; // IN A,(n) + case /*op*/0xDC: CALL_COND( _F & CF, 0xdc ); break; // CALL C,a + case /*op*/0xDD: _R++; EXEC(dd,ROP()); break; // **** DD xx + case /*op*/0xDE: SBC(ARG()); break; // SBC A,n + case /*op*/0xDF: RST(0x18); break; // RST 3 + + case /*op*/0xE0: RET_COND( !(_F & PF), 0xe0 ); break; // RET PO + case /*op*/0xE1: _HL = POP(); break; // POP HL + case /*op*/0xE2: JP_COND( !(_F & PF) ); break; // JP PO,a + case /*op*/0xE3: _HL = EXSP16(_HL); break; // EX HL,(SP) + case /*op*/0xE4: CALL_COND( !(_F & PF), 0xe4 ); break; // CALL PO,a + case /*op*/0xE5: PUSH( _HL ); break; // PUSH HL + case /*op*/0xE6: AND(ARG()); break; // AND n + case /*op*/0xE7: RST(0x20); break; // RST 4 + + case /*op*/0xE8: RET_COND( _F & PF, 0xe8 ); break; // RET PE + case /*op*/0xE9: _PC = _HL; break; // JP (HL) + case /*op*/0xEA: JP_COND( _F & PF ); break; // JP PE,a + case /*op*/0xEB: EX_DE_HL; break; // EX DE,HL + case /*op*/0xEC: CALL_COND( _F & PF, 0xec ); break; // CALL PE,a + case /*op*/0xED: _R++; EXEC(ed,ROP()); break; // **** ED xx + case /*op*/0xEE: XOR(ARG()); break; // XOR n + case /*op*/0xEF: RST(0x28); break; // RST 5 + + case /*op*/0xF0: RET_COND( !(_F & SF), 0xf0 ); break; // RET P + case /*op*/0xF1: _AF = POP(); break; // POP AF + case /*op*/0xF2: JP_COND( !(_F & SF) ); break; // JP P,a + case /*op*/0xF3: DI; break; // DI + case /*op*/0xF4: CALL_COND( !(_F & SF), 0xf4 ); break; // CALL P,a + case /*op*/0xF5: PUSH( _AF ); break; // PUSH AF + case /*op*/0xF6: OR(ARG()); break; // OR n + case /*op*/0xF7: RST(0x30); break; // RST 6 + + case /*op*/0xF8: RET_COND( _F & SF, 0xf8 ); break; // RET M + case /*op*/0xF9: _SP = _HL; break; // LD SP,HL + case /*op*/0xFA: JP_COND(_F & SF); break; // JP M,a + case /*op*/0xFB: EI; break; // EI + case /*op*/0xFC: CALL_COND( _F & SF, 0xfc ); break; // CALL M,a + case /*op*/0xFD: _R++; EXEC(fd,ROP()); break; // **** FD xx + case /*op*/0xFE: CP(ARG()); break; // CP n + case /*op*/0xFF: RST(0x38); break; // RST 7 + } +} + +///////////////////////////////////////////////////////////////////////////// +// +// Returns -1 on error +// +sint32 EMU_CALL z80_execute(void *state, sint32 cycles) { + + if(STATE->imflags & IMFLAGS_BADINS) return -1; + + STATE->cycles_remaining_last_checkpoint = cycles; + STATE->cycles_remaining = cycles; + STATE->cycles_deferred_from_break = 0; + + if(STATE->imflags & IMFLAGS_HALT) { STATE->cycles_remaining = 0; } + +#ifdef TESTZ80 +testz80_newins(); +#endif + checkinterrupts(STATE); +#ifdef TESTZ80 +if(testz80_irq) { testz80_subrst38h(); testz80_irq = 0; } +testz80_compareregs(); +#endif + + while(STATE->cycles_remaining > 0) { +//printf("z80 pc=%04X\n",_PC);fflush(stdout); +#ifdef TESTZ80 +testz80_newins(); +#endif + _R++; EXEC(normal,ROP()); +#ifdef TESTZ80 +testz80_subexec(); +if(testz80_irq) { testz80_subrst38h(); testz80_irq = 0; } +testz80_compareregs(); +#endif + } + + STATE->cycles_remaining_last_checkpoint += STATE->cycles_deferred_from_break; + STATE->cycles_remaining += STATE->cycles_deferred_from_break; + STATE->cycles_deferred_from_break = 0; + + hw_sync(state); + return (STATE->imflags & IMFLAGS_BADINS) ? -1 : 0; +} + +///////////////////////////////////////////////////////////////////////////// diff --git a/Frameworks/HighlyQuixotic/HighlyQuixotic/Core/z80.h b/Frameworks/HighlyQuixotic/HighlyQuixotic/Core/z80.h new file mode 100644 index 000000000..007d6c035 --- /dev/null +++ b/Frameworks/HighlyQuixotic/HighlyQuixotic/Core/z80.h @@ -0,0 +1,64 @@ +///////////////////////////////////////////////////////////////////////////// +// +// z80 - Emulates Z80 CPU +// +///////////////////////////////////////////////////////////////////////////// + +#ifndef __Q_Z80_H__ +#define __Q_Z80_H__ + +#include "emuconfig.h" + +#ifdef __cplusplus +extern "C" { +#endif + +sint32 EMU_CALL z80_init(void); +uint32 EMU_CALL z80_get_state_size(void); +void EMU_CALL z80_clear_state(void *state); + +typedef uint8 (EMU_CALL * z80_read_callback_t )(void *hwstate, uint16 a ); +typedef void (EMU_CALL * z80_write_callback_t )(void *hwstate, uint16 a, uint8 d); +typedef void (EMU_CALL * z80_advance_callback_t)(void *hwstate, uint32 cycles); + +struct Z80_MEMORY_TYPE { uint16 mask, n; void *p; }; +struct Z80_MEMORY_MAP { uint16 x, y; struct Z80_MEMORY_TYPE type; }; +#define Z80_MAP_TYPE_POINTER (0) +#define Z80_MAP_TYPE_CALLBACK (1) + +void EMU_CALL z80_set_memory_maps( + void *state, + struct Z80_MEMORY_MAP *map_op, + struct Z80_MEMORY_MAP *map_read, + struct Z80_MEMORY_MAP *map_write, + struct Z80_MEMORY_MAP *map_in, + struct Z80_MEMORY_MAP *map_out +); +void EMU_CALL z80_set_advance_callback( + void *state, + z80_advance_callback_t advance, + void *hwstate +); + +//uint32 EMU_CALL z80_getreg(void *state, sint32 regnum); +//void EMU_CALL z80_setreg(void *state, sint32 regnum, uint32 value); + +uint16 EMU_CALL z80_getpc(void *state); + +void EMU_CALL z80_setirq(void *state, uint8 irq, uint8 vector); +void EMU_CALL z80_setnmi(void *state, uint8 nmi); +void EMU_CALL z80_break(void *state); + +// +// Returns 0 or positive on success +// Returns negative on error +// (value is otherwise meaningless for now) +// Performs all advance calls according to how many cycles it actually executed +// +sint32 EMU_CALL z80_execute(void *state, sint32 cycles); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Frameworks/HighlyQuixotic/HighlyQuixotic/HighlyQuixotic-Info.plist b/Frameworks/HighlyQuixotic/HighlyQuixotic/HighlyQuixotic-Info.plist new file mode 100644 index 000000000..02c2a8310 --- /dev/null +++ b/Frameworks/HighlyQuixotic/HighlyQuixotic/HighlyQuixotic-Info.plist @@ -0,0 +1,30 @@ + + + + + CFBundleDevelopmentRegion + English + CFBundleExecutable + ${EXECUTABLE_NAME} + CFBundleIconFile + + CFBundleIdentifier + NoWork-Inc.${PRODUCT_NAME:rfc1034identifier} + CFBundleInfoDictionaryVersion + 6.0 + CFBundleName + ${PRODUCT_NAME} + CFBundlePackageType + FMWK + CFBundleShortVersionString + 1.0 + CFBundleSignature + ???? + CFBundleVersion + 1 + NSHumanReadableCopyright + Copyright © 2013 Christopher Snowhill. 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If your program is a subroutine library, you +may consider it more useful to permit linking proprietary applications with +the library. If this is what you want to do, use the GNU Lesser General +Public License instead of this License. But first, please read +. diff --git a/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/Core.pro b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/Core.pro new file mode 100644 index 000000000..a8ef5fcb5 --- /dev/null +++ b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/Core.pro @@ -0,0 +1,53 @@ +#------------------------------------------------- +# +# Project created by QtCreator 2012-12-26T20:57:48 +# +#------------------------------------------------- + +QT -= core gui + +TARGET = SegaCore +TEMPLATE = lib +CONFIG += staticlib + +# C68K: C68K_NO_JUMP_TABLE +# M68K: USE_M68K and LSB_FIRST if host is little endian +# Starscream: USE_STARSCREAM + +DEFINES += EMU_COMPILE EMU_LITTLE_ENDIAN HAVE_STDINT_H USE_M68K LSB_FIRST HAVE_MPROTECT + +SOURCES += \ + sega.c \ + dcsound.c \ + satsound.c \ + yam.c \ + arm.c \ + m68k/m68kops.c \ + m68k/m68kcpu.c + +HEADERS += \ + sega.h \ + dcsound.h \ + satsound.h \ + emuconfig.h \ + yam.h \ + arm.h \ + m68k/m68kconf.h \ + m68k/m68kcpu.h \ + m68k/m68k.h \ + m68k/m68kops.h \ + m68k/macros.h +unix:!symbian { + maemo5 { + target.path = /opt/usr/lib + } else { + target.path = /usr/lib + } + INSTALLS += target +} + +OTHER_FILES += \ + COPYING.txt \ + Readme.txt \ + m68k/m68k_in.c \ + m68k/m68kmake.c diff --git a/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/Readme.txt b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/Readme.txt new file mode 100644 index 000000000..bc463977c --- /dev/null +++ b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/Readme.txt @@ -0,0 +1,30 @@ +SegaCore - Saturn and Dreamcast sound emulation + + +The Saturn (SCSP) and Dreamcast (AICA) use almost-identical sound chips both +made by Yamaha, so it's effective to emulate them both using the same code. +They only differ slightly in which features they support. + +To name a few specifics: + + SCSP AICA + ---- ---- +Channels 32 64 +DSP multiplier constants 64 128 +FM support Yes No +4-bit ADPCM samples No Yes + +(The FM support is pretty cool - pretty much arbitrary connections between +channels. Emulating it would be really inefficient, though.) + + +yam.c is the heart and does most of the sound chip emulation. + +dcsound.c and satsound.c are simply front ends for yam.c. + +arm.c handles ARM7 emulation (Dreamcast) and is tragically slow at the moment. + +Starscream handles 68000 emulation (Saturn) and is as speedy as you'd expect. +The version used here is "0.27" which I never made official. The only +difference from 0.26 is that I added a state pointer (EBP) and reshuffled some +of the other registers around. diff --git a/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/SegaCore.vcxproj b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/SegaCore.vcxproj new file mode 100644 index 000000000..c97b1f30b --- /dev/null +++ b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/SegaCore.vcxproj @@ -0,0 +1,176 @@ + + + + + Debug + Win32 + + + Release + Win32 + + + + {D284D37A-BC6D-44BA-AF92-C0713EB8BE21} + + + + + + + + + + + + StaticLibrary + Unicode + true + v100 + + + StaticLibrary + Unicode + v100 + + + + + + + + + + + + + + + <_ProjectFileVersion>10.0.21006.1 + AllRules.ruleset + + + AllRules.ruleset + + + + + + Disabled + OnlyExplicitInline + WIN32;USE_M68K;LSB_FIRST;_DEBUG;_LIB;EMU_COMPILE;EMU_LITTLE_ENDIAN;%(PreprocessorDefinitions) + EnableFastChecks + MultiThreadedDebug + .\Debug/SegaCore.pch + .\Debug/ + .\Debug/ + .\Debug/ + Level3 + true + ProgramDatabase + FastCall + + + _DEBUG;%(PreprocessorDefinitions) + 0x0409 + + + true + + + + + MaxSpeed + AnySuitable + true + Speed + true + WIN32;USE_STARSCREAM;NDEBUG;_LIB;EMU_COMPILE;EMU_LITTLE_ENDIAN;%(PreprocessorDefinitions) + true + MultiThreaded + false + true + .\Release/SegaCore.pch + .\Release/ + .\Release/ + .\Release/ + Level3 + true + FastCall + + + NDEBUG;%(PreprocessorDefinitions) + 0x0409 + + + true + + + + + + WIN32;C68K_NO_JUMP_TABLE;_DEBUG;_LIB;EMU_COMPILE;EMU_LITTLE_ENDIAN;%(PreprocessorDefinitions) + WIN32;C68K_NO_JUMP_TABLE;NDEBUG;_LIB;EMU_COMPILE;EMU_LITTLE_ENDIAN;%(PreprocessorDefinitions) + true + true + + + WIN32;C68K_NO_JUMP_TABLE;_DEBUG;_LIB;EMU_COMPILE;EMU_LITTLE_ENDIAN;%(PreprocessorDefinitions) + WIN32;C68K_NO_JUMP_TABLE;NDEBUG;_LIB;EMU_COMPILE;EMU_LITTLE_ENDIAN;%(PreprocessorDefinitions) + true + true + + + + true + + + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/SegaCore.vcxproj.filters b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/SegaCore.vcxproj.filters new file mode 100644 index 000000000..458a93f39 --- /dev/null +++ b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/SegaCore.vcxproj.filters @@ -0,0 +1,151 @@ + + + + + {fa08c089-e29d-41b4-a0ec-df151f82f17d} + h;hpp;hxx;hm;inl + + + {61a513d4-d05c-48e9-9199-903526c7098a} + cpp;c;cxx;rc;def;r;odl;idl;hpj;bat + + + {f00dacbe-f20a-49f6-9151-c41e4ce2752b} + + + {b62210c8-e7eb-4724-be9b-f7e5509f30df} + + + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + C68K + + + C68K + + + m68k + + + m68k + + + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + C68K + + + C68K + + + m68k + + + m68k + + + m68k + + + m68k + + + m68k + + + + + + + + C68K + + + C68K + + + C68K + + + C68K + + + C68K + + + C68K + + + C68K + + + C68K + + + C68K + + + C68K + + + C68K + + + C68K + + + C68K + + + C68K + + + C68K + + + C68K + + + C68K + + + C68K + + + m68k + + + \ No newline at end of file diff --git a/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/Starscream/cpudebug.c b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/Starscream/cpudebug.c new file mode 100644 index 000000000..7c8b5cb1a --- /dev/null +++ b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/Starscream/cpudebug.c @@ -0,0 +1,1375 @@ +/* +** Starscream 680x0 emulation library +** Copyright 1997, 1998, 1999 Neill Corlett +** +** Refer to STARDOC.TXT for terms of use, API reference, and directions on +** how to compile. +*/ + +#include +#include +#include +#include +#include +#include "starcpu.h" +#include "cpudebug.h" + +static void *starcontext; + +static void cpudebug_gets(char *s, int n) { +// if(cpudebug_get) cpudebug_get(s, n); +// else + fgets(s, n, stdin); +} + +static void cpudebug_putc(char c) { + static char buffer[100]; + static unsigned l = 0; + buffer[l++] = c; + if((c == '\n') || (l == (sizeof(buffer) - 1))) { + buffer[l] = 0; +// if(cpudebug_put) cpudebug_put(buffer); +// else + fputs(buffer, stdout); + l = 0; + } +} + +static void cpudebug_printf(const char *fmt, ...) { + static char buffer[400]; + char *s = buffer; + va_list ap; + va_start(ap, fmt); + vsprintf(s, fmt, ap); + va_end(ap); + while(*s) cpudebug_putc(*s++); +} + +#define byte unsigned char +#define word unsigned short int +#define dword unsigned int + +#define int08 signed char +#define int16 signed short int +#define int32 signed int + +#define ea eacalc[inst&0x3F]() + +/****************************** +** SNAGS / EA CONSIDERATIONS ** +******************************* + +- ADDX is encoded the same way as ADD->ea +- SUBX is encoded the same way as SUB->ea +- ABCD is encoded the same way as AND->ea +- EXG is encoded the same way as AND->ea +- SBCD is encoded the same way as OR->ea +- EOR is encoded the same way as CMPM +- ASR is encoded the same way as LSR + (so are LSL and ASL, but they do the same thing) +- Bcc does NOT support 32-bit offsets on the 68000. + (this is a reminder, don't bother implementing 32-bit offsets!) +- Look on p. 3-19 for how to calculate branch conditions (GE, LT, GT, etc.) +- Bit operations are 32-bit for registers, 8-bit for memory locations. +- MOVEM->memory is encoded the same way as EXT + If the EA is just a register, then it's EXT, otherwise it's MOVEM. +- MOVEP done the same way as the bit operations +- Scc done the same way as DBcc. + Assume it's Scc, unless the EA is a direct An mode (then it's a DBcc). +- SWAP done the same way as PEA +- TAS done the same way as ILLEGAL + +- LINK, NOP, RTR, RTS, TRAP, TRAPV, UNLK are encoded the same way. + +******************************/ + +#define hex08 "%02X" +#define hex16 "%04X" +#define hex32 "%08X" +#define hexlong "%06X" + +#define isregister ((inst&0x0030)==0x0000) +#define isaddressr ((inst&0x0038)==0x0008) + +static char eabuffer[20],sdebug[80]; +static dword debugpc,hexaddr; +static int isize; +static word inst; + +static word fetch(void){ + debugpc+=2; + isize+=2; + return(s68000fetch(starcontext,debugpc-2)&0xFFFF); +} + +static dword fetchl(void){ + dword t; + t=(s68000fetch(starcontext,debugpc)&0xFFFF); + t<<=16; + t|=(s68000fetch(starcontext,debugpc+2)&0xFFFF); + debugpc+=4; + isize+=4; + return t; +} + +static int08 opsize[1024]={ +1,2,4,0,0,0,0,0,1,2,4,0,0,0,0,0,1,2,4,0,0,0,0,0,1,2,4,0,0,0,0,0, +0,0,0,0,0,0,0,0,1,2,4,0,0,0,0,0,1,2,4,0,0,0,0,0,0,0,0,0,0,0,0,0, +1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, +1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, +4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4, +4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4, +2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2, +2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2, +1,2,4,2,0,0,2,4,1,2,4,1,0,0,2,4,1,2,4,1,0,0,2,4,1,2,4,2,0,0,2,4, +1,4,2,4,0,0,2,4,1,2,4,1,0,0,2,4,0,0,2,4,0,0,2,4,0,2,0,0,0,0,2,4, +1,2,4,0,1,2,4,0,1,2,4,0,1,2,4,0,1,2,4,0,1,2,4,0,1,2,4,0,1,2,4,0, +1,2,4,0,1,2,4,0,1,2,4,0,1,2,4,0,1,2,4,0,1,2,4,0,1,2,4,0,1,2,4,0, +0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, +0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, +4,4,4,4,0,0,0,0,4,4,4,4,0,0,0,0,4,4,4,4,0,0,0,0,4,4,4,4,0,0,0,0, +4,4,4,4,0,0,0,0,4,4,4,4,0,0,0,0,4,4,4,4,0,0,0,0,4,4,4,4,0,0,0,0, +1,2,4,2,1,2,4,2,1,2,4,2,1,2,4,2,1,2,4,2,1,2,4,2,1,2,4,2,1,2,4,2, +1,2,4,2,1,2,4,2,1,2,4,2,1,2,4,2,1,2,4,2,1,2,4,2,1,2,4,2,1,2,4,2, +1,2,4,2,1,2,4,4,1,2,4,2,1,2,4,4,1,2,4,2,1,2,4,4,1,2,4,2,1,2,4,4, +1,2,4,2,1,2,4,4,1,2,4,2,1,2,4,4,1,2,4,2,1,2,4,4,1,2,4,2,1,2,4,4, +0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, +0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, +1,2,4,2,1,2,4,4,1,2,4,2,1,2,4,4,1,2,4,2,1,2,4,4,1,2,4,2,1,2,4,4, +1,2,4,2,1,2,4,4,1,2,4,2,1,2,4,4,1,2,4,2,1,2,4,4,1,2,4,2,1,2,4,4, +1,2,4,2,1,2,4,2,1,2,4,2,1,2,4,2,1,2,4,2,1,2,4,2,1,2,4,2,1,2,4,2, +1,2,4,2,1,2,4,2,1,2,4,2,1,2,4,2,1,2,4,2,1,2,4,2,1,2,4,2,1,2,4,2, +1,2,4,2,1,2,4,4,1,2,4,2,1,2,4,4,1,2,4,2,1,2,4,4,1,2,4,2,1,2,4,4, +1,2,4,2,1,2,4,4,1,2,4,2,1,2,4,4,1,2,4,2,1,2,4,4,1,2,4,2,1,2,4,4, +1,2,4,2,1,2,4,2,1,2,4,2,1,2,4,2,1,2,4,2,1,2,4,2,1,2,4,2,1,2,4,2, +1,2,4,0,1,2,4,0,1,2,4,0,1,2,4,0,1,2,4,0,1,2,4,0,1,2,4,0,1,2,4,0, +0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, +0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; + +/******************** EA GENERATION ********************/ + +/* These are the functions to generate effective addresses. + Here is the syntax: + + eacalc[mode](); + + mode is the EA mode << 3 + register number + + The function sets addr so you can use m68read and m68write. + + These routines screw around with the PC, and might call fetch() a couple + times to get extension words. Place the eacalc() calls strategically to + get the extension words in the right order. +*/ + +/* These are the jump tables for EA calculation. + drd = data reg direct Dn + ard = address reg direct An + ari = address reg indirect (An) + ari_inc = address reg indirect, postincrement (An)+ + ari_dec = address reg indirect, predecrement -(An) + ari_dis = address reg indirect, displacement (d16,An) + ari_ind = address reg indirect, index (d8,An,Xn) + pci_dis = prog. counter indirect, displacement (d16,PC) + pci_ind = prog. counter indirect, index (d8,PC,Xn) +*/ + +#define eacalc_drd(n,r) static void n(void){sprintf(eabuffer,"d%d",r);} +#define eacalc_ard(n,r) static void n(void){sprintf(eabuffer,"a%d",r);} +#define eacalc_ari(n,r) static void n(void){sprintf(eabuffer,"(a%d)",r);} +#define eacalc_ari_inc(n,r) static void n(void){sprintf(eabuffer,"(a%d)+",r);} +#define eacalc_ari_dec(n,r) static void n(void){sprintf(eabuffer,"-(a%d)",r);} +#define eacalc_ari_dis(n,r) static void n(void){\ + int16 briefext=fetch();\ + sprintf(eabuffer,"%c$" hex16 "(a%d)",(briefext<0)?'-':'+',(briefext<0)?-briefext:briefext,r);\ +} +#define eacalc_ari_ind(n,r) static void n(void){\ + int16 briefext=fetch();\ + if(briefext<0)sprintf(eabuffer,"-$" hex08 "(a%d,%c%d.%c)",\ + (int08)-briefext,r,\ + briefext&0x8000?'a':'d',(briefext>>12)&7,\ + briefext&0x800?'l':'w');\ + else sprintf(eabuffer,"+$" hex08 "(a%d,%c%d.%c)",\ + (int08)briefext,r,\ + briefext&0x8000?'a':'d',(briefext>>12)&7,\ + briefext&0x800?'l':'w');\ +} +eacalc_drd(ea_0_0,0) +eacalc_drd(ea_0_1,1) +eacalc_drd(ea_0_2,2) +eacalc_drd(ea_0_3,3) +eacalc_drd(ea_0_4,4) +eacalc_drd(ea_0_5,5) +eacalc_drd(ea_0_6,6) +eacalc_drd(ea_0_7,7) +eacalc_ard(ea_1_0,0) +eacalc_ard(ea_1_1,1) +eacalc_ard(ea_1_2,2) +eacalc_ard(ea_1_3,3) +eacalc_ard(ea_1_4,4) +eacalc_ard(ea_1_5,5) +eacalc_ard(ea_1_6,6) +eacalc_ard(ea_1_7,7) +eacalc_ari(ea_2_0,0) +eacalc_ari(ea_2_1,1) +eacalc_ari(ea_2_2,2) +eacalc_ari(ea_2_3,3) +eacalc_ari(ea_2_4,4) +eacalc_ari(ea_2_5,5) +eacalc_ari(ea_2_6,6) +eacalc_ari(ea_2_7,7) +eacalc_ari_inc(ea_3_0,0) +eacalc_ari_inc(ea_3_1,1) +eacalc_ari_inc(ea_3_2,2) +eacalc_ari_inc(ea_3_3,3) +eacalc_ari_inc(ea_3_4,4) +eacalc_ari_inc(ea_3_5,5) +eacalc_ari_inc(ea_3_6,6) +eacalc_ari_inc(ea_3_7,7) +eacalc_ari_dec(ea_4_0,0) +eacalc_ari_dec(ea_4_1,1) +eacalc_ari_dec(ea_4_2,2) +eacalc_ari_dec(ea_4_3,3) +eacalc_ari_dec(ea_4_4,4) +eacalc_ari_dec(ea_4_5,5) +eacalc_ari_dec(ea_4_6,6) +eacalc_ari_dec(ea_4_7,7) +eacalc_ari_dis(ea_5_0,0) +eacalc_ari_dis(ea_5_1,1) +eacalc_ari_dis(ea_5_2,2) +eacalc_ari_dis(ea_5_3,3) +eacalc_ari_dis(ea_5_4,4) +eacalc_ari_dis(ea_5_5,5) +eacalc_ari_dis(ea_5_6,6) +eacalc_ari_dis(ea_5_7,7) +eacalc_ari_ind(ea_6_0,0) +eacalc_ari_ind(ea_6_1,1) +eacalc_ari_ind(ea_6_2,2) +eacalc_ari_ind(ea_6_3,3) +eacalc_ari_ind(ea_6_4,4) +eacalc_ari_ind(ea_6_5,5) +eacalc_ari_ind(ea_6_6,6) +eacalc_ari_ind(ea_6_7,7) + +/* These are the "special" addressing modes: + abshort absolute short address + abslong absolute long address + immdata immediate data +*/ + +static void eacalcspecial_abshort(void){ + word briefext; + briefext=fetch(); + sprintf(eabuffer,"($" hex16 ")",briefext); +} + +static void eacalcspecial_abslong(void){ + dword briefext; + briefext=fetch(); + briefext<<=16; + briefext|=fetch(); + sprintf(eabuffer,"($"hexlong")",briefext); +} + +static void eacalcspecial_immdata(void){ + dword briefext; + switch(opsize[inst>>6]){ + case 1: + briefext=fetch()&0xFF; + sprintf(eabuffer,"#$" hex08,briefext); + break; + case 2: + briefext=fetch(); + sprintf(eabuffer,"#$" hex16,briefext); + break; + default: + briefext=fetch(); + briefext<<=16; + briefext|=fetch(); + sprintf(eabuffer,"#$" hex32,briefext); + break; + } +} + +static void eacalcspecial_pci_dis(void){ + dword dpc = debugpc; + word briefext = fetch(); + sprintf(eabuffer,"$" hexlong "(pc)",((int16)(briefext))+dpc); +} + +static void eacalcspecial_pci_ind(void){ + dword dpc = debugpc; + word briefext = fetch(); + sprintf(eabuffer,"$" hexlong "(pc,%c%d)", + ((int08)(briefext))+dpc, + briefext&0x8000?'a':'d',(briefext>>12)&7); +} + +static void eacalcspecial_unknown(void){ + sprintf(eabuffer,"*** UNKNOWN EA MODE ***"); +} + +static void (*(eacalc[64]))(void)={ +ea_0_0,ea_0_1,ea_0_2,ea_0_3,ea_0_4,ea_0_5,ea_0_6,ea_0_7, +ea_1_0,ea_1_1,ea_1_2,ea_1_3,ea_1_4,ea_1_5,ea_1_6,ea_1_7, +ea_2_0,ea_2_1,ea_2_2,ea_2_3,ea_2_4,ea_2_5,ea_2_6,ea_2_7, +ea_3_0,ea_3_1,ea_3_2,ea_3_3,ea_3_4,ea_3_5,ea_3_6,ea_3_7, +ea_4_0,ea_4_1,ea_4_2,ea_4_3,ea_4_4,ea_4_5,ea_4_6,ea_4_7, +ea_5_0,ea_5_1,ea_5_2,ea_5_3,ea_5_4,ea_5_5,ea_5_6,ea_5_7, +ea_6_0,ea_6_1,ea_6_2,ea_6_3,ea_6_4,ea_6_5,ea_6_6,ea_6_7, +eacalcspecial_abshort,eacalcspecial_abslong,eacalcspecial_pci_dis,eacalcspecial_pci_ind, +eacalcspecial_immdata,eacalcspecial_unknown,eacalcspecial_unknown,eacalcspecial_unknown}; + +static void m68unsupported(void){ + sprintf(sdebug,"*** NOT RECOGNIZED ***"); +} + +static void m68_unrecog_x(void){ + sprintf(sdebug,"unrecognized"); +} + +/******************** BIT TEST-AND-____ ********************/ + +static void m68_bitopdn_x(void){ + int16 d16; + if((inst&0x38)==0x08){ + d16=fetch(); + sprintf(eabuffer,"%c$" hex16 "(a%d)",(d16<0)?'-':'+',(d16<0)?-d16:d16,inst&7); + if(!(inst&0x80)){ + sprintf(sdebug,"movep%s %s,d%d", + ((inst&0x40)==0x40)?".l":" ", + eabuffer,inst>>9 + ); + }else{ + sprintf(sdebug,"movep%s d%d,%s", + ((inst&0x40)==0x40)?".l":" ", + inst>>9,eabuffer + ); + } + }else{ + ea; + switch((inst>>6)&3){ + case 0:sprintf(sdebug,"btst d%d,%s",inst>>9,eabuffer);break; + case 1:sprintf(sdebug,"bchg d%d,%s",inst>>9,eabuffer);break; + case 2:sprintf(sdebug,"bclr d%d,%s",inst>>9,eabuffer);break; + case 3:sprintf(sdebug,"bset d%d,%s",inst>>9,eabuffer);break; + default:break; + } + } +} + +#define bittest_st(name,dump) static void name(void){\ + byte shiftby=(fetch()&0xFF);\ + ea;sprintf(sdebug,"%s #$"hex08",%s",dump,shiftby,eabuffer);\ +} + +bittest_st(m68_btst_st_x,"btst") +bittest_st(m68_bclr_st_x,"bclr") +bittest_st(m68_bset_st_x,"bset") +bittest_st(m68_bchg_st_x,"bchg") + +/******************** Bcc ********************/ + +#define conditional_branch(name,dump) static void name(void){\ + int16 disp;\ + int32 currentpc=debugpc;\ + disp=(int08)(inst&0xFF);\ + if(!disp)disp=fetch();\ + sprintf(sdebug,"%s ($"hexlong")",dump,currentpc+disp);\ +} + +conditional_branch(m68_bra_____x,"bra") +conditional_branch(m68_bhi_____x,"bhi") +conditional_branch(m68_bls_____x,"bls") +conditional_branch(m68_bcc_____x,"bcc") +conditional_branch(m68_bcs_____x,"bcs") +conditional_branch(m68_bne_____x,"bne") +conditional_branch(m68_beq_____x,"beq") +conditional_branch(m68_bvc_____x,"bvc") +conditional_branch(m68_bvs_____x,"bvs") +conditional_branch(m68_bpl_____x,"bpl") +conditional_branch(m68_bmi_____x,"bmi") +conditional_branch(m68_bge_____x,"bge") +conditional_branch(m68_blt_____x,"blt") +conditional_branch(m68_bgt_____x,"bgt") +conditional_branch(m68_ble_____x,"ble") + +/******************** Scc, DBcc ********************/ + +#define scc_dbcc(name,dump1,dump2)\ +static void name(void){\ + ea;if(isaddressr){\ + int16 disp;\ + disp=fetch();\ + sprintf(sdebug,"%s d%d,($"hexlong")",dump2,inst&7,debugpc+disp-2);\ + }else sprintf(sdebug,"%s %s",dump1,eabuffer);\ +} + +scc_dbcc(m68_st______x,"st ","dbt ") +scc_dbcc(m68_sf______x,"sf ","dbra") +scc_dbcc(m68_shi_____x,"shi","dbhi") +scc_dbcc(m68_sls_____x,"sls","dbls") +scc_dbcc(m68_scc_____x,"scc","dbcc") +scc_dbcc(m68_scs_____x,"scs","dbcs") +scc_dbcc(m68_sne_____x,"sne","dbne") +scc_dbcc(m68_seq_____x,"seq","dbeq") +scc_dbcc(m68_svc_____x,"svc","dbvc") +scc_dbcc(m68_svs_____x,"svs","dbvs") +scc_dbcc(m68_spl_____x,"spl","dbpl") +scc_dbcc(m68_smi_____x,"smi","dbmi") +scc_dbcc(m68_sge_____x,"sge","dbge") +scc_dbcc(m68_slt_____x,"slt","dblt") +scc_dbcc(m68_sgt_____x,"sgt","dbgt") +scc_dbcc(m68_sle_____x,"sle","dble") + +/******************** JMP ********************/ + +static void m68_jmp_____x(void){ea;sprintf(sdebug,"jmp %s",eabuffer);} + +/******************** JSR/BSR ********************/ + +static void m68_jsr_____x(void){ea;sprintf(sdebug,"jsr %s",eabuffer);} + +static void m68_bsr_____x(void){ + int16 disp; + int32 currentpc=debugpc; + disp=(int08)(inst&0xFF); + if(!disp)disp=fetch(); + sprintf(sdebug,"%s ($"hexlong")","bsr",disp+currentpc); +} + +/******************** TAS ********************/ + +/* Test-and-set / illegal */ +static void m68_tas_____b(void){ + if(inst==0x4AFC){ + sprintf(sdebug,"illegal"); + }else{ + ea; + sprintf(sdebug,"tas %s",eabuffer); + } +} + +/******************** LEA ********************/ + +static void m68_lea___n_l(void){ + ea;sprintf(sdebug,"lea %s,a%d",eabuffer,(inst>>9)&7); +} + +/******************** PEA ********************/ + +static void m68_pea_____l(void){ + ea;if(isregister){/* SWAP Dn */ + sprintf(sdebug,"swap d%d",inst&7); + }else{ + sprintf(sdebug,"pea %s",eabuffer); + } +} + +/******************** CLR, NEG, NEGX, NOT, TST ********************/ + +#define negate_ea(name,dump) static void name(void){\ + ea;sprintf(sdebug,"%s %s",dump,eabuffer);\ +} + +negate_ea(m68_neg_____b,"neg.b ") +negate_ea(m68_neg_____w,"neg ") +negate_ea(m68_neg_____l,"neg.l ") +negate_ea(m68_negx____b,"negx.b") +negate_ea(m68_negx____w,"negx ") +negate_ea(m68_negx____l,"negx.l") +negate_ea(m68_not_____b,"not.b ") +negate_ea(m68_not_____w,"not ") +negate_ea(m68_not_____l,"not.l ") +negate_ea(m68_clr_____b,"clr.b ") +negate_ea(m68_clr_____w,"clr ") +negate_ea(m68_clr_____l,"clr.l ") +negate_ea(m68_tst_____b,"tst.b ") +negate_ea(m68_tst_____w,"tst ") +negate_ea(m68_tst_____l,"tst.l ") + +/******************** SOURCE: IMMEDIATE DATA +********************* DESTINATION: EFFECTIVE ADDRESS +********************/ + +#define im_to_ea(name,type,hextype,fetchtype,dump,r) static void name(void){\ + type src=(type)fetchtype();\ + if((inst&0x3F)==0x3C){\ + sprintf(sdebug,"%s #$"hextype",%s",dump,src,r);\ + }else{\ + ea;sprintf(sdebug,"%s #$"hextype",%s",dump,src,eabuffer);\ + }\ +} + +im_to_ea(m68_ori_____b,byte ,hex08,fetch ,"or.b ","ccr") +im_to_ea(m68_ori_____w,word ,hex16,fetch ,"or ","sr" ) +im_to_ea(m68_ori_____l,dword,hex32,fetchl,"or.l ","" ) +im_to_ea(m68_andi____b,byte ,hex08,fetch ,"and.b","ccr") +im_to_ea(m68_andi____w,word ,hex16,fetch ,"and ","sr" ) +im_to_ea(m68_andi____l,dword,hex32,fetchl,"and.l","" ) +im_to_ea(m68_eori____b,byte ,hex08,fetch ,"eor.b","ccr") +im_to_ea(m68_eori____w,word ,hex16,fetch ,"eor ","sr" ) +im_to_ea(m68_eori____l,dword,hex32,fetchl,"eor.l","" ) +im_to_ea(m68_addi____b,byte ,hex08,fetch ,"add.b","" ) +im_to_ea(m68_addi____w,word ,hex16,fetch ,"add ","" ) +im_to_ea(m68_addi____l,dword,hex32,fetchl,"add.l","" ) +im_to_ea(m68_subi____b,byte ,hex08,fetch ,"sub.b","" ) +im_to_ea(m68_subi____w,word ,hex16,fetch ,"sub ","" ) +im_to_ea(m68_subi____l,dword,hex32,fetchl,"sub.l","" ) +im_to_ea(m68_cmpi____b,byte ,hex08,fetch ,"cmp.b","" ) +im_to_ea(m68_cmpi____w,word ,hex16,fetch ,"cmp ","" ) +im_to_ea(m68_cmpi____l,dword,hex32,fetchl,"cmp.l","" ) + +/******************** SOURCE: EFFECTIVE ADDRESS +********************* DESTINATION: DATA REGISTER +********************/ + +#define ea_to_dn(name,dump) static void name(void){\ + ea;sprintf(sdebug,"%s %s,d%d",dump,eabuffer,(inst>>9)&7);\ +} + +ea_to_dn(m68_or__d_n_b,"or.b ") +ea_to_dn(m68_or__d_n_w,"or ") +ea_to_dn(m68_or__d_n_l,"or.l ") +ea_to_dn(m68_and_d_n_b,"and.b") +ea_to_dn(m68_and_d_n_w,"and ") +ea_to_dn(m68_and_d_n_l,"and.l") +ea_to_dn(m68_add_d_n_b,"add.b") +ea_to_dn(m68_add_d_n_w,"add ") +ea_to_dn(m68_add_d_n_l,"add.l") +ea_to_dn(m68_sub_d_n_b,"sub.b") +ea_to_dn(m68_sub_d_n_w,"sub ") +ea_to_dn(m68_sub_d_n_l,"sub.l") +ea_to_dn(m68_cmp_d_n_b,"cmp.b") +ea_to_dn(m68_cmp_d_n_w,"cmp ") +ea_to_dn(m68_cmp_d_n_l,"cmp.l") + +/******************** SOURCE: EFFECTIVE ADDRESS +********************* DESTINATION: ADDRESS REGISTER +********************/ + +#define ea_to_an(name,dump) static void name(void){\ + ea;sprintf(sdebug,"%s %s,a%d",dump,eabuffer,((inst>>9)&7));\ +} + +ea_to_an(m68_adda__n_w,"add ") +ea_to_an(m68_adda__n_l,"add.l") +ea_to_an(m68_suba__n_w,"sub ") +ea_to_an(m68_suba__n_l,"sub.l") +ea_to_an(m68_cmpa__n_w,"cmp ") +ea_to_an(m68_cmpa__n_l,"cmp.l") + +/******************** SUPPORT ROUTINE: ADDX AND SUBX +********************/ + +#define support_addsubx(name,dump)\ +static void name(void){\ + word nregx=(inst>>9)&7,nregy=inst&7;\ + if(inst&0x0008)sprintf(sdebug,"%s -(a%d),-(a%d)",dump,nregy,nregx);\ + else sprintf(sdebug,"%s d%d,d%d",dump,nregy,nregx);\ +} + +support_addsubx(m68support_addx_b,"addx.b") +support_addsubx(m68support_addx_w,"addx ") +support_addsubx(m68support_addx_l,"addx.l") +support_addsubx(m68support_subx_b,"subx.b") +support_addsubx(m68support_subx_w,"subx ") +support_addsubx(m68support_subx_l,"subx.l") + +#define support_bcd(name,dump)\ +static void name(void){\ + word nregx=(inst>>9)&7,nregy=inst&7;\ + if(inst&0x0008)sprintf(sdebug,"%s -(a%d),-(a%d)",dump,nregy,nregx);\ + else sprintf(sdebug,"%s d%d,d%d",dump,nregy,nregx);\ +} + +support_bcd(m68support_abcd,"abcd") +support_bcd(m68support_sbcd,"sbcd") + +/******************** SUPPORT ROUTINE: CMPM +********************/ + +#define support_cmpm(name,dump) static void name(void){\ + sprintf(sdebug,"%s (a%d)+,(a%d)+",dump,inst&7,(inst>>9)&7);\ +} + +support_cmpm(m68support_cmpm_b,"cmp.b") +support_cmpm(m68support_cmpm_w,"cmp ") +support_cmpm(m68support_cmpm_l,"cmp.l") + +/******************** SUPPORT ROUTINE: EXG +********************/ + +static void m68support_exg_same(void){ + dword rx; + rx=(inst&8)|((inst>>9)&7); + sprintf(sdebug,"exg %c%d,%c%d", + rx&8?'a':'d',rx&7,inst&8?'a':'d',inst&7); +} + +static void m68support_exg_diff(void){ + sprintf(sdebug,"exg d%d,a%d",(inst>>9)&7,inst&7); +} + +/******************** SOURCE: DATA REGISTER +********************* DESTINATION: EFFECTIVE ADDRESS +********************* +********************* calls a support routine if EA is a register +********************/ + +#define dn_to_ea(name,dump,s_cond,s_routine)\ +static void name(void){\ + ea;if(s_cond)s_routine();\ + else sprintf(sdebug,"%s d%d,%s",dump,(inst>>9)&7,eabuffer);\ +} + +dn_to_ea(m68_add_e_n_b,"add.b",isregister,m68support_addx_b) +dn_to_ea(m68_add_e_n_w,"add ",isregister,m68support_addx_w) +dn_to_ea(m68_add_e_n_l,"add.l",isregister,m68support_addx_l) +dn_to_ea(m68_sub_e_n_b,"sub.b",isregister,m68support_subx_b) +dn_to_ea(m68_sub_e_n_w,"sub ",isregister,m68support_subx_w) +dn_to_ea(m68_sub_e_n_l,"sub.l",isregister,m68support_subx_l) +dn_to_ea(m68_eor_e_n_b,"eor.b",isaddressr,m68support_cmpm_b) +dn_to_ea(m68_eor_e_n_w,"eor ",isaddressr,m68support_cmpm_w) +dn_to_ea(m68_eor_e_n_l,"eor.l",isaddressr,m68support_cmpm_l) +dn_to_ea(m68_or__e_n_b,"or.b ",isregister,m68support_sbcd) +dn_to_ea(m68_or__e_n_w,"or ",isregister,m68unsupported) +dn_to_ea(m68_or__e_n_l,"or.l ",isregister,m68unsupported) +dn_to_ea(m68_and_e_n_b,"and.b",isregister,m68support_abcd) +dn_to_ea(m68_and_e_n_w,"and ",isregister,m68support_exg_same) +dn_to_ea(m68_and_e_n_l,"and.l",isaddressr,m68support_exg_diff) + +/******************** SOURCE: QUICK DATA +********************* DESTINATION: EFFECTIVE ADDRESS +********************/ + +#define qn_to_ea(name,dump1) static void name(void){\ + ea;sprintf(sdebug,"%s #%d,%s",dump1,(((inst>>9)&7)==0)?8:(inst>>9)&7,eabuffer);\ +} + +qn_to_ea(m68_addq__n_b,"add.b") +qn_to_ea(m68_addq__n_w,"add ") +qn_to_ea(m68_addq__n_l,"add.l") +qn_to_ea(m68_subq__n_b,"sub.b") +qn_to_ea(m68_subq__n_w,"sub ") +qn_to_ea(m68_subq__n_l,"sub.l") + +/******************** SOURCE: QUICK DATA +********************* DESTINATION: DATA REGISTER +********************/ +/* MOVEQ is the only instruction that uses this form */ + +static void m68_moveq_n_l(void){ + sprintf(sdebug,"moveq #$"hex08",d%d",inst&0xFF,(inst>>9)&7); +} + +/******************** SOURCE: EFFECTIVE ADDRESS +********************* DESTINATION: EFFECTIVE ADDRESS +********************/ +/* MOVE is the only instruction that uses this form */ + +#define ea_to_ea(name,dump) static void name(void){\ + char tmpbuf[40];\ + ea;strcpy(tmpbuf,eabuffer);\ + eacalc[((((inst>>3)&(7<<3)))|((inst>>9)&7))]();\ + sprintf(sdebug,"%s %s,%s",dump,tmpbuf,eabuffer);\ +} + +ea_to_ea(m68_move____b,"move.b") +ea_to_ea(m68_move____w,"move ") +ea_to_ea(m68_move____l,"move.l") + +/******************** MOVEM, EXT +********************/ + +static void getreglistf(word mask,char*rl){ + if(mask&0x0001){*(rl++)='d';*(rl++)='0';*(rl++)='/';} + if(mask&0x0002){*(rl++)='d';*(rl++)='1';*(rl++)='/';} + if(mask&0x0004){*(rl++)='d';*(rl++)='2';*(rl++)='/';} + if(mask&0x0008){*(rl++)='d';*(rl++)='3';*(rl++)='/';} + if(mask&0x0010){*(rl++)='d';*(rl++)='4';*(rl++)='/';} + if(mask&0x0020){*(rl++)='d';*(rl++)='5';*(rl++)='/';} + if(mask&0x0040){*(rl++)='d';*(rl++)='6';*(rl++)='/';} + if(mask&0x0080){*(rl++)='d';*(rl++)='7';*(rl++)='/';} + if(mask&0x0100){*(rl++)='a';*(rl++)='0';*(rl++)='/';} + if(mask&0x0200){*(rl++)='a';*(rl++)='1';*(rl++)='/';} + if(mask&0x0400){*(rl++)='a';*(rl++)='2';*(rl++)='/';} + if(mask&0x0800){*(rl++)='a';*(rl++)='3';*(rl++)='/';} + if(mask&0x1000){*(rl++)='a';*(rl++)='4';*(rl++)='/';} + if(mask&0x2000){*(rl++)='a';*(rl++)='5';*(rl++)='/';} + if(mask&0x4000){*(rl++)='a';*(rl++)='6';*(rl++)='/';} + if(mask&0x8000){*(rl++)='a';*(rl++)='7';*(rl++)='/';} + *(--rl)=0; +} + +static void getreglistb(word mask,char*rl){ + if(mask&0x0001){*(rl++)='a';*(rl++)='7';*(rl++)='/';} + if(mask&0x0002){*(rl++)='a';*(rl++)='6';*(rl++)='/';} + if(mask&0x0004){*(rl++)='a';*(rl++)='5';*(rl++)='/';} + if(mask&0x0008){*(rl++)='a';*(rl++)='4';*(rl++)='/';} + if(mask&0x0010){*(rl++)='a';*(rl++)='3';*(rl++)='/';} + if(mask&0x0020){*(rl++)='a';*(rl++)='2';*(rl++)='/';} + if(mask&0x0040){*(rl++)='a';*(rl++)='1';*(rl++)='/';} + if(mask&0x0080){*(rl++)='a';*(rl++)='0';*(rl++)='/';} + if(mask&0x0100){*(rl++)='d';*(rl++)='7';*(rl++)='/';} + if(mask&0x0200){*(rl++)='d';*(rl++)='6';*(rl++)='/';} + if(mask&0x0400){*(rl++)='d';*(rl++)='5';*(rl++)='/';} + if(mask&0x0800){*(rl++)='d';*(rl++)='4';*(rl++)='/';} + if(mask&0x1000){*(rl++)='d';*(rl++)='3';*(rl++)='/';} + if(mask&0x2000){*(rl++)='d';*(rl++)='2';*(rl++)='/';} + if(mask&0x4000){*(rl++)='d';*(rl++)='1';*(rl++)='/';} + if(mask&0x8000){*(rl++)='d';*(rl++)='0';*(rl++)='/';} + *(--rl)=0; +} + +#define movem_mem(name,dumpm,dumpx)\ +static void name(void){\ + word regmask;\ + char reglist[50];\ + if((inst&0x38)==0x0000){ /* ext */\ + sprintf(sdebug,dumpx"d%d",inst&7);\ + }else if((inst&0x38)==0x0020){ /* predecrement addressing mode */\ + regmask=fetch();\ + getreglistb(regmask,reglist);\ + sprintf(sdebug,dumpm"%s,-(a%d)",reglist,inst&7);\ + }else{\ + regmask=fetch();\ + ea;getreglistf(regmask,reglist);\ + sprintf(sdebug,dumpm "%s,%s",reglist,eabuffer);\ + }\ +} + +movem_mem(m68_movem___w,"movem ","ext ") +movem_mem(m68_movem___l,"movem.l ","ext.l ") + +#define movem_reg(name,dump) static void name(void){\ + word regmask;\ + char reglist[50];\ + regmask=fetch();\ + ea;getreglistf(regmask,reglist);\ + sprintf(sdebug,dump "%s,%s",eabuffer,reglist);\ +} + +movem_reg(m68_movem_r_w,"movem ") +movem_reg(m68_movem_r_l,"movem.l ") + +/******************** INSTRUCTIONS THAT INVOLVE SR/CCR ********************/ + +static void m68_move2sr_w(void){ea;sprintf(sdebug,"move %s,sr",eabuffer);} +static void m68_movefsr_w(void){ea;sprintf(sdebug,"move sr,%s",eabuffer);} +static void m68_move2cc_w(void){ea;sprintf(sdebug,"move.b %s,ccr",eabuffer);} +static void m68_movefcc_w(void){ea;sprintf(sdebug,"move.b ccr,%s",eabuffer);} + +static void m68_rts_____x(void){sprintf(sdebug,"rts");} + +/******************** SHIFTS AND ROTATES ********************/ + +#define regshift(name,sizedump) \ +static void name(void){\ + char tmpbuf[10];\ + if((inst&0x20)==0)sprintf(tmpbuf,"#$"hex08",d%d",(((inst>>9)&7)==0)?8:(inst>>9)&7,inst&7);\ + else sprintf(tmpbuf,"d%d,d%d",(inst>>9)&7,inst&7);\ + switch(inst&0x18){\ + case 0x00:sprintf(sdebug,"as%s %s",sizedump,tmpbuf);break;\ + case 0x08:sprintf(sdebug,"ls%s %s",sizedump,tmpbuf);break;\ + case 0x10:sprintf(sdebug,"rox%s %s",sizedump,tmpbuf);break;\ + case 0x18:sprintf(sdebug,"ro%s %s",sizedump,tmpbuf);break;\ + }\ +} + +regshift(m68_shl_r_n_b,"l.b") +regshift(m68_shl_r_n_w,"l ") +regshift(m68_shl_r_n_l,"l.l") +regshift(m68_shr_r_n_b,"r.b") +regshift(m68_shr_r_n_w,"r ") +regshift(m68_shr_r_n_l,"r.l") + +/******************** NOP ********************/ + +static void m68_nop_____x(void){sprintf(sdebug,"nop");} + +/******************** LINK / UNLINK ********************/ + +static void m68_link_an_w(void){ + int16 briefext=fetch(); + sprintf(sdebug,"link a%d,%c#$"hex16,inst&7,briefext<0?'-':'+', + briefext<0?-briefext:briefext + ); +} + +static void m68_unlk_an_x(void){ + sprintf(sdebug,"unlk a%d",inst&7); +} + +static void m68_stop____x(void){sprintf(sdebug,"stop #$%04X",fetch());} +static void m68_rte_____x(void){sprintf(sdebug,"rte");} +static void m68_rtr_____x(void){sprintf(sdebug,"rtr");} +static void m68_reset___x(void){sprintf(sdebug,"reset");} +static void m68_rtd_____x(void){ + int16 briefext=fetch(); + sprintf(sdebug,"rtd %c#$"hex16,briefext<0?'-':'+', + briefext<0?-briefext:briefext); +} +static void m68_divu__n_w(void){ea;sprintf(sdebug,"divu %s,d%d",eabuffer,(inst>>9)&7);} +static void m68_divs__n_w(void){ea;sprintf(sdebug,"divs %s,d%d",eabuffer,(inst>>9)&7);} +static void m68_mulu__n_w(void){ea;sprintf(sdebug,"mulu %s,d%d",eabuffer,(inst>>9)&7);} +static void m68_muls__n_w(void){ea;sprintf(sdebug,"muls %s,d%d",eabuffer,(inst>>9)&7);} + +static void m68_asr_m___w(void){ea;sprintf(sdebug,"asr %s",eabuffer);} +static void m68_asl_m___w(void){ea;sprintf(sdebug,"asl %s",eabuffer);} +static void m68_lsr_m___w(void){ea;sprintf(sdebug,"lsr %s",eabuffer);} +static void m68_lsl_m___w(void){ea;sprintf(sdebug,"lsl %s",eabuffer);} +static void m68_roxr_m__w(void){ea;sprintf(sdebug,"roxr %s",eabuffer);} +static void m68_roxl_m__w(void){ea;sprintf(sdebug,"roxl %s",eabuffer);} +static void m68_ror_m___w(void){ea;sprintf(sdebug,"ror %s",eabuffer);} +static void m68_rol_m___w(void){ea;sprintf(sdebug,"rol %s",eabuffer);} + +static void m68_nbcd____b(void){ea;sprintf(sdebug,"nbcd.b %s",eabuffer);} +static void m68_chk___n_w(void){ea;sprintf(sdebug,"chk %s,d%d",eabuffer,(inst>>9)&7);} + +static void m68_trap_nn_x(void){sprintf(sdebug,"trap #%d",inst&0xF);} +static void m68_move_2u_l(void){sprintf(sdebug,"move.l a%d,usp",inst&7);} +static void m68_move_fu_l(void){sprintf(sdebug,"move.l usp,a%d",inst&7);} + +static void m68_trapv___x(void){sprintf(sdebug,"trapv");} + +static char*specialregister(unsigned short int code){ + switch(code&0xFFF){ + case 0x000:return("sfc"); + case 0x001:return("dfc"); + case 0x800:return("usp"); + case 0x801:return("vbr"); + } + return("???"); +} + +static void m68_movec_r_x(void){ + unsigned short int f=fetch(); + sprintf(sdebug,"movec %s,%c%d", + specialregister(f), + (f&0x8000)?'a':'d',(f>>12)&7 + ); +} + +static void m68_movec_c_x(void){ + unsigned short int f=fetch(); + sprintf(sdebug,"movec %c%d,%s", + (f&0x8000)?'a':'d',(f>>12)&7, + specialregister(f) + ); +} + +/******************** SPECIAL INSTRUCTION TABLE ********************/ + +/* This table is used for 0100111001xxxxxx instructions (4E4x-4E7x) */ +static void(*(debugspecialmap[64]))(void)={ +/* 0000xx */ m68_trap_nn_x,m68_trap_nn_x,m68_trap_nn_x,m68_trap_nn_x, +/* 0001xx */ m68_trap_nn_x,m68_trap_nn_x,m68_trap_nn_x,m68_trap_nn_x, +/* 0010xx */ m68_trap_nn_x,m68_trap_nn_x,m68_trap_nn_x,m68_trap_nn_x, +/* 0011xx */ m68_trap_nn_x,m68_trap_nn_x,m68_trap_nn_x,m68_trap_nn_x, +/* 0100xx */ m68_link_an_w,m68_link_an_w,m68_link_an_w,m68_link_an_w, +/* 0101xx */ m68_link_an_w,m68_link_an_w,m68_link_an_w,m68_link_an_w, +/* 0110xx */ m68_unlk_an_x,m68_unlk_an_x,m68_unlk_an_x,m68_unlk_an_x, +/* 0111xx */ m68_unlk_an_x,m68_unlk_an_x,m68_unlk_an_x,m68_unlk_an_x, +/* 1000xx */ m68_move_2u_l,m68_move_2u_l,m68_move_2u_l,m68_move_2u_l, +/* 1001xx */ m68_move_2u_l,m68_move_2u_l,m68_move_2u_l,m68_move_2u_l, +/* 1010xx */ m68_move_fu_l,m68_move_fu_l,m68_move_fu_l,m68_move_fu_l, +/* 1011xx */ m68_move_fu_l,m68_move_fu_l,m68_move_fu_l,m68_move_fu_l, +/* 1100xx */ m68_reset___x,m68_nop_____x,m68_stop____x,m68_rte_____x, +/* 1101xx */ m68_rtd_____x,m68_rts_____x,m68_trapv___x,m68_rtr_____x, +/* 1110xx */ m68_unrecog_x,m68_unrecog_x,m68_movec_r_x,m68_movec_c_x, +/* 1111xx */ m68_unrecog_x,m68_unrecog_x,m68_unrecog_x,m68_unrecog_x}; + +static void m68_special_x(void){ + debugspecialmap[inst&0x3F](); +} + +/******************** INSTRUCTION TABLE ********************/ + +/* The big 1024-element jump table that handles all possible opcodes + is in the following header file. + Use this syntax to execute an instruction: + + cpumap[i>>6](); + + ("i" is the instruction word) +*/ + +static void(*(debugmap[1024]))(void)={ +/* 00000000ss */ m68_ori_____b,m68_ori_____w,m68_ori_____l,m68_unrecog_x, +/* 00000001ss */ m68_bitopdn_x,m68_bitopdn_x,m68_bitopdn_x,m68_bitopdn_x, +/* 00000010ss */ m68_andi____b,m68_andi____w,m68_andi____l,m68_unrecog_x, +/* 00000011ss */ m68_bitopdn_x,m68_bitopdn_x,m68_bitopdn_x,m68_bitopdn_x, +/* 00000100ss */ m68_subi____b,m68_subi____w,m68_subi____l,m68_unrecog_x, +/* 00000101ss */ m68_bitopdn_x,m68_bitopdn_x,m68_bitopdn_x,m68_bitopdn_x, +/* 00000110ss */ m68_addi____b,m68_addi____w,m68_addi____l,m68_unrecog_x, +/* 00000111ss */ m68_bitopdn_x,m68_bitopdn_x,m68_bitopdn_x,m68_bitopdn_x, +/* 00001000ss */ m68_btst_st_x,m68_bchg_st_x,m68_bclr_st_x,m68_bset_st_x, +/* 00001001ss */ m68_bitopdn_x,m68_bitopdn_x,m68_bitopdn_x,m68_bitopdn_x, +/* 00001010ss */ m68_eori____b,m68_eori____w,m68_eori____l,m68_unrecog_x, +/* 00001011ss */ m68_bitopdn_x,m68_bitopdn_x,m68_bitopdn_x,m68_bitopdn_x, +/* 00001100ss */ m68_cmpi____b,m68_cmpi____w,m68_cmpi____l,m68_unrecog_x, +/* 00001101ss */ m68_bitopdn_x,m68_bitopdn_x,m68_bitopdn_x,m68_bitopdn_x, +/* 00001110ss */ m68_unrecog_x,m68_unrecog_x,m68_unrecog_x,m68_unrecog_x, +/* 00001111ss */ m68_bitopdn_x,m68_bitopdn_x,m68_bitopdn_x,m68_bitopdn_x, +/* 00010000ss */ m68_move____b,m68_move____b,m68_move____b,m68_move____b, +/* 00010001ss */ m68_move____b,m68_move____b,m68_move____b,m68_move____b, +/* 00010010ss */ m68_move____b,m68_move____b,m68_move____b,m68_move____b, +/* 00010011ss */ m68_move____b,m68_move____b,m68_move____b,m68_move____b, +/* 00010100ss */ m68_move____b,m68_move____b,m68_move____b,m68_move____b, +/* 00010101ss */ m68_move____b,m68_move____b,m68_move____b,m68_move____b, +/* 00010110ss */ m68_move____b,m68_move____b,m68_move____b,m68_move____b, +/* 00010111ss */ m68_move____b,m68_move____b,m68_move____b,m68_move____b, +/* 00011000ss */ m68_move____b,m68_move____b,m68_move____b,m68_move____b, +/* 00011001ss */ m68_move____b,m68_move____b,m68_move____b,m68_move____b, +/* 00011010ss */ m68_move____b,m68_move____b,m68_move____b,m68_move____b, +/* 00011011ss */ m68_move____b,m68_move____b,m68_move____b,m68_move____b, +/* 00011100ss */ m68_move____b,m68_move____b,m68_move____b,m68_move____b, +/* 00011101ss */ m68_move____b,m68_move____b,m68_move____b,m68_move____b, +/* 00011110ss */ m68_move____b,m68_move____b,m68_move____b,m68_move____b, +/* 00011111ss */ m68_move____b,m68_move____b,m68_move____b,m68_move____b, +/* 00100000ss */ m68_move____l,m68_move____l,m68_move____l,m68_move____l, +/* 00100001ss */ m68_move____l,m68_move____l,m68_move____l,m68_move____l, +/* 00100010ss */ m68_move____l,m68_move____l,m68_move____l,m68_move____l, +/* 00100011ss */ m68_move____l,m68_move____l,m68_move____l,m68_move____l, +/* 00100100ss */ m68_move____l,m68_move____l,m68_move____l,m68_move____l, +/* 00100101ss */ m68_move____l,m68_move____l,m68_move____l,m68_move____l, +/* 00100110ss */ m68_move____l,m68_move____l,m68_move____l,m68_move____l, +/* 00100111ss */ m68_move____l,m68_move____l,m68_move____l,m68_move____l, +/* 00101000ss */ m68_move____l,m68_move____l,m68_move____l,m68_move____l, +/* 00101001ss */ m68_move____l,m68_move____l,m68_move____l,m68_move____l, +/* 00101010ss */ m68_move____l,m68_move____l,m68_move____l,m68_move____l, +/* 00101011ss */ m68_move____l,m68_move____l,m68_move____l,m68_move____l, +/* 00101100ss */ m68_move____l,m68_move____l,m68_move____l,m68_move____l, +/* 00101101ss */ m68_move____l,m68_move____l,m68_move____l,m68_move____l, +/* 00101110ss */ m68_move____l,m68_move____l,m68_move____l,m68_move____l, +/* 00101111ss */ m68_move____l,m68_move____l,m68_move____l,m68_move____l, +/* 00110000ss */ m68_move____w,m68_move____w,m68_move____w,m68_move____w, +/* 00110001ss */ m68_move____w,m68_move____w,m68_move____w,m68_move____w, +/* 00110010ss */ m68_move____w,m68_move____w,m68_move____w,m68_move____w, +/* 00110011ss */ m68_move____w,m68_move____w,m68_move____w,m68_move____w, +/* 00110100ss */ m68_move____w,m68_move____w,m68_move____w,m68_move____w, +/* 00110101ss */ m68_move____w,m68_move____w,m68_move____w,m68_move____w, +/* 00110110ss */ m68_move____w,m68_move____w,m68_move____w,m68_move____w, +/* 00110111ss */ m68_move____w,m68_move____w,m68_move____w,m68_move____w, +/* 00111000ss */ m68_move____w,m68_move____w,m68_move____w,m68_move____w, +/* 00111001ss */ m68_move____w,m68_move____w,m68_move____w,m68_move____w, +/* 00111010ss */ m68_move____w,m68_move____w,m68_move____w,m68_move____w, +/* 00111011ss */ m68_move____w,m68_move____w,m68_move____w,m68_move____w, +/* 00111100ss */ m68_move____w,m68_move____w,m68_move____w,m68_move____w, +/* 00111101ss */ m68_move____w,m68_move____w,m68_move____w,m68_move____w, +/* 00111110ss */ m68_move____w,m68_move____w,m68_move____w,m68_move____w, +/* 00111111ss */ m68_move____w,m68_move____w,m68_move____w,m68_move____w, +/* 01000000ss */ m68_negx____b,m68_negx____w,m68_negx____l,m68_movefsr_w, +/* 01000001ss */ m68_unrecog_x,m68_unrecog_x,m68_chk___n_w,m68_lea___n_l, +/* 01000010ss */ m68_clr_____b,m68_clr_____w,m68_clr_____l,m68_movefcc_w, +/* 01000011ss */ m68_unrecog_x,m68_unrecog_x,m68_chk___n_w,m68_lea___n_l, +/* 01000100ss */ m68_neg_____b,m68_neg_____w,m68_neg_____l,m68_move2cc_w, +/* 01000101ss */ m68_unrecog_x,m68_unrecog_x,m68_chk___n_w,m68_lea___n_l, +/* 01000110ss */ m68_not_____b,m68_not_____w,m68_not_____l,m68_move2sr_w, +/* 01000111ss */ m68_unrecog_x,m68_unrecog_x,m68_chk___n_w,m68_lea___n_l, +/* 01001000ss */ m68_nbcd____b,m68_pea_____l,m68_movem___w,m68_movem___l, +/* 01001001ss */ m68_unrecog_x,m68_unrecog_x,m68_chk___n_w,m68_lea___n_l, +/* 01001010ss */ m68_tst_____b,m68_tst_____w,m68_tst_____l,m68_tas_____b, +/* 01001011ss */ m68_unrecog_x,m68_unrecog_x,m68_chk___n_w,m68_lea___n_l, +/* 01001100ss */ m68_unrecog_x,m68_unrecog_x,m68_movem_r_w,m68_movem_r_l, +/* 01001101ss */ m68_unrecog_x,m68_unrecog_x,m68_chk___n_w,m68_lea___n_l, +/* 01001110ss */ m68_unrecog_x,m68_special_x,m68_jsr_____x,m68_jmp_____x, +/* 01001111ss */ m68_unrecog_x,m68_unrecog_x,m68_chk___n_w,m68_lea___n_l, +/* 01010000ss */ m68_addq__n_b,m68_addq__n_w,m68_addq__n_l,m68_st______x, +/* 01010001ss */ m68_subq__n_b,m68_subq__n_w,m68_subq__n_l,m68_sf______x, +/* 01010010ss */ m68_addq__n_b,m68_addq__n_w,m68_addq__n_l,m68_shi_____x, +/* 01010011ss */ m68_subq__n_b,m68_subq__n_w,m68_subq__n_l,m68_sls_____x, +/* 01010100ss */ m68_addq__n_b,m68_addq__n_w,m68_addq__n_l,m68_scc_____x, +/* 01010101ss */ m68_subq__n_b,m68_subq__n_w,m68_subq__n_l,m68_scs_____x, +/* 01010110ss */ m68_addq__n_b,m68_addq__n_w,m68_addq__n_l,m68_sne_____x, +/* 01010111ss */ m68_subq__n_b,m68_subq__n_w,m68_subq__n_l,m68_seq_____x, +/* 01011000ss */ m68_addq__n_b,m68_addq__n_w,m68_addq__n_l,m68_svc_____x, +/* 01011001ss */ m68_subq__n_b,m68_subq__n_w,m68_subq__n_l,m68_svs_____x, +/* 01011010ss */ m68_addq__n_b,m68_addq__n_w,m68_addq__n_l,m68_spl_____x, +/* 01011011ss */ m68_subq__n_b,m68_subq__n_w,m68_subq__n_l,m68_smi_____x, +/* 01011100ss */ m68_addq__n_b,m68_addq__n_w,m68_addq__n_l,m68_sge_____x, +/* 01011101ss */ m68_subq__n_b,m68_subq__n_w,m68_subq__n_l,m68_slt_____x, +/* 01011110ss */ m68_addq__n_b,m68_addq__n_w,m68_addq__n_l,m68_sgt_____x, +/* 01011111ss */ m68_subq__n_b,m68_subq__n_w,m68_subq__n_l,m68_sle_____x, +/* 01100000ss */ m68_bra_____x,m68_bra_____x,m68_bra_____x,m68_bra_____x, +/* 01100001ss */ m68_bsr_____x,m68_bsr_____x,m68_bsr_____x,m68_bsr_____x, +/* 01100010ss */ m68_bhi_____x,m68_bhi_____x,m68_bhi_____x,m68_bhi_____x, +/* 01100011ss */ m68_bls_____x,m68_bls_____x,m68_bls_____x,m68_bls_____x, +/* 01100100ss */ m68_bcc_____x,m68_bcc_____x,m68_bcc_____x,m68_bcc_____x, +/* 01100101ss */ m68_bcs_____x,m68_bcs_____x,m68_bcs_____x,m68_bcs_____x, +/* 01100110ss */ m68_bne_____x,m68_bne_____x,m68_bne_____x,m68_bne_____x, +/* 01100111ss */ m68_beq_____x,m68_beq_____x,m68_beq_____x,m68_beq_____x, +/* 01101000ss */ m68_bvc_____x,m68_bvc_____x,m68_bvc_____x,m68_bvc_____x, +/* 01101001ss */ m68_bvs_____x,m68_bvs_____x,m68_bvs_____x,m68_bvs_____x, +/* 01101010ss */ m68_bpl_____x,m68_bpl_____x,m68_bpl_____x,m68_bpl_____x, +/* 01101011ss */ m68_bmi_____x,m68_bmi_____x,m68_bmi_____x,m68_bmi_____x, +/* 01101100ss */ m68_bge_____x,m68_bge_____x,m68_bge_____x,m68_bge_____x, +/* 01101101ss */ m68_blt_____x,m68_blt_____x,m68_blt_____x,m68_blt_____x, +/* 01101110ss */ m68_bgt_____x,m68_bgt_____x,m68_bgt_____x,m68_bgt_____x, +/* 01101111ss */ m68_ble_____x,m68_ble_____x,m68_ble_____x,m68_ble_____x, +/* 01110000ss */ m68_moveq_n_l,m68_moveq_n_l,m68_moveq_n_l,m68_moveq_n_l, +/* 01110001ss */ m68_unrecog_x,m68_unrecog_x,m68_unrecog_x,m68_unrecog_x, +/* 01110010ss */ m68_moveq_n_l,m68_moveq_n_l,m68_moveq_n_l,m68_moveq_n_l, +/* 01110011ss */ m68_unrecog_x,m68_unrecog_x,m68_unrecog_x,m68_unrecog_x, +/* 01110100ss */ m68_moveq_n_l,m68_moveq_n_l,m68_moveq_n_l,m68_moveq_n_l, +/* 01110101ss */ m68_unrecog_x,m68_unrecog_x,m68_unrecog_x,m68_unrecog_x, +/* 01110110ss */ m68_moveq_n_l,m68_moveq_n_l,m68_moveq_n_l,m68_moveq_n_l, +/* 01110111ss */ m68_unrecog_x,m68_unrecog_x,m68_unrecog_x,m68_unrecog_x, +/* 01111000ss */ m68_moveq_n_l,m68_moveq_n_l,m68_moveq_n_l,m68_moveq_n_l, +/* 01111001ss */ m68_unrecog_x,m68_unrecog_x,m68_unrecog_x,m68_unrecog_x, +/* 01111010ss */ m68_moveq_n_l,m68_moveq_n_l,m68_moveq_n_l,m68_moveq_n_l, +/* 01111011ss */ m68_unrecog_x,m68_unrecog_x,m68_unrecog_x,m68_unrecog_x, +/* 01111100ss */ m68_moveq_n_l,m68_moveq_n_l,m68_moveq_n_l,m68_moveq_n_l, +/* 01111101ss */ m68_unrecog_x,m68_unrecog_x,m68_unrecog_x,m68_unrecog_x, +/* 01111110ss */ m68_moveq_n_l,m68_moveq_n_l,m68_moveq_n_l,m68_moveq_n_l, +/* 01111111ss */ m68_unrecog_x,m68_unrecog_x,m68_unrecog_x,m68_unrecog_x, +/* 10000000ss */ m68_or__d_n_b,m68_or__d_n_w,m68_or__d_n_l,m68_divu__n_w, +/* 10000001ss */ m68_or__e_n_b,m68_or__e_n_w,m68_or__e_n_l,m68_divs__n_w, +/* 10000010ss */ m68_or__d_n_b,m68_or__d_n_w,m68_or__d_n_l,m68_divu__n_w, +/* 10000011ss */ m68_or__e_n_b,m68_or__e_n_w,m68_or__e_n_l,m68_divs__n_w, +/* 10000100ss */ m68_or__d_n_b,m68_or__d_n_w,m68_or__d_n_l,m68_divu__n_w, +/* 10000101ss */ m68_or__e_n_b,m68_or__e_n_w,m68_or__e_n_l,m68_divs__n_w, +/* 10000110ss */ m68_or__d_n_b,m68_or__d_n_w,m68_or__d_n_l,m68_divu__n_w, +/* 10000111ss */ m68_or__e_n_b,m68_or__e_n_w,m68_or__e_n_l,m68_divs__n_w, +/* 10001000ss */ m68_or__d_n_b,m68_or__d_n_w,m68_or__d_n_l,m68_divu__n_w, +/* 10001001ss */ m68_or__e_n_b,m68_or__e_n_w,m68_or__e_n_l,m68_divs__n_w, +/* 10001010ss */ m68_or__d_n_b,m68_or__d_n_w,m68_or__d_n_l,m68_divu__n_w, +/* 10001011ss */ m68_or__e_n_b,m68_or__e_n_w,m68_or__e_n_l,m68_divs__n_w, +/* 10001100ss */ m68_or__d_n_b,m68_or__d_n_w,m68_or__d_n_l,m68_divu__n_w, +/* 10001101ss */ m68_or__e_n_b,m68_or__e_n_w,m68_or__e_n_l,m68_divs__n_w, +/* 10001110ss */ m68_or__d_n_b,m68_or__d_n_w,m68_or__d_n_l,m68_divu__n_w, +/* 10001111ss */ m68_or__e_n_b,m68_or__e_n_w,m68_or__e_n_l,m68_divs__n_w, +/* 10010000ss */ m68_sub_d_n_b,m68_sub_d_n_w,m68_sub_d_n_l,m68_suba__n_w, +/* 10010001ss */ m68_sub_e_n_b,m68_sub_e_n_w,m68_sub_e_n_l,m68_suba__n_l, +/* 10010010ss */ m68_sub_d_n_b,m68_sub_d_n_w,m68_sub_d_n_l,m68_suba__n_w, +/* 10010011ss */ m68_sub_e_n_b,m68_sub_e_n_w,m68_sub_e_n_l,m68_suba__n_l, +/* 10010100ss */ m68_sub_d_n_b,m68_sub_d_n_w,m68_sub_d_n_l,m68_suba__n_w, +/* 10010101ss */ m68_sub_e_n_b,m68_sub_e_n_w,m68_sub_e_n_l,m68_suba__n_l, +/* 10010110ss */ m68_sub_d_n_b,m68_sub_d_n_w,m68_sub_d_n_l,m68_suba__n_w, +/* 10010111ss */ m68_sub_e_n_b,m68_sub_e_n_w,m68_sub_e_n_l,m68_suba__n_l, +/* 10011000ss */ m68_sub_d_n_b,m68_sub_d_n_w,m68_sub_d_n_l,m68_suba__n_w, +/* 10011001ss */ m68_sub_e_n_b,m68_sub_e_n_w,m68_sub_e_n_l,m68_suba__n_l, +/* 10011010ss */ m68_sub_d_n_b,m68_sub_d_n_w,m68_sub_d_n_l,m68_suba__n_w, +/* 10011011ss */ m68_sub_e_n_b,m68_sub_e_n_w,m68_sub_e_n_l,m68_suba__n_l, +/* 10011100ss */ m68_sub_d_n_b,m68_sub_d_n_w,m68_sub_d_n_l,m68_suba__n_w, +/* 10011101ss */ m68_sub_e_n_b,m68_sub_e_n_w,m68_sub_e_n_l,m68_suba__n_l, +/* 10011110ss */ m68_sub_d_n_b,m68_sub_d_n_w,m68_sub_d_n_l,m68_suba__n_w, +/* 10011111ss */ m68_sub_e_n_b,m68_sub_e_n_w,m68_sub_e_n_l,m68_suba__n_l, +/* 10100000ss */ m68_unrecog_x,m68_unrecog_x,m68_unrecog_x,m68_unrecog_x, +/* 10100001ss */ m68_unrecog_x,m68_unrecog_x,m68_unrecog_x,m68_unrecog_x, +/* 10100010ss */ m68_unrecog_x,m68_unrecog_x,m68_unrecog_x,m68_unrecog_x, +/* 10100011ss */ m68_unrecog_x,m68_unrecog_x,m68_unrecog_x,m68_unrecog_x, +/* 10100100ss */ m68_unrecog_x,m68_unrecog_x,m68_unrecog_x,m68_unrecog_x, +/* 10100101ss */ m68_unrecog_x,m68_unrecog_x,m68_unrecog_x,m68_unrecog_x, +/* 10100110ss */ m68_unrecog_x,m68_unrecog_x,m68_unrecog_x,m68_unrecog_x, +/* 10100111ss */ m68_unrecog_x,m68_unrecog_x,m68_unrecog_x,m68_unrecog_x, +/* 10101000ss */ m68_unrecog_x,m68_unrecog_x,m68_unrecog_x,m68_unrecog_x, +/* 10101001ss */ m68_unrecog_x,m68_unrecog_x,m68_unrecog_x,m68_unrecog_x, +/* 10101010ss */ m68_unrecog_x,m68_unrecog_x,m68_unrecog_x,m68_unrecog_x, +/* 10101011ss */ m68_unrecog_x,m68_unrecog_x,m68_unrecog_x,m68_unrecog_x, +/* 10101100ss */ m68_unrecog_x,m68_unrecog_x,m68_unrecog_x,m68_unrecog_x, +/* 10101101ss */ m68_unrecog_x,m68_unrecog_x,m68_unrecog_x,m68_unrecog_x, +/* 10101110ss */ m68_unrecog_x,m68_unrecog_x,m68_unrecog_x,m68_unrecog_x, +/* 10101111ss */ m68_unrecog_x,m68_unrecog_x,m68_unrecog_x,m68_unrecog_x, +/* 10110000ss */ m68_cmp_d_n_b,m68_cmp_d_n_w,m68_cmp_d_n_l,m68_cmpa__n_w, +/* 10110001ss */ m68_eor_e_n_b,m68_eor_e_n_w,m68_eor_e_n_l,m68_cmpa__n_l, +/* 10110010ss */ m68_cmp_d_n_b,m68_cmp_d_n_w,m68_cmp_d_n_l,m68_cmpa__n_w, +/* 10110011ss */ m68_eor_e_n_b,m68_eor_e_n_w,m68_eor_e_n_l,m68_cmpa__n_l, +/* 10110100ss */ m68_cmp_d_n_b,m68_cmp_d_n_w,m68_cmp_d_n_l,m68_cmpa__n_w, +/* 10110101ss */ m68_eor_e_n_b,m68_eor_e_n_w,m68_eor_e_n_l,m68_cmpa__n_l, +/* 10110110ss */ m68_cmp_d_n_b,m68_cmp_d_n_w,m68_cmp_d_n_l,m68_cmpa__n_w, +/* 10110111ss */ m68_eor_e_n_b,m68_eor_e_n_w,m68_eor_e_n_l,m68_cmpa__n_l, +/* 10111000ss */ m68_cmp_d_n_b,m68_cmp_d_n_w,m68_cmp_d_n_l,m68_cmpa__n_w, +/* 10111001ss */ m68_eor_e_n_b,m68_eor_e_n_w,m68_eor_e_n_l,m68_cmpa__n_l, +/* 10111010ss */ m68_cmp_d_n_b,m68_cmp_d_n_w,m68_cmp_d_n_l,m68_cmpa__n_w, +/* 10111011ss */ m68_eor_e_n_b,m68_eor_e_n_w,m68_eor_e_n_l,m68_cmpa__n_l, +/* 10111100ss */ m68_cmp_d_n_b,m68_cmp_d_n_w,m68_cmp_d_n_l,m68_cmpa__n_w, +/* 10111101ss */ m68_eor_e_n_b,m68_eor_e_n_w,m68_eor_e_n_l,m68_cmpa__n_l, +/* 10111110ss */ m68_cmp_d_n_b,m68_cmp_d_n_w,m68_cmp_d_n_l,m68_cmpa__n_w, +/* 10111111ss */ m68_eor_e_n_b,m68_eor_e_n_w,m68_eor_e_n_l,m68_cmpa__n_l, +/* 11000000ss */ m68_and_d_n_b,m68_and_d_n_w,m68_and_d_n_l,m68_mulu__n_w, +/* 11000001ss */ m68_and_e_n_b,m68_and_e_n_w,m68_and_e_n_l,m68_muls__n_w, +/* 11000010ss */ m68_and_d_n_b,m68_and_d_n_w,m68_and_d_n_l,m68_mulu__n_w, +/* 11000011ss */ m68_and_e_n_b,m68_and_e_n_w,m68_and_e_n_l,m68_muls__n_w, +/* 11000100ss */ m68_and_d_n_b,m68_and_d_n_w,m68_and_d_n_l,m68_mulu__n_w, +/* 11000101ss */ m68_and_e_n_b,m68_and_e_n_w,m68_and_e_n_l,m68_muls__n_w, +/* 11000110ss */ m68_and_d_n_b,m68_and_d_n_w,m68_and_d_n_l,m68_mulu__n_w, +/* 11000111ss */ m68_and_e_n_b,m68_and_e_n_w,m68_and_e_n_l,m68_muls__n_w, +/* 11001000ss */ m68_and_d_n_b,m68_and_d_n_w,m68_and_d_n_l,m68_mulu__n_w, +/* 11001001ss */ m68_and_e_n_b,m68_and_e_n_w,m68_and_e_n_l,m68_muls__n_w, +/* 11001010ss */ m68_and_d_n_b,m68_and_d_n_w,m68_and_d_n_l,m68_mulu__n_w, +/* 11001011ss */ m68_and_e_n_b,m68_and_e_n_w,m68_and_e_n_l,m68_muls__n_w, +/* 11001100ss */ m68_and_d_n_b,m68_and_d_n_w,m68_and_d_n_l,m68_mulu__n_w, +/* 11001101ss */ m68_and_e_n_b,m68_and_e_n_w,m68_and_e_n_l,m68_muls__n_w, +/* 11001110ss */ m68_and_d_n_b,m68_and_d_n_w,m68_and_d_n_l,m68_mulu__n_w, +/* 11001111ss */ m68_and_e_n_b,m68_and_e_n_w,m68_and_e_n_l,m68_muls__n_w, +/* 11010000ss */ m68_add_d_n_b,m68_add_d_n_w,m68_add_d_n_l,m68_adda__n_w, +/* 11010001ss */ m68_add_e_n_b,m68_add_e_n_w,m68_add_e_n_l,m68_adda__n_l, +/* 11010010ss */ m68_add_d_n_b,m68_add_d_n_w,m68_add_d_n_l,m68_adda__n_w, +/* 11010011ss */ m68_add_e_n_b,m68_add_e_n_w,m68_add_e_n_l,m68_adda__n_l, +/* 11010100ss */ m68_add_d_n_b,m68_add_d_n_w,m68_add_d_n_l,m68_adda__n_w, +/* 11010101ss */ m68_add_e_n_b,m68_add_e_n_w,m68_add_e_n_l,m68_adda__n_l, +/* 11010110ss */ m68_add_d_n_b,m68_add_d_n_w,m68_add_d_n_l,m68_adda__n_w, +/* 11010111ss */ m68_add_e_n_b,m68_add_e_n_w,m68_add_e_n_l,m68_adda__n_l, +/* 11011000ss */ m68_add_d_n_b,m68_add_d_n_w,m68_add_d_n_l,m68_adda__n_w, +/* 11011001ss */ m68_add_e_n_b,m68_add_e_n_w,m68_add_e_n_l,m68_adda__n_l, +/* 11011010ss */ m68_add_d_n_b,m68_add_d_n_w,m68_add_d_n_l,m68_adda__n_w, +/* 11011011ss */ m68_add_e_n_b,m68_add_e_n_w,m68_add_e_n_l,m68_adda__n_l, +/* 11011100ss */ m68_add_d_n_b,m68_add_d_n_w,m68_add_d_n_l,m68_adda__n_w, +/* 11011101ss */ m68_add_e_n_b,m68_add_e_n_w,m68_add_e_n_l,m68_adda__n_l, +/* 11011110ss */ m68_add_d_n_b,m68_add_d_n_w,m68_add_d_n_l,m68_adda__n_w, +/* 11011111ss */ m68_add_e_n_b,m68_add_e_n_w,m68_add_e_n_l,m68_adda__n_l, +/* 11100000ss */ m68_shr_r_n_b,m68_shr_r_n_w,m68_shr_r_n_l,m68_asr_m___w, +/* 11100001ss */ m68_shl_r_n_b,m68_shl_r_n_w,m68_shl_r_n_l,m68_asl_m___w, +/* 11100010ss */ m68_shr_r_n_b,m68_shr_r_n_w,m68_shr_r_n_l,m68_lsr_m___w, +/* 11100011ss */ m68_shl_r_n_b,m68_shl_r_n_w,m68_shl_r_n_l,m68_lsl_m___w, +/* 11100100ss */ m68_shr_r_n_b,m68_shr_r_n_w,m68_shr_r_n_l,m68_roxr_m__w, +/* 11100101ss */ m68_shl_r_n_b,m68_shl_r_n_w,m68_shl_r_n_l,m68_roxl_m__w, +/* 11100110ss */ m68_shr_r_n_b,m68_shr_r_n_w,m68_shr_r_n_l,m68_ror_m___w, +/* 11100111ss */ m68_shl_r_n_b,m68_shl_r_n_w,m68_shl_r_n_l,m68_rol_m___w, +/* 11101000ss */ m68_shr_r_n_b,m68_shr_r_n_w,m68_shr_r_n_l,m68_unrecog_x, +/* 11101001ss */ m68_shl_r_n_b,m68_shl_r_n_w,m68_shl_r_n_l,m68_unrecog_x, +/* 11101010ss */ m68_shr_r_n_b,m68_shr_r_n_w,m68_shr_r_n_l,m68_unrecog_x, +/* 11101011ss */ m68_shl_r_n_b,m68_shl_r_n_w,m68_shl_r_n_l,m68_unrecog_x, +/* 11101100ss */ m68_shr_r_n_b,m68_shr_r_n_w,m68_shr_r_n_l,m68_unrecog_x, +/* 11101101ss */ m68_shl_r_n_b,m68_shl_r_n_w,m68_shl_r_n_l,m68_unrecog_x, +/* 11101110ss */ m68_shr_r_n_b,m68_shr_r_n_w,m68_shr_r_n_l,m68_unrecog_x, +/* 11101111ss */ m68_shl_r_n_b,m68_shl_r_n_w,m68_shl_r_n_l,m68_unrecog_x, +/* 11110000ss */ m68_unrecog_x,m68_unrecog_x,m68_unrecog_x,m68_unrecog_x, +/* 11110001ss */ m68_unrecog_x,m68_unrecog_x,m68_unrecog_x,m68_unrecog_x, +/* 11110010ss */ m68_unrecog_x,m68_unrecog_x,m68_unrecog_x,m68_unrecog_x, +/* 11110011ss */ m68_unrecog_x,m68_unrecog_x,m68_unrecog_x,m68_unrecog_x, +/* 11110100ss */ m68_unrecog_x,m68_unrecog_x,m68_unrecog_x,m68_unrecog_x, +/* 11110101ss */ m68_unrecog_x,m68_unrecog_x,m68_unrecog_x,m68_unrecog_x, +/* 11110110ss */ m68_unrecog_x,m68_unrecog_x,m68_unrecog_x,m68_unrecog_x, +/* 11110111ss */ m68_unrecog_x,m68_unrecog_x,m68_unrecog_x,m68_unrecog_x, +/* 11111000ss */ m68_unrecog_x,m68_unrecog_x,m68_unrecog_x,m68_unrecog_x, +/* 11111001ss */ m68_unrecog_x,m68_unrecog_x,m68_unrecog_x,m68_unrecog_x, +/* 11111010ss */ m68_unrecog_x,m68_unrecog_x,m68_unrecog_x,m68_unrecog_x, +/* 11111011ss */ m68_unrecog_x,m68_unrecog_x,m68_unrecog_x,m68_unrecog_x, +/* 11111100ss */ m68_unrecog_x,m68_unrecog_x,m68_unrecog_x,m68_unrecog_x, +/* 11111101ss */ m68_unrecog_x,m68_unrecog_x,m68_unrecog_x,m68_unrecog_x, +/* 11111110ss */ m68_unrecog_x,m68_unrecog_x,m68_unrecog_x,m68_unrecog_x, +/* 11111111ss */ m68_unrecog_x,m68_unrecog_x,m68_unrecog_x,m68_unrecog_x}; + +static void cpudebug_disassemble(int n) { + while(n--) { + dword addr = debugpc; + cpudebug_printf("%08X: ", addr); + isize = 0; + inst = fetch(); + debugmap[inst >> 6](); + while(addr < debugpc) { + cpudebug_printf("%04X ", s68000fetch(starcontext,addr) & 0xFFFF); + addr += 2; + } + while(isize < 10) { + cpudebug_printf(" "); + isize += 2; + } + cpudebug_printf("%s\n", sdebug); + } +} + +static void cpudebug_hexdump(void) { + byte c, tmpchar[16]; + dword tmpaddr; + int i, j, k; + tmpaddr = hexaddr & 0xFFFFFFF0; + for(i = 0; i < 8; i++) { + cpudebug_printf("%08X: %c", tmpaddr, + (hexaddr == tmpaddr) ? '>' : ' ' + ); + for(j = 0; j < 16; j += 2) { + k = s68000fetch(starcontext,tmpaddr) & 0xFFFF; + tmpchar[j ] = k >> 8; + tmpchar[j + 1] = k & 0xFF; + tmpaddr += 2; + cpudebug_printf("%02X%02X%c", + tmpchar[j], tmpchar[j + 1], + (( hexaddr == tmpaddr )&&(j!=14))?'>': + (((hexaddr&0xFFFFFFFE)==(tmpaddr-2))?'<':' ') + ); + } + cpudebug_printf(" "); + for(j = 0; j < 16; j++) { + c = tmpchar[j]; + if((c<32)||(c>126))c='.'; + cpudebug_printf("%c", c); + } + cpudebug_printf("\n"); + } + hexaddr += 0x80; +} + +static void cpudebug_registerdump(void) { + int i; + unsigned dreg[8]; + unsigned areg[8]; + unsigned asp; + unsigned sr; + unsigned pc; + + for(i=0;i<8;i++) { + dreg[i] = s68000readReg(starcontext, STARSCREAM_REG_DATA+i); + areg[i] = s68000readReg(starcontext, STARSCREAM_REG_ADDRESS+i); + } + asp = s68000readReg(starcontext, STARSCREAM_REG_ASP); + sr = s68000readSR(starcontext); + pc = s68000readPC(starcontext); + + cpudebug_printf( + "d0=%08X d4=%08X a0=%08X a4=%08X %c%c%c%c%c\n", + dreg[0],dreg[4], + areg[0],areg[4], + (sr >> 4) & 1 ? 'X' : '-', + (sr >> 3) & 1 ? 'N' : '-', + (sr >> 2) & 1 ? 'Z' : '-', + (sr >> 1) & 1 ? 'V' : '-', + (sr ) & 1 ? 'C' : '-' + ); + cpudebug_printf( + "d1=%08X d5=%08X a1=%08X a5=%08X intmask=%d\n", + dreg[1], dreg[5], + areg[1], areg[5], + ( sr >> 8) & 7 + ); + cpudebug_printf( + "d2=%08X d6=%08X a2=%08X a6=%08X ", + dreg[2], dreg[6], + areg[2], areg[6] + ); + for(i = 1; i <= 7; i++) { + if( interrupts[0] & (1 << i)) { + cpudebug_printf("%02X", interrupts[i]); + } else { + cpudebug_printf("--"); + } + } + cpudebug_printf( + "\nd3=%08X d7=%08X a3=%08X a7=%08X %csp=%08X\n", + dreg[3], dreg[7], + areg[3], areg[7], + (( sr)&0x2000)?'u':'s', asp + ); + debugpc = pc; + cpudebug_disassemble(1); + debugpc = pc; +} + +int cpudebug_interactive( + int cpun, + void (*execstep)(void *execcontext), + void *execcontext, + void *scontext +) { + char inputstr[80]; + char *cmd, *args, *argsend; + dword tmppc; + hexaddr = 0; + starcontext = scontext; + for(;;) { + s68000flushInterrupts(starcontext); + cpudebug_printf("cpu%d-", cpun); + cpudebug_gets(inputstr, sizeof(inputstr)); + cmd = inputstr; + while((tolower(*cmd) < 'a') && (tolower(*cmd) > 'z')) { + if(!(*cmd)) break; + cmd++; + } + if(!(*cmd)) continue; + *cmd = tolower(*cmd); + args = cmd + 1; + while((*args) && ((*args) < 32)) args++; + switch(*cmd) { + case '?': + cpudebug_printf( +"b [address] Run continuously, break at PC=[address]\n" +"d [address] Dump memory, starting at [address]\n" +"i [number] Generate hardware interrupt [number]\n" +"q Quit\n" +"r Show register dump and next instruction\n" +"s [n] Switch to CPU [n]\n" +"t [hex number] Trace through [hex number] instructions\n" +"u [address] Unassemble code, starting at [address]\n" + ); + break; + case 'b': + if(*args) { + tmppc = strtoul(args, &argsend, 16); + if(argsend != args) { + while(s68000readPC(starcontext) != tmppc) + if(execstep) execstep(execcontext); + else s68000exec(starcontext, 1); + cpudebug_registerdump(); + } else { + cpudebug_printf("Invalid address\n"); + } + } else { + cpudebug_printf("Need an address\n"); + } + break; + case 'u': + if(*args) { + tmppc = strtoul(args, &argsend, 16); + if(argsend != args) debugpc = tmppc; + } + cpudebug_disassemble(16); + break; + case 'd': + if(*args) { + tmppc = strtoul(args,&argsend,16); + if(argsend != args) hexaddr = tmppc; + } + cpudebug_hexdump(); + break; + case 'i': + if(*args) { + tmppc = strtoul(args, &argsend, 10); + if(argsend != args) { + cpudebug_printf("Interrupt %d generated\n", tmppc); + s68000interrupt(starcontext, tmppc, -1); + s68000flushInterrupts(starcontext); + cpudebug_registerdump(); + debugpc = s68000readPC(starcontext); + } else { + cpudebug_printf("Invalid interrupt number\n"); + } + } else { + cpudebug_printf("Need an interrupt number\n"); + } + break; + case 't': + tmppc = 1; + if(*args) { + tmppc = strtoul(args, &argsend, 16); + if(argsend == args) tmppc = 1; + } + if(tmppc > 0) { + while(tmppc--) { + if(execstep) execstep(); + else s68000exec(starcontext, 1); + } + cpudebug_registerdump(); + } + break; + case 'r': + cpudebug_registerdump(); + break; + case 'q': + return -1; + case 's': + if(*args) { + tmppc = strtoul(args, &argsend, 10); + if(tmppc > 0) return tmppc; + else cpudebug_printf("Invalid CPU number\n"); + } else return 0; + break; + default: +/* cpudebug_printf("Unknown command\n");*/ + break; + } + } + return -1; +} diff --git a/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/Starscream/mk.bat b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/Starscream/mk.bat new file mode 100644 index 000000000..3a37d2d2b --- /dev/null +++ b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/Starscream/mk.bat @@ -0,0 +1,4 @@ +@echo off +gcc -O2 -Wall star.c -s -o star.exe +star s68000.asm -fastcall -hog +nasmw -o s68000.obj -f win32 s68000.asm diff --git a/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/Starscream/s68000.asm b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/Starscream/s68000.asm new file mode 100644 index 000000000..a822acf88 --- /dev/null +++ b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/Starscream/s68000.asm @@ -0,0 +1,141663 @@ +; Generated by STARSCREAM version 0.27 +; For assembly by NASM only +; +; Options: +; * CPU type: 68000 (24-bit addresses) +; * Identifiers begin with "s68000" +; * __fastcall calling conventions +; * Hog mode: On +; +bits 32 +__fetch equ 0 +__readbyte equ 4 +__readword equ 8 +__writebyte equ 12 +__writeword equ 16 +__s_fetch equ 20 +__s_readbyte equ 24 +__s_readword equ 28 +__s_writebyte equ 32 +__s_writeword equ 36 +__u_fetch equ 40 +__u_readbyte equ 44 +__u_readword equ 48 +__u_writebyte equ 52 +__u_writeword equ 56 +__hwstate equ 60 +__resethandler equ 64 +__reg equ 68 +__dreg equ 68 +__areg equ 100 +__a7 equ 128 +__asp equ 132 +__pc equ 136 +__odometer equ 140 +__interrupts equ 144 +__sr equ 152 +__cycles_needed equ 156 +__cycles_leftover equ 160 +__fetch_region_start equ 164 +__fetch_region_end equ 168 +__xflag equ 172 +__execinfo equ 173 +__trace_trickybit equ 174 +__io_cycle_counter equ 176 +__io_fetchbase equ 180 +__io_fetchbased_pc equ 184 +__access_address equ 188 +save_01 equ 192 +contexttop equ 196 +section .text +bits 32 +top: +global @s68000_init@0 +@s68000_init@0: +pushad +mov edi,_jmptbl +mov esi,_jmptblcomp +.decomp: +lodsd +mov ecx,eax +and eax,0FFFFFFh +shr ecx,24 +add eax,top +inc ecx +.jloop: +mov [edi],eax +add edi,byte 4 +dec ecx +jnz short .jloop +cmp edi,_jmptbl+262144 +jne short .decomp +popad +xor eax,eax +ret +versioninfo: +db "Starscream v0.27 (built Oct 12 2003)",0 +global @s68000_get_version@0 +@s68000_get_version@0: +mov eax,versioninfo +ret +global @s68000_get_state_size@0 +@s68000_get_state_size@0: +mov eax,contexttop +ret +global @s68000_clear_state@4 +@s68000_clear_state@4: +push ebp +mov ebp,ecx +xor eax,eax +.clearloop: +mov dword[ebp+eax],0 +add eax,byte 4 +cmp eax,contexttop +jb .clearloop +mov dword[ebp+__io_cycle_counter],-1 +mov word[ebp+__sr],2700h +pop ebp +ret +global @s68000_set_memory_maps@8 +@s68000_set_memory_maps@8: +push ebp +mov ebp,ecx +mov eax,[edx+0] +mov [ebp+__s_fetch],eax +mov eax,[edx+4] +mov [ebp+__s_readbyte],eax +mov eax,[edx+8] +mov [ebp+__s_readword],eax +mov eax,[edx+12] +mov [ebp+__s_writebyte],eax +mov eax,[edx+16] +mov [ebp+__s_writeword],eax +mov eax,[edx+20] +mov [ebp+__u_fetch],eax +mov eax,[edx+24] +mov [ebp+__u_readbyte],eax +mov eax,[edx+28] +mov [ebp+__u_readword],eax +mov eax,[edx+32] +mov [ebp+__u_writebyte],eax +mov eax,[edx+36] +mov [ebp+__u_writeword],eax +test byte[ebp+__sr+1],20h +jz short .user +mov ecx,[ebp+__s_fetch] +mov [ebp+__fetch],ecx +mov ecx,[ebp+__s_readbyte] +mov [ebp+__readbyte],ecx +mov ecx,[ebp+__s_readword] +mov [ebp+__readword],ecx +mov ecx,[ebp+__s_writebyte] +mov [ebp+__writebyte],ecx +mov ecx,[ebp+__s_writeword] +mov [ebp+__writeword],ecx +jmp short .return +.user: +mov ecx,[ebp+__u_fetch] +mov [ebp+__fetch],ecx +mov ecx,[ebp+__u_readbyte] +mov [ebp+__readbyte],ecx +mov ecx,[ebp+__u_readword] +mov [ebp+__readword],ecx +mov ecx,[ebp+__u_writebyte] +mov [ebp+__writebyte],ecx +mov ecx,[ebp+__u_writeword] +mov [ebp+__writeword],ecx +.return: +pop ebp +ret +global @s68000_reset@4 +@s68000_reset@4: +push ebp +push esi +mov ebp,ecx +mov eax,1 +test [ebp+__execinfo],al +jnz near .return +cmp dword[ebp+__s_fetch],0 +je near .return +dec eax +mov [ebp+__execinfo],al +sub eax,byte 16 +.gp: +mov dword[ebp+__reg+64+eax*4],0 +inc eax +jnz short .gp +mov [ebp+__asp],eax +mov word[ebp+__sr],2700h +mov eax,[ebp+__s_fetch] +mov [ebp+__fetch],eax +mov eax,[ebp+__s_readbyte] +mov [ebp+__readbyte],eax +mov eax,[ebp+__s_readword] +mov [ebp+__readword],eax +mov eax,[ebp+__s_writebyte] +mov [ebp+__writebyte],eax +mov eax,[ebp+__s_writeword] +mov [ebp+__writeword],eax +mov eax,1 +mov [ebp+__pc],eax +mov [ebp+__interrupts],al +xor esi,esi +call basefunction +test byte[ebp+__execinfo],2 +jnz short .return +add esi,[ebp+__io_fetchbase] +mov eax,[esi] +rol eax,16 +mov [ebp+__a7],eax +mov eax,[esi+4] +rol eax,16 +mov [ebp+__pc],eax +and eax,byte 1 +mov [ebp+__interrupts],al +neg eax +.return: +pop esi +pop ebp +ret +global @s68000_execute@8 +@s68000_execute@8: +push ebp +push ebx +push ecx +push edx +push esi +push edi +mov ebp,ecx +mov eax,edx +test byte[ebp+__interrupts],1 +jz .notstopped +test byte[ebp+__pc],1 +jz .notfaulted +or eax,byte -1 +jmp execreturn +.notfaulted: +add [ebp+__odometer],eax +mov eax,80000000h +jmp execreturn +.notstopped: +mov [ebp+__cycles_needed],eax +mov edi,eax +dec edi +xor ebx,ebx +mov esi,[ebp+__pc] +mov al,[ebp+__sr] +mov ah,al +and ax,0C10h +shl ah,3 +shr al,4 +mov [ebp+__xflag],al +mov al,[ebp+__sr] +and al,3 +shr al,1 +adc ah,ah +mov dword[ebp+__io_fetchbase],0 +mov byte[ebp+__execinfo],1 +call basefunction +add esi,[ebp+__io_fetchbase] +test byte[ebp+__execinfo],2 +jnz near exec_bounderror +mov dword[ebp+__cycles_leftover],0 +exec_checkpoint: +js execquit +mov cl,[ebp+__sr+1] +and ecx,byte 7 +inc ecx +mov ch,[ebp+__interrupts] +or ch,ch +js short .yesint +shr ch,cl +jz short .noint +.yesint: +call flush_interrupts +call basefunction +add esi,[ebp+__io_fetchbase] +test byte[ebp+__execinfo],2 +jnz near exec_bounderror +.noint: +mov ch,[ebp+__sr+1] +and ch,80h +mov [ebp+__trace_trickybit],ch +jz execloop +inc edi +add [ebp+__cycles_leftover],edi +or edi,byte -1 +execloop: +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +execquit: +cmp byte[ebp+__trace_trickybit],0 +je short execquit_notrace +mov edx,24h +call group_1_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln0 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1 +ln0: +call basefunction +ln1: +add esi,[ebp+__io_fetchbase] +sub edi,byte 34 +execquit_notrace: +mov cl,[ebp+__sr+1] +and ecx,byte 7 +inc ecx +mov ch,[ebp+__interrupts] +or ch,ch +js short execquit_yesinterrupt +shr ch,cl +jz short execquit_nointerrupt +execquit_yesinterrupt: +call flush_interrupts +call basefunction +add esi,[ebp+__io_fetchbase] +test byte[ebp+__execinfo],2 +jnz short exec_bounderror +execquit_nointerrupt: +add edi,[ebp+__cycles_leftover] +mov dword[ebp+__cycles_leftover],0 +jns execloop +mov ecx,80000000h +execexit: +sub esi,[ebp+__io_fetchbase] +shr ah,1 +adc ax,ax +and ax,0C003h +or ah,[ebp+__xflag] +ror ah,4 +or al,ah +mov [ebp+__sr],al +mov [ebp+__pc],esi +inc edi +mov edx,[ebp+__cycles_needed] +sub edx,edi +add [ebp+__odometer],edx +mov byte[ebp+__execinfo],0 +mov dword[ebp+__cycles_needed],0 +mov dword[ebp+__io_cycle_counter],-1 +mov eax,ecx +execreturn: +pop edi +pop esi +pop edx +pop ecx +pop ebx +pop ebp +ret +exec_bounderror: +mov ecx,80000001h +jmp short execexit +invalidins: +sub esi,byte 2 +mov ecx,esi +sub ecx,[ebp+__io_fetchbase] +and ecx,16777215 +jmp short execexit +global @s68000_getreg@8 +@s68000_getreg@8: +push ebp +mov ebp,ecx +cmp edx,byte 17 +jb short .normalreg +je short .pc +cmp edx,byte 18 +je short .sr +ja short .none +.normalreg: +mov eax,[ebp+__reg+edx*4] +jmp short .exit +.pc: +test byte[ebp+__execinfo],1 +jnz short .pclive +mov eax,[ebp+__pc] +jmp short .exit +.pclive: +mov eax,[ebp+__io_fetchbased_pc] +sub eax,[ebp+__io_fetchbase] +jmp short .exit +.sr: +movzx eax,word[ebp+__sr] +jmp short .exit +.none: +xor eax,eax +.exit: +pop ebp +ret +global @s68000_interrupt@8 +@s68000_interrupt@8: +push ebp +push ecx +push edx +mov ebp,ecx +mov eax,edx +sar edx,8 +and eax,0FFh +cmp eax,byte 7 +ja short .badinput +or eax,eax +jz short .badinput +cmp edx,255 +jg short .badinput +cmp edx,byte -2 +jl short .badinput +jne short .notspurious +mov edx,18h +.notspurious: +or edx,edx +jns short .notauto +lea edx,[eax+18h] +.notauto: +push ecx +mov cl,al +mov ah,1 +shl ah,cl +pop ecx +test [ebp+__interrupts],ah +jnz .failure +or [ebp+__interrupts],ah +mov ah,0 +mov [ebp+__interrupts+eax],dl +and byte[ebp+__interrupts],0FEh +mov edx,[ebp+__io_cycle_counter] +inc edx +add [ebp+__cycles_leftover],edx +mov dword[ebp+__io_cycle_counter],-1 +pop edx +pop ecx +pop ebp +xor eax,eax +ret +.failure: +pop edx +pop ecx +pop ebp +mov eax,1 +ret +.badinput: +pop edx +pop ecx +pop ebp +mov eax,2 +ret +global @s68000_flush_interrupts@4 +@s68000_flush_interrupts@4: +push ebp +mov ebp,ecx +test byte[ebp+__execinfo],1 +jnz .noflush +pushad +mov esi,[ebp+__pc] +mov dword[ebp+__io_fetchbase],0 +mov al,[ebp+__sr] +mov ah,al +and ax,0C10h +shl ah,3 +shr al,4 +mov [ebp+__xflag],al +mov al,[ebp+__sr] +and al,3 +shr al,1 +adc ah,ah +xor edi,edi +call flush_interrupts +sub [ebp+__odometer],edi +mov [ebp+__pc],esi +shr ah,1 +adc ax,ax +and ax,0C003h +or ah,[ebp+__xflag] +ror ah,4 +or al,ah +mov [ebp+__sr],al +popad +.noflush: +pop ebp +ret +global @s68000_fetch@8 +@s68000_fetch@8: +push ebx +push esi +push edi +push ebp +mov ebp,ecx +mov eax,edx +push dword[ebp+__fetch] +mov ebx,[ebp+__s_fetch] +mov [ebp+__fetch],ebx +push dword[ebp+__fetch_region_start] +push dword[ebp+__fetch_region_end] +mov bl,[ebp+__execinfo] +push ebx +mov dword[ebp+__io_fetchbase],0 +mov esi,eax +and byte[ebp+__execinfo],0FDh +call basefunction +test byte[ebp+__execinfo],2 +mov eax,-1 +jnz short .badfetch +add esi,[ebp+__io_fetchbase] +inc eax +mov ax,[esi] +.badfetch: +pop ebx +mov [ebp+__execinfo],bl +pop dword[ebp+__fetch_region_end] +pop dword[ebp+__fetch_region_start] +pop dword[ebp+__fetch] +pop ebp +pop edi +pop esi +pop ebx +ret +global @s68000_read_odometer@4 +@s68000_read_odometer@4: +push ebp +mov ebp,ecx +mov eax,[ebp+__cycles_needed] +sub eax,[ebp+__io_cycle_counter] +dec eax +sub eax,[ebp+__cycles_leftover] +add eax,[ebp+__odometer] +pop ebp +ret +global @s68000_break@4 +@s68000_break@4: +push ebp +mov ebp,ecx +mov eax,[ebp+__cycles_needed] +sub [ebp+__io_cycle_counter],eax +xor eax,eax +mov [ebp+__cycles_needed],eax +pop ebp +ret +basefunction: +push ecx +push esi +and esi,16777215 +mov ecx,[ebp+__fetch] +.check: +cmp esi,[ecx] +jb short .next +cmp esi,[ecx+4] +jbe short .base +.next: +cmp dword [ecx],byte -1 +je short .outofrange +add ecx,byte 12 +jmp short .check +.outofrange: +pop esi +mov dword[ebp+__io_fetchbase],0 +mov dword[ebp+__fetch_region_start],-1 +mov dword[ebp+__fetch_region_end],0 +sub edi,[ebp+__cycles_needed] +mov dword[ebp+__cycles_needed],0 +or byte[ebp+__execinfo],2 +pop ecx +ret +.base: +mov esi,[esp] +and esi,-16777216 +push edx +mov edx,ecx +mov ecx,[edx] +or ecx,esi +mov [ebp+__fetch_region_start],ecx +mov ecx,[edx+4] +or ecx,esi +mov [ebp+__fetch_region_end],ecx +mov ecx,[edx+8] +mov [ebp+__io_fetchbase],ecx +pop edx +sub [ebp+__io_fetchbase],esi +pop esi +pop ecx +ret +decode_ext: +push ecx +movzx edx,word[esi] +movsx ecx,dl +add esi,byte 2 +shr edx,12 +mov edx,[ebp+__reg+edx*4] +jc short .long +movsx edx,dx +.long: +add edx,ecx +pop ecx +ret +times ($$-$)&15 db 0 +readmemorybyte: +mov [ebp+__access_address],edx +and edx,16777215 +mov ecx,[ebp+__readbyte] +readb_check: +cmp edx,[ecx] +jb short readb_next +cmp edx,[ecx+4] +jbe short readb_call +readb_next: +cmp dword[ecx],byte -1 +je short readb_outofrange +add ecx,byte 16 +jmp short readb_check +readb_outofrange: +or ecx,byte -1 +mov edx,[ebp+__access_address] +ret +readb_call: +cmp dword[ecx+8],byte 0 +jne short readb_callio +sub edx,[ecx] +add edx,[ecx+12] +xor edx,byte 1 +mov cl,[edx] +mov edx,[ebp+__access_address] +ret +readb_callio: +mov [ebp+__io_cycle_counter],edi +mov [ebp+__io_fetchbased_pc],esi +push ebx +push eax +mov eax,ecx +mov ecx,[ecx+12] +call dword[eax+8] +mov ecx,eax +pop eax +pop ebx +mov edi,[ebp+__io_cycle_counter] +mov esi,[ebp+__io_fetchbased_pc] +mov edx,[ebp+__access_address] +ret +times ($$-$)&15 db 0 +readmemoryword: +mov [ebp+__access_address],edx +and edx,16777215 +mov ecx,[ebp+__readword] +readw_check: +cmp edx,[ecx] +jb short readw_next +cmp edx,[ecx+4] +jbe short readw_call +readw_next: +cmp dword[ecx],byte -1 +je short readw_outofrange +add ecx,byte 16 +jmp short readw_check +readw_outofrange: +or ecx,byte -1 +mov edx,[ebp+__access_address] +ret +readw_call: +cmp dword[ecx+8],byte 0 +jne short readw_callio +sub edx,[ecx] +add edx,[ecx+12] +mov cx,[edx] +mov edx,[ebp+__access_address] +ret +readw_callio: +mov [ebp+__io_cycle_counter],edi +mov [ebp+__io_fetchbased_pc],esi +push ebx +push eax +mov eax,ecx +mov ecx,[ecx+12] +call dword[eax+8] +mov ecx,eax +pop eax +pop ebx +mov edi,[ebp+__io_cycle_counter] +mov esi,[ebp+__io_fetchbased_pc] +mov edx,[ebp+__access_address] +ret +times ($$-$)&15 db 0 +readmemorydword: +call readmemoryword +shl ecx,16 +push ecx +add edx,byte 2 +call readmemoryword +sub edx,byte 2 +and ecx,0FFFFh +or ecx,[esp] +add esp,byte 4 +ret +times ($$-$)&15 db 0 +writememorybyte: +mov [ebp+__access_address],edx +push ecx +writeb_top: +and edx,16777215 +mov ecx,[ebp+__writebyte] +writeb_check: +cmp edx,[ecx] +jb short writeb_next +cmp edx,[ecx+4] +jbe short writeb_call +writeb_next: +cmp dword[ecx],byte -1 +je short writeb_end +add ecx,byte 16 +jmp short writeb_check +writeb_call: +cmp dword[ecx+8],byte 0 +jne short writeb_callio +sub edx,[ecx] +add edx,[ecx+12] +xor edx,byte 1 +pop ecx +mov [edx],cl +mov edx,[ebp+__access_address] +ret +writeb_callio: +mov [ebp+__io_cycle_counter],edi +mov [ebp+__io_fetchbased_pc],esi +push ebx +push eax +mov ebx,ecx +mov eax,edx +xor edx,edx +mov dl,[esp+8] +push edx +mov edx,eax +mov ecx,[ebx+12] +call dword[ebx+8] +pop eax +pop ebx +mov edi,[ebp+__io_cycle_counter] +mov esi,[ebp+__io_fetchbased_pc] +writeb_end: +pop ecx +mov edx,[ebp+__access_address] +ret +times ($$-$)&15 db 0 +writememoryword: +mov [ebp+__access_address],edx +push ecx +writew_top: +and edx,16777215 +mov ecx,[ebp+__writeword] +writew_check: +cmp edx,[ecx] +jb short writew_next +cmp edx,[ecx+4] +jbe short writew_call +writew_next: +cmp dword[ecx],byte -1 +je short writew_end +add ecx,byte 16 +jmp short writew_check +writew_call: +cmp dword[ecx+8],byte 0 +jne short writew_callio +sub edx,[ecx] +add edx,[ecx+12] +pop ecx +mov [edx],cx +mov edx,[ebp+__access_address] +ret +writew_callio: +mov [ebp+__io_cycle_counter],edi +mov [ebp+__io_fetchbased_pc],esi +push ebx +push eax +mov ebx,ecx +mov eax,edx +xor edx,edx +mov dx,[esp+8] +push edx +mov edx,eax +mov ecx,[ebx+12] +call dword[ebx+8] +pop eax +pop ebx +mov edi,[ebp+__io_cycle_counter] +mov esi,[ebp+__io_fetchbased_pc] +writew_end: +pop ecx +mov edx,[ebp+__access_address] +ret +times ($$-$)&15 db 0 +writememorydword: +push ecx +shr ecx,16 +call writememoryword +mov ecx,[esp] +and ecx,0FFFFh +add edx,byte 2 +call writememoryword +sub edx,byte 2 +pop ecx +ret +group_1_exception: +group_2_exception: +and byte[ebp+__interrupts],0FEh +call readmemorydword +push ecx +mov ch,[ebp+__xflag] +mov cl,ah +shr cx,6 +add cl,cl +or cl,al +mov ch,ah +shl ch,8 +adc cl,cl +mov ch,[ebp+__sr+1] +push ecx +test byte[ebp+__sr+1],20h +jnz short ln2 +mov ecx,[ebp+__a7] +xchg ecx,[ebp+__asp] +mov [ebp+__a7],ecx +mov ecx,[ebp+__s_fetch] +mov [ebp+__fetch],ecx +mov ecx,[ebp+__s_readbyte] +mov [ebp+__readbyte],ecx +mov ecx,[ebp+__s_readword] +mov [ebp+__readword],ecx +mov ecx,[ebp+__s_writebyte] +mov [ebp+__writebyte],ecx +mov ecx,[ebp+__s_writeword] +mov [ebp+__writeword],ecx +or byte[ebp+__sr+1],20h +ln2: +and byte[ebp+__sr+1],27h +mov byte[ebp+__trace_trickybit],0 +mov ecx,esi +sub ecx,[ebp+__io_fetchbase] +mov edx,[ebp+__a7] +sub edx,byte 4 +call writememorydword +pop ecx +sub edx,byte 2 +call writememoryword +mov [ebp+__a7],edx +pop esi +ret +privilege_violation: +sub esi,byte 2 +mov edx,20h +call group_1_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln3 +cmp esi,[ebp+__fetch_region_end] +jbe short ln4 +ln3: +call basefunction +ln4: +add esi,[ebp+__io_fetchbase] +sub edi,byte 34 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +flush_interrupts: +sub esi,[ebp+__io_fetchbase] +mov dword[ebp+__io_fetchbase],0 +mov edx,7 +mov cl,80h +mov ch,[ebp+__sr+1] +and ch,7 +.loop: +test [ebp+__interrupts],cl +jz short .noint +mov [ebp+save_01], dl +mov dl,[ebp+__interrupts+edx] +not cl +and [ebp+__interrupts],cl +shl edx,2 +call group_1_exception +and [ebp+__sr + 1], byte 0xF8 +mov dl, [ebp+save_01] +sub edi,byte 44 +or [ebp+__sr + 1], dl +jmp short .intdone +.noint: +dec edx +jz short .intdone +shr cl,1 +cmp dl,ch +jg short .loop +.intdone: +ret +; Opcodes 0000 - 0007 +K000: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +or [ebp+__dreg+ebx*4],cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0010 - 0017 +K010: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +or cl,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0018 - 001F +K018: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +or cl,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0020 - 0027 +K020: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +or cl,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0028 - 002F +K028: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +or cl,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0030 - 0037 +K030: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +or cl,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememorybyte +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0038 +K038: +mov cx,[esi] +add esi,byte 2 +push ecx +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +or cl,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0039 +K039: +mov cx,[esi] +add esi,byte 2 +push ecx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +or cl,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememorybyte +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 003C +K03C: +mov ch,[ebp+__xflag] +mov cl,ah +shr cx,6 +add cl,cl +or cl,al +mov ch,ah +shl ch,8 +adc cl,cl +or cl,[esi] +add esi,byte 2 +mov al,cl +mov ah,al +and ax,0C10h +shl ah,3 +shr al,4 +mov [ebp+__xflag],al +mov al,cl +and al,3 +shr al,1 +adc ah,ah +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0040 - 0047 +K040: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +or [ebp+__dreg+ebx*4],cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0050 - 0057 +K050: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +or cx,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0058 - 005F +K058: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +or cx,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0060 - 0067 +K060: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +or cx,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0068 - 006F +K068: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +or cx,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0070 - 0077 +K070: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +or cx,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememoryword +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0078 +K078: +mov cx,[esi] +add esi,byte 2 +push ecx +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +or cx,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0079 +K079: +mov cx,[esi] +add esi,byte 2 +push ecx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +or cx,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememoryword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 007C +K07C: +test byte[ebp+__sr+1],20h +jz near privilege_violation +mov ch,[ebp+__xflag] +mov cl,ah +shr cx,6 +add cl,cl +or cl,al +mov ch,ah +shl ch,8 +adc cl,cl +mov ch,[ebp+__sr+1] +or cx,[esi] +add esi,byte 2 +push ecx +mov cl,[ebp+__sr+1] +and cx,2020h +xor ch,cl +jz near ln5 +mov ecx,[ebp+__a7] +xchg ecx,[ebp+__asp] +mov [ebp+__a7],ecx +test byte[esp+1],20h +jz short ln6 +mov ecx,[ebp+__s_fetch] +mov [ebp+__fetch],ecx +mov ecx,[ebp+__s_readbyte] +mov [ebp+__readbyte],ecx +mov ecx,[ebp+__s_readword] +mov [ebp+__readword],ecx +mov ecx,[ebp+__s_writebyte] +mov [ebp+__writebyte],ecx +mov ecx,[ebp+__s_writeword] +mov [ebp+__writeword],ecx +jmp short ln5 +ln6: +mov ecx,[ebp+__u_fetch] +mov [ebp+__fetch],ecx +mov ecx,[ebp+__u_readbyte] +mov [ebp+__readbyte],ecx +mov ecx,[ebp+__u_readword] +mov [ebp+__readword],ecx +mov ecx,[ebp+__u_writebyte] +mov [ebp+__writebyte],ecx +mov ecx,[ebp+__u_writeword] +mov [ebp+__writeword],ecx +ln5: +pop ecx +mov [ebp+__sr+1],ch +and byte[ebp+__sr+1],0A7h +mov al,cl +mov ah,al +and ax,0C10h +shl ah,3 +shr al,4 +mov [ebp+__xflag],al +mov al,cl +and al,3 +shr al,1 +adc ah,ah +sub edi,byte 20 +jmp exec_checkpoint +; Opcodes 0080 - 0087 +K080: +and ebx,byte 7 +mov ecx,[esi] +rol ecx,16 +add esi,byte 4 +or [ebp+__dreg+ebx*4],ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0090 - 0097 +K090: +and ebx,byte 7 +mov ecx,[esi] +rol ecx,16 +add esi,byte 4 +push ecx +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +or ecx,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0098 - 009F +K098: +and ebx,byte 7 +mov ecx,[esi] +rol ecx,16 +add esi,byte 4 +push ecx +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +or ecx,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 00A0 - 00A7 +K0A0: +and ebx,byte 7 +mov ecx,[esi] +rol ecx,16 +add esi,byte 4 +push ecx +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +or ecx,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 00A8 - 00AF +K0A8: +and ebx,byte 7 +mov ecx,[esi] +rol ecx,16 +add esi,byte 4 +push ecx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +or ecx,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememorydword +sub edi,byte 32 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 00B0 - 00B7 +K0B0: +and ebx,byte 7 +mov ecx,[esi] +rol ecx,16 +add esi,byte 4 +push ecx +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +or ecx,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememorydword +sub edi,byte 34 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 00B8 +K0B8: +mov ecx,[esi] +rol ecx,16 +add esi,byte 4 +push ecx +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +or ecx,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememorydword +sub edi,byte 32 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 00B9 +K0B9: +mov ecx,[esi] +rol ecx,16 +add esi,byte 4 +push ecx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +or ecx,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememorydword +sub edi,byte 36 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0100 - 0107 +K100: +mov cl,byte[ebp+__dreg+0] +and ebx,byte 7 +and ecx,byte 31 +mov edx,1 +shl edx,cl +test [ebp+__dreg+ebx*4],edx +jz short ln7 +and ah,0BFh +jmp short ln8 +ln7: +or ah,40h +ln8: +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0108 - 010F +K108: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov bh,cl +add edx,byte 2 +call readmemorybyte +mov bl,cl +mov [ebp+__dreg+0],bx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0110 - 0117 +K110: +mov cl,byte[ebp+__dreg+0] +and ebx,byte 7 +and ecx,byte 7 +push ecx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln9 +and ah,0BFh +jmp short ln10 +ln9: +or ah,40h +ln10: +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0118 - 011F +K118: +mov cl,byte[ebp+__dreg+0] +and ebx,byte 7 +and ecx,byte 7 +push ecx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln11 +and ah,0BFh +jmp short ln12 +ln11: +or ah,40h +ln12: +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0120 - 0127 +K120: +mov cl,byte[ebp+__dreg+0] +and ebx,byte 7 +and ecx,byte 7 +push ecx +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln13 +and ah,0BFh +jmp short ln14 +ln13: +or ah,40h +ln14: +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0128 - 012F +K128: +mov cl,byte[ebp+__dreg+0] +and ebx,byte 7 +and ecx,byte 7 +push ecx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln15 +and ah,0BFh +jmp short ln16 +ln15: +or ah,40h +ln16: +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0130 - 0137 +K130: +mov cl,byte[ebp+__dreg+0] +and ebx,byte 7 +and ecx,byte 7 +push ecx +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln17 +and ah,0BFh +jmp short ln18 +ln17: +or ah,40h +ln18: +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0138 +K138: +mov cl,byte[ebp+__dreg+0] +and ecx,byte 7 +push ecx +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln19 +and ah,0BFh +jmp short ln20 +ln19: +or ah,40h +ln20: +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0139 +K139: +mov cl,byte[ebp+__dreg+0] +and ecx,byte 7 +push ecx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln21 +and ah,0BFh +jmp short ln22 +ln21: +or ah,40h +ln22: +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 013A +K13A: +mov cl,byte[ebp+__dreg+0] +and ecx,byte 7 +push ecx +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln23 +and ah,0BFh +jmp short ln24 +ln23: +or ah,40h +ln24: +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 013B +K13B: +mov cl,byte[ebp+__dreg+0] +and ecx,byte 7 +push ecx +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln25 +and ah,0BFh +jmp short ln26 +ln25: +or ah,40h +ln26: +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 013C +K13C: +mov cl,byte[ebp+__dreg+0] +and ecx,byte 7 +push ecx +mov cx,[esi] +add esi,byte 2 +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln27 +and ah,0BFh +jmp short ln28 +ln27: +or ah,40h +ln28: +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0140 - 0147 +K140: +mov cl,byte[ebp+__dreg+0] +and ebx,byte 7 +and ecx,byte 31 +mov edx,1 +shl edx,cl +mov ecx,[ebp+__dreg+ebx*4] +test ecx,edx +jz short ln29 +and ah,0BFh +jmp short ln30 +ln29: +or ah,40h +ln30: +xor ecx,edx +mov [ebp+__dreg+ebx*4],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0148 - 014F +K148: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov bh,cl +add edx,byte 2 +call readmemorybyte +mov bl,cl +add edx,byte 2 +shl ebx,16 +call readmemorybyte +mov bh,cl +add edx,byte 2 +call readmemorybyte +mov bl,cl +mov [ebp+__dreg+0],ebx +xor ebx,ebx +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0150 - 0157 +K150: +mov cl,byte[ebp+__dreg+0] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln31 +and ah,0BFh +jmp short ln32 +ln31: +or ah,40h +ln32: +xor cl,dl +pop edx +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0158 - 015F +K158: +mov cl,byte[ebp+__dreg+0] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln33 +and ah,0BFh +jmp short ln34 +ln33: +or ah,40h +ln34: +xor cl,dl +pop edx +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0160 - 0167 +K160: +mov cl,byte[ebp+__dreg+0] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln35 +and ah,0BFh +jmp short ln36 +ln35: +or ah,40h +ln36: +xor cl,dl +pop edx +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0168 - 016F +K168: +mov cl,byte[ebp+__dreg+0] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln37 +and ah,0BFh +jmp short ln38 +ln37: +or ah,40h +ln38: +xor cl,dl +pop edx +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0170 - 0177 +K170: +mov cl,byte[ebp+__dreg+0] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln39 +and ah,0BFh +jmp short ln40 +ln39: +or ah,40h +ln40: +xor cl,dl +pop edx +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0178 +K178: +mov cl,byte[ebp+__dreg+0] +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln41 +and ah,0BFh +jmp short ln42 +ln41: +or ah,40h +ln42: +xor cl,dl +pop edx +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0179 +K179: +mov cl,byte[ebp+__dreg+0] +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln43 +and ah,0BFh +jmp short ln44 +ln43: +or ah,40h +ln44: +xor cl,dl +pop edx +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0180 - 0187 +K180: +mov cl,byte[ebp+__dreg+0] +and ebx,byte 7 +and ecx,byte 31 +mov edx,1 +shl edx,cl +mov ecx,[ebp+__dreg+ebx*4] +test ecx,edx +jz short ln45 +and ah,0BFh +jmp short ln46 +ln45: +or ah,40h +ln46: +not edx +and ecx,edx +mov [ebp+__dreg+ebx*4],ecx +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0188 - 018F +K188: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +mov ebx,[ebp+__dreg+0] +mov cl,bh +call writememorybyte +add edx,byte 2 +mov cl,bl +call writememorybyte +xor ebx,ebx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0190 - 0197 +K190: +mov cl,byte[ebp+__dreg+0] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln47 +and ah,0BFh +jmp short ln48 +ln47: +or ah,40h +ln48: +not dl +and cl,dl +pop edx +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0198 - 019F +K198: +mov cl,byte[ebp+__dreg+0] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln49 +and ah,0BFh +jmp short ln50 +ln49: +or ah,40h +ln50: +not dl +and cl,dl +pop edx +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 01A0 - 01A7 +K1A0: +mov cl,byte[ebp+__dreg+0] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln51 +and ah,0BFh +jmp short ln52 +ln51: +or ah,40h +ln52: +not dl +and cl,dl +pop edx +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 01A8 - 01AF +K1A8: +mov cl,byte[ebp+__dreg+0] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln53 +and ah,0BFh +jmp short ln54 +ln53: +or ah,40h +ln54: +not dl +and cl,dl +pop edx +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 01B0 - 01B7 +K1B0: +mov cl,byte[ebp+__dreg+0] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln55 +and ah,0BFh +jmp short ln56 +ln55: +or ah,40h +ln56: +not dl +and cl,dl +pop edx +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 01B8 +K1B8: +mov cl,byte[ebp+__dreg+0] +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln57 +and ah,0BFh +jmp short ln58 +ln57: +or ah,40h +ln58: +not dl +and cl,dl +pop edx +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 01B9 +K1B9: +mov cl,byte[ebp+__dreg+0] +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln59 +and ah,0BFh +jmp short ln60 +ln59: +or ah,40h +ln60: +not dl +and cl,dl +pop edx +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 01C0 - 01C7 +K1C0: +mov cl,byte[ebp+__dreg+0] +and ebx,byte 7 +and ecx,byte 31 +mov edx,1 +shl edx,cl +mov ecx,[ebp+__dreg+ebx*4] +test ecx,edx +jz short ln61 +and ah,0BFh +jmp short ln62 +ln61: +or ah,40h +ln62: +or ecx,edx +mov [ebp+__dreg+ebx*4],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 01C8 - 01CF +K1C8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +mov ebx,[ebp+__dreg+0] +rol ebx,16 +mov cl,bh +call writememorybyte +add edx,byte 2 +mov cl,bl +call writememorybyte +add edx,byte 2 +rol ebx,16 +mov cl,bh +call writememorybyte +add edx,byte 2 +mov cl,bl +call writememorybyte +xor ebx,ebx +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 01D0 - 01D7 +K1D0: +mov cl,byte[ebp+__dreg+0] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln63 +and ah,0BFh +jmp short ln64 +ln63: +or ah,40h +ln64: +or cl,dl +pop edx +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 01D8 - 01DF +K1D8: +mov cl,byte[ebp+__dreg+0] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln65 +and ah,0BFh +jmp short ln66 +ln65: +or ah,40h +ln66: +or cl,dl +pop edx +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 01E0 - 01E7 +K1E0: +mov cl,byte[ebp+__dreg+0] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln67 +and ah,0BFh +jmp short ln68 +ln67: +or ah,40h +ln68: +or cl,dl +pop edx +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 01E8 - 01EF +K1E8: +mov cl,byte[ebp+__dreg+0] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln69 +and ah,0BFh +jmp short ln70 +ln69: +or ah,40h +ln70: +or cl,dl +pop edx +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 01F0 - 01F7 +K1F0: +mov cl,byte[ebp+__dreg+0] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln71 +and ah,0BFh +jmp short ln72 +ln71: +or ah,40h +ln72: +or cl,dl +pop edx +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 01F8 +K1F8: +mov cl,byte[ebp+__dreg+0] +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln73 +and ah,0BFh +jmp short ln74 +ln73: +or ah,40h +ln74: +or cl,dl +pop edx +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 01F9 +K1F9: +mov cl,byte[ebp+__dreg+0] +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln75 +and ah,0BFh +jmp short ln76 +ln75: +or ah,40h +ln76: +or cl,dl +pop edx +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0200 - 0207 +K200: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +and [ebp+__dreg+ebx*4],cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0210 - 0217 +K210: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +and cl,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0218 - 021F +K218: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +and cl,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0220 - 0227 +K220: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +and cl,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0228 - 022F +K228: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +and cl,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0230 - 0237 +K230: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +and cl,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememorybyte +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0238 +K238: +mov cx,[esi] +add esi,byte 2 +push ecx +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +and cl,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0239 +K239: +mov cx,[esi] +add esi,byte 2 +push ecx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +and cl,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememorybyte +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 023C +K23C: +mov ch,[ebp+__xflag] +mov cl,ah +shr cx,6 +add cl,cl +or cl,al +mov ch,ah +shl ch,8 +adc cl,cl +and cl,[esi] +add esi,byte 2 +mov al,cl +mov ah,al +and ax,0C10h +shl ah,3 +shr al,4 +mov [ebp+__xflag],al +mov al,cl +and al,3 +shr al,1 +adc ah,ah +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0240 - 0247 +K240: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +and [ebp+__dreg+ebx*4],cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0250 - 0257 +K250: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +and cx,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0258 - 025F +K258: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +and cx,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0260 - 0267 +K260: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +and cx,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0268 - 026F +K268: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +and cx,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0270 - 0277 +K270: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +and cx,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememoryword +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0278 +K278: +mov cx,[esi] +add esi,byte 2 +push ecx +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +and cx,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0279 +K279: +mov cx,[esi] +add esi,byte 2 +push ecx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +and cx,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememoryword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 027C +K27C: +test byte[ebp+__sr+1],20h +jz near privilege_violation +mov ch,[ebp+__xflag] +mov cl,ah +shr cx,6 +add cl,cl +or cl,al +mov ch,ah +shl ch,8 +adc cl,cl +mov ch,[ebp+__sr+1] +and cx,[esi] +add esi,byte 2 +push ecx +mov cl,[ebp+__sr+1] +and cx,2020h +xor ch,cl +jz near ln77 +mov ecx,[ebp+__a7] +xchg ecx,[ebp+__asp] +mov [ebp+__a7],ecx +test byte[esp+1],20h +jz short ln78 +mov ecx,[ebp+__s_fetch] +mov [ebp+__fetch],ecx +mov ecx,[ebp+__s_readbyte] +mov [ebp+__readbyte],ecx +mov ecx,[ebp+__s_readword] +mov [ebp+__readword],ecx +mov ecx,[ebp+__s_writebyte] +mov [ebp+__writebyte],ecx +mov ecx,[ebp+__s_writeword] +mov [ebp+__writeword],ecx +jmp short ln77 +ln78: +mov ecx,[ebp+__u_fetch] +mov [ebp+__fetch],ecx +mov ecx,[ebp+__u_readbyte] +mov [ebp+__readbyte],ecx +mov ecx,[ebp+__u_readword] +mov [ebp+__readword],ecx +mov ecx,[ebp+__u_writebyte] +mov [ebp+__writebyte],ecx +mov ecx,[ebp+__u_writeword] +mov [ebp+__writeword],ecx +ln77: +pop ecx +mov [ebp+__sr+1],ch +and byte[ebp+__sr+1],0A7h +mov al,cl +mov ah,al +and ax,0C10h +shl ah,3 +shr al,4 +mov [ebp+__xflag],al +mov al,cl +and al,3 +shr al,1 +adc ah,ah +sub edi,byte 20 +jmp exec_checkpoint +; Opcodes 0280 - 0287 +K280: +and ebx,byte 7 +mov ecx,[esi] +rol ecx,16 +add esi,byte 4 +and [ebp+__dreg+ebx*4],ecx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0290 - 0297 +K290: +and ebx,byte 7 +mov ecx,[esi] +rol ecx,16 +add esi,byte 4 +push ecx +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +and ecx,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0298 - 029F +K298: +and ebx,byte 7 +mov ecx,[esi] +rol ecx,16 +add esi,byte 4 +push ecx +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +and ecx,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 02A0 - 02A7 +K2A0: +and ebx,byte 7 +mov ecx,[esi] +rol ecx,16 +add esi,byte 4 +push ecx +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +and ecx,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 02A8 - 02AF +K2A8: +and ebx,byte 7 +mov ecx,[esi] +rol ecx,16 +add esi,byte 4 +push ecx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +and ecx,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememorydword +sub edi,byte 32 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 02B0 - 02B7 +K2B0: +and ebx,byte 7 +mov ecx,[esi] +rol ecx,16 +add esi,byte 4 +push ecx +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +and ecx,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememorydword +sub edi,byte 34 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 02B8 +K2B8: +mov ecx,[esi] +rol ecx,16 +add esi,byte 4 +push ecx +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +and ecx,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememorydword +sub edi,byte 32 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 02B9 +K2B9: +mov ecx,[esi] +rol ecx,16 +add esi,byte 4 +push ecx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +and ecx,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememorydword +sub edi,byte 36 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0300 - 0307 +K300: +mov cl,byte[ebp+__dreg+4] +and ebx,byte 7 +and ecx,byte 31 +mov edx,1 +shl edx,cl +test [ebp+__dreg+ebx*4],edx +jz short ln79 +and ah,0BFh +jmp short ln80 +ln79: +or ah,40h +ln80: +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0308 - 030F +K308: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov bh,cl +add edx,byte 2 +call readmemorybyte +mov bl,cl +mov [ebp+__dreg+4],bx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0310 - 0317 +K310: +mov cl,byte[ebp+__dreg+4] +and ebx,byte 7 +and ecx,byte 7 +push ecx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln81 +and ah,0BFh +jmp short ln82 +ln81: +or ah,40h +ln82: +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0318 - 031F +K318: +mov cl,byte[ebp+__dreg+4] +and ebx,byte 7 +and ecx,byte 7 +push ecx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln83 +and ah,0BFh +jmp short ln84 +ln83: +or ah,40h +ln84: +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0320 - 0327 +K320: +mov cl,byte[ebp+__dreg+4] +and ebx,byte 7 +and ecx,byte 7 +push ecx +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln85 +and ah,0BFh +jmp short ln86 +ln85: +or ah,40h +ln86: +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0328 - 032F +K328: +mov cl,byte[ebp+__dreg+4] +and ebx,byte 7 +and ecx,byte 7 +push ecx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln87 +and ah,0BFh +jmp short ln88 +ln87: +or ah,40h +ln88: +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0330 - 0337 +K330: +mov cl,byte[ebp+__dreg+4] +and ebx,byte 7 +and ecx,byte 7 +push ecx +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln89 +and ah,0BFh +jmp short ln90 +ln89: +or ah,40h +ln90: +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0338 +K338: +mov cl,byte[ebp+__dreg+4] +and ecx,byte 7 +push ecx +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln91 +and ah,0BFh +jmp short ln92 +ln91: +or ah,40h +ln92: +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0339 +K339: +mov cl,byte[ebp+__dreg+4] +and ecx,byte 7 +push ecx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln93 +and ah,0BFh +jmp short ln94 +ln93: +or ah,40h +ln94: +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 033A +K33A: +mov cl,byte[ebp+__dreg+4] +and ecx,byte 7 +push ecx +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln95 +and ah,0BFh +jmp short ln96 +ln95: +or ah,40h +ln96: +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 033B +K33B: +mov cl,byte[ebp+__dreg+4] +and ecx,byte 7 +push ecx +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln97 +and ah,0BFh +jmp short ln98 +ln97: +or ah,40h +ln98: +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 033C +K33C: +mov cl,byte[ebp+__dreg+4] +and ecx,byte 7 +push ecx +mov cx,[esi] +add esi,byte 2 +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln99 +and ah,0BFh +jmp short ln100 +ln99: +or ah,40h +ln100: +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0340 - 0347 +K340: +mov cl,byte[ebp+__dreg+4] +and ebx,byte 7 +and ecx,byte 31 +mov edx,1 +shl edx,cl +mov ecx,[ebp+__dreg+ebx*4] +test ecx,edx +jz short ln101 +and ah,0BFh +jmp short ln102 +ln101: +or ah,40h +ln102: +xor ecx,edx +mov [ebp+__dreg+ebx*4],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0348 - 034F +K348: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov bh,cl +add edx,byte 2 +call readmemorybyte +mov bl,cl +add edx,byte 2 +shl ebx,16 +call readmemorybyte +mov bh,cl +add edx,byte 2 +call readmemorybyte +mov bl,cl +mov [ebp+__dreg+4],ebx +xor ebx,ebx +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0350 - 0357 +K350: +mov cl,byte[ebp+__dreg+4] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln103 +and ah,0BFh +jmp short ln104 +ln103: +or ah,40h +ln104: +xor cl,dl +pop edx +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0358 - 035F +K358: +mov cl,byte[ebp+__dreg+4] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln105 +and ah,0BFh +jmp short ln106 +ln105: +or ah,40h +ln106: +xor cl,dl +pop edx +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0360 - 0367 +K360: +mov cl,byte[ebp+__dreg+4] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln107 +and ah,0BFh +jmp short ln108 +ln107: +or ah,40h +ln108: +xor cl,dl +pop edx +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0368 - 036F +K368: +mov cl,byte[ebp+__dreg+4] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln109 +and ah,0BFh +jmp short ln110 +ln109: +or ah,40h +ln110: +xor cl,dl +pop edx +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0370 - 0377 +K370: +mov cl,byte[ebp+__dreg+4] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln111 +and ah,0BFh +jmp short ln112 +ln111: +or ah,40h +ln112: +xor cl,dl +pop edx +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0378 +K378: +mov cl,byte[ebp+__dreg+4] +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln113 +and ah,0BFh +jmp short ln114 +ln113: +or ah,40h +ln114: +xor cl,dl +pop edx +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0379 +K379: +mov cl,byte[ebp+__dreg+4] +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln115 +and ah,0BFh +jmp short ln116 +ln115: +or ah,40h +ln116: +xor cl,dl +pop edx +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0380 - 0387 +K380: +mov cl,byte[ebp+__dreg+4] +and ebx,byte 7 +and ecx,byte 31 +mov edx,1 +shl edx,cl +mov ecx,[ebp+__dreg+ebx*4] +test ecx,edx +jz short ln117 +and ah,0BFh +jmp short ln118 +ln117: +or ah,40h +ln118: +not edx +and ecx,edx +mov [ebp+__dreg+ebx*4],ecx +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0388 - 038F +K388: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +mov ebx,[ebp+__dreg+4] +mov cl,bh +call writememorybyte +add edx,byte 2 +mov cl,bl +call writememorybyte +xor ebx,ebx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0390 - 0397 +K390: +mov cl,byte[ebp+__dreg+4] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln119 +and ah,0BFh +jmp short ln120 +ln119: +or ah,40h +ln120: +not dl +and cl,dl +pop edx +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0398 - 039F +K398: +mov cl,byte[ebp+__dreg+4] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln121 +and ah,0BFh +jmp short ln122 +ln121: +or ah,40h +ln122: +not dl +and cl,dl +pop edx +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 03A0 - 03A7 +K3A0: +mov cl,byte[ebp+__dreg+4] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln123 +and ah,0BFh +jmp short ln124 +ln123: +or ah,40h +ln124: +not dl +and cl,dl +pop edx +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 03A8 - 03AF +K3A8: +mov cl,byte[ebp+__dreg+4] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln125 +and ah,0BFh +jmp short ln126 +ln125: +or ah,40h +ln126: +not dl +and cl,dl +pop edx +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 03B0 - 03B7 +K3B0: +mov cl,byte[ebp+__dreg+4] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln127 +and ah,0BFh +jmp short ln128 +ln127: +or ah,40h +ln128: +not dl +and cl,dl +pop edx +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 03B8 +K3B8: +mov cl,byte[ebp+__dreg+4] +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln129 +and ah,0BFh +jmp short ln130 +ln129: +or ah,40h +ln130: +not dl +and cl,dl +pop edx +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 03B9 +K3B9: +mov cl,byte[ebp+__dreg+4] +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln131 +and ah,0BFh +jmp short ln132 +ln131: +or ah,40h +ln132: +not dl +and cl,dl +pop edx +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 03C0 - 03C7 +K3C0: +mov cl,byte[ebp+__dreg+4] +and ebx,byte 7 +and ecx,byte 31 +mov edx,1 +shl edx,cl +mov ecx,[ebp+__dreg+ebx*4] +test ecx,edx +jz short ln133 +and ah,0BFh +jmp short ln134 +ln133: +or ah,40h +ln134: +or ecx,edx +mov [ebp+__dreg+ebx*4],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 03C8 - 03CF +K3C8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +mov ebx,[ebp+__dreg+4] +rol ebx,16 +mov cl,bh +call writememorybyte +add edx,byte 2 +mov cl,bl +call writememorybyte +add edx,byte 2 +rol ebx,16 +mov cl,bh +call writememorybyte +add edx,byte 2 +mov cl,bl +call writememorybyte +xor ebx,ebx +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 03D0 - 03D7 +K3D0: +mov cl,byte[ebp+__dreg+4] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln135 +and ah,0BFh +jmp short ln136 +ln135: +or ah,40h +ln136: +or cl,dl +pop edx +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 03D8 - 03DF +K3D8: +mov cl,byte[ebp+__dreg+4] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln137 +and ah,0BFh +jmp short ln138 +ln137: +or ah,40h +ln138: +or cl,dl +pop edx +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 03E0 - 03E7 +K3E0: +mov cl,byte[ebp+__dreg+4] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln139 +and ah,0BFh +jmp short ln140 +ln139: +or ah,40h +ln140: +or cl,dl +pop edx +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 03E8 - 03EF +K3E8: +mov cl,byte[ebp+__dreg+4] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln141 +and ah,0BFh +jmp short ln142 +ln141: +or ah,40h +ln142: +or cl,dl +pop edx +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 03F0 - 03F7 +K3F0: +mov cl,byte[ebp+__dreg+4] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln143 +and ah,0BFh +jmp short ln144 +ln143: +or ah,40h +ln144: +or cl,dl +pop edx +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 03F8 +K3F8: +mov cl,byte[ebp+__dreg+4] +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln145 +and ah,0BFh +jmp short ln146 +ln145: +or ah,40h +ln146: +or cl,dl +pop edx +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 03F9 +K3F9: +mov cl,byte[ebp+__dreg+4] +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln147 +and ah,0BFh +jmp short ln148 +ln147: +or ah,40h +ln148: +or cl,dl +pop edx +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0400 - 0407 +K400: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +sub [ebp+__dreg+ebx*4],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0410 - 0417 +K410: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,[esp] +lahf +seto al +setc [ebp+__xflag] +add esp,byte 4 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0418 - 041F +K418: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,[esp] +lahf +seto al +setc [ebp+__xflag] +add esp,byte 4 +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0420 - 0427 +K420: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +sub cl,[esp] +lahf +seto al +setc [ebp+__xflag] +add esp,byte 4 +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0428 - 042F +K428: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,[esp] +lahf +seto al +setc [ebp+__xflag] +add esp,byte 4 +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0430 - 0437 +K430: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,[esp] +lahf +seto al +setc [ebp+__xflag] +add esp,byte 4 +call writememorybyte +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0438 +K438: +mov cx,[esi] +add esi,byte 2 +push ecx +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +sub cl,[esp] +lahf +seto al +setc [ebp+__xflag] +add esp,byte 4 +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0439 +K439: +mov cx,[esi] +add esi,byte 2 +push ecx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +sub cl,[esp] +lahf +seto al +setc [ebp+__xflag] +add esp,byte 4 +call writememorybyte +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0440 - 0447 +K440: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +sub [ebp+__dreg+ebx*4],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0450 - 0457 +K450: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,[esp] +lahf +seto al +setc [ebp+__xflag] +add esp,byte 4 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0458 - 045F +K458: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,[esp] +lahf +seto al +setc [ebp+__xflag] +add esp,byte 4 +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0460 - 0467 +K460: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +sub cx,[esp] +lahf +seto al +setc [ebp+__xflag] +add esp,byte 4 +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0468 - 046F +K468: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,[esp] +lahf +seto al +setc [ebp+__xflag] +add esp,byte 4 +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0470 - 0477 +K470: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,[esp] +lahf +seto al +setc [ebp+__xflag] +add esp,byte 4 +call writememoryword +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0478 +K478: +mov cx,[esi] +add esi,byte 2 +push ecx +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +sub cx,[esp] +lahf +seto al +setc [ebp+__xflag] +add esp,byte 4 +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0479 +K479: +mov cx,[esi] +add esi,byte 2 +push ecx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +sub cx,[esp] +lahf +seto al +setc [ebp+__xflag] +add esp,byte 4 +call writememoryword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0480 - 0487 +K480: +and ebx,byte 7 +mov ecx,[esi] +rol ecx,16 +add esi,byte 4 +sub [ebp+__dreg+ebx*4],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0490 - 0497 +K490: +and ebx,byte 7 +mov ecx,[esi] +rol ecx,16 +add esi,byte 4 +push ecx +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,[esp] +lahf +seto al +setc [ebp+__xflag] +add esp,byte 4 +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0498 - 049F +K498: +and ebx,byte 7 +mov ecx,[esi] +rol ecx,16 +add esi,byte 4 +push ecx +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,[esp] +lahf +seto al +setc [ebp+__xflag] +add esp,byte 4 +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 04A0 - 04A7 +K4A0: +and ebx,byte 7 +mov ecx,[esi] +rol ecx,16 +add esi,byte 4 +push ecx +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +sub ecx,[esp] +lahf +seto al +setc [ebp+__xflag] +add esp,byte 4 +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 04A8 - 04AF +K4A8: +and ebx,byte 7 +mov ecx,[esi] +rol ecx,16 +add esi,byte 4 +push ecx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,[esp] +lahf +seto al +setc [ebp+__xflag] +add esp,byte 4 +call writememorydword +sub edi,byte 32 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 04B0 - 04B7 +K4B0: +and ebx,byte 7 +mov ecx,[esi] +rol ecx,16 +add esi,byte 4 +push ecx +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,[esp] +lahf +seto al +setc [ebp+__xflag] +add esp,byte 4 +call writememorydword +sub edi,byte 34 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 04B8 +K4B8: +mov ecx,[esi] +rol ecx,16 +add esi,byte 4 +push ecx +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +sub ecx,[esp] +lahf +seto al +setc [ebp+__xflag] +add esp,byte 4 +call writememorydword +sub edi,byte 32 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 04B9 +K4B9: +mov ecx,[esi] +rol ecx,16 +add esi,byte 4 +push ecx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +sub ecx,[esp] +lahf +seto al +setc [ebp+__xflag] +add esp,byte 4 +call writememorydword +sub edi,byte 36 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0500 - 0507 +K500: +mov cl,byte[ebp+__dreg+8] +and ebx,byte 7 +and ecx,byte 31 +mov edx,1 +shl edx,cl +test [ebp+__dreg+ebx*4],edx +jz short ln149 +and ah,0BFh +jmp short ln150 +ln149: +or ah,40h +ln150: +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0508 - 050F +K508: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov bh,cl +add edx,byte 2 +call readmemorybyte +mov bl,cl +mov [ebp+__dreg+8],bx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0510 - 0517 +K510: +mov cl,byte[ebp+__dreg+8] +and ebx,byte 7 +and ecx,byte 7 +push ecx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln151 +and ah,0BFh +jmp short ln152 +ln151: +or ah,40h +ln152: +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0518 - 051F +K518: +mov cl,byte[ebp+__dreg+8] +and ebx,byte 7 +and ecx,byte 7 +push ecx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln153 +and ah,0BFh +jmp short ln154 +ln153: +or ah,40h +ln154: +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0520 - 0527 +K520: +mov cl,byte[ebp+__dreg+8] +and ebx,byte 7 +and ecx,byte 7 +push ecx +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln155 +and ah,0BFh +jmp short ln156 +ln155: +or ah,40h +ln156: +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0528 - 052F +K528: +mov cl,byte[ebp+__dreg+8] +and ebx,byte 7 +and ecx,byte 7 +push ecx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln157 +and ah,0BFh +jmp short ln158 +ln157: +or ah,40h +ln158: +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0530 - 0537 +K530: +mov cl,byte[ebp+__dreg+8] +and ebx,byte 7 +and ecx,byte 7 +push ecx +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln159 +and ah,0BFh +jmp short ln160 +ln159: +or ah,40h +ln160: +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0538 +K538: +mov cl,byte[ebp+__dreg+8] +and ecx,byte 7 +push ecx +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln161 +and ah,0BFh +jmp short ln162 +ln161: +or ah,40h +ln162: +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0539 +K539: +mov cl,byte[ebp+__dreg+8] +and ecx,byte 7 +push ecx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln163 +and ah,0BFh +jmp short ln164 +ln163: +or ah,40h +ln164: +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 053A +K53A: +mov cl,byte[ebp+__dreg+8] +and ecx,byte 7 +push ecx +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln165 +and ah,0BFh +jmp short ln166 +ln165: +or ah,40h +ln166: +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 053B +K53B: +mov cl,byte[ebp+__dreg+8] +and ecx,byte 7 +push ecx +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln167 +and ah,0BFh +jmp short ln168 +ln167: +or ah,40h +ln168: +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 053C +K53C: +mov cl,byte[ebp+__dreg+8] +and ecx,byte 7 +push ecx +mov cx,[esi] +add esi,byte 2 +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln169 +and ah,0BFh +jmp short ln170 +ln169: +or ah,40h +ln170: +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0540 - 0547 +K540: +mov cl,byte[ebp+__dreg+8] +and ebx,byte 7 +and ecx,byte 31 +mov edx,1 +shl edx,cl +mov ecx,[ebp+__dreg+ebx*4] +test ecx,edx +jz short ln171 +and ah,0BFh +jmp short ln172 +ln171: +or ah,40h +ln172: +xor ecx,edx +mov [ebp+__dreg+ebx*4],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0548 - 054F +K548: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov bh,cl +add edx,byte 2 +call readmemorybyte +mov bl,cl +add edx,byte 2 +shl ebx,16 +call readmemorybyte +mov bh,cl +add edx,byte 2 +call readmemorybyte +mov bl,cl +mov [ebp+__dreg+8],ebx +xor ebx,ebx +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0550 - 0557 +K550: +mov cl,byte[ebp+__dreg+8] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln173 +and ah,0BFh +jmp short ln174 +ln173: +or ah,40h +ln174: +xor cl,dl +pop edx +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0558 - 055F +K558: +mov cl,byte[ebp+__dreg+8] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln175 +and ah,0BFh +jmp short ln176 +ln175: +or ah,40h +ln176: +xor cl,dl +pop edx +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0560 - 0567 +K560: +mov cl,byte[ebp+__dreg+8] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln177 +and ah,0BFh +jmp short ln178 +ln177: +or ah,40h +ln178: +xor cl,dl +pop edx +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0568 - 056F +K568: +mov cl,byte[ebp+__dreg+8] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln179 +and ah,0BFh +jmp short ln180 +ln179: +or ah,40h +ln180: +xor cl,dl +pop edx +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0570 - 0577 +K570: +mov cl,byte[ebp+__dreg+8] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln181 +and ah,0BFh +jmp short ln182 +ln181: +or ah,40h +ln182: +xor cl,dl +pop edx +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0578 +K578: +mov cl,byte[ebp+__dreg+8] +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln183 +and ah,0BFh +jmp short ln184 +ln183: +or ah,40h +ln184: +xor cl,dl +pop edx +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0579 +K579: +mov cl,byte[ebp+__dreg+8] +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln185 +and ah,0BFh +jmp short ln186 +ln185: +or ah,40h +ln186: +xor cl,dl +pop edx +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0580 - 0587 +K580: +mov cl,byte[ebp+__dreg+8] +and ebx,byte 7 +and ecx,byte 31 +mov edx,1 +shl edx,cl +mov ecx,[ebp+__dreg+ebx*4] +test ecx,edx +jz short ln187 +and ah,0BFh +jmp short ln188 +ln187: +or ah,40h +ln188: +not edx +and ecx,edx +mov [ebp+__dreg+ebx*4],ecx +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0588 - 058F +K588: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +mov ebx,[ebp+__dreg+8] +mov cl,bh +call writememorybyte +add edx,byte 2 +mov cl,bl +call writememorybyte +xor ebx,ebx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0590 - 0597 +K590: +mov cl,byte[ebp+__dreg+8] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln189 +and ah,0BFh +jmp short ln190 +ln189: +or ah,40h +ln190: +not dl +and cl,dl +pop edx +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0598 - 059F +K598: +mov cl,byte[ebp+__dreg+8] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln191 +and ah,0BFh +jmp short ln192 +ln191: +or ah,40h +ln192: +not dl +and cl,dl +pop edx +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 05A0 - 05A7 +K5A0: +mov cl,byte[ebp+__dreg+8] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln193 +and ah,0BFh +jmp short ln194 +ln193: +or ah,40h +ln194: +not dl +and cl,dl +pop edx +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 05A8 - 05AF +K5A8: +mov cl,byte[ebp+__dreg+8] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln195 +and ah,0BFh +jmp short ln196 +ln195: +or ah,40h +ln196: +not dl +and cl,dl +pop edx +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 05B0 - 05B7 +K5B0: +mov cl,byte[ebp+__dreg+8] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln197 +and ah,0BFh +jmp short ln198 +ln197: +or ah,40h +ln198: +not dl +and cl,dl +pop edx +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 05B8 +K5B8: +mov cl,byte[ebp+__dreg+8] +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln199 +and ah,0BFh +jmp short ln200 +ln199: +or ah,40h +ln200: +not dl +and cl,dl +pop edx +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 05B9 +K5B9: +mov cl,byte[ebp+__dreg+8] +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln201 +and ah,0BFh +jmp short ln202 +ln201: +or ah,40h +ln202: +not dl +and cl,dl +pop edx +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 05C0 - 05C7 +K5C0: +mov cl,byte[ebp+__dreg+8] +and ebx,byte 7 +and ecx,byte 31 +mov edx,1 +shl edx,cl +mov ecx,[ebp+__dreg+ebx*4] +test ecx,edx +jz short ln203 +and ah,0BFh +jmp short ln204 +ln203: +or ah,40h +ln204: +or ecx,edx +mov [ebp+__dreg+ebx*4],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 05C8 - 05CF +K5C8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +mov ebx,[ebp+__dreg+8] +rol ebx,16 +mov cl,bh +call writememorybyte +add edx,byte 2 +mov cl,bl +call writememorybyte +add edx,byte 2 +rol ebx,16 +mov cl,bh +call writememorybyte +add edx,byte 2 +mov cl,bl +call writememorybyte +xor ebx,ebx +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 05D0 - 05D7 +K5D0: +mov cl,byte[ebp+__dreg+8] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln205 +and ah,0BFh +jmp short ln206 +ln205: +or ah,40h +ln206: +or cl,dl +pop edx +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 05D8 - 05DF +K5D8: +mov cl,byte[ebp+__dreg+8] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln207 +and ah,0BFh +jmp short ln208 +ln207: +or ah,40h +ln208: +or cl,dl +pop edx +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 05E0 - 05E7 +K5E0: +mov cl,byte[ebp+__dreg+8] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln209 +and ah,0BFh +jmp short ln210 +ln209: +or ah,40h +ln210: +or cl,dl +pop edx +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 05E8 - 05EF +K5E8: +mov cl,byte[ebp+__dreg+8] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln211 +and ah,0BFh +jmp short ln212 +ln211: +or ah,40h +ln212: +or cl,dl +pop edx +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 05F0 - 05F7 +K5F0: +mov cl,byte[ebp+__dreg+8] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln213 +and ah,0BFh +jmp short ln214 +ln213: +or ah,40h +ln214: +or cl,dl +pop edx +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 05F8 +K5F8: +mov cl,byte[ebp+__dreg+8] +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln215 +and ah,0BFh +jmp short ln216 +ln215: +or ah,40h +ln216: +or cl,dl +pop edx +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 05F9 +K5F9: +mov cl,byte[ebp+__dreg+8] +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln217 +and ah,0BFh +jmp short ln218 +ln217: +or ah,40h +ln218: +or cl,dl +pop edx +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0600 - 0607 +K600: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +add [ebp+__dreg+ebx*4],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0610 - 0617 +K610: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,[esp] +lahf +seto al +setc [ebp+__xflag] +add esp,byte 4 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0618 - 061F +K618: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,[esp] +lahf +seto al +setc [ebp+__xflag] +add esp,byte 4 +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0620 - 0627 +K620: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +add cl,[esp] +lahf +seto al +setc [ebp+__xflag] +add esp,byte 4 +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0628 - 062F +K628: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,[esp] +lahf +seto al +setc [ebp+__xflag] +add esp,byte 4 +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0630 - 0637 +K630: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,[esp] +lahf +seto al +setc [ebp+__xflag] +add esp,byte 4 +call writememorybyte +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0638 +K638: +mov cx,[esi] +add esi,byte 2 +push ecx +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +add cl,[esp] +lahf +seto al +setc [ebp+__xflag] +add esp,byte 4 +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0639 +K639: +mov cx,[esi] +add esi,byte 2 +push ecx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +add cl,[esp] +lahf +seto al +setc [ebp+__xflag] +add esp,byte 4 +call writememorybyte +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0640 - 0647 +K640: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +add [ebp+__dreg+ebx*4],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0650 - 0657 +K650: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,[esp] +lahf +seto al +setc [ebp+__xflag] +add esp,byte 4 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0658 - 065F +K658: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,[esp] +lahf +seto al +setc [ebp+__xflag] +add esp,byte 4 +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0660 - 0667 +K660: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +add cx,[esp] +lahf +seto al +setc [ebp+__xflag] +add esp,byte 4 +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0668 - 066F +K668: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,[esp] +lahf +seto al +setc [ebp+__xflag] +add esp,byte 4 +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0670 - 0677 +K670: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,[esp] +lahf +seto al +setc [ebp+__xflag] +add esp,byte 4 +call writememoryword +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0678 +K678: +mov cx,[esi] +add esi,byte 2 +push ecx +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +add cx,[esp] +lahf +seto al +setc [ebp+__xflag] +add esp,byte 4 +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0679 +K679: +mov cx,[esi] +add esi,byte 2 +push ecx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +add cx,[esp] +lahf +seto al +setc [ebp+__xflag] +add esp,byte 4 +call writememoryword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0680 - 0687 +K680: +and ebx,byte 7 +mov ecx,[esi] +rol ecx,16 +add esi,byte 4 +add [ebp+__dreg+ebx*4],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0690 - 0697 +K690: +and ebx,byte 7 +mov ecx,[esi] +rol ecx,16 +add esi,byte 4 +push ecx +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,[esp] +lahf +seto al +setc [ebp+__xflag] +add esp,byte 4 +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0698 - 069F +K698: +and ebx,byte 7 +mov ecx,[esi] +rol ecx,16 +add esi,byte 4 +push ecx +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,[esp] +lahf +seto al +setc [ebp+__xflag] +add esp,byte 4 +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 06A0 - 06A7 +K6A0: +and ebx,byte 7 +mov ecx,[esi] +rol ecx,16 +add esi,byte 4 +push ecx +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +add ecx,[esp] +lahf +seto al +setc [ebp+__xflag] +add esp,byte 4 +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 06A8 - 06AF +K6A8: +and ebx,byte 7 +mov ecx,[esi] +rol ecx,16 +add esi,byte 4 +push ecx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,[esp] +lahf +seto al +setc [ebp+__xflag] +add esp,byte 4 +call writememorydword +sub edi,byte 32 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 06B0 - 06B7 +K6B0: +and ebx,byte 7 +mov ecx,[esi] +rol ecx,16 +add esi,byte 4 +push ecx +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,[esp] +lahf +seto al +setc [ebp+__xflag] +add esp,byte 4 +call writememorydword +sub edi,byte 34 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 06B8 +K6B8: +mov ecx,[esi] +rol ecx,16 +add esi,byte 4 +push ecx +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +add ecx,[esp] +lahf +seto al +setc [ebp+__xflag] +add esp,byte 4 +call writememorydword +sub edi,byte 32 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 06B9 +K6B9: +mov ecx,[esi] +rol ecx,16 +add esi,byte 4 +push ecx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +add ecx,[esp] +lahf +seto al +setc [ebp+__xflag] +add esp,byte 4 +call writememorydword +sub edi,byte 36 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0700 - 0707 +K700: +mov cl,byte[ebp+__dreg+12] +and ebx,byte 7 +and ecx,byte 31 +mov edx,1 +shl edx,cl +test [ebp+__dreg+ebx*4],edx +jz short ln219 +and ah,0BFh +jmp short ln220 +ln219: +or ah,40h +ln220: +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0708 - 070F +K708: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov bh,cl +add edx,byte 2 +call readmemorybyte +mov bl,cl +mov [ebp+__dreg+12],bx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0710 - 0717 +K710: +mov cl,byte[ebp+__dreg+12] +and ebx,byte 7 +and ecx,byte 7 +push ecx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln221 +and ah,0BFh +jmp short ln222 +ln221: +or ah,40h +ln222: +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0718 - 071F +K718: +mov cl,byte[ebp+__dreg+12] +and ebx,byte 7 +and ecx,byte 7 +push ecx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln223 +and ah,0BFh +jmp short ln224 +ln223: +or ah,40h +ln224: +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0720 - 0727 +K720: +mov cl,byte[ebp+__dreg+12] +and ebx,byte 7 +and ecx,byte 7 +push ecx +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln225 +and ah,0BFh +jmp short ln226 +ln225: +or ah,40h +ln226: +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0728 - 072F +K728: +mov cl,byte[ebp+__dreg+12] +and ebx,byte 7 +and ecx,byte 7 +push ecx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln227 +and ah,0BFh +jmp short ln228 +ln227: +or ah,40h +ln228: +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0730 - 0737 +K730: +mov cl,byte[ebp+__dreg+12] +and ebx,byte 7 +and ecx,byte 7 +push ecx +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln229 +and ah,0BFh +jmp short ln230 +ln229: +or ah,40h +ln230: +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0738 +K738: +mov cl,byte[ebp+__dreg+12] +and ecx,byte 7 +push ecx +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln231 +and ah,0BFh +jmp short ln232 +ln231: +or ah,40h +ln232: +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0739 +K739: +mov cl,byte[ebp+__dreg+12] +and ecx,byte 7 +push ecx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln233 +and ah,0BFh +jmp short ln234 +ln233: +or ah,40h +ln234: +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 073A +K73A: +mov cl,byte[ebp+__dreg+12] +and ecx,byte 7 +push ecx +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln235 +and ah,0BFh +jmp short ln236 +ln235: +or ah,40h +ln236: +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 073B +K73B: +mov cl,byte[ebp+__dreg+12] +and ecx,byte 7 +push ecx +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln237 +and ah,0BFh +jmp short ln238 +ln237: +or ah,40h +ln238: +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 073C +K73C: +mov cl,byte[ebp+__dreg+12] +and ecx,byte 7 +push ecx +mov cx,[esi] +add esi,byte 2 +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln239 +and ah,0BFh +jmp short ln240 +ln239: +or ah,40h +ln240: +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0740 - 0747 +K740: +mov cl,byte[ebp+__dreg+12] +and ebx,byte 7 +and ecx,byte 31 +mov edx,1 +shl edx,cl +mov ecx,[ebp+__dreg+ebx*4] +test ecx,edx +jz short ln241 +and ah,0BFh +jmp short ln242 +ln241: +or ah,40h +ln242: +xor ecx,edx +mov [ebp+__dreg+ebx*4],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0748 - 074F +K748: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov bh,cl +add edx,byte 2 +call readmemorybyte +mov bl,cl +add edx,byte 2 +shl ebx,16 +call readmemorybyte +mov bh,cl +add edx,byte 2 +call readmemorybyte +mov bl,cl +mov [ebp+__dreg+12],ebx +xor ebx,ebx +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0750 - 0757 +K750: +mov cl,byte[ebp+__dreg+12] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln243 +and ah,0BFh +jmp short ln244 +ln243: +or ah,40h +ln244: +xor cl,dl +pop edx +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0758 - 075F +K758: +mov cl,byte[ebp+__dreg+12] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln245 +and ah,0BFh +jmp short ln246 +ln245: +or ah,40h +ln246: +xor cl,dl +pop edx +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0760 - 0767 +K760: +mov cl,byte[ebp+__dreg+12] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln247 +and ah,0BFh +jmp short ln248 +ln247: +or ah,40h +ln248: +xor cl,dl +pop edx +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0768 - 076F +K768: +mov cl,byte[ebp+__dreg+12] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln249 +and ah,0BFh +jmp short ln250 +ln249: +or ah,40h +ln250: +xor cl,dl +pop edx +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0770 - 0777 +K770: +mov cl,byte[ebp+__dreg+12] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln251 +and ah,0BFh +jmp short ln252 +ln251: +or ah,40h +ln252: +xor cl,dl +pop edx +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0778 +K778: +mov cl,byte[ebp+__dreg+12] +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln253 +and ah,0BFh +jmp short ln254 +ln253: +or ah,40h +ln254: +xor cl,dl +pop edx +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0779 +K779: +mov cl,byte[ebp+__dreg+12] +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln255 +and ah,0BFh +jmp short ln256 +ln255: +or ah,40h +ln256: +xor cl,dl +pop edx +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0780 - 0787 +K780: +mov cl,byte[ebp+__dreg+12] +and ebx,byte 7 +and ecx,byte 31 +mov edx,1 +shl edx,cl +mov ecx,[ebp+__dreg+ebx*4] +test ecx,edx +jz short ln257 +and ah,0BFh +jmp short ln258 +ln257: +or ah,40h +ln258: +not edx +and ecx,edx +mov [ebp+__dreg+ebx*4],ecx +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0788 - 078F +K788: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +mov ebx,[ebp+__dreg+12] +mov cl,bh +call writememorybyte +add edx,byte 2 +mov cl,bl +call writememorybyte +xor ebx,ebx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0790 - 0797 +K790: +mov cl,byte[ebp+__dreg+12] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln259 +and ah,0BFh +jmp short ln260 +ln259: +or ah,40h +ln260: +not dl +and cl,dl +pop edx +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0798 - 079F +K798: +mov cl,byte[ebp+__dreg+12] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln261 +and ah,0BFh +jmp short ln262 +ln261: +or ah,40h +ln262: +not dl +and cl,dl +pop edx +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 07A0 - 07A7 +K7A0: +mov cl,byte[ebp+__dreg+12] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln263 +and ah,0BFh +jmp short ln264 +ln263: +or ah,40h +ln264: +not dl +and cl,dl +pop edx +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 07A8 - 07AF +K7A8: +mov cl,byte[ebp+__dreg+12] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln265 +and ah,0BFh +jmp short ln266 +ln265: +or ah,40h +ln266: +not dl +and cl,dl +pop edx +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 07B0 - 07B7 +K7B0: +mov cl,byte[ebp+__dreg+12] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln267 +and ah,0BFh +jmp short ln268 +ln267: +or ah,40h +ln268: +not dl +and cl,dl +pop edx +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 07B8 +K7B8: +mov cl,byte[ebp+__dreg+12] +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln269 +and ah,0BFh +jmp short ln270 +ln269: +or ah,40h +ln270: +not dl +and cl,dl +pop edx +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 07B9 +K7B9: +mov cl,byte[ebp+__dreg+12] +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln271 +and ah,0BFh +jmp short ln272 +ln271: +or ah,40h +ln272: +not dl +and cl,dl +pop edx +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 07C0 - 07C7 +K7C0: +mov cl,byte[ebp+__dreg+12] +and ebx,byte 7 +and ecx,byte 31 +mov edx,1 +shl edx,cl +mov ecx,[ebp+__dreg+ebx*4] +test ecx,edx +jz short ln273 +and ah,0BFh +jmp short ln274 +ln273: +or ah,40h +ln274: +or ecx,edx +mov [ebp+__dreg+ebx*4],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 07C8 - 07CF +K7C8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +mov ebx,[ebp+__dreg+12] +rol ebx,16 +mov cl,bh +call writememorybyte +add edx,byte 2 +mov cl,bl +call writememorybyte +add edx,byte 2 +rol ebx,16 +mov cl,bh +call writememorybyte +add edx,byte 2 +mov cl,bl +call writememorybyte +xor ebx,ebx +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 07D0 - 07D7 +K7D0: +mov cl,byte[ebp+__dreg+12] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln275 +and ah,0BFh +jmp short ln276 +ln275: +or ah,40h +ln276: +or cl,dl +pop edx +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 07D8 - 07DF +K7D8: +mov cl,byte[ebp+__dreg+12] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln277 +and ah,0BFh +jmp short ln278 +ln277: +or ah,40h +ln278: +or cl,dl +pop edx +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 07E0 - 07E7 +K7E0: +mov cl,byte[ebp+__dreg+12] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln279 +and ah,0BFh +jmp short ln280 +ln279: +or ah,40h +ln280: +or cl,dl +pop edx +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 07E8 - 07EF +K7E8: +mov cl,byte[ebp+__dreg+12] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln281 +and ah,0BFh +jmp short ln282 +ln281: +or ah,40h +ln282: +or cl,dl +pop edx +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 07F0 - 07F7 +K7F0: +mov cl,byte[ebp+__dreg+12] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln283 +and ah,0BFh +jmp short ln284 +ln283: +or ah,40h +ln284: +or cl,dl +pop edx +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 07F8 +K7F8: +mov cl,byte[ebp+__dreg+12] +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln285 +and ah,0BFh +jmp short ln286 +ln285: +or ah,40h +ln286: +or cl,dl +pop edx +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 07F9 +K7F9: +mov cl,byte[ebp+__dreg+12] +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln287 +and ah,0BFh +jmp short ln288 +ln287: +or ah,40h +ln288: +or cl,dl +pop edx +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0800 - 0807 +K800: +mov cl,[esi] +add esi,byte 2 +and ebx,byte 7 +and ecx,byte 31 +mov edx,1 +shl edx,cl +test [ebp+__dreg+ebx*4],edx +jz short ln289 +and ah,0BFh +jmp short ln290 +ln289: +or ah,40h +ln290: +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0810 - 0817 +K810: +mov cl,[esi] +add esi,byte 2 +and ebx,byte 7 +and ecx,byte 7 +push ecx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln291 +and ah,0BFh +jmp short ln292 +ln291: +or ah,40h +ln292: +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0818 - 081F +K818: +mov cl,[esi] +add esi,byte 2 +and ebx,byte 7 +and ecx,byte 7 +push ecx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln293 +and ah,0BFh +jmp short ln294 +ln293: +or ah,40h +ln294: +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0820 - 0827 +K820: +mov cl,[esi] +add esi,byte 2 +and ebx,byte 7 +and ecx,byte 7 +push ecx +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln295 +and ah,0BFh +jmp short ln296 +ln295: +or ah,40h +ln296: +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0828 - 082F +K828: +mov cl,[esi] +add esi,byte 2 +and ebx,byte 7 +and ecx,byte 7 +push ecx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln297 +and ah,0BFh +jmp short ln298 +ln297: +or ah,40h +ln298: +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0830 - 0837 +K830: +mov cl,[esi] +add esi,byte 2 +and ebx,byte 7 +and ecx,byte 7 +push ecx +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln299 +and ah,0BFh +jmp short ln300 +ln299: +or ah,40h +ln300: +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0838 +K838: +mov cl,[esi] +add esi,byte 2 +and ecx,byte 7 +push ecx +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln301 +and ah,0BFh +jmp short ln302 +ln301: +or ah,40h +ln302: +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0839 +K839: +mov cl,[esi] +add esi,byte 2 +and ecx,byte 7 +push ecx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln303 +and ah,0BFh +jmp short ln304 +ln303: +or ah,40h +ln304: +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 083A +K83A: +mov cl,[esi] +add esi,byte 2 +and ecx,byte 7 +push ecx +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln305 +and ah,0BFh +jmp short ln306 +ln305: +or ah,40h +ln306: +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 083B +K83B: +mov cl,[esi] +add esi,byte 2 +and ecx,byte 7 +push ecx +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln307 +and ah,0BFh +jmp short ln308 +ln307: +or ah,40h +ln308: +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 083C +K83C: +mov cl,[esi] +add esi,byte 2 +and ecx,byte 7 +push ecx +mov cx,[esi] +add esi,byte 2 +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln309 +and ah,0BFh +jmp short ln310 +ln309: +or ah,40h +ln310: +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0840 - 0847 +K840: +mov cl,[esi] +add esi,byte 2 +and ebx,byte 7 +and ecx,byte 31 +mov edx,1 +shl edx,cl +mov ecx,[ebp+__dreg+ebx*4] +test ecx,edx +jz short ln311 +and ah,0BFh +jmp short ln312 +ln311: +or ah,40h +ln312: +xor ecx,edx +mov [ebp+__dreg+ebx*4],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0850 - 0857 +K850: +mov cl,[esi] +add esi,byte 2 +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln313 +and ah,0BFh +jmp short ln314 +ln313: +or ah,40h +ln314: +xor cl,dl +pop edx +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0858 - 085F +K858: +mov cl,[esi] +add esi,byte 2 +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln315 +and ah,0BFh +jmp short ln316 +ln315: +or ah,40h +ln316: +xor cl,dl +pop edx +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0860 - 0867 +K860: +mov cl,[esi] +add esi,byte 2 +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln317 +and ah,0BFh +jmp short ln318 +ln317: +or ah,40h +ln318: +xor cl,dl +pop edx +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0868 - 086F +K868: +mov cl,[esi] +add esi,byte 2 +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln319 +and ah,0BFh +jmp short ln320 +ln319: +or ah,40h +ln320: +xor cl,dl +pop edx +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0870 - 0877 +K870: +mov cl,[esi] +add esi,byte 2 +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln321 +and ah,0BFh +jmp short ln322 +ln321: +or ah,40h +ln322: +xor cl,dl +pop edx +call writememorybyte +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0878 +K878: +mov cl,[esi] +add esi,byte 2 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln323 +and ah,0BFh +jmp short ln324 +ln323: +or ah,40h +ln324: +xor cl,dl +pop edx +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0879 +K879: +mov cl,[esi] +add esi,byte 2 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln325 +and ah,0BFh +jmp short ln326 +ln325: +or ah,40h +ln326: +xor cl,dl +pop edx +call writememorybyte +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0880 - 0887 +K880: +mov cl,[esi] +add esi,byte 2 +and ebx,byte 7 +and ecx,byte 31 +mov edx,1 +shl edx,cl +mov ecx,[ebp+__dreg+ebx*4] +test ecx,edx +jz short ln327 +and ah,0BFh +jmp short ln328 +ln327: +or ah,40h +ln328: +not edx +and ecx,edx +mov [ebp+__dreg+ebx*4],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0890 - 0897 +K890: +mov cl,[esi] +add esi,byte 2 +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln329 +and ah,0BFh +jmp short ln330 +ln329: +or ah,40h +ln330: +not dl +and cl,dl +pop edx +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0898 - 089F +K898: +mov cl,[esi] +add esi,byte 2 +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln331 +and ah,0BFh +jmp short ln332 +ln331: +or ah,40h +ln332: +not dl +and cl,dl +pop edx +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 08A0 - 08A7 +K8A0: +mov cl,[esi] +add esi,byte 2 +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln333 +and ah,0BFh +jmp short ln334 +ln333: +or ah,40h +ln334: +not dl +and cl,dl +pop edx +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 08A8 - 08AF +K8A8: +mov cl,[esi] +add esi,byte 2 +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln335 +and ah,0BFh +jmp short ln336 +ln335: +or ah,40h +ln336: +not dl +and cl,dl +pop edx +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 08B0 - 08B7 +K8B0: +mov cl,[esi] +add esi,byte 2 +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln337 +and ah,0BFh +jmp short ln338 +ln337: +or ah,40h +ln338: +not dl +and cl,dl +pop edx +call writememorybyte +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 08B8 +K8B8: +mov cl,[esi] +add esi,byte 2 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln339 +and ah,0BFh +jmp short ln340 +ln339: +or ah,40h +ln340: +not dl +and cl,dl +pop edx +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 08B9 +K8B9: +mov cl,[esi] +add esi,byte 2 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln341 +and ah,0BFh +jmp short ln342 +ln341: +or ah,40h +ln342: +not dl +and cl,dl +pop edx +call writememorybyte +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 08C0 - 08C7 +K8C0: +mov cl,[esi] +add esi,byte 2 +and ebx,byte 7 +and ecx,byte 31 +mov edx,1 +shl edx,cl +mov ecx,[ebp+__dreg+ebx*4] +test ecx,edx +jz short ln343 +and ah,0BFh +jmp short ln344 +ln343: +or ah,40h +ln344: +or ecx,edx +mov [ebp+__dreg+ebx*4],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 08D0 - 08D7 +K8D0: +mov cl,[esi] +add esi,byte 2 +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln345 +and ah,0BFh +jmp short ln346 +ln345: +or ah,40h +ln346: +or cl,dl +pop edx +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 08D8 - 08DF +K8D8: +mov cl,[esi] +add esi,byte 2 +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln347 +and ah,0BFh +jmp short ln348 +ln347: +or ah,40h +ln348: +or cl,dl +pop edx +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 08E0 - 08E7 +K8E0: +mov cl,[esi] +add esi,byte 2 +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln349 +and ah,0BFh +jmp short ln350 +ln349: +or ah,40h +ln350: +or cl,dl +pop edx +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 08E8 - 08EF +K8E8: +mov cl,[esi] +add esi,byte 2 +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln351 +and ah,0BFh +jmp short ln352 +ln351: +or ah,40h +ln352: +or cl,dl +pop edx +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 08F0 - 08F7 +K8F0: +mov cl,[esi] +add esi,byte 2 +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln353 +and ah,0BFh +jmp short ln354 +ln353: +or ah,40h +ln354: +or cl,dl +pop edx +call writememorybyte +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 08F8 +K8F8: +mov cl,[esi] +add esi,byte 2 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln355 +and ah,0BFh +jmp short ln356 +ln355: +or ah,40h +ln356: +or cl,dl +pop edx +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 08F9 +K8F9: +mov cl,[esi] +add esi,byte 2 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln357 +and ah,0BFh +jmp short ln358 +ln357: +or ah,40h +ln358: +or cl,dl +pop edx +call writememorybyte +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0900 - 0907 +K900: +mov cl,byte[ebp+__dreg+16] +and ebx,byte 7 +and ecx,byte 31 +mov edx,1 +shl edx,cl +test [ebp+__dreg+ebx*4],edx +jz short ln359 +and ah,0BFh +jmp short ln360 +ln359: +or ah,40h +ln360: +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0908 - 090F +K908: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov bh,cl +add edx,byte 2 +call readmemorybyte +mov bl,cl +mov [ebp+__dreg+16],bx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0910 - 0917 +K910: +mov cl,byte[ebp+__dreg+16] +and ebx,byte 7 +and ecx,byte 7 +push ecx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln361 +and ah,0BFh +jmp short ln362 +ln361: +or ah,40h +ln362: +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0918 - 091F +K918: +mov cl,byte[ebp+__dreg+16] +and ebx,byte 7 +and ecx,byte 7 +push ecx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln363 +and ah,0BFh +jmp short ln364 +ln363: +or ah,40h +ln364: +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0920 - 0927 +K920: +mov cl,byte[ebp+__dreg+16] +and ebx,byte 7 +and ecx,byte 7 +push ecx +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln365 +and ah,0BFh +jmp short ln366 +ln365: +or ah,40h +ln366: +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0928 - 092F +K928: +mov cl,byte[ebp+__dreg+16] +and ebx,byte 7 +and ecx,byte 7 +push ecx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln367 +and ah,0BFh +jmp short ln368 +ln367: +or ah,40h +ln368: +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0930 - 0937 +K930: +mov cl,byte[ebp+__dreg+16] +and ebx,byte 7 +and ecx,byte 7 +push ecx +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln369 +and ah,0BFh +jmp short ln370 +ln369: +or ah,40h +ln370: +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0938 +K938: +mov cl,byte[ebp+__dreg+16] +and ecx,byte 7 +push ecx +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln371 +and ah,0BFh +jmp short ln372 +ln371: +or ah,40h +ln372: +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0939 +K939: +mov cl,byte[ebp+__dreg+16] +and ecx,byte 7 +push ecx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln373 +and ah,0BFh +jmp short ln374 +ln373: +or ah,40h +ln374: +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 093A +K93A: +mov cl,byte[ebp+__dreg+16] +and ecx,byte 7 +push ecx +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln375 +and ah,0BFh +jmp short ln376 +ln375: +or ah,40h +ln376: +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 093B +K93B: +mov cl,byte[ebp+__dreg+16] +and ecx,byte 7 +push ecx +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln377 +and ah,0BFh +jmp short ln378 +ln377: +or ah,40h +ln378: +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 093C +K93C: +mov cl,byte[ebp+__dreg+16] +and ecx,byte 7 +push ecx +mov cx,[esi] +add esi,byte 2 +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln379 +and ah,0BFh +jmp short ln380 +ln379: +or ah,40h +ln380: +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0940 - 0947 +K940: +mov cl,byte[ebp+__dreg+16] +and ebx,byte 7 +and ecx,byte 31 +mov edx,1 +shl edx,cl +mov ecx,[ebp+__dreg+ebx*4] +test ecx,edx +jz short ln381 +and ah,0BFh +jmp short ln382 +ln381: +or ah,40h +ln382: +xor ecx,edx +mov [ebp+__dreg+ebx*4],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0948 - 094F +K948: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov bh,cl +add edx,byte 2 +call readmemorybyte +mov bl,cl +add edx,byte 2 +shl ebx,16 +call readmemorybyte +mov bh,cl +add edx,byte 2 +call readmemorybyte +mov bl,cl +mov [ebp+__dreg+16],ebx +xor ebx,ebx +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0950 - 0957 +K950: +mov cl,byte[ebp+__dreg+16] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln383 +and ah,0BFh +jmp short ln384 +ln383: +or ah,40h +ln384: +xor cl,dl +pop edx +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0958 - 095F +K958: +mov cl,byte[ebp+__dreg+16] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln385 +and ah,0BFh +jmp short ln386 +ln385: +or ah,40h +ln386: +xor cl,dl +pop edx +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0960 - 0967 +K960: +mov cl,byte[ebp+__dreg+16] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln387 +and ah,0BFh +jmp short ln388 +ln387: +or ah,40h +ln388: +xor cl,dl +pop edx +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0968 - 096F +K968: +mov cl,byte[ebp+__dreg+16] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln389 +and ah,0BFh +jmp short ln390 +ln389: +or ah,40h +ln390: +xor cl,dl +pop edx +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0970 - 0977 +K970: +mov cl,byte[ebp+__dreg+16] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln391 +and ah,0BFh +jmp short ln392 +ln391: +or ah,40h +ln392: +xor cl,dl +pop edx +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0978 +K978: +mov cl,byte[ebp+__dreg+16] +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln393 +and ah,0BFh +jmp short ln394 +ln393: +or ah,40h +ln394: +xor cl,dl +pop edx +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0979 +K979: +mov cl,byte[ebp+__dreg+16] +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln395 +and ah,0BFh +jmp short ln396 +ln395: +or ah,40h +ln396: +xor cl,dl +pop edx +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0980 - 0987 +K980: +mov cl,byte[ebp+__dreg+16] +and ebx,byte 7 +and ecx,byte 31 +mov edx,1 +shl edx,cl +mov ecx,[ebp+__dreg+ebx*4] +test ecx,edx +jz short ln397 +and ah,0BFh +jmp short ln398 +ln397: +or ah,40h +ln398: +not edx +and ecx,edx +mov [ebp+__dreg+ebx*4],ecx +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0988 - 098F +K988: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +mov ebx,[ebp+__dreg+16] +mov cl,bh +call writememorybyte +add edx,byte 2 +mov cl,bl +call writememorybyte +xor ebx,ebx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0990 - 0997 +K990: +mov cl,byte[ebp+__dreg+16] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln399 +and ah,0BFh +jmp short ln400 +ln399: +or ah,40h +ln400: +not dl +and cl,dl +pop edx +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0998 - 099F +K998: +mov cl,byte[ebp+__dreg+16] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln401 +and ah,0BFh +jmp short ln402 +ln401: +or ah,40h +ln402: +not dl +and cl,dl +pop edx +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 09A0 - 09A7 +K9A0: +mov cl,byte[ebp+__dreg+16] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln403 +and ah,0BFh +jmp short ln404 +ln403: +or ah,40h +ln404: +not dl +and cl,dl +pop edx +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 09A8 - 09AF +K9A8: +mov cl,byte[ebp+__dreg+16] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln405 +and ah,0BFh +jmp short ln406 +ln405: +or ah,40h +ln406: +not dl +and cl,dl +pop edx +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 09B0 - 09B7 +K9B0: +mov cl,byte[ebp+__dreg+16] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln407 +and ah,0BFh +jmp short ln408 +ln407: +or ah,40h +ln408: +not dl +and cl,dl +pop edx +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 09B8 +K9B8: +mov cl,byte[ebp+__dreg+16] +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln409 +and ah,0BFh +jmp short ln410 +ln409: +or ah,40h +ln410: +not dl +and cl,dl +pop edx +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 09B9 +K9B9: +mov cl,byte[ebp+__dreg+16] +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln411 +and ah,0BFh +jmp short ln412 +ln411: +or ah,40h +ln412: +not dl +and cl,dl +pop edx +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 09C0 - 09C7 +K9C0: +mov cl,byte[ebp+__dreg+16] +and ebx,byte 7 +and ecx,byte 31 +mov edx,1 +shl edx,cl +mov ecx,[ebp+__dreg+ebx*4] +test ecx,edx +jz short ln413 +and ah,0BFh +jmp short ln414 +ln413: +or ah,40h +ln414: +or ecx,edx +mov [ebp+__dreg+ebx*4],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 09C8 - 09CF +K9C8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +mov ebx,[ebp+__dreg+16] +rol ebx,16 +mov cl,bh +call writememorybyte +add edx,byte 2 +mov cl,bl +call writememorybyte +add edx,byte 2 +rol ebx,16 +mov cl,bh +call writememorybyte +add edx,byte 2 +mov cl,bl +call writememorybyte +xor ebx,ebx +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 09D0 - 09D7 +K9D0: +mov cl,byte[ebp+__dreg+16] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln415 +and ah,0BFh +jmp short ln416 +ln415: +or ah,40h +ln416: +or cl,dl +pop edx +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 09D8 - 09DF +K9D8: +mov cl,byte[ebp+__dreg+16] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln417 +and ah,0BFh +jmp short ln418 +ln417: +or ah,40h +ln418: +or cl,dl +pop edx +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 09E0 - 09E7 +K9E0: +mov cl,byte[ebp+__dreg+16] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln419 +and ah,0BFh +jmp short ln420 +ln419: +or ah,40h +ln420: +or cl,dl +pop edx +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 09E8 - 09EF +K9E8: +mov cl,byte[ebp+__dreg+16] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln421 +and ah,0BFh +jmp short ln422 +ln421: +or ah,40h +ln422: +or cl,dl +pop edx +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 09F0 - 09F7 +K9F0: +mov cl,byte[ebp+__dreg+16] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln423 +and ah,0BFh +jmp short ln424 +ln423: +or ah,40h +ln424: +or cl,dl +pop edx +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 09F8 +K9F8: +mov cl,byte[ebp+__dreg+16] +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln425 +and ah,0BFh +jmp short ln426 +ln425: +or ah,40h +ln426: +or cl,dl +pop edx +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 09F9 +K9F9: +mov cl,byte[ebp+__dreg+16] +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln427 +and ah,0BFh +jmp short ln428 +ln427: +or ah,40h +ln428: +or cl,dl +pop edx +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0A00 - 0A07 +KA00: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +xor [ebp+__dreg+ebx*4],cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0A10 - 0A17 +KA10: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xor cl,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0A18 - 0A1F +KA18: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xor cl,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0A20 - 0A27 +KA20: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +xor cl,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0A28 - 0A2F +KA28: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xor cl,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0A30 - 0A37 +KA30: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xor cl,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememorybyte +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0A38 +KA38: +mov cx,[esi] +add esi,byte 2 +push ecx +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +xor cl,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0A39 +KA39: +mov cx,[esi] +add esi,byte 2 +push ecx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +xor cl,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememorybyte +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0A3C +KA3C: +mov ch,[ebp+__xflag] +mov cl,ah +shr cx,6 +add cl,cl +or cl,al +mov ch,ah +shl ch,8 +adc cl,cl +xor cl,[esi] +add esi,byte 2 +mov al,cl +mov ah,al +and ax,0C10h +shl ah,3 +shr al,4 +mov [ebp+__xflag],al +mov al,cl +and al,3 +shr al,1 +adc ah,ah +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0A40 - 0A47 +KA40: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +xor [ebp+__dreg+ebx*4],cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0A50 - 0A57 +KA50: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +xor cx,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0A58 - 0A5F +KA58: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +xor cx,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0A60 - 0A67 +KA60: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +xor cx,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0A68 - 0A6F +KA68: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +xor cx,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0A70 - 0A77 +KA70: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +xor cx,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememoryword +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0A78 +KA78: +mov cx,[esi] +add esi,byte 2 +push ecx +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +xor cx,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0A79 +KA79: +mov cx,[esi] +add esi,byte 2 +push ecx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +xor cx,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememoryword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0A7C +KA7C: +test byte[ebp+__sr+1],20h +jz near privilege_violation +mov ch,[ebp+__xflag] +mov cl,ah +shr cx,6 +add cl,cl +or cl,al +mov ch,ah +shl ch,8 +adc cl,cl +mov ch,[ebp+__sr+1] +xor cx,[esi] +add esi,byte 2 +push ecx +mov cl,[ebp+__sr+1] +and cx,2020h +xor ch,cl +jz near ln429 +mov ecx,[ebp+__a7] +xchg ecx,[ebp+__asp] +mov [ebp+__a7],ecx +test byte[esp+1],20h +jz short ln430 +mov ecx,[ebp+__s_fetch] +mov [ebp+__fetch],ecx +mov ecx,[ebp+__s_readbyte] +mov [ebp+__readbyte],ecx +mov ecx,[ebp+__s_readword] +mov [ebp+__readword],ecx +mov ecx,[ebp+__s_writebyte] +mov [ebp+__writebyte],ecx +mov ecx,[ebp+__s_writeword] +mov [ebp+__writeword],ecx +jmp short ln429 +ln430: +mov ecx,[ebp+__u_fetch] +mov [ebp+__fetch],ecx +mov ecx,[ebp+__u_readbyte] +mov [ebp+__readbyte],ecx +mov ecx,[ebp+__u_readword] +mov [ebp+__readword],ecx +mov ecx,[ebp+__u_writebyte] +mov [ebp+__writebyte],ecx +mov ecx,[ebp+__u_writeword] +mov [ebp+__writeword],ecx +ln429: +pop ecx +mov [ebp+__sr+1],ch +and byte[ebp+__sr+1],0A7h +mov al,cl +mov ah,al +and ax,0C10h +shl ah,3 +shr al,4 +mov [ebp+__xflag],al +mov al,cl +and al,3 +shr al,1 +adc ah,ah +sub edi,byte 20 +jmp exec_checkpoint +; Opcodes 0A80 - 0A87 +KA80: +and ebx,byte 7 +mov ecx,[esi] +rol ecx,16 +add esi,byte 4 +xor [ebp+__dreg+ebx*4],ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0A90 - 0A97 +KA90: +and ebx,byte 7 +mov ecx,[esi] +rol ecx,16 +add esi,byte 4 +push ecx +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +xor ecx,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0A98 - 0A9F +KA98: +and ebx,byte 7 +mov ecx,[esi] +rol ecx,16 +add esi,byte 4 +push ecx +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +xor ecx,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0AA0 - 0AA7 +KAA0: +and ebx,byte 7 +mov ecx,[esi] +rol ecx,16 +add esi,byte 4 +push ecx +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +xor ecx,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0AA8 - 0AAF +KAA8: +and ebx,byte 7 +mov ecx,[esi] +rol ecx,16 +add esi,byte 4 +push ecx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +xor ecx,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememorydword +sub edi,byte 32 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0AB0 - 0AB7 +KAB0: +and ebx,byte 7 +mov ecx,[esi] +rol ecx,16 +add esi,byte 4 +push ecx +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +xor ecx,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememorydword +sub edi,byte 34 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0AB8 +KAB8: +mov ecx,[esi] +rol ecx,16 +add esi,byte 4 +push ecx +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +xor ecx,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememorydword +sub edi,byte 32 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0AB9 +KAB9: +mov ecx,[esi] +rol ecx,16 +add esi,byte 4 +push ecx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +xor ecx,[esp] +lahf +mov al,0 +add esp,byte 4 +call writememorydword +sub edi,byte 36 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0B00 - 0B07 +KB00: +mov cl,byte[ebp+__dreg+20] +and ebx,byte 7 +and ecx,byte 31 +mov edx,1 +shl edx,cl +test [ebp+__dreg+ebx*4],edx +jz short ln431 +and ah,0BFh +jmp short ln432 +ln431: +or ah,40h +ln432: +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0B08 - 0B0F +KB08: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov bh,cl +add edx,byte 2 +call readmemorybyte +mov bl,cl +mov [ebp+__dreg+20],bx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0B10 - 0B17 +KB10: +mov cl,byte[ebp+__dreg+20] +and ebx,byte 7 +and ecx,byte 7 +push ecx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln433 +and ah,0BFh +jmp short ln434 +ln433: +or ah,40h +ln434: +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0B18 - 0B1F +KB18: +mov cl,byte[ebp+__dreg+20] +and ebx,byte 7 +and ecx,byte 7 +push ecx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln435 +and ah,0BFh +jmp short ln436 +ln435: +or ah,40h +ln436: +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0B20 - 0B27 +KB20: +mov cl,byte[ebp+__dreg+20] +and ebx,byte 7 +and ecx,byte 7 +push ecx +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln437 +and ah,0BFh +jmp short ln438 +ln437: +or ah,40h +ln438: +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0B28 - 0B2F +KB28: +mov cl,byte[ebp+__dreg+20] +and ebx,byte 7 +and ecx,byte 7 +push ecx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln439 +and ah,0BFh +jmp short ln440 +ln439: +or ah,40h +ln440: +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0B30 - 0B37 +KB30: +mov cl,byte[ebp+__dreg+20] +and ebx,byte 7 +and ecx,byte 7 +push ecx +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln441 +and ah,0BFh +jmp short ln442 +ln441: +or ah,40h +ln442: +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0B38 +KB38: +mov cl,byte[ebp+__dreg+20] +and ecx,byte 7 +push ecx +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln443 +and ah,0BFh +jmp short ln444 +ln443: +or ah,40h +ln444: +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0B39 +KB39: +mov cl,byte[ebp+__dreg+20] +and ecx,byte 7 +push ecx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln445 +and ah,0BFh +jmp short ln446 +ln445: +or ah,40h +ln446: +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0B3A +KB3A: +mov cl,byte[ebp+__dreg+20] +and ecx,byte 7 +push ecx +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln447 +and ah,0BFh +jmp short ln448 +ln447: +or ah,40h +ln448: +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0B3B +KB3B: +mov cl,byte[ebp+__dreg+20] +and ecx,byte 7 +push ecx +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln449 +and ah,0BFh +jmp short ln450 +ln449: +or ah,40h +ln450: +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0B3C +KB3C: +mov cl,byte[ebp+__dreg+20] +and ecx,byte 7 +push ecx +mov cx,[esi] +add esi,byte 2 +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln451 +and ah,0BFh +jmp short ln452 +ln451: +or ah,40h +ln452: +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0B40 - 0B47 +KB40: +mov cl,byte[ebp+__dreg+20] +and ebx,byte 7 +and ecx,byte 31 +mov edx,1 +shl edx,cl +mov ecx,[ebp+__dreg+ebx*4] +test ecx,edx +jz short ln453 +and ah,0BFh +jmp short ln454 +ln453: +or ah,40h +ln454: +xor ecx,edx +mov [ebp+__dreg+ebx*4],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0B48 - 0B4F +KB48: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov bh,cl +add edx,byte 2 +call readmemorybyte +mov bl,cl +add edx,byte 2 +shl ebx,16 +call readmemorybyte +mov bh,cl +add edx,byte 2 +call readmemorybyte +mov bl,cl +mov [ebp+__dreg+20],ebx +xor ebx,ebx +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0B50 - 0B57 +KB50: +mov cl,byte[ebp+__dreg+20] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln455 +and ah,0BFh +jmp short ln456 +ln455: +or ah,40h +ln456: +xor cl,dl +pop edx +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0B58 - 0B5F +KB58: +mov cl,byte[ebp+__dreg+20] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln457 +and ah,0BFh +jmp short ln458 +ln457: +or ah,40h +ln458: +xor cl,dl +pop edx +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0B60 - 0B67 +KB60: +mov cl,byte[ebp+__dreg+20] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln459 +and ah,0BFh +jmp short ln460 +ln459: +or ah,40h +ln460: +xor cl,dl +pop edx +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0B68 - 0B6F +KB68: +mov cl,byte[ebp+__dreg+20] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln461 +and ah,0BFh +jmp short ln462 +ln461: +or ah,40h +ln462: +xor cl,dl +pop edx +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0B70 - 0B77 +KB70: +mov cl,byte[ebp+__dreg+20] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln463 +and ah,0BFh +jmp short ln464 +ln463: +or ah,40h +ln464: +xor cl,dl +pop edx +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0B78 +KB78: +mov cl,byte[ebp+__dreg+20] +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln465 +and ah,0BFh +jmp short ln466 +ln465: +or ah,40h +ln466: +xor cl,dl +pop edx +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0B79 +KB79: +mov cl,byte[ebp+__dreg+20] +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln467 +and ah,0BFh +jmp short ln468 +ln467: +or ah,40h +ln468: +xor cl,dl +pop edx +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0B80 - 0B87 +KB80: +mov cl,byte[ebp+__dreg+20] +and ebx,byte 7 +and ecx,byte 31 +mov edx,1 +shl edx,cl +mov ecx,[ebp+__dreg+ebx*4] +test ecx,edx +jz short ln469 +and ah,0BFh +jmp short ln470 +ln469: +or ah,40h +ln470: +not edx +and ecx,edx +mov [ebp+__dreg+ebx*4],ecx +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0B88 - 0B8F +KB88: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +mov ebx,[ebp+__dreg+20] +mov cl,bh +call writememorybyte +add edx,byte 2 +mov cl,bl +call writememorybyte +xor ebx,ebx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0B90 - 0B97 +KB90: +mov cl,byte[ebp+__dreg+20] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln471 +and ah,0BFh +jmp short ln472 +ln471: +or ah,40h +ln472: +not dl +and cl,dl +pop edx +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0B98 - 0B9F +KB98: +mov cl,byte[ebp+__dreg+20] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln473 +and ah,0BFh +jmp short ln474 +ln473: +or ah,40h +ln474: +not dl +and cl,dl +pop edx +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0BA0 - 0BA7 +KBA0: +mov cl,byte[ebp+__dreg+20] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln475 +and ah,0BFh +jmp short ln476 +ln475: +or ah,40h +ln476: +not dl +and cl,dl +pop edx +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0BA8 - 0BAF +KBA8: +mov cl,byte[ebp+__dreg+20] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln477 +and ah,0BFh +jmp short ln478 +ln477: +or ah,40h +ln478: +not dl +and cl,dl +pop edx +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0BB0 - 0BB7 +KBB0: +mov cl,byte[ebp+__dreg+20] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln479 +and ah,0BFh +jmp short ln480 +ln479: +or ah,40h +ln480: +not dl +and cl,dl +pop edx +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0BB8 +KBB8: +mov cl,byte[ebp+__dreg+20] +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln481 +and ah,0BFh +jmp short ln482 +ln481: +or ah,40h +ln482: +not dl +and cl,dl +pop edx +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0BB9 +KBB9: +mov cl,byte[ebp+__dreg+20] +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln483 +and ah,0BFh +jmp short ln484 +ln483: +or ah,40h +ln484: +not dl +and cl,dl +pop edx +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0BC0 - 0BC7 +KBC0: +mov cl,byte[ebp+__dreg+20] +and ebx,byte 7 +and ecx,byte 31 +mov edx,1 +shl edx,cl +mov ecx,[ebp+__dreg+ebx*4] +test ecx,edx +jz short ln485 +and ah,0BFh +jmp short ln486 +ln485: +or ah,40h +ln486: +or ecx,edx +mov [ebp+__dreg+ebx*4],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0BC8 - 0BCF +KBC8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +mov ebx,[ebp+__dreg+20] +rol ebx,16 +mov cl,bh +call writememorybyte +add edx,byte 2 +mov cl,bl +call writememorybyte +add edx,byte 2 +rol ebx,16 +mov cl,bh +call writememorybyte +add edx,byte 2 +mov cl,bl +call writememorybyte +xor ebx,ebx +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0BD0 - 0BD7 +KBD0: +mov cl,byte[ebp+__dreg+20] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln487 +and ah,0BFh +jmp short ln488 +ln487: +or ah,40h +ln488: +or cl,dl +pop edx +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0BD8 - 0BDF +KBD8: +mov cl,byte[ebp+__dreg+20] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln489 +and ah,0BFh +jmp short ln490 +ln489: +or ah,40h +ln490: +or cl,dl +pop edx +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0BE0 - 0BE7 +KBE0: +mov cl,byte[ebp+__dreg+20] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln491 +and ah,0BFh +jmp short ln492 +ln491: +or ah,40h +ln492: +or cl,dl +pop edx +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0BE8 - 0BEF +KBE8: +mov cl,byte[ebp+__dreg+20] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln493 +and ah,0BFh +jmp short ln494 +ln493: +or ah,40h +ln494: +or cl,dl +pop edx +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0BF0 - 0BF7 +KBF0: +mov cl,byte[ebp+__dreg+20] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln495 +and ah,0BFh +jmp short ln496 +ln495: +or ah,40h +ln496: +or cl,dl +pop edx +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0BF8 +KBF8: +mov cl,byte[ebp+__dreg+20] +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln497 +and ah,0BFh +jmp short ln498 +ln497: +or ah,40h +ln498: +or cl,dl +pop edx +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0BF9 +KBF9: +mov cl,byte[ebp+__dreg+20] +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln499 +and ah,0BFh +jmp short ln500 +ln499: +or ah,40h +ln500: +or cl,dl +pop edx +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0C00 - 0C07 +KC00: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +cmp [ebp+__dreg+ebx*4],cl +lahf +seto al +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0C10 - 0C17 +KC10: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp cl,[esp] +lahf +seto al +add esp,byte 4 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0C18 - 0C1F +KC18: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +cmp cl,[esp] +lahf +seto al +add esp,byte 4 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0C20 - 0C27 +KC20: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +cmp cl,[esp] +lahf +seto al +add esp,byte 4 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0C28 - 0C2F +KC28: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp cl,[esp] +lahf +seto al +add esp,byte 4 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0C30 - 0C37 +KC30: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp cl,[esp] +lahf +seto al +add esp,byte 4 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0C38 +KC38: +mov cx,[esi] +add esi,byte 2 +push ecx +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +cmp cl,[esp] +lahf +seto al +add esp,byte 4 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0C39 +KC39: +mov cx,[esi] +add esi,byte 2 +push ecx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +cmp cl,[esp] +lahf +seto al +add esp,byte 4 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0C40 - 0C47 +KC40: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +cmp [ebp+__dreg+ebx*4],cx +lahf +seto al +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0C50 - 0C57 +KC50: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +cmp cx,[esp] +lahf +seto al +add esp,byte 4 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0C58 - 0C5F +KC58: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +cmp cx,[esp] +lahf +seto al +add esp,byte 4 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0C60 - 0C67 +KC60: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +cmp cx,[esp] +lahf +seto al +add esp,byte 4 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0C68 - 0C6F +KC68: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +cmp cx,[esp] +lahf +seto al +add esp,byte 4 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0C70 - 0C77 +KC70: +and ebx,byte 7 +mov cx,[esi] +add esi,byte 2 +push ecx +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +cmp cx,[esp] +lahf +seto al +add esp,byte 4 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0C78 +KC78: +mov cx,[esi] +add esi,byte 2 +push ecx +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +cmp cx,[esp] +lahf +seto al +add esp,byte 4 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0C79 +KC79: +mov cx,[esi] +add esi,byte 2 +push ecx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +cmp cx,[esp] +lahf +seto al +add esp,byte 4 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0C80 - 0C87 +KC80: +and ebx,byte 7 +mov ecx,[esi] +rol ecx,16 +add esi,byte 4 +cmp [ebp+__dreg+ebx*4],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0C90 - 0C97 +KC90: +and ebx,byte 7 +mov ecx,[esi] +rol ecx,16 +add esi,byte 4 +push ecx +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +cmp ecx,[esp] +lahf +seto al +add esp,byte 4 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0C98 - 0C9F +KC98: +and ebx,byte 7 +mov ecx,[esi] +rol ecx,16 +add esi,byte 4 +push ecx +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +cmp ecx,[esp] +lahf +seto al +add esp,byte 4 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0CA0 - 0CA7 +KCA0: +and ebx,byte 7 +mov ecx,[esi] +rol ecx,16 +add esi,byte 4 +push ecx +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +cmp ecx,[esp] +lahf +seto al +add esp,byte 4 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0CA8 - 0CAF +KCA8: +and ebx,byte 7 +mov ecx,[esi] +rol ecx,16 +add esi,byte 4 +push ecx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +cmp ecx,[esp] +lahf +seto al +add esp,byte 4 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0CB0 - 0CB7 +KCB0: +and ebx,byte 7 +mov ecx,[esi] +rol ecx,16 +add esi,byte 4 +push ecx +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +cmp ecx,[esp] +lahf +seto al +add esp,byte 4 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0CB8 +KCB8: +mov ecx,[esi] +rol ecx,16 +add esi,byte 4 +push ecx +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +cmp ecx,[esp] +lahf +seto al +add esp,byte 4 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0CB9 +KCB9: +mov ecx,[esi] +rol ecx,16 +add esi,byte 4 +push ecx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +cmp ecx,[esp] +lahf +seto al +add esp,byte 4 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0D00 - 0D07 +KD00: +mov cl,byte[ebp+__dreg+24] +and ebx,byte 7 +and ecx,byte 31 +mov edx,1 +shl edx,cl +test [ebp+__dreg+ebx*4],edx +jz short ln501 +and ah,0BFh +jmp short ln502 +ln501: +or ah,40h +ln502: +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0D08 - 0D0F +KD08: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov bh,cl +add edx,byte 2 +call readmemorybyte +mov bl,cl +mov [ebp+__dreg+24],bx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0D10 - 0D17 +KD10: +mov cl,byte[ebp+__dreg+24] +and ebx,byte 7 +and ecx,byte 7 +push ecx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln503 +and ah,0BFh +jmp short ln504 +ln503: +or ah,40h +ln504: +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0D18 - 0D1F +KD18: +mov cl,byte[ebp+__dreg+24] +and ebx,byte 7 +and ecx,byte 7 +push ecx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln505 +and ah,0BFh +jmp short ln506 +ln505: +or ah,40h +ln506: +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0D20 - 0D27 +KD20: +mov cl,byte[ebp+__dreg+24] +and ebx,byte 7 +and ecx,byte 7 +push ecx +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln507 +and ah,0BFh +jmp short ln508 +ln507: +or ah,40h +ln508: +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0D28 - 0D2F +KD28: +mov cl,byte[ebp+__dreg+24] +and ebx,byte 7 +and ecx,byte 7 +push ecx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln509 +and ah,0BFh +jmp short ln510 +ln509: +or ah,40h +ln510: +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0D30 - 0D37 +KD30: +mov cl,byte[ebp+__dreg+24] +and ebx,byte 7 +and ecx,byte 7 +push ecx +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln511 +and ah,0BFh +jmp short ln512 +ln511: +or ah,40h +ln512: +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0D38 +KD38: +mov cl,byte[ebp+__dreg+24] +and ecx,byte 7 +push ecx +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln513 +and ah,0BFh +jmp short ln514 +ln513: +or ah,40h +ln514: +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0D39 +KD39: +mov cl,byte[ebp+__dreg+24] +and ecx,byte 7 +push ecx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln515 +and ah,0BFh +jmp short ln516 +ln515: +or ah,40h +ln516: +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0D3A +KD3A: +mov cl,byte[ebp+__dreg+24] +and ecx,byte 7 +push ecx +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln517 +and ah,0BFh +jmp short ln518 +ln517: +or ah,40h +ln518: +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0D3B +KD3B: +mov cl,byte[ebp+__dreg+24] +and ecx,byte 7 +push ecx +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln519 +and ah,0BFh +jmp short ln520 +ln519: +or ah,40h +ln520: +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0D3C +KD3C: +mov cl,byte[ebp+__dreg+24] +and ecx,byte 7 +push ecx +mov cx,[esi] +add esi,byte 2 +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln521 +and ah,0BFh +jmp short ln522 +ln521: +or ah,40h +ln522: +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0D40 - 0D47 +KD40: +mov cl,byte[ebp+__dreg+24] +and ebx,byte 7 +and ecx,byte 31 +mov edx,1 +shl edx,cl +mov ecx,[ebp+__dreg+ebx*4] +test ecx,edx +jz short ln523 +and ah,0BFh +jmp short ln524 +ln523: +or ah,40h +ln524: +xor ecx,edx +mov [ebp+__dreg+ebx*4],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0D48 - 0D4F +KD48: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov bh,cl +add edx,byte 2 +call readmemorybyte +mov bl,cl +add edx,byte 2 +shl ebx,16 +call readmemorybyte +mov bh,cl +add edx,byte 2 +call readmemorybyte +mov bl,cl +mov [ebp+__dreg+24],ebx +xor ebx,ebx +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0D50 - 0D57 +KD50: +mov cl,byte[ebp+__dreg+24] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln525 +and ah,0BFh +jmp short ln526 +ln525: +or ah,40h +ln526: +xor cl,dl +pop edx +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0D58 - 0D5F +KD58: +mov cl,byte[ebp+__dreg+24] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln527 +and ah,0BFh +jmp short ln528 +ln527: +or ah,40h +ln528: +xor cl,dl +pop edx +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0D60 - 0D67 +KD60: +mov cl,byte[ebp+__dreg+24] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln529 +and ah,0BFh +jmp short ln530 +ln529: +or ah,40h +ln530: +xor cl,dl +pop edx +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0D68 - 0D6F +KD68: +mov cl,byte[ebp+__dreg+24] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln531 +and ah,0BFh +jmp short ln532 +ln531: +or ah,40h +ln532: +xor cl,dl +pop edx +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0D70 - 0D77 +KD70: +mov cl,byte[ebp+__dreg+24] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln533 +and ah,0BFh +jmp short ln534 +ln533: +or ah,40h +ln534: +xor cl,dl +pop edx +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0D78 +KD78: +mov cl,byte[ebp+__dreg+24] +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln535 +and ah,0BFh +jmp short ln536 +ln535: +or ah,40h +ln536: +xor cl,dl +pop edx +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0D79 +KD79: +mov cl,byte[ebp+__dreg+24] +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln537 +and ah,0BFh +jmp short ln538 +ln537: +or ah,40h +ln538: +xor cl,dl +pop edx +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0D80 - 0D87 +KD80: +mov cl,byte[ebp+__dreg+24] +and ebx,byte 7 +and ecx,byte 31 +mov edx,1 +shl edx,cl +mov ecx,[ebp+__dreg+ebx*4] +test ecx,edx +jz short ln539 +and ah,0BFh +jmp short ln540 +ln539: +or ah,40h +ln540: +not edx +and ecx,edx +mov [ebp+__dreg+ebx*4],ecx +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0D88 - 0D8F +KD88: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +mov ebx,[ebp+__dreg+24] +mov cl,bh +call writememorybyte +add edx,byte 2 +mov cl,bl +call writememorybyte +xor ebx,ebx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0D90 - 0D97 +KD90: +mov cl,byte[ebp+__dreg+24] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln541 +and ah,0BFh +jmp short ln542 +ln541: +or ah,40h +ln542: +not dl +and cl,dl +pop edx +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0D98 - 0D9F +KD98: +mov cl,byte[ebp+__dreg+24] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln543 +and ah,0BFh +jmp short ln544 +ln543: +or ah,40h +ln544: +not dl +and cl,dl +pop edx +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0DA0 - 0DA7 +KDA0: +mov cl,byte[ebp+__dreg+24] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln545 +and ah,0BFh +jmp short ln546 +ln545: +or ah,40h +ln546: +not dl +and cl,dl +pop edx +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0DA8 - 0DAF +KDA8: +mov cl,byte[ebp+__dreg+24] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln547 +and ah,0BFh +jmp short ln548 +ln547: +or ah,40h +ln548: +not dl +and cl,dl +pop edx +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0DB0 - 0DB7 +KDB0: +mov cl,byte[ebp+__dreg+24] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln549 +and ah,0BFh +jmp short ln550 +ln549: +or ah,40h +ln550: +not dl +and cl,dl +pop edx +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0DB8 +KDB8: +mov cl,byte[ebp+__dreg+24] +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln551 +and ah,0BFh +jmp short ln552 +ln551: +or ah,40h +ln552: +not dl +and cl,dl +pop edx +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0DB9 +KDB9: +mov cl,byte[ebp+__dreg+24] +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln553 +and ah,0BFh +jmp short ln554 +ln553: +or ah,40h +ln554: +not dl +and cl,dl +pop edx +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0DC0 - 0DC7 +KDC0: +mov cl,byte[ebp+__dreg+24] +and ebx,byte 7 +and ecx,byte 31 +mov edx,1 +shl edx,cl +mov ecx,[ebp+__dreg+ebx*4] +test ecx,edx +jz short ln555 +and ah,0BFh +jmp short ln556 +ln555: +or ah,40h +ln556: +or ecx,edx +mov [ebp+__dreg+ebx*4],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0DC8 - 0DCF +KDC8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +mov ebx,[ebp+__dreg+24] +rol ebx,16 +mov cl,bh +call writememorybyte +add edx,byte 2 +mov cl,bl +call writememorybyte +add edx,byte 2 +rol ebx,16 +mov cl,bh +call writememorybyte +add edx,byte 2 +mov cl,bl +call writememorybyte +xor ebx,ebx +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0DD0 - 0DD7 +KDD0: +mov cl,byte[ebp+__dreg+24] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln557 +and ah,0BFh +jmp short ln558 +ln557: +or ah,40h +ln558: +or cl,dl +pop edx +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0DD8 - 0DDF +KDD8: +mov cl,byte[ebp+__dreg+24] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln559 +and ah,0BFh +jmp short ln560 +ln559: +or ah,40h +ln560: +or cl,dl +pop edx +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0DE0 - 0DE7 +KDE0: +mov cl,byte[ebp+__dreg+24] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln561 +and ah,0BFh +jmp short ln562 +ln561: +or ah,40h +ln562: +or cl,dl +pop edx +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0DE8 - 0DEF +KDE8: +mov cl,byte[ebp+__dreg+24] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln563 +and ah,0BFh +jmp short ln564 +ln563: +or ah,40h +ln564: +or cl,dl +pop edx +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0DF0 - 0DF7 +KDF0: +mov cl,byte[ebp+__dreg+24] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln565 +and ah,0BFh +jmp short ln566 +ln565: +or ah,40h +ln566: +or cl,dl +pop edx +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0DF8 +KDF8: +mov cl,byte[ebp+__dreg+24] +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln567 +and ah,0BFh +jmp short ln568 +ln567: +or ah,40h +ln568: +or cl,dl +pop edx +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0DF9 +KDF9: +mov cl,byte[ebp+__dreg+24] +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln569 +and ah,0BFh +jmp short ln570 +ln569: +or ah,40h +ln570: +or cl,dl +pop edx +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0F00 - 0F07 +KF00: +mov cl,byte[ebp+__dreg+28] +and ebx,byte 7 +and ecx,byte 31 +mov edx,1 +shl edx,cl +test [ebp+__dreg+ebx*4],edx +jz short ln571 +and ah,0BFh +jmp short ln572 +ln571: +or ah,40h +ln572: +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0F08 - 0F0F +KF08: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov bh,cl +add edx,byte 2 +call readmemorybyte +mov bl,cl +mov [ebp+__dreg+28],bx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0F10 - 0F17 +KF10: +mov cl,byte[ebp+__dreg+28] +and ebx,byte 7 +and ecx,byte 7 +push ecx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln573 +and ah,0BFh +jmp short ln574 +ln573: +or ah,40h +ln574: +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0F18 - 0F1F +KF18: +mov cl,byte[ebp+__dreg+28] +and ebx,byte 7 +and ecx,byte 7 +push ecx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln575 +and ah,0BFh +jmp short ln576 +ln575: +or ah,40h +ln576: +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0F20 - 0F27 +KF20: +mov cl,byte[ebp+__dreg+28] +and ebx,byte 7 +and ecx,byte 7 +push ecx +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln577 +and ah,0BFh +jmp short ln578 +ln577: +or ah,40h +ln578: +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0F28 - 0F2F +KF28: +mov cl,byte[ebp+__dreg+28] +and ebx,byte 7 +and ecx,byte 7 +push ecx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln579 +and ah,0BFh +jmp short ln580 +ln579: +or ah,40h +ln580: +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0F30 - 0F37 +KF30: +mov cl,byte[ebp+__dreg+28] +and ebx,byte 7 +and ecx,byte 7 +push ecx +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln581 +and ah,0BFh +jmp short ln582 +ln581: +or ah,40h +ln582: +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0F38 +KF38: +mov cl,byte[ebp+__dreg+28] +and ecx,byte 7 +push ecx +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln583 +and ah,0BFh +jmp short ln584 +ln583: +or ah,40h +ln584: +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0F39 +KF39: +mov cl,byte[ebp+__dreg+28] +and ecx,byte 7 +push ecx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln585 +and ah,0BFh +jmp short ln586 +ln585: +or ah,40h +ln586: +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0F3A +KF3A: +mov cl,byte[ebp+__dreg+28] +and ecx,byte 7 +push ecx +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln587 +and ah,0BFh +jmp short ln588 +ln587: +or ah,40h +ln588: +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0F3B +KF3B: +mov cl,byte[ebp+__dreg+28] +and ecx,byte 7 +push ecx +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln589 +and ah,0BFh +jmp short ln590 +ln589: +or ah,40h +ln590: +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0F3C +KF3C: +mov cl,byte[ebp+__dreg+28] +and ecx,byte 7 +push ecx +mov cx,[esi] +add esi,byte 2 +mov edx,ecx +pop ecx +inc cl +shr dl,cl +jnc short ln591 +and ah,0BFh +jmp short ln592 +ln591: +or ah,40h +ln592: +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0F40 - 0F47 +KF40: +mov cl,byte[ebp+__dreg+28] +and ebx,byte 7 +and ecx,byte 31 +mov edx,1 +shl edx,cl +mov ecx,[ebp+__dreg+ebx*4] +test ecx,edx +jz short ln593 +and ah,0BFh +jmp short ln594 +ln593: +or ah,40h +ln594: +xor ecx,edx +mov [ebp+__dreg+ebx*4],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0F48 - 0F4F +KF48: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov bh,cl +add edx,byte 2 +call readmemorybyte +mov bl,cl +add edx,byte 2 +shl ebx,16 +call readmemorybyte +mov bh,cl +add edx,byte 2 +call readmemorybyte +mov bl,cl +mov [ebp+__dreg+28],ebx +xor ebx,ebx +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0F50 - 0F57 +KF50: +mov cl,byte[ebp+__dreg+28] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln595 +and ah,0BFh +jmp short ln596 +ln595: +or ah,40h +ln596: +xor cl,dl +pop edx +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0F58 - 0F5F +KF58: +mov cl,byte[ebp+__dreg+28] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln597 +and ah,0BFh +jmp short ln598 +ln597: +or ah,40h +ln598: +xor cl,dl +pop edx +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0F60 - 0F67 +KF60: +mov cl,byte[ebp+__dreg+28] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln599 +and ah,0BFh +jmp short ln600 +ln599: +or ah,40h +ln600: +xor cl,dl +pop edx +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0F68 - 0F6F +KF68: +mov cl,byte[ebp+__dreg+28] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln601 +and ah,0BFh +jmp short ln602 +ln601: +or ah,40h +ln602: +xor cl,dl +pop edx +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0F70 - 0F77 +KF70: +mov cl,byte[ebp+__dreg+28] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln603 +and ah,0BFh +jmp short ln604 +ln603: +or ah,40h +ln604: +xor cl,dl +pop edx +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0F78 +KF78: +mov cl,byte[ebp+__dreg+28] +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln605 +and ah,0BFh +jmp short ln606 +ln605: +or ah,40h +ln606: +xor cl,dl +pop edx +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0F79 +KF79: +mov cl,byte[ebp+__dreg+28] +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln607 +and ah,0BFh +jmp short ln608 +ln607: +or ah,40h +ln608: +xor cl,dl +pop edx +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0F80 - 0F87 +KF80: +mov cl,byte[ebp+__dreg+28] +and ebx,byte 7 +and ecx,byte 31 +mov edx,1 +shl edx,cl +mov ecx,[ebp+__dreg+ebx*4] +test ecx,edx +jz short ln609 +and ah,0BFh +jmp short ln610 +ln609: +or ah,40h +ln610: +not edx +and ecx,edx +mov [ebp+__dreg+ebx*4],ecx +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0F88 - 0F8F +KF88: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +mov ebx,[ebp+__dreg+28] +mov cl,bh +call writememorybyte +add edx,byte 2 +mov cl,bl +call writememorybyte +xor ebx,ebx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0F90 - 0F97 +KF90: +mov cl,byte[ebp+__dreg+28] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln611 +and ah,0BFh +jmp short ln612 +ln611: +or ah,40h +ln612: +not dl +and cl,dl +pop edx +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0F98 - 0F9F +KF98: +mov cl,byte[ebp+__dreg+28] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln613 +and ah,0BFh +jmp short ln614 +ln613: +or ah,40h +ln614: +not dl +and cl,dl +pop edx +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0FA0 - 0FA7 +KFA0: +mov cl,byte[ebp+__dreg+28] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln615 +and ah,0BFh +jmp short ln616 +ln615: +or ah,40h +ln616: +not dl +and cl,dl +pop edx +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0FA8 - 0FAF +KFA8: +mov cl,byte[ebp+__dreg+28] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln617 +and ah,0BFh +jmp short ln618 +ln617: +or ah,40h +ln618: +not dl +and cl,dl +pop edx +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0FB0 - 0FB7 +KFB0: +mov cl,byte[ebp+__dreg+28] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln619 +and ah,0BFh +jmp short ln620 +ln619: +or ah,40h +ln620: +not dl +and cl,dl +pop edx +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0FB8 +KFB8: +mov cl,byte[ebp+__dreg+28] +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln621 +and ah,0BFh +jmp short ln622 +ln621: +or ah,40h +ln622: +not dl +and cl,dl +pop edx +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0FB9 +KFB9: +mov cl,byte[ebp+__dreg+28] +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln623 +and ah,0BFh +jmp short ln624 +ln623: +or ah,40h +ln624: +not dl +and cl,dl +pop edx +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0FC0 - 0FC7 +KFC0: +mov cl,byte[ebp+__dreg+28] +and ebx,byte 7 +and ecx,byte 31 +mov edx,1 +shl edx,cl +mov ecx,[ebp+__dreg+ebx*4] +test ecx,edx +jz short ln625 +and ah,0BFh +jmp short ln626 +ln625: +or ah,40h +ln626: +or ecx,edx +mov [ebp+__dreg+ebx*4],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0FC8 - 0FCF +KFC8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +mov ebx,[ebp+__dreg+28] +rol ebx,16 +mov cl,bh +call writememorybyte +add edx,byte 2 +mov cl,bl +call writememorybyte +add edx,byte 2 +rol ebx,16 +mov cl,bh +call writememorybyte +add edx,byte 2 +mov cl,bl +call writememorybyte +xor ebx,ebx +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0FD0 - 0FD7 +KFD0: +mov cl,byte[ebp+__dreg+28] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln627 +and ah,0BFh +jmp short ln628 +ln627: +or ah,40h +ln628: +or cl,dl +pop edx +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0FD8 - 0FDF +KFD8: +mov cl,byte[ebp+__dreg+28] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln629 +and ah,0BFh +jmp short ln630 +ln629: +or ah,40h +ln630: +or cl,dl +pop edx +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0FE0 - 0FE7 +KFE0: +mov cl,byte[ebp+__dreg+28] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln631 +and ah,0BFh +jmp short ln632 +ln631: +or ah,40h +ln632: +or cl,dl +pop edx +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0FE8 - 0FEF +KFE8: +mov cl,byte[ebp+__dreg+28] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln633 +and ah,0BFh +jmp short ln634 +ln633: +or ah,40h +ln634: +or cl,dl +pop edx +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 0FF0 - 0FF7 +KFF0: +mov cl,byte[ebp+__dreg+28] +and ebx,byte 7 +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln635 +and ah,0BFh +jmp short ln636 +ln635: +or ah,40h +ln636: +or cl,dl +pop edx +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0FF8 +KFF8: +mov cl,byte[ebp+__dreg+28] +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln637 +and ah,0BFh +jmp short ln638 +ln637: +or ah,40h +ln638: +or cl,dl +pop edx +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 0FF9 +KFF9: +mov cl,byte[ebp+__dreg+28] +and ecx,byte 7 +mov dl,1 +shl dl,cl +push edx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +xchg edx,[esp] +test cl,dl +jz short ln639 +and ah,0BFh +jmp short ln640 +ln639: +or ah,40h +ln640: +or cl,dl +pop edx +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1000 - 1007 +L000: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+0],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1008 - 100F +L008: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov [ebp+__dreg+0],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1010 - 1017 +L010: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov [ebp+__dreg+0],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1018 - 101F +L018: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +mov [ebp+__dreg+0],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1020 - 1027 +L020: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov [ebp+__dreg+0],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1028 - 102F +L028: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov [ebp+__dreg+0],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1030 - 1037 +L030: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov [ebp+__dreg+0],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1038 +L038: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +mov [ebp+__dreg+0],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1039 +L039: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +mov [ebp+__dreg+0],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 103A +L03A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +mov [ebp+__dreg+0],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 103B +L03B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +mov [ebp+__dreg+0],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 103C +L03C: +mov cx,[esi] +add esi,byte 2 +mov [ebp+__dreg+0],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1080 - 1087 +L080: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+0] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1088 - 108F +L088: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+0] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1090 - 1097 +L090: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+0] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1098 - 109F +L098: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+0] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 10A0 - 10A7 +L0A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+0] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 10A8 - 10AF +L0A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+0] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 10B0 - 10B7 +L0B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+0] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 10B8 +L0B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+0] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 10B9 +L0B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +mov edx,[ebp+__areg+0] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 10BA +L0BA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+0] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 10BB +L0BB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+0] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 10BC +L0BC: +mov cx,[esi] +add esi,byte 2 +mov edx,[ebp+__areg+0] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 10C0 - 10C7 +L0C0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+0] +call writememorybyte +inc edx +mov [ebp+__areg+0],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 10C8 - 10CF +L0C8: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+0] +call writememorybyte +inc edx +mov [ebp+__areg+0],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 10D0 - 10D7 +L0D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+0] +call writememorybyte +inc edx +mov [ebp+__areg+0],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 10D8 - 10DF +L0D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+0] +call writememorybyte +inc edx +mov [ebp+__areg+0],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 10E0 - 10E7 +L0E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+0] +call writememorybyte +inc edx +mov [ebp+__areg+0],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 10E8 - 10EF +L0E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+0] +call writememorybyte +inc edx +mov [ebp+__areg+0],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 10F0 - 10F7 +L0F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+0] +call writememorybyte +inc edx +mov [ebp+__areg+0],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 10F8 +L0F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+0] +call writememorybyte +inc edx +mov [ebp+__areg+0],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 10F9 +L0F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +mov edx,[ebp+__areg+0] +call writememorybyte +inc edx +mov [ebp+__areg+0],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 10FA +L0FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+0] +call writememorybyte +inc edx +mov [ebp+__areg+0],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 10FB +L0FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+0] +call writememorybyte +inc edx +mov [ebp+__areg+0],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 10FC +L0FC: +mov cx,[esi] +add esi,byte 2 +mov edx,[ebp+__areg+0] +call writememorybyte +inc edx +mov [ebp+__areg+0],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1100 - 1107 +L100: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+0] +dec edx +call writememorybyte +mov [ebp+__areg+0],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1108 - 110F +L108: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+0] +dec edx +call writememorybyte +mov [ebp+__areg+0],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1110 - 1117 +L110: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+0] +dec edx +call writememorybyte +mov [ebp+__areg+0],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1118 - 111F +L118: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+0] +dec edx +call writememorybyte +mov [ebp+__areg+0],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1120 - 1127 +L120: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+0] +dec edx +call writememorybyte +mov [ebp+__areg+0],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1128 - 112F +L128: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+0] +dec edx +call writememorybyte +mov [ebp+__areg+0],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1130 - 1137 +L130: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+0] +dec edx +call writememorybyte +mov [ebp+__areg+0],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1138 +L138: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+0] +dec edx +call writememorybyte +mov [ebp+__areg+0],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1139 +L139: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +mov edx,[ebp+__areg+0] +dec edx +call writememorybyte +mov [ebp+__areg+0],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 113A +L13A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+0] +dec edx +call writememorybyte +mov [ebp+__areg+0],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 113B +L13B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+0] +dec edx +call writememorybyte +mov [ebp+__areg+0],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 113C +L13C: +mov cx,[esi] +add esi,byte 2 +mov edx,[ebp+__areg+0] +dec edx +call writememorybyte +mov [ebp+__areg+0],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1140 - 1147 +L140: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+0] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1148 - 114F +L148: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+0] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1150 - 1157 +L150: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+0] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1158 - 115F +L158: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+0] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1160 - 1167 +L160: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+0] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1168 - 116F +L168: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+0] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1170 - 1177 +L170: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+0] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1178 +L178: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+0] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1179 +L179: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+0] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 117A +L17A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+0] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 117B +L17B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+0] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 117C +L17C: +mov cx,[esi] +add esi,byte 2 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+0] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1180 - 1187 +L180: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +call decode_ext +add edx,[ebp+__areg+0] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1188 - 118F +L188: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +call decode_ext +add edx,[ebp+__areg+0] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1190 - 1197 +L190: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +call decode_ext +add edx,[ebp+__areg+0] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1198 - 119F +L198: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +call decode_ext +add edx,[ebp+__areg+0] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 11A0 - 11A7 +L1A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +call decode_ext +add edx,[ebp+__areg+0] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 11A8 - 11AF +L1A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +call decode_ext +add edx,[ebp+__areg+0] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 11B0 - 11B7 +L1B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +call decode_ext +add edx,[ebp+__areg+0] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 11B8 +L1B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +call decode_ext +add edx,[ebp+__areg+0] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 11B9 +L1B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +call decode_ext +add edx,[ebp+__areg+0] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 11BA +L1BA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +call decode_ext +add edx,[ebp+__areg+0] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 11BB +L1BB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +call decode_ext +add edx,[ebp+__areg+0] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 11BC +L1BC: +mov cx,[esi] +add esi,byte 2 +call decode_ext +add edx,[ebp+__areg+0] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 11C0 - 11C7 +L1C0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +movsx edx,word[esi] +add esi,byte 2 +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 11C8 - 11CF +L1C8: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +movsx edx,word[esi] +add esi,byte 2 +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 11D0 - 11D7 +L1D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 11D8 - 11DF +L1D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +movsx edx,word[esi] +add esi,byte 2 +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 11E0 - 11E7 +L1E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +movsx edx,word[esi] +add esi,byte 2 +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 11E8 - 11EF +L1E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 11F0 - 11F7 +L1F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 11F8 +L1F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 11F9 +L1F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 11FA +L1FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 11FB +L1FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 11FC +L1FC: +mov cx,[esi] +add esi,byte 2 +movsx edx,word[esi] +add esi,byte 2 +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1200 - 1207 +L200: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+4],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1208 - 120F +L208: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov [ebp+__dreg+4],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1210 - 1217 +L210: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov [ebp+__dreg+4],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1218 - 121F +L218: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +mov [ebp+__dreg+4],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1220 - 1227 +L220: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov [ebp+__dreg+4],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1228 - 122F +L228: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov [ebp+__dreg+4],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1230 - 1237 +L230: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov [ebp+__dreg+4],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1238 +L238: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +mov [ebp+__dreg+4],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1239 +L239: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +mov [ebp+__dreg+4],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 123A +L23A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +mov [ebp+__dreg+4],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 123B +L23B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +mov [ebp+__dreg+4],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 123C +L23C: +mov cx,[esi] +add esi,byte 2 +mov [ebp+__dreg+4],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1280 - 1287 +L280: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+4] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1288 - 128F +L288: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+4] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1290 - 1297 +L290: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+4] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1298 - 129F +L298: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+4] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 12A0 - 12A7 +L2A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+4] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 12A8 - 12AF +L2A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+4] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 12B0 - 12B7 +L2B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+4] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 12B8 +L2B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+4] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 12B9 +L2B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +mov edx,[ebp+__areg+4] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 12BA +L2BA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+4] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 12BB +L2BB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+4] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 12BC +L2BC: +mov cx,[esi] +add esi,byte 2 +mov edx,[ebp+__areg+4] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 12C0 - 12C7 +L2C0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+4] +call writememorybyte +inc edx +mov [ebp+__areg+4],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 12C8 - 12CF +L2C8: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+4] +call writememorybyte +inc edx +mov [ebp+__areg+4],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 12D0 - 12D7 +L2D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+4] +call writememorybyte +inc edx +mov [ebp+__areg+4],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 12D8 - 12DF +L2D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+4] +call writememorybyte +inc edx +mov [ebp+__areg+4],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 12E0 - 12E7 +L2E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+4] +call writememorybyte +inc edx +mov [ebp+__areg+4],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 12E8 - 12EF +L2E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+4] +call writememorybyte +inc edx +mov [ebp+__areg+4],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 12F0 - 12F7 +L2F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+4] +call writememorybyte +inc edx +mov [ebp+__areg+4],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 12F8 +L2F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+4] +call writememorybyte +inc edx +mov [ebp+__areg+4],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 12F9 +L2F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +mov edx,[ebp+__areg+4] +call writememorybyte +inc edx +mov [ebp+__areg+4],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 12FA +L2FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+4] +call writememorybyte +inc edx +mov [ebp+__areg+4],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 12FB +L2FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+4] +call writememorybyte +inc edx +mov [ebp+__areg+4],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 12FC +L2FC: +mov cx,[esi] +add esi,byte 2 +mov edx,[ebp+__areg+4] +call writememorybyte +inc edx +mov [ebp+__areg+4],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1300 - 1307 +L300: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+4] +dec edx +call writememorybyte +mov [ebp+__areg+4],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1308 - 130F +L308: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+4] +dec edx +call writememorybyte +mov [ebp+__areg+4],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1310 - 1317 +L310: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+4] +dec edx +call writememorybyte +mov [ebp+__areg+4],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1318 - 131F +L318: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+4] +dec edx +call writememorybyte +mov [ebp+__areg+4],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1320 - 1327 +L320: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+4] +dec edx +call writememorybyte +mov [ebp+__areg+4],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1328 - 132F +L328: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+4] +dec edx +call writememorybyte +mov [ebp+__areg+4],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1330 - 1337 +L330: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+4] +dec edx +call writememorybyte +mov [ebp+__areg+4],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1338 +L338: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+4] +dec edx +call writememorybyte +mov [ebp+__areg+4],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1339 +L339: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +mov edx,[ebp+__areg+4] +dec edx +call writememorybyte +mov [ebp+__areg+4],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 133A +L33A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+4] +dec edx +call writememorybyte +mov [ebp+__areg+4],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 133B +L33B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+4] +dec edx +call writememorybyte +mov [ebp+__areg+4],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 133C +L33C: +mov cx,[esi] +add esi,byte 2 +mov edx,[ebp+__areg+4] +dec edx +call writememorybyte +mov [ebp+__areg+4],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1340 - 1347 +L340: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+4] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1348 - 134F +L348: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+4] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1350 - 1357 +L350: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+4] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1358 - 135F +L358: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+4] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1360 - 1367 +L360: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+4] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1368 - 136F +L368: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+4] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1370 - 1377 +L370: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+4] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1378 +L378: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+4] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1379 +L379: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+4] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 137A +L37A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+4] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 137B +L37B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+4] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 137C +L37C: +mov cx,[esi] +add esi,byte 2 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+4] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1380 - 1387 +L380: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +call decode_ext +add edx,[ebp+__areg+4] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1388 - 138F +L388: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +call decode_ext +add edx,[ebp+__areg+4] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1390 - 1397 +L390: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +call decode_ext +add edx,[ebp+__areg+4] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1398 - 139F +L398: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +call decode_ext +add edx,[ebp+__areg+4] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 13A0 - 13A7 +L3A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +call decode_ext +add edx,[ebp+__areg+4] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 13A8 - 13AF +L3A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +call decode_ext +add edx,[ebp+__areg+4] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 13B0 - 13B7 +L3B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +call decode_ext +add edx,[ebp+__areg+4] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 13B8 +L3B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +call decode_ext +add edx,[ebp+__areg+4] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 13B9 +L3B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +call decode_ext +add edx,[ebp+__areg+4] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 13BA +L3BA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +call decode_ext +add edx,[ebp+__areg+4] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 13BB +L3BB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +call decode_ext +add edx,[ebp+__areg+4] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 13BC +L3BC: +mov cx,[esi] +add esi,byte 2 +call decode_ext +add edx,[ebp+__areg+4] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 13C0 - 13C7 +L3C0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 13C8 - 13CF +L3C8: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 13D0 - 13D7 +L3D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 13D8 - 13DF +L3D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 13E0 - 13E7 +L3E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 13E8 - 13EF +L3E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 13F0 - 13F7 +L3F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 13F8 +L3F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 13F9 +L3F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 13FA +L3FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 13FB +L3FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 13FC +L3FC: +mov cx,[esi] +add esi,byte 2 +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1400 - 1407 +L400: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+8],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1408 - 140F +L408: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov [ebp+__dreg+8],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1410 - 1417 +L410: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov [ebp+__dreg+8],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1418 - 141F +L418: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +mov [ebp+__dreg+8],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1420 - 1427 +L420: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov [ebp+__dreg+8],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1428 - 142F +L428: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov [ebp+__dreg+8],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1430 - 1437 +L430: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov [ebp+__dreg+8],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1438 +L438: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +mov [ebp+__dreg+8],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1439 +L439: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +mov [ebp+__dreg+8],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 143A +L43A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +mov [ebp+__dreg+8],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 143B +L43B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +mov [ebp+__dreg+8],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 143C +L43C: +mov cx,[esi] +add esi,byte 2 +mov [ebp+__dreg+8],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1480 - 1487 +L480: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+8] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1488 - 148F +L488: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+8] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1490 - 1497 +L490: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+8] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1498 - 149F +L498: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+8] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 14A0 - 14A7 +L4A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+8] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 14A8 - 14AF +L4A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+8] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 14B0 - 14B7 +L4B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+8] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 14B8 +L4B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+8] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 14B9 +L4B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +mov edx,[ebp+__areg+8] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 14BA +L4BA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+8] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 14BB +L4BB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+8] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 14BC +L4BC: +mov cx,[esi] +add esi,byte 2 +mov edx,[ebp+__areg+8] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 14C0 - 14C7 +L4C0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+8] +call writememorybyte +inc edx +mov [ebp+__areg+8],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 14C8 - 14CF +L4C8: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+8] +call writememorybyte +inc edx +mov [ebp+__areg+8],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 14D0 - 14D7 +L4D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+8] +call writememorybyte +inc edx +mov [ebp+__areg+8],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 14D8 - 14DF +L4D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+8] +call writememorybyte +inc edx +mov [ebp+__areg+8],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 14E0 - 14E7 +L4E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+8] +call writememorybyte +inc edx +mov [ebp+__areg+8],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 14E8 - 14EF +L4E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+8] +call writememorybyte +inc edx +mov [ebp+__areg+8],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 14F0 - 14F7 +L4F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+8] +call writememorybyte +inc edx +mov [ebp+__areg+8],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 14F8 +L4F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+8] +call writememorybyte +inc edx +mov [ebp+__areg+8],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 14F9 +L4F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +mov edx,[ebp+__areg+8] +call writememorybyte +inc edx +mov [ebp+__areg+8],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 14FA +L4FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+8] +call writememorybyte +inc edx +mov [ebp+__areg+8],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 14FB +L4FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+8] +call writememorybyte +inc edx +mov [ebp+__areg+8],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 14FC +L4FC: +mov cx,[esi] +add esi,byte 2 +mov edx,[ebp+__areg+8] +call writememorybyte +inc edx +mov [ebp+__areg+8],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1500 - 1507 +L500: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+8] +dec edx +call writememorybyte +mov [ebp+__areg+8],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1508 - 150F +L508: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+8] +dec edx +call writememorybyte +mov [ebp+__areg+8],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1510 - 1517 +L510: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+8] +dec edx +call writememorybyte +mov [ebp+__areg+8],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1518 - 151F +L518: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+8] +dec edx +call writememorybyte +mov [ebp+__areg+8],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1520 - 1527 +L520: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+8] +dec edx +call writememorybyte +mov [ebp+__areg+8],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1528 - 152F +L528: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+8] +dec edx +call writememorybyte +mov [ebp+__areg+8],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1530 - 1537 +L530: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+8] +dec edx +call writememorybyte +mov [ebp+__areg+8],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1538 +L538: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+8] +dec edx +call writememorybyte +mov [ebp+__areg+8],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1539 +L539: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +mov edx,[ebp+__areg+8] +dec edx +call writememorybyte +mov [ebp+__areg+8],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 153A +L53A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+8] +dec edx +call writememorybyte +mov [ebp+__areg+8],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 153B +L53B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+8] +dec edx +call writememorybyte +mov [ebp+__areg+8],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 153C +L53C: +mov cx,[esi] +add esi,byte 2 +mov edx,[ebp+__areg+8] +dec edx +call writememorybyte +mov [ebp+__areg+8],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1540 - 1547 +L540: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+8] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1548 - 154F +L548: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+8] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1550 - 1557 +L550: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+8] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1558 - 155F +L558: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+8] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1560 - 1567 +L560: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+8] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1568 - 156F +L568: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+8] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1570 - 1577 +L570: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+8] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1578 +L578: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+8] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1579 +L579: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+8] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 157A +L57A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+8] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 157B +L57B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+8] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 157C +L57C: +mov cx,[esi] +add esi,byte 2 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+8] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1580 - 1587 +L580: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +call decode_ext +add edx,[ebp+__areg+8] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1588 - 158F +L588: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +call decode_ext +add edx,[ebp+__areg+8] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1590 - 1597 +L590: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +call decode_ext +add edx,[ebp+__areg+8] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1598 - 159F +L598: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +call decode_ext +add edx,[ebp+__areg+8] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 15A0 - 15A7 +L5A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +call decode_ext +add edx,[ebp+__areg+8] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 15A8 - 15AF +L5A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +call decode_ext +add edx,[ebp+__areg+8] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 15B0 - 15B7 +L5B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +call decode_ext +add edx,[ebp+__areg+8] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 15B8 +L5B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +call decode_ext +add edx,[ebp+__areg+8] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 15B9 +L5B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +call decode_ext +add edx,[ebp+__areg+8] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 15BA +L5BA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +call decode_ext +add edx,[ebp+__areg+8] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 15BB +L5BB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +call decode_ext +add edx,[ebp+__areg+8] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 15BC +L5BC: +mov cx,[esi] +add esi,byte 2 +call decode_ext +add edx,[ebp+__areg+8] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1600 - 1607 +L600: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+12],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1608 - 160F +L608: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov [ebp+__dreg+12],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1610 - 1617 +L610: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov [ebp+__dreg+12],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1618 - 161F +L618: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +mov [ebp+__dreg+12],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1620 - 1627 +L620: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov [ebp+__dreg+12],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1628 - 162F +L628: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov [ebp+__dreg+12],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1630 - 1637 +L630: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov [ebp+__dreg+12],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1638 +L638: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +mov [ebp+__dreg+12],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1639 +L639: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +mov [ebp+__dreg+12],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 163A +L63A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +mov [ebp+__dreg+12],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 163B +L63B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +mov [ebp+__dreg+12],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 163C +L63C: +mov cx,[esi] +add esi,byte 2 +mov [ebp+__dreg+12],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1680 - 1687 +L680: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+12] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1688 - 168F +L688: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+12] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1690 - 1697 +L690: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+12] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1698 - 169F +L698: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+12] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 16A0 - 16A7 +L6A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+12] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 16A8 - 16AF +L6A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+12] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 16B0 - 16B7 +L6B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+12] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 16B8 +L6B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+12] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 16B9 +L6B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +mov edx,[ebp+__areg+12] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 16BA +L6BA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+12] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 16BB +L6BB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+12] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 16BC +L6BC: +mov cx,[esi] +add esi,byte 2 +mov edx,[ebp+__areg+12] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 16C0 - 16C7 +L6C0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+12] +call writememorybyte +inc edx +mov [ebp+__areg+12],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 16C8 - 16CF +L6C8: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+12] +call writememorybyte +inc edx +mov [ebp+__areg+12],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 16D0 - 16D7 +L6D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+12] +call writememorybyte +inc edx +mov [ebp+__areg+12],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 16D8 - 16DF +L6D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+12] +call writememorybyte +inc edx +mov [ebp+__areg+12],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 16E0 - 16E7 +L6E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+12] +call writememorybyte +inc edx +mov [ebp+__areg+12],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 16E8 - 16EF +L6E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+12] +call writememorybyte +inc edx +mov [ebp+__areg+12],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 16F0 - 16F7 +L6F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+12] +call writememorybyte +inc edx +mov [ebp+__areg+12],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 16F8 +L6F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+12] +call writememorybyte +inc edx +mov [ebp+__areg+12],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 16F9 +L6F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +mov edx,[ebp+__areg+12] +call writememorybyte +inc edx +mov [ebp+__areg+12],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 16FA +L6FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+12] +call writememorybyte +inc edx +mov [ebp+__areg+12],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 16FB +L6FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+12] +call writememorybyte +inc edx +mov [ebp+__areg+12],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 16FC +L6FC: +mov cx,[esi] +add esi,byte 2 +mov edx,[ebp+__areg+12] +call writememorybyte +inc edx +mov [ebp+__areg+12],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1700 - 1707 +L700: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+12] +dec edx +call writememorybyte +mov [ebp+__areg+12],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1708 - 170F +L708: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+12] +dec edx +call writememorybyte +mov [ebp+__areg+12],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1710 - 1717 +L710: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+12] +dec edx +call writememorybyte +mov [ebp+__areg+12],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1718 - 171F +L718: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+12] +dec edx +call writememorybyte +mov [ebp+__areg+12],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1720 - 1727 +L720: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+12] +dec edx +call writememorybyte +mov [ebp+__areg+12],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1728 - 172F +L728: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+12] +dec edx +call writememorybyte +mov [ebp+__areg+12],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1730 - 1737 +L730: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+12] +dec edx +call writememorybyte +mov [ebp+__areg+12],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1738 +L738: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+12] +dec edx +call writememorybyte +mov [ebp+__areg+12],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1739 +L739: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +mov edx,[ebp+__areg+12] +dec edx +call writememorybyte +mov [ebp+__areg+12],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 173A +L73A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+12] +dec edx +call writememorybyte +mov [ebp+__areg+12],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 173B +L73B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+12] +dec edx +call writememorybyte +mov [ebp+__areg+12],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 173C +L73C: +mov cx,[esi] +add esi,byte 2 +mov edx,[ebp+__areg+12] +dec edx +call writememorybyte +mov [ebp+__areg+12],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1740 - 1747 +L740: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+12] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1748 - 174F +L748: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+12] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1750 - 1757 +L750: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+12] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1758 - 175F +L758: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+12] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1760 - 1767 +L760: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+12] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1768 - 176F +L768: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+12] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1770 - 1777 +L770: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+12] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1778 +L778: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+12] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1779 +L779: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+12] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 177A +L77A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+12] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 177B +L77B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+12] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 177C +L77C: +mov cx,[esi] +add esi,byte 2 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+12] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1780 - 1787 +L780: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +call decode_ext +add edx,[ebp+__areg+12] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1788 - 178F +L788: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +call decode_ext +add edx,[ebp+__areg+12] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1790 - 1797 +L790: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +call decode_ext +add edx,[ebp+__areg+12] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1798 - 179F +L798: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +call decode_ext +add edx,[ebp+__areg+12] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 17A0 - 17A7 +L7A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +call decode_ext +add edx,[ebp+__areg+12] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 17A8 - 17AF +L7A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +call decode_ext +add edx,[ebp+__areg+12] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 17B0 - 17B7 +L7B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +call decode_ext +add edx,[ebp+__areg+12] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 17B8 +L7B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +call decode_ext +add edx,[ebp+__areg+12] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 17B9 +L7B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +call decode_ext +add edx,[ebp+__areg+12] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 17BA +L7BA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +call decode_ext +add edx,[ebp+__areg+12] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 17BB +L7BB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +call decode_ext +add edx,[ebp+__areg+12] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 17BC +L7BC: +mov cx,[esi] +add esi,byte 2 +call decode_ext +add edx,[ebp+__areg+12] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1800 - 1807 +L800: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+16],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1808 - 180F +L808: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov [ebp+__dreg+16],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1810 - 1817 +L810: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov [ebp+__dreg+16],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1818 - 181F +L818: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +mov [ebp+__dreg+16],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1820 - 1827 +L820: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov [ebp+__dreg+16],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1828 - 182F +L828: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov [ebp+__dreg+16],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1830 - 1837 +L830: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov [ebp+__dreg+16],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1838 +L838: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +mov [ebp+__dreg+16],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1839 +L839: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +mov [ebp+__dreg+16],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 183A +L83A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +mov [ebp+__dreg+16],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 183B +L83B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +mov [ebp+__dreg+16],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 183C +L83C: +mov cx,[esi] +add esi,byte 2 +mov [ebp+__dreg+16],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1880 - 1887 +L880: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+16] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1888 - 188F +L888: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+16] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1890 - 1897 +L890: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+16] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1898 - 189F +L898: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+16] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 18A0 - 18A7 +L8A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+16] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 18A8 - 18AF +L8A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+16] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 18B0 - 18B7 +L8B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+16] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 18B8 +L8B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+16] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 18B9 +L8B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +mov edx,[ebp+__areg+16] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 18BA +L8BA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+16] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 18BB +L8BB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+16] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 18BC +L8BC: +mov cx,[esi] +add esi,byte 2 +mov edx,[ebp+__areg+16] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 18C0 - 18C7 +L8C0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+16] +call writememorybyte +inc edx +mov [ebp+__areg+16],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 18C8 - 18CF +L8C8: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+16] +call writememorybyte +inc edx +mov [ebp+__areg+16],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 18D0 - 18D7 +L8D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+16] +call writememorybyte +inc edx +mov [ebp+__areg+16],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 18D8 - 18DF +L8D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+16] +call writememorybyte +inc edx +mov [ebp+__areg+16],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 18E0 - 18E7 +L8E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+16] +call writememorybyte +inc edx +mov [ebp+__areg+16],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 18E8 - 18EF +L8E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+16] +call writememorybyte +inc edx +mov [ebp+__areg+16],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 18F0 - 18F7 +L8F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+16] +call writememorybyte +inc edx +mov [ebp+__areg+16],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 18F8 +L8F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+16] +call writememorybyte +inc edx +mov [ebp+__areg+16],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 18F9 +L8F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +mov edx,[ebp+__areg+16] +call writememorybyte +inc edx +mov [ebp+__areg+16],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 18FA +L8FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+16] +call writememorybyte +inc edx +mov [ebp+__areg+16],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 18FB +L8FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+16] +call writememorybyte +inc edx +mov [ebp+__areg+16],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 18FC +L8FC: +mov cx,[esi] +add esi,byte 2 +mov edx,[ebp+__areg+16] +call writememorybyte +inc edx +mov [ebp+__areg+16],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1900 - 1907 +L900: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+16] +dec edx +call writememorybyte +mov [ebp+__areg+16],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1908 - 190F +L908: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+16] +dec edx +call writememorybyte +mov [ebp+__areg+16],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1910 - 1917 +L910: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+16] +dec edx +call writememorybyte +mov [ebp+__areg+16],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1918 - 191F +L918: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+16] +dec edx +call writememorybyte +mov [ebp+__areg+16],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1920 - 1927 +L920: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+16] +dec edx +call writememorybyte +mov [ebp+__areg+16],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1928 - 192F +L928: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+16] +dec edx +call writememorybyte +mov [ebp+__areg+16],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1930 - 1937 +L930: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+16] +dec edx +call writememorybyte +mov [ebp+__areg+16],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1938 +L938: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+16] +dec edx +call writememorybyte +mov [ebp+__areg+16],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1939 +L939: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +mov edx,[ebp+__areg+16] +dec edx +call writememorybyte +mov [ebp+__areg+16],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 193A +L93A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+16] +dec edx +call writememorybyte +mov [ebp+__areg+16],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 193B +L93B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+16] +dec edx +call writememorybyte +mov [ebp+__areg+16],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 193C +L93C: +mov cx,[esi] +add esi,byte 2 +mov edx,[ebp+__areg+16] +dec edx +call writememorybyte +mov [ebp+__areg+16],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1940 - 1947 +L940: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+16] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1948 - 194F +L948: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+16] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1950 - 1957 +L950: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+16] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1958 - 195F +L958: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+16] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1960 - 1967 +L960: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+16] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1968 - 196F +L968: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+16] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1970 - 1977 +L970: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+16] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1978 +L978: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+16] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1979 +L979: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+16] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 197A +L97A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+16] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 197B +L97B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+16] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 197C +L97C: +mov cx,[esi] +add esi,byte 2 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+16] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1980 - 1987 +L980: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +call decode_ext +add edx,[ebp+__areg+16] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1988 - 198F +L988: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +call decode_ext +add edx,[ebp+__areg+16] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1990 - 1997 +L990: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +call decode_ext +add edx,[ebp+__areg+16] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1998 - 199F +L998: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +call decode_ext +add edx,[ebp+__areg+16] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 19A0 - 19A7 +L9A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +call decode_ext +add edx,[ebp+__areg+16] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 19A8 - 19AF +L9A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +call decode_ext +add edx,[ebp+__areg+16] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 19B0 - 19B7 +L9B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +call decode_ext +add edx,[ebp+__areg+16] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 19B8 +L9B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +call decode_ext +add edx,[ebp+__areg+16] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 19B9 +L9B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +call decode_ext +add edx,[ebp+__areg+16] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 19BA +L9BA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +call decode_ext +add edx,[ebp+__areg+16] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 19BB +L9BB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +call decode_ext +add edx,[ebp+__areg+16] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 19BC +L9BC: +mov cx,[esi] +add esi,byte 2 +call decode_ext +add edx,[ebp+__areg+16] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1A00 - 1A07 +LA00: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+20],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1A08 - 1A0F +LA08: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov [ebp+__dreg+20],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1A10 - 1A17 +LA10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov [ebp+__dreg+20],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1A18 - 1A1F +LA18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +mov [ebp+__dreg+20],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1A20 - 1A27 +LA20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov [ebp+__dreg+20],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1A28 - 1A2F +LA28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov [ebp+__dreg+20],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1A30 - 1A37 +LA30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov [ebp+__dreg+20],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1A38 +LA38: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +mov [ebp+__dreg+20],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1A39 +LA39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +mov [ebp+__dreg+20],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1A3A +LA3A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +mov [ebp+__dreg+20],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1A3B +LA3B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +mov [ebp+__dreg+20],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1A3C +LA3C: +mov cx,[esi] +add esi,byte 2 +mov [ebp+__dreg+20],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1A80 - 1A87 +LA80: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+20] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1A88 - 1A8F +LA88: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+20] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1A90 - 1A97 +LA90: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+20] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1A98 - 1A9F +LA98: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+20] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1AA0 - 1AA7 +LAA0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+20] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1AA8 - 1AAF +LAA8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+20] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1AB0 - 1AB7 +LAB0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+20] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1AB8 +LAB8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+20] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1AB9 +LAB9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +mov edx,[ebp+__areg+20] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1ABA +LABA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+20] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1ABB +LABB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+20] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1ABC +LABC: +mov cx,[esi] +add esi,byte 2 +mov edx,[ebp+__areg+20] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1AC0 - 1AC7 +LAC0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+20] +call writememorybyte +inc edx +mov [ebp+__areg+20],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1AC8 - 1ACF +LAC8: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+20] +call writememorybyte +inc edx +mov [ebp+__areg+20],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1AD0 - 1AD7 +LAD0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+20] +call writememorybyte +inc edx +mov [ebp+__areg+20],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1AD8 - 1ADF +LAD8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+20] +call writememorybyte +inc edx +mov [ebp+__areg+20],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1AE0 - 1AE7 +LAE0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+20] +call writememorybyte +inc edx +mov [ebp+__areg+20],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1AE8 - 1AEF +LAE8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+20] +call writememorybyte +inc edx +mov [ebp+__areg+20],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1AF0 - 1AF7 +LAF0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+20] +call writememorybyte +inc edx +mov [ebp+__areg+20],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1AF8 +LAF8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+20] +call writememorybyte +inc edx +mov [ebp+__areg+20],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1AF9 +LAF9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +mov edx,[ebp+__areg+20] +call writememorybyte +inc edx +mov [ebp+__areg+20],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1AFA +LAFA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+20] +call writememorybyte +inc edx +mov [ebp+__areg+20],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1AFB +LAFB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+20] +call writememorybyte +inc edx +mov [ebp+__areg+20],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1AFC +LAFC: +mov cx,[esi] +add esi,byte 2 +mov edx,[ebp+__areg+20] +call writememorybyte +inc edx +mov [ebp+__areg+20],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1B00 - 1B07 +LB00: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+20] +dec edx +call writememorybyte +mov [ebp+__areg+20],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1B08 - 1B0F +LB08: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+20] +dec edx +call writememorybyte +mov [ebp+__areg+20],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1B10 - 1B17 +LB10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+20] +dec edx +call writememorybyte +mov [ebp+__areg+20],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1B18 - 1B1F +LB18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+20] +dec edx +call writememorybyte +mov [ebp+__areg+20],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1B20 - 1B27 +LB20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+20] +dec edx +call writememorybyte +mov [ebp+__areg+20],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1B28 - 1B2F +LB28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+20] +dec edx +call writememorybyte +mov [ebp+__areg+20],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1B30 - 1B37 +LB30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+20] +dec edx +call writememorybyte +mov [ebp+__areg+20],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1B38 +LB38: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+20] +dec edx +call writememorybyte +mov [ebp+__areg+20],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1B39 +LB39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +mov edx,[ebp+__areg+20] +dec edx +call writememorybyte +mov [ebp+__areg+20],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1B3A +LB3A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+20] +dec edx +call writememorybyte +mov [ebp+__areg+20],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1B3B +LB3B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+20] +dec edx +call writememorybyte +mov [ebp+__areg+20],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1B3C +LB3C: +mov cx,[esi] +add esi,byte 2 +mov edx,[ebp+__areg+20] +dec edx +call writememorybyte +mov [ebp+__areg+20],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1B40 - 1B47 +LB40: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+20] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1B48 - 1B4F +LB48: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+20] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1B50 - 1B57 +LB50: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+20] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1B58 - 1B5F +LB58: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+20] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1B60 - 1B67 +LB60: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+20] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1B68 - 1B6F +LB68: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+20] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1B70 - 1B77 +LB70: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+20] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1B78 +LB78: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+20] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1B79 +LB79: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+20] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1B7A +LB7A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+20] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1B7B +LB7B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+20] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1B7C +LB7C: +mov cx,[esi] +add esi,byte 2 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+20] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1B80 - 1B87 +LB80: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +call decode_ext +add edx,[ebp+__areg+20] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1B88 - 1B8F +LB88: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +call decode_ext +add edx,[ebp+__areg+20] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1B90 - 1B97 +LB90: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +call decode_ext +add edx,[ebp+__areg+20] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1B98 - 1B9F +LB98: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +call decode_ext +add edx,[ebp+__areg+20] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1BA0 - 1BA7 +LBA0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +call decode_ext +add edx,[ebp+__areg+20] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1BA8 - 1BAF +LBA8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +call decode_ext +add edx,[ebp+__areg+20] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1BB0 - 1BB7 +LBB0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +call decode_ext +add edx,[ebp+__areg+20] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1BB8 +LBB8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +call decode_ext +add edx,[ebp+__areg+20] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1BB9 +LBB9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +call decode_ext +add edx,[ebp+__areg+20] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1BBA +LBBA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +call decode_ext +add edx,[ebp+__areg+20] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1BBB +LBBB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +call decode_ext +add edx,[ebp+__areg+20] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1BBC +LBBC: +mov cx,[esi] +add esi,byte 2 +call decode_ext +add edx,[ebp+__areg+20] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1C00 - 1C07 +LC00: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+24],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1C08 - 1C0F +LC08: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov [ebp+__dreg+24],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1C10 - 1C17 +LC10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov [ebp+__dreg+24],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1C18 - 1C1F +LC18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +mov [ebp+__dreg+24],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1C20 - 1C27 +LC20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov [ebp+__dreg+24],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1C28 - 1C2F +LC28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov [ebp+__dreg+24],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1C30 - 1C37 +LC30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov [ebp+__dreg+24],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1C38 +LC38: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +mov [ebp+__dreg+24],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1C39 +LC39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +mov [ebp+__dreg+24],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1C3A +LC3A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +mov [ebp+__dreg+24],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1C3B +LC3B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +mov [ebp+__dreg+24],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1C3C +LC3C: +mov cx,[esi] +add esi,byte 2 +mov [ebp+__dreg+24],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1C80 - 1C87 +LC80: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+24] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1C88 - 1C8F +LC88: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+24] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1C90 - 1C97 +LC90: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+24] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1C98 - 1C9F +LC98: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+24] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1CA0 - 1CA7 +LCA0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+24] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1CA8 - 1CAF +LCA8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+24] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1CB0 - 1CB7 +LCB0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+24] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1CB8 +LCB8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+24] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1CB9 +LCB9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +mov edx,[ebp+__areg+24] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1CBA +LCBA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+24] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1CBB +LCBB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+24] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1CBC +LCBC: +mov cx,[esi] +add esi,byte 2 +mov edx,[ebp+__areg+24] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1CC0 - 1CC7 +LCC0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+24] +call writememorybyte +inc edx +mov [ebp+__areg+24],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1CC8 - 1CCF +LCC8: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+24] +call writememorybyte +inc edx +mov [ebp+__areg+24],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1CD0 - 1CD7 +LCD0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+24] +call writememorybyte +inc edx +mov [ebp+__areg+24],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1CD8 - 1CDF +LCD8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+24] +call writememorybyte +inc edx +mov [ebp+__areg+24],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1CE0 - 1CE7 +LCE0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+24] +call writememorybyte +inc edx +mov [ebp+__areg+24],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1CE8 - 1CEF +LCE8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+24] +call writememorybyte +inc edx +mov [ebp+__areg+24],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1CF0 - 1CF7 +LCF0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+24] +call writememorybyte +inc edx +mov [ebp+__areg+24],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1CF8 +LCF8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+24] +call writememorybyte +inc edx +mov [ebp+__areg+24],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1CF9 +LCF9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +mov edx,[ebp+__areg+24] +call writememorybyte +inc edx +mov [ebp+__areg+24],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1CFA +LCFA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+24] +call writememorybyte +inc edx +mov [ebp+__areg+24],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1CFB +LCFB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+24] +call writememorybyte +inc edx +mov [ebp+__areg+24],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1CFC +LCFC: +mov cx,[esi] +add esi,byte 2 +mov edx,[ebp+__areg+24] +call writememorybyte +inc edx +mov [ebp+__areg+24],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1D00 - 1D07 +LD00: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+24] +dec edx +call writememorybyte +mov [ebp+__areg+24],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1D08 - 1D0F +LD08: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+24] +dec edx +call writememorybyte +mov [ebp+__areg+24],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1D10 - 1D17 +LD10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+24] +dec edx +call writememorybyte +mov [ebp+__areg+24],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1D18 - 1D1F +LD18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+24] +dec edx +call writememorybyte +mov [ebp+__areg+24],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1D20 - 1D27 +LD20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+24] +dec edx +call writememorybyte +mov [ebp+__areg+24],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1D28 - 1D2F +LD28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+24] +dec edx +call writememorybyte +mov [ebp+__areg+24],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1D30 - 1D37 +LD30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+24] +dec edx +call writememorybyte +mov [ebp+__areg+24],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1D38 +LD38: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+24] +dec edx +call writememorybyte +mov [ebp+__areg+24],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1D39 +LD39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +mov edx,[ebp+__areg+24] +dec edx +call writememorybyte +mov [ebp+__areg+24],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1D3A +LD3A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+24] +dec edx +call writememorybyte +mov [ebp+__areg+24],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1D3B +LD3B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+24] +dec edx +call writememorybyte +mov [ebp+__areg+24],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1D3C +LD3C: +mov cx,[esi] +add esi,byte 2 +mov edx,[ebp+__areg+24] +dec edx +call writememorybyte +mov [ebp+__areg+24],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1D40 - 1D47 +LD40: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+24] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1D48 - 1D4F +LD48: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+24] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1D50 - 1D57 +LD50: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+24] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1D58 - 1D5F +LD58: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+24] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1D60 - 1D67 +LD60: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+24] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1D68 - 1D6F +LD68: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+24] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1D70 - 1D77 +LD70: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+24] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1D78 +LD78: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+24] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1D79 +LD79: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+24] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1D7A +LD7A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+24] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1D7B +LD7B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+24] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1D7C +LD7C: +mov cx,[esi] +add esi,byte 2 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+24] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1D80 - 1D87 +LD80: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +call decode_ext +add edx,[ebp+__areg+24] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1D88 - 1D8F +LD88: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +call decode_ext +add edx,[ebp+__areg+24] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1D90 - 1D97 +LD90: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +call decode_ext +add edx,[ebp+__areg+24] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1D98 - 1D9F +LD98: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +call decode_ext +add edx,[ebp+__areg+24] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1DA0 - 1DA7 +LDA0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +call decode_ext +add edx,[ebp+__areg+24] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1DA8 - 1DAF +LDA8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +call decode_ext +add edx,[ebp+__areg+24] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1DB0 - 1DB7 +LDB0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +call decode_ext +add edx,[ebp+__areg+24] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1DB8 +LDB8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +call decode_ext +add edx,[ebp+__areg+24] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1DB9 +LDB9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +call decode_ext +add edx,[ebp+__areg+24] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1DBA +LDBA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +call decode_ext +add edx,[ebp+__areg+24] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1DBB +LDBB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +call decode_ext +add edx,[ebp+__areg+24] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1DBC +LDBC: +mov cx,[esi] +add esi,byte 2 +call decode_ext +add edx,[ebp+__areg+24] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1E00 - 1E07 +LE00: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+28],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1E08 - 1E0F +LE08: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov [ebp+__dreg+28],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1E10 - 1E17 +LE10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov [ebp+__dreg+28],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1E18 - 1E1F +LE18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +mov [ebp+__dreg+28],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1E20 - 1E27 +LE20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov [ebp+__dreg+28],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1E28 - 1E2F +LE28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov [ebp+__dreg+28],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1E30 - 1E37 +LE30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov [ebp+__dreg+28],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1E38 +LE38: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +mov [ebp+__dreg+28],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1E39 +LE39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +mov [ebp+__dreg+28],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1E3A +LE3A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +mov [ebp+__dreg+28],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1E3B +LE3B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +mov [ebp+__dreg+28],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1E3C +LE3C: +mov cx,[esi] +add esi,byte 2 +mov [ebp+__dreg+28],cl +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1E80 - 1E87 +LE80: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+28] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1E88 - 1E8F +LE88: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+28] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1E90 - 1E97 +LE90: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+28] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1E98 - 1E9F +LE98: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+28] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1EA0 - 1EA7 +LEA0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+28] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1EA8 - 1EAF +LEA8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+28] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1EB0 - 1EB7 +LEB0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+28] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1EB8 +LEB8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+28] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1EB9 +LEB9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +mov edx,[ebp+__areg+28] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1EBA +LEBA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+28] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1EBB +LEBB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+28] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1EBC +LEBC: +mov cx,[esi] +add esi,byte 2 +mov edx,[ebp+__areg+28] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1EC0 - 1EC7 +LEC0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+28] +call writememorybyte +add edx,byte 2 +mov [ebp+__areg+28],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1EC8 - 1ECF +LEC8: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+28] +call writememorybyte +add edx,byte 2 +mov [ebp+__areg+28],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1ED0 - 1ED7 +LED0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+28] +call writememorybyte +add edx,byte 2 +mov [ebp+__areg+28],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1ED8 - 1EDF +LED8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+28] +call writememorybyte +add edx,byte 2 +mov [ebp+__areg+28],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1EE0 - 1EE7 +LEE0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+28] +call writememorybyte +add edx,byte 2 +mov [ebp+__areg+28],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1EE8 - 1EEF +LEE8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+28] +call writememorybyte +add edx,byte 2 +mov [ebp+__areg+28],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1EF0 - 1EF7 +LEF0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+28] +call writememorybyte +add edx,byte 2 +mov [ebp+__areg+28],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1EF8 +LEF8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+28] +call writememorybyte +add edx,byte 2 +mov [ebp+__areg+28],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1EF9 +LEF9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +mov edx,[ebp+__areg+28] +call writememorybyte +add edx,byte 2 +mov [ebp+__areg+28],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1EFA +LEFA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+28] +call writememorybyte +add edx,byte 2 +mov [ebp+__areg+28],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1EFB +LEFB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+28] +call writememorybyte +add edx,byte 2 +mov [ebp+__areg+28],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1EFC +LEFC: +mov cx,[esi] +add esi,byte 2 +mov edx,[ebp+__areg+28] +call writememorybyte +add edx,byte 2 +mov [ebp+__areg+28],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1F00 - 1F07 +LF00: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+28] +sub edx,byte 2 +call writememorybyte +mov [ebp+__areg+28],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1F08 - 1F0F +LF08: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+28] +sub edx,byte 2 +call writememorybyte +mov [ebp+__areg+28],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1F10 - 1F17 +LF10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+28] +sub edx,byte 2 +call writememorybyte +mov [ebp+__areg+28],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1F18 - 1F1F +LF18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+28] +sub edx,byte 2 +call writememorybyte +mov [ebp+__areg+28],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1F20 - 1F27 +LF20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+28] +sub edx,byte 2 +call writememorybyte +mov [ebp+__areg+28],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1F28 - 1F2F +LF28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+28] +sub edx,byte 2 +call writememorybyte +mov [ebp+__areg+28],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1F30 - 1F37 +LF30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov edx,[ebp+__areg+28] +sub edx,byte 2 +call writememorybyte +mov [ebp+__areg+28],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1F38 +LF38: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+28] +sub edx,byte 2 +call writememorybyte +mov [ebp+__areg+28],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1F39 +LF39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +mov edx,[ebp+__areg+28] +sub edx,byte 2 +call writememorybyte +mov [ebp+__areg+28],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1F3A +LF3A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+28] +sub edx,byte 2 +call writememorybyte +mov [ebp+__areg+28],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1F3B +LF3B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +mov edx,[ebp+__areg+28] +sub edx,byte 2 +call writememorybyte +mov [ebp+__areg+28],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1F3C +LF3C: +mov cx,[esi] +add esi,byte 2 +mov edx,[ebp+__areg+28] +sub edx,byte 2 +call writememorybyte +mov [ebp+__areg+28],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1F40 - 1F47 +LF40: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+28] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1F48 - 1F4F +LF48: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+28] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1F50 - 1F57 +LF50: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+28] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1F58 - 1F5F +LF58: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+28] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1F60 - 1F67 +LF60: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+28] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1F68 - 1F6F +LF68: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+28] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1F70 - 1F77 +LF70: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+28] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1F78 +LF78: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+28] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1F79 +LF79: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+28] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1F7A +LF7A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+28] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1F7B +LF7B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+28] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1F7C +LF7C: +mov cx,[esi] +add esi,byte 2 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+28] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1F80 - 1F87 +LF80: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +call decode_ext +add edx,[ebp+__areg+28] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1F88 - 1F8F +LF88: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +call decode_ext +add edx,[ebp+__areg+28] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1F90 - 1F97 +LF90: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +call decode_ext +add edx,[ebp+__areg+28] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1F98 - 1F9F +LF98: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +call decode_ext +add edx,[ebp+__areg+28] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1FA0 - 1FA7 +LFA0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +call decode_ext +add edx,[ebp+__areg+28] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1FA8 - 1FAF +LFA8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +call decode_ext +add edx,[ebp+__areg+28] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 1FB0 - 1FB7 +LFB0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +call decode_ext +add edx,[ebp+__areg+28] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1FB8 +LFB8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +call decode_ext +add edx,[ebp+__areg+28] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1FB9 +LFB9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +call decode_ext +add edx,[ebp+__areg+28] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1FBA +LFBA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +call decode_ext +add edx,[ebp+__areg+28] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1FBB +LFBB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +call decode_ext +add edx,[ebp+__areg+28] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 1FBC +LFBC: +mov cx,[esi] +add esi,byte 2 +call decode_ext +add edx,[ebp+__areg+28] +call writememorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2000 - 2007 +M000: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+0],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2008 - 200F +M008: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov [ebp+__dreg+0],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2010 - 2017 +M010: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +mov [ebp+__dreg+0],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2018 - 201F +M018: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +mov [ebp+__dreg+0],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2020 - 2027 +M020: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +mov [ebp+__dreg+0],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2028 - 202F +M028: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov [ebp+__dreg+0],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2030 - 2037 +M030: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov [ebp+__dreg+0],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2038 +M038: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +mov [ebp+__dreg+0],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2039 +M039: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +mov [ebp+__dreg+0],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 203A +M03A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +mov [ebp+__dreg+0],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 203B +M03B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +mov [ebp+__dreg+0],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 203C +M03C: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +mov [ebp+__dreg+0],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2040 - 2047 +M040: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov [ebp+__areg+0],ecx +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2048 - 204F +M048: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov [ebp+__areg+0],ecx +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2050 - 2057 +M050: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +mov [ebp+__areg+0],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2058 - 205F +M058: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +mov [ebp+__areg+0],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2060 - 2067 +M060: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +mov [ebp+__areg+0],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2068 - 206F +M068: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov [ebp+__areg+0],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2070 - 2077 +M070: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov [ebp+__areg+0],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2078 +M078: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +mov [ebp+__areg+0],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2079 +M079: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +mov [ebp+__areg+0],ecx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 207A +M07A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +mov [ebp+__areg+0],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 207B +M07B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +mov [ebp+__areg+0],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 207C +M07C: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +mov [ebp+__areg+0],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2080 - 2087 +M080: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+0] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2088 - 208F +M088: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+0] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2090 - 2097 +M090: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+0] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2098 - 209F +M098: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+0] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 20A0 - 20A7 +M0A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+0] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 20A8 - 20AF +M0A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+0] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 20B0 - 20B7 +M0B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+0] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 20B8 +M0B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +mov edx,[ebp+__areg+0] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 20B9 +M0B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +mov edx,[ebp+__areg+0] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 20BA +M0BA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +mov edx,[ebp+__areg+0] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 20BB +M0BB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +mov edx,[ebp+__areg+0] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 20BC +M0BC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +mov edx,[ebp+__areg+0] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 20C0 - 20C7 +M0C0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+0] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+0],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 20C8 - 20CF +M0C8: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+0] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+0],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 20D0 - 20D7 +M0D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+0] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+0],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 20D8 - 20DF +M0D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+0] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+0],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 20E0 - 20E7 +M0E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+0] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+0],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 20E8 - 20EF +M0E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+0] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+0],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 20F0 - 20F7 +M0F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+0] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+0],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 20F8 +M0F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +mov edx,[ebp+__areg+0] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+0],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 20F9 +M0F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +mov edx,[ebp+__areg+0] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+0],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 20FA +M0FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +mov edx,[ebp+__areg+0] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+0],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 20FB +M0FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +mov edx,[ebp+__areg+0] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+0],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 20FC +M0FC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +mov edx,[ebp+__areg+0] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+0],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2100 - 2107 +M100: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+0] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+0],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2108 - 210F +M108: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+0] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+0],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2110 - 2117 +M110: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+0] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+0],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2118 - 211F +M118: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+0] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+0],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2120 - 2127 +M120: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+0] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+0],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2128 - 212F +M128: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+0] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+0],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2130 - 2137 +M130: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+0] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+0],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2138 +M138: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +mov edx,[ebp+__areg+0] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+0],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2139 +M139: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +mov edx,[ebp+__areg+0] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+0],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 213A +M13A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +mov edx,[ebp+__areg+0] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+0],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 213B +M13B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +mov edx,[ebp+__areg+0] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+0],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 213C +M13C: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +mov edx,[ebp+__areg+0] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+0],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2140 - 2147 +M140: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+0] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2148 - 214F +M148: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+0] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2150 - 2157 +M150: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+0] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2158 - 215F +M158: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+0] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2160 - 2167 +M160: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+0] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2168 - 216F +M168: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+0] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2170 - 2177 +M170: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+0] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2178 +M178: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+0] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2179 +M179: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+0] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 32 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 217A +M17A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+0] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 217B +M17B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+0] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 217C +M17C: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+0] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2180 - 2187 +M180: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +call decode_ext +add edx,[ebp+__areg+0] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2188 - 218F +M188: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +call decode_ext +add edx,[ebp+__areg+0] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2190 - 2197 +M190: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +call decode_ext +add edx,[ebp+__areg+0] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2198 - 219F +M198: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +call decode_ext +add edx,[ebp+__areg+0] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 21A0 - 21A7 +M1A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +call decode_ext +add edx,[ebp+__areg+0] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 21A8 - 21AF +M1A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +call decode_ext +add edx,[ebp+__areg+0] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 21B0 - 21B7 +M1B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +call decode_ext +add edx,[ebp+__areg+0] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 32 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 21B8 +M1B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +call decode_ext +add edx,[ebp+__areg+0] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 21B9 +M1B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +call decode_ext +add edx,[ebp+__areg+0] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 34 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 21BA +M1BA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +call decode_ext +add edx,[ebp+__areg+0] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 21BB +M1BB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +call decode_ext +add edx,[ebp+__areg+0] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 32 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 21BC +M1BC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +call decode_ext +add edx,[ebp+__areg+0] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 21C0 - 21C7 +M1C0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +movsx edx,word[esi] +add esi,byte 2 +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 21C8 - 21CF +M1C8: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +movsx edx,word[esi] +add esi,byte 2 +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 21D0 - 21D7 +M1D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 21D8 - 21DF +M1D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +movsx edx,word[esi] +add esi,byte 2 +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 21E0 - 21E7 +M1E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +movsx edx,word[esi] +add esi,byte 2 +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 21E8 - 21EF +M1E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 21F0 - 21F7 +M1F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 21F8 +M1F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 21F9 +M1F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 32 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 21FA +M1FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 21FB +M1FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 21FC +M1FC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +movsx edx,word[esi] +add esi,byte 2 +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2200 - 2207 +M200: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+4],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2208 - 220F +M208: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov [ebp+__dreg+4],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2210 - 2217 +M210: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +mov [ebp+__dreg+4],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2218 - 221F +M218: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +mov [ebp+__dreg+4],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2220 - 2227 +M220: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +mov [ebp+__dreg+4],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2228 - 222F +M228: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov [ebp+__dreg+4],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2230 - 2237 +M230: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov [ebp+__dreg+4],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2238 +M238: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +mov [ebp+__dreg+4],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2239 +M239: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +mov [ebp+__dreg+4],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 223A +M23A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +mov [ebp+__dreg+4],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 223B +M23B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +mov [ebp+__dreg+4],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 223C +M23C: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +mov [ebp+__dreg+4],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2240 - 2247 +M240: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov [ebp+__areg+4],ecx +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2248 - 224F +M248: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov [ebp+__areg+4],ecx +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2250 - 2257 +M250: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +mov [ebp+__areg+4],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2258 - 225F +M258: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +mov [ebp+__areg+4],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2260 - 2267 +M260: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +mov [ebp+__areg+4],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2268 - 226F +M268: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov [ebp+__areg+4],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2270 - 2277 +M270: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov [ebp+__areg+4],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2278 +M278: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +mov [ebp+__areg+4],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2279 +M279: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +mov [ebp+__areg+4],ecx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 227A +M27A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +mov [ebp+__areg+4],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 227B +M27B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +mov [ebp+__areg+4],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 227C +M27C: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +mov [ebp+__areg+4],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2280 - 2287 +M280: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+4] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2288 - 228F +M288: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+4] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2290 - 2297 +M290: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+4] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2298 - 229F +M298: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+4] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 22A0 - 22A7 +M2A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+4] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 22A8 - 22AF +M2A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+4] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 22B0 - 22B7 +M2B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+4] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 22B8 +M2B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +mov edx,[ebp+__areg+4] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 22B9 +M2B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +mov edx,[ebp+__areg+4] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 22BA +M2BA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +mov edx,[ebp+__areg+4] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 22BB +M2BB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +mov edx,[ebp+__areg+4] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 22BC +M2BC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +mov edx,[ebp+__areg+4] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 22C0 - 22C7 +M2C0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+4] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+4],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 22C8 - 22CF +M2C8: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+4] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+4],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 22D0 - 22D7 +M2D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+4] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+4],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 22D8 - 22DF +M2D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+4] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+4],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 22E0 - 22E7 +M2E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+4] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+4],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 22E8 - 22EF +M2E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+4] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+4],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 22F0 - 22F7 +M2F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+4] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+4],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 22F8 +M2F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +mov edx,[ebp+__areg+4] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+4],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 22F9 +M2F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +mov edx,[ebp+__areg+4] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+4],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 22FA +M2FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +mov edx,[ebp+__areg+4] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+4],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 22FB +M2FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +mov edx,[ebp+__areg+4] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+4],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 22FC +M2FC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +mov edx,[ebp+__areg+4] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+4],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2300 - 2307 +M300: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+4] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+4],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2308 - 230F +M308: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+4] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+4],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2310 - 2317 +M310: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+4] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+4],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2318 - 231F +M318: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+4] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+4],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2320 - 2327 +M320: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+4] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+4],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2328 - 232F +M328: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+4] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+4],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2330 - 2337 +M330: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+4] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+4],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2338 +M338: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +mov edx,[ebp+__areg+4] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+4],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2339 +M339: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +mov edx,[ebp+__areg+4] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+4],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 233A +M33A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +mov edx,[ebp+__areg+4] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+4],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 233B +M33B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +mov edx,[ebp+__areg+4] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+4],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 233C +M33C: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +mov edx,[ebp+__areg+4] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+4],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2340 - 2347 +M340: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+4] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2348 - 234F +M348: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+4] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2350 - 2357 +M350: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+4] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2358 - 235F +M358: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+4] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2360 - 2367 +M360: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+4] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2368 - 236F +M368: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+4] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2370 - 2377 +M370: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+4] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2378 +M378: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+4] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2379 +M379: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+4] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 32 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 237A +M37A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+4] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 237B +M37B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+4] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 237C +M37C: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+4] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2380 - 2387 +M380: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +call decode_ext +add edx,[ebp+__areg+4] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2388 - 238F +M388: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +call decode_ext +add edx,[ebp+__areg+4] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2390 - 2397 +M390: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +call decode_ext +add edx,[ebp+__areg+4] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2398 - 239F +M398: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +call decode_ext +add edx,[ebp+__areg+4] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 23A0 - 23A7 +M3A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +call decode_ext +add edx,[ebp+__areg+4] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 23A8 - 23AF +M3A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +call decode_ext +add edx,[ebp+__areg+4] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 23B0 - 23B7 +M3B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +call decode_ext +add edx,[ebp+__areg+4] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 32 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 23B8 +M3B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +call decode_ext +add edx,[ebp+__areg+4] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 23B9 +M3B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +call decode_ext +add edx,[ebp+__areg+4] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 34 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 23BA +M3BA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +call decode_ext +add edx,[ebp+__areg+4] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 23BB +M3BB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +call decode_ext +add edx,[ebp+__areg+4] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 32 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 23BC +M3BC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +call decode_ext +add edx,[ebp+__areg+4] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 23C0 - 23C7 +M3C0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 23C8 - 23CF +M3C8: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 23D0 - 23D7 +M3D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 23D8 - 23DF +M3D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 23E0 - 23E7 +M3E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 23E8 - 23EF +M3E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 32 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 23F0 - 23F7 +M3F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 34 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 23F8 +M3F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 32 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 23F9 +M3F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 36 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 23FA +M3FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 32 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 23FB +M3FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 34 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 23FC +M3FC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2400 - 2407 +M400: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+8],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2408 - 240F +M408: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov [ebp+__dreg+8],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2410 - 2417 +M410: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +mov [ebp+__dreg+8],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2418 - 241F +M418: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +mov [ebp+__dreg+8],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2420 - 2427 +M420: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +mov [ebp+__dreg+8],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2428 - 242F +M428: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov [ebp+__dreg+8],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2430 - 2437 +M430: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov [ebp+__dreg+8],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2438 +M438: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +mov [ebp+__dreg+8],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2439 +M439: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +mov [ebp+__dreg+8],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 243A +M43A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +mov [ebp+__dreg+8],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 243B +M43B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +mov [ebp+__dreg+8],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 243C +M43C: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +mov [ebp+__dreg+8],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2440 - 2447 +M440: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov [ebp+__areg+8],ecx +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2448 - 244F +M448: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov [ebp+__areg+8],ecx +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2450 - 2457 +M450: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +mov [ebp+__areg+8],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2458 - 245F +M458: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +mov [ebp+__areg+8],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2460 - 2467 +M460: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +mov [ebp+__areg+8],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2468 - 246F +M468: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov [ebp+__areg+8],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2470 - 2477 +M470: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov [ebp+__areg+8],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2478 +M478: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +mov [ebp+__areg+8],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2479 +M479: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +mov [ebp+__areg+8],ecx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 247A +M47A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +mov [ebp+__areg+8],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 247B +M47B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +mov [ebp+__areg+8],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 247C +M47C: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +mov [ebp+__areg+8],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2480 - 2487 +M480: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+8] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2488 - 248F +M488: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+8] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2490 - 2497 +M490: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+8] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2498 - 249F +M498: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+8] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 24A0 - 24A7 +M4A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+8] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 24A8 - 24AF +M4A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+8] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 24B0 - 24B7 +M4B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+8] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 24B8 +M4B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +mov edx,[ebp+__areg+8] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 24B9 +M4B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +mov edx,[ebp+__areg+8] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 24BA +M4BA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +mov edx,[ebp+__areg+8] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 24BB +M4BB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +mov edx,[ebp+__areg+8] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 24BC +M4BC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +mov edx,[ebp+__areg+8] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 24C0 - 24C7 +M4C0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+8] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+8],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 24C8 - 24CF +M4C8: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+8] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+8],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 24D0 - 24D7 +M4D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+8] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+8],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 24D8 - 24DF +M4D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+8] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+8],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 24E0 - 24E7 +M4E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+8] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+8],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 24E8 - 24EF +M4E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+8] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+8],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 24F0 - 24F7 +M4F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+8] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+8],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 24F8 +M4F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +mov edx,[ebp+__areg+8] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+8],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 24F9 +M4F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +mov edx,[ebp+__areg+8] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+8],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 24FA +M4FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +mov edx,[ebp+__areg+8] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+8],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 24FB +M4FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +mov edx,[ebp+__areg+8] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+8],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 24FC +M4FC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +mov edx,[ebp+__areg+8] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+8],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2500 - 2507 +M500: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+8] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+8],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2508 - 250F +M508: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+8] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+8],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2510 - 2517 +M510: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+8] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+8],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2518 - 251F +M518: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+8] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+8],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2520 - 2527 +M520: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+8] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+8],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2528 - 252F +M528: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+8] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+8],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2530 - 2537 +M530: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+8] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+8],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2538 +M538: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +mov edx,[ebp+__areg+8] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+8],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2539 +M539: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +mov edx,[ebp+__areg+8] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+8],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 253A +M53A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +mov edx,[ebp+__areg+8] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+8],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 253B +M53B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +mov edx,[ebp+__areg+8] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+8],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 253C +M53C: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +mov edx,[ebp+__areg+8] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+8],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2540 - 2547 +M540: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+8] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2548 - 254F +M548: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+8] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2550 - 2557 +M550: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+8] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2558 - 255F +M558: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+8] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2560 - 2567 +M560: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+8] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2568 - 256F +M568: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+8] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2570 - 2577 +M570: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+8] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2578 +M578: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+8] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2579 +M579: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+8] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 32 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 257A +M57A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+8] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 257B +M57B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+8] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 257C +M57C: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+8] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2580 - 2587 +M580: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +call decode_ext +add edx,[ebp+__areg+8] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2588 - 258F +M588: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +call decode_ext +add edx,[ebp+__areg+8] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2590 - 2597 +M590: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +call decode_ext +add edx,[ebp+__areg+8] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2598 - 259F +M598: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +call decode_ext +add edx,[ebp+__areg+8] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 25A0 - 25A7 +M5A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +call decode_ext +add edx,[ebp+__areg+8] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 25A8 - 25AF +M5A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +call decode_ext +add edx,[ebp+__areg+8] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 25B0 - 25B7 +M5B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +call decode_ext +add edx,[ebp+__areg+8] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 32 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 25B8 +M5B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +call decode_ext +add edx,[ebp+__areg+8] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 25B9 +M5B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +call decode_ext +add edx,[ebp+__areg+8] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 34 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 25BA +M5BA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +call decode_ext +add edx,[ebp+__areg+8] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 25BB +M5BB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +call decode_ext +add edx,[ebp+__areg+8] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 32 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 25BC +M5BC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +call decode_ext +add edx,[ebp+__areg+8] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2600 - 2607 +M600: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+12],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2608 - 260F +M608: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov [ebp+__dreg+12],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2610 - 2617 +M610: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +mov [ebp+__dreg+12],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2618 - 261F +M618: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +mov [ebp+__dreg+12],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2620 - 2627 +M620: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +mov [ebp+__dreg+12],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2628 - 262F +M628: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov [ebp+__dreg+12],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2630 - 2637 +M630: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov [ebp+__dreg+12],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2638 +M638: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +mov [ebp+__dreg+12],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2639 +M639: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +mov [ebp+__dreg+12],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 263A +M63A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +mov [ebp+__dreg+12],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 263B +M63B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +mov [ebp+__dreg+12],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 263C +M63C: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +mov [ebp+__dreg+12],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2640 - 2647 +M640: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov [ebp+__areg+12],ecx +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2648 - 264F +M648: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov [ebp+__areg+12],ecx +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2650 - 2657 +M650: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +mov [ebp+__areg+12],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2658 - 265F +M658: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +mov [ebp+__areg+12],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2660 - 2667 +M660: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +mov [ebp+__areg+12],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2668 - 266F +M668: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov [ebp+__areg+12],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2670 - 2677 +M670: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov [ebp+__areg+12],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2678 +M678: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +mov [ebp+__areg+12],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2679 +M679: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +mov [ebp+__areg+12],ecx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 267A +M67A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +mov [ebp+__areg+12],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 267B +M67B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +mov [ebp+__areg+12],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 267C +M67C: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +mov [ebp+__areg+12],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2680 - 2687 +M680: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+12] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2688 - 268F +M688: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+12] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2690 - 2697 +M690: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+12] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2698 - 269F +M698: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+12] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 26A0 - 26A7 +M6A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+12] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 26A8 - 26AF +M6A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+12] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 26B0 - 26B7 +M6B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+12] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 26B8 +M6B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +mov edx,[ebp+__areg+12] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 26B9 +M6B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +mov edx,[ebp+__areg+12] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 26BA +M6BA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +mov edx,[ebp+__areg+12] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 26BB +M6BB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +mov edx,[ebp+__areg+12] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 26BC +M6BC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +mov edx,[ebp+__areg+12] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 26C0 - 26C7 +M6C0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+12] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+12],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 26C8 - 26CF +M6C8: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+12] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+12],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 26D0 - 26D7 +M6D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+12] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+12],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 26D8 - 26DF +M6D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+12] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+12],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 26E0 - 26E7 +M6E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+12] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+12],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 26E8 - 26EF +M6E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+12] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+12],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 26F0 - 26F7 +M6F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+12] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+12],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 26F8 +M6F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +mov edx,[ebp+__areg+12] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+12],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 26F9 +M6F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +mov edx,[ebp+__areg+12] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+12],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 26FA +M6FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +mov edx,[ebp+__areg+12] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+12],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 26FB +M6FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +mov edx,[ebp+__areg+12] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+12],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 26FC +M6FC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +mov edx,[ebp+__areg+12] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+12],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2700 - 2707 +M700: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+12] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+12],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2708 - 270F +M708: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+12] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+12],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2710 - 2717 +M710: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+12] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+12],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2718 - 271F +M718: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+12] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+12],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2720 - 2727 +M720: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+12] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+12],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2728 - 272F +M728: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+12] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+12],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2730 - 2737 +M730: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+12] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+12],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2738 +M738: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +mov edx,[ebp+__areg+12] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+12],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2739 +M739: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +mov edx,[ebp+__areg+12] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+12],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 273A +M73A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +mov edx,[ebp+__areg+12] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+12],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 273B +M73B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +mov edx,[ebp+__areg+12] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+12],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 273C +M73C: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +mov edx,[ebp+__areg+12] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+12],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2740 - 2747 +M740: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+12] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2748 - 274F +M748: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+12] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2750 - 2757 +M750: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+12] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2758 - 275F +M758: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+12] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2760 - 2767 +M760: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+12] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2768 - 276F +M768: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+12] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2770 - 2777 +M770: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+12] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2778 +M778: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+12] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2779 +M779: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+12] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 32 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 277A +M77A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+12] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 277B +M77B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+12] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 277C +M77C: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+12] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2780 - 2787 +M780: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +call decode_ext +add edx,[ebp+__areg+12] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2788 - 278F +M788: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +call decode_ext +add edx,[ebp+__areg+12] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2790 - 2797 +M790: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +call decode_ext +add edx,[ebp+__areg+12] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2798 - 279F +M798: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +call decode_ext +add edx,[ebp+__areg+12] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 27A0 - 27A7 +M7A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +call decode_ext +add edx,[ebp+__areg+12] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 27A8 - 27AF +M7A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +call decode_ext +add edx,[ebp+__areg+12] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 27B0 - 27B7 +M7B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +call decode_ext +add edx,[ebp+__areg+12] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 32 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 27B8 +M7B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +call decode_ext +add edx,[ebp+__areg+12] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 27B9 +M7B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +call decode_ext +add edx,[ebp+__areg+12] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 34 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 27BA +M7BA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +call decode_ext +add edx,[ebp+__areg+12] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 27BB +M7BB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +call decode_ext +add edx,[ebp+__areg+12] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 32 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 27BC +M7BC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +call decode_ext +add edx,[ebp+__areg+12] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2800 - 2807 +M800: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+16],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2808 - 280F +M808: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov [ebp+__dreg+16],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2810 - 2817 +M810: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +mov [ebp+__dreg+16],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2818 - 281F +M818: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +mov [ebp+__dreg+16],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2820 - 2827 +M820: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +mov [ebp+__dreg+16],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2828 - 282F +M828: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov [ebp+__dreg+16],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2830 - 2837 +M830: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov [ebp+__dreg+16],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2838 +M838: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +mov [ebp+__dreg+16],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2839 +M839: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +mov [ebp+__dreg+16],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 283A +M83A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +mov [ebp+__dreg+16],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 283B +M83B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +mov [ebp+__dreg+16],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 283C +M83C: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +mov [ebp+__dreg+16],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2840 - 2847 +M840: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov [ebp+__areg+16],ecx +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2848 - 284F +M848: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov [ebp+__areg+16],ecx +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2850 - 2857 +M850: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +mov [ebp+__areg+16],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2858 - 285F +M858: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +mov [ebp+__areg+16],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2860 - 2867 +M860: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +mov [ebp+__areg+16],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2868 - 286F +M868: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov [ebp+__areg+16],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2870 - 2877 +M870: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov [ebp+__areg+16],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2878 +M878: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +mov [ebp+__areg+16],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2879 +M879: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +mov [ebp+__areg+16],ecx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 287A +M87A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +mov [ebp+__areg+16],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 287B +M87B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +mov [ebp+__areg+16],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 287C +M87C: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +mov [ebp+__areg+16],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2880 - 2887 +M880: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+16] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2888 - 288F +M888: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+16] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2890 - 2897 +M890: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+16] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2898 - 289F +M898: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+16] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 28A0 - 28A7 +M8A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+16] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 28A8 - 28AF +M8A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+16] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 28B0 - 28B7 +M8B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+16] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 28B8 +M8B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +mov edx,[ebp+__areg+16] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 28B9 +M8B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +mov edx,[ebp+__areg+16] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 28BA +M8BA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +mov edx,[ebp+__areg+16] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 28BB +M8BB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +mov edx,[ebp+__areg+16] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 28BC +M8BC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +mov edx,[ebp+__areg+16] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 28C0 - 28C7 +M8C0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+16] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+16],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 28C8 - 28CF +M8C8: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+16] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+16],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 28D0 - 28D7 +M8D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+16] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+16],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 28D8 - 28DF +M8D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+16] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+16],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 28E0 - 28E7 +M8E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+16] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+16],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 28E8 - 28EF +M8E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+16] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+16],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 28F0 - 28F7 +M8F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+16] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+16],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 28F8 +M8F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +mov edx,[ebp+__areg+16] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+16],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 28F9 +M8F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +mov edx,[ebp+__areg+16] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+16],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 28FA +M8FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +mov edx,[ebp+__areg+16] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+16],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 28FB +M8FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +mov edx,[ebp+__areg+16] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+16],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 28FC +M8FC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +mov edx,[ebp+__areg+16] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+16],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2900 - 2907 +M900: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+16] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+16],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2908 - 290F +M908: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+16] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+16],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2910 - 2917 +M910: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+16] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+16],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2918 - 291F +M918: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+16] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+16],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2920 - 2927 +M920: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+16] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+16],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2928 - 292F +M928: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+16] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+16],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2930 - 2937 +M930: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+16] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+16],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2938 +M938: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +mov edx,[ebp+__areg+16] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+16],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2939 +M939: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +mov edx,[ebp+__areg+16] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+16],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 293A +M93A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +mov edx,[ebp+__areg+16] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+16],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 293B +M93B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +mov edx,[ebp+__areg+16] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+16],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 293C +M93C: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +mov edx,[ebp+__areg+16] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+16],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2940 - 2947 +M940: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+16] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2948 - 294F +M948: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+16] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2950 - 2957 +M950: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+16] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2958 - 295F +M958: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+16] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2960 - 2967 +M960: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+16] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2968 - 296F +M968: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+16] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2970 - 2977 +M970: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+16] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2978 +M978: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+16] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2979 +M979: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+16] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 32 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 297A +M97A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+16] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 297B +M97B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+16] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 297C +M97C: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+16] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2980 - 2987 +M980: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +call decode_ext +add edx,[ebp+__areg+16] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2988 - 298F +M988: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +call decode_ext +add edx,[ebp+__areg+16] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2990 - 2997 +M990: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +call decode_ext +add edx,[ebp+__areg+16] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2998 - 299F +M998: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +call decode_ext +add edx,[ebp+__areg+16] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 29A0 - 29A7 +M9A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +call decode_ext +add edx,[ebp+__areg+16] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 29A8 - 29AF +M9A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +call decode_ext +add edx,[ebp+__areg+16] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 29B0 - 29B7 +M9B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +call decode_ext +add edx,[ebp+__areg+16] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 32 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 29B8 +M9B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +call decode_ext +add edx,[ebp+__areg+16] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 29B9 +M9B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +call decode_ext +add edx,[ebp+__areg+16] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 34 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 29BA +M9BA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +call decode_ext +add edx,[ebp+__areg+16] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 29BB +M9BB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +call decode_ext +add edx,[ebp+__areg+16] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 32 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 29BC +M9BC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +call decode_ext +add edx,[ebp+__areg+16] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2A00 - 2A07 +MA00: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+20],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2A08 - 2A0F +MA08: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov [ebp+__dreg+20],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2A10 - 2A17 +MA10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +mov [ebp+__dreg+20],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2A18 - 2A1F +MA18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +mov [ebp+__dreg+20],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2A20 - 2A27 +MA20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +mov [ebp+__dreg+20],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2A28 - 2A2F +MA28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov [ebp+__dreg+20],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2A30 - 2A37 +MA30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov [ebp+__dreg+20],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2A38 +MA38: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +mov [ebp+__dreg+20],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2A39 +MA39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +mov [ebp+__dreg+20],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2A3A +MA3A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +mov [ebp+__dreg+20],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2A3B +MA3B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +mov [ebp+__dreg+20],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2A3C +MA3C: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +mov [ebp+__dreg+20],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2A40 - 2A47 +MA40: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov [ebp+__areg+20],ecx +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2A48 - 2A4F +MA48: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov [ebp+__areg+20],ecx +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2A50 - 2A57 +MA50: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +mov [ebp+__areg+20],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2A58 - 2A5F +MA58: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +mov [ebp+__areg+20],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2A60 - 2A67 +MA60: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +mov [ebp+__areg+20],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2A68 - 2A6F +MA68: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov [ebp+__areg+20],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2A70 - 2A77 +MA70: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov [ebp+__areg+20],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2A78 +MA78: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +mov [ebp+__areg+20],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2A79 +MA79: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +mov [ebp+__areg+20],ecx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2A7A +MA7A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +mov [ebp+__areg+20],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2A7B +MA7B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +mov [ebp+__areg+20],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2A7C +MA7C: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +mov [ebp+__areg+20],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2A80 - 2A87 +MA80: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+20] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2A88 - 2A8F +MA88: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+20] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2A90 - 2A97 +MA90: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+20] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2A98 - 2A9F +MA98: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+20] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2AA0 - 2AA7 +MAA0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+20] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2AA8 - 2AAF +MAA8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+20] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2AB0 - 2AB7 +MAB0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+20] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2AB8 +MAB8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +mov edx,[ebp+__areg+20] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2AB9 +MAB9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +mov edx,[ebp+__areg+20] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2ABA +MABA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +mov edx,[ebp+__areg+20] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2ABB +MABB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +mov edx,[ebp+__areg+20] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2ABC +MABC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +mov edx,[ebp+__areg+20] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2AC0 - 2AC7 +MAC0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+20] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+20],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2AC8 - 2ACF +MAC8: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+20] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+20],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2AD0 - 2AD7 +MAD0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+20] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+20],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2AD8 - 2ADF +MAD8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+20] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+20],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2AE0 - 2AE7 +MAE0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+20] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+20],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2AE8 - 2AEF +MAE8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+20] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+20],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2AF0 - 2AF7 +MAF0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+20] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+20],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2AF8 +MAF8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +mov edx,[ebp+__areg+20] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+20],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2AF9 +MAF9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +mov edx,[ebp+__areg+20] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+20],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2AFA +MAFA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +mov edx,[ebp+__areg+20] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+20],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2AFB +MAFB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +mov edx,[ebp+__areg+20] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+20],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2AFC +MAFC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +mov edx,[ebp+__areg+20] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+20],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2B00 - 2B07 +MB00: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+20] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+20],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2B08 - 2B0F +MB08: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+20] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+20],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2B10 - 2B17 +MB10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+20] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+20],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2B18 - 2B1F +MB18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+20] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+20],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2B20 - 2B27 +MB20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+20] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+20],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2B28 - 2B2F +MB28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+20] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+20],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2B30 - 2B37 +MB30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+20] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+20],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2B38 +MB38: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +mov edx,[ebp+__areg+20] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+20],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2B39 +MB39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +mov edx,[ebp+__areg+20] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+20],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2B3A +MB3A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +mov edx,[ebp+__areg+20] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+20],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2B3B +MB3B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +mov edx,[ebp+__areg+20] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+20],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2B3C +MB3C: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +mov edx,[ebp+__areg+20] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+20],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2B40 - 2B47 +MB40: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+20] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2B48 - 2B4F +MB48: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+20] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2B50 - 2B57 +MB50: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+20] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2B58 - 2B5F +MB58: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+20] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2B60 - 2B67 +MB60: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+20] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2B68 - 2B6F +MB68: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+20] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2B70 - 2B77 +MB70: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+20] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2B78 +MB78: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+20] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2B79 +MB79: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+20] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 32 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2B7A +MB7A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+20] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2B7B +MB7B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+20] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2B7C +MB7C: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+20] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2B80 - 2B87 +MB80: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +call decode_ext +add edx,[ebp+__areg+20] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2B88 - 2B8F +MB88: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +call decode_ext +add edx,[ebp+__areg+20] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2B90 - 2B97 +MB90: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +call decode_ext +add edx,[ebp+__areg+20] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2B98 - 2B9F +MB98: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +call decode_ext +add edx,[ebp+__areg+20] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2BA0 - 2BA7 +MBA0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +call decode_ext +add edx,[ebp+__areg+20] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2BA8 - 2BAF +MBA8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +call decode_ext +add edx,[ebp+__areg+20] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2BB0 - 2BB7 +MBB0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +call decode_ext +add edx,[ebp+__areg+20] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 32 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2BB8 +MBB8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +call decode_ext +add edx,[ebp+__areg+20] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2BB9 +MBB9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +call decode_ext +add edx,[ebp+__areg+20] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 34 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2BBA +MBBA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +call decode_ext +add edx,[ebp+__areg+20] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2BBB +MBBB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +call decode_ext +add edx,[ebp+__areg+20] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 32 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2BBC +MBBC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +call decode_ext +add edx,[ebp+__areg+20] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2C00 - 2C07 +MC00: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+24],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2C08 - 2C0F +MC08: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov [ebp+__dreg+24],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2C10 - 2C17 +MC10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +mov [ebp+__dreg+24],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2C18 - 2C1F +MC18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +mov [ebp+__dreg+24],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2C20 - 2C27 +MC20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +mov [ebp+__dreg+24],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2C28 - 2C2F +MC28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov [ebp+__dreg+24],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2C30 - 2C37 +MC30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov [ebp+__dreg+24],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2C38 +MC38: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +mov [ebp+__dreg+24],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2C39 +MC39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +mov [ebp+__dreg+24],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2C3A +MC3A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +mov [ebp+__dreg+24],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2C3B +MC3B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +mov [ebp+__dreg+24],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2C3C +MC3C: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +mov [ebp+__dreg+24],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2C40 - 2C47 +MC40: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov [ebp+__areg+24],ecx +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2C48 - 2C4F +MC48: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov [ebp+__areg+24],ecx +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2C50 - 2C57 +MC50: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +mov [ebp+__areg+24],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2C58 - 2C5F +MC58: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +mov [ebp+__areg+24],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2C60 - 2C67 +MC60: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +mov [ebp+__areg+24],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2C68 - 2C6F +MC68: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov [ebp+__areg+24],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2C70 - 2C77 +MC70: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov [ebp+__areg+24],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2C78 +MC78: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +mov [ebp+__areg+24],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2C79 +MC79: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +mov [ebp+__areg+24],ecx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2C7A +MC7A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +mov [ebp+__areg+24],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2C7B +MC7B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +mov [ebp+__areg+24],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2C7C +MC7C: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +mov [ebp+__areg+24],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2C80 - 2C87 +MC80: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+24] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2C88 - 2C8F +MC88: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+24] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2C90 - 2C97 +MC90: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+24] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2C98 - 2C9F +MC98: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+24] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2CA0 - 2CA7 +MCA0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+24] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2CA8 - 2CAF +MCA8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+24] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2CB0 - 2CB7 +MCB0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+24] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2CB8 +MCB8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +mov edx,[ebp+__areg+24] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2CB9 +MCB9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +mov edx,[ebp+__areg+24] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2CBA +MCBA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +mov edx,[ebp+__areg+24] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2CBB +MCBB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +mov edx,[ebp+__areg+24] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2CBC +MCBC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +mov edx,[ebp+__areg+24] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2CC0 - 2CC7 +MCC0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+24] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+24],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2CC8 - 2CCF +MCC8: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+24] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+24],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2CD0 - 2CD7 +MCD0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+24] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+24],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2CD8 - 2CDF +MCD8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+24] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+24],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2CE0 - 2CE7 +MCE0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+24] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+24],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2CE8 - 2CEF +MCE8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+24] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+24],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2CF0 - 2CF7 +MCF0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+24] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+24],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2CF8 +MCF8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +mov edx,[ebp+__areg+24] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+24],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2CF9 +MCF9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +mov edx,[ebp+__areg+24] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+24],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2CFA +MCFA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +mov edx,[ebp+__areg+24] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+24],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2CFB +MCFB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +mov edx,[ebp+__areg+24] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+24],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2CFC +MCFC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +mov edx,[ebp+__areg+24] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+24],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2D00 - 2D07 +MD00: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+24] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+24],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2D08 - 2D0F +MD08: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+24] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+24],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2D10 - 2D17 +MD10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+24] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+24],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2D18 - 2D1F +MD18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+24] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+24],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2D20 - 2D27 +MD20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+24] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+24],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2D28 - 2D2F +MD28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+24] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+24],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2D30 - 2D37 +MD30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+24] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+24],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2D38 +MD38: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +mov edx,[ebp+__areg+24] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+24],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2D39 +MD39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +mov edx,[ebp+__areg+24] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+24],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2D3A +MD3A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +mov edx,[ebp+__areg+24] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+24],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2D3B +MD3B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +mov edx,[ebp+__areg+24] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+24],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2D3C +MD3C: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +mov edx,[ebp+__areg+24] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+24],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2D40 - 2D47 +MD40: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+24] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2D48 - 2D4F +MD48: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+24] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2D50 - 2D57 +MD50: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+24] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2D58 - 2D5F +MD58: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+24] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2D60 - 2D67 +MD60: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+24] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2D68 - 2D6F +MD68: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+24] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2D70 - 2D77 +MD70: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+24] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2D78 +MD78: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+24] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2D79 +MD79: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+24] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 32 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2D7A +MD7A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+24] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2D7B +MD7B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+24] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2D7C +MD7C: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+24] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2D80 - 2D87 +MD80: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +call decode_ext +add edx,[ebp+__areg+24] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2D88 - 2D8F +MD88: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +call decode_ext +add edx,[ebp+__areg+24] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2D90 - 2D97 +MD90: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +call decode_ext +add edx,[ebp+__areg+24] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2D98 - 2D9F +MD98: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +call decode_ext +add edx,[ebp+__areg+24] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2DA0 - 2DA7 +MDA0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +call decode_ext +add edx,[ebp+__areg+24] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2DA8 - 2DAF +MDA8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +call decode_ext +add edx,[ebp+__areg+24] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2DB0 - 2DB7 +MDB0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +call decode_ext +add edx,[ebp+__areg+24] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 32 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2DB8 +MDB8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +call decode_ext +add edx,[ebp+__areg+24] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2DB9 +MDB9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +call decode_ext +add edx,[ebp+__areg+24] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 34 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2DBA +MDBA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +call decode_ext +add edx,[ebp+__areg+24] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2DBB +MDBB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +call decode_ext +add edx,[ebp+__areg+24] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 32 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2DBC +MDBC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +call decode_ext +add edx,[ebp+__areg+24] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2E00 - 2E07 +ME00: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+28],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2E08 - 2E0F +ME08: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov [ebp+__dreg+28],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2E10 - 2E17 +ME10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +mov [ebp+__dreg+28],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2E18 - 2E1F +ME18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +mov [ebp+__dreg+28],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2E20 - 2E27 +ME20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +mov [ebp+__dreg+28],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2E28 - 2E2F +ME28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov [ebp+__dreg+28],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2E30 - 2E37 +ME30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov [ebp+__dreg+28],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2E38 +ME38: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +mov [ebp+__dreg+28],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2E39 +ME39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +mov [ebp+__dreg+28],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2E3A +ME3A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +mov [ebp+__dreg+28],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2E3B +ME3B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +mov [ebp+__dreg+28],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2E3C +ME3C: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +mov [ebp+__dreg+28],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2E40 - 2E47 +ME40: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov [ebp+__areg+28],ecx +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2E48 - 2E4F +ME48: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov [ebp+__areg+28],ecx +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2E50 - 2E57 +ME50: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +mov [ebp+__areg+28],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2E58 - 2E5F +ME58: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +mov [ebp+__areg+28],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2E60 - 2E67 +ME60: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +mov [ebp+__areg+28],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2E68 - 2E6F +ME68: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov [ebp+__areg+28],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2E70 - 2E77 +ME70: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov [ebp+__areg+28],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2E78 +ME78: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +mov [ebp+__areg+28],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2E79 +ME79: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +mov [ebp+__areg+28],ecx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2E7A +ME7A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +mov [ebp+__areg+28],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2E7B +ME7B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +mov [ebp+__areg+28],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2E7C +ME7C: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +mov [ebp+__areg+28],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2E80 - 2E87 +ME80: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+28] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2E88 - 2E8F +ME88: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+28] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2E90 - 2E97 +ME90: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+28] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2E98 - 2E9F +ME98: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+28] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2EA0 - 2EA7 +MEA0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+28] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2EA8 - 2EAF +MEA8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+28] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2EB0 - 2EB7 +MEB0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+28] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2EB8 +MEB8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +mov edx,[ebp+__areg+28] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2EB9 +MEB9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +mov edx,[ebp+__areg+28] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2EBA +MEBA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +mov edx,[ebp+__areg+28] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2EBB +MEBB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +mov edx,[ebp+__areg+28] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2EBC +MEBC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +mov edx,[ebp+__areg+28] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2EC0 - 2EC7 +MEC0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+28] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+28],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2EC8 - 2ECF +MEC8: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+28] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+28],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2ED0 - 2ED7 +MED0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+28] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+28],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2ED8 - 2EDF +MED8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+28] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+28],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2EE0 - 2EE7 +MEE0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+28] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+28],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2EE8 - 2EEF +MEE8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+28] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+28],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2EF0 - 2EF7 +MEF0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+28] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+28],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2EF8 +MEF8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +mov edx,[ebp+__areg+28] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+28],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2EF9 +MEF9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +mov edx,[ebp+__areg+28] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+28],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2EFA +MEFA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +mov edx,[ebp+__areg+28] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+28],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2EFB +MEFB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +mov edx,[ebp+__areg+28] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+28],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2EFC +MEFC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +mov edx,[ebp+__areg+28] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+28],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2F00 - 2F07 +MF00: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+28] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+28],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2F08 - 2F0F +MF08: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+28] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+28],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2F10 - 2F17 +MF10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+28] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+28],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2F18 - 2F1F +MF18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+28] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+28],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2F20 - 2F27 +MF20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+28] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+28],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2F28 - 2F2F +MF28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+28] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+28],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2F30 - 2F37 +MF30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +mov edx,[ebp+__areg+28] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+28],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2F38 +MF38: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +mov edx,[ebp+__areg+28] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+28],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2F39 +MF39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +mov edx,[ebp+__areg+28] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+28],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2F3A +MF3A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +mov edx,[ebp+__areg+28] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+28],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2F3B +MF3B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +mov edx,[ebp+__areg+28] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+28],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2F3C +MF3C: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +mov edx,[ebp+__areg+28] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+28],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2F40 - 2F47 +MF40: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+28] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2F48 - 2F4F +MF48: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+28] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2F50 - 2F57 +MF50: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+28] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2F58 - 2F5F +MF58: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+28] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2F60 - 2F67 +MF60: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+28] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2F68 - 2F6F +MF68: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+28] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2F70 - 2F77 +MF70: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+28] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2F78 +MF78: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+28] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2F79 +MF79: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+28] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 32 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2F7A +MF7A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+28] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2F7B +MF7B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+28] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2F7C +MF7C: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+28] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2F80 - 2F87 +MF80: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +call decode_ext +add edx,[ebp+__areg+28] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2F88 - 2F8F +MF88: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +call decode_ext +add edx,[ebp+__areg+28] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2F90 - 2F97 +MF90: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +call decode_ext +add edx,[ebp+__areg+28] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2F98 - 2F9F +MF98: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +call decode_ext +add edx,[ebp+__areg+28] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2FA0 - 2FA7 +MFA0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +call decode_ext +add edx,[ebp+__areg+28] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2FA8 - 2FAF +MFA8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +call decode_ext +add edx,[ebp+__areg+28] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 2FB0 - 2FB7 +MFB0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +call decode_ext +add edx,[ebp+__areg+28] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 32 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2FB8 +MFB8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +call decode_ext +add edx,[ebp+__areg+28] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2FB9 +MFB9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +call decode_ext +add edx,[ebp+__areg+28] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 34 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2FBA +MFBA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +call decode_ext +add edx,[ebp+__areg+28] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2FBB +MFBB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +call decode_ext +add edx,[ebp+__areg+28] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 32 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 2FBC +MFBC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +call decode_ext +add edx,[ebp+__areg+28] +call writememorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3000 - 3007 +N000: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+0],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3008 - 300F +N008: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov [ebp+__dreg+0],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3010 - 3017 +N010: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov [ebp+__dreg+0],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3018 - 301F +N018: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov [ebp+__dreg+0],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3020 - 3027 +N020: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov [ebp+__dreg+0],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3028 - 302F +N028: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov [ebp+__dreg+0],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3030 - 3037 +N030: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov [ebp+__dreg+0],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3038 +N038: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +mov [ebp+__dreg+0],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3039 +N039: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +mov [ebp+__dreg+0],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 303A +N03A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +mov [ebp+__dreg+0],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 303B +N03B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +mov [ebp+__dreg+0],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 303C +N03C: +mov cx,[esi] +add esi,byte 2 +mov [ebp+__dreg+0],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3040 - 3047 +N040: +and ebx,byte 7 +movsx ecx,word[ebp+__dreg+ebx*4] +mov [ebp+__areg+0],ecx +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3048 - 304F +N048: +and ebx,byte 7 +movsx ecx,word[ebp+__areg+ebx*4] +mov [ebp+__areg+0],ecx +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3050 - 3057 +N050: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+0],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3058 - 305F +N058: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov [ebp+__areg+0],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3060 - 3067 +N060: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+ebx*4],edx +mov [ebp+__areg+0],ecx +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3068 - 306F +N068: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+0],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3070 - 3077 +N070: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+0],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3078 +N078: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+0],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3079 +N079: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+0],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 307A +N07A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+0],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 307B +N07B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+0],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 307C +N07C: +movsx ecx,word[esi] +add esi,byte 2 +mov [ebp+__areg+0],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3080 - 3087 +N080: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+0] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3088 - 308F +N088: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+0] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3090 - 3097 +N090: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+0] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3098 - 309F +N098: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+0] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 30A0 - 30A7 +N0A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+0] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 30A8 - 30AF +N0A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+0] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 30B0 - 30B7 +N0B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+0] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 30B8 +N0B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +mov edx,[ebp+__areg+0] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 30B9 +N0B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +mov edx,[ebp+__areg+0] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 30BA +N0BA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +mov edx,[ebp+__areg+0] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 30BB +N0BB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +mov edx,[ebp+__areg+0] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 30BC +N0BC: +mov cx,[esi] +add esi,byte 2 +mov edx,[ebp+__areg+0] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 30C0 - 30C7 +N0C0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+0] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+0],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 30C8 - 30CF +N0C8: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+0] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+0],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 30D0 - 30D7 +N0D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+0] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+0],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 30D8 - 30DF +N0D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+0] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+0],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 30E0 - 30E7 +N0E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+0] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+0],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 30E8 - 30EF +N0E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+0] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+0],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 30F0 - 30F7 +N0F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+0] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+0],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 30F8 +N0F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +mov edx,[ebp+__areg+0] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+0],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 30F9 +N0F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +mov edx,[ebp+__areg+0] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+0],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 30FA +N0FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +mov edx,[ebp+__areg+0] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+0],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 30FB +N0FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +mov edx,[ebp+__areg+0] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+0],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 30FC +N0FC: +mov cx,[esi] +add esi,byte 2 +mov edx,[ebp+__areg+0] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+0],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3100 - 3107 +N100: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+0] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+0],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3108 - 310F +N108: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+0] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+0],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3110 - 3117 +N110: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+0] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+0],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3118 - 311F +N118: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+0] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+0],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3120 - 3127 +N120: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+0] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+0],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3128 - 312F +N128: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+0] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+0],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3130 - 3137 +N130: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+0] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+0],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3138 +N138: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +mov edx,[ebp+__areg+0] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+0],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3139 +N139: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +mov edx,[ebp+__areg+0] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+0],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 313A +N13A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +mov edx,[ebp+__areg+0] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+0],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 313B +N13B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +mov edx,[ebp+__areg+0] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+0],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 313C +N13C: +mov cx,[esi] +add esi,byte 2 +mov edx,[ebp+__areg+0] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+0],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3140 - 3147 +N140: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+0] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3148 - 314F +N148: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+0] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3150 - 3157 +N150: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+0] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3158 - 315F +N158: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+0] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3160 - 3167 +N160: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+0] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3168 - 316F +N168: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+0] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3170 - 3177 +N170: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+0] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3178 +N178: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+0] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3179 +N179: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+0] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 317A +N17A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+0] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 317B +N17B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+0] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 317C +N17C: +mov cx,[esi] +add esi,byte 2 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+0] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3180 - 3187 +N180: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +call decode_ext +add edx,[ebp+__areg+0] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3188 - 318F +N188: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +call decode_ext +add edx,[ebp+__areg+0] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3190 - 3197 +N190: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +call decode_ext +add edx,[ebp+__areg+0] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3198 - 319F +N198: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +call decode_ext +add edx,[ebp+__areg+0] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 31A0 - 31A7 +N1A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +call decode_ext +add edx,[ebp+__areg+0] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 31A8 - 31AF +N1A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +call decode_ext +add edx,[ebp+__areg+0] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 31B0 - 31B7 +N1B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +call decode_ext +add edx,[ebp+__areg+0] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 31B8 +N1B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +call decode_ext +add edx,[ebp+__areg+0] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 31B9 +N1B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +call decode_ext +add edx,[ebp+__areg+0] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 31BA +N1BA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +call decode_ext +add edx,[ebp+__areg+0] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 31BB +N1BB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +call decode_ext +add edx,[ebp+__areg+0] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 31BC +N1BC: +mov cx,[esi] +add esi,byte 2 +call decode_ext +add edx,[ebp+__areg+0] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 31C0 - 31C7 +N1C0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +movsx edx,word[esi] +add esi,byte 2 +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 31C8 - 31CF +N1C8: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +movsx edx,word[esi] +add esi,byte 2 +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 31D0 - 31D7 +N1D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 31D8 - 31DF +N1D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +movsx edx,word[esi] +add esi,byte 2 +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 31E0 - 31E7 +N1E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +movsx edx,word[esi] +add esi,byte 2 +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 31E8 - 31EF +N1E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 31F0 - 31F7 +N1F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 31F8 +N1F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 31F9 +N1F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 31FA +N1FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 31FB +N1FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 31FC +N1FC: +mov cx,[esi] +add esi,byte 2 +movsx edx,word[esi] +add esi,byte 2 +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3200 - 3207 +N200: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+4],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3208 - 320F +N208: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov [ebp+__dreg+4],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3210 - 3217 +N210: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov [ebp+__dreg+4],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3218 - 321F +N218: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov [ebp+__dreg+4],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3220 - 3227 +N220: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov [ebp+__dreg+4],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3228 - 322F +N228: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov [ebp+__dreg+4],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3230 - 3237 +N230: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov [ebp+__dreg+4],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3238 +N238: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +mov [ebp+__dreg+4],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3239 +N239: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +mov [ebp+__dreg+4],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 323A +N23A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +mov [ebp+__dreg+4],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 323B +N23B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +mov [ebp+__dreg+4],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 323C +N23C: +mov cx,[esi] +add esi,byte 2 +mov [ebp+__dreg+4],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3240 - 3247 +N240: +and ebx,byte 7 +movsx ecx,word[ebp+__dreg+ebx*4] +mov [ebp+__areg+4],ecx +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3248 - 324F +N248: +and ebx,byte 7 +movsx ecx,word[ebp+__areg+ebx*4] +mov [ebp+__areg+4],ecx +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3250 - 3257 +N250: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+4],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3258 - 325F +N258: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov [ebp+__areg+4],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3260 - 3267 +N260: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+ebx*4],edx +mov [ebp+__areg+4],ecx +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3268 - 326F +N268: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+4],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3270 - 3277 +N270: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+4],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3278 +N278: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+4],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3279 +N279: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+4],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 327A +N27A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+4],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 327B +N27B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+4],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 327C +N27C: +movsx ecx,word[esi] +add esi,byte 2 +mov [ebp+__areg+4],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3280 - 3287 +N280: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+4] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3288 - 328F +N288: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+4] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3290 - 3297 +N290: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+4] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3298 - 329F +N298: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+4] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 32A0 - 32A7 +N2A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+4] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 32A8 - 32AF +N2A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+4] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 32B0 - 32B7 +N2B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+4] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 32B8 +N2B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +mov edx,[ebp+__areg+4] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 32B9 +N2B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +mov edx,[ebp+__areg+4] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 32BA +N2BA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +mov edx,[ebp+__areg+4] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 32BB +N2BB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +mov edx,[ebp+__areg+4] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 32BC +N2BC: +mov cx,[esi] +add esi,byte 2 +mov edx,[ebp+__areg+4] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 32C0 - 32C7 +N2C0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+4] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+4],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 32C8 - 32CF +N2C8: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+4] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+4],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 32D0 - 32D7 +N2D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+4] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+4],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 32D8 - 32DF +N2D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+4] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+4],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 32E0 - 32E7 +N2E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+4] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+4],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 32E8 - 32EF +N2E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+4] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+4],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 32F0 - 32F7 +N2F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+4] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+4],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 32F8 +N2F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +mov edx,[ebp+__areg+4] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+4],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 32F9 +N2F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +mov edx,[ebp+__areg+4] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+4],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 32FA +N2FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +mov edx,[ebp+__areg+4] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+4],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 32FB +N2FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +mov edx,[ebp+__areg+4] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+4],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 32FC +N2FC: +mov cx,[esi] +add esi,byte 2 +mov edx,[ebp+__areg+4] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+4],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3300 - 3307 +N300: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+4] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+4],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3308 - 330F +N308: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+4] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+4],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3310 - 3317 +N310: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+4] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+4],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3318 - 331F +N318: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+4] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+4],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3320 - 3327 +N320: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+4] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+4],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3328 - 332F +N328: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+4] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+4],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3330 - 3337 +N330: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+4] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+4],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3338 +N338: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +mov edx,[ebp+__areg+4] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+4],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3339 +N339: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +mov edx,[ebp+__areg+4] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+4],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 333A +N33A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +mov edx,[ebp+__areg+4] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+4],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 333B +N33B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +mov edx,[ebp+__areg+4] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+4],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 333C +N33C: +mov cx,[esi] +add esi,byte 2 +mov edx,[ebp+__areg+4] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+4],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3340 - 3347 +N340: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+4] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3348 - 334F +N348: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+4] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3350 - 3357 +N350: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+4] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3358 - 335F +N358: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+4] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3360 - 3367 +N360: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+4] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3368 - 336F +N368: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+4] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3370 - 3377 +N370: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+4] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3378 +N378: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+4] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3379 +N379: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+4] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 337A +N37A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+4] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 337B +N37B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+4] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 337C +N37C: +mov cx,[esi] +add esi,byte 2 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+4] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3380 - 3387 +N380: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +call decode_ext +add edx,[ebp+__areg+4] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3388 - 338F +N388: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +call decode_ext +add edx,[ebp+__areg+4] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3390 - 3397 +N390: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +call decode_ext +add edx,[ebp+__areg+4] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3398 - 339F +N398: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +call decode_ext +add edx,[ebp+__areg+4] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 33A0 - 33A7 +N3A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +call decode_ext +add edx,[ebp+__areg+4] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 33A8 - 33AF +N3A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +call decode_ext +add edx,[ebp+__areg+4] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 33B0 - 33B7 +N3B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +call decode_ext +add edx,[ebp+__areg+4] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 33B8 +N3B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +call decode_ext +add edx,[ebp+__areg+4] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 33B9 +N3B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +call decode_ext +add edx,[ebp+__areg+4] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 33BA +N3BA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +call decode_ext +add edx,[ebp+__areg+4] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 33BB +N3BB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +call decode_ext +add edx,[ebp+__areg+4] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 33BC +N3BC: +mov cx,[esi] +add esi,byte 2 +call decode_ext +add edx,[ebp+__areg+4] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 33C0 - 33C7 +N3C0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 33C8 - 33CF +N3C8: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 33D0 - 33D7 +N3D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 33D8 - 33DF +N3D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 33E0 - 33E7 +N3E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 33E8 - 33EF +N3E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 33F0 - 33F7 +N3F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 33F8 +N3F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 33F9 +N3F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 33FA +N3FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 33FB +N3FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 33FC +N3FC: +mov cx,[esi] +add esi,byte 2 +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3400 - 3407 +N400: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+8],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3408 - 340F +N408: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov [ebp+__dreg+8],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3410 - 3417 +N410: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov [ebp+__dreg+8],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3418 - 341F +N418: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov [ebp+__dreg+8],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3420 - 3427 +N420: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov [ebp+__dreg+8],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3428 - 342F +N428: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov [ebp+__dreg+8],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3430 - 3437 +N430: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov [ebp+__dreg+8],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3438 +N438: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +mov [ebp+__dreg+8],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3439 +N439: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +mov [ebp+__dreg+8],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 343A +N43A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +mov [ebp+__dreg+8],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 343B +N43B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +mov [ebp+__dreg+8],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 343C +N43C: +mov cx,[esi] +add esi,byte 2 +mov [ebp+__dreg+8],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3440 - 3447 +N440: +and ebx,byte 7 +movsx ecx,word[ebp+__dreg+ebx*4] +mov [ebp+__areg+8],ecx +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3448 - 344F +N448: +and ebx,byte 7 +movsx ecx,word[ebp+__areg+ebx*4] +mov [ebp+__areg+8],ecx +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3450 - 3457 +N450: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+8],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3458 - 345F +N458: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov [ebp+__areg+8],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3460 - 3467 +N460: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+ebx*4],edx +mov [ebp+__areg+8],ecx +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3468 - 346F +N468: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+8],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3470 - 3477 +N470: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+8],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3478 +N478: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+8],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3479 +N479: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+8],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 347A +N47A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+8],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 347B +N47B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+8],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 347C +N47C: +movsx ecx,word[esi] +add esi,byte 2 +mov [ebp+__areg+8],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3480 - 3487 +N480: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+8] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3488 - 348F +N488: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+8] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3490 - 3497 +N490: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+8] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3498 - 349F +N498: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+8] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 34A0 - 34A7 +N4A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+8] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 34A8 - 34AF +N4A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+8] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 34B0 - 34B7 +N4B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+8] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 34B8 +N4B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +mov edx,[ebp+__areg+8] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 34B9 +N4B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +mov edx,[ebp+__areg+8] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 34BA +N4BA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +mov edx,[ebp+__areg+8] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 34BB +N4BB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +mov edx,[ebp+__areg+8] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 34BC +N4BC: +mov cx,[esi] +add esi,byte 2 +mov edx,[ebp+__areg+8] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 34C0 - 34C7 +N4C0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+8] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+8],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 34C8 - 34CF +N4C8: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+8] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+8],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 34D0 - 34D7 +N4D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+8] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+8],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 34D8 - 34DF +N4D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+8] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+8],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 34E0 - 34E7 +N4E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+8] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+8],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 34E8 - 34EF +N4E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+8] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+8],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 34F0 - 34F7 +N4F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+8] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+8],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 34F8 +N4F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +mov edx,[ebp+__areg+8] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+8],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 34F9 +N4F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +mov edx,[ebp+__areg+8] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+8],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 34FA +N4FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +mov edx,[ebp+__areg+8] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+8],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 34FB +N4FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +mov edx,[ebp+__areg+8] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+8],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 34FC +N4FC: +mov cx,[esi] +add esi,byte 2 +mov edx,[ebp+__areg+8] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+8],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3500 - 3507 +N500: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+8] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+8],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3508 - 350F +N508: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+8] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+8],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3510 - 3517 +N510: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+8] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+8],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3518 - 351F +N518: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+8] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+8],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3520 - 3527 +N520: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+8] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+8],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3528 - 352F +N528: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+8] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+8],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3530 - 3537 +N530: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+8] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+8],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3538 +N538: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +mov edx,[ebp+__areg+8] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+8],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3539 +N539: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +mov edx,[ebp+__areg+8] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+8],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 353A +N53A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +mov edx,[ebp+__areg+8] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+8],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 353B +N53B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +mov edx,[ebp+__areg+8] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+8],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 353C +N53C: +mov cx,[esi] +add esi,byte 2 +mov edx,[ebp+__areg+8] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+8],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3540 - 3547 +N540: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+8] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3548 - 354F +N548: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+8] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3550 - 3557 +N550: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+8] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3558 - 355F +N558: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+8] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3560 - 3567 +N560: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+8] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3568 - 356F +N568: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+8] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3570 - 3577 +N570: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+8] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3578 +N578: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+8] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3579 +N579: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+8] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 357A +N57A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+8] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 357B +N57B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+8] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 357C +N57C: +mov cx,[esi] +add esi,byte 2 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+8] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3580 - 3587 +N580: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +call decode_ext +add edx,[ebp+__areg+8] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3588 - 358F +N588: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +call decode_ext +add edx,[ebp+__areg+8] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3590 - 3597 +N590: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +call decode_ext +add edx,[ebp+__areg+8] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3598 - 359F +N598: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +call decode_ext +add edx,[ebp+__areg+8] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 35A0 - 35A7 +N5A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +call decode_ext +add edx,[ebp+__areg+8] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 35A8 - 35AF +N5A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +call decode_ext +add edx,[ebp+__areg+8] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 35B0 - 35B7 +N5B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +call decode_ext +add edx,[ebp+__areg+8] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 35B8 +N5B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +call decode_ext +add edx,[ebp+__areg+8] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 35B9 +N5B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +call decode_ext +add edx,[ebp+__areg+8] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 35BA +N5BA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +call decode_ext +add edx,[ebp+__areg+8] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 35BB +N5BB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +call decode_ext +add edx,[ebp+__areg+8] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 35BC +N5BC: +mov cx,[esi] +add esi,byte 2 +call decode_ext +add edx,[ebp+__areg+8] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3600 - 3607 +N600: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+12],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3608 - 360F +N608: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov [ebp+__dreg+12],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3610 - 3617 +N610: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov [ebp+__dreg+12],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3618 - 361F +N618: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov [ebp+__dreg+12],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3620 - 3627 +N620: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov [ebp+__dreg+12],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3628 - 362F +N628: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov [ebp+__dreg+12],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3630 - 3637 +N630: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov [ebp+__dreg+12],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3638 +N638: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +mov [ebp+__dreg+12],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3639 +N639: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +mov [ebp+__dreg+12],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 363A +N63A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +mov [ebp+__dreg+12],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 363B +N63B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +mov [ebp+__dreg+12],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 363C +N63C: +mov cx,[esi] +add esi,byte 2 +mov [ebp+__dreg+12],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3640 - 3647 +N640: +and ebx,byte 7 +movsx ecx,word[ebp+__dreg+ebx*4] +mov [ebp+__areg+12],ecx +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3648 - 364F +N648: +and ebx,byte 7 +movsx ecx,word[ebp+__areg+ebx*4] +mov [ebp+__areg+12],ecx +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3650 - 3657 +N650: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+12],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3658 - 365F +N658: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov [ebp+__areg+12],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3660 - 3667 +N660: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+ebx*4],edx +mov [ebp+__areg+12],ecx +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3668 - 366F +N668: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+12],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3670 - 3677 +N670: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+12],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3678 +N678: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+12],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3679 +N679: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+12],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 367A +N67A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+12],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 367B +N67B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+12],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 367C +N67C: +movsx ecx,word[esi] +add esi,byte 2 +mov [ebp+__areg+12],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3680 - 3687 +N680: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+12] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3688 - 368F +N688: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+12] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3690 - 3697 +N690: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+12] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3698 - 369F +N698: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+12] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 36A0 - 36A7 +N6A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+12] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 36A8 - 36AF +N6A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+12] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 36B0 - 36B7 +N6B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+12] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 36B8 +N6B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +mov edx,[ebp+__areg+12] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 36B9 +N6B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +mov edx,[ebp+__areg+12] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 36BA +N6BA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +mov edx,[ebp+__areg+12] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 36BB +N6BB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +mov edx,[ebp+__areg+12] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 36BC +N6BC: +mov cx,[esi] +add esi,byte 2 +mov edx,[ebp+__areg+12] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 36C0 - 36C7 +N6C0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+12] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+12],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 36C8 - 36CF +N6C8: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+12] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+12],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 36D0 - 36D7 +N6D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+12] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+12],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 36D8 - 36DF +N6D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+12] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+12],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 36E0 - 36E7 +N6E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+12] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+12],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 36E8 - 36EF +N6E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+12] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+12],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 36F0 - 36F7 +N6F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+12] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+12],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 36F8 +N6F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +mov edx,[ebp+__areg+12] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+12],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 36F9 +N6F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +mov edx,[ebp+__areg+12] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+12],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 36FA +N6FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +mov edx,[ebp+__areg+12] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+12],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 36FB +N6FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +mov edx,[ebp+__areg+12] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+12],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 36FC +N6FC: +mov cx,[esi] +add esi,byte 2 +mov edx,[ebp+__areg+12] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+12],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3700 - 3707 +N700: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+12] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+12],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3708 - 370F +N708: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+12] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+12],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3710 - 3717 +N710: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+12] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+12],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3718 - 371F +N718: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+12] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+12],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3720 - 3727 +N720: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+12] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+12],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3728 - 372F +N728: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+12] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+12],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3730 - 3737 +N730: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+12] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+12],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3738 +N738: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +mov edx,[ebp+__areg+12] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+12],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3739 +N739: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +mov edx,[ebp+__areg+12] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+12],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 373A +N73A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +mov edx,[ebp+__areg+12] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+12],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 373B +N73B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +mov edx,[ebp+__areg+12] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+12],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 373C +N73C: +mov cx,[esi] +add esi,byte 2 +mov edx,[ebp+__areg+12] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+12],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3740 - 3747 +N740: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+12] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3748 - 374F +N748: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+12] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3750 - 3757 +N750: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+12] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3758 - 375F +N758: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+12] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3760 - 3767 +N760: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+12] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3768 - 376F +N768: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+12] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3770 - 3777 +N770: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+12] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3778 +N778: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+12] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3779 +N779: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+12] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 377A +N77A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+12] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 377B +N77B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+12] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 377C +N77C: +mov cx,[esi] +add esi,byte 2 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+12] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3780 - 3787 +N780: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +call decode_ext +add edx,[ebp+__areg+12] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3788 - 378F +N788: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +call decode_ext +add edx,[ebp+__areg+12] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3790 - 3797 +N790: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +call decode_ext +add edx,[ebp+__areg+12] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3798 - 379F +N798: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +call decode_ext +add edx,[ebp+__areg+12] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 37A0 - 37A7 +N7A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +call decode_ext +add edx,[ebp+__areg+12] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 37A8 - 37AF +N7A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +call decode_ext +add edx,[ebp+__areg+12] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 37B0 - 37B7 +N7B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +call decode_ext +add edx,[ebp+__areg+12] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 37B8 +N7B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +call decode_ext +add edx,[ebp+__areg+12] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 37B9 +N7B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +call decode_ext +add edx,[ebp+__areg+12] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 37BA +N7BA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +call decode_ext +add edx,[ebp+__areg+12] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 37BB +N7BB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +call decode_ext +add edx,[ebp+__areg+12] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 37BC +N7BC: +mov cx,[esi] +add esi,byte 2 +call decode_ext +add edx,[ebp+__areg+12] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3800 - 3807 +N800: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+16],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3808 - 380F +N808: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov [ebp+__dreg+16],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3810 - 3817 +N810: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov [ebp+__dreg+16],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3818 - 381F +N818: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov [ebp+__dreg+16],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3820 - 3827 +N820: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov [ebp+__dreg+16],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3828 - 382F +N828: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov [ebp+__dreg+16],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3830 - 3837 +N830: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov [ebp+__dreg+16],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3838 +N838: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +mov [ebp+__dreg+16],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3839 +N839: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +mov [ebp+__dreg+16],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 383A +N83A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +mov [ebp+__dreg+16],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 383B +N83B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +mov [ebp+__dreg+16],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 383C +N83C: +mov cx,[esi] +add esi,byte 2 +mov [ebp+__dreg+16],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3840 - 3847 +N840: +and ebx,byte 7 +movsx ecx,word[ebp+__dreg+ebx*4] +mov [ebp+__areg+16],ecx +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3848 - 384F +N848: +and ebx,byte 7 +movsx ecx,word[ebp+__areg+ebx*4] +mov [ebp+__areg+16],ecx +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3850 - 3857 +N850: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+16],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3858 - 385F +N858: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov [ebp+__areg+16],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3860 - 3867 +N860: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+ebx*4],edx +mov [ebp+__areg+16],ecx +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3868 - 386F +N868: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+16],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3870 - 3877 +N870: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+16],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3878 +N878: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+16],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3879 +N879: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+16],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 387A +N87A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+16],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 387B +N87B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+16],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 387C +N87C: +movsx ecx,word[esi] +add esi,byte 2 +mov [ebp+__areg+16],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3880 - 3887 +N880: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+16] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3888 - 388F +N888: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+16] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3890 - 3897 +N890: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+16] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3898 - 389F +N898: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+16] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 38A0 - 38A7 +N8A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+16] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 38A8 - 38AF +N8A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+16] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 38B0 - 38B7 +N8B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+16] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 38B8 +N8B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +mov edx,[ebp+__areg+16] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 38B9 +N8B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +mov edx,[ebp+__areg+16] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 38BA +N8BA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +mov edx,[ebp+__areg+16] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 38BB +N8BB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +mov edx,[ebp+__areg+16] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 38BC +N8BC: +mov cx,[esi] +add esi,byte 2 +mov edx,[ebp+__areg+16] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 38C0 - 38C7 +N8C0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+16] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+16],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 38C8 - 38CF +N8C8: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+16] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+16],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 38D0 - 38D7 +N8D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+16] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+16],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 38D8 - 38DF +N8D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+16] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+16],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 38E0 - 38E7 +N8E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+16] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+16],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 38E8 - 38EF +N8E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+16] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+16],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 38F0 - 38F7 +N8F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+16] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+16],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 38F8 +N8F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +mov edx,[ebp+__areg+16] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+16],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 38F9 +N8F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +mov edx,[ebp+__areg+16] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+16],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 38FA +N8FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +mov edx,[ebp+__areg+16] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+16],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 38FB +N8FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +mov edx,[ebp+__areg+16] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+16],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 38FC +N8FC: +mov cx,[esi] +add esi,byte 2 +mov edx,[ebp+__areg+16] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+16],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3900 - 3907 +N900: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+16] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+16],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3908 - 390F +N908: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+16] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+16],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3910 - 3917 +N910: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+16] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+16],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3918 - 391F +N918: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+16] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+16],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3920 - 3927 +N920: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+16] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+16],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3928 - 392F +N928: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+16] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+16],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3930 - 3937 +N930: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+16] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+16],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3938 +N938: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +mov edx,[ebp+__areg+16] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+16],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3939 +N939: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +mov edx,[ebp+__areg+16] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+16],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 393A +N93A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +mov edx,[ebp+__areg+16] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+16],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 393B +N93B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +mov edx,[ebp+__areg+16] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+16],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 393C +N93C: +mov cx,[esi] +add esi,byte 2 +mov edx,[ebp+__areg+16] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+16],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3940 - 3947 +N940: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+16] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3948 - 394F +N948: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+16] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3950 - 3957 +N950: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+16] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3958 - 395F +N958: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+16] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3960 - 3967 +N960: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+16] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3968 - 396F +N968: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+16] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3970 - 3977 +N970: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+16] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3978 +N978: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+16] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3979 +N979: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+16] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 397A +N97A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+16] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 397B +N97B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+16] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 397C +N97C: +mov cx,[esi] +add esi,byte 2 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+16] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3980 - 3987 +N980: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +call decode_ext +add edx,[ebp+__areg+16] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3988 - 398F +N988: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +call decode_ext +add edx,[ebp+__areg+16] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3990 - 3997 +N990: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +call decode_ext +add edx,[ebp+__areg+16] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3998 - 399F +N998: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +call decode_ext +add edx,[ebp+__areg+16] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 39A0 - 39A7 +N9A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +call decode_ext +add edx,[ebp+__areg+16] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 39A8 - 39AF +N9A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +call decode_ext +add edx,[ebp+__areg+16] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 39B0 - 39B7 +N9B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +call decode_ext +add edx,[ebp+__areg+16] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 39B8 +N9B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +call decode_ext +add edx,[ebp+__areg+16] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 39B9 +N9B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +call decode_ext +add edx,[ebp+__areg+16] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 39BA +N9BA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +call decode_ext +add edx,[ebp+__areg+16] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 39BB +N9BB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +call decode_ext +add edx,[ebp+__areg+16] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 39BC +N9BC: +mov cx,[esi] +add esi,byte 2 +call decode_ext +add edx,[ebp+__areg+16] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3A00 - 3A07 +NA00: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+20],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3A08 - 3A0F +NA08: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov [ebp+__dreg+20],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3A10 - 3A17 +NA10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov [ebp+__dreg+20],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3A18 - 3A1F +NA18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov [ebp+__dreg+20],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3A20 - 3A27 +NA20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov [ebp+__dreg+20],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3A28 - 3A2F +NA28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov [ebp+__dreg+20],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3A30 - 3A37 +NA30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov [ebp+__dreg+20],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3A38 +NA38: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +mov [ebp+__dreg+20],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3A39 +NA39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +mov [ebp+__dreg+20],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3A3A +NA3A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +mov [ebp+__dreg+20],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3A3B +NA3B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +mov [ebp+__dreg+20],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3A3C +NA3C: +mov cx,[esi] +add esi,byte 2 +mov [ebp+__dreg+20],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3A40 - 3A47 +NA40: +and ebx,byte 7 +movsx ecx,word[ebp+__dreg+ebx*4] +mov [ebp+__areg+20],ecx +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3A48 - 3A4F +NA48: +and ebx,byte 7 +movsx ecx,word[ebp+__areg+ebx*4] +mov [ebp+__areg+20],ecx +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3A50 - 3A57 +NA50: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+20],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3A58 - 3A5F +NA58: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov [ebp+__areg+20],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3A60 - 3A67 +NA60: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+ebx*4],edx +mov [ebp+__areg+20],ecx +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3A68 - 3A6F +NA68: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+20],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3A70 - 3A77 +NA70: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+20],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3A78 +NA78: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+20],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3A79 +NA79: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+20],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3A7A +NA7A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+20],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3A7B +NA7B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+20],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3A7C +NA7C: +movsx ecx,word[esi] +add esi,byte 2 +mov [ebp+__areg+20],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3A80 - 3A87 +NA80: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+20] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3A88 - 3A8F +NA88: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+20] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3A90 - 3A97 +NA90: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+20] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3A98 - 3A9F +NA98: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+20] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3AA0 - 3AA7 +NAA0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+20] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3AA8 - 3AAF +NAA8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+20] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3AB0 - 3AB7 +NAB0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+20] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3AB8 +NAB8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +mov edx,[ebp+__areg+20] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3AB9 +NAB9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +mov edx,[ebp+__areg+20] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3ABA +NABA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +mov edx,[ebp+__areg+20] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3ABB +NABB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +mov edx,[ebp+__areg+20] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3ABC +NABC: +mov cx,[esi] +add esi,byte 2 +mov edx,[ebp+__areg+20] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3AC0 - 3AC7 +NAC0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+20] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+20],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3AC8 - 3ACF +NAC8: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+20] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+20],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3AD0 - 3AD7 +NAD0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+20] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+20],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3AD8 - 3ADF +NAD8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+20] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+20],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3AE0 - 3AE7 +NAE0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+20] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+20],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3AE8 - 3AEF +NAE8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+20] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+20],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3AF0 - 3AF7 +NAF0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+20] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+20],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3AF8 +NAF8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +mov edx,[ebp+__areg+20] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+20],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3AF9 +NAF9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +mov edx,[ebp+__areg+20] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+20],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3AFA +NAFA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +mov edx,[ebp+__areg+20] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+20],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3AFB +NAFB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +mov edx,[ebp+__areg+20] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+20],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3AFC +NAFC: +mov cx,[esi] +add esi,byte 2 +mov edx,[ebp+__areg+20] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+20],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3B00 - 3B07 +NB00: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+20] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+20],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3B08 - 3B0F +NB08: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+20] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+20],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3B10 - 3B17 +NB10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+20] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+20],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3B18 - 3B1F +NB18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+20] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+20],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3B20 - 3B27 +NB20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+20] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+20],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3B28 - 3B2F +NB28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+20] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+20],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3B30 - 3B37 +NB30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+20] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+20],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3B38 +NB38: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +mov edx,[ebp+__areg+20] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+20],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3B39 +NB39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +mov edx,[ebp+__areg+20] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+20],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3B3A +NB3A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +mov edx,[ebp+__areg+20] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+20],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3B3B +NB3B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +mov edx,[ebp+__areg+20] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+20],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3B3C +NB3C: +mov cx,[esi] +add esi,byte 2 +mov edx,[ebp+__areg+20] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+20],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3B40 - 3B47 +NB40: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+20] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3B48 - 3B4F +NB48: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+20] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3B50 - 3B57 +NB50: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+20] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3B58 - 3B5F +NB58: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+20] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3B60 - 3B67 +NB60: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+20] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3B68 - 3B6F +NB68: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+20] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3B70 - 3B77 +NB70: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+20] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3B78 +NB78: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+20] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3B79 +NB79: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+20] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3B7A +NB7A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+20] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3B7B +NB7B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+20] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3B7C +NB7C: +mov cx,[esi] +add esi,byte 2 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+20] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3B80 - 3B87 +NB80: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +call decode_ext +add edx,[ebp+__areg+20] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3B88 - 3B8F +NB88: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +call decode_ext +add edx,[ebp+__areg+20] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3B90 - 3B97 +NB90: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +call decode_ext +add edx,[ebp+__areg+20] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3B98 - 3B9F +NB98: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +call decode_ext +add edx,[ebp+__areg+20] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3BA0 - 3BA7 +NBA0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +call decode_ext +add edx,[ebp+__areg+20] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3BA8 - 3BAF +NBA8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +call decode_ext +add edx,[ebp+__areg+20] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3BB0 - 3BB7 +NBB0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +call decode_ext +add edx,[ebp+__areg+20] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3BB8 +NBB8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +call decode_ext +add edx,[ebp+__areg+20] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3BB9 +NBB9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +call decode_ext +add edx,[ebp+__areg+20] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3BBA +NBBA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +call decode_ext +add edx,[ebp+__areg+20] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3BBB +NBBB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +call decode_ext +add edx,[ebp+__areg+20] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3BBC +NBBC: +mov cx,[esi] +add esi,byte 2 +call decode_ext +add edx,[ebp+__areg+20] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3C00 - 3C07 +NC00: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+24],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3C08 - 3C0F +NC08: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov [ebp+__dreg+24],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3C10 - 3C17 +NC10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov [ebp+__dreg+24],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3C18 - 3C1F +NC18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov [ebp+__dreg+24],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3C20 - 3C27 +NC20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov [ebp+__dreg+24],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3C28 - 3C2F +NC28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov [ebp+__dreg+24],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3C30 - 3C37 +NC30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov [ebp+__dreg+24],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3C38 +NC38: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +mov [ebp+__dreg+24],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3C39 +NC39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +mov [ebp+__dreg+24],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3C3A +NC3A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +mov [ebp+__dreg+24],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3C3B +NC3B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +mov [ebp+__dreg+24],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3C3C +NC3C: +mov cx,[esi] +add esi,byte 2 +mov [ebp+__dreg+24],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3C40 - 3C47 +NC40: +and ebx,byte 7 +movsx ecx,word[ebp+__dreg+ebx*4] +mov [ebp+__areg+24],ecx +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3C48 - 3C4F +NC48: +and ebx,byte 7 +movsx ecx,word[ebp+__areg+ebx*4] +mov [ebp+__areg+24],ecx +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3C50 - 3C57 +NC50: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+24],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3C58 - 3C5F +NC58: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov [ebp+__areg+24],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3C60 - 3C67 +NC60: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+ebx*4],edx +mov [ebp+__areg+24],ecx +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3C68 - 3C6F +NC68: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+24],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3C70 - 3C77 +NC70: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+24],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3C78 +NC78: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+24],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3C79 +NC79: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+24],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3C7A +NC7A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+24],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3C7B +NC7B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+24],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3C7C +NC7C: +movsx ecx,word[esi] +add esi,byte 2 +mov [ebp+__areg+24],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3C80 - 3C87 +NC80: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+24] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3C88 - 3C8F +NC88: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+24] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3C90 - 3C97 +NC90: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+24] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3C98 - 3C9F +NC98: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+24] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3CA0 - 3CA7 +NCA0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+24] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3CA8 - 3CAF +NCA8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+24] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3CB0 - 3CB7 +NCB0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+24] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3CB8 +NCB8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +mov edx,[ebp+__areg+24] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3CB9 +NCB9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +mov edx,[ebp+__areg+24] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3CBA +NCBA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +mov edx,[ebp+__areg+24] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3CBB +NCBB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +mov edx,[ebp+__areg+24] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3CBC +NCBC: +mov cx,[esi] +add esi,byte 2 +mov edx,[ebp+__areg+24] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3CC0 - 3CC7 +NCC0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+24] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+24],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3CC8 - 3CCF +NCC8: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+24] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+24],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3CD0 - 3CD7 +NCD0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+24] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+24],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3CD8 - 3CDF +NCD8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+24] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+24],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3CE0 - 3CE7 +NCE0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+24] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+24],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3CE8 - 3CEF +NCE8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+24] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+24],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3CF0 - 3CF7 +NCF0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+24] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+24],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3CF8 +NCF8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +mov edx,[ebp+__areg+24] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+24],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3CF9 +NCF9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +mov edx,[ebp+__areg+24] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+24],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3CFA +NCFA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +mov edx,[ebp+__areg+24] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+24],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3CFB +NCFB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +mov edx,[ebp+__areg+24] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+24],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3CFC +NCFC: +mov cx,[esi] +add esi,byte 2 +mov edx,[ebp+__areg+24] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+24],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3D00 - 3D07 +ND00: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+24] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+24],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3D08 - 3D0F +ND08: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+24] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+24],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3D10 - 3D17 +ND10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+24] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+24],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3D18 - 3D1F +ND18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+24] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+24],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3D20 - 3D27 +ND20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+24] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+24],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3D28 - 3D2F +ND28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+24] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+24],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3D30 - 3D37 +ND30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+24] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+24],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3D38 +ND38: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +mov edx,[ebp+__areg+24] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+24],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3D39 +ND39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +mov edx,[ebp+__areg+24] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+24],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3D3A +ND3A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +mov edx,[ebp+__areg+24] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+24],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3D3B +ND3B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +mov edx,[ebp+__areg+24] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+24],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3D3C +ND3C: +mov cx,[esi] +add esi,byte 2 +mov edx,[ebp+__areg+24] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+24],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3D40 - 3D47 +ND40: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+24] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3D48 - 3D4F +ND48: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+24] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3D50 - 3D57 +ND50: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+24] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3D58 - 3D5F +ND58: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+24] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3D60 - 3D67 +ND60: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+24] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3D68 - 3D6F +ND68: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+24] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3D70 - 3D77 +ND70: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+24] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3D78 +ND78: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+24] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3D79 +ND79: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+24] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3D7A +ND7A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+24] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3D7B +ND7B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+24] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3D7C +ND7C: +mov cx,[esi] +add esi,byte 2 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+24] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3D80 - 3D87 +ND80: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +call decode_ext +add edx,[ebp+__areg+24] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3D88 - 3D8F +ND88: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +call decode_ext +add edx,[ebp+__areg+24] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3D90 - 3D97 +ND90: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +call decode_ext +add edx,[ebp+__areg+24] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3D98 - 3D9F +ND98: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +call decode_ext +add edx,[ebp+__areg+24] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3DA0 - 3DA7 +NDA0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +call decode_ext +add edx,[ebp+__areg+24] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3DA8 - 3DAF +NDA8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +call decode_ext +add edx,[ebp+__areg+24] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3DB0 - 3DB7 +NDB0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +call decode_ext +add edx,[ebp+__areg+24] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3DB8 +NDB8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +call decode_ext +add edx,[ebp+__areg+24] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3DB9 +NDB9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +call decode_ext +add edx,[ebp+__areg+24] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3DBA +NDBA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +call decode_ext +add edx,[ebp+__areg+24] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3DBB +NDBB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +call decode_ext +add edx,[ebp+__areg+24] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3DBC +NDBC: +mov cx,[esi] +add esi,byte 2 +call decode_ext +add edx,[ebp+__areg+24] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3E00 - 3E07 +NE00: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+28],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3E08 - 3E0F +NE08: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov [ebp+__dreg+28],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3E10 - 3E17 +NE10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov [ebp+__dreg+28],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3E18 - 3E1F +NE18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov [ebp+__dreg+28],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3E20 - 3E27 +NE20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov [ebp+__dreg+28],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3E28 - 3E2F +NE28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov [ebp+__dreg+28],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3E30 - 3E37 +NE30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov [ebp+__dreg+28],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3E38 +NE38: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +mov [ebp+__dreg+28],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3E39 +NE39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +mov [ebp+__dreg+28],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3E3A +NE3A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +mov [ebp+__dreg+28],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3E3B +NE3B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +mov [ebp+__dreg+28],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3E3C +NE3C: +mov cx,[esi] +add esi,byte 2 +mov [ebp+__dreg+28],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3E40 - 3E47 +NE40: +and ebx,byte 7 +movsx ecx,word[ebp+__dreg+ebx*4] +mov [ebp+__areg+28],ecx +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3E48 - 3E4F +NE48: +and ebx,byte 7 +movsx ecx,word[ebp+__areg+ebx*4] +mov [ebp+__areg+28],ecx +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3E50 - 3E57 +NE50: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+28],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3E58 - 3E5F +NE58: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov [ebp+__areg+28],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3E60 - 3E67 +NE60: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+ebx*4],edx +mov [ebp+__areg+28],ecx +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3E68 - 3E6F +NE68: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+28],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3E70 - 3E77 +NE70: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+28],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3E78 +NE78: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+28],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3E79 +NE79: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+28],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3E7A +NE7A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+28],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3E7B +NE7B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+28],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3E7C +NE7C: +movsx ecx,word[esi] +add esi,byte 2 +mov [ebp+__areg+28],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3E80 - 3E87 +NE80: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+28] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3E88 - 3E8F +NE88: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+28] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3E90 - 3E97 +NE90: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+28] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3E98 - 3E9F +NE98: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+28] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3EA0 - 3EA7 +NEA0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+28] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3EA8 - 3EAF +NEA8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+28] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3EB0 - 3EB7 +NEB0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+28] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3EB8 +NEB8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +mov edx,[ebp+__areg+28] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3EB9 +NEB9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +mov edx,[ebp+__areg+28] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3EBA +NEBA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +mov edx,[ebp+__areg+28] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3EBB +NEBB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +mov edx,[ebp+__areg+28] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3EBC +NEBC: +mov cx,[esi] +add esi,byte 2 +mov edx,[ebp+__areg+28] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3EC0 - 3EC7 +NEC0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+28] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+28],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3EC8 - 3ECF +NEC8: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+28] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+28],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3ED0 - 3ED7 +NED0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+28] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+28],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3ED8 - 3EDF +NED8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+28] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+28],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3EE0 - 3EE7 +NEE0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+28] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+28],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3EE8 - 3EEF +NEE8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+28] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+28],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3EF0 - 3EF7 +NEF0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+28] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+28],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3EF8 +NEF8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +mov edx,[ebp+__areg+28] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+28],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3EF9 +NEF9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +mov edx,[ebp+__areg+28] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+28],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3EFA +NEFA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +mov edx,[ebp+__areg+28] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+28],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3EFB +NEFB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +mov edx,[ebp+__areg+28] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+28],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3EFC +NEFC: +mov cx,[esi] +add esi,byte 2 +mov edx,[ebp+__areg+28] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+28],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3F00 - 3F07 +NF00: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov edx,[ebp+__areg+28] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+28],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3F08 - 3F0F +NF08: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+28] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+28],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3F10 - 3F17 +NF10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+28] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+28],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3F18 - 3F1F +NF18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+28] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+28],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3F20 - 3F27 +NF20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov edx,[ebp+__areg+28] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+28],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3F28 - 3F2F +NF28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+28] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+28],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3F30 - 3F37 +NF30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov edx,[ebp+__areg+28] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+28],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3F38 +NF38: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +mov edx,[ebp+__areg+28] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+28],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3F39 +NF39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +mov edx,[ebp+__areg+28] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+28],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3F3A +NF3A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +mov edx,[ebp+__areg+28] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+28],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3F3B +NF3B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +mov edx,[ebp+__areg+28] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+28],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3F3C +NF3C: +mov cx,[esi] +add esi,byte 2 +mov edx,[ebp+__areg+28] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+28],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3F40 - 3F47 +NF40: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+28] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3F48 - 3F4F +NF48: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+28] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3F50 - 3F57 +NF50: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+28] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3F58 - 3F5F +NF58: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+28] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3F60 - 3F67 +NF60: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+28] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3F68 - 3F6F +NF68: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+28] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3F70 - 3F77 +NF70: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+28] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3F78 +NF78: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+28] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3F79 +NF79: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+28] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3F7A +NF7A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+28] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3F7B +NF7B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+28] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3F7C +NF7C: +mov cx,[esi] +add esi,byte 2 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+28] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3F80 - 3F87 +NF80: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +call decode_ext +add edx,[ebp+__areg+28] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3F88 - 3F8F +NF88: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +call decode_ext +add edx,[ebp+__areg+28] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3F90 - 3F97 +NF90: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +call decode_ext +add edx,[ebp+__areg+28] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3F98 - 3F9F +NF98: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +call decode_ext +add edx,[ebp+__areg+28] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3FA0 - 3FA7 +NFA0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +call decode_ext +add edx,[ebp+__areg+28] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3FA8 - 3FAF +NFA8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +call decode_ext +add edx,[ebp+__areg+28] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 3FB0 - 3FB7 +NFB0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +call decode_ext +add edx,[ebp+__areg+28] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3FB8 +NFB8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +call decode_ext +add edx,[ebp+__areg+28] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3FB9 +NFB9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +call decode_ext +add edx,[ebp+__areg+28] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3FBA +NFBA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +call decode_ext +add edx,[ebp+__areg+28] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3FBB +NFBB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +call decode_ext +add edx,[ebp+__areg+28] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 3FBC +NFBC: +mov cx,[esi] +add esi,byte 2 +call decode_ext +add edx,[ebp+__areg+28] +call writememoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4000 - 4007 +O000: +and ebx,byte 7 +mov cl,[ebp+__xflag] +shr cl,1 +mov cl,0 +sbb cl,[ebp+__dreg+ebx*4] +mov edx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln641 +or dh,0BFh +and ah,dh +ln641: +mov [ebp+__dreg+ebx*4],cl +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4010 - 4017 +O010: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +push ebx +mov bl,[ebp+__xflag] +shr bl,1 +mov bl,0 +sbb bl,cl +mov ecx,ebx +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln642 +or bh,0BFh +and ah,bh +ln642: +pop ebx +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4018 - 401F +O018: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +push ebx +mov bl,[ebp+__xflag] +shr bl,1 +mov bl,0 +sbb bl,cl +mov ecx,ebx +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln643 +or bh,0BFh +and ah,bh +ln643: +pop ebx +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4020 - 4027 +O020: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +push ebx +mov bl,[ebp+__xflag] +shr bl,1 +mov bl,0 +sbb bl,cl +mov ecx,ebx +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln644 +or bh,0BFh +and ah,bh +ln644: +pop ebx +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4028 - 402F +O028: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +push ebx +mov bl,[ebp+__xflag] +shr bl,1 +mov bl,0 +sbb bl,cl +mov ecx,ebx +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln645 +or bh,0BFh +and ah,bh +ln645: +pop ebx +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4030 - 4037 +O030: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +push ebx +mov bl,[ebp+__xflag] +shr bl,1 +mov bl,0 +sbb bl,cl +mov ecx,ebx +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln646 +or bh,0BFh +and ah,bh +ln646: +pop ebx +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4038 +O038: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +push ebx +mov bl,[ebp+__xflag] +shr bl,1 +mov bl,0 +sbb bl,cl +mov ecx,ebx +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln647 +or bh,0BFh +and ah,bh +ln647: +pop ebx +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4039 +O039: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +push ebx +mov bl,[ebp+__xflag] +shr bl,1 +mov bl,0 +sbb bl,cl +mov ecx,ebx +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln648 +or bh,0BFh +and ah,bh +ln648: +pop ebx +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4040 - 4047 +O040: +and ebx,byte 7 +mov cl,[ebp+__xflag] +shr cl,1 +mov ecx,0 +sbb cx,[ebp+__dreg+ebx*4] +mov edx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln649 +or dh,0BFh +and ah,dh +ln649: +mov [ebp+__dreg+ebx*4],cx +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4050 - 4057 +O050: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +push ebx +mov bl,[ebp+__xflag] +shr bl,1 +mov ebx,0 +sbb bx,cx +mov ecx,ebx +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln650 +or bh,0BFh +and ah,bh +ln650: +pop ebx +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4058 - 405F +O058: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +push ebx +mov bl,[ebp+__xflag] +shr bl,1 +mov ebx,0 +sbb bx,cx +mov ecx,ebx +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln651 +or bh,0BFh +and ah,bh +ln651: +pop ebx +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4060 - 4067 +O060: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +push ebx +mov bl,[ebp+__xflag] +shr bl,1 +mov ebx,0 +sbb bx,cx +mov ecx,ebx +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln652 +or bh,0BFh +and ah,bh +ln652: +pop ebx +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4068 - 406F +O068: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +push ebx +mov bl,[ebp+__xflag] +shr bl,1 +mov ebx,0 +sbb bx,cx +mov ecx,ebx +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln653 +or bh,0BFh +and ah,bh +ln653: +pop ebx +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4070 - 4077 +O070: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +push ebx +mov bl,[ebp+__xflag] +shr bl,1 +mov ebx,0 +sbb bx,cx +mov ecx,ebx +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln654 +or bh,0BFh +and ah,bh +ln654: +pop ebx +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4078 +O078: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +push ebx +mov bl,[ebp+__xflag] +shr bl,1 +mov ebx,0 +sbb bx,cx +mov ecx,ebx +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln655 +or bh,0BFh +and ah,bh +ln655: +pop ebx +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4079 +O079: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +push ebx +mov bl,[ebp+__xflag] +shr bl,1 +mov ebx,0 +sbb bx,cx +mov ecx,ebx +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln656 +or bh,0BFh +and ah,bh +ln656: +pop ebx +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4080 - 4087 +O080: +and ebx,byte 7 +mov cl,[ebp+__xflag] +shr cl,1 +mov ecx,0 +sbb ecx,[ebp+__dreg+ebx*4] +mov edx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln657 +or dh,0BFh +and ah,dh +ln657: +mov [ebp+__dreg+ebx*4],ecx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4090 - 4097 +O090: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +push ebx +mov bl,[ebp+__xflag] +shr bl,1 +mov ebx,0 +sbb ebx,ecx +mov ecx,ebx +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln658 +or bh,0BFh +and ah,bh +ln658: +pop ebx +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4098 - 409F +O098: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +push ebx +mov bl,[ebp+__xflag] +shr bl,1 +mov ebx,0 +sbb ebx,ecx +mov ecx,ebx +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln659 +or bh,0BFh +and ah,bh +ln659: +pop ebx +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 40A0 - 40A7 +O0A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +push ebx +mov bl,[ebp+__xflag] +shr bl,1 +mov ebx,0 +sbb ebx,ecx +mov ecx,ebx +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln660 +or bh,0BFh +and ah,bh +ln660: +pop ebx +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 40A8 - 40AF +O0A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +push ebx +mov bl,[ebp+__xflag] +shr bl,1 +mov ebx,0 +sbb ebx,ecx +mov ecx,ebx +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln661 +or bh,0BFh +and ah,bh +ln661: +pop ebx +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 40B0 - 40B7 +O0B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +push ebx +mov bl,[ebp+__xflag] +shr bl,1 +mov ebx,0 +sbb ebx,ecx +mov ecx,ebx +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln662 +or bh,0BFh +and ah,bh +ln662: +pop ebx +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 40B8 +O0B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +push ebx +mov bl,[ebp+__xflag] +shr bl,1 +mov ebx,0 +sbb ebx,ecx +mov ecx,ebx +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln663 +or bh,0BFh +and ah,bh +ln663: +pop ebx +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 40B9 +O0B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +push ebx +mov bl,[ebp+__xflag] +shr bl,1 +mov ebx,0 +sbb ebx,ecx +mov ecx,ebx +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln664 +or bh,0BFh +and ah,bh +ln664: +pop ebx +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 40C0 - 40C7 +O0C0: +and ebx,byte 7 +mov ch,[ebp+__xflag] +mov cl,ah +shr cx,6 +add cl,cl +or cl,al +mov ch,ah +shl ch,8 +adc cl,cl +mov ch,[ebp+__sr+1] +mov [ebp+__dreg+ebx*4],cx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 40D0 - 40D7 +O0D0: +and ebx,byte 7 +mov ch,[ebp+__xflag] +mov cl,ah +shr cx,6 +add cl,cl +or cl,al +mov ch,ah +shl ch,8 +adc cl,cl +mov ch,[ebp+__sr+1] +mov edx,[ebp+__areg+ebx*4] +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 40D8 - 40DF +O0D8: +and ebx,byte 7 +mov ch,[ebp+__xflag] +mov cl,ah +shr cx,6 +add cl,cl +or cl,al +mov ch,ah +shl ch,8 +adc cl,cl +mov ch,[ebp+__sr+1] +mov edx,[ebp+__areg+ebx*4] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 40E0 - 40E7 +O0E0: +and ebx,byte 7 +mov ch,[ebp+__xflag] +mov cl,ah +shr cx,6 +add cl,cl +or cl,al +mov ch,ah +shl ch,8 +adc cl,cl +mov ch,[ebp+__sr+1] +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 40E8 - 40EF +O0E8: +and ebx,byte 7 +mov ch,[ebp+__xflag] +mov cl,ah +shr cx,6 +add cl,cl +or cl,al +mov ch,ah +shl ch,8 +adc cl,cl +mov ch,[ebp+__sr+1] +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 40F0 - 40F7 +O0F0: +and ebx,byte 7 +mov ch,[ebp+__xflag] +mov cl,ah +shr cx,6 +add cl,cl +or cl,al +mov ch,ah +shl ch,8 +adc cl,cl +mov ch,[ebp+__sr+1] +call decode_ext +add edx,[ebp+__areg+ebx*4] +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 40F8 +O0F8: +mov ch,[ebp+__xflag] +mov cl,ah +shr cx,6 +add cl,cl +or cl,al +mov ch,ah +shl ch,8 +adc cl,cl +mov ch,[ebp+__sr+1] +movsx edx,word[esi] +add esi,byte 2 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 40F9 +O0F9: +mov ch,[ebp+__xflag] +mov cl,ah +shr cx,6 +add cl,cl +or cl,al +mov ch,ah +shl ch,8 +adc cl,cl +mov ch,[ebp+__sr+1] +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4100 - 4107 +O100: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +cmp word[ebp+__dreg+0],byte 0 +mov ax,8000h +jl short ln665 +cmp [ebp+__dreg+0],cx +mov ax,0 +jg short ln665 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln665:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln666 +cmp esi,[ebp+__fetch_region_end] +jbe short ln667 +ln666: +call basefunction +ln667: +add esi,[ebp+__io_fetchbase] +sub edi,byte 40 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4110 - 4117 +O110: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +cmp word[ebp+__dreg+0],byte 0 +mov ax,8000h +jl short ln668 +cmp [ebp+__dreg+0],cx +mov ax,0 +jg short ln668 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln668:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln669 +cmp esi,[ebp+__fetch_region_end] +jbe short ln670 +ln669: +call basefunction +ln670: +add esi,[ebp+__io_fetchbase] +sub edi,byte 44 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4118 - 411F +O118: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +cmp word[ebp+__dreg+0],byte 0 +mov ax,8000h +jl short ln671 +cmp [ebp+__dreg+0],cx +mov ax,0 +jg short ln671 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln671:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln672 +cmp esi,[ebp+__fetch_region_end] +jbe short ln673 +ln672: +call basefunction +ln673: +add esi,[ebp+__io_fetchbase] +sub edi,byte 44 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4120 - 4127 +O120: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +cmp word[ebp+__dreg+0],byte 0 +mov ax,8000h +jl short ln674 +cmp [ebp+__dreg+0],cx +mov ax,0 +jg short ln674 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln674:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln675 +cmp esi,[ebp+__fetch_region_end] +jbe short ln676 +ln675: +call basefunction +ln676: +add esi,[ebp+__io_fetchbase] +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4128 - 412F +O128: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +cmp word[ebp+__dreg+0],byte 0 +mov ax,8000h +jl short ln677 +cmp [ebp+__dreg+0],cx +mov ax,0 +jg short ln677 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln677:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln678 +cmp esi,[ebp+__fetch_region_end] +jbe short ln679 +ln678: +call basefunction +ln679: +add esi,[ebp+__io_fetchbase] +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4130 - 4137 +O130: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +cmp word[ebp+__dreg+0],byte 0 +mov ax,8000h +jl short ln680 +cmp [ebp+__dreg+0],cx +mov ax,0 +jg short ln680 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln680:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln681 +cmp esi,[ebp+__fetch_region_end] +jbe short ln682 +ln681: +call basefunction +ln682: +add esi,[ebp+__io_fetchbase] +sub edi,byte 50 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4138 +O138: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +cmp word[ebp+__dreg+0],byte 0 +mov ax,8000h +jl short ln683 +cmp [ebp+__dreg+0],cx +mov ax,0 +jg short ln683 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln683:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln684 +cmp esi,[ebp+__fetch_region_end] +jbe short ln685 +ln684: +call basefunction +ln685: +add esi,[ebp+__io_fetchbase] +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4139 +O139: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +cmp word[ebp+__dreg+0],byte 0 +mov ax,8000h +jl short ln686 +cmp [ebp+__dreg+0],cx +mov ax,0 +jg short ln686 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln686:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln687 +cmp esi,[ebp+__fetch_region_end] +jbe short ln688 +ln687: +call basefunction +ln688: +add esi,[ebp+__io_fetchbase] +sub edi,byte 52 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 413A +O13A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +cmp word[ebp+__dreg+0],byte 0 +mov ax,8000h +jl short ln689 +cmp [ebp+__dreg+0],cx +mov ax,0 +jg short ln689 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln689:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln690 +cmp esi,[ebp+__fetch_region_end] +jbe short ln691 +ln690: +call basefunction +ln691: +add esi,[ebp+__io_fetchbase] +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 413B +O13B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +cmp word[ebp+__dreg+0],byte 0 +mov ax,8000h +jl short ln692 +cmp [ebp+__dreg+0],cx +mov ax,0 +jg short ln692 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln692:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln693 +cmp esi,[ebp+__fetch_region_end] +jbe short ln694 +ln693: +call basefunction +ln694: +add esi,[ebp+__io_fetchbase] +sub edi,byte 50 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 413C +O13C: +mov cx,[esi] +add esi,byte 2 +cmp word[ebp+__dreg+0],byte 0 +mov ax,8000h +jl short ln695 +cmp [ebp+__dreg+0],cx +mov ax,0 +jg short ln695 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln695:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln696 +cmp esi,[ebp+__fetch_region_end] +jbe short ln697 +ln696: +call basefunction +ln697: +add esi,[ebp+__io_fetchbase] +sub edi,byte 44 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 41D0 - 41D7 +O1D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +mov [ebp+__areg+0],edx +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 41E8 - 41EF +O1E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +mov [ebp+__areg+0],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 41F0 - 41F7 +O1F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +mov [ebp+__areg+0],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 41F8 +O1F8: +movsx edx,word[esi] +add esi,byte 2 +mov [ebp+__areg+0],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 41F9 +O1F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +mov [ebp+__areg+0],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 41FA +O1FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +mov [ebp+__areg+0],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 41FB +O1FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +mov [ebp+__areg+0],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4200 - 4207 +O200: +and ebx,byte 7 +xor ecx,ecx +mov [ebp+__dreg+ebx*4],cl +mov ax,4000h +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4210 - 4217 +O210: +and ebx,byte 7 +xor ecx,ecx +mov edx,[ebp+__areg+ebx*4] +call writememorybyte +mov ax,4000h +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4218 - 421F +O218: +and ebx,byte 7 +xor ecx,ecx +mov edx,[ebp+__areg+ebx*4] +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +mov ax,4000h +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4220 - 4227 +O220: +and ebx,byte 7 +xor ecx,ecx +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call writememorybyte +mov [ebp+__areg+ebx*4],edx +mov ax,4000h +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4228 - 422F +O228: +and ebx,byte 7 +xor ecx,ecx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call writememorybyte +mov ax,4000h +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4230 - 4237 +O230: +and ebx,byte 7 +xor ecx,ecx +call decode_ext +add edx,[ebp+__areg+ebx*4] +call writememorybyte +mov ax,4000h +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4238 +O238: +xor ecx,ecx +movsx edx,word[esi] +add esi,byte 2 +call writememorybyte +mov ax,4000h +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4239 +O239: +xor ecx,ecx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call writememorybyte +mov ax,4000h +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4240 - 4247 +O240: +and ebx,byte 7 +xor ecx,ecx +mov [ebp+__dreg+ebx*4],cx +mov ax,4000h +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4250 - 4257 +O250: +and ebx,byte 7 +xor ecx,ecx +mov edx,[ebp+__areg+ebx*4] +call writememoryword +mov ax,4000h +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4258 - 425F +O258: +and ebx,byte 7 +xor ecx,ecx +mov edx,[ebp+__areg+ebx*4] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov ax,4000h +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4260 - 4267 +O260: +and ebx,byte 7 +xor ecx,ecx +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call writememoryword +mov [ebp+__areg+ebx*4],edx +mov ax,4000h +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4268 - 426F +O268: +and ebx,byte 7 +xor ecx,ecx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call writememoryword +mov ax,4000h +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4270 - 4277 +O270: +and ebx,byte 7 +xor ecx,ecx +call decode_ext +add edx,[ebp+__areg+ebx*4] +call writememoryword +mov ax,4000h +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4278 +O278: +xor ecx,ecx +movsx edx,word[esi] +add esi,byte 2 +call writememoryword +mov ax,4000h +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4279 +O279: +xor ecx,ecx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call writememoryword +mov ax,4000h +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4280 - 4287 +O280: +and ebx,byte 7 +xor ecx,ecx +mov [ebp+__dreg+ebx*4],ecx +mov ax,4000h +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4290 - 4297 +O290: +and ebx,byte 7 +xor ecx,ecx +mov edx,[ebp+__areg+ebx*4] +call writememorydword +mov ax,4000h +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4298 - 429F +O298: +and ebx,byte 7 +xor ecx,ecx +mov edx,[ebp+__areg+ebx*4] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +mov ax,4000h +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 42A0 - 42A7 +O2A0: +and ebx,byte 7 +xor ecx,ecx +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+ebx*4],edx +mov ax,4000h +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 42A8 - 42AF +O2A8: +and ebx,byte 7 +xor ecx,ecx +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call writememorydword +mov ax,4000h +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 42B0 - 42B7 +O2B0: +and ebx,byte 7 +xor ecx,ecx +call decode_ext +add edx,[ebp+__areg+ebx*4] +call writememorydword +mov ax,4000h +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 42B8 +O2B8: +xor ecx,ecx +movsx edx,word[esi] +add esi,byte 2 +call writememorydword +mov ax,4000h +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 42B9 +O2B9: +xor ecx,ecx +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call writememorydword +mov ax,4000h +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4300 - 4307 +O300: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +cmp word[ebp+__dreg+4],byte 0 +mov ax,8000h +jl short ln698 +cmp [ebp+__dreg+4],cx +mov ax,0 +jg short ln698 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln698:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln699 +cmp esi,[ebp+__fetch_region_end] +jbe short ln700 +ln699: +call basefunction +ln700: +add esi,[ebp+__io_fetchbase] +sub edi,byte 40 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4310 - 4317 +O310: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +cmp word[ebp+__dreg+4],byte 0 +mov ax,8000h +jl short ln701 +cmp [ebp+__dreg+4],cx +mov ax,0 +jg short ln701 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln701:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln702 +cmp esi,[ebp+__fetch_region_end] +jbe short ln703 +ln702: +call basefunction +ln703: +add esi,[ebp+__io_fetchbase] +sub edi,byte 44 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4318 - 431F +O318: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +cmp word[ebp+__dreg+4],byte 0 +mov ax,8000h +jl short ln704 +cmp [ebp+__dreg+4],cx +mov ax,0 +jg short ln704 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln704:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln705 +cmp esi,[ebp+__fetch_region_end] +jbe short ln706 +ln705: +call basefunction +ln706: +add esi,[ebp+__io_fetchbase] +sub edi,byte 44 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4320 - 4327 +O320: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +cmp word[ebp+__dreg+4],byte 0 +mov ax,8000h +jl short ln707 +cmp [ebp+__dreg+4],cx +mov ax,0 +jg short ln707 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln707:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln708 +cmp esi,[ebp+__fetch_region_end] +jbe short ln709 +ln708: +call basefunction +ln709: +add esi,[ebp+__io_fetchbase] +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4328 - 432F +O328: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +cmp word[ebp+__dreg+4],byte 0 +mov ax,8000h +jl short ln710 +cmp [ebp+__dreg+4],cx +mov ax,0 +jg short ln710 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln710:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln711 +cmp esi,[ebp+__fetch_region_end] +jbe short ln712 +ln711: +call basefunction +ln712: +add esi,[ebp+__io_fetchbase] +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4330 - 4337 +O330: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +cmp word[ebp+__dreg+4],byte 0 +mov ax,8000h +jl short ln713 +cmp [ebp+__dreg+4],cx +mov ax,0 +jg short ln713 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln713:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln714 +cmp esi,[ebp+__fetch_region_end] +jbe short ln715 +ln714: +call basefunction +ln715: +add esi,[ebp+__io_fetchbase] +sub edi,byte 50 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4338 +O338: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +cmp word[ebp+__dreg+4],byte 0 +mov ax,8000h +jl short ln716 +cmp [ebp+__dreg+4],cx +mov ax,0 +jg short ln716 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln716:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln717 +cmp esi,[ebp+__fetch_region_end] +jbe short ln718 +ln717: +call basefunction +ln718: +add esi,[ebp+__io_fetchbase] +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4339 +O339: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +cmp word[ebp+__dreg+4],byte 0 +mov ax,8000h +jl short ln719 +cmp [ebp+__dreg+4],cx +mov ax,0 +jg short ln719 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln719:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln720 +cmp esi,[ebp+__fetch_region_end] +jbe short ln721 +ln720: +call basefunction +ln721: +add esi,[ebp+__io_fetchbase] +sub edi,byte 52 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 433A +O33A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +cmp word[ebp+__dreg+4],byte 0 +mov ax,8000h +jl short ln722 +cmp [ebp+__dreg+4],cx +mov ax,0 +jg short ln722 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln722:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln723 +cmp esi,[ebp+__fetch_region_end] +jbe short ln724 +ln723: +call basefunction +ln724: +add esi,[ebp+__io_fetchbase] +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 433B +O33B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +cmp word[ebp+__dreg+4],byte 0 +mov ax,8000h +jl short ln725 +cmp [ebp+__dreg+4],cx +mov ax,0 +jg short ln725 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln725:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln726 +cmp esi,[ebp+__fetch_region_end] +jbe short ln727 +ln726: +call basefunction +ln727: +add esi,[ebp+__io_fetchbase] +sub edi,byte 50 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 433C +O33C: +mov cx,[esi] +add esi,byte 2 +cmp word[ebp+__dreg+4],byte 0 +mov ax,8000h +jl short ln728 +cmp [ebp+__dreg+4],cx +mov ax,0 +jg short ln728 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln728:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln729 +cmp esi,[ebp+__fetch_region_end] +jbe short ln730 +ln729: +call basefunction +ln730: +add esi,[ebp+__io_fetchbase] +sub edi,byte 44 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 43D0 - 43D7 +O3D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +mov [ebp+__areg+4],edx +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 43E8 - 43EF +O3E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +mov [ebp+__areg+4],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 43F0 - 43F7 +O3F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +mov [ebp+__areg+4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 43F8 +O3F8: +movsx edx,word[esi] +add esi,byte 2 +mov [ebp+__areg+4],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 43F9 +O3F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +mov [ebp+__areg+4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 43FA +O3FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +mov [ebp+__areg+4],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 43FB +O3FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +mov [ebp+__areg+4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4400 - 4407 +O400: +and ebx,byte 7 +neg byte[ebp+__dreg+ebx*4] +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4410 - 4417 +O410: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +neg cl +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4418 - 441F +O418: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +neg cl +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4420 - 4427 +O420: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +neg cl +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4428 - 442F +O428: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +neg cl +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4430 - 4437 +O430: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +neg cl +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4438 +O438: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +neg cl +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4439 +O439: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +neg cl +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4440 - 4447 +O440: +and ebx,byte 7 +neg word[ebp+__dreg+ebx*4] +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4450 - 4457 +O450: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +neg cx +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4458 - 445F +O458: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +neg cx +lahf +seto al +setc [ebp+__xflag] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4460 - 4467 +O460: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +neg cx +lahf +seto al +setc [ebp+__xflag] +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4468 - 446F +O468: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +neg cx +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4470 - 4477 +O470: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +neg cx +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4478 +O478: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +neg cx +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4479 +O479: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +neg cx +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4480 - 4487 +O480: +and ebx,byte 7 +neg dword[ebp+__dreg+ebx*4] +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4490 - 4497 +O490: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +neg ecx +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4498 - 449F +O498: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +neg ecx +lahf +seto al +setc [ebp+__xflag] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 44A0 - 44A7 +O4A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +neg ecx +lahf +seto al +setc [ebp+__xflag] +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 44A8 - 44AF +O4A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +neg ecx +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 44B0 - 44B7 +O4B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +neg ecx +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 44B8 +O4B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +neg ecx +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 44B9 +O4B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +neg ecx +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 44C0 - 44C7 +O4C0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov al,cl +mov ah,al +and ax,0C10h +shl ah,3 +shr al,4 +mov [ebp+__xflag],al +mov al,cl +and al,3 +shr al,1 +adc ah,ah +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 44D0 - 44D7 +O4D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov al,cl +mov ah,al +and ax,0C10h +shl ah,3 +shr al,4 +mov [ebp+__xflag],al +mov al,cl +and al,3 +shr al,1 +adc ah,ah +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 44D8 - 44DF +O4D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov al,cl +mov ah,al +and ax,0C10h +shl ah,3 +shr al,4 +mov [ebp+__xflag],al +mov al,cl +and al,3 +shr al,1 +adc ah,ah +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 44E0 - 44E7 +O4E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov al,cl +mov ah,al +and ax,0C10h +shl ah,3 +shr al,4 +mov [ebp+__xflag],al +mov al,cl +and al,3 +shr al,1 +adc ah,ah +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 44E8 - 44EF +O4E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov al,cl +mov ah,al +and ax,0C10h +shl ah,3 +shr al,4 +mov [ebp+__xflag],al +mov al,cl +and al,3 +shr al,1 +adc ah,ah +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 44F0 - 44F7 +O4F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov al,cl +mov ah,al +and ax,0C10h +shl ah,3 +shr al,4 +mov [ebp+__xflag],al +mov al,cl +and al,3 +shr al,1 +adc ah,ah +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 44F8 +O4F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +mov al,cl +mov ah,al +and ax,0C10h +shl ah,3 +shr al,4 +mov [ebp+__xflag],al +mov al,cl +and al,3 +shr al,1 +adc ah,ah +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 44F9 +O4F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +mov al,cl +mov ah,al +and ax,0C10h +shl ah,3 +shr al,4 +mov [ebp+__xflag],al +mov al,cl +and al,3 +shr al,1 +adc ah,ah +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 44FA +O4FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +mov al,cl +mov ah,al +and ax,0C10h +shl ah,3 +shr al,4 +mov [ebp+__xflag],al +mov al,cl +and al,3 +shr al,1 +adc ah,ah +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 44FB +O4FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +mov al,cl +mov ah,al +and ax,0C10h +shl ah,3 +shr al,4 +mov [ebp+__xflag],al +mov al,cl +and al,3 +shr al,1 +adc ah,ah +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 44FC +O4FC: +mov cx,[esi] +add esi,byte 2 +mov al,cl +mov ah,al +and ax,0C10h +shl ah,3 +shr al,4 +mov [ebp+__xflag],al +mov al,cl +and al,3 +shr al,1 +adc ah,ah +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4500 - 4507 +O500: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +cmp word[ebp+__dreg+8],byte 0 +mov ax,8000h +jl short ln731 +cmp [ebp+__dreg+8],cx +mov ax,0 +jg short ln731 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln731:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln732 +cmp esi,[ebp+__fetch_region_end] +jbe short ln733 +ln732: +call basefunction +ln733: +add esi,[ebp+__io_fetchbase] +sub edi,byte 40 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4510 - 4517 +O510: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +cmp word[ebp+__dreg+8],byte 0 +mov ax,8000h +jl short ln734 +cmp [ebp+__dreg+8],cx +mov ax,0 +jg short ln734 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln734:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln735 +cmp esi,[ebp+__fetch_region_end] +jbe short ln736 +ln735: +call basefunction +ln736: +add esi,[ebp+__io_fetchbase] +sub edi,byte 44 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4518 - 451F +O518: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +cmp word[ebp+__dreg+8],byte 0 +mov ax,8000h +jl short ln737 +cmp [ebp+__dreg+8],cx +mov ax,0 +jg short ln737 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln737:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln738 +cmp esi,[ebp+__fetch_region_end] +jbe short ln739 +ln738: +call basefunction +ln739: +add esi,[ebp+__io_fetchbase] +sub edi,byte 44 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4520 - 4527 +O520: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +cmp word[ebp+__dreg+8],byte 0 +mov ax,8000h +jl short ln740 +cmp [ebp+__dreg+8],cx +mov ax,0 +jg short ln740 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln740:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln741 +cmp esi,[ebp+__fetch_region_end] +jbe short ln742 +ln741: +call basefunction +ln742: +add esi,[ebp+__io_fetchbase] +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4528 - 452F +O528: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +cmp word[ebp+__dreg+8],byte 0 +mov ax,8000h +jl short ln743 +cmp [ebp+__dreg+8],cx +mov ax,0 +jg short ln743 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln743:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln744 +cmp esi,[ebp+__fetch_region_end] +jbe short ln745 +ln744: +call basefunction +ln745: +add esi,[ebp+__io_fetchbase] +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4530 - 4537 +O530: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +cmp word[ebp+__dreg+8],byte 0 +mov ax,8000h +jl short ln746 +cmp [ebp+__dreg+8],cx +mov ax,0 +jg short ln746 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln746:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln747 +cmp esi,[ebp+__fetch_region_end] +jbe short ln748 +ln747: +call basefunction +ln748: +add esi,[ebp+__io_fetchbase] +sub edi,byte 50 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4538 +O538: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +cmp word[ebp+__dreg+8],byte 0 +mov ax,8000h +jl short ln749 +cmp [ebp+__dreg+8],cx +mov ax,0 +jg short ln749 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln749:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln750 +cmp esi,[ebp+__fetch_region_end] +jbe short ln751 +ln750: +call basefunction +ln751: +add esi,[ebp+__io_fetchbase] +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4539 +O539: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +cmp word[ebp+__dreg+8],byte 0 +mov ax,8000h +jl short ln752 +cmp [ebp+__dreg+8],cx +mov ax,0 +jg short ln752 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln752:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln753 +cmp esi,[ebp+__fetch_region_end] +jbe short ln754 +ln753: +call basefunction +ln754: +add esi,[ebp+__io_fetchbase] +sub edi,byte 52 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 453A +O53A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +cmp word[ebp+__dreg+8],byte 0 +mov ax,8000h +jl short ln755 +cmp [ebp+__dreg+8],cx +mov ax,0 +jg short ln755 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln755:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln756 +cmp esi,[ebp+__fetch_region_end] +jbe short ln757 +ln756: +call basefunction +ln757: +add esi,[ebp+__io_fetchbase] +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 453B +O53B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +cmp word[ebp+__dreg+8],byte 0 +mov ax,8000h +jl short ln758 +cmp [ebp+__dreg+8],cx +mov ax,0 +jg short ln758 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln758:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln759 +cmp esi,[ebp+__fetch_region_end] +jbe short ln760 +ln759: +call basefunction +ln760: +add esi,[ebp+__io_fetchbase] +sub edi,byte 50 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 453C +O53C: +mov cx,[esi] +add esi,byte 2 +cmp word[ebp+__dreg+8],byte 0 +mov ax,8000h +jl short ln761 +cmp [ebp+__dreg+8],cx +mov ax,0 +jg short ln761 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln761:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln762 +cmp esi,[ebp+__fetch_region_end] +jbe short ln763 +ln762: +call basefunction +ln763: +add esi,[ebp+__io_fetchbase] +sub edi,byte 44 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 45D0 - 45D7 +O5D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +mov [ebp+__areg+8],edx +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 45E8 - 45EF +O5E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +mov [ebp+__areg+8],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 45F0 - 45F7 +O5F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +mov [ebp+__areg+8],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 45F8 +O5F8: +movsx edx,word[esi] +add esi,byte 2 +mov [ebp+__areg+8],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 45F9 +O5F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +mov [ebp+__areg+8],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 45FA +O5FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +mov [ebp+__areg+8],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 45FB +O5FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +mov [ebp+__areg+8],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4600 - 4607 +O600: +and ebx,byte 7 +xor byte[ebp+__dreg+ebx*4],byte -1 +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4610 - 4617 +O610: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xor cl,byte -1 +lahf +mov al,0 +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4618 - 461F +O618: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xor cl,byte -1 +lahf +mov al,0 +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4620 - 4627 +O620: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +xor cl,byte -1 +lahf +mov al,0 +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4628 - 462F +O628: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xor cl,byte -1 +lahf +mov al,0 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4630 - 4637 +O630: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xor cl,byte -1 +lahf +mov al,0 +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4638 +O638: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +xor cl,byte -1 +lahf +mov al,0 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4639 +O639: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +xor cl,byte -1 +lahf +mov al,0 +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4640 - 4647 +O640: +and ebx,byte 7 +xor word[ebp+__dreg+ebx*4],byte -1 +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4650 - 4657 +O650: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +xor cx,byte -1 +lahf +mov al,0 +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4658 - 465F +O658: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +xor cx,byte -1 +lahf +mov al,0 +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4660 - 4667 +O660: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +xor cx,byte -1 +lahf +mov al,0 +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4668 - 466F +O668: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +xor cx,byte -1 +lahf +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4670 - 4677 +O670: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +xor cx,byte -1 +lahf +mov al,0 +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4678 +O678: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +xor cx,byte -1 +lahf +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4679 +O679: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +xor cx,byte -1 +lahf +mov al,0 +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4680 - 4687 +O680: +and ebx,byte 7 +xor dword[ebp+__dreg+ebx*4],byte -1 +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4690 - 4697 +O690: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +xor ecx,byte -1 +lahf +mov al,0 +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4698 - 469F +O698: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +xor ecx,byte -1 +lahf +mov al,0 +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 46A0 - 46A7 +O6A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +xor ecx,byte -1 +lahf +mov al,0 +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 46A8 - 46AF +O6A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +xor ecx,byte -1 +lahf +mov al,0 +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 46B0 - 46B7 +O6B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +xor ecx,byte -1 +lahf +mov al,0 +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 46B8 +O6B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +xor ecx,byte -1 +lahf +mov al,0 +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 46B9 +O6B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +xor ecx,byte -1 +lahf +mov al,0 +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 46C0 - 46C7 +O6C0: +test byte[ebp+__sr+1],20h +jz near privilege_violation +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +push ecx +mov cl,[ebp+__sr+1] +and cx,2020h +xor ch,cl +jz near ln764 +mov ecx,[ebp+__a7] +xchg ecx,[ebp+__asp] +mov [ebp+__a7],ecx +test byte[esp+1],20h +jz short ln765 +mov ecx,[ebp+__s_fetch] +mov [ebp+__fetch],ecx +mov ecx,[ebp+__s_readbyte] +mov [ebp+__readbyte],ecx +mov ecx,[ebp+__s_readword] +mov [ebp+__readword],ecx +mov ecx,[ebp+__s_writebyte] +mov [ebp+__writebyte],ecx +mov ecx,[ebp+__s_writeword] +mov [ebp+__writeword],ecx +jmp short ln764 +ln765: +mov ecx,[ebp+__u_fetch] +mov [ebp+__fetch],ecx +mov ecx,[ebp+__u_readbyte] +mov [ebp+__readbyte],ecx +mov ecx,[ebp+__u_readword] +mov [ebp+__readword],ecx +mov ecx,[ebp+__u_writebyte] +mov [ebp+__writebyte],ecx +mov ecx,[ebp+__u_writeword] +mov [ebp+__writeword],ecx +ln764: +pop ecx +mov [ebp+__sr+1],ch +and byte[ebp+__sr+1],0A7h +mov al,cl +mov ah,al +and ax,0C10h +shl ah,3 +shr al,4 +mov [ebp+__xflag],al +mov al,cl +and al,3 +shr al,1 +adc ah,ah +sub edi,byte 12 +jmp exec_checkpoint +; Opcodes 46D0 - 46D7 +O6D0: +test byte[ebp+__sr+1],20h +jz near privilege_violation +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +push ecx +mov cl,[ebp+__sr+1] +and cx,2020h +xor ch,cl +jz near ln766 +mov ecx,[ebp+__a7] +xchg ecx,[ebp+__asp] +mov [ebp+__a7],ecx +test byte[esp+1],20h +jz short ln767 +mov ecx,[ebp+__s_fetch] +mov [ebp+__fetch],ecx +mov ecx,[ebp+__s_readbyte] +mov [ebp+__readbyte],ecx +mov ecx,[ebp+__s_readword] +mov [ebp+__readword],ecx +mov ecx,[ebp+__s_writebyte] +mov [ebp+__writebyte],ecx +mov ecx,[ebp+__s_writeword] +mov [ebp+__writeword],ecx +jmp short ln766 +ln767: +mov ecx,[ebp+__u_fetch] +mov [ebp+__fetch],ecx +mov ecx,[ebp+__u_readbyte] +mov [ebp+__readbyte],ecx +mov ecx,[ebp+__u_readword] +mov [ebp+__readword],ecx +mov ecx,[ebp+__u_writebyte] +mov [ebp+__writebyte],ecx +mov ecx,[ebp+__u_writeword] +mov [ebp+__writeword],ecx +ln766: +pop ecx +mov [ebp+__sr+1],ch +and byte[ebp+__sr+1],0A7h +mov al,cl +mov ah,al +and ax,0C10h +shl ah,3 +shr al,4 +mov [ebp+__xflag],al +mov al,cl +and al,3 +shr al,1 +adc ah,ah +sub edi,byte 16 +jmp exec_checkpoint +; Opcodes 46D8 - 46DF +O6D8: +test byte[ebp+__sr+1],20h +jz near privilege_violation +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +push ecx +mov cl,[ebp+__sr+1] +and cx,2020h +xor ch,cl +jz near ln768 +mov ecx,[ebp+__a7] +xchg ecx,[ebp+__asp] +mov [ebp+__a7],ecx +test byte[esp+1],20h +jz short ln769 +mov ecx,[ebp+__s_fetch] +mov [ebp+__fetch],ecx +mov ecx,[ebp+__s_readbyte] +mov [ebp+__readbyte],ecx +mov ecx,[ebp+__s_readword] +mov [ebp+__readword],ecx +mov ecx,[ebp+__s_writebyte] +mov [ebp+__writebyte],ecx +mov ecx,[ebp+__s_writeword] +mov [ebp+__writeword],ecx +jmp short ln768 +ln769: +mov ecx,[ebp+__u_fetch] +mov [ebp+__fetch],ecx +mov ecx,[ebp+__u_readbyte] +mov [ebp+__readbyte],ecx +mov ecx,[ebp+__u_readword] +mov [ebp+__readword],ecx +mov ecx,[ebp+__u_writebyte] +mov [ebp+__writebyte],ecx +mov ecx,[ebp+__u_writeword] +mov [ebp+__writeword],ecx +ln768: +pop ecx +mov [ebp+__sr+1],ch +and byte[ebp+__sr+1],0A7h +mov al,cl +mov ah,al +and ax,0C10h +shl ah,3 +shr al,4 +mov [ebp+__xflag],al +mov al,cl +and al,3 +shr al,1 +adc ah,ah +sub edi,byte 16 +jmp exec_checkpoint +; Opcodes 46E0 - 46E7 +O6E0: +test byte[ebp+__sr+1],20h +jz near privilege_violation +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +push ecx +mov cl,[ebp+__sr+1] +and cx,2020h +xor ch,cl +jz near ln770 +mov ecx,[ebp+__a7] +xchg ecx,[ebp+__asp] +mov [ebp+__a7],ecx +test byte[esp+1],20h +jz short ln771 +mov ecx,[ebp+__s_fetch] +mov [ebp+__fetch],ecx +mov ecx,[ebp+__s_readbyte] +mov [ebp+__readbyte],ecx +mov ecx,[ebp+__s_readword] +mov [ebp+__readword],ecx +mov ecx,[ebp+__s_writebyte] +mov [ebp+__writebyte],ecx +mov ecx,[ebp+__s_writeword] +mov [ebp+__writeword],ecx +jmp short ln770 +ln771: +mov ecx,[ebp+__u_fetch] +mov [ebp+__fetch],ecx +mov ecx,[ebp+__u_readbyte] +mov [ebp+__readbyte],ecx +mov ecx,[ebp+__u_readword] +mov [ebp+__readword],ecx +mov ecx,[ebp+__u_writebyte] +mov [ebp+__writebyte],ecx +mov ecx,[ebp+__u_writeword] +mov [ebp+__writeword],ecx +ln770: +pop ecx +mov [ebp+__sr+1],ch +and byte[ebp+__sr+1],0A7h +mov al,cl +mov ah,al +and ax,0C10h +shl ah,3 +shr al,4 +mov [ebp+__xflag],al +mov al,cl +and al,3 +shr al,1 +adc ah,ah +sub edi,byte 18 +jmp exec_checkpoint +; Opcodes 46E8 - 46EF +O6E8: +test byte[ebp+__sr+1],20h +jz near privilege_violation +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +push ecx +mov cl,[ebp+__sr+1] +and cx,2020h +xor ch,cl +jz near ln772 +mov ecx,[ebp+__a7] +xchg ecx,[ebp+__asp] +mov [ebp+__a7],ecx +test byte[esp+1],20h +jz short ln773 +mov ecx,[ebp+__s_fetch] +mov [ebp+__fetch],ecx +mov ecx,[ebp+__s_readbyte] +mov [ebp+__readbyte],ecx +mov ecx,[ebp+__s_readword] +mov [ebp+__readword],ecx +mov ecx,[ebp+__s_writebyte] +mov [ebp+__writebyte],ecx +mov ecx,[ebp+__s_writeword] +mov [ebp+__writeword],ecx +jmp short ln772 +ln773: +mov ecx,[ebp+__u_fetch] +mov [ebp+__fetch],ecx +mov ecx,[ebp+__u_readbyte] +mov [ebp+__readbyte],ecx +mov ecx,[ebp+__u_readword] +mov [ebp+__readword],ecx +mov ecx,[ebp+__u_writebyte] +mov [ebp+__writebyte],ecx +mov ecx,[ebp+__u_writeword] +mov [ebp+__writeword],ecx +ln772: +pop ecx +mov [ebp+__sr+1],ch +and byte[ebp+__sr+1],0A7h +mov al,cl +mov ah,al +and ax,0C10h +shl ah,3 +shr al,4 +mov [ebp+__xflag],al +mov al,cl +and al,3 +shr al,1 +adc ah,ah +sub edi,byte 20 +jmp exec_checkpoint +; Opcodes 46F0 - 46F7 +O6F0: +test byte[ebp+__sr+1],20h +jz near privilege_violation +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +push ecx +mov cl,[ebp+__sr+1] +and cx,2020h +xor ch,cl +jz near ln774 +mov ecx,[ebp+__a7] +xchg ecx,[ebp+__asp] +mov [ebp+__a7],ecx +test byte[esp+1],20h +jz short ln775 +mov ecx,[ebp+__s_fetch] +mov [ebp+__fetch],ecx +mov ecx,[ebp+__s_readbyte] +mov [ebp+__readbyte],ecx +mov ecx,[ebp+__s_readword] +mov [ebp+__readword],ecx +mov ecx,[ebp+__s_writebyte] +mov [ebp+__writebyte],ecx +mov ecx,[ebp+__s_writeword] +mov [ebp+__writeword],ecx +jmp short ln774 +ln775: +mov ecx,[ebp+__u_fetch] +mov [ebp+__fetch],ecx +mov ecx,[ebp+__u_readbyte] +mov [ebp+__readbyte],ecx +mov ecx,[ebp+__u_readword] +mov [ebp+__readword],ecx +mov ecx,[ebp+__u_writebyte] +mov [ebp+__writebyte],ecx +mov ecx,[ebp+__u_writeword] +mov [ebp+__writeword],ecx +ln774: +pop ecx +mov [ebp+__sr+1],ch +and byte[ebp+__sr+1],0A7h +mov al,cl +mov ah,al +and ax,0C10h +shl ah,3 +shr al,4 +mov [ebp+__xflag],al +mov al,cl +and al,3 +shr al,1 +adc ah,ah +sub edi,byte 22 +jmp exec_checkpoint +; Opcode 46F8 +O6F8: +test byte[ebp+__sr+1],20h +jz near privilege_violation +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +push ecx +mov cl,[ebp+__sr+1] +and cx,2020h +xor ch,cl +jz near ln776 +mov ecx,[ebp+__a7] +xchg ecx,[ebp+__asp] +mov [ebp+__a7],ecx +test byte[esp+1],20h +jz short ln777 +mov ecx,[ebp+__s_fetch] +mov [ebp+__fetch],ecx +mov ecx,[ebp+__s_readbyte] +mov [ebp+__readbyte],ecx +mov ecx,[ebp+__s_readword] +mov [ebp+__readword],ecx +mov ecx,[ebp+__s_writebyte] +mov [ebp+__writebyte],ecx +mov ecx,[ebp+__s_writeword] +mov [ebp+__writeword],ecx +jmp short ln776 +ln777: +mov ecx,[ebp+__u_fetch] +mov [ebp+__fetch],ecx +mov ecx,[ebp+__u_readbyte] +mov [ebp+__readbyte],ecx +mov ecx,[ebp+__u_readword] +mov [ebp+__readword],ecx +mov ecx,[ebp+__u_writebyte] +mov [ebp+__writebyte],ecx +mov ecx,[ebp+__u_writeword] +mov [ebp+__writeword],ecx +ln776: +pop ecx +mov [ebp+__sr+1],ch +and byte[ebp+__sr+1],0A7h +mov al,cl +mov ah,al +and ax,0C10h +shl ah,3 +shr al,4 +mov [ebp+__xflag],al +mov al,cl +and al,3 +shr al,1 +adc ah,ah +sub edi,byte 20 +jmp exec_checkpoint +; Opcode 46F9 +O6F9: +test byte[ebp+__sr+1],20h +jz near privilege_violation +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +push ecx +mov cl,[ebp+__sr+1] +and cx,2020h +xor ch,cl +jz near ln778 +mov ecx,[ebp+__a7] +xchg ecx,[ebp+__asp] +mov [ebp+__a7],ecx +test byte[esp+1],20h +jz short ln779 +mov ecx,[ebp+__s_fetch] +mov [ebp+__fetch],ecx +mov ecx,[ebp+__s_readbyte] +mov [ebp+__readbyte],ecx +mov ecx,[ebp+__s_readword] +mov [ebp+__readword],ecx +mov ecx,[ebp+__s_writebyte] +mov [ebp+__writebyte],ecx +mov ecx,[ebp+__s_writeword] +mov [ebp+__writeword],ecx +jmp short ln778 +ln779: +mov ecx,[ebp+__u_fetch] +mov [ebp+__fetch],ecx +mov ecx,[ebp+__u_readbyte] +mov [ebp+__readbyte],ecx +mov ecx,[ebp+__u_readword] +mov [ebp+__readword],ecx +mov ecx,[ebp+__u_writebyte] +mov [ebp+__writebyte],ecx +mov ecx,[ebp+__u_writeword] +mov [ebp+__writeword],ecx +ln778: +pop ecx +mov [ebp+__sr+1],ch +and byte[ebp+__sr+1],0A7h +mov al,cl +mov ah,al +and ax,0C10h +shl ah,3 +shr al,4 +mov [ebp+__xflag],al +mov al,cl +and al,3 +shr al,1 +adc ah,ah +sub edi,byte 24 +jmp exec_checkpoint +; Opcode 46FA +O6FA: +test byte[ebp+__sr+1],20h +jz near privilege_violation +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +push ecx +mov cl,[ebp+__sr+1] +and cx,2020h +xor ch,cl +jz near ln780 +mov ecx,[ebp+__a7] +xchg ecx,[ebp+__asp] +mov [ebp+__a7],ecx +test byte[esp+1],20h +jz short ln781 +mov ecx,[ebp+__s_fetch] +mov [ebp+__fetch],ecx +mov ecx,[ebp+__s_readbyte] +mov [ebp+__readbyte],ecx +mov ecx,[ebp+__s_readword] +mov [ebp+__readword],ecx +mov ecx,[ebp+__s_writebyte] +mov [ebp+__writebyte],ecx +mov ecx,[ebp+__s_writeword] +mov [ebp+__writeword],ecx +jmp short ln780 +ln781: +mov ecx,[ebp+__u_fetch] +mov [ebp+__fetch],ecx +mov ecx,[ebp+__u_readbyte] +mov [ebp+__readbyte],ecx +mov ecx,[ebp+__u_readword] +mov [ebp+__readword],ecx +mov ecx,[ebp+__u_writebyte] +mov [ebp+__writebyte],ecx +mov ecx,[ebp+__u_writeword] +mov [ebp+__writeword],ecx +ln780: +pop ecx +mov [ebp+__sr+1],ch +and byte[ebp+__sr+1],0A7h +mov al,cl +mov ah,al +and ax,0C10h +shl ah,3 +shr al,4 +mov [ebp+__xflag],al +mov al,cl +and al,3 +shr al,1 +adc ah,ah +sub edi,byte 20 +jmp exec_checkpoint +; Opcode 46FB +O6FB: +test byte[ebp+__sr+1],20h +jz near privilege_violation +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +push ecx +mov cl,[ebp+__sr+1] +and cx,2020h +xor ch,cl +jz near ln782 +mov ecx,[ebp+__a7] +xchg ecx,[ebp+__asp] +mov [ebp+__a7],ecx +test byte[esp+1],20h +jz short ln783 +mov ecx,[ebp+__s_fetch] +mov [ebp+__fetch],ecx +mov ecx,[ebp+__s_readbyte] +mov [ebp+__readbyte],ecx +mov ecx,[ebp+__s_readword] +mov [ebp+__readword],ecx +mov ecx,[ebp+__s_writebyte] +mov [ebp+__writebyte],ecx +mov ecx,[ebp+__s_writeword] +mov [ebp+__writeword],ecx +jmp short ln782 +ln783: +mov ecx,[ebp+__u_fetch] +mov [ebp+__fetch],ecx +mov ecx,[ebp+__u_readbyte] +mov [ebp+__readbyte],ecx +mov ecx,[ebp+__u_readword] +mov [ebp+__readword],ecx +mov ecx,[ebp+__u_writebyte] +mov [ebp+__writebyte],ecx +mov ecx,[ebp+__u_writeword] +mov [ebp+__writeword],ecx +ln782: +pop ecx +mov [ebp+__sr+1],ch +and byte[ebp+__sr+1],0A7h +mov al,cl +mov ah,al +and ax,0C10h +shl ah,3 +shr al,4 +mov [ebp+__xflag],al +mov al,cl +and al,3 +shr al,1 +adc ah,ah +sub edi,byte 22 +jmp exec_checkpoint +; Opcode 46FC +O6FC: +test byte[ebp+__sr+1],20h +jz near privilege_violation +mov cx,[esi] +add esi,byte 2 +push ecx +mov cl,[ebp+__sr+1] +and cx,2020h +xor ch,cl +jz near ln784 +mov ecx,[ebp+__a7] +xchg ecx,[ebp+__asp] +mov [ebp+__a7],ecx +test byte[esp+1],20h +jz short ln785 +mov ecx,[ebp+__s_fetch] +mov [ebp+__fetch],ecx +mov ecx,[ebp+__s_readbyte] +mov [ebp+__readbyte],ecx +mov ecx,[ebp+__s_readword] +mov [ebp+__readword],ecx +mov ecx,[ebp+__s_writebyte] +mov [ebp+__writebyte],ecx +mov ecx,[ebp+__s_writeword] +mov [ebp+__writeword],ecx +jmp short ln784 +ln785: +mov ecx,[ebp+__u_fetch] +mov [ebp+__fetch],ecx +mov ecx,[ebp+__u_readbyte] +mov [ebp+__readbyte],ecx +mov ecx,[ebp+__u_readword] +mov [ebp+__readword],ecx +mov ecx,[ebp+__u_writebyte] +mov [ebp+__writebyte],ecx +mov ecx,[ebp+__u_writeword] +mov [ebp+__writeword],ecx +ln784: +pop ecx +mov [ebp+__sr+1],ch +and byte[ebp+__sr+1],0A7h +mov al,cl +mov ah,al +and ax,0C10h +shl ah,3 +shr al,4 +mov [ebp+__xflag],al +mov al,cl +and al,3 +shr al,1 +adc ah,ah +sub edi,byte 16 +jmp exec_checkpoint +; Opcodes 4700 - 4707 +O700: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +cmp word[ebp+__dreg+12],byte 0 +mov ax,8000h +jl short ln786 +cmp [ebp+__dreg+12],cx +mov ax,0 +jg short ln786 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln786:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln787 +cmp esi,[ebp+__fetch_region_end] +jbe short ln788 +ln787: +call basefunction +ln788: +add esi,[ebp+__io_fetchbase] +sub edi,byte 40 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4710 - 4717 +O710: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +cmp word[ebp+__dreg+12],byte 0 +mov ax,8000h +jl short ln789 +cmp [ebp+__dreg+12],cx +mov ax,0 +jg short ln789 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln789:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln790 +cmp esi,[ebp+__fetch_region_end] +jbe short ln791 +ln790: +call basefunction +ln791: +add esi,[ebp+__io_fetchbase] +sub edi,byte 44 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4718 - 471F +O718: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +cmp word[ebp+__dreg+12],byte 0 +mov ax,8000h +jl short ln792 +cmp [ebp+__dreg+12],cx +mov ax,0 +jg short ln792 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln792:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln793 +cmp esi,[ebp+__fetch_region_end] +jbe short ln794 +ln793: +call basefunction +ln794: +add esi,[ebp+__io_fetchbase] +sub edi,byte 44 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4720 - 4727 +O720: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +cmp word[ebp+__dreg+12],byte 0 +mov ax,8000h +jl short ln795 +cmp [ebp+__dreg+12],cx +mov ax,0 +jg short ln795 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln795:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln796 +cmp esi,[ebp+__fetch_region_end] +jbe short ln797 +ln796: +call basefunction +ln797: +add esi,[ebp+__io_fetchbase] +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4728 - 472F +O728: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +cmp word[ebp+__dreg+12],byte 0 +mov ax,8000h +jl short ln798 +cmp [ebp+__dreg+12],cx +mov ax,0 +jg short ln798 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln798:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln799 +cmp esi,[ebp+__fetch_region_end] +jbe short ln800 +ln799: +call basefunction +ln800: +add esi,[ebp+__io_fetchbase] +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4730 - 4737 +O730: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +cmp word[ebp+__dreg+12],byte 0 +mov ax,8000h +jl short ln801 +cmp [ebp+__dreg+12],cx +mov ax,0 +jg short ln801 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln801:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln802 +cmp esi,[ebp+__fetch_region_end] +jbe short ln803 +ln802: +call basefunction +ln803: +add esi,[ebp+__io_fetchbase] +sub edi,byte 50 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4738 +O738: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +cmp word[ebp+__dreg+12],byte 0 +mov ax,8000h +jl short ln804 +cmp [ebp+__dreg+12],cx +mov ax,0 +jg short ln804 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln804:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln805 +cmp esi,[ebp+__fetch_region_end] +jbe short ln806 +ln805: +call basefunction +ln806: +add esi,[ebp+__io_fetchbase] +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4739 +O739: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +cmp word[ebp+__dreg+12],byte 0 +mov ax,8000h +jl short ln807 +cmp [ebp+__dreg+12],cx +mov ax,0 +jg short ln807 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln807:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln808 +cmp esi,[ebp+__fetch_region_end] +jbe short ln809 +ln808: +call basefunction +ln809: +add esi,[ebp+__io_fetchbase] +sub edi,byte 52 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 473A +O73A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +cmp word[ebp+__dreg+12],byte 0 +mov ax,8000h +jl short ln810 +cmp [ebp+__dreg+12],cx +mov ax,0 +jg short ln810 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln810:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln811 +cmp esi,[ebp+__fetch_region_end] +jbe short ln812 +ln811: +call basefunction +ln812: +add esi,[ebp+__io_fetchbase] +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 473B +O73B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +cmp word[ebp+__dreg+12],byte 0 +mov ax,8000h +jl short ln813 +cmp [ebp+__dreg+12],cx +mov ax,0 +jg short ln813 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln813:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln814 +cmp esi,[ebp+__fetch_region_end] +jbe short ln815 +ln814: +call basefunction +ln815: +add esi,[ebp+__io_fetchbase] +sub edi,byte 50 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 473C +O73C: +mov cx,[esi] +add esi,byte 2 +cmp word[ebp+__dreg+12],byte 0 +mov ax,8000h +jl short ln816 +cmp [ebp+__dreg+12],cx +mov ax,0 +jg short ln816 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln816:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln817 +cmp esi,[ebp+__fetch_region_end] +jbe short ln818 +ln817: +call basefunction +ln818: +add esi,[ebp+__io_fetchbase] +sub edi,byte 44 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 47D0 - 47D7 +O7D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +mov [ebp+__areg+12],edx +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 47E8 - 47EF +O7E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +mov [ebp+__areg+12],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 47F0 - 47F7 +O7F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +mov [ebp+__areg+12],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 47F8 +O7F8: +movsx edx,word[esi] +add esi,byte 2 +mov [ebp+__areg+12],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 47F9 +O7F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +mov [ebp+__areg+12],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 47FA +O7FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +mov [ebp+__areg+12],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 47FB +O7FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +mov [ebp+__areg+12],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4800 - 4807 +O800: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov cl,[ebp+__xflag] +shr cl,1 +mov ch,ah +mov al,0 +sbb al,cl +das +mov cl,al +lahf +mov al,0 +setc [ebp+__xflag] +jnz short ln819 +or ch,0BFh +and ah,ch +ln819: +mov [ebp+__dreg+ebx*4],cl +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4810 - 4817 +O810: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov cl,[ebp+__xflag] +shr cl,1 +mov ch,ah +mov al,0 +sbb al,cl +das +mov cl,al +lahf +mov al,0 +setc [ebp+__xflag] +jnz short ln820 +or ch,0BFh +and ah,ch +ln820: +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4818 - 481F +O818: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov cl,[ebp+__xflag] +shr cl,1 +mov ch,ah +mov al,0 +sbb al,cl +das +mov cl,al +lahf +mov al,0 +setc [ebp+__xflag] +jnz short ln821 +or ch,0BFh +and ah,ch +ln821: +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4820 - 4827 +O820: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov cl,[ebp+__xflag] +shr cl,1 +mov ch,ah +mov al,0 +sbb al,cl +das +mov cl,al +lahf +mov al,0 +setc [ebp+__xflag] +jnz short ln822 +or ch,0BFh +and ah,ch +ln822: +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4828 - 482F +O828: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov cl,[ebp+__xflag] +shr cl,1 +mov ch,ah +mov al,0 +sbb al,cl +das +mov cl,al +lahf +mov al,0 +setc [ebp+__xflag] +jnz short ln823 +or ch,0BFh +and ah,ch +ln823: +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4830 - 4837 +O830: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +mov cl,[ebp+__xflag] +shr cl,1 +mov ch,ah +mov al,0 +sbb al,cl +das +mov cl,al +lahf +mov al,0 +setc [ebp+__xflag] +jnz short ln824 +or ch,0BFh +and ah,ch +ln824: +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4838 +O838: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +mov cl,[ebp+__xflag] +shr cl,1 +mov ch,ah +mov al,0 +sbb al,cl +das +mov cl,al +lahf +mov al,0 +setc [ebp+__xflag] +jnz short ln825 +or ch,0BFh +and ah,ch +ln825: +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4839 +O839: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +mov cl,[ebp+__xflag] +shr cl,1 +mov ch,ah +mov al,0 +sbb al,cl +das +mov cl,al +lahf +mov al,0 +setc [ebp+__xflag] +jnz short ln826 +or ch,0BFh +and ah,ch +ln826: +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4840 - 4847 +O840: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +rol ecx,16 +mov [ebp+__dreg+ebx*4],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4850 - 4857 +O850: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +mov ecx,edx +mov edx,[ebp+__areg+28] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+28],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4868 - 486F +O868: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +mov ecx,edx +mov edx,[ebp+__areg+28] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+28],edx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4870 - 4877 +O870: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +mov ecx,edx +mov edx,[ebp+__areg+28] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+28],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4878 +O878: +movsx edx,word[esi] +add esi,byte 2 +mov ecx,edx +mov edx,[ebp+__areg+28] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+28],edx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4879 +O879: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +mov ecx,edx +mov edx,[ebp+__areg+28] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+28],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 487A +O87A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +mov ecx,edx +mov edx,[ebp+__areg+28] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+28],edx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 487B +O87B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +mov ecx,edx +mov edx,[ebp+__areg+28] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+28],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4880 - 4887 +O880: +and ebx,byte 7 +movsx cx,byte[ebp+__dreg+ebx*4] +mov [ebp+__dreg+ebx*4],cx +test cx,cx +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4890 - 4897 +O890: +push eax +and ebx,byte 7 +mov ax,[esi] +add esi,byte 2 +mov edx,[ebp+__areg+ebx*4] +xor ebx,ebx +ln827: +shr eax,1 +jnc short ln828 +mov ecx,[ebp+__reg+ebx] +call writememoryword +add edx,byte 2 +sub edi,byte 4 +ln828: +add ebx,byte 4 +cmp ebx,byte 64 +jne short ln827 +pop eax +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 48A0 - 48A7 +O8A0: +and ebx,byte 7 +push eax +mov ax,[esi] +add esi,byte 2 +mov edx,[ebp+__areg+ebx*4] +push ebx +mov ebx,60 +ln829: +shr eax,1 +jnc short ln830 +mov ecx,[ebp+__reg+ebx] +sub edx,byte 2 +sub edi,byte 4 +call writememoryword +ln830: +sub ebx,byte 4 +jns short ln829 +pop ebx +pop eax +mov [ebp+__areg+ebx*4],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 48A8 - 48AF +O8A8: +push eax +and ebx,byte 7 +mov ax,[esi] +add esi,byte 2 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +xor ebx,ebx +ln831: +shr eax,1 +jnc short ln832 +mov ecx,[ebp+__reg+ebx] +call writememoryword +add edx,byte 2 +sub edi,byte 4 +ln832: +add ebx,byte 4 +cmp ebx,byte 64 +jne short ln831 +pop eax +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 48B0 - 48B7 +O8B0: +push eax +and ebx,byte 7 +mov ax,[esi] +add esi,byte 2 +call decode_ext +add edx,[ebp+__areg+ebx*4] +xor ebx,ebx +ln833: +shr eax,1 +jnc short ln834 +mov ecx,[ebp+__reg+ebx] +call writememoryword +add edx,byte 2 +sub edi,byte 4 +ln834: +add ebx,byte 4 +cmp ebx,byte 64 +jne short ln833 +pop eax +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 48B8 +O8B8: +push eax +mov ax,[esi] +add esi,byte 2 +movsx edx,word[esi] +add esi,byte 2 +xor ebx,ebx +ln835: +shr eax,1 +jnc short ln836 +mov ecx,[ebp+__reg+ebx] +call writememoryword +add edx,byte 2 +sub edi,byte 4 +ln836: +add ebx,byte 4 +cmp ebx,byte 64 +jne short ln835 +pop eax +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 48B9 +O8B9: +push eax +mov ax,[esi] +add esi,byte 2 +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +xor ebx,ebx +ln837: +shr eax,1 +jnc short ln838 +mov ecx,[ebp+__reg+ebx] +call writememoryword +add edx,byte 2 +sub edi,byte 4 +ln838: +add ebx,byte 4 +cmp ebx,byte 64 +jne short ln837 +pop eax +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 48C0 - 48C7 +O8C0: +and ebx,byte 7 +movsx ecx,word[ebp+__dreg+ebx*4] +mov [ebp+__dreg+ebx*4],ecx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 48D0 - 48D7 +O8D0: +push eax +and ebx,byte 7 +mov ax,[esi] +add esi,byte 2 +mov edx,[ebp+__areg+ebx*4] +xor ebx,ebx +ln839: +shr eax,1 +jnc short ln840 +mov ecx,[ebp+__reg+ebx] +call writememorydword +add edx,byte 4 +sub edi,byte 8 +ln840: +add ebx,byte 4 +cmp ebx,byte 64 +jne short ln839 +pop eax +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 48E0 - 48E7 +O8E0: +and ebx,byte 7 +push eax +mov ax,[esi] +add esi,byte 2 +mov edx,[ebp+__areg+ebx*4] +push ebx +mov ebx,60 +ln841: +shr eax,1 +jnc short ln842 +mov ecx,[ebp+__reg+ebx] +sub edx,byte 4 +sub edi,byte 8 +call writememorydword +ln842: +sub ebx,byte 4 +jns short ln841 +pop ebx +pop eax +mov [ebp+__areg+ebx*4],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 48E8 - 48EF +O8E8: +push eax +and ebx,byte 7 +mov ax,[esi] +add esi,byte 2 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +xor ebx,ebx +ln843: +shr eax,1 +jnc short ln844 +mov ecx,[ebp+__reg+ebx] +call writememorydword +add edx,byte 4 +sub edi,byte 8 +ln844: +add ebx,byte 4 +cmp ebx,byte 64 +jne short ln843 +pop eax +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 48F0 - 48F7 +O8F0: +push eax +and ebx,byte 7 +mov ax,[esi] +add esi,byte 2 +call decode_ext +add edx,[ebp+__areg+ebx*4] +xor ebx,ebx +ln845: +shr eax,1 +jnc short ln846 +mov ecx,[ebp+__reg+ebx] +call writememorydword +add edx,byte 4 +sub edi,byte 8 +ln846: +add ebx,byte 4 +cmp ebx,byte 64 +jne short ln845 +pop eax +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 48F8 +O8F8: +push eax +mov ax,[esi] +add esi,byte 2 +movsx edx,word[esi] +add esi,byte 2 +xor ebx,ebx +ln847: +shr eax,1 +jnc short ln848 +mov ecx,[ebp+__reg+ebx] +call writememorydword +add edx,byte 4 +sub edi,byte 8 +ln848: +add ebx,byte 4 +cmp ebx,byte 64 +jne short ln847 +pop eax +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 48F9 +O8F9: +push eax +mov ax,[esi] +add esi,byte 2 +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +xor ebx,ebx +ln849: +shr eax,1 +jnc short ln850 +mov ecx,[ebp+__reg+ebx] +call writememorydword +add edx,byte 4 +sub edi,byte 8 +ln850: +add ebx,byte 4 +cmp ebx,byte 64 +jne short ln849 +pop eax +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4900 - 4907 +O900: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +cmp word[ebp+__dreg+16],byte 0 +mov ax,8000h +jl short ln851 +cmp [ebp+__dreg+16],cx +mov ax,0 +jg short ln851 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln851:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln852 +cmp esi,[ebp+__fetch_region_end] +jbe short ln853 +ln852: +call basefunction +ln853: +add esi,[ebp+__io_fetchbase] +sub edi,byte 40 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4910 - 4917 +O910: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +cmp word[ebp+__dreg+16],byte 0 +mov ax,8000h +jl short ln854 +cmp [ebp+__dreg+16],cx +mov ax,0 +jg short ln854 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln854:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln855 +cmp esi,[ebp+__fetch_region_end] +jbe short ln856 +ln855: +call basefunction +ln856: +add esi,[ebp+__io_fetchbase] +sub edi,byte 44 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4918 - 491F +O918: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +cmp word[ebp+__dreg+16],byte 0 +mov ax,8000h +jl short ln857 +cmp [ebp+__dreg+16],cx +mov ax,0 +jg short ln857 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln857:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln858 +cmp esi,[ebp+__fetch_region_end] +jbe short ln859 +ln858: +call basefunction +ln859: +add esi,[ebp+__io_fetchbase] +sub edi,byte 44 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4920 - 4927 +O920: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +cmp word[ebp+__dreg+16],byte 0 +mov ax,8000h +jl short ln860 +cmp [ebp+__dreg+16],cx +mov ax,0 +jg short ln860 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln860:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln861 +cmp esi,[ebp+__fetch_region_end] +jbe short ln862 +ln861: +call basefunction +ln862: +add esi,[ebp+__io_fetchbase] +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4928 - 492F +O928: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +cmp word[ebp+__dreg+16],byte 0 +mov ax,8000h +jl short ln863 +cmp [ebp+__dreg+16],cx +mov ax,0 +jg short ln863 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln863:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln864 +cmp esi,[ebp+__fetch_region_end] +jbe short ln865 +ln864: +call basefunction +ln865: +add esi,[ebp+__io_fetchbase] +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4930 - 4937 +O930: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +cmp word[ebp+__dreg+16],byte 0 +mov ax,8000h +jl short ln866 +cmp [ebp+__dreg+16],cx +mov ax,0 +jg short ln866 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln866:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln867 +cmp esi,[ebp+__fetch_region_end] +jbe short ln868 +ln867: +call basefunction +ln868: +add esi,[ebp+__io_fetchbase] +sub edi,byte 50 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4938 +O938: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +cmp word[ebp+__dreg+16],byte 0 +mov ax,8000h +jl short ln869 +cmp [ebp+__dreg+16],cx +mov ax,0 +jg short ln869 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln869:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln870 +cmp esi,[ebp+__fetch_region_end] +jbe short ln871 +ln870: +call basefunction +ln871: +add esi,[ebp+__io_fetchbase] +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4939 +O939: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +cmp word[ebp+__dreg+16],byte 0 +mov ax,8000h +jl short ln872 +cmp [ebp+__dreg+16],cx +mov ax,0 +jg short ln872 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln872:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln873 +cmp esi,[ebp+__fetch_region_end] +jbe short ln874 +ln873: +call basefunction +ln874: +add esi,[ebp+__io_fetchbase] +sub edi,byte 52 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 493A +O93A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +cmp word[ebp+__dreg+16],byte 0 +mov ax,8000h +jl short ln875 +cmp [ebp+__dreg+16],cx +mov ax,0 +jg short ln875 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln875:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln876 +cmp esi,[ebp+__fetch_region_end] +jbe short ln877 +ln876: +call basefunction +ln877: +add esi,[ebp+__io_fetchbase] +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 493B +O93B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +cmp word[ebp+__dreg+16],byte 0 +mov ax,8000h +jl short ln878 +cmp [ebp+__dreg+16],cx +mov ax,0 +jg short ln878 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln878:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln879 +cmp esi,[ebp+__fetch_region_end] +jbe short ln880 +ln879: +call basefunction +ln880: +add esi,[ebp+__io_fetchbase] +sub edi,byte 50 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 493C +O93C: +mov cx,[esi] +add esi,byte 2 +cmp word[ebp+__dreg+16],byte 0 +mov ax,8000h +jl short ln881 +cmp [ebp+__dreg+16],cx +mov ax,0 +jg short ln881 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln881:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln882 +cmp esi,[ebp+__fetch_region_end] +jbe short ln883 +ln882: +call basefunction +ln883: +add esi,[ebp+__io_fetchbase] +sub edi,byte 44 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 49D0 - 49D7 +O9D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +mov [ebp+__areg+16],edx +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 49E8 - 49EF +O9E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +mov [ebp+__areg+16],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 49F0 - 49F7 +O9F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +mov [ebp+__areg+16],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 49F8 +O9F8: +movsx edx,word[esi] +add esi,byte 2 +mov [ebp+__areg+16],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 49F9 +O9F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +mov [ebp+__areg+16],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 49FA +O9FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +mov [ebp+__areg+16],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 49FB +O9FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +mov [ebp+__areg+16],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4A00 - 4A07 +OA00: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4A10 - 4A17 +OA10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4A18 - 4A1F +OA18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4A20 - 4A27 +OA20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +test cl,cl +lahf +mov al,0 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4A28 - 4A2F +OA28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4A30 - 4A37 +OA30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4A38 +OA38: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4A39 +OA39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +test cl,cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4A40 - 4A47 +OA40: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4A50 - 4A57 +OA50: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4A58 - 4A5F +OA58: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4A60 - 4A67 +OA60: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +test cx,cx +lahf +mov al,0 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4A68 - 4A6F +OA68: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4A70 - 4A77 +OA70: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4A78 +OA78: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4A79 +OA79: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +test cx,cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4A80 - 4A87 +OA80: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4A90 - 4A97 +OA90: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4A98 - 4A9F +OA98: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4AA0 - 4AA7 +OAA0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +test ecx,ecx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4AA8 - 4AAF +OAA8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4AB0 - 4AB7 +OAB0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4AB8 +OAB8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4AB9 +OAB9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +test ecx,ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4AC0 - 4AC7 +OAC0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +or cl,80h +mov [ebp+__dreg+ebx*4],cl +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4AD0 - 4AD7 +OAD0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +test cl,cl +lahf +mov al,0 +or cl,80h +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4AD8 - 4ADF +OAD8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +test cl,cl +lahf +mov al,0 +or cl,80h +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4AE0 - 4AE7 +OAE0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +test cl,cl +lahf +mov al,0 +or cl,80h +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4AE8 - 4AEF +OAE8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +test cl,cl +lahf +mov al,0 +or cl,80h +call writememorybyte +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4AF0 - 4AF7 +OAF0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +test cl,cl +lahf +mov al,0 +or cl,80h +call writememorybyte +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4AF8 +OAF8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +test cl,cl +lahf +mov al,0 +or cl,80h +call writememorybyte +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4AF9 +OAF9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +test cl,cl +lahf +mov al,0 +or cl,80h +call writememorybyte +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4AFA +OAFA: +r_illegal: +sub esi,byte 2 +mov edx,10h +call group_1_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln884 +cmp esi,[ebp+__fetch_region_end] +jbe short ln885 +ln884: +call basefunction +ln885: +add esi,[ebp+__io_fetchbase] +sub edi,byte 34 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4AFB +OAFB: +sub esi,byte 2 +mov edx,10h +call group_1_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln886 +cmp esi,[ebp+__fetch_region_end] +jbe short ln887 +ln886: +call basefunction +ln887: +add esi,[ebp+__io_fetchbase] +sub edi,byte 34 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4AFC +OAFC: +sub esi,byte 2 +mov edx,10h +call group_1_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln888 +cmp esi,[ebp+__fetch_region_end] +jbe short ln889 +ln888: +call basefunction +ln889: +add esi,[ebp+__io_fetchbase] +sub edi,byte 34 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4B00 - 4B07 +OB00: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +cmp word[ebp+__dreg+20],byte 0 +mov ax,8000h +jl short ln890 +cmp [ebp+__dreg+20],cx +mov ax,0 +jg short ln890 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln890:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln891 +cmp esi,[ebp+__fetch_region_end] +jbe short ln892 +ln891: +call basefunction +ln892: +add esi,[ebp+__io_fetchbase] +sub edi,byte 40 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4B10 - 4B17 +OB10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +cmp word[ebp+__dreg+20],byte 0 +mov ax,8000h +jl short ln893 +cmp [ebp+__dreg+20],cx +mov ax,0 +jg short ln893 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln893:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln894 +cmp esi,[ebp+__fetch_region_end] +jbe short ln895 +ln894: +call basefunction +ln895: +add esi,[ebp+__io_fetchbase] +sub edi,byte 44 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4B18 - 4B1F +OB18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +cmp word[ebp+__dreg+20],byte 0 +mov ax,8000h +jl short ln896 +cmp [ebp+__dreg+20],cx +mov ax,0 +jg short ln896 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln896:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln897 +cmp esi,[ebp+__fetch_region_end] +jbe short ln898 +ln897: +call basefunction +ln898: +add esi,[ebp+__io_fetchbase] +sub edi,byte 44 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4B20 - 4B27 +OB20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +cmp word[ebp+__dreg+20],byte 0 +mov ax,8000h +jl short ln899 +cmp [ebp+__dreg+20],cx +mov ax,0 +jg short ln899 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln899:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln900 +cmp esi,[ebp+__fetch_region_end] +jbe short ln901 +ln900: +call basefunction +ln901: +add esi,[ebp+__io_fetchbase] +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4B28 - 4B2F +OB28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +cmp word[ebp+__dreg+20],byte 0 +mov ax,8000h +jl short ln902 +cmp [ebp+__dreg+20],cx +mov ax,0 +jg short ln902 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln902:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln903 +cmp esi,[ebp+__fetch_region_end] +jbe short ln904 +ln903: +call basefunction +ln904: +add esi,[ebp+__io_fetchbase] +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4B30 - 4B37 +OB30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +cmp word[ebp+__dreg+20],byte 0 +mov ax,8000h +jl short ln905 +cmp [ebp+__dreg+20],cx +mov ax,0 +jg short ln905 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln905:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln906 +cmp esi,[ebp+__fetch_region_end] +jbe short ln907 +ln906: +call basefunction +ln907: +add esi,[ebp+__io_fetchbase] +sub edi,byte 50 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4B38 +OB38: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +cmp word[ebp+__dreg+20],byte 0 +mov ax,8000h +jl short ln908 +cmp [ebp+__dreg+20],cx +mov ax,0 +jg short ln908 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln908:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln909 +cmp esi,[ebp+__fetch_region_end] +jbe short ln910 +ln909: +call basefunction +ln910: +add esi,[ebp+__io_fetchbase] +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4B39 +OB39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +cmp word[ebp+__dreg+20],byte 0 +mov ax,8000h +jl short ln911 +cmp [ebp+__dreg+20],cx +mov ax,0 +jg short ln911 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln911:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln912 +cmp esi,[ebp+__fetch_region_end] +jbe short ln913 +ln912: +call basefunction +ln913: +add esi,[ebp+__io_fetchbase] +sub edi,byte 52 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4B3A +OB3A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +cmp word[ebp+__dreg+20],byte 0 +mov ax,8000h +jl short ln914 +cmp [ebp+__dreg+20],cx +mov ax,0 +jg short ln914 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln914:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln915 +cmp esi,[ebp+__fetch_region_end] +jbe short ln916 +ln915: +call basefunction +ln916: +add esi,[ebp+__io_fetchbase] +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4B3B +OB3B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +cmp word[ebp+__dreg+20],byte 0 +mov ax,8000h +jl short ln917 +cmp [ebp+__dreg+20],cx +mov ax,0 +jg short ln917 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln917:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln918 +cmp esi,[ebp+__fetch_region_end] +jbe short ln919 +ln918: +call basefunction +ln919: +add esi,[ebp+__io_fetchbase] +sub edi,byte 50 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4B3C +OB3C: +mov cx,[esi] +add esi,byte 2 +cmp word[ebp+__dreg+20],byte 0 +mov ax,8000h +jl short ln920 +cmp [ebp+__dreg+20],cx +mov ax,0 +jg short ln920 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln920:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln921 +cmp esi,[ebp+__fetch_region_end] +jbe short ln922 +ln921: +call basefunction +ln922: +add esi,[ebp+__io_fetchbase] +sub edi,byte 44 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4BD0 - 4BD7 +OBD0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +mov [ebp+__areg+20],edx +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4BE8 - 4BEF +OBE8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +mov [ebp+__areg+20],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4BF0 - 4BF7 +OBF0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +mov [ebp+__areg+20],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4BF8 +OBF8: +movsx edx,word[esi] +add esi,byte 2 +mov [ebp+__areg+20],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4BF9 +OBF9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +mov [ebp+__areg+20],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4BFA +OBFA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +mov [ebp+__areg+20],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4BFB +OBFB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +mov [ebp+__areg+20],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4C90 - 4C97 +OC90: +push eax +and ebx,byte 7 +mov ax,[esi] +add esi,byte 2 +mov edx,[ebp+__areg+ebx*4] +xor ebx,ebx +ln923: +shr eax,1 +jnc short ln924 +call readmemoryword +movsx ecx,cx +mov [ebp+__reg+ebx],ecx +add edx,byte 2 +sub edi,byte 4 +ln924: +add ebx,byte 4 +cmp ebx,byte 64 +jne short ln923 +pop eax +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4C98 - 4C9F +OC98: +and ebx,byte 7 +push eax +mov ax,[esi] +add esi,byte 2 +mov edx,[ebp+__areg+ebx*4] +push ebx +xor ebx,ebx +ln925: +shr eax,1 +jnc short ln926 +call readmemoryword +movsx ecx,cx +mov [ebp+__reg+ebx],ecx +add edx,byte 2 +sub edi,byte 4 +ln926: +add ebx,byte 4 +cmp ebx,byte 64 +jne short ln925 +pop ebx +pop eax +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4CA8 - 4CAF +OCA8: +push eax +and ebx,byte 7 +mov ax,[esi] +add esi,byte 2 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +xor ebx,ebx +ln927: +shr eax,1 +jnc short ln928 +call readmemoryword +movsx ecx,cx +mov [ebp+__reg+ebx],ecx +add edx,byte 2 +sub edi,byte 4 +ln928: +add ebx,byte 4 +cmp ebx,byte 64 +jne short ln927 +pop eax +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4CB0 - 4CB7 +OCB0: +push eax +and ebx,byte 7 +mov ax,[esi] +add esi,byte 2 +call decode_ext +add edx,[ebp+__areg+ebx*4] +xor ebx,ebx +ln929: +shr eax,1 +jnc short ln930 +call readmemoryword +movsx ecx,cx +mov [ebp+__reg+ebx],ecx +add edx,byte 2 +sub edi,byte 4 +ln930: +add ebx,byte 4 +cmp ebx,byte 64 +jne short ln929 +pop eax +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4CB8 +OCB8: +push eax +mov ax,[esi] +add esi,byte 2 +movsx edx,word[esi] +add esi,byte 2 +xor ebx,ebx +ln931: +shr eax,1 +jnc short ln932 +call readmemoryword +movsx ecx,cx +mov [ebp+__reg+ebx],ecx +add edx,byte 2 +sub edi,byte 4 +ln932: +add ebx,byte 4 +cmp ebx,byte 64 +jne short ln931 +pop eax +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4CB9 +OCB9: +push eax +mov ax,[esi] +add esi,byte 2 +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +xor ebx,ebx +ln933: +shr eax,1 +jnc short ln934 +call readmemoryword +movsx ecx,cx +mov [ebp+__reg+ebx],ecx +add edx,byte 2 +sub edi,byte 4 +ln934: +add ebx,byte 4 +cmp ebx,byte 64 +jne short ln933 +pop eax +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4CBA +OCBA: +push eax +mov ax,[esi] +add esi,byte 2 +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +xor ebx,ebx +ln935: +shr eax,1 +jnc short ln936 +call readmemoryword +movsx ecx,cx +mov [ebp+__reg+ebx],ecx +add edx,byte 2 +sub edi,byte 4 +ln936: +add ebx,byte 4 +cmp ebx,byte 64 +jne short ln935 +pop eax +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4CBB +OCBB: +push eax +mov ax,[esi] +add esi,byte 2 +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +xor ebx,ebx +ln937: +shr eax,1 +jnc short ln938 +call readmemoryword +movsx ecx,cx +mov [ebp+__reg+ebx],ecx +add edx,byte 2 +sub edi,byte 4 +ln938: +add ebx,byte 4 +cmp ebx,byte 64 +jne short ln937 +pop eax +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4CD0 - 4CD7 +OCD0: +push eax +and ebx,byte 7 +mov ax,[esi] +add esi,byte 2 +mov edx,[ebp+__areg+ebx*4] +xor ebx,ebx +ln939: +shr eax,1 +jnc short ln940 +call readmemorydword +mov [ebp+__reg+ebx],ecx +add edx,byte 4 +sub edi,byte 8 +ln940: +add ebx,byte 4 +cmp ebx,byte 64 +jne short ln939 +pop eax +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4CD8 - 4CDF +OCD8: +and ebx,byte 7 +push eax +mov ax,[esi] +add esi,byte 2 +mov edx,[ebp+__areg+ebx*4] +push ebx +xor ebx,ebx +ln941: +shr eax,1 +jnc short ln942 +call readmemorydword +mov [ebp+__reg+ebx],ecx +add edx,byte 4 +sub edi,byte 8 +ln942: +add ebx,byte 4 +cmp ebx,byte 64 +jne short ln941 +pop ebx +pop eax +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4CE8 - 4CEF +OCE8: +push eax +and ebx,byte 7 +mov ax,[esi] +add esi,byte 2 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +xor ebx,ebx +ln943: +shr eax,1 +jnc short ln944 +call readmemorydword +mov [ebp+__reg+ebx],ecx +add edx,byte 4 +sub edi,byte 8 +ln944: +add ebx,byte 4 +cmp ebx,byte 64 +jne short ln943 +pop eax +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4CF0 - 4CF7 +OCF0: +push eax +and ebx,byte 7 +mov ax,[esi] +add esi,byte 2 +call decode_ext +add edx,[ebp+__areg+ebx*4] +xor ebx,ebx +ln945: +shr eax,1 +jnc short ln946 +call readmemorydword +mov [ebp+__reg+ebx],ecx +add edx,byte 4 +sub edi,byte 8 +ln946: +add ebx,byte 4 +cmp ebx,byte 64 +jne short ln945 +pop eax +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4CF8 +OCF8: +push eax +mov ax,[esi] +add esi,byte 2 +movsx edx,word[esi] +add esi,byte 2 +xor ebx,ebx +ln947: +shr eax,1 +jnc short ln948 +call readmemorydword +mov [ebp+__reg+ebx],ecx +add edx,byte 4 +sub edi,byte 8 +ln948: +add ebx,byte 4 +cmp ebx,byte 64 +jne short ln947 +pop eax +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4CF9 +OCF9: +push eax +mov ax,[esi] +add esi,byte 2 +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +xor ebx,ebx +ln949: +shr eax,1 +jnc short ln950 +call readmemorydword +mov [ebp+__reg+ebx],ecx +add edx,byte 4 +sub edi,byte 8 +ln950: +add ebx,byte 4 +cmp ebx,byte 64 +jne short ln949 +pop eax +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4CFA +OCFA: +push eax +mov ax,[esi] +add esi,byte 2 +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +xor ebx,ebx +ln951: +shr eax,1 +jnc short ln952 +call readmemorydword +mov [ebp+__reg+ebx],ecx +add edx,byte 4 +sub edi,byte 8 +ln952: +add ebx,byte 4 +cmp ebx,byte 64 +jne short ln951 +pop eax +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4CFB +OCFB: +push eax +mov ax,[esi] +add esi,byte 2 +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +xor ebx,ebx +ln953: +shr eax,1 +jnc short ln954 +call readmemorydword +mov [ebp+__reg+ebx],ecx +add edx,byte 4 +sub edi,byte 8 +ln954: +add ebx,byte 4 +cmp ebx,byte 64 +jne short ln953 +pop eax +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4D00 - 4D07 +OD00: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +cmp word[ebp+__dreg+24],byte 0 +mov ax,8000h +jl short ln955 +cmp [ebp+__dreg+24],cx +mov ax,0 +jg short ln955 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln955:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln956 +cmp esi,[ebp+__fetch_region_end] +jbe short ln957 +ln956: +call basefunction +ln957: +add esi,[ebp+__io_fetchbase] +sub edi,byte 40 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4D10 - 4D17 +OD10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +cmp word[ebp+__dreg+24],byte 0 +mov ax,8000h +jl short ln958 +cmp [ebp+__dreg+24],cx +mov ax,0 +jg short ln958 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln958:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln959 +cmp esi,[ebp+__fetch_region_end] +jbe short ln960 +ln959: +call basefunction +ln960: +add esi,[ebp+__io_fetchbase] +sub edi,byte 44 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4D18 - 4D1F +OD18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +cmp word[ebp+__dreg+24],byte 0 +mov ax,8000h +jl short ln961 +cmp [ebp+__dreg+24],cx +mov ax,0 +jg short ln961 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln961:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln962 +cmp esi,[ebp+__fetch_region_end] +jbe short ln963 +ln962: +call basefunction +ln963: +add esi,[ebp+__io_fetchbase] +sub edi,byte 44 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4D20 - 4D27 +OD20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +cmp word[ebp+__dreg+24],byte 0 +mov ax,8000h +jl short ln964 +cmp [ebp+__dreg+24],cx +mov ax,0 +jg short ln964 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln964:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln965 +cmp esi,[ebp+__fetch_region_end] +jbe short ln966 +ln965: +call basefunction +ln966: +add esi,[ebp+__io_fetchbase] +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4D28 - 4D2F +OD28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +cmp word[ebp+__dreg+24],byte 0 +mov ax,8000h +jl short ln967 +cmp [ebp+__dreg+24],cx +mov ax,0 +jg short ln967 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln967:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln968 +cmp esi,[ebp+__fetch_region_end] +jbe short ln969 +ln968: +call basefunction +ln969: +add esi,[ebp+__io_fetchbase] +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4D30 - 4D37 +OD30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +cmp word[ebp+__dreg+24],byte 0 +mov ax,8000h +jl short ln970 +cmp [ebp+__dreg+24],cx +mov ax,0 +jg short ln970 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln970:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln971 +cmp esi,[ebp+__fetch_region_end] +jbe short ln972 +ln971: +call basefunction +ln972: +add esi,[ebp+__io_fetchbase] +sub edi,byte 50 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4D38 +OD38: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +cmp word[ebp+__dreg+24],byte 0 +mov ax,8000h +jl short ln973 +cmp [ebp+__dreg+24],cx +mov ax,0 +jg short ln973 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln973:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln974 +cmp esi,[ebp+__fetch_region_end] +jbe short ln975 +ln974: +call basefunction +ln975: +add esi,[ebp+__io_fetchbase] +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4D39 +OD39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +cmp word[ebp+__dreg+24],byte 0 +mov ax,8000h +jl short ln976 +cmp [ebp+__dreg+24],cx +mov ax,0 +jg short ln976 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln976:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln977 +cmp esi,[ebp+__fetch_region_end] +jbe short ln978 +ln977: +call basefunction +ln978: +add esi,[ebp+__io_fetchbase] +sub edi,byte 52 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4D3A +OD3A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +cmp word[ebp+__dreg+24],byte 0 +mov ax,8000h +jl short ln979 +cmp [ebp+__dreg+24],cx +mov ax,0 +jg short ln979 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln979:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln980 +cmp esi,[ebp+__fetch_region_end] +jbe short ln981 +ln980: +call basefunction +ln981: +add esi,[ebp+__io_fetchbase] +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4D3B +OD3B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +cmp word[ebp+__dreg+24],byte 0 +mov ax,8000h +jl short ln982 +cmp [ebp+__dreg+24],cx +mov ax,0 +jg short ln982 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln982:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln983 +cmp esi,[ebp+__fetch_region_end] +jbe short ln984 +ln983: +call basefunction +ln984: +add esi,[ebp+__io_fetchbase] +sub edi,byte 50 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4D3C +OD3C: +mov cx,[esi] +add esi,byte 2 +cmp word[ebp+__dreg+24],byte 0 +mov ax,8000h +jl short ln985 +cmp [ebp+__dreg+24],cx +mov ax,0 +jg short ln985 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln985:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln986 +cmp esi,[ebp+__fetch_region_end] +jbe short ln987 +ln986: +call basefunction +ln987: +add esi,[ebp+__io_fetchbase] +sub edi,byte 44 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4DD0 - 4DD7 +ODD0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +mov [ebp+__areg+24],edx +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4DE8 - 4DEF +ODE8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +mov [ebp+__areg+24],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4DF0 - 4DF7 +ODF0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +mov [ebp+__areg+24],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4DF8 +ODF8: +movsx edx,word[esi] +add esi,byte 2 +mov [ebp+__areg+24],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4DF9 +ODF9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +mov [ebp+__areg+24],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4DFA +ODFA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +mov [ebp+__areg+24],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4DFB +ODFB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +mov [ebp+__areg+24],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4E40 - 4E4F +OE40: +and ebx,byte 0Fh +lea edx,[80h+ebx*4] +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln988 +cmp esi,[ebp+__fetch_region_end] +jbe short ln989 +ln988: +call basefunction +ln989: +add esi,[ebp+__io_fetchbase] +sub edi,byte 34 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4E50 - 4E57 +OE50: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov edx,[ebp+__areg+28] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+28],edx +mov ecx,[ebp+__a7] +mov [ebp+__areg+ebx*4],ecx +movsx edx,word[esi] +add ecx,edx +mov [ebp+__a7],ecx +add esi,byte 2 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4E58 - 4E5F +OE58: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov [ebp+__a7],ecx +mov edx,[ebp+__areg+28] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+28],edx +mov [ebp+__areg+ebx*4],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4E60 - 4E67 +OE60: +test byte[ebp+__sr+1],20h +jz near privilege_violation +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +mov [ebp+__asp],ecx +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4E68 - 4E6F +OE68: +test byte[ebp+__sr+1],20h +jz near privilege_violation +and ebx,byte 7 +mov ecx,[ebp+__asp] +mov [ebp+__areg+ebx*4],ecx +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4E70 +OE70: +test byte[ebp+__sr+1],20h +jz near privilege_violation +mov edx,[ebp+__resethandler] +or edx,edx +jz near invalidins +mov [ebp+__io_cycle_counter],edi +mov [ebp+__io_fetchbased_pc],esi +push ebx +push eax +mov ecx,[ebp+__hwstate] +call edx +pop eax +pop ebx +mov edi,[ebp+__io_cycle_counter] +mov esi,[ebp+__io_fetchbased_pc] +sub edi,132 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4E71 +OE71: +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4E72 +OE72: +test byte[ebp+__sr+1],20h +jz near privilege_violation +mov cx,[esi] +add esi,2 +push ecx +mov cl,[ebp+__sr+1] +and cx,2020h +xor ch,cl +jz near ln991 +mov ecx,[ebp+__a7] +xchg ecx,[ebp+__asp] +mov [ebp+__a7],ecx +test byte[esp+1],20h +jz short ln992 +mov ecx,[ebp+__s_fetch] +mov [ebp+__fetch],ecx +mov ecx,[ebp+__s_readbyte] +mov [ebp+__readbyte],ecx +mov ecx,[ebp+__s_readword] +mov [ebp+__readword],ecx +mov ecx,[ebp+__s_writebyte] +mov [ebp+__writebyte],ecx +mov ecx,[ebp+__s_writeword] +mov [ebp+__writeword],ecx +jmp short ln991 +ln992: +mov ecx,[ebp+__u_fetch] +mov [ebp+__fetch],ecx +mov ecx,[ebp+__u_readbyte] +mov [ebp+__readbyte],ecx +mov ecx,[ebp+__u_readword] +mov [ebp+__readword],ecx +mov ecx,[ebp+__u_writebyte] +mov [ebp+__writebyte],ecx +mov ecx,[ebp+__u_writeword] +mov [ebp+__writeword],ecx +ln991: +pop ecx +mov [ebp+__sr+1],ch +and byte[ebp+__sr+1],0A7h +mov al,cl +mov ah,al +and ax,0C10h +shl ah,3 +shr al,4 +mov [ebp+__xflag],al +mov al,cl +and al,3 +shr al,1 +adc ah,ah +or byte[ebp+__interrupts],1 +sub edi,byte 4 +js short ln990 +xor edi,edi +dec edi +ln990: +or edi,edi +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4E73 +OE73: +test byte[ebp+__sr+1],20h +jz near privilege_violation +mov edx,[ebp+__a7] +call readmemoryword +add edx,byte 2 +push ecx +mov cl,[ebp+__sr+1] +and cx,2020h +xor ch,cl +jz near ln994 +mov ecx,[ebp+__a7] +xchg ecx,[ebp+__asp] +mov [ebp+__a7],ecx +test byte[esp+1],20h +jz short ln995 +mov ecx,[ebp+__s_fetch] +mov [ebp+__fetch],ecx +mov ecx,[ebp+__s_readbyte] +mov [ebp+__readbyte],ecx +mov ecx,[ebp+__s_readword] +mov [ebp+__readword],ecx +mov ecx,[ebp+__s_writebyte] +mov [ebp+__writebyte],ecx +mov ecx,[ebp+__s_writeword] +mov [ebp+__writeword],ecx +jmp short ln994 +ln995: +mov ecx,[ebp+__u_fetch] +mov [ebp+__fetch],ecx +mov ecx,[ebp+__u_readbyte] +mov [ebp+__readbyte],ecx +mov ecx,[ebp+__u_readword] +mov [ebp+__readword],ecx +mov ecx,[ebp+__u_writebyte] +mov [ebp+__writebyte],ecx +mov ecx,[ebp+__u_writeword] +mov [ebp+__writeword],ecx +ln994: +pop ecx +mov [ebp+__sr+1],ch +and byte[ebp+__sr+1],0A7h +mov al,cl +mov ah,al +and ax,0C10h +shl ah,3 +shr al,4 +mov [ebp+__xflag],al +mov al,cl +and al,3 +shr al,1 +adc ah,ah +test ch,20h +jz short ln993_nosupe +add dword [ebp+__a7],byte 6 +jmp short ln993_finish +ln993_nosupe: +add dword [ebp+__asp],byte 6 +ln993_finish: +call readmemorydword +mov esi,ecx +cmp esi,[ebp+__fetch_region_start] +jb short ln996 +cmp esi,[ebp+__fetch_region_end] +jbe short ln997 +ln996: +call basefunction +ln997: +add esi,[ebp+__io_fetchbase] +sub edi,byte 20 +jmp exec_checkpoint +; Opcode 4E75 +OE75: +mov edx,[ebp+__areg+28] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+28],edx +mov esi,ecx +cmp esi,[ebp+__fetch_region_start] +jb short ln998 +cmp esi,[ebp+__fetch_region_end] +jbe short ln999 +ln998: +call basefunction +ln999: +add esi,[ebp+__io_fetchbase] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4E76 +OE76: +test al,1 +jnz short ln1000 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1000: +mov edx,1Ch +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1001 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1002 +ln1001: +call basefunction +ln1002: +add esi,[ebp+__io_fetchbase] +sub edi,byte 38 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4E77 +OE77: +mov edx,[ebp+__areg+28] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+28],edx +mov al,cl +mov ah,al +and ax,0C10h +shl ah,3 +shr al,4 +mov [ebp+__xflag],al +mov al,cl +and al,3 +shr al,1 +adc ah,ah +mov edx,[ebp+__areg+28] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+28],edx +mov esi,ecx +cmp esi,[ebp+__fetch_region_start] +jb short ln1003 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1004 +ln1003: +call basefunction +ln1004: +add esi,[ebp+__io_fetchbase] +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4E90 - 4E97 +OE90: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +mov ecx,esi +sub ecx,[ebp+__io_fetchbase] +mov esi,edx +cmp esi,[ebp+__fetch_region_start] +jb short ln1005 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1006 +ln1005: +call basefunction +ln1006: +add esi,[ebp+__io_fetchbase] +mov edx,[ebp+__areg+28] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+28],edx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4EA8 - 4EAF +OEA8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +mov ecx,esi +sub ecx,[ebp+__io_fetchbase] +mov esi,edx +cmp esi,[ebp+__fetch_region_start] +jb short ln1007 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1008 +ln1007: +call basefunction +ln1008: +add esi,[ebp+__io_fetchbase] +mov edx,[ebp+__areg+28] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+28],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4EB0 - 4EB7 +OEB0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +mov ecx,esi +sub ecx,[ebp+__io_fetchbase] +mov esi,edx +cmp esi,[ebp+__fetch_region_start] +jb short ln1009 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1010 +ln1009: +call basefunction +ln1010: +add esi,[ebp+__io_fetchbase] +mov edx,[ebp+__areg+28] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+28],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4EB8 +OEB8: +movsx edx,word[esi] +add esi,byte 2 +mov ecx,esi +sub ecx,[ebp+__io_fetchbase] +mov esi,edx +cmp esi,[ebp+__fetch_region_start] +jb short ln1011 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1012 +ln1011: +call basefunction +ln1012: +add esi,[ebp+__io_fetchbase] +mov edx,[ebp+__areg+28] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+28],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4EB9 +OEB9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +mov ecx,esi +sub ecx,[ebp+__io_fetchbase] +mov esi,edx +cmp esi,[ebp+__fetch_region_start] +jb short ln1013 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1014 +ln1013: +call basefunction +ln1014: +add esi,[ebp+__io_fetchbase] +mov edx,[ebp+__areg+28] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+28],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4EBA +OEBA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +mov ecx,esi +sub ecx,[ebp+__io_fetchbase] +mov esi,edx +cmp esi,[ebp+__fetch_region_start] +jb short ln1015 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1016 +ln1015: +call basefunction +ln1016: +add esi,[ebp+__io_fetchbase] +mov edx,[ebp+__areg+28] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+28],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4EBB +OEBB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +mov ecx,esi +sub ecx,[ebp+__io_fetchbase] +mov esi,edx +cmp esi,[ebp+__fetch_region_start] +jb short ln1017 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1018 +ln1017: +call basefunction +ln1018: +add esi,[ebp+__io_fetchbase] +mov edx,[ebp+__areg+28] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+28],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4ED0 - 4ED7 +OED0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +mov esi,edx +cmp esi,[ebp+__fetch_region_start] +jb short ln1019 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1020 +ln1019: +call basefunction +ln1020: +add esi,[ebp+__io_fetchbase] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4EE8 - 4EEF +OEE8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +mov esi,edx +cmp esi,[ebp+__fetch_region_start] +jb short ln1021 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1022 +ln1021: +call basefunction +ln1022: +add esi,[ebp+__io_fetchbase] +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4EF0 - 4EF7 +OEF0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +mov esi,edx +cmp esi,[ebp+__fetch_region_start] +jb short ln1023 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1024 +ln1023: +call basefunction +ln1024: +add esi,[ebp+__io_fetchbase] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4EF8 +OEF8: +movsx edx,word[esi] +add esi,byte 2 +mov esi,edx +cmp esi,[ebp+__fetch_region_start] +jb short ln1025 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1026 +ln1025: +call basefunction +ln1026: +add esi,[ebp+__io_fetchbase] +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4EF9 +OEF9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +mov esi,edx +cmp esi,[ebp+__fetch_region_start] +jb short ln1027 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1028 +ln1027: +call basefunction +ln1028: +add esi,[ebp+__io_fetchbase] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4EFA +OEFA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +mov esi,edx +cmp esi,[ebp+__fetch_region_start] +jb short ln1029 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1030 +ln1029: +call basefunction +ln1030: +add esi,[ebp+__io_fetchbase] +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4EFB +OEFB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +mov esi,edx +cmp esi,[ebp+__fetch_region_start] +jb short ln1031 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1032 +ln1031: +call basefunction +ln1032: +add esi,[ebp+__io_fetchbase] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4F00 - 4F07 +OF00: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +cmp word[ebp+__dreg+28],byte 0 +mov ax,8000h +jl short ln1033 +cmp [ebp+__dreg+28],cx +mov ax,0 +jg short ln1033 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1033:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1034 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1035 +ln1034: +call basefunction +ln1035: +add esi,[ebp+__io_fetchbase] +sub edi,byte 40 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4F10 - 4F17 +OF10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +cmp word[ebp+__dreg+28],byte 0 +mov ax,8000h +jl short ln1036 +cmp [ebp+__dreg+28],cx +mov ax,0 +jg short ln1036 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1036:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1037 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1038 +ln1037: +call basefunction +ln1038: +add esi,[ebp+__io_fetchbase] +sub edi,byte 44 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4F18 - 4F1F +OF18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +cmp word[ebp+__dreg+28],byte 0 +mov ax,8000h +jl short ln1039 +cmp [ebp+__dreg+28],cx +mov ax,0 +jg short ln1039 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1039:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1040 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1041 +ln1040: +call basefunction +ln1041: +add esi,[ebp+__io_fetchbase] +sub edi,byte 44 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4F20 - 4F27 +OF20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +cmp word[ebp+__dreg+28],byte 0 +mov ax,8000h +jl short ln1042 +cmp [ebp+__dreg+28],cx +mov ax,0 +jg short ln1042 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1042:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1043 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1044 +ln1043: +call basefunction +ln1044: +add esi,[ebp+__io_fetchbase] +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4F28 - 4F2F +OF28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +cmp word[ebp+__dreg+28],byte 0 +mov ax,8000h +jl short ln1045 +cmp [ebp+__dreg+28],cx +mov ax,0 +jg short ln1045 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1045:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1046 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1047 +ln1046: +call basefunction +ln1047: +add esi,[ebp+__io_fetchbase] +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4F30 - 4F37 +OF30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +cmp word[ebp+__dreg+28],byte 0 +mov ax,8000h +jl short ln1048 +cmp [ebp+__dreg+28],cx +mov ax,0 +jg short ln1048 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1048:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1049 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1050 +ln1049: +call basefunction +ln1050: +add esi,[ebp+__io_fetchbase] +sub edi,byte 50 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4F38 +OF38: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +cmp word[ebp+__dreg+28],byte 0 +mov ax,8000h +jl short ln1051 +cmp [ebp+__dreg+28],cx +mov ax,0 +jg short ln1051 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1051:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1052 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1053 +ln1052: +call basefunction +ln1053: +add esi,[ebp+__io_fetchbase] +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4F39 +OF39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +cmp word[ebp+__dreg+28],byte 0 +mov ax,8000h +jl short ln1054 +cmp [ebp+__dreg+28],cx +mov ax,0 +jg short ln1054 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1054:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1055 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1056 +ln1055: +call basefunction +ln1056: +add esi,[ebp+__io_fetchbase] +sub edi,byte 52 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4F3A +OF3A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +cmp word[ebp+__dreg+28],byte 0 +mov ax,8000h +jl short ln1057 +cmp [ebp+__dreg+28],cx +mov ax,0 +jg short ln1057 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1057:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1058 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1059 +ln1058: +call basefunction +ln1059: +add esi,[ebp+__io_fetchbase] +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4F3B +OF3B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +cmp word[ebp+__dreg+28],byte 0 +mov ax,8000h +jl short ln1060 +cmp [ebp+__dreg+28],cx +mov ax,0 +jg short ln1060 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1060:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1061 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1062 +ln1061: +call basefunction +ln1062: +add esi,[ebp+__io_fetchbase] +sub edi,byte 50 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4F3C +OF3C: +mov cx,[esi] +add esi,byte 2 +cmp word[ebp+__dreg+28],byte 0 +mov ax,8000h +jl short ln1063 +cmp [ebp+__dreg+28],cx +mov ax,0 +jg short ln1063 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1063:mov edx,18h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1064 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1065 +ln1064: +call basefunction +ln1065: +add esi,[ebp+__io_fetchbase] +sub edi,byte 44 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4FD0 - 4FD7 +OFD0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +mov [ebp+__areg+28],edx +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4FE8 - 4FEF +OFE8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +mov [ebp+__areg+28],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 4FF0 - 4FF7 +OFF0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +mov [ebp+__areg+28],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4FF8 +OFF8: +movsx edx,word[esi] +add esi,byte 2 +mov [ebp+__areg+28],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4FF9 +OFF9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +mov [ebp+__areg+28],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4FFA +OFFA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +mov [ebp+__areg+28],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 4FFB +OFFB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +mov [ebp+__areg+28],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5000 - 5007 +P000: +and ebx,byte 7 +add byte[ebp+__dreg+ebx*4],byte 8 +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5010 - 5017 +P010: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,byte 8 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5018 - 501F +P018: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,byte 8 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5020 - 5027 +P020: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +add cl,byte 8 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5028 - 502F +P028: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,byte 8 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5030 - 5037 +P030: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,byte 8 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5038 +P038: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +add cl,byte 8 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5039 +P039: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +add cl,byte 8 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5040 - 5047 +P040: +and ebx,byte 7 +add word[ebp+__dreg+ebx*4],byte 8 +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5048 - 504F +P048: +and ebx,byte 7 +add dword[ebp+__areg+ebx*4],byte 8 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5050 - 5057 +P050: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,byte 8 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5058 - 505F +P058: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,byte 8 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5060 - 5067 +P060: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +add cx,byte 8 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5068 - 506F +P068: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,byte 8 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5070 - 5077 +P070: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,byte 8 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5078 +P078: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +add cx,byte 8 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5079 +P079: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +add cx,byte 8 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5080 - 5087 +P080: +and ebx,byte 7 +add dword[ebp+__dreg+ebx*4],byte 8 +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5088 - 508F +P088: +and ebx,byte 7 +add dword[ebp+__areg+ebx*4],byte 8 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5090 - 5097 +P090: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,byte 8 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5098 - 509F +P098: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,byte 8 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 50A0 - 50A7 +P0A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +add ecx,byte 8 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 50A8 - 50AF +P0A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,byte 8 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 50B0 - 50B7 +P0B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,byte 8 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 50B8 +P0B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +add ecx,byte 8 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 50B9 +P0B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +add ecx,byte 8 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 50C0 - 50C7 +P0C0: +and ebx,byte 7 +mov cl,255 +mov [ebp+__dreg+ebx*4],cl +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 50D0 - 50D7 +P0D0: +and ebx,byte 7 +mov cl,255 +mov edx,[ebp+__areg+ebx*4] +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 50D8 - 50DF +P0D8: +and ebx,byte 7 +mov cl,255 +mov edx,[ebp+__areg+ebx*4] +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 50E0 - 50E7 +P0E0: +and ebx,byte 7 +mov cl,255 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 50E8 - 50EF +P0E8: +and ebx,byte 7 +mov cl,255 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 50F0 - 50F7 +P0F0: +and ebx,byte 7 +mov cl,255 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 50F8 +P0F8: +mov cl,255 +movsx edx,word[esi] +add esi,byte 2 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 50F9 +P0F9: +mov cl,255 +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5100 - 5107 +P100: +and ebx,byte 7 +sub byte[ebp+__dreg+ebx*4],byte 8 +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5110 - 5117 +P110: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,byte 8 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5118 - 511F +P118: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,byte 8 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5120 - 5127 +P120: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +sub cl,byte 8 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5128 - 512F +P128: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,byte 8 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5130 - 5137 +P130: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,byte 8 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5138 +P138: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +sub cl,byte 8 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5139 +P139: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +sub cl,byte 8 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5140 - 5147 +P140: +and ebx,byte 7 +sub word[ebp+__dreg+ebx*4],byte 8 +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5148 - 514F +P148: +and ebx,byte 7 +sub dword[ebp+__areg+ebx*4],byte 8 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5150 - 5157 +P150: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,byte 8 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5158 - 515F +P158: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,byte 8 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5160 - 5167 +P160: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +sub cx,byte 8 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5168 - 516F +P168: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,byte 8 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5170 - 5177 +P170: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,byte 8 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5178 +P178: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +sub cx,byte 8 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5179 +P179: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +sub cx,byte 8 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5180 - 5187 +P180: +and ebx,byte 7 +sub dword[ebp+__dreg+ebx*4],byte 8 +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5188 - 518F +P188: +and ebx,byte 7 +sub dword[ebp+__areg+ebx*4],byte 8 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5190 - 5197 +P190: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,byte 8 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5198 - 519F +P198: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,byte 8 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 51A0 - 51A7 +P1A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +sub ecx,byte 8 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 51A8 - 51AF +P1A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,byte 8 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 51B0 - 51B7 +P1B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,byte 8 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 51B8 +P1B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +sub ecx,byte 8 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 51B9 +P1B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +sub ecx,byte 8 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 51C0 - 51C7 +P1C0: +and ebx,byte 7 +mov cl,0 +mov [ebp+__dreg+ebx*4],cl +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 51C8 - 51CF +P1C8: +r_dbra: +and ebx,byte 7 +sub word[ebp+__dreg+ebx*4],byte 1 +jnc near r_bra_w +add esi,byte 2 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 51D0 - 51D7 +P1D0: +and ebx,byte 7 +mov cl,0 +mov edx,[ebp+__areg+ebx*4] +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 51D8 - 51DF +P1D8: +and ebx,byte 7 +mov cl,0 +mov edx,[ebp+__areg+ebx*4] +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 51E0 - 51E7 +P1E0: +and ebx,byte 7 +mov cl,0 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 51E8 - 51EF +P1E8: +and ebx,byte 7 +mov cl,0 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 51F0 - 51F7 +P1F0: +and ebx,byte 7 +mov cl,0 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 51F8 +P1F8: +mov cl,0 +movsx edx,word[esi] +add esi,byte 2 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 51F9 +P1F9: +mov cl,0 +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5200 - 5207 +P200: +and ebx,byte 7 +add byte[ebp+__dreg+ebx*4],byte 1 +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5210 - 5217 +P210: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,byte 1 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5218 - 521F +P218: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,byte 1 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5220 - 5227 +P220: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +add cl,byte 1 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5228 - 522F +P228: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,byte 1 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5230 - 5237 +P230: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,byte 1 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5238 +P238: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +add cl,byte 1 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5239 +P239: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +add cl,byte 1 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5240 - 5247 +P240: +and ebx,byte 7 +add word[ebp+__dreg+ebx*4],byte 1 +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5248 - 524F +P248: +and ebx,byte 7 +add dword[ebp+__areg+ebx*4],byte 1 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5250 - 5257 +P250: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,byte 1 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5258 - 525F +P258: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,byte 1 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5260 - 5267 +P260: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +add cx,byte 1 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5268 - 526F +P268: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,byte 1 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5270 - 5277 +P270: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,byte 1 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5278 +P278: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +add cx,byte 1 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5279 +P279: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +add cx,byte 1 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5280 - 5287 +P280: +and ebx,byte 7 +add dword[ebp+__dreg+ebx*4],byte 1 +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5288 - 528F +P288: +and ebx,byte 7 +add dword[ebp+__areg+ebx*4],byte 1 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5290 - 5297 +P290: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,byte 1 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5298 - 529F +P298: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,byte 1 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 52A0 - 52A7 +P2A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +add ecx,byte 1 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 52A8 - 52AF +P2A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,byte 1 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 52B0 - 52B7 +P2B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,byte 1 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 52B8 +P2B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +add ecx,byte 1 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 52B9 +P2B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +add ecx,byte 1 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 52C0 - 52C7 +P2C0: +and ebx,byte 7 +xor ecx,ecx +test ah,41h +setz cl +sub edi,ecx +sub edi,ecx +neg cl +mov [ebp+__dreg+ebx*4],cl +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 52C8 - 52CF +P2C8: +test ah,41h +jnz near r_dbra +add esi,byte 2 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 52D0 - 52D7 +P2D0: +and ebx,byte 7 +test ah,41h +setz cl +neg cl +mov edx,[ebp+__areg+ebx*4] +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 52D8 - 52DF +P2D8: +and ebx,byte 7 +test ah,41h +setz cl +neg cl +mov edx,[ebp+__areg+ebx*4] +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 52E0 - 52E7 +P2E0: +and ebx,byte 7 +test ah,41h +setz cl +neg cl +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 52E8 - 52EF +P2E8: +and ebx,byte 7 +test ah,41h +setz cl +neg cl +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 52F0 - 52F7 +P2F0: +and ebx,byte 7 +test ah,41h +setz cl +neg cl +call decode_ext +add edx,[ebp+__areg+ebx*4] +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 52F8 +P2F8: +test ah,41h +setz cl +neg cl +movsx edx,word[esi] +add esi,byte 2 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 52F9 +P2F9: +test ah,41h +setz cl +neg cl +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5300 - 5307 +P300: +and ebx,byte 7 +sub byte[ebp+__dreg+ebx*4],byte 1 +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5310 - 5317 +P310: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,byte 1 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5318 - 531F +P318: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,byte 1 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5320 - 5327 +P320: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +sub cl,byte 1 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5328 - 532F +P328: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,byte 1 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5330 - 5337 +P330: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,byte 1 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5338 +P338: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +sub cl,byte 1 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5339 +P339: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +sub cl,byte 1 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5340 - 5347 +P340: +and ebx,byte 7 +sub word[ebp+__dreg+ebx*4],byte 1 +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5348 - 534F +P348: +and ebx,byte 7 +sub dword[ebp+__areg+ebx*4],byte 1 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5350 - 5357 +P350: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,byte 1 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5358 - 535F +P358: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,byte 1 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5360 - 5367 +P360: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +sub cx,byte 1 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5368 - 536F +P368: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,byte 1 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5370 - 5377 +P370: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,byte 1 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5378 +P378: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +sub cx,byte 1 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5379 +P379: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +sub cx,byte 1 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5380 - 5387 +P380: +and ebx,byte 7 +sub dword[ebp+__dreg+ebx*4],byte 1 +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5388 - 538F +P388: +and ebx,byte 7 +sub dword[ebp+__areg+ebx*4],byte 1 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5390 - 5397 +P390: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,byte 1 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5398 - 539F +P398: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,byte 1 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 53A0 - 53A7 +P3A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +sub ecx,byte 1 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 53A8 - 53AF +P3A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,byte 1 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 53B0 - 53B7 +P3B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,byte 1 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 53B8 +P3B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +sub ecx,byte 1 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 53B9 +P3B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +sub ecx,byte 1 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 53C0 - 53C7 +P3C0: +and ebx,byte 7 +xor ecx,ecx +test ah,41h +setnz cl +sub edi,ecx +sub edi,ecx +neg cl +mov [ebp+__dreg+ebx*4],cl +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 53C8 - 53CF +P3C8: +test ah,41h +jz near r_dbra +add esi,byte 2 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 53D0 - 53D7 +P3D0: +and ebx,byte 7 +test ah,41h +setnz cl +neg cl +mov edx,[ebp+__areg+ebx*4] +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 53D8 - 53DF +P3D8: +and ebx,byte 7 +test ah,41h +setnz cl +neg cl +mov edx,[ebp+__areg+ebx*4] +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 53E0 - 53E7 +P3E0: +and ebx,byte 7 +test ah,41h +setnz cl +neg cl +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 53E8 - 53EF +P3E8: +and ebx,byte 7 +test ah,41h +setnz cl +neg cl +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 53F0 - 53F7 +P3F0: +and ebx,byte 7 +test ah,41h +setnz cl +neg cl +call decode_ext +add edx,[ebp+__areg+ebx*4] +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 53F8 +P3F8: +test ah,41h +setnz cl +neg cl +movsx edx,word[esi] +add esi,byte 2 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 53F9 +P3F9: +test ah,41h +setnz cl +neg cl +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5400 - 5407 +P400: +and ebx,byte 7 +add byte[ebp+__dreg+ebx*4],byte 2 +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5410 - 5417 +P410: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,byte 2 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5418 - 541F +P418: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,byte 2 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5420 - 5427 +P420: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +add cl,byte 2 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5428 - 542F +P428: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,byte 2 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5430 - 5437 +P430: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,byte 2 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5438 +P438: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +add cl,byte 2 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5439 +P439: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +add cl,byte 2 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5440 - 5447 +P440: +and ebx,byte 7 +add word[ebp+__dreg+ebx*4],byte 2 +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5448 - 544F +P448: +and ebx,byte 7 +add dword[ebp+__areg+ebx*4],byte 2 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5450 - 5457 +P450: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,byte 2 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5458 - 545F +P458: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,byte 2 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5460 - 5467 +P460: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +add cx,byte 2 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5468 - 546F +P468: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,byte 2 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5470 - 5477 +P470: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,byte 2 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5478 +P478: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +add cx,byte 2 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5479 +P479: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +add cx,byte 2 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5480 - 5487 +P480: +and ebx,byte 7 +add dword[ebp+__dreg+ebx*4],byte 2 +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5488 - 548F +P488: +and ebx,byte 7 +add dword[ebp+__areg+ebx*4],byte 2 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5490 - 5497 +P490: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,byte 2 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5498 - 549F +P498: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,byte 2 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 54A0 - 54A7 +P4A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +add ecx,byte 2 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 54A8 - 54AF +P4A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,byte 2 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 54B0 - 54B7 +P4B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,byte 2 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 54B8 +P4B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +add ecx,byte 2 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 54B9 +P4B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +add ecx,byte 2 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 54C0 - 54C7 +P4C0: +and ebx,byte 7 +xor ecx,ecx +test ah,1 +setz cl +sub edi,ecx +sub edi,ecx +neg cl +mov [ebp+__dreg+ebx*4],cl +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 54C8 - 54CF +P4C8: +test ah,1 +jnz near r_dbra +add esi,byte 2 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 54D0 - 54D7 +P4D0: +and ebx,byte 7 +test ah,1 +setz cl +neg cl +mov edx,[ebp+__areg+ebx*4] +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 54D8 - 54DF +P4D8: +and ebx,byte 7 +test ah,1 +setz cl +neg cl +mov edx,[ebp+__areg+ebx*4] +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 54E0 - 54E7 +P4E0: +and ebx,byte 7 +test ah,1 +setz cl +neg cl +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 54E8 - 54EF +P4E8: +and ebx,byte 7 +test ah,1 +setz cl +neg cl +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 54F0 - 54F7 +P4F0: +and ebx,byte 7 +test ah,1 +setz cl +neg cl +call decode_ext +add edx,[ebp+__areg+ebx*4] +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 54F8 +P4F8: +test ah,1 +setz cl +neg cl +movsx edx,word[esi] +add esi,byte 2 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 54F9 +P4F9: +test ah,1 +setz cl +neg cl +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5500 - 5507 +P500: +and ebx,byte 7 +sub byte[ebp+__dreg+ebx*4],byte 2 +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5510 - 5517 +P510: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,byte 2 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5518 - 551F +P518: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,byte 2 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5520 - 5527 +P520: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +sub cl,byte 2 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5528 - 552F +P528: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,byte 2 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5530 - 5537 +P530: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,byte 2 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5538 +P538: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +sub cl,byte 2 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5539 +P539: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +sub cl,byte 2 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5540 - 5547 +P540: +and ebx,byte 7 +sub word[ebp+__dreg+ebx*4],byte 2 +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5548 - 554F +P548: +and ebx,byte 7 +sub dword[ebp+__areg+ebx*4],byte 2 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5550 - 5557 +P550: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,byte 2 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5558 - 555F +P558: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,byte 2 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5560 - 5567 +P560: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +sub cx,byte 2 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5568 - 556F +P568: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,byte 2 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5570 - 5577 +P570: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,byte 2 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5578 +P578: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +sub cx,byte 2 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5579 +P579: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +sub cx,byte 2 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5580 - 5587 +P580: +and ebx,byte 7 +sub dword[ebp+__dreg+ebx*4],byte 2 +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5588 - 558F +P588: +and ebx,byte 7 +sub dword[ebp+__areg+ebx*4],byte 2 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5590 - 5597 +P590: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,byte 2 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5598 - 559F +P598: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,byte 2 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 55A0 - 55A7 +P5A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +sub ecx,byte 2 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 55A8 - 55AF +P5A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,byte 2 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 55B0 - 55B7 +P5B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,byte 2 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 55B8 +P5B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +sub ecx,byte 2 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 55B9 +P5B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +sub ecx,byte 2 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 55C0 - 55C7 +P5C0: +and ebx,byte 7 +xor ecx,ecx +test ah,1 +setnz cl +sub edi,ecx +sub edi,ecx +neg cl +mov [ebp+__dreg+ebx*4],cl +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 55C8 - 55CF +P5C8: +test ah,1 +jz near r_dbra +add esi,byte 2 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 55D0 - 55D7 +P5D0: +and ebx,byte 7 +test ah,1 +setnz cl +neg cl +mov edx,[ebp+__areg+ebx*4] +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 55D8 - 55DF +P5D8: +and ebx,byte 7 +test ah,1 +setnz cl +neg cl +mov edx,[ebp+__areg+ebx*4] +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 55E0 - 55E7 +P5E0: +and ebx,byte 7 +test ah,1 +setnz cl +neg cl +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 55E8 - 55EF +P5E8: +and ebx,byte 7 +test ah,1 +setnz cl +neg cl +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 55F0 - 55F7 +P5F0: +and ebx,byte 7 +test ah,1 +setnz cl +neg cl +call decode_ext +add edx,[ebp+__areg+ebx*4] +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 55F8 +P5F8: +test ah,1 +setnz cl +neg cl +movsx edx,word[esi] +add esi,byte 2 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 55F9 +P5F9: +test ah,1 +setnz cl +neg cl +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5600 - 5607 +P600: +and ebx,byte 7 +add byte[ebp+__dreg+ebx*4],byte 3 +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5610 - 5617 +P610: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,byte 3 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5618 - 561F +P618: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,byte 3 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5620 - 5627 +P620: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +add cl,byte 3 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5628 - 562F +P628: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,byte 3 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5630 - 5637 +P630: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,byte 3 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5638 +P638: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +add cl,byte 3 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5639 +P639: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +add cl,byte 3 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5640 - 5647 +P640: +and ebx,byte 7 +add word[ebp+__dreg+ebx*4],byte 3 +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5648 - 564F +P648: +and ebx,byte 7 +add dword[ebp+__areg+ebx*4],byte 3 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5650 - 5657 +P650: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,byte 3 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5658 - 565F +P658: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,byte 3 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5660 - 5667 +P660: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +add cx,byte 3 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5668 - 566F +P668: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,byte 3 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5670 - 5677 +P670: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,byte 3 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5678 +P678: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +add cx,byte 3 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5679 +P679: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +add cx,byte 3 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5680 - 5687 +P680: +and ebx,byte 7 +add dword[ebp+__dreg+ebx*4],byte 3 +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5688 - 568F +P688: +and ebx,byte 7 +add dword[ebp+__areg+ebx*4],byte 3 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5690 - 5697 +P690: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,byte 3 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5698 - 569F +P698: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,byte 3 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 56A0 - 56A7 +P6A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +add ecx,byte 3 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 56A8 - 56AF +P6A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,byte 3 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 56B0 - 56B7 +P6B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,byte 3 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 56B8 +P6B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +add ecx,byte 3 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 56B9 +P6B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +add ecx,byte 3 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 56C0 - 56C7 +P6C0: +and ebx,byte 7 +xor ecx,ecx +test ah,40h +setz cl +sub edi,ecx +sub edi,ecx +neg cl +mov [ebp+__dreg+ebx*4],cl +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 56C8 - 56CF +P6C8: +test ah,40h +jnz near r_dbra +add esi,byte 2 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 56D0 - 56D7 +P6D0: +and ebx,byte 7 +test ah,40h +setz cl +neg cl +mov edx,[ebp+__areg+ebx*4] +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 56D8 - 56DF +P6D8: +and ebx,byte 7 +test ah,40h +setz cl +neg cl +mov edx,[ebp+__areg+ebx*4] +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 56E0 - 56E7 +P6E0: +and ebx,byte 7 +test ah,40h +setz cl +neg cl +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 56E8 - 56EF +P6E8: +and ebx,byte 7 +test ah,40h +setz cl +neg cl +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 56F0 - 56F7 +P6F0: +and ebx,byte 7 +test ah,40h +setz cl +neg cl +call decode_ext +add edx,[ebp+__areg+ebx*4] +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 56F8 +P6F8: +test ah,40h +setz cl +neg cl +movsx edx,word[esi] +add esi,byte 2 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 56F9 +P6F9: +test ah,40h +setz cl +neg cl +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5700 - 5707 +P700: +and ebx,byte 7 +sub byte[ebp+__dreg+ebx*4],byte 3 +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5710 - 5717 +P710: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,byte 3 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5718 - 571F +P718: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,byte 3 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5720 - 5727 +P720: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +sub cl,byte 3 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5728 - 572F +P728: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,byte 3 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5730 - 5737 +P730: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,byte 3 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5738 +P738: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +sub cl,byte 3 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5739 +P739: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +sub cl,byte 3 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5740 - 5747 +P740: +and ebx,byte 7 +sub word[ebp+__dreg+ebx*4],byte 3 +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5748 - 574F +P748: +and ebx,byte 7 +sub dword[ebp+__areg+ebx*4],byte 3 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5750 - 5757 +P750: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,byte 3 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5758 - 575F +P758: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,byte 3 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5760 - 5767 +P760: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +sub cx,byte 3 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5768 - 576F +P768: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,byte 3 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5770 - 5777 +P770: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,byte 3 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5778 +P778: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +sub cx,byte 3 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5779 +P779: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +sub cx,byte 3 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5780 - 5787 +P780: +and ebx,byte 7 +sub dword[ebp+__dreg+ebx*4],byte 3 +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5788 - 578F +P788: +and ebx,byte 7 +sub dword[ebp+__areg+ebx*4],byte 3 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5790 - 5797 +P790: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,byte 3 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5798 - 579F +P798: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,byte 3 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 57A0 - 57A7 +P7A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +sub ecx,byte 3 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 57A8 - 57AF +P7A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,byte 3 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 57B0 - 57B7 +P7B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,byte 3 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 57B8 +P7B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +sub ecx,byte 3 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 57B9 +P7B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +sub ecx,byte 3 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 57C0 - 57C7 +P7C0: +and ebx,byte 7 +xor ecx,ecx +test ah,40h +setnz cl +sub edi,ecx +sub edi,ecx +neg cl +mov [ebp+__dreg+ebx*4],cl +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 57C8 - 57CF +P7C8: +test ah,40h +jz near r_dbra +add esi,byte 2 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 57D0 - 57D7 +P7D0: +and ebx,byte 7 +test ah,40h +setnz cl +neg cl +mov edx,[ebp+__areg+ebx*4] +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 57D8 - 57DF +P7D8: +and ebx,byte 7 +test ah,40h +setnz cl +neg cl +mov edx,[ebp+__areg+ebx*4] +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 57E0 - 57E7 +P7E0: +and ebx,byte 7 +test ah,40h +setnz cl +neg cl +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 57E8 - 57EF +P7E8: +and ebx,byte 7 +test ah,40h +setnz cl +neg cl +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 57F0 - 57F7 +P7F0: +and ebx,byte 7 +test ah,40h +setnz cl +neg cl +call decode_ext +add edx,[ebp+__areg+ebx*4] +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 57F8 +P7F8: +test ah,40h +setnz cl +neg cl +movsx edx,word[esi] +add esi,byte 2 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 57F9 +P7F9: +test ah,40h +setnz cl +neg cl +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5800 - 5807 +P800: +and ebx,byte 7 +add byte[ebp+__dreg+ebx*4],byte 4 +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5810 - 5817 +P810: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,byte 4 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5818 - 581F +P818: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,byte 4 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5820 - 5827 +P820: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +add cl,byte 4 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5828 - 582F +P828: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,byte 4 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5830 - 5837 +P830: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,byte 4 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5838 +P838: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +add cl,byte 4 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5839 +P839: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +add cl,byte 4 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5840 - 5847 +P840: +and ebx,byte 7 +add word[ebp+__dreg+ebx*4],byte 4 +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5848 - 584F +P848: +and ebx,byte 7 +add dword[ebp+__areg+ebx*4],byte 4 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5850 - 5857 +P850: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,byte 4 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5858 - 585F +P858: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,byte 4 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5860 - 5867 +P860: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +add cx,byte 4 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5868 - 586F +P868: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,byte 4 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5870 - 5877 +P870: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,byte 4 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5878 +P878: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +add cx,byte 4 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5879 +P879: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +add cx,byte 4 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5880 - 5887 +P880: +and ebx,byte 7 +add dword[ebp+__dreg+ebx*4],byte 4 +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5888 - 588F +P888: +and ebx,byte 7 +add dword[ebp+__areg+ebx*4],byte 4 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5890 - 5897 +P890: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,byte 4 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5898 - 589F +P898: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,byte 4 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 58A0 - 58A7 +P8A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +add ecx,byte 4 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 58A8 - 58AF +P8A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,byte 4 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 58B0 - 58B7 +P8B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,byte 4 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 58B8 +P8B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +add ecx,byte 4 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 58B9 +P8B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +add ecx,byte 4 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 58C0 - 58C7 +P8C0: +and ebx,byte 7 +xor ecx,ecx +test al,1 +setz cl +sub edi,ecx +sub edi,ecx +neg cl +mov [ebp+__dreg+ebx*4],cl +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 58C8 - 58CF +P8C8: +test al,1 +jnz near r_dbra +add esi,byte 2 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 58D0 - 58D7 +P8D0: +and ebx,byte 7 +test al,1 +setz cl +neg cl +mov edx,[ebp+__areg+ebx*4] +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 58D8 - 58DF +P8D8: +and ebx,byte 7 +test al,1 +setz cl +neg cl +mov edx,[ebp+__areg+ebx*4] +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 58E0 - 58E7 +P8E0: +and ebx,byte 7 +test al,1 +setz cl +neg cl +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 58E8 - 58EF +P8E8: +and ebx,byte 7 +test al,1 +setz cl +neg cl +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 58F0 - 58F7 +P8F0: +and ebx,byte 7 +test al,1 +setz cl +neg cl +call decode_ext +add edx,[ebp+__areg+ebx*4] +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 58F8 +P8F8: +test al,1 +setz cl +neg cl +movsx edx,word[esi] +add esi,byte 2 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 58F9 +P8F9: +test al,1 +setz cl +neg cl +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5900 - 5907 +P900: +and ebx,byte 7 +sub byte[ebp+__dreg+ebx*4],byte 4 +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5910 - 5917 +P910: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,byte 4 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5918 - 591F +P918: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,byte 4 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5920 - 5927 +P920: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +sub cl,byte 4 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5928 - 592F +P928: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,byte 4 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5930 - 5937 +P930: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,byte 4 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5938 +P938: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +sub cl,byte 4 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5939 +P939: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +sub cl,byte 4 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5940 - 5947 +P940: +and ebx,byte 7 +sub word[ebp+__dreg+ebx*4],byte 4 +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5948 - 594F +P948: +and ebx,byte 7 +sub dword[ebp+__areg+ebx*4],byte 4 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5950 - 5957 +P950: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,byte 4 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5958 - 595F +P958: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,byte 4 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5960 - 5967 +P960: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +sub cx,byte 4 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5968 - 596F +P968: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,byte 4 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5970 - 5977 +P970: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,byte 4 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5978 +P978: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +sub cx,byte 4 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5979 +P979: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +sub cx,byte 4 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5980 - 5987 +P980: +and ebx,byte 7 +sub dword[ebp+__dreg+ebx*4],byte 4 +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5988 - 598F +P988: +and ebx,byte 7 +sub dword[ebp+__areg+ebx*4],byte 4 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5990 - 5997 +P990: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,byte 4 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5998 - 599F +P998: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,byte 4 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 59A0 - 59A7 +P9A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +sub ecx,byte 4 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 59A8 - 59AF +P9A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,byte 4 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 59B0 - 59B7 +P9B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,byte 4 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 59B8 +P9B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +sub ecx,byte 4 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 59B9 +P9B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +sub ecx,byte 4 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 59C0 - 59C7 +P9C0: +and ebx,byte 7 +xor ecx,ecx +test al,1 +setnz cl +sub edi,ecx +sub edi,ecx +neg cl +mov [ebp+__dreg+ebx*4],cl +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 59C8 - 59CF +P9C8: +test al,1 +jz near r_dbra +add esi,byte 2 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 59D0 - 59D7 +P9D0: +and ebx,byte 7 +test al,1 +setnz cl +neg cl +mov edx,[ebp+__areg+ebx*4] +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 59D8 - 59DF +P9D8: +and ebx,byte 7 +test al,1 +setnz cl +neg cl +mov edx,[ebp+__areg+ebx*4] +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 59E0 - 59E7 +P9E0: +and ebx,byte 7 +test al,1 +setnz cl +neg cl +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 59E8 - 59EF +P9E8: +and ebx,byte 7 +test al,1 +setnz cl +neg cl +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 59F0 - 59F7 +P9F0: +and ebx,byte 7 +test al,1 +setnz cl +neg cl +call decode_ext +add edx,[ebp+__areg+ebx*4] +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 59F8 +P9F8: +test al,1 +setnz cl +neg cl +movsx edx,word[esi] +add esi,byte 2 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 59F9 +P9F9: +test al,1 +setnz cl +neg cl +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5A00 - 5A07 +PA00: +and ebx,byte 7 +add byte[ebp+__dreg+ebx*4],byte 5 +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5A10 - 5A17 +PA10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,byte 5 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5A18 - 5A1F +PA18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,byte 5 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5A20 - 5A27 +PA20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +add cl,byte 5 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5A28 - 5A2F +PA28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,byte 5 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5A30 - 5A37 +PA30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,byte 5 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5A38 +PA38: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +add cl,byte 5 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5A39 +PA39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +add cl,byte 5 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5A40 - 5A47 +PA40: +and ebx,byte 7 +add word[ebp+__dreg+ebx*4],byte 5 +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5A48 - 5A4F +PA48: +and ebx,byte 7 +add dword[ebp+__areg+ebx*4],byte 5 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5A50 - 5A57 +PA50: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,byte 5 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5A58 - 5A5F +PA58: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,byte 5 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5A60 - 5A67 +PA60: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +add cx,byte 5 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5A68 - 5A6F +PA68: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,byte 5 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5A70 - 5A77 +PA70: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,byte 5 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5A78 +PA78: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +add cx,byte 5 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5A79 +PA79: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +add cx,byte 5 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5A80 - 5A87 +PA80: +and ebx,byte 7 +add dword[ebp+__dreg+ebx*4],byte 5 +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5A88 - 5A8F +PA88: +and ebx,byte 7 +add dword[ebp+__areg+ebx*4],byte 5 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5A90 - 5A97 +PA90: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,byte 5 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5A98 - 5A9F +PA98: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,byte 5 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5AA0 - 5AA7 +PAA0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +add ecx,byte 5 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5AA8 - 5AAF +PAA8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,byte 5 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5AB0 - 5AB7 +PAB0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,byte 5 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5AB8 +PAB8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +add ecx,byte 5 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5AB9 +PAB9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +add ecx,byte 5 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5AC0 - 5AC7 +PAC0: +and ebx,byte 7 +xor ecx,ecx +or ah,ah +setns cl +sub edi,ecx +sub edi,ecx +neg cl +mov [ebp+__dreg+ebx*4],cl +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5AC8 - 5ACF +PAC8: +or ah,ah +js near r_dbra +add esi,byte 2 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5AD0 - 5AD7 +PAD0: +and ebx,byte 7 +or ah,ah +setns cl +neg cl +mov edx,[ebp+__areg+ebx*4] +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5AD8 - 5ADF +PAD8: +and ebx,byte 7 +or ah,ah +setns cl +neg cl +mov edx,[ebp+__areg+ebx*4] +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5AE0 - 5AE7 +PAE0: +and ebx,byte 7 +or ah,ah +setns cl +neg cl +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5AE8 - 5AEF +PAE8: +and ebx,byte 7 +or ah,ah +setns cl +neg cl +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5AF0 - 5AF7 +PAF0: +and ebx,byte 7 +or ah,ah +setns cl +neg cl +call decode_ext +add edx,[ebp+__areg+ebx*4] +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5AF8 +PAF8: +or ah,ah +setns cl +neg cl +movsx edx,word[esi] +add esi,byte 2 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5AF9 +PAF9: +or ah,ah +setns cl +neg cl +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5B00 - 5B07 +PB00: +and ebx,byte 7 +sub byte[ebp+__dreg+ebx*4],byte 5 +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5B10 - 5B17 +PB10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,byte 5 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5B18 - 5B1F +PB18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,byte 5 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5B20 - 5B27 +PB20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +sub cl,byte 5 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5B28 - 5B2F +PB28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,byte 5 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5B30 - 5B37 +PB30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,byte 5 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5B38 +PB38: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +sub cl,byte 5 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5B39 +PB39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +sub cl,byte 5 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5B40 - 5B47 +PB40: +and ebx,byte 7 +sub word[ebp+__dreg+ebx*4],byte 5 +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5B48 - 5B4F +PB48: +and ebx,byte 7 +sub dword[ebp+__areg+ebx*4],byte 5 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5B50 - 5B57 +PB50: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,byte 5 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5B58 - 5B5F +PB58: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,byte 5 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5B60 - 5B67 +PB60: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +sub cx,byte 5 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5B68 - 5B6F +PB68: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,byte 5 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5B70 - 5B77 +PB70: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,byte 5 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5B78 +PB78: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +sub cx,byte 5 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5B79 +PB79: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +sub cx,byte 5 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5B80 - 5B87 +PB80: +and ebx,byte 7 +sub dword[ebp+__dreg+ebx*4],byte 5 +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5B88 - 5B8F +PB88: +and ebx,byte 7 +sub dword[ebp+__areg+ebx*4],byte 5 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5B90 - 5B97 +PB90: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,byte 5 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5B98 - 5B9F +PB98: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,byte 5 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5BA0 - 5BA7 +PBA0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +sub ecx,byte 5 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5BA8 - 5BAF +PBA8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,byte 5 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5BB0 - 5BB7 +PBB0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,byte 5 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5BB8 +PBB8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +sub ecx,byte 5 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5BB9 +PBB9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +sub ecx,byte 5 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5BC0 - 5BC7 +PBC0: +and ebx,byte 7 +xor ecx,ecx +or ah,ah +sets cl +sub edi,ecx +sub edi,ecx +neg cl +mov [ebp+__dreg+ebx*4],cl +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5BC8 - 5BCF +PBC8: +or ah,ah +jns near r_dbra +add esi,byte 2 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5BD0 - 5BD7 +PBD0: +and ebx,byte 7 +or ah,ah +sets cl +neg cl +mov edx,[ebp+__areg+ebx*4] +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5BD8 - 5BDF +PBD8: +and ebx,byte 7 +or ah,ah +sets cl +neg cl +mov edx,[ebp+__areg+ebx*4] +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5BE0 - 5BE7 +PBE0: +and ebx,byte 7 +or ah,ah +sets cl +neg cl +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5BE8 - 5BEF +PBE8: +and ebx,byte 7 +or ah,ah +sets cl +neg cl +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5BF0 - 5BF7 +PBF0: +and ebx,byte 7 +or ah,ah +sets cl +neg cl +call decode_ext +add edx,[ebp+__areg+ebx*4] +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5BF8 +PBF8: +or ah,ah +sets cl +neg cl +movsx edx,word[esi] +add esi,byte 2 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5BF9 +PBF9: +or ah,ah +sets cl +neg cl +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5C00 - 5C07 +PC00: +and ebx,byte 7 +add byte[ebp+__dreg+ebx*4],byte 6 +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5C10 - 5C17 +PC10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,byte 6 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5C18 - 5C1F +PC18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,byte 6 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5C20 - 5C27 +PC20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +add cl,byte 6 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5C28 - 5C2F +PC28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,byte 6 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5C30 - 5C37 +PC30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,byte 6 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5C38 +PC38: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +add cl,byte 6 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5C39 +PC39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +add cl,byte 6 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5C40 - 5C47 +PC40: +and ebx,byte 7 +add word[ebp+__dreg+ebx*4],byte 6 +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5C48 - 5C4F +PC48: +and ebx,byte 7 +add dword[ebp+__areg+ebx*4],byte 6 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5C50 - 5C57 +PC50: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,byte 6 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5C58 - 5C5F +PC58: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,byte 6 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5C60 - 5C67 +PC60: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +add cx,byte 6 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5C68 - 5C6F +PC68: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,byte 6 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5C70 - 5C77 +PC70: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,byte 6 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5C78 +PC78: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +add cx,byte 6 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5C79 +PC79: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +add cx,byte 6 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5C80 - 5C87 +PC80: +and ebx,byte 7 +add dword[ebp+__dreg+ebx*4],byte 6 +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5C88 - 5C8F +PC88: +and ebx,byte 7 +add dword[ebp+__areg+ebx*4],byte 6 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5C90 - 5C97 +PC90: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,byte 6 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5C98 - 5C9F +PC98: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,byte 6 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5CA0 - 5CA7 +PCA0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +add ecx,byte 6 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5CA8 - 5CAF +PCA8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,byte 6 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5CB0 - 5CB7 +PCB0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,byte 6 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5CB8 +PCB8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +add ecx,byte 6 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5CB9 +PCB9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +add ecx,byte 6 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5CC0 - 5CC7 +PCC0: +and ebx,byte 7 +xor ecx,ecx +push eax +neg al +xor al,ah +pop eax +setns cl +sub edi,ecx +sub edi,ecx +neg cl +mov [ebp+__dreg+ebx*4],cl +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5CC8 - 5CCF +PCC8: +push eax +neg al +xor al,ah +pop eax +js near r_dbra +add esi,byte 2 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5CD0 - 5CD7 +PCD0: +and ebx,byte 7 +push eax +neg al +xor al,ah +pop eax +setns cl +neg cl +mov edx,[ebp+__areg+ebx*4] +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5CD8 - 5CDF +PCD8: +and ebx,byte 7 +push eax +neg al +xor al,ah +pop eax +setns cl +neg cl +mov edx,[ebp+__areg+ebx*4] +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5CE0 - 5CE7 +PCE0: +and ebx,byte 7 +push eax +neg al +xor al,ah +pop eax +setns cl +neg cl +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5CE8 - 5CEF +PCE8: +and ebx,byte 7 +push eax +neg al +xor al,ah +pop eax +setns cl +neg cl +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5CF0 - 5CF7 +PCF0: +and ebx,byte 7 +push eax +neg al +xor al,ah +pop eax +setns cl +neg cl +call decode_ext +add edx,[ebp+__areg+ebx*4] +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5CF8 +PCF8: +push eax +neg al +xor al,ah +pop eax +setns cl +neg cl +movsx edx,word[esi] +add esi,byte 2 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5CF9 +PCF9: +push eax +neg al +xor al,ah +pop eax +setns cl +neg cl +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5D00 - 5D07 +PD00: +and ebx,byte 7 +sub byte[ebp+__dreg+ebx*4],byte 6 +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5D10 - 5D17 +PD10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,byte 6 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5D18 - 5D1F +PD18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,byte 6 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5D20 - 5D27 +PD20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +sub cl,byte 6 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5D28 - 5D2F +PD28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,byte 6 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5D30 - 5D37 +PD30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,byte 6 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5D38 +PD38: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +sub cl,byte 6 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5D39 +PD39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +sub cl,byte 6 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5D40 - 5D47 +PD40: +and ebx,byte 7 +sub word[ebp+__dreg+ebx*4],byte 6 +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5D48 - 5D4F +PD48: +and ebx,byte 7 +sub dword[ebp+__areg+ebx*4],byte 6 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5D50 - 5D57 +PD50: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,byte 6 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5D58 - 5D5F +PD58: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,byte 6 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5D60 - 5D67 +PD60: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +sub cx,byte 6 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5D68 - 5D6F +PD68: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,byte 6 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5D70 - 5D77 +PD70: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,byte 6 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5D78 +PD78: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +sub cx,byte 6 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5D79 +PD79: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +sub cx,byte 6 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5D80 - 5D87 +PD80: +and ebx,byte 7 +sub dword[ebp+__dreg+ebx*4],byte 6 +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5D88 - 5D8F +PD88: +and ebx,byte 7 +sub dword[ebp+__areg+ebx*4],byte 6 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5D90 - 5D97 +PD90: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,byte 6 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5D98 - 5D9F +PD98: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,byte 6 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5DA0 - 5DA7 +PDA0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +sub ecx,byte 6 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5DA8 - 5DAF +PDA8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,byte 6 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5DB0 - 5DB7 +PDB0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,byte 6 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5DB8 +PDB8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +sub ecx,byte 6 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5DB9 +PDB9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +sub ecx,byte 6 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5DC0 - 5DC7 +PDC0: +and ebx,byte 7 +xor ecx,ecx +push eax +neg al +xor al,ah +pop eax +sets cl +sub edi,ecx +sub edi,ecx +neg cl +mov [ebp+__dreg+ebx*4],cl +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5DC8 - 5DCF +PDC8: +push eax +neg al +xor al,ah +pop eax +jns near r_dbra +add esi,byte 2 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5DD0 - 5DD7 +PDD0: +and ebx,byte 7 +push eax +neg al +xor al,ah +pop eax +sets cl +neg cl +mov edx,[ebp+__areg+ebx*4] +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5DD8 - 5DDF +PDD8: +and ebx,byte 7 +push eax +neg al +xor al,ah +pop eax +sets cl +neg cl +mov edx,[ebp+__areg+ebx*4] +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5DE0 - 5DE7 +PDE0: +and ebx,byte 7 +push eax +neg al +xor al,ah +pop eax +sets cl +neg cl +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5DE8 - 5DEF +PDE8: +and ebx,byte 7 +push eax +neg al +xor al,ah +pop eax +sets cl +neg cl +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5DF0 - 5DF7 +PDF0: +and ebx,byte 7 +push eax +neg al +xor al,ah +pop eax +sets cl +neg cl +call decode_ext +add edx,[ebp+__areg+ebx*4] +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5DF8 +PDF8: +push eax +neg al +xor al,ah +pop eax +sets cl +neg cl +movsx edx,word[esi] +add esi,byte 2 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5DF9 +PDF9: +push eax +neg al +xor al,ah +pop eax +sets cl +neg cl +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5E00 - 5E07 +PE00: +and ebx,byte 7 +add byte[ebp+__dreg+ebx*4],byte 7 +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5E10 - 5E17 +PE10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,byte 7 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5E18 - 5E1F +PE18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,byte 7 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5E20 - 5E27 +PE20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +add cl,byte 7 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5E28 - 5E2F +PE28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,byte 7 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5E30 - 5E37 +PE30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,byte 7 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5E38 +PE38: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +add cl,byte 7 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5E39 +PE39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +add cl,byte 7 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5E40 - 5E47 +PE40: +and ebx,byte 7 +add word[ebp+__dreg+ebx*4],byte 7 +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5E48 - 5E4F +PE48: +and ebx,byte 7 +add dword[ebp+__areg+ebx*4],byte 7 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5E50 - 5E57 +PE50: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,byte 7 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5E58 - 5E5F +PE58: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,byte 7 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5E60 - 5E67 +PE60: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +add cx,byte 7 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5E68 - 5E6F +PE68: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,byte 7 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5E70 - 5E77 +PE70: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,byte 7 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5E78 +PE78: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +add cx,byte 7 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5E79 +PE79: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +add cx,byte 7 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5E80 - 5E87 +PE80: +and ebx,byte 7 +add dword[ebp+__dreg+ebx*4],byte 7 +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5E88 - 5E8F +PE88: +and ebx,byte 7 +add dword[ebp+__areg+ebx*4],byte 7 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5E90 - 5E97 +PE90: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,byte 7 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5E98 - 5E9F +PE98: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,byte 7 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5EA0 - 5EA7 +PEA0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +add ecx,byte 7 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5EA8 - 5EAF +PEA8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,byte 7 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5EB0 - 5EB7 +PEB0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,byte 7 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5EB8 +PEB8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +add ecx,byte 7 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5EB9 +PEB9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +add ecx,byte 7 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5EC0 - 5EC7 +PEC0: +and ebx,byte 7 +xor ecx,ecx +push eax +neg al +xor al,ah +add ah,ah +or al,ah +pop eax +setns cl +sub edi,ecx +sub edi,ecx +neg cl +mov [ebp+__dreg+ebx*4],cl +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5EC8 - 5ECF +PEC8: +push eax +neg al +xor al,ah +add ah,ah +or al,ah +pop eax +js near r_dbra +add esi,byte 2 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5ED0 - 5ED7 +PED0: +and ebx,byte 7 +push eax +neg al +xor al,ah +add ah,ah +or al,ah +pop eax +setns cl +neg cl +mov edx,[ebp+__areg+ebx*4] +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5ED8 - 5EDF +PED8: +and ebx,byte 7 +push eax +neg al +xor al,ah +add ah,ah +or al,ah +pop eax +setns cl +neg cl +mov edx,[ebp+__areg+ebx*4] +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5EE0 - 5EE7 +PEE0: +and ebx,byte 7 +push eax +neg al +xor al,ah +add ah,ah +or al,ah +pop eax +setns cl +neg cl +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5EE8 - 5EEF +PEE8: +and ebx,byte 7 +push eax +neg al +xor al,ah +add ah,ah +or al,ah +pop eax +setns cl +neg cl +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5EF0 - 5EF7 +PEF0: +and ebx,byte 7 +push eax +neg al +xor al,ah +add ah,ah +or al,ah +pop eax +setns cl +neg cl +call decode_ext +add edx,[ebp+__areg+ebx*4] +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5EF8 +PEF8: +push eax +neg al +xor al,ah +add ah,ah +or al,ah +pop eax +setns cl +neg cl +movsx edx,word[esi] +add esi,byte 2 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5EF9 +PEF9: +push eax +neg al +xor al,ah +add ah,ah +or al,ah +pop eax +setns cl +neg cl +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5F00 - 5F07 +PF00: +and ebx,byte 7 +sub byte[ebp+__dreg+ebx*4],byte 7 +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5F10 - 5F17 +PF10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,byte 7 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5F18 - 5F1F +PF18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,byte 7 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5F20 - 5F27 +PF20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +sub cl,byte 7 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5F28 - 5F2F +PF28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,byte 7 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5F30 - 5F37 +PF30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,byte 7 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5F38 +PF38: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +sub cl,byte 7 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5F39 +PF39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +sub cl,byte 7 +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5F40 - 5F47 +PF40: +and ebx,byte 7 +sub word[ebp+__dreg+ebx*4],byte 7 +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5F48 - 5F4F +PF48: +and ebx,byte 7 +sub dword[ebp+__areg+ebx*4],byte 7 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5F50 - 5F57 +PF50: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,byte 7 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5F58 - 5F5F +PF58: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,byte 7 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5F60 - 5F67 +PF60: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +sub cx,byte 7 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5F68 - 5F6F +PF68: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,byte 7 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5F70 - 5F77 +PF70: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,byte 7 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5F78 +PF78: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +sub cx,byte 7 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5F79 +PF79: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +sub cx,byte 7 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5F80 - 5F87 +PF80: +and ebx,byte 7 +sub dword[ebp+__dreg+ebx*4],byte 7 +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5F88 - 5F8F +PF88: +and ebx,byte 7 +sub dword[ebp+__areg+ebx*4],byte 7 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5F90 - 5F97 +PF90: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,byte 7 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5F98 - 5F9F +PF98: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,byte 7 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5FA0 - 5FA7 +PFA0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +sub ecx,byte 7 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5FA8 - 5FAF +PFA8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,byte 7 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5FB0 - 5FB7 +PFB0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,byte 7 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5FB8 +PFB8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +sub ecx,byte 7 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5FB9 +PFB9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +sub ecx,byte 7 +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5FC0 - 5FC7 +PFC0: +and ebx,byte 7 +xor ecx,ecx +push eax +neg al +xor al,ah +add ah,ah +or al,ah +pop eax +sets cl +sub edi,ecx +sub edi,ecx +neg cl +mov [ebp+__dreg+ebx*4],cl +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5FC8 - 5FCF +PFC8: +push eax +neg al +xor al,ah +add ah,ah +or al,ah +pop eax +jns near r_dbra +add esi,byte 2 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5FD0 - 5FD7 +PFD0: +and ebx,byte 7 +push eax +neg al +xor al,ah +add ah,ah +or al,ah +pop eax +sets cl +neg cl +mov edx,[ebp+__areg+ebx*4] +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5FD8 - 5FDF +PFD8: +and ebx,byte 7 +push eax +neg al +xor al,ah +add ah,ah +or al,ah +pop eax +sets cl +neg cl +mov edx,[ebp+__areg+ebx*4] +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5FE0 - 5FE7 +PFE0: +and ebx,byte 7 +push eax +neg al +xor al,ah +add ah,ah +or al,ah +pop eax +sets cl +neg cl +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5FE8 - 5FEF +PFE8: +and ebx,byte 7 +push eax +neg al +xor al,ah +add ah,ah +or al,ah +pop eax +sets cl +neg cl +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 5FF0 - 5FF7 +PFF0: +and ebx,byte 7 +push eax +neg al +xor al,ah +add ah,ah +or al,ah +pop eax +sets cl +neg cl +call decode_ext +add edx,[ebp+__areg+ebx*4] +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5FF8 +PFF8: +push eax +neg al +xor al,ah +add ah,ah +or al,ah +pop eax +sets cl +neg cl +movsx edx,word[esi] +add esi,byte 2 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 5FF9 +PFF9: +push eax +neg al +xor al,ah +add ah,ah +or al,ah +pop eax +sets cl +neg cl +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 6000 +Q000: +r_bra_w: +movsx ebx,word[esi] +add esi,ebx +xor ebx,ebx +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 6001 - 60FF +Q001: +r_bra_b: +movsx ebx,bl +add esi,ebx +xor ebx,ebx +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 6100 +Q100: +movsx ebx,word[esi] +mov ecx,esi +add ecx,byte 2 +sub ecx,[ebp+__io_fetchbase] +add esi,ebx +xor ebx,ebx +mov edx,[ebp+__areg+28] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+28],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 6101 - 61FF +Q101: +movsx ebx,bl +mov ecx,esi +sub ecx,[ebp+__io_fetchbase] +add esi,ebx +xor ebx,ebx +mov edx,[ebp+__areg+28] +sub edx,byte 4 +call writememorydword +mov [ebp+__areg+28],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 6200 +Q200: +test ah,41h +jz near r_bra_w +add esi,byte 2 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 6201 - 62FF +Q201: +test ah,41h +jz near r_bra_b +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 6300 +Q300: +test ah,41h +jnz near r_bra_w +add esi,byte 2 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 6301 - 63FF +Q301: +test ah,41h +jnz near r_bra_b +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 6400 +Q400: +test ah,1 +jz near r_bra_w +add esi,byte 2 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 6401 - 64FF +Q401: +test ah,1 +jz near r_bra_b +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 6500 +Q500: +test ah,1 +jnz near r_bra_w +add esi,byte 2 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 6501 - 65FF +Q501: +test ah,1 +jnz near r_bra_b +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 6600 +Q600: +test ah,40h +jz near r_bra_w +add esi,byte 2 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 6601 - 66FF +Q601: +test ah,40h +jz near r_bra_b +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 6700 +Q700: +test ah,40h +jnz near r_bra_w +add esi,byte 2 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 6701 - 67FF +Q701: +test ah,40h +jnz near r_bra_b +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 6800 +Q800: +test al,1 +jz near r_bra_w +add esi,byte 2 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 6801 - 68FF +Q801: +test al,1 +jz near r_bra_b +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 6900 +Q900: +test al,1 +jnz near r_bra_w +add esi,byte 2 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 6901 - 69FF +Q901: +test al,1 +jnz near r_bra_b +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 6A00 +QA00: +or ah,ah +jns near r_bra_w +add esi,byte 2 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 6A01 - 6AFF +QA01: +or ah,ah +jns near r_bra_b +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 6B00 +QB00: +or ah,ah +js near r_bra_w +add esi,byte 2 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 6B01 - 6BFF +QB01: +or ah,ah +js near r_bra_b +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 6C00 +QC00: +push eax +neg al +xor al,ah +pop eax +jns near r_bra_w +add esi,byte 2 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 6C01 - 6CFF +QC01: +push eax +neg al +xor al,ah +pop eax +jns near r_bra_b +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 6D00 +QD00: +push eax +neg al +xor al,ah +pop eax +js near r_bra_w +add esi,byte 2 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 6D01 - 6DFF +QD01: +push eax +neg al +xor al,ah +pop eax +js near r_bra_b +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 6E00 +QE00: +push eax +neg al +xor al,ah +add ah,ah +or al,ah +pop eax +jns near r_bra_w +add esi,byte 2 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 6E01 - 6EFF +QE01: +push eax +neg al +xor al,ah +add ah,ah +or al,ah +pop eax +jns near r_bra_b +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 6F00 +QF00: +push eax +neg al +xor al,ah +add ah,ah +or al,ah +pop eax +js near r_bra_w +add esi,byte 2 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 6F01 - 6FFF +QF01: +push eax +neg al +xor al,ah +add ah,ah +or al,ah +pop eax +js near r_bra_b +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 7000 - 70FF +R000: +movsx ecx,bl +mov [ebp+__dreg+0],ecx +test cl,cl +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 7200 - 72FF +R200: +movsx ecx,bl +mov [ebp+__dreg+4],ecx +test cl,cl +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 7400 - 74FF +R400: +movsx ecx,bl +mov [ebp+__dreg+8],ecx +test cl,cl +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 7600 - 76FF +R600: +movsx ecx,bl +mov [ebp+__dreg+12],ecx +test cl,cl +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 7800 - 78FF +R800: +movsx ecx,bl +mov [ebp+__dreg+16],ecx +test cl,cl +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 7A00 - 7AFF +RA00: +movsx ecx,bl +mov [ebp+__dreg+20],ecx +test cl,cl +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 7C00 - 7CFF +RC00: +movsx ecx,bl +mov [ebp+__dreg+24],ecx +test cl,cl +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 7E00 - 7EFF +RE00: +movsx ecx,bl +mov [ebp+__dreg+28],ecx +test cl,cl +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8000 - 8007 +S000: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +or [ebp+__dreg+0],cl +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8010 - 8017 +S010: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +or [ebp+__dreg+0],cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8018 - 801F +S018: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +or [ebp+__dreg+0],cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8020 - 8027 +S020: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +or [ebp+__dreg+0],cl +lahf +mov al,0 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8028 - 802F +S028: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +or [ebp+__dreg+0],cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8030 - 8037 +S030: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +or [ebp+__dreg+0],cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8038 +S038: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +or [ebp+__dreg+0],cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8039 +S039: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +or [ebp+__dreg+0],cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 803A +S03A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +or [ebp+__dreg+0],cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 803B +S03B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +or [ebp+__dreg+0],cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 803C +S03C: +mov cx,[esi] +add esi,byte 2 +or [ebp+__dreg+0],cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8040 - 8047 +S040: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +or [ebp+__dreg+0],cx +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8050 - 8057 +S050: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +or [ebp+__dreg+0],cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8058 - 805F +S058: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +or [ebp+__dreg+0],cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8060 - 8067 +S060: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +or [ebp+__dreg+0],cx +lahf +mov al,0 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8068 - 806F +S068: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +or [ebp+__dreg+0],cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8070 - 8077 +S070: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +or [ebp+__dreg+0],cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8078 +S078: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +or [ebp+__dreg+0],cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8079 +S079: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +or [ebp+__dreg+0],cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 807A +S07A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +or [ebp+__dreg+0],cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 807B +S07B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +or [ebp+__dreg+0],cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 807C +S07C: +mov cx,[esi] +add esi,byte 2 +or [ebp+__dreg+0],cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8080 - 8087 +S080: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +or [ebp+__dreg+0],ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8090 - 8097 +S090: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +or [ebp+__dreg+0],ecx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8098 - 809F +S098: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +or [ebp+__dreg+0],ecx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 80A0 - 80A7 +S0A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +or [ebp+__dreg+0],ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 80A8 - 80AF +S0A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +or [ebp+__dreg+0],ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 80B0 - 80B7 +S0B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +or [ebp+__dreg+0],ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 80B8 +S0B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +or [ebp+__dreg+0],ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 80B9 +S0B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +or [ebp+__dreg+0],ecx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 80BA +S0BA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +or [ebp+__dreg+0],ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 80BB +S0BB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +or [ebp+__dreg+0],ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 80BC +S0BC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +or [ebp+__dreg+0],ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 80C0 - 80C7 +S0C0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +jnz short ln1066 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1068 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1069 +ln1068: +call basefunction +ln1069: +add esi,[ebp+__io_fetchbase] +sub edi,byte 38 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1066: +and ecx,0FFFFh +mov eax,[ebp+__dreg+0] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1067 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+0],edx +sub edi,133 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1067: +mov ax,1 +sub edi,133 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 80D0 - 80D7 +S0D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +test cx,cx +jnz short ln1070 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1072 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1073 +ln1072: +call basefunction +ln1073: +add esi,[ebp+__io_fetchbase] +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1070: +and ecx,0FFFFh +mov eax,[ebp+__dreg+0] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1071 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+0],edx +sub edi,137 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1071: +mov ax,1 +sub edi,137 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 80D8 - 80DF +S0D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +test cx,cx +jnz short ln1074 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1076 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1077 +ln1076: +call basefunction +ln1077: +add esi,[ebp+__io_fetchbase] +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1074: +and ecx,0FFFFh +mov eax,[ebp+__dreg+0] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1075 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+0],edx +sub edi,137 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1075: +mov ax,1 +sub edi,137 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 80E0 - 80E7 +S0E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +test cx,cx +jnz short ln1078 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1080 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1081 +ln1080: +call basefunction +ln1081: +add esi,[ebp+__io_fetchbase] +sub edi,byte 44 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1078: +and ecx,0FFFFh +mov eax,[ebp+__dreg+0] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1079 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+0],edx +sub edi,139 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1079: +mov ax,1 +sub edi,139 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 80E8 - 80EF +S0E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +test cx,cx +jnz short ln1082 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1084 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1085 +ln1084: +call basefunction +ln1085: +add esi,[ebp+__io_fetchbase] +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1082: +and ecx,0FFFFh +mov eax,[ebp+__dreg+0] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1083 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+0],edx +sub edi,141 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1083: +mov ax,1 +sub edi,141 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 80F0 - 80F7 +S0F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +test cx,cx +jnz short ln1086 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1088 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1089 +ln1088: +call basefunction +ln1089: +add esi,[ebp+__io_fetchbase] +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1086: +and ecx,0FFFFh +mov eax,[ebp+__dreg+0] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1087 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+0],edx +sub edi,143 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1087: +mov ax,1 +sub edi,143 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 80F8 +S0F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +test cx,cx +jnz short ln1090 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1092 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1093 +ln1092: +call basefunction +ln1093: +add esi,[ebp+__io_fetchbase] +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1090: +and ecx,0FFFFh +mov eax,[ebp+__dreg+0] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1091 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+0],edx +sub edi,141 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1091: +mov ax,1 +sub edi,141 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 80F9 +S0F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +test cx,cx +jnz short ln1094 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1096 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1097 +ln1096: +call basefunction +ln1097: +add esi,[ebp+__io_fetchbase] +sub edi,byte 50 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1094: +and ecx,0FFFFh +mov eax,[ebp+__dreg+0] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1095 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+0],edx +sub edi,145 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1095: +mov ax,1 +sub edi,145 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 80FA +S0FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +test cx,cx +jnz short ln1098 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1100 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1101 +ln1100: +call basefunction +ln1101: +add esi,[ebp+__io_fetchbase] +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1098: +and ecx,0FFFFh +mov eax,[ebp+__dreg+0] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1099 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+0],edx +sub edi,141 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1099: +mov ax,1 +sub edi,141 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 80FB +S0FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +test cx,cx +jnz short ln1102 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1104 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1105 +ln1104: +call basefunction +ln1105: +add esi,[ebp+__io_fetchbase] +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1102: +and ecx,0FFFFh +mov eax,[ebp+__dreg+0] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1103 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+0],edx +sub edi,143 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1103: +mov ax,1 +sub edi,143 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 80FC +S0FC: +mov cx,[esi] +add esi,byte 2 +test cx,cx +jnz short ln1106 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1108 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1109 +ln1108: +call basefunction +ln1109: +add esi,[ebp+__io_fetchbase] +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1106: +and ecx,0FFFFh +mov eax,[ebp+__dreg+0] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1107 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+0],edx +sub edi,137 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1107: +mov ax,1 +sub edi,137 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8100 - 8107 +S100: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+0] +sbb al,[ebp+__dreg+ebx*4] +das +mov [ebp+__dreg+0],al +lahf +mov al,0 +setc [ebp+__xflag] +jnz short ln1110 +or ch,0BFh +and ah,ch +ln1110: +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8108 - 810F +S108: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+0] +dec edx +call readmemorybyte +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +sbb al,bl +das +mov ebx,eax +lahf +mov al,0 +setc [ebp+__xflag] +jnz short ln1111 +or ch,0BFh +and ah,ch +ln1111: +mov ecx,ebx +xor ebx,ebx +call writememorybyte +mov [ebp+__areg+0],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8110 - 8117 +S110: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +or cl,[ebp+__dreg+0] +lahf +mov al,0 +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8118 - 811F +S118: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +or cl,[ebp+__dreg+0] +lahf +mov al,0 +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8120 - 8127 +S120: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +or cl,[ebp+__dreg+0] +lahf +mov al,0 +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8128 - 812F +S128: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +or cl,[ebp+__dreg+0] +lahf +mov al,0 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8130 - 8137 +S130: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +or cl,[ebp+__dreg+0] +lahf +mov al,0 +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8138 +S138: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +or cl,[ebp+__dreg+0] +lahf +mov al,0 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8139 +S139: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +or cl,[ebp+__dreg+0] +lahf +mov al,0 +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8150 - 8157 +S150: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +or cx,[ebp+__dreg+0] +lahf +mov al,0 +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8158 - 815F +S158: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +or cx,[ebp+__dreg+0] +lahf +mov al,0 +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8160 - 8167 +S160: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +or cx,[ebp+__dreg+0] +lahf +mov al,0 +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8168 - 816F +S168: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +or cx,[ebp+__dreg+0] +lahf +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8170 - 8177 +S170: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +or cx,[ebp+__dreg+0] +lahf +mov al,0 +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8178 +S178: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +or cx,[ebp+__dreg+0] +lahf +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8179 +S179: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +or cx,[ebp+__dreg+0] +lahf +mov al,0 +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8190 - 8197 +S190: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +or ecx,[ebp+__dreg+0] +lahf +mov al,0 +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8198 - 819F +S198: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +or ecx,[ebp+__dreg+0] +lahf +mov al,0 +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 81A0 - 81A7 +S1A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +or ecx,[ebp+__dreg+0] +lahf +mov al,0 +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 81A8 - 81AF +S1A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +or ecx,[ebp+__dreg+0] +lahf +mov al,0 +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 81B0 - 81B7 +S1B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +or ecx,[ebp+__dreg+0] +lahf +mov al,0 +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 81B8 +S1B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +or ecx,[ebp+__dreg+0] +lahf +mov al,0 +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 81B9 +S1B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +or ecx,[ebp+__dreg+0] +lahf +mov al,0 +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 81C0 - 81C7 +S1C0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +jnz short ln1112 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1114 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1115 +ln1114: +call basefunction +ln1115: +add esi,[ebp+__io_fetchbase] +sub edi,byte 38 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1112: +movsx ecx,cx +mov eax,[ebp+__dreg+0] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1116 +inc ecx +jne short ln1113 +ln1116: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+0],edx +sub edi,150 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1113: +mov ax,1 +sub edi,150 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 81D0 - 81D7 +S1D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +test cx,cx +jnz short ln1117 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1119 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1120 +ln1119: +call basefunction +ln1120: +add esi,[ebp+__io_fetchbase] +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1117: +movsx ecx,cx +mov eax,[ebp+__dreg+0] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1121 +inc ecx +jne short ln1118 +ln1121: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+0],edx +sub edi,154 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1118: +mov ax,1 +sub edi,154 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 81D8 - 81DF +S1D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +test cx,cx +jnz short ln1122 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1124 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1125 +ln1124: +call basefunction +ln1125: +add esi,[ebp+__io_fetchbase] +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1122: +movsx ecx,cx +mov eax,[ebp+__dreg+0] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1126 +inc ecx +jne short ln1123 +ln1126: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+0],edx +sub edi,154 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1123: +mov ax,1 +sub edi,154 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 81E0 - 81E7 +S1E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +test cx,cx +jnz short ln1127 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1129 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1130 +ln1129: +call basefunction +ln1130: +add esi,[ebp+__io_fetchbase] +sub edi,byte 44 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1127: +movsx ecx,cx +mov eax,[ebp+__dreg+0] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1131 +inc ecx +jne short ln1128 +ln1131: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+0],edx +sub edi,156 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1128: +mov ax,1 +sub edi,156 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 81E8 - 81EF +S1E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +test cx,cx +jnz short ln1132 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1134 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1135 +ln1134: +call basefunction +ln1135: +add esi,[ebp+__io_fetchbase] +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1132: +movsx ecx,cx +mov eax,[ebp+__dreg+0] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1136 +inc ecx +jne short ln1133 +ln1136: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+0],edx +sub edi,158 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1133: +mov ax,1 +sub edi,158 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 81F0 - 81F7 +S1F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +test cx,cx +jnz short ln1137 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1139 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1140 +ln1139: +call basefunction +ln1140: +add esi,[ebp+__io_fetchbase] +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1137: +movsx ecx,cx +mov eax,[ebp+__dreg+0] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1141 +inc ecx +jne short ln1138 +ln1141: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+0],edx +sub edi,160 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1138: +mov ax,1 +sub edi,160 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 81F8 +S1F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +test cx,cx +jnz short ln1142 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1144 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1145 +ln1144: +call basefunction +ln1145: +add esi,[ebp+__io_fetchbase] +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1142: +movsx ecx,cx +mov eax,[ebp+__dreg+0] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1146 +inc ecx +jne short ln1143 +ln1146: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+0],edx +sub edi,158 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1143: +mov ax,1 +sub edi,158 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 81F9 +S1F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +test cx,cx +jnz short ln1147 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1149 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1150 +ln1149: +call basefunction +ln1150: +add esi,[ebp+__io_fetchbase] +sub edi,byte 50 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1147: +movsx ecx,cx +mov eax,[ebp+__dreg+0] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1151 +inc ecx +jne short ln1148 +ln1151: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+0],edx +sub edi,162 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1148: +mov ax,1 +sub edi,162 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 81FA +S1FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +test cx,cx +jnz short ln1152 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1154 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1155 +ln1154: +call basefunction +ln1155: +add esi,[ebp+__io_fetchbase] +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1152: +movsx ecx,cx +mov eax,[ebp+__dreg+0] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1156 +inc ecx +jne short ln1153 +ln1156: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+0],edx +sub edi,158 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1153: +mov ax,1 +sub edi,158 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 81FB +S1FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +test cx,cx +jnz short ln1157 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1159 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1160 +ln1159: +call basefunction +ln1160: +add esi,[ebp+__io_fetchbase] +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1157: +movsx ecx,cx +mov eax,[ebp+__dreg+0] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1161 +inc ecx +jne short ln1158 +ln1161: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+0],edx +sub edi,160 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1158: +mov ax,1 +sub edi,160 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 81FC +S1FC: +mov cx,[esi] +add esi,byte 2 +test cx,cx +jnz short ln1162 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1164 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1165 +ln1164: +call basefunction +ln1165: +add esi,[ebp+__io_fetchbase] +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1162: +movsx ecx,cx +mov eax,[ebp+__dreg+0] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1166 +inc ecx +jne short ln1163 +ln1166: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+0],edx +sub edi,154 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1163: +mov ax,1 +sub edi,154 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8200 - 8207 +S200: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +or [ebp+__dreg+4],cl +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8210 - 8217 +S210: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +or [ebp+__dreg+4],cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8218 - 821F +S218: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +or [ebp+__dreg+4],cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8220 - 8227 +S220: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +or [ebp+__dreg+4],cl +lahf +mov al,0 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8228 - 822F +S228: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +or [ebp+__dreg+4],cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8230 - 8237 +S230: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +or [ebp+__dreg+4],cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8238 +S238: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +or [ebp+__dreg+4],cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8239 +S239: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +or [ebp+__dreg+4],cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 823A +S23A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +or [ebp+__dreg+4],cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 823B +S23B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +or [ebp+__dreg+4],cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 823C +S23C: +mov cx,[esi] +add esi,byte 2 +or [ebp+__dreg+4],cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8240 - 8247 +S240: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +or [ebp+__dreg+4],cx +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8250 - 8257 +S250: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +or [ebp+__dreg+4],cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8258 - 825F +S258: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +or [ebp+__dreg+4],cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8260 - 8267 +S260: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +or [ebp+__dreg+4],cx +lahf +mov al,0 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8268 - 826F +S268: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +or [ebp+__dreg+4],cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8270 - 8277 +S270: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +or [ebp+__dreg+4],cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8278 +S278: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +or [ebp+__dreg+4],cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8279 +S279: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +or [ebp+__dreg+4],cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 827A +S27A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +or [ebp+__dreg+4],cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 827B +S27B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +or [ebp+__dreg+4],cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 827C +S27C: +mov cx,[esi] +add esi,byte 2 +or [ebp+__dreg+4],cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8280 - 8287 +S280: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +or [ebp+__dreg+4],ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8290 - 8297 +S290: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +or [ebp+__dreg+4],ecx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8298 - 829F +S298: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +or [ebp+__dreg+4],ecx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 82A0 - 82A7 +S2A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +or [ebp+__dreg+4],ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 82A8 - 82AF +S2A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +or [ebp+__dreg+4],ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 82B0 - 82B7 +S2B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +or [ebp+__dreg+4],ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 82B8 +S2B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +or [ebp+__dreg+4],ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 82B9 +S2B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +or [ebp+__dreg+4],ecx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 82BA +S2BA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +or [ebp+__dreg+4],ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 82BB +S2BB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +or [ebp+__dreg+4],ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 82BC +S2BC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +or [ebp+__dreg+4],ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 82C0 - 82C7 +S2C0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +jnz short ln1167 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1169 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1170 +ln1169: +call basefunction +ln1170: +add esi,[ebp+__io_fetchbase] +sub edi,byte 38 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1167: +and ecx,0FFFFh +mov eax,[ebp+__dreg+4] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1168 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+4],edx +sub edi,133 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1168: +mov ax,1 +sub edi,133 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 82D0 - 82D7 +S2D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +test cx,cx +jnz short ln1171 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1173 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1174 +ln1173: +call basefunction +ln1174: +add esi,[ebp+__io_fetchbase] +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1171: +and ecx,0FFFFh +mov eax,[ebp+__dreg+4] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1172 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+4],edx +sub edi,137 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1172: +mov ax,1 +sub edi,137 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 82D8 - 82DF +S2D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +test cx,cx +jnz short ln1175 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1177 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1178 +ln1177: +call basefunction +ln1178: +add esi,[ebp+__io_fetchbase] +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1175: +and ecx,0FFFFh +mov eax,[ebp+__dreg+4] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1176 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+4],edx +sub edi,137 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1176: +mov ax,1 +sub edi,137 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 82E0 - 82E7 +S2E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +test cx,cx +jnz short ln1179 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1181 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1182 +ln1181: +call basefunction +ln1182: +add esi,[ebp+__io_fetchbase] +sub edi,byte 44 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1179: +and ecx,0FFFFh +mov eax,[ebp+__dreg+4] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1180 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+4],edx +sub edi,139 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1180: +mov ax,1 +sub edi,139 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 82E8 - 82EF +S2E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +test cx,cx +jnz short ln1183 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1185 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1186 +ln1185: +call basefunction +ln1186: +add esi,[ebp+__io_fetchbase] +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1183: +and ecx,0FFFFh +mov eax,[ebp+__dreg+4] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1184 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+4],edx +sub edi,141 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1184: +mov ax,1 +sub edi,141 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 82F0 - 82F7 +S2F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +test cx,cx +jnz short ln1187 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1189 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1190 +ln1189: +call basefunction +ln1190: +add esi,[ebp+__io_fetchbase] +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1187: +and ecx,0FFFFh +mov eax,[ebp+__dreg+4] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1188 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+4],edx +sub edi,143 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1188: +mov ax,1 +sub edi,143 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 82F8 +S2F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +test cx,cx +jnz short ln1191 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1193 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1194 +ln1193: +call basefunction +ln1194: +add esi,[ebp+__io_fetchbase] +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1191: +and ecx,0FFFFh +mov eax,[ebp+__dreg+4] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1192 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+4],edx +sub edi,141 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1192: +mov ax,1 +sub edi,141 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 82F9 +S2F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +test cx,cx +jnz short ln1195 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1197 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1198 +ln1197: +call basefunction +ln1198: +add esi,[ebp+__io_fetchbase] +sub edi,byte 50 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1195: +and ecx,0FFFFh +mov eax,[ebp+__dreg+4] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1196 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+4],edx +sub edi,145 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1196: +mov ax,1 +sub edi,145 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 82FA +S2FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +test cx,cx +jnz short ln1199 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1201 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1202 +ln1201: +call basefunction +ln1202: +add esi,[ebp+__io_fetchbase] +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1199: +and ecx,0FFFFh +mov eax,[ebp+__dreg+4] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1200 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+4],edx +sub edi,141 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1200: +mov ax,1 +sub edi,141 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 82FB +S2FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +test cx,cx +jnz short ln1203 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1205 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1206 +ln1205: +call basefunction +ln1206: +add esi,[ebp+__io_fetchbase] +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1203: +and ecx,0FFFFh +mov eax,[ebp+__dreg+4] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1204 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+4],edx +sub edi,143 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1204: +mov ax,1 +sub edi,143 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 82FC +S2FC: +mov cx,[esi] +add esi,byte 2 +test cx,cx +jnz short ln1207 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1209 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1210 +ln1209: +call basefunction +ln1210: +add esi,[ebp+__io_fetchbase] +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1207: +and ecx,0FFFFh +mov eax,[ebp+__dreg+4] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1208 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+4],edx +sub edi,137 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1208: +mov ax,1 +sub edi,137 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8300 - 8307 +S300: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+4] +sbb al,[ebp+__dreg+ebx*4] +das +mov [ebp+__dreg+4],al +lahf +mov al,0 +setc [ebp+__xflag] +jnz short ln1211 +or ch,0BFh +and ah,ch +ln1211: +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8308 - 830F +S308: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+4] +dec edx +call readmemorybyte +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +sbb al,bl +das +mov ebx,eax +lahf +mov al,0 +setc [ebp+__xflag] +jnz short ln1212 +or ch,0BFh +and ah,ch +ln1212: +mov ecx,ebx +xor ebx,ebx +call writememorybyte +mov [ebp+__areg+4],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8310 - 8317 +S310: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +or cl,[ebp+__dreg+4] +lahf +mov al,0 +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8318 - 831F +S318: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +or cl,[ebp+__dreg+4] +lahf +mov al,0 +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8320 - 8327 +S320: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +or cl,[ebp+__dreg+4] +lahf +mov al,0 +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8328 - 832F +S328: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +or cl,[ebp+__dreg+4] +lahf +mov al,0 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8330 - 8337 +S330: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +or cl,[ebp+__dreg+4] +lahf +mov al,0 +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8338 +S338: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +or cl,[ebp+__dreg+4] +lahf +mov al,0 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8339 +S339: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +or cl,[ebp+__dreg+4] +lahf +mov al,0 +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8350 - 8357 +S350: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +or cx,[ebp+__dreg+4] +lahf +mov al,0 +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8358 - 835F +S358: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +or cx,[ebp+__dreg+4] +lahf +mov al,0 +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8360 - 8367 +S360: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +or cx,[ebp+__dreg+4] +lahf +mov al,0 +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8368 - 836F +S368: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +or cx,[ebp+__dreg+4] +lahf +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8370 - 8377 +S370: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +or cx,[ebp+__dreg+4] +lahf +mov al,0 +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8378 +S378: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +or cx,[ebp+__dreg+4] +lahf +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8379 +S379: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +or cx,[ebp+__dreg+4] +lahf +mov al,0 +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8390 - 8397 +S390: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +or ecx,[ebp+__dreg+4] +lahf +mov al,0 +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8398 - 839F +S398: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +or ecx,[ebp+__dreg+4] +lahf +mov al,0 +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 83A0 - 83A7 +S3A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +or ecx,[ebp+__dreg+4] +lahf +mov al,0 +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 83A8 - 83AF +S3A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +or ecx,[ebp+__dreg+4] +lahf +mov al,0 +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 83B0 - 83B7 +S3B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +or ecx,[ebp+__dreg+4] +lahf +mov al,0 +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 83B8 +S3B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +or ecx,[ebp+__dreg+4] +lahf +mov al,0 +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 83B9 +S3B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +or ecx,[ebp+__dreg+4] +lahf +mov al,0 +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 83C0 - 83C7 +S3C0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +jnz short ln1213 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1215 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1216 +ln1215: +call basefunction +ln1216: +add esi,[ebp+__io_fetchbase] +sub edi,byte 38 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1213: +movsx ecx,cx +mov eax,[ebp+__dreg+4] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1217 +inc ecx +jne short ln1214 +ln1217: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+4],edx +sub edi,150 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1214: +mov ax,1 +sub edi,150 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 83D0 - 83D7 +S3D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +test cx,cx +jnz short ln1218 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1220 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1221 +ln1220: +call basefunction +ln1221: +add esi,[ebp+__io_fetchbase] +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1218: +movsx ecx,cx +mov eax,[ebp+__dreg+4] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1222 +inc ecx +jne short ln1219 +ln1222: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+4],edx +sub edi,154 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1219: +mov ax,1 +sub edi,154 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 83D8 - 83DF +S3D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +test cx,cx +jnz short ln1223 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1225 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1226 +ln1225: +call basefunction +ln1226: +add esi,[ebp+__io_fetchbase] +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1223: +movsx ecx,cx +mov eax,[ebp+__dreg+4] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1227 +inc ecx +jne short ln1224 +ln1227: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+4],edx +sub edi,154 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1224: +mov ax,1 +sub edi,154 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 83E0 - 83E7 +S3E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +test cx,cx +jnz short ln1228 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1230 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1231 +ln1230: +call basefunction +ln1231: +add esi,[ebp+__io_fetchbase] +sub edi,byte 44 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1228: +movsx ecx,cx +mov eax,[ebp+__dreg+4] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1232 +inc ecx +jne short ln1229 +ln1232: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+4],edx +sub edi,156 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1229: +mov ax,1 +sub edi,156 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 83E8 - 83EF +S3E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +test cx,cx +jnz short ln1233 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1235 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1236 +ln1235: +call basefunction +ln1236: +add esi,[ebp+__io_fetchbase] +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1233: +movsx ecx,cx +mov eax,[ebp+__dreg+4] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1237 +inc ecx +jne short ln1234 +ln1237: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+4],edx +sub edi,158 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1234: +mov ax,1 +sub edi,158 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 83F0 - 83F7 +S3F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +test cx,cx +jnz short ln1238 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1240 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1241 +ln1240: +call basefunction +ln1241: +add esi,[ebp+__io_fetchbase] +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1238: +movsx ecx,cx +mov eax,[ebp+__dreg+4] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1242 +inc ecx +jne short ln1239 +ln1242: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+4],edx +sub edi,160 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1239: +mov ax,1 +sub edi,160 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 83F8 +S3F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +test cx,cx +jnz short ln1243 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1245 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1246 +ln1245: +call basefunction +ln1246: +add esi,[ebp+__io_fetchbase] +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1243: +movsx ecx,cx +mov eax,[ebp+__dreg+4] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1247 +inc ecx +jne short ln1244 +ln1247: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+4],edx +sub edi,158 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1244: +mov ax,1 +sub edi,158 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 83F9 +S3F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +test cx,cx +jnz short ln1248 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1250 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1251 +ln1250: +call basefunction +ln1251: +add esi,[ebp+__io_fetchbase] +sub edi,byte 50 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1248: +movsx ecx,cx +mov eax,[ebp+__dreg+4] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1252 +inc ecx +jne short ln1249 +ln1252: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+4],edx +sub edi,162 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1249: +mov ax,1 +sub edi,162 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 83FA +S3FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +test cx,cx +jnz short ln1253 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1255 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1256 +ln1255: +call basefunction +ln1256: +add esi,[ebp+__io_fetchbase] +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1253: +movsx ecx,cx +mov eax,[ebp+__dreg+4] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1257 +inc ecx +jne short ln1254 +ln1257: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+4],edx +sub edi,158 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1254: +mov ax,1 +sub edi,158 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 83FB +S3FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +test cx,cx +jnz short ln1258 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1260 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1261 +ln1260: +call basefunction +ln1261: +add esi,[ebp+__io_fetchbase] +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1258: +movsx ecx,cx +mov eax,[ebp+__dreg+4] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1262 +inc ecx +jne short ln1259 +ln1262: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+4],edx +sub edi,160 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1259: +mov ax,1 +sub edi,160 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 83FC +S3FC: +mov cx,[esi] +add esi,byte 2 +test cx,cx +jnz short ln1263 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1265 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1266 +ln1265: +call basefunction +ln1266: +add esi,[ebp+__io_fetchbase] +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1263: +movsx ecx,cx +mov eax,[ebp+__dreg+4] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1267 +inc ecx +jne short ln1264 +ln1267: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+4],edx +sub edi,154 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1264: +mov ax,1 +sub edi,154 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8400 - 8407 +S400: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +or [ebp+__dreg+8],cl +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8410 - 8417 +S410: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +or [ebp+__dreg+8],cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8418 - 841F +S418: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +or [ebp+__dreg+8],cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8420 - 8427 +S420: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +or [ebp+__dreg+8],cl +lahf +mov al,0 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8428 - 842F +S428: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +or [ebp+__dreg+8],cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8430 - 8437 +S430: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +or [ebp+__dreg+8],cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8438 +S438: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +or [ebp+__dreg+8],cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8439 +S439: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +or [ebp+__dreg+8],cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 843A +S43A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +or [ebp+__dreg+8],cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 843B +S43B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +or [ebp+__dreg+8],cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 843C +S43C: +mov cx,[esi] +add esi,byte 2 +or [ebp+__dreg+8],cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8440 - 8447 +S440: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +or [ebp+__dreg+8],cx +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8450 - 8457 +S450: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +or [ebp+__dreg+8],cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8458 - 845F +S458: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +or [ebp+__dreg+8],cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8460 - 8467 +S460: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +or [ebp+__dreg+8],cx +lahf +mov al,0 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8468 - 846F +S468: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +or [ebp+__dreg+8],cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8470 - 8477 +S470: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +or [ebp+__dreg+8],cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8478 +S478: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +or [ebp+__dreg+8],cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8479 +S479: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +or [ebp+__dreg+8],cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 847A +S47A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +or [ebp+__dreg+8],cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 847B +S47B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +or [ebp+__dreg+8],cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 847C +S47C: +mov cx,[esi] +add esi,byte 2 +or [ebp+__dreg+8],cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8480 - 8487 +S480: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +or [ebp+__dreg+8],ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8490 - 8497 +S490: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +or [ebp+__dreg+8],ecx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8498 - 849F +S498: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +or [ebp+__dreg+8],ecx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 84A0 - 84A7 +S4A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +or [ebp+__dreg+8],ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 84A8 - 84AF +S4A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +or [ebp+__dreg+8],ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 84B0 - 84B7 +S4B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +or [ebp+__dreg+8],ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 84B8 +S4B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +or [ebp+__dreg+8],ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 84B9 +S4B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +or [ebp+__dreg+8],ecx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 84BA +S4BA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +or [ebp+__dreg+8],ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 84BB +S4BB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +or [ebp+__dreg+8],ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 84BC +S4BC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +or [ebp+__dreg+8],ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 84C0 - 84C7 +S4C0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +jnz short ln1268 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1270 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1271 +ln1270: +call basefunction +ln1271: +add esi,[ebp+__io_fetchbase] +sub edi,byte 38 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1268: +and ecx,0FFFFh +mov eax,[ebp+__dreg+8] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1269 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+8],edx +sub edi,133 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1269: +mov ax,1 +sub edi,133 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 84D0 - 84D7 +S4D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +test cx,cx +jnz short ln1272 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1274 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1275 +ln1274: +call basefunction +ln1275: +add esi,[ebp+__io_fetchbase] +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1272: +and ecx,0FFFFh +mov eax,[ebp+__dreg+8] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1273 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+8],edx +sub edi,137 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1273: +mov ax,1 +sub edi,137 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 84D8 - 84DF +S4D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +test cx,cx +jnz short ln1276 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1278 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1279 +ln1278: +call basefunction +ln1279: +add esi,[ebp+__io_fetchbase] +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1276: +and ecx,0FFFFh +mov eax,[ebp+__dreg+8] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1277 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+8],edx +sub edi,137 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1277: +mov ax,1 +sub edi,137 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 84E0 - 84E7 +S4E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +test cx,cx +jnz short ln1280 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1282 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1283 +ln1282: +call basefunction +ln1283: +add esi,[ebp+__io_fetchbase] +sub edi,byte 44 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1280: +and ecx,0FFFFh +mov eax,[ebp+__dreg+8] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1281 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+8],edx +sub edi,139 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1281: +mov ax,1 +sub edi,139 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 84E8 - 84EF +S4E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +test cx,cx +jnz short ln1284 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1286 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1287 +ln1286: +call basefunction +ln1287: +add esi,[ebp+__io_fetchbase] +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1284: +and ecx,0FFFFh +mov eax,[ebp+__dreg+8] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1285 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+8],edx +sub edi,141 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1285: +mov ax,1 +sub edi,141 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 84F0 - 84F7 +S4F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +test cx,cx +jnz short ln1288 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1290 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1291 +ln1290: +call basefunction +ln1291: +add esi,[ebp+__io_fetchbase] +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1288: +and ecx,0FFFFh +mov eax,[ebp+__dreg+8] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1289 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+8],edx +sub edi,143 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1289: +mov ax,1 +sub edi,143 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 84F8 +S4F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +test cx,cx +jnz short ln1292 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1294 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1295 +ln1294: +call basefunction +ln1295: +add esi,[ebp+__io_fetchbase] +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1292: +and ecx,0FFFFh +mov eax,[ebp+__dreg+8] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1293 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+8],edx +sub edi,141 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1293: +mov ax,1 +sub edi,141 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 84F9 +S4F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +test cx,cx +jnz short ln1296 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1298 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1299 +ln1298: +call basefunction +ln1299: +add esi,[ebp+__io_fetchbase] +sub edi,byte 50 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1296: +and ecx,0FFFFh +mov eax,[ebp+__dreg+8] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1297 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+8],edx +sub edi,145 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1297: +mov ax,1 +sub edi,145 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 84FA +S4FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +test cx,cx +jnz short ln1300 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1302 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1303 +ln1302: +call basefunction +ln1303: +add esi,[ebp+__io_fetchbase] +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1300: +and ecx,0FFFFh +mov eax,[ebp+__dreg+8] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1301 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+8],edx +sub edi,141 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1301: +mov ax,1 +sub edi,141 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 84FB +S4FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +test cx,cx +jnz short ln1304 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1306 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1307 +ln1306: +call basefunction +ln1307: +add esi,[ebp+__io_fetchbase] +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1304: +and ecx,0FFFFh +mov eax,[ebp+__dreg+8] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1305 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+8],edx +sub edi,143 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1305: +mov ax,1 +sub edi,143 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 84FC +S4FC: +mov cx,[esi] +add esi,byte 2 +test cx,cx +jnz short ln1308 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1310 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1311 +ln1310: +call basefunction +ln1311: +add esi,[ebp+__io_fetchbase] +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1308: +and ecx,0FFFFh +mov eax,[ebp+__dreg+8] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1309 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+8],edx +sub edi,137 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1309: +mov ax,1 +sub edi,137 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8500 - 8507 +S500: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+8] +sbb al,[ebp+__dreg+ebx*4] +das +mov [ebp+__dreg+8],al +lahf +mov al,0 +setc [ebp+__xflag] +jnz short ln1312 +or ch,0BFh +and ah,ch +ln1312: +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8508 - 850F +S508: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+8] +dec edx +call readmemorybyte +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +sbb al,bl +das +mov ebx,eax +lahf +mov al,0 +setc [ebp+__xflag] +jnz short ln1313 +or ch,0BFh +and ah,ch +ln1313: +mov ecx,ebx +xor ebx,ebx +call writememorybyte +mov [ebp+__areg+8],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8510 - 8517 +S510: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +or cl,[ebp+__dreg+8] +lahf +mov al,0 +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8518 - 851F +S518: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +or cl,[ebp+__dreg+8] +lahf +mov al,0 +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8520 - 8527 +S520: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +or cl,[ebp+__dreg+8] +lahf +mov al,0 +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8528 - 852F +S528: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +or cl,[ebp+__dreg+8] +lahf +mov al,0 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8530 - 8537 +S530: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +or cl,[ebp+__dreg+8] +lahf +mov al,0 +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8538 +S538: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +or cl,[ebp+__dreg+8] +lahf +mov al,0 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8539 +S539: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +or cl,[ebp+__dreg+8] +lahf +mov al,0 +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8550 - 8557 +S550: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +or cx,[ebp+__dreg+8] +lahf +mov al,0 +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8558 - 855F +S558: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +or cx,[ebp+__dreg+8] +lahf +mov al,0 +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8560 - 8567 +S560: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +or cx,[ebp+__dreg+8] +lahf +mov al,0 +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8568 - 856F +S568: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +or cx,[ebp+__dreg+8] +lahf +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8570 - 8577 +S570: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +or cx,[ebp+__dreg+8] +lahf +mov al,0 +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8578 +S578: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +or cx,[ebp+__dreg+8] +lahf +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8579 +S579: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +or cx,[ebp+__dreg+8] +lahf +mov al,0 +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8590 - 8597 +S590: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +or ecx,[ebp+__dreg+8] +lahf +mov al,0 +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8598 - 859F +S598: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +or ecx,[ebp+__dreg+8] +lahf +mov al,0 +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 85A0 - 85A7 +S5A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +or ecx,[ebp+__dreg+8] +lahf +mov al,0 +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 85A8 - 85AF +S5A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +or ecx,[ebp+__dreg+8] +lahf +mov al,0 +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 85B0 - 85B7 +S5B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +or ecx,[ebp+__dreg+8] +lahf +mov al,0 +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 85B8 +S5B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +or ecx,[ebp+__dreg+8] +lahf +mov al,0 +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 85B9 +S5B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +or ecx,[ebp+__dreg+8] +lahf +mov al,0 +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 85C0 - 85C7 +S5C0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +jnz short ln1314 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1316 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1317 +ln1316: +call basefunction +ln1317: +add esi,[ebp+__io_fetchbase] +sub edi,byte 38 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1314: +movsx ecx,cx +mov eax,[ebp+__dreg+8] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1318 +inc ecx +jne short ln1315 +ln1318: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+8],edx +sub edi,150 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1315: +mov ax,1 +sub edi,150 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 85D0 - 85D7 +S5D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +test cx,cx +jnz short ln1319 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1321 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1322 +ln1321: +call basefunction +ln1322: +add esi,[ebp+__io_fetchbase] +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1319: +movsx ecx,cx +mov eax,[ebp+__dreg+8] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1323 +inc ecx +jne short ln1320 +ln1323: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+8],edx +sub edi,154 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1320: +mov ax,1 +sub edi,154 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 85D8 - 85DF +S5D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +test cx,cx +jnz short ln1324 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1326 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1327 +ln1326: +call basefunction +ln1327: +add esi,[ebp+__io_fetchbase] +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1324: +movsx ecx,cx +mov eax,[ebp+__dreg+8] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1328 +inc ecx +jne short ln1325 +ln1328: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+8],edx +sub edi,154 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1325: +mov ax,1 +sub edi,154 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 85E0 - 85E7 +S5E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +test cx,cx +jnz short ln1329 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1331 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1332 +ln1331: +call basefunction +ln1332: +add esi,[ebp+__io_fetchbase] +sub edi,byte 44 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1329: +movsx ecx,cx +mov eax,[ebp+__dreg+8] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1333 +inc ecx +jne short ln1330 +ln1333: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+8],edx +sub edi,156 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1330: +mov ax,1 +sub edi,156 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 85E8 - 85EF +S5E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +test cx,cx +jnz short ln1334 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1336 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1337 +ln1336: +call basefunction +ln1337: +add esi,[ebp+__io_fetchbase] +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1334: +movsx ecx,cx +mov eax,[ebp+__dreg+8] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1338 +inc ecx +jne short ln1335 +ln1338: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+8],edx +sub edi,158 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1335: +mov ax,1 +sub edi,158 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 85F0 - 85F7 +S5F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +test cx,cx +jnz short ln1339 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1341 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1342 +ln1341: +call basefunction +ln1342: +add esi,[ebp+__io_fetchbase] +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1339: +movsx ecx,cx +mov eax,[ebp+__dreg+8] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1343 +inc ecx +jne short ln1340 +ln1343: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+8],edx +sub edi,160 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1340: +mov ax,1 +sub edi,160 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 85F8 +S5F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +test cx,cx +jnz short ln1344 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1346 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1347 +ln1346: +call basefunction +ln1347: +add esi,[ebp+__io_fetchbase] +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1344: +movsx ecx,cx +mov eax,[ebp+__dreg+8] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1348 +inc ecx +jne short ln1345 +ln1348: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+8],edx +sub edi,158 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1345: +mov ax,1 +sub edi,158 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 85F9 +S5F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +test cx,cx +jnz short ln1349 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1351 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1352 +ln1351: +call basefunction +ln1352: +add esi,[ebp+__io_fetchbase] +sub edi,byte 50 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1349: +movsx ecx,cx +mov eax,[ebp+__dreg+8] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1353 +inc ecx +jne short ln1350 +ln1353: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+8],edx +sub edi,162 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1350: +mov ax,1 +sub edi,162 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 85FA +S5FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +test cx,cx +jnz short ln1354 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1356 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1357 +ln1356: +call basefunction +ln1357: +add esi,[ebp+__io_fetchbase] +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1354: +movsx ecx,cx +mov eax,[ebp+__dreg+8] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1358 +inc ecx +jne short ln1355 +ln1358: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+8],edx +sub edi,158 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1355: +mov ax,1 +sub edi,158 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 85FB +S5FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +test cx,cx +jnz short ln1359 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1361 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1362 +ln1361: +call basefunction +ln1362: +add esi,[ebp+__io_fetchbase] +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1359: +movsx ecx,cx +mov eax,[ebp+__dreg+8] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1363 +inc ecx +jne short ln1360 +ln1363: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+8],edx +sub edi,160 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1360: +mov ax,1 +sub edi,160 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 85FC +S5FC: +mov cx,[esi] +add esi,byte 2 +test cx,cx +jnz short ln1364 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1366 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1367 +ln1366: +call basefunction +ln1367: +add esi,[ebp+__io_fetchbase] +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1364: +movsx ecx,cx +mov eax,[ebp+__dreg+8] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1368 +inc ecx +jne short ln1365 +ln1368: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+8],edx +sub edi,154 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1365: +mov ax,1 +sub edi,154 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8600 - 8607 +S600: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +or [ebp+__dreg+12],cl +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8610 - 8617 +S610: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +or [ebp+__dreg+12],cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8618 - 861F +S618: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +or [ebp+__dreg+12],cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8620 - 8627 +S620: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +or [ebp+__dreg+12],cl +lahf +mov al,0 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8628 - 862F +S628: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +or [ebp+__dreg+12],cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8630 - 8637 +S630: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +or [ebp+__dreg+12],cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8638 +S638: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +or [ebp+__dreg+12],cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8639 +S639: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +or [ebp+__dreg+12],cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 863A +S63A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +or [ebp+__dreg+12],cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 863B +S63B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +or [ebp+__dreg+12],cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 863C +S63C: +mov cx,[esi] +add esi,byte 2 +or [ebp+__dreg+12],cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8640 - 8647 +S640: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +or [ebp+__dreg+12],cx +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8650 - 8657 +S650: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +or [ebp+__dreg+12],cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8658 - 865F +S658: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +or [ebp+__dreg+12],cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8660 - 8667 +S660: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +or [ebp+__dreg+12],cx +lahf +mov al,0 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8668 - 866F +S668: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +or [ebp+__dreg+12],cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8670 - 8677 +S670: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +or [ebp+__dreg+12],cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8678 +S678: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +or [ebp+__dreg+12],cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8679 +S679: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +or [ebp+__dreg+12],cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 867A +S67A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +or [ebp+__dreg+12],cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 867B +S67B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +or [ebp+__dreg+12],cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 867C +S67C: +mov cx,[esi] +add esi,byte 2 +or [ebp+__dreg+12],cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8680 - 8687 +S680: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +or [ebp+__dreg+12],ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8690 - 8697 +S690: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +or [ebp+__dreg+12],ecx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8698 - 869F +S698: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +or [ebp+__dreg+12],ecx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 86A0 - 86A7 +S6A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +or [ebp+__dreg+12],ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 86A8 - 86AF +S6A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +or [ebp+__dreg+12],ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 86B0 - 86B7 +S6B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +or [ebp+__dreg+12],ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 86B8 +S6B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +or [ebp+__dreg+12],ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 86B9 +S6B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +or [ebp+__dreg+12],ecx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 86BA +S6BA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +or [ebp+__dreg+12],ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 86BB +S6BB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +or [ebp+__dreg+12],ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 86BC +S6BC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +or [ebp+__dreg+12],ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 86C0 - 86C7 +S6C0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +jnz short ln1369 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1371 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1372 +ln1371: +call basefunction +ln1372: +add esi,[ebp+__io_fetchbase] +sub edi,byte 38 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1369: +and ecx,0FFFFh +mov eax,[ebp+__dreg+12] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1370 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+12],edx +sub edi,133 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1370: +mov ax,1 +sub edi,133 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 86D0 - 86D7 +S6D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +test cx,cx +jnz short ln1373 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1375 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1376 +ln1375: +call basefunction +ln1376: +add esi,[ebp+__io_fetchbase] +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1373: +and ecx,0FFFFh +mov eax,[ebp+__dreg+12] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1374 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+12],edx +sub edi,137 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1374: +mov ax,1 +sub edi,137 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 86D8 - 86DF +S6D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +test cx,cx +jnz short ln1377 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1379 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1380 +ln1379: +call basefunction +ln1380: +add esi,[ebp+__io_fetchbase] +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1377: +and ecx,0FFFFh +mov eax,[ebp+__dreg+12] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1378 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+12],edx +sub edi,137 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1378: +mov ax,1 +sub edi,137 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 86E0 - 86E7 +S6E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +test cx,cx +jnz short ln1381 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1383 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1384 +ln1383: +call basefunction +ln1384: +add esi,[ebp+__io_fetchbase] +sub edi,byte 44 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1381: +and ecx,0FFFFh +mov eax,[ebp+__dreg+12] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1382 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+12],edx +sub edi,139 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1382: +mov ax,1 +sub edi,139 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 86E8 - 86EF +S6E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +test cx,cx +jnz short ln1385 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1387 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1388 +ln1387: +call basefunction +ln1388: +add esi,[ebp+__io_fetchbase] +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1385: +and ecx,0FFFFh +mov eax,[ebp+__dreg+12] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1386 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+12],edx +sub edi,141 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1386: +mov ax,1 +sub edi,141 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 86F0 - 86F7 +S6F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +test cx,cx +jnz short ln1389 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1391 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1392 +ln1391: +call basefunction +ln1392: +add esi,[ebp+__io_fetchbase] +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1389: +and ecx,0FFFFh +mov eax,[ebp+__dreg+12] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1390 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+12],edx +sub edi,143 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1390: +mov ax,1 +sub edi,143 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 86F8 +S6F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +test cx,cx +jnz short ln1393 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1395 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1396 +ln1395: +call basefunction +ln1396: +add esi,[ebp+__io_fetchbase] +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1393: +and ecx,0FFFFh +mov eax,[ebp+__dreg+12] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1394 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+12],edx +sub edi,141 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1394: +mov ax,1 +sub edi,141 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 86F9 +S6F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +test cx,cx +jnz short ln1397 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1399 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1400 +ln1399: +call basefunction +ln1400: +add esi,[ebp+__io_fetchbase] +sub edi,byte 50 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1397: +and ecx,0FFFFh +mov eax,[ebp+__dreg+12] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1398 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+12],edx +sub edi,145 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1398: +mov ax,1 +sub edi,145 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 86FA +S6FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +test cx,cx +jnz short ln1401 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1403 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1404 +ln1403: +call basefunction +ln1404: +add esi,[ebp+__io_fetchbase] +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1401: +and ecx,0FFFFh +mov eax,[ebp+__dreg+12] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1402 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+12],edx +sub edi,141 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1402: +mov ax,1 +sub edi,141 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 86FB +S6FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +test cx,cx +jnz short ln1405 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1407 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1408 +ln1407: +call basefunction +ln1408: +add esi,[ebp+__io_fetchbase] +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1405: +and ecx,0FFFFh +mov eax,[ebp+__dreg+12] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1406 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+12],edx +sub edi,143 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1406: +mov ax,1 +sub edi,143 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 86FC +S6FC: +mov cx,[esi] +add esi,byte 2 +test cx,cx +jnz short ln1409 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1411 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1412 +ln1411: +call basefunction +ln1412: +add esi,[ebp+__io_fetchbase] +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1409: +and ecx,0FFFFh +mov eax,[ebp+__dreg+12] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1410 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+12],edx +sub edi,137 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1410: +mov ax,1 +sub edi,137 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8700 - 8707 +S700: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+12] +sbb al,[ebp+__dreg+ebx*4] +das +mov [ebp+__dreg+12],al +lahf +mov al,0 +setc [ebp+__xflag] +jnz short ln1413 +or ch,0BFh +and ah,ch +ln1413: +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8708 - 870F +S708: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+12] +dec edx +call readmemorybyte +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +sbb al,bl +das +mov ebx,eax +lahf +mov al,0 +setc [ebp+__xflag] +jnz short ln1414 +or ch,0BFh +and ah,ch +ln1414: +mov ecx,ebx +xor ebx,ebx +call writememorybyte +mov [ebp+__areg+12],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8710 - 8717 +S710: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +or cl,[ebp+__dreg+12] +lahf +mov al,0 +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8718 - 871F +S718: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +or cl,[ebp+__dreg+12] +lahf +mov al,0 +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8720 - 8727 +S720: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +or cl,[ebp+__dreg+12] +lahf +mov al,0 +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8728 - 872F +S728: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +or cl,[ebp+__dreg+12] +lahf +mov al,0 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8730 - 8737 +S730: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +or cl,[ebp+__dreg+12] +lahf +mov al,0 +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8738 +S738: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +or cl,[ebp+__dreg+12] +lahf +mov al,0 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8739 +S739: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +or cl,[ebp+__dreg+12] +lahf +mov al,0 +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8750 - 8757 +S750: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +or cx,[ebp+__dreg+12] +lahf +mov al,0 +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8758 - 875F +S758: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +or cx,[ebp+__dreg+12] +lahf +mov al,0 +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8760 - 8767 +S760: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +or cx,[ebp+__dreg+12] +lahf +mov al,0 +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8768 - 876F +S768: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +or cx,[ebp+__dreg+12] +lahf +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8770 - 8777 +S770: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +or cx,[ebp+__dreg+12] +lahf +mov al,0 +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8778 +S778: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +or cx,[ebp+__dreg+12] +lahf +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8779 +S779: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +or cx,[ebp+__dreg+12] +lahf +mov al,0 +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8790 - 8797 +S790: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +or ecx,[ebp+__dreg+12] +lahf +mov al,0 +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8798 - 879F +S798: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +or ecx,[ebp+__dreg+12] +lahf +mov al,0 +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 87A0 - 87A7 +S7A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +or ecx,[ebp+__dreg+12] +lahf +mov al,0 +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 87A8 - 87AF +S7A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +or ecx,[ebp+__dreg+12] +lahf +mov al,0 +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 87B0 - 87B7 +S7B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +or ecx,[ebp+__dreg+12] +lahf +mov al,0 +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 87B8 +S7B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +or ecx,[ebp+__dreg+12] +lahf +mov al,0 +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 87B9 +S7B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +or ecx,[ebp+__dreg+12] +lahf +mov al,0 +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 87C0 - 87C7 +S7C0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +jnz short ln1415 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1417 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1418 +ln1417: +call basefunction +ln1418: +add esi,[ebp+__io_fetchbase] +sub edi,byte 38 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1415: +movsx ecx,cx +mov eax,[ebp+__dreg+12] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1419 +inc ecx +jne short ln1416 +ln1419: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+12],edx +sub edi,150 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1416: +mov ax,1 +sub edi,150 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 87D0 - 87D7 +S7D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +test cx,cx +jnz short ln1420 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1422 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1423 +ln1422: +call basefunction +ln1423: +add esi,[ebp+__io_fetchbase] +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1420: +movsx ecx,cx +mov eax,[ebp+__dreg+12] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1424 +inc ecx +jne short ln1421 +ln1424: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+12],edx +sub edi,154 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1421: +mov ax,1 +sub edi,154 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 87D8 - 87DF +S7D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +test cx,cx +jnz short ln1425 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1427 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1428 +ln1427: +call basefunction +ln1428: +add esi,[ebp+__io_fetchbase] +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1425: +movsx ecx,cx +mov eax,[ebp+__dreg+12] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1429 +inc ecx +jne short ln1426 +ln1429: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+12],edx +sub edi,154 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1426: +mov ax,1 +sub edi,154 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 87E0 - 87E7 +S7E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +test cx,cx +jnz short ln1430 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1432 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1433 +ln1432: +call basefunction +ln1433: +add esi,[ebp+__io_fetchbase] +sub edi,byte 44 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1430: +movsx ecx,cx +mov eax,[ebp+__dreg+12] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1434 +inc ecx +jne short ln1431 +ln1434: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+12],edx +sub edi,156 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1431: +mov ax,1 +sub edi,156 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 87E8 - 87EF +S7E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +test cx,cx +jnz short ln1435 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1437 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1438 +ln1437: +call basefunction +ln1438: +add esi,[ebp+__io_fetchbase] +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1435: +movsx ecx,cx +mov eax,[ebp+__dreg+12] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1439 +inc ecx +jne short ln1436 +ln1439: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+12],edx +sub edi,158 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1436: +mov ax,1 +sub edi,158 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 87F0 - 87F7 +S7F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +test cx,cx +jnz short ln1440 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1442 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1443 +ln1442: +call basefunction +ln1443: +add esi,[ebp+__io_fetchbase] +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1440: +movsx ecx,cx +mov eax,[ebp+__dreg+12] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1444 +inc ecx +jne short ln1441 +ln1444: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+12],edx +sub edi,160 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1441: +mov ax,1 +sub edi,160 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 87F8 +S7F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +test cx,cx +jnz short ln1445 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1447 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1448 +ln1447: +call basefunction +ln1448: +add esi,[ebp+__io_fetchbase] +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1445: +movsx ecx,cx +mov eax,[ebp+__dreg+12] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1449 +inc ecx +jne short ln1446 +ln1449: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+12],edx +sub edi,158 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1446: +mov ax,1 +sub edi,158 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 87F9 +S7F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +test cx,cx +jnz short ln1450 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1452 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1453 +ln1452: +call basefunction +ln1453: +add esi,[ebp+__io_fetchbase] +sub edi,byte 50 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1450: +movsx ecx,cx +mov eax,[ebp+__dreg+12] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1454 +inc ecx +jne short ln1451 +ln1454: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+12],edx +sub edi,162 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1451: +mov ax,1 +sub edi,162 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 87FA +S7FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +test cx,cx +jnz short ln1455 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1457 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1458 +ln1457: +call basefunction +ln1458: +add esi,[ebp+__io_fetchbase] +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1455: +movsx ecx,cx +mov eax,[ebp+__dreg+12] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1459 +inc ecx +jne short ln1456 +ln1459: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+12],edx +sub edi,158 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1456: +mov ax,1 +sub edi,158 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 87FB +S7FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +test cx,cx +jnz short ln1460 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1462 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1463 +ln1462: +call basefunction +ln1463: +add esi,[ebp+__io_fetchbase] +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1460: +movsx ecx,cx +mov eax,[ebp+__dreg+12] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1464 +inc ecx +jne short ln1461 +ln1464: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+12],edx +sub edi,160 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1461: +mov ax,1 +sub edi,160 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 87FC +S7FC: +mov cx,[esi] +add esi,byte 2 +test cx,cx +jnz short ln1465 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1467 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1468 +ln1467: +call basefunction +ln1468: +add esi,[ebp+__io_fetchbase] +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1465: +movsx ecx,cx +mov eax,[ebp+__dreg+12] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1469 +inc ecx +jne short ln1466 +ln1469: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+12],edx +sub edi,154 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1466: +mov ax,1 +sub edi,154 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8800 - 8807 +S800: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +or [ebp+__dreg+16],cl +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8810 - 8817 +S810: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +or [ebp+__dreg+16],cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8818 - 881F +S818: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +or [ebp+__dreg+16],cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8820 - 8827 +S820: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +or [ebp+__dreg+16],cl +lahf +mov al,0 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8828 - 882F +S828: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +or [ebp+__dreg+16],cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8830 - 8837 +S830: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +or [ebp+__dreg+16],cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8838 +S838: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +or [ebp+__dreg+16],cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8839 +S839: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +or [ebp+__dreg+16],cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 883A +S83A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +or [ebp+__dreg+16],cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 883B +S83B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +or [ebp+__dreg+16],cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 883C +S83C: +mov cx,[esi] +add esi,byte 2 +or [ebp+__dreg+16],cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8840 - 8847 +S840: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +or [ebp+__dreg+16],cx +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8850 - 8857 +S850: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +or [ebp+__dreg+16],cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8858 - 885F +S858: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +or [ebp+__dreg+16],cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8860 - 8867 +S860: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +or [ebp+__dreg+16],cx +lahf +mov al,0 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8868 - 886F +S868: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +or [ebp+__dreg+16],cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8870 - 8877 +S870: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +or [ebp+__dreg+16],cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8878 +S878: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +or [ebp+__dreg+16],cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8879 +S879: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +or [ebp+__dreg+16],cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 887A +S87A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +or [ebp+__dreg+16],cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 887B +S87B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +or [ebp+__dreg+16],cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 887C +S87C: +mov cx,[esi] +add esi,byte 2 +or [ebp+__dreg+16],cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8880 - 8887 +S880: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +or [ebp+__dreg+16],ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8890 - 8897 +S890: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +or [ebp+__dreg+16],ecx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8898 - 889F +S898: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +or [ebp+__dreg+16],ecx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 88A0 - 88A7 +S8A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +or [ebp+__dreg+16],ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 88A8 - 88AF +S8A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +or [ebp+__dreg+16],ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 88B0 - 88B7 +S8B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +or [ebp+__dreg+16],ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 88B8 +S8B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +or [ebp+__dreg+16],ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 88B9 +S8B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +or [ebp+__dreg+16],ecx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 88BA +S8BA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +or [ebp+__dreg+16],ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 88BB +S8BB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +or [ebp+__dreg+16],ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 88BC +S8BC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +or [ebp+__dreg+16],ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 88C0 - 88C7 +S8C0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +jnz short ln1470 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1472 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1473 +ln1472: +call basefunction +ln1473: +add esi,[ebp+__io_fetchbase] +sub edi,byte 38 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1470: +and ecx,0FFFFh +mov eax,[ebp+__dreg+16] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1471 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+16],edx +sub edi,133 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1471: +mov ax,1 +sub edi,133 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 88D0 - 88D7 +S8D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +test cx,cx +jnz short ln1474 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1476 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1477 +ln1476: +call basefunction +ln1477: +add esi,[ebp+__io_fetchbase] +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1474: +and ecx,0FFFFh +mov eax,[ebp+__dreg+16] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1475 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+16],edx +sub edi,137 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1475: +mov ax,1 +sub edi,137 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 88D8 - 88DF +S8D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +test cx,cx +jnz short ln1478 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1480 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1481 +ln1480: +call basefunction +ln1481: +add esi,[ebp+__io_fetchbase] +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1478: +and ecx,0FFFFh +mov eax,[ebp+__dreg+16] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1479 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+16],edx +sub edi,137 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1479: +mov ax,1 +sub edi,137 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 88E0 - 88E7 +S8E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +test cx,cx +jnz short ln1482 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1484 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1485 +ln1484: +call basefunction +ln1485: +add esi,[ebp+__io_fetchbase] +sub edi,byte 44 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1482: +and ecx,0FFFFh +mov eax,[ebp+__dreg+16] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1483 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+16],edx +sub edi,139 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1483: +mov ax,1 +sub edi,139 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 88E8 - 88EF +S8E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +test cx,cx +jnz short ln1486 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1488 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1489 +ln1488: +call basefunction +ln1489: +add esi,[ebp+__io_fetchbase] +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1486: +and ecx,0FFFFh +mov eax,[ebp+__dreg+16] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1487 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+16],edx +sub edi,141 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1487: +mov ax,1 +sub edi,141 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 88F0 - 88F7 +S8F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +test cx,cx +jnz short ln1490 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1492 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1493 +ln1492: +call basefunction +ln1493: +add esi,[ebp+__io_fetchbase] +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1490: +and ecx,0FFFFh +mov eax,[ebp+__dreg+16] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1491 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+16],edx +sub edi,143 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1491: +mov ax,1 +sub edi,143 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 88F8 +S8F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +test cx,cx +jnz short ln1494 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1496 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1497 +ln1496: +call basefunction +ln1497: +add esi,[ebp+__io_fetchbase] +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1494: +and ecx,0FFFFh +mov eax,[ebp+__dreg+16] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1495 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+16],edx +sub edi,141 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1495: +mov ax,1 +sub edi,141 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 88F9 +S8F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +test cx,cx +jnz short ln1498 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1500 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1501 +ln1500: +call basefunction +ln1501: +add esi,[ebp+__io_fetchbase] +sub edi,byte 50 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1498: +and ecx,0FFFFh +mov eax,[ebp+__dreg+16] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1499 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+16],edx +sub edi,145 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1499: +mov ax,1 +sub edi,145 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 88FA +S8FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +test cx,cx +jnz short ln1502 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1504 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1505 +ln1504: +call basefunction +ln1505: +add esi,[ebp+__io_fetchbase] +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1502: +and ecx,0FFFFh +mov eax,[ebp+__dreg+16] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1503 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+16],edx +sub edi,141 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1503: +mov ax,1 +sub edi,141 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 88FB +S8FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +test cx,cx +jnz short ln1506 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1508 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1509 +ln1508: +call basefunction +ln1509: +add esi,[ebp+__io_fetchbase] +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1506: +and ecx,0FFFFh +mov eax,[ebp+__dreg+16] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1507 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+16],edx +sub edi,143 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1507: +mov ax,1 +sub edi,143 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 88FC +S8FC: +mov cx,[esi] +add esi,byte 2 +test cx,cx +jnz short ln1510 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1512 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1513 +ln1512: +call basefunction +ln1513: +add esi,[ebp+__io_fetchbase] +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1510: +and ecx,0FFFFh +mov eax,[ebp+__dreg+16] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1511 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+16],edx +sub edi,137 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1511: +mov ax,1 +sub edi,137 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8900 - 8907 +S900: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+16] +sbb al,[ebp+__dreg+ebx*4] +das +mov [ebp+__dreg+16],al +lahf +mov al,0 +setc [ebp+__xflag] +jnz short ln1514 +or ch,0BFh +and ah,ch +ln1514: +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8908 - 890F +S908: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+16] +dec edx +call readmemorybyte +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +sbb al,bl +das +mov ebx,eax +lahf +mov al,0 +setc [ebp+__xflag] +jnz short ln1515 +or ch,0BFh +and ah,ch +ln1515: +mov ecx,ebx +xor ebx,ebx +call writememorybyte +mov [ebp+__areg+16],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8910 - 8917 +S910: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +or cl,[ebp+__dreg+16] +lahf +mov al,0 +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8918 - 891F +S918: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +or cl,[ebp+__dreg+16] +lahf +mov al,0 +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8920 - 8927 +S920: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +or cl,[ebp+__dreg+16] +lahf +mov al,0 +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8928 - 892F +S928: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +or cl,[ebp+__dreg+16] +lahf +mov al,0 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8930 - 8937 +S930: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +or cl,[ebp+__dreg+16] +lahf +mov al,0 +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8938 +S938: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +or cl,[ebp+__dreg+16] +lahf +mov al,0 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8939 +S939: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +or cl,[ebp+__dreg+16] +lahf +mov al,0 +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8950 - 8957 +S950: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +or cx,[ebp+__dreg+16] +lahf +mov al,0 +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8958 - 895F +S958: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +or cx,[ebp+__dreg+16] +lahf +mov al,0 +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8960 - 8967 +S960: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +or cx,[ebp+__dreg+16] +lahf +mov al,0 +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8968 - 896F +S968: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +or cx,[ebp+__dreg+16] +lahf +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8970 - 8977 +S970: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +or cx,[ebp+__dreg+16] +lahf +mov al,0 +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8978 +S978: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +or cx,[ebp+__dreg+16] +lahf +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8979 +S979: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +or cx,[ebp+__dreg+16] +lahf +mov al,0 +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8990 - 8997 +S990: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +or ecx,[ebp+__dreg+16] +lahf +mov al,0 +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8998 - 899F +S998: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +or ecx,[ebp+__dreg+16] +lahf +mov al,0 +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 89A0 - 89A7 +S9A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +or ecx,[ebp+__dreg+16] +lahf +mov al,0 +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 89A8 - 89AF +S9A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +or ecx,[ebp+__dreg+16] +lahf +mov al,0 +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 89B0 - 89B7 +S9B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +or ecx,[ebp+__dreg+16] +lahf +mov al,0 +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 89B8 +S9B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +or ecx,[ebp+__dreg+16] +lahf +mov al,0 +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 89B9 +S9B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +or ecx,[ebp+__dreg+16] +lahf +mov al,0 +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 89C0 - 89C7 +S9C0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +jnz short ln1516 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1518 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1519 +ln1518: +call basefunction +ln1519: +add esi,[ebp+__io_fetchbase] +sub edi,byte 38 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1516: +movsx ecx,cx +mov eax,[ebp+__dreg+16] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1520 +inc ecx +jne short ln1517 +ln1520: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+16],edx +sub edi,150 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1517: +mov ax,1 +sub edi,150 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 89D0 - 89D7 +S9D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +test cx,cx +jnz short ln1521 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1523 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1524 +ln1523: +call basefunction +ln1524: +add esi,[ebp+__io_fetchbase] +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1521: +movsx ecx,cx +mov eax,[ebp+__dreg+16] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1525 +inc ecx +jne short ln1522 +ln1525: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+16],edx +sub edi,154 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1522: +mov ax,1 +sub edi,154 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 89D8 - 89DF +S9D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +test cx,cx +jnz short ln1526 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1528 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1529 +ln1528: +call basefunction +ln1529: +add esi,[ebp+__io_fetchbase] +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1526: +movsx ecx,cx +mov eax,[ebp+__dreg+16] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1530 +inc ecx +jne short ln1527 +ln1530: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+16],edx +sub edi,154 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1527: +mov ax,1 +sub edi,154 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 89E0 - 89E7 +S9E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +test cx,cx +jnz short ln1531 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1533 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1534 +ln1533: +call basefunction +ln1534: +add esi,[ebp+__io_fetchbase] +sub edi,byte 44 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1531: +movsx ecx,cx +mov eax,[ebp+__dreg+16] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1535 +inc ecx +jne short ln1532 +ln1535: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+16],edx +sub edi,156 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1532: +mov ax,1 +sub edi,156 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 89E8 - 89EF +S9E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +test cx,cx +jnz short ln1536 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1538 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1539 +ln1538: +call basefunction +ln1539: +add esi,[ebp+__io_fetchbase] +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1536: +movsx ecx,cx +mov eax,[ebp+__dreg+16] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1540 +inc ecx +jne short ln1537 +ln1540: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+16],edx +sub edi,158 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1537: +mov ax,1 +sub edi,158 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 89F0 - 89F7 +S9F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +test cx,cx +jnz short ln1541 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1543 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1544 +ln1543: +call basefunction +ln1544: +add esi,[ebp+__io_fetchbase] +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1541: +movsx ecx,cx +mov eax,[ebp+__dreg+16] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1545 +inc ecx +jne short ln1542 +ln1545: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+16],edx +sub edi,160 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1542: +mov ax,1 +sub edi,160 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 89F8 +S9F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +test cx,cx +jnz short ln1546 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1548 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1549 +ln1548: +call basefunction +ln1549: +add esi,[ebp+__io_fetchbase] +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1546: +movsx ecx,cx +mov eax,[ebp+__dreg+16] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1550 +inc ecx +jne short ln1547 +ln1550: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+16],edx +sub edi,158 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1547: +mov ax,1 +sub edi,158 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 89F9 +S9F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +test cx,cx +jnz short ln1551 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1553 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1554 +ln1553: +call basefunction +ln1554: +add esi,[ebp+__io_fetchbase] +sub edi,byte 50 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1551: +movsx ecx,cx +mov eax,[ebp+__dreg+16] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1555 +inc ecx +jne short ln1552 +ln1555: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+16],edx +sub edi,162 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1552: +mov ax,1 +sub edi,162 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 89FA +S9FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +test cx,cx +jnz short ln1556 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1558 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1559 +ln1558: +call basefunction +ln1559: +add esi,[ebp+__io_fetchbase] +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1556: +movsx ecx,cx +mov eax,[ebp+__dreg+16] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1560 +inc ecx +jne short ln1557 +ln1560: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+16],edx +sub edi,158 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1557: +mov ax,1 +sub edi,158 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 89FB +S9FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +test cx,cx +jnz short ln1561 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1563 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1564 +ln1563: +call basefunction +ln1564: +add esi,[ebp+__io_fetchbase] +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1561: +movsx ecx,cx +mov eax,[ebp+__dreg+16] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1565 +inc ecx +jne short ln1562 +ln1565: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+16],edx +sub edi,160 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1562: +mov ax,1 +sub edi,160 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 89FC +S9FC: +mov cx,[esi] +add esi,byte 2 +test cx,cx +jnz short ln1566 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1568 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1569 +ln1568: +call basefunction +ln1569: +add esi,[ebp+__io_fetchbase] +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1566: +movsx ecx,cx +mov eax,[ebp+__dreg+16] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1570 +inc ecx +jne short ln1567 +ln1570: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+16],edx +sub edi,154 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1567: +mov ax,1 +sub edi,154 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8A00 - 8A07 +SA00: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +or [ebp+__dreg+20],cl +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8A10 - 8A17 +SA10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +or [ebp+__dreg+20],cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8A18 - 8A1F +SA18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +or [ebp+__dreg+20],cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8A20 - 8A27 +SA20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +or [ebp+__dreg+20],cl +lahf +mov al,0 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8A28 - 8A2F +SA28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +or [ebp+__dreg+20],cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8A30 - 8A37 +SA30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +or [ebp+__dreg+20],cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8A38 +SA38: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +or [ebp+__dreg+20],cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8A39 +SA39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +or [ebp+__dreg+20],cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8A3A +SA3A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +or [ebp+__dreg+20],cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8A3B +SA3B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +or [ebp+__dreg+20],cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8A3C +SA3C: +mov cx,[esi] +add esi,byte 2 +or [ebp+__dreg+20],cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8A40 - 8A47 +SA40: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +or [ebp+__dreg+20],cx +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8A50 - 8A57 +SA50: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +or [ebp+__dreg+20],cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8A58 - 8A5F +SA58: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +or [ebp+__dreg+20],cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8A60 - 8A67 +SA60: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +or [ebp+__dreg+20],cx +lahf +mov al,0 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8A68 - 8A6F +SA68: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +or [ebp+__dreg+20],cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8A70 - 8A77 +SA70: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +or [ebp+__dreg+20],cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8A78 +SA78: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +or [ebp+__dreg+20],cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8A79 +SA79: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +or [ebp+__dreg+20],cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8A7A +SA7A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +or [ebp+__dreg+20],cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8A7B +SA7B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +or [ebp+__dreg+20],cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8A7C +SA7C: +mov cx,[esi] +add esi,byte 2 +or [ebp+__dreg+20],cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8A80 - 8A87 +SA80: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +or [ebp+__dreg+20],ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8A90 - 8A97 +SA90: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +or [ebp+__dreg+20],ecx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8A98 - 8A9F +SA98: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +or [ebp+__dreg+20],ecx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8AA0 - 8AA7 +SAA0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +or [ebp+__dreg+20],ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8AA8 - 8AAF +SAA8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +or [ebp+__dreg+20],ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8AB0 - 8AB7 +SAB0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +or [ebp+__dreg+20],ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8AB8 +SAB8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +or [ebp+__dreg+20],ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8AB9 +SAB9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +or [ebp+__dreg+20],ecx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8ABA +SABA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +or [ebp+__dreg+20],ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8ABB +SABB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +or [ebp+__dreg+20],ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8ABC +SABC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +or [ebp+__dreg+20],ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8AC0 - 8AC7 +SAC0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +jnz short ln1571 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1573 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1574 +ln1573: +call basefunction +ln1574: +add esi,[ebp+__io_fetchbase] +sub edi,byte 38 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1571: +and ecx,0FFFFh +mov eax,[ebp+__dreg+20] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1572 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+20],edx +sub edi,133 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1572: +mov ax,1 +sub edi,133 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8AD0 - 8AD7 +SAD0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +test cx,cx +jnz short ln1575 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1577 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1578 +ln1577: +call basefunction +ln1578: +add esi,[ebp+__io_fetchbase] +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1575: +and ecx,0FFFFh +mov eax,[ebp+__dreg+20] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1576 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+20],edx +sub edi,137 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1576: +mov ax,1 +sub edi,137 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8AD8 - 8ADF +SAD8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +test cx,cx +jnz short ln1579 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1581 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1582 +ln1581: +call basefunction +ln1582: +add esi,[ebp+__io_fetchbase] +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1579: +and ecx,0FFFFh +mov eax,[ebp+__dreg+20] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1580 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+20],edx +sub edi,137 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1580: +mov ax,1 +sub edi,137 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8AE0 - 8AE7 +SAE0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +test cx,cx +jnz short ln1583 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1585 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1586 +ln1585: +call basefunction +ln1586: +add esi,[ebp+__io_fetchbase] +sub edi,byte 44 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1583: +and ecx,0FFFFh +mov eax,[ebp+__dreg+20] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1584 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+20],edx +sub edi,139 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1584: +mov ax,1 +sub edi,139 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8AE8 - 8AEF +SAE8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +test cx,cx +jnz short ln1587 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1589 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1590 +ln1589: +call basefunction +ln1590: +add esi,[ebp+__io_fetchbase] +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1587: +and ecx,0FFFFh +mov eax,[ebp+__dreg+20] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1588 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+20],edx +sub edi,141 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1588: +mov ax,1 +sub edi,141 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8AF0 - 8AF7 +SAF0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +test cx,cx +jnz short ln1591 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1593 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1594 +ln1593: +call basefunction +ln1594: +add esi,[ebp+__io_fetchbase] +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1591: +and ecx,0FFFFh +mov eax,[ebp+__dreg+20] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1592 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+20],edx +sub edi,143 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1592: +mov ax,1 +sub edi,143 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8AF8 +SAF8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +test cx,cx +jnz short ln1595 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1597 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1598 +ln1597: +call basefunction +ln1598: +add esi,[ebp+__io_fetchbase] +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1595: +and ecx,0FFFFh +mov eax,[ebp+__dreg+20] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1596 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+20],edx +sub edi,141 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1596: +mov ax,1 +sub edi,141 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8AF9 +SAF9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +test cx,cx +jnz short ln1599 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1601 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1602 +ln1601: +call basefunction +ln1602: +add esi,[ebp+__io_fetchbase] +sub edi,byte 50 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1599: +and ecx,0FFFFh +mov eax,[ebp+__dreg+20] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1600 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+20],edx +sub edi,145 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1600: +mov ax,1 +sub edi,145 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8AFA +SAFA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +test cx,cx +jnz short ln1603 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1605 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1606 +ln1605: +call basefunction +ln1606: +add esi,[ebp+__io_fetchbase] +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1603: +and ecx,0FFFFh +mov eax,[ebp+__dreg+20] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1604 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+20],edx +sub edi,141 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1604: +mov ax,1 +sub edi,141 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8AFB +SAFB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +test cx,cx +jnz short ln1607 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1609 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1610 +ln1609: +call basefunction +ln1610: +add esi,[ebp+__io_fetchbase] +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1607: +and ecx,0FFFFh +mov eax,[ebp+__dreg+20] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1608 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+20],edx +sub edi,143 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1608: +mov ax,1 +sub edi,143 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8AFC +SAFC: +mov cx,[esi] +add esi,byte 2 +test cx,cx +jnz short ln1611 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1613 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1614 +ln1613: +call basefunction +ln1614: +add esi,[ebp+__io_fetchbase] +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1611: +and ecx,0FFFFh +mov eax,[ebp+__dreg+20] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1612 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+20],edx +sub edi,137 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1612: +mov ax,1 +sub edi,137 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8B00 - 8B07 +SB00: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+20] +sbb al,[ebp+__dreg+ebx*4] +das +mov [ebp+__dreg+20],al +lahf +mov al,0 +setc [ebp+__xflag] +jnz short ln1615 +or ch,0BFh +and ah,ch +ln1615: +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8B08 - 8B0F +SB08: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+20] +dec edx +call readmemorybyte +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +sbb al,bl +das +mov ebx,eax +lahf +mov al,0 +setc [ebp+__xflag] +jnz short ln1616 +or ch,0BFh +and ah,ch +ln1616: +mov ecx,ebx +xor ebx,ebx +call writememorybyte +mov [ebp+__areg+20],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8B10 - 8B17 +SB10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +or cl,[ebp+__dreg+20] +lahf +mov al,0 +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8B18 - 8B1F +SB18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +or cl,[ebp+__dreg+20] +lahf +mov al,0 +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8B20 - 8B27 +SB20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +or cl,[ebp+__dreg+20] +lahf +mov al,0 +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8B28 - 8B2F +SB28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +or cl,[ebp+__dreg+20] +lahf +mov al,0 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8B30 - 8B37 +SB30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +or cl,[ebp+__dreg+20] +lahf +mov al,0 +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8B38 +SB38: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +or cl,[ebp+__dreg+20] +lahf +mov al,0 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8B39 +SB39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +or cl,[ebp+__dreg+20] +lahf +mov al,0 +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8B50 - 8B57 +SB50: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +or cx,[ebp+__dreg+20] +lahf +mov al,0 +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8B58 - 8B5F +SB58: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +or cx,[ebp+__dreg+20] +lahf +mov al,0 +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8B60 - 8B67 +SB60: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +or cx,[ebp+__dreg+20] +lahf +mov al,0 +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8B68 - 8B6F +SB68: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +or cx,[ebp+__dreg+20] +lahf +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8B70 - 8B77 +SB70: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +or cx,[ebp+__dreg+20] +lahf +mov al,0 +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8B78 +SB78: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +or cx,[ebp+__dreg+20] +lahf +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8B79 +SB79: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +or cx,[ebp+__dreg+20] +lahf +mov al,0 +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8B90 - 8B97 +SB90: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +or ecx,[ebp+__dreg+20] +lahf +mov al,0 +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8B98 - 8B9F +SB98: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +or ecx,[ebp+__dreg+20] +lahf +mov al,0 +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8BA0 - 8BA7 +SBA0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +or ecx,[ebp+__dreg+20] +lahf +mov al,0 +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8BA8 - 8BAF +SBA8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +or ecx,[ebp+__dreg+20] +lahf +mov al,0 +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8BB0 - 8BB7 +SBB0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +or ecx,[ebp+__dreg+20] +lahf +mov al,0 +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8BB8 +SBB8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +or ecx,[ebp+__dreg+20] +lahf +mov al,0 +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8BB9 +SBB9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +or ecx,[ebp+__dreg+20] +lahf +mov al,0 +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8BC0 - 8BC7 +SBC0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +jnz short ln1617 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1619 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1620 +ln1619: +call basefunction +ln1620: +add esi,[ebp+__io_fetchbase] +sub edi,byte 38 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1617: +movsx ecx,cx +mov eax,[ebp+__dreg+20] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1621 +inc ecx +jne short ln1618 +ln1621: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+20],edx +sub edi,150 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1618: +mov ax,1 +sub edi,150 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8BD0 - 8BD7 +SBD0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +test cx,cx +jnz short ln1622 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1624 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1625 +ln1624: +call basefunction +ln1625: +add esi,[ebp+__io_fetchbase] +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1622: +movsx ecx,cx +mov eax,[ebp+__dreg+20] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1626 +inc ecx +jne short ln1623 +ln1626: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+20],edx +sub edi,154 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1623: +mov ax,1 +sub edi,154 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8BD8 - 8BDF +SBD8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +test cx,cx +jnz short ln1627 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1629 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1630 +ln1629: +call basefunction +ln1630: +add esi,[ebp+__io_fetchbase] +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1627: +movsx ecx,cx +mov eax,[ebp+__dreg+20] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1631 +inc ecx +jne short ln1628 +ln1631: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+20],edx +sub edi,154 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1628: +mov ax,1 +sub edi,154 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8BE0 - 8BE7 +SBE0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +test cx,cx +jnz short ln1632 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1634 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1635 +ln1634: +call basefunction +ln1635: +add esi,[ebp+__io_fetchbase] +sub edi,byte 44 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1632: +movsx ecx,cx +mov eax,[ebp+__dreg+20] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1636 +inc ecx +jne short ln1633 +ln1636: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+20],edx +sub edi,156 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1633: +mov ax,1 +sub edi,156 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8BE8 - 8BEF +SBE8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +test cx,cx +jnz short ln1637 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1639 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1640 +ln1639: +call basefunction +ln1640: +add esi,[ebp+__io_fetchbase] +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1637: +movsx ecx,cx +mov eax,[ebp+__dreg+20] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1641 +inc ecx +jne short ln1638 +ln1641: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+20],edx +sub edi,158 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1638: +mov ax,1 +sub edi,158 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8BF0 - 8BF7 +SBF0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +test cx,cx +jnz short ln1642 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1644 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1645 +ln1644: +call basefunction +ln1645: +add esi,[ebp+__io_fetchbase] +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1642: +movsx ecx,cx +mov eax,[ebp+__dreg+20] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1646 +inc ecx +jne short ln1643 +ln1646: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+20],edx +sub edi,160 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1643: +mov ax,1 +sub edi,160 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8BF8 +SBF8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +test cx,cx +jnz short ln1647 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1649 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1650 +ln1649: +call basefunction +ln1650: +add esi,[ebp+__io_fetchbase] +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1647: +movsx ecx,cx +mov eax,[ebp+__dreg+20] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1651 +inc ecx +jne short ln1648 +ln1651: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+20],edx +sub edi,158 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1648: +mov ax,1 +sub edi,158 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8BF9 +SBF9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +test cx,cx +jnz short ln1652 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1654 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1655 +ln1654: +call basefunction +ln1655: +add esi,[ebp+__io_fetchbase] +sub edi,byte 50 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1652: +movsx ecx,cx +mov eax,[ebp+__dreg+20] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1656 +inc ecx +jne short ln1653 +ln1656: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+20],edx +sub edi,162 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1653: +mov ax,1 +sub edi,162 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8BFA +SBFA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +test cx,cx +jnz short ln1657 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1659 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1660 +ln1659: +call basefunction +ln1660: +add esi,[ebp+__io_fetchbase] +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1657: +movsx ecx,cx +mov eax,[ebp+__dreg+20] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1661 +inc ecx +jne short ln1658 +ln1661: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+20],edx +sub edi,158 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1658: +mov ax,1 +sub edi,158 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8BFB +SBFB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +test cx,cx +jnz short ln1662 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1664 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1665 +ln1664: +call basefunction +ln1665: +add esi,[ebp+__io_fetchbase] +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1662: +movsx ecx,cx +mov eax,[ebp+__dreg+20] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1666 +inc ecx +jne short ln1663 +ln1666: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+20],edx +sub edi,160 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1663: +mov ax,1 +sub edi,160 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8BFC +SBFC: +mov cx,[esi] +add esi,byte 2 +test cx,cx +jnz short ln1667 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1669 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1670 +ln1669: +call basefunction +ln1670: +add esi,[ebp+__io_fetchbase] +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1667: +movsx ecx,cx +mov eax,[ebp+__dreg+20] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1671 +inc ecx +jne short ln1668 +ln1671: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+20],edx +sub edi,154 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1668: +mov ax,1 +sub edi,154 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8C00 - 8C07 +SC00: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +or [ebp+__dreg+24],cl +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8C10 - 8C17 +SC10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +or [ebp+__dreg+24],cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8C18 - 8C1F +SC18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +or [ebp+__dreg+24],cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8C20 - 8C27 +SC20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +or [ebp+__dreg+24],cl +lahf +mov al,0 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8C28 - 8C2F +SC28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +or [ebp+__dreg+24],cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8C30 - 8C37 +SC30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +or [ebp+__dreg+24],cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8C38 +SC38: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +or [ebp+__dreg+24],cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8C39 +SC39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +or [ebp+__dreg+24],cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8C3A +SC3A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +or [ebp+__dreg+24],cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8C3B +SC3B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +or [ebp+__dreg+24],cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8C3C +SC3C: +mov cx,[esi] +add esi,byte 2 +or [ebp+__dreg+24],cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8C40 - 8C47 +SC40: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +or [ebp+__dreg+24],cx +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8C50 - 8C57 +SC50: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +or [ebp+__dreg+24],cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8C58 - 8C5F +SC58: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +or [ebp+__dreg+24],cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8C60 - 8C67 +SC60: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +or [ebp+__dreg+24],cx +lahf +mov al,0 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8C68 - 8C6F +SC68: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +or [ebp+__dreg+24],cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8C70 - 8C77 +SC70: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +or [ebp+__dreg+24],cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8C78 +SC78: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +or [ebp+__dreg+24],cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8C79 +SC79: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +or [ebp+__dreg+24],cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8C7A +SC7A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +or [ebp+__dreg+24],cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8C7B +SC7B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +or [ebp+__dreg+24],cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8C7C +SC7C: +mov cx,[esi] +add esi,byte 2 +or [ebp+__dreg+24],cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8C80 - 8C87 +SC80: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +or [ebp+__dreg+24],ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8C90 - 8C97 +SC90: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +or [ebp+__dreg+24],ecx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8C98 - 8C9F +SC98: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +or [ebp+__dreg+24],ecx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8CA0 - 8CA7 +SCA0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +or [ebp+__dreg+24],ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8CA8 - 8CAF +SCA8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +or [ebp+__dreg+24],ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8CB0 - 8CB7 +SCB0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +or [ebp+__dreg+24],ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8CB8 +SCB8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +or [ebp+__dreg+24],ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8CB9 +SCB9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +or [ebp+__dreg+24],ecx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8CBA +SCBA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +or [ebp+__dreg+24],ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8CBB +SCBB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +or [ebp+__dreg+24],ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8CBC +SCBC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +or [ebp+__dreg+24],ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8CC0 - 8CC7 +SCC0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +jnz short ln1672 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1674 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1675 +ln1674: +call basefunction +ln1675: +add esi,[ebp+__io_fetchbase] +sub edi,byte 38 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1672: +and ecx,0FFFFh +mov eax,[ebp+__dreg+24] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1673 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+24],edx +sub edi,133 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1673: +mov ax,1 +sub edi,133 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8CD0 - 8CD7 +SCD0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +test cx,cx +jnz short ln1676 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1678 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1679 +ln1678: +call basefunction +ln1679: +add esi,[ebp+__io_fetchbase] +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1676: +and ecx,0FFFFh +mov eax,[ebp+__dreg+24] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1677 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+24],edx +sub edi,137 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1677: +mov ax,1 +sub edi,137 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8CD8 - 8CDF +SCD8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +test cx,cx +jnz short ln1680 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1682 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1683 +ln1682: +call basefunction +ln1683: +add esi,[ebp+__io_fetchbase] +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1680: +and ecx,0FFFFh +mov eax,[ebp+__dreg+24] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1681 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+24],edx +sub edi,137 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1681: +mov ax,1 +sub edi,137 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8CE0 - 8CE7 +SCE0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +test cx,cx +jnz short ln1684 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1686 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1687 +ln1686: +call basefunction +ln1687: +add esi,[ebp+__io_fetchbase] +sub edi,byte 44 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1684: +and ecx,0FFFFh +mov eax,[ebp+__dreg+24] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1685 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+24],edx +sub edi,139 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1685: +mov ax,1 +sub edi,139 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8CE8 - 8CEF +SCE8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +test cx,cx +jnz short ln1688 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1690 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1691 +ln1690: +call basefunction +ln1691: +add esi,[ebp+__io_fetchbase] +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1688: +and ecx,0FFFFh +mov eax,[ebp+__dreg+24] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1689 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+24],edx +sub edi,141 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1689: +mov ax,1 +sub edi,141 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8CF0 - 8CF7 +SCF0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +test cx,cx +jnz short ln1692 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1694 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1695 +ln1694: +call basefunction +ln1695: +add esi,[ebp+__io_fetchbase] +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1692: +and ecx,0FFFFh +mov eax,[ebp+__dreg+24] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1693 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+24],edx +sub edi,143 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1693: +mov ax,1 +sub edi,143 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8CF8 +SCF8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +test cx,cx +jnz short ln1696 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1698 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1699 +ln1698: +call basefunction +ln1699: +add esi,[ebp+__io_fetchbase] +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1696: +and ecx,0FFFFh +mov eax,[ebp+__dreg+24] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1697 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+24],edx +sub edi,141 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1697: +mov ax,1 +sub edi,141 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8CF9 +SCF9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +test cx,cx +jnz short ln1700 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1702 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1703 +ln1702: +call basefunction +ln1703: +add esi,[ebp+__io_fetchbase] +sub edi,byte 50 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1700: +and ecx,0FFFFh +mov eax,[ebp+__dreg+24] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1701 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+24],edx +sub edi,145 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1701: +mov ax,1 +sub edi,145 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8CFA +SCFA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +test cx,cx +jnz short ln1704 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1706 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1707 +ln1706: +call basefunction +ln1707: +add esi,[ebp+__io_fetchbase] +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1704: +and ecx,0FFFFh +mov eax,[ebp+__dreg+24] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1705 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+24],edx +sub edi,141 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1705: +mov ax,1 +sub edi,141 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8CFB +SCFB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +test cx,cx +jnz short ln1708 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1710 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1711 +ln1710: +call basefunction +ln1711: +add esi,[ebp+__io_fetchbase] +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1708: +and ecx,0FFFFh +mov eax,[ebp+__dreg+24] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1709 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+24],edx +sub edi,143 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1709: +mov ax,1 +sub edi,143 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8CFC +SCFC: +mov cx,[esi] +add esi,byte 2 +test cx,cx +jnz short ln1712 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1714 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1715 +ln1714: +call basefunction +ln1715: +add esi,[ebp+__io_fetchbase] +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1712: +and ecx,0FFFFh +mov eax,[ebp+__dreg+24] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1713 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+24],edx +sub edi,137 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1713: +mov ax,1 +sub edi,137 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8D00 - 8D07 +SD00: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+24] +sbb al,[ebp+__dreg+ebx*4] +das +mov [ebp+__dreg+24],al +lahf +mov al,0 +setc [ebp+__xflag] +jnz short ln1716 +or ch,0BFh +and ah,ch +ln1716: +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8D08 - 8D0F +SD08: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+24] +dec edx +call readmemorybyte +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +sbb al,bl +das +mov ebx,eax +lahf +mov al,0 +setc [ebp+__xflag] +jnz short ln1717 +or ch,0BFh +and ah,ch +ln1717: +mov ecx,ebx +xor ebx,ebx +call writememorybyte +mov [ebp+__areg+24],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8D10 - 8D17 +SD10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +or cl,[ebp+__dreg+24] +lahf +mov al,0 +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8D18 - 8D1F +SD18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +or cl,[ebp+__dreg+24] +lahf +mov al,0 +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8D20 - 8D27 +SD20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +or cl,[ebp+__dreg+24] +lahf +mov al,0 +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8D28 - 8D2F +SD28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +or cl,[ebp+__dreg+24] +lahf +mov al,0 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8D30 - 8D37 +SD30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +or cl,[ebp+__dreg+24] +lahf +mov al,0 +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8D38 +SD38: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +or cl,[ebp+__dreg+24] +lahf +mov al,0 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8D39 +SD39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +or cl,[ebp+__dreg+24] +lahf +mov al,0 +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8D50 - 8D57 +SD50: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +or cx,[ebp+__dreg+24] +lahf +mov al,0 +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8D58 - 8D5F +SD58: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +or cx,[ebp+__dreg+24] +lahf +mov al,0 +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8D60 - 8D67 +SD60: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +or cx,[ebp+__dreg+24] +lahf +mov al,0 +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8D68 - 8D6F +SD68: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +or cx,[ebp+__dreg+24] +lahf +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8D70 - 8D77 +SD70: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +or cx,[ebp+__dreg+24] +lahf +mov al,0 +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8D78 +SD78: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +or cx,[ebp+__dreg+24] +lahf +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8D79 +SD79: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +or cx,[ebp+__dreg+24] +lahf +mov al,0 +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8D90 - 8D97 +SD90: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +or ecx,[ebp+__dreg+24] +lahf +mov al,0 +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8D98 - 8D9F +SD98: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +or ecx,[ebp+__dreg+24] +lahf +mov al,0 +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8DA0 - 8DA7 +SDA0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +or ecx,[ebp+__dreg+24] +lahf +mov al,0 +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8DA8 - 8DAF +SDA8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +or ecx,[ebp+__dreg+24] +lahf +mov al,0 +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8DB0 - 8DB7 +SDB0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +or ecx,[ebp+__dreg+24] +lahf +mov al,0 +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8DB8 +SDB8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +or ecx,[ebp+__dreg+24] +lahf +mov al,0 +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8DB9 +SDB9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +or ecx,[ebp+__dreg+24] +lahf +mov al,0 +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8DC0 - 8DC7 +SDC0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +jnz short ln1718 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1720 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1721 +ln1720: +call basefunction +ln1721: +add esi,[ebp+__io_fetchbase] +sub edi,byte 38 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1718: +movsx ecx,cx +mov eax,[ebp+__dreg+24] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1722 +inc ecx +jne short ln1719 +ln1722: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+24],edx +sub edi,150 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1719: +mov ax,1 +sub edi,150 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8DD0 - 8DD7 +SDD0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +test cx,cx +jnz short ln1723 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1725 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1726 +ln1725: +call basefunction +ln1726: +add esi,[ebp+__io_fetchbase] +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1723: +movsx ecx,cx +mov eax,[ebp+__dreg+24] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1727 +inc ecx +jne short ln1724 +ln1727: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+24],edx +sub edi,154 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1724: +mov ax,1 +sub edi,154 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8DD8 - 8DDF +SDD8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +test cx,cx +jnz short ln1728 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1730 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1731 +ln1730: +call basefunction +ln1731: +add esi,[ebp+__io_fetchbase] +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1728: +movsx ecx,cx +mov eax,[ebp+__dreg+24] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1732 +inc ecx +jne short ln1729 +ln1732: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+24],edx +sub edi,154 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1729: +mov ax,1 +sub edi,154 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8DE0 - 8DE7 +SDE0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +test cx,cx +jnz short ln1733 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1735 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1736 +ln1735: +call basefunction +ln1736: +add esi,[ebp+__io_fetchbase] +sub edi,byte 44 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1733: +movsx ecx,cx +mov eax,[ebp+__dreg+24] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1737 +inc ecx +jne short ln1734 +ln1737: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+24],edx +sub edi,156 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1734: +mov ax,1 +sub edi,156 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8DE8 - 8DEF +SDE8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +test cx,cx +jnz short ln1738 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1740 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1741 +ln1740: +call basefunction +ln1741: +add esi,[ebp+__io_fetchbase] +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1738: +movsx ecx,cx +mov eax,[ebp+__dreg+24] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1742 +inc ecx +jne short ln1739 +ln1742: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+24],edx +sub edi,158 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1739: +mov ax,1 +sub edi,158 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8DF0 - 8DF7 +SDF0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +test cx,cx +jnz short ln1743 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1745 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1746 +ln1745: +call basefunction +ln1746: +add esi,[ebp+__io_fetchbase] +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1743: +movsx ecx,cx +mov eax,[ebp+__dreg+24] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1747 +inc ecx +jne short ln1744 +ln1747: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+24],edx +sub edi,160 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1744: +mov ax,1 +sub edi,160 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8DF8 +SDF8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +test cx,cx +jnz short ln1748 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1750 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1751 +ln1750: +call basefunction +ln1751: +add esi,[ebp+__io_fetchbase] +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1748: +movsx ecx,cx +mov eax,[ebp+__dreg+24] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1752 +inc ecx +jne short ln1749 +ln1752: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+24],edx +sub edi,158 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1749: +mov ax,1 +sub edi,158 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8DF9 +SDF9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +test cx,cx +jnz short ln1753 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1755 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1756 +ln1755: +call basefunction +ln1756: +add esi,[ebp+__io_fetchbase] +sub edi,byte 50 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1753: +movsx ecx,cx +mov eax,[ebp+__dreg+24] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1757 +inc ecx +jne short ln1754 +ln1757: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+24],edx +sub edi,162 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1754: +mov ax,1 +sub edi,162 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8DFA +SDFA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +test cx,cx +jnz short ln1758 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1760 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1761 +ln1760: +call basefunction +ln1761: +add esi,[ebp+__io_fetchbase] +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1758: +movsx ecx,cx +mov eax,[ebp+__dreg+24] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1762 +inc ecx +jne short ln1759 +ln1762: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+24],edx +sub edi,158 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1759: +mov ax,1 +sub edi,158 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8DFB +SDFB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +test cx,cx +jnz short ln1763 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1765 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1766 +ln1765: +call basefunction +ln1766: +add esi,[ebp+__io_fetchbase] +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1763: +movsx ecx,cx +mov eax,[ebp+__dreg+24] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1767 +inc ecx +jne short ln1764 +ln1767: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+24],edx +sub edi,160 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1764: +mov ax,1 +sub edi,160 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8DFC +SDFC: +mov cx,[esi] +add esi,byte 2 +test cx,cx +jnz short ln1768 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1770 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1771 +ln1770: +call basefunction +ln1771: +add esi,[ebp+__io_fetchbase] +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1768: +movsx ecx,cx +mov eax,[ebp+__dreg+24] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1772 +inc ecx +jne short ln1769 +ln1772: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+24],edx +sub edi,154 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1769: +mov ax,1 +sub edi,154 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8E00 - 8E07 +SE00: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +or [ebp+__dreg+28],cl +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8E10 - 8E17 +SE10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +or [ebp+__dreg+28],cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8E18 - 8E1F +SE18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +or [ebp+__dreg+28],cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8E20 - 8E27 +SE20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +or [ebp+__dreg+28],cl +lahf +mov al,0 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8E28 - 8E2F +SE28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +or [ebp+__dreg+28],cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8E30 - 8E37 +SE30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +or [ebp+__dreg+28],cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8E38 +SE38: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +or [ebp+__dreg+28],cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8E39 +SE39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +or [ebp+__dreg+28],cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8E3A +SE3A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +or [ebp+__dreg+28],cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8E3B +SE3B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +or [ebp+__dreg+28],cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8E3C +SE3C: +mov cx,[esi] +add esi,byte 2 +or [ebp+__dreg+28],cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8E40 - 8E47 +SE40: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +or [ebp+__dreg+28],cx +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8E50 - 8E57 +SE50: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +or [ebp+__dreg+28],cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8E58 - 8E5F +SE58: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +or [ebp+__dreg+28],cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8E60 - 8E67 +SE60: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +or [ebp+__dreg+28],cx +lahf +mov al,0 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8E68 - 8E6F +SE68: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +or [ebp+__dreg+28],cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8E70 - 8E77 +SE70: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +or [ebp+__dreg+28],cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8E78 +SE78: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +or [ebp+__dreg+28],cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8E79 +SE79: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +or [ebp+__dreg+28],cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8E7A +SE7A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +or [ebp+__dreg+28],cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8E7B +SE7B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +or [ebp+__dreg+28],cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8E7C +SE7C: +mov cx,[esi] +add esi,byte 2 +or [ebp+__dreg+28],cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8E80 - 8E87 +SE80: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +or [ebp+__dreg+28],ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8E90 - 8E97 +SE90: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +or [ebp+__dreg+28],ecx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8E98 - 8E9F +SE98: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +or [ebp+__dreg+28],ecx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8EA0 - 8EA7 +SEA0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +or [ebp+__dreg+28],ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8EA8 - 8EAF +SEA8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +or [ebp+__dreg+28],ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8EB0 - 8EB7 +SEB0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +or [ebp+__dreg+28],ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8EB8 +SEB8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +or [ebp+__dreg+28],ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8EB9 +SEB9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +or [ebp+__dreg+28],ecx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8EBA +SEBA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +or [ebp+__dreg+28],ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8EBB +SEBB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +or [ebp+__dreg+28],ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8EBC +SEBC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +or [ebp+__dreg+28],ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8EC0 - 8EC7 +SEC0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +jnz short ln1773 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1775 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1776 +ln1775: +call basefunction +ln1776: +add esi,[ebp+__io_fetchbase] +sub edi,byte 38 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1773: +and ecx,0FFFFh +mov eax,[ebp+__dreg+28] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1774 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+28],edx +sub edi,133 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1774: +mov ax,1 +sub edi,133 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8ED0 - 8ED7 +SED0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +test cx,cx +jnz short ln1777 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1779 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1780 +ln1779: +call basefunction +ln1780: +add esi,[ebp+__io_fetchbase] +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1777: +and ecx,0FFFFh +mov eax,[ebp+__dreg+28] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1778 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+28],edx +sub edi,137 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1778: +mov ax,1 +sub edi,137 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8ED8 - 8EDF +SED8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +test cx,cx +jnz short ln1781 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1783 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1784 +ln1783: +call basefunction +ln1784: +add esi,[ebp+__io_fetchbase] +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1781: +and ecx,0FFFFh +mov eax,[ebp+__dreg+28] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1782 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+28],edx +sub edi,137 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1782: +mov ax,1 +sub edi,137 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8EE0 - 8EE7 +SEE0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +test cx,cx +jnz short ln1785 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1787 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1788 +ln1787: +call basefunction +ln1788: +add esi,[ebp+__io_fetchbase] +sub edi,byte 44 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1785: +and ecx,0FFFFh +mov eax,[ebp+__dreg+28] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1786 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+28],edx +sub edi,139 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1786: +mov ax,1 +sub edi,139 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8EE8 - 8EEF +SEE8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +test cx,cx +jnz short ln1789 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1791 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1792 +ln1791: +call basefunction +ln1792: +add esi,[ebp+__io_fetchbase] +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1789: +and ecx,0FFFFh +mov eax,[ebp+__dreg+28] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1790 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+28],edx +sub edi,141 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1790: +mov ax,1 +sub edi,141 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8EF0 - 8EF7 +SEF0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +test cx,cx +jnz short ln1793 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1795 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1796 +ln1795: +call basefunction +ln1796: +add esi,[ebp+__io_fetchbase] +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1793: +and ecx,0FFFFh +mov eax,[ebp+__dreg+28] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1794 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+28],edx +sub edi,143 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1794: +mov ax,1 +sub edi,143 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8EF8 +SEF8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +test cx,cx +jnz short ln1797 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1799 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1800 +ln1799: +call basefunction +ln1800: +add esi,[ebp+__io_fetchbase] +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1797: +and ecx,0FFFFh +mov eax,[ebp+__dreg+28] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1798 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+28],edx +sub edi,141 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1798: +mov ax,1 +sub edi,141 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8EF9 +SEF9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +test cx,cx +jnz short ln1801 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1803 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1804 +ln1803: +call basefunction +ln1804: +add esi,[ebp+__io_fetchbase] +sub edi,byte 50 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1801: +and ecx,0FFFFh +mov eax,[ebp+__dreg+28] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1802 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+28],edx +sub edi,145 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1802: +mov ax,1 +sub edi,145 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8EFA +SEFA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +test cx,cx +jnz short ln1805 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1807 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1808 +ln1807: +call basefunction +ln1808: +add esi,[ebp+__io_fetchbase] +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1805: +and ecx,0FFFFh +mov eax,[ebp+__dreg+28] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1806 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+28],edx +sub edi,141 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1806: +mov ax,1 +sub edi,141 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8EFB +SEFB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +test cx,cx +jnz short ln1809 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1811 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1812 +ln1811: +call basefunction +ln1812: +add esi,[ebp+__io_fetchbase] +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1809: +and ecx,0FFFFh +mov eax,[ebp+__dreg+28] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1810 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+28],edx +sub edi,143 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1810: +mov ax,1 +sub edi,143 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8EFC +SEFC: +mov cx,[esi] +add esi,byte 2 +test cx,cx +jnz short ln1813 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1815 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1816 +ln1815: +call basefunction +ln1816: +add esi,[ebp+__io_fetchbase] +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1813: +and ecx,0FFFFh +mov eax,[ebp+__dreg+28] +xor edx,edx +div ecx +test eax,0FFFF0000h +jnz short ln1814 +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+28],edx +sub edi,137 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1814: +mov ax,1 +sub edi,137 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8F00 - 8F07 +SF00: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+28] +sbb al,[ebp+__dreg+ebx*4] +das +mov [ebp+__dreg+28],al +lahf +mov al,0 +setc [ebp+__xflag] +jnz short ln1817 +or ch,0BFh +and ah,ch +ln1817: +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8F08 - 8F0F +SF08: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+28] +sub edx,byte 2 +call readmemorybyte +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +sbb al,bl +das +mov ebx,eax +lahf +mov al,0 +setc [ebp+__xflag] +jnz short ln1818 +or ch,0BFh +and ah,ch +ln1818: +mov ecx,ebx +xor ebx,ebx +call writememorybyte +mov [ebp+__areg+28],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8F10 - 8F17 +SF10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +or cl,[ebp+__dreg+28] +lahf +mov al,0 +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8F18 - 8F1F +SF18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +or cl,[ebp+__dreg+28] +lahf +mov al,0 +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8F20 - 8F27 +SF20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +or cl,[ebp+__dreg+28] +lahf +mov al,0 +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8F28 - 8F2F +SF28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +or cl,[ebp+__dreg+28] +lahf +mov al,0 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8F30 - 8F37 +SF30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +or cl,[ebp+__dreg+28] +lahf +mov al,0 +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8F38 +SF38: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +or cl,[ebp+__dreg+28] +lahf +mov al,0 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8F39 +SF39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +or cl,[ebp+__dreg+28] +lahf +mov al,0 +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8F50 - 8F57 +SF50: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +or cx,[ebp+__dreg+28] +lahf +mov al,0 +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8F58 - 8F5F +SF58: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +or cx,[ebp+__dreg+28] +lahf +mov al,0 +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8F60 - 8F67 +SF60: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +or cx,[ebp+__dreg+28] +lahf +mov al,0 +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8F68 - 8F6F +SF68: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +or cx,[ebp+__dreg+28] +lahf +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8F70 - 8F77 +SF70: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +or cx,[ebp+__dreg+28] +lahf +mov al,0 +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8F78 +SF78: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +or cx,[ebp+__dreg+28] +lahf +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8F79 +SF79: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +or cx,[ebp+__dreg+28] +lahf +mov al,0 +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8F90 - 8F97 +SF90: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +or ecx,[ebp+__dreg+28] +lahf +mov al,0 +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8F98 - 8F9F +SF98: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +or ecx,[ebp+__dreg+28] +lahf +mov al,0 +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8FA0 - 8FA7 +SFA0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +or ecx,[ebp+__dreg+28] +lahf +mov al,0 +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8FA8 - 8FAF +SFA8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +or ecx,[ebp+__dreg+28] +lahf +mov al,0 +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8FB0 - 8FB7 +SFB0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +or ecx,[ebp+__dreg+28] +lahf +mov al,0 +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8FB8 +SFB8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +or ecx,[ebp+__dreg+28] +lahf +mov al,0 +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8FB9 +SFB9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +or ecx,[ebp+__dreg+28] +lahf +mov al,0 +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8FC0 - 8FC7 +SFC0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +jnz short ln1819 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1821 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1822 +ln1821: +call basefunction +ln1822: +add esi,[ebp+__io_fetchbase] +sub edi,byte 38 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1819: +movsx ecx,cx +mov eax,[ebp+__dreg+28] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1823 +inc ecx +jne short ln1820 +ln1823: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+28],edx +sub edi,150 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1820: +mov ax,1 +sub edi,150 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8FD0 - 8FD7 +SFD0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +test cx,cx +jnz short ln1824 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1826 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1827 +ln1826: +call basefunction +ln1827: +add esi,[ebp+__io_fetchbase] +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1824: +movsx ecx,cx +mov eax,[ebp+__dreg+28] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1828 +inc ecx +jne short ln1825 +ln1828: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+28],edx +sub edi,154 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1825: +mov ax,1 +sub edi,154 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8FD8 - 8FDF +SFD8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +test cx,cx +jnz short ln1829 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1831 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1832 +ln1831: +call basefunction +ln1832: +add esi,[ebp+__io_fetchbase] +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1829: +movsx ecx,cx +mov eax,[ebp+__dreg+28] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1833 +inc ecx +jne short ln1830 +ln1833: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+28],edx +sub edi,154 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1830: +mov ax,1 +sub edi,154 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8FE0 - 8FE7 +SFE0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +test cx,cx +jnz short ln1834 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1836 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1837 +ln1836: +call basefunction +ln1837: +add esi,[ebp+__io_fetchbase] +sub edi,byte 44 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1834: +movsx ecx,cx +mov eax,[ebp+__dreg+28] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1838 +inc ecx +jne short ln1835 +ln1838: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+28],edx +sub edi,156 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1835: +mov ax,1 +sub edi,156 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8FE8 - 8FEF +SFE8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +test cx,cx +jnz short ln1839 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1841 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1842 +ln1841: +call basefunction +ln1842: +add esi,[ebp+__io_fetchbase] +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1839: +movsx ecx,cx +mov eax,[ebp+__dreg+28] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1843 +inc ecx +jne short ln1840 +ln1843: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+28],edx +sub edi,158 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1840: +mov ax,1 +sub edi,158 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 8FF0 - 8FF7 +SFF0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +test cx,cx +jnz short ln1844 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1846 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1847 +ln1846: +call basefunction +ln1847: +add esi,[ebp+__io_fetchbase] +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1844: +movsx ecx,cx +mov eax,[ebp+__dreg+28] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1848 +inc ecx +jne short ln1845 +ln1848: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+28],edx +sub edi,160 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1845: +mov ax,1 +sub edi,160 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8FF8 +SFF8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +test cx,cx +jnz short ln1849 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1851 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1852 +ln1851: +call basefunction +ln1852: +add esi,[ebp+__io_fetchbase] +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1849: +movsx ecx,cx +mov eax,[ebp+__dreg+28] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1853 +inc ecx +jne short ln1850 +ln1853: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+28],edx +sub edi,158 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1850: +mov ax,1 +sub edi,158 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8FF9 +SFF9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +test cx,cx +jnz short ln1854 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1856 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1857 +ln1856: +call basefunction +ln1857: +add esi,[ebp+__io_fetchbase] +sub edi,byte 50 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1854: +movsx ecx,cx +mov eax,[ebp+__dreg+28] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1858 +inc ecx +jne short ln1855 +ln1858: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+28],edx +sub edi,162 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1855: +mov ax,1 +sub edi,162 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8FFA +SFFA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +test cx,cx +jnz short ln1859 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1861 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1862 +ln1861: +call basefunction +ln1862: +add esi,[ebp+__io_fetchbase] +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1859: +movsx ecx,cx +mov eax,[ebp+__dreg+28] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1863 +inc ecx +jne short ln1860 +ln1863: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+28],edx +sub edi,158 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1860: +mov ax,1 +sub edi,158 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8FFB +SFFB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +test cx,cx +jnz short ln1864 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1866 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1867 +ln1866: +call basefunction +ln1867: +add esi,[ebp+__io_fetchbase] +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1864: +movsx ecx,cx +mov eax,[ebp+__dreg+28] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1868 +inc ecx +jne short ln1865 +ln1868: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+28],edx +sub edi,160 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1865: +mov ax,1 +sub edi,160 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 8FFC +SFFC: +mov cx,[esi] +add esi,byte 2 +test cx,cx +jnz short ln1869 +mov edx,14h +call group_2_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1871 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1872 +ln1871: +call basefunction +ln1872: +add esi,[ebp+__io_fetchbase] +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1869: +movsx ecx,cx +mov eax,[ebp+__dreg+28] +mov edx,eax +sar edx,31 +idiv ecx +mov ecx,eax +sar cx,15 +or ecx,ecx +je short ln1873 +inc ecx +jne short ln1870 +ln1873: +and eax,0FFFFh +shl edx,16 +mov dx,ax +test dx,dx +lahf +mov al,0 +mov [ebp+__dreg+28],edx +sub edi,154 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln1870: +mov ax,1 +sub edi,154 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9000 - 9007 +T000: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +sub [ebp+__dreg+0],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9010 - 9017 +T010: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub [ebp+__dreg+0],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9018 - 901F +T018: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub [ebp+__dreg+0],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9020 - 9027 +T020: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +sub [ebp+__dreg+0],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9028 - 902F +T028: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub [ebp+__dreg+0],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9030 - 9037 +T030: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub [ebp+__dreg+0],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9038 +T038: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +sub [ebp+__dreg+0],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9039 +T039: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +sub [ebp+__dreg+0],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 903A +T03A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +sub [ebp+__dreg+0],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 903B +T03B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +sub [ebp+__dreg+0],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 903C +T03C: +mov cx,[esi] +add esi,byte 2 +sub [ebp+__dreg+0],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9040 - 9047 +T040: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +sub [ebp+__dreg+0],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9048 - 904F +T048: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +sub [ebp+__dreg+0],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9050 - 9057 +T050: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +sub [ebp+__dreg+0],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9058 - 905F +T058: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub [ebp+__dreg+0],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9060 - 9067 +T060: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +sub [ebp+__dreg+0],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9068 - 906F +T068: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +sub [ebp+__dreg+0],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9070 - 9077 +T070: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +sub [ebp+__dreg+0],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9078 +T078: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +sub [ebp+__dreg+0],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9079 +T079: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +sub [ebp+__dreg+0],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 907A +T07A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +sub [ebp+__dreg+0],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 907B +T07B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +sub [ebp+__dreg+0],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 907C +T07C: +mov cx,[esi] +add esi,byte 2 +sub [ebp+__dreg+0],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9080 - 9087 +T080: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +sub [ebp+__dreg+0],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9088 - 908F +T088: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +sub [ebp+__dreg+0],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9090 - 9097 +T090: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +sub [ebp+__dreg+0],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9098 - 909F +T098: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub [ebp+__dreg+0],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 90A0 - 90A7 +T0A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +sub [ebp+__dreg+0],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 90A8 - 90AF +T0A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub [ebp+__dreg+0],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 90B0 - 90B7 +T0B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub [ebp+__dreg+0],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 90B8 +T0B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +sub [ebp+__dreg+0],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 90B9 +T0B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +sub [ebp+__dreg+0],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 90BA +T0BA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +sub [ebp+__dreg+0],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 90BB +T0BB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +sub [ebp+__dreg+0],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 90BC +T0BC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +sub [ebp+__dreg+0],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 90C0 - 90C7 +T0C0: +and ebx,byte 7 +movsx ecx,word[ebp+__dreg+ebx*4] +sub [ebp+__areg+0],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 90C8 - 90CF +T0C8: +and ebx,byte 7 +movsx ecx,word[ebp+__areg+ebx*4] +sub [ebp+__areg+0],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 90D0 - 90D7 +T0D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +sub [ebp+__areg+0],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 90D8 - 90DF +T0D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub [ebp+__areg+0],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 90E0 - 90E7 +T0E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+ebx*4],edx +sub [ebp+__areg+0],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 90E8 - 90EF +T0E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +sub [ebp+__areg+0],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 90F0 - 90F7 +T0F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +sub [ebp+__areg+0],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 90F8 +T0F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +sub [ebp+__areg+0],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 90F9 +T0F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +movsx ecx,cx +sub [ebp+__areg+0],ecx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 90FA +T0FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +sub [ebp+__areg+0],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 90FB +T0FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +sub [ebp+__areg+0],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 90FC +T0FC: +movsx ecx,word[esi] +add esi,byte 2 +sub [ebp+__areg+0],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9100 - 9107 +T100: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+0] +sbb al,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+0],al +lahf +seto al +setc [ebp+__xflag] +jnz short ln1874 +or ch,0BFh +and ah,ch +ln1874: +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9108 - 910F +T108: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+0] +dec edx +call readmemorybyte +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +sbb al,bl +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln1875 +or ch,0BFh +and ah,ch +ln1875: +mov ecx,ebx +xor ebx,ebx +call writememorybyte +mov [ebp+__areg+0],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9110 - 9117 +T110: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,[ebp+__dreg+0] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9118 - 911F +T118: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,[ebp+__dreg+0] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9120 - 9127 +T120: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +sub cl,[ebp+__dreg+0] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9128 - 912F +T128: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,[ebp+__dreg+0] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9130 - 9137 +T130: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,[ebp+__dreg+0] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9138 +T138: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +sub cl,[ebp+__dreg+0] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9139 +T139: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +sub cl,[ebp+__dreg+0] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9140 - 9147 +T140: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+0] +sbb ax,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+0],ax +lahf +seto al +setc [ebp+__xflag] +jnz short ln1876 +or ch,0BFh +and ah,ch +ln1876: +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9148 - 914F +T148: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+0] +sub edx,byte 2 +call readmemoryword +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +sbb ax,bx +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln1877 +or ch,0BFh +and ah,ch +ln1877: +mov ecx,ebx +xor ebx,ebx +call writememoryword +mov [ebp+__areg+0],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9150 - 9157 +T150: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,[ebp+__dreg+0] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9158 - 915F +T158: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,[ebp+__dreg+0] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9160 - 9167 +T160: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +sub cx,[ebp+__dreg+0] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9168 - 916F +T168: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,[ebp+__dreg+0] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9170 - 9177 +T170: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,[ebp+__dreg+0] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9178 +T178: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +sub cx,[ebp+__dreg+0] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9179 +T179: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +sub cx,[ebp+__dreg+0] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9180 - 9187 +T180: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+0] +sbb eax,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+0],eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln1878 +or ch,0BFh +and ah,ch +ln1878: +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9188 - 918F +T188: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+0] +sub edx,byte 4 +call readmemorydword +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +sbb eax,ebx +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln1879 +or ch,0BFh +and ah,ch +ln1879: +mov ecx,ebx +xor ebx,ebx +call writememorydword +mov [ebp+__areg+0],edx +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9190 - 9197 +T190: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,[ebp+__dreg+0] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9198 - 919F +T198: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,[ebp+__dreg+0] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 91A0 - 91A7 +T1A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +sub ecx,[ebp+__dreg+0] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 91A8 - 91AF +T1A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,[ebp+__dreg+0] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 91B0 - 91B7 +T1B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,[ebp+__dreg+0] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 91B8 +T1B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +sub ecx,[ebp+__dreg+0] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 91B9 +T1B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +sub ecx,[ebp+__dreg+0] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 91C0 - 91C7 +T1C0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +sub [ebp+__areg+0],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 91C8 - 91CF +T1C8: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +sub [ebp+__areg+0],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 91D0 - 91D7 +T1D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +sub [ebp+__areg+0],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 91D8 - 91DF +T1D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub [ebp+__areg+0],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 91E0 - 91E7 +T1E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +sub [ebp+__areg+0],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 91E8 - 91EF +T1E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub [ebp+__areg+0],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 91F0 - 91F7 +T1F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub [ebp+__areg+0],ecx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 91F8 +T1F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +sub [ebp+__areg+0],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 91F9 +T1F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +sub [ebp+__areg+0],ecx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 91FA +T1FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +sub [ebp+__areg+0],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 91FB +T1FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +sub [ebp+__areg+0],ecx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 91FC +T1FC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +sub [ebp+__areg+0],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9200 - 9207 +T200: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +sub [ebp+__dreg+4],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9210 - 9217 +T210: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub [ebp+__dreg+4],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9218 - 921F +T218: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub [ebp+__dreg+4],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9220 - 9227 +T220: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +sub [ebp+__dreg+4],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9228 - 922F +T228: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub [ebp+__dreg+4],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9230 - 9237 +T230: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub [ebp+__dreg+4],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9238 +T238: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +sub [ebp+__dreg+4],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9239 +T239: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +sub [ebp+__dreg+4],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 923A +T23A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +sub [ebp+__dreg+4],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 923B +T23B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +sub [ebp+__dreg+4],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 923C +T23C: +mov cx,[esi] +add esi,byte 2 +sub [ebp+__dreg+4],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9240 - 9247 +T240: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +sub [ebp+__dreg+4],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9248 - 924F +T248: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +sub [ebp+__dreg+4],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9250 - 9257 +T250: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +sub [ebp+__dreg+4],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9258 - 925F +T258: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub [ebp+__dreg+4],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9260 - 9267 +T260: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +sub [ebp+__dreg+4],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9268 - 926F +T268: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +sub [ebp+__dreg+4],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9270 - 9277 +T270: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +sub [ebp+__dreg+4],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9278 +T278: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +sub [ebp+__dreg+4],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9279 +T279: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +sub [ebp+__dreg+4],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 927A +T27A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +sub [ebp+__dreg+4],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 927B +T27B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +sub [ebp+__dreg+4],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 927C +T27C: +mov cx,[esi] +add esi,byte 2 +sub [ebp+__dreg+4],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9280 - 9287 +T280: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +sub [ebp+__dreg+4],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9288 - 928F +T288: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +sub [ebp+__dreg+4],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9290 - 9297 +T290: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +sub [ebp+__dreg+4],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9298 - 929F +T298: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub [ebp+__dreg+4],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 92A0 - 92A7 +T2A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +sub [ebp+__dreg+4],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 92A8 - 92AF +T2A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub [ebp+__dreg+4],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 92B0 - 92B7 +T2B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub [ebp+__dreg+4],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 92B8 +T2B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +sub [ebp+__dreg+4],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 92B9 +T2B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +sub [ebp+__dreg+4],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 92BA +T2BA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +sub [ebp+__dreg+4],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 92BB +T2BB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +sub [ebp+__dreg+4],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 92BC +T2BC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +sub [ebp+__dreg+4],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 92C0 - 92C7 +T2C0: +and ebx,byte 7 +movsx ecx,word[ebp+__dreg+ebx*4] +sub [ebp+__areg+4],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 92C8 - 92CF +T2C8: +and ebx,byte 7 +movsx ecx,word[ebp+__areg+ebx*4] +sub [ebp+__areg+4],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 92D0 - 92D7 +T2D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +sub [ebp+__areg+4],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 92D8 - 92DF +T2D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub [ebp+__areg+4],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 92E0 - 92E7 +T2E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+ebx*4],edx +sub [ebp+__areg+4],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 92E8 - 92EF +T2E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +sub [ebp+__areg+4],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 92F0 - 92F7 +T2F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +sub [ebp+__areg+4],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 92F8 +T2F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +sub [ebp+__areg+4],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 92F9 +T2F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +movsx ecx,cx +sub [ebp+__areg+4],ecx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 92FA +T2FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +sub [ebp+__areg+4],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 92FB +T2FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +sub [ebp+__areg+4],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 92FC +T2FC: +movsx ecx,word[esi] +add esi,byte 2 +sub [ebp+__areg+4],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9300 - 9307 +T300: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+4] +sbb al,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+4],al +lahf +seto al +setc [ebp+__xflag] +jnz short ln1880 +or ch,0BFh +and ah,ch +ln1880: +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9308 - 930F +T308: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+4] +dec edx +call readmemorybyte +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +sbb al,bl +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln1881 +or ch,0BFh +and ah,ch +ln1881: +mov ecx,ebx +xor ebx,ebx +call writememorybyte +mov [ebp+__areg+4],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9310 - 9317 +T310: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,[ebp+__dreg+4] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9318 - 931F +T318: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,[ebp+__dreg+4] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9320 - 9327 +T320: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +sub cl,[ebp+__dreg+4] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9328 - 932F +T328: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,[ebp+__dreg+4] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9330 - 9337 +T330: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,[ebp+__dreg+4] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9338 +T338: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +sub cl,[ebp+__dreg+4] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9339 +T339: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +sub cl,[ebp+__dreg+4] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9340 - 9347 +T340: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+4] +sbb ax,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+4],ax +lahf +seto al +setc [ebp+__xflag] +jnz short ln1882 +or ch,0BFh +and ah,ch +ln1882: +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9348 - 934F +T348: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+4] +sub edx,byte 2 +call readmemoryword +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +sbb ax,bx +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln1883 +or ch,0BFh +and ah,ch +ln1883: +mov ecx,ebx +xor ebx,ebx +call writememoryword +mov [ebp+__areg+4],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9350 - 9357 +T350: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,[ebp+__dreg+4] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9358 - 935F +T358: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,[ebp+__dreg+4] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9360 - 9367 +T360: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +sub cx,[ebp+__dreg+4] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9368 - 936F +T368: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,[ebp+__dreg+4] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9370 - 9377 +T370: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,[ebp+__dreg+4] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9378 +T378: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +sub cx,[ebp+__dreg+4] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9379 +T379: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +sub cx,[ebp+__dreg+4] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9380 - 9387 +T380: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+4] +sbb eax,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+4],eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln1884 +or ch,0BFh +and ah,ch +ln1884: +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9388 - 938F +T388: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+4] +sub edx,byte 4 +call readmemorydword +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +sbb eax,ebx +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln1885 +or ch,0BFh +and ah,ch +ln1885: +mov ecx,ebx +xor ebx,ebx +call writememorydword +mov [ebp+__areg+4],edx +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9390 - 9397 +T390: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,[ebp+__dreg+4] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9398 - 939F +T398: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,[ebp+__dreg+4] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 93A0 - 93A7 +T3A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +sub ecx,[ebp+__dreg+4] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 93A8 - 93AF +T3A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,[ebp+__dreg+4] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 93B0 - 93B7 +T3B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,[ebp+__dreg+4] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 93B8 +T3B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +sub ecx,[ebp+__dreg+4] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 93B9 +T3B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +sub ecx,[ebp+__dreg+4] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 93C0 - 93C7 +T3C0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +sub [ebp+__areg+4],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 93C8 - 93CF +T3C8: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +sub [ebp+__areg+4],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 93D0 - 93D7 +T3D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +sub [ebp+__areg+4],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 93D8 - 93DF +T3D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub [ebp+__areg+4],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 93E0 - 93E7 +T3E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +sub [ebp+__areg+4],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 93E8 - 93EF +T3E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub [ebp+__areg+4],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 93F0 - 93F7 +T3F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub [ebp+__areg+4],ecx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 93F8 +T3F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +sub [ebp+__areg+4],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 93F9 +T3F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +sub [ebp+__areg+4],ecx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 93FA +T3FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +sub [ebp+__areg+4],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 93FB +T3FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +sub [ebp+__areg+4],ecx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 93FC +T3FC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +sub [ebp+__areg+4],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9400 - 9407 +T400: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +sub [ebp+__dreg+8],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9410 - 9417 +T410: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub [ebp+__dreg+8],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9418 - 941F +T418: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub [ebp+__dreg+8],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9420 - 9427 +T420: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +sub [ebp+__dreg+8],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9428 - 942F +T428: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub [ebp+__dreg+8],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9430 - 9437 +T430: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub [ebp+__dreg+8],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9438 +T438: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +sub [ebp+__dreg+8],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9439 +T439: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +sub [ebp+__dreg+8],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 943A +T43A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +sub [ebp+__dreg+8],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 943B +T43B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +sub [ebp+__dreg+8],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 943C +T43C: +mov cx,[esi] +add esi,byte 2 +sub [ebp+__dreg+8],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9440 - 9447 +T440: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +sub [ebp+__dreg+8],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9448 - 944F +T448: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +sub [ebp+__dreg+8],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9450 - 9457 +T450: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +sub [ebp+__dreg+8],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9458 - 945F +T458: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub [ebp+__dreg+8],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9460 - 9467 +T460: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +sub [ebp+__dreg+8],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9468 - 946F +T468: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +sub [ebp+__dreg+8],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9470 - 9477 +T470: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +sub [ebp+__dreg+8],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9478 +T478: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +sub [ebp+__dreg+8],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9479 +T479: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +sub [ebp+__dreg+8],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 947A +T47A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +sub [ebp+__dreg+8],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 947B +T47B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +sub [ebp+__dreg+8],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 947C +T47C: +mov cx,[esi] +add esi,byte 2 +sub [ebp+__dreg+8],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9480 - 9487 +T480: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +sub [ebp+__dreg+8],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9488 - 948F +T488: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +sub [ebp+__dreg+8],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9490 - 9497 +T490: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +sub [ebp+__dreg+8],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9498 - 949F +T498: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub [ebp+__dreg+8],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 94A0 - 94A7 +T4A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +sub [ebp+__dreg+8],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 94A8 - 94AF +T4A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub [ebp+__dreg+8],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 94B0 - 94B7 +T4B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub [ebp+__dreg+8],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 94B8 +T4B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +sub [ebp+__dreg+8],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 94B9 +T4B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +sub [ebp+__dreg+8],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 94BA +T4BA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +sub [ebp+__dreg+8],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 94BB +T4BB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +sub [ebp+__dreg+8],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 94BC +T4BC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +sub [ebp+__dreg+8],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 94C0 - 94C7 +T4C0: +and ebx,byte 7 +movsx ecx,word[ebp+__dreg+ebx*4] +sub [ebp+__areg+8],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 94C8 - 94CF +T4C8: +and ebx,byte 7 +movsx ecx,word[ebp+__areg+ebx*4] +sub [ebp+__areg+8],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 94D0 - 94D7 +T4D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +sub [ebp+__areg+8],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 94D8 - 94DF +T4D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub [ebp+__areg+8],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 94E0 - 94E7 +T4E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+ebx*4],edx +sub [ebp+__areg+8],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 94E8 - 94EF +T4E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +sub [ebp+__areg+8],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 94F0 - 94F7 +T4F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +sub [ebp+__areg+8],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 94F8 +T4F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +sub [ebp+__areg+8],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 94F9 +T4F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +movsx ecx,cx +sub [ebp+__areg+8],ecx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 94FA +T4FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +sub [ebp+__areg+8],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 94FB +T4FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +sub [ebp+__areg+8],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 94FC +T4FC: +movsx ecx,word[esi] +add esi,byte 2 +sub [ebp+__areg+8],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9500 - 9507 +T500: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+8] +sbb al,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+8],al +lahf +seto al +setc [ebp+__xflag] +jnz short ln1886 +or ch,0BFh +and ah,ch +ln1886: +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9508 - 950F +T508: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+8] +dec edx +call readmemorybyte +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +sbb al,bl +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln1887 +or ch,0BFh +and ah,ch +ln1887: +mov ecx,ebx +xor ebx,ebx +call writememorybyte +mov [ebp+__areg+8],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9510 - 9517 +T510: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,[ebp+__dreg+8] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9518 - 951F +T518: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,[ebp+__dreg+8] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9520 - 9527 +T520: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +sub cl,[ebp+__dreg+8] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9528 - 952F +T528: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,[ebp+__dreg+8] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9530 - 9537 +T530: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,[ebp+__dreg+8] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9538 +T538: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +sub cl,[ebp+__dreg+8] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9539 +T539: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +sub cl,[ebp+__dreg+8] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9540 - 9547 +T540: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+8] +sbb ax,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+8],ax +lahf +seto al +setc [ebp+__xflag] +jnz short ln1888 +or ch,0BFh +and ah,ch +ln1888: +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9548 - 954F +T548: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+8] +sub edx,byte 2 +call readmemoryword +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +sbb ax,bx +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln1889 +or ch,0BFh +and ah,ch +ln1889: +mov ecx,ebx +xor ebx,ebx +call writememoryword +mov [ebp+__areg+8],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9550 - 9557 +T550: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,[ebp+__dreg+8] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9558 - 955F +T558: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,[ebp+__dreg+8] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9560 - 9567 +T560: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +sub cx,[ebp+__dreg+8] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9568 - 956F +T568: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,[ebp+__dreg+8] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9570 - 9577 +T570: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,[ebp+__dreg+8] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9578 +T578: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +sub cx,[ebp+__dreg+8] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9579 +T579: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +sub cx,[ebp+__dreg+8] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9580 - 9587 +T580: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+8] +sbb eax,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+8],eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln1890 +or ch,0BFh +and ah,ch +ln1890: +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9588 - 958F +T588: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+8] +sub edx,byte 4 +call readmemorydword +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +sbb eax,ebx +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln1891 +or ch,0BFh +and ah,ch +ln1891: +mov ecx,ebx +xor ebx,ebx +call writememorydword +mov [ebp+__areg+8],edx +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9590 - 9597 +T590: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,[ebp+__dreg+8] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9598 - 959F +T598: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,[ebp+__dreg+8] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 95A0 - 95A7 +T5A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +sub ecx,[ebp+__dreg+8] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 95A8 - 95AF +T5A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,[ebp+__dreg+8] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 95B0 - 95B7 +T5B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,[ebp+__dreg+8] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 95B8 +T5B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +sub ecx,[ebp+__dreg+8] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 95B9 +T5B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +sub ecx,[ebp+__dreg+8] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 95C0 - 95C7 +T5C0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +sub [ebp+__areg+8],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 95C8 - 95CF +T5C8: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +sub [ebp+__areg+8],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 95D0 - 95D7 +T5D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +sub [ebp+__areg+8],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 95D8 - 95DF +T5D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub [ebp+__areg+8],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 95E0 - 95E7 +T5E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +sub [ebp+__areg+8],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 95E8 - 95EF +T5E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub [ebp+__areg+8],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 95F0 - 95F7 +T5F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub [ebp+__areg+8],ecx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 95F8 +T5F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +sub [ebp+__areg+8],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 95F9 +T5F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +sub [ebp+__areg+8],ecx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 95FA +T5FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +sub [ebp+__areg+8],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 95FB +T5FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +sub [ebp+__areg+8],ecx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 95FC +T5FC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +sub [ebp+__areg+8],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9600 - 9607 +T600: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +sub [ebp+__dreg+12],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9610 - 9617 +T610: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub [ebp+__dreg+12],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9618 - 961F +T618: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub [ebp+__dreg+12],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9620 - 9627 +T620: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +sub [ebp+__dreg+12],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9628 - 962F +T628: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub [ebp+__dreg+12],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9630 - 9637 +T630: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub [ebp+__dreg+12],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9638 +T638: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +sub [ebp+__dreg+12],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9639 +T639: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +sub [ebp+__dreg+12],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 963A +T63A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +sub [ebp+__dreg+12],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 963B +T63B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +sub [ebp+__dreg+12],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 963C +T63C: +mov cx,[esi] +add esi,byte 2 +sub [ebp+__dreg+12],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9640 - 9647 +T640: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +sub [ebp+__dreg+12],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9648 - 964F +T648: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +sub [ebp+__dreg+12],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9650 - 9657 +T650: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +sub [ebp+__dreg+12],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9658 - 965F +T658: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub [ebp+__dreg+12],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9660 - 9667 +T660: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +sub [ebp+__dreg+12],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9668 - 966F +T668: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +sub [ebp+__dreg+12],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9670 - 9677 +T670: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +sub [ebp+__dreg+12],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9678 +T678: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +sub [ebp+__dreg+12],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9679 +T679: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +sub [ebp+__dreg+12],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 967A +T67A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +sub [ebp+__dreg+12],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 967B +T67B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +sub [ebp+__dreg+12],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 967C +T67C: +mov cx,[esi] +add esi,byte 2 +sub [ebp+__dreg+12],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9680 - 9687 +T680: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +sub [ebp+__dreg+12],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9688 - 968F +T688: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +sub [ebp+__dreg+12],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9690 - 9697 +T690: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +sub [ebp+__dreg+12],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9698 - 969F +T698: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub [ebp+__dreg+12],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 96A0 - 96A7 +T6A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +sub [ebp+__dreg+12],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 96A8 - 96AF +T6A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub [ebp+__dreg+12],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 96B0 - 96B7 +T6B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub [ebp+__dreg+12],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 96B8 +T6B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +sub [ebp+__dreg+12],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 96B9 +T6B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +sub [ebp+__dreg+12],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 96BA +T6BA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +sub [ebp+__dreg+12],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 96BB +T6BB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +sub [ebp+__dreg+12],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 96BC +T6BC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +sub [ebp+__dreg+12],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 96C0 - 96C7 +T6C0: +and ebx,byte 7 +movsx ecx,word[ebp+__dreg+ebx*4] +sub [ebp+__areg+12],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 96C8 - 96CF +T6C8: +and ebx,byte 7 +movsx ecx,word[ebp+__areg+ebx*4] +sub [ebp+__areg+12],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 96D0 - 96D7 +T6D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +sub [ebp+__areg+12],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 96D8 - 96DF +T6D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub [ebp+__areg+12],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 96E0 - 96E7 +T6E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+ebx*4],edx +sub [ebp+__areg+12],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 96E8 - 96EF +T6E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +sub [ebp+__areg+12],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 96F0 - 96F7 +T6F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +sub [ebp+__areg+12],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 96F8 +T6F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +sub [ebp+__areg+12],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 96F9 +T6F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +movsx ecx,cx +sub [ebp+__areg+12],ecx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 96FA +T6FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +sub [ebp+__areg+12],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 96FB +T6FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +sub [ebp+__areg+12],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 96FC +T6FC: +movsx ecx,word[esi] +add esi,byte 2 +sub [ebp+__areg+12],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9700 - 9707 +T700: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+12] +sbb al,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+12],al +lahf +seto al +setc [ebp+__xflag] +jnz short ln1892 +or ch,0BFh +and ah,ch +ln1892: +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9708 - 970F +T708: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+12] +dec edx +call readmemorybyte +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +sbb al,bl +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln1893 +or ch,0BFh +and ah,ch +ln1893: +mov ecx,ebx +xor ebx,ebx +call writememorybyte +mov [ebp+__areg+12],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9710 - 9717 +T710: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,[ebp+__dreg+12] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9718 - 971F +T718: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,[ebp+__dreg+12] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9720 - 9727 +T720: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +sub cl,[ebp+__dreg+12] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9728 - 972F +T728: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,[ebp+__dreg+12] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9730 - 9737 +T730: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,[ebp+__dreg+12] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9738 +T738: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +sub cl,[ebp+__dreg+12] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9739 +T739: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +sub cl,[ebp+__dreg+12] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9740 - 9747 +T740: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+12] +sbb ax,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+12],ax +lahf +seto al +setc [ebp+__xflag] +jnz short ln1894 +or ch,0BFh +and ah,ch +ln1894: +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9748 - 974F +T748: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+12] +sub edx,byte 2 +call readmemoryword +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +sbb ax,bx +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln1895 +or ch,0BFh +and ah,ch +ln1895: +mov ecx,ebx +xor ebx,ebx +call writememoryword +mov [ebp+__areg+12],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9750 - 9757 +T750: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,[ebp+__dreg+12] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9758 - 975F +T758: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,[ebp+__dreg+12] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9760 - 9767 +T760: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +sub cx,[ebp+__dreg+12] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9768 - 976F +T768: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,[ebp+__dreg+12] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9770 - 9777 +T770: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,[ebp+__dreg+12] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9778 +T778: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +sub cx,[ebp+__dreg+12] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9779 +T779: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +sub cx,[ebp+__dreg+12] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9780 - 9787 +T780: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+12] +sbb eax,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+12],eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln1896 +or ch,0BFh +and ah,ch +ln1896: +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9788 - 978F +T788: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+12] +sub edx,byte 4 +call readmemorydword +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +sbb eax,ebx +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln1897 +or ch,0BFh +and ah,ch +ln1897: +mov ecx,ebx +xor ebx,ebx +call writememorydword +mov [ebp+__areg+12],edx +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9790 - 9797 +T790: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,[ebp+__dreg+12] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9798 - 979F +T798: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,[ebp+__dreg+12] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 97A0 - 97A7 +T7A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +sub ecx,[ebp+__dreg+12] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 97A8 - 97AF +T7A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,[ebp+__dreg+12] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 97B0 - 97B7 +T7B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,[ebp+__dreg+12] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 97B8 +T7B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +sub ecx,[ebp+__dreg+12] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 97B9 +T7B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +sub ecx,[ebp+__dreg+12] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 97C0 - 97C7 +T7C0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +sub [ebp+__areg+12],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 97C8 - 97CF +T7C8: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +sub [ebp+__areg+12],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 97D0 - 97D7 +T7D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +sub [ebp+__areg+12],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 97D8 - 97DF +T7D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub [ebp+__areg+12],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 97E0 - 97E7 +T7E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +sub [ebp+__areg+12],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 97E8 - 97EF +T7E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub [ebp+__areg+12],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 97F0 - 97F7 +T7F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub [ebp+__areg+12],ecx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 97F8 +T7F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +sub [ebp+__areg+12],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 97F9 +T7F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +sub [ebp+__areg+12],ecx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 97FA +T7FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +sub [ebp+__areg+12],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 97FB +T7FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +sub [ebp+__areg+12],ecx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 97FC +T7FC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +sub [ebp+__areg+12],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9800 - 9807 +T800: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +sub [ebp+__dreg+16],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9810 - 9817 +T810: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub [ebp+__dreg+16],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9818 - 981F +T818: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub [ebp+__dreg+16],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9820 - 9827 +T820: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +sub [ebp+__dreg+16],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9828 - 982F +T828: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub [ebp+__dreg+16],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9830 - 9837 +T830: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub [ebp+__dreg+16],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9838 +T838: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +sub [ebp+__dreg+16],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9839 +T839: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +sub [ebp+__dreg+16],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 983A +T83A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +sub [ebp+__dreg+16],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 983B +T83B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +sub [ebp+__dreg+16],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 983C +T83C: +mov cx,[esi] +add esi,byte 2 +sub [ebp+__dreg+16],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9840 - 9847 +T840: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +sub [ebp+__dreg+16],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9848 - 984F +T848: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +sub [ebp+__dreg+16],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9850 - 9857 +T850: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +sub [ebp+__dreg+16],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9858 - 985F +T858: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub [ebp+__dreg+16],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9860 - 9867 +T860: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +sub [ebp+__dreg+16],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9868 - 986F +T868: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +sub [ebp+__dreg+16],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9870 - 9877 +T870: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +sub [ebp+__dreg+16],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9878 +T878: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +sub [ebp+__dreg+16],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9879 +T879: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +sub [ebp+__dreg+16],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 987A +T87A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +sub [ebp+__dreg+16],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 987B +T87B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +sub [ebp+__dreg+16],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 987C +T87C: +mov cx,[esi] +add esi,byte 2 +sub [ebp+__dreg+16],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9880 - 9887 +T880: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +sub [ebp+__dreg+16],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9888 - 988F +T888: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +sub [ebp+__dreg+16],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9890 - 9897 +T890: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +sub [ebp+__dreg+16],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9898 - 989F +T898: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub [ebp+__dreg+16],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 98A0 - 98A7 +T8A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +sub [ebp+__dreg+16],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 98A8 - 98AF +T8A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub [ebp+__dreg+16],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 98B0 - 98B7 +T8B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub [ebp+__dreg+16],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 98B8 +T8B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +sub [ebp+__dreg+16],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 98B9 +T8B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +sub [ebp+__dreg+16],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 98BA +T8BA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +sub [ebp+__dreg+16],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 98BB +T8BB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +sub [ebp+__dreg+16],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 98BC +T8BC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +sub [ebp+__dreg+16],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 98C0 - 98C7 +T8C0: +and ebx,byte 7 +movsx ecx,word[ebp+__dreg+ebx*4] +sub [ebp+__areg+16],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 98C8 - 98CF +T8C8: +and ebx,byte 7 +movsx ecx,word[ebp+__areg+ebx*4] +sub [ebp+__areg+16],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 98D0 - 98D7 +T8D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +sub [ebp+__areg+16],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 98D8 - 98DF +T8D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub [ebp+__areg+16],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 98E0 - 98E7 +T8E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+ebx*4],edx +sub [ebp+__areg+16],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 98E8 - 98EF +T8E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +sub [ebp+__areg+16],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 98F0 - 98F7 +T8F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +sub [ebp+__areg+16],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 98F8 +T8F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +sub [ebp+__areg+16],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 98F9 +T8F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +movsx ecx,cx +sub [ebp+__areg+16],ecx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 98FA +T8FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +sub [ebp+__areg+16],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 98FB +T8FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +sub [ebp+__areg+16],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 98FC +T8FC: +movsx ecx,word[esi] +add esi,byte 2 +sub [ebp+__areg+16],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9900 - 9907 +T900: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+16] +sbb al,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+16],al +lahf +seto al +setc [ebp+__xflag] +jnz short ln1898 +or ch,0BFh +and ah,ch +ln1898: +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9908 - 990F +T908: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+16] +dec edx +call readmemorybyte +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +sbb al,bl +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln1899 +or ch,0BFh +and ah,ch +ln1899: +mov ecx,ebx +xor ebx,ebx +call writememorybyte +mov [ebp+__areg+16],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9910 - 9917 +T910: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,[ebp+__dreg+16] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9918 - 991F +T918: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,[ebp+__dreg+16] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9920 - 9927 +T920: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +sub cl,[ebp+__dreg+16] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9928 - 992F +T928: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,[ebp+__dreg+16] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9930 - 9937 +T930: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,[ebp+__dreg+16] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9938 +T938: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +sub cl,[ebp+__dreg+16] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9939 +T939: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +sub cl,[ebp+__dreg+16] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9940 - 9947 +T940: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+16] +sbb ax,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+16],ax +lahf +seto al +setc [ebp+__xflag] +jnz short ln1900 +or ch,0BFh +and ah,ch +ln1900: +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9948 - 994F +T948: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+16] +sub edx,byte 2 +call readmemoryword +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +sbb ax,bx +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln1901 +or ch,0BFh +and ah,ch +ln1901: +mov ecx,ebx +xor ebx,ebx +call writememoryword +mov [ebp+__areg+16],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9950 - 9957 +T950: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,[ebp+__dreg+16] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9958 - 995F +T958: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,[ebp+__dreg+16] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9960 - 9967 +T960: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +sub cx,[ebp+__dreg+16] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9968 - 996F +T968: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,[ebp+__dreg+16] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9970 - 9977 +T970: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,[ebp+__dreg+16] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9978 +T978: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +sub cx,[ebp+__dreg+16] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9979 +T979: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +sub cx,[ebp+__dreg+16] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9980 - 9987 +T980: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+16] +sbb eax,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+16],eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln1902 +or ch,0BFh +and ah,ch +ln1902: +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9988 - 998F +T988: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+16] +sub edx,byte 4 +call readmemorydword +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +sbb eax,ebx +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln1903 +or ch,0BFh +and ah,ch +ln1903: +mov ecx,ebx +xor ebx,ebx +call writememorydword +mov [ebp+__areg+16],edx +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9990 - 9997 +T990: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,[ebp+__dreg+16] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9998 - 999F +T998: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,[ebp+__dreg+16] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 99A0 - 99A7 +T9A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +sub ecx,[ebp+__dreg+16] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 99A8 - 99AF +T9A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,[ebp+__dreg+16] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 99B0 - 99B7 +T9B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,[ebp+__dreg+16] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 99B8 +T9B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +sub ecx,[ebp+__dreg+16] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 99B9 +T9B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +sub ecx,[ebp+__dreg+16] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 99C0 - 99C7 +T9C0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +sub [ebp+__areg+16],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 99C8 - 99CF +T9C8: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +sub [ebp+__areg+16],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 99D0 - 99D7 +T9D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +sub [ebp+__areg+16],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 99D8 - 99DF +T9D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub [ebp+__areg+16],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 99E0 - 99E7 +T9E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +sub [ebp+__areg+16],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 99E8 - 99EF +T9E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub [ebp+__areg+16],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 99F0 - 99F7 +T9F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub [ebp+__areg+16],ecx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 99F8 +T9F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +sub [ebp+__areg+16],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 99F9 +T9F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +sub [ebp+__areg+16],ecx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 99FA +T9FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +sub [ebp+__areg+16],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 99FB +T9FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +sub [ebp+__areg+16],ecx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 99FC +T9FC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +sub [ebp+__areg+16],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9A00 - 9A07 +TA00: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +sub [ebp+__dreg+20],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9A10 - 9A17 +TA10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub [ebp+__dreg+20],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9A18 - 9A1F +TA18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub [ebp+__dreg+20],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9A20 - 9A27 +TA20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +sub [ebp+__dreg+20],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9A28 - 9A2F +TA28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub [ebp+__dreg+20],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9A30 - 9A37 +TA30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub [ebp+__dreg+20],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9A38 +TA38: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +sub [ebp+__dreg+20],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9A39 +TA39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +sub [ebp+__dreg+20],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9A3A +TA3A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +sub [ebp+__dreg+20],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9A3B +TA3B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +sub [ebp+__dreg+20],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9A3C +TA3C: +mov cx,[esi] +add esi,byte 2 +sub [ebp+__dreg+20],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9A40 - 9A47 +TA40: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +sub [ebp+__dreg+20],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9A48 - 9A4F +TA48: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +sub [ebp+__dreg+20],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9A50 - 9A57 +TA50: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +sub [ebp+__dreg+20],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9A58 - 9A5F +TA58: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub [ebp+__dreg+20],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9A60 - 9A67 +TA60: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +sub [ebp+__dreg+20],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9A68 - 9A6F +TA68: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +sub [ebp+__dreg+20],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9A70 - 9A77 +TA70: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +sub [ebp+__dreg+20],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9A78 +TA78: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +sub [ebp+__dreg+20],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9A79 +TA79: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +sub [ebp+__dreg+20],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9A7A +TA7A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +sub [ebp+__dreg+20],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9A7B +TA7B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +sub [ebp+__dreg+20],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9A7C +TA7C: +mov cx,[esi] +add esi,byte 2 +sub [ebp+__dreg+20],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9A80 - 9A87 +TA80: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +sub [ebp+__dreg+20],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9A88 - 9A8F +TA88: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +sub [ebp+__dreg+20],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9A90 - 9A97 +TA90: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +sub [ebp+__dreg+20],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9A98 - 9A9F +TA98: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub [ebp+__dreg+20],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9AA0 - 9AA7 +TAA0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +sub [ebp+__dreg+20],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9AA8 - 9AAF +TAA8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub [ebp+__dreg+20],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9AB0 - 9AB7 +TAB0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub [ebp+__dreg+20],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9AB8 +TAB8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +sub [ebp+__dreg+20],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9AB9 +TAB9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +sub [ebp+__dreg+20],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9ABA +TABA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +sub [ebp+__dreg+20],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9ABB +TABB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +sub [ebp+__dreg+20],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9ABC +TABC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +sub [ebp+__dreg+20],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9AC0 - 9AC7 +TAC0: +and ebx,byte 7 +movsx ecx,word[ebp+__dreg+ebx*4] +sub [ebp+__areg+20],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9AC8 - 9ACF +TAC8: +and ebx,byte 7 +movsx ecx,word[ebp+__areg+ebx*4] +sub [ebp+__areg+20],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9AD0 - 9AD7 +TAD0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +sub [ebp+__areg+20],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9AD8 - 9ADF +TAD8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub [ebp+__areg+20],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9AE0 - 9AE7 +TAE0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+ebx*4],edx +sub [ebp+__areg+20],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9AE8 - 9AEF +TAE8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +sub [ebp+__areg+20],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9AF0 - 9AF7 +TAF0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +sub [ebp+__areg+20],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9AF8 +TAF8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +sub [ebp+__areg+20],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9AF9 +TAF9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +movsx ecx,cx +sub [ebp+__areg+20],ecx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9AFA +TAFA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +sub [ebp+__areg+20],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9AFB +TAFB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +sub [ebp+__areg+20],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9AFC +TAFC: +movsx ecx,word[esi] +add esi,byte 2 +sub [ebp+__areg+20],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9B00 - 9B07 +TB00: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+20] +sbb al,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+20],al +lahf +seto al +setc [ebp+__xflag] +jnz short ln1904 +or ch,0BFh +and ah,ch +ln1904: +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9B08 - 9B0F +TB08: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+20] +dec edx +call readmemorybyte +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +sbb al,bl +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln1905 +or ch,0BFh +and ah,ch +ln1905: +mov ecx,ebx +xor ebx,ebx +call writememorybyte +mov [ebp+__areg+20],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9B10 - 9B17 +TB10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,[ebp+__dreg+20] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9B18 - 9B1F +TB18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,[ebp+__dreg+20] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9B20 - 9B27 +TB20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +sub cl,[ebp+__dreg+20] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9B28 - 9B2F +TB28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,[ebp+__dreg+20] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9B30 - 9B37 +TB30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,[ebp+__dreg+20] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9B38 +TB38: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +sub cl,[ebp+__dreg+20] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9B39 +TB39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +sub cl,[ebp+__dreg+20] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9B40 - 9B47 +TB40: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+20] +sbb ax,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+20],ax +lahf +seto al +setc [ebp+__xflag] +jnz short ln1906 +or ch,0BFh +and ah,ch +ln1906: +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9B48 - 9B4F +TB48: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+20] +sub edx,byte 2 +call readmemoryword +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +sbb ax,bx +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln1907 +or ch,0BFh +and ah,ch +ln1907: +mov ecx,ebx +xor ebx,ebx +call writememoryword +mov [ebp+__areg+20],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9B50 - 9B57 +TB50: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,[ebp+__dreg+20] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9B58 - 9B5F +TB58: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,[ebp+__dreg+20] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9B60 - 9B67 +TB60: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +sub cx,[ebp+__dreg+20] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9B68 - 9B6F +TB68: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,[ebp+__dreg+20] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9B70 - 9B77 +TB70: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,[ebp+__dreg+20] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9B78 +TB78: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +sub cx,[ebp+__dreg+20] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9B79 +TB79: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +sub cx,[ebp+__dreg+20] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9B80 - 9B87 +TB80: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+20] +sbb eax,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+20],eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln1908 +or ch,0BFh +and ah,ch +ln1908: +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9B88 - 9B8F +TB88: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+20] +sub edx,byte 4 +call readmemorydword +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +sbb eax,ebx +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln1909 +or ch,0BFh +and ah,ch +ln1909: +mov ecx,ebx +xor ebx,ebx +call writememorydword +mov [ebp+__areg+20],edx +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9B90 - 9B97 +TB90: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,[ebp+__dreg+20] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9B98 - 9B9F +TB98: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,[ebp+__dreg+20] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9BA0 - 9BA7 +TBA0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +sub ecx,[ebp+__dreg+20] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9BA8 - 9BAF +TBA8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,[ebp+__dreg+20] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9BB0 - 9BB7 +TBB0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,[ebp+__dreg+20] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9BB8 +TBB8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +sub ecx,[ebp+__dreg+20] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9BB9 +TBB9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +sub ecx,[ebp+__dreg+20] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9BC0 - 9BC7 +TBC0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +sub [ebp+__areg+20],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9BC8 - 9BCF +TBC8: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +sub [ebp+__areg+20],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9BD0 - 9BD7 +TBD0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +sub [ebp+__areg+20],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9BD8 - 9BDF +TBD8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub [ebp+__areg+20],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9BE0 - 9BE7 +TBE0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +sub [ebp+__areg+20],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9BE8 - 9BEF +TBE8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub [ebp+__areg+20],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9BF0 - 9BF7 +TBF0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub [ebp+__areg+20],ecx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9BF8 +TBF8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +sub [ebp+__areg+20],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9BF9 +TBF9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +sub [ebp+__areg+20],ecx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9BFA +TBFA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +sub [ebp+__areg+20],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9BFB +TBFB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +sub [ebp+__areg+20],ecx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9BFC +TBFC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +sub [ebp+__areg+20],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9C00 - 9C07 +TC00: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +sub [ebp+__dreg+24],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9C10 - 9C17 +TC10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub [ebp+__dreg+24],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9C18 - 9C1F +TC18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub [ebp+__dreg+24],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9C20 - 9C27 +TC20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +sub [ebp+__dreg+24],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9C28 - 9C2F +TC28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub [ebp+__dreg+24],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9C30 - 9C37 +TC30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub [ebp+__dreg+24],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9C38 +TC38: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +sub [ebp+__dreg+24],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9C39 +TC39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +sub [ebp+__dreg+24],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9C3A +TC3A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +sub [ebp+__dreg+24],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9C3B +TC3B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +sub [ebp+__dreg+24],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9C3C +TC3C: +mov cx,[esi] +add esi,byte 2 +sub [ebp+__dreg+24],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9C40 - 9C47 +TC40: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +sub [ebp+__dreg+24],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9C48 - 9C4F +TC48: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +sub [ebp+__dreg+24],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9C50 - 9C57 +TC50: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +sub [ebp+__dreg+24],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9C58 - 9C5F +TC58: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub [ebp+__dreg+24],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9C60 - 9C67 +TC60: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +sub [ebp+__dreg+24],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9C68 - 9C6F +TC68: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +sub [ebp+__dreg+24],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9C70 - 9C77 +TC70: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +sub [ebp+__dreg+24],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9C78 +TC78: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +sub [ebp+__dreg+24],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9C79 +TC79: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +sub [ebp+__dreg+24],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9C7A +TC7A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +sub [ebp+__dreg+24],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9C7B +TC7B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +sub [ebp+__dreg+24],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9C7C +TC7C: +mov cx,[esi] +add esi,byte 2 +sub [ebp+__dreg+24],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9C80 - 9C87 +TC80: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +sub [ebp+__dreg+24],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9C88 - 9C8F +TC88: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +sub [ebp+__dreg+24],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9C90 - 9C97 +TC90: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +sub [ebp+__dreg+24],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9C98 - 9C9F +TC98: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub [ebp+__dreg+24],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9CA0 - 9CA7 +TCA0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +sub [ebp+__dreg+24],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9CA8 - 9CAF +TCA8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub [ebp+__dreg+24],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9CB0 - 9CB7 +TCB0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub [ebp+__dreg+24],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9CB8 +TCB8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +sub [ebp+__dreg+24],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9CB9 +TCB9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +sub [ebp+__dreg+24],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9CBA +TCBA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +sub [ebp+__dreg+24],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9CBB +TCBB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +sub [ebp+__dreg+24],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9CBC +TCBC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +sub [ebp+__dreg+24],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9CC0 - 9CC7 +TCC0: +and ebx,byte 7 +movsx ecx,word[ebp+__dreg+ebx*4] +sub [ebp+__areg+24],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9CC8 - 9CCF +TCC8: +and ebx,byte 7 +movsx ecx,word[ebp+__areg+ebx*4] +sub [ebp+__areg+24],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9CD0 - 9CD7 +TCD0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +sub [ebp+__areg+24],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9CD8 - 9CDF +TCD8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub [ebp+__areg+24],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9CE0 - 9CE7 +TCE0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+ebx*4],edx +sub [ebp+__areg+24],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9CE8 - 9CEF +TCE8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +sub [ebp+__areg+24],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9CF0 - 9CF7 +TCF0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +sub [ebp+__areg+24],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9CF8 +TCF8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +sub [ebp+__areg+24],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9CF9 +TCF9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +movsx ecx,cx +sub [ebp+__areg+24],ecx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9CFA +TCFA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +sub [ebp+__areg+24],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9CFB +TCFB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +sub [ebp+__areg+24],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9CFC +TCFC: +movsx ecx,word[esi] +add esi,byte 2 +sub [ebp+__areg+24],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9D00 - 9D07 +TD00: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+24] +sbb al,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+24],al +lahf +seto al +setc [ebp+__xflag] +jnz short ln1910 +or ch,0BFh +and ah,ch +ln1910: +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9D08 - 9D0F +TD08: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+24] +dec edx +call readmemorybyte +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +sbb al,bl +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln1911 +or ch,0BFh +and ah,ch +ln1911: +mov ecx,ebx +xor ebx,ebx +call writememorybyte +mov [ebp+__areg+24],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9D10 - 9D17 +TD10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,[ebp+__dreg+24] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9D18 - 9D1F +TD18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,[ebp+__dreg+24] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9D20 - 9D27 +TD20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +sub cl,[ebp+__dreg+24] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9D28 - 9D2F +TD28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,[ebp+__dreg+24] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9D30 - 9D37 +TD30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,[ebp+__dreg+24] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9D38 +TD38: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +sub cl,[ebp+__dreg+24] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9D39 +TD39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +sub cl,[ebp+__dreg+24] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9D40 - 9D47 +TD40: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+24] +sbb ax,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+24],ax +lahf +seto al +setc [ebp+__xflag] +jnz short ln1912 +or ch,0BFh +and ah,ch +ln1912: +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9D48 - 9D4F +TD48: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+24] +sub edx,byte 2 +call readmemoryword +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +sbb ax,bx +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln1913 +or ch,0BFh +and ah,ch +ln1913: +mov ecx,ebx +xor ebx,ebx +call writememoryword +mov [ebp+__areg+24],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9D50 - 9D57 +TD50: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,[ebp+__dreg+24] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9D58 - 9D5F +TD58: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,[ebp+__dreg+24] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9D60 - 9D67 +TD60: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +sub cx,[ebp+__dreg+24] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9D68 - 9D6F +TD68: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,[ebp+__dreg+24] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9D70 - 9D77 +TD70: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,[ebp+__dreg+24] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9D78 +TD78: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +sub cx,[ebp+__dreg+24] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9D79 +TD79: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +sub cx,[ebp+__dreg+24] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9D80 - 9D87 +TD80: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+24] +sbb eax,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+24],eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln1914 +or ch,0BFh +and ah,ch +ln1914: +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9D88 - 9D8F +TD88: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+24] +sub edx,byte 4 +call readmemorydword +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +sbb eax,ebx +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln1915 +or ch,0BFh +and ah,ch +ln1915: +mov ecx,ebx +xor ebx,ebx +call writememorydword +mov [ebp+__areg+24],edx +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9D90 - 9D97 +TD90: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,[ebp+__dreg+24] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9D98 - 9D9F +TD98: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,[ebp+__dreg+24] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9DA0 - 9DA7 +TDA0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +sub ecx,[ebp+__dreg+24] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9DA8 - 9DAF +TDA8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,[ebp+__dreg+24] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9DB0 - 9DB7 +TDB0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,[ebp+__dreg+24] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9DB8 +TDB8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +sub ecx,[ebp+__dreg+24] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9DB9 +TDB9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +sub ecx,[ebp+__dreg+24] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9DC0 - 9DC7 +TDC0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +sub [ebp+__areg+24],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9DC8 - 9DCF +TDC8: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +sub [ebp+__areg+24],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9DD0 - 9DD7 +TDD0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +sub [ebp+__areg+24],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9DD8 - 9DDF +TDD8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub [ebp+__areg+24],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9DE0 - 9DE7 +TDE0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +sub [ebp+__areg+24],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9DE8 - 9DEF +TDE8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub [ebp+__areg+24],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9DF0 - 9DF7 +TDF0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub [ebp+__areg+24],ecx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9DF8 +TDF8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +sub [ebp+__areg+24],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9DF9 +TDF9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +sub [ebp+__areg+24],ecx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9DFA +TDFA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +sub [ebp+__areg+24],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9DFB +TDFB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +sub [ebp+__areg+24],ecx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9DFC +TDFC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +sub [ebp+__areg+24],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9E00 - 9E07 +TE00: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +sub [ebp+__dreg+28],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9E10 - 9E17 +TE10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub [ebp+__dreg+28],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9E18 - 9E1F +TE18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub [ebp+__dreg+28],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9E20 - 9E27 +TE20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +sub [ebp+__dreg+28],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9E28 - 9E2F +TE28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub [ebp+__dreg+28],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9E30 - 9E37 +TE30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub [ebp+__dreg+28],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9E38 +TE38: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +sub [ebp+__dreg+28],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9E39 +TE39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +sub [ebp+__dreg+28],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9E3A +TE3A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +sub [ebp+__dreg+28],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9E3B +TE3B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +sub [ebp+__dreg+28],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9E3C +TE3C: +mov cx,[esi] +add esi,byte 2 +sub [ebp+__dreg+28],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9E40 - 9E47 +TE40: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +sub [ebp+__dreg+28],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9E48 - 9E4F +TE48: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +sub [ebp+__dreg+28],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9E50 - 9E57 +TE50: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +sub [ebp+__dreg+28],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9E58 - 9E5F +TE58: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub [ebp+__dreg+28],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9E60 - 9E67 +TE60: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +sub [ebp+__dreg+28],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9E68 - 9E6F +TE68: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +sub [ebp+__dreg+28],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9E70 - 9E77 +TE70: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +sub [ebp+__dreg+28],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9E78 +TE78: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +sub [ebp+__dreg+28],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9E79 +TE79: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +sub [ebp+__dreg+28],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9E7A +TE7A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +sub [ebp+__dreg+28],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9E7B +TE7B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +sub [ebp+__dreg+28],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9E7C +TE7C: +mov cx,[esi] +add esi,byte 2 +sub [ebp+__dreg+28],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9E80 - 9E87 +TE80: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +sub [ebp+__dreg+28],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9E88 - 9E8F +TE88: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +sub [ebp+__dreg+28],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9E90 - 9E97 +TE90: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +sub [ebp+__dreg+28],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9E98 - 9E9F +TE98: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub [ebp+__dreg+28],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9EA0 - 9EA7 +TEA0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +sub [ebp+__dreg+28],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9EA8 - 9EAF +TEA8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub [ebp+__dreg+28],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9EB0 - 9EB7 +TEB0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub [ebp+__dreg+28],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9EB8 +TEB8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +sub [ebp+__dreg+28],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9EB9 +TEB9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +sub [ebp+__dreg+28],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9EBA +TEBA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +sub [ebp+__dreg+28],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9EBB +TEBB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +sub [ebp+__dreg+28],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9EBC +TEBC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +sub [ebp+__dreg+28],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9EC0 - 9EC7 +TEC0: +and ebx,byte 7 +movsx ecx,word[ebp+__dreg+ebx*4] +sub [ebp+__areg+28],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9EC8 - 9ECF +TEC8: +and ebx,byte 7 +movsx ecx,word[ebp+__areg+ebx*4] +sub [ebp+__areg+28],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9ED0 - 9ED7 +TED0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +sub [ebp+__areg+28],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9ED8 - 9EDF +TED8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub [ebp+__areg+28],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9EE0 - 9EE7 +TEE0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+ebx*4],edx +sub [ebp+__areg+28],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9EE8 - 9EEF +TEE8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +sub [ebp+__areg+28],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9EF0 - 9EF7 +TEF0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +sub [ebp+__areg+28],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9EF8 +TEF8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +sub [ebp+__areg+28],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9EF9 +TEF9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +movsx ecx,cx +sub [ebp+__areg+28],ecx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9EFA +TEFA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +sub [ebp+__areg+28],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9EFB +TEFB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +sub [ebp+__areg+28],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9EFC +TEFC: +movsx ecx,word[esi] +add esi,byte 2 +sub [ebp+__areg+28],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9F00 - 9F07 +TF00: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+28] +sbb al,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+28],al +lahf +seto al +setc [ebp+__xflag] +jnz short ln1916 +or ch,0BFh +and ah,ch +ln1916: +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9F08 - 9F0F +TF08: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+28] +sub edx,byte 2 +call readmemorybyte +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +sbb al,bl +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln1917 +or ch,0BFh +and ah,ch +ln1917: +mov ecx,ebx +xor ebx,ebx +call writememorybyte +mov [ebp+__areg+28],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9F10 - 9F17 +TF10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,[ebp+__dreg+28] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9F18 - 9F1F +TF18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,[ebp+__dreg+28] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9F20 - 9F27 +TF20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +sub cl,[ebp+__dreg+28] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9F28 - 9F2F +TF28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,[ebp+__dreg+28] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9F30 - 9F37 +TF30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +sub cl,[ebp+__dreg+28] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9F38 +TF38: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +sub cl,[ebp+__dreg+28] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9F39 +TF39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +sub cl,[ebp+__dreg+28] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9F40 - 9F47 +TF40: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+28] +sbb ax,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+28],ax +lahf +seto al +setc [ebp+__xflag] +jnz short ln1918 +or ch,0BFh +and ah,ch +ln1918: +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9F48 - 9F4F +TF48: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+28] +sub edx,byte 2 +call readmemoryword +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +sbb ax,bx +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln1919 +or ch,0BFh +and ah,ch +ln1919: +mov ecx,ebx +xor ebx,ebx +call writememoryword +mov [ebp+__areg+28],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9F50 - 9F57 +TF50: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,[ebp+__dreg+28] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9F58 - 9F5F +TF58: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,[ebp+__dreg+28] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9F60 - 9F67 +TF60: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +sub cx,[ebp+__dreg+28] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9F68 - 9F6F +TF68: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,[ebp+__dreg+28] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9F70 - 9F77 +TF70: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +sub cx,[ebp+__dreg+28] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9F78 +TF78: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +sub cx,[ebp+__dreg+28] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9F79 +TF79: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +sub cx,[ebp+__dreg+28] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9F80 - 9F87 +TF80: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+28] +sbb eax,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+28],eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln1920 +or ch,0BFh +and ah,ch +ln1920: +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9F88 - 9F8F +TF88: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+28] +sub edx,byte 4 +call readmemorydword +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +sbb eax,ebx +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln1921 +or ch,0BFh +and ah,ch +ln1921: +mov ecx,ebx +xor ebx,ebx +call writememorydword +mov [ebp+__areg+28],edx +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9F90 - 9F97 +TF90: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,[ebp+__dreg+28] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9F98 - 9F9F +TF98: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,[ebp+__dreg+28] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9FA0 - 9FA7 +TFA0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +sub ecx,[ebp+__dreg+28] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9FA8 - 9FAF +TFA8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,[ebp+__dreg+28] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9FB0 - 9FB7 +TFB0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub ecx,[ebp+__dreg+28] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9FB8 +TFB8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +sub ecx,[ebp+__dreg+28] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9FB9 +TFB9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +sub ecx,[ebp+__dreg+28] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9FC0 - 9FC7 +TFC0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +sub [ebp+__areg+28],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9FC8 - 9FCF +TFC8: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +sub [ebp+__areg+28],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9FD0 - 9FD7 +TFD0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +sub [ebp+__areg+28],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9FD8 - 9FDF +TFD8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub [ebp+__areg+28],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9FE0 - 9FE7 +TFE0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +sub [ebp+__areg+28],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9FE8 - 9FEF +TFE8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub [ebp+__areg+28],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes 9FF0 - 9FF7 +TFF0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +sub [ebp+__areg+28],ecx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9FF8 +TFF8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +sub [ebp+__areg+28],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9FF9 +TFF9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +sub [ebp+__areg+28],ecx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9FFA +TFFA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +sub [ebp+__areg+28],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9FFB +TFFB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +sub [ebp+__areg+28],ecx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode 9FFC +TFFC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +sub [ebp+__areg+28],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes A000 - AFFF +U000: +sub esi,byte 2 +mov edx,28h +call group_1_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln1922 +cmp esi,[ebp+__fetch_region_end] +jbe short ln1923 +ln1922: +call basefunction +ln1923: +add esi,[ebp+__io_fetchbase] +sub edi,byte 34 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B000 - B007 +V000: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +cmp [ebp+__dreg+0],cl +lahf +seto al +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B010 - B017 +V010: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp [ebp+__dreg+0],cl +lahf +seto al +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B018 - B01F +V018: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__dreg+0],cl +lahf +seto al +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B020 - B027 +V020: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__dreg+0],cl +lahf +seto al +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B028 - B02F +V028: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp [ebp+__dreg+0],cl +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B030 - B037 +V030: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp [ebp+__dreg+0],cl +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B038 +V038: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +cmp [ebp+__dreg+0],cl +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B039 +V039: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +cmp [ebp+__dreg+0],cl +lahf +seto al +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B03A +V03A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +cmp [ebp+__dreg+0],cl +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B03B +V03B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +cmp [ebp+__dreg+0],cl +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B03C +V03C: +mov cx,[esi] +add esi,byte 2 +cmp [ebp+__dreg+0],cl +lahf +seto al +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B040 - B047 +V040: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +cmp [ebp+__dreg+0],cx +lahf +seto al +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B048 - B04F +V048: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +cmp [ebp+__dreg+0],cx +lahf +seto al +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B050 - B057 +V050: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +cmp [ebp+__dreg+0],cx +lahf +seto al +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B058 - B05F +V058: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__dreg+0],cx +lahf +seto al +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B060 - B067 +V060: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__dreg+0],cx +lahf +seto al +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B068 - B06F +V068: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +cmp [ebp+__dreg+0],cx +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B070 - B077 +V070: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +cmp [ebp+__dreg+0],cx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B078 +V078: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +cmp [ebp+__dreg+0],cx +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B079 +V079: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +cmp [ebp+__dreg+0],cx +lahf +seto al +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B07A +V07A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +cmp [ebp+__dreg+0],cx +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B07B +V07B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +cmp [ebp+__dreg+0],cx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B07C +V07C: +mov cx,[esi] +add esi,byte 2 +cmp [ebp+__dreg+0],cx +lahf +seto al +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B080 - B087 +V080: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +cmp [ebp+__dreg+0],ecx +lahf +seto al +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B088 - B08F +V088: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +cmp [ebp+__dreg+0],ecx +lahf +seto al +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B090 - B097 +V090: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +cmp [ebp+__dreg+0],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B098 - B09F +V098: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__dreg+0],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B0A0 - B0A7 +V0A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__dreg+0],ecx +lahf +seto al +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B0A8 - B0AF +V0A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +cmp [ebp+__dreg+0],ecx +lahf +seto al +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B0B0 - B0B7 +V0B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +cmp [ebp+__dreg+0],ecx +lahf +seto al +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B0B8 +V0B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +cmp [ebp+__dreg+0],ecx +lahf +seto al +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B0B9 +V0B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +cmp [ebp+__dreg+0],ecx +lahf +seto al +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B0BA +V0BA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +cmp [ebp+__dreg+0],ecx +lahf +seto al +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B0BB +V0BB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +cmp [ebp+__dreg+0],ecx +lahf +seto al +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B0BC +V0BC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +cmp [ebp+__dreg+0],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B0C0 - B0C7 +V0C0: +and ebx,byte 7 +movsx ecx,word[ebp+__dreg+ebx*4] +cmp [ebp+__areg+0],ecx +lahf +seto al +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B0C8 - B0CF +V0C8: +and ebx,byte 7 +movsx ecx,word[ebp+__areg+ebx*4] +cmp [ebp+__areg+0],ecx +lahf +seto al +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B0D0 - B0D7 +V0D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +cmp [ebp+__areg+0],ecx +lahf +seto al +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B0D8 - B0DF +V0D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__areg+0],ecx +lahf +seto al +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B0E0 - B0E7 +V0E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__areg+0],ecx +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B0E8 - B0EF +V0E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +cmp [ebp+__areg+0],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B0F0 - B0F7 +V0F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +cmp [ebp+__areg+0],ecx +lahf +seto al +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B0F8 +V0F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +cmp [ebp+__areg+0],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B0F9 +V0F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +movsx ecx,cx +cmp [ebp+__areg+0],ecx +lahf +seto al +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B0FA +V0FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +cmp [ebp+__areg+0],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B0FB +V0FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +cmp [ebp+__areg+0],ecx +lahf +seto al +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B0FC +V0FC: +movsx ecx,word[esi] +add esi,byte 2 +cmp [ebp+__areg+0],ecx +lahf +seto al +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B100 - B107 +V100: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +xor cl,[ebp+__dreg+0] +lahf +mov al,0 +mov [ebp+__dreg+ebx*4],cl +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B108 - B10F +V108: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +mov eax,ecx +mov edx,[ebp+__areg+0] +call readmemorybyte +inc edx +mov [ebp+__areg+0],edx +cmp cl,al +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B110 - B117 +V110: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xor cl,[ebp+__dreg+0] +lahf +mov al,0 +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B118 - B11F +V118: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xor cl,[ebp+__dreg+0] +lahf +mov al,0 +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B120 - B127 +V120: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +xor cl,[ebp+__dreg+0] +lahf +mov al,0 +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B128 - B12F +V128: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xor cl,[ebp+__dreg+0] +lahf +mov al,0 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B130 - B137 +V130: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xor cl,[ebp+__dreg+0] +lahf +mov al,0 +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B138 +V138: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +xor cl,[ebp+__dreg+0] +lahf +mov al,0 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B139 +V139: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +xor cl,[ebp+__dreg+0] +lahf +mov al,0 +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B140 - B147 +V140: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +xor cx,[ebp+__dreg+0] +lahf +mov al,0 +mov [ebp+__dreg+ebx*4],cx +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B148 - B14F +V148: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov eax,ecx +mov edx,[ebp+__areg+0] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+0],edx +cmp cx,ax +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B150 - B157 +V150: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +xor cx,[ebp+__dreg+0] +lahf +mov al,0 +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B158 - B15F +V158: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +xor cx,[ebp+__dreg+0] +lahf +mov al,0 +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B160 - B167 +V160: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +xor cx,[ebp+__dreg+0] +lahf +mov al,0 +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B168 - B16F +V168: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +xor cx,[ebp+__dreg+0] +lahf +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B170 - B177 +V170: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +xor cx,[ebp+__dreg+0] +lahf +mov al,0 +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B178 +V178: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +xor cx,[ebp+__dreg+0] +lahf +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B179 +V179: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +xor cx,[ebp+__dreg+0] +lahf +mov al,0 +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B180 - B187 +V180: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +xor ecx,[ebp+__dreg+0] +lahf +mov al,0 +mov [ebp+__dreg+ebx*4],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B188 - B18F +V188: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +mov eax,ecx +mov edx,[ebp+__areg+0] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+0],edx +cmp ecx,eax +lahf +seto al +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B190 - B197 +V190: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +xor ecx,[ebp+__dreg+0] +lahf +mov al,0 +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B198 - B19F +V198: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +xor ecx,[ebp+__dreg+0] +lahf +mov al,0 +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B1A0 - B1A7 +V1A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +xor ecx,[ebp+__dreg+0] +lahf +mov al,0 +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B1A8 - B1AF +V1A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +xor ecx,[ebp+__dreg+0] +lahf +mov al,0 +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B1B0 - B1B7 +V1B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +xor ecx,[ebp+__dreg+0] +lahf +mov al,0 +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B1B8 +V1B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +xor ecx,[ebp+__dreg+0] +lahf +mov al,0 +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B1B9 +V1B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +xor ecx,[ebp+__dreg+0] +lahf +mov al,0 +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B1C0 - B1C7 +V1C0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +cmp [ebp+__areg+0],ecx +lahf +seto al +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B1C8 - B1CF +V1C8: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +cmp [ebp+__areg+0],ecx +lahf +seto al +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B1D0 - B1D7 +V1D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +cmp [ebp+__areg+0],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B1D8 - B1DF +V1D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__areg+0],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B1E0 - B1E7 +V1E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__areg+0],ecx +lahf +seto al +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B1E8 - B1EF +V1E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +cmp [ebp+__areg+0],ecx +lahf +seto al +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B1F0 - B1F7 +V1F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +cmp [ebp+__areg+0],ecx +lahf +seto al +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B1F8 +V1F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +cmp [ebp+__areg+0],ecx +lahf +seto al +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B1F9 +V1F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +cmp [ebp+__areg+0],ecx +lahf +seto al +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B1FA +V1FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +cmp [ebp+__areg+0],ecx +lahf +seto al +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B1FB +V1FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +cmp [ebp+__areg+0],ecx +lahf +seto al +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B1FC +V1FC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +cmp [ebp+__areg+0],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B200 - B207 +V200: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +cmp [ebp+__dreg+4],cl +lahf +seto al +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B210 - B217 +V210: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp [ebp+__dreg+4],cl +lahf +seto al +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B218 - B21F +V218: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__dreg+4],cl +lahf +seto al +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B220 - B227 +V220: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__dreg+4],cl +lahf +seto al +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B228 - B22F +V228: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp [ebp+__dreg+4],cl +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B230 - B237 +V230: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp [ebp+__dreg+4],cl +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B238 +V238: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +cmp [ebp+__dreg+4],cl +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B239 +V239: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +cmp [ebp+__dreg+4],cl +lahf +seto al +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B23A +V23A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +cmp [ebp+__dreg+4],cl +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B23B +V23B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +cmp [ebp+__dreg+4],cl +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B23C +V23C: +mov cx,[esi] +add esi,byte 2 +cmp [ebp+__dreg+4],cl +lahf +seto al +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B240 - B247 +V240: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +cmp [ebp+__dreg+4],cx +lahf +seto al +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B248 - B24F +V248: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +cmp [ebp+__dreg+4],cx +lahf +seto al +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B250 - B257 +V250: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +cmp [ebp+__dreg+4],cx +lahf +seto al +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B258 - B25F +V258: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__dreg+4],cx +lahf +seto al +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B260 - B267 +V260: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__dreg+4],cx +lahf +seto al +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B268 - B26F +V268: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +cmp [ebp+__dreg+4],cx +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B270 - B277 +V270: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +cmp [ebp+__dreg+4],cx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B278 +V278: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +cmp [ebp+__dreg+4],cx +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B279 +V279: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +cmp [ebp+__dreg+4],cx +lahf +seto al +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B27A +V27A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +cmp [ebp+__dreg+4],cx +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B27B +V27B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +cmp [ebp+__dreg+4],cx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B27C +V27C: +mov cx,[esi] +add esi,byte 2 +cmp [ebp+__dreg+4],cx +lahf +seto al +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B280 - B287 +V280: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +cmp [ebp+__dreg+4],ecx +lahf +seto al +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B288 - B28F +V288: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +cmp [ebp+__dreg+4],ecx +lahf +seto al +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B290 - B297 +V290: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +cmp [ebp+__dreg+4],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B298 - B29F +V298: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__dreg+4],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B2A0 - B2A7 +V2A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__dreg+4],ecx +lahf +seto al +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B2A8 - B2AF +V2A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +cmp [ebp+__dreg+4],ecx +lahf +seto al +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B2B0 - B2B7 +V2B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +cmp [ebp+__dreg+4],ecx +lahf +seto al +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B2B8 +V2B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +cmp [ebp+__dreg+4],ecx +lahf +seto al +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B2B9 +V2B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +cmp [ebp+__dreg+4],ecx +lahf +seto al +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B2BA +V2BA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +cmp [ebp+__dreg+4],ecx +lahf +seto al +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B2BB +V2BB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +cmp [ebp+__dreg+4],ecx +lahf +seto al +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B2BC +V2BC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +cmp [ebp+__dreg+4],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B2C0 - B2C7 +V2C0: +and ebx,byte 7 +movsx ecx,word[ebp+__dreg+ebx*4] +cmp [ebp+__areg+4],ecx +lahf +seto al +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B2C8 - B2CF +V2C8: +and ebx,byte 7 +movsx ecx,word[ebp+__areg+ebx*4] +cmp [ebp+__areg+4],ecx +lahf +seto al +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B2D0 - B2D7 +V2D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +cmp [ebp+__areg+4],ecx +lahf +seto al +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B2D8 - B2DF +V2D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__areg+4],ecx +lahf +seto al +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B2E0 - B2E7 +V2E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__areg+4],ecx +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B2E8 - B2EF +V2E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +cmp [ebp+__areg+4],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B2F0 - B2F7 +V2F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +cmp [ebp+__areg+4],ecx +lahf +seto al +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B2F8 +V2F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +cmp [ebp+__areg+4],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B2F9 +V2F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +movsx ecx,cx +cmp [ebp+__areg+4],ecx +lahf +seto al +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B2FA +V2FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +cmp [ebp+__areg+4],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B2FB +V2FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +cmp [ebp+__areg+4],ecx +lahf +seto al +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B2FC +V2FC: +movsx ecx,word[esi] +add esi,byte 2 +cmp [ebp+__areg+4],ecx +lahf +seto al +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B300 - B307 +V300: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +xor cl,[ebp+__dreg+4] +lahf +mov al,0 +mov [ebp+__dreg+ebx*4],cl +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B308 - B30F +V308: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +mov eax,ecx +mov edx,[ebp+__areg+4] +call readmemorybyte +inc edx +mov [ebp+__areg+4],edx +cmp cl,al +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B310 - B317 +V310: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xor cl,[ebp+__dreg+4] +lahf +mov al,0 +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B318 - B31F +V318: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xor cl,[ebp+__dreg+4] +lahf +mov al,0 +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B320 - B327 +V320: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +xor cl,[ebp+__dreg+4] +lahf +mov al,0 +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B328 - B32F +V328: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xor cl,[ebp+__dreg+4] +lahf +mov al,0 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B330 - B337 +V330: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xor cl,[ebp+__dreg+4] +lahf +mov al,0 +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B338 +V338: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +xor cl,[ebp+__dreg+4] +lahf +mov al,0 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B339 +V339: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +xor cl,[ebp+__dreg+4] +lahf +mov al,0 +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B340 - B347 +V340: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +xor cx,[ebp+__dreg+4] +lahf +mov al,0 +mov [ebp+__dreg+ebx*4],cx +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B348 - B34F +V348: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov eax,ecx +mov edx,[ebp+__areg+4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+4],edx +cmp cx,ax +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B350 - B357 +V350: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +xor cx,[ebp+__dreg+4] +lahf +mov al,0 +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B358 - B35F +V358: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +xor cx,[ebp+__dreg+4] +lahf +mov al,0 +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B360 - B367 +V360: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +xor cx,[ebp+__dreg+4] +lahf +mov al,0 +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B368 - B36F +V368: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +xor cx,[ebp+__dreg+4] +lahf +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B370 - B377 +V370: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +xor cx,[ebp+__dreg+4] +lahf +mov al,0 +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B378 +V378: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +xor cx,[ebp+__dreg+4] +lahf +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B379 +V379: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +xor cx,[ebp+__dreg+4] +lahf +mov al,0 +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B380 - B387 +V380: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +xor ecx,[ebp+__dreg+4] +lahf +mov al,0 +mov [ebp+__dreg+ebx*4],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B388 - B38F +V388: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +mov eax,ecx +mov edx,[ebp+__areg+4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+4],edx +cmp ecx,eax +lahf +seto al +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B390 - B397 +V390: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +xor ecx,[ebp+__dreg+4] +lahf +mov al,0 +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B398 - B39F +V398: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +xor ecx,[ebp+__dreg+4] +lahf +mov al,0 +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B3A0 - B3A7 +V3A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +xor ecx,[ebp+__dreg+4] +lahf +mov al,0 +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B3A8 - B3AF +V3A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +xor ecx,[ebp+__dreg+4] +lahf +mov al,0 +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B3B0 - B3B7 +V3B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +xor ecx,[ebp+__dreg+4] +lahf +mov al,0 +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B3B8 +V3B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +xor ecx,[ebp+__dreg+4] +lahf +mov al,0 +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B3B9 +V3B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +xor ecx,[ebp+__dreg+4] +lahf +mov al,0 +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B3C0 - B3C7 +V3C0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +cmp [ebp+__areg+4],ecx +lahf +seto al +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B3C8 - B3CF +V3C8: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +cmp [ebp+__areg+4],ecx +lahf +seto al +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B3D0 - B3D7 +V3D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +cmp [ebp+__areg+4],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B3D8 - B3DF +V3D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__areg+4],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B3E0 - B3E7 +V3E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__areg+4],ecx +lahf +seto al +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B3E8 - B3EF +V3E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +cmp [ebp+__areg+4],ecx +lahf +seto al +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B3F0 - B3F7 +V3F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +cmp [ebp+__areg+4],ecx +lahf +seto al +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B3F8 +V3F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +cmp [ebp+__areg+4],ecx +lahf +seto al +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B3F9 +V3F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +cmp [ebp+__areg+4],ecx +lahf +seto al +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B3FA +V3FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +cmp [ebp+__areg+4],ecx +lahf +seto al +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B3FB +V3FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +cmp [ebp+__areg+4],ecx +lahf +seto al +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B3FC +V3FC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +cmp [ebp+__areg+4],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B400 - B407 +V400: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +cmp [ebp+__dreg+8],cl +lahf +seto al +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B410 - B417 +V410: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp [ebp+__dreg+8],cl +lahf +seto al +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B418 - B41F +V418: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__dreg+8],cl +lahf +seto al +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B420 - B427 +V420: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__dreg+8],cl +lahf +seto al +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B428 - B42F +V428: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp [ebp+__dreg+8],cl +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B430 - B437 +V430: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp [ebp+__dreg+8],cl +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B438 +V438: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +cmp [ebp+__dreg+8],cl +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B439 +V439: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +cmp [ebp+__dreg+8],cl +lahf +seto al +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B43A +V43A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +cmp [ebp+__dreg+8],cl +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B43B +V43B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +cmp [ebp+__dreg+8],cl +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B43C +V43C: +mov cx,[esi] +add esi,byte 2 +cmp [ebp+__dreg+8],cl +lahf +seto al +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B440 - B447 +V440: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +cmp [ebp+__dreg+8],cx +lahf +seto al +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B448 - B44F +V448: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +cmp [ebp+__dreg+8],cx +lahf +seto al +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B450 - B457 +V450: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +cmp [ebp+__dreg+8],cx +lahf +seto al +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B458 - B45F +V458: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__dreg+8],cx +lahf +seto al +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B460 - B467 +V460: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__dreg+8],cx +lahf +seto al +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B468 - B46F +V468: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +cmp [ebp+__dreg+8],cx +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B470 - B477 +V470: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +cmp [ebp+__dreg+8],cx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B478 +V478: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +cmp [ebp+__dreg+8],cx +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B479 +V479: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +cmp [ebp+__dreg+8],cx +lahf +seto al +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B47A +V47A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +cmp [ebp+__dreg+8],cx +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B47B +V47B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +cmp [ebp+__dreg+8],cx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B47C +V47C: +mov cx,[esi] +add esi,byte 2 +cmp [ebp+__dreg+8],cx +lahf +seto al +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B480 - B487 +V480: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +cmp [ebp+__dreg+8],ecx +lahf +seto al +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B488 - B48F +V488: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +cmp [ebp+__dreg+8],ecx +lahf +seto al +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B490 - B497 +V490: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +cmp [ebp+__dreg+8],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B498 - B49F +V498: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__dreg+8],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B4A0 - B4A7 +V4A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__dreg+8],ecx +lahf +seto al +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B4A8 - B4AF +V4A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +cmp [ebp+__dreg+8],ecx +lahf +seto al +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B4B0 - B4B7 +V4B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +cmp [ebp+__dreg+8],ecx +lahf +seto al +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B4B8 +V4B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +cmp [ebp+__dreg+8],ecx +lahf +seto al +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B4B9 +V4B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +cmp [ebp+__dreg+8],ecx +lahf +seto al +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B4BA +V4BA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +cmp [ebp+__dreg+8],ecx +lahf +seto al +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B4BB +V4BB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +cmp [ebp+__dreg+8],ecx +lahf +seto al +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B4BC +V4BC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +cmp [ebp+__dreg+8],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B4C0 - B4C7 +V4C0: +and ebx,byte 7 +movsx ecx,word[ebp+__dreg+ebx*4] +cmp [ebp+__areg+8],ecx +lahf +seto al +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B4C8 - B4CF +V4C8: +and ebx,byte 7 +movsx ecx,word[ebp+__areg+ebx*4] +cmp [ebp+__areg+8],ecx +lahf +seto al +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B4D0 - B4D7 +V4D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +cmp [ebp+__areg+8],ecx +lahf +seto al +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B4D8 - B4DF +V4D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__areg+8],ecx +lahf +seto al +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B4E0 - B4E7 +V4E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__areg+8],ecx +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B4E8 - B4EF +V4E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +cmp [ebp+__areg+8],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B4F0 - B4F7 +V4F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +cmp [ebp+__areg+8],ecx +lahf +seto al +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B4F8 +V4F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +cmp [ebp+__areg+8],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B4F9 +V4F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +movsx ecx,cx +cmp [ebp+__areg+8],ecx +lahf +seto al +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B4FA +V4FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +cmp [ebp+__areg+8],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B4FB +V4FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +cmp [ebp+__areg+8],ecx +lahf +seto al +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B4FC +V4FC: +movsx ecx,word[esi] +add esi,byte 2 +cmp [ebp+__areg+8],ecx +lahf +seto al +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B500 - B507 +V500: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +xor cl,[ebp+__dreg+8] +lahf +mov al,0 +mov [ebp+__dreg+ebx*4],cl +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B508 - B50F +V508: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +mov eax,ecx +mov edx,[ebp+__areg+8] +call readmemorybyte +inc edx +mov [ebp+__areg+8],edx +cmp cl,al +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B510 - B517 +V510: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xor cl,[ebp+__dreg+8] +lahf +mov al,0 +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B518 - B51F +V518: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xor cl,[ebp+__dreg+8] +lahf +mov al,0 +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B520 - B527 +V520: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +xor cl,[ebp+__dreg+8] +lahf +mov al,0 +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B528 - B52F +V528: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xor cl,[ebp+__dreg+8] +lahf +mov al,0 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B530 - B537 +V530: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xor cl,[ebp+__dreg+8] +lahf +mov al,0 +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B538 +V538: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +xor cl,[ebp+__dreg+8] +lahf +mov al,0 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B539 +V539: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +xor cl,[ebp+__dreg+8] +lahf +mov al,0 +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B540 - B547 +V540: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +xor cx,[ebp+__dreg+8] +lahf +mov al,0 +mov [ebp+__dreg+ebx*4],cx +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B548 - B54F +V548: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov eax,ecx +mov edx,[ebp+__areg+8] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+8],edx +cmp cx,ax +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B550 - B557 +V550: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +xor cx,[ebp+__dreg+8] +lahf +mov al,0 +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B558 - B55F +V558: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +xor cx,[ebp+__dreg+8] +lahf +mov al,0 +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B560 - B567 +V560: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +xor cx,[ebp+__dreg+8] +lahf +mov al,0 +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B568 - B56F +V568: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +xor cx,[ebp+__dreg+8] +lahf +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B570 - B577 +V570: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +xor cx,[ebp+__dreg+8] +lahf +mov al,0 +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B578 +V578: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +xor cx,[ebp+__dreg+8] +lahf +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B579 +V579: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +xor cx,[ebp+__dreg+8] +lahf +mov al,0 +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B580 - B587 +V580: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +xor ecx,[ebp+__dreg+8] +lahf +mov al,0 +mov [ebp+__dreg+ebx*4],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B588 - B58F +V588: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +mov eax,ecx +mov edx,[ebp+__areg+8] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+8],edx +cmp ecx,eax +lahf +seto al +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B590 - B597 +V590: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +xor ecx,[ebp+__dreg+8] +lahf +mov al,0 +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B598 - B59F +V598: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +xor ecx,[ebp+__dreg+8] +lahf +mov al,0 +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B5A0 - B5A7 +V5A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +xor ecx,[ebp+__dreg+8] +lahf +mov al,0 +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B5A8 - B5AF +V5A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +xor ecx,[ebp+__dreg+8] +lahf +mov al,0 +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B5B0 - B5B7 +V5B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +xor ecx,[ebp+__dreg+8] +lahf +mov al,0 +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B5B8 +V5B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +xor ecx,[ebp+__dreg+8] +lahf +mov al,0 +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B5B9 +V5B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +xor ecx,[ebp+__dreg+8] +lahf +mov al,0 +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B5C0 - B5C7 +V5C0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +cmp [ebp+__areg+8],ecx +lahf +seto al +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B5C8 - B5CF +V5C8: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +cmp [ebp+__areg+8],ecx +lahf +seto al +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B5D0 - B5D7 +V5D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +cmp [ebp+__areg+8],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B5D8 - B5DF +V5D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__areg+8],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B5E0 - B5E7 +V5E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__areg+8],ecx +lahf +seto al +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B5E8 - B5EF +V5E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +cmp [ebp+__areg+8],ecx +lahf +seto al +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B5F0 - B5F7 +V5F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +cmp [ebp+__areg+8],ecx +lahf +seto al +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B5F8 +V5F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +cmp [ebp+__areg+8],ecx +lahf +seto al +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B5F9 +V5F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +cmp [ebp+__areg+8],ecx +lahf +seto al +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B5FA +V5FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +cmp [ebp+__areg+8],ecx +lahf +seto al +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B5FB +V5FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +cmp [ebp+__areg+8],ecx +lahf +seto al +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B5FC +V5FC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +cmp [ebp+__areg+8],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B600 - B607 +V600: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +cmp [ebp+__dreg+12],cl +lahf +seto al +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B610 - B617 +V610: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp [ebp+__dreg+12],cl +lahf +seto al +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B618 - B61F +V618: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__dreg+12],cl +lahf +seto al +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B620 - B627 +V620: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__dreg+12],cl +lahf +seto al +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B628 - B62F +V628: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp [ebp+__dreg+12],cl +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B630 - B637 +V630: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp [ebp+__dreg+12],cl +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B638 +V638: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +cmp [ebp+__dreg+12],cl +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B639 +V639: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +cmp [ebp+__dreg+12],cl +lahf +seto al +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B63A +V63A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +cmp [ebp+__dreg+12],cl +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B63B +V63B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +cmp [ebp+__dreg+12],cl +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B63C +V63C: +mov cx,[esi] +add esi,byte 2 +cmp [ebp+__dreg+12],cl +lahf +seto al +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B640 - B647 +V640: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +cmp [ebp+__dreg+12],cx +lahf +seto al +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B648 - B64F +V648: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +cmp [ebp+__dreg+12],cx +lahf +seto al +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B650 - B657 +V650: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +cmp [ebp+__dreg+12],cx +lahf +seto al +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B658 - B65F +V658: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__dreg+12],cx +lahf +seto al +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B660 - B667 +V660: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__dreg+12],cx +lahf +seto al +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B668 - B66F +V668: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +cmp [ebp+__dreg+12],cx +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B670 - B677 +V670: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +cmp [ebp+__dreg+12],cx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B678 +V678: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +cmp [ebp+__dreg+12],cx +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B679 +V679: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +cmp [ebp+__dreg+12],cx +lahf +seto al +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B67A +V67A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +cmp [ebp+__dreg+12],cx +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B67B +V67B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +cmp [ebp+__dreg+12],cx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B67C +V67C: +mov cx,[esi] +add esi,byte 2 +cmp [ebp+__dreg+12],cx +lahf +seto al +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B680 - B687 +V680: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +cmp [ebp+__dreg+12],ecx +lahf +seto al +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B688 - B68F +V688: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +cmp [ebp+__dreg+12],ecx +lahf +seto al +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B690 - B697 +V690: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +cmp [ebp+__dreg+12],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B698 - B69F +V698: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__dreg+12],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B6A0 - B6A7 +V6A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__dreg+12],ecx +lahf +seto al +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B6A8 - B6AF +V6A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +cmp [ebp+__dreg+12],ecx +lahf +seto al +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B6B0 - B6B7 +V6B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +cmp [ebp+__dreg+12],ecx +lahf +seto al +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B6B8 +V6B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +cmp [ebp+__dreg+12],ecx +lahf +seto al +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B6B9 +V6B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +cmp [ebp+__dreg+12],ecx +lahf +seto al +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B6BA +V6BA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +cmp [ebp+__dreg+12],ecx +lahf +seto al +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B6BB +V6BB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +cmp [ebp+__dreg+12],ecx +lahf +seto al +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B6BC +V6BC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +cmp [ebp+__dreg+12],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B6C0 - B6C7 +V6C0: +and ebx,byte 7 +movsx ecx,word[ebp+__dreg+ebx*4] +cmp [ebp+__areg+12],ecx +lahf +seto al +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B6C8 - B6CF +V6C8: +and ebx,byte 7 +movsx ecx,word[ebp+__areg+ebx*4] +cmp [ebp+__areg+12],ecx +lahf +seto al +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B6D0 - B6D7 +V6D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +cmp [ebp+__areg+12],ecx +lahf +seto al +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B6D8 - B6DF +V6D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__areg+12],ecx +lahf +seto al +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B6E0 - B6E7 +V6E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__areg+12],ecx +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B6E8 - B6EF +V6E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +cmp [ebp+__areg+12],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B6F0 - B6F7 +V6F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +cmp [ebp+__areg+12],ecx +lahf +seto al +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B6F8 +V6F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +cmp [ebp+__areg+12],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B6F9 +V6F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +movsx ecx,cx +cmp [ebp+__areg+12],ecx +lahf +seto al +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B6FA +V6FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +cmp [ebp+__areg+12],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B6FB +V6FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +cmp [ebp+__areg+12],ecx +lahf +seto al +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B6FC +V6FC: +movsx ecx,word[esi] +add esi,byte 2 +cmp [ebp+__areg+12],ecx +lahf +seto al +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B700 - B707 +V700: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +xor cl,[ebp+__dreg+12] +lahf +mov al,0 +mov [ebp+__dreg+ebx*4],cl +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B708 - B70F +V708: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +mov eax,ecx +mov edx,[ebp+__areg+12] +call readmemorybyte +inc edx +mov [ebp+__areg+12],edx +cmp cl,al +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B710 - B717 +V710: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xor cl,[ebp+__dreg+12] +lahf +mov al,0 +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B718 - B71F +V718: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xor cl,[ebp+__dreg+12] +lahf +mov al,0 +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B720 - B727 +V720: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +xor cl,[ebp+__dreg+12] +lahf +mov al,0 +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B728 - B72F +V728: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xor cl,[ebp+__dreg+12] +lahf +mov al,0 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B730 - B737 +V730: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xor cl,[ebp+__dreg+12] +lahf +mov al,0 +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B738 +V738: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +xor cl,[ebp+__dreg+12] +lahf +mov al,0 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B739 +V739: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +xor cl,[ebp+__dreg+12] +lahf +mov al,0 +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B740 - B747 +V740: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +xor cx,[ebp+__dreg+12] +lahf +mov al,0 +mov [ebp+__dreg+ebx*4],cx +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B748 - B74F +V748: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov eax,ecx +mov edx,[ebp+__areg+12] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+12],edx +cmp cx,ax +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B750 - B757 +V750: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +xor cx,[ebp+__dreg+12] +lahf +mov al,0 +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B758 - B75F +V758: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +xor cx,[ebp+__dreg+12] +lahf +mov al,0 +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B760 - B767 +V760: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +xor cx,[ebp+__dreg+12] +lahf +mov al,0 +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B768 - B76F +V768: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +xor cx,[ebp+__dreg+12] +lahf +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B770 - B777 +V770: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +xor cx,[ebp+__dreg+12] +lahf +mov al,0 +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B778 +V778: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +xor cx,[ebp+__dreg+12] +lahf +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B779 +V779: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +xor cx,[ebp+__dreg+12] +lahf +mov al,0 +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B780 - B787 +V780: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +xor ecx,[ebp+__dreg+12] +lahf +mov al,0 +mov [ebp+__dreg+ebx*4],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B788 - B78F +V788: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +mov eax,ecx +mov edx,[ebp+__areg+12] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+12],edx +cmp ecx,eax +lahf +seto al +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B790 - B797 +V790: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +xor ecx,[ebp+__dreg+12] +lahf +mov al,0 +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B798 - B79F +V798: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +xor ecx,[ebp+__dreg+12] +lahf +mov al,0 +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B7A0 - B7A7 +V7A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +xor ecx,[ebp+__dreg+12] +lahf +mov al,0 +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B7A8 - B7AF +V7A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +xor ecx,[ebp+__dreg+12] +lahf +mov al,0 +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B7B0 - B7B7 +V7B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +xor ecx,[ebp+__dreg+12] +lahf +mov al,0 +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B7B8 +V7B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +xor ecx,[ebp+__dreg+12] +lahf +mov al,0 +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B7B9 +V7B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +xor ecx,[ebp+__dreg+12] +lahf +mov al,0 +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B7C0 - B7C7 +V7C0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +cmp [ebp+__areg+12],ecx +lahf +seto al +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B7C8 - B7CF +V7C8: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +cmp [ebp+__areg+12],ecx +lahf +seto al +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B7D0 - B7D7 +V7D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +cmp [ebp+__areg+12],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B7D8 - B7DF +V7D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__areg+12],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B7E0 - B7E7 +V7E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__areg+12],ecx +lahf +seto al +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B7E8 - B7EF +V7E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +cmp [ebp+__areg+12],ecx +lahf +seto al +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B7F0 - B7F7 +V7F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +cmp [ebp+__areg+12],ecx +lahf +seto al +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B7F8 +V7F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +cmp [ebp+__areg+12],ecx +lahf +seto al +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B7F9 +V7F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +cmp [ebp+__areg+12],ecx +lahf +seto al +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B7FA +V7FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +cmp [ebp+__areg+12],ecx +lahf +seto al +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B7FB +V7FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +cmp [ebp+__areg+12],ecx +lahf +seto al +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B7FC +V7FC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +cmp [ebp+__areg+12],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B800 - B807 +V800: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +cmp [ebp+__dreg+16],cl +lahf +seto al +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B810 - B817 +V810: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp [ebp+__dreg+16],cl +lahf +seto al +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B818 - B81F +V818: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__dreg+16],cl +lahf +seto al +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B820 - B827 +V820: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__dreg+16],cl +lahf +seto al +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B828 - B82F +V828: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp [ebp+__dreg+16],cl +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B830 - B837 +V830: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp [ebp+__dreg+16],cl +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B838 +V838: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +cmp [ebp+__dreg+16],cl +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B839 +V839: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +cmp [ebp+__dreg+16],cl +lahf +seto al +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B83A +V83A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +cmp [ebp+__dreg+16],cl +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B83B +V83B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +cmp [ebp+__dreg+16],cl +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B83C +V83C: +mov cx,[esi] +add esi,byte 2 +cmp [ebp+__dreg+16],cl +lahf +seto al +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B840 - B847 +V840: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +cmp [ebp+__dreg+16],cx +lahf +seto al +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B848 - B84F +V848: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +cmp [ebp+__dreg+16],cx +lahf +seto al +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B850 - B857 +V850: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +cmp [ebp+__dreg+16],cx +lahf +seto al +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B858 - B85F +V858: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__dreg+16],cx +lahf +seto al +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B860 - B867 +V860: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__dreg+16],cx +lahf +seto al +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B868 - B86F +V868: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +cmp [ebp+__dreg+16],cx +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B870 - B877 +V870: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +cmp [ebp+__dreg+16],cx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B878 +V878: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +cmp [ebp+__dreg+16],cx +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B879 +V879: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +cmp [ebp+__dreg+16],cx +lahf +seto al +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B87A +V87A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +cmp [ebp+__dreg+16],cx +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B87B +V87B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +cmp [ebp+__dreg+16],cx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B87C +V87C: +mov cx,[esi] +add esi,byte 2 +cmp [ebp+__dreg+16],cx +lahf +seto al +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B880 - B887 +V880: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +cmp [ebp+__dreg+16],ecx +lahf +seto al +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B888 - B88F +V888: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +cmp [ebp+__dreg+16],ecx +lahf +seto al +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B890 - B897 +V890: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +cmp [ebp+__dreg+16],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B898 - B89F +V898: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__dreg+16],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B8A0 - B8A7 +V8A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__dreg+16],ecx +lahf +seto al +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B8A8 - B8AF +V8A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +cmp [ebp+__dreg+16],ecx +lahf +seto al +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B8B0 - B8B7 +V8B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +cmp [ebp+__dreg+16],ecx +lahf +seto al +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B8B8 +V8B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +cmp [ebp+__dreg+16],ecx +lahf +seto al +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B8B9 +V8B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +cmp [ebp+__dreg+16],ecx +lahf +seto al +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B8BA +V8BA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +cmp [ebp+__dreg+16],ecx +lahf +seto al +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B8BB +V8BB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +cmp [ebp+__dreg+16],ecx +lahf +seto al +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B8BC +V8BC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +cmp [ebp+__dreg+16],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B8C0 - B8C7 +V8C0: +and ebx,byte 7 +movsx ecx,word[ebp+__dreg+ebx*4] +cmp [ebp+__areg+16],ecx +lahf +seto al +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B8C8 - B8CF +V8C8: +and ebx,byte 7 +movsx ecx,word[ebp+__areg+ebx*4] +cmp [ebp+__areg+16],ecx +lahf +seto al +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B8D0 - B8D7 +V8D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +cmp [ebp+__areg+16],ecx +lahf +seto al +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B8D8 - B8DF +V8D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__areg+16],ecx +lahf +seto al +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B8E0 - B8E7 +V8E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__areg+16],ecx +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B8E8 - B8EF +V8E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +cmp [ebp+__areg+16],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B8F0 - B8F7 +V8F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +cmp [ebp+__areg+16],ecx +lahf +seto al +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B8F8 +V8F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +cmp [ebp+__areg+16],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B8F9 +V8F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +movsx ecx,cx +cmp [ebp+__areg+16],ecx +lahf +seto al +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B8FA +V8FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +cmp [ebp+__areg+16],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B8FB +V8FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +cmp [ebp+__areg+16],ecx +lahf +seto al +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B8FC +V8FC: +movsx ecx,word[esi] +add esi,byte 2 +cmp [ebp+__areg+16],ecx +lahf +seto al +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B900 - B907 +V900: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +xor cl,[ebp+__dreg+16] +lahf +mov al,0 +mov [ebp+__dreg+ebx*4],cl +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B908 - B90F +V908: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +mov eax,ecx +mov edx,[ebp+__areg+16] +call readmemorybyte +inc edx +mov [ebp+__areg+16],edx +cmp cl,al +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B910 - B917 +V910: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xor cl,[ebp+__dreg+16] +lahf +mov al,0 +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B918 - B91F +V918: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xor cl,[ebp+__dreg+16] +lahf +mov al,0 +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B920 - B927 +V920: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +xor cl,[ebp+__dreg+16] +lahf +mov al,0 +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B928 - B92F +V928: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xor cl,[ebp+__dreg+16] +lahf +mov al,0 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B930 - B937 +V930: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xor cl,[ebp+__dreg+16] +lahf +mov al,0 +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B938 +V938: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +xor cl,[ebp+__dreg+16] +lahf +mov al,0 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B939 +V939: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +xor cl,[ebp+__dreg+16] +lahf +mov al,0 +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B940 - B947 +V940: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +xor cx,[ebp+__dreg+16] +lahf +mov al,0 +mov [ebp+__dreg+ebx*4],cx +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B948 - B94F +V948: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov eax,ecx +mov edx,[ebp+__areg+16] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+16],edx +cmp cx,ax +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B950 - B957 +V950: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +xor cx,[ebp+__dreg+16] +lahf +mov al,0 +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B958 - B95F +V958: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +xor cx,[ebp+__dreg+16] +lahf +mov al,0 +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B960 - B967 +V960: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +xor cx,[ebp+__dreg+16] +lahf +mov al,0 +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B968 - B96F +V968: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +xor cx,[ebp+__dreg+16] +lahf +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B970 - B977 +V970: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +xor cx,[ebp+__dreg+16] +lahf +mov al,0 +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B978 +V978: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +xor cx,[ebp+__dreg+16] +lahf +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B979 +V979: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +xor cx,[ebp+__dreg+16] +lahf +mov al,0 +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B980 - B987 +V980: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +xor ecx,[ebp+__dreg+16] +lahf +mov al,0 +mov [ebp+__dreg+ebx*4],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B988 - B98F +V988: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +mov eax,ecx +mov edx,[ebp+__areg+16] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+16],edx +cmp ecx,eax +lahf +seto al +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B990 - B997 +V990: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +xor ecx,[ebp+__dreg+16] +lahf +mov al,0 +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B998 - B99F +V998: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +xor ecx,[ebp+__dreg+16] +lahf +mov al,0 +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B9A0 - B9A7 +V9A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +xor ecx,[ebp+__dreg+16] +lahf +mov al,0 +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B9A8 - B9AF +V9A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +xor ecx,[ebp+__dreg+16] +lahf +mov al,0 +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B9B0 - B9B7 +V9B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +xor ecx,[ebp+__dreg+16] +lahf +mov al,0 +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B9B8 +V9B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +xor ecx,[ebp+__dreg+16] +lahf +mov al,0 +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B9B9 +V9B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +xor ecx,[ebp+__dreg+16] +lahf +mov al,0 +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B9C0 - B9C7 +V9C0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +cmp [ebp+__areg+16],ecx +lahf +seto al +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B9C8 - B9CF +V9C8: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +cmp [ebp+__areg+16],ecx +lahf +seto al +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B9D0 - B9D7 +V9D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +cmp [ebp+__areg+16],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B9D8 - B9DF +V9D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__areg+16],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B9E0 - B9E7 +V9E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__areg+16],ecx +lahf +seto al +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B9E8 - B9EF +V9E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +cmp [ebp+__areg+16],ecx +lahf +seto al +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes B9F0 - B9F7 +V9F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +cmp [ebp+__areg+16],ecx +lahf +seto al +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B9F8 +V9F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +cmp [ebp+__areg+16],ecx +lahf +seto al +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B9F9 +V9F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +cmp [ebp+__areg+16],ecx +lahf +seto al +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B9FA +V9FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +cmp [ebp+__areg+16],ecx +lahf +seto al +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B9FB +V9FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +cmp [ebp+__areg+16],ecx +lahf +seto al +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode B9FC +V9FC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +cmp [ebp+__areg+16],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BA00 - BA07 +VA00: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +cmp [ebp+__dreg+20],cl +lahf +seto al +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BA10 - BA17 +VA10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp [ebp+__dreg+20],cl +lahf +seto al +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BA18 - BA1F +VA18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__dreg+20],cl +lahf +seto al +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BA20 - BA27 +VA20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__dreg+20],cl +lahf +seto al +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BA28 - BA2F +VA28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp [ebp+__dreg+20],cl +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BA30 - BA37 +VA30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp [ebp+__dreg+20],cl +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BA38 +VA38: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +cmp [ebp+__dreg+20],cl +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BA39 +VA39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +cmp [ebp+__dreg+20],cl +lahf +seto al +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BA3A +VA3A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +cmp [ebp+__dreg+20],cl +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BA3B +VA3B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +cmp [ebp+__dreg+20],cl +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BA3C +VA3C: +mov cx,[esi] +add esi,byte 2 +cmp [ebp+__dreg+20],cl +lahf +seto al +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BA40 - BA47 +VA40: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +cmp [ebp+__dreg+20],cx +lahf +seto al +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BA48 - BA4F +VA48: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +cmp [ebp+__dreg+20],cx +lahf +seto al +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BA50 - BA57 +VA50: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +cmp [ebp+__dreg+20],cx +lahf +seto al +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BA58 - BA5F +VA58: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__dreg+20],cx +lahf +seto al +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BA60 - BA67 +VA60: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__dreg+20],cx +lahf +seto al +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BA68 - BA6F +VA68: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +cmp [ebp+__dreg+20],cx +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BA70 - BA77 +VA70: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +cmp [ebp+__dreg+20],cx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BA78 +VA78: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +cmp [ebp+__dreg+20],cx +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BA79 +VA79: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +cmp [ebp+__dreg+20],cx +lahf +seto al +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BA7A +VA7A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +cmp [ebp+__dreg+20],cx +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BA7B +VA7B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +cmp [ebp+__dreg+20],cx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BA7C +VA7C: +mov cx,[esi] +add esi,byte 2 +cmp [ebp+__dreg+20],cx +lahf +seto al +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BA80 - BA87 +VA80: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +cmp [ebp+__dreg+20],ecx +lahf +seto al +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BA88 - BA8F +VA88: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +cmp [ebp+__dreg+20],ecx +lahf +seto al +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BA90 - BA97 +VA90: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +cmp [ebp+__dreg+20],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BA98 - BA9F +VA98: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__dreg+20],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BAA0 - BAA7 +VAA0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__dreg+20],ecx +lahf +seto al +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BAA8 - BAAF +VAA8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +cmp [ebp+__dreg+20],ecx +lahf +seto al +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BAB0 - BAB7 +VAB0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +cmp [ebp+__dreg+20],ecx +lahf +seto al +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BAB8 +VAB8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +cmp [ebp+__dreg+20],ecx +lahf +seto al +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BAB9 +VAB9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +cmp [ebp+__dreg+20],ecx +lahf +seto al +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BABA +VABA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +cmp [ebp+__dreg+20],ecx +lahf +seto al +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BABB +VABB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +cmp [ebp+__dreg+20],ecx +lahf +seto al +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BABC +VABC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +cmp [ebp+__dreg+20],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BAC0 - BAC7 +VAC0: +and ebx,byte 7 +movsx ecx,word[ebp+__dreg+ebx*4] +cmp [ebp+__areg+20],ecx +lahf +seto al +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BAC8 - BACF +VAC8: +and ebx,byte 7 +movsx ecx,word[ebp+__areg+ebx*4] +cmp [ebp+__areg+20],ecx +lahf +seto al +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BAD0 - BAD7 +VAD0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +cmp [ebp+__areg+20],ecx +lahf +seto al +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BAD8 - BADF +VAD8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__areg+20],ecx +lahf +seto al +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BAE0 - BAE7 +VAE0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__areg+20],ecx +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BAE8 - BAEF +VAE8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +cmp [ebp+__areg+20],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BAF0 - BAF7 +VAF0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +cmp [ebp+__areg+20],ecx +lahf +seto al +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BAF8 +VAF8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +cmp [ebp+__areg+20],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BAF9 +VAF9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +movsx ecx,cx +cmp [ebp+__areg+20],ecx +lahf +seto al +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BAFA +VAFA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +cmp [ebp+__areg+20],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BAFB +VAFB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +cmp [ebp+__areg+20],ecx +lahf +seto al +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BAFC +VAFC: +movsx ecx,word[esi] +add esi,byte 2 +cmp [ebp+__areg+20],ecx +lahf +seto al +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BB00 - BB07 +VB00: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +xor cl,[ebp+__dreg+20] +lahf +mov al,0 +mov [ebp+__dreg+ebx*4],cl +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BB08 - BB0F +VB08: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +mov eax,ecx +mov edx,[ebp+__areg+20] +call readmemorybyte +inc edx +mov [ebp+__areg+20],edx +cmp cl,al +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BB10 - BB17 +VB10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xor cl,[ebp+__dreg+20] +lahf +mov al,0 +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BB18 - BB1F +VB18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xor cl,[ebp+__dreg+20] +lahf +mov al,0 +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BB20 - BB27 +VB20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +xor cl,[ebp+__dreg+20] +lahf +mov al,0 +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BB28 - BB2F +VB28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xor cl,[ebp+__dreg+20] +lahf +mov al,0 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BB30 - BB37 +VB30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xor cl,[ebp+__dreg+20] +lahf +mov al,0 +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BB38 +VB38: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +xor cl,[ebp+__dreg+20] +lahf +mov al,0 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BB39 +VB39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +xor cl,[ebp+__dreg+20] +lahf +mov al,0 +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BB40 - BB47 +VB40: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +xor cx,[ebp+__dreg+20] +lahf +mov al,0 +mov [ebp+__dreg+ebx*4],cx +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BB48 - BB4F +VB48: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov eax,ecx +mov edx,[ebp+__areg+20] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+20],edx +cmp cx,ax +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BB50 - BB57 +VB50: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +xor cx,[ebp+__dreg+20] +lahf +mov al,0 +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BB58 - BB5F +VB58: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +xor cx,[ebp+__dreg+20] +lahf +mov al,0 +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BB60 - BB67 +VB60: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +xor cx,[ebp+__dreg+20] +lahf +mov al,0 +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BB68 - BB6F +VB68: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +xor cx,[ebp+__dreg+20] +lahf +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BB70 - BB77 +VB70: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +xor cx,[ebp+__dreg+20] +lahf +mov al,0 +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BB78 +VB78: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +xor cx,[ebp+__dreg+20] +lahf +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BB79 +VB79: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +xor cx,[ebp+__dreg+20] +lahf +mov al,0 +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BB80 - BB87 +VB80: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +xor ecx,[ebp+__dreg+20] +lahf +mov al,0 +mov [ebp+__dreg+ebx*4],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BB88 - BB8F +VB88: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +mov eax,ecx +mov edx,[ebp+__areg+20] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+20],edx +cmp ecx,eax +lahf +seto al +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BB90 - BB97 +VB90: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +xor ecx,[ebp+__dreg+20] +lahf +mov al,0 +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BB98 - BB9F +VB98: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +xor ecx,[ebp+__dreg+20] +lahf +mov al,0 +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BBA0 - BBA7 +VBA0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +xor ecx,[ebp+__dreg+20] +lahf +mov al,0 +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BBA8 - BBAF +VBA8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +xor ecx,[ebp+__dreg+20] +lahf +mov al,0 +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BBB0 - BBB7 +VBB0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +xor ecx,[ebp+__dreg+20] +lahf +mov al,0 +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BBB8 +VBB8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +xor ecx,[ebp+__dreg+20] +lahf +mov al,0 +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BBB9 +VBB9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +xor ecx,[ebp+__dreg+20] +lahf +mov al,0 +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BBC0 - BBC7 +VBC0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +cmp [ebp+__areg+20],ecx +lahf +seto al +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BBC8 - BBCF +VBC8: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +cmp [ebp+__areg+20],ecx +lahf +seto al +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BBD0 - BBD7 +VBD0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +cmp [ebp+__areg+20],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BBD8 - BBDF +VBD8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__areg+20],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BBE0 - BBE7 +VBE0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__areg+20],ecx +lahf +seto al +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BBE8 - BBEF +VBE8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +cmp [ebp+__areg+20],ecx +lahf +seto al +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BBF0 - BBF7 +VBF0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +cmp [ebp+__areg+20],ecx +lahf +seto al +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BBF8 +VBF8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +cmp [ebp+__areg+20],ecx +lahf +seto al +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BBF9 +VBF9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +cmp [ebp+__areg+20],ecx +lahf +seto al +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BBFA +VBFA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +cmp [ebp+__areg+20],ecx +lahf +seto al +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BBFB +VBFB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +cmp [ebp+__areg+20],ecx +lahf +seto al +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BBFC +VBFC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +cmp [ebp+__areg+20],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BC00 - BC07 +VC00: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +cmp [ebp+__dreg+24],cl +lahf +seto al +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BC10 - BC17 +VC10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp [ebp+__dreg+24],cl +lahf +seto al +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BC18 - BC1F +VC18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__dreg+24],cl +lahf +seto al +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BC20 - BC27 +VC20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__dreg+24],cl +lahf +seto al +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BC28 - BC2F +VC28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp [ebp+__dreg+24],cl +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BC30 - BC37 +VC30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp [ebp+__dreg+24],cl +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BC38 +VC38: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +cmp [ebp+__dreg+24],cl +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BC39 +VC39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +cmp [ebp+__dreg+24],cl +lahf +seto al +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BC3A +VC3A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +cmp [ebp+__dreg+24],cl +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BC3B +VC3B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +cmp [ebp+__dreg+24],cl +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BC3C +VC3C: +mov cx,[esi] +add esi,byte 2 +cmp [ebp+__dreg+24],cl +lahf +seto al +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BC40 - BC47 +VC40: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +cmp [ebp+__dreg+24],cx +lahf +seto al +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BC48 - BC4F +VC48: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +cmp [ebp+__dreg+24],cx +lahf +seto al +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BC50 - BC57 +VC50: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +cmp [ebp+__dreg+24],cx +lahf +seto al +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BC58 - BC5F +VC58: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__dreg+24],cx +lahf +seto al +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BC60 - BC67 +VC60: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__dreg+24],cx +lahf +seto al +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BC68 - BC6F +VC68: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +cmp [ebp+__dreg+24],cx +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BC70 - BC77 +VC70: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +cmp [ebp+__dreg+24],cx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BC78 +VC78: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +cmp [ebp+__dreg+24],cx +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BC79 +VC79: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +cmp [ebp+__dreg+24],cx +lahf +seto al +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BC7A +VC7A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +cmp [ebp+__dreg+24],cx +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BC7B +VC7B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +cmp [ebp+__dreg+24],cx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BC7C +VC7C: +mov cx,[esi] +add esi,byte 2 +cmp [ebp+__dreg+24],cx +lahf +seto al +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BC80 - BC87 +VC80: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +cmp [ebp+__dreg+24],ecx +lahf +seto al +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BC88 - BC8F +VC88: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +cmp [ebp+__dreg+24],ecx +lahf +seto al +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BC90 - BC97 +VC90: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +cmp [ebp+__dreg+24],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BC98 - BC9F +VC98: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__dreg+24],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BCA0 - BCA7 +VCA0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__dreg+24],ecx +lahf +seto al +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BCA8 - BCAF +VCA8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +cmp [ebp+__dreg+24],ecx +lahf +seto al +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BCB0 - BCB7 +VCB0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +cmp [ebp+__dreg+24],ecx +lahf +seto al +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BCB8 +VCB8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +cmp [ebp+__dreg+24],ecx +lahf +seto al +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BCB9 +VCB9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +cmp [ebp+__dreg+24],ecx +lahf +seto al +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BCBA +VCBA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +cmp [ebp+__dreg+24],ecx +lahf +seto al +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BCBB +VCBB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +cmp [ebp+__dreg+24],ecx +lahf +seto al +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BCBC +VCBC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +cmp [ebp+__dreg+24],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BCC0 - BCC7 +VCC0: +and ebx,byte 7 +movsx ecx,word[ebp+__dreg+ebx*4] +cmp [ebp+__areg+24],ecx +lahf +seto al +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BCC8 - BCCF +VCC8: +and ebx,byte 7 +movsx ecx,word[ebp+__areg+ebx*4] +cmp [ebp+__areg+24],ecx +lahf +seto al +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BCD0 - BCD7 +VCD0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +cmp [ebp+__areg+24],ecx +lahf +seto al +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BCD8 - BCDF +VCD8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__areg+24],ecx +lahf +seto al +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BCE0 - BCE7 +VCE0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__areg+24],ecx +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BCE8 - BCEF +VCE8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +cmp [ebp+__areg+24],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BCF0 - BCF7 +VCF0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +cmp [ebp+__areg+24],ecx +lahf +seto al +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BCF8 +VCF8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +cmp [ebp+__areg+24],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BCF9 +VCF9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +movsx ecx,cx +cmp [ebp+__areg+24],ecx +lahf +seto al +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BCFA +VCFA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +cmp [ebp+__areg+24],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BCFB +VCFB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +cmp [ebp+__areg+24],ecx +lahf +seto al +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BCFC +VCFC: +movsx ecx,word[esi] +add esi,byte 2 +cmp [ebp+__areg+24],ecx +lahf +seto al +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BD00 - BD07 +VD00: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +xor cl,[ebp+__dreg+24] +lahf +mov al,0 +mov [ebp+__dreg+ebx*4],cl +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BD08 - BD0F +VD08: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +mov eax,ecx +mov edx,[ebp+__areg+24] +call readmemorybyte +inc edx +mov [ebp+__areg+24],edx +cmp cl,al +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BD10 - BD17 +VD10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xor cl,[ebp+__dreg+24] +lahf +mov al,0 +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BD18 - BD1F +VD18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xor cl,[ebp+__dreg+24] +lahf +mov al,0 +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BD20 - BD27 +VD20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +xor cl,[ebp+__dreg+24] +lahf +mov al,0 +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BD28 - BD2F +VD28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xor cl,[ebp+__dreg+24] +lahf +mov al,0 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BD30 - BD37 +VD30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xor cl,[ebp+__dreg+24] +lahf +mov al,0 +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BD38 +VD38: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +xor cl,[ebp+__dreg+24] +lahf +mov al,0 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BD39 +VD39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +xor cl,[ebp+__dreg+24] +lahf +mov al,0 +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BD40 - BD47 +VD40: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +xor cx,[ebp+__dreg+24] +lahf +mov al,0 +mov [ebp+__dreg+ebx*4],cx +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BD48 - BD4F +VD48: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov eax,ecx +mov edx,[ebp+__areg+24] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+24],edx +cmp cx,ax +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BD50 - BD57 +VD50: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +xor cx,[ebp+__dreg+24] +lahf +mov al,0 +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BD58 - BD5F +VD58: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +xor cx,[ebp+__dreg+24] +lahf +mov al,0 +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BD60 - BD67 +VD60: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +xor cx,[ebp+__dreg+24] +lahf +mov al,0 +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BD68 - BD6F +VD68: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +xor cx,[ebp+__dreg+24] +lahf +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BD70 - BD77 +VD70: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +xor cx,[ebp+__dreg+24] +lahf +mov al,0 +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BD78 +VD78: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +xor cx,[ebp+__dreg+24] +lahf +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BD79 +VD79: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +xor cx,[ebp+__dreg+24] +lahf +mov al,0 +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BD80 - BD87 +VD80: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +xor ecx,[ebp+__dreg+24] +lahf +mov al,0 +mov [ebp+__dreg+ebx*4],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BD88 - BD8F +VD88: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +mov eax,ecx +mov edx,[ebp+__areg+24] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+24],edx +cmp ecx,eax +lahf +seto al +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BD90 - BD97 +VD90: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +xor ecx,[ebp+__dreg+24] +lahf +mov al,0 +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BD98 - BD9F +VD98: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +xor ecx,[ebp+__dreg+24] +lahf +mov al,0 +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BDA0 - BDA7 +VDA0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +xor ecx,[ebp+__dreg+24] +lahf +mov al,0 +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BDA8 - BDAF +VDA8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +xor ecx,[ebp+__dreg+24] +lahf +mov al,0 +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BDB0 - BDB7 +VDB0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +xor ecx,[ebp+__dreg+24] +lahf +mov al,0 +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BDB8 +VDB8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +xor ecx,[ebp+__dreg+24] +lahf +mov al,0 +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BDB9 +VDB9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +xor ecx,[ebp+__dreg+24] +lahf +mov al,0 +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BDC0 - BDC7 +VDC0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +cmp [ebp+__areg+24],ecx +lahf +seto al +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BDC8 - BDCF +VDC8: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +cmp [ebp+__areg+24],ecx +lahf +seto al +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BDD0 - BDD7 +VDD0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +cmp [ebp+__areg+24],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BDD8 - BDDF +VDD8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__areg+24],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BDE0 - BDE7 +VDE0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__areg+24],ecx +lahf +seto al +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BDE8 - BDEF +VDE8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +cmp [ebp+__areg+24],ecx +lahf +seto al +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BDF0 - BDF7 +VDF0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +cmp [ebp+__areg+24],ecx +lahf +seto al +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BDF8 +VDF8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +cmp [ebp+__areg+24],ecx +lahf +seto al +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BDF9 +VDF9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +cmp [ebp+__areg+24],ecx +lahf +seto al +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BDFA +VDFA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +cmp [ebp+__areg+24],ecx +lahf +seto al +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BDFB +VDFB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +cmp [ebp+__areg+24],ecx +lahf +seto al +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BDFC +VDFC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +cmp [ebp+__areg+24],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BE00 - BE07 +VE00: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +cmp [ebp+__dreg+28],cl +lahf +seto al +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BE10 - BE17 +VE10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp [ebp+__dreg+28],cl +lahf +seto al +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BE18 - BE1F +VE18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__dreg+28],cl +lahf +seto al +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BE20 - BE27 +VE20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__dreg+28],cl +lahf +seto al +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BE28 - BE2F +VE28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp [ebp+__dreg+28],cl +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BE30 - BE37 +VE30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp [ebp+__dreg+28],cl +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BE38 +VE38: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +cmp [ebp+__dreg+28],cl +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BE39 +VE39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +cmp [ebp+__dreg+28],cl +lahf +seto al +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BE3A +VE3A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +cmp [ebp+__dreg+28],cl +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BE3B +VE3B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +cmp [ebp+__dreg+28],cl +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BE3C +VE3C: +mov cx,[esi] +add esi,byte 2 +cmp [ebp+__dreg+28],cl +lahf +seto al +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BE40 - BE47 +VE40: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +cmp [ebp+__dreg+28],cx +lahf +seto al +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BE48 - BE4F +VE48: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +cmp [ebp+__dreg+28],cx +lahf +seto al +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BE50 - BE57 +VE50: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +cmp [ebp+__dreg+28],cx +lahf +seto al +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BE58 - BE5F +VE58: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__dreg+28],cx +lahf +seto al +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BE60 - BE67 +VE60: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__dreg+28],cx +lahf +seto al +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BE68 - BE6F +VE68: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +cmp [ebp+__dreg+28],cx +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BE70 - BE77 +VE70: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +cmp [ebp+__dreg+28],cx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BE78 +VE78: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +cmp [ebp+__dreg+28],cx +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BE79 +VE79: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +cmp [ebp+__dreg+28],cx +lahf +seto al +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BE7A +VE7A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +cmp [ebp+__dreg+28],cx +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BE7B +VE7B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +cmp [ebp+__dreg+28],cx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BE7C +VE7C: +mov cx,[esi] +add esi,byte 2 +cmp [ebp+__dreg+28],cx +lahf +seto al +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BE80 - BE87 +VE80: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +cmp [ebp+__dreg+28],ecx +lahf +seto al +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BE88 - BE8F +VE88: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +cmp [ebp+__dreg+28],ecx +lahf +seto al +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BE90 - BE97 +VE90: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +cmp [ebp+__dreg+28],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BE98 - BE9F +VE98: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__dreg+28],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BEA0 - BEA7 +VEA0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__dreg+28],ecx +lahf +seto al +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BEA8 - BEAF +VEA8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +cmp [ebp+__dreg+28],ecx +lahf +seto al +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BEB0 - BEB7 +VEB0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +cmp [ebp+__dreg+28],ecx +lahf +seto al +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BEB8 +VEB8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +cmp [ebp+__dreg+28],ecx +lahf +seto al +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BEB9 +VEB9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +cmp [ebp+__dreg+28],ecx +lahf +seto al +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BEBA +VEBA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +cmp [ebp+__dreg+28],ecx +lahf +seto al +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BEBB +VEBB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +cmp [ebp+__dreg+28],ecx +lahf +seto al +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BEBC +VEBC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +cmp [ebp+__dreg+28],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BEC0 - BEC7 +VEC0: +and ebx,byte 7 +movsx ecx,word[ebp+__dreg+ebx*4] +cmp [ebp+__areg+28],ecx +lahf +seto al +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BEC8 - BECF +VEC8: +and ebx,byte 7 +movsx ecx,word[ebp+__areg+ebx*4] +cmp [ebp+__areg+28],ecx +lahf +seto al +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BED0 - BED7 +VED0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +cmp [ebp+__areg+28],ecx +lahf +seto al +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BED8 - BEDF +VED8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__areg+28],ecx +lahf +seto al +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BEE0 - BEE7 +VEE0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__areg+28],ecx +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BEE8 - BEEF +VEE8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +cmp [ebp+__areg+28],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BEF0 - BEF7 +VEF0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +cmp [ebp+__areg+28],ecx +lahf +seto al +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BEF8 +VEF8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +cmp [ebp+__areg+28],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BEF9 +VEF9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +movsx ecx,cx +cmp [ebp+__areg+28],ecx +lahf +seto al +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BEFA +VEFA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +cmp [ebp+__areg+28],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BEFB +VEFB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +cmp [ebp+__areg+28],ecx +lahf +seto al +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BEFC +VEFC: +movsx ecx,word[esi] +add esi,byte 2 +cmp [ebp+__areg+28],ecx +lahf +seto al +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BF00 - BF07 +VF00: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +xor cl,[ebp+__dreg+28] +lahf +mov al,0 +mov [ebp+__dreg+ebx*4],cl +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BF08 - BF0F +VF08: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +mov eax,ecx +mov edx,[ebp+__areg+28] +call readmemorybyte +add edx,byte 2 +mov [ebp+__areg+28],edx +cmp cl,al +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BF10 - BF17 +VF10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xor cl,[ebp+__dreg+28] +lahf +mov al,0 +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BF18 - BF1F +VF18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +xor cl,[ebp+__dreg+28] +lahf +mov al,0 +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BF20 - BF27 +VF20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +xor cl,[ebp+__dreg+28] +lahf +mov al,0 +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BF28 - BF2F +VF28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xor cl,[ebp+__dreg+28] +lahf +mov al,0 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BF30 - BF37 +VF30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +xor cl,[ebp+__dreg+28] +lahf +mov al,0 +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BF38 +VF38: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +xor cl,[ebp+__dreg+28] +lahf +mov al,0 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BF39 +VF39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +xor cl,[ebp+__dreg+28] +lahf +mov al,0 +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BF40 - BF47 +VF40: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +xor cx,[ebp+__dreg+28] +lahf +mov al,0 +mov [ebp+__dreg+ebx*4],cx +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BF48 - BF4F +VF48: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov eax,ecx +mov edx,[ebp+__areg+28] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+28],edx +cmp cx,ax +lahf +seto al +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BF50 - BF57 +VF50: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +xor cx,[ebp+__dreg+28] +lahf +mov al,0 +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BF58 - BF5F +VF58: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +xor cx,[ebp+__dreg+28] +lahf +mov al,0 +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BF60 - BF67 +VF60: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +xor cx,[ebp+__dreg+28] +lahf +mov al,0 +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BF68 - BF6F +VF68: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +xor cx,[ebp+__dreg+28] +lahf +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BF70 - BF77 +VF70: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +xor cx,[ebp+__dreg+28] +lahf +mov al,0 +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BF78 +VF78: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +xor cx,[ebp+__dreg+28] +lahf +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BF79 +VF79: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +xor cx,[ebp+__dreg+28] +lahf +mov al,0 +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BF80 - BF87 +VF80: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +xor ecx,[ebp+__dreg+28] +lahf +mov al,0 +mov [ebp+__dreg+ebx*4],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BF88 - BF8F +VF88: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +mov eax,ecx +mov edx,[ebp+__areg+28] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+28],edx +cmp ecx,eax +lahf +seto al +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BF90 - BF97 +VF90: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +xor ecx,[ebp+__dreg+28] +lahf +mov al,0 +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BF98 - BF9F +VF98: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +xor ecx,[ebp+__dreg+28] +lahf +mov al,0 +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BFA0 - BFA7 +VFA0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +xor ecx,[ebp+__dreg+28] +lahf +mov al,0 +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BFA8 - BFAF +VFA8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +xor ecx,[ebp+__dreg+28] +lahf +mov al,0 +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BFB0 - BFB7 +VFB0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +xor ecx,[ebp+__dreg+28] +lahf +mov al,0 +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BFB8 +VFB8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +xor ecx,[ebp+__dreg+28] +lahf +mov al,0 +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BFB9 +VFB9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +xor ecx,[ebp+__dreg+28] +lahf +mov al,0 +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BFC0 - BFC7 +VFC0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +cmp [ebp+__areg+28],ecx +lahf +seto al +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BFC8 - BFCF +VFC8: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +cmp [ebp+__areg+28],ecx +lahf +seto al +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BFD0 - BFD7 +VFD0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +cmp [ebp+__areg+28],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BFD8 - BFDF +VFD8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__areg+28],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BFE0 - BFE7 +VFE0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +cmp [ebp+__areg+28],ecx +lahf +seto al +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BFE8 - BFEF +VFE8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +cmp [ebp+__areg+28],ecx +lahf +seto al +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes BFF0 - BFF7 +VFF0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +cmp [ebp+__areg+28],ecx +lahf +seto al +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BFF8 +VFF8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +cmp [ebp+__areg+28],ecx +lahf +seto al +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BFF9 +VFF9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +cmp [ebp+__areg+28],ecx +lahf +seto al +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BFFA +VFFA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +cmp [ebp+__areg+28],ecx +lahf +seto al +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BFFB +VFFB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +cmp [ebp+__areg+28],ecx +lahf +seto al +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode BFFC +VFFC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +cmp [ebp+__areg+28],ecx +lahf +seto al +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C000 - C007 +W000: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +and [ebp+__dreg+0],cl +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C010 - C017 +W010: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +and [ebp+__dreg+0],cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C018 - C01F +W018: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +and [ebp+__dreg+0],cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C020 - C027 +W020: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +and [ebp+__dreg+0],cl +lahf +mov al,0 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C028 - C02F +W028: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +and [ebp+__dreg+0],cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C030 - C037 +W030: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +and [ebp+__dreg+0],cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C038 +W038: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +and [ebp+__dreg+0],cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C039 +W039: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +and [ebp+__dreg+0],cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C03A +W03A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +and [ebp+__dreg+0],cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C03B +W03B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +and [ebp+__dreg+0],cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C03C +W03C: +mov cx,[esi] +add esi,byte 2 +and [ebp+__dreg+0],cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C040 - C047 +W040: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +and [ebp+__dreg+0],cx +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C050 - C057 +W050: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +and [ebp+__dreg+0],cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C058 - C05F +W058: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +and [ebp+__dreg+0],cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C060 - C067 +W060: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +and [ebp+__dreg+0],cx +lahf +mov al,0 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C068 - C06F +W068: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +and [ebp+__dreg+0],cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C070 - C077 +W070: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +and [ebp+__dreg+0],cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C078 +W078: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +and [ebp+__dreg+0],cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C079 +W079: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +and [ebp+__dreg+0],cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C07A +W07A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +and [ebp+__dreg+0],cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C07B +W07B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +and [ebp+__dreg+0],cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C07C +W07C: +mov cx,[esi] +add esi,byte 2 +and [ebp+__dreg+0],cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C080 - C087 +W080: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +and [ebp+__dreg+0],ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C090 - C097 +W090: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +and [ebp+__dreg+0],ecx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C098 - C09F +W098: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +and [ebp+__dreg+0],ecx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C0A0 - C0A7 +W0A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +and [ebp+__dreg+0],ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C0A8 - C0AF +W0A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +and [ebp+__dreg+0],ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C0B0 - C0B7 +W0B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +and [ebp+__dreg+0],ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C0B8 +W0B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +and [ebp+__dreg+0],ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C0B9 +W0B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +and [ebp+__dreg+0],ecx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C0BA +W0BA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +and [ebp+__dreg+0],ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C0BB +W0BB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +and [ebp+__dreg+0],ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C0BC +W0BC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +and [ebp+__dreg+0],ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C0C0 - C0C7 +W0C0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov eax,ecx +mov dl,0 +mov bl,16 +ln1924: +add cx,cx +adc dl,0 +dec bl +jnz ln1924 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+0] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+0],ecx +sub edi,byte 38 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C0D0 - C0D7 +W0D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln1925: +add cx,cx +adc dl,0 +dec bl +jnz ln1925 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+0] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+0],ecx +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C0D8 - C0DF +W0D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov eax,ecx +mov dl,0 +mov bl,16 +ln1926: +add cx,cx +adc dl,0 +dec bl +jnz ln1926 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+0] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+0],ecx +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C0E0 - C0E7 +W0E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov eax,ecx +mov dl,0 +mov bl,16 +ln1927: +add cx,cx +adc dl,0 +dec bl +jnz ln1927 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+0] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+0],ecx +sub edi,byte 44 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C0E8 - C0EF +W0E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln1928: +add cx,cx +adc dl,0 +dec bl +jnz ln1928 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+0] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+0],ecx +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C0F0 - C0F7 +W0F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln1929: +add cx,cx +adc dl,0 +dec bl +jnz ln1929 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+0] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+0],ecx +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C0F8 +W0F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln1930: +add cx,cx +adc dl,0 +dec bl +jnz ln1930 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+0] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+0],ecx +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C0F9 +W0F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln1931: +add cx,cx +adc dl,0 +dec bl +jnz ln1931 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+0] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+0],ecx +sub edi,byte 50 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C0FA +W0FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln1932: +add cx,cx +adc dl,0 +dec bl +jnz ln1932 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+0] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+0],ecx +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C0FB +W0FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln1933: +add cx,cx +adc dl,0 +dec bl +jnz ln1933 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+0] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+0],ecx +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C0FC +W0FC: +mov cx,[esi] +add esi,byte 2 +mov eax,ecx +mov dl,0 +mov bl,16 +ln1934: +add cx,cx +adc dl,0 +dec bl +jnz ln1934 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+0] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+0],ecx +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C100 - C107 +W100: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+0] +adc al,[ebp+__dreg+ebx*4] +daa +mov [ebp+__dreg+0],al +lahf +mov al,0 +setc [ebp+__xflag] +jnz short ln1935 +or ch,0BFh +and ah,ch +ln1935: +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C108 - C10F +W108: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+0] +dec edx +call readmemorybyte +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +adc al,bl +daa +mov ebx,eax +lahf +mov al,0 +setc [ebp+__xflag] +jnz short ln1936 +or ch,0BFh +and ah,ch +ln1936: +mov ecx,ebx +xor ebx,ebx +call writememorybyte +mov [ebp+__areg+0],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C110 - C117 +W110: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +and cl,[ebp+__dreg+0] +lahf +mov al,0 +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C118 - C11F +W118: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +and cl,[ebp+__dreg+0] +lahf +mov al,0 +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C120 - C127 +W120: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +and cl,[ebp+__dreg+0] +lahf +mov al,0 +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C128 - C12F +W128: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +and cl,[ebp+__dreg+0] +lahf +mov al,0 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C130 - C137 +W130: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +and cl,[ebp+__dreg+0] +lahf +mov al,0 +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C138 +W138: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +and cl,[ebp+__dreg+0] +lahf +mov al,0 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C139 +W139: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +and cl,[ebp+__dreg+0] +lahf +mov al,0 +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C140 - C147 +W140: +and ebx,byte 7 +mov ecx,[ebp+__reg+0] +mov edx,[ebp+__reg+0+ebx*4] +mov [ebp+__reg+0],edx +mov [ebp+__reg+0+ebx*4],ecx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C148 - C14F +W148: +and ebx,byte 7 +mov ecx,[ebp+__reg+32] +mov edx,[ebp+__reg+32+ebx*4] +mov [ebp+__reg+32],edx +mov [ebp+__reg+32+ebx*4],ecx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C150 - C157 +W150: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +and cx,[ebp+__dreg+0] +lahf +mov al,0 +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C158 - C15F +W158: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +and cx,[ebp+__dreg+0] +lahf +mov al,0 +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C160 - C167 +W160: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +and cx,[ebp+__dreg+0] +lahf +mov al,0 +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C168 - C16F +W168: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +and cx,[ebp+__dreg+0] +lahf +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C170 - C177 +W170: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +and cx,[ebp+__dreg+0] +lahf +mov al,0 +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C178 +W178: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +and cx,[ebp+__dreg+0] +lahf +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C179 +W179: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +and cx,[ebp+__dreg+0] +lahf +mov al,0 +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C188 - C18F +W188: +and ebx,byte 7 +mov ecx,[ebp+__reg+0] +mov edx,[ebp+__reg+32+ebx*4] +mov [ebp+__reg+0],edx +mov [ebp+__reg+32+ebx*4],ecx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C190 - C197 +W190: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +and ecx,[ebp+__dreg+0] +lahf +mov al,0 +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C198 - C19F +W198: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +and ecx,[ebp+__dreg+0] +lahf +mov al,0 +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C1A0 - C1A7 +W1A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +and ecx,[ebp+__dreg+0] +lahf +mov al,0 +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C1A8 - C1AF +W1A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +and ecx,[ebp+__dreg+0] +lahf +mov al,0 +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C1B0 - C1B7 +W1B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +and ecx,[ebp+__dreg+0] +lahf +mov al,0 +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C1B8 +W1B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +and ecx,[ebp+__dreg+0] +lahf +mov al,0 +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C1B9 +W1B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +and ecx,[ebp+__dreg+0] +lahf +mov al,0 +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C1C0 - C1C7 +W1C0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov eax,ecx +mov dl,0 +mov bl,16 +ln1937: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln1937 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+0] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+0],ecx +sub edi,byte 38 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C1D0 - C1D7 +W1D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln1938: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln1938 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+0] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+0],ecx +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C1D8 - C1DF +W1D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov eax,ecx +mov dl,0 +mov bl,16 +ln1939: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln1939 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+0] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+0],ecx +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C1E0 - C1E7 +W1E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov eax,ecx +mov dl,0 +mov bl,16 +ln1940: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln1940 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+0] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+0],ecx +sub edi,byte 44 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C1E8 - C1EF +W1E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln1941: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln1941 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+0] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+0],ecx +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C1F0 - C1F7 +W1F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln1942: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln1942 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+0] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+0],ecx +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C1F8 +W1F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln1943: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln1943 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+0] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+0],ecx +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C1F9 +W1F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln1944: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln1944 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+0] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+0],ecx +sub edi,byte 50 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C1FA +W1FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln1945: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln1945 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+0] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+0],ecx +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C1FB +W1FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln1946: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln1946 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+0] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+0],ecx +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C1FC +W1FC: +mov cx,[esi] +add esi,byte 2 +mov eax,ecx +mov dl,0 +mov bl,16 +ln1947: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln1947 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+0] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+0],ecx +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C200 - C207 +W200: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +and [ebp+__dreg+4],cl +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C210 - C217 +W210: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +and [ebp+__dreg+4],cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C218 - C21F +W218: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +and [ebp+__dreg+4],cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C220 - C227 +W220: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +and [ebp+__dreg+4],cl +lahf +mov al,0 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C228 - C22F +W228: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +and [ebp+__dreg+4],cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C230 - C237 +W230: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +and [ebp+__dreg+4],cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C238 +W238: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +and [ebp+__dreg+4],cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C239 +W239: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +and [ebp+__dreg+4],cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C23A +W23A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +and [ebp+__dreg+4],cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C23B +W23B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +and [ebp+__dreg+4],cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C23C +W23C: +mov cx,[esi] +add esi,byte 2 +and [ebp+__dreg+4],cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C240 - C247 +W240: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +and [ebp+__dreg+4],cx +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C250 - C257 +W250: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +and [ebp+__dreg+4],cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C258 - C25F +W258: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +and [ebp+__dreg+4],cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C260 - C267 +W260: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +and [ebp+__dreg+4],cx +lahf +mov al,0 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C268 - C26F +W268: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +and [ebp+__dreg+4],cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C270 - C277 +W270: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +and [ebp+__dreg+4],cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C278 +W278: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +and [ebp+__dreg+4],cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C279 +W279: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +and [ebp+__dreg+4],cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C27A +W27A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +and [ebp+__dreg+4],cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C27B +W27B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +and [ebp+__dreg+4],cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C27C +W27C: +mov cx,[esi] +add esi,byte 2 +and [ebp+__dreg+4],cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C280 - C287 +W280: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +and [ebp+__dreg+4],ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C290 - C297 +W290: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +and [ebp+__dreg+4],ecx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C298 - C29F +W298: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +and [ebp+__dreg+4],ecx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C2A0 - C2A7 +W2A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +and [ebp+__dreg+4],ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C2A8 - C2AF +W2A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +and [ebp+__dreg+4],ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C2B0 - C2B7 +W2B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +and [ebp+__dreg+4],ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C2B8 +W2B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +and [ebp+__dreg+4],ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C2B9 +W2B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +and [ebp+__dreg+4],ecx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C2BA +W2BA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +and [ebp+__dreg+4],ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C2BB +W2BB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +and [ebp+__dreg+4],ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C2BC +W2BC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +and [ebp+__dreg+4],ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C2C0 - C2C7 +W2C0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov eax,ecx +mov dl,0 +mov bl,16 +ln1948: +add cx,cx +adc dl,0 +dec bl +jnz ln1948 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+4] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+4],ecx +sub edi,byte 38 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C2D0 - C2D7 +W2D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln1949: +add cx,cx +adc dl,0 +dec bl +jnz ln1949 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+4] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+4],ecx +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C2D8 - C2DF +W2D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov eax,ecx +mov dl,0 +mov bl,16 +ln1950: +add cx,cx +adc dl,0 +dec bl +jnz ln1950 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+4] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+4],ecx +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C2E0 - C2E7 +W2E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov eax,ecx +mov dl,0 +mov bl,16 +ln1951: +add cx,cx +adc dl,0 +dec bl +jnz ln1951 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+4] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+4],ecx +sub edi,byte 44 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C2E8 - C2EF +W2E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln1952: +add cx,cx +adc dl,0 +dec bl +jnz ln1952 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+4] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+4],ecx +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C2F0 - C2F7 +W2F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln1953: +add cx,cx +adc dl,0 +dec bl +jnz ln1953 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+4] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+4],ecx +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C2F8 +W2F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln1954: +add cx,cx +adc dl,0 +dec bl +jnz ln1954 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+4] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+4],ecx +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C2F9 +W2F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln1955: +add cx,cx +adc dl,0 +dec bl +jnz ln1955 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+4] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+4],ecx +sub edi,byte 50 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C2FA +W2FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln1956: +add cx,cx +adc dl,0 +dec bl +jnz ln1956 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+4] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+4],ecx +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C2FB +W2FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln1957: +add cx,cx +adc dl,0 +dec bl +jnz ln1957 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+4] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+4],ecx +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C2FC +W2FC: +mov cx,[esi] +add esi,byte 2 +mov eax,ecx +mov dl,0 +mov bl,16 +ln1958: +add cx,cx +adc dl,0 +dec bl +jnz ln1958 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+4] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+4],ecx +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C300 - C307 +W300: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+4] +adc al,[ebp+__dreg+ebx*4] +daa +mov [ebp+__dreg+4],al +lahf +mov al,0 +setc [ebp+__xflag] +jnz short ln1959 +or ch,0BFh +and ah,ch +ln1959: +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C308 - C30F +W308: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+4] +dec edx +call readmemorybyte +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +adc al,bl +daa +mov ebx,eax +lahf +mov al,0 +setc [ebp+__xflag] +jnz short ln1960 +or ch,0BFh +and ah,ch +ln1960: +mov ecx,ebx +xor ebx,ebx +call writememorybyte +mov [ebp+__areg+4],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C310 - C317 +W310: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +and cl,[ebp+__dreg+4] +lahf +mov al,0 +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C318 - C31F +W318: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +and cl,[ebp+__dreg+4] +lahf +mov al,0 +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C320 - C327 +W320: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +and cl,[ebp+__dreg+4] +lahf +mov al,0 +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C328 - C32F +W328: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +and cl,[ebp+__dreg+4] +lahf +mov al,0 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C330 - C337 +W330: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +and cl,[ebp+__dreg+4] +lahf +mov al,0 +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C338 +W338: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +and cl,[ebp+__dreg+4] +lahf +mov al,0 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C339 +W339: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +and cl,[ebp+__dreg+4] +lahf +mov al,0 +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C340 - C347 +W340: +and ebx,byte 7 +mov ecx,[ebp+__reg+4] +mov edx,[ebp+__reg+0+ebx*4] +mov [ebp+__reg+4],edx +mov [ebp+__reg+0+ebx*4],ecx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C348 - C34F +W348: +and ebx,byte 7 +mov ecx,[ebp+__reg+36] +mov edx,[ebp+__reg+32+ebx*4] +mov [ebp+__reg+36],edx +mov [ebp+__reg+32+ebx*4],ecx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C350 - C357 +W350: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +and cx,[ebp+__dreg+4] +lahf +mov al,0 +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C358 - C35F +W358: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +and cx,[ebp+__dreg+4] +lahf +mov al,0 +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C360 - C367 +W360: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +and cx,[ebp+__dreg+4] +lahf +mov al,0 +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C368 - C36F +W368: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +and cx,[ebp+__dreg+4] +lahf +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C370 - C377 +W370: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +and cx,[ebp+__dreg+4] +lahf +mov al,0 +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C378 +W378: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +and cx,[ebp+__dreg+4] +lahf +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C379 +W379: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +and cx,[ebp+__dreg+4] +lahf +mov al,0 +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C388 - C38F +W388: +and ebx,byte 7 +mov ecx,[ebp+__reg+4] +mov edx,[ebp+__reg+32+ebx*4] +mov [ebp+__reg+4],edx +mov [ebp+__reg+32+ebx*4],ecx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C390 - C397 +W390: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +and ecx,[ebp+__dreg+4] +lahf +mov al,0 +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C398 - C39F +W398: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +and ecx,[ebp+__dreg+4] +lahf +mov al,0 +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C3A0 - C3A7 +W3A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +and ecx,[ebp+__dreg+4] +lahf +mov al,0 +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C3A8 - C3AF +W3A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +and ecx,[ebp+__dreg+4] +lahf +mov al,0 +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C3B0 - C3B7 +W3B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +and ecx,[ebp+__dreg+4] +lahf +mov al,0 +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C3B8 +W3B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +and ecx,[ebp+__dreg+4] +lahf +mov al,0 +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C3B9 +W3B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +and ecx,[ebp+__dreg+4] +lahf +mov al,0 +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C3C0 - C3C7 +W3C0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov eax,ecx +mov dl,0 +mov bl,16 +ln1961: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln1961 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+4] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+4],ecx +sub edi,byte 38 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C3D0 - C3D7 +W3D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln1962: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln1962 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+4] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+4],ecx +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C3D8 - C3DF +W3D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov eax,ecx +mov dl,0 +mov bl,16 +ln1963: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln1963 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+4] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+4],ecx +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C3E0 - C3E7 +W3E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov eax,ecx +mov dl,0 +mov bl,16 +ln1964: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln1964 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+4] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+4],ecx +sub edi,byte 44 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C3E8 - C3EF +W3E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln1965: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln1965 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+4] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+4],ecx +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C3F0 - C3F7 +W3F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln1966: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln1966 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+4] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+4],ecx +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C3F8 +W3F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln1967: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln1967 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+4] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+4],ecx +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C3F9 +W3F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln1968: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln1968 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+4] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+4],ecx +sub edi,byte 50 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C3FA +W3FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln1969: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln1969 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+4] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+4],ecx +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C3FB +W3FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln1970: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln1970 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+4] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+4],ecx +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C3FC +W3FC: +mov cx,[esi] +add esi,byte 2 +mov eax,ecx +mov dl,0 +mov bl,16 +ln1971: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln1971 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+4] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+4],ecx +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C400 - C407 +W400: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +and [ebp+__dreg+8],cl +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C410 - C417 +W410: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +and [ebp+__dreg+8],cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C418 - C41F +W418: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +and [ebp+__dreg+8],cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C420 - C427 +W420: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +and [ebp+__dreg+8],cl +lahf +mov al,0 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C428 - C42F +W428: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +and [ebp+__dreg+8],cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C430 - C437 +W430: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +and [ebp+__dreg+8],cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C438 +W438: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +and [ebp+__dreg+8],cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C439 +W439: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +and [ebp+__dreg+8],cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C43A +W43A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +and [ebp+__dreg+8],cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C43B +W43B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +and [ebp+__dreg+8],cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C43C +W43C: +mov cx,[esi] +add esi,byte 2 +and [ebp+__dreg+8],cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C440 - C447 +W440: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +and [ebp+__dreg+8],cx +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C450 - C457 +W450: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +and [ebp+__dreg+8],cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C458 - C45F +W458: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +and [ebp+__dreg+8],cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C460 - C467 +W460: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +and [ebp+__dreg+8],cx +lahf +mov al,0 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C468 - C46F +W468: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +and [ebp+__dreg+8],cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C470 - C477 +W470: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +and [ebp+__dreg+8],cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C478 +W478: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +and [ebp+__dreg+8],cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C479 +W479: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +and [ebp+__dreg+8],cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C47A +W47A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +and [ebp+__dreg+8],cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C47B +W47B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +and [ebp+__dreg+8],cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C47C +W47C: +mov cx,[esi] +add esi,byte 2 +and [ebp+__dreg+8],cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C480 - C487 +W480: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +and [ebp+__dreg+8],ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C490 - C497 +W490: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +and [ebp+__dreg+8],ecx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C498 - C49F +W498: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +and [ebp+__dreg+8],ecx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C4A0 - C4A7 +W4A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +and [ebp+__dreg+8],ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C4A8 - C4AF +W4A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +and [ebp+__dreg+8],ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C4B0 - C4B7 +W4B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +and [ebp+__dreg+8],ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C4B8 +W4B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +and [ebp+__dreg+8],ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C4B9 +W4B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +and [ebp+__dreg+8],ecx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C4BA +W4BA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +and [ebp+__dreg+8],ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C4BB +W4BB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +and [ebp+__dreg+8],ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C4BC +W4BC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +and [ebp+__dreg+8],ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C4C0 - C4C7 +W4C0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov eax,ecx +mov dl,0 +mov bl,16 +ln1972: +add cx,cx +adc dl,0 +dec bl +jnz ln1972 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+8] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+8],ecx +sub edi,byte 38 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C4D0 - C4D7 +W4D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln1973: +add cx,cx +adc dl,0 +dec bl +jnz ln1973 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+8] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+8],ecx +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C4D8 - C4DF +W4D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov eax,ecx +mov dl,0 +mov bl,16 +ln1974: +add cx,cx +adc dl,0 +dec bl +jnz ln1974 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+8] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+8],ecx +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C4E0 - C4E7 +W4E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov eax,ecx +mov dl,0 +mov bl,16 +ln1975: +add cx,cx +adc dl,0 +dec bl +jnz ln1975 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+8] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+8],ecx +sub edi,byte 44 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C4E8 - C4EF +W4E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln1976: +add cx,cx +adc dl,0 +dec bl +jnz ln1976 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+8] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+8],ecx +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C4F0 - C4F7 +W4F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln1977: +add cx,cx +adc dl,0 +dec bl +jnz ln1977 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+8] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+8],ecx +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C4F8 +W4F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln1978: +add cx,cx +adc dl,0 +dec bl +jnz ln1978 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+8] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+8],ecx +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C4F9 +W4F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln1979: +add cx,cx +adc dl,0 +dec bl +jnz ln1979 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+8] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+8],ecx +sub edi,byte 50 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C4FA +W4FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln1980: +add cx,cx +adc dl,0 +dec bl +jnz ln1980 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+8] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+8],ecx +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C4FB +W4FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln1981: +add cx,cx +adc dl,0 +dec bl +jnz ln1981 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+8] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+8],ecx +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C4FC +W4FC: +mov cx,[esi] +add esi,byte 2 +mov eax,ecx +mov dl,0 +mov bl,16 +ln1982: +add cx,cx +adc dl,0 +dec bl +jnz ln1982 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+8] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+8],ecx +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C500 - C507 +W500: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+8] +adc al,[ebp+__dreg+ebx*4] +daa +mov [ebp+__dreg+8],al +lahf +mov al,0 +setc [ebp+__xflag] +jnz short ln1983 +or ch,0BFh +and ah,ch +ln1983: +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C508 - C50F +W508: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+8] +dec edx +call readmemorybyte +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +adc al,bl +daa +mov ebx,eax +lahf +mov al,0 +setc [ebp+__xflag] +jnz short ln1984 +or ch,0BFh +and ah,ch +ln1984: +mov ecx,ebx +xor ebx,ebx +call writememorybyte +mov [ebp+__areg+8],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C510 - C517 +W510: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +and cl,[ebp+__dreg+8] +lahf +mov al,0 +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C518 - C51F +W518: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +and cl,[ebp+__dreg+8] +lahf +mov al,0 +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C520 - C527 +W520: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +and cl,[ebp+__dreg+8] +lahf +mov al,0 +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C528 - C52F +W528: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +and cl,[ebp+__dreg+8] +lahf +mov al,0 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C530 - C537 +W530: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +and cl,[ebp+__dreg+8] +lahf +mov al,0 +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C538 +W538: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +and cl,[ebp+__dreg+8] +lahf +mov al,0 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C539 +W539: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +and cl,[ebp+__dreg+8] +lahf +mov al,0 +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C540 - C547 +W540: +and ebx,byte 7 +mov ecx,[ebp+__reg+8] +mov edx,[ebp+__reg+0+ebx*4] +mov [ebp+__reg+8],edx +mov [ebp+__reg+0+ebx*4],ecx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C548 - C54F +W548: +and ebx,byte 7 +mov ecx,[ebp+__reg+40] +mov edx,[ebp+__reg+32+ebx*4] +mov [ebp+__reg+40],edx +mov [ebp+__reg+32+ebx*4],ecx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C550 - C557 +W550: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +and cx,[ebp+__dreg+8] +lahf +mov al,0 +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C558 - C55F +W558: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +and cx,[ebp+__dreg+8] +lahf +mov al,0 +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C560 - C567 +W560: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +and cx,[ebp+__dreg+8] +lahf +mov al,0 +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C568 - C56F +W568: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +and cx,[ebp+__dreg+8] +lahf +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C570 - C577 +W570: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +and cx,[ebp+__dreg+8] +lahf +mov al,0 +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C578 +W578: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +and cx,[ebp+__dreg+8] +lahf +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C579 +W579: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +and cx,[ebp+__dreg+8] +lahf +mov al,0 +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C588 - C58F +W588: +and ebx,byte 7 +mov ecx,[ebp+__reg+8] +mov edx,[ebp+__reg+32+ebx*4] +mov [ebp+__reg+8],edx +mov [ebp+__reg+32+ebx*4],ecx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C590 - C597 +W590: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +and ecx,[ebp+__dreg+8] +lahf +mov al,0 +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C598 - C59F +W598: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +and ecx,[ebp+__dreg+8] +lahf +mov al,0 +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C5A0 - C5A7 +W5A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +and ecx,[ebp+__dreg+8] +lahf +mov al,0 +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C5A8 - C5AF +W5A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +and ecx,[ebp+__dreg+8] +lahf +mov al,0 +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C5B0 - C5B7 +W5B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +and ecx,[ebp+__dreg+8] +lahf +mov al,0 +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C5B8 +W5B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +and ecx,[ebp+__dreg+8] +lahf +mov al,0 +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C5B9 +W5B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +and ecx,[ebp+__dreg+8] +lahf +mov al,0 +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C5C0 - C5C7 +W5C0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov eax,ecx +mov dl,0 +mov bl,16 +ln1985: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln1985 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+8] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+8],ecx +sub edi,byte 38 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C5D0 - C5D7 +W5D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln1986: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln1986 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+8] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+8],ecx +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C5D8 - C5DF +W5D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov eax,ecx +mov dl,0 +mov bl,16 +ln1987: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln1987 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+8] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+8],ecx +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C5E0 - C5E7 +W5E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov eax,ecx +mov dl,0 +mov bl,16 +ln1988: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln1988 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+8] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+8],ecx +sub edi,byte 44 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C5E8 - C5EF +W5E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln1989: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln1989 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+8] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+8],ecx +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C5F0 - C5F7 +W5F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln1990: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln1990 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+8] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+8],ecx +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C5F8 +W5F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln1991: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln1991 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+8] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+8],ecx +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C5F9 +W5F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln1992: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln1992 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+8] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+8],ecx +sub edi,byte 50 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C5FA +W5FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln1993: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln1993 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+8] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+8],ecx +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C5FB +W5FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln1994: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln1994 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+8] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+8],ecx +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C5FC +W5FC: +mov cx,[esi] +add esi,byte 2 +mov eax,ecx +mov dl,0 +mov bl,16 +ln1995: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln1995 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+8] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+8],ecx +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C600 - C607 +W600: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +and [ebp+__dreg+12],cl +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C610 - C617 +W610: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +and [ebp+__dreg+12],cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C618 - C61F +W618: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +and [ebp+__dreg+12],cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C620 - C627 +W620: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +and [ebp+__dreg+12],cl +lahf +mov al,0 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C628 - C62F +W628: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +and [ebp+__dreg+12],cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C630 - C637 +W630: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +and [ebp+__dreg+12],cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C638 +W638: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +and [ebp+__dreg+12],cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C639 +W639: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +and [ebp+__dreg+12],cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C63A +W63A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +and [ebp+__dreg+12],cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C63B +W63B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +and [ebp+__dreg+12],cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C63C +W63C: +mov cx,[esi] +add esi,byte 2 +and [ebp+__dreg+12],cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C640 - C647 +W640: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +and [ebp+__dreg+12],cx +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C650 - C657 +W650: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +and [ebp+__dreg+12],cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C658 - C65F +W658: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +and [ebp+__dreg+12],cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C660 - C667 +W660: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +and [ebp+__dreg+12],cx +lahf +mov al,0 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C668 - C66F +W668: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +and [ebp+__dreg+12],cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C670 - C677 +W670: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +and [ebp+__dreg+12],cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C678 +W678: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +and [ebp+__dreg+12],cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C679 +W679: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +and [ebp+__dreg+12],cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C67A +W67A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +and [ebp+__dreg+12],cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C67B +W67B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +and [ebp+__dreg+12],cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C67C +W67C: +mov cx,[esi] +add esi,byte 2 +and [ebp+__dreg+12],cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C680 - C687 +W680: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +and [ebp+__dreg+12],ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C690 - C697 +W690: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +and [ebp+__dreg+12],ecx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C698 - C69F +W698: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +and [ebp+__dreg+12],ecx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C6A0 - C6A7 +W6A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +and [ebp+__dreg+12],ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C6A8 - C6AF +W6A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +and [ebp+__dreg+12],ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C6B0 - C6B7 +W6B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +and [ebp+__dreg+12],ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C6B8 +W6B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +and [ebp+__dreg+12],ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C6B9 +W6B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +and [ebp+__dreg+12],ecx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C6BA +W6BA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +and [ebp+__dreg+12],ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C6BB +W6BB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +and [ebp+__dreg+12],ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C6BC +W6BC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +and [ebp+__dreg+12],ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C6C0 - C6C7 +W6C0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov eax,ecx +mov dl,0 +mov bl,16 +ln1996: +add cx,cx +adc dl,0 +dec bl +jnz ln1996 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+12] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+12],ecx +sub edi,byte 38 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C6D0 - C6D7 +W6D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln1997: +add cx,cx +adc dl,0 +dec bl +jnz ln1997 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+12] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+12],ecx +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C6D8 - C6DF +W6D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov eax,ecx +mov dl,0 +mov bl,16 +ln1998: +add cx,cx +adc dl,0 +dec bl +jnz ln1998 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+12] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+12],ecx +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C6E0 - C6E7 +W6E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov eax,ecx +mov dl,0 +mov bl,16 +ln1999: +add cx,cx +adc dl,0 +dec bl +jnz ln1999 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+12] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+12],ecx +sub edi,byte 44 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C6E8 - C6EF +W6E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2000: +add cx,cx +adc dl,0 +dec bl +jnz ln2000 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+12] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+12],ecx +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C6F0 - C6F7 +W6F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2001: +add cx,cx +adc dl,0 +dec bl +jnz ln2001 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+12] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+12],ecx +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C6F8 +W6F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2002: +add cx,cx +adc dl,0 +dec bl +jnz ln2002 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+12] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+12],ecx +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C6F9 +W6F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2003: +add cx,cx +adc dl,0 +dec bl +jnz ln2003 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+12] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+12],ecx +sub edi,byte 50 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C6FA +W6FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2004: +add cx,cx +adc dl,0 +dec bl +jnz ln2004 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+12] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+12],ecx +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C6FB +W6FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2005: +add cx,cx +adc dl,0 +dec bl +jnz ln2005 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+12] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+12],ecx +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C6FC +W6FC: +mov cx,[esi] +add esi,byte 2 +mov eax,ecx +mov dl,0 +mov bl,16 +ln2006: +add cx,cx +adc dl,0 +dec bl +jnz ln2006 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+12] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+12],ecx +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C700 - C707 +W700: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+12] +adc al,[ebp+__dreg+ebx*4] +daa +mov [ebp+__dreg+12],al +lahf +mov al,0 +setc [ebp+__xflag] +jnz short ln2007 +or ch,0BFh +and ah,ch +ln2007: +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C708 - C70F +W708: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+12] +dec edx +call readmemorybyte +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +adc al,bl +daa +mov ebx,eax +lahf +mov al,0 +setc [ebp+__xflag] +jnz short ln2008 +or ch,0BFh +and ah,ch +ln2008: +mov ecx,ebx +xor ebx,ebx +call writememorybyte +mov [ebp+__areg+12],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C710 - C717 +W710: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +and cl,[ebp+__dreg+12] +lahf +mov al,0 +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C718 - C71F +W718: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +and cl,[ebp+__dreg+12] +lahf +mov al,0 +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C720 - C727 +W720: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +and cl,[ebp+__dreg+12] +lahf +mov al,0 +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C728 - C72F +W728: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +and cl,[ebp+__dreg+12] +lahf +mov al,0 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C730 - C737 +W730: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +and cl,[ebp+__dreg+12] +lahf +mov al,0 +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C738 +W738: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +and cl,[ebp+__dreg+12] +lahf +mov al,0 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C739 +W739: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +and cl,[ebp+__dreg+12] +lahf +mov al,0 +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C740 - C747 +W740: +and ebx,byte 7 +mov ecx,[ebp+__reg+12] +mov edx,[ebp+__reg+0+ebx*4] +mov [ebp+__reg+12],edx +mov [ebp+__reg+0+ebx*4],ecx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C748 - C74F +W748: +and ebx,byte 7 +mov ecx,[ebp+__reg+44] +mov edx,[ebp+__reg+32+ebx*4] +mov [ebp+__reg+44],edx +mov [ebp+__reg+32+ebx*4],ecx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C750 - C757 +W750: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +and cx,[ebp+__dreg+12] +lahf +mov al,0 +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C758 - C75F +W758: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +and cx,[ebp+__dreg+12] +lahf +mov al,0 +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C760 - C767 +W760: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +and cx,[ebp+__dreg+12] +lahf +mov al,0 +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C768 - C76F +W768: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +and cx,[ebp+__dreg+12] +lahf +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C770 - C777 +W770: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +and cx,[ebp+__dreg+12] +lahf +mov al,0 +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C778 +W778: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +and cx,[ebp+__dreg+12] +lahf +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C779 +W779: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +and cx,[ebp+__dreg+12] +lahf +mov al,0 +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C788 - C78F +W788: +and ebx,byte 7 +mov ecx,[ebp+__reg+12] +mov edx,[ebp+__reg+32+ebx*4] +mov [ebp+__reg+12],edx +mov [ebp+__reg+32+ebx*4],ecx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C790 - C797 +W790: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +and ecx,[ebp+__dreg+12] +lahf +mov al,0 +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C798 - C79F +W798: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +and ecx,[ebp+__dreg+12] +lahf +mov al,0 +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C7A0 - C7A7 +W7A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +and ecx,[ebp+__dreg+12] +lahf +mov al,0 +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C7A8 - C7AF +W7A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +and ecx,[ebp+__dreg+12] +lahf +mov al,0 +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C7B0 - C7B7 +W7B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +and ecx,[ebp+__dreg+12] +lahf +mov al,0 +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C7B8 +W7B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +and ecx,[ebp+__dreg+12] +lahf +mov al,0 +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C7B9 +W7B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +and ecx,[ebp+__dreg+12] +lahf +mov al,0 +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C7C0 - C7C7 +W7C0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov eax,ecx +mov dl,0 +mov bl,16 +ln2009: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln2009 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+12] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+12],ecx +sub edi,byte 38 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C7D0 - C7D7 +W7D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2010: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln2010 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+12] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+12],ecx +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C7D8 - C7DF +W7D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov eax,ecx +mov dl,0 +mov bl,16 +ln2011: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln2011 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+12] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+12],ecx +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C7E0 - C7E7 +W7E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov eax,ecx +mov dl,0 +mov bl,16 +ln2012: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln2012 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+12] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+12],ecx +sub edi,byte 44 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C7E8 - C7EF +W7E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2013: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln2013 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+12] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+12],ecx +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C7F0 - C7F7 +W7F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2014: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln2014 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+12] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+12],ecx +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C7F8 +W7F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2015: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln2015 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+12] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+12],ecx +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C7F9 +W7F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2016: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln2016 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+12] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+12],ecx +sub edi,byte 50 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C7FA +W7FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2017: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln2017 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+12] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+12],ecx +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C7FB +W7FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2018: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln2018 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+12] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+12],ecx +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C7FC +W7FC: +mov cx,[esi] +add esi,byte 2 +mov eax,ecx +mov dl,0 +mov bl,16 +ln2019: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln2019 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+12] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+12],ecx +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C800 - C807 +W800: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +and [ebp+__dreg+16],cl +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C810 - C817 +W810: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +and [ebp+__dreg+16],cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C818 - C81F +W818: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +and [ebp+__dreg+16],cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C820 - C827 +W820: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +and [ebp+__dreg+16],cl +lahf +mov al,0 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C828 - C82F +W828: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +and [ebp+__dreg+16],cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C830 - C837 +W830: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +and [ebp+__dreg+16],cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C838 +W838: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +and [ebp+__dreg+16],cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C839 +W839: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +and [ebp+__dreg+16],cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C83A +W83A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +and [ebp+__dreg+16],cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C83B +W83B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +and [ebp+__dreg+16],cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C83C +W83C: +mov cx,[esi] +add esi,byte 2 +and [ebp+__dreg+16],cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C840 - C847 +W840: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +and [ebp+__dreg+16],cx +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C850 - C857 +W850: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +and [ebp+__dreg+16],cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C858 - C85F +W858: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +and [ebp+__dreg+16],cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C860 - C867 +W860: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +and [ebp+__dreg+16],cx +lahf +mov al,0 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C868 - C86F +W868: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +and [ebp+__dreg+16],cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C870 - C877 +W870: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +and [ebp+__dreg+16],cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C878 +W878: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +and [ebp+__dreg+16],cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C879 +W879: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +and [ebp+__dreg+16],cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C87A +W87A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +and [ebp+__dreg+16],cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C87B +W87B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +and [ebp+__dreg+16],cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C87C +W87C: +mov cx,[esi] +add esi,byte 2 +and [ebp+__dreg+16],cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C880 - C887 +W880: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +and [ebp+__dreg+16],ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C890 - C897 +W890: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +and [ebp+__dreg+16],ecx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C898 - C89F +W898: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +and [ebp+__dreg+16],ecx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C8A0 - C8A7 +W8A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +and [ebp+__dreg+16],ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C8A8 - C8AF +W8A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +and [ebp+__dreg+16],ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C8B0 - C8B7 +W8B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +and [ebp+__dreg+16],ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C8B8 +W8B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +and [ebp+__dreg+16],ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C8B9 +W8B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +and [ebp+__dreg+16],ecx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C8BA +W8BA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +and [ebp+__dreg+16],ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C8BB +W8BB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +and [ebp+__dreg+16],ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C8BC +W8BC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +and [ebp+__dreg+16],ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C8C0 - C8C7 +W8C0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov eax,ecx +mov dl,0 +mov bl,16 +ln2020: +add cx,cx +adc dl,0 +dec bl +jnz ln2020 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+16] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+16],ecx +sub edi,byte 38 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C8D0 - C8D7 +W8D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2021: +add cx,cx +adc dl,0 +dec bl +jnz ln2021 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+16] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+16],ecx +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C8D8 - C8DF +W8D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov eax,ecx +mov dl,0 +mov bl,16 +ln2022: +add cx,cx +adc dl,0 +dec bl +jnz ln2022 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+16] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+16],ecx +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C8E0 - C8E7 +W8E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov eax,ecx +mov dl,0 +mov bl,16 +ln2023: +add cx,cx +adc dl,0 +dec bl +jnz ln2023 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+16] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+16],ecx +sub edi,byte 44 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C8E8 - C8EF +W8E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2024: +add cx,cx +adc dl,0 +dec bl +jnz ln2024 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+16] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+16],ecx +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C8F0 - C8F7 +W8F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2025: +add cx,cx +adc dl,0 +dec bl +jnz ln2025 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+16] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+16],ecx +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C8F8 +W8F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2026: +add cx,cx +adc dl,0 +dec bl +jnz ln2026 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+16] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+16],ecx +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C8F9 +W8F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2027: +add cx,cx +adc dl,0 +dec bl +jnz ln2027 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+16] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+16],ecx +sub edi,byte 50 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C8FA +W8FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2028: +add cx,cx +adc dl,0 +dec bl +jnz ln2028 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+16] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+16],ecx +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C8FB +W8FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2029: +add cx,cx +adc dl,0 +dec bl +jnz ln2029 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+16] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+16],ecx +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C8FC +W8FC: +mov cx,[esi] +add esi,byte 2 +mov eax,ecx +mov dl,0 +mov bl,16 +ln2030: +add cx,cx +adc dl,0 +dec bl +jnz ln2030 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+16] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+16],ecx +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C900 - C907 +W900: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+16] +adc al,[ebp+__dreg+ebx*4] +daa +mov [ebp+__dreg+16],al +lahf +mov al,0 +setc [ebp+__xflag] +jnz short ln2031 +or ch,0BFh +and ah,ch +ln2031: +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C908 - C90F +W908: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+16] +dec edx +call readmemorybyte +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +adc al,bl +daa +mov ebx,eax +lahf +mov al,0 +setc [ebp+__xflag] +jnz short ln2032 +or ch,0BFh +and ah,ch +ln2032: +mov ecx,ebx +xor ebx,ebx +call writememorybyte +mov [ebp+__areg+16],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C910 - C917 +W910: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +and cl,[ebp+__dreg+16] +lahf +mov al,0 +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C918 - C91F +W918: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +and cl,[ebp+__dreg+16] +lahf +mov al,0 +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C920 - C927 +W920: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +and cl,[ebp+__dreg+16] +lahf +mov al,0 +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C928 - C92F +W928: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +and cl,[ebp+__dreg+16] +lahf +mov al,0 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C930 - C937 +W930: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +and cl,[ebp+__dreg+16] +lahf +mov al,0 +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C938 +W938: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +and cl,[ebp+__dreg+16] +lahf +mov al,0 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C939 +W939: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +and cl,[ebp+__dreg+16] +lahf +mov al,0 +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C940 - C947 +W940: +and ebx,byte 7 +mov ecx,[ebp+__reg+16] +mov edx,[ebp+__reg+0+ebx*4] +mov [ebp+__reg+16],edx +mov [ebp+__reg+0+ebx*4],ecx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C948 - C94F +W948: +and ebx,byte 7 +mov ecx,[ebp+__reg+48] +mov edx,[ebp+__reg+32+ebx*4] +mov [ebp+__reg+48],edx +mov [ebp+__reg+32+ebx*4],ecx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C950 - C957 +W950: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +and cx,[ebp+__dreg+16] +lahf +mov al,0 +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C958 - C95F +W958: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +and cx,[ebp+__dreg+16] +lahf +mov al,0 +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C960 - C967 +W960: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +and cx,[ebp+__dreg+16] +lahf +mov al,0 +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C968 - C96F +W968: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +and cx,[ebp+__dreg+16] +lahf +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C970 - C977 +W970: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +and cx,[ebp+__dreg+16] +lahf +mov al,0 +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C978 +W978: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +and cx,[ebp+__dreg+16] +lahf +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C979 +W979: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +and cx,[ebp+__dreg+16] +lahf +mov al,0 +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C988 - C98F +W988: +and ebx,byte 7 +mov ecx,[ebp+__reg+16] +mov edx,[ebp+__reg+32+ebx*4] +mov [ebp+__reg+16],edx +mov [ebp+__reg+32+ebx*4],ecx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C990 - C997 +W990: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +and ecx,[ebp+__dreg+16] +lahf +mov al,0 +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C998 - C99F +W998: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +and ecx,[ebp+__dreg+16] +lahf +mov al,0 +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C9A0 - C9A7 +W9A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +and ecx,[ebp+__dreg+16] +lahf +mov al,0 +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C9A8 - C9AF +W9A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +and ecx,[ebp+__dreg+16] +lahf +mov al,0 +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C9B0 - C9B7 +W9B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +and ecx,[ebp+__dreg+16] +lahf +mov al,0 +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C9B8 +W9B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +and ecx,[ebp+__dreg+16] +lahf +mov al,0 +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C9B9 +W9B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +and ecx,[ebp+__dreg+16] +lahf +mov al,0 +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C9C0 - C9C7 +W9C0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov eax,ecx +mov dl,0 +mov bl,16 +ln2033: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln2033 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+16] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+16],ecx +sub edi,byte 38 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C9D0 - C9D7 +W9D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2034: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln2034 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+16] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+16],ecx +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C9D8 - C9DF +W9D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov eax,ecx +mov dl,0 +mov bl,16 +ln2035: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln2035 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+16] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+16],ecx +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C9E0 - C9E7 +W9E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov eax,ecx +mov dl,0 +mov bl,16 +ln2036: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln2036 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+16] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+16],ecx +sub edi,byte 44 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C9E8 - C9EF +W9E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2037: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln2037 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+16] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+16],ecx +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes C9F0 - C9F7 +W9F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2038: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln2038 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+16] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+16],ecx +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C9F8 +W9F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2039: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln2039 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+16] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+16],ecx +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C9F9 +W9F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2040: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln2040 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+16] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+16],ecx +sub edi,byte 50 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C9FA +W9FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2041: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln2041 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+16] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+16],ecx +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C9FB +W9FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2042: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln2042 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+16] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+16],ecx +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode C9FC +W9FC: +mov cx,[esi] +add esi,byte 2 +mov eax,ecx +mov dl,0 +mov bl,16 +ln2043: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln2043 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+16] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+16],ecx +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CA00 - CA07 +WA00: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +and [ebp+__dreg+20],cl +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CA10 - CA17 +WA10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +and [ebp+__dreg+20],cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CA18 - CA1F +WA18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +and [ebp+__dreg+20],cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CA20 - CA27 +WA20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +and [ebp+__dreg+20],cl +lahf +mov al,0 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CA28 - CA2F +WA28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +and [ebp+__dreg+20],cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CA30 - CA37 +WA30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +and [ebp+__dreg+20],cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CA38 +WA38: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +and [ebp+__dreg+20],cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CA39 +WA39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +and [ebp+__dreg+20],cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CA3A +WA3A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +and [ebp+__dreg+20],cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CA3B +WA3B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +and [ebp+__dreg+20],cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CA3C +WA3C: +mov cx,[esi] +add esi,byte 2 +and [ebp+__dreg+20],cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CA40 - CA47 +WA40: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +and [ebp+__dreg+20],cx +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CA50 - CA57 +WA50: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +and [ebp+__dreg+20],cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CA58 - CA5F +WA58: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +and [ebp+__dreg+20],cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CA60 - CA67 +WA60: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +and [ebp+__dreg+20],cx +lahf +mov al,0 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CA68 - CA6F +WA68: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +and [ebp+__dreg+20],cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CA70 - CA77 +WA70: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +and [ebp+__dreg+20],cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CA78 +WA78: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +and [ebp+__dreg+20],cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CA79 +WA79: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +and [ebp+__dreg+20],cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CA7A +WA7A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +and [ebp+__dreg+20],cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CA7B +WA7B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +and [ebp+__dreg+20],cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CA7C +WA7C: +mov cx,[esi] +add esi,byte 2 +and [ebp+__dreg+20],cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CA80 - CA87 +WA80: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +and [ebp+__dreg+20],ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CA90 - CA97 +WA90: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +and [ebp+__dreg+20],ecx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CA98 - CA9F +WA98: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +and [ebp+__dreg+20],ecx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CAA0 - CAA7 +WAA0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +and [ebp+__dreg+20],ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CAA8 - CAAF +WAA8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +and [ebp+__dreg+20],ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CAB0 - CAB7 +WAB0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +and [ebp+__dreg+20],ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CAB8 +WAB8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +and [ebp+__dreg+20],ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CAB9 +WAB9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +and [ebp+__dreg+20],ecx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CABA +WABA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +and [ebp+__dreg+20],ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CABB +WABB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +and [ebp+__dreg+20],ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CABC +WABC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +and [ebp+__dreg+20],ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CAC0 - CAC7 +WAC0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov eax,ecx +mov dl,0 +mov bl,16 +ln2044: +add cx,cx +adc dl,0 +dec bl +jnz ln2044 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+20] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+20],ecx +sub edi,byte 38 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CAD0 - CAD7 +WAD0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2045: +add cx,cx +adc dl,0 +dec bl +jnz ln2045 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+20] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+20],ecx +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CAD8 - CADF +WAD8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov eax,ecx +mov dl,0 +mov bl,16 +ln2046: +add cx,cx +adc dl,0 +dec bl +jnz ln2046 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+20] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+20],ecx +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CAE0 - CAE7 +WAE0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov eax,ecx +mov dl,0 +mov bl,16 +ln2047: +add cx,cx +adc dl,0 +dec bl +jnz ln2047 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+20] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+20],ecx +sub edi,byte 44 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CAE8 - CAEF +WAE8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2048: +add cx,cx +adc dl,0 +dec bl +jnz ln2048 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+20] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+20],ecx +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CAF0 - CAF7 +WAF0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2049: +add cx,cx +adc dl,0 +dec bl +jnz ln2049 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+20] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+20],ecx +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CAF8 +WAF8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2050: +add cx,cx +adc dl,0 +dec bl +jnz ln2050 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+20] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+20],ecx +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CAF9 +WAF9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2051: +add cx,cx +adc dl,0 +dec bl +jnz ln2051 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+20] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+20],ecx +sub edi,byte 50 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CAFA +WAFA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2052: +add cx,cx +adc dl,0 +dec bl +jnz ln2052 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+20] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+20],ecx +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CAFB +WAFB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2053: +add cx,cx +adc dl,0 +dec bl +jnz ln2053 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+20] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+20],ecx +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CAFC +WAFC: +mov cx,[esi] +add esi,byte 2 +mov eax,ecx +mov dl,0 +mov bl,16 +ln2054: +add cx,cx +adc dl,0 +dec bl +jnz ln2054 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+20] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+20],ecx +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CB00 - CB07 +WB00: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+20] +adc al,[ebp+__dreg+ebx*4] +daa +mov [ebp+__dreg+20],al +lahf +mov al,0 +setc [ebp+__xflag] +jnz short ln2055 +or ch,0BFh +and ah,ch +ln2055: +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CB08 - CB0F +WB08: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+20] +dec edx +call readmemorybyte +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +adc al,bl +daa +mov ebx,eax +lahf +mov al,0 +setc [ebp+__xflag] +jnz short ln2056 +or ch,0BFh +and ah,ch +ln2056: +mov ecx,ebx +xor ebx,ebx +call writememorybyte +mov [ebp+__areg+20],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CB10 - CB17 +WB10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +and cl,[ebp+__dreg+20] +lahf +mov al,0 +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CB18 - CB1F +WB18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +and cl,[ebp+__dreg+20] +lahf +mov al,0 +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CB20 - CB27 +WB20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +and cl,[ebp+__dreg+20] +lahf +mov al,0 +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CB28 - CB2F +WB28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +and cl,[ebp+__dreg+20] +lahf +mov al,0 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CB30 - CB37 +WB30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +and cl,[ebp+__dreg+20] +lahf +mov al,0 +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CB38 +WB38: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +and cl,[ebp+__dreg+20] +lahf +mov al,0 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CB39 +WB39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +and cl,[ebp+__dreg+20] +lahf +mov al,0 +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CB40 - CB47 +WB40: +and ebx,byte 7 +mov ecx,[ebp+__reg+20] +mov edx,[ebp+__reg+0+ebx*4] +mov [ebp+__reg+20],edx +mov [ebp+__reg+0+ebx*4],ecx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CB48 - CB4F +WB48: +and ebx,byte 7 +mov ecx,[ebp+__reg+52] +mov edx,[ebp+__reg+32+ebx*4] +mov [ebp+__reg+52],edx +mov [ebp+__reg+32+ebx*4],ecx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CB50 - CB57 +WB50: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +and cx,[ebp+__dreg+20] +lahf +mov al,0 +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CB58 - CB5F +WB58: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +and cx,[ebp+__dreg+20] +lahf +mov al,0 +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CB60 - CB67 +WB60: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +and cx,[ebp+__dreg+20] +lahf +mov al,0 +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CB68 - CB6F +WB68: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +and cx,[ebp+__dreg+20] +lahf +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CB70 - CB77 +WB70: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +and cx,[ebp+__dreg+20] +lahf +mov al,0 +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CB78 +WB78: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +and cx,[ebp+__dreg+20] +lahf +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CB79 +WB79: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +and cx,[ebp+__dreg+20] +lahf +mov al,0 +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CB88 - CB8F +WB88: +and ebx,byte 7 +mov ecx,[ebp+__reg+20] +mov edx,[ebp+__reg+32+ebx*4] +mov [ebp+__reg+20],edx +mov [ebp+__reg+32+ebx*4],ecx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CB90 - CB97 +WB90: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +and ecx,[ebp+__dreg+20] +lahf +mov al,0 +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CB98 - CB9F +WB98: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +and ecx,[ebp+__dreg+20] +lahf +mov al,0 +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CBA0 - CBA7 +WBA0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +and ecx,[ebp+__dreg+20] +lahf +mov al,0 +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CBA8 - CBAF +WBA8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +and ecx,[ebp+__dreg+20] +lahf +mov al,0 +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CBB0 - CBB7 +WBB0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +and ecx,[ebp+__dreg+20] +lahf +mov al,0 +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CBB8 +WBB8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +and ecx,[ebp+__dreg+20] +lahf +mov al,0 +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CBB9 +WBB9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +and ecx,[ebp+__dreg+20] +lahf +mov al,0 +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CBC0 - CBC7 +WBC0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov eax,ecx +mov dl,0 +mov bl,16 +ln2057: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln2057 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+20] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+20],ecx +sub edi,byte 38 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CBD0 - CBD7 +WBD0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2058: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln2058 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+20] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+20],ecx +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CBD8 - CBDF +WBD8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov eax,ecx +mov dl,0 +mov bl,16 +ln2059: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln2059 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+20] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+20],ecx +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CBE0 - CBE7 +WBE0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov eax,ecx +mov dl,0 +mov bl,16 +ln2060: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln2060 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+20] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+20],ecx +sub edi,byte 44 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CBE8 - CBEF +WBE8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2061: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln2061 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+20] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+20],ecx +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CBF0 - CBF7 +WBF0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2062: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln2062 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+20] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+20],ecx +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CBF8 +WBF8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2063: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln2063 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+20] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+20],ecx +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CBF9 +WBF9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2064: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln2064 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+20] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+20],ecx +sub edi,byte 50 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CBFA +WBFA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2065: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln2065 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+20] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+20],ecx +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CBFB +WBFB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2066: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln2066 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+20] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+20],ecx +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CBFC +WBFC: +mov cx,[esi] +add esi,byte 2 +mov eax,ecx +mov dl,0 +mov bl,16 +ln2067: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln2067 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+20] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+20],ecx +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CC00 - CC07 +WC00: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +and [ebp+__dreg+24],cl +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CC10 - CC17 +WC10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +and [ebp+__dreg+24],cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CC18 - CC1F +WC18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +and [ebp+__dreg+24],cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CC20 - CC27 +WC20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +and [ebp+__dreg+24],cl +lahf +mov al,0 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CC28 - CC2F +WC28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +and [ebp+__dreg+24],cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CC30 - CC37 +WC30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +and [ebp+__dreg+24],cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CC38 +WC38: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +and [ebp+__dreg+24],cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CC39 +WC39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +and [ebp+__dreg+24],cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CC3A +WC3A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +and [ebp+__dreg+24],cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CC3B +WC3B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +and [ebp+__dreg+24],cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CC3C +WC3C: +mov cx,[esi] +add esi,byte 2 +and [ebp+__dreg+24],cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CC40 - CC47 +WC40: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +and [ebp+__dreg+24],cx +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CC50 - CC57 +WC50: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +and [ebp+__dreg+24],cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CC58 - CC5F +WC58: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +and [ebp+__dreg+24],cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CC60 - CC67 +WC60: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +and [ebp+__dreg+24],cx +lahf +mov al,0 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CC68 - CC6F +WC68: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +and [ebp+__dreg+24],cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CC70 - CC77 +WC70: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +and [ebp+__dreg+24],cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CC78 +WC78: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +and [ebp+__dreg+24],cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CC79 +WC79: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +and [ebp+__dreg+24],cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CC7A +WC7A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +and [ebp+__dreg+24],cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CC7B +WC7B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +and [ebp+__dreg+24],cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CC7C +WC7C: +mov cx,[esi] +add esi,byte 2 +and [ebp+__dreg+24],cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CC80 - CC87 +WC80: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +and [ebp+__dreg+24],ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CC90 - CC97 +WC90: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +and [ebp+__dreg+24],ecx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CC98 - CC9F +WC98: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +and [ebp+__dreg+24],ecx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CCA0 - CCA7 +WCA0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +and [ebp+__dreg+24],ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CCA8 - CCAF +WCA8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +and [ebp+__dreg+24],ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CCB0 - CCB7 +WCB0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +and [ebp+__dreg+24],ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CCB8 +WCB8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +and [ebp+__dreg+24],ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CCB9 +WCB9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +and [ebp+__dreg+24],ecx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CCBA +WCBA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +and [ebp+__dreg+24],ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CCBB +WCBB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +and [ebp+__dreg+24],ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CCBC +WCBC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +and [ebp+__dreg+24],ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CCC0 - CCC7 +WCC0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov eax,ecx +mov dl,0 +mov bl,16 +ln2068: +add cx,cx +adc dl,0 +dec bl +jnz ln2068 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+24] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+24],ecx +sub edi,byte 38 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CCD0 - CCD7 +WCD0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2069: +add cx,cx +adc dl,0 +dec bl +jnz ln2069 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+24] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+24],ecx +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CCD8 - CCDF +WCD8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov eax,ecx +mov dl,0 +mov bl,16 +ln2070: +add cx,cx +adc dl,0 +dec bl +jnz ln2070 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+24] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+24],ecx +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CCE0 - CCE7 +WCE0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov eax,ecx +mov dl,0 +mov bl,16 +ln2071: +add cx,cx +adc dl,0 +dec bl +jnz ln2071 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+24] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+24],ecx +sub edi,byte 44 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CCE8 - CCEF +WCE8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2072: +add cx,cx +adc dl,0 +dec bl +jnz ln2072 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+24] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+24],ecx +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CCF0 - CCF7 +WCF0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2073: +add cx,cx +adc dl,0 +dec bl +jnz ln2073 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+24] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+24],ecx +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CCF8 +WCF8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2074: +add cx,cx +adc dl,0 +dec bl +jnz ln2074 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+24] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+24],ecx +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CCF9 +WCF9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2075: +add cx,cx +adc dl,0 +dec bl +jnz ln2075 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+24] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+24],ecx +sub edi,byte 50 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CCFA +WCFA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2076: +add cx,cx +adc dl,0 +dec bl +jnz ln2076 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+24] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+24],ecx +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CCFB +WCFB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2077: +add cx,cx +adc dl,0 +dec bl +jnz ln2077 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+24] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+24],ecx +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CCFC +WCFC: +mov cx,[esi] +add esi,byte 2 +mov eax,ecx +mov dl,0 +mov bl,16 +ln2078: +add cx,cx +adc dl,0 +dec bl +jnz ln2078 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+24] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+24],ecx +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CD00 - CD07 +WD00: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+24] +adc al,[ebp+__dreg+ebx*4] +daa +mov [ebp+__dreg+24],al +lahf +mov al,0 +setc [ebp+__xflag] +jnz short ln2079 +or ch,0BFh +and ah,ch +ln2079: +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CD08 - CD0F +WD08: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+24] +dec edx +call readmemorybyte +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +adc al,bl +daa +mov ebx,eax +lahf +mov al,0 +setc [ebp+__xflag] +jnz short ln2080 +or ch,0BFh +and ah,ch +ln2080: +mov ecx,ebx +xor ebx,ebx +call writememorybyte +mov [ebp+__areg+24],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CD10 - CD17 +WD10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +and cl,[ebp+__dreg+24] +lahf +mov al,0 +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CD18 - CD1F +WD18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +and cl,[ebp+__dreg+24] +lahf +mov al,0 +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CD20 - CD27 +WD20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +and cl,[ebp+__dreg+24] +lahf +mov al,0 +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CD28 - CD2F +WD28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +and cl,[ebp+__dreg+24] +lahf +mov al,0 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CD30 - CD37 +WD30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +and cl,[ebp+__dreg+24] +lahf +mov al,0 +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CD38 +WD38: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +and cl,[ebp+__dreg+24] +lahf +mov al,0 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CD39 +WD39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +and cl,[ebp+__dreg+24] +lahf +mov al,0 +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CD40 - CD47 +WD40: +and ebx,byte 7 +mov ecx,[ebp+__reg+24] +mov edx,[ebp+__reg+0+ebx*4] +mov [ebp+__reg+24],edx +mov [ebp+__reg+0+ebx*4],ecx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CD48 - CD4F +WD48: +and ebx,byte 7 +mov ecx,[ebp+__reg+56] +mov edx,[ebp+__reg+32+ebx*4] +mov [ebp+__reg+56],edx +mov [ebp+__reg+32+ebx*4],ecx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CD50 - CD57 +WD50: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +and cx,[ebp+__dreg+24] +lahf +mov al,0 +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CD58 - CD5F +WD58: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +and cx,[ebp+__dreg+24] +lahf +mov al,0 +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CD60 - CD67 +WD60: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +and cx,[ebp+__dreg+24] +lahf +mov al,0 +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CD68 - CD6F +WD68: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +and cx,[ebp+__dreg+24] +lahf +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CD70 - CD77 +WD70: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +and cx,[ebp+__dreg+24] +lahf +mov al,0 +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CD78 +WD78: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +and cx,[ebp+__dreg+24] +lahf +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CD79 +WD79: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +and cx,[ebp+__dreg+24] +lahf +mov al,0 +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CD88 - CD8F +WD88: +and ebx,byte 7 +mov ecx,[ebp+__reg+24] +mov edx,[ebp+__reg+32+ebx*4] +mov [ebp+__reg+24],edx +mov [ebp+__reg+32+ebx*4],ecx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CD90 - CD97 +WD90: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +and ecx,[ebp+__dreg+24] +lahf +mov al,0 +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CD98 - CD9F +WD98: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +and ecx,[ebp+__dreg+24] +lahf +mov al,0 +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CDA0 - CDA7 +WDA0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +and ecx,[ebp+__dreg+24] +lahf +mov al,0 +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CDA8 - CDAF +WDA8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +and ecx,[ebp+__dreg+24] +lahf +mov al,0 +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CDB0 - CDB7 +WDB0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +and ecx,[ebp+__dreg+24] +lahf +mov al,0 +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CDB8 +WDB8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +and ecx,[ebp+__dreg+24] +lahf +mov al,0 +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CDB9 +WDB9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +and ecx,[ebp+__dreg+24] +lahf +mov al,0 +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CDC0 - CDC7 +WDC0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov eax,ecx +mov dl,0 +mov bl,16 +ln2081: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln2081 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+24] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+24],ecx +sub edi,byte 38 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CDD0 - CDD7 +WDD0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2082: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln2082 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+24] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+24],ecx +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CDD8 - CDDF +WDD8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov eax,ecx +mov dl,0 +mov bl,16 +ln2083: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln2083 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+24] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+24],ecx +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CDE0 - CDE7 +WDE0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov eax,ecx +mov dl,0 +mov bl,16 +ln2084: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln2084 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+24] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+24],ecx +sub edi,byte 44 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CDE8 - CDEF +WDE8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2085: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln2085 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+24] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+24],ecx +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CDF0 - CDF7 +WDF0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2086: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln2086 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+24] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+24],ecx +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CDF8 +WDF8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2087: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln2087 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+24] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+24],ecx +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CDF9 +WDF9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2088: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln2088 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+24] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+24],ecx +sub edi,byte 50 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CDFA +WDFA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2089: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln2089 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+24] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+24],ecx +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CDFB +WDFB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2090: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln2090 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+24] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+24],ecx +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CDFC +WDFC: +mov cx,[esi] +add esi,byte 2 +mov eax,ecx +mov dl,0 +mov bl,16 +ln2091: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln2091 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+24] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+24],ecx +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CE00 - CE07 +WE00: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +and [ebp+__dreg+28],cl +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CE10 - CE17 +WE10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +and [ebp+__dreg+28],cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CE18 - CE1F +WE18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +and [ebp+__dreg+28],cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CE20 - CE27 +WE20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +and [ebp+__dreg+28],cl +lahf +mov al,0 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CE28 - CE2F +WE28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +and [ebp+__dreg+28],cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CE30 - CE37 +WE30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +and [ebp+__dreg+28],cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CE38 +WE38: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +and [ebp+__dreg+28],cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CE39 +WE39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +and [ebp+__dreg+28],cl +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CE3A +WE3A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +and [ebp+__dreg+28],cl +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CE3B +WE3B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +and [ebp+__dreg+28],cl +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CE3C +WE3C: +mov cx,[esi] +add esi,byte 2 +and [ebp+__dreg+28],cl +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CE40 - CE47 +WE40: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +and [ebp+__dreg+28],cx +lahf +mov al,0 +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CE50 - CE57 +WE50: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +and [ebp+__dreg+28],cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CE58 - CE5F +WE58: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +and [ebp+__dreg+28],cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CE60 - CE67 +WE60: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +and [ebp+__dreg+28],cx +lahf +mov al,0 +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CE68 - CE6F +WE68: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +and [ebp+__dreg+28],cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CE70 - CE77 +WE70: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +and [ebp+__dreg+28],cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CE78 +WE78: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +and [ebp+__dreg+28],cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CE79 +WE79: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +and [ebp+__dreg+28],cx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CE7A +WE7A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +and [ebp+__dreg+28],cx +lahf +mov al,0 +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CE7B +WE7B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +and [ebp+__dreg+28],cx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CE7C +WE7C: +mov cx,[esi] +add esi,byte 2 +and [ebp+__dreg+28],cx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CE80 - CE87 +WE80: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +and [ebp+__dreg+28],ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CE90 - CE97 +WE90: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +and [ebp+__dreg+28],ecx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CE98 - CE9F +WE98: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +and [ebp+__dreg+28],ecx +lahf +mov al,0 +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CEA0 - CEA7 +WEA0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +and [ebp+__dreg+28],ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CEA8 - CEAF +WEA8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +and [ebp+__dreg+28],ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CEB0 - CEB7 +WEB0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +and [ebp+__dreg+28],ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CEB8 +WEB8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +and [ebp+__dreg+28],ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CEB9 +WEB9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +and [ebp+__dreg+28],ecx +lahf +mov al,0 +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CEBA +WEBA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +and [ebp+__dreg+28],ecx +lahf +mov al,0 +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CEBB +WEBB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +and [ebp+__dreg+28],ecx +lahf +mov al,0 +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CEBC +WEBC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +and [ebp+__dreg+28],ecx +lahf +mov al,0 +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CEC0 - CEC7 +WEC0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov eax,ecx +mov dl,0 +mov bl,16 +ln2092: +add cx,cx +adc dl,0 +dec bl +jnz ln2092 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+28] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+28],ecx +sub edi,byte 38 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CED0 - CED7 +WED0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2093: +add cx,cx +adc dl,0 +dec bl +jnz ln2093 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+28] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+28],ecx +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CED8 - CEDF +WED8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov eax,ecx +mov dl,0 +mov bl,16 +ln2094: +add cx,cx +adc dl,0 +dec bl +jnz ln2094 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+28] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+28],ecx +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CEE0 - CEE7 +WEE0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov eax,ecx +mov dl,0 +mov bl,16 +ln2095: +add cx,cx +adc dl,0 +dec bl +jnz ln2095 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+28] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+28],ecx +sub edi,byte 44 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CEE8 - CEEF +WEE8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2096: +add cx,cx +adc dl,0 +dec bl +jnz ln2096 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+28] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+28],ecx +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CEF0 - CEF7 +WEF0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2097: +add cx,cx +adc dl,0 +dec bl +jnz ln2097 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+28] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+28],ecx +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CEF8 +WEF8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2098: +add cx,cx +adc dl,0 +dec bl +jnz ln2098 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+28] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+28],ecx +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CEF9 +WEF9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2099: +add cx,cx +adc dl,0 +dec bl +jnz ln2099 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+28] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+28],ecx +sub edi,byte 50 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CEFA +WEFA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2100: +add cx,cx +adc dl,0 +dec bl +jnz ln2100 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+28] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+28],ecx +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CEFB +WEFB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2101: +add cx,cx +adc dl,0 +dec bl +jnz ln2101 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+28] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+28],ecx +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CEFC +WEFC: +mov cx,[esi] +add esi,byte 2 +mov eax,ecx +mov dl,0 +mov bl,16 +ln2102: +add cx,cx +adc dl,0 +dec bl +jnz ln2102 +and edx,byte 127 +sub edi,edx +sub edi,edx +mul word[ebp+__dreg+28] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+28],ecx +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CF00 - CF07 +WF00: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+28] +adc al,[ebp+__dreg+ebx*4] +daa +mov [ebp+__dreg+28],al +lahf +mov al,0 +setc [ebp+__xflag] +jnz short ln2103 +or ch,0BFh +and ah,ch +ln2103: +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CF08 - CF0F +WF08: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+28] +sub edx,byte 2 +call readmemorybyte +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +adc al,bl +daa +mov ebx,eax +lahf +mov al,0 +setc [ebp+__xflag] +jnz short ln2104 +or ch,0BFh +and ah,ch +ln2104: +mov ecx,ebx +xor ebx,ebx +call writememorybyte +mov [ebp+__areg+28],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CF10 - CF17 +WF10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +and cl,[ebp+__dreg+28] +lahf +mov al,0 +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CF18 - CF1F +WF18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +and cl,[ebp+__dreg+28] +lahf +mov al,0 +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CF20 - CF27 +WF20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +and cl,[ebp+__dreg+28] +lahf +mov al,0 +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CF28 - CF2F +WF28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +and cl,[ebp+__dreg+28] +lahf +mov al,0 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CF30 - CF37 +WF30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +and cl,[ebp+__dreg+28] +lahf +mov al,0 +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CF38 +WF38: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +and cl,[ebp+__dreg+28] +lahf +mov al,0 +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CF39 +WF39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +and cl,[ebp+__dreg+28] +lahf +mov al,0 +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CF40 - CF47 +WF40: +and ebx,byte 7 +mov ecx,[ebp+__reg+28] +mov edx,[ebp+__reg+0+ebx*4] +mov [ebp+__reg+28],edx +mov [ebp+__reg+0+ebx*4],ecx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CF48 - CF4F +WF48: +and ebx,byte 7 +mov ecx,[ebp+__reg+60] +mov edx,[ebp+__reg+32+ebx*4] +mov [ebp+__reg+60],edx +mov [ebp+__reg+32+ebx*4],ecx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CF50 - CF57 +WF50: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +and cx,[ebp+__dreg+28] +lahf +mov al,0 +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CF58 - CF5F +WF58: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +and cx,[ebp+__dreg+28] +lahf +mov al,0 +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CF60 - CF67 +WF60: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +and cx,[ebp+__dreg+28] +lahf +mov al,0 +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CF68 - CF6F +WF68: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +and cx,[ebp+__dreg+28] +lahf +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CF70 - CF77 +WF70: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +and cx,[ebp+__dreg+28] +lahf +mov al,0 +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CF78 +WF78: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +and cx,[ebp+__dreg+28] +lahf +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CF79 +WF79: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +and cx,[ebp+__dreg+28] +lahf +mov al,0 +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CF88 - CF8F +WF88: +and ebx,byte 7 +mov ecx,[ebp+__reg+28] +mov edx,[ebp+__reg+32+ebx*4] +mov [ebp+__reg+28],edx +mov [ebp+__reg+32+ebx*4],ecx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CF90 - CF97 +WF90: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +and ecx,[ebp+__dreg+28] +lahf +mov al,0 +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CF98 - CF9F +WF98: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +and ecx,[ebp+__dreg+28] +lahf +mov al,0 +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CFA0 - CFA7 +WFA0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +and ecx,[ebp+__dreg+28] +lahf +mov al,0 +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CFA8 - CFAF +WFA8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +and ecx,[ebp+__dreg+28] +lahf +mov al,0 +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CFB0 - CFB7 +WFB0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +and ecx,[ebp+__dreg+28] +lahf +mov al,0 +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CFB8 +WFB8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +and ecx,[ebp+__dreg+28] +lahf +mov al,0 +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CFB9 +WFB9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +and ecx,[ebp+__dreg+28] +lahf +mov al,0 +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CFC0 - CFC7 +WFC0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +mov eax,ecx +mov dl,0 +mov bl,16 +ln2105: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln2105 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+28] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+28],ecx +sub edi,byte 38 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CFD0 - CFD7 +WFD0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2106: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln2106 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+28] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+28],ecx +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CFD8 - CFDF +WFD8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +mov eax,ecx +mov dl,0 +mov bl,16 +ln2107: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln2107 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+28] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+28],ecx +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CFE0 - CFE7 +WFE0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov eax,ecx +mov dl,0 +mov bl,16 +ln2108: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln2108 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+28] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+28],ecx +sub edi,byte 44 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CFE8 - CFEF +WFE8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2109: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln2109 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+28] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+28],ecx +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes CFF0 - CFF7 +WFF0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2110: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln2110 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+28] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+28],ecx +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CFF8 +WFF8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2111: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln2111 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+28] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+28],ecx +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CFF9 +WFF9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2112: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln2112 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+28] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+28],ecx +sub edi,byte 50 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CFFA +WFFA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2113: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln2113 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+28] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+28],ecx +sub edi,byte 46 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CFFB +WFFB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +mov eax,ecx +mov dl,0 +mov bl,16 +ln2114: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln2114 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+28] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+28],ecx +sub edi,byte 48 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode CFFC +WFFC: +mov cx,[esi] +add esi,byte 2 +mov eax,ecx +mov dl,0 +mov bl,16 +ln2115: +add cx,cx +seto dh +add dl,dh +dec bl +jnz ln2115 +and edx,byte 127 +sub edi,edx +sub edi,edx +imul word[ebp+__dreg+28] +shl edx,16 +and eax,0FFFFh +mov ecx,edx +or ecx,eax +lahf +mov al,0 +mov [ebp+__dreg+28],ecx +sub edi,byte 42 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D000 - D007 +X000: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +add [ebp+__dreg+0],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D010 - D017 +X010: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +add [ebp+__dreg+0],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D018 - D01F +X018: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +add [ebp+__dreg+0],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D020 - D027 +X020: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +add [ebp+__dreg+0],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D028 - D02F +X028: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +add [ebp+__dreg+0],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D030 - D037 +X030: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +add [ebp+__dreg+0],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D038 +X038: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +add [ebp+__dreg+0],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D039 +X039: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +add [ebp+__dreg+0],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D03A +X03A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +add [ebp+__dreg+0],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D03B +X03B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +add [ebp+__dreg+0],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D03C +X03C: +mov cx,[esi] +add esi,byte 2 +add [ebp+__dreg+0],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D040 - D047 +X040: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +add [ebp+__dreg+0],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D048 - D04F +X048: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +add [ebp+__dreg+0],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D050 - D057 +X050: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add [ebp+__dreg+0],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D058 - D05F +X058: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +add [ebp+__dreg+0],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D060 - D067 +X060: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +add [ebp+__dreg+0],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D068 - D06F +X068: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +add [ebp+__dreg+0],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D070 - D077 +X070: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +add [ebp+__dreg+0],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D078 +X078: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +add [ebp+__dreg+0],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D079 +X079: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +add [ebp+__dreg+0],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D07A +X07A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +add [ebp+__dreg+0],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D07B +X07B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +add [ebp+__dreg+0],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D07C +X07C: +mov cx,[esi] +add esi,byte 2 +add [ebp+__dreg+0],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D080 - D087 +X080: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +add [ebp+__dreg+0],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D088 - D08F +X088: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +add [ebp+__dreg+0],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D090 - D097 +X090: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add [ebp+__dreg+0],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D098 - D09F +X098: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +add [ebp+__dreg+0],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D0A0 - D0A7 +X0A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +add [ebp+__dreg+0],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D0A8 - D0AF +X0A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add [ebp+__dreg+0],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D0B0 - D0B7 +X0B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add [ebp+__dreg+0],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D0B8 +X0B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +add [ebp+__dreg+0],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D0B9 +X0B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +add [ebp+__dreg+0],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D0BA +X0BA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +add [ebp+__dreg+0],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D0BB +X0BB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +add [ebp+__dreg+0],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D0BC +X0BC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +add [ebp+__dreg+0],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D0C0 - D0C7 +X0C0: +and ebx,byte 7 +movsx ecx,word[ebp+__dreg+ebx*4] +add [ebp+__areg+0],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D0C8 - D0CF +X0C8: +and ebx,byte 7 +movsx ecx,word[ebp+__areg+ebx*4] +add [ebp+__areg+0],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D0D0 - D0D7 +X0D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +add [ebp+__areg+0],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D0D8 - D0DF +X0D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +add [ebp+__areg+0],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D0E0 - D0E7 +X0E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+ebx*4],edx +add [ebp+__areg+0],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D0E8 - D0EF +X0E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +add [ebp+__areg+0],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D0F0 - D0F7 +X0F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +add [ebp+__areg+0],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D0F8 +X0F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +add [ebp+__areg+0],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D0F9 +X0F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +movsx ecx,cx +add [ebp+__areg+0],ecx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D0FA +X0FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +add [ebp+__areg+0],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D0FB +X0FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +add [ebp+__areg+0],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D0FC +X0FC: +movsx ecx,word[esi] +add esi,byte 2 +add [ebp+__areg+0],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D100 - D107 +X100: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+0] +adc al,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+0],al +lahf +seto al +setc [ebp+__xflag] +jnz short ln2116 +or ch,0BFh +and ah,ch +ln2116: +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D108 - D10F +X108: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+0] +dec edx +call readmemorybyte +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +adc al,bl +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln2117 +or ch,0BFh +and ah,ch +ln2117: +mov ecx,ebx +xor ebx,ebx +call writememorybyte +mov [ebp+__areg+0],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D110 - D117 +X110: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,[ebp+__dreg+0] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D118 - D11F +X118: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,[ebp+__dreg+0] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D120 - D127 +X120: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +add cl,[ebp+__dreg+0] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D128 - D12F +X128: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,[ebp+__dreg+0] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D130 - D137 +X130: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,[ebp+__dreg+0] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D138 +X138: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +add cl,[ebp+__dreg+0] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D139 +X139: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +add cl,[ebp+__dreg+0] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D140 - D147 +X140: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+0] +adc ax,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+0],ax +lahf +seto al +setc [ebp+__xflag] +jnz short ln2118 +or ch,0BFh +and ah,ch +ln2118: +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D148 - D14F +X148: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+0] +sub edx,byte 2 +call readmemoryword +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +adc ax,bx +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln2119 +or ch,0BFh +and ah,ch +ln2119: +mov ecx,ebx +xor ebx,ebx +call writememoryword +mov [ebp+__areg+0],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D150 - D157 +X150: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,[ebp+__dreg+0] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D158 - D15F +X158: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,[ebp+__dreg+0] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D160 - D167 +X160: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +add cx,[ebp+__dreg+0] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D168 - D16F +X168: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,[ebp+__dreg+0] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D170 - D177 +X170: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,[ebp+__dreg+0] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D178 +X178: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +add cx,[ebp+__dreg+0] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D179 +X179: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +add cx,[ebp+__dreg+0] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D180 - D187 +X180: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+0] +adc eax,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+0],eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln2120 +or ch,0BFh +and ah,ch +ln2120: +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D188 - D18F +X188: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+0] +sub edx,byte 4 +call readmemorydword +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +adc eax,ebx +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln2121 +or ch,0BFh +and ah,ch +ln2121: +mov ecx,ebx +xor ebx,ebx +call writememorydword +mov [ebp+__areg+0],edx +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D190 - D197 +X190: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,[ebp+__dreg+0] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D198 - D19F +X198: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,[ebp+__dreg+0] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D1A0 - D1A7 +X1A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +add ecx,[ebp+__dreg+0] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D1A8 - D1AF +X1A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,[ebp+__dreg+0] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D1B0 - D1B7 +X1B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,[ebp+__dreg+0] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D1B8 +X1B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +add ecx,[ebp+__dreg+0] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D1B9 +X1B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +add ecx,[ebp+__dreg+0] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D1C0 - D1C7 +X1C0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +add [ebp+__areg+0],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D1C8 - D1CF +X1C8: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +add [ebp+__areg+0],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D1D0 - D1D7 +X1D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add [ebp+__areg+0],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D1D8 - D1DF +X1D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +add [ebp+__areg+0],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D1E0 - D1E7 +X1E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +add [ebp+__areg+0],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D1E8 - D1EF +X1E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add [ebp+__areg+0],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D1F0 - D1F7 +X1F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add [ebp+__areg+0],ecx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D1F8 +X1F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +add [ebp+__areg+0],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D1F9 +X1F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +add [ebp+__areg+0],ecx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D1FA +X1FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +add [ebp+__areg+0],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D1FB +X1FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +add [ebp+__areg+0],ecx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D1FC +X1FC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +add [ebp+__areg+0],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D200 - D207 +X200: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +add [ebp+__dreg+4],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D210 - D217 +X210: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +add [ebp+__dreg+4],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D218 - D21F +X218: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +add [ebp+__dreg+4],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D220 - D227 +X220: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +add [ebp+__dreg+4],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D228 - D22F +X228: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +add [ebp+__dreg+4],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D230 - D237 +X230: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +add [ebp+__dreg+4],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D238 +X238: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +add [ebp+__dreg+4],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D239 +X239: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +add [ebp+__dreg+4],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D23A +X23A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +add [ebp+__dreg+4],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D23B +X23B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +add [ebp+__dreg+4],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D23C +X23C: +mov cx,[esi] +add esi,byte 2 +add [ebp+__dreg+4],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D240 - D247 +X240: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +add [ebp+__dreg+4],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D248 - D24F +X248: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +add [ebp+__dreg+4],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D250 - D257 +X250: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add [ebp+__dreg+4],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D258 - D25F +X258: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +add [ebp+__dreg+4],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D260 - D267 +X260: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +add [ebp+__dreg+4],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D268 - D26F +X268: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +add [ebp+__dreg+4],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D270 - D277 +X270: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +add [ebp+__dreg+4],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D278 +X278: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +add [ebp+__dreg+4],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D279 +X279: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +add [ebp+__dreg+4],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D27A +X27A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +add [ebp+__dreg+4],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D27B +X27B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +add [ebp+__dreg+4],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D27C +X27C: +mov cx,[esi] +add esi,byte 2 +add [ebp+__dreg+4],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D280 - D287 +X280: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +add [ebp+__dreg+4],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D288 - D28F +X288: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +add [ebp+__dreg+4],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D290 - D297 +X290: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add [ebp+__dreg+4],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D298 - D29F +X298: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +add [ebp+__dreg+4],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D2A0 - D2A7 +X2A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +add [ebp+__dreg+4],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D2A8 - D2AF +X2A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add [ebp+__dreg+4],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D2B0 - D2B7 +X2B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add [ebp+__dreg+4],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D2B8 +X2B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +add [ebp+__dreg+4],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D2B9 +X2B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +add [ebp+__dreg+4],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D2BA +X2BA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +add [ebp+__dreg+4],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D2BB +X2BB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +add [ebp+__dreg+4],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D2BC +X2BC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +add [ebp+__dreg+4],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D2C0 - D2C7 +X2C0: +and ebx,byte 7 +movsx ecx,word[ebp+__dreg+ebx*4] +add [ebp+__areg+4],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D2C8 - D2CF +X2C8: +and ebx,byte 7 +movsx ecx,word[ebp+__areg+ebx*4] +add [ebp+__areg+4],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D2D0 - D2D7 +X2D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +add [ebp+__areg+4],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D2D8 - D2DF +X2D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +add [ebp+__areg+4],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D2E0 - D2E7 +X2E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+ebx*4],edx +add [ebp+__areg+4],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D2E8 - D2EF +X2E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +add [ebp+__areg+4],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D2F0 - D2F7 +X2F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +add [ebp+__areg+4],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D2F8 +X2F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +add [ebp+__areg+4],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D2F9 +X2F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +movsx ecx,cx +add [ebp+__areg+4],ecx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D2FA +X2FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +add [ebp+__areg+4],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D2FB +X2FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +add [ebp+__areg+4],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D2FC +X2FC: +movsx ecx,word[esi] +add esi,byte 2 +add [ebp+__areg+4],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D300 - D307 +X300: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+4] +adc al,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+4],al +lahf +seto al +setc [ebp+__xflag] +jnz short ln2122 +or ch,0BFh +and ah,ch +ln2122: +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D308 - D30F +X308: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+4] +dec edx +call readmemorybyte +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +adc al,bl +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln2123 +or ch,0BFh +and ah,ch +ln2123: +mov ecx,ebx +xor ebx,ebx +call writememorybyte +mov [ebp+__areg+4],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D310 - D317 +X310: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,[ebp+__dreg+4] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D318 - D31F +X318: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,[ebp+__dreg+4] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D320 - D327 +X320: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +add cl,[ebp+__dreg+4] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D328 - D32F +X328: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,[ebp+__dreg+4] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D330 - D337 +X330: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,[ebp+__dreg+4] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D338 +X338: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +add cl,[ebp+__dreg+4] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D339 +X339: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +add cl,[ebp+__dreg+4] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D340 - D347 +X340: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+4] +adc ax,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+4],ax +lahf +seto al +setc [ebp+__xflag] +jnz short ln2124 +or ch,0BFh +and ah,ch +ln2124: +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D348 - D34F +X348: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+4] +sub edx,byte 2 +call readmemoryword +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +adc ax,bx +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln2125 +or ch,0BFh +and ah,ch +ln2125: +mov ecx,ebx +xor ebx,ebx +call writememoryword +mov [ebp+__areg+4],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D350 - D357 +X350: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,[ebp+__dreg+4] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D358 - D35F +X358: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,[ebp+__dreg+4] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D360 - D367 +X360: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +add cx,[ebp+__dreg+4] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D368 - D36F +X368: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,[ebp+__dreg+4] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D370 - D377 +X370: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,[ebp+__dreg+4] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D378 +X378: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +add cx,[ebp+__dreg+4] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D379 +X379: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +add cx,[ebp+__dreg+4] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D380 - D387 +X380: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+4] +adc eax,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+4],eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln2126 +or ch,0BFh +and ah,ch +ln2126: +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D388 - D38F +X388: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+4] +sub edx,byte 4 +call readmemorydword +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +adc eax,ebx +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln2127 +or ch,0BFh +and ah,ch +ln2127: +mov ecx,ebx +xor ebx,ebx +call writememorydword +mov [ebp+__areg+4],edx +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D390 - D397 +X390: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,[ebp+__dreg+4] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D398 - D39F +X398: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,[ebp+__dreg+4] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D3A0 - D3A7 +X3A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +add ecx,[ebp+__dreg+4] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D3A8 - D3AF +X3A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,[ebp+__dreg+4] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D3B0 - D3B7 +X3B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,[ebp+__dreg+4] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D3B8 +X3B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +add ecx,[ebp+__dreg+4] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D3B9 +X3B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +add ecx,[ebp+__dreg+4] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D3C0 - D3C7 +X3C0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +add [ebp+__areg+4],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D3C8 - D3CF +X3C8: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +add [ebp+__areg+4],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D3D0 - D3D7 +X3D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add [ebp+__areg+4],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D3D8 - D3DF +X3D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +add [ebp+__areg+4],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D3E0 - D3E7 +X3E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +add [ebp+__areg+4],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D3E8 - D3EF +X3E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add [ebp+__areg+4],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D3F0 - D3F7 +X3F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add [ebp+__areg+4],ecx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D3F8 +X3F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +add [ebp+__areg+4],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D3F9 +X3F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +add [ebp+__areg+4],ecx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D3FA +X3FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +add [ebp+__areg+4],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D3FB +X3FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +add [ebp+__areg+4],ecx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D3FC +X3FC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +add [ebp+__areg+4],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D400 - D407 +X400: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +add [ebp+__dreg+8],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D410 - D417 +X410: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +add [ebp+__dreg+8],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D418 - D41F +X418: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +add [ebp+__dreg+8],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D420 - D427 +X420: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +add [ebp+__dreg+8],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D428 - D42F +X428: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +add [ebp+__dreg+8],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D430 - D437 +X430: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +add [ebp+__dreg+8],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D438 +X438: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +add [ebp+__dreg+8],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D439 +X439: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +add [ebp+__dreg+8],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D43A +X43A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +add [ebp+__dreg+8],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D43B +X43B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +add [ebp+__dreg+8],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D43C +X43C: +mov cx,[esi] +add esi,byte 2 +add [ebp+__dreg+8],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D440 - D447 +X440: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +add [ebp+__dreg+8],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D448 - D44F +X448: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +add [ebp+__dreg+8],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D450 - D457 +X450: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add [ebp+__dreg+8],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D458 - D45F +X458: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +add [ebp+__dreg+8],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D460 - D467 +X460: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +add [ebp+__dreg+8],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D468 - D46F +X468: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +add [ebp+__dreg+8],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D470 - D477 +X470: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +add [ebp+__dreg+8],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D478 +X478: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +add [ebp+__dreg+8],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D479 +X479: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +add [ebp+__dreg+8],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D47A +X47A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +add [ebp+__dreg+8],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D47B +X47B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +add [ebp+__dreg+8],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D47C +X47C: +mov cx,[esi] +add esi,byte 2 +add [ebp+__dreg+8],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D480 - D487 +X480: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +add [ebp+__dreg+8],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D488 - D48F +X488: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +add [ebp+__dreg+8],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D490 - D497 +X490: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add [ebp+__dreg+8],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D498 - D49F +X498: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +add [ebp+__dreg+8],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D4A0 - D4A7 +X4A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +add [ebp+__dreg+8],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D4A8 - D4AF +X4A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add [ebp+__dreg+8],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D4B0 - D4B7 +X4B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add [ebp+__dreg+8],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D4B8 +X4B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +add [ebp+__dreg+8],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D4B9 +X4B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +add [ebp+__dreg+8],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D4BA +X4BA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +add [ebp+__dreg+8],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D4BB +X4BB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +add [ebp+__dreg+8],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D4BC +X4BC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +add [ebp+__dreg+8],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D4C0 - D4C7 +X4C0: +and ebx,byte 7 +movsx ecx,word[ebp+__dreg+ebx*4] +add [ebp+__areg+8],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D4C8 - D4CF +X4C8: +and ebx,byte 7 +movsx ecx,word[ebp+__areg+ebx*4] +add [ebp+__areg+8],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D4D0 - D4D7 +X4D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +add [ebp+__areg+8],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D4D8 - D4DF +X4D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +add [ebp+__areg+8],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D4E0 - D4E7 +X4E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+ebx*4],edx +add [ebp+__areg+8],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D4E8 - D4EF +X4E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +add [ebp+__areg+8],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D4F0 - D4F7 +X4F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +add [ebp+__areg+8],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D4F8 +X4F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +add [ebp+__areg+8],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D4F9 +X4F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +movsx ecx,cx +add [ebp+__areg+8],ecx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D4FA +X4FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +add [ebp+__areg+8],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D4FB +X4FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +add [ebp+__areg+8],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D4FC +X4FC: +movsx ecx,word[esi] +add esi,byte 2 +add [ebp+__areg+8],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D500 - D507 +X500: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+8] +adc al,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+8],al +lahf +seto al +setc [ebp+__xflag] +jnz short ln2128 +or ch,0BFh +and ah,ch +ln2128: +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D508 - D50F +X508: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+8] +dec edx +call readmemorybyte +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +adc al,bl +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln2129 +or ch,0BFh +and ah,ch +ln2129: +mov ecx,ebx +xor ebx,ebx +call writememorybyte +mov [ebp+__areg+8],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D510 - D517 +X510: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,[ebp+__dreg+8] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D518 - D51F +X518: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,[ebp+__dreg+8] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D520 - D527 +X520: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +add cl,[ebp+__dreg+8] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D528 - D52F +X528: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,[ebp+__dreg+8] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D530 - D537 +X530: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,[ebp+__dreg+8] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D538 +X538: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +add cl,[ebp+__dreg+8] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D539 +X539: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +add cl,[ebp+__dreg+8] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D540 - D547 +X540: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+8] +adc ax,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+8],ax +lahf +seto al +setc [ebp+__xflag] +jnz short ln2130 +or ch,0BFh +and ah,ch +ln2130: +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D548 - D54F +X548: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+8] +sub edx,byte 2 +call readmemoryword +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +adc ax,bx +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln2131 +or ch,0BFh +and ah,ch +ln2131: +mov ecx,ebx +xor ebx,ebx +call writememoryword +mov [ebp+__areg+8],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D550 - D557 +X550: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,[ebp+__dreg+8] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D558 - D55F +X558: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,[ebp+__dreg+8] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D560 - D567 +X560: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +add cx,[ebp+__dreg+8] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D568 - D56F +X568: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,[ebp+__dreg+8] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D570 - D577 +X570: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,[ebp+__dreg+8] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D578 +X578: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +add cx,[ebp+__dreg+8] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D579 +X579: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +add cx,[ebp+__dreg+8] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D580 - D587 +X580: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+8] +adc eax,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+8],eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln2132 +or ch,0BFh +and ah,ch +ln2132: +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D588 - D58F +X588: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+8] +sub edx,byte 4 +call readmemorydword +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +adc eax,ebx +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln2133 +or ch,0BFh +and ah,ch +ln2133: +mov ecx,ebx +xor ebx,ebx +call writememorydword +mov [ebp+__areg+8],edx +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D590 - D597 +X590: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,[ebp+__dreg+8] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D598 - D59F +X598: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,[ebp+__dreg+8] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D5A0 - D5A7 +X5A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +add ecx,[ebp+__dreg+8] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D5A8 - D5AF +X5A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,[ebp+__dreg+8] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D5B0 - D5B7 +X5B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,[ebp+__dreg+8] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D5B8 +X5B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +add ecx,[ebp+__dreg+8] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D5B9 +X5B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +add ecx,[ebp+__dreg+8] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D5C0 - D5C7 +X5C0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +add [ebp+__areg+8],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D5C8 - D5CF +X5C8: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +add [ebp+__areg+8],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D5D0 - D5D7 +X5D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add [ebp+__areg+8],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D5D8 - D5DF +X5D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +add [ebp+__areg+8],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D5E0 - D5E7 +X5E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +add [ebp+__areg+8],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D5E8 - D5EF +X5E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add [ebp+__areg+8],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D5F0 - D5F7 +X5F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add [ebp+__areg+8],ecx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D5F8 +X5F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +add [ebp+__areg+8],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D5F9 +X5F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +add [ebp+__areg+8],ecx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D5FA +X5FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +add [ebp+__areg+8],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D5FB +X5FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +add [ebp+__areg+8],ecx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D5FC +X5FC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +add [ebp+__areg+8],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D600 - D607 +X600: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +add [ebp+__dreg+12],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D610 - D617 +X610: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +add [ebp+__dreg+12],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D618 - D61F +X618: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +add [ebp+__dreg+12],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D620 - D627 +X620: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +add [ebp+__dreg+12],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D628 - D62F +X628: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +add [ebp+__dreg+12],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D630 - D637 +X630: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +add [ebp+__dreg+12],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D638 +X638: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +add [ebp+__dreg+12],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D639 +X639: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +add [ebp+__dreg+12],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D63A +X63A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +add [ebp+__dreg+12],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D63B +X63B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +add [ebp+__dreg+12],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D63C +X63C: +mov cx,[esi] +add esi,byte 2 +add [ebp+__dreg+12],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D640 - D647 +X640: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +add [ebp+__dreg+12],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D648 - D64F +X648: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +add [ebp+__dreg+12],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D650 - D657 +X650: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add [ebp+__dreg+12],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D658 - D65F +X658: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +add [ebp+__dreg+12],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D660 - D667 +X660: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +add [ebp+__dreg+12],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D668 - D66F +X668: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +add [ebp+__dreg+12],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D670 - D677 +X670: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +add [ebp+__dreg+12],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D678 +X678: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +add [ebp+__dreg+12],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D679 +X679: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +add [ebp+__dreg+12],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D67A +X67A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +add [ebp+__dreg+12],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D67B +X67B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +add [ebp+__dreg+12],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D67C +X67C: +mov cx,[esi] +add esi,byte 2 +add [ebp+__dreg+12],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D680 - D687 +X680: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +add [ebp+__dreg+12],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D688 - D68F +X688: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +add [ebp+__dreg+12],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D690 - D697 +X690: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add [ebp+__dreg+12],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D698 - D69F +X698: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +add [ebp+__dreg+12],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D6A0 - D6A7 +X6A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +add [ebp+__dreg+12],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D6A8 - D6AF +X6A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add [ebp+__dreg+12],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D6B0 - D6B7 +X6B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add [ebp+__dreg+12],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D6B8 +X6B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +add [ebp+__dreg+12],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D6B9 +X6B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +add [ebp+__dreg+12],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D6BA +X6BA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +add [ebp+__dreg+12],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D6BB +X6BB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +add [ebp+__dreg+12],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D6BC +X6BC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +add [ebp+__dreg+12],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D6C0 - D6C7 +X6C0: +and ebx,byte 7 +movsx ecx,word[ebp+__dreg+ebx*4] +add [ebp+__areg+12],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D6C8 - D6CF +X6C8: +and ebx,byte 7 +movsx ecx,word[ebp+__areg+ebx*4] +add [ebp+__areg+12],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D6D0 - D6D7 +X6D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +add [ebp+__areg+12],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D6D8 - D6DF +X6D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +add [ebp+__areg+12],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D6E0 - D6E7 +X6E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+ebx*4],edx +add [ebp+__areg+12],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D6E8 - D6EF +X6E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +add [ebp+__areg+12],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D6F0 - D6F7 +X6F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +add [ebp+__areg+12],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D6F8 +X6F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +add [ebp+__areg+12],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D6F9 +X6F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +movsx ecx,cx +add [ebp+__areg+12],ecx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D6FA +X6FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +add [ebp+__areg+12],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D6FB +X6FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +add [ebp+__areg+12],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D6FC +X6FC: +movsx ecx,word[esi] +add esi,byte 2 +add [ebp+__areg+12],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D700 - D707 +X700: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+12] +adc al,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+12],al +lahf +seto al +setc [ebp+__xflag] +jnz short ln2134 +or ch,0BFh +and ah,ch +ln2134: +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D708 - D70F +X708: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+12] +dec edx +call readmemorybyte +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +adc al,bl +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln2135 +or ch,0BFh +and ah,ch +ln2135: +mov ecx,ebx +xor ebx,ebx +call writememorybyte +mov [ebp+__areg+12],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D710 - D717 +X710: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,[ebp+__dreg+12] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D718 - D71F +X718: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,[ebp+__dreg+12] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D720 - D727 +X720: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +add cl,[ebp+__dreg+12] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D728 - D72F +X728: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,[ebp+__dreg+12] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D730 - D737 +X730: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,[ebp+__dreg+12] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D738 +X738: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +add cl,[ebp+__dreg+12] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D739 +X739: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +add cl,[ebp+__dreg+12] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D740 - D747 +X740: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+12] +adc ax,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+12],ax +lahf +seto al +setc [ebp+__xflag] +jnz short ln2136 +or ch,0BFh +and ah,ch +ln2136: +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D748 - D74F +X748: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+12] +sub edx,byte 2 +call readmemoryword +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +adc ax,bx +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln2137 +or ch,0BFh +and ah,ch +ln2137: +mov ecx,ebx +xor ebx,ebx +call writememoryword +mov [ebp+__areg+12],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D750 - D757 +X750: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,[ebp+__dreg+12] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D758 - D75F +X758: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,[ebp+__dreg+12] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D760 - D767 +X760: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +add cx,[ebp+__dreg+12] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D768 - D76F +X768: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,[ebp+__dreg+12] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D770 - D777 +X770: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,[ebp+__dreg+12] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D778 +X778: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +add cx,[ebp+__dreg+12] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D779 +X779: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +add cx,[ebp+__dreg+12] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D780 - D787 +X780: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+12] +adc eax,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+12],eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln2138 +or ch,0BFh +and ah,ch +ln2138: +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D788 - D78F +X788: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+12] +sub edx,byte 4 +call readmemorydword +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +adc eax,ebx +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln2139 +or ch,0BFh +and ah,ch +ln2139: +mov ecx,ebx +xor ebx,ebx +call writememorydword +mov [ebp+__areg+12],edx +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D790 - D797 +X790: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,[ebp+__dreg+12] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D798 - D79F +X798: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,[ebp+__dreg+12] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D7A0 - D7A7 +X7A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +add ecx,[ebp+__dreg+12] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D7A8 - D7AF +X7A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,[ebp+__dreg+12] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D7B0 - D7B7 +X7B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,[ebp+__dreg+12] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D7B8 +X7B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +add ecx,[ebp+__dreg+12] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D7B9 +X7B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +add ecx,[ebp+__dreg+12] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D7C0 - D7C7 +X7C0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +add [ebp+__areg+12],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D7C8 - D7CF +X7C8: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +add [ebp+__areg+12],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D7D0 - D7D7 +X7D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add [ebp+__areg+12],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D7D8 - D7DF +X7D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +add [ebp+__areg+12],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D7E0 - D7E7 +X7E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +add [ebp+__areg+12],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D7E8 - D7EF +X7E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add [ebp+__areg+12],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D7F0 - D7F7 +X7F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add [ebp+__areg+12],ecx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D7F8 +X7F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +add [ebp+__areg+12],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D7F9 +X7F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +add [ebp+__areg+12],ecx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D7FA +X7FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +add [ebp+__areg+12],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D7FB +X7FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +add [ebp+__areg+12],ecx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D7FC +X7FC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +add [ebp+__areg+12],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D800 - D807 +X800: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +add [ebp+__dreg+16],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D810 - D817 +X810: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +add [ebp+__dreg+16],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D818 - D81F +X818: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +add [ebp+__dreg+16],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D820 - D827 +X820: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +add [ebp+__dreg+16],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D828 - D82F +X828: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +add [ebp+__dreg+16],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D830 - D837 +X830: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +add [ebp+__dreg+16],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D838 +X838: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +add [ebp+__dreg+16],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D839 +X839: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +add [ebp+__dreg+16],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D83A +X83A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +add [ebp+__dreg+16],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D83B +X83B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +add [ebp+__dreg+16],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D83C +X83C: +mov cx,[esi] +add esi,byte 2 +add [ebp+__dreg+16],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D840 - D847 +X840: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +add [ebp+__dreg+16],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D848 - D84F +X848: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +add [ebp+__dreg+16],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D850 - D857 +X850: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add [ebp+__dreg+16],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D858 - D85F +X858: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +add [ebp+__dreg+16],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D860 - D867 +X860: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +add [ebp+__dreg+16],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D868 - D86F +X868: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +add [ebp+__dreg+16],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D870 - D877 +X870: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +add [ebp+__dreg+16],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D878 +X878: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +add [ebp+__dreg+16],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D879 +X879: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +add [ebp+__dreg+16],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D87A +X87A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +add [ebp+__dreg+16],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D87B +X87B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +add [ebp+__dreg+16],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D87C +X87C: +mov cx,[esi] +add esi,byte 2 +add [ebp+__dreg+16],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D880 - D887 +X880: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +add [ebp+__dreg+16],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D888 - D88F +X888: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +add [ebp+__dreg+16],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D890 - D897 +X890: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add [ebp+__dreg+16],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D898 - D89F +X898: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +add [ebp+__dreg+16],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D8A0 - D8A7 +X8A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +add [ebp+__dreg+16],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D8A8 - D8AF +X8A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add [ebp+__dreg+16],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D8B0 - D8B7 +X8B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add [ebp+__dreg+16],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D8B8 +X8B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +add [ebp+__dreg+16],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D8B9 +X8B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +add [ebp+__dreg+16],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D8BA +X8BA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +add [ebp+__dreg+16],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D8BB +X8BB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +add [ebp+__dreg+16],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D8BC +X8BC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +add [ebp+__dreg+16],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D8C0 - D8C7 +X8C0: +and ebx,byte 7 +movsx ecx,word[ebp+__dreg+ebx*4] +add [ebp+__areg+16],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D8C8 - D8CF +X8C8: +and ebx,byte 7 +movsx ecx,word[ebp+__areg+ebx*4] +add [ebp+__areg+16],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D8D0 - D8D7 +X8D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +add [ebp+__areg+16],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D8D8 - D8DF +X8D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +add [ebp+__areg+16],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D8E0 - D8E7 +X8E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+ebx*4],edx +add [ebp+__areg+16],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D8E8 - D8EF +X8E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +add [ebp+__areg+16],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D8F0 - D8F7 +X8F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +add [ebp+__areg+16],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D8F8 +X8F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +add [ebp+__areg+16],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D8F9 +X8F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +movsx ecx,cx +add [ebp+__areg+16],ecx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D8FA +X8FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +add [ebp+__areg+16],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D8FB +X8FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +add [ebp+__areg+16],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D8FC +X8FC: +movsx ecx,word[esi] +add esi,byte 2 +add [ebp+__areg+16],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D900 - D907 +X900: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+16] +adc al,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+16],al +lahf +seto al +setc [ebp+__xflag] +jnz short ln2140 +or ch,0BFh +and ah,ch +ln2140: +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D908 - D90F +X908: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+16] +dec edx +call readmemorybyte +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +adc al,bl +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln2141 +or ch,0BFh +and ah,ch +ln2141: +mov ecx,ebx +xor ebx,ebx +call writememorybyte +mov [ebp+__areg+16],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D910 - D917 +X910: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,[ebp+__dreg+16] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D918 - D91F +X918: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,[ebp+__dreg+16] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D920 - D927 +X920: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +add cl,[ebp+__dreg+16] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D928 - D92F +X928: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,[ebp+__dreg+16] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D930 - D937 +X930: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,[ebp+__dreg+16] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D938 +X938: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +add cl,[ebp+__dreg+16] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D939 +X939: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +add cl,[ebp+__dreg+16] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D940 - D947 +X940: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+16] +adc ax,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+16],ax +lahf +seto al +setc [ebp+__xflag] +jnz short ln2142 +or ch,0BFh +and ah,ch +ln2142: +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D948 - D94F +X948: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+16] +sub edx,byte 2 +call readmemoryword +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +adc ax,bx +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln2143 +or ch,0BFh +and ah,ch +ln2143: +mov ecx,ebx +xor ebx,ebx +call writememoryword +mov [ebp+__areg+16],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D950 - D957 +X950: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,[ebp+__dreg+16] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D958 - D95F +X958: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,[ebp+__dreg+16] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D960 - D967 +X960: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +add cx,[ebp+__dreg+16] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D968 - D96F +X968: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,[ebp+__dreg+16] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D970 - D977 +X970: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,[ebp+__dreg+16] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D978 +X978: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +add cx,[ebp+__dreg+16] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D979 +X979: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +add cx,[ebp+__dreg+16] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D980 - D987 +X980: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+16] +adc eax,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+16],eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln2144 +or ch,0BFh +and ah,ch +ln2144: +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D988 - D98F +X988: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+16] +sub edx,byte 4 +call readmemorydword +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +adc eax,ebx +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln2145 +or ch,0BFh +and ah,ch +ln2145: +mov ecx,ebx +xor ebx,ebx +call writememorydword +mov [ebp+__areg+16],edx +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D990 - D997 +X990: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,[ebp+__dreg+16] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D998 - D99F +X998: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,[ebp+__dreg+16] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D9A0 - D9A7 +X9A0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +add ecx,[ebp+__dreg+16] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D9A8 - D9AF +X9A8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,[ebp+__dreg+16] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D9B0 - D9B7 +X9B0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,[ebp+__dreg+16] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D9B8 +X9B8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +add ecx,[ebp+__dreg+16] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D9B9 +X9B9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +add ecx,[ebp+__dreg+16] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D9C0 - D9C7 +X9C0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +add [ebp+__areg+16],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D9C8 - D9CF +X9C8: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +add [ebp+__areg+16],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D9D0 - D9D7 +X9D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add [ebp+__areg+16],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D9D8 - D9DF +X9D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +add [ebp+__areg+16],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D9E0 - D9E7 +X9E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +add [ebp+__areg+16],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D9E8 - D9EF +X9E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add [ebp+__areg+16],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes D9F0 - D9F7 +X9F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add [ebp+__areg+16],ecx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D9F8 +X9F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +add [ebp+__areg+16],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D9F9 +X9F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +add [ebp+__areg+16],ecx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D9FA +X9FA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +add [ebp+__areg+16],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D9FB +X9FB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +add [ebp+__areg+16],ecx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode D9FC +X9FC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +add [ebp+__areg+16],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DA00 - DA07 +XA00: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +add [ebp+__dreg+20],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DA10 - DA17 +XA10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +add [ebp+__dreg+20],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DA18 - DA1F +XA18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +add [ebp+__dreg+20],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DA20 - DA27 +XA20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +add [ebp+__dreg+20],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DA28 - DA2F +XA28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +add [ebp+__dreg+20],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DA30 - DA37 +XA30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +add [ebp+__dreg+20],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DA38 +XA38: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +add [ebp+__dreg+20],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DA39 +XA39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +add [ebp+__dreg+20],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DA3A +XA3A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +add [ebp+__dreg+20],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DA3B +XA3B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +add [ebp+__dreg+20],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DA3C +XA3C: +mov cx,[esi] +add esi,byte 2 +add [ebp+__dreg+20],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DA40 - DA47 +XA40: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +add [ebp+__dreg+20],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DA48 - DA4F +XA48: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +add [ebp+__dreg+20],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DA50 - DA57 +XA50: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add [ebp+__dreg+20],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DA58 - DA5F +XA58: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +add [ebp+__dreg+20],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DA60 - DA67 +XA60: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +add [ebp+__dreg+20],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DA68 - DA6F +XA68: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +add [ebp+__dreg+20],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DA70 - DA77 +XA70: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +add [ebp+__dreg+20],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DA78 +XA78: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +add [ebp+__dreg+20],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DA79 +XA79: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +add [ebp+__dreg+20],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DA7A +XA7A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +add [ebp+__dreg+20],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DA7B +XA7B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +add [ebp+__dreg+20],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DA7C +XA7C: +mov cx,[esi] +add esi,byte 2 +add [ebp+__dreg+20],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DA80 - DA87 +XA80: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +add [ebp+__dreg+20],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DA88 - DA8F +XA88: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +add [ebp+__dreg+20],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DA90 - DA97 +XA90: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add [ebp+__dreg+20],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DA98 - DA9F +XA98: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +add [ebp+__dreg+20],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DAA0 - DAA7 +XAA0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +add [ebp+__dreg+20],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DAA8 - DAAF +XAA8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add [ebp+__dreg+20],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DAB0 - DAB7 +XAB0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add [ebp+__dreg+20],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DAB8 +XAB8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +add [ebp+__dreg+20],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DAB9 +XAB9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +add [ebp+__dreg+20],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DABA +XABA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +add [ebp+__dreg+20],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DABB +XABB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +add [ebp+__dreg+20],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DABC +XABC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +add [ebp+__dreg+20],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DAC0 - DAC7 +XAC0: +and ebx,byte 7 +movsx ecx,word[ebp+__dreg+ebx*4] +add [ebp+__areg+20],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DAC8 - DACF +XAC8: +and ebx,byte 7 +movsx ecx,word[ebp+__areg+ebx*4] +add [ebp+__areg+20],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DAD0 - DAD7 +XAD0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +add [ebp+__areg+20],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DAD8 - DADF +XAD8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +add [ebp+__areg+20],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DAE0 - DAE7 +XAE0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+ebx*4],edx +add [ebp+__areg+20],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DAE8 - DAEF +XAE8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +add [ebp+__areg+20],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DAF0 - DAF7 +XAF0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +add [ebp+__areg+20],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DAF8 +XAF8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +add [ebp+__areg+20],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DAF9 +XAF9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +movsx ecx,cx +add [ebp+__areg+20],ecx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DAFA +XAFA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +add [ebp+__areg+20],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DAFB +XAFB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +add [ebp+__areg+20],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DAFC +XAFC: +movsx ecx,word[esi] +add esi,byte 2 +add [ebp+__areg+20],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DB00 - DB07 +XB00: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+20] +adc al,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+20],al +lahf +seto al +setc [ebp+__xflag] +jnz short ln2146 +or ch,0BFh +and ah,ch +ln2146: +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DB08 - DB0F +XB08: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+20] +dec edx +call readmemorybyte +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +adc al,bl +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln2147 +or ch,0BFh +and ah,ch +ln2147: +mov ecx,ebx +xor ebx,ebx +call writememorybyte +mov [ebp+__areg+20],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DB10 - DB17 +XB10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,[ebp+__dreg+20] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DB18 - DB1F +XB18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,[ebp+__dreg+20] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DB20 - DB27 +XB20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +add cl,[ebp+__dreg+20] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DB28 - DB2F +XB28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,[ebp+__dreg+20] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DB30 - DB37 +XB30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,[ebp+__dreg+20] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DB38 +XB38: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +add cl,[ebp+__dreg+20] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DB39 +XB39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +add cl,[ebp+__dreg+20] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DB40 - DB47 +XB40: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+20] +adc ax,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+20],ax +lahf +seto al +setc [ebp+__xflag] +jnz short ln2148 +or ch,0BFh +and ah,ch +ln2148: +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DB48 - DB4F +XB48: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+20] +sub edx,byte 2 +call readmemoryword +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +adc ax,bx +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln2149 +or ch,0BFh +and ah,ch +ln2149: +mov ecx,ebx +xor ebx,ebx +call writememoryword +mov [ebp+__areg+20],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DB50 - DB57 +XB50: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,[ebp+__dreg+20] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DB58 - DB5F +XB58: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,[ebp+__dreg+20] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DB60 - DB67 +XB60: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +add cx,[ebp+__dreg+20] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DB68 - DB6F +XB68: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,[ebp+__dreg+20] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DB70 - DB77 +XB70: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,[ebp+__dreg+20] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DB78 +XB78: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +add cx,[ebp+__dreg+20] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DB79 +XB79: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +add cx,[ebp+__dreg+20] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DB80 - DB87 +XB80: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+20] +adc eax,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+20],eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln2150 +or ch,0BFh +and ah,ch +ln2150: +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DB88 - DB8F +XB88: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+20] +sub edx,byte 4 +call readmemorydword +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +adc eax,ebx +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln2151 +or ch,0BFh +and ah,ch +ln2151: +mov ecx,ebx +xor ebx,ebx +call writememorydword +mov [ebp+__areg+20],edx +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DB90 - DB97 +XB90: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,[ebp+__dreg+20] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DB98 - DB9F +XB98: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,[ebp+__dreg+20] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DBA0 - DBA7 +XBA0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +add ecx,[ebp+__dreg+20] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DBA8 - DBAF +XBA8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,[ebp+__dreg+20] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DBB0 - DBB7 +XBB0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,[ebp+__dreg+20] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DBB8 +XBB8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +add ecx,[ebp+__dreg+20] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DBB9 +XBB9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +add ecx,[ebp+__dreg+20] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DBC0 - DBC7 +XBC0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +add [ebp+__areg+20],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DBC8 - DBCF +XBC8: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +add [ebp+__areg+20],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DBD0 - DBD7 +XBD0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add [ebp+__areg+20],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DBD8 - DBDF +XBD8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +add [ebp+__areg+20],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DBE0 - DBE7 +XBE0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +add [ebp+__areg+20],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DBE8 - DBEF +XBE8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add [ebp+__areg+20],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DBF0 - DBF7 +XBF0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add [ebp+__areg+20],ecx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DBF8 +XBF8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +add [ebp+__areg+20],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DBF9 +XBF9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +add [ebp+__areg+20],ecx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DBFA +XBFA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +add [ebp+__areg+20],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DBFB +XBFB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +add [ebp+__areg+20],ecx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DBFC +XBFC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +add [ebp+__areg+20],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DC00 - DC07 +XC00: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +add [ebp+__dreg+24],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DC10 - DC17 +XC10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +add [ebp+__dreg+24],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DC18 - DC1F +XC18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +add [ebp+__dreg+24],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DC20 - DC27 +XC20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +add [ebp+__dreg+24],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DC28 - DC2F +XC28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +add [ebp+__dreg+24],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DC30 - DC37 +XC30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +add [ebp+__dreg+24],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DC38 +XC38: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +add [ebp+__dreg+24],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DC39 +XC39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +add [ebp+__dreg+24],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DC3A +XC3A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +add [ebp+__dreg+24],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DC3B +XC3B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +add [ebp+__dreg+24],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DC3C +XC3C: +mov cx,[esi] +add esi,byte 2 +add [ebp+__dreg+24],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DC40 - DC47 +XC40: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +add [ebp+__dreg+24],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DC48 - DC4F +XC48: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +add [ebp+__dreg+24],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DC50 - DC57 +XC50: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add [ebp+__dreg+24],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DC58 - DC5F +XC58: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +add [ebp+__dreg+24],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DC60 - DC67 +XC60: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +add [ebp+__dreg+24],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DC68 - DC6F +XC68: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +add [ebp+__dreg+24],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DC70 - DC77 +XC70: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +add [ebp+__dreg+24],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DC78 +XC78: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +add [ebp+__dreg+24],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DC79 +XC79: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +add [ebp+__dreg+24],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DC7A +XC7A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +add [ebp+__dreg+24],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DC7B +XC7B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +add [ebp+__dreg+24],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DC7C +XC7C: +mov cx,[esi] +add esi,byte 2 +add [ebp+__dreg+24],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DC80 - DC87 +XC80: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +add [ebp+__dreg+24],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DC88 - DC8F +XC88: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +add [ebp+__dreg+24],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DC90 - DC97 +XC90: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add [ebp+__dreg+24],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DC98 - DC9F +XC98: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +add [ebp+__dreg+24],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DCA0 - DCA7 +XCA0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +add [ebp+__dreg+24],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DCA8 - DCAF +XCA8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add [ebp+__dreg+24],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DCB0 - DCB7 +XCB0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add [ebp+__dreg+24],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DCB8 +XCB8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +add [ebp+__dreg+24],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DCB9 +XCB9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +add [ebp+__dreg+24],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DCBA +XCBA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +add [ebp+__dreg+24],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DCBB +XCBB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +add [ebp+__dreg+24],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DCBC +XCBC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +add [ebp+__dreg+24],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DCC0 - DCC7 +XCC0: +and ebx,byte 7 +movsx ecx,word[ebp+__dreg+ebx*4] +add [ebp+__areg+24],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DCC8 - DCCF +XCC8: +and ebx,byte 7 +movsx ecx,word[ebp+__areg+ebx*4] +add [ebp+__areg+24],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DCD0 - DCD7 +XCD0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +add [ebp+__areg+24],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DCD8 - DCDF +XCD8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +add [ebp+__areg+24],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DCE0 - DCE7 +XCE0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+ebx*4],edx +add [ebp+__areg+24],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DCE8 - DCEF +XCE8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +add [ebp+__areg+24],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DCF0 - DCF7 +XCF0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +add [ebp+__areg+24],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DCF8 +XCF8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +add [ebp+__areg+24],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DCF9 +XCF9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +movsx ecx,cx +add [ebp+__areg+24],ecx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DCFA +XCFA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +add [ebp+__areg+24],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DCFB +XCFB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +add [ebp+__areg+24],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DCFC +XCFC: +movsx ecx,word[esi] +add esi,byte 2 +add [ebp+__areg+24],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DD00 - DD07 +XD00: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+24] +adc al,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+24],al +lahf +seto al +setc [ebp+__xflag] +jnz short ln2152 +or ch,0BFh +and ah,ch +ln2152: +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DD08 - DD0F +XD08: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+24] +dec edx +call readmemorybyte +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +adc al,bl +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln2153 +or ch,0BFh +and ah,ch +ln2153: +mov ecx,ebx +xor ebx,ebx +call writememorybyte +mov [ebp+__areg+24],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DD10 - DD17 +XD10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,[ebp+__dreg+24] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DD18 - DD1F +XD18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,[ebp+__dreg+24] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DD20 - DD27 +XD20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +add cl,[ebp+__dreg+24] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DD28 - DD2F +XD28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,[ebp+__dreg+24] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DD30 - DD37 +XD30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,[ebp+__dreg+24] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DD38 +XD38: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +add cl,[ebp+__dreg+24] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DD39 +XD39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +add cl,[ebp+__dreg+24] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DD40 - DD47 +XD40: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+24] +adc ax,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+24],ax +lahf +seto al +setc [ebp+__xflag] +jnz short ln2154 +or ch,0BFh +and ah,ch +ln2154: +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DD48 - DD4F +XD48: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+24] +sub edx,byte 2 +call readmemoryword +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +adc ax,bx +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln2155 +or ch,0BFh +and ah,ch +ln2155: +mov ecx,ebx +xor ebx,ebx +call writememoryword +mov [ebp+__areg+24],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DD50 - DD57 +XD50: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,[ebp+__dreg+24] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DD58 - DD5F +XD58: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,[ebp+__dreg+24] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DD60 - DD67 +XD60: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +add cx,[ebp+__dreg+24] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DD68 - DD6F +XD68: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,[ebp+__dreg+24] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DD70 - DD77 +XD70: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,[ebp+__dreg+24] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DD78 +XD78: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +add cx,[ebp+__dreg+24] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DD79 +XD79: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +add cx,[ebp+__dreg+24] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DD80 - DD87 +XD80: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+24] +adc eax,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+24],eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln2156 +or ch,0BFh +and ah,ch +ln2156: +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DD88 - DD8F +XD88: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+24] +sub edx,byte 4 +call readmemorydword +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +adc eax,ebx +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln2157 +or ch,0BFh +and ah,ch +ln2157: +mov ecx,ebx +xor ebx,ebx +call writememorydword +mov [ebp+__areg+24],edx +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DD90 - DD97 +XD90: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,[ebp+__dreg+24] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DD98 - DD9F +XD98: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,[ebp+__dreg+24] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DDA0 - DDA7 +XDA0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +add ecx,[ebp+__dreg+24] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DDA8 - DDAF +XDA8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,[ebp+__dreg+24] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DDB0 - DDB7 +XDB0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,[ebp+__dreg+24] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DDB8 +XDB8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +add ecx,[ebp+__dreg+24] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DDB9 +XDB9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +add ecx,[ebp+__dreg+24] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DDC0 - DDC7 +XDC0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +add [ebp+__areg+24],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DDC8 - DDCF +XDC8: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +add [ebp+__areg+24],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DDD0 - DDD7 +XDD0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add [ebp+__areg+24],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DDD8 - DDDF +XDD8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +add [ebp+__areg+24],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DDE0 - DDE7 +XDE0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +add [ebp+__areg+24],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DDE8 - DDEF +XDE8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add [ebp+__areg+24],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DDF0 - DDF7 +XDF0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add [ebp+__areg+24],ecx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DDF8 +XDF8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +add [ebp+__areg+24],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DDF9 +XDF9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +add [ebp+__areg+24],ecx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DDFA +XDFA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +add [ebp+__areg+24],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DDFB +XDFB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +add [ebp+__areg+24],ecx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DDFC +XDFC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +add [ebp+__areg+24],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DE00 - DE07 +XE00: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +add [ebp+__dreg+28],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DE10 - DE17 +XE10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +add [ebp+__dreg+28],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DE18 - DE1F +XE18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +add [ebp+__dreg+28],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DE20 - DE27 +XE20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +add [ebp+__dreg+28],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DE28 - DE2F +XE28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +add [ebp+__dreg+28],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DE30 - DE37 +XE30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +add [ebp+__dreg+28],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DE38 +XE38: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +add [ebp+__dreg+28],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DE39 +XE39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +add [ebp+__dreg+28],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DE3A +XE3A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorybyte +add [ebp+__dreg+28],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DE3B +XE3B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorybyte +add [ebp+__dreg+28],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DE3C +XE3C: +mov cx,[esi] +add esi,byte 2 +add [ebp+__dreg+28],cl +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DE40 - DE47 +XE40: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +add [ebp+__dreg+28],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DE48 - DE4F +XE48: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +add [ebp+__dreg+28],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DE50 - DE57 +XE50: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add [ebp+__dreg+28],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DE58 - DE5F +XE58: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +add [ebp+__dreg+28],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DE60 - DE67 +XE60: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +add [ebp+__dreg+28],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DE68 - DE6F +XE68: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +add [ebp+__dreg+28],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DE70 - DE77 +XE70: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +add [ebp+__dreg+28],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DE78 +XE78: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +add [ebp+__dreg+28],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DE79 +XE79: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +add [ebp+__dreg+28],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DE7A +XE7A: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +add [ebp+__dreg+28],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DE7B +XE7B: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +add [ebp+__dreg+28],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DE7C +XE7C: +mov cx,[esi] +add esi,byte 2 +add [ebp+__dreg+28],cx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DE80 - DE87 +XE80: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +add [ebp+__dreg+28],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DE88 - DE8F +XE88: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +add [ebp+__dreg+28],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DE90 - DE97 +XE90: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add [ebp+__dreg+28],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DE98 - DE9F +XE98: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +add [ebp+__dreg+28],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DEA0 - DEA7 +XEA0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +add [ebp+__dreg+28],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DEA8 - DEAF +XEA8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add [ebp+__dreg+28],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DEB0 - DEB7 +XEB0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add [ebp+__dreg+28],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DEB8 +XEB8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +add [ebp+__dreg+28],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DEB9 +XEB9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +add [ebp+__dreg+28],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DEBA +XEBA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +add [ebp+__dreg+28],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DEBB +XEBB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +add [ebp+__dreg+28],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DEBC +XEBC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +add [ebp+__dreg+28],ecx +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DEC0 - DEC7 +XEC0: +and ebx,byte 7 +movsx ecx,word[ebp+__dreg+ebx*4] +add [ebp+__areg+28],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DEC8 - DECF +XEC8: +and ebx,byte 7 +movsx ecx,word[ebp+__areg+ebx*4] +add [ebp+__areg+28],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DED0 - DED7 +XED0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +add [ebp+__areg+28],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DED8 - DEDF +XED8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +add [ebp+__areg+28],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DEE0 - DEE7 +XEE0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +mov [ebp+__areg+ebx*4],edx +add [ebp+__areg+28],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DEE8 - DEEF +XEE8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +add [ebp+__areg+28],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DEF0 - DEF7 +XEF0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +movsx ecx,cx +add [ebp+__areg+28],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DEF8 +XEF8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +add [ebp+__areg+28],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DEF9 +XEF9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +movsx ecx,cx +add [ebp+__areg+28],ecx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DEFA +XEFA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemoryword +movsx ecx,cx +add [ebp+__areg+28],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DEFB +XEFB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemoryword +movsx ecx,cx +add [ebp+__areg+28],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DEFC +XEFC: +movsx ecx,word[esi] +add esi,byte 2 +add [ebp+__areg+28],ecx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DF00 - DF07 +XF00: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+28] +adc al,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+28],al +lahf +seto al +setc [ebp+__xflag] +jnz short ln2158 +or ch,0BFh +and ah,ch +ln2158: +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DF08 - DF0F +XF08: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+28] +sub edx,byte 2 +call readmemorybyte +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +adc al,bl +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln2159 +or ch,0BFh +and ah,ch +ln2159: +mov ecx,ebx +xor ebx,ebx +call writememorybyte +mov [ebp+__areg+28],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DF10 - DF17 +XF10: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,[ebp+__dreg+28] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DF18 - DF1F +XF18: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,[ebp+__dreg+28] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +cmp bl,7 +sbb edx,byte -2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DF20 - DF27 +XF20: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +cmp bl,7 +adc edx,byte -2 +call readmemorybyte +add cl,[ebp+__dreg+28] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DF28 - DF2F +XF28: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,[ebp+__dreg+28] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DF30 - DF37 +XF30: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorybyte +add cl,[ebp+__dreg+28] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DF38 +XF38: +movsx edx,word[esi] +add esi,byte 2 +call readmemorybyte +add cl,[ebp+__dreg+28] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DF39 +XF39: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorybyte +add cl,[ebp+__dreg+28] +lahf +seto al +setc [ebp+__xflag] +call writememorybyte +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DF40 - DF47 +XF40: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+28] +adc ax,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+28],ax +lahf +seto al +setc [ebp+__xflag] +jnz short ln2160 +or ch,0BFh +and ah,ch +ln2160: +sub edi,byte 4 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DF48 - DF4F +XF48: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+28] +sub edx,byte 2 +call readmemoryword +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +adc ax,bx +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln2161 +or ch,0BFh +and ah,ch +ln2161: +mov ecx,ebx +xor ebx,ebx +call writememoryword +mov [ebp+__areg+28],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DF50 - DF57 +XF50: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,[ebp+__dreg+28] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DF58 - DF5F +XF58: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,[ebp+__dreg+28] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DF60 - DF67 +XF60: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +add cx,[ebp+__dreg+28] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DF68 - DF6F +XF68: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,[ebp+__dreg+28] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DF70 - DF77 +XF70: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +add cx,[ebp+__dreg+28] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DF78 +XF78: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +add cx,[ebp+__dreg+28] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DF79 +XF79: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +add cx,[ebp+__dreg+28] +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DF80 - DF87 +XF80: +and ebx,byte 7 +mov ch,ah +mov cl,[ebp+__xflag] +shr cl,1 +mov eax,[ebp+__dreg+28] +adc eax,[ebp+__dreg+ebx*4] +mov [ebp+__dreg+28],eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln2162 +or ch,0BFh +and ah,ch +ln2162: +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DF88 - DF8F +XF88: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +mov ebx,ecx +mov edx,[ebp+__areg+28] +sub edx,byte 4 +call readmemorydword +xchg ecx,eax +mov cl,[ebp+__xflag] +shr cl,1 +adc eax,ebx +mov ebx,eax +lahf +seto al +setc [ebp+__xflag] +jnz short ln2163 +or ch,0BFh +and ah,ch +ln2163: +mov ecx,ebx +xor ebx,ebx +call writememorydword +mov [ebp+__areg+28],edx +sub edi,byte 30 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DF90 - DF97 +XF90: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,[ebp+__dreg+28] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DF98 - DF9F +XF98: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,[ebp+__dreg+28] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DFA0 - DFA7 +XFA0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +add ecx,[ebp+__dreg+28] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DFA8 - DFAF +XFA8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,[ebp+__dreg+28] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DFB0 - DFB7 +XFB0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add ecx,[ebp+__dreg+28] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 26 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DFB8 +XFB8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +add ecx,[ebp+__dreg+28] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DFB9 +XFB9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +add ecx,[ebp+__dreg+28] +lahf +seto al +setc [ebp+__xflag] +call writememorydword +sub edi,byte 28 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DFC0 - DFC7 +XFC0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+ebx*4] +add [ebp+__areg+28],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DFC8 - DFCF +XFC8: +and ebx,byte 7 +mov ecx,[ebp+__areg+ebx*4] +add [ebp+__areg+28],ecx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DFD0 - DFD7 +XFD0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add [ebp+__areg+28],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DFD8 - DFDF +XFD8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemorydword +add edx,byte 4 +mov [ebp+__areg+ebx*4],edx +add [ebp+__areg+28],ecx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DFE0 - DFE7 +XFE0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 4 +call readmemorydword +mov [ebp+__areg+ebx*4],edx +add [ebp+__areg+28],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DFE8 - DFEF +XFE8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add [ebp+__areg+28],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes DFF0 - DFF7 +XFF0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemorydword +add [ebp+__areg+28],ecx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DFF8 +XFF8: +movsx edx,word[esi] +add esi,byte 2 +call readmemorydword +add [ebp+__areg+28],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DFF9 +XFF9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemorydword +add [ebp+__areg+28],ecx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DFFA +XFFA: +movsx edx,word[esi] +add edx,esi +sub edx,[ebp+__io_fetchbase] +add esi,byte 2 +call readmemorydword +add [ebp+__areg+28],ecx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DFFB +XFFB: +call decode_ext +add edx,esi +sub edx,[ebp+__io_fetchbase] +sub edx,byte 2 +call readmemorydword +add [ebp+__areg+28],ecx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode DFFC +XFFC: +mov ecx,[esi] +add esi,byte 4 +rol ecx,16 +add [ebp+__areg+28],ecx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E000 - E007 +Y000: +and ebx,byte 7 +mov al,0 +sar byte[ebp+__dreg+ebx*4],8 +lahf +setc [ebp+__xflag] +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E008 - E00F +Y008: +and ebx,byte 7 +mov al,0 +shr byte[ebp+__dreg+ebx*4],8 +lahf +setc [ebp+__xflag] +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E010 - E017 +Y010: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +shr al,1 +rcr dl,8 +adc al,al +or dl,dl +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E018 - E01F +Y018: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +ror dl,8 +adc al,al +or dl,dl +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E020 - E027 +Y020: +and ebx,byte 7 +mov ecx,[ebp+__dreg+0] +and ecx,byte 63 +jnz short ln2164 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2164: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2165 +sub cl, 31 +sar byte[ebp+__dreg+ebx*4], 31 +jmp short ln2166 +ln2165: +sar byte[ebp+__dreg+ebx*4],cl +ln2166: +lahf +setc [ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E028 - E02F +Y028: +and ebx,byte 7 +mov ecx,[ebp+__dreg+0] +and ecx,byte 63 +jnz short ln2167 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2167: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2168 +sub cl, 31 +shr byte[ebp+__dreg+ebx*4], 31 +jmp short ln2169 +ln2168: +shr byte[ebp+__dreg+ebx*4],cl +ln2169: +lahf +setc [ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E030 - E037 +Y030: +and ebx,byte 7 +mov ecx,[ebp+__dreg+0] +and ecx,byte 63 +jnz short ln2170 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +and ah,0FEh +or ah,[ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2170: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +cmp cl, 32 +jb short ln2171 +sub cl, 31 +shr al, 1 +rcr dl, 31 +rcr dl,cl +jmp short ln2172 +ln2171: +shr al, 1 +rcr dl,cl +ln2172: +adc al,al +or dl,dl +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E038 - E03F +Y038: +and ebx,byte 7 +mov ecx,[ebp+__dreg+0] +and ecx,byte 63 +jnz short ln2173 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2173: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +cmp cl, 32 +jb short ln2174 +sub cl, 31 +ror dl, 31 +ror dl,cl +jmp short ln2175 +ln2174: +ror dl,cl +ln2175: +adc al,al +or dl,dl +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E040 - E047 +Y040: +and ebx,byte 7 +mov al,0 +sar word[ebp+__dreg+ebx*4],8 +lahf +setc [ebp+__xflag] +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E048 - E04F +Y048: +and ebx,byte 7 +mov al,0 +shr word[ebp+__dreg+ebx*4],8 +lahf +setc [ebp+__xflag] +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E050 - E057 +Y050: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +shr al,1 +rcr dx,8 +adc al,al +or dx,dx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E058 - E05F +Y058: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +ror dx,8 +adc al,al +or dx,dx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E060 - E067 +Y060: +and ebx,byte 7 +mov ecx,[ebp+__dreg+0] +and ecx,byte 63 +jnz short ln2176 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2176: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2177 +sub cl, 31 +sar word[ebp+__dreg+ebx*4], 31 +jmp short ln2178 +ln2177: +sar word[ebp+__dreg+ebx*4],cl +ln2178: +lahf +setc [ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E068 - E06F +Y068: +and ebx,byte 7 +mov ecx,[ebp+__dreg+0] +and ecx,byte 63 +jnz short ln2179 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2179: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2180 +sub cl, 31 +shr word[ebp+__dreg+ebx*4], 31 +jmp short ln2181 +ln2180: +shr word[ebp+__dreg+ebx*4],cl +ln2181: +lahf +setc [ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E070 - E077 +Y070: +and ebx,byte 7 +mov ecx,[ebp+__dreg+0] +and ecx,byte 63 +jnz short ln2182 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +and ah,0FEh +or ah,[ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2182: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +cmp cl, 32 +jb short ln2183 +sub cl, 31 +shr al, 1 +rcr dx, 31 +rcr dx,cl +jmp short ln2184 +ln2183: +shr al, 1 +rcr dx,cl +ln2184: +adc al,al +or dx,dx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E078 - E07F +Y078: +and ebx,byte 7 +mov ecx,[ebp+__dreg+0] +and ecx,byte 63 +jnz short ln2185 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2185: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +cmp cl, 32 +jb short ln2186 +sub cl, 31 +ror dx, 31 +ror dx,cl +jmp short ln2187 +ln2186: +ror dx,cl +ln2187: +adc al,al +or dx,dx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E080 - E087 +Y080: +and ebx,byte 7 +mov al,0 +sar dword[ebp+__dreg+ebx*4],8 +lahf +setc [ebp+__xflag] +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E088 - E08F +Y088: +and ebx,byte 7 +mov al,0 +shr dword[ebp+__dreg+ebx*4],8 +lahf +setc [ebp+__xflag] +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E090 - E097 +Y090: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +shr al,1 +rcr edx,8 +adc al,al +or edx,edx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E098 - E09F +Y098: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +ror edx,8 +adc al,al +or edx,edx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E0A0 - E0A7 +Y0A0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+0] +and ecx,byte 63 +jnz short ln2188 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2188: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2189 +sub cl, 31 +sar dword[ebp+__dreg+ebx*4], 31 +jmp short ln2190 +ln2189: +sar dword[ebp+__dreg+ebx*4],cl +ln2190: +lahf +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E0A8 - E0AF +Y0A8: +and ebx,byte 7 +mov ecx,[ebp+__dreg+0] +and ecx,byte 63 +jnz short ln2191 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2191: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2192 +sub cl, 31 +shr dword[ebp+__dreg+ebx*4], 31 +jmp short ln2193 +ln2192: +shr dword[ebp+__dreg+ebx*4],cl +ln2193: +lahf +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E0B0 - E0B7 +Y0B0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+0] +and ecx,byte 63 +jnz short ln2194 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +and ah,0FEh +or ah,[ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2194: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +cmp cl, 32 +jb short ln2195 +sub cl, 31 +shr al, 1 +rcr edx, 31 +rcr edx,cl +jmp short ln2196 +ln2195: +shr al, 1 +rcr edx,cl +ln2196: +adc al,al +or edx,edx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E0B8 - E0BF +Y0B8: +and ebx,byte 7 +mov ecx,[ebp+__dreg+0] +and ecx,byte 63 +jnz short ln2197 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2197: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +cmp cl, 32 +jb short ln2198 +sub cl, 31 +ror edx, 31 +ror edx,cl +jmp short ln2199 +ln2198: +ror edx,cl +ln2199: +adc al,al +or edx,edx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E0D0 - E0D7 +Y0D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +sar cx,1 +lahf +mov al,0 +setc [ebp+__xflag] +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E0D8 - E0DF +Y0D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +sar cx,1 +lahf +mov al,0 +setc [ebp+__xflag] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E0E0 - E0E7 +Y0E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +sar cx,1 +lahf +mov al,0 +setc [ebp+__xflag] +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E0E8 - E0EF +Y0E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +sar cx,1 +lahf +mov al,0 +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E0F0 - E0F7 +Y0F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +sar cx,1 +lahf +mov al,0 +setc [ebp+__xflag] +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode E0F8 +Y0F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +sar cx,1 +lahf +mov al,0 +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode E0F9 +Y0F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +sar cx,1 +lahf +mov al,0 +setc [ebp+__xflag] +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E100 - E107 +Y100: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +add dl,dl +seto ch +or al,ch +add dl,dl +seto ch +or al,ch +add dl,dl +seto ch +or al,ch +add dl,dl +seto ch +or al,ch +add dl,dl +seto ch +or al,ch +add dl,dl +seto ch +or al,ch +add dl,dl +seto ch +or al,ch +add dl,dl +lahf +seto ch +or al,ch +mov [ebp+__dreg+ebx*4],dl +mov cl,ah +and cl,1 +mov [ebp+__xflag],cl +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E108 - E10F +Y108: +and ebx,byte 7 +mov al,0 +shl byte[ebp+__dreg+ebx*4],8 +lahf +setc [ebp+__xflag] +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E110 - E117 +Y110: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +shr al,1 +rcl dl,8 +adc al,al +or dl,dl +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E118 - E11F +Y118: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +rol dl,8 +adc al,al +or dl,dl +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E120 - E127 +Y120: +and ebx,byte 7 +mov ecx,[ebp+__dreg+0] +and ecx,byte 63 +jnz short ln2200 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2200: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +ln2201: +add dl,dl +lahf +seto ch +or al,ch +dec cl +jnz short ln2201 +mov [ebp+__dreg+ebx*4],dl +mov cl,ah +and cl,1 +mov [ebp+__xflag],cl +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E128 - E12F +Y128: +and ebx,byte 7 +mov ecx,[ebp+__dreg+0] +and ecx,byte 63 +jnz short ln2202 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2202: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2203 +sub cl, 31 +shl byte[ebp+__dreg+ebx*4], 31 +jmp short ln2204 +ln2203: +shl byte[ebp+__dreg+ebx*4],cl +ln2204: +lahf +setc [ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E130 - E137 +Y130: +and ebx,byte 7 +mov ecx,[ebp+__dreg+0] +and ecx,byte 63 +jnz short ln2205 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +and ah,0FEh +or ah,[ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2205: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +cmp cl, 32 +jb short ln2206 +sub cl, 31 +shr al, 1 +rcl dl, 31 +rcl dl,cl +jmp short ln2207 +ln2206: +shr al, 1 +rcl dl,cl +ln2207: +adc al,al +or dl,dl +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E138 - E13F +Y138: +and ebx,byte 7 +mov ecx,[ebp+__dreg+0] +and ecx,byte 63 +jnz short ln2208 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2208: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +cmp cl, 32 +jb short ln2209 +sub cl, 31 +rol dl, 31 +rol dl,cl +jmp short ln2210 +ln2209: +rol dl,cl +ln2210: +adc al,al +or dl,dl +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E140 - E147 +Y140: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +add dx,dx +seto ch +or al,ch +add dx,dx +seto ch +or al,ch +add dx,dx +seto ch +or al,ch +add dx,dx +seto ch +or al,ch +add dx,dx +seto ch +or al,ch +add dx,dx +seto ch +or al,ch +add dx,dx +seto ch +or al,ch +add dx,dx +lahf +seto ch +or al,ch +mov [ebp+__dreg+ebx*4],dx +mov cl,ah +and cl,1 +mov [ebp+__xflag],cl +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E148 - E14F +Y148: +and ebx,byte 7 +mov al,0 +shl word[ebp+__dreg+ebx*4],8 +lahf +setc [ebp+__xflag] +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E150 - E157 +Y150: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +shr al,1 +rcl dx,8 +adc al,al +or dx,dx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E158 - E15F +Y158: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +rol dx,8 +adc al,al +or dx,dx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E160 - E167 +Y160: +and ebx,byte 7 +mov ecx,[ebp+__dreg+0] +and ecx,byte 63 +jnz short ln2211 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2211: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +ln2212: +add dx,dx +lahf +seto ch +or al,ch +dec cl +jnz short ln2212 +mov [ebp+__dreg+ebx*4],dx +mov cl,ah +and cl,1 +mov [ebp+__xflag],cl +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E168 - E16F +Y168: +and ebx,byte 7 +mov ecx,[ebp+__dreg+0] +and ecx,byte 63 +jnz short ln2213 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2213: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2214 +sub cl, 31 +shl word[ebp+__dreg+ebx*4], 31 +jmp short ln2215 +ln2214: +shl word[ebp+__dreg+ebx*4],cl +ln2215: +lahf +setc [ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E170 - E177 +Y170: +and ebx,byte 7 +mov ecx,[ebp+__dreg+0] +and ecx,byte 63 +jnz short ln2216 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +and ah,0FEh +or ah,[ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2216: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +cmp cl, 32 +jb short ln2217 +sub cl, 31 +shr al, 1 +rcl dx, 31 +rcl dx,cl +jmp short ln2218 +ln2217: +shr al, 1 +rcl dx,cl +ln2218: +adc al,al +or dx,dx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E178 - E17F +Y178: +and ebx,byte 7 +mov ecx,[ebp+__dreg+0] +and ecx,byte 63 +jnz short ln2219 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2219: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +cmp cl, 32 +jb short ln2220 +sub cl, 31 +rol dx, 31 +rol dx,cl +jmp short ln2221 +ln2220: +rol dx,cl +ln2221: +adc al,al +or dx,dx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E180 - E187 +Y180: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +add edx,edx +seto ch +or al,ch +add edx,edx +seto ch +or al,ch +add edx,edx +seto ch +or al,ch +add edx,edx +seto ch +or al,ch +add edx,edx +seto ch +or al,ch +add edx,edx +seto ch +or al,ch +add edx,edx +seto ch +or al,ch +add edx,edx +lahf +seto ch +or al,ch +mov [ebp+__dreg+ebx*4],edx +mov cl,ah +and cl,1 +mov [ebp+__xflag],cl +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E188 - E18F +Y188: +and ebx,byte 7 +mov al,0 +shl dword[ebp+__dreg+ebx*4],8 +lahf +setc [ebp+__xflag] +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E190 - E197 +Y190: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +shr al,1 +rcl edx,8 +adc al,al +or edx,edx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E198 - E19F +Y198: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +rol edx,8 +adc al,al +or edx,edx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 24 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E1A0 - E1A7 +Y1A0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+0] +and ecx,byte 63 +jnz short ln2222 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2222: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +ln2223: +add edx,edx +lahf +seto ch +or al,ch +dec cl +jnz short ln2223 +mov [ebp+__dreg+ebx*4],edx +mov cl,ah +and cl,1 +mov [ebp+__xflag],cl +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E1A8 - E1AF +Y1A8: +and ebx,byte 7 +mov ecx,[ebp+__dreg+0] +and ecx,byte 63 +jnz short ln2224 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2224: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2225 +sub cl, 31 +shl dword[ebp+__dreg+ebx*4], 31 +jmp short ln2226 +ln2225: +shl dword[ebp+__dreg+ebx*4],cl +ln2226: +lahf +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E1B0 - E1B7 +Y1B0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+0] +and ecx,byte 63 +jnz short ln2227 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +and ah,0FEh +or ah,[ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2227: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +cmp cl, 32 +jb short ln2228 +sub cl, 31 +shr al, 1 +rcl edx, 31 +rcl edx,cl +jmp short ln2229 +ln2228: +shr al, 1 +rcl edx,cl +ln2229: +adc al,al +or edx,edx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E1B8 - E1BF +Y1B8: +and ebx,byte 7 +mov ecx,[ebp+__dreg+0] +and ecx,byte 63 +jnz short ln2230 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2230: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +cmp cl, 32 +jb short ln2231 +sub cl, 31 +rol edx, 31 +rol edx,cl +jmp short ln2232 +ln2231: +rol edx,cl +ln2232: +adc al,al +or edx,edx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E1D0 - E1D7 +Y1D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +sal cx,1 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E1D8 - E1DF +Y1D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +sal cx,1 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E1E0 - E1E7 +Y1E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +sal cx,1 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E1E8 - E1EF +Y1E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +sal cx,1 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E1F0 - E1F7 +Y1F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +sal cx,1 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode E1F8 +Y1F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +sal cx,1 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode E1F9 +Y1F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +sal cx,1 +lahf +seto al +setc [ebp+__xflag] +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E200 - E207 +Y200: +and ebx,byte 7 +mov al,0 +sar byte[ebp+__dreg+ebx*4],1 +lahf +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E208 - E20F +Y208: +and ebx,byte 7 +mov al,0 +shr byte[ebp+__dreg+ebx*4],1 +lahf +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E210 - E217 +Y210: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +shr al,1 +rcr dl,1 +adc al,al +or dl,dl +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E218 - E21F +Y218: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +ror dl,1 +adc al,al +or dl,dl +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E220 - E227 +Y220: +and ebx,byte 7 +mov ecx,[ebp+__dreg+4] +and ecx,byte 63 +jnz short ln2233 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2233: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2234 +sub cl, 31 +sar byte[ebp+__dreg+ebx*4], 31 +jmp short ln2235 +ln2234: +sar byte[ebp+__dreg+ebx*4],cl +ln2235: +lahf +setc [ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E228 - E22F +Y228: +and ebx,byte 7 +mov ecx,[ebp+__dreg+4] +and ecx,byte 63 +jnz short ln2236 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2236: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2237 +sub cl, 31 +shr byte[ebp+__dreg+ebx*4], 31 +jmp short ln2238 +ln2237: +shr byte[ebp+__dreg+ebx*4],cl +ln2238: +lahf +setc [ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E230 - E237 +Y230: +and ebx,byte 7 +mov ecx,[ebp+__dreg+4] +and ecx,byte 63 +jnz short ln2239 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +and ah,0FEh +or ah,[ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2239: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +cmp cl, 32 +jb short ln2240 +sub cl, 31 +shr al, 1 +rcr dl, 31 +rcr dl,cl +jmp short ln2241 +ln2240: +shr al, 1 +rcr dl,cl +ln2241: +adc al,al +or dl,dl +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E238 - E23F +Y238: +and ebx,byte 7 +mov ecx,[ebp+__dreg+4] +and ecx,byte 63 +jnz short ln2242 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2242: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +cmp cl, 32 +jb short ln2243 +sub cl, 31 +ror dl, 31 +ror dl,cl +jmp short ln2244 +ln2243: +ror dl,cl +ln2244: +adc al,al +or dl,dl +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E240 - E247 +Y240: +and ebx,byte 7 +mov al,0 +sar word[ebp+__dreg+ebx*4],1 +lahf +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E248 - E24F +Y248: +and ebx,byte 7 +mov al,0 +shr word[ebp+__dreg+ebx*4],1 +lahf +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E250 - E257 +Y250: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +shr al,1 +rcr dx,1 +adc al,al +or dx,dx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E258 - E25F +Y258: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +ror dx,1 +adc al,al +or dx,dx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E260 - E267 +Y260: +and ebx,byte 7 +mov ecx,[ebp+__dreg+4] +and ecx,byte 63 +jnz short ln2245 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2245: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2246 +sub cl, 31 +sar word[ebp+__dreg+ebx*4], 31 +jmp short ln2247 +ln2246: +sar word[ebp+__dreg+ebx*4],cl +ln2247: +lahf +setc [ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E268 - E26F +Y268: +and ebx,byte 7 +mov ecx,[ebp+__dreg+4] +and ecx,byte 63 +jnz short ln2248 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2248: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2249 +sub cl, 31 +shr word[ebp+__dreg+ebx*4], 31 +jmp short ln2250 +ln2249: +shr word[ebp+__dreg+ebx*4],cl +ln2250: +lahf +setc [ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E270 - E277 +Y270: +and ebx,byte 7 +mov ecx,[ebp+__dreg+4] +and ecx,byte 63 +jnz short ln2251 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +and ah,0FEh +or ah,[ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2251: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +cmp cl, 32 +jb short ln2252 +sub cl, 31 +shr al, 1 +rcr dx, 31 +rcr dx,cl +jmp short ln2253 +ln2252: +shr al, 1 +rcr dx,cl +ln2253: +adc al,al +or dx,dx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E278 - E27F +Y278: +and ebx,byte 7 +mov ecx,[ebp+__dreg+4] +and ecx,byte 63 +jnz short ln2254 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2254: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +cmp cl, 32 +jb short ln2255 +sub cl, 31 +ror dx, 31 +ror dx,cl +jmp short ln2256 +ln2255: +ror dx,cl +ln2256: +adc al,al +or dx,dx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E280 - E287 +Y280: +and ebx,byte 7 +mov al,0 +sar dword[ebp+__dreg+ebx*4],1 +lahf +setc [ebp+__xflag] +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E288 - E28F +Y288: +and ebx,byte 7 +mov al,0 +shr dword[ebp+__dreg+ebx*4],1 +lahf +setc [ebp+__xflag] +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E290 - E297 +Y290: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +shr al,1 +rcr edx,1 +adc al,al +or edx,edx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E298 - E29F +Y298: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +ror edx,1 +adc al,al +or edx,edx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E2A0 - E2A7 +Y2A0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+4] +and ecx,byte 63 +jnz short ln2257 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2257: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2258 +sub cl, 31 +sar dword[ebp+__dreg+ebx*4], 31 +jmp short ln2259 +ln2258: +sar dword[ebp+__dreg+ebx*4],cl +ln2259: +lahf +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E2A8 - E2AF +Y2A8: +and ebx,byte 7 +mov ecx,[ebp+__dreg+4] +and ecx,byte 63 +jnz short ln2260 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2260: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2261 +sub cl, 31 +shr dword[ebp+__dreg+ebx*4], 31 +jmp short ln2262 +ln2261: +shr dword[ebp+__dreg+ebx*4],cl +ln2262: +lahf +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E2B0 - E2B7 +Y2B0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+4] +and ecx,byte 63 +jnz short ln2263 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +and ah,0FEh +or ah,[ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2263: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +cmp cl, 32 +jb short ln2264 +sub cl, 31 +shr al, 1 +rcr edx, 31 +rcr edx,cl +jmp short ln2265 +ln2264: +shr al, 1 +rcr edx,cl +ln2265: +adc al,al +or edx,edx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E2B8 - E2BF +Y2B8: +and ebx,byte 7 +mov ecx,[ebp+__dreg+4] +and ecx,byte 63 +jnz short ln2266 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2266: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +cmp cl, 32 +jb short ln2267 +sub cl, 31 +ror edx, 31 +ror edx,cl +jmp short ln2268 +ln2267: +ror edx,cl +ln2268: +adc al,al +or edx,edx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E2D0 - E2D7 +Y2D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +shr cx,1 +lahf +mov al,0 +setc [ebp+__xflag] +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E2D8 - E2DF +Y2D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +shr cx,1 +lahf +mov al,0 +setc [ebp+__xflag] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E2E0 - E2E7 +Y2E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +shr cx,1 +lahf +mov al,0 +setc [ebp+__xflag] +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E2E8 - E2EF +Y2E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +shr cx,1 +lahf +mov al,0 +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E2F0 - E2F7 +Y2F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +shr cx,1 +lahf +mov al,0 +setc [ebp+__xflag] +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode E2F8 +Y2F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +shr cx,1 +lahf +mov al,0 +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode E2F9 +Y2F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +shr cx,1 +lahf +mov al,0 +setc [ebp+__xflag] +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E300 - E307 +Y300: +and ebx,byte 7 +sal byte[ebp+__dreg+ebx*4],1 +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E308 - E30F +Y308: +and ebx,byte 7 +mov al,0 +shl byte[ebp+__dreg+ebx*4],1 +lahf +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E310 - E317 +Y310: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +shr al,1 +rcl dl,1 +adc al,al +or dl,dl +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E318 - E31F +Y318: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +rol dl,1 +adc al,al +or dl,dl +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E320 - E327 +Y320: +and ebx,byte 7 +mov ecx,[ebp+__dreg+4] +and ecx,byte 63 +jnz short ln2269 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2269: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +ln2270: +add dl,dl +lahf +seto ch +or al,ch +dec cl +jnz short ln2270 +mov [ebp+__dreg+ebx*4],dl +mov cl,ah +and cl,1 +mov [ebp+__xflag],cl +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E328 - E32F +Y328: +and ebx,byte 7 +mov ecx,[ebp+__dreg+4] +and ecx,byte 63 +jnz short ln2271 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2271: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2272 +sub cl, 31 +shl byte[ebp+__dreg+ebx*4], 31 +jmp short ln2273 +ln2272: +shl byte[ebp+__dreg+ebx*4],cl +ln2273: +lahf +setc [ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E330 - E337 +Y330: +and ebx,byte 7 +mov ecx,[ebp+__dreg+4] +and ecx,byte 63 +jnz short ln2274 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +and ah,0FEh +or ah,[ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2274: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +cmp cl, 32 +jb short ln2275 +sub cl, 31 +shr al, 1 +rcl dl, 31 +rcl dl,cl +jmp short ln2276 +ln2275: +shr al, 1 +rcl dl,cl +ln2276: +adc al,al +or dl,dl +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E338 - E33F +Y338: +and ebx,byte 7 +mov ecx,[ebp+__dreg+4] +and ecx,byte 63 +jnz short ln2277 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2277: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +cmp cl, 32 +jb short ln2278 +sub cl, 31 +rol dl, 31 +rol dl,cl +jmp short ln2279 +ln2278: +rol dl,cl +ln2279: +adc al,al +or dl,dl +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E340 - E347 +Y340: +and ebx,byte 7 +sal word[ebp+__dreg+ebx*4],1 +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E348 - E34F +Y348: +and ebx,byte 7 +mov al,0 +shl word[ebp+__dreg+ebx*4],1 +lahf +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E350 - E357 +Y350: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +shr al,1 +rcl dx,1 +adc al,al +or dx,dx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E358 - E35F +Y358: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +rol dx,1 +adc al,al +or dx,dx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E360 - E367 +Y360: +and ebx,byte 7 +mov ecx,[ebp+__dreg+4] +and ecx,byte 63 +jnz short ln2280 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2280: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +ln2281: +add dx,dx +lahf +seto ch +or al,ch +dec cl +jnz short ln2281 +mov [ebp+__dreg+ebx*4],dx +mov cl,ah +and cl,1 +mov [ebp+__xflag],cl +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E368 - E36F +Y368: +and ebx,byte 7 +mov ecx,[ebp+__dreg+4] +and ecx,byte 63 +jnz short ln2282 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2282: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2283 +sub cl, 31 +shl word[ebp+__dreg+ebx*4], 31 +jmp short ln2284 +ln2283: +shl word[ebp+__dreg+ebx*4],cl +ln2284: +lahf +setc [ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E370 - E377 +Y370: +and ebx,byte 7 +mov ecx,[ebp+__dreg+4] +and ecx,byte 63 +jnz short ln2285 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +and ah,0FEh +or ah,[ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2285: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +cmp cl, 32 +jb short ln2286 +sub cl, 31 +shr al, 1 +rcl dx, 31 +rcl dx,cl +jmp short ln2287 +ln2286: +shr al, 1 +rcl dx,cl +ln2287: +adc al,al +or dx,dx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E378 - E37F +Y378: +and ebx,byte 7 +mov ecx,[ebp+__dreg+4] +and ecx,byte 63 +jnz short ln2288 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2288: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +cmp cl, 32 +jb short ln2289 +sub cl, 31 +rol dx, 31 +rol dx,cl +jmp short ln2290 +ln2289: +rol dx,cl +ln2290: +adc al,al +or dx,dx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E380 - E387 +Y380: +and ebx,byte 7 +sal dword[ebp+__dreg+ebx*4],1 +lahf +seto al +setc [ebp+__xflag] +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E388 - E38F +Y388: +and ebx,byte 7 +mov al,0 +shl dword[ebp+__dreg+ebx*4],1 +lahf +setc [ebp+__xflag] +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E390 - E397 +Y390: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +shr al,1 +rcl edx,1 +adc al,al +or edx,edx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E398 - E39F +Y398: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +rol edx,1 +adc al,al +or edx,edx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E3A0 - E3A7 +Y3A0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+4] +and ecx,byte 63 +jnz short ln2291 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2291: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +ln2292: +add edx,edx +lahf +seto ch +or al,ch +dec cl +jnz short ln2292 +mov [ebp+__dreg+ebx*4],edx +mov cl,ah +and cl,1 +mov [ebp+__xflag],cl +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E3A8 - E3AF +Y3A8: +and ebx,byte 7 +mov ecx,[ebp+__dreg+4] +and ecx,byte 63 +jnz short ln2293 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2293: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2294 +sub cl, 31 +shl dword[ebp+__dreg+ebx*4], 31 +jmp short ln2295 +ln2294: +shl dword[ebp+__dreg+ebx*4],cl +ln2295: +lahf +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E3B0 - E3B7 +Y3B0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+4] +and ecx,byte 63 +jnz short ln2296 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +and ah,0FEh +or ah,[ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2296: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +cmp cl, 32 +jb short ln2297 +sub cl, 31 +shr al, 1 +rcl edx, 31 +rcl edx,cl +jmp short ln2298 +ln2297: +shr al, 1 +rcl edx,cl +ln2298: +adc al,al +or edx,edx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E3B8 - E3BF +Y3B8: +and ebx,byte 7 +mov ecx,[ebp+__dreg+4] +and ecx,byte 63 +jnz short ln2299 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2299: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +cmp cl, 32 +jb short ln2300 +sub cl, 31 +rol edx, 31 +rol edx,cl +jmp short ln2301 +ln2300: +rol edx,cl +ln2301: +adc al,al +or edx,edx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E3D0 - E3D7 +Y3D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +shl cx,1 +lahf +mov al,0 +setc [ebp+__xflag] +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E3D8 - E3DF +Y3D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +shl cx,1 +lahf +mov al,0 +setc [ebp+__xflag] +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E3E0 - E3E7 +Y3E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +shl cx,1 +lahf +mov al,0 +setc [ebp+__xflag] +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E3E8 - E3EF +Y3E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +shl cx,1 +lahf +mov al,0 +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E3F0 - E3F7 +Y3F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +shl cx,1 +lahf +mov al,0 +setc [ebp+__xflag] +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode E3F8 +Y3F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +shl cx,1 +lahf +mov al,0 +setc [ebp+__xflag] +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode E3F9 +Y3F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +shl cx,1 +lahf +mov al,0 +setc [ebp+__xflag] +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E400 - E407 +Y400: +and ebx,byte 7 +mov al,0 +sar byte[ebp+__dreg+ebx*4],2 +lahf +setc [ebp+__xflag] +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E408 - E40F +Y408: +and ebx,byte 7 +mov al,0 +shr byte[ebp+__dreg+ebx*4],2 +lahf +setc [ebp+__xflag] +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E410 - E417 +Y410: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +shr al,1 +rcr dl,2 +adc al,al +or dl,dl +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E418 - E41F +Y418: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +ror dl,2 +adc al,al +or dl,dl +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E420 - E427 +Y420: +and ebx,byte 7 +mov ecx,[ebp+__dreg+8] +and ecx,byte 63 +jnz short ln2302 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2302: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2303 +sub cl, 31 +sar byte[ebp+__dreg+ebx*4], 31 +jmp short ln2304 +ln2303: +sar byte[ebp+__dreg+ebx*4],cl +ln2304: +lahf +setc [ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E428 - E42F +Y428: +and ebx,byte 7 +mov ecx,[ebp+__dreg+8] +and ecx,byte 63 +jnz short ln2305 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2305: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2306 +sub cl, 31 +shr byte[ebp+__dreg+ebx*4], 31 +jmp short ln2307 +ln2306: +shr byte[ebp+__dreg+ebx*4],cl +ln2307: +lahf +setc [ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E430 - E437 +Y430: +and ebx,byte 7 +mov ecx,[ebp+__dreg+8] +and ecx,byte 63 +jnz short ln2308 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +and ah,0FEh +or ah,[ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2308: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +cmp cl, 32 +jb short ln2309 +sub cl, 31 +shr al, 1 +rcr dl, 31 +rcr dl,cl +jmp short ln2310 +ln2309: +shr al, 1 +rcr dl,cl +ln2310: +adc al,al +or dl,dl +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E438 - E43F +Y438: +and ebx,byte 7 +mov ecx,[ebp+__dreg+8] +and ecx,byte 63 +jnz short ln2311 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2311: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +cmp cl, 32 +jb short ln2312 +sub cl, 31 +ror dl, 31 +ror dl,cl +jmp short ln2313 +ln2312: +ror dl,cl +ln2313: +adc al,al +or dl,dl +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E440 - E447 +Y440: +and ebx,byte 7 +mov al,0 +sar word[ebp+__dreg+ebx*4],2 +lahf +setc [ebp+__xflag] +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E448 - E44F +Y448: +and ebx,byte 7 +mov al,0 +shr word[ebp+__dreg+ebx*4],2 +lahf +setc [ebp+__xflag] +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E450 - E457 +Y450: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +shr al,1 +rcr dx,2 +adc al,al +or dx,dx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E458 - E45F +Y458: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +ror dx,2 +adc al,al +or dx,dx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E460 - E467 +Y460: +and ebx,byte 7 +mov ecx,[ebp+__dreg+8] +and ecx,byte 63 +jnz short ln2314 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2314: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2315 +sub cl, 31 +sar word[ebp+__dreg+ebx*4], 31 +jmp short ln2316 +ln2315: +sar word[ebp+__dreg+ebx*4],cl +ln2316: +lahf +setc [ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E468 - E46F +Y468: +and ebx,byte 7 +mov ecx,[ebp+__dreg+8] +and ecx,byte 63 +jnz short ln2317 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2317: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2318 +sub cl, 31 +shr word[ebp+__dreg+ebx*4], 31 +jmp short ln2319 +ln2318: +shr word[ebp+__dreg+ebx*4],cl +ln2319: +lahf +setc [ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E470 - E477 +Y470: +and ebx,byte 7 +mov ecx,[ebp+__dreg+8] +and ecx,byte 63 +jnz short ln2320 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +and ah,0FEh +or ah,[ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2320: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +cmp cl, 32 +jb short ln2321 +sub cl, 31 +shr al, 1 +rcr dx, 31 +rcr dx,cl +jmp short ln2322 +ln2321: +shr al, 1 +rcr dx,cl +ln2322: +adc al,al +or dx,dx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E478 - E47F +Y478: +and ebx,byte 7 +mov ecx,[ebp+__dreg+8] +and ecx,byte 63 +jnz short ln2323 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2323: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +cmp cl, 32 +jb short ln2324 +sub cl, 31 +ror dx, 31 +ror dx,cl +jmp short ln2325 +ln2324: +ror dx,cl +ln2325: +adc al,al +or dx,dx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E480 - E487 +Y480: +and ebx,byte 7 +mov al,0 +sar dword[ebp+__dreg+ebx*4],2 +lahf +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E488 - E48F +Y488: +and ebx,byte 7 +mov al,0 +shr dword[ebp+__dreg+ebx*4],2 +lahf +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E490 - E497 +Y490: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +shr al,1 +rcr edx,2 +adc al,al +or edx,edx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E498 - E49F +Y498: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +ror edx,2 +adc al,al +or edx,edx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E4A0 - E4A7 +Y4A0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+8] +and ecx,byte 63 +jnz short ln2326 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2326: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2327 +sub cl, 31 +sar dword[ebp+__dreg+ebx*4], 31 +jmp short ln2328 +ln2327: +sar dword[ebp+__dreg+ebx*4],cl +ln2328: +lahf +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E4A8 - E4AF +Y4A8: +and ebx,byte 7 +mov ecx,[ebp+__dreg+8] +and ecx,byte 63 +jnz short ln2329 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2329: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2330 +sub cl, 31 +shr dword[ebp+__dreg+ebx*4], 31 +jmp short ln2331 +ln2330: +shr dword[ebp+__dreg+ebx*4],cl +ln2331: +lahf +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E4B0 - E4B7 +Y4B0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+8] +and ecx,byte 63 +jnz short ln2332 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +and ah,0FEh +or ah,[ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2332: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +cmp cl, 32 +jb short ln2333 +sub cl, 31 +shr al, 1 +rcr edx, 31 +rcr edx,cl +jmp short ln2334 +ln2333: +shr al, 1 +rcr edx,cl +ln2334: +adc al,al +or edx,edx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E4B8 - E4BF +Y4B8: +and ebx,byte 7 +mov ecx,[ebp+__dreg+8] +and ecx,byte 63 +jnz short ln2335 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2335: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +cmp cl, 32 +jb short ln2336 +sub cl, 31 +ror edx, 31 +ror edx,cl +jmp short ln2337 +ln2336: +ror edx,cl +ln2337: +adc al,al +or edx,edx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E4D0 - E4D7 +Y4D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov al,[ebp+__xflag] +shr al,1 +rcr cx,1 +adc al,al +test cx,cx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E4D8 - E4DF +Y4D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov al,[ebp+__xflag] +shr al,1 +rcr cx,1 +adc al,al +test cx,cx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E4E0 - E4E7 +Y4E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov al,[ebp+__xflag] +shr al,1 +rcr cx,1 +adc al,al +test cx,cx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E4E8 - E4EF +Y4E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov al,[ebp+__xflag] +shr al,1 +rcr cx,1 +adc al,al +test cx,cx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E4F0 - E4F7 +Y4F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov al,[ebp+__xflag] +shr al,1 +rcr cx,1 +adc al,al +test cx,cx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode E4F8 +Y4F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +mov al,[ebp+__xflag] +shr al,1 +rcr cx,1 +adc al,al +test cx,cx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode E4F9 +Y4F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +mov al,[ebp+__xflag] +shr al,1 +rcr cx,1 +adc al,al +test cx,cx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E500 - E507 +Y500: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +add dl,dl +seto ch +or al,ch +add dl,dl +lahf +seto ch +or al,ch +mov [ebp+__dreg+ebx*4],dl +mov cl,ah +and cl,1 +mov [ebp+__xflag],cl +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E508 - E50F +Y508: +and ebx,byte 7 +mov al,0 +shl byte[ebp+__dreg+ebx*4],2 +lahf +setc [ebp+__xflag] +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E510 - E517 +Y510: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +shr al,1 +rcl dl,2 +adc al,al +or dl,dl +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E518 - E51F +Y518: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +rol dl,2 +adc al,al +or dl,dl +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E520 - E527 +Y520: +and ebx,byte 7 +mov ecx,[ebp+__dreg+8] +and ecx,byte 63 +jnz short ln2338 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2338: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +ln2339: +add dl,dl +lahf +seto ch +or al,ch +dec cl +jnz short ln2339 +mov [ebp+__dreg+ebx*4],dl +mov cl,ah +and cl,1 +mov [ebp+__xflag],cl +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E528 - E52F +Y528: +and ebx,byte 7 +mov ecx,[ebp+__dreg+8] +and ecx,byte 63 +jnz short ln2340 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2340: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2341 +sub cl, 31 +shl byte[ebp+__dreg+ebx*4], 31 +jmp short ln2342 +ln2341: +shl byte[ebp+__dreg+ebx*4],cl +ln2342: +lahf +setc [ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E530 - E537 +Y530: +and ebx,byte 7 +mov ecx,[ebp+__dreg+8] +and ecx,byte 63 +jnz short ln2343 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +and ah,0FEh +or ah,[ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2343: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +cmp cl, 32 +jb short ln2344 +sub cl, 31 +shr al, 1 +rcl dl, 31 +rcl dl,cl +jmp short ln2345 +ln2344: +shr al, 1 +rcl dl,cl +ln2345: +adc al,al +or dl,dl +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E538 - E53F +Y538: +and ebx,byte 7 +mov ecx,[ebp+__dreg+8] +and ecx,byte 63 +jnz short ln2346 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2346: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +cmp cl, 32 +jb short ln2347 +sub cl, 31 +rol dl, 31 +rol dl,cl +jmp short ln2348 +ln2347: +rol dl,cl +ln2348: +adc al,al +or dl,dl +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E540 - E547 +Y540: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +add dx,dx +seto ch +or al,ch +add dx,dx +lahf +seto ch +or al,ch +mov [ebp+__dreg+ebx*4],dx +mov cl,ah +and cl,1 +mov [ebp+__xflag],cl +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E548 - E54F +Y548: +and ebx,byte 7 +mov al,0 +shl word[ebp+__dreg+ebx*4],2 +lahf +setc [ebp+__xflag] +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E550 - E557 +Y550: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +shr al,1 +rcl dx,2 +adc al,al +or dx,dx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E558 - E55F +Y558: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +rol dx,2 +adc al,al +or dx,dx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 10 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E560 - E567 +Y560: +and ebx,byte 7 +mov ecx,[ebp+__dreg+8] +and ecx,byte 63 +jnz short ln2349 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2349: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +ln2350: +add dx,dx +lahf +seto ch +or al,ch +dec cl +jnz short ln2350 +mov [ebp+__dreg+ebx*4],dx +mov cl,ah +and cl,1 +mov [ebp+__xflag],cl +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E568 - E56F +Y568: +and ebx,byte 7 +mov ecx,[ebp+__dreg+8] +and ecx,byte 63 +jnz short ln2351 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2351: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2352 +sub cl, 31 +shl word[ebp+__dreg+ebx*4], 31 +jmp short ln2353 +ln2352: +shl word[ebp+__dreg+ebx*4],cl +ln2353: +lahf +setc [ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E570 - E577 +Y570: +and ebx,byte 7 +mov ecx,[ebp+__dreg+8] +and ecx,byte 63 +jnz short ln2354 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +and ah,0FEh +or ah,[ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2354: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +cmp cl, 32 +jb short ln2355 +sub cl, 31 +shr al, 1 +rcl dx, 31 +rcl dx,cl +jmp short ln2356 +ln2355: +shr al, 1 +rcl dx,cl +ln2356: +adc al,al +or dx,dx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E578 - E57F +Y578: +and ebx,byte 7 +mov ecx,[ebp+__dreg+8] +and ecx,byte 63 +jnz short ln2357 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2357: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +cmp cl, 32 +jb short ln2358 +sub cl, 31 +rol dx, 31 +rol dx,cl +jmp short ln2359 +ln2358: +rol dx,cl +ln2359: +adc al,al +or dx,dx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E580 - E587 +Y580: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +add edx,edx +seto ch +or al,ch +add edx,edx +lahf +seto ch +or al,ch +mov [ebp+__dreg+ebx*4],edx +mov cl,ah +and cl,1 +mov [ebp+__xflag],cl +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E588 - E58F +Y588: +and ebx,byte 7 +mov al,0 +shl dword[ebp+__dreg+ebx*4],2 +lahf +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E590 - E597 +Y590: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +shr al,1 +rcl edx,2 +adc al,al +or edx,edx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E598 - E59F +Y598: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +rol edx,2 +adc al,al +or edx,edx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E5A0 - E5A7 +Y5A0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+8] +and ecx,byte 63 +jnz short ln2360 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2360: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +ln2361: +add edx,edx +lahf +seto ch +or al,ch +dec cl +jnz short ln2361 +mov [ebp+__dreg+ebx*4],edx +mov cl,ah +and cl,1 +mov [ebp+__xflag],cl +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E5A8 - E5AF +Y5A8: +and ebx,byte 7 +mov ecx,[ebp+__dreg+8] +and ecx,byte 63 +jnz short ln2362 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2362: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2363 +sub cl, 31 +shl dword[ebp+__dreg+ebx*4], 31 +jmp short ln2364 +ln2363: +shl dword[ebp+__dreg+ebx*4],cl +ln2364: +lahf +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E5B0 - E5B7 +Y5B0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+8] +and ecx,byte 63 +jnz short ln2365 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +and ah,0FEh +or ah,[ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2365: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +cmp cl, 32 +jb short ln2366 +sub cl, 31 +shr al, 1 +rcl edx, 31 +rcl edx,cl +jmp short ln2367 +ln2366: +shr al, 1 +rcl edx,cl +ln2367: +adc al,al +or edx,edx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E5B8 - E5BF +Y5B8: +and ebx,byte 7 +mov ecx,[ebp+__dreg+8] +and ecx,byte 63 +jnz short ln2368 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2368: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +cmp cl, 32 +jb short ln2369 +sub cl, 31 +rol edx, 31 +rol edx,cl +jmp short ln2370 +ln2369: +rol edx,cl +ln2370: +adc al,al +or edx,edx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E5D0 - E5D7 +Y5D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov al,[ebp+__xflag] +shr al,1 +rcl cx,1 +adc al,al +test cx,cx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E5D8 - E5DF +Y5D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov al,[ebp+__xflag] +shr al,1 +rcl cx,1 +adc al,al +test cx,cx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E5E0 - E5E7 +Y5E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov al,[ebp+__xflag] +shr al,1 +rcl cx,1 +adc al,al +test cx,cx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E5E8 - E5EF +Y5E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov al,[ebp+__xflag] +shr al,1 +rcl cx,1 +adc al,al +test cx,cx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E5F0 - E5F7 +Y5F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov al,[ebp+__xflag] +shr al,1 +rcl cx,1 +adc al,al +test cx,cx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode E5F8 +Y5F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +mov al,[ebp+__xflag] +shr al,1 +rcl cx,1 +adc al,al +test cx,cx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode E5F9 +Y5F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +mov al,[ebp+__xflag] +shr al,1 +rcl cx,1 +adc al,al +test cx,cx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E600 - E607 +Y600: +and ebx,byte 7 +mov al,0 +sar byte[ebp+__dreg+ebx*4],3 +lahf +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E608 - E60F +Y608: +and ebx,byte 7 +mov al,0 +shr byte[ebp+__dreg+ebx*4],3 +lahf +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E610 - E617 +Y610: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +shr al,1 +rcr dl,3 +adc al,al +or dl,dl +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E618 - E61F +Y618: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +ror dl,3 +adc al,al +or dl,dl +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E620 - E627 +Y620: +and ebx,byte 7 +mov ecx,[ebp+__dreg+12] +and ecx,byte 63 +jnz short ln2371 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2371: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2372 +sub cl, 31 +sar byte[ebp+__dreg+ebx*4], 31 +jmp short ln2373 +ln2372: +sar byte[ebp+__dreg+ebx*4],cl +ln2373: +lahf +setc [ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E628 - E62F +Y628: +and ebx,byte 7 +mov ecx,[ebp+__dreg+12] +and ecx,byte 63 +jnz short ln2374 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2374: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2375 +sub cl, 31 +shr byte[ebp+__dreg+ebx*4], 31 +jmp short ln2376 +ln2375: +shr byte[ebp+__dreg+ebx*4],cl +ln2376: +lahf +setc [ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E630 - E637 +Y630: +and ebx,byte 7 +mov ecx,[ebp+__dreg+12] +and ecx,byte 63 +jnz short ln2377 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +and ah,0FEh +or ah,[ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2377: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +cmp cl, 32 +jb short ln2378 +sub cl, 31 +shr al, 1 +rcr dl, 31 +rcr dl,cl +jmp short ln2379 +ln2378: +shr al, 1 +rcr dl,cl +ln2379: +adc al,al +or dl,dl +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E638 - E63F +Y638: +and ebx,byte 7 +mov ecx,[ebp+__dreg+12] +and ecx,byte 63 +jnz short ln2380 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2380: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +cmp cl, 32 +jb short ln2381 +sub cl, 31 +ror dl, 31 +ror dl,cl +jmp short ln2382 +ln2381: +ror dl,cl +ln2382: +adc al,al +or dl,dl +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E640 - E647 +Y640: +and ebx,byte 7 +mov al,0 +sar word[ebp+__dreg+ebx*4],3 +lahf +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E648 - E64F +Y648: +and ebx,byte 7 +mov al,0 +shr word[ebp+__dreg+ebx*4],3 +lahf +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E650 - E657 +Y650: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +shr al,1 +rcr dx,3 +adc al,al +or dx,dx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E658 - E65F +Y658: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +ror dx,3 +adc al,al +or dx,dx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E660 - E667 +Y660: +and ebx,byte 7 +mov ecx,[ebp+__dreg+12] +and ecx,byte 63 +jnz short ln2383 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2383: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2384 +sub cl, 31 +sar word[ebp+__dreg+ebx*4], 31 +jmp short ln2385 +ln2384: +sar word[ebp+__dreg+ebx*4],cl +ln2385: +lahf +setc [ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E668 - E66F +Y668: +and ebx,byte 7 +mov ecx,[ebp+__dreg+12] +and ecx,byte 63 +jnz short ln2386 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2386: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2387 +sub cl, 31 +shr word[ebp+__dreg+ebx*4], 31 +jmp short ln2388 +ln2387: +shr word[ebp+__dreg+ebx*4],cl +ln2388: +lahf +setc [ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E670 - E677 +Y670: +and ebx,byte 7 +mov ecx,[ebp+__dreg+12] +and ecx,byte 63 +jnz short ln2389 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +and ah,0FEh +or ah,[ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2389: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +cmp cl, 32 +jb short ln2390 +sub cl, 31 +shr al, 1 +rcr dx, 31 +rcr dx,cl +jmp short ln2391 +ln2390: +shr al, 1 +rcr dx,cl +ln2391: +adc al,al +or dx,dx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E678 - E67F +Y678: +and ebx,byte 7 +mov ecx,[ebp+__dreg+12] +and ecx,byte 63 +jnz short ln2392 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2392: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +cmp cl, 32 +jb short ln2393 +sub cl, 31 +ror dx, 31 +ror dx,cl +jmp short ln2394 +ln2393: +ror dx,cl +ln2394: +adc al,al +or dx,dx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E680 - E687 +Y680: +and ebx,byte 7 +mov al,0 +sar dword[ebp+__dreg+ebx*4],3 +lahf +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E688 - E68F +Y688: +and ebx,byte 7 +mov al,0 +shr dword[ebp+__dreg+ebx*4],3 +lahf +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E690 - E697 +Y690: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +shr al,1 +rcr edx,3 +adc al,al +or edx,edx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E698 - E69F +Y698: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +ror edx,3 +adc al,al +or edx,edx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E6A0 - E6A7 +Y6A0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+12] +and ecx,byte 63 +jnz short ln2395 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2395: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2396 +sub cl, 31 +sar dword[ebp+__dreg+ebx*4], 31 +jmp short ln2397 +ln2396: +sar dword[ebp+__dreg+ebx*4],cl +ln2397: +lahf +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E6A8 - E6AF +Y6A8: +and ebx,byte 7 +mov ecx,[ebp+__dreg+12] +and ecx,byte 63 +jnz short ln2398 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2398: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2399 +sub cl, 31 +shr dword[ebp+__dreg+ebx*4], 31 +jmp short ln2400 +ln2399: +shr dword[ebp+__dreg+ebx*4],cl +ln2400: +lahf +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E6B0 - E6B7 +Y6B0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+12] +and ecx,byte 63 +jnz short ln2401 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +and ah,0FEh +or ah,[ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2401: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +cmp cl, 32 +jb short ln2402 +sub cl, 31 +shr al, 1 +rcr edx, 31 +rcr edx,cl +jmp short ln2403 +ln2402: +shr al, 1 +rcr edx,cl +ln2403: +adc al,al +or edx,edx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E6B8 - E6BF +Y6B8: +and ebx,byte 7 +mov ecx,[ebp+__dreg+12] +and ecx,byte 63 +jnz short ln2404 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2404: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +cmp cl, 32 +jb short ln2405 +sub cl, 31 +ror edx, 31 +ror edx,cl +jmp short ln2406 +ln2405: +ror edx,cl +ln2406: +adc al,al +or edx,edx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E6D0 - E6D7 +Y6D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov al,0 +ror cx,1 +adc al,al +test cx,cx +lahf +or ah,al +mov al,0 +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E6D8 - E6DF +Y6D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov al,0 +ror cx,1 +adc al,al +test cx,cx +lahf +or ah,al +mov al,0 +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E6E0 - E6E7 +Y6E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov al,0 +ror cx,1 +adc al,al +test cx,cx +lahf +or ah,al +mov al,0 +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E6E8 - E6EF +Y6E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov al,0 +ror cx,1 +adc al,al +test cx,cx +lahf +or ah,al +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E6F0 - E6F7 +Y6F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov al,0 +ror cx,1 +adc al,al +test cx,cx +lahf +or ah,al +mov al,0 +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode E6F8 +Y6F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +mov al,0 +ror cx,1 +adc al,al +test cx,cx +lahf +or ah,al +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode E6F9 +Y6F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +mov al,0 +ror cx,1 +adc al,al +test cx,cx +lahf +or ah,al +mov al,0 +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E700 - E707 +Y700: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +add dl,dl +seto ch +or al,ch +add dl,dl +seto ch +or al,ch +add dl,dl +lahf +seto ch +or al,ch +mov [ebp+__dreg+ebx*4],dl +mov cl,ah +and cl,1 +mov [ebp+__xflag],cl +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E708 - E70F +Y708: +and ebx,byte 7 +mov al,0 +shl byte[ebp+__dreg+ebx*4],3 +lahf +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E710 - E717 +Y710: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +shr al,1 +rcl dl,3 +adc al,al +or dl,dl +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E718 - E71F +Y718: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +rol dl,3 +adc al,al +or dl,dl +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E720 - E727 +Y720: +and ebx,byte 7 +mov ecx,[ebp+__dreg+12] +and ecx,byte 63 +jnz short ln2407 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2407: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +ln2408: +add dl,dl +lahf +seto ch +or al,ch +dec cl +jnz short ln2408 +mov [ebp+__dreg+ebx*4],dl +mov cl,ah +and cl,1 +mov [ebp+__xflag],cl +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E728 - E72F +Y728: +and ebx,byte 7 +mov ecx,[ebp+__dreg+12] +and ecx,byte 63 +jnz short ln2409 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2409: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2410 +sub cl, 31 +shl byte[ebp+__dreg+ebx*4], 31 +jmp short ln2411 +ln2410: +shl byte[ebp+__dreg+ebx*4],cl +ln2411: +lahf +setc [ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E730 - E737 +Y730: +and ebx,byte 7 +mov ecx,[ebp+__dreg+12] +and ecx,byte 63 +jnz short ln2412 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +and ah,0FEh +or ah,[ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2412: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +cmp cl, 32 +jb short ln2413 +sub cl, 31 +shr al, 1 +rcl dl, 31 +rcl dl,cl +jmp short ln2414 +ln2413: +shr al, 1 +rcl dl,cl +ln2414: +adc al,al +or dl,dl +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E738 - E73F +Y738: +and ebx,byte 7 +mov ecx,[ebp+__dreg+12] +and ecx,byte 63 +jnz short ln2415 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2415: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +cmp cl, 32 +jb short ln2416 +sub cl, 31 +rol dl, 31 +rol dl,cl +jmp short ln2417 +ln2416: +rol dl,cl +ln2417: +adc al,al +or dl,dl +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E740 - E747 +Y740: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +add dx,dx +seto ch +or al,ch +add dx,dx +seto ch +or al,ch +add dx,dx +lahf +seto ch +or al,ch +mov [ebp+__dreg+ebx*4],dx +mov cl,ah +and cl,1 +mov [ebp+__xflag],cl +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E748 - E74F +Y748: +and ebx,byte 7 +mov al,0 +shl word[ebp+__dreg+ebx*4],3 +lahf +setc [ebp+__xflag] +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E750 - E757 +Y750: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +shr al,1 +rcl dx,3 +adc al,al +or dx,dx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E758 - E75F +Y758: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +rol dx,3 +adc al,al +or dx,dx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E760 - E767 +Y760: +and ebx,byte 7 +mov ecx,[ebp+__dreg+12] +and ecx,byte 63 +jnz short ln2418 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2418: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +ln2419: +add dx,dx +lahf +seto ch +or al,ch +dec cl +jnz short ln2419 +mov [ebp+__dreg+ebx*4],dx +mov cl,ah +and cl,1 +mov [ebp+__xflag],cl +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E768 - E76F +Y768: +and ebx,byte 7 +mov ecx,[ebp+__dreg+12] +and ecx,byte 63 +jnz short ln2420 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2420: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2421 +sub cl, 31 +shl word[ebp+__dreg+ebx*4], 31 +jmp short ln2422 +ln2421: +shl word[ebp+__dreg+ebx*4],cl +ln2422: +lahf +setc [ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E770 - E777 +Y770: +and ebx,byte 7 +mov ecx,[ebp+__dreg+12] +and ecx,byte 63 +jnz short ln2423 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +and ah,0FEh +or ah,[ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2423: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +cmp cl, 32 +jb short ln2424 +sub cl, 31 +shr al, 1 +rcl dx, 31 +rcl dx,cl +jmp short ln2425 +ln2424: +shr al, 1 +rcl dx,cl +ln2425: +adc al,al +or dx,dx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E778 - E77F +Y778: +and ebx,byte 7 +mov ecx,[ebp+__dreg+12] +and ecx,byte 63 +jnz short ln2426 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2426: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +cmp cl, 32 +jb short ln2427 +sub cl, 31 +rol dx, 31 +rol dx,cl +jmp short ln2428 +ln2427: +rol dx,cl +ln2428: +adc al,al +or dx,dx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E780 - E787 +Y780: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +add edx,edx +seto ch +or al,ch +add edx,edx +seto ch +or al,ch +add edx,edx +lahf +seto ch +or al,ch +mov [ebp+__dreg+ebx*4],edx +mov cl,ah +and cl,1 +mov [ebp+__xflag],cl +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E788 - E78F +Y788: +and ebx,byte 7 +mov al,0 +shl dword[ebp+__dreg+ebx*4],3 +lahf +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E790 - E797 +Y790: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +shr al,1 +rcl edx,3 +adc al,al +or edx,edx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E798 - E79F +Y798: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +rol edx,3 +adc al,al +or edx,edx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E7A0 - E7A7 +Y7A0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+12] +and ecx,byte 63 +jnz short ln2429 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2429: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +ln2430: +add edx,edx +lahf +seto ch +or al,ch +dec cl +jnz short ln2430 +mov [ebp+__dreg+ebx*4],edx +mov cl,ah +and cl,1 +mov [ebp+__xflag],cl +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E7A8 - E7AF +Y7A8: +and ebx,byte 7 +mov ecx,[ebp+__dreg+12] +and ecx,byte 63 +jnz short ln2431 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2431: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2432 +sub cl, 31 +shl dword[ebp+__dreg+ebx*4], 31 +jmp short ln2433 +ln2432: +shl dword[ebp+__dreg+ebx*4],cl +ln2433: +lahf +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E7B0 - E7B7 +Y7B0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+12] +and ecx,byte 63 +jnz short ln2434 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +and ah,0FEh +or ah,[ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2434: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +cmp cl, 32 +jb short ln2435 +sub cl, 31 +shr al, 1 +rcl edx, 31 +rcl edx,cl +jmp short ln2436 +ln2435: +shr al, 1 +rcl edx,cl +ln2436: +adc al,al +or edx,edx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E7B8 - E7BF +Y7B8: +and ebx,byte 7 +mov ecx,[ebp+__dreg+12] +and ecx,byte 63 +jnz short ln2437 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2437: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +cmp cl, 32 +jb short ln2438 +sub cl, 31 +rol edx, 31 +rol edx,cl +jmp short ln2439 +ln2438: +rol edx,cl +ln2439: +adc al,al +or edx,edx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E7D0 - E7D7 +Y7D0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov al,0 +rol cx,1 +adc al,al +test cx,cx +lahf +or ah,al +mov al,0 +call writememoryword +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E7D8 - E7DF +Y7D8: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +call readmemoryword +mov al,0 +rol cx,1 +adc al,al +test cx,cx +lahf +or ah,al +mov al,0 +call writememoryword +add edx,byte 2 +mov [ebp+__areg+ebx*4],edx +sub edi,byte 12 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E7E0 - E7E7 +Y7E0: +and ebx,byte 7 +mov edx,[ebp+__areg+ebx*4] +sub edx,byte 2 +call readmemoryword +mov al,0 +rol cx,1 +adc al,al +test cx,cx +lahf +or ah,al +mov al,0 +call writememoryword +mov [ebp+__areg+ebx*4],edx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E7E8 - E7EF +Y7E8: +and ebx,byte 7 +movsx edx,word[esi] +add esi,byte 2 +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov al,0 +rol cx,1 +adc al,al +test cx,cx +lahf +or ah,al +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E7F0 - E7F7 +Y7F0: +and ebx,byte 7 +call decode_ext +add edx,[ebp+__areg+ebx*4] +call readmemoryword +mov al,0 +rol cx,1 +adc al,al +test cx,cx +lahf +or ah,al +mov al,0 +call writememoryword +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode E7F8 +Y7F8: +movsx edx,word[esi] +add esi,byte 2 +call readmemoryword +mov al,0 +rol cx,1 +adc al,al +test cx,cx +lahf +or ah,al +mov al,0 +call writememoryword +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcode E7F9 +Y7F9: +mov edx,dword[esi] +add esi,byte 4 +rol edx,16 +call readmemoryword +mov al,0 +rol cx,1 +adc al,al +test cx,cx +lahf +or ah,al +mov al,0 +call writememoryword +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E800 - E807 +Y800: +and ebx,byte 7 +mov al,0 +sar byte[ebp+__dreg+ebx*4],4 +lahf +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E808 - E80F +Y808: +and ebx,byte 7 +mov al,0 +shr byte[ebp+__dreg+ebx*4],4 +lahf +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E810 - E817 +Y810: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +shr al,1 +rcr dl,4 +adc al,al +or dl,dl +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E818 - E81F +Y818: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +ror dl,4 +adc al,al +or dl,dl +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E820 - E827 +Y820: +and ebx,byte 7 +mov ecx,[ebp+__dreg+16] +and ecx,byte 63 +jnz short ln2440 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2440: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2441 +sub cl, 31 +sar byte[ebp+__dreg+ebx*4], 31 +jmp short ln2442 +ln2441: +sar byte[ebp+__dreg+ebx*4],cl +ln2442: +lahf +setc [ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E828 - E82F +Y828: +and ebx,byte 7 +mov ecx,[ebp+__dreg+16] +and ecx,byte 63 +jnz short ln2443 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2443: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2444 +sub cl, 31 +shr byte[ebp+__dreg+ebx*4], 31 +jmp short ln2445 +ln2444: +shr byte[ebp+__dreg+ebx*4],cl +ln2445: +lahf +setc [ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E830 - E837 +Y830: +and ebx,byte 7 +mov ecx,[ebp+__dreg+16] +and ecx,byte 63 +jnz short ln2446 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +and ah,0FEh +or ah,[ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2446: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +cmp cl, 32 +jb short ln2447 +sub cl, 31 +shr al, 1 +rcr dl, 31 +rcr dl,cl +jmp short ln2448 +ln2447: +shr al, 1 +rcr dl,cl +ln2448: +adc al,al +or dl,dl +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E838 - E83F +Y838: +and ebx,byte 7 +mov ecx,[ebp+__dreg+16] +and ecx,byte 63 +jnz short ln2449 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2449: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +cmp cl, 32 +jb short ln2450 +sub cl, 31 +ror dl, 31 +ror dl,cl +jmp short ln2451 +ln2450: +ror dl,cl +ln2451: +adc al,al +or dl,dl +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E840 - E847 +Y840: +and ebx,byte 7 +mov al,0 +sar word[ebp+__dreg+ebx*4],4 +lahf +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E848 - E84F +Y848: +and ebx,byte 7 +mov al,0 +shr word[ebp+__dreg+ebx*4],4 +lahf +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E850 - E857 +Y850: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +shr al,1 +rcr dx,4 +adc al,al +or dx,dx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E858 - E85F +Y858: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +ror dx,4 +adc al,al +or dx,dx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E860 - E867 +Y860: +and ebx,byte 7 +mov ecx,[ebp+__dreg+16] +and ecx,byte 63 +jnz short ln2452 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2452: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2453 +sub cl, 31 +sar word[ebp+__dreg+ebx*4], 31 +jmp short ln2454 +ln2453: +sar word[ebp+__dreg+ebx*4],cl +ln2454: +lahf +setc [ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E868 - E86F +Y868: +and ebx,byte 7 +mov ecx,[ebp+__dreg+16] +and ecx,byte 63 +jnz short ln2455 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2455: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2456 +sub cl, 31 +shr word[ebp+__dreg+ebx*4], 31 +jmp short ln2457 +ln2456: +shr word[ebp+__dreg+ebx*4],cl +ln2457: +lahf +setc [ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E870 - E877 +Y870: +and ebx,byte 7 +mov ecx,[ebp+__dreg+16] +and ecx,byte 63 +jnz short ln2458 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +and ah,0FEh +or ah,[ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2458: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +cmp cl, 32 +jb short ln2459 +sub cl, 31 +shr al, 1 +rcr dx, 31 +rcr dx,cl +jmp short ln2460 +ln2459: +shr al, 1 +rcr dx,cl +ln2460: +adc al,al +or dx,dx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E878 - E87F +Y878: +and ebx,byte 7 +mov ecx,[ebp+__dreg+16] +and ecx,byte 63 +jnz short ln2461 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2461: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +cmp cl, 32 +jb short ln2462 +sub cl, 31 +ror dx, 31 +ror dx,cl +jmp short ln2463 +ln2462: +ror dx,cl +ln2463: +adc al,al +or dx,dx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E880 - E887 +Y880: +and ebx,byte 7 +mov al,0 +sar dword[ebp+__dreg+ebx*4],4 +lahf +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E888 - E88F +Y888: +and ebx,byte 7 +mov al,0 +shr dword[ebp+__dreg+ebx*4],4 +lahf +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E890 - E897 +Y890: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +shr al,1 +rcr edx,4 +adc al,al +or edx,edx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E898 - E89F +Y898: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +ror edx,4 +adc al,al +or edx,edx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E8A0 - E8A7 +Y8A0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+16] +and ecx,byte 63 +jnz short ln2464 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2464: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2465 +sub cl, 31 +sar dword[ebp+__dreg+ebx*4], 31 +jmp short ln2466 +ln2465: +sar dword[ebp+__dreg+ebx*4],cl +ln2466: +lahf +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E8A8 - E8AF +Y8A8: +and ebx,byte 7 +mov ecx,[ebp+__dreg+16] +and ecx,byte 63 +jnz short ln2467 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2467: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2468 +sub cl, 31 +shr dword[ebp+__dreg+ebx*4], 31 +jmp short ln2469 +ln2468: +shr dword[ebp+__dreg+ebx*4],cl +ln2469: +lahf +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E8B0 - E8B7 +Y8B0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+16] +and ecx,byte 63 +jnz short ln2470 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +and ah,0FEh +or ah,[ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2470: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +cmp cl, 32 +jb short ln2471 +sub cl, 31 +shr al, 1 +rcr edx, 31 +rcr edx,cl +jmp short ln2472 +ln2471: +shr al, 1 +rcr edx,cl +ln2472: +adc al,al +or edx,edx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E8B8 - E8BF +Y8B8: +and ebx,byte 7 +mov ecx,[ebp+__dreg+16] +and ecx,byte 63 +jnz short ln2473 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2473: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +cmp cl, 32 +jb short ln2474 +sub cl, 31 +ror edx, 31 +ror edx,cl +jmp short ln2475 +ln2474: +ror edx,cl +ln2475: +adc al,al +or edx,edx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E900 - E907 +Y900: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +add dl,dl +seto ch +or al,ch +add dl,dl +seto ch +or al,ch +add dl,dl +seto ch +or al,ch +add dl,dl +lahf +seto ch +or al,ch +mov [ebp+__dreg+ebx*4],dl +mov cl,ah +and cl,1 +mov [ebp+__xflag],cl +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E908 - E90F +Y908: +and ebx,byte 7 +mov al,0 +shl byte[ebp+__dreg+ebx*4],4 +lahf +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E910 - E917 +Y910: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +shr al,1 +rcl dl,4 +adc al,al +or dl,dl +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E918 - E91F +Y918: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +rol dl,4 +adc al,al +or dl,dl +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E920 - E927 +Y920: +and ebx,byte 7 +mov ecx,[ebp+__dreg+16] +and ecx,byte 63 +jnz short ln2476 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2476: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +ln2477: +add dl,dl +lahf +seto ch +or al,ch +dec cl +jnz short ln2477 +mov [ebp+__dreg+ebx*4],dl +mov cl,ah +and cl,1 +mov [ebp+__xflag],cl +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E928 - E92F +Y928: +and ebx,byte 7 +mov ecx,[ebp+__dreg+16] +and ecx,byte 63 +jnz short ln2478 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2478: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2479 +sub cl, 31 +shl byte[ebp+__dreg+ebx*4], 31 +jmp short ln2480 +ln2479: +shl byte[ebp+__dreg+ebx*4],cl +ln2480: +lahf +setc [ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E930 - E937 +Y930: +and ebx,byte 7 +mov ecx,[ebp+__dreg+16] +and ecx,byte 63 +jnz short ln2481 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +and ah,0FEh +or ah,[ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2481: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +cmp cl, 32 +jb short ln2482 +sub cl, 31 +shr al, 1 +rcl dl, 31 +rcl dl,cl +jmp short ln2483 +ln2482: +shr al, 1 +rcl dl,cl +ln2483: +adc al,al +or dl,dl +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E938 - E93F +Y938: +and ebx,byte 7 +mov ecx,[ebp+__dreg+16] +and ecx,byte 63 +jnz short ln2484 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2484: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +cmp cl, 32 +jb short ln2485 +sub cl, 31 +rol dl, 31 +rol dl,cl +jmp short ln2486 +ln2485: +rol dl,cl +ln2486: +adc al,al +or dl,dl +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E940 - E947 +Y940: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +add dx,dx +seto ch +or al,ch +add dx,dx +seto ch +or al,ch +add dx,dx +seto ch +or al,ch +add dx,dx +lahf +seto ch +or al,ch +mov [ebp+__dreg+ebx*4],dx +mov cl,ah +and cl,1 +mov [ebp+__xflag],cl +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E948 - E94F +Y948: +and ebx,byte 7 +mov al,0 +shl word[ebp+__dreg+ebx*4],4 +lahf +setc [ebp+__xflag] +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E950 - E957 +Y950: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +shr al,1 +rcl dx,4 +adc al,al +or dx,dx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E958 - E95F +Y958: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +rol dx,4 +adc al,al +or dx,dx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 14 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E960 - E967 +Y960: +and ebx,byte 7 +mov ecx,[ebp+__dreg+16] +and ecx,byte 63 +jnz short ln2487 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2487: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +ln2488: +add dx,dx +lahf +seto ch +or al,ch +dec cl +jnz short ln2488 +mov [ebp+__dreg+ebx*4],dx +mov cl,ah +and cl,1 +mov [ebp+__xflag],cl +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E968 - E96F +Y968: +and ebx,byte 7 +mov ecx,[ebp+__dreg+16] +and ecx,byte 63 +jnz short ln2489 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2489: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2490 +sub cl, 31 +shl word[ebp+__dreg+ebx*4], 31 +jmp short ln2491 +ln2490: +shl word[ebp+__dreg+ebx*4],cl +ln2491: +lahf +setc [ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E970 - E977 +Y970: +and ebx,byte 7 +mov ecx,[ebp+__dreg+16] +and ecx,byte 63 +jnz short ln2492 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +and ah,0FEh +or ah,[ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2492: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +cmp cl, 32 +jb short ln2493 +sub cl, 31 +shr al, 1 +rcl dx, 31 +rcl dx,cl +jmp short ln2494 +ln2493: +shr al, 1 +rcl dx,cl +ln2494: +adc al,al +or dx,dx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E978 - E97F +Y978: +and ebx,byte 7 +mov ecx,[ebp+__dreg+16] +and ecx,byte 63 +jnz short ln2495 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2495: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +cmp cl, 32 +jb short ln2496 +sub cl, 31 +rol dx, 31 +rol dx,cl +jmp short ln2497 +ln2496: +rol dx,cl +ln2497: +adc al,al +or dx,dx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E980 - E987 +Y980: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +add edx,edx +seto ch +or al,ch +add edx,edx +seto ch +or al,ch +add edx,edx +seto ch +or al,ch +add edx,edx +lahf +seto ch +or al,ch +mov [ebp+__dreg+ebx*4],edx +mov cl,ah +and cl,1 +mov [ebp+__xflag],cl +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E988 - E98F +Y988: +and ebx,byte 7 +mov al,0 +shl dword[ebp+__dreg+ebx*4],4 +lahf +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E990 - E997 +Y990: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +shr al,1 +rcl edx,4 +adc al,al +or edx,edx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E998 - E99F +Y998: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +rol edx,4 +adc al,al +or edx,edx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E9A0 - E9A7 +Y9A0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+16] +and ecx,byte 63 +jnz short ln2498 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2498: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +ln2499: +add edx,edx +lahf +seto ch +or al,ch +dec cl +jnz short ln2499 +mov [ebp+__dreg+ebx*4],edx +mov cl,ah +and cl,1 +mov [ebp+__xflag],cl +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E9A8 - E9AF +Y9A8: +and ebx,byte 7 +mov ecx,[ebp+__dreg+16] +and ecx,byte 63 +jnz short ln2500 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2500: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2501 +sub cl, 31 +shl dword[ebp+__dreg+ebx*4], 31 +jmp short ln2502 +ln2501: +shl dword[ebp+__dreg+ebx*4],cl +ln2502: +lahf +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E9B0 - E9B7 +Y9B0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+16] +and ecx,byte 63 +jnz short ln2503 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +and ah,0FEh +or ah,[ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2503: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +cmp cl, 32 +jb short ln2504 +sub cl, 31 +shr al, 1 +rcl edx, 31 +rcl edx,cl +jmp short ln2505 +ln2504: +shr al, 1 +rcl edx,cl +ln2505: +adc al,al +or edx,edx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes E9B8 - E9BF +Y9B8: +and ebx,byte 7 +mov ecx,[ebp+__dreg+16] +and ecx,byte 63 +jnz short ln2506 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2506: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +cmp cl, 32 +jb short ln2507 +sub cl, 31 +rol edx, 31 +rol edx,cl +jmp short ln2508 +ln2507: +rol edx,cl +ln2508: +adc al,al +or edx,edx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EA00 - EA07 +YA00: +and ebx,byte 7 +mov al,0 +sar byte[ebp+__dreg+ebx*4],5 +lahf +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EA08 - EA0F +YA08: +and ebx,byte 7 +mov al,0 +shr byte[ebp+__dreg+ebx*4],5 +lahf +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EA10 - EA17 +YA10: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +shr al,1 +rcr dl,5 +adc al,al +or dl,dl +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EA18 - EA1F +YA18: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +ror dl,5 +adc al,al +or dl,dl +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EA20 - EA27 +YA20: +and ebx,byte 7 +mov ecx,[ebp+__dreg+20] +and ecx,byte 63 +jnz short ln2509 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2509: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2510 +sub cl, 31 +sar byte[ebp+__dreg+ebx*4], 31 +jmp short ln2511 +ln2510: +sar byte[ebp+__dreg+ebx*4],cl +ln2511: +lahf +setc [ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EA28 - EA2F +YA28: +and ebx,byte 7 +mov ecx,[ebp+__dreg+20] +and ecx,byte 63 +jnz short ln2512 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2512: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2513 +sub cl, 31 +shr byte[ebp+__dreg+ebx*4], 31 +jmp short ln2514 +ln2513: +shr byte[ebp+__dreg+ebx*4],cl +ln2514: +lahf +setc [ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EA30 - EA37 +YA30: +and ebx,byte 7 +mov ecx,[ebp+__dreg+20] +and ecx,byte 63 +jnz short ln2515 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +and ah,0FEh +or ah,[ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2515: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +cmp cl, 32 +jb short ln2516 +sub cl, 31 +shr al, 1 +rcr dl, 31 +rcr dl,cl +jmp short ln2517 +ln2516: +shr al, 1 +rcr dl,cl +ln2517: +adc al,al +or dl,dl +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EA38 - EA3F +YA38: +and ebx,byte 7 +mov ecx,[ebp+__dreg+20] +and ecx,byte 63 +jnz short ln2518 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2518: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +cmp cl, 32 +jb short ln2519 +sub cl, 31 +ror dl, 31 +ror dl,cl +jmp short ln2520 +ln2519: +ror dl,cl +ln2520: +adc al,al +or dl,dl +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EA40 - EA47 +YA40: +and ebx,byte 7 +mov al,0 +sar word[ebp+__dreg+ebx*4],5 +lahf +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EA48 - EA4F +YA48: +and ebx,byte 7 +mov al,0 +shr word[ebp+__dreg+ebx*4],5 +lahf +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EA50 - EA57 +YA50: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +shr al,1 +rcr dx,5 +adc al,al +or dx,dx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EA58 - EA5F +YA58: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +ror dx,5 +adc al,al +or dx,dx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EA60 - EA67 +YA60: +and ebx,byte 7 +mov ecx,[ebp+__dreg+20] +and ecx,byte 63 +jnz short ln2521 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2521: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2522 +sub cl, 31 +sar word[ebp+__dreg+ebx*4], 31 +jmp short ln2523 +ln2522: +sar word[ebp+__dreg+ebx*4],cl +ln2523: +lahf +setc [ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EA68 - EA6F +YA68: +and ebx,byte 7 +mov ecx,[ebp+__dreg+20] +and ecx,byte 63 +jnz short ln2524 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2524: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2525 +sub cl, 31 +shr word[ebp+__dreg+ebx*4], 31 +jmp short ln2526 +ln2525: +shr word[ebp+__dreg+ebx*4],cl +ln2526: +lahf +setc [ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EA70 - EA77 +YA70: +and ebx,byte 7 +mov ecx,[ebp+__dreg+20] +and ecx,byte 63 +jnz short ln2527 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +and ah,0FEh +or ah,[ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2527: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +cmp cl, 32 +jb short ln2528 +sub cl, 31 +shr al, 1 +rcr dx, 31 +rcr dx,cl +jmp short ln2529 +ln2528: +shr al, 1 +rcr dx,cl +ln2529: +adc al,al +or dx,dx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EA78 - EA7F +YA78: +and ebx,byte 7 +mov ecx,[ebp+__dreg+20] +and ecx,byte 63 +jnz short ln2530 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2530: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +cmp cl, 32 +jb short ln2531 +sub cl, 31 +ror dx, 31 +ror dx,cl +jmp short ln2532 +ln2531: +ror dx,cl +ln2532: +adc al,al +or dx,dx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EA80 - EA87 +YA80: +and ebx,byte 7 +mov al,0 +sar dword[ebp+__dreg+ebx*4],5 +lahf +setc [ebp+__xflag] +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EA88 - EA8F +YA88: +and ebx,byte 7 +mov al,0 +shr dword[ebp+__dreg+ebx*4],5 +lahf +setc [ebp+__xflag] +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EA90 - EA97 +YA90: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +shr al,1 +rcr edx,5 +adc al,al +or edx,edx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EA98 - EA9F +YA98: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +ror edx,5 +adc al,al +or edx,edx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EAA0 - EAA7 +YAA0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+20] +and ecx,byte 63 +jnz short ln2533 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2533: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2534 +sub cl, 31 +sar dword[ebp+__dreg+ebx*4], 31 +jmp short ln2535 +ln2534: +sar dword[ebp+__dreg+ebx*4],cl +ln2535: +lahf +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EAA8 - EAAF +YAA8: +and ebx,byte 7 +mov ecx,[ebp+__dreg+20] +and ecx,byte 63 +jnz short ln2536 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2536: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2537 +sub cl, 31 +shr dword[ebp+__dreg+ebx*4], 31 +jmp short ln2538 +ln2537: +shr dword[ebp+__dreg+ebx*4],cl +ln2538: +lahf +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EAB0 - EAB7 +YAB0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+20] +and ecx,byte 63 +jnz short ln2539 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +and ah,0FEh +or ah,[ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2539: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +cmp cl, 32 +jb short ln2540 +sub cl, 31 +shr al, 1 +rcr edx, 31 +rcr edx,cl +jmp short ln2541 +ln2540: +shr al, 1 +rcr edx,cl +ln2541: +adc al,al +or edx,edx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EAB8 - EABF +YAB8: +and ebx,byte 7 +mov ecx,[ebp+__dreg+20] +and ecx,byte 63 +jnz short ln2542 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2542: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +cmp cl, 32 +jb short ln2543 +sub cl, 31 +ror edx, 31 +ror edx,cl +jmp short ln2544 +ln2543: +ror edx,cl +ln2544: +adc al,al +or edx,edx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EB00 - EB07 +YB00: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +add dl,dl +seto ch +or al,ch +add dl,dl +seto ch +or al,ch +add dl,dl +seto ch +or al,ch +add dl,dl +seto ch +or al,ch +add dl,dl +lahf +seto ch +or al,ch +mov [ebp+__dreg+ebx*4],dl +mov cl,ah +and cl,1 +mov [ebp+__xflag],cl +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EB08 - EB0F +YB08: +and ebx,byte 7 +mov al,0 +shl byte[ebp+__dreg+ebx*4],5 +lahf +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EB10 - EB17 +YB10: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +shr al,1 +rcl dl,5 +adc al,al +or dl,dl +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EB18 - EB1F +YB18: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +rol dl,5 +adc al,al +or dl,dl +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EB20 - EB27 +YB20: +and ebx,byte 7 +mov ecx,[ebp+__dreg+20] +and ecx,byte 63 +jnz short ln2545 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2545: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +ln2546: +add dl,dl +lahf +seto ch +or al,ch +dec cl +jnz short ln2546 +mov [ebp+__dreg+ebx*4],dl +mov cl,ah +and cl,1 +mov [ebp+__xflag],cl +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EB28 - EB2F +YB28: +and ebx,byte 7 +mov ecx,[ebp+__dreg+20] +and ecx,byte 63 +jnz short ln2547 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2547: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2548 +sub cl, 31 +shl byte[ebp+__dreg+ebx*4], 31 +jmp short ln2549 +ln2548: +shl byte[ebp+__dreg+ebx*4],cl +ln2549: +lahf +setc [ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EB30 - EB37 +YB30: +and ebx,byte 7 +mov ecx,[ebp+__dreg+20] +and ecx,byte 63 +jnz short ln2550 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +and ah,0FEh +or ah,[ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2550: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +cmp cl, 32 +jb short ln2551 +sub cl, 31 +shr al, 1 +rcl dl, 31 +rcl dl,cl +jmp short ln2552 +ln2551: +shr al, 1 +rcl dl,cl +ln2552: +adc al,al +or dl,dl +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EB38 - EB3F +YB38: +and ebx,byte 7 +mov ecx,[ebp+__dreg+20] +and ecx,byte 63 +jnz short ln2553 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2553: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +cmp cl, 32 +jb short ln2554 +sub cl, 31 +rol dl, 31 +rol dl,cl +jmp short ln2555 +ln2554: +rol dl,cl +ln2555: +adc al,al +or dl,dl +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EB40 - EB47 +YB40: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +add dx,dx +seto ch +or al,ch +add dx,dx +seto ch +or al,ch +add dx,dx +seto ch +or al,ch +add dx,dx +seto ch +or al,ch +add dx,dx +lahf +seto ch +or al,ch +mov [ebp+__dreg+ebx*4],dx +mov cl,ah +and cl,1 +mov [ebp+__xflag],cl +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EB48 - EB4F +YB48: +and ebx,byte 7 +mov al,0 +shl word[ebp+__dreg+ebx*4],5 +lahf +setc [ebp+__xflag] +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EB50 - EB57 +YB50: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +shr al,1 +rcl dx,5 +adc al,al +or dx,dx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EB58 - EB5F +YB58: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +rol dx,5 +adc al,al +or dx,dx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 16 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EB60 - EB67 +YB60: +and ebx,byte 7 +mov ecx,[ebp+__dreg+20] +and ecx,byte 63 +jnz short ln2556 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2556: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +ln2557: +add dx,dx +lahf +seto ch +or al,ch +dec cl +jnz short ln2557 +mov [ebp+__dreg+ebx*4],dx +mov cl,ah +and cl,1 +mov [ebp+__xflag],cl +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EB68 - EB6F +YB68: +and ebx,byte 7 +mov ecx,[ebp+__dreg+20] +and ecx,byte 63 +jnz short ln2558 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2558: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2559 +sub cl, 31 +shl word[ebp+__dreg+ebx*4], 31 +jmp short ln2560 +ln2559: +shl word[ebp+__dreg+ebx*4],cl +ln2560: +lahf +setc [ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EB70 - EB77 +YB70: +and ebx,byte 7 +mov ecx,[ebp+__dreg+20] +and ecx,byte 63 +jnz short ln2561 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +and ah,0FEh +or ah,[ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2561: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +cmp cl, 32 +jb short ln2562 +sub cl, 31 +shr al, 1 +rcl dx, 31 +rcl dx,cl +jmp short ln2563 +ln2562: +shr al, 1 +rcl dx,cl +ln2563: +adc al,al +or dx,dx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EB78 - EB7F +YB78: +and ebx,byte 7 +mov ecx,[ebp+__dreg+20] +and ecx,byte 63 +jnz short ln2564 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2564: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +cmp cl, 32 +jb short ln2565 +sub cl, 31 +rol dx, 31 +rol dx,cl +jmp short ln2566 +ln2565: +rol dx,cl +ln2566: +adc al,al +or dx,dx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EB80 - EB87 +YB80: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +add edx,edx +seto ch +or al,ch +add edx,edx +seto ch +or al,ch +add edx,edx +seto ch +or al,ch +add edx,edx +seto ch +or al,ch +add edx,edx +lahf +seto ch +or al,ch +mov [ebp+__dreg+ebx*4],edx +mov cl,ah +and cl,1 +mov [ebp+__xflag],cl +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EB88 - EB8F +YB88: +and ebx,byte 7 +mov al,0 +shl dword[ebp+__dreg+ebx*4],5 +lahf +setc [ebp+__xflag] +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EB90 - EB97 +YB90: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +shr al,1 +rcl edx,5 +adc al,al +or edx,edx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EB98 - EB9F +YB98: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +rol edx,5 +adc al,al +or edx,edx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EBA0 - EBA7 +YBA0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+20] +and ecx,byte 63 +jnz short ln2567 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2567: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +ln2568: +add edx,edx +lahf +seto ch +or al,ch +dec cl +jnz short ln2568 +mov [ebp+__dreg+ebx*4],edx +mov cl,ah +and cl,1 +mov [ebp+__xflag],cl +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EBA8 - EBAF +YBA8: +and ebx,byte 7 +mov ecx,[ebp+__dreg+20] +and ecx,byte 63 +jnz short ln2569 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2569: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2570 +sub cl, 31 +shl dword[ebp+__dreg+ebx*4], 31 +jmp short ln2571 +ln2570: +shl dword[ebp+__dreg+ebx*4],cl +ln2571: +lahf +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EBB0 - EBB7 +YBB0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+20] +and ecx,byte 63 +jnz short ln2572 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +and ah,0FEh +or ah,[ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2572: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +cmp cl, 32 +jb short ln2573 +sub cl, 31 +shr al, 1 +rcl edx, 31 +rcl edx,cl +jmp short ln2574 +ln2573: +shr al, 1 +rcl edx,cl +ln2574: +adc al,al +or edx,edx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EBB8 - EBBF +YBB8: +and ebx,byte 7 +mov ecx,[ebp+__dreg+20] +and ecx,byte 63 +jnz short ln2575 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2575: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +cmp cl, 32 +jb short ln2576 +sub cl, 31 +rol edx, 31 +rol edx,cl +jmp short ln2577 +ln2576: +rol edx,cl +ln2577: +adc al,al +or edx,edx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EC00 - EC07 +YC00: +and ebx,byte 7 +mov al,0 +sar byte[ebp+__dreg+ebx*4],6 +lahf +setc [ebp+__xflag] +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EC08 - EC0F +YC08: +and ebx,byte 7 +mov al,0 +shr byte[ebp+__dreg+ebx*4],6 +lahf +setc [ebp+__xflag] +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EC10 - EC17 +YC10: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +shr al,1 +rcr dl,6 +adc al,al +or dl,dl +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EC18 - EC1F +YC18: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +ror dl,6 +adc al,al +or dl,dl +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EC20 - EC27 +YC20: +and ebx,byte 7 +mov ecx,[ebp+__dreg+24] +and ecx,byte 63 +jnz short ln2578 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2578: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2579 +sub cl, 31 +sar byte[ebp+__dreg+ebx*4], 31 +jmp short ln2580 +ln2579: +sar byte[ebp+__dreg+ebx*4],cl +ln2580: +lahf +setc [ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EC28 - EC2F +YC28: +and ebx,byte 7 +mov ecx,[ebp+__dreg+24] +and ecx,byte 63 +jnz short ln2581 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2581: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2582 +sub cl, 31 +shr byte[ebp+__dreg+ebx*4], 31 +jmp short ln2583 +ln2582: +shr byte[ebp+__dreg+ebx*4],cl +ln2583: +lahf +setc [ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EC30 - EC37 +YC30: +and ebx,byte 7 +mov ecx,[ebp+__dreg+24] +and ecx,byte 63 +jnz short ln2584 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +and ah,0FEh +or ah,[ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2584: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +cmp cl, 32 +jb short ln2585 +sub cl, 31 +shr al, 1 +rcr dl, 31 +rcr dl,cl +jmp short ln2586 +ln2585: +shr al, 1 +rcr dl,cl +ln2586: +adc al,al +or dl,dl +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EC38 - EC3F +YC38: +and ebx,byte 7 +mov ecx,[ebp+__dreg+24] +and ecx,byte 63 +jnz short ln2587 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2587: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +cmp cl, 32 +jb short ln2588 +sub cl, 31 +ror dl, 31 +ror dl,cl +jmp short ln2589 +ln2588: +ror dl,cl +ln2589: +adc al,al +or dl,dl +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EC40 - EC47 +YC40: +and ebx,byte 7 +mov al,0 +sar word[ebp+__dreg+ebx*4],6 +lahf +setc [ebp+__xflag] +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EC48 - EC4F +YC48: +and ebx,byte 7 +mov al,0 +shr word[ebp+__dreg+ebx*4],6 +lahf +setc [ebp+__xflag] +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EC50 - EC57 +YC50: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +shr al,1 +rcr dx,6 +adc al,al +or dx,dx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EC58 - EC5F +YC58: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +ror dx,6 +adc al,al +or dx,dx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EC60 - EC67 +YC60: +and ebx,byte 7 +mov ecx,[ebp+__dreg+24] +and ecx,byte 63 +jnz short ln2590 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2590: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2591 +sub cl, 31 +sar word[ebp+__dreg+ebx*4], 31 +jmp short ln2592 +ln2591: +sar word[ebp+__dreg+ebx*4],cl +ln2592: +lahf +setc [ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EC68 - EC6F +YC68: +and ebx,byte 7 +mov ecx,[ebp+__dreg+24] +and ecx,byte 63 +jnz short ln2593 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2593: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2594 +sub cl, 31 +shr word[ebp+__dreg+ebx*4], 31 +jmp short ln2595 +ln2594: +shr word[ebp+__dreg+ebx*4],cl +ln2595: +lahf +setc [ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EC70 - EC77 +YC70: +and ebx,byte 7 +mov ecx,[ebp+__dreg+24] +and ecx,byte 63 +jnz short ln2596 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +and ah,0FEh +or ah,[ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2596: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +cmp cl, 32 +jb short ln2597 +sub cl, 31 +shr al, 1 +rcr dx, 31 +rcr dx,cl +jmp short ln2598 +ln2597: +shr al, 1 +rcr dx,cl +ln2598: +adc al,al +or dx,dx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EC78 - EC7F +YC78: +and ebx,byte 7 +mov ecx,[ebp+__dreg+24] +and ecx,byte 63 +jnz short ln2599 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2599: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +cmp cl, 32 +jb short ln2600 +sub cl, 31 +ror dx, 31 +ror dx,cl +jmp short ln2601 +ln2600: +ror dx,cl +ln2601: +adc al,al +or dx,dx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EC80 - EC87 +YC80: +and ebx,byte 7 +mov al,0 +sar dword[ebp+__dreg+ebx*4],6 +lahf +setc [ebp+__xflag] +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EC88 - EC8F +YC88: +and ebx,byte 7 +mov al,0 +shr dword[ebp+__dreg+ebx*4],6 +lahf +setc [ebp+__xflag] +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EC90 - EC97 +YC90: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +shr al,1 +rcr edx,6 +adc al,al +or edx,edx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EC98 - EC9F +YC98: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +ror edx,6 +adc al,al +or edx,edx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes ECA0 - ECA7 +YCA0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+24] +and ecx,byte 63 +jnz short ln2602 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2602: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2603 +sub cl, 31 +sar dword[ebp+__dreg+ebx*4], 31 +jmp short ln2604 +ln2603: +sar dword[ebp+__dreg+ebx*4],cl +ln2604: +lahf +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes ECA8 - ECAF +YCA8: +and ebx,byte 7 +mov ecx,[ebp+__dreg+24] +and ecx,byte 63 +jnz short ln2605 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2605: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2606 +sub cl, 31 +shr dword[ebp+__dreg+ebx*4], 31 +jmp short ln2607 +ln2606: +shr dword[ebp+__dreg+ebx*4],cl +ln2607: +lahf +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes ECB0 - ECB7 +YCB0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+24] +and ecx,byte 63 +jnz short ln2608 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +and ah,0FEh +or ah,[ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2608: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +cmp cl, 32 +jb short ln2609 +sub cl, 31 +shr al, 1 +rcr edx, 31 +rcr edx,cl +jmp short ln2610 +ln2609: +shr al, 1 +rcr edx,cl +ln2610: +adc al,al +or edx,edx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes ECB8 - ECBF +YCB8: +and ebx,byte 7 +mov ecx,[ebp+__dreg+24] +and ecx,byte 63 +jnz short ln2611 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2611: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +cmp cl, 32 +jb short ln2612 +sub cl, 31 +ror edx, 31 +ror edx,cl +jmp short ln2613 +ln2612: +ror edx,cl +ln2613: +adc al,al +or edx,edx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes ED00 - ED07 +YD00: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +add dl,dl +seto ch +or al,ch +add dl,dl +seto ch +or al,ch +add dl,dl +seto ch +or al,ch +add dl,dl +seto ch +or al,ch +add dl,dl +seto ch +or al,ch +add dl,dl +lahf +seto ch +or al,ch +mov [ebp+__dreg+ebx*4],dl +mov cl,ah +and cl,1 +mov [ebp+__xflag],cl +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes ED08 - ED0F +YD08: +and ebx,byte 7 +mov al,0 +shl byte[ebp+__dreg+ebx*4],6 +lahf +setc [ebp+__xflag] +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes ED10 - ED17 +YD10: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +shr al,1 +rcl dl,6 +adc al,al +or dl,dl +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes ED18 - ED1F +YD18: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +rol dl,6 +adc al,al +or dl,dl +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes ED20 - ED27 +YD20: +and ebx,byte 7 +mov ecx,[ebp+__dreg+24] +and ecx,byte 63 +jnz short ln2614 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2614: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +ln2615: +add dl,dl +lahf +seto ch +or al,ch +dec cl +jnz short ln2615 +mov [ebp+__dreg+ebx*4],dl +mov cl,ah +and cl,1 +mov [ebp+__xflag],cl +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes ED28 - ED2F +YD28: +and ebx,byte 7 +mov ecx,[ebp+__dreg+24] +and ecx,byte 63 +jnz short ln2616 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2616: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2617 +sub cl, 31 +shl byte[ebp+__dreg+ebx*4], 31 +jmp short ln2618 +ln2617: +shl byte[ebp+__dreg+ebx*4],cl +ln2618: +lahf +setc [ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes ED30 - ED37 +YD30: +and ebx,byte 7 +mov ecx,[ebp+__dreg+24] +and ecx,byte 63 +jnz short ln2619 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +and ah,0FEh +or ah,[ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2619: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +cmp cl, 32 +jb short ln2620 +sub cl, 31 +shr al, 1 +rcl dl, 31 +rcl dl,cl +jmp short ln2621 +ln2620: +shr al, 1 +rcl dl,cl +ln2621: +adc al,al +or dl,dl +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes ED38 - ED3F +YD38: +and ebx,byte 7 +mov ecx,[ebp+__dreg+24] +and ecx,byte 63 +jnz short ln2622 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2622: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +cmp cl, 32 +jb short ln2623 +sub cl, 31 +rol dl, 31 +rol dl,cl +jmp short ln2624 +ln2623: +rol dl,cl +ln2624: +adc al,al +or dl,dl +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes ED40 - ED47 +YD40: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +add dx,dx +seto ch +or al,ch +add dx,dx +seto ch +or al,ch +add dx,dx +seto ch +or al,ch +add dx,dx +seto ch +or al,ch +add dx,dx +seto ch +or al,ch +add dx,dx +lahf +seto ch +or al,ch +mov [ebp+__dreg+ebx*4],dx +mov cl,ah +and cl,1 +mov [ebp+__xflag],cl +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes ED48 - ED4F +YD48: +and ebx,byte 7 +mov al,0 +shl word[ebp+__dreg+ebx*4],6 +lahf +setc [ebp+__xflag] +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes ED50 - ED57 +YD50: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +shr al,1 +rcl dx,6 +adc al,al +or dx,dx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes ED58 - ED5F +YD58: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +rol dx,6 +adc al,al +or dx,dx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 18 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes ED60 - ED67 +YD60: +and ebx,byte 7 +mov ecx,[ebp+__dreg+24] +and ecx,byte 63 +jnz short ln2625 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2625: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +ln2626: +add dx,dx +lahf +seto ch +or al,ch +dec cl +jnz short ln2626 +mov [ebp+__dreg+ebx*4],dx +mov cl,ah +and cl,1 +mov [ebp+__xflag],cl +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes ED68 - ED6F +YD68: +and ebx,byte 7 +mov ecx,[ebp+__dreg+24] +and ecx,byte 63 +jnz short ln2627 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2627: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2628 +sub cl, 31 +shl word[ebp+__dreg+ebx*4], 31 +jmp short ln2629 +ln2628: +shl word[ebp+__dreg+ebx*4],cl +ln2629: +lahf +setc [ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes ED70 - ED77 +YD70: +and ebx,byte 7 +mov ecx,[ebp+__dreg+24] +and ecx,byte 63 +jnz short ln2630 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +and ah,0FEh +or ah,[ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2630: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +cmp cl, 32 +jb short ln2631 +sub cl, 31 +shr al, 1 +rcl dx, 31 +rcl dx,cl +jmp short ln2632 +ln2631: +shr al, 1 +rcl dx,cl +ln2632: +adc al,al +or dx,dx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes ED78 - ED7F +YD78: +and ebx,byte 7 +mov ecx,[ebp+__dreg+24] +and ecx,byte 63 +jnz short ln2633 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2633: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +cmp cl, 32 +jb short ln2634 +sub cl, 31 +rol dx, 31 +rol dx,cl +jmp short ln2635 +ln2634: +rol dx,cl +ln2635: +adc al,al +or dx,dx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes ED80 - ED87 +YD80: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +add edx,edx +seto ch +or al,ch +add edx,edx +seto ch +or al,ch +add edx,edx +seto ch +or al,ch +add edx,edx +seto ch +or al,ch +add edx,edx +seto ch +or al,ch +add edx,edx +lahf +seto ch +or al,ch +mov [ebp+__dreg+ebx*4],edx +mov cl,ah +and cl,1 +mov [ebp+__xflag],cl +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes ED88 - ED8F +YD88: +and ebx,byte 7 +mov al,0 +shl dword[ebp+__dreg+ebx*4],6 +lahf +setc [ebp+__xflag] +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes ED90 - ED97 +YD90: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +shr al,1 +rcl edx,6 +adc al,al +or edx,edx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes ED98 - ED9F +YD98: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +rol edx,6 +adc al,al +or edx,edx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EDA0 - EDA7 +YDA0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+24] +and ecx,byte 63 +jnz short ln2636 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2636: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +ln2637: +add edx,edx +lahf +seto ch +or al,ch +dec cl +jnz short ln2637 +mov [ebp+__dreg+ebx*4],edx +mov cl,ah +and cl,1 +mov [ebp+__xflag],cl +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EDA8 - EDAF +YDA8: +and ebx,byte 7 +mov ecx,[ebp+__dreg+24] +and ecx,byte 63 +jnz short ln2638 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2638: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2639 +sub cl, 31 +shl dword[ebp+__dreg+ebx*4], 31 +jmp short ln2640 +ln2639: +shl dword[ebp+__dreg+ebx*4],cl +ln2640: +lahf +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EDB0 - EDB7 +YDB0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+24] +and ecx,byte 63 +jnz short ln2641 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +and ah,0FEh +or ah,[ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2641: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +cmp cl, 32 +jb short ln2642 +sub cl, 31 +shr al, 1 +rcl edx, 31 +rcl edx,cl +jmp short ln2643 +ln2642: +shr al, 1 +rcl edx,cl +ln2643: +adc al,al +or edx,edx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EDB8 - EDBF +YDB8: +and ebx,byte 7 +mov ecx,[ebp+__dreg+24] +and ecx,byte 63 +jnz short ln2644 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2644: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +cmp cl, 32 +jb short ln2645 +sub cl, 31 +rol edx, 31 +rol edx,cl +jmp short ln2646 +ln2645: +rol edx,cl +ln2646: +adc al,al +or edx,edx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EE00 - EE07 +YE00: +and ebx,byte 7 +mov al,0 +sar byte[ebp+__dreg+ebx*4],7 +lahf +setc [ebp+__xflag] +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EE08 - EE0F +YE08: +and ebx,byte 7 +mov al,0 +shr byte[ebp+__dreg+ebx*4],7 +lahf +setc [ebp+__xflag] +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EE10 - EE17 +YE10: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +shr al,1 +rcr dl,7 +adc al,al +or dl,dl +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EE18 - EE1F +YE18: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +ror dl,7 +adc al,al +or dl,dl +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EE20 - EE27 +YE20: +and ebx,byte 7 +mov ecx,[ebp+__dreg+28] +and ecx,byte 63 +jnz short ln2647 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2647: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2648 +sub cl, 31 +sar byte[ebp+__dreg+ebx*4], 31 +jmp short ln2649 +ln2648: +sar byte[ebp+__dreg+ebx*4],cl +ln2649: +lahf +setc [ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EE28 - EE2F +YE28: +and ebx,byte 7 +mov ecx,[ebp+__dreg+28] +and ecx,byte 63 +jnz short ln2650 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2650: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2651 +sub cl, 31 +shr byte[ebp+__dreg+ebx*4], 31 +jmp short ln2652 +ln2651: +shr byte[ebp+__dreg+ebx*4],cl +ln2652: +lahf +setc [ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EE30 - EE37 +YE30: +and ebx,byte 7 +mov ecx,[ebp+__dreg+28] +and ecx,byte 63 +jnz short ln2653 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +and ah,0FEh +or ah,[ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2653: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +cmp cl, 32 +jb short ln2654 +sub cl, 31 +shr al, 1 +rcr dl, 31 +rcr dl,cl +jmp short ln2655 +ln2654: +shr al, 1 +rcr dl,cl +ln2655: +adc al,al +or dl,dl +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EE38 - EE3F +YE38: +and ebx,byte 7 +mov ecx,[ebp+__dreg+28] +and ecx,byte 63 +jnz short ln2656 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2656: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +cmp cl, 32 +jb short ln2657 +sub cl, 31 +ror dl, 31 +ror dl,cl +jmp short ln2658 +ln2657: +ror dl,cl +ln2658: +adc al,al +or dl,dl +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EE40 - EE47 +YE40: +and ebx,byte 7 +mov al,0 +sar word[ebp+__dreg+ebx*4],7 +lahf +setc [ebp+__xflag] +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EE48 - EE4F +YE48: +and ebx,byte 7 +mov al,0 +shr word[ebp+__dreg+ebx*4],7 +lahf +setc [ebp+__xflag] +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EE50 - EE57 +YE50: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +shr al,1 +rcr dx,7 +adc al,al +or dx,dx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EE58 - EE5F +YE58: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +ror dx,7 +adc al,al +or dx,dx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EE60 - EE67 +YE60: +and ebx,byte 7 +mov ecx,[ebp+__dreg+28] +and ecx,byte 63 +jnz short ln2659 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2659: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2660 +sub cl, 31 +sar word[ebp+__dreg+ebx*4], 31 +jmp short ln2661 +ln2660: +sar word[ebp+__dreg+ebx*4],cl +ln2661: +lahf +setc [ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EE68 - EE6F +YE68: +and ebx,byte 7 +mov ecx,[ebp+__dreg+28] +and ecx,byte 63 +jnz short ln2662 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2662: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2663 +sub cl, 31 +shr word[ebp+__dreg+ebx*4], 31 +jmp short ln2664 +ln2663: +shr word[ebp+__dreg+ebx*4],cl +ln2664: +lahf +setc [ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EE70 - EE77 +YE70: +and ebx,byte 7 +mov ecx,[ebp+__dreg+28] +and ecx,byte 63 +jnz short ln2665 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +and ah,0FEh +or ah,[ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2665: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +cmp cl, 32 +jb short ln2666 +sub cl, 31 +shr al, 1 +rcr dx, 31 +rcr dx,cl +jmp short ln2667 +ln2666: +shr al, 1 +rcr dx,cl +ln2667: +adc al,al +or dx,dx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EE78 - EE7F +YE78: +and ebx,byte 7 +mov ecx,[ebp+__dreg+28] +and ecx,byte 63 +jnz short ln2668 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2668: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +cmp cl, 32 +jb short ln2669 +sub cl, 31 +ror dx, 31 +ror dx,cl +jmp short ln2670 +ln2669: +ror dx,cl +ln2670: +adc al,al +or dx,dx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EE80 - EE87 +YE80: +and ebx,byte 7 +mov al,0 +sar dword[ebp+__dreg+ebx*4],7 +lahf +setc [ebp+__xflag] +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EE88 - EE8F +YE88: +and ebx,byte 7 +mov al,0 +shr dword[ebp+__dreg+ebx*4],7 +lahf +setc [ebp+__xflag] +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EE90 - EE97 +YE90: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +shr al,1 +rcr edx,7 +adc al,al +or edx,edx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EE98 - EE9F +YE98: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +ror edx,7 +adc al,al +or edx,edx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EEA0 - EEA7 +YEA0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+28] +and ecx,byte 63 +jnz short ln2671 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2671: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2672 +sub cl, 31 +sar dword[ebp+__dreg+ebx*4], 31 +jmp short ln2673 +ln2672: +sar dword[ebp+__dreg+ebx*4],cl +ln2673: +lahf +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EEA8 - EEAF +YEA8: +and ebx,byte 7 +mov ecx,[ebp+__dreg+28] +and ecx,byte 63 +jnz short ln2674 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2674: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2675 +sub cl, 31 +shr dword[ebp+__dreg+ebx*4], 31 +jmp short ln2676 +ln2675: +shr dword[ebp+__dreg+ebx*4],cl +ln2676: +lahf +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EEB0 - EEB7 +YEB0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+28] +and ecx,byte 63 +jnz short ln2677 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +and ah,0FEh +or ah,[ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2677: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +cmp cl, 32 +jb short ln2678 +sub cl, 31 +shr al, 1 +rcr edx, 31 +rcr edx,cl +jmp short ln2679 +ln2678: +shr al, 1 +rcr edx,cl +ln2679: +adc al,al +or edx,edx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EEB8 - EEBF +YEB8: +and ebx,byte 7 +mov ecx,[ebp+__dreg+28] +and ecx,byte 63 +jnz short ln2680 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2680: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +cmp cl, 32 +jb short ln2681 +sub cl, 31 +ror edx, 31 +ror edx,cl +jmp short ln2682 +ln2681: +ror edx,cl +ln2682: +adc al,al +or edx,edx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EF00 - EF07 +YF00: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +add dl,dl +seto ch +or al,ch +add dl,dl +seto ch +or al,ch +add dl,dl +seto ch +or al,ch +add dl,dl +seto ch +or al,ch +add dl,dl +seto ch +or al,ch +add dl,dl +seto ch +or al,ch +add dl,dl +lahf +seto ch +or al,ch +mov [ebp+__dreg+ebx*4],dl +mov cl,ah +and cl,1 +mov [ebp+__xflag],cl +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EF08 - EF0F +YF08: +and ebx,byte 7 +mov al,0 +shl byte[ebp+__dreg+ebx*4],7 +lahf +setc [ebp+__xflag] +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EF10 - EF17 +YF10: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +shr al,1 +rcl dl,7 +adc al,al +or dl,dl +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EF18 - EF1F +YF18: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +rol dl,7 +adc al,al +or dl,dl +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EF20 - EF27 +YF20: +and ebx,byte 7 +mov ecx,[ebp+__dreg+28] +and ecx,byte 63 +jnz short ln2683 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2683: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +ln2684: +add dl,dl +lahf +seto ch +or al,ch +dec cl +jnz short ln2684 +mov [ebp+__dreg+ebx*4],dl +mov cl,ah +and cl,1 +mov [ebp+__xflag],cl +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EF28 - EF2F +YF28: +and ebx,byte 7 +mov ecx,[ebp+__dreg+28] +and ecx,byte 63 +jnz short ln2685 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2685: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2686 +sub cl, 31 +shl byte[ebp+__dreg+ebx*4], 31 +jmp short ln2687 +ln2686: +shl byte[ebp+__dreg+ebx*4],cl +ln2687: +lahf +setc [ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EF30 - EF37 +YF30: +and ebx,byte 7 +mov ecx,[ebp+__dreg+28] +and ecx,byte 63 +jnz short ln2688 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +and ah,0FEh +or ah,[ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2688: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +cmp cl, 32 +jb short ln2689 +sub cl, 31 +shr al, 1 +rcl dl, 31 +rcl dl,cl +jmp short ln2690 +ln2689: +shr al, 1 +rcl dl,cl +ln2690: +adc al,al +or dl,dl +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EF38 - EF3F +YF38: +and ebx,byte 7 +mov ecx,[ebp+__dreg+28] +and ecx,byte 63 +jnz short ln2691 +mov ecx,[ebp+__dreg+ebx*4] +test cl,cl +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2691: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +cmp cl, 32 +jb short ln2692 +sub cl, 31 +rol dl, 31 +rol dl,cl +jmp short ln2693 +ln2692: +rol dl,cl +ln2693: +adc al,al +or dl,dl +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dl +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EF40 - EF47 +YF40: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +add dx,dx +seto ch +or al,ch +add dx,dx +seto ch +or al,ch +add dx,dx +seto ch +or al,ch +add dx,dx +seto ch +or al,ch +add dx,dx +seto ch +or al,ch +add dx,dx +seto ch +or al,ch +add dx,dx +lahf +seto ch +or al,ch +mov [ebp+__dreg+ebx*4],dx +mov cl,ah +and cl,1 +mov [ebp+__xflag],cl +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EF48 - EF4F +YF48: +and ebx,byte 7 +mov al,0 +shl word[ebp+__dreg+ebx*4],7 +lahf +setc [ebp+__xflag] +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EF50 - EF57 +YF50: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +shr al,1 +rcl dx,7 +adc al,al +or dx,dx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EF58 - EF5F +YF58: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +rol dx,7 +adc al,al +or dx,dx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 20 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EF60 - EF67 +YF60: +and ebx,byte 7 +mov ecx,[ebp+__dreg+28] +and ecx,byte 63 +jnz short ln2694 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2694: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +ln2695: +add dx,dx +lahf +seto ch +or al,ch +dec cl +jnz short ln2695 +mov [ebp+__dreg+ebx*4],dx +mov cl,ah +and cl,1 +mov [ebp+__xflag],cl +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EF68 - EF6F +YF68: +and ebx,byte 7 +mov ecx,[ebp+__dreg+28] +and ecx,byte 63 +jnz short ln2696 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2696: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2697 +sub cl, 31 +shl word[ebp+__dreg+ebx*4], 31 +jmp short ln2698 +ln2697: +shl word[ebp+__dreg+ebx*4],cl +ln2698: +lahf +setc [ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EF70 - EF77 +YF70: +and ebx,byte 7 +mov ecx,[ebp+__dreg+28] +and ecx,byte 63 +jnz short ln2699 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +and ah,0FEh +or ah,[ebp+__xflag] +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2699: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +cmp cl, 32 +jb short ln2700 +sub cl, 31 +shr al, 1 +rcl dx, 31 +rcl dx,cl +jmp short ln2701 +ln2700: +shr al, 1 +rcl dx,cl +ln2701: +adc al,al +or dx,dx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EF78 - EF7F +YF78: +and ebx,byte 7 +mov ecx,[ebp+__dreg+28] +and ecx,byte 63 +jnz short ln2702 +mov ecx,[ebp+__dreg+ebx*4] +test cx,cx +lahf +mov al,0 +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2702: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +cmp cl, 32 +jb short ln2703 +sub cl, 31 +rol dx, 31 +rol dx,cl +jmp short ln2704 +ln2703: +rol dx,cl +ln2704: +adc al,al +or dx,dx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],dx +sub edi,byte 6 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EF80 - EF87 +YF80: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +add edx,edx +seto ch +or al,ch +add edx,edx +seto ch +or al,ch +add edx,edx +seto ch +or al,ch +add edx,edx +seto ch +or al,ch +add edx,edx +seto ch +or al,ch +add edx,edx +seto ch +or al,ch +add edx,edx +lahf +seto ch +or al,ch +mov [ebp+__dreg+ebx*4],edx +mov cl,ah +and cl,1 +mov [ebp+__xflag],cl +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EF88 - EF8F +YF88: +and ebx,byte 7 +mov al,0 +shl dword[ebp+__dreg+ebx*4],7 +lahf +setc [ebp+__xflag] +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EF90 - EF97 +YF90: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +shr al,1 +rcl edx,7 +adc al,al +or edx,edx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EF98 - EF9F +YF98: +and ebx,byte 7 +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +rol edx,7 +adc al,al +or edx,edx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 22 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EFA0 - EFA7 +YFA0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+28] +and ecx,byte 63 +jnz short ln2705 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2705: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +ln2706: +add edx,edx +lahf +seto ch +or al,ch +dec cl +jnz short ln2706 +mov [ebp+__dreg+ebx*4],edx +mov cl,ah +and cl,1 +mov [ebp+__xflag],cl +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EFA8 - EFAF +YFA8: +and ebx,byte 7 +mov ecx,[ebp+__dreg+28] +and ecx,byte 63 +jnz short ln2707 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2707: +sub edi,ecx +sub edi,ecx +mov al,0 +cmp cl, 32 +jb short ln2708 +sub cl, 31 +shl dword[ebp+__dreg+ebx*4], 31 +jmp short ln2709 +ln2708: +shl dword[ebp+__dreg+ebx*4],cl +ln2709: +lahf +setc [ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EFB0 - EFB7 +YFB0: +and ebx,byte 7 +mov ecx,[ebp+__dreg+28] +and ecx,byte 63 +jnz short ln2710 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +and ah,0FEh +or ah,[ebp+__xflag] +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2710: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,[ebp+__xflag] +cmp cl, 32 +jb short ln2711 +sub cl, 31 +shr al, 1 +rcl edx, 31 +rcl edx,cl +jmp short ln2712 +ln2711: +shr al, 1 +rcl edx,cl +ln2712: +adc al,al +or edx,edx +lahf +or ah,al +mov [ebp+__xflag],al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes EFB8 - EFBF +YFB8: +and ebx,byte 7 +mov ecx,[ebp+__dreg+28] +and ecx,byte 63 +jnz short ln2713 +mov ecx,[ebp+__dreg+ebx*4] +test ecx,ecx +lahf +mov al,0 +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +ln2713: +sub edi,ecx +sub edi,ecx +mov edx,[ebp+__dreg+ebx*4] +mov al,0 +cmp cl, 32 +jb short ln2714 +sub cl, 31 +rol edx, 31 +rol edx,cl +jmp short ln2715 +ln2714: +rol edx,cl +ln2715: +adc al,al +or edx,edx +lahf +or ah,al +mov al,0 +mov [ebp+__dreg+ebx*4],edx +sub edi,byte 8 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +; Opcodes F000 - FFFF +Z000: +sub esi,byte 2 +mov edx,2Ch +call group_1_exception +cmp esi,[ebp+__fetch_region_start] +jb short ln2716 +cmp esi,[ebp+__fetch_region_end] +jbe short ln2717 +ln2716: +call basefunction +ln2717: +add esi,[ebp+__io_fetchbase] +sub edi,byte 34 +js near execquit +mov bx,[esi] +add esi,byte 2 +jmp dword[_jmptbl+ebx*4] +section .bss +bits 32 +times ($$-$)&3 db 0 +_jmptbl resb 262144 +section .data +bits 32 +times ($$-$)&3 db 0 +_jmptblcomp: +dd K000-top+117440512 +dd r_illegal-top+117440512 +dd K010-top+117440512 +dd K018-top+117440512 +dd K020-top+117440512 +dd K028-top+117440512 +dd K030-top+117440512 +dd K038-top +dd K039-top +dd r_illegal-top+16777216 +dd K03C-top +dd r_illegal-top+33554432 +dd K040-top+117440512 +dd r_illegal-top+117440512 +dd K050-top+117440512 +dd K058-top+117440512 +dd K060-top+117440512 +dd K068-top+117440512 +dd K070-top+117440512 +dd K078-top +dd K079-top +dd r_illegal-top+16777216 +dd K07C-top +dd r_illegal-top+33554432 +dd K080-top+117440512 +dd r_illegal-top+117440512 +dd K090-top+117440512 +dd K098-top+117440512 +dd K0A0-top+117440512 +dd K0A8-top+117440512 +dd K0B0-top+117440512 +dd K0B8-top +dd K0B9-top +dd r_illegal-top+1157627904 +dd K100-top+117440512 +dd K108-top+117440512 +dd K110-top+117440512 +dd K118-top+117440512 +dd K120-top+117440512 +dd K128-top+117440512 +dd K130-top+117440512 +dd K138-top +dd K139-top +dd K13A-top +dd K13B-top +dd K13C-top +dd r_illegal-top+33554432 +dd K140-top+117440512 +dd K148-top+117440512 +dd K150-top+117440512 +dd K158-top+117440512 +dd K160-top+117440512 +dd K168-top+117440512 +dd K170-top+117440512 +dd K178-top +dd K179-top +dd r_illegal-top+83886080 +dd K180-top+117440512 +dd K188-top+117440512 +dd K190-top+117440512 +dd K198-top+117440512 +dd K1A0-top+117440512 +dd K1A8-top+117440512 +dd K1B0-top+117440512 +dd K1B8-top +dd K1B9-top +dd r_illegal-top+83886080 +dd K1C0-top+117440512 +dd K1C8-top+117440512 +dd K1D0-top+117440512 +dd K1D8-top+117440512 +dd K1E0-top+117440512 +dd K1E8-top+117440512 +dd K1F0-top+117440512 +dd K1F8-top +dd K1F9-top +dd r_illegal-top+83886080 +dd K200-top+117440512 +dd r_illegal-top+117440512 +dd K210-top+117440512 +dd K218-top+117440512 +dd K220-top+117440512 +dd K228-top+117440512 +dd K230-top+117440512 +dd K238-top +dd K239-top +dd r_illegal-top+16777216 +dd K23C-top +dd r_illegal-top+33554432 +dd K240-top+117440512 +dd r_illegal-top+117440512 +dd K250-top+117440512 +dd K258-top+117440512 +dd K260-top+117440512 +dd K268-top+117440512 +dd K270-top+117440512 +dd K278-top +dd K279-top +dd r_illegal-top+16777216 +dd K27C-top +dd r_illegal-top+33554432 +dd K280-top+117440512 +dd r_illegal-top+117440512 +dd K290-top+117440512 +dd K298-top+117440512 +dd K2A0-top+117440512 +dd K2A8-top+117440512 +dd K2B0-top+117440512 +dd K2B8-top +dd K2B9-top +dd r_illegal-top+1157627904 +dd K300-top+117440512 +dd K308-top+117440512 +dd K310-top+117440512 +dd K318-top+117440512 +dd K320-top+117440512 +dd K328-top+117440512 +dd K330-top+117440512 +dd K338-top +dd K339-top +dd K33A-top +dd K33B-top +dd K33C-top +dd r_illegal-top+33554432 +dd K340-top+117440512 +dd K348-top+117440512 +dd K350-top+117440512 +dd K358-top+117440512 +dd K360-top+117440512 +dd K368-top+117440512 +dd K370-top+117440512 +dd K378-top +dd K379-top +dd r_illegal-top+83886080 +dd K380-top+117440512 +dd K388-top+117440512 +dd K390-top+117440512 +dd K398-top+117440512 +dd K3A0-top+117440512 +dd K3A8-top+117440512 +dd K3B0-top+117440512 +dd K3B8-top +dd K3B9-top +dd r_illegal-top+83886080 +dd K3C0-top+117440512 +dd K3C8-top+117440512 +dd K3D0-top+117440512 +dd K3D8-top+117440512 +dd K3E0-top+117440512 +dd K3E8-top+117440512 +dd K3F0-top+117440512 +dd K3F8-top +dd K3F9-top +dd r_illegal-top+83886080 +dd K400-top+117440512 +dd r_illegal-top+117440512 +dd K410-top+117440512 +dd K418-top+117440512 +dd K420-top+117440512 +dd K428-top+117440512 +dd K430-top+117440512 +dd K438-top +dd K439-top +dd r_illegal-top+83886080 +dd K440-top+117440512 +dd r_illegal-top+117440512 +dd K450-top+117440512 +dd K458-top+117440512 +dd K460-top+117440512 +dd K468-top+117440512 +dd K470-top+117440512 +dd K478-top +dd K479-top +dd r_illegal-top+83886080 +dd K480-top+117440512 +dd r_illegal-top+117440512 +dd K490-top+117440512 +dd K498-top+117440512 +dd K4A0-top+117440512 +dd K4A8-top+117440512 +dd K4B0-top+117440512 +dd K4B8-top +dd K4B9-top +dd r_illegal-top+1157627904 +dd K500-top+117440512 +dd K508-top+117440512 +dd K510-top+117440512 +dd K518-top+117440512 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YE90-top+117440512 +dd YE98-top+117440512 +dd YEA0-top+117440512 +dd YEA8-top+117440512 +dd YEB0-top+117440512 +dd YEB8-top+117440512 +dd r_illegal-top+1056964608 +dd YF00-top+117440512 +dd YF08-top+117440512 +dd YF10-top+117440512 +dd YF18-top+117440512 +dd YF20-top+117440512 +dd YF28-top+117440512 +dd YF30-top+117440512 +dd YF38-top+117440512 +dd YF40-top+117440512 +dd YF48-top+117440512 +dd YF50-top+117440512 +dd YF58-top+117440512 +dd YF60-top+117440512 +dd YF68-top+117440512 +dd YF70-top+117440512 +dd YF78-top+117440512 +dd YF80-top+117440512 +dd YF88-top+117440512 +dd YF90-top+117440512 +dd YF98-top+117440512 +dd YFA0-top+117440512 +dd YFA8-top+117440512 +dd YFB0-top+117440512 +dd YFB8-top+117440512 +dd r_illegal-top+1056964608 +dd Z000-top+4278190080 +dd Z000-top+4278190080 +dd Z000-top+4278190080 +dd Z000-top+4278190080 +dd Z000-top+4278190080 +dd Z000-top+4278190080 +dd Z000-top+4278190080 +dd Z000-top+4278190080 +dd Z000-top+4278190080 +dd Z000-top+4278190080 +dd Z000-top+4278190080 +dd Z000-top+4278190080 +dd Z000-top+4278190080 +dd Z000-top+4278190080 +dd Z000-top+4278190080 +dd Z000-top+4278190080 +times ($$-$)&3 db 0 +end diff --git a/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/Starscream/s68000.obj b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/Starscream/s68000.obj new file mode 100644 index 000000000..d81d9c849 Binary files /dev/null and b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/Starscream/s68000.obj differ diff --git a/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/Starscream/star.c b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/Starscream/star.c new file mode 100644 index 000000000..4651dd15b --- /dev/null +++ b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/Starscream/star.c @@ -0,0 +1,5065 @@ +/* +** Starscream 680x0 emulation library +** Copyright 1997, 1998, 1999 Neill Corlett +** +** Refer to STARDOC.TXT for terms of use, API reference, and directions on +** how to compile. +*/ + +#define VERSION "0.27" + +/***************************************************************************/ +/* +** NOTE +** +** All 68020-related variables and functions are currently experimental, and +** unsupported. +*/ + +#include +#include +#include +#include + +/***************************************************************************/ +/* +** Register Usage +** -------------- +** +** This is fairly consistent throughout the file. Occasionally, EAX or EDX +** will be used as a scratch register (in some cases the x86 instruction set +** demands this). +** +** EAX: Bit 0 : V flag +** Bit 1-7 : MUST BE ZERO +** Bit 8 : C flag +** Bit 14 : Z flag +** Bit 15 : N flag +** Bit 16-31: undefined +** EBX: Lower 16 bits: Current instruction word or register number +** Upper 16 bits: zero +** ECX: Primary data +** EDX: Primary address +** EBP: State pointer +** ESI: Current PC, including base offset +** EDI: Cycle counter +*/ +/***************************************************************************/ +/* +** 68010 Loop Mode Timing +** ---------------------- +** +** Loop mode is implemented entirely in the DBRA instruction. It will +** detect when it's supposed to be in loop mode, and adjust its timing when +** applicable. +** +** The __loopmode variable controls when loop mode is active. It is set to +** 1 after an eligible loop is completed. It is set to 0 when the loop +** terminates, or when an interrupt / exception occurs. +** +** Loop info byte: +** +** Bits 1-3: Continuation cycles / 2 +** Bits 4-6: Termination cycles / 2 +** Bits 7-0: (Expiration cycles - continuation cycles) / 2 +** (bit 7 wraps around to bit 0) +** +** With the loop info byte in AL: +** To get the continuation cycles: +** and eax,byte 0Eh +** To get the termination cycles: +** shr al,3 +** and eax,byte 0Eh +** To get the continue/expire difference: +** rol al,2 +** and eax,byte 06h +** +** Default = DBh +** (11011011) +** 101 : 101 = 5 2*5 = 10 continuation cycles +** 101 : 101 = 5 2*5 = 10 termination cycles +** 1 1: 11 = 3 2*3 = 6 10+6 = 16 expiration cycles +** +** (10/10/16 corresponds to the normal DBRA timing behavior) +*/ +/***************************************************************************/ +/* +** Algorithm for trace checkpoint in s680x0exec: +** +** If the SR trace flag is set { +** Set the trace trickybit. This differentiates us from the out-of-time +** case above. +** Set cycles_leftover = cycles_needed. +** Force a context switch. +** } otherwise { +** Clear the trace trickybit. +** } +** Begin the fetch/decode/execute loop as usual. +** +** +** In selected ret_timing routines: +** +** Subtract usual number of cycles from edi +** If I'm out of time (edi is negative) { +** Jump to execend with SF set, as usual. +** } otherwise (guaranteed at least one more instruction) { +** Jump to the s680x0exec trace checkpoint. +** } +** +** +** Make sure that the group 1 exception handler clears the trace trickybit. +** +** +** Upon reaching execend: +** +** If the trace trickybit is set { +** Set cycles_needed = cycles_leftover. +** Add cycles_needed to edi. +** Generate a trace exception (clearing the SR trace flag in the process). +** Clear the trace trickybit. +** If edi is positive, resume the fetch/decode/execute loop. +** Otherwise, fall through to the usual epilogue code. +** } +*/ +/***************************************************************************/ +/* +** Rebasing notes +** -------------- +** +** Cached rebase happens on: +** * JMP, JSR, RTS, RTE, RTR, RTD +** * Exceptions (except hardware interrupts) +** +** Uncached rebase happens on: +** * Entry to s680x0exec() +** * Hardware interrupts +** * Supervisor flag change +** * Cache disable/invalidate (68020+) +** +** I can't think of any good reason why the hardware interrupt case should be +** uncached, except it happens to be convenient. +*/ + +typedef unsigned char byte; +typedef unsigned short word; +typedef unsigned int dword; + +static int use_stack = -1; +static int hog = -1; +static int addressbits = -1; +static int cputype = -1; +static char *sourcename = NULL; + +/* This counts the number of instruction handling routines. There's not much +** point to it except for curiosity. */ +static int routine_counter = 0; + +/* Misc. constants */ +static char *x86ax [5] = {"?", "al" , "ax" , "?", "eax" }; +static char *x86bx [5] = {"?", "bl" , "bx" , "?", "ebx" }; +static char *x86cx [5] = {"?", "cl" , "cx" , "?", "ecx" }; +static char *x86dx [5] = {"?", "dl" , "dx" , "?", "edx" }; +static char *sizename[5] = {"?", "byte", "word", "?", "dword"}; +static int quickvalue[8] = {8, 1, 2, 3, 4, 5, 6, 7}; +static char direction[2] = {'r','l'}; + +// Version info string +static char versioninfo[] = "Starscream v" VERSION " (built " __DATE__ ")"; + +/* Output file where code will be emitted */ +static FILE *codefile; + +/* Line number - used to make temporary labels i.e. "ln1234" */ +static int linenum; + +/* Context size */ +static int contextsize = 0; + +/* Effective address modes */ +enum eamode { + dreg, areg, aind, ainc, adec, adsp, + axdp, absw, absl, pcdp, pcxd, immd +}; + +/* Loop information (68010) */ +static int loop_c_cycles; +static int loop_t_cycles; +static int loop_x_cycles; +static unsigned char loopinfo[0x10000]; + +/* +** Misc. global variables which are used while generating instruction +** handling routines. Some of these may assume more than one role. +*/ +static enum eamode main_eamode; /* EA mode, usually source */ +static enum eamode main_destmode; /* EA mode, destination (for MOVE) */ +static int main_size; /* Operand size (1, 2, or 4) */ +static int sizedef; /* Size field in instruction word */ +static int main_reg; /* Register number */ +static int main_cc; /* Condition code (0-F) */ +static int main_dr; /* Direction (right or left) */ +static int main_ir; /* Immediate or register (for shifts) */ +static int main_qv; /* Quick value */ + +/* Emit a line of code (format string with other junk) */ +static void emit(const char *fmt, ...) { + va_list a; + va_start(a, fmt); + if(codefile) { + vfprintf(codefile, fmt, a); + } else { + fprintf(stderr, "Bad news: Tried to emit() to null file\n"); + exit(1); + } +} + +/* Dump all options. This is delivered to stderr and to the code file. */ +static void optiondump(FILE *o, char *prefix) { + fprintf(o, "%sCPU type: %d (%d-bit addresses)\n", prefix, + cputype, addressbits); + fprintf(o, "%sIdentifiers begin with \"%s\"\n", prefix, + sourcename); + fprintf(o, "%s%s calling conventions\n", prefix, + use_stack ? "__cdecl" : "__fastcall"); + fprintf(o, "%sHog mode: %s\n", prefix, + hog ? "On" : "Off"); +} + +static void gen_banner(void) { + emit("; Generated by STARSCREAM version " VERSION "\n"); + emit("; For assembly by NASM only\n"); + emit(";\n"); + emit("; Options:\n"); + optiondump(codefile, "; * "); + emit(";\n"); + emit("bits 32\n"); +} + +static void align(int n) { + emit("times ($$-$)&%d db 0\n", n - 1); +} + +static void maskaddress(char *reg) { + if(addressbits < 32) { + emit("and %s,%d\n", reg, (1 << addressbits) - 1); + } +} + +static void begin_source_proc(const char *fname, int params) { + char s[1000]; + // generate properly mangled name for the calling convention + if(use_stack) { + sprintf(s, "_%s_%s", sourcename, fname); + } else { + sprintf(s, "@%s_%s@%d", sourcename, fname, 4 * params); + } + emit("global %s\n", s); + emit("%s:\n", s); +} + +static void emitvar(const char *name, int align, int size) { + if(align) { + contextsize += (align-1); + contextsize &= ~(align-1); + } + emit("%s equ %d\n", name, contextsize); + contextsize += size; +} + +/* Generate variables */ +static void gen_variables(void) { + /* + ** CONTEXTINFO_MEM16 + ** CONTEXTINFO_MEM16FC + ** + ** 16-bit memory interface + */ + if(cputype <= 68010) { + emitvar("__fetch" ,4,4); + emitvar("__readbyte" ,4,4); + emitvar("__readword" ,4,4); + emitvar("__writebyte" ,4,4); + emitvar("__writeword" ,4,4); + emitvar("__s_fetch" ,4,4); + emitvar("__s_readbyte" ,4,4); + emitvar("__s_readword" ,4,4); + emitvar("__s_writebyte" ,4,4); + emitvar("__s_writeword" ,4,4); + emitvar("__u_fetch" ,4,4); + emitvar("__u_readbyte" ,4,4); + emitvar("__u_readword" ,4,4); + emitvar("__u_writebyte" ,4,4); + emitvar("__u_writeword" ,4,4); + if(cputype == 68010) { + emitvar("__f_readbyte" ,4,4); + emitvar("__f_readword" ,4,4); + emitvar("__f_writebyte",4,4); + emitvar("__f_writeword",4,4); + } + /* + ** CONTEXTINFO_MEM32 + ** + ** 32-bit memory interface + */ + } else { + emitvar("__fetch" ,4,4); + emitvar("__readbus" ,4,4); + emitvar("__writebus" ,4,4); + emitvar("__s_fetch" ,4,4); + emitvar("__s_readbus" ,4,4); + emitvar("__s_writebus",4,4); + emitvar("__u_fetch" ,4,4); + emitvar("__u_readbus" ,4,4); + emitvar("__u_writebus",4,4); + emitvar("__f_readbus" ,4,4); + emitvar("__f_writebus",4,4); + } + /* + ** CONTEXTINFO_COMMON + ** + ** Registers and other info common to all CPU types + ** + ** It should be noted that on a double fault, bit 0 of both __pc and + ** __interrupts will be set to 1. + */ + if(cputype >= 68000) { + emitvar("__hwstate",4,4); + emitvar("__resethandler",4,4); + emitvar("__reg",4,0); + emitvar("__dreg",4,8*4); + emitvar("__areg",4,7*4); + emitvar("__a7",4,4); + emitvar("__asp",4,4); + emitvar("__pc",4,4); + emitvar("__odometer",4,4); + /* Bit 0 of __interrupts = stopped state */ + emitvar("__interrupts",1,8); + emitvar("__sr",2,2); + } + /* + ** CONTEXTINFO_68010 + ** + ** Registers used on the 68010 and higher + */ + if(cputype >= 68010) { + emitvar("__sfc",1,1); + emitvar("__dfc",1,1); + emitvar("__vbr",4,4); + emitvar("__bkpthandler",4,4); + } + /* + ** CONTEXTINFO_68010SPECIFIC + ** + ** Registers used only on the 68010 + */ + if(cputype == 68010) { + emitvar("__loopmode",1,1); + } + /* + ** CONTEXTINFO_68020 + ** + ** Registers used on the 68020 and higher + */ + if(cputype >= 68020) { + /* + ** 68020 stack pointer rules (tentative) + ** + ** First of all, the 68000/68010 stack pointer behavior has + ** not changed: + ** + ** 1. In supervisor mode, __a7 contains the supervisor stack + ** pointer and __asp contains the user stack pointer. + ** 2. In user mode, __a7 contains the user stack pointer and + ** __asp contains the supervisor stack pointer. + ** + ** The only difference is that the "supervisor stack pointer" + ** can be either ISP or MSP. __xsp contains whichever stack + ** pointer is _not_ the current "supervisor stack pointer". + ** + ** Here's a table summarizing the above rules: + ** + ** S M | __a7 __asp __xsp + ** ----+----------------- + ** 0 0 | USP ISP MSP + ** 0 1 | USP MSP ISP + ** 1 0 | ISP USP MSP + ** 1 1 | MSP USP ISP + ** + ** As usual, whenever SR changes, we have to play Stack + ** Pointer Switcheroo: + ** + ** * If S changes: swap __asp and __a7 (as usual) + ** * If M changes: + ** - If S=0, swap __xsp and __asp + ** - If S=1, swap __xsp and __a7 + */ + emitvar("__xsp",4,4); + } + emitvar("__cycles_needed",4,4); + emitvar("__cycles_leftover",4,4); + emitvar("__fetch_region_start",4,4); // Fetch region cache + emitvar("__fetch_region_end",4,4); + emitvar("__xflag",1,1); + /* + ** Format of __execinfo: + ** Bit 0: s680x0exec currently running + ** Bit 1: PC out of bounds + ** Bit 2: Special I/O section + ** + ** "Special I/O section" is enabled during group 0 exception + ** processing, and it means a couple things: + ** * Address and bus errors will not be tolerated (the CPU will + ** just keel over and die). Therefore, information such as the + ** current PC is not relevant. + ** * Registers are not necessarily live. Since special I/O + ** sections are guaranteed not to cause exceptions, this is not a + ** problem. + */ + emitvar("__execinfo",1,1); + emitvar("__trace_trickybit",1,1); // Pending trace exception + emitvar("__io_cycle_counter",4,4); // always -1 when idle + emitvar("__io_fetchbase",4,4); + emitvar("__io_fetchbased_pc",4,4); + emitvar("__access_address",4,4); + emitvar("save_01",4,4); // Stef Fix (Gens) + + emitvar("contexttop",4,0); +} + +/* Prepare to leave into the cold, dark world of compiled C code */ +static void airlock_exit(void) { + emit("mov [ebp+__io_cycle_counter],edi\n"); + emit("mov [ebp+__io_fetchbased_pc],esi\n"); + emit("push ebx\n"); + emit("push eax\n"); +} + +/* Prepare to return to the warm fuzzy world of assembly code +** (where everybody knows your name) */ +static void airlock_enter(void) { + emit("pop eax\n"); + emit("pop ebx\n"); + emit("mov edi,[ebp+__io_cycle_counter]\n"); + emit("mov esi,[ebp+__io_fetchbased_pc]\n"); +} + +enum { airlock_stacksize = 8 }; + +static void cache_ccr(void) { + emit("mov al,[ebp+__sr]\n"); /* read CCR -> AL */ /* ????????000XNZVC */ + emit("mov ah,al\n"); /* copy to AH */ /* 000XNZVC000XNZVC */ + emit("and ax,0C10h\n"); /* isolate NZ...X */ /* 0000NZ00000X0000 */ + emit("shl ah,3\n"); /* put NZ almost where we want it */ /* 0NZ00000000X0000 */ + emit("shr al,4\n"); /* shift X flag into bit 0 */ /* 0NZ000000000000X */ + emit("mov [ebp+__xflag],al\n"); /* store X flag */ /* 0NZ000000000000X al -> xflag */ + emit("mov al,[ebp+__sr]\n"); /* read CCR -> AL again */ /* 0NZ00000000XNZVC */ + emit("and al,3\n"); /* isolate VC */ /* 0NZ00000000000VC */ + emit("shr al,1\n"); /* just V */ /* 0NZ000000000000V carry */ + emit("adc ah,ah\n"); /* append C to rest of flags */ /* NZ00000C0000000V */ +} + +static void writeback_ccr(void) { + emit("shr ah,1\n"); /* C flag -> x86 carry */ /* 0NZ?????0000000V carry */ + emit("adc ax,ax\n"); /* append to V flag */ /* NZ?????0000000VC */ + emit("and ax,0C003h\n"); /* isolate NZ.......VC */ /* NZ000000000000VC */ + emit("or ah,[ebp+__xflag]\n"); /* load X flag */ /* NZ00000X000000VC */ + emit("ror ah,4\n"); /* now we have XNZ....VC */ /* 000XNZ00000000VC */ + emit("or al,ah\n"); /* OR them together */ /* 000XNZ00000XNZVC */ + emit("mov [ebp+__sr],al\n"); /* store the result */ /* 000XNZ00000XNZVC al -> sr */ +} + +/* +** This will make edi _very_ negative... far enough negative that the +** leftover cycle incorporation at the end of s68000exec() shouldn't be +** enough to make it positive. +*/ +static void force_context_switch(void) { + emit("sub edi,[ebp+__cycles_needed]\n"); + emit("mov dword[ebp+__cycles_needed],0\n"); +} + +/* +** Put all the unused cycles in the leftover cycle bank, so we can call +** attention to the tricky bit processor. +*/ +static void force_trickybit_process(void) { + emit("inc edi\n"); + emit("add [ebp+__cycles_leftover],edi\n"); + emit("or edi,byte -1\n");/* smaller than a mov */ +} + +/* "newpc" has been renamed to this */ +void perform_cached_rebase(void); + +/* Copy either __s_* or __u_* memory map pointers */ +static void copy_memory_map(char *map, char *reg) { + emit("mov %s,[ebp+__%s_fetch]\n", reg, map); + emit("mov [ebp+__fetch],%s\n", reg); + if(cputype < 68020) { + emit("mov %s,[ebp+__%s_readbyte]\n" , reg, map); + emit("mov [ebp+__readbyte],%s\n" , reg); + emit("mov %s,[ebp+__%s_readword]\n" , reg, map); + emit("mov [ebp+__readword],%s\n" , reg); + emit("mov %s,[ebp+__%s_writebyte]\n", reg, map); + emit("mov [ebp+__writebyte],%s\n", reg); + emit("mov %s,[ebp+__%s_writeword]\n", reg, map); + emit("mov [ebp+__writeword],%s\n", reg); + } else { + emit("mov %s,[ebp+__%s_readbus]\n" , reg, map); + emit("mov [ebp+__readbus],%s\n" , reg); + emit("mov %s,[ebp+__%s_writebus]\n" , reg, map); + emit("mov [ebp+__writebus],%s\n" , reg); + } +} + +/***************************************************************************/ + +static void gen_interface(void) { + emit("section .text\n"); + emit("bits 32\n"); + emit("top:\n"); + +/***************************************************************************/ +/* +** int s680x0_init(void) +** +** Entry: Nothing +** Exit: Zero +** +** This must be called before anything else. It decompresses the main jump +** table (and loop info, in the case of the 68010). +*/ + begin_source_proc("init", 0); + + emit("pushad\n"); + emit("mov edi,_jmptbl\n"); + emit("mov esi,_jmptblcomp\n"); + if(cputype == 68010) { + emit("mov ebx,_looptbl\n"); + } + emit(".decomp:\n"); + emit("lodsd\n"); + emit("mov ecx,eax\n"); + emit("and eax,0FFFFFFh\n"); + emit("shr ecx,24\n"); + emit("add eax,top\n"); + emit("inc ecx\n"); + if(cputype == 68010) { + emit("mov ebp,ecx\n"); + } + emit(".jloop:\n"); + emit("mov [edi],eax\n"); + emit("add edi,byte 4\n"); + emit("dec ecx\n"); + emit("jnz short .jloop\n"); + if(cputype == 68010) { + emit("lodsb\n"); + emit(".lloop:\n"); + emit("mov [ebx],al\n"); + emit("inc ebx\n"); + emit("dec ebp\n"); + emit("jnz short .lloop\n"); + } + emit("cmp edi,_jmptbl+262144\n"); + emit("jne short .decomp\n"); + + emit("popad\n"); + emit("xor eax,eax\n"); + emit("ret\n"); + +/***************************************************************************/ +/* +** const char *s680x0_get_version(void) +** +** Entry: Nothing +** Exit: Pointer to version info string +*/ + + emit("versioninfo:\n"); + emit("db \"%s\",0\n", versioninfo); + + begin_source_proc("get_version", 0); + + emit("mov eax,versioninfo\n"); + emit("ret\n"); + +/***************************************************************************/ +/* +** unsigned s680x0_get_state_size(void) +** +** Entry: Nothing +** Exit: Size of context array (in bytes) +*/ + begin_source_proc("get_state_size", 0); + + emit("mov eax,contexttop\n"); + emit("ret\n"); + +/***************************************************************************/ +/* +** void s680x0_clear_state(state) +*/ + begin_source_proc("clear_state", 1); + + emit("push ebp\n"); + if(use_stack) { + emit("mov ebp,[esp+4+4]\n"); + } else { + emit("mov ebp,ecx\n"); + } + + emit("xor eax,eax\n"); + emit(".clearloop:\n"); + emit("mov dword[ebp+eax],0\n"); + emit("add eax,byte 4\n"); + emit("cmp eax,contexttop\n"); + emit("jb .clearloop\n"); + + // remember to init __io_cycle_counter to -1 + emit("mov dword[ebp+__io_cycle_counter],-1\n"); + // also initialize SR just because + emit("mov word[ebp+__sr],2700h\n"); + + emit("pop ebp\n"); + emit("ret\n"); + +/***************************************************************************/ +/* +** void s680x0_set_memory_maps(state,infostruct) +*/ + begin_source_proc("set_memory_maps", 2); + + emit("push ebp\n"); + + if(use_stack) { + emit("mov ebp,[esp+4+4]\n"); + emit("mov edx,[esp+4+8]\n"); + } else { + emit("mov ebp,ecx\n"); + } + + emit("mov eax,[edx+0]\n"); + emit("mov [ebp+__s_fetch],eax\n"); + emit("mov eax,[edx+4]\n"); + emit("mov [ebp+__s_readbyte],eax\n"); + emit("mov eax,[edx+8]\n"); + emit("mov [ebp+__s_readword],eax\n"); + emit("mov eax,[edx+12]\n"); + emit("mov [ebp+__s_writebyte],eax\n"); + emit("mov eax,[edx+16]\n"); + emit("mov [ebp+__s_writeword],eax\n"); + emit("mov eax,[edx+20]\n"); + emit("mov [ebp+__u_fetch],eax\n"); + emit("mov eax,[edx+24]\n"); + emit("mov [ebp+__u_readbyte],eax\n"); + emit("mov eax,[edx+28]\n"); + emit("mov [ebp+__u_readword],eax\n"); + emit("mov eax,[edx+32]\n"); + emit("mov [ebp+__u_writebyte],eax\n"); + emit("mov eax,[edx+36]\n"); + emit("mov [ebp+__u_writeword],eax\n"); + // copy the appropriate memory map + emit("test byte[ebp+__sr+1],20h\n"); + emit("jz short .user\n"); + copy_memory_map("s", "ecx"); + emit("jmp short .return\n"); + emit(".user:\n"); + copy_memory_map("u", "ecx"); + emit(".return:\n"); + emit("pop ebp\n"); + emit("ret\n"); + +/***************************************************************************/ +/* +** int s680x0_reset(state) +** +** Entry: Nothing +** Exit: 0 on success +** 1 on failure: +** * if there's no Supervisor Program entry for address 0 +** * if s680x0exec() is active +** -1 on double fault +*/ + begin_source_proc("reset", 1); + + emit("push ebp\n"); + emit("push esi\n"); + + if(use_stack) { + emit("mov ebp,[esp+4+8]\n"); + } else { + emit("mov ebp,ecx\n"); + } + + emit("mov eax,1\n"); + emit("test [ebp+__execinfo],al\n"); /* Ensure s680x0exec() inactive */ + emit("jnz near .return\n"); + emit("cmp dword[ebp+__s_fetch],0\n"); + emit("je near .return\n"); + emit("dec eax\n"); + emit("mov [ebp+__execinfo],al\n"); + emit("sub eax,byte 16\n"); + emit(".gp:\n"); + emit("mov dword[ebp+__reg+64+eax*4],0\n"); + emit("inc eax\n"); + emit("jnz short .gp\n"); + emit("mov [ebp+__asp],eax\n"); + if(cputype >= 68020) emit("mov [ebp+__xsp],eax\n"); + /* Set up SR for no tracing, supervisor mode, ISP, PPL 7 */ + emit("mov word[ebp+__sr],2700h\n"); + if(cputype >= 68010) { + emit("mov [ebp+__vbr],eax\n"); + emit("mov [ebp+__sfc],al\n"); + emit("mov [ebp+__dfc],al\n"); + } + if(cputype == 68010) { + emit("mov [ebp+__loopmode],al\n"); + } + /* Copy supervisor address space information */ + copy_memory_map("s", "eax"); + /* Generate Supervisor Program Space reads to get the initial PC and + ** SSP/ISP */ + emit("mov eax,1\n"); /* assume failure */ + emit("mov [ebp+__pc],eax\n"); + emit("mov [ebp+__interrupts],al\n"); + emit("xor esi,esi\n"); + emit("call basefunction\n");/* will preserve eax */ + emit("test byte[ebp+__execinfo],2\n"); + emit("jnz short .return\n"); + emit("add esi,[ebp+__io_fetchbase]\n"); + emit("mov eax,[esi]\n"); + emit("rol eax,16\n"); + emit("mov [ebp+__a7],eax\n"); + emit("mov eax,[esi+4]\n"); + emit("rol eax,16\n"); + emit("mov [ebp+__pc],eax\n"); + /* An address error here will cause a double fault */ + emit("and eax,byte 1\n"); + emit("mov [ebp+__interrupts],al\n"); + emit("neg eax\n"); /* -1 on double fault, 0 on success */ + + emit(".return:\n"); + emit("pop esi\n"); + emit("pop ebp\n"); + emit("ret\n"); + +/***************************************************************************/ +/* +** unsigned s680x0_execute(state, cycles) +** +** Entry: state pointer, # cycles to execute +** Exit: 80000000h: success +** 80000001h: PC out of range +** 80000002h: unsupported stack frame +** FFFFFFFFh: CPU is dead because of a double fault +** < 80000000h: invalid instruction = address of invalid instr. +*/ + begin_source_proc("execute", 2); + + emit("push ebp\n"); + emit("push ebx\n"); + emit("push ecx\n"); + emit("push edx\n"); + emit("push esi\n"); + emit("push edi\n"); + + if(use_stack) { + emit("mov ebp,[esp+4+24]\n"); + emit("mov eax,[esp+4+28]\n"); + } else { + emit("mov ebp,ecx\n"); + emit("mov eax,edx\n"); + } + + /* + ** Check for stopped and double-faulted states. + */ + emit("test byte[ebp+__interrupts],1\n"); + emit("jz .notstopped\n"); + emit("test byte[ebp+__pc],1\n"); + emit("jz .notfaulted\n"); + emit("or eax,byte -1\n"); + emit("jmp execreturn\n"); + emit(".notfaulted:\n"); + emit("add [ebp+__odometer],eax\n"); + emit("mov eax,80000000h\n"); + emit("jmp execreturn\n"); + emit(".notstopped:\n"); + + emit("mov [ebp+__cycles_needed],eax\n"); + emit("mov edi,eax\n");/* store # of cycles to execute */ + emit("dec edi\n"); + + emit("xor ebx,ebx\n"); + emit("mov esi,[ebp+__pc]\n"); + cache_ccr(); + emit("mov dword[ebp+__io_fetchbase],0\n"); + emit("mov byte[ebp+__execinfo],1\n"); + + /* + ** Force an uncached re-base. + ** This fulfills the "Entry to s680x0exec()" case. + */ + emit("call basefunction\n"); + emit("add esi,[ebp+__io_fetchbase]\n"); + emit("test byte[ebp+__execinfo],2\n"); /* Check for PC out of bounds */ + emit("jnz near exec_bounderror\n"); + + emit("mov dword[ebp+__cycles_leftover],0\n");/* an extra precaution */ + + /* PPL and Trace checkpoint */ + emit("exec_checkpoint:\n"); + emit("js execquit\n"); + + /* Check PPL */ + emit("mov cl,[ebp+__sr+1]\n"); + emit("and ecx,byte 7\n"); + emit("inc ecx\n"); + emit("mov ch,[ebp+__interrupts]\n"); + emit("or ch,ch\n"); + emit("js short .yesint\n"); + emit("shr ch,cl\n"); + emit("jz short .noint\n"); + emit(".yesint:\n"); + emit("call flush_interrupts\n"); + /* Force an uncached re-base */ + emit("call basefunction\n"); + emit("add esi,[ebp+__io_fetchbase]\n"); + emit("test byte[ebp+__execinfo],2\n"); /* Check for PC out of bounds */ + emit("jnz near exec_bounderror\n"); + emit(".noint:\n"); + + /* + ** If the SR Trace flag is set, generate a pending trace exception. + */ + emit("mov ch,[ebp+__sr+1]\n"); + emit("and ch,80h\n"); /* isolate trace flag */ + emit("mov [ebp+__trace_trickybit],ch\n"); + emit("jz execloop\n"); + /* + ** Activate the tricky bit processor. + ** + ** Because edi isn't checked for negativity before entering the + ** fetch/decode/execute loop, we're guaranteed to execute at least + ** one more instruction before any trace exception. + ** + ** If another group 1 exception happens in the course of executing + ** this next instruction, then the group_1_exception routine will + ** clear the trace tricky bit and re-adjust the cycle counters, and + ** we'll pretend none of this ever happened. + */ + force_trickybit_process(); + + emit("execloop:\n"); +/* emit("xor ebx,ebx\n");suffice to say, bits 16-31 should be zero... */ + emit("mov bx,[esi]\n"); + emit("add esi,byte 2\n"); + emit("jmp dword[_jmptbl+ebx*4]\n"); + /* Traditional loop - used when hog mode is off */ + if(!hog) { + emit("execend:\n"); + emit("jns execloop\n"); + } + emit("execquit:\n"); + + /* + ** Tricky Bit Processor + */ + /* Look for trace tricky bit */ + emit("cmp byte[ebp+__trace_trickybit],0\n"); + emit("je short execquit_notrace\n"); + /* Generate trace exception */ + emit("mov edx,24h\n"); + emit("call group_1_exception\n"); + perform_cached_rebase(); + /* Subtract time used by exception processing */ + emit("sub edi,byte %d\n", (cputype == 68010) ? 38 : 34); + emit("execquit_notrace:\n"); + + /* + ** Look for pending interrupts that exceed the current PPL. These + ** are higher priority and are therefore processed last (the ISR will + ** end up getting control). + */ + emit("mov cl,[ebp+__sr+1]\n"); + emit("and ecx,byte 7\n"); + emit("inc ecx\n"); + emit("mov ch,[ebp+__interrupts]\n"); + emit("or ch,ch\n"); + emit("js short execquit_yesinterrupt\n"); + emit("shr ch,cl\n"); + emit("jz short execquit_nointerrupt\n"); + emit("execquit_yesinterrupt:\n"); + emit("call flush_interrupts\n"); + /* + ** Force an uncached re-base. + ** This fulfills the "Hardware interrupt" case. + */ + emit("call basefunction\n"); + emit("add esi,[ebp+__io_fetchbase]\n"); + emit("test byte[ebp+__execinfo],2\n"); /* Check for PC out of bounds */ + emit("jnz short exec_bounderror\n"); + emit("execquit_nointerrupt:\n"); + + /* + ** Incorporate leftover cycles (if any) and see if we should keep + ** running. + */ + emit("add edi,[ebp+__cycles_leftover]\n"); + emit("mov dword[ebp+__cycles_leftover],0\n"); + emit("jns execloop\n"); + + /* Leave s680x0exec with "Success" code. */ + emit("mov ecx,80000000h\n"); + + /* + ** Exit the s680x0exec routine. By this time the return code should + ** already be in ecx. + */ + emit("execexit:\n"); + emit("sub esi,[ebp+__io_fetchbase]\n"); + writeback_ccr(); + emit("mov [ebp+__pc],esi\n"); + emit("inc edi\n"); + emit("mov edx,[ebp+__cycles_needed]\n"); + emit("sub edx,edi\n"); + emit("add [ebp+__odometer],edx\n"); + emit("mov byte[ebp+__execinfo],0\n"); + + /* + ** Remember: __io_cycle_counter is always -1 when idle! + ** + ** This prevents us from having to check __execinfo during the + ** readOdometer / tripOdometer calls. + */ + emit("mov dword[ebp+__cycles_needed],0\n"); + emit("mov dword[ebp+__io_cycle_counter],-1\n"); + + emit("mov eax,ecx\n");/* return code */ + + emit("execreturn:\n"); + + emit("pop edi\n"); + emit("pop esi\n"); + emit("pop edx\n"); + emit("pop ecx\n"); + emit("pop ebx\n"); + emit("pop ebp\n"); + emit("ret\n"); + + /* + ** Leave s680x0exec with "Out of bounds" code. + */ + emit("exec_bounderror:\n"); + emit("mov ecx,80000001h\n"); + emit("jmp short execexit\n"); + + /* + ** Invalid instruction handler + */ + emit("invalidins:\n"); + emit("sub esi,byte 2\n"); /* back up one word */ + emit("mov ecx,esi\n");/* get address in ecx */ + emit("sub ecx,[ebp+__io_fetchbase]\n");/* subtract base */ + maskaddress("ecx"); + if(addressbits == 32) { + emit("and ecx,7FFFFFFFh\n"); + } +/* emit("or byte[__stopped],2\n");*/ + emit("jmp short execexit\n"); + +/***************************************************************************/ +/* +** unsigned s680x0_getreg(state,n) +*/ + begin_source_proc("getreg", 2); + + emit("push ebp\n"); + if(use_stack) { + emit("mov ebp,[esp+4+4]\n"); + emit("mov edx,[esp+4+8]\n"); + } else { + emit("mov ebp,ecx\n"); + } + emit("cmp edx,byte 17\n"); + emit("jb short .normalreg\n"); + emit("je short .pc\n"); + emit("cmp edx,byte 18\n"); + emit("je short .sr\n"); + emit("ja short .none\n"); + + emit(".normalreg:\n"); + emit("mov eax,[ebp+__reg+edx*4]\n"); + emit("jmp short .exit\n"); + + emit(".pc:\n"); + /* + ** Returns the current program counter. Works anywhere, including I/O, + ** RESET, and BKPT handlers. + ** + ** Note that the value returned won't necessarily coincide exactly with the + ** beginning of an instruction. + */ + emit("test byte[ebp+__execinfo],1\n"); + emit("jnz short .pclive\n"); + emit("mov eax,[ebp+__pc]\n"); + emit("jmp short .exit\n"); + emit(".pclive:\n"); + emit("mov eax,[ebp+__io_fetchbased_pc]\n"); + emit("sub eax,[ebp+__io_fetchbase]\n"); + emit("jmp short .exit\n"); + + emit(".sr:\n"); + emit("movzx eax,word[ebp+__sr]\n"); + emit("jmp short .exit\n"); + + emit(".none:\n"); + emit("xor eax,eax\n"); + emit(".exit:\n"); + emit("pop ebp\n"); + emit("ret\n"); + +/***************************************************************************/ +/* +** s680x0_interrupt(state, 256*vector+level) +** +** Entry: interrupt level +** 256*vector (-1 for auto, -2 for spurious) +** Exit: EAX = 0 on success +** 1 on failure, previous vector exists +** 2 on invalid input +*/ + begin_source_proc("interrupt", 2); + + emit("push ebp\n"); + emit("push ecx\n"); + emit("push edx\n"); + if(use_stack) { + emit("mov ebp,[esp+4+12]\n"); /* state */ + emit("mov edx,[esp+8+12]\n"); /* vector*256+level */ + } else { + emit("mov ebp,ecx\n"); + } + emit("mov eax,edx\n"); + emit("sar edx,8\n"); // edx=vector + emit("and eax,0FFh\n"); // eax=level + /* + ** Verify parameters. + */ + emit("cmp eax,byte 7\n"); + emit("ja short .badinput\n"); + emit("or eax,eax\n"); + emit("jz short .badinput\n"); + emit("cmp edx,255\n"); + emit("jg short .badinput\n"); + emit("cmp edx,byte -2\n"); + emit("jl short .badinput\n"); + /* + ** Calculate the vector number. + */ + emit("jne short .notspurious\n"); + emit("mov edx,18h\n"); + emit(".notspurious:\n"); + emit("or edx,edx\n"); + emit("jns short .notauto\n"); + emit("lea edx,[eax+18h]\n"); + emit(".notauto:\n"); + /* + ** Test to see if this interrupt level is already pending. + ** If it is, return with failure. + */ + emit("push ecx\n"); + emit("mov cl,al\n"); + emit("mov ah,1\n"); + emit("shl ah,cl\n"); + emit("pop ecx\n"); + emit("test [ebp+__interrupts],ah\n"); + emit("jnz .failure\n"); + /* + ** Commit the given interrupt and vector number. + */ + emit("or [ebp+__interrupts],ah\n"); + emit("mov ah,0\n"); + emit("mov [ebp+__interrupts+eax],dl\n"); + emit("and byte[ebp+__interrupts],0FEh\n"); + /* + ** Notify the tricky bit handler. If we're doing this outside of + ** s680x0exec(), then the notification will have no effect, because + ** __io_cycle_counter is always -1 when idle. + */ + emit("mov edx,[ebp+__io_cycle_counter]\n"); + emit("inc edx\n"); + emit("add [ebp+__cycles_leftover],edx\n"); + emit("mov dword[ebp+__io_cycle_counter],-1\n"); + /* + ** Success (0) + */ + emit("pop edx\n"); + emit("pop ecx\n"); + emit("pop ebp\n"); + emit("xor eax,eax\n"); + emit("ret\n"); + /* + ** Failure (1) + */ + emit(".failure:\n"); + emit("pop edx\n"); + emit("pop ecx\n"); + emit("pop ebp\n"); + emit("mov eax,1\n"); + emit("ret\n"); + /* + ** Bad input (2) + */ + emit(".badinput:\n"); + emit("pop edx\n"); + emit("pop ecx\n"); + emit("pop ebp\n"); + emit("mov eax,2\n"); + emit("ret\n"); + +/***************************************************************************/ +/* +** s680x0_flush_interrupts(state) +** +** Flushes all pending interrupts. +** +** Entry: Nothing +** Exit: Nothing +*/ + begin_source_proc("flush_interrupts", 1); + + emit("push ebp\n"); + if(use_stack) { + emit("mov ebp,[esp+4+4]\n"); + } else { + emit("mov ebp,ecx\n"); + } + + /* + ** If s680x0exec() is already running, then the interrupts are about + ** to get flushed anyway. So ignore this call. + */ + emit("test byte[ebp+__execinfo],1\n"); + emit("jnz .noflush\n"); + /* Make registers "live" */ + emit("pushad\n"); + emit("mov esi,[ebp+__pc]\n"); + emit("mov dword[ebp+__io_fetchbase],0\n"); + cache_ccr(); + emit("xor edi,edi\n"); /* well, semi-live */ + emit("call flush_interrupts\n"); + emit("sub [ebp+__odometer],edi\n"); /* edi will be <= 0 here */ + emit("mov [ebp+__pc],esi\n"); /* PC guaranteed unbased */ + writeback_ccr(); + emit("popad\n"); + emit(".noflush:\n"); + + emit("pop ebp\n"); + emit("ret\n"); + +/***************************************************************************/ +/* +** unsigned s680x0_read_odometer(state) +** +** Reads the odometer (works from anywhere) +** Entry: Nothing +** Exit: Odometer in EAX +*/ + begin_source_proc("read_odometer", 1); + + emit("push ebp\n"); + if(use_stack) { + emit("mov ebp,[esp+4+4]\n"); + } else { + emit("mov ebp,ecx\n"); + } + + emit("mov eax,[ebp+__cycles_needed]\n"); + emit("sub eax,[ebp+__io_cycle_counter]\n"); + emit("dec eax\n"); /* eax = elapsed cycles */ + emit("sub eax,[ebp+__cycles_leftover]\n"); + emit("add eax,[ebp+__odometer]\n"); /* add to old __odometer */ + + emit("pop ebp\n"); + emit("ret\n"); + +/***************************************************************************/ +/* +** s680x0_break(state) +** +** Ends the s680x0exec call prematurely. The early exit is reflected in +** __odometer. +** Entry: Nothing +** Exit: Nothing +*/ + begin_source_proc("break", 1); + + emit("push ebp\n"); + if(use_stack) { + emit("mov ebp,[esp+4+4]\n"); + } else { + emit("mov ebp,ecx\n"); + } + + emit("mov eax,[ebp+__cycles_needed]\n"); + emit("sub [ebp+__io_cycle_counter],eax\n"); + emit("xor eax,eax\n"); + emit("mov [ebp+__cycles_needed],eax\n"); + + emit("pop ebp\n"); + emit("ret\n"); + + +} + +/***************************************************************************/ + +/* +** Routine that flushes pending interrupts (with correct priority). +** Assumes "live" registers, including EDI and [__io_fetchbase]. +** +** Does not rebase the PC. In fact, it will un-base the PC even if there +** aren't any pending interrupts. +** +** s680x0flushInterrupts() is actually a wrapper for this. +*/ +static void gen_flush_interrupts(void) { + int cycles = (cputype == 68010) ? 46 : 44; + emit("flush_interrupts:\n"); + /* Unbase PC */ + emit("sub esi,[ebp+__io_fetchbase]\n"); + emit("mov dword[ebp+__io_fetchbase],0\n"); + /* This loop is intentionally post-tested because interrupt level 7 + ** is non-maskable. */ + emit("mov edx,7\n"); + emit("mov cl,80h\n"); + emit("mov ch,[ebp+__sr+1]\n"); /* current PPL */ + emit("and ch,7\n"); + emit(".loop:\n"); + emit("test [ebp+__interrupts],cl\n"); + emit("jz short .noint\n"); + +emit("mov [ebp+save_01], dl\n"); // Stef Fix (Gens) + + emit("mov dl,[ebp+__interrupts+edx]\n"); + emit("not cl\n"); + emit("and [ebp+__interrupts],cl\n"); + emit("shl edx,2\n"); + emit("call group_1_exception\n"); + +emit("and [ebp+__sr + 1], byte 0xF8\n"); // Stef Fix (Gens) +emit("mov dl, [ebp+save_01]\n"); // Stef Fix (Gens) + + emit("sub edi,byte %d\n", cycles); + +emit("or [ebp+__sr + 1], dl\n"); // Stef Fix (Gens) + + emit("jmp short .intdone\n"); + emit(".noint:\n"); + emit("dec edx\n"); + emit("jz short .intdone\n"); + emit("shr cl,1\n"); + emit("cmp dl,ch\n"); + emit("jg short .loop\n"); + emit(".intdone:\n"); + emit("ret\n"); +} + +/***************************************************************************/ + +static void ret_timing(int n) { + if(n) { + emit("sub edi,%s%d\n", (n < 128) ? "byte " : "", n); + } else { + emit("or edi,edi\n"); + } + /* If hog mode is off, jump back to the main loop */ + if(!hog) { + emit("jmp execend\n"); + /* If hog mode is on, fetch and execute the next instruction */ + } else { + emit("js near execquit\n"); + emit("mov bx,[esi]\n"); + emit("add esi,byte 2\n"); + emit("jmp dword[_jmptbl+ebx*4]\n"); + } +} + +/* +** This version of ret_timing does a trace flag check. +** +** Note: this only needs to be used for instructions which can potentially +** _set_ the trace flag. Instructions which can't set the trace flag (even +** if they can clear it) are OK to use ret_timing as usual. Why? Well, if +** an instruction is run in trace mode, that instruction is doomed to be +** traced, regardless if it clears the trace flag during its execution. +** Furthermore, the trace exception (being a group 1 exception after all) +** will clear the trace tricky bit as well as the trace flag. +*/ +static void ret_timing_checkpoint(int n) { + if(n) { + emit("sub edi,%s%d\n", (n < 128) ? "byte " : "", n); + } else { + emit("or edi,edi\n"); + } + emit("jmp exec_checkpoint\n"); +} + +/***************************************************************************/ + +/* This routine decodes an extension word into EDX. */ +static void gen_decode_ext(void) { + emit("decode_ext:\n"); + if(cputype <= 68010) { + emit("push ecx\n"); + emit("movzx edx,word[esi]\n"); + emit("movsx ecx,dl\n"); + emit("add esi,byte 2\n"); + emit("shr edx,12\n"); + emit("mov edx,[ebp+__reg+edx*4]\n"); + emit("jc short .long\n"); + emit("movsx edx,dx\n"); + emit(".long:\n"); + emit("add edx,ecx\n"); + emit("pop ecx\n"); + emit("ret\n"); + } else { + /* For future expansion... */ + /* need an extra jump table here */ + } +} + +/***************************************************************************/ + +/* +** Perform a cached rebase +*/ +void perform_cached_rebase(void) { + int myline = linenum; linenum += 2; + emit("cmp esi,[ebp+__fetch_region_start]\n"); + emit("jb short ln%d\n", myline); + emit("cmp esi,[ebp+__fetch_region_end]\n"); + emit("jbe short ln%d\n", myline + 1); + emit("ln%d:\n", myline); + emit("call basefunction\n"); + emit("ln%d:\n", myline + 1); + emit("add esi,[ebp+__io_fetchbase]\n"); +} + +/***************************************************************************/ + +/* +** This is the function that generates a base for a given 68K PC. +** +** Entry: 68K PC in ESI +** Exit: Newly calculated base in [__io_fetchbase] +** +** Sounds like a simple lookup into the __fetch array, and in the case of +** 32-bit addresses, it is. But for anything less, we'll need to compensate +** for potential garbage in the unused address bits, by subtracting the value +** of these unused bits from the base. This way the full 32 bits of the PC +** are preserved, even if they're not used. +** +** The only registers which need to be "live" here are ESI and +** [__io_fetchbase]. The fetch region cache is updated, and bit 1 of +** __execinfo is set if the base couldn't be calculated. +*/ +static void gen_basefunction(void) { + emit("basefunction:\n"); + emit("push ecx\n"); + /* + ** Prepare ESI by masking off unused address bits (but save it + ** first). + */ + if(addressbits < 32) { + emit("push esi\n"); + maskaddress("esi"); + } + emit("mov ecx,[ebp+__fetch]\n"); + emit(".check:\n"); + emit("cmp esi,[ecx]\n"); /* Are we smaller? */ + emit("jb short .next\n"); /* Yes, go to next address */ + emit("cmp esi,[ecx+4]\n"); /* Are we bigger? */ + emit("jbe short .base\n"); + emit(".next:\n"); + emit("cmp dword [ecx],byte -1\n"); /* End of list? */ + emit("je short .outofrange\n"); + emit("add ecx,byte 12\n"); /* To the next structure */ + emit("jmp short .check\n"); + /* Bad news... we jumped out into the weeds. */ + emit(".outofrange:\n"); + if(addressbits < 32) emit("pop esi\n"); + emit("mov dword[ebp+__io_fetchbase],0\n"); + emit("mov dword[ebp+__fetch_region_start],-1\n"); + emit("mov dword[ebp+__fetch_region_end],0\n"); + force_context_switch(); + emit("or byte[ebp+__execinfo],2\n"); + emit("pop ecx\n"); + emit("ret\n"); + + emit(".base:\n"); + /* + ** Dealing with addressbits < 32 again... if the unused PC bits are + ** anything but zero, then we'll need to adjust the base to + ** compensate. + */ + if(addressbits < 32) { + emit("mov esi,[esp]\n"); + emit("and esi,%d\n", 0xFFFFFFFF << addressbits); + } + emit("push edx\n"); + emit("mov edx,ecx\n"); + /* + ** Update the fetch region cache, adding in the garbage bits where + ** applicable. + */ + emit("mov ecx,[edx]\n"); + if(addressbits < 32) emit("or ecx,esi\n"); + emit("mov [ebp+__fetch_region_start],ecx\n"); + emit("mov ecx,[edx+4]\n"); + if(addressbits < 32) emit("or ecx,esi\n"); + emit("mov [ebp+__fetch_region_end],ecx\n"); + emit("mov ecx,[edx+8]\n"); + emit("mov [ebp+__io_fetchbase],ecx\n"); + emit("pop edx\n"); + if(addressbits < 32) { + /* + ** Subtract garbage bits from the base, and restore the + ** original 32-bit PC value. + */ + emit("sub [ebp+__io_fetchbase],esi\n"); + emit("pop esi\n"); + } + emit("pop ecx\n"); + emit("ret\n"); +} + +/***************************************************************************/ + +/* Read flags from CL into our CCR. CX is unmodified. */ +static void cl2ccr(void){ + emit("mov al,cl\n"); /* read CCR -> AL */ /* ???????????XNZVC */ + emit("mov ah,al\n"); /* copy to AH */ /* ???XNZVC???XNZVC */ + emit("and ax,0C10h\n"); /* isolate NZ...X */ /* 0000NZ00000X0000 */ + emit("shl ah,3\n"); /* put NZ almost where we want it */ /* 0NZ00000000X0000 */ + emit("shr al,4\n"); /* shift X flag into bit 0 */ /* 0NZ000000000000X */ + emit("mov [ebp+__xflag],al\n"); /* store X flag */ /* 0NZ000000000000X al -> xflag */ + emit("mov al,cl\n"); /* read CCR -> AL again */ /* 0NZ00000000XNZVC */ + emit("and al,3\n"); /* isolate VC */ /* 0NZ00000000000VC */ + emit("shr al,1\n"); /* just V */ /* 0NZ000000000000V carry */ + emit("adc ah,ah\n"); /* append C to rest of flags */ /* NZ00000C0000000V */ +} + +/* +** Read flags from CX into our SR, performing a mode switch where applicable. +** CX is unmodified. Uses 4 bytes of stack. +** +** This does not do any of the trace flag mojo, so be sure to check for it +** explicitly where applicable (hint: ret_timing_checkpoint). +*/ +static void cx2sr(void){ + int myline = linenum; linenum += 2; + + emit("push ecx\n"); + /* Step 1: switch supervisor mode */ + /* Is the new mode different from the last? */ + emit("mov cl,[ebp+__sr+1]\n"); + emit("and cx,2020h\n"); + emit("xor ch,cl\n"); + emit("jz near ln%d\n", myline); + /* If so, swap stack pointers */ + emit("mov ecx,[ebp+__a7]\n"); + emit("xchg ecx,[ebp+__asp]\n"); + emit("mov [ebp+__a7],ecx\n"); + /* and copy the appropriate memory map */ + emit("test byte[esp+1],20h\n"); + emit("jz short ln%d\n", myline + 1); + copy_memory_map("s", "ecx"); + emit("jmp short ln%d\n", myline); + emit("ln%d:\n", myline + 1); + copy_memory_map("u", "ecx"); + emit("ln%d:\n", myline); + emit("pop ecx\n"); + + /* Step 2: set new PPL / supervisor mode / trace flag */ + emit("mov [ebp+__sr+1],ch\n"); + emit("and byte[ebp+__sr+1],0A7h\n"); + + /* Step 3: Store CL into CCR */ + cl2ccr(); +} + +/* Read flags from our CCR into CL. CH is zeroed. */ +static void ccr2cl(void){ + /* Read XNZ */ + emit("mov ch,[ebp+__xflag]\n"); /* 0000000X???????? */ + emit("mov cl,ah\n"); /* 0000000XNZ?????C */ + emit("shr cx,6\n"); /* 0000000000000XNZ */ + /* Read V */ + emit("add cl,cl\n"); /* 000000000000XNZ0 */ + emit("or cl,al\n"); /* 000000000000XNZV */ + /* Read C */ + emit("mov ch,ah\n"); /* NZ?????C0000XNZV */ + emit("shl ch,8\n"); /* 000000000000XNZV carry */ + emit("adc cl,cl\n"); /* 00000000000XNZVC */ +} + +/* Read flags from our SR into CX. */ +static void sr2cx(void){ + /* Condition codes */ + ccr2cl(); + /* PPL / supervisor mode / trace flag */ + emit("mov ch,[ebp+__sr+1]\n"); +} + +/* Switch to supervisor mode. Can potentially destroy ECX. */ +static void supervisor(void){ + int myline=linenum;linenum++; + emit("test byte[ebp+__sr+1],20h\n"); + emit("jnz short ln%d\n",myline); + emit("mov ecx,[ebp+__a7]\n"); + emit("xchg ecx,[ebp+__asp]\n"); + emit("mov [ebp+__a7],ecx\n"); + copy_memory_map("s", "ecx"); + emit("or byte[ebp+__sr+1],20h\n"); + emit("ln%d:\n",myline); +} + +/***************************************************************************/ + +static void gen_readbw(int size){ + char z='x'; + if(size==1)z='b'; + if(size==2)z='w'; + + align(16); + emit("readmemory%s:\n",sizename[size]); + + emit("mov [ebp+__access_address],edx\n"); + maskaddress("edx"); + emit("mov ecx,[ebp+__read%s]\n",sizename[size]); + emit("read%c_check:\n",z); + emit("cmp edx,[ecx]\n"); /* Are we smaller? */ + emit("jb short read%c_next\n",z); /* Yes, go to next address */ + emit("cmp edx,[ecx+4]\n"); /* Are we bigger? */ + emit("jbe short read%c_call\n",z); + emit("read%c_next:\n",z); + emit("cmp dword[ecx],byte -1\n");/* End of list? */ + emit("je short read%c_outofrange\n",z); + emit("add ecx,byte 16\n"); /* To the next structure */ + emit("jmp short read%c_check\n",z); + + emit("read%c_outofrange:\n",z); + emit("or ecx,byte -1\n"); + emit("mov edx,[ebp+__access_address]\n"); + emit("ret\n"); + + emit("read%c_call:\n",z); + emit("cmp dword[ecx+8],byte 0\n"); + emit("jne short read%c_callio\n",z); + emit("sub edx,[ecx]\n"); + emit("add edx,[ecx+12]\n"); + if(size==1){ + emit("xor edx,byte 1\n"); + emit("mov cl,[edx]\n"); + }else{ + emit("mov cx,[edx]\n"); + } + emit("mov edx,[ebp+__access_address]\n"); + emit("ret\n"); + + emit("read%c_callio:\n",z); + airlock_exit(); + // edx=address + emit("mov eax,ecx\n"); // eax=pointer to structure (for my purposes) + emit("mov ecx,[ecx+12]\n"); // userdata + if(use_stack){ + emit("push edx\n"); + emit("push ecx\n"); + } + emit("call dword[eax+8]\n"); + if(use_stack)emit("add esp,byte 8\n"); + emit("mov ecx,eax\n"); + airlock_enter(); + emit("mov edx,[ebp+__access_address]\n"); + emit("ret\n"); +} + +static void gen_readl(void){ + align(16); + emit("readmemory%s:\n",sizename[4]); + emit("call readmemoryword\n"); + emit("shl ecx,16\n"); + emit("push ecx\n"); + emit("add edx,byte 2\n"); + emit("call readmemoryword\n"); + emit("sub edx,byte 2\n"); + emit("and ecx,0FFFFh\n"); + emit("or ecx,[esp]\n"); + emit("add esp,byte 4\n"); + emit("ret\n"); +} + +static void gen_writebw(int size){ + char z='x'; + if(size==1)z='b'; + if(size==2)z='w'; + + align(16); + emit("writememory%s:\n",sizename[size]); + + emit("mov [ebp+__access_address],edx\n"); + emit("push ecx\n"); + emit("write%c_top:\n",z); + maskaddress("edx"); + emit("mov ecx,[ebp+__write%s]\n",sizename[size]); + emit("write%c_check:\n",z); + emit("cmp edx,[ecx]\n"); /* Are we smaller? */ + emit("jb short write%c_next\n",z); /* Yes, go to next address */ + emit("cmp edx,[ecx+4]\n"); /* Are we bigger? */ + emit("jbe short write%c_call\n",z); + emit("write%c_next:\n",z); + emit("cmp dword[ecx],byte -1\n");/* End of list? */ + emit("je short write%c_end\n",z); + emit("add ecx,byte 16\n"); /* To the next structure */ + emit("jmp short write%c_check\n",z); + emit("write%c_call:\n",z); + emit("cmp dword[ecx+8],byte 0\n"); + emit("jne short write%c_callio\n",z); + emit("sub edx,[ecx]\n"); + emit("add edx,[ecx+12]\n"); + if(z=='b')emit("xor edx,byte 1\n"); + emit("pop ecx\n"); + emit("mov [edx],%s\n",x86cx[size]); + emit("mov edx,[ebp+__access_address]\n"); + emit("ret\n"); + + emit("write%c_callio:\n",z); + /* --- we have: + ** index in ecx + ** address in edx + ** value in [esp] + ** --- we want: + ** index in anything (saved first) + ** address in eax + ** value in edx + */ + airlock_exit(); + emit("mov ebx,ecx\n"); /* pointer to structure */ + emit("mov eax,edx\n"); /* address */ + emit("xor edx,edx\n"); /* data */ + emit("mov %s,[esp+%d]\n",x86dx[size],airlock_stacksize); + if(use_stack){ + emit("push edx\n"); + emit("push eax\n"); + emit("push dword[ebx+12]\n"); + } else { + emit("push edx\n"); + emit("mov edx,eax\n"); + emit("mov ecx,[ebx+12]\n"); + } + emit("call dword[ebx+8]\n"); + if(use_stack)emit("add esp,byte 12\n"); + airlock_enter(); + + emit("write%c_end:\n",z); + emit("pop ecx\n"); + emit("mov edx,[ebp+__access_address]\n"); + emit("ret\n"); +} + +static void gen_writel(void){ + align(16); + emit("writememory%s:\n",sizename[4]); + emit("push ecx\n"); + emit("shr ecx,16\n"); + emit("call writememoryword\n"); + emit("mov ecx,[esp]\n"); + emit("and ecx,0FFFFh\n"); + emit("add edx,byte 2\n"); + emit("call writememoryword\n"); + emit("sub edx,byte 2\n"); + emit("pop ecx\n"); + emit("ret\n"); +} + +/***************************************************************************/ +/* +** Group 1 and 2 exceptions +** Exception address is passed in EDX +** +** Does not fix the new PC! +*/ +static void gen_group_12_exception(void) { + emit("group_1_exception:\n"); + emit("group_2_exception:\n"); + emit("and byte[ebp+__interrupts],0FEh\n"); /* first thing's first */ + if(cputype == 68010) { + emit("mov byte[ebp+__loopmode],0\n"); + } + if(cputype >= 68010) { + emit("push edx\n"); + emit("add edx,[ebp+__vbr]\n"); + } + emit("call readmemorydword\n"); + if(cputype >= 68010) { + emit("pop edx\n"); + } + emit("push ecx\n");/* dest. PC */ + sr2cx(); + emit("push ecx\n");/* old SR */ + supervisor(); + /* + ** Exception handlers do not like being traced, so clear the SR trace + ** flag as well as the trace tricky bit. + ** + ** Leave the cycle leftover count alone, in case we still need to + ** call attention to other unrelated tricky bits. + */ + emit("and byte[ebp+__sr+1],27h\n"); + emit("mov byte[ebp+__trace_trickybit],0\n"); + + emit("mov ecx,esi\n"); + emit("sub ecx,[ebp+__io_fetchbase]\n"); + if(cputype >= 68010) { + emit("push ecx\n");/* old PC */ + emit("mov ecx,edx\n"); + } + emit("mov edx,[ebp+__a7]\n"); + if(cputype >= 68010) { + emit("and ecx,0FFCh\n");/* Format code */ + emit("sub edx,byte 2\n"); + emit("call writememoryword\n"); + emit("pop ecx\n"); + } + emit("sub edx,byte 4\n"); + emit("call writememorydword\n"); + emit("pop ecx\n");/* old SR */ + emit("sub edx,byte 2\n"); + emit("call writememoryword\n"); + emit("mov [ebp+__a7],edx\n"); + emit("pop esi\n");/* dest. PC */ + emit("ret\n"); +} + +/***************************************************************************/ + +/* Privilege violation */ +static void gen_privilege_violation(void){ + emit("privilege_violation:\n"); + emit("sub esi,byte 2\n"); + emit("mov edx,20h\n"); + emit("call group_1_exception\n"); + perform_cached_rebase(); + ret_timing((cputype==68010)?38:34); +} + +/***************************************************************************/ + +static void usereg(void) { + emit("and ebx,byte 7\n"); +} + +/* usereg only where applicable */ +static void selective_usereg(void) { + switch(main_eamode) { + case dreg: case areg: + case aind: case ainc: case adec: + case adsp: case axdp: + usereg(); + default: + ; + } +} + +static void selftest(int size) { + emit("test %s,%s\n", x86cx[size], x86cx[size]); +} + +/***************************************************************************/ + +/* Get condition: Less Than (N^V) +** If true, the x86 sign flag will be set */ +static void getcondition_l_s_ns(void) { + emit("push eax\n"); + emit("neg al\n"); + emit("xor al,ah\n"); + emit("pop eax\n"); +} + +/* Get condition: Less Than or Equal ((N^V)|Z) +** If true, the x86 sign flag will be set */ +static void getcondition_le_s_ns(void) { + emit("push eax\n"); + emit("neg al\n"); + emit("xor al,ah\n"); + emit("add ah,ah\n"); + emit("or al,ah\n"); + emit("pop eax\n"); +} + +static char optcc[5]; +static char optrc[5]; + +static void getcondition(int cc) { + switch(cc) { + case 0x0: + case 0x1: + break; + case 0x2:/* a */ + emit("test ah,41h\n"); + sprintf(optcc, "z"); + sprintf(optrc, "nz"); + break; + case 0x3:/* be */ + emit("test ah,41h\n"); + sprintf(optcc, "nz"); + sprintf(optrc, "z"); + break; + case 0x4:/* nc */ + emit("test ah,1\n"); + sprintf(optcc, "z"); + sprintf(optrc, "nz"); + break; + case 0x5:/* c */ + emit("test ah,1\n"); + sprintf(optcc, "nz"); + sprintf(optrc, "z"); + break; + case 0x6:/* ne */ + emit("test ah,40h\n"); + sprintf(optcc, "z"); + sprintf(optrc, "nz"); + break; + case 0x7:/* e */ + emit("test ah,40h\n"); + sprintf(optcc, "nz"); + sprintf(optrc, "z"); + break; + case 0x8:/* no */ + emit("test al,1\n"); + sprintf(optcc, "z"); + sprintf(optrc, "nz"); + break; + case 0x9:/* o */ + emit("test al,1\n"); + sprintf(optcc, "nz"); + sprintf(optrc, "z"); + break; + case 0xA:/* ns */ + emit("or ah,ah\n"); + sprintf(optcc, "ns"); + sprintf(optrc, "s"); + break; + case 0xB:/* s */ + emit("or ah,ah\n"); + sprintf(optcc, "s"); + sprintf(optrc, "ns"); + break; + case 0xC:/* ge */ + getcondition_l_s_ns(); + sprintf(optcc, "ns"); + sprintf(optrc, "s"); + break; + case 0xD:/* l */ + getcondition_l_s_ns(); + sprintf(optcc, "s"); + sprintf(optrc, "ns"); + break; + case 0xE:/* g */ + getcondition_le_s_ns(); + sprintf(optcc, "ns"); + sprintf(optrc, "s"); + break; + case 0xF:/* le */ + getcondition_le_s_ns(); + sprintf(optcc, "s"); + sprintf(optrc, "ns"); + break; + default:break; + } +} + +static void flags(void) { + emit("lahf\n"); + emit("seto al\n"); +} + +static void flags_v0(void) { + emit("lahf\n"); + emit("mov al,0\n"); +} + +/* Put one of the x86 flags into the 68K zero flag. */ +static void flag_to_z(char *f) { + int myline = linenum; linenum += 2; + emit("j%s short ln%d\n", f, myline); + emit("and ah,0BFh\n"); + emit("jmp short ln%d\n", myline + 1); + emit("ln%d:\n", myline); + emit("or ah,40h\n"); + emit("ln%d:\n", myline + 1); +} + +/* carry to X flag */ +static void c2x(void) { + emit("setc [ebp+__xflag]\n"); +} + +/* with previous flags in another register, adjust for non-changing zero */ +static void adjzero(char *reg) { + int myline = linenum; linenum++; + emit("jnz short ln%d\n", myline); + emit("or %s,0BFh\n", reg); + emit("and ah,%s\n", reg); + emit("ln%d:\n", myline); +} + +/* Check for privilege violation */ +static void privilegecheck(void) { + emit("test byte[ebp+__sr+1],20h\n"); + emit("jz near privilege_violation\n"); +} + +/**************************************************************************** +** EFFECTIVE ADDRESS GENERATION +****************************************************************************/ + +/* +** There are five types of EA activity: +** +** 1. Read: precalc -> read -> postcalc +** 2. Write: precalc -> write -> postcalc +** 3. R-M-W: precalc -> read -> (modify) -> write -> postcalc +** 4. Move: Read followed by Write +** 5. Control: precalc +*/ + +/* Calculate address */ +static void ea_step_precalc(int size, enum eamode mode, int reg) { + char regs[100]; + if(reg == -1) sprintf(regs, "ebx*4"); + else sprintf(regs, "%d", reg * 4); + switch(mode) { + case dreg: case areg: + break; + case aind: case ainc: case adec: + emit("mov edx,[ebp+__areg+%s]\n",regs); + if(mode == adec) { + /* Compensate for byte-sized stack ops */ + if(size == 1) { + if(reg == -1) { + emit("cmp bl,7\n"); + emit("adc edx,byte -2\n"); + } else if(reg == 7) { + emit("sub edx,byte 2\n"); + } else { + emit("dec edx\n"); + } + } else { + emit("sub edx,byte %d\n", size); + } + } + break; + case adsp: + emit("movsx edx,word[esi]\n"); + emit("add esi,byte 2\n"); + emit("add edx,[ebp+__areg+%s]\n", regs); + break; + case axdp: + emit("call decode_ext\n"); + emit("add edx,[ebp+__areg+%s]\n", regs); + break; + case absw: + emit("movsx edx,word[esi]\n"); + emit("add esi,byte 2\n"); + break; + case absl: + emit("mov edx,dword[esi]\n"); + emit("add esi,byte 4\n"); + emit("rol edx,16\n"); + break; + case pcdp: + emit("movsx edx,word[esi]\n"); + emit("add edx,esi\n"); + emit("sub edx,[ebp+__io_fetchbase]\n"); + emit("add esi,byte 2\n"); + break; + case pcxd: + emit("call decode_ext\n"); + emit("add edx,esi\n"); + emit("sub edx,[ebp+__io_fetchbase]\n"); + emit("sub edx,byte 2\n"); + break; + case immd: + break; + default: + emit("#error ea_step_precalc\n"); + break; + } +} + +static void ea_step_read(int size, enum eamode mode, int reg) { + char regs[100]; + if(reg == -1) sprintf(regs, "ebx*4"); + else sprintf(regs, "%d", reg * 4); + switch(mode) { + case dreg: emit("mov ecx,[ebp+__dreg+%s]\n", regs); break; + case areg: emit("mov ecx,[ebp+__areg+%s]\n", regs); break; + case aind: case ainc: case adec: + case adsp: case axdp: + case absw: case absl: + case pcdp: case pcxd: + emit("call readmemory%s\n", sizename[size]); + break; + case immd: + switch(size) { + case 1: + case 2: + emit("mov cx,[esi]\n"); + emit("add esi,byte 2\n"); + break; + case 4: + emit("mov ecx,[esi]\n"); + emit("add esi,byte 4\n"); + emit("rol ecx,16\n"); + break; + default: + emit("#error ea_step_read\n"); + break; + } + break; + default: + emit("#error ea_step_read\n"); + break; + } +} + +/* +** Special case for when you need to load a word and sign-extend it. +** This cuts some fat out of a few instructions (i.e. MOVEA). +*/ +static void ea_step_read_signword(enum eamode mode, int reg) { + char regs[100]; + if(reg == -1) sprintf(regs, "ebx*4"); + else sprintf(regs, "%d", reg * 4); + switch(mode) { + case dreg: emit("movsx ecx,word[ebp+__dreg+%s]\n", regs); break; + case areg: emit("movsx ecx,word[ebp+__areg+%s]\n", regs); break; + case aind: case ainc: case adec: + case adsp: case axdp: + case absw: case absl: + case pcdp: case pcxd: + emit("call readmemory%s\n", sizename[2]); + emit("movsx ecx,cx\n"); + break; + case immd: + emit("movsx ecx,word[esi]\n"); + emit("add esi,byte 2\n"); + break; + default: + emit("#error ea_step_read_signword\n"); + break; + } +} + +static void ea_step_write(int size, enum eamode mode, int reg) { + char regs[100]; + if(reg == -1) sprintf(regs, "ebx*4"); + else sprintf(regs, "%d", reg * 4); + switch(mode) { + case dreg: + emit("mov [ebp+__dreg+%s],%s\n", regs, x86cx[size]); + break; + case aind: case ainc: case adec: + case adsp: case axdp: + case absw: case absl: + emit("call writememory%s\n", sizename[size]); + break; + default: + emit("#error ea_step_write\n"); + break; + } +} + +static void ea_step_postcalc(int size, enum eamode mode, int reg) { + char regs[100]; + if(reg == -1) sprintf(regs, "ebx*4"); + else sprintf(regs, "%d", reg * 4); + switch(mode) { + case ainc: + /* Compensate for byte-sized stack ops */ + if(size == 1) { + if(reg == -1) { + emit("cmp bl,7\n"); + emit("sbb edx,byte -2\n"); + } else if(reg == 7) { + emit("add edx,byte 2\n"); + } else { + emit("inc edx\n"); + } + } else { + emit("add edx,byte %d\n", size); + } + /* Fall through */ + case adec: + /* Store already-predecremented address */ + emit("mov [ebp+__areg+%s],edx\n", regs); + break; + case dreg: case areg: + case aind: case adsp: case axdp: + case absw: case absl: + case pcdp: case pcxd: + case immd: + break; + default: + emit("#error ea_step_postcalc\n"); + break; + } +} + +/* Combined EA routines */ + +static void ea_load(int size, enum eamode mode, int reg) { + ea_step_precalc (size, mode, reg); + ea_step_read (size, mode, reg); + ea_step_postcalc(size, mode, reg); +} + +static void ea_load_signword(enum eamode mode, int reg) { + ea_step_precalc (2, mode, reg); + ea_step_read_signword( mode, reg); + ea_step_postcalc (2, mode, reg); +} + +static void ea_store(int size, enum eamode mode, int reg) { + ea_step_precalc (size, mode, reg); + ea_step_write (size, mode, reg); + ea_step_postcalc(size, mode, reg); +} + +static void ea_rmw_load(int size, enum eamode mode, int reg) { + ea_step_precalc (size, mode, reg); + ea_step_read (size, mode, reg); +} + +static void ea_rmw_store(int size, enum eamode mode, int reg) { + ea_step_write (size, mode, reg); + ea_step_postcalc(size, mode, reg); +} + +static void ea_control(enum eamode mode, int reg) { + ea_step_precalc (0, mode, reg); +} + +static void main_ea_load(void) { + ea_load(main_size, main_eamode, -1); +} + +static void main_ea_load_signed(void) { + if(main_size < 4) { + ea_load_signword(main_eamode, -1); + } else { + ea_load(main_size, main_eamode, -1); + } +} + +static void main_ea_store(void) { + ea_store(main_size, main_eamode, -1); +} + +static void main_ea_rmw_load(void) { + ea_rmw_load(main_size, main_eamode, -1); +} + +static void main_ea_rmw_store(void) { + ea_rmw_store(main_size, main_eamode, -1); +} + +static void main_ea_control(void) { + ea_control(main_eamode, -1); +} + +/***************************************************************************/ +/* +** Calculate cycles for main EA mode +** (68000, 68010) +*/ +static int main_ea_cycles(void) { + int l; + if(main_size == 4) l = 4; else l = 0; + switch(main_eamode) { + case aind: return(l + 4); + case ainc: return(l + 4); + case adec: return(l + 6); + case adsp: return(l + 8); + case axdp: return(l + 10); + case absw: return(l + 8); + case absl: return(l + 12); + case pcdp: return(l + 8); + case pcxd: return(l + 10); + case immd: return(l + 4); + default: break; + } + return 0; +} + +/* Calculate cycles for main EA mode, without fetching (68010 only) */ +static int main_ea_cycles_nofetch(void){ + switch(main_eamode) { + case aind: return(2); + case ainc: return(4); + case adec: return(4); + case adsp: return(4); + case axdp: return(8); + case absw: return(4); + case absl: return(8); + default: break; + } + return 0; +} + +/**************************************************************************** +** PREFIXES / SUFFIXES +****************************************************************************/ + +/* +** Prefixes - stuff that appears before the instruction handling routines +*/ +static void prefixes(void) { + /* Basic stuff - banner, variable section, API */ + gen_banner(); + gen_variables(); + gen_interface(); + /* Internal functions - PC rebasing, I/O, etc. */ + gen_basefunction(); + gen_decode_ext(); + gen_readbw(1); + gen_readbw(2); + gen_readl(); + gen_writebw(1); + gen_writebw(2); + gen_writel(); + gen_group_12_exception(); + gen_privilege_violation(); + gen_flush_interrupts(); +} + +/* +** Suffixes - stuff that appears after the instruction handling routines and +** the jump table / loop info table +*/ +static void suffixes(void) { + emit("end\n"); +} + +/**************************************************************************** +** INSTRUCTION HANDLING ROUTINES +****************************************************************************/ + +/* called 600 times (!) */ +static void i_move(void) { + int cycles; + selective_usereg(); + main_ea_load(); + ea_store(main_size, main_destmode, main_reg); + selftest(main_size); + flags_v0(); + cycles = 4 + main_ea_cycles(); + switch(main_destmode) { + case aind: if(main_size == 4) cycles += 4; cycles += 4; break; + case ainc: if(main_size == 4) cycles += 4; cycles += 4; break; + case adec: if(main_size == 4) cycles += 4; cycles += 4; break; + case adsp: if(main_size == 4) cycles += 4; cycles += 8; break; + case axdp: if(main_size == 4) cycles += 4; cycles += 10; break; + case absw: if(main_size == 4) cycles += 4; cycles += 8; break; + case absl: if(main_size == 4) cycles += 4; cycles += 12; break; + default: break; + } + /* Calculate loop mode timings */ + if(cputype == 68010) { + switch(main_eamode) { + case dreg: case areg: + switch(main_destmode) { + case aind: case ainc: + if(main_size <= 2) { + loop_c_cycles = 2; + loop_t_cycles = 10; + loop_x_cycles = 8; + }else{ + loop_c_cycles = 2; + loop_t_cycles = 8; + loop_x_cycles = 6; + } + break; + default:break; + } + break; + case aind: case ainc: case adec: + switch(main_destmode) { + case aind: case ainc: + loop_c_cycles = 2; + loop_t_cycles = 8; + loop_x_cycles = 6; + break; + case adec: + loop_c_cycles = 4; + loop_t_cycles = 10; + loop_x_cycles = 8; + break; + default:break; + } + break; + default:break; + } + } + ret_timing(cycles); +} + +static void i_moveq(void) { + emit("movsx ecx,bl\n"); + emit("mov [ebp+__dreg+%d],ecx\n", main_reg * 4); + selftest(1); + flags_v0(); + /* No loop mode */ + ret_timing(4); +} + +static void op_to_areg(char *s) { + selective_usereg(); + main_ea_load_signed(); /* sign extends to ecx where necessary */ + emit("%s [ebp+__areg+%d],ecx\n", s, main_reg * 4); +} + +static void i_movea(void) { + op_to_areg("mov"); + /* No loop mode */ + ret_timing(4 + main_ea_cycles()); +} + +/* ADDA or SUBA */ +static void addsuba(char *op) { + int base_cycles; + op_to_areg(op); + if(main_size==4){ + base_cycles=6; + /* Register direct / immediate penalty (68000) */ + if(cputype==68000){ + switch(main_eamode){ + case areg:case dreg:case immd: + base_cycles+=2; + break; + default:break; + } + } + }else{ + base_cycles=8; + } + /* Calculate loop mode timings */ + if(cputype==68010){ + switch(main_eamode){ + case aind:case ainc:case adec: + if(main_size<=2){ + loop_c_cycles = 6; + loop_t_cycles = 12; + loop_x_cycles = 10; + }else{ + loop_c_cycles = 8; + loop_t_cycles = 14; + loop_x_cycles = 12; + } + break; + default:break; + } + } + ret_timing(base_cycles+main_ea_cycles()); +} + +static void i_adda(void){addsuba("add");} +static void i_suba(void){addsuba("sub");} + +static void i_cmpa(void){ + op_to_areg("cmp"); + flags(); + /* Calculate loop mode timings */ + if(cputype==68010){ + switch(main_eamode){ + case aind:case ainc:case adec: + if(main_size<=2){ + loop_c_cycles = 2; + loop_t_cycles = 8; + loop_x_cycles = 6; + }else{ + loop_c_cycles = 4; + loop_t_cycles = 10; + loop_x_cycles = 6; + } + break; + default:break; + } + } + ret_timing(6+main_ea_cycles()); +} + +static void i_move_to_sr(void){ + main_size=2; + privilegecheck(); + selective_usereg(); + main_ea_load(); + cx2sr(); + /* No loop mode; check PPL and trace flag */ + ret_timing_checkpoint(12+main_ea_cycles()); +} + +static void i_move_to_ccr(void){ + main_size=2;/* WEIRD! But it works! */ + selective_usereg(); + main_ea_load(); + cl2ccr(); + /* No loop mode */ + ret_timing(12+main_ea_cycles()); +} + +static void i_move_from_sr(void){ + int cycles; + /* This is privileged on 68010 and up */ + if(cputype>=68010)privilegecheck(); + main_size=2; + selective_usereg(); + sr2cx(); + main_ea_store(); + if(cputype==68010){ + cycles=8+main_ea_cycles_nofetch(); + }else{ + cycles=8+main_ea_cycles(); + } + if((main_eamode==dreg)||(main_eamode==areg)){ + cycles-=2; + /* Speed demon 68010 can do it in 2 fewer cycles... :p */ + if(cputype==68010)cycles-=2; + } + /* No loop mode */ + ret_timing(cycles); +} + +/* 68000/68008 aren't supposed to have this */ +static void i_move_from_ccr(void){ + int cycles; + main_size=2; + selective_usereg(); + ccr2cl(); + main_ea_store(); + if(cputype==68010){ + cycles=8+main_ea_cycles_nofetch(); + }else{ + cycles=8+main_ea_cycles(); + } + if((main_eamode==dreg)||(main_eamode==areg)){ + cycles-=2; + if(cputype==68010)cycles-=2; + } + /* No loop mode */ + ret_timing(cycles); +} + +static void op_to_ccr(char*op){ + ccr2cl(); + emit("%s cl,[esi]\n",op); + emit("add esi,byte 2\n"); + cl2ccr(); + /* No loop mode */ + ret_timing((cputype==68010)?16:20); +} + +static void op_to_sr(char*op){ + privilegecheck(); + sr2cx(); + emit("%s cx,[esi]\n",op); + emit("add esi,byte 2\n"); + cx2sr(); + /* No loop mode */ + /* Check PPL and trace flag */ + ret_timing_checkpoint((cputype==68010)?16:20); +} + +static void i_ori_ccr(void){op_to_ccr("or" );} +static void i_andi_ccr(void){op_to_ccr("and");} +static void i_eori_ccr(void){op_to_ccr("xor");} +static void i_ori_sr (void){op_to_sr ("or" );} +static void i_andi_sr (void){op_to_sr ("and");} +static void i_eori_sr (void){op_to_sr ("xor");} + +static void i_clr(void){ + int cycles=0; + selective_usereg(); + emit("xor ecx,ecx\n"); + main_ea_store(); + if(cputype==68000){ + cycles=main_ea_cycles(); + if((main_eamode==dreg)||(main_eamode==areg)){ + cycles+=4;if(main_size==4)cycles+=4; + }else{ + cycles+=6;if(main_size==4)cycles+=6; + } + }else if(cputype==68010){ + switch(main_eamode){ + case dreg:cycles= 4;break; + case aind:cycles= 8;break; + case ainc:cycles= 8;break; + case adec:cycles=10;break; + case adsp:cycles=12;break; + case axdp:cycles=16;break; + case absw:cycles=12;break; + case absl:cycles=16;break; + default:break; + } + if(main_size==4){ + cycles+=4; + if(main_eamode==dreg)cycles-=2; + } + /* Calculate loop mode timings */ + switch(main_eamode){ + case aind:case ainc:case adec: + loop_c_cycles = 2; + loop_t_cycles = 10; + loop_x_cycles = 8; + break; + default:break; + } + } + emit("mov ax,4000h\n"); + ret_timing(cycles); +} + +static void i_tst(void){ + selective_usereg(); + main_ea_load(); + /* Calculate loop mode timings */ + if(cputype==68010){ + switch(main_eamode){ + case aind:case ainc:case adec: + if(main_size<=2){ + loop_c_cycles = 4; + loop_t_cycles = 10; + loop_x_cycles = 8; + }else{ + loop_c_cycles = 6; + loop_t_cycles = 12; + loop_x_cycles = 8; + } + break; + default:break; + } + } + selftest(main_size); + flags_v0(); + ret_timing(4+main_ea_cycles()); +} + +/* Always affects X flag +** (except for #,An which affects no flags whatsoever) */ +static void op_quick(char*op){ + int cycles; + selective_usereg(); + if(main_eamode==dreg){ + emit( + "%s %s[ebp+__dreg+ebx*4],byte %d\n", + op,sizename[main_size],quickvalue[main_qv] + ); + flags(); + c2x(); + cycles=4; + }else if(main_eamode==areg){ + emit( + "%s dword[ebp+__areg+ebx*4],byte %d\n", + op,quickvalue[main_qv] + ); + cycles=4; + /* SUBQ.W #,An incurs 4-cycle penalty (68000 only) */ + if(cputype==68000){ + if((main_size==2)&&(op[0]=='s'))cycles+=4; + } + }else{ + main_ea_rmw_load(); + emit( + "%s %s,byte %d\n",op,x86cx[main_size],quickvalue[main_qv] + ); + flags(); + c2x(); + main_ea_rmw_store(); + cycles=8+main_ea_cycles(); + } + if(main_size==4)cycles+=4; + /* No loop mode */ + ret_timing(cycles); +} + +static void i_addq(void){op_quick("add");} +static void i_subq(void){op_quick("sub");} + +static void op_to_dn(char*op,int affectx,int logical){ + int cycles; + selective_usereg(); + main_ea_load(); + emit("%s [ebp+__dreg+%d],%s\n", + op,main_reg*4,x86cx[main_size] + ); + if(logical){ + flags_v0(); + }else{ + flags(); + } + if(affectx)c2x(); + cycles=4+main_ea_cycles(); + if(main_size==4){ + cycles+=2; + /* Register direct / immediate penalty (68000) */ + if((cputype==68000)&&(op[0]!='c')){ + switch(main_eamode){ + case areg:case dreg:case immd: + cycles+=2; + break; + default:break; + } + } + } + /* Calculate loop mode timings */ + if(cputype==68010){ + switch(main_eamode){ + case aind:case ainc:case adec: + switch(op[0]){ + case 'a':/* ADD, AND */ + case 'o':/* OR */ + loop_c_cycles = 8; + loop_t_cycles = 14; + loop_x_cycles = 12; + break; + case 's':/* SUB */ + if(main_size<=2){ + loop_c_cycles = 8; + loop_t_cycles = 14; + loop_x_cycles = 12; + }else{ + loop_c_cycles = 6; + loop_t_cycles = 12; + loop_x_cycles = 10; + } + break; + case 'c':/* CMP */ + loop_c_cycles = 4; + loop_t_cycles = 10; + loop_x_cycles = 8; + if(main_size==4)loop_x_cycles = 6; + break; + default:break; + } + break; + default:break; + } + } + ret_timing(cycles); +} + +static void i_cmp_dn(void){op_to_dn("cmp",0,0);} +static void i_add_dn(void){op_to_dn("add",1,0);} +static void i_sub_dn(void){op_to_dn("sub",1,0);} +static void i_and_dn(void){op_to_dn("and",0,1);} +static void i_or_dn (void){op_to_dn("or" ,0,1);} + +static void op_to_ea(char*op,int logical){ + int cycles; + selective_usereg(); + main_ea_rmw_load(); + emit( + "%s %s,[ebp+__dreg+%d]\n", + op,x86cx[main_size],main_reg*4 + ); + if(logical){ + flags_v0(); + }else{ + flags(); + } + /* Logical instructions don't affect X flag */ + if(!logical)c2x(); + main_ea_rmw_store(); + cycles=8+main_ea_cycles(); + if(main_size==4)cycles+=4; + /* EOR Dn,Dn takes fewer cycles than we'd expect */ + if((op[0]=='x')&&(main_eamode==dreg)){ + cycles-=4; + if(cputype==68010)cycles-=2; + } + /* Calculate loop mode timings */ + if(cputype==68010){ + switch(main_eamode){ + case aind:case ainc:case adec: + loop_c_cycles = 4; + loop_t_cycles = 10; + loop_x_cycles = 8; + break; + default:break; + } + } + ret_timing(cycles); +} + +static void i_eor_ea(void){op_to_ea("xor",1);} +static void i_add_ea(void){op_to_ea("add",0);} +static void i_sub_ea(void){op_to_ea("sub",0);} +static void i_and_ea(void){op_to_ea("and",1);} +static void i_or_ea (void){op_to_ea("or" ,1);} + +/* called 144 times */ +/* +** c1: Total cycles for #,Dn (byte/word) +** c2: Total cycles for #,Dn (long) +** c3: Basic cycles for #,M (byte/word) +** c4: Basic cycles for #,M (long) +*/ +static void im_to_ea(char*op,int wback,int affectx,int logical, + int c1,int c2,int c3,int c4){ + int cycles; + selective_usereg(); + switch(main_size){ + case 1: + case 2: + emit("mov cx,[esi]\n"); + emit("add esi,byte 2\n"); + break; + case 4: + emit("mov ecx,[esi]\n"); + emit("rol ecx,16\n"); + emit("add esi,byte 4\n"); + break; + default:break; + } + if(main_eamode==dreg){ + emit("%s [ebp+__dreg+ebx*4],%s\n", + op,x86cx[main_size] + ); + if(logical){ + flags_v0(); + }else{ + flags(); + } + if(affectx)c2x(); + if(main_size<4)cycles=c1;else cycles=c2; + }else{ + emit("push ecx\n"); + if(wback)main_ea_rmw_load();else main_ea_load(); + emit("%s %s,[esp]\n",op,x86cx[main_size]); + if(logical){ + flags_v0(); + }else{ + flags(); + } + if(affectx)c2x(); + emit("add esp,byte 4\n"); + if(wback)main_ea_rmw_store(); + if(main_size<4)cycles=c3;else cycles=c4; + cycles+=main_ea_cycles(); + } + /* No loop mode */ + ret_timing(cycles); +} + +/* each called 24 times */ +static void i_addi(void){im_to_ea("add",1,1,0,8,(cputype==68010)?14:16,12,20);} +static void i_subi(void){im_to_ea("sub",1,1,0,8,(cputype==68010)?14:16,12,20);} +static void i_cmpi(void){im_to_ea("cmp",0,0,0,8,(cputype==68010)?12:14, 8,12);} +static void i_andi(void){im_to_ea("and",1,0,1,8,(cputype==68010)?14:14,12,20);} +static void i_ori (void){im_to_ea("or" ,1,0,1,8,(cputype==68010)?14:16,12,20);} +static void i_eori(void){im_to_ea("xor",1,0,1,8,(cputype==68010)?14:16,12,20);} + +static void flick_reg(char*op,int needxf,int affectx,int asl,int rotate){ + int cycles; + char tmps[5]; + int i; + usereg(); + cycles=6; + if(main_size==4)cycles+=2; + /* ASR doesn't need overflow checking */ + if(direction[main_dr]=='r')asl=0; + if(main_ir==1){ + int myline=linenum;linenum++; + emit("mov ecx,[ebp+__dreg+%d]\n",main_reg*4); + emit("and ecx,byte 63\n"); + emit("jnz short ln%d\n",myline); + /* The shift count was zero. Strange things are about to + ** happen... */ + ea_load(main_size,dreg,-1);/* get data in eax */ + selftest(main_size); + flags_v0(); + if(needxf){/* ROXL/ROXR: Set C flag equal to X */ + emit("and ah,0FEh\n"); + emit("or ah,[ebp+__xflag]\n"); + } + ret_timing(cycles); + /* Shift count non-zero */ + emit("ln%d:\n",myline); + emit("sub edi,ecx\n"); + emit("sub edi,ecx\n"); + sprintf(tmps,"cl"); + }else{ + sprintf(tmps,"%d",quickvalue[main_reg]); + cycles+=2*quickvalue[main_reg]; + } + if(asl){ + switch(tmps[0]){ + case 'c':/* register shift count */ + emit("mov edx,[ebp+__dreg+ebx*4]\n"); + emit("mov al,0\n");/* overflow starts at 0 */ + emit("ln%d:\n",linenum); + emit("add %s,%s\n", + x86dx[main_size],x86dx[main_size] + ); + emit("lahf\n");/* grab N,Z,C flags */ + emit("seto ch\n"); + emit("or al,ch\n");/* add overflow */ + emit("dec cl\n"); + emit("jnz short ln%d\n",linenum);linenum++; + emit("mov [ebp+__dreg+ebx*4],%s\n",x86dx[main_size]); + if(affectx){ + emit("mov cl,ah\n"); + emit("and cl,1\n"); + emit("mov [ebp+__xflag],cl\n"); + } + break; + case '1':/* immediate shift count ==1 */ + emit("sal %s[ebp+__dreg+ebx*4],1\n", + sizename[main_size] + ); + flags(); + if(affectx)c2x(); + break; + default:/* immediate shift count >1 */ + emit("mov edx,[ebp+__dreg+ebx*4]\n"); + emit("mov al,0\n");/* overflow starts at 0 */ + for(i='1';i<=tmps[0];i++){ + emit("add %s,%s\n", + x86dx[main_size],x86dx[main_size] + ); + if(i==tmps[0]){ + /* grab N,Z,C flags */ + emit("lahf\n"); + } + emit("seto ch\n"); + emit("or al,ch\n");/* add overflow */ + } + emit("mov [ebp+__dreg+ebx*4],%s\n",x86dx[main_size]); + if(affectx){ + emit("mov cl,ah\n"); + emit("and cl,1\n"); + emit("mov [ebp+__xflag],cl\n"); + } + break; + } + }else{ + if(rotate){ + emit("mov edx,[ebp+__dreg+ebx*4]\n"); + if(needxf){ + emit("mov al,[ebp+__xflag]\n"); + }else{ + emit("mov al,0\n"); + } + +/******** Stef Fix (Gens) *********/ + + switch(tmps[0]) + { + case 'c':/* register shift count */ + emit("cmp cl, 32\n"); + emit("jb short ln%d\n",linenum); + emit("sub cl, 31\n"); + if(needxf){ + emit("shr al, 1\n"); + } + emit("%s%c %s, 31\n", op,direction[main_dr],x86dx[main_size]); + emit("%s%c %s,%s\n", op,direction[main_dr],x86dx[main_size],tmps); + emit("jmp short ln%d\n",linenum + 1); + emit("ln%d:\n",linenum); linenum++; + if(needxf){ + emit("shr al, 1\n"); + } + emit("%s%c %s,%s\n", op,direction[main_dr],x86dx[main_size],tmps); + emit("ln%d:\n",linenum); linenum++; + break; + + default:/* immediate shift count >1 */ + if(needxf){ + emit("shr al,1\n"); + } + emit("%s%c %s,%s\n", op,direction[main_dr],x86dx[main_size],tmps); + break; + } + +/******** End Fix *********/ + + emit("adc al,al\n"); + emit("or %s,%s\n", + x86dx[main_size],x86dx[main_size] + ); + emit("lahf\n"); + emit("or ah,al\n"); + if(affectx){ + emit("mov [ebp+__xflag],al\n"); + } + emit("mov al,0\n"); + emit("mov [ebp+__dreg+ebx*4],%s\n",x86dx[main_size]); + }else{ + if(needxf){ + emit("mov al,[ebp+__xflag]\n"); + }else{ + emit("mov al,0\n"); + } + +/******** Stef Fix (Gens) *********/ + + switch(tmps[0]) + { + case 'c':/* register shift count */ + emit("cmp cl, 32\n"); + emit("jb short ln%d\n",linenum); + emit("sub cl, 31\n"); + if(needxf){ + emit("shr al, 1\n"); + } + emit("%s%c %s[ebp+__dreg+ebx*4], 31\n", op,direction[main_dr],sizename[main_size]); + emit("jmp short ln%d\n",linenum + 1); + emit("ln%d:\n",linenum); linenum++; + if(needxf){ + emit("shr al, 1\n"); + } + emit("%s%c %s[ebp+__dreg+ebx*4],%s\n", op,direction[main_dr],sizename[main_size],tmps); + emit("ln%d:\n",linenum); linenum++; + break; + + default:/* immediate shift count >1 */ + if(needxf){ + emit("shr al, 1\n"); + } + emit("%s%c %s[ebp+__dreg+ebx*4],%s\n", op,direction[main_dr],sizename[main_size],tmps); + break; + } + +/******** End Fix *********/ + + emit("lahf\n"); + if(affectx)c2x(); + } + } + /* No loop mode */ + ret_timing(cycles); +} + +static void i_lsx_reg(void){flick_reg("sh",0,1,0,0);} +static void i_asx_reg(void){flick_reg("sa",0,1,1,0);} +static void i_rox_reg(void){flick_reg("ro",0,0,0,1);} +static void i_rxx_reg(void){flick_reg("rc",1,1,0,1);} + +static void flick_mem(char*op,int needxf,int affectx,int vf,int rotate){ + /* ASR doesn't need overflow checking */ + if(direction[main_dr]=='r')vf=0; + main_size=2; + selective_usereg(); + main_ea_rmw_load(); + if(needxf){ + emit("mov al,[ebp+__xflag]\n"); + emit("shr al,1\n"); + }else{ + if(rotate)emit("mov al,0\n"); + } + emit("%s%c cx,1\n",op,direction[main_dr]); + if(rotate){ + emit("adc al,al\n"); + emit("test cx,cx\n"); + emit("lahf\n"); + emit("or ah,al\n"); + if(affectx)emit("mov [ebp+__xflag],al\n"); + emit("mov al,0\n"); + }else{ + if(vf){ + flags(); + }else{ + flags_v0(); + } + if(affectx)c2x(); + } + main_ea_rmw_store(); + /* Calculate loop mode timings */ + if(cputype==68010){ + switch(main_eamode){ + case aind:case ainc:case adec: + loop_c_cycles = 6; + loop_t_cycles = 12; + loop_x_cycles = 10; + break; + default:break; + } + } + ret_timing(8+main_ea_cycles()); +} + +static void i_lsx_mem(void){flick_mem("sh",0,1,0,0);} +static void i_asx_mem(void){flick_mem("sa",0,1,1,0);} +static void i_rox_mem(void){flick_mem("ro",0,0,0,1);} +static void i_rxx_mem(void){flick_mem("rc",1,1,0,1);} + +static int created_bra_b=0; +static void i_bra_b(void){ + if(!created_bra_b){emit("r_bra_b:\n");created_bra_b=1;} + emit("movsx ebx,bl\n"); + emit("add esi,ebx\n"); + emit("xor ebx,ebx\n"); + ret_timing(10); +} + +static int created_bra_w=0; +static void i_bra_w(void){ + if(!created_bra_w){emit("r_bra_w:\n");created_bra_w=1;} + emit("movsx ebx,word[esi]\n"); + emit("add esi,ebx\n"); + emit("xor ebx,ebx\n"); + ret_timing(10); +} + +static void i_bsr_b(void){ + emit("movsx ebx,bl\n"); + emit("mov ecx,esi\n"); + emit("sub ecx,[ebp+__io_fetchbase]\n"); + emit("add esi,ebx\n"); + emit("xor ebx,ebx\n"); + ea_store(4,adec,7); + ret_timing(18); +} + +static void i_bsr_w(void){ + emit("movsx ebx,word[esi]\n"); + emit("mov ecx,esi\n"); + emit("add ecx,byte 2\n"); + emit("sub ecx,[ebp+__io_fetchbase]\n"); + emit("add esi,ebx\n"); + emit("xor ebx,ebx\n"); + ea_store(4,adec,7); + ret_timing(18); +} + +static void i_bcc_b(void){ + getcondition(main_cc); + emit("j%s near r_bra_b\n",optcc); + ret_timing((cputype==68010)?6:8); +} + +static void i_bcc_w(void){ + getcondition(main_cc); + emit("j%s near r_bra_w\n",optcc); + emit("add esi,byte 2\n");/* skip relative offset */ + ret_timing(12); +} + +/* called once */ +static void i_dbra(void){ + emit("r_dbra:\n"); + usereg(); + if(cputype==68010){ + emit("movsx ecx,word[esi]\n"); + emit("cmp ecx,byte -4\n"); + emit("je short r_loopmode_dbra\n"); + + /* Regular DBRA */ + emit("r_regular_dbra:\n"); + emit("sub word[ebp+__dreg+ebx*4],byte 1\n"); + emit("jc short r_dbra_expire\n"); + emit("add esi,ecx\n"); + ret_timing(10); + emit("r_dbra_expire:\n"); + emit("add esi,byte 2\n"); + ret_timing(16); + + /* Loop mode DBRA */ + emit("r_loopmode_dbra:\n"); + emit("cmp byte[ebp+__loopmode],0\n"); + emit("jnz short r_loopmode_dbra_inloop\n"); + emit("mov byte[ebp+__loopmode],1\n"); + emit("jmp short r_regular_dbra\n"); + emit("r_loopmode_dbra_inloop:\n"); + emit("sub word[ebp+__dreg+ebx*4],byte 1\n"); + emit("jc short r_loopmode_dbra_expire\n"); + + /* Continue */ + emit("mov bx,word[esi-4]\n"); + emit("add esi,ecx\n"); + /* Subtract continuation cycles */ + emit("mov cl,byte[_looptbl+ebx]\n"); + emit("and ecx,byte 0Eh\n"); + emit("sub edi,ecx\n"); + ret_timing(0); + + /* Expire */ + emit("r_loopmode_dbra_expire:\n"); + emit("mov bx,word[esi-4]\n"); + emit("mov byte[ebp+__loopmode],0\n"); + /* Subtract continuation and extra expiration cycles */ + emit("mov cl,byte[_looptbl+ebx]\n"); + emit("mov ebx,ecx\n"); + emit("rol cl,2\n"); + emit("add esi,byte 2\n"); + emit("and ebx,byte 0Eh\n"); + emit("and ecx,byte 06h\n"); + emit("sub edi,ebx\n"); + emit("sub edi,ecx\n"); + ret_timing(0); + + /* Terminate (visited externally by i_dbcc) */ + emit("r_dbra_terminate:\n"); + emit("cmp word[esi],byte -4\n"); + emit("jne short r_dbra_terminate_regular\n"); + emit("cmp byte[ebp+__loopmode],0\n"); + emit("je short r_dbra_terminate_regular\n"); + emit("mov bx,word[esi-4]\n"); + emit("mov byte[ebp+__loopmode],0\n"); + /* Subtract termination cycles */ + emit("mov cl,byte[_looptbl+ebx]\n"); + emit("shr cl,3\n"); + emit("add esi,byte 2\n"); + emit("and ecx,byte 0Eh\n"); + emit("sub edi,ecx\n"); + ret_timing(0); + emit("r_dbra_terminate_regular:\n"); + ret_timing(10); + }else{ + emit("sub word[ebp+__dreg+ebx*4],byte 1\n"); + emit("jnc near r_bra_w\n"); + emit("add esi,byte 2\n"); + ret_timing(14); + } +} + +static void i_dbcc(void){ + getcondition(main_cc); + emit("j%s near r_dbra\n",optrc); + /* Terminate */ + if(cputype==68010){ + emit("jmp r_dbra_terminate\n"); + }else{ + emit("add esi,byte 2\n"); + ret_timing(12); + } +} + +static void i_scc(void){ + int cycles; + main_size=1; + selective_usereg(); + if(main_cc>1){ + if((main_eamode==dreg)||(main_eamode==areg)){ + if(cputype==68000){ + emit("xor ecx,ecx\n"); + } + getcondition(main_cc); + emit("set%s cl\n",optcc); + if(cputype==68000){ + /* 2 extra cycles if it's true */ + emit("sub edi,ecx\n"); + emit("sub edi,ecx\n"); + } + emit("neg cl\n"); + cycles=4; + }else{ + getcondition(main_cc); + emit("set%s cl\n",optcc); + emit("neg cl\n"); + cycles=8; + } + }else{ + emit("mov cl,%d\n",(main_cc^1)*0xFF); + if((main_eamode==dreg)||(main_eamode==areg)){ + cycles=4; + if(cputype==68000){ + /* 2 extra cycles if it's true */ + if(!main_cc)cycles+=2; + } + }else{ + cycles=8; + } + } + main_ea_store(); + if(cputype==68010){ + cycles+=main_ea_cycles_nofetch(); + }else{ + cycles+=main_ea_cycles(); + } + /* No loop mode */ + ret_timing(cycles); +} + +/* bit operations */ + +/* called 315 times */ +/* 0=btst,1=bchg,2=bclr,3=bset */ +static void bitop(int static_cycles){ + int cycles; + selective_usereg(); + emit("and ecx,byte %d\n",(main_eamode==dreg)?31:7); + if(main_eamode==dreg){ + main_size=4; + if(!main_cc){/* BTST */ + emit("mov edx,1\n"); + emit("shl edx,cl\n"); + emit("test [ebp+__dreg+ebx*4],edx\n"); + flag_to_z("z"); + }else{ + emit("mov edx,1\n"); + emit("shl edx,cl\n"); + emit("mov ecx,[ebp+__dreg+ebx*4]\n"); + emit("test ecx,edx\n"); + flag_to_z("z"); + switch(main_cc){ + case 1:emit("xor ecx,edx\n");break; + case 2:emit("not edx\nand ecx,edx\n");break; + case 3:emit("or ecx,edx\n");break; + default:break; + } + emit("mov [ebp+__dreg+ebx*4],ecx\n"); + } + cycles=6+static_cycles; + if(main_cc)cycles+=2; + if(main_cc==2)cycles+=2; + }else{ + main_size=1; + if(!main_cc){ + emit("push ecx\n"); + main_ea_load(); + emit("mov edx,ecx\n"); + emit("pop ecx\n"); + emit("inc cl\n"); + emit("shr dl,cl\n"); + flag_to_z("nc"); + }else{ + emit("mov dl,1\n"); + emit("shl dl,cl\n"); + emit("push edx\n"); + main_ea_rmw_load(); + emit("xchg edx,[esp]\n"); + emit("test cl,dl\n"); + flag_to_z("z"); + switch(main_cc){ + case 1:emit("xor cl,dl\n");break; + case 2:emit("not dl\nand cl,dl\n");break; + case 3:emit("or cl,dl\n");break; + default:break; + } + emit("pop edx\n"); + main_ea_rmw_store(); + } + cycles=4+static_cycles+main_ea_cycles(); + if(main_cc)cycles+=4; + if((cputype==68010)&&(main_cc==2))cycles+=2; + } + ret_timing(cycles); +} + +/* called 35 times */ +static void i_bitop_imm(void){ + emit("mov cl,[esi]\n"); + emit("add esi,byte 2\n"); + bitop(4); +} + +/* called 280 times */ +static void i_bitop_reg(void){ + emit("mov cl,byte[ebp+__dreg+%d]\n",main_reg*4); + bitop(0); +} + +static void i_jmp(void){ + int cycles=0; + selective_usereg(); + main_ea_control(); + emit("mov esi,edx\n"); + perform_cached_rebase(); + switch(main_eamode){ + case aind:cycles= 8;break; + case adsp:cycles=10;break; + case axdp:cycles=14;break; + case absw:cycles=10;break; + case absl:cycles=12;break; + case pcdp:cycles=10;break; + case pcxd:cycles=14;break; + default:break; + } + /* No loop mode */ + ret_timing(cycles); +} + +static void i_jsr(void){ + int cycles=0; + selective_usereg(); + main_ea_control(); + emit("mov ecx,esi\n"); + emit("sub ecx,[ebp+__io_fetchbase]\n"); + emit("mov esi,edx\n"); + perform_cached_rebase(); + ea_store(4,adec,7); + switch(main_eamode){ + case aind:cycles=16;break; + case adsp:cycles=18;break; + case axdp:cycles=22;break; + case absw:cycles=18;break; + case absl:cycles=20;break; + case pcdp:cycles=18;break; + case pcxd:cycles=22;break; + default:break; + } + /* No loop mode */ + ret_timing(cycles); +} + +static void i_rts(void){ + ea_load(4,ainc,7); + emit("mov esi,ecx\n"); + perform_cached_rebase(); + /* No loop mode */ + ret_timing(16); +} + +/* 68010 and higher */ +static void i_rtd(void){ + emit("mov edx,[ebp+__a7]\n"); + emit("call readmemorydword\n"); + emit("movsx ebx,word[esi]\n"); + emit("add edx,ebx\n"); + emit("mov esi,ecx\n"); + emit("add edx,byte 4\n"); + emit("xor ebx,ebx\n"); + emit("mov [ebp+__a7],edx\n"); + perform_cached_rebase(); + /* No loop mode */ + ret_timing(16); +} + +static void i_rtr(void){ + ea_load(2,ainc,7); + cl2ccr(); + ea_load(4,ainc,7); + emit("mov esi,ecx\n"); + perform_cached_rebase(); + /* No loop mode */ + ret_timing(20); +} + +static void i_rte(void){ + int myline=linenum; + linenum++; + privilegecheck(); + if(cputype>=68010){ + /* Check stack frame format - must be 0xxx or 8xxx */ + emit("mov edx,[ebp+__a7]\n"); + emit("add edx,byte 6\n"); + emit("call readmemory%s\n",sizename[2]); + emit("test ch,70h\n"); + emit("jnz short ln%d_formatok\n",myline); + /* Generate Format Error exception where necessary */ + emit("mov edx,38h\n"); + emit("call group_1_exception\n"); + perform_cached_rebase(); + ret_timing(50);/* RTE, Illegal Format */ + emit("ln%d_formatok:\n",myline); + + /* Now _we_ check to make sure the format isn't 8xxx (since + ** that's not implemented yet). */ + emit("or ch,ch\n"); + emit("jns short ln%d_formatok2\n",myline); + /* Double fault with error code 80000002h. */ + emit("mov ecx,80000002h\n"); + emit("or byte[ebp+__pc],1\n"); + emit("or byte[ebp+__interrupts],1\n"); + emit("jmp execexit\n"); + emit("ln%d_formatok2:\n",myline); + + /* Now RTE as usual */ + emit("sub edx,byte 6\n"); + emit("call readmemory%s\n",sizename[2]); + emit("add edx,byte 2\n"); + cx2sr(); + emit("test ch,20h\n"); + emit("jz short ln%d_nosupe\n",myline); + emit("add dword [ebp+__a7],byte 8\n"); + emit("jmp short ln%d_finish\n",myline); + emit("ln%d_nosupe:\n",myline); + emit("add dword [ebp+__asp],byte 8\n"); + emit("ln%d_finish:\n",myline); + emit("call readmemory%s\n",sizename[4]); + emit("mov esi,ecx\n"); + perform_cached_rebase(); + ret_timing_checkpoint(24);/* RTE with no trouble */ + }else{ + emit("mov edx,[ebp+__a7]\n"); + emit("call readmemory%s\n",sizename[2]); + emit("add edx,byte 2\n"); + cx2sr(); + emit("test ch,20h\n"); + emit("jz short ln%d_nosupe\n",myline); + emit("add dword [ebp+__a7],byte 6\n"); + emit("jmp short ln%d_finish\n",myline); + emit("ln%d_nosupe:\n",myline); + emit("add dword [ebp+__asp],byte 6\n"); + emit("ln%d_finish:\n",myline); + emit("call readmemory%s\n",sizename[4]); + emit("mov esi,ecx\n"); + perform_cached_rebase(); + ret_timing_checkpoint(20); + } +} + +static void i_lea(void){ + int cycles=0; + selective_usereg(); + main_ea_control(); + emit("mov [ebp+__areg+%d],edx\n",main_reg*4); + switch(main_eamode){ + case aind:cycles= 4;break; + case adsp:cycles= 8;break; + case axdp:cycles=12;break; + case absw:cycles= 8;break; + case absl:cycles=12;break; + case pcdp:cycles= 8;break; + case pcxd:cycles=12;break; + default:break; + } + /* No loop mode */ + ret_timing(cycles); +} + +static void i_pea(void){ + int cycles=0; + selective_usereg(); + main_ea_control(); + emit("mov ecx,edx\n"); + ea_store(4,adec,7); + switch(main_eamode){ + case aind:cycles=12;break; + case adsp:cycles=16;break; + case axdp:cycles=20;break; + case absw:cycles=16;break; + case absl:cycles=20;break; + case pcdp:cycles=16;break; + case pcxd:cycles=20;break; + default:break; + } + /* No loop mode */ + ret_timing(cycles); +} + +static void i_nop(void){ + /* No loop mode */ + ret_timing(4); +} + +static void i_movem_control(void){ + int cycles=0; + int myline=linenum;linenum+=2; + emit("push eax\n"); + selective_usereg(); + emit("mov ax,[esi]\n"); + emit("add esi,byte 2\n"); + main_ea_control(); + emit("xor ebx,ebx\n"); + emit("ln%d:\n",myline); + emit("shr eax,1\n"); + emit("jnc short ln%d\n",myline+1); + if(main_dr==0){/*register->memory*/ + switch(main_eamode){ + case aind:cycles= 8;break; + case adsp:cycles=12;break; + case axdp:cycles=14;break; + case absw:cycles=12;break; + case absl:cycles=16;break; + default:break; + } + emit("mov ecx,[ebp+__reg+ebx]\n"); + emit("call writememory%s\n",sizename[main_size]); + }else{/*memory->register*/ + switch(main_eamode){ + case aind:cycles=12; + if((cputype==68010)&&(main_size==4))cycles=24; + break; + case adsp:cycles=16;break; + case axdp:cycles=18;break; + case absw:cycles=16;break; + case absl:cycles=20;break; + case pcdp:cycles=16;break; + case pcxd:cycles=18;break; + default:break; + } + emit("call readmemory%s\n",sizename[main_size]); + if(main_size==2)emit("movsx ecx,cx\n"); + emit("mov [ebp+__reg+ebx],ecx\n"); + } + emit("add edx,byte %d\n",main_size); + emit("sub edi,byte %d\n",main_size*2); + emit("ln%d:\n",myline+1); + emit("add ebx,byte 4\n"); + emit("cmp ebx,byte 64\n"); + emit("jne short ln%d\n",myline); + emit("pop eax\n"); + ret_timing(cycles); +} + +static void i_movem_postinc(void){ + int myline=linenum;linenum+=2; + usereg(); + emit("push eax\n"); + emit("mov ax,[esi]\n"); + emit("add esi,byte 2\n"); + emit("mov edx,[ebp+__areg+ebx*4]\n"); + emit("push ebx\n"); + emit("xor ebx,ebx\n"); + emit("ln%d:\n",myline); + emit("shr eax,1\n"); + emit("jnc short ln%d\n",myline+1); + emit("call readmemory%s\n",sizename[main_size]); + if(main_size==2)emit("movsx ecx,cx\n"); + emit("mov [ebp+__reg+ebx],ecx\n"); + emit("add edx,byte %d\n",main_size); + emit("sub edi,byte %d\n",main_size*2); + emit("ln%d:\n",myline+1); + emit("add ebx,byte 4\n"); + emit("cmp ebx,byte 64\n"); + emit("jne short ln%d\n",myline); + emit("pop ebx\n"); + emit("pop eax\n"); + emit("mov [ebp+__areg+ebx*4],edx\n"); + ret_timing(12); +} + +static void i_movem_predec(void){ + int myline=linenum;linenum+=2; + usereg(); + emit("push eax\n"); + emit("mov ax,[esi]\n"); + emit("add esi,byte 2\n"); + emit("mov edx,[ebp+__areg+ebx*4]\n"); + emit("push ebx\n"); + emit("mov ebx,60\n"); + emit("ln%d:\n",myline); + emit("shr eax,1\n"); + emit("jnc short ln%d\n",myline+1); + emit("mov ecx,[ebp+__reg+ebx]\n"); + emit("sub edx,byte %d\n",main_size); + emit("sub edi,byte %d\n",main_size*2); + emit("call writememory%s\n",sizename[main_size]); + emit("ln%d:\n",myline+1); + emit("sub ebx,byte 4\n"); + emit("jns short ln%d\n",myline); + emit("pop ebx\n"); + emit("pop eax\n"); + emit("mov [ebp+__areg+ebx*4],edx\n"); + ret_timing(8); +} + +static void i_link(void){ + usereg(); + emit("mov ecx,[ebp+__areg+ebx*4]\n"); + ea_store(4,adec,7); + emit("mov ecx,[ebp+__a7]\n"); + emit("mov [ebp+__areg+ebx*4],ecx\n"); + emit("movsx edx,word[esi]\n"); + emit("add ecx,edx\n"); + emit("mov [ebp+__a7],ecx\n"); + emit("add esi,byte 2\n"); + ret_timing(16); +} + +static void i_unlk(void){ + usereg(); + emit("mov ecx,[ebp+__areg+ebx*4]\n"); + emit("mov [ebp+__a7],ecx\n"); + ea_load(4,ainc,7); + emit("mov [ebp+__areg+ebx*4],ecx\n"); + ret_timing(12); +} + +static void i_move_from_usp(void){ + privilegecheck(); /* makes our job much easier... */ + usereg(); + emit("mov ecx,[ebp+__asp]\n"); + emit("mov [ebp+__areg+ebx*4],ecx\n"); + ret_timing((cputype==68010)?6:4); +} + +static void i_move_to_usp(void){ + privilegecheck(); + usereg(); + emit("mov ecx,[ebp+__areg+ebx*4]\n"); + emit("mov [ebp+__asp],ecx\n"); + ret_timing((cputype==68010)?6:4); +} + +static void i_trap(void){ + emit("and ebx,byte 0Fh\n"); + emit("lea edx,[80h+ebx*4]\n"); + emit("call group_2_exception\n"); + perform_cached_rebase(); + ret_timing((cputype==68010)?38:34); +} + +static void i_trapv(void){ + int myline=linenum;linenum++; + emit("test al,1\n"); + emit("jnz short ln%d\n",myline); + ret_timing(4); + emit("ln%d:\n",myline); + emit("mov edx,1Ch\n"); + emit("call group_2_exception\n"); + perform_cached_rebase(); + ret_timing(4+((cputype==68010)?38:34)); +} + +static void i_stop(void){ + int myline=linenum;linenum++; + privilegecheck(); + emit("mov cx,[esi]\n"); + emit("add esi,2\n"); + cx2sr(); + emit("or byte[ebp+__interrupts],1\n"); + /* Forfeit all remaining cycles */ + emit("sub edi,byte 4\n"); + emit("js short ln%d\n",myline); + emit("xor edi,edi\n"); + emit("dec edi\n"); + emit("ln%d:\n",myline); + ret_timing(0); +} + +static void i_extbw(void){ + usereg(); + emit("movsx cx,byte[ebp+__dreg+ebx*4]\n"); + emit("mov [ebp+__dreg+ebx*4],cx\n"); + selftest(2); + flags_v0(); + ret_timing(4); +} + +static void i_extwl(void){ + usereg(); + emit("movsx ecx,word[ebp+__dreg+ebx*4]\n"); + emit("mov [ebp+__dreg+ebx*4],ecx\n"); + selftest(4); + flags_v0(); + ret_timing(4); +} + +static void i_swap(void){ + usereg(); + emit("mov ecx,[ebp+__dreg+ebx*4]\n"); + emit("rol ecx,16\n"); + emit("mov [ebp+__dreg+ebx*4],ecx\n"); + selftest(4); + flags_v0(); + ret_timing(4); +} + +/* if main_cc==1 then it's signed */ +static void i_mul(void){ + int base_cycles; + selective_usereg(); + main_size=2; + main_ea_load(); + emit("mov eax,ecx\n"); + /* Finally! Real MULS/MULU timing! */ + if(cputype==68000){ + emit("mov dl,0\n"); + emit("mov bl,16\n"); + emit("ln%d:\n",linenum); + emit("add cx,cx\n"); + if(main_cc==1){ + /* MULS: count the number of 10 or 01 pairs */ + emit("seto dh\n"); + emit("add dl,dh\n"); + }else{ + /* MULU: count the number of 1s */ + emit("adc dl,0\n"); + } + emit("dec bl\n"); + emit("jnz ln%d\n",linenum);linenum++; + emit("and edx,byte 127\n"); + emit("sub edi,edx\n"); + emit("sub edi,edx\n"); + } + emit("%smul word[ebp+__dreg+%d]\n", + (main_cc==1)?"i":"",main_reg*4 + ); + emit("shl edx,16\n"); + emit("and eax,0FFFFh\n"); + emit("mov ecx,edx\n"); + emit("or ecx,eax\n"); + flags_v0(); + emit("mov [ebp+__dreg+%d],ecx\n",main_reg*4); + if(cputype==68010){ + /* Maximum is 42 signed, 40 unsigned */ + base_cycles=36; + if(main_cc)base_cycles+=2; + }else{ + /* 38+2n, signed or unsigned, maximum is 70 */ + base_cycles=38; + } + /* No loop mode */ + ret_timing(base_cycles+main_ea_cycles()); +} + +/* if main_cc=1 then it's signed */ +static void i_div(void){ + int base_cycles; + int myline=linenum;linenum+=2; + selective_usereg(); + main_size=2; + main_ea_load(); + emit("test cx,cx\n"); + emit("jnz short ln%d\n",myline); + /* Forgot to put on our Division by Zero Suit... */ + emit("mov edx,14h\n"); + emit("call group_2_exception\n"); + perform_cached_rebase(); + base_cycles=38; + if(cputype==68010)base_cycles+=4; + ret_timing(base_cycles+main_ea_cycles()); + emit("ln%d:\n",myline);myline++; + if(main_cc){ + emit("movsx ecx,cx\n"); + }else{ + emit("and ecx,0FFFFh\n"); + } + emit("mov eax,[ebp+__dreg+%d]\n",main_reg*4); + if(main_cc){ + emit("mov edx,eax\n"); + emit("sar edx,31\n"); + }else{ + emit("xor edx,edx\n"); + } + emit("%sdiv ecx\n",main_cc?"i":""); + if(main_cc){ + emit("mov ecx,eax\n"); + emit("sar cx,15\n"); + emit("or ecx,ecx\n"); + emit("je short ln%d\n",linenum); + emit("inc ecx\n"); + emit("jne short ln%d\n",myline); + emit("ln%d:\n",linenum);linenum++; + emit("and eax,0FFFFh\n"); + }else{ + emit("test eax,0FFFF0000h\n"); + emit("jnz short ln%d\n",myline); + } + emit("shl edx,16\n"); + emit("mov dx,ax\n"); + emit("test dx,dx\n"); + flags_v0(); + emit("mov [ebp+__dreg+%d],edx\n",main_reg*4); + if(cputype==68010){ + base_cycles=108; + if(main_cc)base_cycles=122; + }else{ + /* Varies from 142-158 signed, 126-140 unsigned */ + base_cycles=133; + if(main_cc)base_cycles=150; + } + ret_timing(base_cycles+main_ea_cycles()); + /* Overflow */ + emit("ln%d:\n",myline);myline++; + emit("mov ax,1\n"); + /* No loop mode */ + ret_timing(base_cycles+main_ea_cycles()); +} + +static void i_neg(void){ + int cycles; + selective_usereg(); + cycles=4; + if(main_size==4)cycles=6; + if(main_eamode==dreg){ + emit("neg %s[ebp+__dreg+ebx*4]\n", + sizename[main_size] + ); + flags(); + c2x(); + }else{ + cycles*=2; + main_ea_rmw_load(); + emit("neg %s\n",x86cx[main_size]); + flags(); + c2x(); + main_ea_rmw_store(); + cycles+=main_ea_cycles(); + } + /* Calculate loop mode timings */ + if(cputype==68010){ + switch(main_eamode){ + case aind:case ainc:case adec: + loop_c_cycles = 4; + loop_t_cycles = 10; + loop_x_cycles = 8; + break; + default:break; + } + } + ret_timing(cycles); +} + +static void i_negx(void){ + int cycles; + selective_usereg(); + cycles=4; + if(main_size==4)cycles=6; + if(main_eamode==dreg){ + emit("mov cl,[ebp+__xflag]\n"); + emit("shr cl,1\n"); + if(main_size==1)emit("mov cl,0\n"); + else emit("mov ecx,0\n"); + emit("sbb %s,[ebp+__dreg+ebx*4]\n",x86cx[main_size]); + emit("mov edx,eax\n"); + flags();c2x(); + adjzero("dh"); + emit("mov [ebp+__dreg+ebx*4],%s\n",x86cx[main_size]); + }else{ + cycles*=2; + main_ea_rmw_load(); + emit("push ebx\n"); + emit("mov bl,[ebp+__xflag]\n"); + emit("shr bl,1\n"); + if(main_size==1)emit("mov bl,0\n"); + else emit("mov ebx,0\n"); + emit("sbb %s,%s\n",x86bx[main_size],x86cx[main_size]); + emit("mov ecx,ebx\n"); + emit("mov ebx,eax\n"); + flags();c2x(); + adjzero("bh"); + emit("pop ebx\n"); + main_ea_rmw_store(); + cycles+=main_ea_cycles(); + } + /* Calculate loop mode timings */ + if(cputype==68010){ + switch(main_eamode){ + case aind:case ainc:case adec: + loop_c_cycles = 4; + loop_t_cycles = 10; + loop_x_cycles = 8; + break; + default:break; + } + } + ret_timing(cycles); +} + +static void i_nbcd(void){ + int cycles; + main_size=1; + selective_usereg(); + main_ea_rmw_load(); + /* Get the X flag into carry */ + emit("mov cl,[ebp+__xflag]\n"); + emit("shr cl,1\n"); + /* Save the previous Z flag in CH */ + emit("mov ch,ah\n"); + /* Perform the BCD subtraction */ + emit("mov al,0\n"); + emit("sbb al,cl\n"); + emit("das\n"); + /* Save result in CL */ + emit("mov cl,al\n"); + /* Set flags - V undefined */ + flags_v0(); + c2x(); + /* Adjust for non-changing Z (previous Z flag in CH) */ + adjzero("ch"); + main_ea_rmw_store(); + if(main_eamode==dreg){ + cycles=6; + }else{ + cycles=8+main_ea_cycles(); + } + /* Calculate loop mode timings */ + if(cputype==68010){ + switch(main_eamode){ + case aind:case ainc:case adec: + loop_c_cycles = 6; + loop_t_cycles = 12; + loop_x_cycles = 10; + break; + default:break; + } + } + ret_timing(cycles); +} + +static void i_tas(void){ + int cycles; + main_size=1; + selective_usereg(); + main_ea_rmw_load(); + selftest(1); + flags_v0(); + emit("or cl,80h\n"); + main_ea_rmw_store(); + if((main_eamode==dreg)||(main_eamode==areg)){ + cycles=4; + }else{ + cycles=14+main_ea_cycles(); + } + /* No loop mode */ + ret_timing(cycles); +} + +static void i_not(void){ + int cycles; + selective_usereg(); + cycles=4; + if(main_size==4)cycles=6; + if(main_eamode==dreg){ + emit("xor %s[ebp+__dreg+ebx*4],byte -1\n", + sizename[main_size] + ); + flags_v0(); + }else{ + cycles*=2; + main_ea_rmw_load(); + emit("xor %s,byte -1\n",x86cx[main_size]); + flags_v0(); + main_ea_rmw_store(); + cycles+=main_ea_cycles(); + } + /* Calculate loop mode timings */ + if(cputype==68010){ + switch(main_eamode){ + case aind:case ainc:case adec: + loop_c_cycles = 4; + loop_t_cycles = 10; + loop_x_cycles = 8; + break; + default:break; + } + } + ret_timing(cycles); +} + +/* main_reg=rx, main_dr is 0 or 32 (rx a/d), main_ir is 0 or 32 (ry a/d) */ +static void i_exg(void){ + usereg(); + emit("mov ecx,[ebp+__reg+%d]\n",(main_reg*4)+main_dr); + emit("mov edx,[ebp+__reg+%d+ebx*4]\n",main_ir); + emit("mov [ebp+__reg+%d],edx\n",(main_reg*4)+main_dr); + emit("mov [ebp+__reg+%d+ebx*4],ecx\n",main_ir); + /* No loop mode */ + ret_timing(6); +} + +static void i_cmpm(void){ + usereg(); + ea_load(main_size,ainc,-1);/* Keep this in order */ + emit("mov eax,ecx\n"); + ea_load(main_size,ainc,main_reg); + emit("cmp %s,%s\n",x86cx[main_size],x86ax[main_size]); + flags(); + /* Calculate loop mode timings */ + if(cputype==68010){ + if(main_size<=2){ + loop_c_cycles = 2; + loop_t_cycles = 8; + loop_x_cycles = 6; + }else{ + loop_c_cycles = 4; + loop_t_cycles = 10; + loop_x_cycles = 6; + } + } + ret_timing((main_size==4)?20:12); +} + +static void opx_dreg(char*op,char*adjust){ + int cycles; + usereg(); + emit("mov ch,ah\n");/* Save old Z flag in CH */ + emit("mov cl,[ebp+__xflag]\n"); + emit("shr cl,1\n");/* X -> x86 carry */ + emit("mov eax,[ebp+__dreg+%d]\n",main_reg*4); + emit("%s %s,[ebp+__dreg+ebx*4]\n",op,x86ax[main_size]); + if(adjust[0]){ + emit("%s\n",adjust); + } + emit("mov [ebp+__dreg+%d],%s\n",main_reg*4,x86ax[main_size]); + emit("lahf\n"); + if(adjust[0]){ + emit("mov al,0\n"); + }else{ + emit("seto al\n"); + } + c2x(); + adjzero("ch"); + if(main_size<=2){ + cycles=4; + if(adjust[0])cycles=6; + }else{ + cycles=8; + if(cputype==68010)cycles=6; + } + /* No loop mode */ + ret_timing(cycles); +} + +static void opx_adec(char*op,char*adjust){ + int cycles; + usereg(); + ea_load(main_size,adec,-1);/* Keep this in order */ + emit("mov ebx,ecx\n"); + ea_rmw_load(main_size,adec,main_reg); + emit("xchg ecx,eax\n");/* flags -> ECX, dest -> EAX */ + emit("mov cl,[ebp+__xflag]\n"); + emit("shr cl,1\n");/* X -> x86 carry */ + emit("%s %s,%s\n",op,x86ax[main_size],x86bx[main_size]); + if(adjust[0]){ + emit("%s\n",adjust); + } + emit("mov ebx,eax\n"); + emit("lahf\n"); + if(adjust[0]){ + emit("mov al,0\n"); + }else{ + emit("seto al\n"); + } + c2x(); + adjzero("ch"); + emit("mov ecx,ebx\n"); + emit("xor ebx,ebx\n"); + ea_rmw_store(main_size,adec,main_reg); + if(main_size<=2){ + cycles=18; + }else{ + cycles=30; + } + /* Calculate loop mode timings */ + if(cputype==68010){ + if(adjust[0]){ + loop_c_cycles = 6; + loop_t_cycles = 12; + loop_x_cycles = 10; + }else{ + if(main_size<=2){ + loop_c_cycles = 4; + loop_t_cycles = 10; + loop_x_cycles = 8; + }else{ + loop_c_cycles = 2; + loop_t_cycles = 8; + loop_x_cycles = 6; + } + } + } + ret_timing(cycles); +} + +static void i_addx_dreg(void){opx_dreg("adc","");} +static void i_addx_adec(void){opx_adec("adc","");} +static void i_subx_dreg(void){opx_dreg("sbb","");} +static void i_subx_adec(void){opx_adec("sbb","");} +static void i_abcd_dreg(void){main_size=1;opx_dreg("adc","daa");} +static void i_abcd_adec(void){main_size=1;opx_adec("adc","daa");} +static void i_sbcd_dreg(void){main_size=1;opx_dreg("sbb","das");} +static void i_sbcd_adec(void){main_size=1;opx_adec("sbb","das");} + +static void i_movep_mem2reg(void){ + int cycles; + usereg(); + emit("movsx edx,word[esi]\n"); + emit("add esi,byte 2\n"); + emit("add edx,[ebp+__areg+ebx*4]\n"); + emit("call readmemorybyte\n"); + emit("mov bh,cl\n"); + emit("add edx,byte 2\n"); + emit("call readmemorybyte\n"); + emit("mov bl,cl\n"); + if(main_size==2){ + emit("mov [ebp+__dreg+%d],bx\n",main_reg*4); + cycles=16; + }else{ + emit("add edx,byte 2\n"); + emit("shl ebx,16\n"); + emit("call readmemorybyte\n"); + emit("mov bh,cl\n"); + emit("add edx,byte 2\n"); + emit("call readmemorybyte\n"); + emit("mov bl,cl\n"); + emit("mov [ebp+__dreg+%d],ebx\n",main_reg*4); + emit("xor ebx,ebx\n"); + cycles=24; + } + /* No loop mode */ + ret_timing(cycles); +} + +static void i_movep_reg2mem(void){ + int cycles; + usereg(); + emit("movsx edx,word[esi]\n"); + emit("add esi,byte 2\n"); + emit("add edx,[ebp+__areg+ebx*4]\n"); + emit("mov ebx,[ebp+__dreg+%d]\n",main_reg*4); + if(main_size==4)emit("rol ebx,16\n"); + emit("mov cl,bh\n"); + emit("call writememorybyte\n"); + emit("add edx,byte 2\n"); + emit("mov cl,bl\n"); + emit("call writememorybyte\n"); + if(main_size==4){ + emit("add edx,byte 2\n"); + emit("rol ebx,16\n"); + emit("mov cl,bh\n"); + emit("call writememorybyte\n"); + emit("add edx,byte 2\n"); + emit("mov cl,bl\n"); + emit("call writememorybyte\n"); + cycles=24; + }else{ + cycles=16; + } + emit("xor ebx,ebx\n"); + /* No loop mode */ + ret_timing(cycles); +} + +static void i_chk(void){ + int cycles; + int myline=linenum;linenum++; + selective_usereg(); + main_ea_load(); + emit("cmp %s[ebp+__dreg+%d],byte 0\n", + sizename[main_size],main_reg*4 + ); + emit("mov ax,8000h\n"); + emit("jl short ln%d\n",myline); + emit("cmp [ebp+__dreg+%d],%s\n", + main_reg*4,x86cx[main_size] + ); + emit("mov ax,0\n"); + emit("jg short ln%d\n",myline); + cycles=10; + if(cputype==68010)cycles=8; + ret_timing(cycles+main_ea_cycles()); + /* Out of bounds, so generate CHK exception */ + emit("ln%d:",myline); + emit("mov edx,18h\n"); + emit("call group_2_exception\n"); + perform_cached_rebase(); + cycles=40; + if(cputype==68010)cycles=44; + /* No loop mode */ + ret_timing(cycles+main_ea_cycles()); +} + +static int created_illegal=0; +static void i_illegal(void){ + if(!created_illegal){emit("r_illegal:\n");created_illegal=1;} + emit("sub esi,byte 2\n"); + emit("mov edx,10h\n"); + emit("call group_1_exception\n"); + perform_cached_rebase(); + ret_timing((cputype==68010)?38:34); +} + +/* Breakpoint - notify hardware */ +static void i_bkpt(void){ + int myline=linenum; + linenum++; + emit("mov edx,[ebp+__bkpthandler]\n"); + emit("or edx,edx\n"); + emit("jz ln%d\n",myline); + airlock_exit(); + if(use_stack) { + emit("push dword[ebp+__hwstate]\n"); + } else { + emit("mov ecx,[ebp+__hwstate]\n"); + } + emit("call edx\n"); + if(use_stack) { + emit("add esp,byte 4\n"); + } + airlock_enter(); + emit("ln%d:\n",myline); + emit("mov edx,10h\n"); + emit("call group_1_exception\n"); + perform_cached_rebase(); + ret_timing((cputype==68010)?38:34); +} + +static void i_aline(void){ + emit("sub esi,byte 2\n"); + emit("mov edx,28h\n"); + emit("call group_1_exception\n"); + perform_cached_rebase(); + /* This is just a guess */ + ret_timing((cputype==68010)?38:34); +} + +static void i_fline(void){ + emit("sub esi,byte 2\n"); + emit("mov edx,2Ch\n"); + emit("call group_1_exception\n"); + perform_cached_rebase(); + /* This is just a guess */ + ret_timing((cputype==68010)?38:34); +} + +static void i_reset(void){ + privilegecheck(); + emit("mov edx,[ebp+__resethandler]\n"); + emit("or edx,edx\n"); + emit("jz near invalidins\n"); + airlock_exit(); + if(use_stack) { + emit("push dword[ebp+__hwstate]\n"); + } else { + emit("mov ecx,[ebp+__hwstate]\n"); + } + emit("call edx\n"); + if(use_stack) { + emit("add esp,byte 4\n"); + } + airlock_enter(); + ret_timing((cputype==68010)?130:132); +} + +static void i_movec_c_to_r(void){ + int myline=linenum;linenum++; + privilegecheck(); + emit("mov bx,word[esi]\n"); + emit("mov edx,ebx\n"); + emit("shr ebx,12\n"); + + emit("and edx,0FFFh\n"); + emit("jnz short ln%d\n",linenum); + emit("mov cl,[ebp+__sfc]\n"); + emit("and ecx,byte 7\n"); + emit("jmp short ln%d\n",myline); + emit("ln%d:\n",linenum);linenum++; + + emit("cmp edx,byte 1\n"); + emit("jnz short ln%d\n",linenum); + emit("mov cl,[ebp+__dfc]\n"); + emit("and ecx,byte 7\n"); + emit("jmp short ln%d\n",myline); + emit("ln%d:\n",linenum);linenum++; + + emit("cmp edx,0800h\n"); + emit("jnz short ln%d\n",linenum); + emit("mov ecx,[ebp+__asp]\n"); + emit("jmp short ln%d\n",myline); + emit("ln%d:\n",linenum);linenum++; + + emit("cmp edx,0801h\n"); + emit("jnz short ln%d\n",linenum); + emit("mov ecx,[ebp+__vbr]\n"); + emit("jmp short ln%d\n",myline); + emit("ln%d:\n",linenum);linenum++; + + emit("jmp r_illegal\n"); + + emit("ln%d:\n",myline); + emit("add esi,byte 2\n"); + emit("mov dword[ebp+__reg+ebx*4],ecx\n"); + ret_timing(12); +} + +static void i_movec_r_to_c(void){ + int myline=linenum;linenum++; + privilegecheck(); + emit("mov bx,word[esi]\n"); + emit("mov edx,ebx\n"); + emit("shr ebx,12\n"); + emit("mov ecx,dword[ebp+__reg+ebx*4]\n"); + + emit("and edx,0FFFh\n"); + emit("jnz short ln%d\n",linenum); + emit("and cl,7\n"); + emit("mov [ebp+__sfc],cl\n"); + emit("jmp short ln%d\n",myline); + emit("ln%d:\n",linenum);linenum++; + + emit("cmp edx,byte 1\n"); + emit("jnz short ln%d\n",linenum); + emit("and cl,7\n"); + emit("mov [ebp+__dfc],cl\n"); + emit("jmp short ln%d\n",myline); + emit("ln%d:\n",linenum);linenum++; + + emit("cmp edx,0800h\n"); + emit("jnz short ln%d\n",linenum); + emit("mov [ebp+__asp],ecx\n"); + emit("jmp short ln%d\n",myline); + emit("ln%d:\n",linenum);linenum++; + + emit("cmp edx,0801h\n"); + emit("jnz short ln%d\n",linenum); + emit("mov [ebp+__vbr],ecx\n"); + emit("jmp short ln%d\n",myline); + emit("ln%d:\n",linenum);linenum++; + + emit("jmp r_illegal\n"); + + emit("ln%d:\n",myline); + emit("add esi,byte 2\n"); + ret_timing(10); +} + +#if 0 +/* called not-quite-so-many times as i_move */ +static void i_moves(void){ + int cycles; + int unitsize = main_size == 4 ? 2 : main_size; + int myline=linenum; + linenum++; + selective_usereg(); + emit("push esi\n"); /* save in case it's invalid */ + emit("movzx ecx,word[esi]\n"); + emit("add esi,byte 2\n"); + ea_step_precalc(main_size,main_eamode,-1); /* edx=address */ + emit("shr ecx,12\n"); + emit("jc short ln%d_write\n",myline); + /* read */ + emit("cmp byte[ebp+__sfc],1\n"); + emit("je ln%d_read_userdata\n"); + emit("cmp byte[ebp+__sfc],2\n"); + emit("je ln%d_read_userprogram\n"); + emit("cmp byte[ebp+__sfc],5\n"); + emit("je ln%d_read_superdata\n"); + emit("cmp byte[ebp+__sfc],6\n"); + emit("je ln%d_read_superprogram\n"); + + /* + ** Generic address space read routine; SFC in {0,3,4,7} + */ + emit("cmp dword[ebp+__fc_read%s],byte 0\n",sizename[unitsize]); + emit("je short ln%d_inv\n",myline); + emit("push ecx\n"); + emit("push edx\n"); + airlock_exit(); + emit("mov al,[ebp+__sfc]\n"); + emit("and eax,byte 7\n"); + if(use_stack) { + emit("push edx\n"); + emit("push eax\n"); + } + emit("call dword[ebp+__fc_read%s]\n"); + if(use_stack) { + emit("add esp,byte 8\n"); + } + emit("mov ecx,[esp+%d]\n",airlock_stacksize+4); + switch(main_size) { + case 1:emit("mov [ebp+__reg+ecx*4],al\n");break; + case 2:emit("mov [ebp+__reg+ecx*4],ax\n");break; + case 4:emit("mov [ebp+__reg+ecx*4+2],ax\n"); + emit("mov edx,[esp+%d]\n",airlock_stacksize); + emit("add edx,byte 2\n"); + emit("mov al,[ebp+__sfc]\n"); + emit("and eax,byte 7\n"); + if(use_stack) { + emit("push edx\n"); + emit("push eax\n"); + } + emit("call dword[ebp+__fc_read%s]\n"); + if(use_stack) { + emit("add esp,byte 8\n"); + } + emit("mov ecx,[esp+%d]\n",airlock_stacksize+4); + emit("mov [ebp+__reg+ecx*4],ax\n"); + break; + } + airlock_enter(); + emit("pop edx\n"); + emit("pop ecx\n"); + ea_step_postcalc(main_size,main_eamode,-1); /* edx=address */ + emit("jmp ln%d_end\n"); + + ret_timing(cycles); +} +#endif + +/**************************************************************************** +** DECODE ROUTINES +****************************************************************************/ + +static int rproc [0x10000]; +static byte unique[0x10000]; +static int cease_decode; + +static int test(int n, int m, int op) { + int t; + if((n & m) != op) return 0; + for(t = op & 0xF000; t < n; t++) { + if((!unique[t]) && ((t & m) == (n & m))) { + rproc[n] = t; + return 2; + } + } + unique[n] = (m >> 16) & 1; + rproc[n] = n; + t = (m ^ 0xFFFF) & 0xFFF; + if(!t) { + emit("; Opcode %04X\n", n); + } else { + emit("; Opcodes %04X - %04X\n", n, op + t); + } + emit("%c%03X:\n", ((n >> 12) & 0xF) + 'K', n & 0xFFF); + routine_counter++; + return 1; +} + +/* Instruction definition routine */ +static void idef( + int n, int mask, int op, void(*proc)(void) +) { + if(cease_decode) return; + cease_decode = test(n, mask, op); + if(cease_decode == 1) { + if(cputype == 68010) { + loop_c_cycles = 10; + loop_t_cycles = 10; + loop_x_cycles = 16; + } + proc(); + if(cputype == 68010) { + if(loop_c_cycles > 14) { + fprintf(stderr, + "Bad news: instruction %04X:\n" + "loop_c_cycles (%d) exceeds limit\n", + n, loop_c_cycles + ); + exit(1); + } + if(loop_t_cycles > 14) { + fprintf(stderr, + "Bad news: instruction %04X:\n" + "loop_t_cycles (%d) exceeds limit\n", + n, loop_t_cycles + ); + exit(1); + } + if(loop_x_cycles > (loop_c_cycles + 6)) { + fprintf(stderr, + "Bad news: instruction %04X:\n" + "loop_c_cycles (%d) and " + "loop_x_cycles (%d) too far apart\n", + n, loop_c_cycles, loop_x_cycles + ); + exit(1); + } + loop_x_cycles -= loop_c_cycles; + loopinfo[n] = + (((loop_c_cycles ) & 0x0E) | + ((loop_t_cycles << 3) & 0x70)) | + (((loop_x_cycles << 6) & 0x80) | + ((loop_x_cycles >> 2) & 0x01)); + } + } +} + +/* Batch idef for all addressing modes */ +static void eadef_all( + int n, int m, int op, void(*proc)(void) +) { + if(cease_decode) return; + main_eamode = dreg; idef(n, m | 0x38, op | 0x00, proc); + main_eamode = areg; idef(n, m | 0x38, op | 0x08, proc); + main_eamode = aind; idef(n, m | 0x38, op | 0x10, proc); + main_eamode = ainc; idef(n, m | 0x38, op | 0x18, proc); + main_eamode = adec; idef(n, m | 0x38, op | 0x20, proc); + main_eamode = adsp; idef(n, m | 0x38, op | 0x28, proc); + main_eamode = axdp; idef(n, m | 0x38, op | 0x30, proc); + main_eamode = absw; idef(n, m | 0x3F, op | 0x38, proc); + main_eamode = absl; idef(n, m | 0x3F, op | 0x39, proc); + main_eamode = pcdp; idef(n, m | 0x3F, op | 0x3A, proc); + main_eamode = pcxd; idef(n, m | 0x3F, op | 0x3B, proc); + main_eamode = immd; idef(n, m | 0x3F, op | 0x3C, proc); +} + +/* Batch idef for all addressing modes, excluding Address Register Direct +** mode when the operand size is 1 */ +static void eadef_all_nobyteaddress( + int n, int m, int op, void(*proc)(void) +) { + if(cease_decode) return; + main_eamode = dreg; idef(n, m | 0x38, op | 0x00, proc); + if(main_size != 1) { + main_eamode = areg; idef(n, m | 0x38, op | 0x08, proc); + } + main_eamode = aind; idef(n, m | 0x38, op | 0x10, proc); + main_eamode = ainc; idef(n, m | 0x38, op | 0x18, proc); + main_eamode = adec; idef(n, m | 0x38, op | 0x20, proc); + main_eamode = adsp; idef(n, m | 0x38, op | 0x28, proc); + main_eamode = axdp; idef(n, m | 0x38, op | 0x30, proc); + main_eamode = absw; idef(n, m | 0x3F, op | 0x38, proc); + main_eamode = absl; idef(n, m | 0x3F, op | 0x39, proc); + main_eamode = pcdp; idef(n, m | 0x3F, op | 0x3A, proc); + main_eamode = pcxd; idef(n, m | 0x3F, op | 0x3B, proc); + main_eamode = immd; idef(n, m | 0x3F, op | 0x3C, proc); +} + +/* Batch idef for all data addressing modes */ +static void eadef_data( + int n, int m, int op, void(*proc)(void) +) { + if(cease_decode) return; + main_eamode = dreg; idef(n, m | 0x38, op | 0x00, proc); + main_eamode = aind; idef(n, m | 0x38, op | 0x10, proc); + main_eamode = ainc; idef(n, m | 0x38, op | 0x18, proc); + main_eamode = adec; idef(n, m | 0x38, op | 0x20, proc); + main_eamode = adsp; idef(n, m | 0x38, op | 0x28, proc); + main_eamode = axdp; idef(n, m | 0x38, op | 0x30, proc); + main_eamode = absw; idef(n, m | 0x3F, op | 0x38, proc); + main_eamode = absl; idef(n, m | 0x3F, op | 0x39, proc); + main_eamode = pcdp; idef(n, m | 0x3F, op | 0x3A, proc); + main_eamode = pcxd; idef(n, m | 0x3F, op | 0x3B, proc); + main_eamode = immd; idef(n, m | 0x3F, op | 0x3C, proc); +} + +/* Batch idef for all alterable addressing modes, excluding Address Register +** Direct mode when the operand size is 1 */ +static void eadef_alterable_nobyteaddress( + int n, int m, int op, void(*proc)(void) +) { + if(cease_decode) return; + main_eamode = dreg; idef(n, m | 0x38, op | 0x00, proc); + if(main_size != 1) { + main_eamode = areg; idef(n, m | 0x38, op | 0x08, proc); + } + main_eamode = aind; idef(n, m | 0x38, op | 0x10, proc); + main_eamode = ainc; idef(n, m | 0x38, op | 0x18, proc); + main_eamode = adec; idef(n, m | 0x38, op | 0x20, proc); + main_eamode = adsp; idef(n, m | 0x38, op | 0x28, proc); + main_eamode = axdp; idef(n, m | 0x38, op | 0x30, proc); + main_eamode = absw; idef(n, m | 0x3F, op | 0x38, proc); + main_eamode = absl; idef(n, m | 0x3F, op | 0x39, proc); +} + +/* Batch idef for all data alterable addressing modes */ +static void eadef_data_alterable( + int n, int m, int op, void(*proc)(void) +) { + if(cease_decode) return; + main_eamode = dreg; idef(n, m | 0x38, op | 0x00, proc); + main_eamode = aind; idef(n, m | 0x38, op | 0x10, proc); + main_eamode = ainc; idef(n, m | 0x38, op | 0x18, proc); + main_eamode = adec; idef(n, m | 0x38, op | 0x20, proc); + main_eamode = adsp; idef(n, m | 0x38, op | 0x28, proc); + main_eamode = axdp; idef(n, m | 0x38, op | 0x30, proc); + main_eamode = absw; idef(n, m | 0x3F, op | 0x38, proc); + main_eamode = absl; idef(n, m | 0x3F, op | 0x39, proc); +} + +/* Batch idef for all memory alterable addressing modes */ +static void eadef_memory_alterable( + int n, int m, int op, void(*proc)(void) +) { + if(cease_decode) return; + main_eamode = aind; idef(n, m | 0x38, op | 0x10, proc); + main_eamode = ainc; idef(n, m | 0x38, op | 0x18, proc); + main_eamode = adec; idef(n, m | 0x38, op | 0x20, proc); + main_eamode = adsp; idef(n, m | 0x38, op | 0x28, proc); + main_eamode = axdp; idef(n, m | 0x38, op | 0x30, proc); + main_eamode = absw; idef(n, m | 0x3F, op | 0x38, proc); + main_eamode = absl; idef(n, m | 0x3F, op | 0x39, proc); +} + +/* Batch idef for all control addressing modes */ +static void eadef_control( + int n, int m, int op, void(*proc)(void) +) { + if(cease_decode) return; + main_eamode = aind; idef(n, m | 0x38, op | 0x10, proc); + main_eamode = adsp; idef(n, m | 0x38, op | 0x28, proc); + main_eamode = axdp; idef(n, m | 0x38, op | 0x30, proc); + main_eamode = absw; idef(n, m | 0x3F, op | 0x38, proc); + main_eamode = absl; idef(n, m | 0x3F, op | 0x39, proc); + main_eamode = pcdp; idef(n, m | 0x3F, op | 0x3A, proc); + main_eamode = pcxd; idef(n, m | 0x3F, op | 0x3B, proc); +} + +/* Batch idef for all control alterable addressing modes */ +static void eadef_control_alterable( + int n, int m, int op, void(*proc)(void) +) { + if(cease_decode) return; + main_eamode = aind; idef(n, m | 0x38, op | 0x10, proc); + main_eamode = adsp; idef(n, m | 0x38, op | 0x28, proc); + main_eamode = axdp; idef(n, m | 0x38, op | 0x30, proc); + main_eamode = absw; idef(n, m | 0x3F, op | 0x38, proc); + main_eamode = absl; idef(n, m | 0x3F, op | 0x39, proc); +} + +/* Batch eadef for MOVE instructions */ +static void defmove(int majorop, int n) { + if(cease_decode) return; + for(main_reg = 0; main_reg < 8; main_reg++) { + word w = majorop | (main_reg << 9); + main_destmode = dreg; eadef_all(n, 0xFFC0, 0x000 | w, i_move); + main_destmode = aind; eadef_all(n, 0xFFC0, 0x080 | w, i_move); + main_destmode = ainc; eadef_all(n, 0xFFC0, 0x0C0 | w, i_move); + main_destmode = adec; eadef_all(n, 0xFFC0, 0x100 | w, i_move); + main_destmode = adsp; eadef_all(n, 0xFFC0, 0x140 | w, i_move); + main_destmode = axdp; eadef_all(n, 0xFFC0, 0x180 | w, i_move); + } + main_destmode = absw; eadef_all(n, 0xFFC0, 0x1C0 | majorop, i_move); + main_destmode = absl; eadef_all(n, 0xFFC0, 0x3C0 | majorop, i_move); +} + +/***************************************************************************/ + +static void decode0(int n) { + cease_decode = 0; + for(sizedef = 0; sizedef < 3; sizedef++) { + main_size = 1 << sizedef; + eadef_data_alterable(n, 0xFFC0, 0x0000 | (sizedef << 6), i_ori); + eadef_data_alterable(n, 0xFFC0, 0x0200 | (sizedef << 6), i_andi); + eadef_data_alterable(n, 0xFFC0, 0x0400 | (sizedef << 6), i_subi); + eadef_data_alterable(n, 0xFFC0, 0x0600 | (sizedef << 6), i_addi); + eadef_data_alterable(n, 0xFFC0, 0x0A00 | (sizedef << 6), i_eori); + eadef_data_alterable(n, 0xFFC0, 0x0C00 | (sizedef << 6), i_cmpi); + /* Not quite ready for prime time yet */ +/* if(cputype >= 68010) { + eadef_memory_alterable(n, 0xFFC0, 0x0E00 | (sizedef << 6), i_moves); + }*/ + } + /* + ** Bit operations + ** BTST (main_cc 0) works with all data addressing modes; the others + ** require data alterable addressing modes + */ + for(main_cc = 0; main_cc < 4; main_cc++) { + void (*eadef)(int n, int m, int op, void(*proc)(void)) = + main_cc ? eadef_data_alterable : eadef_data; + eadef(n, 0xFFC0, 0x0800 | (main_cc << 6), i_bitop_imm); + for(main_reg = 0; main_reg < 8; main_reg++) { + eadef(n, 0xFFC0, + 0x0100 | (main_cc << 6) | (main_reg << 9), + i_bitop_reg + ); + } + } + idef(n, 0xFFFF, 0x003C, i_ori_ccr ); + idef(n, 0xFFFF, 0x023C, i_andi_ccr); + idef(n, 0xFFFF, 0x0A3C, i_eori_ccr); + idef(n, 0xFFFF, 0x007C, i_ori_sr ); + idef(n, 0xFFFF, 0x027C, i_andi_sr ); + idef(n, 0xFFFF, 0x0A7C, i_eori_sr ); + for(main_reg=0;main_reg<8;main_reg++)for(main_size=2;main_size<=4;main_size+=2){ + idef(n,0xFFF8,0x0108|((main_size&4)<<4)|(main_reg<<9),i_movep_mem2reg); + idef(n,0xFFF8,0x0188|((main_size&4)<<4)|(main_reg<<9),i_movep_reg2mem); + } +} + +static void decode1(int n) { + cease_decode = 0; + main_size = 1; + defmove(0x1000, n); +} + +static void decode2(int n) { + cease_decode = 0; + main_size = 4; + defmove(0x2000, n); + for(main_reg = 0; main_reg < 8; main_reg++) { + eadef_all(n, 0xFFC0, 0x2040 | (main_reg << 9), i_movea); + } +} + +static void decode3(int n) { + cease_decode = 0; + main_size = 2; + defmove(0x3000, n); + for(main_reg = 0; main_reg < 8; main_reg++) { + eadef_all(n, 0xFFC0, 0x3040 | (main_reg << 9), i_movea); + } +} + +static void decode4(int n) { + cease_decode = 0; + eadef_data_alterable(n, 0xFFC0, 0x40C0, i_move_from_sr); + if(cputype >= 68010) { + eadef_data_alterable(n, 0xFFC0, 0x42C0, i_move_from_ccr); + } + eadef_data(n, 0xFFC0, 0x44C0, i_move_to_ccr); + eadef_data(n, 0xFFC0, 0x46C0, i_move_to_sr ); + eadef_control(n, 0xFFC0, 0x4EC0, i_jmp); + eadef_control(n, 0xFFC0, 0x4E80, i_jsr); + for(main_reg=0;main_reg<8;main_reg++)eadef_control(n,0xFFC0,0x41C0|(main_reg<<9),i_lea); + main_size=2;for(main_reg=0;main_reg<8;main_reg++)eadef_data(n,0xFFC0,0x4100|(main_reg<<9),i_chk); + eadef_control(n,0xFFC0,0x4840,i_pea); + for(sizedef = 0; sizedef < 3; sizedef++) { + main_size = 1 << sizedef; + eadef_data_alterable(n, 0xFFC0, 0x4200 | (sizedef << 6), i_clr); + eadef_data_alterable(n, 0xFFC0, 0x4A00 | (sizedef << 6), i_tst); + } + idef(n, 0xFFFF, 0x4E70, i_reset); + idef(n, 0xFFFF, 0x4E71, i_nop); + idef(n, 0xFFFF, 0x4E72, i_stop); + idef(n, 0xFFFF, 0x4E73, i_rte); + idef(n, 0xFFFF, 0x4E75, i_rts); + idef(n, 0xFFFF, 0x4E76, i_trapv); + idef(n, 0xFFFF, 0x4E77, i_rtr); + if(cputype >= 68010) { + idef(n, 0xFFFF, 0x4E74, i_rtd); + idef(n, 0xFFFF, 0x4E7A, i_movec_c_to_r); + idef(n, 0xFFFF, 0x4E7B, i_movec_r_to_c); + } + main_dr=0;for(sizedef=0;sizedef<2;sizedef++){main_size=1<<(sizedef+1);eadef_control_alterable(n,0xFFC0,0x4880|(main_dr<<10)|(sizedef<<6),i_movem_control);} + main_dr=1;for(sizedef=0;sizedef<2;sizedef++){main_size=1<<(sizedef+1);eadef_control (n,0xFFC0,0x4880|(main_dr<<10)|(sizedef<<6),i_movem_control);} + for(sizedef = 0; sizedef < 2; sizedef++) { + main_size = 1 << (sizedef + 1); + idef(n, 0xFFF8, 0x4C98 | (sizedef << 6), i_movem_postinc); + idef(n, 0xFFF8, 0x48A0 | (sizedef << 6), i_movem_predec ); + } + idef(n, 0xFFF8, 0x4E50, i_link); + idef(n, 0xFFF8, 0x4E58, i_unlk); + idef(n, 0xFFF0, 0x4E40, i_trap); + idef(n, 0xFFF8, 0x4E60, i_move_to_usp); + idef(n, 0xFFF8, 0x4E68, i_move_from_usp); + idef(n, 0xFFF8, 0x4840, i_swap); + idef(n, 0xFFF8, 0x4880, i_extbw); + idef(n, 0xFFF8, 0x48C0, i_extwl); + for(sizedef = 0; sizedef < 3; sizedef++) { + main_size = 1 << sizedef; + eadef_data_alterable(n, 0xFFC0, 0x4000 | (sizedef << 6), + i_negx); + eadef_data_alterable(n, 0xFFC0, 0x4400 | (sizedef << 6), + i_neg); + eadef_data_alterable(n, 0xFFC0, 0x4600 | (sizedef << 6), + i_not); + } + eadef_data_alterable(n, 0xFFC0, 0x4800, i_nbcd); + eadef_data_alterable(n, 0xFFC0, 0x4AC0, i_tas); + if(cputype == 68010) idef(n, 0xFFF8, 0x4848, i_bkpt); + idef(n, 0xFFFF, 0x4AFA, i_illegal); + idef(n, 0xFFFF, 0x4AFB, i_illegal); + idef(n, 0xFFFF, 0x4AFC, i_illegal); +} + +static void decode5(int n) { + cease_decode = 0; + for(sizedef = 0; sizedef < 3; sizedef++) { + main_size = 1 << sizedef; + for(main_qv = 0; main_qv < 8; main_qv++) { + word w = (sizedef << 6) | (main_qv << 9); + eadef_alterable_nobyteaddress(n, 0xFFC0, 0x5000 | w, + i_addq); + eadef_alterable_nobyteaddress(n, 0xFFC0, 0x5100 | w, + i_subq); + } + } + for(main_cc = 0x2; main_cc <= 0xF; main_cc++) { + idef(n, 0xFFF8, 0x50C8 | (main_cc << 8), i_dbcc); + } + idef(n, 0xFFF8, 0x51C8, i_dbra); + main_size = 1; + for(main_cc = 0x0; main_cc <= 0xF; main_cc++) { + eadef_data_alterable(n, 0xFFC0, 0x50C0 | (main_cc << 8), + i_scc); + } +} + +static void decode6(int n){ + cease_decode=0; + idef(n,0x1FFFF,0x6000,i_bra_w); + idef(n,0x1FFFF,0x6100,i_bsr_w); + for(main_cc=0x2;main_cc<=0xF;main_cc++){ + idef(n,0x1FFFF,0x6000|(main_cc<<8),i_bcc_w); + } + idef(n,0x0FF00,0x6000,i_bra_b); + idef(n,0x0FF00,0x6100,i_bsr_b); + for(main_cc=0x2;main_cc<=0xF;main_cc++){ + idef(n,0x0FF00,0x6000|(main_cc<<8),i_bcc_b); + } +} + +static void decode7(int n){ + cease_decode=0; + for(main_reg=0;main_reg<8;main_reg++)idef(n,0xFF00,0x7000|(main_reg<<9),i_moveq); +} + +static void decode8(int n){ + cease_decode=0; + for(sizedef=0;sizedef<3;sizedef++){main_size=1<> 12) & 0xF) + 'K', last & 0xFFF + ); + } + if(rl > 1) emit("+%u", ((dword)(rl - 1)) << 24); + emit("\n"); + if(cputype == 68010) emit("db %d\n", loopinfo[last]); +} + +/* Return the next parameter (or NULL if there isn't one */ +static char *getparameter(int *ip, int argc, char **argv) { + int i; + (*ip)++; + i = (*ip); + if(i >= argc) { + fprintf(stderr, "Invalid use of %s option\n", argv[i - 1]); + return NULL; + } + return argv[i]; +} + +int main(int argc, char **argv) { + int i, j, last, rl, bank; + char *codefilename = NULL; + char default_sourcename[10]; + + fprintf(stderr, "STARSCREAM version " VERSION "\n"); + + /* Read options from the command line */ + for(i = 1; i < argc; i++) { + char *a = argv[i]; + if(*a == '-') { + a++; + if(!strcmp("fastcall" , a)) { use_stack = 0; + } else if(!strcmp("cdecl" , a)) { use_stack = 1; + } else if(!strcmp("nohog" , a)) { hog = 0; + } else if(!strcmp("hog" , a)) { hog = 1; + } else if(!strcmp("addressbits", a)) { + int n; + char *s = getparameter(&i, argc, argv); + if(!s) return 1; + n = atol(s); + if(n < 1 || n > 32) { + fprintf(stderr, + "Invalid number of address " + "bits: \"%s\"\n", argv[i] + ); + return 1; + } + addressbits = n; + } else if(!strcmp("cputype" , a)) { + int n; + char *s = getparameter(&i, argc, argv); + if(!s) return 1; + n = atol(s); + switch(n) { + case 68000: + case 68010: + case 68020: + cputype = n; + break; + default: + fprintf(stderr, + "Invalid CPU type: \"%s\"\n", + argv[i] + ); + return 1; + } + } else if(!strcmp("name" , a)) { + sourcename = getparameter(&i, argc, argv); + if(!sourcename) return 1; + } else { + fprintf(stderr, + "\nUnrecognized option: \"%s\"\n", + argv[i] + ); + return 1; + } + } else { + if(codefilename) { + fprintf(stderr, + "\n\"%s\": only one output filename " + "is allowed\n", + argv[i] + ); + return 1; + } + codefilename = argv[i]; + } + } + + if(!codefilename) { + fprintf(stderr, "usage: %s outputfile [options]\n", argv[0]); + fprintf(stderr, "see STARDOC.TXT for details\n"); + return 1; + } + + /* Set default options where applicable */ + if(use_stack < 0) use_stack = 1; + if(hog < 0) hog = 0; + if(cputype < 0) cputype = 68000; + if(addressbits < 0) { + if(cputype <= 68010) addressbits = 24; + else addressbits = 32; + } + if(!sourcename) { + sprintf(default_sourcename, "s%d", cputype); + sourcename = default_sourcename; + } + + /* Prepare to generate the code file */ + linenum = 0; + fflush(stdout); + fflush(stderr); + codefile = fopen(codefilename, "w"); + if(!codefile) { + perror(codefilename); + return 1; + } + + fprintf(stderr, "Generating \"%s\" with the following options:\n", + codefilename + ); + optiondump(stderr, " * "); + prefixes(); + for(i = 0; i < 0x10000; i++) rproc[i] = -1; + /* Clear loop timings for 68010 */ + if(cputype == 68010) { + for(i = 0; i < 0x10000; i++) loopinfo[i] = 0xDB; + } + + /* + ** Decode instructions + ** (this is where the vast majority of the code is emitted) + */ + fprintf(stderr, "Decoding instructions: "); + for(bank = 0; bank <= 0xF; bank++) { + int bankend = (bank + 1) << 12; + void (*decoderoutine)(int n) = decodetable[bank]; + fprintf(stderr, "%X", bank); + fflush(stderr); + for(i = bank << 12; i < bankend; i++) decoderoutine(i); + } + fprintf(stderr, " done\n"); + + /* + ** Build the main jump table (all CPUs) / loop info table (68010) + */ + fprintf(stderr, "Building table: "); + emit("section .bss\n"); + emit("bits 32\n"); + align(4); + emit("_jmptbl resb 262144\n"); + if(cputype == 68010) emit("_looptbl resb 65536\n"); + emit("section .data\n"); + emit("bits 32\n"); + align(4); + emit("_jmptblcomp:\n"); + last = -2; + rl = 0; + for(i = 0; i < 0x10000; i++) { + j = rproc[i]; + if(j == last){ + if(rl == 256) { + tableentry(last, rl); + rl = 1; + } else { + rl++; + } + } else { + if(rl) tableentry(last, rl); + rl = 1; + last = j; + } + } + tableentry(last, rl); + align(4); + + /* Finish up */ + suffixes(); + fprintf(stderr, "done\n"); + fprintf(stderr, "routine_counter = %d\n", routine_counter); + fclose(codefile); + return 0; +} diff --git a/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/Starscream/star.exe b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/Starscream/star.exe new file mode 100644 index 000000000..6b19b2f4d Binary files /dev/null and b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/Starscream/star.exe differ diff --git a/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/Starscream/starcpu.h b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/Starscream/starcpu.h new file mode 100644 index 000000000..e4ef6dda6 --- /dev/null +++ b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/Starscream/starcpu.h @@ -0,0 +1,60 @@ +/* +** Starscream 680x0 emulation library +** Copyright 1997, 1998, 1999 Neill Corlett +** +** Refer to STARDOC.TXT for terms of use, API reference, and directions on +** how to compile. +*/ + +#ifndef __STARCPU_H__ +#define __STARCPU_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#define STARSCREAM_CALL __fastcall + +/* Remember to byte-swap these regions. (read STARDOC.TXT for details) */ +struct STARSCREAM_PROGRAMREGION { + unsigned lowaddr; + unsigned highaddr; + void *offset; +}; + +struct STARSCREAM_DATAREGION { + unsigned lowaddr; + unsigned highaddr; + void *memorycall; + void *userdata; +}; + +#define STARSCREAM_IDENTIFIERS(SNC,SN) \ + \ +int STARSCREAM_CALL SN##_init (void); \ +const char* STARSCREAM_CALL SN##_get_version (void); \ +unsigned STARSCREAM_CALL SN##_get_state_size (void); \ +void STARSCREAM_CALL SN##_clear_state (void *state); \ +void STARSCREAM_CALL SN##_set_memory_maps (void *state, void **info); \ +unsigned STARSCREAM_CALL SN##_reset (void *state); \ +unsigned STARSCREAM_CALL SN##_execute (void *state, int n); \ +unsigned STARSCREAM_CALL SN##_getreg (void *state, int n); \ +int STARSCREAM_CALL SN##_interrupt (void *state, int veclevel); \ +void STARSCREAM_CALL SN##_flush_interrupts (void *state); \ +unsigned STARSCREAM_CALL SN##_read_odometer (void *state); \ +void STARSCREAM_CALL SN##_break (void *state); \ + +#define STARSCREAM_REG_DATA (0) +#define STARSCREAM_REG_ADDRESS (8) +#define STARSCREAM_REG_ASP (16) +#define STARSCREAM_REG_PC (17) +#define STARSCREAM_REG_SR (18) + +STARSCREAM_IDENTIFIERS(S68000,s68000) +STARSCREAM_IDENTIFIERS(S68010,s68010) + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/Starscream/stardoc.txt b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/Starscream/stardoc.txt new file mode 100644 index 000000000..4ab120081 --- /dev/null +++ b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/Starscream/stardoc.txt @@ -0,0 +1,1056 @@ +----------------------------------------------------------------------------- +Starscream 680x0 emulation library version 0.26c +Copyright 1997, 1998, 1999 Neill Corlett +Modified by Stéphane Dallongeville +----------------------------------------------------------------------------- + +"Pathetic flesh creatures... can't you see we're INVINCIBLE? Come, +Decepticons, follow me to victory!" + + +How to contact Neill Corlett: +email: neill@neillcorlett.com +www: www.neillcorlett.com + + +Contents +-------- + + 0. Terms of Use + + 1. What's New + + 2. Getting Started + 2.1. What You Will Need + 2.2. How to Compile + + 3. The Starscream Interface + 3.1. Function Reference + 3.2. Contexts + 3.3. Address Spaces + 3.4. Executing Code + 3.5. Read and Write Handlers + 3.6. The Odometer + 3.7. Interrupts + 3.8. Emulating More Than One CPU + 3.9. RESET and BKPT Instructions + 3.10. Using the Interactive Debugger + 3.11. Emulating the 68010 + + 4. Tricks of the Trade + 4.1. Inter-CPU Communication + 4.2. Other Helpful Tips + 4.3. Pitfalls + 4.4. Ways to Abuse Starscream + 4.5. Emulating Other 68K-Series CPUs + + 5. Known Bugs + + 6. Credits + + +----------------------------------------------------------------------------- +0. Terms of Use +----------------------------------------------------------------------------- + +"Starscream" refers to the following files: +* STAR.C +* STARCPU.H +* CPUDEBUG.C +* CPUDEBUG.H +* STARDOC.TXT +* any object file or executable compiled from the above +* any source code generated from STAR.C, or object file assembled from such + code + +Starscream may be distributed freely in unmodified form, as long as this +documentation is included. + +No money, goods, or services may be charged or solicited for Starscream, or +any emulator or other program which includes Starscream, in whole or in part. +Using Starscream in a shareware or commercial application is forbidden. +Contact Neill Corlett if you'd like to license Starscream for commercial use. + +Any program which uses Starscream must include the following credit text, in +its documentation or in the program itself: + +"Starscream 680x0 emulation library by Neill Corlett" + + +----------------------------------------------------------------------------- +1. What's New +----------------------------------------------------------------------------- + +Version 0.26c: +* Shift bits instructions fixed. + +Version 0.26b: +* IO DWord Write bug fixed. +* Interrupt processing bug fixed. + (all lines added are followed by "// Stef Fix (Gens)" ) + +Version 0.26a: +* Egregious GetContext/SetContext bug fixed. +* Minor tweaking was done to the alignment rules. + +Version 0.26: +* First publicly redistributable version. +* Added the following exceptions: + Trace + Format Error (68010+) +* Added a Double Fault mechanism. Currently the only thing that can cause + this is s68000reset(). +* The memory map interface has changed to support different function codes / + address spaces (see section 3.3). +* Many improvements have been made to interrupt handling (see section 3.7). +* The unused bits of PC are now handled and preserved properly. +* Added fetch region caching. Jumps within the same program region are + now faster. +* Added a user-definable BKPT instruction handler (68010+). +* All Illegal Instruction exceptions are now emulated. The -illegal and + -noillegal options have been removed. +* Some features were added to the interactive debugger (see section 3.10). +* A few experimental 68020-related functions and variables have been added. + Ignore them for now. + +Version 0.25 and earlier: +Ask if interested. + + +----------------------------------------------------------------------------- +2. Getting Started +----------------------------------------------------------------------------- + +2.1. What You Will Need +------------------------ + +* A 32-bit C or C++ compiler. So far, the following compilers have been + proven to work: + - DJGPP 2.01 + - Watcom 10.6 + - GCC, running under Linux + - Microsoft Visual C++ + +* Netwide Assembler (NASM) version 0.95 or higher. NASM is freeware, with + publicly available source code, and available on a multitude of x86-based + platforms. It's available from Programmer's Heaven: + http://www.programmersheaven.com/ + +* Basic knowledge about the 680x0. You don't (theoretically) need to know + any 680x0 assembly, but it helps. A lot. + + You can get a copy of the M68000 Family Programmer's Reference Manual (in + Adobe Acrobat .PDF format) from this web page: + http://www.mot.com/SPS/HPESD/prod/0X0/frames/68K.html + + +2.2. How to Compile +-------------------- + +Step 1 + Generate the Starscream "code builder" executable by compiling STAR.C. + (for example: gcc star.c -o star) + +Step 2 + Generate the CPU source code. Run the code builder with the following + command line: + + star source.asm [options] + + Replace "source.asm" with the source code filename of your choice. + + Options that you might need: + + -regcall Use register calling conventions. + -stackcall Use stack-based calling conventions (default). + + -hog Enable Hog mode. This inlines the fetch-decode- + execute loop, resulting in a decent speed increase, + at the cost of about 130K of executable size. + -nohog Disable Hog mode (default). + + -cputype Specify the CPU type, 68000 or 68010 (default=68000). + + Options that you should never need (but they're here anyway): + + -addressbits n Use n-bit addresses. The default value depends on + the CPU type (currently it's just 24). + + "-addressbits 32" might allow some 68020/68070 code + to work. No guarantees, though. + + -name Appends the string to all identifiers. This + overrides the default of s68000 or s68010 (depending + on the CPU type). + +Step 3 + Assemble the CPU source code. Refer to the NASM documentation for how to + do this. + + If you run out of memory, try using NASMW.EXE instead of NASM.EXE (note, + however, that the NASMW.EXE executable from v0.97 is somewhat unstable). + Better yet, just recompile NASM yourself. Worked for me. + + To generate a COFF object for DJGPP or GNUWin32, try this: + + nasm -f coff source.asm + + or to generate a Win32 object for Watcom or Visual C++: + + nasm -f win32 source.asm + +Step 4 + Strip your executable when you're done! Starscream spews out symbols all + over the place (over 7000 of them), and you can save a ton of space by + stripping them once you're finished debugging. + + For GCC, this means use the -s option in the linking phase. + + +----------------------------------------------------------------------------- +3. The Starscream Interface +----------------------------------------------------------------------------- + +3.1. Function Reference +------------------------ + +The following is a brief summary of the functions declared in STARCPU.H. For +more information on a particular function, read the associated section. + + int s68000init(void); (section 3.4) + Initializes Starscream. Always returns 0. + + int s68000reset(void); (section 3.4) + Resets the current CPU. + Return value: + 0 Success + 1 Failure: Reset vector couldn't be fetched + -1 Failure: Double fault + + unsigned s68000exec(int n); (section 3.4) + Executes n cycles' worth of instructions on the current CPU. + Return value: + = 0x80000000 Success + = 0x80000001 Out of bounds + = 0x80000002 Unsupported stack frame (68010+) + = 0xFFFFFFFF Double fault + < 0x80000000 Invalid instruction; the value returned is the address + of the instruction + + int s68000interrupt(int level, int vector); (section 3.7) + Generates a hardware interrupt on the current CPU, with a given priority + level and vector number. The interrupt is queued for processing as soon + as possible. + Valid levels: 1-7 + Valid vectors: + 0-255 Deliberately vectored interrupt + -1 Auto-vectored interrupt + -2 Spurious interrupt + Return value: + 0 The interrupt was queued successfully. + 1 The interrupt was not queued, because a previously queued + interrupt exists at the same level. + 2 The interrupt was not queued, because either "level" or "vector" + were invalid. + + void s68000flushInterrupts(void); (section 3.7) + Check if there are any unmasked interrupts pending, and if so, process + them. + + int s68000GetContextSize(void); + Returns the size of the context structure. Useful for verifying that + the context struct is packed correctly, i.e.: + ASSERT(s68000GetContextSize() == sizeof(struct S68000CONTEXT)); + + void s68000GetContext(void *context); (section 3.2) + Copies the current context into another context structure. + + void s68000SetContext(void *context); (section 3.2) + Copies a context structure into the current context. + + int s68000fetch(unsigned address); + Fetches the word at the specified address, using the memoryfetch array. + Returns -1 if the address is out of bounds. + + unsigned s68000readOdometer(void); (section 3.6) + Returns the value of the odometer for the current CPU. Works anywhere, + even from within memory read/write, RESET, or BKPT handlers. + + unsigned s68000tripOdometer(void); (section 3.6) + Returns the value of the odometer for the current CPU, and resets it to + zero. Works anywhere. + + unsigned s68000controlOdometer(int n); (section 3.6) + Returns the value of the odometer for the current CPU. If n!=0, it also + resets the odometer to zero. Works anywhere. + + void s68000releaseTimeslice(void); (section 3.5) + When called from inside a memory read/write, RESET, or BKPT handler, + this causes s68000exec to end prematurely. The early exit is reflected + in the odometer. + + unsigned s68000readPC(void); + Returns the current program counter. Works anywhere. + + +3.2. Contexts +-------------- + +A "context" is a memory structure which holds all the information needed to +emulate a single CPU. Starscream defines a 68000 context as follows: + + struct S68000CONTEXT { + struct STARSCREAM_PROGRAMREGION *fetch; + struct STARSCREAM_DATAREGION *readbyte; + struct STARSCREAM_DATAREGION *readword; + struct STARSCREAM_DATAREGION *writebyte; + struct STARSCREAM_DATAREGION *writeword; + struct STARSCREAM_PROGRAMREGION *s_fetch; + struct STARSCREAM_DATAREGION *s_readbyte; + struct STARSCREAM_DATAREGION *s_readword; + struct STARSCREAM_DATAREGION *s_writebyte; + struct STARSCREAM_DATAREGION *s_writeword; + struct STARSCREAM_PROGRAMREGION *u_fetch; + struct STARSCREAM_DATAREGION *u_readbyte; + struct STARSCREAM_DATAREGION *u_readword; + struct STARSCREAM_DATAREGION *u_writebyte; + struct STARSCREAM_DATAREGION *u_writeword; + void (*resethandler)(void); + unsigned dreg[8]; + unsigned areg[8]; + unsigned asp; + unsigned pc; + unsigned odometer; + unsigned char interrupts[8]; + unsigned short sr; + }; + +There is a built-in context, called s68000context, which contains information +about the current CPU. If you're only emulating one 68000, then +s68000context is the only context you need. On the other hand, if you're +emulating more than one 68000, you'll need to define your own context for +each one. + +Here is a detailed description of the contents of a S68000CONTEXT structure: + +* "s_fetch", "s_readbyte", "s_readword", "s_writebyte", and "s_writeword" + are used to define the supervisor address space. "u_fetch", etc. are + used to define the user address space. (see section 3.3) + +* "resethandler" points to your reset handler routine. (see section 3.9) + +* "pc" is the program counter. + +* "dreg" holds the eight data registers, d0-d7, in order. + +* "areg" holds the eight address registers, a0-a7, in order. In supervisor + mode, areg[7] is the interrupt stack pointer. Otherwise, it's the user + stack pointer. + +* "asp" is whatever stack register areg[7] isn't. In supervisor mode, asp + is the user stack pointer. Othewise, it's the supervisor stack pointer. + +* "odometer" holds the number of cycles executed so far. It's incremented + as necessary on calls to s68000exec or s68000flushInterrupts. + +* "interrupts" is an array containing information about pending interrupts. + (see section 3.7) + +* "sr" is the status register. The lower 8 bits are the condition code + register. + + +3.3. Address Spaces +-------------------- + +The 68000 communicates with other devices via a number of address spaces. +There are different address spaces for program code and data, as well as +different address spaces for Supervisor and User modes. Most 68000-based +architectures use the same address space for all these, but the distinction +is there nonetheless. + +Starscream emulates program address spaces by translating the 68K address +into a native host address, and fetching data directly from host memory (from +an array of words with native byte order). A program address space is +defined using an array of STARSCREAM_PROGRAMREGION structures: + + struct STARSCREAM_PROGRAMREGION { + unsigned lowaddr; + unsigned highaddr; + unsigned offset; + }; + +Each structure contains the range of addresses in a program region, and an +offset which is added to the 68K address to obtain the equivalent host +address. + +IMPORTANT NOTE: Program regions must be stored as an array of words with +native byte order. Since Intel's byte order is different than Motorola's, +this means every other byte must be swapped. + +The s68000context fields "s_fetch" and "u_fetch" should be set to point to +arrays of STARSCREAM_PROGRAMREGION structures in order to define the +Supervisor Program and User Program address spaces, respectively. Each array +may contain any number of entries, and is terminated by an entry containing +-1 for both lowaddr and highaddr, and NULL for the offset. + +Starscream emulates data address spaces in a completely different way. Since +the 68000 has no dedicated I/O bus, device interfaces (video/sound chips, +input devices, etc.) are often mapped directly into a data address space. +This raises some complex issues; for example, writing to an emulated serial +port address might require that an extra routine be called, in order to pass +the data through a real serial port, append it to a log file, etc. To this +end, Starscream defines data address spaces using an array of +STARSCREAM_DATAREGION structures: + + struct STARSCREAM_DATAREGION { + unsigned lowaddr; + unsigned highaddr; + void *memorycall; + void *userdata; + }; + +Each structure contains the low and high addresses in a region, as before. +Rather than simply adding a constant offset to translate a 68K address into +a native one, Starscream offers two different ways to handle accesses to a +data region: + + 1. Call a user-defined handler routine whenever this region is accessed. + + unsigned read_handler(unsigned address); + void write_handler(unsigned address, unsigned data); + + memorycall = pointer to user handler + userdata = unused + + (For some important information about read and write handlers, refer + to section 3.5.) + + 2. Handle accesses internally by reading/writing to an area of native + memory. Don't trap anything. This is ideal for a simple RAM or ROM + area as it requires the least processing. + + memorycall = NULL + userdata = pointer to native memory area where reads or writes + will occur + + NOTE: The native memory area must be byte swapped, same as program + regions are. + +The s68000context fields "s_readbyte", "u_readbyte", "s_writebyte", etc. +should be set to point to arrays of STARSCREAM_DATAREGION structures in order +to define the Supervisor Data and User Data address spaces. Each array may +contain any number of entries, and is terminated by an entry containing -1 +for lowaddr and highaddr, and NULL for memorycall and userdata. + +And now, for an example of address space definition. Consider the following +make-believe memory map: + + 000000-03FFFF: Program ROM + 300000-307FFF: Main RAM + 400000-407FFF: Extra RAM + 800000-81FFFF: Video RAM + A00000-A00007: Sound chip + +Assume that: + * Program ROM is in an array called program_rom + * Main RAM is in an array called main_ram + * Extra RAM is in an array called extra_ram + * Video RAM is in an array called video_ram + * You've set up two routines to write to the sound chip: + void soundchip_writebyte(unsigned address, unsigned data); + void soundchip_writeword(unsigned address, unsigned data); + +The first step is to build the program address space. Program code is +probably only going to be fetched from Program ROM, Main RAM, or Extra RAM. +The address space would thus be defined: + + struct STARSCREAM_PROGRAMREGION pretend_programfetch[] = { + {0x000000, 0x03FFFF, (unsigned)program_rom - 0x000000}, + {0x300000, 0x307FFF, (unsigned)main_ram - 0x300000}, + {0x400000, 0x407FFF, (unsigned)extra_ram - 0x400000}, + {-1, -1, NULL} + }; + +The last entry must be {-1, -1, NULL}. + +The next step is to build the data address space. This is accomplished with +four arrays of STARSCREAM_DATAREGION structures: one for byte reads, word +reads, byte writes, and word writes. For example: + + struct STARSCREAM_DATAREGION pretend_readbyte[] = { + {0x000000, 0x03FFFF, NULL, program_rom}, + {0x300000, 0x307FFF, NULL, main_ram}, + {0x400000, 0x407FFF, NULL, extra_ram}, + {0x800000, 0x81FFFF, NULL, video_ram}, + {-1, -1, NULL, NULL} + }; + + struct STARSCREAM_DATAREGION pretend_readword[] = { + {0x000000, 0x03FFFF, NULL, program_rom}, + {0x300000, 0x307FFF, NULL, main_ram}, + {0x400000, 0x407FFF, NULL, extra_ram}, + {0x800000, 0x81FFFF, NULL, video_ram}, + {-1, -1, NULL, NULL} + }; + + struct STARSCREAM_DATAREGION pretend_writebyte[] = { + {0x300000, 0x307FFF, NULL, main_ram}, + {0x400000, 0x407FFF, NULL, extra_ram}, + {0x800000, 0x81FFFF, NULL, video_ram}, + {0xA00000, 0xA00007, soundchip_writebyte, NULL}, + {-1, -1, NULL, NULL} + }; + + struct STARSCREAM_DATAREGION pretend_writeword[] = { + {0x300000, 0x307FFF, NULL, main_ram}, + {0x400000, 0x407FFF, NULL, extra_ram}, + {0x800000, 0x81FFFF, NULL, video_ram}, + {0xA00000, 0xA00007, soundchip_writeword, NULL}, + {-1, -1, NULL, NULL} + }; + +The last entry of each array must be {-1, -1, NULL, NULL}. + +The above structures take advantage of Starscream's internal handling for the +Program ROM, Main RAM, Extra RAM, and Video RAM, and use the custom handler +when writing to the sound chip. + +Now that you've defined your address spaces, you need to tie it in with the +context (since each CPU can have different address spaces). This is done by +setting the address space pointers (s_fetch, u_fetch, etc.) to point to your +addres space definitions. + + s68000context.s_fetch = pretend_programfetch; + s68000context.u_fetch = pretend_programfetch; + + s68000context.s_readbyte = pretend_readbyte; + s68000context.u_readbyte = pretend_readbyte; + s68000context.s_readword = pretend_readword; + s68000context.u_readword = pretend_readword; + s68000context.s_writebyte = pretend_writebyte; + s68000context.u_writebyte = pretend_writebyte; + s68000context.s_writeword = pretend_writeword; + s68000context.u_writeword = pretend_writeword; + +In this example, the Supervisor and User address spaces are set up to point +to the same definitions. For most 68000-based architectures, this is +correct. + +If you are dynamically allocating memory for your emulated RAM or ROM areas +(using malloc() or a similar function), you will have to set up the address +space definitions at run time. This is left as a trivial exercise for the +reader. + +Veteran users of the UAE 680x0 core might wonder why there is no "readlong" +or "writelong". This is because the real 68000 has a 16-bit data bus, and +therefore breaks up each 32-bit access into two 16-bit accesses. Using +separate handlers for 32-bit accesses is cumbersome and unnecessary. For +speed considerations, Starscream's internal memory read/write handlers access +32 bits at a time wherever possible (using the readword/writeword map). + + +3.4. Executing Code +-------------------- + +Before you execute any code, you must call s68000init(). It only needs to +be called one time. + +Once that's done, and you've set up the memory map, call s68000reset() to +reset the CPU. If everything works, it should read the initial stack pointer +from address 0x000000, and the initial program counter from 0x000004, using +the Supervisor Program address space. (You can verify this by examining +s68000context.areg[7] and s68000context.pc.) + +At this point, you can call the interactive debugger to try disassembling or +stepping through code, and to make sure everything is in the right place. +(see section 3.10 for details) + +To execute 68000 code, call s68000exec(n), where n is the number of cycles. +s68000exec will return one of the following: + + = 0x80000000: Success. + = 0x80000001: Out of range - the program "went off into the weeds". + More specifically, the program jumped to an address which was + not defined in the s_fetch or u_fetch array. + = 0x80000002: Unsupported stack frame (68010+). This happens when an RTE + instruction encounters a stack frame format that hasn't been + implemented (see section 5). + = 0xFFFFFFFF: Double fault. The CPU is dead and will stay dead until it + gets reset again. + < 0x80000000: Invalid instruction. The value returned is the address of + the instruction. For 32-bit addresses, the highest bit is + cut off (s68000context.pc contains the complete address, + however). + +If you get a return code of 0x80000001, 0x80000002, or 0xFFFFFFFF, then the +68000 CPU will be in an unstable state and should be reset. + +The real 68000 generates an exception for illegal instructions. As of v0.26, +this exception is always emulated. You will only get a return code less than +0x80000000 in an unexpected circumstance; upon encountering an invalid +instruction that isn't supposed to be. For example, a RESET instruction will +cause this if the user-defined RESET handler is null (see section 3.9 for +details on RESET handlers). + +Whenever you call s68000exec, it increments the odometer (see section 3.6). + + +3.5. Read and Write Handlers +----------------------------- + +Memory read and write handlers (as described in section 3.3) are a special +case, as they involve Starscream calling your code instead of the other way +around. Since Starscream is not re-entrant, there are some rules which all +read and write handlers must follow. + +1. They must not call any of the following routines: + s68000reset s68000exec + s68000SetContext s68000GetContext + +2. They must not attempt to read or modify s68000context directly. All + data in s68000context is undefined. + +The primary purpose of a read handler is to return data, and the primary +purpose of a write handler is to take data and store it somewhere. However, +read and write handlers do have some control over the emulation process, +beyond the data that they send or receive: + +* You can call s68000interrupt() as much as you like (see section 3.7). + +* You can cause s68000exec to quit early, by calling the + s68000releaseTimeslice() function. This is useful if you need to transfer + control over to another emulated CPU. + +* You can read and/or clear the odometer, with some specialized functions + (see section 3.6). + +* You can read the program counter with s68000readPC(), but it probably + won't be located exactly at the beginning of the instruction. + + +3.6. The Odometer +------------------ + +Every context contains an integer field called "odometer". Whenever you +call s68000exec, the number of elapsed clock cycles is added to +s68000context.odometer. + +Note: When calling s68000exec, the number of elapsed cycles is not +necessarily the same as the number of cycles you specify. Imagine this +scenario: You call s68000exec(100). The next instruction in the code stream +is... + + movem.l ($100000).L,d0-d7/a0-a7 + +s68000exec would quit after that one instruction, returning the success code, +80000000h (assuming nothing else went wrong), and s68000context.odometer +would be incremented by 148. + +You can freely change the odometer between calls to s68000exec, but not from +within read/write handlers (as it's part of the context). If you need to use +the odometer from a read or write handler, there are some specialized +functions for that: + +s68000readOdometer() - Returns the value of the odometer. +s68000tripOdometer() - Returns the value of the odometer, and sets it to + zero in the process. + +s68000controlOdometer(n) - If n==0, it works just like s68000readOdometer. + If n!=0, it works just like s68000tripOdometer. + (We have Neil Bradley to thank for this gem...) + + +3.7. Interrupts +---------------- + +Hardware interrupts can be generated at any time, including within read/write +handlers, by calling s68000interrupt(l, v) where l is the interrupt priority +level, and v is the vector number. Levels 1-7 are valid; vector numbers +0-255 are valid. Vector number -1 means "auto-vectored". -2 will generate a +Spurious Interrupt. + +The interrupt in question will be made pending until the Processor Priority +Level allows it to be processed. You can tell which interrupt levels are +pending, if any, by examining s68000context.interrupts[0]. Bits 1-7 +correspond to interrupt level 1-7; bit 0 is set if the CPU is in a stopped +state (waiting for an interrupt). The vector numbers are stored in +s68000context.interrupts[n] where n is the interrupt level. + +s68000interrupt returns one of the following values: + + 0 The interrupt was added successfully. + 1 The interrupt was not added, because there was already a pending + interrupt at the same level. + 2 The interrupt was not added, because the parameters were invalid. + +Pending interrupts are checked at the following times: + +* s68000exec checks for pending interrupts before executing any code. The + cycles taken by interrupt processing are subtracted from the total "cycle + budget", though s68000exec is still guaranteed to execute at least one + instruction. + +* Interrupts generated from within a read/write, RESET, or BKPT handler will + be checked when the current instruction is finished. + +* You can force a pending interrupt check by calling s68000flushInterrupts. + This has no effect if called from within a read/write, RESET, or BKPT + handler. + + +3.8. Emulating More Than One CPU +--------------------------------- + +If you want to emulate multiple 68000s, you'll need to create a context and a +memory map for each one (see sections 3.2 and 3.3). For example: + + struct S68000CONTEXT myContext[number_of_68000s]; + +When you use your own contexts, it's a good idea to initialize all the bytes +in the new contexts to zero: + + memset (myContext, 0, sizeof(myContext)); + +To use one of your own contexts, you must follow these three steps: + +1. Copy your context into s68000context: + s68000SetContext(myContext); + +2. Use a function which reads or modifies the context - s68000exec, + s68000reset, s68000interrupt, etc. + +3. Copy s68000context back into your context: + s68000GetContext(myContext); + +Expanding on the example in section 3.2 - say you're emulating two 68000s, +and you've set up two contexts for them: + + struct S68000CONTEXT myContext[2]; + +To reset both CPUs, you'd do this: + + for(i = 0; i < 2; i++) { + s68000SetContext(&myContext[i]); + s68000reset(); + s68000GetContext(&myContext[i]); + } + +An emulation loop involving both CPUs might look something like this. (Note: +This is a CRUDE example.) + + while(!done) { + /* Emulate primary 68000 */ + s68000SetContext(&myContext[0]); + s68000exec(100000); + s68000GetContext(&myContext[0]); + + /* Emulate secondary 68000 */ + s68000SetContext(&myContext[1]); + s68000exec(100000); + s68000GetContext(&myContext[1]); + } + +The overhead of copying CPU contexts is compensated by the fact that you can +emulate the CPUs in large timeslices. + + +3.9. RESET and BKPT Instructions +--------------------------------- + +Starscream can call a user-defined function to emulate the RESET instruction, +and to notify when a BKPT instruction is executed. The handlers must take no +arguments, and return void. For example: + + void my_reset_handler(void) { + /* Reset some hardware */ + } + +Note: RESET and BKPT handlers must follow the same rules as memory +read/write handlers (see section 3.5). + +To register a handler function, set the "resethandler" and/or "bkpthandler" +field of the appropriate context to point to the function, i.e.: + + s68000context.resethandler = my_reset_handler; + +You can also set "resethandler" or "bkpthandler" to NULL, in which case: + +* A RESET instruction will cause an Invalid Instruction case. s68000exec + will halt and return its address. + +* A BKPT instruction will behave normally, but without notification. + +Calling s68000readPC() during a RESET or BKPT handler will return the address +directly after the RESET or BKPT instruction. So, to determine the exact +BKPT opcode, you can do this: + + opcode = s68000fetch(s68000readPC() - 2); + + +3.10. Using the Interactive Debugger +------------------------------------- + +Included in the Starscream package is an interactive 68000 cross-debugger and +built in disassembler, with an interface similar to the MS-DOS DEBUG utility. +CPUDEBUG.C contains everything needed for the debugger. If you don't need +it, you can leave out CPUDEBUG.C and CPUDEBUG.H altogether. + +Before using the debugger, make sure to set up your memory map, and call +s68000init() and s68000reset(). + +To start the debugger, call the cpudebug_interactive routine, which is +defined in CPUDEBUG.H as: + + int cpudebug_interactive( + int cpun, + void (*put)(const char*), + void (*get)(char*, int), + void (*execstep)(void), + void (*dump)(void) + ); + +"put", "get", "execstep", and "dump" are all optional - you can pass NULL +values for any or all of them. Their purpose is explained below. + +If you're only emulating one CPU, use a value of 1 for "cpun", and keep +calling cpudebug_interactive until the return value is -1. + +If you're debugging more than one CPU, assign an ID number to each (starting +at 1), including any non-68000 CPUs. Switch to the context of the CPU you +want to debug, and then call cpudebug_interactive with the appropriate ID +number in "cpun". Then, take one of the following actions depending on the +return value: + + -1 Quit + 0 Switch to the next CPU in your list (ID + 1), wrap around if necessary, + and call cpudebug_interactive again. Or, if the CPU in question is not + a 680x0, then use whatever debugger is appropriate. + N Switch to CPU #N. If N is invalid, don't switch. In either case, call + the appropriate debugger. + +While you're at the debug prompt, enter "?" for a list of commands. + +Normally, the interactive debugger uses stdin and stdout for its input and +output. If you need to use another source of input or output, you can write +custom replacement functions for puts() and gets(), and pass their addresses +via "put" and "get". + +Normally, the debugger calls s68000exec() directly to step through each +instruction. If your emulator manages its own timing, you can write a custom +replacement single-step function, and pass its address via "execstep". + +The debugger command 'h' (Hardware dump) will call the function specified by +"dump", if it exists. + + +3.11. Emulating the 68010 +-------------------------- + +To generate a 68010 emulator, use the "-cputype 68010" option when building +your source code file. The names of all identifiers will begin with s68010 +instead of s68000 (unless overridden by the -name option). + +When emulating the 68010, use the S68010CONTEXT structure instead of +S68000CONTEXT. + +S68010CONTEXT has six new fields: + + unsigned char sfc; + unsigned char dfc; + unsigned vbr; + void (*bkpthandler)(void); + unsigned char loopmode; + unsigned char contextfiller10[3]; + +"vbr", "sfc", and "dfc" are control registers. + +"bkpthandler" is a user-defined routine for BKPT notification (see section +3.8). + +"loopmode" is used internally for loop mode timing. (Did I mention the loop +mode timing is insanely accurate?) + +"contextfiller10" is there just to maintain alignment. + +An invalid MOVEC register code will cause s68010exec to return with an +invalid instruction error, pointing to the MOVEC instruction (not the code +itself). + +NOTE: The interactive debugger currently does not support the 68010. + + +----------------------------------------------------------------------------- +4. Tricks of the Trade +----------------------------------------------------------------------------- + +4.1. Inter-CPU Communication +----------------------------- + +Many arcade and console game systems which use multiple CPUs use a sort of +"mailbox" technique to allow the main CPU to send messages to the sub CPU +(sound effect numbers, etc.) + +When one of your 68000s writes to another CPU's mailbox, it's generally a +good idea to transfer control over to the other CPU temporarily. This can be +achieved by calling s68000releaseTimeslice() from your I/O handler. This +will cause s68000exec to exit, even if it's not finished. (Always check the +odometer to see how many cycles were really executed!) + + +4.2. Other Helpful Tips +------------------------ + +When defining your memory map(s): + +* Take advantage of the built-in RAM and ROM handling as much as possible. + They involve much less "red tape" than using your own handlers. + +* The addresses don't have to be in order. You can rearrange them so that + the most commonly-accessed areas are at the beginning. This will shave a + few cycles off each access. + +* If you have two areas of fetchable RAM or ROM that are right next to each + other, consider coalescing them into one area. This will make the memory + map simpler and facilitate fetch region caching. It will also allow the + 680x0 code to wander from one area into the next. Starscream only checks + boundaries after JMP, JSR, RTS, RTR, RTD, RTE, and exceptions. + +When executing code: + +* Instead of calling s68000exec with a fixed number of cycles, keep track of + how many cycles overflowed from the last call to s68000exec, and subtract + them: + + #define TIMESLICE 100000 + + s68000context.odometer = 0; + while(!done) { + if (s68000context.odometer < TIMESLICE) { + s68000exec(TIMESLICE - s68000context.odometer); + } + s68000context.odometer -= TIMESLICE; + } + +* Use big timeslices. The fewer calls you make to s68000exec, the better. + + +4.3. Pitfalls +-------------- + +* Make sure to include "starcpu.h" in any of your C modules that use + Starscream. Also remember that starcpu.h is subject to change in new + versions. (Hint hint.) + +* Remember to call s68000init before executing any code. s68000init doesn't + automatically call s68000reset, so you must call s68000reset also. + +* Remember to set up your memory map before calling s68000reset. The memory + map is required in order to read the initial SSP/PC from the vector table. + +* When you store a context via s68000SetContext, remember to read it back + via s68000GetContext. + +* The interactive debugger can only read memory areas that are defined in + your STARSCREAM_PROGRAMREGION array. Everything else will appear as FFFF. + The upshot of this is that a memory dump is guaranteed not to trigger any + I/O hardware. + +* Simplify your STARSCREAM_PROGRAMREGION map as much as possible, in case + the emulated code decides to wander from one area to another. + +* Remember the rules for read/write handlers (section 3.5), and remember + that they also apply to RESET and BKPT handlers (section 3.9). + +* When you use your own contexts, make sure to explicitly set "resethandler" + and "bkpthandler" to NULL if you're not using them. (This is why it's a + good idea to initialize every byte of a new context to zero.) + + +4.4. Ways to Abuse Starscream +------------------------------ + +For the adventurous... + +* Upon encountering an unrecognized opcode, s68000exec will return the + address of the opcode, instead of the success code, 0x80000000. If you + need to emulate an instruction that's not implemented yet, you can take + advantage of this behavior and implement it in your own code. + + Outside of s68000exec, the context can be modified freely. You can use + the s68000fetch routine to fetch the unrecognized opcode and anything + after it (see section 3.1 for the declaration of s68000fetch). + +* Using 32-bit addresses (-addressbits 32) saves one cycle for every memory + access, and simplifies the PC re-basing process. This is safe only for + software that is "32-bit clean", however. + +* Make a stand-alone 68000 disassembler out of CPUDEBUG.C. ;) + + +4.5. Emulating Other 68K-Series CPUs +------------------------------------- + +Note: None of these are officially supported. + +68008 + Try "-cputype 68000 -addressbits 20" or "-cputype 68000 -addressbits 22", + depending on the chip package. You'll have to lower the clock speed to get + more accurate timing (try dividing it in half), and you might have to + compensate for the 8-bit data bus. + +68EC000 + "-cputype 68000" should work. If it's running in 8-bit mode, try dividing + the clock speed in half. + +SCC68070 + Try "-cputype 68000 -addressbits 32". Not sure about timing issues. + +6833X (CPU32) + Try "-cputype 68010". Timing might be a little slow. A few instructions + aren't supported. + +68020 and higher + Try "-cputype 68010 -addressbits 32". This is a bit of a stretch, though, + since the 68020 supports many new address modes and instructions. Failing + that, wait until official 68020 support is added. ;) + + +----------------------------------------------------------------------------- +5. Known Bugs +----------------------------------------------------------------------------- + +* Address and Bus Errors are not implemented. For arcade game emulation, + this is probably OK, but if you're emulating a home computer system, this + could be cause for concern. + +* The MOVES instruction (68010+) is not implemented. + +* Stack frame format 8 (68010+) is not supported. Starscream will never + generate such a stack frame itself; however, if this format is + encountered during a RTE, s68010exec() will return with an "Unsupported + stack frame" error. + +* There are a few timing inaccuracies: + 68000: DIVS and DIVU: +/- 5% + 68010: MULS and MULU are inaccurate, but I'm not sure by how much. + +* Flags which Motorola documents as "Undefined" are, in fact, undefined. + I could probably look up how they're calculated, and implement them, but + the need has not arisen (yet). + + +----------------------------------------------------------------------------- +6. Credits +----------------------------------------------------------------------------- + +Thanks to: + +* Heinz Seltmann, for letting me borrow his M68000 Microprocessor User's + Manual (Ninth Edition) for way too long. + +* Neil Bradley, Mike Cuddy, James Boulton, Richard Bush, and Dave (of DTMNT/ + DGen fame) for various tips and ideas. + +* Thierry Lescot, who gave me the idea to distribute Starscream in the first + place. diff --git a/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/arm.c b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/arm.c new file mode 100644 index 000000000..2d280927a --- /dev/null +++ b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/arm.c @@ -0,0 +1,1028 @@ +///////////////////////////////////////////////////////////////////////////// +// +// arm - Emulates ARM7DI CPU +// +///////////////////////////////////////////////////////////////////////////// + +#ifndef EMU_COMPILE +#error "Hi I forgot to set EMU_COMPILE" +#endif + +#include "arm.h" + +//int armcount = 0; + +//extern void subtimeon(void); +//extern void subtimeoff(void); +/* +static EMU_INLINE uint64 myrdtsc(void) { + uint64 r; + __asm { + rdtsc + mov dword ptr [r],eax + mov dword ptr [r+4],edx + } + return r; +} + +uint64 armsubtime = 0; +uint64 armsubtimestart = 0; + +static EMU_INLINE void armsubtimeon(void) { armsubtimestart = myrdtsc(); } +static EMU_INLINE void armsubtimeoff(void) { armsubtime += myrdtsc() - armsubtimestart; } +*/ +///////////////////////////////////////////////////////////////////////////// +// +// Static information +// + +// rows: instruction condition field +// columns: values of nzcv +static uint8 condtable[256]; + +// +// initialize condtable +// +static void condtable_init(void) { + uint8 nzcv, cond; + uint8 *table = condtable; + for(nzcv = 0; nzcv < 16; nzcv++) { + for(cond = 0; cond < 16; cond++) { + uint8 n = (nzcv >> 3) & 1; + uint8 z = (nzcv >> 2) & 1; + uint8 c = (nzcv >> 1) & 1; + uint8 v = (nzcv >> 0) & 1; + uint8 truth = 0; + switch(cond & 0xE) { + case 0x0: /* EQ */ truth = z; break; + case 0x2: /* CS */ truth = c; break; + case 0x4: /* MI */ truth = n; break; + case 0x6: /* VS */ truth = v; break; + case 0x8: /* HI */ truth = ((!z) && c); break; + case 0xA: /* GE */ truth = (n == v); break; + case 0xC: /* GT */ truth = ((!z) && (n == v)); break; + case 0xE: /* AL */ truth = 1; break; + } + if(cond & 1) { truth = !truth; } + *table++ = truth ? 1 : 0; + } + } +} + +// +// Static init +// +sint32 EMU_CALL arm_init(void) { +//int i; + condtable_init(); + +//for(i=0;i<256;i++){ +//printf("%d",condtable[i]); +//if((i&15)==15)printf("\n"); +//} + + return 0; +} + +///////////////////////////////////////////////////////////////////////////// + +#define ARMSTATE ((struct ARM_STATE*)(state)) + +#define MODE_USER (0x10) +#define MODE_FIQ (0x11) +#define MODE_IRQ (0x12) +#define MODE_SVC (0x13) +#define MODE_ABT (0x17) +#define MODE_UND (0x1B) +#define MODE_SYSTEM (0x1F) +#define MODE_MASK (0x1F) + +#define PSR_IRQMASK (0x80) +#define PSR_FIQMASK (0x40) + +#define PSR_POS_N (31) +#define PSR_POS_Z (30) +#define PSR_POS_C (29) +#define PSR_POS_V (28) + +#define PSR_NMASK (1<<31) +#define PSR_ZMASK (1<<30) +#define PSR_CMASK (1<<29) +#define PSR_VMASK (1<<28) + +#define EXCEPTION_RESET (0) +#define EXCEPTION_UDEF (1) +#define EXCEPTION_SWI (2) +#define EXCEPTION_PABT (3) +#define EXCEPTION_DABT (4) +#define EXCEPTION_RESERVED (5) +#define EXCEPTION_IRQ (6) +#define EXCEPTION_FIQ (7) + +struct ARM_STATE { + // + // Registers + // + uint32 r[16]; + uint32 rfiq[7]; + uint32 rirq[2]; + uint32 rsvc[2]; + uint32 rabt[2]; + uint32 rund[2]; + uint32 cpsr; // top 4 bits: nzcv + uint32 spsr; + uint32 spsr_fiq; + uint32 spsr_svc; + uint32 spsr_abt; + uint32 spsr_irq; + uint32 spsr_und; + + sint32 cycles_remaining; + sint32 cycles_remaining_last_checkpoint; + + // + // These are REGISTERED EXTERNAL POINTERS. + // + arm_advance_callback_t advance; + void *hwstate; + struct ARM_MEMORY_MAP *map_load; + struct ARM_MEMORY_MAP *map_store; + + // + // The following are TEMPORARY. + // There are no location invariance issues. + // + uint32 maxpc; + void *fetchbase; + uint32 fetchbox; + + int badinsflag; +}; + +uint32 EMU_CALL arm_get_state_size(void) { + return sizeof(struct ARM_STATE); +} + +///////////////////////////////////////////////////////////////////////////// + +static EMU_INLINE void pcchanged(struct ARM_STATE *state) { state->maxpc = 0; } + +///////////////////////////////////////////////////////////////////////////// +// +// Swap registers either to or from their proper places +// +static void regswap(struct ARM_STATE *state) { + uint32 *a, *b, *s, i, n = 0, t; + switch(state->cpsr & MODE_MASK) { + case MODE_FIQ: a = (state->r) + 8; b = state->rfiq; n = 7; s = &(state->spsr_fiq); break; // FIQ + case MODE_IRQ: a = (state->r) + 13; b = state->rirq; n = 2; s = &(state->spsr_irq); break; // IRQ + case MODE_SVC: a = (state->r) + 13; b = state->rsvc; n = 2; s = &(state->spsr_svc); break; // SVC + case MODE_ABT: a = (state->r) + 13; b = state->rabt; n = 2; s = &(state->spsr_abt); break; // ABT + case MODE_UND: a = (state->r) + 13; b = state->rund; n = 2; s = &(state->spsr_und); break; // UND + default: return; + } + for(i = 0; i < n; i++) { t = a[i]; a[i] = b[i]; b[i] = t; } + t = state->spsr; state->spsr = *s; *s = t; +} + +static uint32 getuserreg(struct ARM_STATE *state, uint32 n) { + uint32 mode = state->cpsr & MODE_MASK; + n &= 0xF; + if((n < 8) || (n > 14)) return state->r[n]; + if(mode == MODE_FIQ) return state->rfiq[n - 8]; + if(n < 13) return state->r[n]; + if(mode == MODE_IRQ) return state->rirq[n - 13]; + if(mode == MODE_SVC) return state->rsvc[n - 13]; + if(mode == MODE_ABT) return state->rabt[n - 13]; + if(mode == MODE_UND) return state->rund[n - 13]; + return state->r[n]; +} + +static void setuserreg(struct ARM_STATE *state, uint32 n, uint32 v) { + uint32 mode = state->cpsr & MODE_MASK; + n &= 0xF; + if((n < 8) || (n > 14)) { state->r[n] = v; return; } + if(mode == MODE_FIQ) { state->rfiq[n - 8] = v; return; } + if(n < 13) { state->r[n] = v; return; } + if(mode == MODE_IRQ) { state->rirq[n - 13] = v; return; } + if(mode == MODE_SVC) { state->rsvc[n - 13] = v; return; } + if(mode == MODE_ABT) { state->rabt[n - 13] = v; return; } + if(mode == MODE_UND) { state->rund[n - 13] = v; return; } + state->r[n] = v; return; +} + +static void setcpsr(struct ARM_STATE *state, uint32 psr) { + regswap(state); + state->cpsr = psr & 0xF00000FF; + regswap(state); +} + +static void exception(struct ARM_STATE *state, uint32 n) { + static const uint32 mode_on_entry[8] = { + MODE_SVC, MODE_UND, MODE_SVC, MODE_ABT, + MODE_ABT, 0, MODE_IRQ, MODE_FIQ + }; + static const uint32 lr_offset[8] = { + 0, 4, 4, 4, 8, 0, 4, 4 + }; + uint32 spsr; + n &= 7; + spsr = state->cpsr; + setcpsr(state, ((state->cpsr) & (~(MODE_MASK))) | mode_on_entry[n]); + state->spsr = spsr; + state->r[14] = state->r[15] + lr_offset[n]; + state->r[15] = 4 * n; + if(n == EXCEPTION_FIQ) { state->cpsr |= PSR_FIQMASK; } + if(n == EXCEPTION_IRQ) { state->cpsr |= PSR_IRQMASK; } +} + +///////////////////////////////////////////////////////////////////////////// + +void EMU_CALL arm_clear_state(void *state) { + memset(state, 0, sizeof(struct ARM_STATE)); + exception(ARMSTATE, EXCEPTION_RESET); +} + +///////////////////////////////////////////////////////////////////////////// +// +// Registration of external pointers within the state +// +void EMU_CALL arm_set_memory_maps( + void *state, + struct ARM_MEMORY_MAP *map_load, + struct ARM_MEMORY_MAP *map_store +) { + ARMSTATE->map_load = map_load; + ARMSTATE->map_store = map_store; +} + +void EMU_CALL arm_set_advance_callback( + void *state, + arm_advance_callback_t advance, + void *hwstate +) { + ARMSTATE->advance = advance; + ARMSTATE->hwstate = hwstate; +} + +///////////////////////////////////////////////////////////////////////////// + +uint32 EMU_CALL arm_getreg(void *state, sint32 regnum) { + if(regnum >= ARM_REG_GEN && regnum < (ARM_REG_GEN+16)) { + sint32 n = regnum - ARM_REG_GEN; + return ARMSTATE->r[n]; + } + switch(regnum) { + case ARM_REG_CPSR: return ARMSTATE->cpsr; + case ARM_REG_SPSR: return ARMSTATE->spsr; + } + return 0; +} + +// unimplemented! +//void EMU_CALL arm_setreg(void *state, sint32 regnum, uint32 value) { } + +///////////////////////////////////////////////////////////////////////////// + +void EMU_CALL arm_break(void *state) { + if(ARMSTATE->cycles_remaining <= 0) return; + ARMSTATE->cycles_remaining_last_checkpoint -= ARMSTATE->cycles_remaining; + ARMSTATE->cycles_remaining = 0; +} + +///////////////////////////////////////////////////////////////////////////// +// +// Memory map walker +// +static EMU_INLINE struct ARM_MEMORY_TYPE* mmwalk(struct ARM_MEMORY_MAP *map, uint32 a) { + for(;; map++) { + uint32 x = map->x; + uint32 y = map->y; + if(a < x || a > y) continue; + return &(map->type); + } +} + +///////////////////////////////////////////////////////////////////////////// + +static void hw_sync(struct ARM_STATE *state) { + sint32 d = state->cycles_remaining_last_checkpoint - state->cycles_remaining; + if(d > 0) { state->advance(state->hwstate, d); } + state->cycles_remaining_last_checkpoint = state->cycles_remaining; +} + +///////////////////////////////////////////////////////////////////////////// + +static EMU_INLINE void renew_fetch_region(struct ARM_STATE *state) { + struct ARM_MEMORY_TYPE *t; + state->r[15] &= ~3; + t = mmwalk(state->map_load, state->r[15]); + if(t->n == ARM_MAP_TYPE_POINTER) { + uint32 astart = (state->r[15]) & (~(t->mask)); + state->maxpc = astart + ((t->mask) + 1); + state->fetchbase = ((uint8*)(t->p)) - astart; + } else { + state->maxpc = state->r[15] + 4; + state->fetchbase = ((uint8*)(&(state->fetchbox)))-(state->r[15]); + state->fetchbox = ((arm_load_callback_t)(t->p))(state->hwstate, state->r[15], 0xFFFFFFFF); + } +} + +///////////////////////////////////////////////////////////////////////////// + +static EMU_INLINE uint32 lb(struct ARM_STATE *state, uint32 a) { + struct ARM_MEMORY_TYPE *t; +//armsubtimeon(); + t = mmwalk(state->map_load, a); + a &= t->mask; + if(t->n == ARM_MAP_TYPE_POINTER) { + a ^= EMU_ENDIAN_XOR(3); +//armsubtimeoff(); + return *((uint8*)(((uint8*)(t->p))+a)); + } else { + uint32 sh = (a & 3) * 8; + hw_sync(state); + a = ((arm_load_callback_t)(t->p))(state->hwstate, a & (~3), 0xFF << sh); + a >>= sh; +//armsubtimeoff(); + return a & 0xFF; + } +} + +static EMU_INLINE uint32 lh(struct ARM_STATE *state, uint32 a) { + struct ARM_MEMORY_TYPE *t; + uint32 sh; +//armsubtimeon(); + t = mmwalk(state->map_load, a); + sh = (a & 3) * 8; + a &= t->mask & (~3); + if(t->n == ARM_MAP_TYPE_POINTER) { + a = *((uint32*)(((uint8*)(t->p))+a)); + } else { + hw_sync(state); + a = ((arm_load_callback_t)(t->p))(state->hwstate, a, 0xFFFF << sh); + } + a >>= sh; +//armsubtimeoff(); + return a & 0xFFFF; +} + +static EMU_INLINE uint32 lw(struct ARM_STATE *state, uint32 a) { + struct ARM_MEMORY_TYPE *t; + uint32 sh; +//armsubtimeon(); + t = mmwalk(state->map_load, a); + sh = (a & 3) * 8; + a &= t->mask & (~3); + if(t->n == ARM_MAP_TYPE_POINTER) { + a = *((uint32*)(((uint8*)(t->p))+a)); + } else { + hw_sync(state); + a = ((arm_load_callback_t)(t->p))(state->hwstate, a, 0xFFFFFFFF); + } +//armsubtimeoff(); + return a >> sh; +} + +static EMU_INLINE void sb(struct ARM_STATE *state, uint32 a, uint32 d) { + struct ARM_MEMORY_TYPE *t; +//armsubtimeon(); + t = mmwalk(state->map_store, a); + a &= t->mask; + if(t->n == ARM_MAP_TYPE_POINTER) { + a ^= EMU_ENDIAN_XOR(3); + *((uint8*)(((uint8*)(t->p))+a)) = d; + } else { + uint32 sh = (a & 3) * 8; + hw_sync(state); + d &= 0xFF; + ((arm_store_callback_t)(t->p))(state->hwstate, a & (~3), d << sh, 0xFF << sh); + } +//armsubtimeoff(); +} + +static EMU_INLINE void sh(struct ARM_STATE *state, uint32 a, uint32 d) { + struct ARM_MEMORY_TYPE *t; + uint32 sh; +//armsubtimeon(); + t = mmwalk(state->map_store, a); + sh = (a & 3) * 8; + a &= t->mask & (~3); + d &= 0xFFFF; + if(t->n == ARM_MAP_TYPE_POINTER) { + *((uint32*)(((uint8*)(t->p))+a)) &= ~(0xFFFF << sh); + *((uint32*)(((uint8*)(t->p))+a)) |= (d << sh); + } else { + hw_sync(state); + ((arm_store_callback_t)(t->p))(state->hwstate, a, d << sh, 0xFFFF << sh); + } +//armsubtimeoff(); +} + +static EMU_INLINE void sw(struct ARM_STATE *state, uint32 a, uint32 d) { + struct ARM_MEMORY_TYPE *t; + uint32 sh; +//armsubtimeon(); + t = mmwalk(state->map_store, a); + sh = (a & 3) * 8; + a &= t->mask & (~3); + if(t->n == ARM_MAP_TYPE_POINTER) { + *((uint32*)(((uint8*)(t->p))+a)) &= ~(0xFFFFFFFF << sh); + *((uint32*)(((uint8*)(t->p))+a)) |= (d << sh); + } else { + hw_sync(state); + ((arm_store_callback_t)(t->p))(state->hwstate, a, d << sh, 0xFFFFFFFF << sh); + } +//armsubtimeoff(); +} + +static EMU_INLINE uint32 fetch(struct ARM_STATE *state) { + if(state->r[15] >= state->maxpc) renew_fetch_region(state); + return *((uint32*)(((uint8*)(state->fetchbase))+(state->r[15]))); +} + +///////////////////////////////////////////////////////////////////////////// + +static void EMU_CALL badins(struct ARM_STATE *state, uint32 insword) { +//armcount++; + state->badinsflag = 1; + arm_break(state); +} + +///////////////////////////////////////////////////////////////////////////// + +#define IFIELD(B,N) ((insword>>(B))&((1<<(N))-1)) +#define WRITESTATUS(N) (((N)&1)!=0) +#define ISLOGIC(N) ((((N)&0x0C)==0x00)||(((N)&0x18)==0x18)) + +#define C_TO_CPSR { state->cpsr &= ~PSR_CMASK; state->cpsr |= (c&1) << PSR_POS_C; } +#define GET_NZ_TO_CPSR(V) { state->cpsr &= ~((PSR_NMASK)|(PSR_ZMASK)); state->cpsr |= ((V)&0x80000000) | (((uint32)((V)==0))<<(PSR_POS_Z)); } + +#define DATAOP(N) (((N)>>1)&0xF) + +#define DATA_AND (0x0) +#define DATA_EOR (0x1) +#define DATA_SUB (0x2) +#define DATA_RSB (0x3) +#define DATA_ADD (0x4) +#define DATA_ADC (0x5) +#define DATA_SBC (0x6) +#define DATA_RSC (0x7) +#define DATA_TST (0x8) +#define DATA_TEQ (0x9) +#define DATA_CMP (0xA) +#define DATA_CMN (0xB) +#define DATA_ORR (0xC) +#define DATA_MOV (0xD) +#define DATA_BIC (0xE) +#define DATA_MVN (0xF) + +///////////////////////////////////////////////////////////////////////////// +// +// Template for a Data Processing instruction (0x00-0x3F in the list) +// +#define INSDATA(N) \ +static void EMU_CALL insdata##N(struct ARM_STATE *state, uint32 insword) { \ + uint32 v, c; \ + uint32 result, operand1, operand2; \ + uint32 rd; \ + /* */ \ + /* Special-case check for nonstandard data processing instructions */ \ + /* */ \ + if(!(N & 0x20)) { \ + /* */ \ + /* Multiply/swap */ \ + /* */ \ + if((insword & 0xF0) == 0x90) { \ + /* */ \ + /* MUL, MLA */ \ + /* */ \ + if((N & 0xFC) == 0x00) { \ + state->r[15] += 8; \ + rd = IFIELD(16,4); \ + result = state->r[IFIELD(0,4)] * state->r[IFIELD(8,4)]; \ + if(N & 2) result += state->r[IFIELD(12,4)]; \ + /* set N and Z here if we want them */ \ + if(WRITESTATUS(N)) { GET_NZ_TO_CPSR(result); } \ + state->r[15] -= 4; \ + state->r[rd] = result; \ + if(rd == 15) pcchanged(state); \ + return; \ + /* */ \ + /* Multiply Long */ \ + /* */ \ + } else if((N & 0xF8) == 0x08) { \ + badins(state, insword); return; \ + /* */ \ + /* Single Data Swap */ \ + /* */ \ + } else if((N & 0xFB) == 0x10) { \ + badins(state, insword); return; \ + } else { \ + badins(state, insword); return; \ + } \ + /* */ \ + /* Load/store halfword */ \ + /* */ \ + } else if((insword & 0x90) == 0x90) { \ + badins(state, insword); return; \ + } \ + } \ + /* */ \ + /* check here for MSR / MRS */ \ + /* */ \ + if((N & 0x19) == 0x10) { \ + if((insword & 0x0FFF0FFF) == 0x010F0000) { \ + state->r[15] += 4; \ + rd = IFIELD(12, 4); \ + if(rd != 15) state->r[rd] = state->cpsr; \ + return; \ + } \ + if((insword & 0x0FFF0FFF) == 0x014F0000) { \ + state->r[15] += 4; \ + rd = IFIELD(12, 4); \ + if(rd != 15) state->r[rd] = state->spsr; \ + return; \ + } \ + if((insword & 0x0FFFFFF0) == 0x0129F000) { \ + state->r[15] += 8; \ + setcpsr(state, state->r[IFIELD(0,4)]); \ + state->r[15] -= 4; \ + arm_break(state); \ + return; \ + } \ + if((insword & 0x0FFFFFF0) == 0x0169F000) { \ + state->r[15] += 8; \ + state->spsr = state->r[IFIELD(0,4)]; \ + state->r[15] -= 4; \ + return; \ + } \ + if((insword & 0x0FFFFFF0) == 0x0128F000) { \ + uint32 src; \ + state->r[15] += 8; \ + src = state->r[IFIELD(0,4)]; \ + state->r[15] -= 4; \ + state->cpsr &= 0x0FFFFFFF; \ + state->cpsr |= (src & 0xF0000000); \ + return; \ + } \ + if((insword & 0x0FFFFFF0) == 0x0168F000) { \ + uint32 src; \ + state->r[15] += 8; \ + src = state->r[IFIELD(0,4)]; \ + state->r[15] -= 4; \ + state->spsr &= 0x0FFFFFFF; \ + state->spsr |= (src & 0xF0000000); \ + return; \ + } \ + if((insword & 0x0FFFF000) == 0x0328F000) { \ + uint32 src = IFIELD(0,8); \ + uint32 ror = IFIELD(8,4) * 2; \ + src = (src >> ror) | (src << (32-ror)); \ + state->cpsr &= 0x0FFFFFFF; \ + state->cpsr |= (src & 0xF0000000); \ + return; \ + } \ + if((insword & 0x0FFFF000) == 0x0368F000) { \ + uint32 src = IFIELD(0,8); \ + uint32 ror = IFIELD(8,4) * 2; \ + src = (src >> ror) | (src << (32-ror)); \ + state->spsr &= 0x0FFFFFFF; \ + state->spsr |= (src & 0xF0000000); \ + return; \ + } \ + } \ + /* */ \ + /* from this point forward, everything is just normal data */ \ + /* */ \ + state->r[15] += 8; \ + /* */ \ + /* Get operand 2 */ \ + /* */ \ + if(!(N & 0x20)) { \ + operand2 = state->r[IFIELD(0,4)]; \ + /* shift */ \ + /* rrx is a special case */ \ + if((insword & 0xFF0) == 0x060) { \ + c = operand2 & 1; \ + operand2 = (operand2 >> 1) | ((state->cpsr << 2) & 0x80000000); \ + if(WRITESTATUS(N) && ISLOGIC(N)) { C_TO_CPSR; } \ + } else { \ + uint8 shiftby; \ + if((insword & 0x10) == 0) { \ + shiftby = IFIELD(7,5); \ + shiftby |= ((shiftby == 0) & ((insword & 0x60) != 0)) << 5; \ + } else { \ + shiftby = state->r[IFIELD(8,4)]; \ + } \ + if(shiftby) { \ + switch(IFIELD(5,2)) { \ + case 0: /* LSL */ \ + if(WRITESTATUS(N) && ISLOGIC(N)) { \ + if(shiftby > 32) { c = 0; } else { c = operand2 >> (32-shiftby); } \ + C_TO_CPSR; \ + } \ + operand2 <<= shiftby; \ + break; \ + case 1: /* LSR */ \ + if(WRITESTATUS(N) && ISLOGIC(N)) { \ + if(shiftby > 32) { c = 0; } else { c = operand2 >> (shiftby-1); } \ + C_TO_CPSR; \ + } \ + operand2 >>= shiftby; \ + break; \ + case 2: /* ASR */ \ + if(WRITESTATUS(N) && ISLOGIC(N)) { \ + if(shiftby >= 32) { c = operand2 >> 31; } else { c = operand2 >> (shiftby-1); } \ + C_TO_CPSR; \ + } \ + operand2 = ((sint32)(((sint32)operand2) >> shiftby)); \ + break; \ + case 3: /* ROR */ \ + if(WRITESTATUS(N) && ISLOGIC(N)) { \ + c = operand2 >> ((shiftby-1)&31); \ + C_TO_CPSR; \ + } \ + shiftby &= 31; \ + operand2 = (operand2 >> shiftby) | (operand2 << (32-shiftby)); \ + break; \ + } \ + } \ + } \ + } else { \ + uint32 ror = IFIELD(8,4) * 2; \ + operand2 = IFIELD(0,8); \ + operand2 = (operand2 >> ror) | (operand2 << (32 - ror)); \ + } \ + /* */ \ + /* Do stuff depending on the instruction */ \ + /* */ \ + /* for anything except MOV and MVN, we want operand1 */ \ + if(DATAOP(N) != DATA_MOV && DATAOP(N) != DATA_MVN) { \ + operand1 = state->r[IFIELD(16,4)]; \ + } \ + if(DATAOP(N) == DATA_MOV) { result = operand2; \ + } else if(DATAOP(N) == DATA_MVN) { result = operand2 ^ 0xFFFFFFFF; \ + } else if(DATAOP(N) == DATA_AND) { result = operand1 & operand2; \ + } else if(DATAOP(N) == DATA_TST) { result = operand1 & operand2; \ + } else if(DATAOP(N) == DATA_EOR) { result = operand1 ^ operand2; \ + } else if(DATAOP(N) == DATA_TEQ) { result = operand1 ^ operand2; \ + } else if(DATAOP(N) == DATA_ORR) { result = operand1 | operand2; \ + } else if(DATAOP(N) == DATA_BIC) { result = operand1 & (~operand2); \ + /* */ \ + /* (moving on to the arithmetic instructions) */ \ + /* */ \ + /* ADD and CMN and ADC */ \ + } else if( \ + DATAOP(N)==DATA_ADD || \ + DATAOP(N)==DATA_CMN || \ + DATAOP(N)==DATA_ADC \ + ) { \ + result = operand1 + operand2; \ + if(DATAOP(N)==DATA_ADC) result += (((state->cpsr) >> PSR_POS_C) & 1); \ + if(WRITESTATUS(N)) { \ + v = ((operand2^result)&(~(operand1^operand2))) >> 31; \ + c = (result^((operand1^operand2)|(operand2^result))) >> 31; \ + state->cpsr &= ~((PSR_CMASK)|(PSR_VMASK)); \ + state->cpsr |= v << PSR_POS_V; \ + state->cpsr |= c << PSR_POS_C; \ + } \ + /* SUB and RSB and CMP and SBC and RSC */ \ + } else if( \ + DATAOP(N)==DATA_SUB || \ + DATAOP(N)==DATA_RSB || \ + DATAOP(N)==DATA_CMP || \ + DATAOP(N)==DATA_SBC || \ + DATAOP(N)==DATA_RSC \ + ) { \ + /* swap for RSB and RSC */ \ + if(DATAOP(N)==DATA_RSB || DATAOP(N)==DATA_RSC) { \ + result = operand1; operand1 = operand2; operand2 = result; } \ + result = operand1 - operand2; \ + /* carry where needed */ \ + if(DATAOP(N)==DATA_SBC || DATAOP(N)==DATA_RSC) { \ + result += (((state->cpsr) >> PSR_POS_C) & 1); \ + result--; \ + } \ + if(WRITESTATUS(N)) { \ + v = ((operand2^operand1)&(~(operand2^result))) >> 31; \ + c = (~(operand1^((operand2^operand1)|(operand1^result)))) >> 31; \ + state->cpsr &= ~((PSR_CMASK)|(PSR_VMASK)); \ + state->cpsr |= v << PSR_POS_V; \ + state->cpsr |= c << PSR_POS_C; \ + } \ + } \ + /* set N and Z here if we want them */ \ + if(WRITESTATUS(N)) { GET_NZ_TO_CPSR(result); } \ + /* it's safe to decrement the program counter again here */ \ + state->r[15] -= 4; \ + /* write results to the destination register if applicable */ \ + if((N & 0x18) != 0x10) { \ + uint32 rd = IFIELD(12,4); \ + state->r[rd] = result; \ + /* if the destination reg was the PC: */ \ + if(rd == 15) { \ + /* force fetch base recalculation */ \ + pcchanged(state); \ + /* and also, if S was set, return from exception */ \ + if(WRITESTATUS(N)) { \ + setcpsr(state, state->spsr); \ + arm_break(state); \ + } \ + } \ + } \ +} + +///////////////////////////////////////////////////////////////////////////// + +INSDATA(0x00) INSDATA(0x01) INSDATA(0x02) INSDATA(0x03) INSDATA(0x04) INSDATA(0x05) INSDATA(0x06) INSDATA(0x07) +INSDATA(0x08) INSDATA(0x09) INSDATA(0x0A) INSDATA(0x0B) INSDATA(0x0C) INSDATA(0x0D) INSDATA(0x0E) INSDATA(0x0F) +INSDATA(0x10) INSDATA(0x11) INSDATA(0x12) INSDATA(0x13) INSDATA(0x14) INSDATA(0x15) INSDATA(0x16) INSDATA(0x17) +INSDATA(0x18) INSDATA(0x19) INSDATA(0x1A) INSDATA(0x1B) INSDATA(0x1C) INSDATA(0x1D) INSDATA(0x1E) INSDATA(0x1F) +INSDATA(0x20) INSDATA(0x21) INSDATA(0x22) INSDATA(0x23) INSDATA(0x24) INSDATA(0x25) INSDATA(0x26) INSDATA(0x27) +INSDATA(0x28) INSDATA(0x29) INSDATA(0x2A) INSDATA(0x2B) INSDATA(0x2C) INSDATA(0x2D) INSDATA(0x2E) INSDATA(0x2F) +INSDATA(0x30) INSDATA(0x31) INSDATA(0x32) INSDATA(0x33) INSDATA(0x34) INSDATA(0x35) INSDATA(0x36) INSDATA(0x37) +INSDATA(0x38) INSDATA(0x39) INSDATA(0x3A) INSDATA(0x3B) INSDATA(0x3C) INSDATA(0x3D) INSDATA(0x3E) INSDATA(0x3F) + +///////////////////////////////////////////////////////////////////////////// +// +// Template for a Single Data Transfer instruction (0x40-0x7F in the list) +// +#define SDT_I(N) (((N)>>5)&1) +#define SDT_P(N) (((N)>>4)&1) +#define SDT_U(N) (((N)>>3)&1) +#define SDT_B(N) (((N)>>2)&1) +#define SDT_W(N) (((N)>>1)&1) +#define SDT_L(N) (((N)>>0)&1) + +#define INSSDT(N) \ +static void EMU_CALL inssdt##N(struct ARM_STATE *state, uint32 insword) { \ + uint32 rn = IFIELD(16,4); \ + uint32 rd = IFIELD(12,4); \ + uint32 address, offset; \ + /* PC is advanced by 8 here */ \ + state->r[15] += 8; \ + /* get base address */ \ + address = state->r[rn]; \ + /* get offset */ \ + if(!(SDT_I(N))) { \ + offset = insword & 0xFFF; \ + } else { \ + offset = state->r[IFIELD(0,4)]; \ + /* shift */ \ + /* rrx is a special case */ \ + if((insword & 0xFF0) == 0x060) { \ + offset = (offset >> 1) | ((state->cpsr << 2) & 0x80000000); \ + } else { \ + uint8 shiftby = IFIELD(7,5); \ + shiftby |= ((shiftby == 0) & ((insword & 0x60) != 0)) << 5; \ + if(shiftby) { \ + switch(IFIELD(5,2)) { \ + case 0: /* LSL */ offset <<= shiftby; break; \ + case 1: /* LSR */ offset >>= shiftby; break; \ + case 2: /* ASR */ offset = ((sint32)(((sint32)offset) >> shiftby)); break; \ + case 3: /* ROR */ \ + shiftby &= 31; \ + offset = (offset >> shiftby) | (offset << (32-shiftby)); \ + break; \ + } \ + } \ + } \ + } \ + if(( SDT_P(N))) { if(SDT_U(N)) { address += offset; } else { address -= offset; } } \ + if(SDT_L(N)) { \ + if(SDT_B(N)) { state->r[rd] = (uint8 )lb(state, address); } \ + else { state->r[rd] = (uint32)lw(state, address); } \ + if(rd == 15) { state->r[15] += 4; pcchanged(state); } \ + } else { \ + if(SDT_B(N)) { sb(state, address, state->r[rd] & 0xFF); } \ + else { sw(state, address, state->r[rd] ); } \ + } \ + if((!SDT_P(N))) { if(SDT_U(N)) { address += offset; } else { address -= offset; } } \ + /* remember: post implies writeback */ \ + if((!SDT_P(N)) || SDT_W(N)) { state->r[rn] = address; } \ + state->r[15] -= 4; \ +} + +///////////////////////////////////////////////////////////////////////////// + +INSSDT(0x40) INSSDT(0x41) INSSDT(0x42) INSSDT(0x43) INSSDT(0x44) INSSDT(0x45) INSSDT(0x46) INSSDT(0x47) +INSSDT(0x48) INSSDT(0x49) INSSDT(0x4A) INSSDT(0x4B) INSSDT(0x4C) INSSDT(0x4D) INSSDT(0x4E) INSSDT(0x4F) +INSSDT(0x50) INSSDT(0x51) INSSDT(0x52) INSSDT(0x53) INSSDT(0x54) INSSDT(0x55) INSSDT(0x56) INSSDT(0x57) +INSSDT(0x58) INSSDT(0x59) INSSDT(0x5A) INSSDT(0x5B) INSSDT(0x5C) INSSDT(0x5D) INSSDT(0x5E) INSSDT(0x5F) +INSSDT(0x60) INSSDT(0x61) INSSDT(0x62) INSSDT(0x63) INSSDT(0x64) INSSDT(0x65) INSSDT(0x66) INSSDT(0x67) +INSSDT(0x68) INSSDT(0x69) INSSDT(0x6A) INSSDT(0x6B) INSSDT(0x6C) INSSDT(0x6D) INSSDT(0x6E) INSSDT(0x6F) +INSSDT(0x70) INSSDT(0x71) INSSDT(0x72) INSSDT(0x73) INSSDT(0x74) INSSDT(0x75) INSSDT(0x76) INSSDT(0x77) +INSSDT(0x78) INSSDT(0x79) INSSDT(0x7A) INSSDT(0x7B) INSSDT(0x7C) INSSDT(0x7D) INSSDT(0x7E) INSSDT(0x7F) + +///////////////////////////////////////////////////////////////////////////// +// +// Template for a Block Data Transfer instruction (0x80-0x9F in the list) +// +#define BDT_P(N) (((N)>>4)&1) +#define BDT_U(N) (((N)>>3)&1) +#define BDT_S(N) (((N)>>2)&1) +#define BDT_W(N) (((N)>>1)&1) +#define BDT_L(N) (((N)>>0)&1) + +#define INSBDT(N) \ +static void EMU_CALL insbdt##N(struct ARM_STATE *state, uint32 insword) { \ + uint32 address = state->r[IFIELD(16,4)]; \ + uint32 rfe = 0; \ + sint32 r = 0; \ + sint32 rend = 16; \ + sint32 rstep = 1; \ + /* R15 is stored as +12 - we can restore later if necessary */ \ + state->r[15] += 12; \ + /* count registers backwards if decrementing */ \ + if(!(BDT_U(N))) { r=15; rend=-1; rstep=-1; } \ + for(; r!=rend; r+=rstep) if((insword>>r)&1) { \ + if(( BDT_P(N))) { if(BDT_U(N)) { address += 4; } else { address -= 4; } } \ + if(BDT_L(N)) { \ + if(BDT_S(N)) { \ + if((insword&0x8000)==0) { setuserreg(state, r, lw(state, address)); } \ + else { state->r[r] = lw(state, address); } \ + } else { \ + state->r[r] = lw(state, address); \ + } \ + /* if we just loaded the PC: */ \ + if(r == 15) { \ + /* adjust for it */ \ + state->r[15] += 8; pcchanged(state); \ + /* also if S is set, return from exception */ \ + if(BDT_S(N)) { \ + rfe = 1; \ + } \ + } \ + } else { \ + if(BDT_S(N)) { sw(state, address, getuserreg(state, r)); } \ + else { sw(state, address, state->r[r]); } \ + } \ + if((!BDT_P(N))) { if(BDT_U(N)) { address += 4; } else { address -= 4; } } \ + } \ + if(BDT_W(N)) { state->r[IFIELD(16,4)] = address; if(IFIELD(16,4)==15) pcchanged(state); } \ + state->r[15] -= 8; \ + if(rfe) { \ + setcpsr(state, state->spsr); \ + arm_break(state); \ + } \ +} + +///////////////////////////////////////////////////////////////////////////// + +INSBDT(0x80) INSBDT(0x81) INSBDT(0x82) INSBDT(0x83) INSBDT(0x84) INSBDT(0x85) INSBDT(0x86) INSBDT(0x87) +INSBDT(0x88) INSBDT(0x89) INSBDT(0x8A) INSBDT(0x8B) INSBDT(0x8C) INSBDT(0x8D) INSBDT(0x8E) INSBDT(0x8F) +INSBDT(0x90) INSBDT(0x91) INSBDT(0x92) INSBDT(0x93) INSBDT(0x94) INSBDT(0x95) INSBDT(0x96) INSBDT(0x97) +INSBDT(0x98) INSBDT(0x99) INSBDT(0x9A) INSBDT(0x9B) INSBDT(0x9C) INSBDT(0x9D) INSBDT(0x9E) INSBDT(0x9F) + +///////////////////////////////////////////////////////////////////////////// + +static void EMU_CALL insbranch(struct ARM_STATE *state, uint32 insword) { + insword <<= 8; + insword = ((sint32)(((sint32)insword) >> 6)); + state->r[15] += 8 + insword; + pcchanged(state); +} + +static void EMU_CALL insbranchlink(struct ARM_STATE *state, uint32 insword) { + state->r[14] = state->r[15] + 4; + insword <<= 8; + insword = ((sint32)(((sint32)insword) >> 6)); + state->r[15] += 8 + insword; + pcchanged(state); +} + +///////////////////////////////////////////////////////////////////////////// + +typedef void (EMU_CALL *inscallback)(struct ARM_STATE *state, uint32 insword); + +static inscallback inscalltable[256] = { +// 00 + insdata0x00,insdata0x01,insdata0x02,insdata0x03,insdata0x04,insdata0x05,insdata0x06,insdata0x07, + insdata0x08,insdata0x09,insdata0x0A,insdata0x0B,insdata0x0C,insdata0x0D,insdata0x0E,insdata0x0F, +// 10 + insdata0x10,insdata0x11,insdata0x12,insdata0x13,insdata0x14,insdata0x15,insdata0x16,insdata0x17, + insdata0x18,insdata0x19,insdata0x1A,insdata0x1B,insdata0x1C,insdata0x1D,insdata0x1E,insdata0x1F, +// 20 + insdata0x20,insdata0x21,insdata0x22,insdata0x23,insdata0x24,insdata0x25,insdata0x26,insdata0x27, + insdata0x28,insdata0x29,insdata0x2A,insdata0x2B,insdata0x2C,insdata0x2D,insdata0x2E,insdata0x2F, +// 30 + insdata0x30,insdata0x31,insdata0x32,insdata0x33,insdata0x34,insdata0x35,insdata0x36,insdata0x37, + insdata0x38,insdata0x39,insdata0x3A,insdata0x3B,insdata0x3C,insdata0x3D,insdata0x3E,insdata0x3F, +// 40 + inssdt0x40,inssdt0x41,inssdt0x42,inssdt0x43,inssdt0x44,inssdt0x45,inssdt0x46,inssdt0x47, + inssdt0x48,inssdt0x49,inssdt0x4A,inssdt0x4B,inssdt0x4C,inssdt0x4D,inssdt0x4E,inssdt0x4F, +// 50 + inssdt0x50,inssdt0x51,inssdt0x52,inssdt0x53,inssdt0x54,inssdt0x55,inssdt0x56,inssdt0x57, + inssdt0x58,inssdt0x59,inssdt0x5A,inssdt0x5B,inssdt0x5C,inssdt0x5D,inssdt0x5E,inssdt0x5F, +// 60 + inssdt0x60,inssdt0x61,inssdt0x62,inssdt0x63,inssdt0x64,inssdt0x65,inssdt0x66,inssdt0x67, + inssdt0x68,inssdt0x69,inssdt0x6A,inssdt0x6B,inssdt0x6C,inssdt0x6D,inssdt0x6E,inssdt0x6F, +// 70 + inssdt0x70,inssdt0x71,inssdt0x72,inssdt0x73,inssdt0x74,inssdt0x75,inssdt0x76,inssdt0x77, + inssdt0x78,inssdt0x79,inssdt0x7A,inssdt0x7B,inssdt0x7C,inssdt0x7D,inssdt0x7E,inssdt0x7F, +// 80 + insbdt0x80,insbdt0x81,insbdt0x82,insbdt0x83,insbdt0x84,insbdt0x85,insbdt0x86,insbdt0x87, + insbdt0x88,insbdt0x89,insbdt0x8A,insbdt0x8B,insbdt0x8C,insbdt0x8D,insbdt0x8E,insbdt0x8F, +// 90 + insbdt0x90,insbdt0x91,insbdt0x92,insbdt0x93,insbdt0x94,insbdt0x95,insbdt0x96,insbdt0x97, + insbdt0x98,insbdt0x99,insbdt0x9A,insbdt0x9B,insbdt0x9C,insbdt0x9D,insbdt0x9E,insbdt0x9F, +// A0 + insbranch,insbranch,insbranch,insbranch,insbranch,insbranch,insbranch,insbranch, + insbranch,insbranch,insbranch,insbranch,insbranch,insbranch,insbranch,insbranch, +// B0 + insbranchlink,insbranchlink,insbranchlink,insbranchlink,insbranchlink,insbranchlink,insbranchlink,insbranchlink, + insbranchlink,insbranchlink,insbranchlink,insbranchlink,insbranchlink,insbranchlink,insbranchlink,insbranchlink, +// C0 + badins,badins,badins,badins,badins,badins,badins,badins, + badins,badins,badins,badins,badins,badins,badins,badins, +// D0 + badins,badins,badins,badins,badins,badins,badins,badins, + badins,badins,badins,badins,badins,badins,badins,badins, +// E0 + badins,badins,badins,badins,badins,badins,badins,badins, + badins,badins,badins,badins,badins,badins,badins,badins, +// F0 + badins,badins,badins,badins,badins,badins,badins,badins, + badins,badins,badins,badins,badins,badins,badins,badins +}; + +///////////////////////////////////////////////////////////////////////////// +// +// Returns 0 or positive on success +// Returns negative on error +// (value is otherwise meaningless for now) +// +sint32 EMU_CALL arm_execute(void *state, sint32 cycles, uint8 fiq) { + uint32 instruction; +//cycles=1; + // + // a lot of checks are done here at the beginning. + // and nowhere else, really, because it expects that it'll arm_break() if + // anything groovy happens that would involve these checks + // +//armcount=(uint32)(ARMSTATE); + +//armcount++; + // + // check for a bad instruction (from last time around) + // + if(ARMSTATE->badinsflag) { return -1; } + + ARMSTATE->cycles_remaining_last_checkpoint = cycles; + ARMSTATE->cycles_remaining = cycles; + + // + // check for pending interrupts + // + // if FIQ unmasked: + if((ARMSTATE->cpsr & PSR_FIQMASK) == 0) { + // if there's a FIQ set and we can enter it, do so + if(fiq) { + exception(ARMSTATE, EXCEPTION_FIQ); + ARMSTATE->cycles_remaining -= 2; + } + } + + // + // This guarantees location invariance on fetchbox/fetchbase + // + ARMSTATE->maxpc = 0; + + while(ARMSTATE->cycles_remaining > 0) { +//armsubtimeon(); + // hw_sync(state); + +//armcount++; + + instruction = fetch(ARMSTATE); + +//armcount = (uint32)(ARMSTATE->maxpc); + +//armsubtimeoff(); +//printf("%08X: %08X\n",ARMSTATE->r[15], instruction); + + // instruction may be skipped due to condition + if(!condtable[(instruction >> 28) + ((ARMSTATE->cpsr) >> 24)]) { + ARMSTATE->r[15] += 4; + ARMSTATE->cycles_remaining -= 2; + continue; + } +//armsubtimeon(); + inscalltable[(instruction>>20)&0xFF](ARMSTATE, instruction); +//armsubtimeoff(); + + ARMSTATE->cycles_remaining -= 2; + } + + // + // finishing sync + // + hw_sync(state); + + if(ARMSTATE->badinsflag) { return -1; } + + return 0; +} + +///////////////////////////////////////////////////////////////////////////// diff --git a/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/arm.h b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/arm.h new file mode 100644 index 000000000..277155220 --- /dev/null +++ b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/arm.h @@ -0,0 +1,62 @@ +///////////////////////////////////////////////////////////////////////////// +// +// arm - Emulates ARM7DI CPU +// +///////////////////////////////////////////////////////////////////////////// + +#ifndef __SEGA_ARM_H__ +#define __SEGA_ARM_H__ + +#include "emuconfig.h" + +#ifdef __cplusplus +extern "C" { +#endif + +sint32 EMU_CALL arm_init(void); +uint32 EMU_CALL arm_get_state_size(void); +void EMU_CALL arm_clear_state(void *state); + +typedef uint32 (EMU_CALL * arm_load_callback_t )(void *hwstate, uint32 a, uint32 dmask); +typedef void (EMU_CALL * arm_store_callback_t )(void *hwstate, uint32 a, uint32 d, uint32 dmask); +typedef void (EMU_CALL * arm_advance_callback_t)(void *hwstate, uint32 cycles); + +struct ARM_MEMORY_TYPE { uint32 mask, n; void *p; }; +struct ARM_MEMORY_MAP { uint32 x, y; struct ARM_MEMORY_TYPE type; }; +#define ARM_MAP_TYPE_POINTER (0) +#define ARM_MAP_TYPE_CALLBACK (1) + +void EMU_CALL arm_set_memory_maps( + void *state, + struct ARM_MEMORY_MAP *map_load, + struct ARM_MEMORY_MAP *map_store +); +void EMU_CALL arm_set_advance_callback( + void *state, + arm_advance_callback_t advance, + void *hwstate +); + +#define ARM_REG_GEN ( 0) +#define ARM_REG_CPSR (16) +#define ARM_REG_SPSR (17) +#define ARM_REG_MAX (18) + +uint32 EMU_CALL arm_getreg(void *state, sint32 regnum); +void EMU_CALL arm_setreg(void *state, sint32 regnum, uint32 value); + +void EMU_CALL arm_break(void *state); + +// +// Returns 0 or positive on success +// Returns negative on error +// (value is otherwise meaningless for now) +// Performs all advance calls according to how many cycles it actually executed +// +sint32 EMU_CALL arm_execute(void *state, sint32 cycles, uint8 fiq); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68k.c b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68k.c new file mode 100644 index 000000000..3de166f21 --- /dev/null +++ b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68k.c @@ -0,0 +1,315 @@ +/* Copyright 2003-2004 Stephane Dallongeville + + This file is part of Yabause. + + Yabause is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + Yabause is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with Yabause; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +/********************************************************************************* + * + * C68K (68000 CPU emulator) version 0.80 + * Compiled with Dev-C++ + * Copyright 2003-2004 Stephane Dallongeville + * + ********************************************************************************/ + +#include +#include + +#include "c68k.h" + +// include macro file +////////////////////// + +#include "c68kmac.inc" + +// prototype +///////////// + +u32 FASTCALL C68k_Read_Dummy(void *param, const u32 adr); +void FASTCALL C68k_Write_Dummy(void *param, const u32 adr, u32 data); + +u32 C68k_Read_Byte(c68k_struc *cpu, u32 adr); +u32 C68k_Read_Word(c68k_struc *cpu, u32 adr); +u32 C68k_Read_Long(c68k_struc *cpu, u32 adr); +void C68k_Write_Byte(c68k_struc *cpu, u32 adr, u32 data); +void C68k_Write_Word(c68k_struc *cpu, u32 adr, u32 data); +void C68k_Write_Long(c68k_struc *cpu, u32 adr, u32 data); + +s32 FASTCALL C68k_Interrupt_Ack_Dummy(void *param, s32 level); +void FASTCALL C68k_Reset_Dummy(void *param); + +// core main functions +/////////////////////// + +void C68k_Init(c68k_struc *cpu, C68K_INT_CALLBACK *int_cb) +{ + memset(cpu, 0, sizeof(c68k_struc)); + + C68k_Set_ReadB(cpu, C68k_Read_Dummy); + C68k_Set_ReadW(cpu, C68k_Read_Dummy); + + C68k_Set_WriteB(cpu, C68k_Write_Dummy); + C68k_Set_WriteW(cpu, C68k_Write_Dummy); + + if (int_cb) cpu->Interrupt_CallBack = int_cb; + else cpu->Interrupt_CallBack = C68k_Interrupt_Ack_Dummy; + cpu->Reset_CallBack = C68k_Reset_Dummy; + + // used to init JumpTable + cpu->Status |= C68K_DISABLE; + C68k_Exec(cpu, 0); + + cpu->Status &= ~C68K_DISABLE; +} + +s32 FASTCALL C68k_Reset(c68k_struc *cpu) +{ + memset(cpu, 0, ((u8 *)&(cpu->dirty1)) - ((u8 *)&(cpu->D[0]))); + + cpu->flag_notZ = 1; + cpu->flag_I = 7; + cpu->flag_S = C68K_SR_S; + + cpu->A[7] = C68k_Read_Long(cpu, 0); + C68k_Set_PC(cpu, C68k_Read_Long(cpu, 4)); + + return cpu->Status; +} + +///////////////////////////////// + +void FASTCALL C68k_Set_IRQ(c68k_struc *cpu, s32 level) +{ + cpu->IRQLine = level; + if (cpu->Status & C68K_RUNNING) + { + cpu->CycleSup = cpu->CycleIO; + cpu->CycleIO = 0; + } + cpu->Status &= ~(C68K_HALTED | C68K_WAITING); +} + +///////////////////////////////// + +s32 FASTCALL C68k_Get_CycleToDo(c68k_struc *cpu) +{ + if (!(cpu->Status & C68K_RUNNING)) return -1; + + return cpu->CycleToDo; +} + +s32 FASTCALL C68k_Get_CycleRemaining(c68k_struc *cpu) +{ + if (!(cpu->Status & C68K_RUNNING)) return -1; + + return (cpu->CycleIO + cpu->CycleSup); +} + +s32 FASTCALL C68k_Get_CycleDone(c68k_struc *cpu) +{ + if (!(cpu->Status & C68K_RUNNING)) return -1; + + return (cpu->CycleToDo - (cpu->CycleIO + cpu->CycleSup)); +} + +void FASTCALL C68k_Release_Cycle(c68k_struc *cpu) +{ + if (cpu->Status & C68K_RUNNING) + { + cpu->CycleToDo -= cpu->CycleIO + cpu->CycleSup; + cpu->CycleIO = cpu->CycleSup = 0; + } +} + +void FASTCALL C68k_Add_Cycle(c68k_struc *cpu, s32 cycle) +{ + if (cpu->Status & C68K_RUNNING) cpu->CycleIO -= cycle; +} + +// Read / Write dummy functions +//////////////////////////////// + +u32 FASTCALL C68k_Read_Dummy(UNUSED void *param, UNUSED const u32 adr) +{ + return 0; +} + +void FASTCALL C68k_Write_Dummy(UNUSED void *param, UNUSED const u32 adr, UNUSED u32 data) +{ + +} + +s32 FASTCALL C68k_Interrupt_Ack_Dummy(UNUSED void *param, s32 level) +{ + // return vector + return (C68K_INTERRUPT_AUTOVECTOR_EX + level); +} + +void FASTCALL C68k_Reset_Dummy(UNUSED void *param) +{ + +} + +// Read / Write core functions +/////////////////////////////// + +u32 C68k_Read_Byte(c68k_struc *cpu, u32 adr) +{ + return cpu->Read_Byte(cpu->Callback_Param, adr); +} + +u32 C68k_Read_Word(c68k_struc *cpu, u32 adr) +{ + return cpu->Read_Word(cpu->Callback_Param, adr); +} + +u32 C68k_Read_Long(c68k_struc *cpu, u32 adr) +{ +#ifdef C68K_BIG_ENDIAN + return (cpu->Read_Word(cpu->Callback_Param, adr) << 16) | (cpu->Read_Word(cpu->Callback_Param, adr + 2) & 0xFFFF); +#else + return (cpu->Read_Word(cpu->Callback_Param, adr) << 16) | (cpu->Read_Word(cpu->Callback_Param, adr + 2) & 0xFFFF); +#endif +} + +void C68k_Write_Byte(c68k_struc *cpu, u32 adr, u32 data) +{ + cpu->Write_Byte(cpu->Callback_Param, adr, data); +} + +void C68k_Write_Word(c68k_struc *cpu, u32 adr, u32 data) +{ + cpu->Write_Word(cpu->Callback_Param, adr, data); +} + +void C68k_Write_Long(c68k_struc *cpu, u32 adr, u32 data) +{ +#ifdef C68K_BIG_ENDIAN + cpu->Write_Word(cpu->Callback_Param, adr, data >> 16); + cpu->Write_Word(cpu->Callback_Param, adr + 2, data & 0xFFFF); +#else + cpu->Write_Word(cpu->Callback_Param, adr, data >> 16); + cpu->Write_Word(cpu->Callback_Param, adr + 2, data & 0xFFFF); +#endif +} + +// setting core functions +////////////////////////// + +void C68k_Set_Fetch(c68k_struc *cpu, u32 low_adr, u32 high_adr, pointer fetch_adr) +{ + u32 i, j; + + i = (low_adr >> C68K_FETCH_SFT) & C68K_FETCH_MASK; + j = (high_adr >> C68K_FETCH_SFT) & C68K_FETCH_MASK; + fetch_adr -= i << C68K_FETCH_SFT; + while (i <= j) cpu->Fetch[i++] = fetch_adr; +} + +void C68k_Set_Callback_Param(c68k_struc *cpu, void *Param) +{ + cpu->Callback_Param = Param; +} + +void C68k_Set_ReadB(c68k_struc *cpu, C68K_READ *Func) +{ + cpu->Read_Byte = Func; +} + +void C68k_Set_ReadW(c68k_struc *cpu, C68K_READ *Func) +{ + cpu->Read_Word = Func; +} + +void C68k_Set_WriteB(c68k_struc *cpu, C68K_WRITE *Func) +{ + cpu->Write_Byte = Func; +} + +void C68k_Set_WriteW(c68k_struc *cpu, C68K_WRITE *Func) +{ + cpu->Write_Word = Func; +} + +// externals main functions +//////////////////////////// + +u32 C68k_Get_DReg(c68k_struc *cpu, u32 num) +{ + return cpu->D[num]; +} + +u32 C68k_Get_AReg(c68k_struc *cpu, u32 num) +{ + return cpu->A[num]; +} + +u32 C68k_Get_PC(c68k_struc *cpu) +{ + return (cpu->PC - cpu->BasePC); +} + +u32 C68k_Get_SR(c68k_struc *cpu) +{ + c68k_struc *CPU = cpu; + return GET_SR; +} + +u32 C68k_Get_USP(c68k_struc *cpu) +{ + if (cpu->flag_S) return cpu->USP; + else return cpu->A[7]; +} + +u32 C68k_Get_MSP(c68k_struc *cpu) +{ + if (cpu->flag_S) return cpu->A[7]; + else return cpu->USP; +} + +void C68k_Set_DReg(c68k_struc *cpu, u32 num, u32 val) +{ + cpu->D[num] = val; +} + +void C68k_Set_AReg(c68k_struc *cpu, u32 num, u32 val) +{ + cpu->A[num] = val; +} + +void C68k_Set_PC(c68k_struc *cpu, u32 val) +{ + cpu->BasePC = cpu->Fetch[(val >> C68K_FETCH_SFT) & C68K_FETCH_MASK]; + cpu->PC = val + cpu->BasePC; +} + +void C68k_Set_SR(c68k_struc *cpu, u32 val) +{ + c68k_struc *CPU = cpu; + SET_SR(val); +} + +void C68k_Set_USP(c68k_struc *cpu, u32 val) +{ + if (cpu->flag_S) cpu->USP = val; + else cpu->A[7] = val; +} + +void C68k_Set_MSP(c68k_struc *cpu, u32 val) +{ + if (cpu->flag_S) cpu->A[7] = val; + else cpu->USP = val; +} diff --git a/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68k.h b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68k.h new file mode 100644 index 000000000..5922fd9e0 --- /dev/null +++ b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68k.h @@ -0,0 +1,211 @@ +/* Copyright 2003-2004 Stephane Dallongeville + Copyright 2004 Theo Berkau + + This file is part of Yabause. + + Yabause is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + Yabause is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with Yabause; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +/********************************************************************************* + * C68K.H : + * + * C68K include file + * + ********************************************************************************/ + +#ifndef _C68K_H_ +#define _C68K_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "core.h" + +// setting +/////////// + +//#define NEOCD_HLE + +//#define C68K_GEN +#define C68K_BYTE_SWAP_OPT + +#ifdef WORDS_BIGENDIAN +#define C68K_BIG_ENDIAN +#endif + +#ifdef C68K_BIG_ENDIAN + #define BYTE_OFF 3 + #define WORD_OFF 1 +#else + #define BYTE_OFF 0 + #define WORD_OFF 0 +#endif + +//#define C68K_NO_JUMP_TABLE +//#define C68K_DEBUG +#define C68K_TAS_CAN_SET_MEMORY +//#define C68K_CONST_JUMP_TABLE +//#define C68K_AUTOVECTOR_CALLBACK + +// 68K core types definitions +////////////////////////////// + +#define C68K_FETCH_BITS 8 // [4-12] default = 8 +#define C68K_ADR_BITS 24 + +#define C68K_FETCH_SFT (C68K_ADR_BITS - C68K_FETCH_BITS) +#define C68K_FETCH_BANK (1 << C68K_FETCH_BITS) +#define C68K_FETCH_MASK (C68K_FETCH_BANK - 1) + +#define C68K_SR_C_SFT 8 +#define C68K_SR_V_SFT 7 +#define C68K_SR_Z_SFT 0 +#define C68K_SR_N_SFT 7 +#define C68K_SR_X_SFT 8 + +#define C68K_SR_S_SFT 13 + +#define C68K_SR_C (1 << C68K_SR_C_SFT) +#define C68K_SR_V (1 << C68K_SR_V_SFT) +#define C68K_SR_Z 0 +#define C68K_SR_N (1 << C68K_SR_N_SFT) +#define C68K_SR_X (1 << C68K_SR_X_SFT) + +#define C68K_SR_S (1 << C68K_SR_S_SFT) + +#define C68K_CCR_MASK 0x1F +#define C68K_SR_MASK (0x2700 | C68K_CCR_MASK) + +// exception defines taken from musashi core +#define C68K_RESET_EX 1 +#define C68K_BUS_ERROR_EX 2 +#define C68K_ADDRESS_ERROR_EX 3 +#define C68K_ILLEGAL_INSTRUCTION_EX 4 +#define C68K_ZERO_DIVIDE_EX 5 +#define C68K_CHK_EX 6 +#define C68K_TRAPV_EX 7 +#define C68K_PRIVILEGE_VIOLATION_EX 8 +#define C68K_TRACE_EX 9 +#define C68K_1010_EX 10 +#define C68K_1111_EX 11 +#define C68K_FORMAT_ERROR_EX 14 +#define C68K_UNINITIALIZED_INTERRUPT_EX 15 +#define C68K_SPURIOUS_INTERRUPT_EX 24 +#define C68K_INTERRUPT_AUTOVECTOR_EX 24 +#define C68K_TRAP_BASE_EX 32 + +#define C68K_INT_ACK_AUTOVECTOR -1 + +#define C68K_RUNNING 0x01 +#define C68K_HALTED 0x02 +#define C68K_WAITING 0x04 +#define C68K_DISABLE 0x10 +#define C68K_FAULTED 0x40 + +typedef u32 FASTCALL C68K_READ(void *param, const u32 adr); +typedef void FASTCALL C68K_WRITE(void *param, const u32 adr, u32 data); + +typedef s32 FASTCALL C68K_INT_CALLBACK(void *param, s32 level); +typedef void FASTCALL C68K_RESET_CALLBACK(void *param); + +typedef struct { + u32 D[8]; // 32 bytes aligned + u32 A[8]; // 16 bytes aligned + + u32 flag_C; // 32 bytes aligned + u32 flag_V; + u32 flag_notZ; + u32 flag_N; + + u32 flag_X; // 16 bytes aligned + u32 flag_I; + u32 flag_S; + + u32 USP; + + pointer PC; // 32 bytes aligned + pointer BasePC; + u32 Status; + s32 IRQLine; + + s32 CycleToDo; // 16 bytes aligned + s32 CycleIO; + s32 CycleSup; + u32 dirty1; + + void *Callback_Param; + + C68K_READ *Read_Byte; // 32 bytes aligned + C68K_READ *Read_Word; + + C68K_WRITE *Write_Byte; + C68K_WRITE *Write_Word; + + C68K_INT_CALLBACK *Interrupt_CallBack; // 16 bytes aligned + C68K_RESET_CALLBACK *Reset_CallBack; + + pointer Fetch[C68K_FETCH_BANK]; // 32 bytes aligned +} c68k_struc; + + +// 68K core function declaration +///////////////////////////////// + +void C68k_Init(c68k_struc *cpu, C68K_INT_CALLBACK *int_cb); + +s32 FASTCALL C68k_Reset(c68k_struc *cpu); + +// if < 0 --> error (cpu state returned) +// if >= 0 --> number of extras cycles done +s32 FASTCALL C68k_Exec(c68k_struc *cpu, s32 cycle); + +void FASTCALL C68k_Set_IRQ(c68k_struc *cpu, s32 level); + +s32 FASTCALL C68k_Get_CycleToDo(c68k_struc *cpu); +s32 FASTCALL C68k_Get_CycleRemaining(c68k_struc *cpu); +s32 FASTCALL C68k_Get_CycleDone(c68k_struc *cpu); +void FASTCALL C68k_Release_Cycle(c68k_struc *cpu); +void FASTCALL C68k_Add_Cycle(c68k_struc *cpu, s32 cycle); + +void C68k_Set_Fetch(c68k_struc *cpu, u32 low_adr, u32 high_adr, pointer fetch_adr); + +void C68k_Set_Callback_Param(c68k_struc *cpu, void *Param); + +void C68k_Set_ReadB(c68k_struc *cpu, C68K_READ *Func); +void C68k_Set_ReadW(c68k_struc *cpu, C68K_READ *Func); +void C68k_Set_WriteB(c68k_struc *cpu, C68K_WRITE *Func); +void C68k_Set_WriteW(c68k_struc *cpu, C68K_WRITE *Func); + +u32 C68k_Get_DReg(c68k_struc *cpu, u32 num); +u32 C68k_Get_AReg(c68k_struc *cpu, u32 num); +u32 C68k_Get_PC(c68k_struc *cpu); +u32 C68k_Get_SR(c68k_struc *cpu); +u32 C68k_Get_USP(c68k_struc *cpu); +u32 C68k_Get_MSP(c68k_struc *cpu); + +void C68k_Set_DReg(c68k_struc *cpu, u32 num, u32 val); +void C68k_Set_AReg(c68k_struc *cpu, u32 num, u32 val); +void C68k_Set_PC(c68k_struc *cpu, u32 val); +void C68k_Set_SR(c68k_struc *cpu, u32 val); +void C68k_Set_USP(c68k_struc *cpu, u32 val); +void C68k_Set_MSP(c68k_struc *cpu, u32 val); + +#ifdef __cplusplus +} +#endif + +#endif // _C68K_H_ + diff --git a/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68k_ini.inc b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68k_ini.inc new file mode 100644 index 000000000..e69de29bb diff --git a/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68k_op0.inc b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68k_op0.inc new file mode 100644 index 000000000..8d7695921 --- /dev/null +++ b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68k_op0.inc @@ -0,0 +1,8330 @@ +case 0x0001: +case 0x0002: +case 0x0003: +case 0x0004: +case 0x0005: +case 0x0006: +case 0x0007: + +// ORI +case 0x0000: +{ + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + res = (u8)CPU->D[(Opcode >> 0) & 7]; + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(8) +case 0x0011: +case 0x0012: +case 0x0013: +case 0x0014: +case 0x0015: +case 0x0016: +case 0x0017: + +// ORI +case 0x0010: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_BYTE_F(adr, res) + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0x0019: +case 0x001A: +case 0x001B: +case 0x001C: +case 0x001D: +case 0x001E: + +// ORI +case 0x0018: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + PRE_IO + READ_BYTE_F(adr, res) + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0x0021: +case 0x0022: +case 0x0023: +case 0x0024: +case 0x0025: +case 0x0026: + +// ORI +case 0x0020: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_BYTE_F(adr, res) + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) +case 0x0029: +case 0x002A: +case 0x002B: +case 0x002C: +case 0x002D: +case 0x002E: +case 0x002F: + +// ORI +case 0x0028: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(20) +case 0x0031: +case 0x0032: +case 0x0033: +case 0x0034: +case 0x0035: +case 0x0036: +case 0x0037: + +// ORI +case 0x0030: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, res) + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(22) + +// ORI +case 0x0038: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(20) + +// ORI +case 0x0039: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_BYTE_F(adr, res) + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(24) + +// ORI +case 0x001F: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_BYTE_F(adr, res) + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) + +// ORI +case 0x0027: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_BYTE_F(adr, res) + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) +case 0x0041: +case 0x0042: +case 0x0043: +case 0x0044: +case 0x0045: +case 0x0046: +case 0x0047: + +// ORI +case 0x0040: +{ + u32 res; + pointer src; + src = FETCH_WORD; + PC += 2; + res = (u16)CPU->D[(Opcode >> 0) & 7]; + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(8) +case 0x0051: +case 0x0052: +case 0x0053: +case 0x0054: +case 0x0055: +case 0x0056: +case 0x0057: + +// ORI +case 0x0050: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_WORD; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_WORD_F(adr, res) + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0x0059: +case 0x005A: +case 0x005B: +case 0x005C: +case 0x005D: +case 0x005E: + +// ORI +case 0x0058: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_WORD; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 2; + PRE_IO + READ_WORD_F(adr, res) + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0x0061: +case 0x0062: +case 0x0063: +case 0x0064: +case 0x0065: +case 0x0066: + +// ORI +case 0x0060: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_WORD; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7] - 2; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_WORD_F(adr, res) + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(18) +case 0x0069: +case 0x006A: +case 0x006B: +case 0x006C: +case 0x006D: +case 0x006E: +case 0x006F: + +// ORI +case 0x0068: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_WORD; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, res) + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(20) +case 0x0071: +case 0x0072: +case 0x0073: +case 0x0074: +case 0x0075: +case 0x0076: +case 0x0077: + +// ORI +case 0x0070: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_WORD; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, res) + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(22) + +// ORI +case 0x0078: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_WORD; + PC += 2; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, res) + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(20) + +// ORI +case 0x0079: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_WORD; + PC += 2; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_WORD_F(adr, res) + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(24) + +// ORI +case 0x005F: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_WORD; + PC += 2; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_WORD_F(adr, res) + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) + +// ORI +case 0x0067: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_WORD; + PC += 2; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_WORD_F(adr, res) + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(18) +case 0x0081: +case 0x0082: +case 0x0083: +case 0x0084: +case 0x0085: +case 0x0086: +case 0x0087: + +// ORI +case 0x0080: +{ + u32 res; + pointer src; + src = FETCH_LONG; + PC += 4; + res = (u32)CPU->D[(Opcode >> 0) & 7]; + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(16) +case 0x0091: +case 0x0092: +case 0x0093: +case 0x0094: +case 0x0095: +case 0x0096: +case 0x0097: + +// ORI +case 0x0090: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_LONG; + PC += 4; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_LONG_F(adr, res) + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(28) +case 0x0099: +case 0x009A: +case 0x009B: +case 0x009C: +case 0x009D: +case 0x009E: + +// ORI +case 0x0098: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_LONG; + PC += 4; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 4; + PRE_IO + READ_LONG_F(adr, res) + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(28) +case 0x00A1: +case 0x00A2: +case 0x00A3: +case 0x00A4: +case 0x00A5: +case 0x00A6: + +// ORI +case 0x00A0: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_LONG; + PC += 4; + adr = CPU->A[(Opcode >> 0) & 7] - 4; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_LONG_F(adr, res) + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(30) +case 0x00A9: +case 0x00AA: +case 0x00AB: +case 0x00AC: +case 0x00AD: +case 0x00AE: +case 0x00AF: + +// ORI +case 0x00A8: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_LONG; + PC += 4; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, res) + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(32) +case 0x00B1: +case 0x00B2: +case 0x00B3: +case 0x00B4: +case 0x00B5: +case 0x00B6: +case 0x00B7: + +// ORI +case 0x00B0: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_LONG; + PC += 4; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_LONG_F(adr, res) + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(34) + +// ORI +case 0x00B8: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_LONG; + PC += 4; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, res) + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(32) + +// ORI +case 0x00B9: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_LONG; + PC += 4; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_LONG_F(adr, res) + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(36) + +// ORI +case 0x009F: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_LONG; + PC += 4; + adr = CPU->A[7]; + CPU->A[7] += 4; + PRE_IO + READ_LONG_F(adr, res) + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(28) + +// ORI +case 0x00A7: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_LONG; + PC += 4; + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + PRE_IO + READ_LONG_F(adr, res) + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(30) + +// ORICCR +case 0x003C: +{ + u32 res; + res = FETCH_BYTE & C68K_CCR_MASK; + PC += 2; + res |= GET_CCR; + SET_CCR(res) +} +RET(20) + +// ORISR +case 0x007C: +{ + u32 res; + if (CPU->flag_S) + { + res = FETCH_WORD & C68K_SR_MASK; + PC += 2; + res |= GET_SR; + SET_SR(res) + } + else + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + res = C68K_PRIVILEGE_VIOLATION_EX; + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + } +} +POST_IO +CCnt -= 20; +goto C68k_Exec_End; +case 0x0201: +case 0x0202: +case 0x0203: +case 0x0204: +case 0x0205: +case 0x0206: +case 0x0207: + +// ANDI +case 0x0200: +{ + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + res = (u8)CPU->D[(Opcode >> 0) & 7]; + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(8) +case 0x0211: +case 0x0212: +case 0x0213: +case 0x0214: +case 0x0215: +case 0x0216: +case 0x0217: + +// ANDI +case 0x0210: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_BYTE_F(adr, res) + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0x0219: +case 0x021A: +case 0x021B: +case 0x021C: +case 0x021D: +case 0x021E: + +// ANDI +case 0x0218: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + PRE_IO + READ_BYTE_F(adr, res) + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0x0221: +case 0x0222: +case 0x0223: +case 0x0224: +case 0x0225: +case 0x0226: + +// ANDI +case 0x0220: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_BYTE_F(adr, res) + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) +case 0x0229: +case 0x022A: +case 0x022B: +case 0x022C: +case 0x022D: +case 0x022E: +case 0x022F: + +// ANDI +case 0x0228: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(20) +case 0x0231: +case 0x0232: +case 0x0233: +case 0x0234: +case 0x0235: +case 0x0236: +case 0x0237: + +// ANDI +case 0x0230: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, res) + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(22) + +// ANDI +case 0x0238: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(20) + +// ANDI +case 0x0239: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_BYTE_F(adr, res) + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(24) + +// ANDI +case 0x021F: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_BYTE_F(adr, res) + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) + +// ANDI +case 0x0227: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_BYTE_F(adr, res) + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) +case 0x0241: +case 0x0242: +case 0x0243: +case 0x0244: +case 0x0245: +case 0x0246: +case 0x0247: + +// ANDI +case 0x0240: +{ + u32 res; + pointer src; + src = FETCH_WORD; + PC += 2; + res = (u16)CPU->D[(Opcode >> 0) & 7]; + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(8) +case 0x0251: +case 0x0252: +case 0x0253: +case 0x0254: +case 0x0255: +case 0x0256: +case 0x0257: + +// ANDI +case 0x0250: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_WORD; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_WORD_F(adr, res) + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0x0259: +case 0x025A: +case 0x025B: +case 0x025C: +case 0x025D: +case 0x025E: + +// ANDI +case 0x0258: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_WORD; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 2; + PRE_IO + READ_WORD_F(adr, res) + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0x0261: +case 0x0262: +case 0x0263: +case 0x0264: +case 0x0265: +case 0x0266: + +// ANDI +case 0x0260: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_WORD; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7] - 2; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_WORD_F(adr, res) + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(18) +case 0x0269: +case 0x026A: +case 0x026B: +case 0x026C: +case 0x026D: +case 0x026E: +case 0x026F: + +// ANDI +case 0x0268: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_WORD; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, res) + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(20) +case 0x0271: +case 0x0272: +case 0x0273: +case 0x0274: +case 0x0275: +case 0x0276: +case 0x0277: + +// ANDI +case 0x0270: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_WORD; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, res) + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(22) + +// ANDI +case 0x0278: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_WORD; + PC += 2; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, res) + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(20) + +// ANDI +case 0x0279: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_WORD; + PC += 2; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_WORD_F(adr, res) + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(24) + +// ANDI +case 0x025F: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_WORD; + PC += 2; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_WORD_F(adr, res) + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) + +// ANDI +case 0x0267: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_WORD; + PC += 2; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_WORD_F(adr, res) + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(18) +case 0x0281: +case 0x0282: +case 0x0283: +case 0x0284: +case 0x0285: +case 0x0286: +case 0x0287: + +// ANDI +case 0x0280: +{ + u32 res; + pointer src; + src = FETCH_LONG; + PC += 4; + res = (u32)CPU->D[(Opcode >> 0) & 7]; + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(16) +case 0x0291: +case 0x0292: +case 0x0293: +case 0x0294: +case 0x0295: +case 0x0296: +case 0x0297: + +// ANDI +case 0x0290: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_LONG; + PC += 4; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_LONG_F(adr, res) + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(28) +case 0x0299: +case 0x029A: +case 0x029B: +case 0x029C: +case 0x029D: +case 0x029E: + +// ANDI +case 0x0298: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_LONG; + PC += 4; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 4; + PRE_IO + READ_LONG_F(adr, res) + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(28) +case 0x02A1: +case 0x02A2: +case 0x02A3: +case 0x02A4: +case 0x02A5: +case 0x02A6: + +// ANDI +case 0x02A0: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_LONG; + PC += 4; + adr = CPU->A[(Opcode >> 0) & 7] - 4; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_LONG_F(adr, res) + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(30) +case 0x02A9: +case 0x02AA: +case 0x02AB: +case 0x02AC: +case 0x02AD: +case 0x02AE: +case 0x02AF: + +// ANDI +case 0x02A8: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_LONG; + PC += 4; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, res) + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(32) +case 0x02B1: +case 0x02B2: +case 0x02B3: +case 0x02B4: +case 0x02B5: +case 0x02B6: +case 0x02B7: + +// ANDI +case 0x02B0: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_LONG; + PC += 4; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_LONG_F(adr, res) + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(34) + +// ANDI +case 0x02B8: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_LONG; + PC += 4; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, res) + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(32) + +// ANDI +case 0x02B9: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_LONG; + PC += 4; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_LONG_F(adr, res) + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(36) + +// ANDI +case 0x029F: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_LONG; + PC += 4; + adr = CPU->A[7]; + CPU->A[7] += 4; + PRE_IO + READ_LONG_F(adr, res) + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(28) + +// ANDI +case 0x02A7: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_LONG; + PC += 4; + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + PRE_IO + READ_LONG_F(adr, res) + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(30) + +// ANDICCR +case 0x023C: +{ + u32 res; + res = FETCH_BYTE & C68K_CCR_MASK; + PC += 2; + res &= GET_CCR; + SET_CCR(res) +} +RET(20) + +// ANDISR +case 0x027C: +{ + u32 res; + if (CPU->flag_S) + { + res = FETCH_WORD & C68K_SR_MASK; + PC += 2; + res &= GET_SR; + SET_SR(res) + if (!CPU->flag_S) + { + res = CPU->A[7]; + CPU->A[7] = CPU->USP; + CPU->USP = res; + } + } + else + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + res = C68K_PRIVILEGE_VIOLATION_EX; + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + } +} +POST_IO +CCnt -= 20; +goto C68k_Exec_End; +case 0x0A01: +case 0x0A02: +case 0x0A03: +case 0x0A04: +case 0x0A05: +case 0x0A06: +case 0x0A07: + +// EORI +case 0x0A00: +{ + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + res = (u8)CPU->D[(Opcode >> 0) & 7]; + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(8) +case 0x0A11: +case 0x0A12: +case 0x0A13: +case 0x0A14: +case 0x0A15: +case 0x0A16: +case 0x0A17: + +// EORI +case 0x0A10: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_BYTE_F(adr, res) + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0x0A19: +case 0x0A1A: +case 0x0A1B: +case 0x0A1C: +case 0x0A1D: +case 0x0A1E: + +// EORI +case 0x0A18: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + PRE_IO + READ_BYTE_F(adr, res) + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0x0A21: +case 0x0A22: +case 0x0A23: +case 0x0A24: +case 0x0A25: +case 0x0A26: + +// EORI +case 0x0A20: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_BYTE_F(adr, res) + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) +case 0x0A29: +case 0x0A2A: +case 0x0A2B: +case 0x0A2C: +case 0x0A2D: +case 0x0A2E: +case 0x0A2F: + +// EORI +case 0x0A28: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(20) +case 0x0A31: +case 0x0A32: +case 0x0A33: +case 0x0A34: +case 0x0A35: +case 0x0A36: +case 0x0A37: + +// EORI +case 0x0A30: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, res) + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(22) + +// EORI +case 0x0A38: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(20) + +// EORI +case 0x0A39: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_BYTE_F(adr, res) + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(24) + +// EORI +case 0x0A1F: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_BYTE_F(adr, res) + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) + +// EORI +case 0x0A27: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_BYTE_F(adr, res) + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) +case 0x0A41: +case 0x0A42: +case 0x0A43: +case 0x0A44: +case 0x0A45: +case 0x0A46: +case 0x0A47: + +// EORI +case 0x0A40: +{ + u32 res; + pointer src; + src = FETCH_WORD; + PC += 2; + res = (u16)CPU->D[(Opcode >> 0) & 7]; + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(8) +case 0x0A51: +case 0x0A52: +case 0x0A53: +case 0x0A54: +case 0x0A55: +case 0x0A56: +case 0x0A57: + +// EORI +case 0x0A50: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_WORD; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_WORD_F(adr, res) + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0x0A59: +case 0x0A5A: +case 0x0A5B: +case 0x0A5C: +case 0x0A5D: +case 0x0A5E: + +// EORI +case 0x0A58: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_WORD; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 2; + PRE_IO + READ_WORD_F(adr, res) + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0x0A61: +case 0x0A62: +case 0x0A63: +case 0x0A64: +case 0x0A65: +case 0x0A66: + +// EORI +case 0x0A60: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_WORD; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7] - 2; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_WORD_F(adr, res) + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(18) +case 0x0A69: +case 0x0A6A: +case 0x0A6B: +case 0x0A6C: +case 0x0A6D: +case 0x0A6E: +case 0x0A6F: + +// EORI +case 0x0A68: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_WORD; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, res) + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(20) +case 0x0A71: +case 0x0A72: +case 0x0A73: +case 0x0A74: +case 0x0A75: +case 0x0A76: +case 0x0A77: + +// EORI +case 0x0A70: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_WORD; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, res) + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(22) + +// EORI +case 0x0A78: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_WORD; + PC += 2; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, res) + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(20) + +// EORI +case 0x0A79: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_WORD; + PC += 2; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_WORD_F(adr, res) + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(24) + +// EORI +case 0x0A5F: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_WORD; + PC += 2; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_WORD_F(adr, res) + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) + +// EORI +case 0x0A67: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_WORD; + PC += 2; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_WORD_F(adr, res) + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(18) +case 0x0A81: +case 0x0A82: +case 0x0A83: +case 0x0A84: +case 0x0A85: +case 0x0A86: +case 0x0A87: + +// EORI +case 0x0A80: +{ + u32 res; + pointer src; + src = FETCH_LONG; + PC += 4; + res = (u32)CPU->D[(Opcode >> 0) & 7]; + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(16) +case 0x0A91: +case 0x0A92: +case 0x0A93: +case 0x0A94: +case 0x0A95: +case 0x0A96: +case 0x0A97: + +// EORI +case 0x0A90: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_LONG; + PC += 4; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_LONG_F(adr, res) + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(28) +case 0x0A99: +case 0x0A9A: +case 0x0A9B: +case 0x0A9C: +case 0x0A9D: +case 0x0A9E: + +// EORI +case 0x0A98: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_LONG; + PC += 4; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 4; + PRE_IO + READ_LONG_F(adr, res) + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(28) +case 0x0AA1: +case 0x0AA2: +case 0x0AA3: +case 0x0AA4: +case 0x0AA5: +case 0x0AA6: + +// EORI +case 0x0AA0: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_LONG; + PC += 4; + adr = CPU->A[(Opcode >> 0) & 7] - 4; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_LONG_F(adr, res) + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(30) +case 0x0AA9: +case 0x0AAA: +case 0x0AAB: +case 0x0AAC: +case 0x0AAD: +case 0x0AAE: +case 0x0AAF: + +// EORI +case 0x0AA8: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_LONG; + PC += 4; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, res) + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(32) +case 0x0AB1: +case 0x0AB2: +case 0x0AB3: +case 0x0AB4: +case 0x0AB5: +case 0x0AB6: +case 0x0AB7: + +// EORI +case 0x0AB0: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_LONG; + PC += 4; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_LONG_F(adr, res) + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(34) + +// EORI +case 0x0AB8: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_LONG; + PC += 4; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, res) + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(32) + +// EORI +case 0x0AB9: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_LONG; + PC += 4; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_LONG_F(adr, res) + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(36) + +// EORI +case 0x0A9F: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_LONG; + PC += 4; + adr = CPU->A[7]; + CPU->A[7] += 4; + PRE_IO + READ_LONG_F(adr, res) + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(28) + +// EORI +case 0x0AA7: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_LONG; + PC += 4; + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + PRE_IO + READ_LONG_F(adr, res) + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(30) + +// EORICCR +case 0x0A3C: +{ + u32 res; + res = FETCH_BYTE & C68K_CCR_MASK; + PC += 2; + res ^= GET_CCR; + SET_CCR(res) +} +RET(20) + +// EORISR +case 0x0A7C: +{ + u32 res; + if (CPU->flag_S) + { + res = FETCH_WORD & C68K_SR_MASK; + PC += 2; + res ^= GET_SR; + SET_SR(res) + if (!CPU->flag_S) + { + res = CPU->A[7]; + CPU->A[7] = CPU->USP; + CPU->USP = res; + } + } + else + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + res = C68K_PRIVILEGE_VIOLATION_EX; + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + } +} +POST_IO +CCnt -= 20; +goto C68k_Exec_End; +case 0x0401: +case 0x0402: +case 0x0403: +case 0x0404: +case 0x0405: +case 0x0406: +case 0x0407: + +// SUBI +case 0x0400: +{ + u32 res; + pointer dst; + pointer src; + src = FETCH_BYTE; + PC += 2; + dst = (u8)CPU->D[(Opcode >> 0) & 7]; + res = dst - src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(8) +case 0x0411: +case 0x0412: +case 0x0413: +case 0x0414: +case 0x0415: +case 0x0416: +case 0x0417: + +// SUBI +case 0x0410: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_BYTE; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_BYTE_F(adr, dst) + res = dst - src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0x0419: +case 0x041A: +case 0x041B: +case 0x041C: +case 0x041D: +case 0x041E: + +// SUBI +case 0x0418: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_BYTE; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + PRE_IO + READ_BYTE_F(adr, dst) + res = dst - src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0x0421: +case 0x0422: +case 0x0423: +case 0x0424: +case 0x0425: +case 0x0426: + +// SUBI +case 0x0420: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_BYTE; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_BYTE_F(adr, dst) + res = dst - src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) +case 0x0429: +case 0x042A: +case 0x042B: +case 0x042C: +case 0x042D: +case 0x042E: +case 0x042F: + +// SUBI +case 0x0428: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_BYTE; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, dst) + res = dst - src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(20) +case 0x0431: +case 0x0432: +case 0x0433: +case 0x0434: +case 0x0435: +case 0x0436: +case 0x0437: + +// SUBI +case 0x0430: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_BYTE; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, dst) + res = dst - src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(22) + +// SUBI +case 0x0438: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_BYTE; + PC += 2; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, dst) + res = dst - src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(20) + +// SUBI +case 0x0439: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_BYTE; + PC += 2; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_BYTE_F(adr, dst) + res = dst - src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(24) + +// SUBI +case 0x041F: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_BYTE; + PC += 2; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_BYTE_F(adr, dst) + res = dst - src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) + +// SUBI +case 0x0427: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_BYTE; + PC += 2; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_BYTE_F(adr, dst) + res = dst - src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) +case 0x0441: +case 0x0442: +case 0x0443: +case 0x0444: +case 0x0445: +case 0x0446: +case 0x0447: + +// SUBI +case 0x0440: +{ + u32 res; + pointer dst; + pointer src; + src = FETCH_WORD; + PC += 2; + dst = (u16)CPU->D[(Opcode >> 0) & 7]; + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(8) +case 0x0451: +case 0x0452: +case 0x0453: +case 0x0454: +case 0x0455: +case 0x0456: +case 0x0457: + +// SUBI +case 0x0450: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_WORD; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_WORD_F(adr, dst) + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0x0459: +case 0x045A: +case 0x045B: +case 0x045C: +case 0x045D: +case 0x045E: + +// SUBI +case 0x0458: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_WORD; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 2; + PRE_IO + READ_WORD_F(adr, dst) + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0x0461: +case 0x0462: +case 0x0463: +case 0x0464: +case 0x0465: +case 0x0466: + +// SUBI +case 0x0460: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_WORD; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7] - 2; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_WORD_F(adr, dst) + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(18) +case 0x0469: +case 0x046A: +case 0x046B: +case 0x046C: +case 0x046D: +case 0x046E: +case 0x046F: + +// SUBI +case 0x0468: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_WORD; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, dst) + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(20) +case 0x0471: +case 0x0472: +case 0x0473: +case 0x0474: +case 0x0475: +case 0x0476: +case 0x0477: + +// SUBI +case 0x0470: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_WORD; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, dst) + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(22) + +// SUBI +case 0x0478: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_WORD; + PC += 2; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, dst) + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(20) + +// SUBI +case 0x0479: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_WORD; + PC += 2; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_WORD_F(adr, dst) + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(24) + +// SUBI +case 0x045F: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_WORD; + PC += 2; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_WORD_F(adr, dst) + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) + +// SUBI +case 0x0467: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_WORD; + PC += 2; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_WORD_F(adr, dst) + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(18) +case 0x0481: +case 0x0482: +case 0x0483: +case 0x0484: +case 0x0485: +case 0x0486: +case 0x0487: + +// SUBI +case 0x0480: +{ + u32 res; + pointer dst; + pointer src; + src = FETCH_LONG; + PC += 4; + dst = (u32)CPU->D[(Opcode >> 0) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(16) +case 0x0491: +case 0x0492: +case 0x0493: +case 0x0494: +case 0x0495: +case 0x0496: +case 0x0497: + +// SUBI +case 0x0490: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_LONG; + PC += 4; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_LONG_F(adr, dst) + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(28) +case 0x0499: +case 0x049A: +case 0x049B: +case 0x049C: +case 0x049D: +case 0x049E: + +// SUBI +case 0x0498: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_LONG; + PC += 4; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 4; + PRE_IO + READ_LONG_F(adr, dst) + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(28) +case 0x04A1: +case 0x04A2: +case 0x04A3: +case 0x04A4: +case 0x04A5: +case 0x04A6: + +// SUBI +case 0x04A0: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_LONG; + PC += 4; + adr = CPU->A[(Opcode >> 0) & 7] - 4; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_LONG_F(adr, dst) + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(30) +case 0x04A9: +case 0x04AA: +case 0x04AB: +case 0x04AC: +case 0x04AD: +case 0x04AE: +case 0x04AF: + +// SUBI +case 0x04A8: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_LONG; + PC += 4; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, dst) + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(32) +case 0x04B1: +case 0x04B2: +case 0x04B3: +case 0x04B4: +case 0x04B5: +case 0x04B6: +case 0x04B7: + +// SUBI +case 0x04B0: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_LONG; + PC += 4; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_LONG_F(adr, dst) + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(34) + +// SUBI +case 0x04B8: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_LONG; + PC += 4; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, dst) + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(32) + +// SUBI +case 0x04B9: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_LONG; + PC += 4; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_LONG_F(adr, dst) + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(36) + +// SUBI +case 0x049F: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_LONG; + PC += 4; + adr = CPU->A[7]; + CPU->A[7] += 4; + PRE_IO + READ_LONG_F(adr, dst) + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(28) + +// SUBI +case 0x04A7: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_LONG; + PC += 4; + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + PRE_IO + READ_LONG_F(adr, dst) + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(30) +case 0x0601: +case 0x0602: +case 0x0603: +case 0x0604: +case 0x0605: +case 0x0606: +case 0x0607: + +// ADDI +case 0x0600: +{ + u32 res; + pointer dst; + pointer src; + src = FETCH_BYTE; + PC += 2; + dst = (u8)CPU->D[(Opcode >> 0) & 7]; + res = dst + src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ res) & (dst ^ res); + CPU->flag_notZ = res & 0xFF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(8) +case 0x0611: +case 0x0612: +case 0x0613: +case 0x0614: +case 0x0615: +case 0x0616: +case 0x0617: + +// ADDI +case 0x0610: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_BYTE; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_BYTE_F(adr, dst) + res = dst + src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ res) & (dst ^ res); + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0x0619: +case 0x061A: +case 0x061B: +case 0x061C: +case 0x061D: +case 0x061E: + +// ADDI +case 0x0618: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_BYTE; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + PRE_IO + READ_BYTE_F(adr, dst) + res = dst + src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ res) & (dst ^ res); + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0x0621: +case 0x0622: +case 0x0623: +case 0x0624: +case 0x0625: +case 0x0626: + +// ADDI +case 0x0620: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_BYTE; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_BYTE_F(adr, dst) + res = dst + src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ res) & (dst ^ res); + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) +case 0x0629: +case 0x062A: +case 0x062B: +case 0x062C: +case 0x062D: +case 0x062E: +case 0x062F: + +// ADDI +case 0x0628: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_BYTE; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, dst) + res = dst + src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ res) & (dst ^ res); + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(20) +case 0x0631: +case 0x0632: +case 0x0633: +case 0x0634: +case 0x0635: +case 0x0636: +case 0x0637: + +// ADDI +case 0x0630: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_BYTE; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, dst) + res = dst + src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ res) & (dst ^ res); + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(22) + +// ADDI +case 0x0638: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_BYTE; + PC += 2; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, dst) + res = dst + src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ res) & (dst ^ res); + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(20) + +// ADDI +case 0x0639: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_BYTE; + PC += 2; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_BYTE_F(adr, dst) + res = dst + src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ res) & (dst ^ res); + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(24) + +// ADDI +case 0x061F: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_BYTE; + PC += 2; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_BYTE_F(adr, dst) + res = dst + src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ res) & (dst ^ res); + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) + +// ADDI +case 0x0627: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_BYTE; + PC += 2; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_BYTE_F(adr, dst) + res = dst + src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ res) & (dst ^ res); + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) +case 0x0641: +case 0x0642: +case 0x0643: +case 0x0644: +case 0x0645: +case 0x0646: +case 0x0647: + +// ADDI +case 0x0640: +{ + u32 res; + pointer dst; + pointer src; + src = FETCH_WORD; + PC += 2; + dst = (u16)CPU->D[(Opcode >> 0) & 7]; + res = dst + src; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(8) +case 0x0651: +case 0x0652: +case 0x0653: +case 0x0654: +case 0x0655: +case 0x0656: +case 0x0657: + +// ADDI +case 0x0650: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_WORD; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_WORD_F(adr, dst) + res = dst + src; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0x0659: +case 0x065A: +case 0x065B: +case 0x065C: +case 0x065D: +case 0x065E: + +// ADDI +case 0x0658: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_WORD; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 2; + PRE_IO + READ_WORD_F(adr, dst) + res = dst + src; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0x0661: +case 0x0662: +case 0x0663: +case 0x0664: +case 0x0665: +case 0x0666: + +// ADDI +case 0x0660: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_WORD; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7] - 2; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_WORD_F(adr, dst) + res = dst + src; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(18) +case 0x0669: +case 0x066A: +case 0x066B: +case 0x066C: +case 0x066D: +case 0x066E: +case 0x066F: + +// ADDI +case 0x0668: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_WORD; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, dst) + res = dst + src; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(20) +case 0x0671: +case 0x0672: +case 0x0673: +case 0x0674: +case 0x0675: +case 0x0676: +case 0x0677: + +// ADDI +case 0x0670: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_WORD; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, dst) + res = dst + src; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(22) + +// ADDI +case 0x0678: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_WORD; + PC += 2; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, dst) + res = dst + src; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(20) + +// ADDI +case 0x0679: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_WORD; + PC += 2; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_WORD_F(adr, dst) + res = dst + src; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(24) + +// ADDI +case 0x065F: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_WORD; + PC += 2; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_WORD_F(adr, dst) + res = dst + src; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) + +// ADDI +case 0x0667: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_WORD; + PC += 2; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_WORD_F(adr, dst) + res = dst + src; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(18) +case 0x0681: +case 0x0682: +case 0x0683: +case 0x0684: +case 0x0685: +case 0x0686: +case 0x0687: + +// ADDI +case 0x0680: +{ + u32 res; + pointer dst; + pointer src; + src = FETCH_LONG; + PC += 4; + dst = (u32)CPU->D[(Opcode >> 0) & 7]; + res = dst + src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 24; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(16) +case 0x0691: +case 0x0692: +case 0x0693: +case 0x0694: +case 0x0695: +case 0x0696: +case 0x0697: + +// ADDI +case 0x0690: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_LONG; + PC += 4; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_LONG_F(adr, dst) + res = dst + src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(28) +case 0x0699: +case 0x069A: +case 0x069B: +case 0x069C: +case 0x069D: +case 0x069E: + +// ADDI +case 0x0698: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_LONG; + PC += 4; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 4; + PRE_IO + READ_LONG_F(adr, dst) + res = dst + src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(28) +case 0x06A1: +case 0x06A2: +case 0x06A3: +case 0x06A4: +case 0x06A5: +case 0x06A6: + +// ADDI +case 0x06A0: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_LONG; + PC += 4; + adr = CPU->A[(Opcode >> 0) & 7] - 4; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_LONG_F(adr, dst) + res = dst + src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(30) +case 0x06A9: +case 0x06AA: +case 0x06AB: +case 0x06AC: +case 0x06AD: +case 0x06AE: +case 0x06AF: + +// ADDI +case 0x06A8: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_LONG; + PC += 4; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, dst) + res = dst + src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(32) +case 0x06B1: +case 0x06B2: +case 0x06B3: +case 0x06B4: +case 0x06B5: +case 0x06B6: +case 0x06B7: + +// ADDI +case 0x06B0: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_LONG; + PC += 4; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_LONG_F(adr, dst) + res = dst + src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(34) + +// ADDI +case 0x06B8: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_LONG; + PC += 4; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, dst) + res = dst + src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(32) + +// ADDI +case 0x06B9: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_LONG; + PC += 4; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_LONG_F(adr, dst) + res = dst + src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(36) + +// ADDI +case 0x069F: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_LONG; + PC += 4; + adr = CPU->A[7]; + CPU->A[7] += 4; + PRE_IO + READ_LONG_F(adr, dst) + res = dst + src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(28) + +// ADDI +case 0x06A7: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_LONG; + PC += 4; + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + PRE_IO + READ_LONG_F(adr, dst) + res = dst + src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(30) +case 0x0C01: +case 0x0C02: +case 0x0C03: +case 0x0C04: +case 0x0C05: +case 0x0C06: +case 0x0C07: + +// CMPI +case 0x0C00: +{ + u32 res; + pointer dst; + pointer src; + src = FETCH_BYTE; + PC += 2; + dst = (u8)CPU->D[(Opcode >> 0) & 7]; + res = dst - src; + CPU->flag_N = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; +} +RET(8) +case 0x0C11: +case 0x0C12: +case 0x0C13: +case 0x0C14: +case 0x0C15: +case 0x0C16: +case 0x0C17: + +// CMPI +case 0x0C10: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_BYTE; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_BYTE_F(adr, dst) + res = dst - src; + CPU->flag_N = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + POST_IO +} +RET(12) +case 0x0C19: +case 0x0C1A: +case 0x0C1B: +case 0x0C1C: +case 0x0C1D: +case 0x0C1E: + +// CMPI +case 0x0C18: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_BYTE; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + PRE_IO + READ_BYTE_F(adr, dst) + res = dst - src; + CPU->flag_N = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + POST_IO +} +RET(12) +case 0x0C21: +case 0x0C22: +case 0x0C23: +case 0x0C24: +case 0x0C25: +case 0x0C26: + +// CMPI +case 0x0C20: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_BYTE; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_BYTE_F(adr, dst) + res = dst - src; + CPU->flag_N = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + POST_IO +} +RET(14) +case 0x0C29: +case 0x0C2A: +case 0x0C2B: +case 0x0C2C: +case 0x0C2D: +case 0x0C2E: +case 0x0C2F: + +// CMPI +case 0x0C28: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_BYTE; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, dst) + res = dst - src; + CPU->flag_N = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + POST_IO +} +RET(16) +case 0x0C31: +case 0x0C32: +case 0x0C33: +case 0x0C34: +case 0x0C35: +case 0x0C36: +case 0x0C37: + +// CMPI +case 0x0C30: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_BYTE; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, dst) + res = dst - src; + CPU->flag_N = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + POST_IO +} +RET(18) + +// CMPI +case 0x0C38: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_BYTE; + PC += 2; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, dst) + res = dst - src; + CPU->flag_N = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + POST_IO +} +RET(16) + +// CMPI +case 0x0C39: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_BYTE; + PC += 2; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_BYTE_F(adr, dst) + res = dst - src; + CPU->flag_N = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + POST_IO +} +RET(20) + +// CMPI +case 0x0C1F: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_BYTE; + PC += 2; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_BYTE_F(adr, dst) + res = dst - src; + CPU->flag_N = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + POST_IO +} +RET(12) + +// CMPI +case 0x0C27: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_BYTE; + PC += 2; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_BYTE_F(adr, dst) + res = dst - src; + CPU->flag_N = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + POST_IO +} +RET(14) +case 0x0C41: +case 0x0C42: +case 0x0C43: +case 0x0C44: +case 0x0C45: +case 0x0C46: +case 0x0C47: + +// CMPI +case 0x0C40: +{ + u32 res; + pointer dst; + pointer src; + src = FETCH_WORD; + PC += 2; + dst = (u16)CPU->D[(Opcode >> 0) & 7]; + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; +} +RET(8) +case 0x0C51: +case 0x0C52: +case 0x0C53: +case 0x0C54: +case 0x0C55: +case 0x0C56: +case 0x0C57: + +// CMPI +case 0x0C50: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_WORD; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_WORD_F(adr, dst) + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + POST_IO +} +RET(12) +case 0x0C59: +case 0x0C5A: +case 0x0C5B: +case 0x0C5C: +case 0x0C5D: +case 0x0C5E: + +// CMPI +case 0x0C58: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_WORD; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 2; + PRE_IO + READ_WORD_F(adr, dst) + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + POST_IO +} +RET(12) +case 0x0C61: +case 0x0C62: +case 0x0C63: +case 0x0C64: +case 0x0C65: +case 0x0C66: + +// CMPI +case 0x0C60: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_WORD; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7] - 2; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_WORD_F(adr, dst) + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + POST_IO +} +RET(14) +case 0x0C69: +case 0x0C6A: +case 0x0C6B: +case 0x0C6C: +case 0x0C6D: +case 0x0C6E: +case 0x0C6F: + +// CMPI +case 0x0C68: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_WORD; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, dst) + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + POST_IO +} +RET(16) +case 0x0C71: +case 0x0C72: +case 0x0C73: +case 0x0C74: +case 0x0C75: +case 0x0C76: +case 0x0C77: + +// CMPI +case 0x0C70: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_WORD; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, dst) + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + POST_IO +} +RET(18) + +// CMPI +case 0x0C78: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_WORD; + PC += 2; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, dst) + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + POST_IO +} +RET(16) + +// CMPI +case 0x0C79: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_WORD; + PC += 2; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_WORD_F(adr, dst) + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + POST_IO +} +RET(20) + +// CMPI +case 0x0C5F: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_WORD; + PC += 2; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_WORD_F(adr, dst) + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + POST_IO +} +RET(12) + +// CMPI +case 0x0C67: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_WORD; + PC += 2; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_WORD_F(adr, dst) + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + POST_IO +} +RET(14) +case 0x0C81: +case 0x0C82: +case 0x0C83: +case 0x0C84: +case 0x0C85: +case 0x0C86: +case 0x0C87: + +// CMPI +case 0x0C80: +{ + u32 res; + pointer dst; + pointer src; + src = FETCH_LONG; + PC += 4; + dst = (u32)CPU->D[(Opcode >> 0) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; +} +RET(14) +case 0x0C91: +case 0x0C92: +case 0x0C93: +case 0x0C94: +case 0x0C95: +case 0x0C96: +case 0x0C97: + +// CMPI +case 0x0C90: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_LONG; + PC += 4; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_LONG_F(adr, dst) + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + POST_IO +} +RET(20) +case 0x0C99: +case 0x0C9A: +case 0x0C9B: +case 0x0C9C: +case 0x0C9D: +case 0x0C9E: + +// CMPI +case 0x0C98: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_LONG; + PC += 4; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 4; + PRE_IO + READ_LONG_F(adr, dst) + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + POST_IO +} +RET(20) +case 0x0CA1: +case 0x0CA2: +case 0x0CA3: +case 0x0CA4: +case 0x0CA5: +case 0x0CA6: + +// CMPI +case 0x0CA0: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_LONG; + PC += 4; + adr = CPU->A[(Opcode >> 0) & 7] - 4; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_LONG_F(adr, dst) + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + POST_IO +} +RET(22) +case 0x0CA9: +case 0x0CAA: +case 0x0CAB: +case 0x0CAC: +case 0x0CAD: +case 0x0CAE: +case 0x0CAF: + +// CMPI +case 0x0CA8: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_LONG; + PC += 4; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, dst) + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + POST_IO +} +RET(24) +case 0x0CB1: +case 0x0CB2: +case 0x0CB3: +case 0x0CB4: +case 0x0CB5: +case 0x0CB6: +case 0x0CB7: + +// CMPI +case 0x0CB0: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_LONG; + PC += 4; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_LONG_F(adr, dst) + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + POST_IO +} +RET(26) + +// CMPI +case 0x0CB8: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_LONG; + PC += 4; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, dst) + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + POST_IO +} +RET(24) + +// CMPI +case 0x0CB9: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_LONG; + PC += 4; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_LONG_F(adr, dst) + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + POST_IO +} +RET(28) + +// CMPI +case 0x0C9F: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_LONG; + PC += 4; + adr = CPU->A[7]; + CPU->A[7] += 4; + PRE_IO + READ_LONG_F(adr, dst) + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + POST_IO +} +RET(20) + +// CMPI +case 0x0CA7: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = FETCH_LONG; + PC += 4; + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + PRE_IO + READ_LONG_F(adr, dst) + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + POST_IO +} +RET(22) +case 0x0801: +case 0x0802: +case 0x0803: +case 0x0804: +case 0x0805: +case 0x0806: +case 0x0807: + +// BTSTn +case 0x0800: +{ + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + src = 1 << (src & 31); + res = (u32)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_notZ = res & src; +} +RET(10) +case 0x0811: +case 0x0812: +case 0x0813: +case 0x0814: +case 0x0815: +case 0x0816: +case 0x0817: + +// BTSTn +case 0x0810: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + src = 1 << (src & 7); + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + POST_IO +} +RET(12) +case 0x0819: +case 0x081A: +case 0x081B: +case 0x081C: +case 0x081D: +case 0x081E: + +// BTSTn +case 0x0818: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + src = 1 << (src & 7); + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + POST_IO +} +RET(12) +case 0x0821: +case 0x0822: +case 0x0823: +case 0x0824: +case 0x0825: +case 0x0826: + +// BTSTn +case 0x0820: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + src = 1 << (src & 7); + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + POST_IO +} +RET(14) +case 0x0829: +case 0x082A: +case 0x082B: +case 0x082C: +case 0x082D: +case 0x082E: +case 0x082F: + +// BTSTn +case 0x0828: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + src = 1 << (src & 7); + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + POST_IO +} +RET(16) +case 0x0831: +case 0x0832: +case 0x0833: +case 0x0834: +case 0x0835: +case 0x0836: +case 0x0837: + +// BTSTn +case 0x0830: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + src = 1 << (src & 7); + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + POST_IO +} +RET(18) + +// BTSTn +case 0x0838: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + src = 1 << (src & 7); + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + POST_IO +} +RET(16) + +// BTSTn +case 0x0839: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + src = 1 << (src & 7); + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + POST_IO +} +RET(20) + +// BTSTn +case 0x083A: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + src = 1 << (src & 7); + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + POST_IO +} +RET(16) + +// BTSTn +case 0x083B: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + src = 1 << (src & 7); + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + POST_IO +} +RET(18) + +// BTSTn +case 0x081F: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + src = 1 << (src & 7); + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + POST_IO +} +RET(12) + +// BTSTn +case 0x0827: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + src = 1 << (src & 7); + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + POST_IO +} +RET(14) +case 0x0841: +case 0x0842: +case 0x0843: +case 0x0844: +case 0x0845: +case 0x0846: +case 0x0847: + +// BCHGn +case 0x0840: +{ + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + src = 1 << (src & 31); + res = (u32)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_notZ = res & src; + res ^= src; + *((u32*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(12) +case 0x0851: +case 0x0852: +case 0x0853: +case 0x0854: +case 0x0855: +case 0x0856: +case 0x0857: + +// BCHGn +case 0x0850: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + src = 1 << (src & 7); + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + res ^= src; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0x0859: +case 0x085A: +case 0x085B: +case 0x085C: +case 0x085D: +case 0x085E: + +// BCHGn +case 0x0858: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + src = 1 << (src & 7); + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + res ^= src; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0x0861: +case 0x0862: +case 0x0863: +case 0x0864: +case 0x0865: +case 0x0866: + +// BCHGn +case 0x0860: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + src = 1 << (src & 7); + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + res ^= src; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) +case 0x0869: +case 0x086A: +case 0x086B: +case 0x086C: +case 0x086D: +case 0x086E: +case 0x086F: + +// BCHGn +case 0x0868: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + src = 1 << (src & 7); + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + res ^= src; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(20) +case 0x0871: +case 0x0872: +case 0x0873: +case 0x0874: +case 0x0875: +case 0x0876: +case 0x0877: + +// BCHGn +case 0x0870: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + src = 1 << (src & 7); + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + res ^= src; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(22) + +// BCHGn +case 0x0878: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + src = 1 << (src & 7); + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + res ^= src; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(20) + +// BCHGn +case 0x0879: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + src = 1 << (src & 7); + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + res ^= src; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(24) + +// BCHGn +case 0x085F: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + src = 1 << (src & 7); + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + res ^= src; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) + +// BCHGn +case 0x0867: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + src = 1 << (src & 7); + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + res ^= src; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) +case 0x0881: +case 0x0882: +case 0x0883: +case 0x0884: +case 0x0885: +case 0x0886: +case 0x0887: + +// BCLRn +case 0x0880: +{ + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + src = 1 << (src & 31); + res = (u32)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_notZ = res & src; + res &= ~src; + *((u32*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(14) +case 0x0891: +case 0x0892: +case 0x0893: +case 0x0894: +case 0x0895: +case 0x0896: +case 0x0897: + +// BCLRn +case 0x0890: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + src = 1 << (src & 7); + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + res &= ~src; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0x0899: +case 0x089A: +case 0x089B: +case 0x089C: +case 0x089D: +case 0x089E: + +// BCLRn +case 0x0898: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + src = 1 << (src & 7); + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + res &= ~src; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0x08A1: +case 0x08A2: +case 0x08A3: +case 0x08A4: +case 0x08A5: +case 0x08A6: + +// BCLRn +case 0x08A0: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + src = 1 << (src & 7); + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + res &= ~src; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) +case 0x08A9: +case 0x08AA: +case 0x08AB: +case 0x08AC: +case 0x08AD: +case 0x08AE: +case 0x08AF: + +// BCLRn +case 0x08A8: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + src = 1 << (src & 7); + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + res &= ~src; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(20) +case 0x08B1: +case 0x08B2: +case 0x08B3: +case 0x08B4: +case 0x08B5: +case 0x08B6: +case 0x08B7: + +// BCLRn +case 0x08B0: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + src = 1 << (src & 7); + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + res &= ~src; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(22) + +// BCLRn +case 0x08B8: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + src = 1 << (src & 7); + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + res &= ~src; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(20) + +// BCLRn +case 0x08B9: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + src = 1 << (src & 7); + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + res &= ~src; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(24) + +// BCLRn +case 0x089F: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + src = 1 << (src & 7); + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + res &= ~src; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) + +// BCLRn +case 0x08A7: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + src = 1 << (src & 7); + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + res &= ~src; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) +case 0x08C1: +case 0x08C2: +case 0x08C3: +case 0x08C4: +case 0x08C5: +case 0x08C6: +case 0x08C7: + +// BSETn +case 0x08C0: +{ + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + src = 1 << (src & 31); + res = (u32)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_notZ = res & src; + res |= src; + *((u32*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(12) +case 0x08D1: +case 0x08D2: +case 0x08D3: +case 0x08D4: +case 0x08D5: +case 0x08D6: +case 0x08D7: + +// BSETn +case 0x08D0: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + src = 1 << (src & 7); + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + res |= src; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0x08D9: +case 0x08DA: +case 0x08DB: +case 0x08DC: +case 0x08DD: +case 0x08DE: + +// BSETn +case 0x08D8: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + src = 1 << (src & 7); + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + res |= src; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0x08E1: +case 0x08E2: +case 0x08E3: +case 0x08E4: +case 0x08E5: +case 0x08E6: + +// BSETn +case 0x08E0: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + src = 1 << (src & 7); + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + res |= src; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) +case 0x08E9: +case 0x08EA: +case 0x08EB: +case 0x08EC: +case 0x08ED: +case 0x08EE: +case 0x08EF: + +// BSETn +case 0x08E8: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + src = 1 << (src & 7); + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + res |= src; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(20) +case 0x08F1: +case 0x08F2: +case 0x08F3: +case 0x08F4: +case 0x08F5: +case 0x08F6: +case 0x08F7: + +// BSETn +case 0x08F0: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + src = 1 << (src & 7); + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + res |= src; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(22) + +// BSETn +case 0x08F8: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + src = 1 << (src & 7); + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + res |= src; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(20) + +// BSETn +case 0x08F9: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + src = 1 << (src & 7); + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + res |= src; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(24) + +// BSETn +case 0x08DF: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + src = 1 << (src & 7); + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + res |= src; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) + +// BSETn +case 0x08E7: +{ + u32 adr; + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + src = 1 << (src & 7); + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + res |= src; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) +case 0x0300: +case 0x0500: +case 0x0700: +case 0x0900: +case 0x0B00: +case 0x0D00: +case 0x0F00: +case 0x0101: +case 0x0301: +case 0x0501: +case 0x0701: +case 0x0901: +case 0x0B01: +case 0x0D01: +case 0x0F01: +case 0x0102: +case 0x0302: +case 0x0502: +case 0x0702: +case 0x0902: +case 0x0B02: +case 0x0D02: +case 0x0F02: +case 0x0103: +case 0x0303: +case 0x0503: +case 0x0703: +case 0x0903: +case 0x0B03: +case 0x0D03: +case 0x0F03: +case 0x0104: +case 0x0304: +case 0x0504: +case 0x0704: +case 0x0904: +case 0x0B04: +case 0x0D04: +case 0x0F04: +case 0x0105: +case 0x0305: +case 0x0505: +case 0x0705: +case 0x0905: +case 0x0B05: +case 0x0D05: +case 0x0F05: +case 0x0106: +case 0x0306: +case 0x0506: +case 0x0706: +case 0x0906: +case 0x0B06: +case 0x0D06: +case 0x0F06: +case 0x0107: +case 0x0307: +case 0x0507: +case 0x0707: +case 0x0907: +case 0x0B07: +case 0x0D07: +case 0x0F07: + +// BTST +case 0x0100: +{ + u32 res; + pointer src; + src = (u32)CPU->D[(Opcode >> 9) & 7]; + src = 1 << (src & 31); + res = (u32)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_notZ = res & src; +} +RET(6) +case 0x0310: +case 0x0510: +case 0x0710: +case 0x0910: +case 0x0B10: +case 0x0D10: +case 0x0F10: +case 0x0111: +case 0x0311: +case 0x0511: +case 0x0711: +case 0x0911: +case 0x0B11: +case 0x0D11: +case 0x0F11: +case 0x0112: +case 0x0312: +case 0x0512: +case 0x0712: +case 0x0912: +case 0x0B12: +case 0x0D12: +case 0x0F12: +case 0x0113: +case 0x0313: +case 0x0513: +case 0x0713: +case 0x0913: +case 0x0B13: +case 0x0D13: +case 0x0F13: +case 0x0114: +case 0x0314: +case 0x0514: +case 0x0714: +case 0x0914: +case 0x0B14: +case 0x0D14: +case 0x0F14: +case 0x0115: +case 0x0315: +case 0x0515: +case 0x0715: +case 0x0915: +case 0x0B15: +case 0x0D15: +case 0x0F15: +case 0x0116: +case 0x0316: +case 0x0516: +case 0x0716: +case 0x0916: +case 0x0B16: +case 0x0D16: +case 0x0F16: +case 0x0117: +case 0x0317: +case 0x0517: +case 0x0717: +case 0x0917: +case 0x0B17: +case 0x0D17: +case 0x0F17: + +// BTST +case 0x0110: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + src = 1 << (src & 7); + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + POST_IO +} +RET(8) +case 0x0318: +case 0x0518: +case 0x0718: +case 0x0918: +case 0x0B18: +case 0x0D18: +case 0x0F18: +case 0x0119: +case 0x0319: +case 0x0519: +case 0x0719: +case 0x0919: +case 0x0B19: +case 0x0D19: +case 0x0F19: +case 0x011A: +case 0x031A: +case 0x051A: +case 0x071A: +case 0x091A: +case 0x0B1A: +case 0x0D1A: +case 0x0F1A: +case 0x011B: +case 0x031B: +case 0x051B: +case 0x071B: +case 0x091B: +case 0x0B1B: +case 0x0D1B: +case 0x0F1B: +case 0x011C: +case 0x031C: +case 0x051C: +case 0x071C: +case 0x091C: +case 0x0B1C: +case 0x0D1C: +case 0x0F1C: +case 0x011D: +case 0x031D: +case 0x051D: +case 0x071D: +case 0x091D: +case 0x0B1D: +case 0x0D1D: +case 0x0F1D: +case 0x011E: +case 0x031E: +case 0x051E: +case 0x071E: +case 0x091E: +case 0x0B1E: +case 0x0D1E: +case 0x0F1E: + +// BTST +case 0x0118: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + src = 1 << (src & 7); + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + POST_IO +} +RET(8) +case 0x0320: +case 0x0520: +case 0x0720: +case 0x0920: +case 0x0B20: +case 0x0D20: +case 0x0F20: +case 0x0121: +case 0x0321: +case 0x0521: +case 0x0721: +case 0x0921: +case 0x0B21: +case 0x0D21: +case 0x0F21: +case 0x0122: +case 0x0322: +case 0x0522: +case 0x0722: +case 0x0922: +case 0x0B22: +case 0x0D22: +case 0x0F22: +case 0x0123: +case 0x0323: +case 0x0523: +case 0x0723: +case 0x0923: +case 0x0B23: +case 0x0D23: +case 0x0F23: +case 0x0124: +case 0x0324: +case 0x0524: +case 0x0724: +case 0x0924: +case 0x0B24: +case 0x0D24: +case 0x0F24: +case 0x0125: +case 0x0325: +case 0x0525: +case 0x0725: +case 0x0925: +case 0x0B25: +case 0x0D25: +case 0x0F25: +case 0x0126: +case 0x0326: +case 0x0526: +case 0x0726: +case 0x0926: +case 0x0B26: +case 0x0D26: +case 0x0F26: + +// BTST +case 0x0120: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + src = 1 << (src & 7); + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + POST_IO +} +RET(10) +case 0x0328: +case 0x0528: +case 0x0728: +case 0x0928: +case 0x0B28: +case 0x0D28: +case 0x0F28: +case 0x0129: +case 0x0329: +case 0x0529: +case 0x0729: +case 0x0929: +case 0x0B29: +case 0x0D29: +case 0x0F29: +case 0x012A: +case 0x032A: +case 0x052A: +case 0x072A: +case 0x092A: +case 0x0B2A: +case 0x0D2A: +case 0x0F2A: +case 0x012B: +case 0x032B: +case 0x052B: +case 0x072B: +case 0x092B: +case 0x0B2B: +case 0x0D2B: +case 0x0F2B: +case 0x012C: +case 0x032C: +case 0x052C: +case 0x072C: +case 0x092C: +case 0x0B2C: +case 0x0D2C: +case 0x0F2C: +case 0x012D: +case 0x032D: +case 0x052D: +case 0x072D: +case 0x092D: +case 0x0B2D: +case 0x0D2D: +case 0x0F2D: +case 0x012E: +case 0x032E: +case 0x052E: +case 0x072E: +case 0x092E: +case 0x0B2E: +case 0x0D2E: +case 0x0F2E: +case 0x012F: +case 0x032F: +case 0x052F: +case 0x072F: +case 0x092F: +case 0x0B2F: +case 0x0D2F: +case 0x0F2F: + +// BTST +case 0x0128: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + src = 1 << (src & 7); + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + POST_IO +} +RET(12) +case 0x0330: +case 0x0530: +case 0x0730: +case 0x0930: +case 0x0B30: +case 0x0D30: +case 0x0F30: +case 0x0131: +case 0x0331: +case 0x0531: +case 0x0731: +case 0x0931: +case 0x0B31: +case 0x0D31: +case 0x0F31: +case 0x0132: +case 0x0332: +case 0x0532: +case 0x0732: +case 0x0932: +case 0x0B32: +case 0x0D32: +case 0x0F32: +case 0x0133: +case 0x0333: +case 0x0533: +case 0x0733: +case 0x0933: +case 0x0B33: +case 0x0D33: +case 0x0F33: +case 0x0134: +case 0x0334: +case 0x0534: +case 0x0734: +case 0x0934: +case 0x0B34: +case 0x0D34: +case 0x0F34: +case 0x0135: +case 0x0335: +case 0x0535: +case 0x0735: +case 0x0935: +case 0x0B35: +case 0x0D35: +case 0x0F35: +case 0x0136: +case 0x0336: +case 0x0536: +case 0x0736: +case 0x0936: +case 0x0B36: +case 0x0D36: +case 0x0F36: +case 0x0137: +case 0x0337: +case 0x0537: +case 0x0737: +case 0x0937: +case 0x0B37: +case 0x0D37: +case 0x0F37: + +// BTST +case 0x0130: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + src = 1 << (src & 7); + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + POST_IO +} +RET(14) +case 0x0338: +case 0x0538: +case 0x0738: +case 0x0938: +case 0x0B38: +case 0x0D38: +case 0x0F38: + +// BTST +case 0x0138: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + src = 1 << (src & 7); + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + POST_IO +} +RET(12) +case 0x0339: +case 0x0539: +case 0x0739: +case 0x0939: +case 0x0B39: +case 0x0D39: +case 0x0F39: + +// BTST +case 0x0139: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + src = 1 << (src & 7); + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + POST_IO +} +RET(16) +case 0x033A: +case 0x053A: +case 0x073A: +case 0x093A: +case 0x0B3A: +case 0x0D3A: +case 0x0F3A: + +// BTST +case 0x013A: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + src = 1 << (src & 7); + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + POST_IO +} +RET(12) +case 0x033B: +case 0x053B: +case 0x073B: +case 0x093B: +case 0x0B3B: +case 0x0D3B: +case 0x0F3B: + +// BTST +case 0x013B: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + src = 1 << (src & 7); + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + POST_IO +} +RET(14) +case 0x033C: +case 0x053C: +case 0x073C: +case 0x093C: +case 0x0B3C: +case 0x0D3C: +case 0x0F3C: + +// BTST +case 0x013C: +{ + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + src = 1 << (src & 7); + res = FETCH_BYTE; + PC += 2; + CPU->flag_notZ = res & src; +} +RET(8) +case 0x031F: +case 0x051F: +case 0x071F: +case 0x091F: +case 0x0B1F: +case 0x0D1F: +case 0x0F1F: + +// BTST +case 0x011F: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + src = 1 << (src & 7); + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + POST_IO +} +RET(8) +case 0x0327: +case 0x0527: +case 0x0727: +case 0x0927: +case 0x0B27: +case 0x0D27: +case 0x0F27: + +// BTST +case 0x0127: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + src = 1 << (src & 7); + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + POST_IO +} +RET(10) +case 0x0340: +case 0x0540: +case 0x0740: +case 0x0940: +case 0x0B40: +case 0x0D40: +case 0x0F40: +case 0x0141: +case 0x0341: +case 0x0541: +case 0x0741: +case 0x0941: +case 0x0B41: +case 0x0D41: +case 0x0F41: +case 0x0142: +case 0x0342: +case 0x0542: +case 0x0742: +case 0x0942: +case 0x0B42: +case 0x0D42: +case 0x0F42: +case 0x0143: +case 0x0343: +case 0x0543: +case 0x0743: +case 0x0943: +case 0x0B43: +case 0x0D43: +case 0x0F43: +case 0x0144: +case 0x0344: +case 0x0544: +case 0x0744: +case 0x0944: +case 0x0B44: +case 0x0D44: +case 0x0F44: +case 0x0145: +case 0x0345: +case 0x0545: +case 0x0745: +case 0x0945: +case 0x0B45: +case 0x0D45: +case 0x0F45: +case 0x0146: +case 0x0346: +case 0x0546: +case 0x0746: +case 0x0946: +case 0x0B46: +case 0x0D46: +case 0x0F46: +case 0x0147: +case 0x0347: +case 0x0547: +case 0x0747: +case 0x0947: +case 0x0B47: +case 0x0D47: +case 0x0F47: + +// BCHG +case 0x0140: +{ + u32 res; + pointer src; + src = (u32)CPU->D[(Opcode >> 9) & 7]; + src = 1 << (src & 31); + res = (u32)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_notZ = res & src; + res ^= src; + *((u32*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(8) +case 0x0350: +case 0x0550: +case 0x0750: +case 0x0950: +case 0x0B50: +case 0x0D50: +case 0x0F50: +case 0x0151: +case 0x0351: +case 0x0551: +case 0x0751: +case 0x0951: +case 0x0B51: +case 0x0D51: +case 0x0F51: +case 0x0152: +case 0x0352: +case 0x0552: +case 0x0752: +case 0x0952: +case 0x0B52: +case 0x0D52: +case 0x0F52: +case 0x0153: +case 0x0353: +case 0x0553: +case 0x0753: +case 0x0953: +case 0x0B53: +case 0x0D53: +case 0x0F53: +case 0x0154: +case 0x0354: +case 0x0554: +case 0x0754: +case 0x0954: +case 0x0B54: +case 0x0D54: +case 0x0F54: +case 0x0155: +case 0x0355: +case 0x0555: +case 0x0755: +case 0x0955: +case 0x0B55: +case 0x0D55: +case 0x0F55: +case 0x0156: +case 0x0356: +case 0x0556: +case 0x0756: +case 0x0956: +case 0x0B56: +case 0x0D56: +case 0x0F56: +case 0x0157: +case 0x0357: +case 0x0557: +case 0x0757: +case 0x0957: +case 0x0B57: +case 0x0D57: +case 0x0F57: + +// BCHG +case 0x0150: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + src = 1 << (src & 7); + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + res ^= src; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0x0358: +case 0x0558: +case 0x0758: +case 0x0958: +case 0x0B58: +case 0x0D58: +case 0x0F58: +case 0x0159: +case 0x0359: +case 0x0559: +case 0x0759: +case 0x0959: +case 0x0B59: +case 0x0D59: +case 0x0F59: +case 0x015A: +case 0x035A: +case 0x055A: +case 0x075A: +case 0x095A: +case 0x0B5A: +case 0x0D5A: +case 0x0F5A: +case 0x015B: +case 0x035B: +case 0x055B: +case 0x075B: +case 0x095B: +case 0x0B5B: +case 0x0D5B: +case 0x0F5B: +case 0x015C: +case 0x035C: +case 0x055C: +case 0x075C: +case 0x095C: +case 0x0B5C: +case 0x0D5C: +case 0x0F5C: +case 0x015D: +case 0x035D: +case 0x055D: +case 0x075D: +case 0x095D: +case 0x0B5D: +case 0x0D5D: +case 0x0F5D: +case 0x015E: +case 0x035E: +case 0x055E: +case 0x075E: +case 0x095E: +case 0x0B5E: +case 0x0D5E: +case 0x0F5E: + +// BCHG +case 0x0158: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + src = 1 << (src & 7); + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + res ^= src; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0x0360: +case 0x0560: +case 0x0760: +case 0x0960: +case 0x0B60: +case 0x0D60: +case 0x0F60: +case 0x0161: +case 0x0361: +case 0x0561: +case 0x0761: +case 0x0961: +case 0x0B61: +case 0x0D61: +case 0x0F61: +case 0x0162: +case 0x0362: +case 0x0562: +case 0x0762: +case 0x0962: +case 0x0B62: +case 0x0D62: +case 0x0F62: +case 0x0163: +case 0x0363: +case 0x0563: +case 0x0763: +case 0x0963: +case 0x0B63: +case 0x0D63: +case 0x0F63: +case 0x0164: +case 0x0364: +case 0x0564: +case 0x0764: +case 0x0964: +case 0x0B64: +case 0x0D64: +case 0x0F64: +case 0x0165: +case 0x0365: +case 0x0565: +case 0x0765: +case 0x0965: +case 0x0B65: +case 0x0D65: +case 0x0F65: +case 0x0166: +case 0x0366: +case 0x0566: +case 0x0766: +case 0x0966: +case 0x0B66: +case 0x0D66: +case 0x0F66: + +// BCHG +case 0x0160: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + src = 1 << (src & 7); + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + res ^= src; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(14) +case 0x0368: +case 0x0568: +case 0x0768: +case 0x0968: +case 0x0B68: +case 0x0D68: +case 0x0F68: +case 0x0169: +case 0x0369: +case 0x0569: +case 0x0769: +case 0x0969: +case 0x0B69: +case 0x0D69: +case 0x0F69: +case 0x016A: +case 0x036A: +case 0x056A: +case 0x076A: +case 0x096A: +case 0x0B6A: +case 0x0D6A: +case 0x0F6A: +case 0x016B: +case 0x036B: +case 0x056B: +case 0x076B: +case 0x096B: +case 0x0B6B: +case 0x0D6B: +case 0x0F6B: +case 0x016C: +case 0x036C: +case 0x056C: +case 0x076C: +case 0x096C: +case 0x0B6C: +case 0x0D6C: +case 0x0F6C: +case 0x016D: +case 0x036D: +case 0x056D: +case 0x076D: +case 0x096D: +case 0x0B6D: +case 0x0D6D: +case 0x0F6D: +case 0x016E: +case 0x036E: +case 0x056E: +case 0x076E: +case 0x096E: +case 0x0B6E: +case 0x0D6E: +case 0x0F6E: +case 0x016F: +case 0x036F: +case 0x056F: +case 0x076F: +case 0x096F: +case 0x0B6F: +case 0x0D6F: +case 0x0F6F: + +// BCHG +case 0x0168: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + src = 1 << (src & 7); + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + res ^= src; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0x0370: +case 0x0570: +case 0x0770: +case 0x0970: +case 0x0B70: +case 0x0D70: +case 0x0F70: +case 0x0171: +case 0x0371: +case 0x0571: +case 0x0771: +case 0x0971: +case 0x0B71: +case 0x0D71: +case 0x0F71: +case 0x0172: +case 0x0372: +case 0x0572: +case 0x0772: +case 0x0972: +case 0x0B72: +case 0x0D72: +case 0x0F72: +case 0x0173: +case 0x0373: +case 0x0573: +case 0x0773: +case 0x0973: +case 0x0B73: +case 0x0D73: +case 0x0F73: +case 0x0174: +case 0x0374: +case 0x0574: +case 0x0774: +case 0x0974: +case 0x0B74: +case 0x0D74: +case 0x0F74: +case 0x0175: +case 0x0375: +case 0x0575: +case 0x0775: +case 0x0975: +case 0x0B75: +case 0x0D75: +case 0x0F75: +case 0x0176: +case 0x0376: +case 0x0576: +case 0x0776: +case 0x0976: +case 0x0B76: +case 0x0D76: +case 0x0F76: +case 0x0177: +case 0x0377: +case 0x0577: +case 0x0777: +case 0x0977: +case 0x0B77: +case 0x0D77: +case 0x0F77: + +// BCHG +case 0x0170: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + src = 1 << (src & 7); + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + res ^= src; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) +case 0x0378: +case 0x0578: +case 0x0778: +case 0x0978: +case 0x0B78: +case 0x0D78: +case 0x0F78: + +// BCHG +case 0x0178: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + src = 1 << (src & 7); + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + res ^= src; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0x0379: +case 0x0579: +case 0x0779: +case 0x0979: +case 0x0B79: +case 0x0D79: +case 0x0F79: + +// BCHG +case 0x0179: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + src = 1 << (src & 7); + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + res ^= src; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(20) +case 0x035F: +case 0x055F: +case 0x075F: +case 0x095F: +case 0x0B5F: +case 0x0D5F: +case 0x0F5F: + +// BCHG +case 0x015F: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + src = 1 << (src & 7); + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + res ^= src; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0x0367: +case 0x0567: +case 0x0767: +case 0x0967: +case 0x0B67: +case 0x0D67: +case 0x0F67: + +// BCHG +case 0x0167: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + src = 1 << (src & 7); + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + res ^= src; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(14) +case 0x0380: +case 0x0580: +case 0x0780: +case 0x0980: +case 0x0B80: +case 0x0D80: +case 0x0F80: +case 0x0181: +case 0x0381: +case 0x0581: +case 0x0781: +case 0x0981: +case 0x0B81: +case 0x0D81: +case 0x0F81: +case 0x0182: +case 0x0382: +case 0x0582: +case 0x0782: +case 0x0982: +case 0x0B82: +case 0x0D82: +case 0x0F82: +case 0x0183: +case 0x0383: +case 0x0583: +case 0x0783: +case 0x0983: +case 0x0B83: +case 0x0D83: +case 0x0F83: +case 0x0184: +case 0x0384: +case 0x0584: +case 0x0784: +case 0x0984: +case 0x0B84: +case 0x0D84: +case 0x0F84: +case 0x0185: +case 0x0385: +case 0x0585: +case 0x0785: +case 0x0985: +case 0x0B85: +case 0x0D85: +case 0x0F85: +case 0x0186: +case 0x0386: +case 0x0586: +case 0x0786: +case 0x0986: +case 0x0B86: +case 0x0D86: +case 0x0F86: +case 0x0187: +case 0x0387: +case 0x0587: +case 0x0787: +case 0x0987: +case 0x0B87: +case 0x0D87: +case 0x0F87: + +// BCLR +case 0x0180: +{ + u32 res; + pointer src; + src = (u32)CPU->D[(Opcode >> 9) & 7]; + src = 1 << (src & 31); + res = (u32)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_notZ = res & src; + res &= ~src; + *((u32*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(10) +case 0x0390: +case 0x0590: +case 0x0790: +case 0x0990: +case 0x0B90: +case 0x0D90: +case 0x0F90: +case 0x0191: +case 0x0391: +case 0x0591: +case 0x0791: +case 0x0991: +case 0x0B91: +case 0x0D91: +case 0x0F91: +case 0x0192: +case 0x0392: +case 0x0592: +case 0x0792: +case 0x0992: +case 0x0B92: +case 0x0D92: +case 0x0F92: +case 0x0193: +case 0x0393: +case 0x0593: +case 0x0793: +case 0x0993: +case 0x0B93: +case 0x0D93: +case 0x0F93: +case 0x0194: +case 0x0394: +case 0x0594: +case 0x0794: +case 0x0994: +case 0x0B94: +case 0x0D94: +case 0x0F94: +case 0x0195: +case 0x0395: +case 0x0595: +case 0x0795: +case 0x0995: +case 0x0B95: +case 0x0D95: +case 0x0F95: +case 0x0196: +case 0x0396: +case 0x0596: +case 0x0796: +case 0x0996: +case 0x0B96: +case 0x0D96: +case 0x0F96: +case 0x0197: +case 0x0397: +case 0x0597: +case 0x0797: +case 0x0997: +case 0x0B97: +case 0x0D97: +case 0x0F97: + +// BCLR +case 0x0190: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + src = 1 << (src & 7); + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + res &= ~src; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0x0398: +case 0x0598: +case 0x0798: +case 0x0998: +case 0x0B98: +case 0x0D98: +case 0x0F98: +case 0x0199: +case 0x0399: +case 0x0599: +case 0x0799: +case 0x0999: +case 0x0B99: +case 0x0D99: +case 0x0F99: +case 0x019A: +case 0x039A: +case 0x059A: +case 0x079A: +case 0x099A: +case 0x0B9A: +case 0x0D9A: +case 0x0F9A: +case 0x019B: +case 0x039B: +case 0x059B: +case 0x079B: +case 0x099B: +case 0x0B9B: +case 0x0D9B: +case 0x0F9B: +case 0x019C: +case 0x039C: +case 0x059C: +case 0x079C: +case 0x099C: +case 0x0B9C: +case 0x0D9C: +case 0x0F9C: +case 0x019D: +case 0x039D: +case 0x059D: +case 0x079D: +case 0x099D: +case 0x0B9D: +case 0x0D9D: +case 0x0F9D: +case 0x019E: +case 0x039E: +case 0x059E: +case 0x079E: +case 0x099E: +case 0x0B9E: +case 0x0D9E: +case 0x0F9E: + +// BCLR +case 0x0198: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + src = 1 << (src & 7); + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + res &= ~src; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0x03A0: +case 0x05A0: +case 0x07A0: +case 0x09A0: +case 0x0BA0: +case 0x0DA0: +case 0x0FA0: +case 0x01A1: +case 0x03A1: +case 0x05A1: +case 0x07A1: +case 0x09A1: +case 0x0BA1: +case 0x0DA1: +case 0x0FA1: +case 0x01A2: +case 0x03A2: +case 0x05A2: +case 0x07A2: +case 0x09A2: +case 0x0BA2: +case 0x0DA2: +case 0x0FA2: +case 0x01A3: +case 0x03A3: +case 0x05A3: +case 0x07A3: +case 0x09A3: +case 0x0BA3: +case 0x0DA3: +case 0x0FA3: +case 0x01A4: +case 0x03A4: +case 0x05A4: +case 0x07A4: +case 0x09A4: +case 0x0BA4: +case 0x0DA4: +case 0x0FA4: +case 0x01A5: +case 0x03A5: +case 0x05A5: +case 0x07A5: +case 0x09A5: +case 0x0BA5: +case 0x0DA5: +case 0x0FA5: +case 0x01A6: +case 0x03A6: +case 0x05A6: +case 0x07A6: +case 0x09A6: +case 0x0BA6: +case 0x0DA6: +case 0x0FA6: + +// BCLR +case 0x01A0: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + src = 1 << (src & 7); + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + res &= ~src; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(14) +case 0x03A8: +case 0x05A8: +case 0x07A8: +case 0x09A8: +case 0x0BA8: +case 0x0DA8: +case 0x0FA8: +case 0x01A9: +case 0x03A9: +case 0x05A9: +case 0x07A9: +case 0x09A9: +case 0x0BA9: +case 0x0DA9: +case 0x0FA9: +case 0x01AA: +case 0x03AA: +case 0x05AA: +case 0x07AA: +case 0x09AA: +case 0x0BAA: +case 0x0DAA: +case 0x0FAA: +case 0x01AB: +case 0x03AB: +case 0x05AB: +case 0x07AB: +case 0x09AB: +case 0x0BAB: +case 0x0DAB: +case 0x0FAB: +case 0x01AC: +case 0x03AC: +case 0x05AC: +case 0x07AC: +case 0x09AC: +case 0x0BAC: +case 0x0DAC: +case 0x0FAC: +case 0x01AD: +case 0x03AD: +case 0x05AD: +case 0x07AD: +case 0x09AD: +case 0x0BAD: +case 0x0DAD: +case 0x0FAD: +case 0x01AE: +case 0x03AE: +case 0x05AE: +case 0x07AE: +case 0x09AE: +case 0x0BAE: +case 0x0DAE: +case 0x0FAE: +case 0x01AF: +case 0x03AF: +case 0x05AF: +case 0x07AF: +case 0x09AF: +case 0x0BAF: +case 0x0DAF: +case 0x0FAF: + +// BCLR +case 0x01A8: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + src = 1 << (src & 7); + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + res &= ~src; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0x03B0: +case 0x05B0: +case 0x07B0: +case 0x09B0: +case 0x0BB0: +case 0x0DB0: +case 0x0FB0: +case 0x01B1: +case 0x03B1: +case 0x05B1: +case 0x07B1: +case 0x09B1: +case 0x0BB1: +case 0x0DB1: +case 0x0FB1: +case 0x01B2: +case 0x03B2: +case 0x05B2: +case 0x07B2: +case 0x09B2: +case 0x0BB2: +case 0x0DB2: +case 0x0FB2: +case 0x01B3: +case 0x03B3: +case 0x05B3: +case 0x07B3: +case 0x09B3: +case 0x0BB3: +case 0x0DB3: +case 0x0FB3: +case 0x01B4: +case 0x03B4: +case 0x05B4: +case 0x07B4: +case 0x09B4: +case 0x0BB4: +case 0x0DB4: +case 0x0FB4: +case 0x01B5: +case 0x03B5: +case 0x05B5: +case 0x07B5: +case 0x09B5: +case 0x0BB5: +case 0x0DB5: +case 0x0FB5: +case 0x01B6: +case 0x03B6: +case 0x05B6: +case 0x07B6: +case 0x09B6: +case 0x0BB6: +case 0x0DB6: +case 0x0FB6: +case 0x01B7: +case 0x03B7: +case 0x05B7: +case 0x07B7: +case 0x09B7: +case 0x0BB7: +case 0x0DB7: +case 0x0FB7: + +// BCLR +case 0x01B0: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + src = 1 << (src & 7); + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + res &= ~src; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) +case 0x03B8: +case 0x05B8: +case 0x07B8: +case 0x09B8: +case 0x0BB8: +case 0x0DB8: +case 0x0FB8: + +// BCLR +case 0x01B8: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + src = 1 << (src & 7); + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + res &= ~src; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0x03B9: +case 0x05B9: +case 0x07B9: +case 0x09B9: +case 0x0BB9: +case 0x0DB9: +case 0x0FB9: + +// BCLR +case 0x01B9: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + src = 1 << (src & 7); + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + res &= ~src; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(20) +case 0x039F: +case 0x059F: +case 0x079F: +case 0x099F: +case 0x0B9F: +case 0x0D9F: +case 0x0F9F: + +// BCLR +case 0x019F: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + src = 1 << (src & 7); + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + res &= ~src; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0x03A7: +case 0x05A7: +case 0x07A7: +case 0x09A7: +case 0x0BA7: +case 0x0DA7: +case 0x0FA7: + +// BCLR +case 0x01A7: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + src = 1 << (src & 7); + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + res &= ~src; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(14) +case 0x03C0: +case 0x05C0: +case 0x07C0: +case 0x09C0: +case 0x0BC0: +case 0x0DC0: +case 0x0FC0: +case 0x01C1: +case 0x03C1: +case 0x05C1: +case 0x07C1: +case 0x09C1: +case 0x0BC1: +case 0x0DC1: +case 0x0FC1: +case 0x01C2: +case 0x03C2: +case 0x05C2: +case 0x07C2: +case 0x09C2: +case 0x0BC2: +case 0x0DC2: +case 0x0FC2: +case 0x01C3: +case 0x03C3: +case 0x05C3: +case 0x07C3: +case 0x09C3: +case 0x0BC3: +case 0x0DC3: +case 0x0FC3: +case 0x01C4: +case 0x03C4: +case 0x05C4: +case 0x07C4: +case 0x09C4: +case 0x0BC4: +case 0x0DC4: +case 0x0FC4: +case 0x01C5: +case 0x03C5: +case 0x05C5: +case 0x07C5: +case 0x09C5: +case 0x0BC5: +case 0x0DC5: +case 0x0FC5: +case 0x01C6: +case 0x03C6: +case 0x05C6: +case 0x07C6: +case 0x09C6: +case 0x0BC6: +case 0x0DC6: +case 0x0FC6: +case 0x01C7: +case 0x03C7: +case 0x05C7: +case 0x07C7: +case 0x09C7: +case 0x0BC7: +case 0x0DC7: +case 0x0FC7: + +// BSET +case 0x01C0: +{ + u32 res; + pointer src; + src = (u32)CPU->D[(Opcode >> 9) & 7]; + src = 1 << (src & 31); + res = (u32)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_notZ = res & src; + res |= src; + *((u32*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(8) +case 0x03D0: +case 0x05D0: +case 0x07D0: +case 0x09D0: +case 0x0BD0: +case 0x0DD0: +case 0x0FD0: +case 0x01D1: +case 0x03D1: +case 0x05D1: +case 0x07D1: +case 0x09D1: +case 0x0BD1: +case 0x0DD1: +case 0x0FD1: +case 0x01D2: +case 0x03D2: +case 0x05D2: +case 0x07D2: +case 0x09D2: +case 0x0BD2: +case 0x0DD2: +case 0x0FD2: +case 0x01D3: +case 0x03D3: +case 0x05D3: +case 0x07D3: +case 0x09D3: +case 0x0BD3: +case 0x0DD3: +case 0x0FD3: +case 0x01D4: +case 0x03D4: +case 0x05D4: +case 0x07D4: +case 0x09D4: +case 0x0BD4: +case 0x0DD4: +case 0x0FD4: +case 0x01D5: +case 0x03D5: +case 0x05D5: +case 0x07D5: +case 0x09D5: +case 0x0BD5: +case 0x0DD5: +case 0x0FD5: +case 0x01D6: +case 0x03D6: +case 0x05D6: +case 0x07D6: +case 0x09D6: +case 0x0BD6: +case 0x0DD6: +case 0x0FD6: +case 0x01D7: +case 0x03D7: +case 0x05D7: +case 0x07D7: +case 0x09D7: +case 0x0BD7: +case 0x0DD7: +case 0x0FD7: + +// BSET +case 0x01D0: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + src = 1 << (src & 7); + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + res |= src; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0x03D8: +case 0x05D8: +case 0x07D8: +case 0x09D8: +case 0x0BD8: +case 0x0DD8: +case 0x0FD8: +case 0x01D9: +case 0x03D9: +case 0x05D9: +case 0x07D9: +case 0x09D9: +case 0x0BD9: +case 0x0DD9: +case 0x0FD9: +case 0x01DA: +case 0x03DA: +case 0x05DA: +case 0x07DA: +case 0x09DA: +case 0x0BDA: +case 0x0DDA: +case 0x0FDA: +case 0x01DB: +case 0x03DB: +case 0x05DB: +case 0x07DB: +case 0x09DB: +case 0x0BDB: +case 0x0DDB: +case 0x0FDB: +case 0x01DC: +case 0x03DC: +case 0x05DC: +case 0x07DC: +case 0x09DC: +case 0x0BDC: +case 0x0DDC: +case 0x0FDC: +case 0x01DD: +case 0x03DD: +case 0x05DD: +case 0x07DD: +case 0x09DD: +case 0x0BDD: +case 0x0DDD: +case 0x0FDD: +case 0x01DE: +case 0x03DE: +case 0x05DE: +case 0x07DE: +case 0x09DE: +case 0x0BDE: +case 0x0DDE: +case 0x0FDE: + +// BSET +case 0x01D8: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + src = 1 << (src & 7); + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + res |= src; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0x03E0: +case 0x05E0: +case 0x07E0: +case 0x09E0: +case 0x0BE0: +case 0x0DE0: +case 0x0FE0: +case 0x01E1: +case 0x03E1: +case 0x05E1: +case 0x07E1: +case 0x09E1: +case 0x0BE1: +case 0x0DE1: +case 0x0FE1: +case 0x01E2: +case 0x03E2: +case 0x05E2: +case 0x07E2: +case 0x09E2: +case 0x0BE2: +case 0x0DE2: +case 0x0FE2: +case 0x01E3: +case 0x03E3: +case 0x05E3: +case 0x07E3: +case 0x09E3: +case 0x0BE3: +case 0x0DE3: +case 0x0FE3: +case 0x01E4: +case 0x03E4: +case 0x05E4: +case 0x07E4: +case 0x09E4: +case 0x0BE4: +case 0x0DE4: +case 0x0FE4: +case 0x01E5: +case 0x03E5: +case 0x05E5: +case 0x07E5: +case 0x09E5: +case 0x0BE5: +case 0x0DE5: +case 0x0FE5: +case 0x01E6: +case 0x03E6: +case 0x05E6: +case 0x07E6: +case 0x09E6: +case 0x0BE6: +case 0x0DE6: +case 0x0FE6: + +// BSET +case 0x01E0: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + src = 1 << (src & 7); + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + res |= src; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(14) +case 0x03E8: +case 0x05E8: +case 0x07E8: +case 0x09E8: +case 0x0BE8: +case 0x0DE8: +case 0x0FE8: +case 0x01E9: +case 0x03E9: +case 0x05E9: +case 0x07E9: +case 0x09E9: +case 0x0BE9: +case 0x0DE9: +case 0x0FE9: +case 0x01EA: +case 0x03EA: +case 0x05EA: +case 0x07EA: +case 0x09EA: +case 0x0BEA: +case 0x0DEA: +case 0x0FEA: +case 0x01EB: +case 0x03EB: +case 0x05EB: +case 0x07EB: +case 0x09EB: +case 0x0BEB: +case 0x0DEB: +case 0x0FEB: +case 0x01EC: +case 0x03EC: +case 0x05EC: +case 0x07EC: +case 0x09EC: +case 0x0BEC: +case 0x0DEC: +case 0x0FEC: +case 0x01ED: +case 0x03ED: +case 0x05ED: +case 0x07ED: +case 0x09ED: +case 0x0BED: +case 0x0DED: +case 0x0FED: +case 0x01EE: +case 0x03EE: +case 0x05EE: +case 0x07EE: +case 0x09EE: +case 0x0BEE: +case 0x0DEE: +case 0x0FEE: +case 0x01EF: +case 0x03EF: +case 0x05EF: +case 0x07EF: +case 0x09EF: +case 0x0BEF: +case 0x0DEF: +case 0x0FEF: + +// BSET +case 0x01E8: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + src = 1 << (src & 7); + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + res |= src; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0x03F0: +case 0x05F0: +case 0x07F0: +case 0x09F0: +case 0x0BF0: +case 0x0DF0: +case 0x0FF0: +case 0x01F1: +case 0x03F1: +case 0x05F1: +case 0x07F1: +case 0x09F1: +case 0x0BF1: +case 0x0DF1: +case 0x0FF1: +case 0x01F2: +case 0x03F2: +case 0x05F2: +case 0x07F2: +case 0x09F2: +case 0x0BF2: +case 0x0DF2: +case 0x0FF2: +case 0x01F3: +case 0x03F3: +case 0x05F3: +case 0x07F3: +case 0x09F3: +case 0x0BF3: +case 0x0DF3: +case 0x0FF3: +case 0x01F4: +case 0x03F4: +case 0x05F4: +case 0x07F4: +case 0x09F4: +case 0x0BF4: +case 0x0DF4: +case 0x0FF4: +case 0x01F5: +case 0x03F5: +case 0x05F5: +case 0x07F5: +case 0x09F5: +case 0x0BF5: +case 0x0DF5: +case 0x0FF5: +case 0x01F6: +case 0x03F6: +case 0x05F6: +case 0x07F6: +case 0x09F6: +case 0x0BF6: +case 0x0DF6: +case 0x0FF6: +case 0x01F7: +case 0x03F7: +case 0x05F7: +case 0x07F7: +case 0x09F7: +case 0x0BF7: +case 0x0DF7: +case 0x0FF7: + +// BSET +case 0x01F0: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + src = 1 << (src & 7); + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + res |= src; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) +case 0x03F8: +case 0x05F8: +case 0x07F8: +case 0x09F8: +case 0x0BF8: +case 0x0DF8: +case 0x0FF8: + +// BSET +case 0x01F8: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + src = 1 << (src & 7); + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + res |= src; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0x03F9: +case 0x05F9: +case 0x07F9: +case 0x09F9: +case 0x0BF9: +case 0x0DF9: +case 0x0FF9: + +// BSET +case 0x01F9: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + src = 1 << (src & 7); + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + res |= src; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(20) +case 0x03DF: +case 0x05DF: +case 0x07DF: +case 0x09DF: +case 0x0BDF: +case 0x0DDF: +case 0x0FDF: + +// BSET +case 0x01DF: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + src = 1 << (src & 7); + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + res |= src; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0x03E7: +case 0x05E7: +case 0x07E7: +case 0x09E7: +case 0x0BE7: +case 0x0DE7: +case 0x0FE7: + +// BSET +case 0x01E7: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + src = 1 << (src & 7); + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_notZ = res & src; + res |= src; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(14) +case 0x0308: +case 0x0508: +case 0x0708: +case 0x0908: +case 0x0B08: +case 0x0D08: +case 0x0F08: +case 0x0109: +case 0x0309: +case 0x0509: +case 0x0709: +case 0x0909: +case 0x0B09: +case 0x0D09: +case 0x0F09: +case 0x010A: +case 0x030A: +case 0x050A: +case 0x070A: +case 0x090A: +case 0x0B0A: +case 0x0D0A: +case 0x0F0A: +case 0x010B: +case 0x030B: +case 0x050B: +case 0x070B: +case 0x090B: +case 0x0B0B: +case 0x0D0B: +case 0x0F0B: +case 0x010C: +case 0x030C: +case 0x050C: +case 0x070C: +case 0x090C: +case 0x0B0C: +case 0x0D0C: +case 0x0F0C: +case 0x010D: +case 0x030D: +case 0x050D: +case 0x070D: +case 0x090D: +case 0x0B0D: +case 0x0D0D: +case 0x0F0D: +case 0x010E: +case 0x030E: +case 0x050E: +case 0x070E: +case 0x090E: +case 0x0B0E: +case 0x0D0E: +case 0x0F0E: +case 0x010F: +case 0x030F: +case 0x050F: +case 0x070F: +case 0x090F: +case 0x0B0F: +case 0x0D0F: +case 0x0F0F: + +// MOVEPWaD +case 0x0108: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr + 0, res) + READ_BYTE_F(adr + 2, src) + *(u16*)(&CPU->D[(Opcode >> 9) & 7]) = (res << 8) | src; + POST_IO +} +RET(24) +case 0x0348: +case 0x0548: +case 0x0748: +case 0x0948: +case 0x0B48: +case 0x0D48: +case 0x0F48: +case 0x0149: +case 0x0349: +case 0x0549: +case 0x0749: +case 0x0949: +case 0x0B49: +case 0x0D49: +case 0x0F49: +case 0x014A: +case 0x034A: +case 0x054A: +case 0x074A: +case 0x094A: +case 0x0B4A: +case 0x0D4A: +case 0x0F4A: +case 0x014B: +case 0x034B: +case 0x054B: +case 0x074B: +case 0x094B: +case 0x0B4B: +case 0x0D4B: +case 0x0F4B: +case 0x014C: +case 0x034C: +case 0x054C: +case 0x074C: +case 0x094C: +case 0x0B4C: +case 0x0D4C: +case 0x0F4C: +case 0x014D: +case 0x034D: +case 0x054D: +case 0x074D: +case 0x094D: +case 0x0B4D: +case 0x0D4D: +case 0x0F4D: +case 0x014E: +case 0x034E: +case 0x054E: +case 0x074E: +case 0x094E: +case 0x0B4E: +case 0x0D4E: +case 0x0F4E: +case 0x014F: +case 0x034F: +case 0x054F: +case 0x074F: +case 0x094F: +case 0x0B4F: +case 0x0D4F: +case 0x0F4F: + +// MOVEPLaD +case 0x0148: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + res <<= 24; + adr += 2; + READ_BYTE_F(adr, src) + res |= src << 16; + adr += 2; + READ_BYTE_F(adr, src) + res |= src << 8; + adr += 2; + READ_BYTE_F(adr, src) + CPU->D[(Opcode >> 9) & 7] = res | src; + POST_IO +} +RET(32) +case 0x0388: +case 0x0588: +case 0x0788: +case 0x0988: +case 0x0B88: +case 0x0D88: +case 0x0F88: +case 0x0189: +case 0x0389: +case 0x0589: +case 0x0789: +case 0x0989: +case 0x0B89: +case 0x0D89: +case 0x0F89: +case 0x018A: +case 0x038A: +case 0x058A: +case 0x078A: +case 0x098A: +case 0x0B8A: +case 0x0D8A: +case 0x0F8A: +case 0x018B: +case 0x038B: +case 0x058B: +case 0x078B: +case 0x098B: +case 0x0B8B: +case 0x0D8B: +case 0x0F8B: +case 0x018C: +case 0x038C: +case 0x058C: +case 0x078C: +case 0x098C: +case 0x0B8C: +case 0x0D8C: +case 0x0F8C: +case 0x018D: +case 0x038D: +case 0x058D: +case 0x078D: +case 0x098D: +case 0x0B8D: +case 0x0D8D: +case 0x0F8D: +case 0x018E: +case 0x038E: +case 0x058E: +case 0x078E: +case 0x098E: +case 0x0B8E: +case 0x0D8E: +case 0x0F8E: +case 0x018F: +case 0x038F: +case 0x058F: +case 0x078F: +case 0x098F: +case 0x0B8F: +case 0x0D8F: +case 0x0F8F: + +// MOVEPWDa +case 0x0188: +{ + u32 adr; + u32 res; + res = (u32)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + WRITE_BYTE_F(adr + 0, res >> 8) + WRITE_BYTE_F(adr + 2, res >> 0) + POST_IO +} +RET(24) +case 0x03C8: +case 0x05C8: +case 0x07C8: +case 0x09C8: +case 0x0BC8: +case 0x0DC8: +case 0x0FC8: +case 0x01C9: +case 0x03C9: +case 0x05C9: +case 0x07C9: +case 0x09C9: +case 0x0BC9: +case 0x0DC9: +case 0x0FC9: +case 0x01CA: +case 0x03CA: +case 0x05CA: +case 0x07CA: +case 0x09CA: +case 0x0BCA: +case 0x0DCA: +case 0x0FCA: +case 0x01CB: +case 0x03CB: +case 0x05CB: +case 0x07CB: +case 0x09CB: +case 0x0BCB: +case 0x0DCB: +case 0x0FCB: +case 0x01CC: +case 0x03CC: +case 0x05CC: +case 0x07CC: +case 0x09CC: +case 0x0BCC: +case 0x0DCC: +case 0x0FCC: +case 0x01CD: +case 0x03CD: +case 0x05CD: +case 0x07CD: +case 0x09CD: +case 0x0BCD: +case 0x0DCD: +case 0x0FCD: +case 0x01CE: +case 0x03CE: +case 0x05CE: +case 0x07CE: +case 0x09CE: +case 0x0BCE: +case 0x0DCE: +case 0x0FCE: +case 0x01CF: +case 0x03CF: +case 0x05CF: +case 0x07CF: +case 0x09CF: +case 0x0BCF: +case 0x0DCF: +case 0x0FCF: + +// MOVEPLDa +case 0x01C8: +{ + u32 adr; + u32 res; + res = (u32)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + WRITE_BYTE_F(adr, res >> 24) + adr += 2; + WRITE_BYTE_F(adr, res >> 16) + adr += 2; + WRITE_BYTE_F(adr, res >> 8) + adr += 2; + WRITE_BYTE_F(adr, res >> 0) + POST_IO +} +RET(32) diff --git a/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68k_op1.inc b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68k_op1.inc new file mode 100644 index 000000000..d8add1a98 --- /dev/null +++ b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68k_op1.inc @@ -0,0 +1,5629 @@ +case 0x1200: +case 0x1400: +case 0x1600: +case 0x1800: +case 0x1A00: +case 0x1C00: +case 0x1E00: +case 0x1001: +case 0x1201: +case 0x1401: +case 0x1601: +case 0x1801: +case 0x1A01: +case 0x1C01: +case 0x1E01: +case 0x1002: +case 0x1202: +case 0x1402: +case 0x1602: +case 0x1802: +case 0x1A02: +case 0x1C02: +case 0x1E02: +case 0x1003: +case 0x1203: +case 0x1403: +case 0x1603: +case 0x1803: +case 0x1A03: +case 0x1C03: +case 0x1E03: +case 0x1004: +case 0x1204: +case 0x1404: +case 0x1604: +case 0x1804: +case 0x1A04: +case 0x1C04: +case 0x1E04: +case 0x1005: +case 0x1205: +case 0x1405: +case 0x1605: +case 0x1805: +case 0x1A05: +case 0x1C05: +case 0x1E05: +case 0x1006: +case 0x1206: +case 0x1406: +case 0x1606: +case 0x1806: +case 0x1A06: +case 0x1C06: +case 0x1E06: +case 0x1007: +case 0x1207: +case 0x1407: +case 0x1607: +case 0x1807: +case 0x1A07: +case 0x1C07: +case 0x1E07: + +// MOVEB +case 0x1000: +{ + u32 res; + res = (u8)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; +} +RET(4) +case 0x1280: +case 0x1480: +case 0x1680: +case 0x1880: +case 0x1A80: +case 0x1C80: +case 0x1E80: +case 0x1081: +case 0x1281: +case 0x1481: +case 0x1681: +case 0x1881: +case 0x1A81: +case 0x1C81: +case 0x1E81: +case 0x1082: +case 0x1282: +case 0x1482: +case 0x1682: +case 0x1882: +case 0x1A82: +case 0x1C82: +case 0x1E82: +case 0x1083: +case 0x1283: +case 0x1483: +case 0x1683: +case 0x1883: +case 0x1A83: +case 0x1C83: +case 0x1E83: +case 0x1084: +case 0x1284: +case 0x1484: +case 0x1684: +case 0x1884: +case 0x1A84: +case 0x1C84: +case 0x1E84: +case 0x1085: +case 0x1285: +case 0x1485: +case 0x1685: +case 0x1885: +case 0x1A85: +case 0x1C85: +case 0x1E85: +case 0x1086: +case 0x1286: +case 0x1486: +case 0x1686: +case 0x1886: +case 0x1A86: +case 0x1C86: +case 0x1E86: +case 0x1087: +case 0x1287: +case 0x1487: +case 0x1687: +case 0x1887: +case 0x1A87: +case 0x1C87: +case 0x1E87: + +// MOVEB +case 0x1080: +{ + u32 adr; + u32 res; + res = (u8)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7]; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(8) +case 0x12C0: +case 0x14C0: +case 0x16C0: +case 0x18C0: +case 0x1AC0: +case 0x1CC0: +case 0x10C1: +case 0x12C1: +case 0x14C1: +case 0x16C1: +case 0x18C1: +case 0x1AC1: +case 0x1CC1: +case 0x10C2: +case 0x12C2: +case 0x14C2: +case 0x16C2: +case 0x18C2: +case 0x1AC2: +case 0x1CC2: +case 0x10C3: +case 0x12C3: +case 0x14C3: +case 0x16C3: +case 0x18C3: +case 0x1AC3: +case 0x1CC3: +case 0x10C4: +case 0x12C4: +case 0x14C4: +case 0x16C4: +case 0x18C4: +case 0x1AC4: +case 0x1CC4: +case 0x10C5: +case 0x12C5: +case 0x14C5: +case 0x16C5: +case 0x18C5: +case 0x1AC5: +case 0x1CC5: +case 0x10C6: +case 0x12C6: +case 0x14C6: +case 0x16C6: +case 0x18C6: +case 0x1AC6: +case 0x1CC6: +case 0x10C7: +case 0x12C7: +case 0x14C7: +case 0x16C7: +case 0x18C7: +case 0x1AC7: +case 0x1CC7: + +// MOVEB +case 0x10C0: +{ + u32 adr; + u32 res; + res = (u8)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7]; + CPU->A[(Opcode >> 9) & 7] += 1; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(8) +case 0x1300: +case 0x1500: +case 0x1700: +case 0x1900: +case 0x1B00: +case 0x1D00: +case 0x1101: +case 0x1301: +case 0x1501: +case 0x1701: +case 0x1901: +case 0x1B01: +case 0x1D01: +case 0x1102: +case 0x1302: +case 0x1502: +case 0x1702: +case 0x1902: +case 0x1B02: +case 0x1D02: +case 0x1103: +case 0x1303: +case 0x1503: +case 0x1703: +case 0x1903: +case 0x1B03: +case 0x1D03: +case 0x1104: +case 0x1304: +case 0x1504: +case 0x1704: +case 0x1904: +case 0x1B04: +case 0x1D04: +case 0x1105: +case 0x1305: +case 0x1505: +case 0x1705: +case 0x1905: +case 0x1B05: +case 0x1D05: +case 0x1106: +case 0x1306: +case 0x1506: +case 0x1706: +case 0x1906: +case 0x1B06: +case 0x1D06: +case 0x1107: +case 0x1307: +case 0x1507: +case 0x1707: +case 0x1907: +case 0x1B07: +case 0x1D07: + +// MOVEB +case 0x1100: +{ + u32 adr; + u32 res; + res = (u8)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7] - 1; + CPU->A[(Opcode >> 9) & 7] = adr; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(8) +case 0x1340: +case 0x1540: +case 0x1740: +case 0x1940: +case 0x1B40: +case 0x1D40: +case 0x1F40: +case 0x1141: +case 0x1341: +case 0x1541: +case 0x1741: +case 0x1941: +case 0x1B41: +case 0x1D41: +case 0x1F41: +case 0x1142: +case 0x1342: +case 0x1542: +case 0x1742: +case 0x1942: +case 0x1B42: +case 0x1D42: +case 0x1F42: +case 0x1143: +case 0x1343: +case 0x1543: +case 0x1743: +case 0x1943: +case 0x1B43: +case 0x1D43: +case 0x1F43: +case 0x1144: +case 0x1344: +case 0x1544: +case 0x1744: +case 0x1944: +case 0x1B44: +case 0x1D44: +case 0x1F44: +case 0x1145: +case 0x1345: +case 0x1545: +case 0x1745: +case 0x1945: +case 0x1B45: +case 0x1D45: +case 0x1F45: +case 0x1146: +case 0x1346: +case 0x1546: +case 0x1746: +case 0x1946: +case 0x1B46: +case 0x1D46: +case 0x1F46: +case 0x1147: +case 0x1347: +case 0x1547: +case 0x1747: +case 0x1947: +case 0x1B47: +case 0x1D47: +case 0x1F47: + +// MOVEB +case 0x1140: +{ + u32 adr; + u32 res; + res = (u8)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0x1380: +case 0x1580: +case 0x1780: +case 0x1980: +case 0x1B80: +case 0x1D80: +case 0x1F80: +case 0x1181: +case 0x1381: +case 0x1581: +case 0x1781: +case 0x1981: +case 0x1B81: +case 0x1D81: +case 0x1F81: +case 0x1182: +case 0x1382: +case 0x1582: +case 0x1782: +case 0x1982: +case 0x1B82: +case 0x1D82: +case 0x1F82: +case 0x1183: +case 0x1383: +case 0x1583: +case 0x1783: +case 0x1983: +case 0x1B83: +case 0x1D83: +case 0x1F83: +case 0x1184: +case 0x1384: +case 0x1584: +case 0x1784: +case 0x1984: +case 0x1B84: +case 0x1D84: +case 0x1F84: +case 0x1185: +case 0x1385: +case 0x1585: +case 0x1785: +case 0x1985: +case 0x1B85: +case 0x1D85: +case 0x1F85: +case 0x1186: +case 0x1386: +case 0x1586: +case 0x1786: +case 0x1986: +case 0x1B86: +case 0x1D86: +case 0x1F86: +case 0x1187: +case 0x1387: +case 0x1587: +case 0x1787: +case 0x1987: +case 0x1B87: +case 0x1D87: +case 0x1F87: + +// MOVEB +case 0x1180: +{ + u32 adr; + u32 res; + res = (u8)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7]; + DECODE_EXT_WORD + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(14) +case 0x11C1: +case 0x11C2: +case 0x11C3: +case 0x11C4: +case 0x11C5: +case 0x11C6: +case 0x11C7: + +// MOVEB +case 0x11C0: +{ + u32 adr; + u32 res; + res = (u8)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0x13C1: +case 0x13C2: +case 0x13C3: +case 0x13C4: +case 0x13C5: +case 0x13C6: +case 0x13C7: + +// MOVEB +case 0x13C0: +{ + u32 adr; + u32 res; + res = (u8)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0x1EC1: +case 0x1EC2: +case 0x1EC3: +case 0x1EC4: +case 0x1EC5: +case 0x1EC6: +case 0x1EC7: + +// MOVEB +case 0x1EC0: +{ + u32 adr; + u32 res; + res = (u8)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(8) +case 0x1F01: +case 0x1F02: +case 0x1F03: +case 0x1F04: +case 0x1F05: +case 0x1F06: +case 0x1F07: + +// MOVEB +case 0x1F00: +{ + u32 adr; + u32 res; + res = (u8)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(8) +case 0x1208: +case 0x1408: +case 0x1608: +case 0x1808: +case 0x1A08: +case 0x1C08: +case 0x1E08: +case 0x1009: +case 0x1209: +case 0x1409: +case 0x1609: +case 0x1809: +case 0x1A09: +case 0x1C09: +case 0x1E09: +case 0x100A: +case 0x120A: +case 0x140A: +case 0x160A: +case 0x180A: +case 0x1A0A: +case 0x1C0A: +case 0x1E0A: +case 0x100B: +case 0x120B: +case 0x140B: +case 0x160B: +case 0x180B: +case 0x1A0B: +case 0x1C0B: +case 0x1E0B: +case 0x100C: +case 0x120C: +case 0x140C: +case 0x160C: +case 0x180C: +case 0x1A0C: +case 0x1C0C: +case 0x1E0C: +case 0x100D: +case 0x120D: +case 0x140D: +case 0x160D: +case 0x180D: +case 0x1A0D: +case 0x1C0D: +case 0x1E0D: +case 0x100E: +case 0x120E: +case 0x140E: +case 0x160E: +case 0x180E: +case 0x1A0E: +case 0x1C0E: +case 0x1E0E: +case 0x100F: +case 0x120F: +case 0x140F: +case 0x160F: +case 0x180F: +case 0x1A0F: +case 0x1C0F: +case 0x1E0F: + +// MOVEB +case 0x1008: +{ + u32 res; + // can't read byte from Ax registers ! + CPU->Status |= C68K_FAULTED; + CCnt = 0; + goto C68k_Exec_Really_End; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; +} +RET(4) +case 0x1288: +case 0x1488: +case 0x1688: +case 0x1888: +case 0x1A88: +case 0x1C88: +case 0x1E88: +case 0x1089: +case 0x1289: +case 0x1489: +case 0x1689: +case 0x1889: +case 0x1A89: +case 0x1C89: +case 0x1E89: +case 0x108A: +case 0x128A: +case 0x148A: +case 0x168A: +case 0x188A: +case 0x1A8A: +case 0x1C8A: +case 0x1E8A: +case 0x108B: +case 0x128B: +case 0x148B: +case 0x168B: +case 0x188B: +case 0x1A8B: +case 0x1C8B: +case 0x1E8B: +case 0x108C: +case 0x128C: +case 0x148C: +case 0x168C: +case 0x188C: +case 0x1A8C: +case 0x1C8C: +case 0x1E8C: +case 0x108D: +case 0x128D: +case 0x148D: +case 0x168D: +case 0x188D: +case 0x1A8D: +case 0x1C8D: +case 0x1E8D: +case 0x108E: +case 0x128E: +case 0x148E: +case 0x168E: +case 0x188E: +case 0x1A8E: +case 0x1C8E: +case 0x1E8E: +case 0x108F: +case 0x128F: +case 0x148F: +case 0x168F: +case 0x188F: +case 0x1A8F: +case 0x1C8F: +case 0x1E8F: + +// MOVEB +case 0x1088: +{ + u32 adr; + u32 res; + // can't read byte from Ax registers ! + CPU->Status |= C68K_FAULTED; + CCnt = 0; + goto C68k_Exec_Really_End; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7]; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(8) +case 0x12C8: +case 0x14C8: +case 0x16C8: +case 0x18C8: +case 0x1AC8: +case 0x1CC8: +case 0x10C9: +case 0x12C9: +case 0x14C9: +case 0x16C9: +case 0x18C9: +case 0x1AC9: +case 0x1CC9: +case 0x10CA: +case 0x12CA: +case 0x14CA: +case 0x16CA: +case 0x18CA: +case 0x1ACA: +case 0x1CCA: +case 0x10CB: +case 0x12CB: +case 0x14CB: +case 0x16CB: +case 0x18CB: +case 0x1ACB: +case 0x1CCB: +case 0x10CC: +case 0x12CC: +case 0x14CC: +case 0x16CC: +case 0x18CC: +case 0x1ACC: +case 0x1CCC: +case 0x10CD: +case 0x12CD: +case 0x14CD: +case 0x16CD: +case 0x18CD: +case 0x1ACD: +case 0x1CCD: +case 0x10CE: +case 0x12CE: +case 0x14CE: +case 0x16CE: +case 0x18CE: +case 0x1ACE: +case 0x1CCE: +case 0x10CF: +case 0x12CF: +case 0x14CF: +case 0x16CF: +case 0x18CF: +case 0x1ACF: +case 0x1CCF: + +// MOVEB +case 0x10C8: +{ + u32 adr; + u32 res; + // can't read byte from Ax registers ! + CPU->Status |= C68K_FAULTED; + CCnt = 0; + goto C68k_Exec_Really_End; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7]; + CPU->A[(Opcode >> 9) & 7] += 1; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(8) +case 0x1308: +case 0x1508: +case 0x1708: +case 0x1908: +case 0x1B08: +case 0x1D08: +case 0x1109: +case 0x1309: +case 0x1509: +case 0x1709: +case 0x1909: +case 0x1B09: +case 0x1D09: +case 0x110A: +case 0x130A: +case 0x150A: +case 0x170A: +case 0x190A: +case 0x1B0A: +case 0x1D0A: +case 0x110B: +case 0x130B: +case 0x150B: +case 0x170B: +case 0x190B: +case 0x1B0B: +case 0x1D0B: +case 0x110C: +case 0x130C: +case 0x150C: +case 0x170C: +case 0x190C: +case 0x1B0C: +case 0x1D0C: +case 0x110D: +case 0x130D: +case 0x150D: +case 0x170D: +case 0x190D: +case 0x1B0D: +case 0x1D0D: +case 0x110E: +case 0x130E: +case 0x150E: +case 0x170E: +case 0x190E: +case 0x1B0E: +case 0x1D0E: +case 0x110F: +case 0x130F: +case 0x150F: +case 0x170F: +case 0x190F: +case 0x1B0F: +case 0x1D0F: + +// MOVEB +case 0x1108: +{ + u32 adr; + u32 res; + // can't read byte from Ax registers ! + CPU->Status |= C68K_FAULTED; + CCnt = 0; + goto C68k_Exec_Really_End; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7] - 1; + CPU->A[(Opcode >> 9) & 7] = adr; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(8) +case 0x1348: +case 0x1548: +case 0x1748: +case 0x1948: +case 0x1B48: +case 0x1D48: +case 0x1F48: +case 0x1149: +case 0x1349: +case 0x1549: +case 0x1749: +case 0x1949: +case 0x1B49: +case 0x1D49: +case 0x1F49: +case 0x114A: +case 0x134A: +case 0x154A: +case 0x174A: +case 0x194A: +case 0x1B4A: +case 0x1D4A: +case 0x1F4A: +case 0x114B: +case 0x134B: +case 0x154B: +case 0x174B: +case 0x194B: +case 0x1B4B: +case 0x1D4B: +case 0x1F4B: +case 0x114C: +case 0x134C: +case 0x154C: +case 0x174C: +case 0x194C: +case 0x1B4C: +case 0x1D4C: +case 0x1F4C: +case 0x114D: +case 0x134D: +case 0x154D: +case 0x174D: +case 0x194D: +case 0x1B4D: +case 0x1D4D: +case 0x1F4D: +case 0x114E: +case 0x134E: +case 0x154E: +case 0x174E: +case 0x194E: +case 0x1B4E: +case 0x1D4E: +case 0x1F4E: +case 0x114F: +case 0x134F: +case 0x154F: +case 0x174F: +case 0x194F: +case 0x1B4F: +case 0x1D4F: +case 0x1F4F: + +// MOVEB +case 0x1148: +{ + u32 adr; + u32 res; + // can't read byte from Ax registers ! + CPU->Status |= C68K_FAULTED; + CCnt = 0; + goto C68k_Exec_Really_End; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0x1388: +case 0x1588: +case 0x1788: +case 0x1988: +case 0x1B88: +case 0x1D88: +case 0x1F88: +case 0x1189: +case 0x1389: +case 0x1589: +case 0x1789: +case 0x1989: +case 0x1B89: +case 0x1D89: +case 0x1F89: +case 0x118A: +case 0x138A: +case 0x158A: +case 0x178A: +case 0x198A: +case 0x1B8A: +case 0x1D8A: +case 0x1F8A: +case 0x118B: +case 0x138B: +case 0x158B: +case 0x178B: +case 0x198B: +case 0x1B8B: +case 0x1D8B: +case 0x1F8B: +case 0x118C: +case 0x138C: +case 0x158C: +case 0x178C: +case 0x198C: +case 0x1B8C: +case 0x1D8C: +case 0x1F8C: +case 0x118D: +case 0x138D: +case 0x158D: +case 0x178D: +case 0x198D: +case 0x1B8D: +case 0x1D8D: +case 0x1F8D: +case 0x118E: +case 0x138E: +case 0x158E: +case 0x178E: +case 0x198E: +case 0x1B8E: +case 0x1D8E: +case 0x1F8E: +case 0x118F: +case 0x138F: +case 0x158F: +case 0x178F: +case 0x198F: +case 0x1B8F: +case 0x1D8F: +case 0x1F8F: + +// MOVEB +case 0x1188: +{ + u32 adr; + u32 res; + // can't read byte from Ax registers ! + CPU->Status |= C68K_FAULTED; + CCnt = 0; + goto C68k_Exec_Really_End; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7]; + DECODE_EXT_WORD + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(14) +case 0x11C9: +case 0x11CA: +case 0x11CB: +case 0x11CC: +case 0x11CD: +case 0x11CE: +case 0x11CF: + +// MOVEB +case 0x11C8: +{ + u32 adr; + u32 res; + // can't read byte from Ax registers ! + CPU->Status |= C68K_FAULTED; + CCnt = 0; + goto C68k_Exec_Really_End; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0x13C9: +case 0x13CA: +case 0x13CB: +case 0x13CC: +case 0x13CD: +case 0x13CE: +case 0x13CF: + +// MOVEB +case 0x13C8: +{ + u32 adr; + u32 res; + // can't read byte from Ax registers ! + CPU->Status |= C68K_FAULTED; + CCnt = 0; + goto C68k_Exec_Really_End; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0x1EC9: +case 0x1ECA: +case 0x1ECB: +case 0x1ECC: +case 0x1ECD: +case 0x1ECE: +case 0x1ECF: + +// MOVEB +case 0x1EC8: +{ + u32 adr; + u32 res; + // can't read byte from Ax registers ! + CPU->Status |= C68K_FAULTED; + CCnt = 0; + goto C68k_Exec_Really_End; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(8) +case 0x1F09: +case 0x1F0A: +case 0x1F0B: +case 0x1F0C: +case 0x1F0D: +case 0x1F0E: +case 0x1F0F: + +// MOVEB +case 0x1F08: +{ + u32 adr; + u32 res; + // can't read byte from Ax registers ! + CPU->Status |= C68K_FAULTED; + CCnt = 0; + goto C68k_Exec_Really_End; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(8) +case 0x1210: +case 0x1410: +case 0x1610: +case 0x1810: +case 0x1A10: +case 0x1C10: +case 0x1E10: +case 0x1011: +case 0x1211: +case 0x1411: +case 0x1611: +case 0x1811: +case 0x1A11: +case 0x1C11: +case 0x1E11: +case 0x1012: +case 0x1212: +case 0x1412: +case 0x1612: +case 0x1812: +case 0x1A12: +case 0x1C12: +case 0x1E12: +case 0x1013: +case 0x1213: +case 0x1413: +case 0x1613: +case 0x1813: +case 0x1A13: +case 0x1C13: +case 0x1E13: +case 0x1014: +case 0x1214: +case 0x1414: +case 0x1614: +case 0x1814: +case 0x1A14: +case 0x1C14: +case 0x1E14: +case 0x1015: +case 0x1215: +case 0x1415: +case 0x1615: +case 0x1815: +case 0x1A15: +case 0x1C15: +case 0x1E15: +case 0x1016: +case 0x1216: +case 0x1416: +case 0x1616: +case 0x1816: +case 0x1A16: +case 0x1C16: +case 0x1E16: +case 0x1017: +case 0x1217: +case 0x1417: +case 0x1617: +case 0x1817: +case 0x1A17: +case 0x1C17: +case 0x1E17: + +// MOVEB +case 0x1010: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(8) +case 0x1290: +case 0x1490: +case 0x1690: +case 0x1890: +case 0x1A90: +case 0x1C90: +case 0x1E90: +case 0x1091: +case 0x1291: +case 0x1491: +case 0x1691: +case 0x1891: +case 0x1A91: +case 0x1C91: +case 0x1E91: +case 0x1092: +case 0x1292: +case 0x1492: +case 0x1692: +case 0x1892: +case 0x1A92: +case 0x1C92: +case 0x1E92: +case 0x1093: +case 0x1293: +case 0x1493: +case 0x1693: +case 0x1893: +case 0x1A93: +case 0x1C93: +case 0x1E93: +case 0x1094: +case 0x1294: +case 0x1494: +case 0x1694: +case 0x1894: +case 0x1A94: +case 0x1C94: +case 0x1E94: +case 0x1095: +case 0x1295: +case 0x1495: +case 0x1695: +case 0x1895: +case 0x1A95: +case 0x1C95: +case 0x1E95: +case 0x1096: +case 0x1296: +case 0x1496: +case 0x1696: +case 0x1896: +case 0x1A96: +case 0x1C96: +case 0x1E96: +case 0x1097: +case 0x1297: +case 0x1497: +case 0x1697: +case 0x1897: +case 0x1A97: +case 0x1C97: +case 0x1E97: + +// MOVEB +case 0x1090: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7]; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0x12D0: +case 0x14D0: +case 0x16D0: +case 0x18D0: +case 0x1AD0: +case 0x1CD0: +case 0x10D1: +case 0x12D1: +case 0x14D1: +case 0x16D1: +case 0x18D1: +case 0x1AD1: +case 0x1CD1: +case 0x10D2: +case 0x12D2: +case 0x14D2: +case 0x16D2: +case 0x18D2: +case 0x1AD2: +case 0x1CD2: +case 0x10D3: +case 0x12D3: +case 0x14D3: +case 0x16D3: +case 0x18D3: +case 0x1AD3: +case 0x1CD3: +case 0x10D4: +case 0x12D4: +case 0x14D4: +case 0x16D4: +case 0x18D4: +case 0x1AD4: +case 0x1CD4: +case 0x10D5: +case 0x12D5: +case 0x14D5: +case 0x16D5: +case 0x18D5: +case 0x1AD5: +case 0x1CD5: +case 0x10D6: +case 0x12D6: +case 0x14D6: +case 0x16D6: +case 0x18D6: +case 0x1AD6: +case 0x1CD6: +case 0x10D7: +case 0x12D7: +case 0x14D7: +case 0x16D7: +case 0x18D7: +case 0x1AD7: +case 0x1CD7: + +// MOVEB +case 0x10D0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7]; + CPU->A[(Opcode >> 9) & 7] += 1; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0x1310: +case 0x1510: +case 0x1710: +case 0x1910: +case 0x1B10: +case 0x1D10: +case 0x1111: +case 0x1311: +case 0x1511: +case 0x1711: +case 0x1911: +case 0x1B11: +case 0x1D11: +case 0x1112: +case 0x1312: +case 0x1512: +case 0x1712: +case 0x1912: +case 0x1B12: +case 0x1D12: +case 0x1113: +case 0x1313: +case 0x1513: +case 0x1713: +case 0x1913: +case 0x1B13: +case 0x1D13: +case 0x1114: +case 0x1314: +case 0x1514: +case 0x1714: +case 0x1914: +case 0x1B14: +case 0x1D14: +case 0x1115: +case 0x1315: +case 0x1515: +case 0x1715: +case 0x1915: +case 0x1B15: +case 0x1D15: +case 0x1116: +case 0x1316: +case 0x1516: +case 0x1716: +case 0x1916: +case 0x1B16: +case 0x1D16: +case 0x1117: +case 0x1317: +case 0x1517: +case 0x1717: +case 0x1917: +case 0x1B17: +case 0x1D17: + +// MOVEB +case 0x1110: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7] - 1; + CPU->A[(Opcode >> 9) & 7] = adr; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0x1350: +case 0x1550: +case 0x1750: +case 0x1950: +case 0x1B50: +case 0x1D50: +case 0x1F50: +case 0x1151: +case 0x1351: +case 0x1551: +case 0x1751: +case 0x1951: +case 0x1B51: +case 0x1D51: +case 0x1F51: +case 0x1152: +case 0x1352: +case 0x1552: +case 0x1752: +case 0x1952: +case 0x1B52: +case 0x1D52: +case 0x1F52: +case 0x1153: +case 0x1353: +case 0x1553: +case 0x1753: +case 0x1953: +case 0x1B53: +case 0x1D53: +case 0x1F53: +case 0x1154: +case 0x1354: +case 0x1554: +case 0x1754: +case 0x1954: +case 0x1B54: +case 0x1D54: +case 0x1F54: +case 0x1155: +case 0x1355: +case 0x1555: +case 0x1755: +case 0x1955: +case 0x1B55: +case 0x1D55: +case 0x1F55: +case 0x1156: +case 0x1356: +case 0x1556: +case 0x1756: +case 0x1956: +case 0x1B56: +case 0x1D56: +case 0x1F56: +case 0x1157: +case 0x1357: +case 0x1557: +case 0x1757: +case 0x1957: +case 0x1B57: +case 0x1D57: +case 0x1F57: + +// MOVEB +case 0x1150: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0x1390: +case 0x1590: +case 0x1790: +case 0x1990: +case 0x1B90: +case 0x1D90: +case 0x1F90: +case 0x1191: +case 0x1391: +case 0x1591: +case 0x1791: +case 0x1991: +case 0x1B91: +case 0x1D91: +case 0x1F91: +case 0x1192: +case 0x1392: +case 0x1592: +case 0x1792: +case 0x1992: +case 0x1B92: +case 0x1D92: +case 0x1F92: +case 0x1193: +case 0x1393: +case 0x1593: +case 0x1793: +case 0x1993: +case 0x1B93: +case 0x1D93: +case 0x1F93: +case 0x1194: +case 0x1394: +case 0x1594: +case 0x1794: +case 0x1994: +case 0x1B94: +case 0x1D94: +case 0x1F94: +case 0x1195: +case 0x1395: +case 0x1595: +case 0x1795: +case 0x1995: +case 0x1B95: +case 0x1D95: +case 0x1F95: +case 0x1196: +case 0x1396: +case 0x1596: +case 0x1796: +case 0x1996: +case 0x1B96: +case 0x1D96: +case 0x1F96: +case 0x1197: +case 0x1397: +case 0x1597: +case 0x1797: +case 0x1997: +case 0x1B97: +case 0x1D97: +case 0x1F97: + +// MOVEB +case 0x1190: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7]; + DECODE_EXT_WORD + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) +case 0x11D1: +case 0x11D2: +case 0x11D3: +case 0x11D4: +case 0x11D5: +case 0x11D6: +case 0x11D7: + +// MOVEB +case 0x11D0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0x13D1: +case 0x13D2: +case 0x13D3: +case 0x13D4: +case 0x13D5: +case 0x13D6: +case 0x13D7: + +// MOVEB +case 0x13D0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = (s32)FETCH_LONG; + PC += 4; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(20) +case 0x1ED1: +case 0x1ED2: +case 0x1ED3: +case 0x1ED4: +case 0x1ED5: +case 0x1ED6: +case 0x1ED7: + +// MOVEB +case 0x1ED0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[7]; + CPU->A[7] += 2; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0x1F11: +case 0x1F12: +case 0x1F13: +case 0x1F14: +case 0x1F15: +case 0x1F16: +case 0x1F17: + +// MOVEB +case 0x1F10: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0x1218: +case 0x1418: +case 0x1618: +case 0x1818: +case 0x1A18: +case 0x1C18: +case 0x1E18: +case 0x1019: +case 0x1219: +case 0x1419: +case 0x1619: +case 0x1819: +case 0x1A19: +case 0x1C19: +case 0x1E19: +case 0x101A: +case 0x121A: +case 0x141A: +case 0x161A: +case 0x181A: +case 0x1A1A: +case 0x1C1A: +case 0x1E1A: +case 0x101B: +case 0x121B: +case 0x141B: +case 0x161B: +case 0x181B: +case 0x1A1B: +case 0x1C1B: +case 0x1E1B: +case 0x101C: +case 0x121C: +case 0x141C: +case 0x161C: +case 0x181C: +case 0x1A1C: +case 0x1C1C: +case 0x1E1C: +case 0x101D: +case 0x121D: +case 0x141D: +case 0x161D: +case 0x181D: +case 0x1A1D: +case 0x1C1D: +case 0x1E1D: +case 0x101E: +case 0x121E: +case 0x141E: +case 0x161E: +case 0x181E: +case 0x1A1E: +case 0x1C1E: +case 0x1E1E: + +// MOVEB +case 0x1018: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(8) +case 0x1298: +case 0x1498: +case 0x1698: +case 0x1898: +case 0x1A98: +case 0x1C98: +case 0x1E98: +case 0x1099: +case 0x1299: +case 0x1499: +case 0x1699: +case 0x1899: +case 0x1A99: +case 0x1C99: +case 0x1E99: +case 0x109A: +case 0x129A: +case 0x149A: +case 0x169A: +case 0x189A: +case 0x1A9A: +case 0x1C9A: +case 0x1E9A: +case 0x109B: +case 0x129B: +case 0x149B: +case 0x169B: +case 0x189B: +case 0x1A9B: +case 0x1C9B: +case 0x1E9B: +case 0x109C: +case 0x129C: +case 0x149C: +case 0x169C: +case 0x189C: +case 0x1A9C: +case 0x1C9C: +case 0x1E9C: +case 0x109D: +case 0x129D: +case 0x149D: +case 0x169D: +case 0x189D: +case 0x1A9D: +case 0x1C9D: +case 0x1E9D: +case 0x109E: +case 0x129E: +case 0x149E: +case 0x169E: +case 0x189E: +case 0x1A9E: +case 0x1C9E: +case 0x1E9E: + +// MOVEB +case 0x1098: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7]; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0x12D8: +case 0x14D8: +case 0x16D8: +case 0x18D8: +case 0x1AD8: +case 0x1CD8: +case 0x10D9: +case 0x12D9: +case 0x14D9: +case 0x16D9: +case 0x18D9: +case 0x1AD9: +case 0x1CD9: +case 0x10DA: +case 0x12DA: +case 0x14DA: +case 0x16DA: +case 0x18DA: +case 0x1ADA: +case 0x1CDA: +case 0x10DB: +case 0x12DB: +case 0x14DB: +case 0x16DB: +case 0x18DB: +case 0x1ADB: +case 0x1CDB: +case 0x10DC: +case 0x12DC: +case 0x14DC: +case 0x16DC: +case 0x18DC: +case 0x1ADC: +case 0x1CDC: +case 0x10DD: +case 0x12DD: +case 0x14DD: +case 0x16DD: +case 0x18DD: +case 0x1ADD: +case 0x1CDD: +case 0x10DE: +case 0x12DE: +case 0x14DE: +case 0x16DE: +case 0x18DE: +case 0x1ADE: +case 0x1CDE: + +// MOVEB +case 0x10D8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7]; + CPU->A[(Opcode >> 9) & 7] += 1; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0x1318: +case 0x1518: +case 0x1718: +case 0x1918: +case 0x1B18: +case 0x1D18: +case 0x1119: +case 0x1319: +case 0x1519: +case 0x1719: +case 0x1919: +case 0x1B19: +case 0x1D19: +case 0x111A: +case 0x131A: +case 0x151A: +case 0x171A: +case 0x191A: +case 0x1B1A: +case 0x1D1A: +case 0x111B: +case 0x131B: +case 0x151B: +case 0x171B: +case 0x191B: +case 0x1B1B: +case 0x1D1B: +case 0x111C: +case 0x131C: +case 0x151C: +case 0x171C: +case 0x191C: +case 0x1B1C: +case 0x1D1C: +case 0x111D: +case 0x131D: +case 0x151D: +case 0x171D: +case 0x191D: +case 0x1B1D: +case 0x1D1D: +case 0x111E: +case 0x131E: +case 0x151E: +case 0x171E: +case 0x191E: +case 0x1B1E: +case 0x1D1E: + +// MOVEB +case 0x1118: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7] - 1; + CPU->A[(Opcode >> 9) & 7] = adr; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0x1358: +case 0x1558: +case 0x1758: +case 0x1958: +case 0x1B58: +case 0x1D58: +case 0x1F58: +case 0x1159: +case 0x1359: +case 0x1559: +case 0x1759: +case 0x1959: +case 0x1B59: +case 0x1D59: +case 0x1F59: +case 0x115A: +case 0x135A: +case 0x155A: +case 0x175A: +case 0x195A: +case 0x1B5A: +case 0x1D5A: +case 0x1F5A: +case 0x115B: +case 0x135B: +case 0x155B: +case 0x175B: +case 0x195B: +case 0x1B5B: +case 0x1D5B: +case 0x1F5B: +case 0x115C: +case 0x135C: +case 0x155C: +case 0x175C: +case 0x195C: +case 0x1B5C: +case 0x1D5C: +case 0x1F5C: +case 0x115D: +case 0x135D: +case 0x155D: +case 0x175D: +case 0x195D: +case 0x1B5D: +case 0x1D5D: +case 0x1F5D: +case 0x115E: +case 0x135E: +case 0x155E: +case 0x175E: +case 0x195E: +case 0x1B5E: +case 0x1D5E: +case 0x1F5E: + +// MOVEB +case 0x1158: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0x1398: +case 0x1598: +case 0x1798: +case 0x1998: +case 0x1B98: +case 0x1D98: +case 0x1F98: +case 0x1199: +case 0x1399: +case 0x1599: +case 0x1799: +case 0x1999: +case 0x1B99: +case 0x1D99: +case 0x1F99: +case 0x119A: +case 0x139A: +case 0x159A: +case 0x179A: +case 0x199A: +case 0x1B9A: +case 0x1D9A: +case 0x1F9A: +case 0x119B: +case 0x139B: +case 0x159B: +case 0x179B: +case 0x199B: +case 0x1B9B: +case 0x1D9B: +case 0x1F9B: +case 0x119C: +case 0x139C: +case 0x159C: +case 0x179C: +case 0x199C: +case 0x1B9C: +case 0x1D9C: +case 0x1F9C: +case 0x119D: +case 0x139D: +case 0x159D: +case 0x179D: +case 0x199D: +case 0x1B9D: +case 0x1D9D: +case 0x1F9D: +case 0x119E: +case 0x139E: +case 0x159E: +case 0x179E: +case 0x199E: +case 0x1B9E: +case 0x1D9E: +case 0x1F9E: + +// MOVEB +case 0x1198: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7]; + DECODE_EXT_WORD + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) +case 0x11D9: +case 0x11DA: +case 0x11DB: +case 0x11DC: +case 0x11DD: +case 0x11DE: + +// MOVEB +case 0x11D8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0x13D9: +case 0x13DA: +case 0x13DB: +case 0x13DC: +case 0x13DD: +case 0x13DE: + +// MOVEB +case 0x13D8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = (s32)FETCH_LONG; + PC += 4; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(20) +case 0x1ED9: +case 0x1EDA: +case 0x1EDB: +case 0x1EDC: +case 0x1EDD: +case 0x1EDE: + +// MOVEB +case 0x1ED8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[7]; + CPU->A[7] += 2; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0x1F19: +case 0x1F1A: +case 0x1F1B: +case 0x1F1C: +case 0x1F1D: +case 0x1F1E: + +// MOVEB +case 0x1F18: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0x1220: +case 0x1420: +case 0x1620: +case 0x1820: +case 0x1A20: +case 0x1C20: +case 0x1E20: +case 0x1021: +case 0x1221: +case 0x1421: +case 0x1621: +case 0x1821: +case 0x1A21: +case 0x1C21: +case 0x1E21: +case 0x1022: +case 0x1222: +case 0x1422: +case 0x1622: +case 0x1822: +case 0x1A22: +case 0x1C22: +case 0x1E22: +case 0x1023: +case 0x1223: +case 0x1423: +case 0x1623: +case 0x1823: +case 0x1A23: +case 0x1C23: +case 0x1E23: +case 0x1024: +case 0x1224: +case 0x1424: +case 0x1624: +case 0x1824: +case 0x1A24: +case 0x1C24: +case 0x1E24: +case 0x1025: +case 0x1225: +case 0x1425: +case 0x1625: +case 0x1825: +case 0x1A25: +case 0x1C25: +case 0x1E25: +case 0x1026: +case 0x1226: +case 0x1426: +case 0x1626: +case 0x1826: +case 0x1A26: +case 0x1C26: +case 0x1E26: + +// MOVEB +case 0x1020: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(10) +case 0x12A0: +case 0x14A0: +case 0x16A0: +case 0x18A0: +case 0x1AA0: +case 0x1CA0: +case 0x1EA0: +case 0x10A1: +case 0x12A1: +case 0x14A1: +case 0x16A1: +case 0x18A1: +case 0x1AA1: +case 0x1CA1: +case 0x1EA1: +case 0x10A2: +case 0x12A2: +case 0x14A2: +case 0x16A2: +case 0x18A2: +case 0x1AA2: +case 0x1CA2: +case 0x1EA2: +case 0x10A3: +case 0x12A3: +case 0x14A3: +case 0x16A3: +case 0x18A3: +case 0x1AA3: +case 0x1CA3: +case 0x1EA3: +case 0x10A4: +case 0x12A4: +case 0x14A4: +case 0x16A4: +case 0x18A4: +case 0x1AA4: +case 0x1CA4: +case 0x1EA4: +case 0x10A5: +case 0x12A5: +case 0x14A5: +case 0x16A5: +case 0x18A5: +case 0x1AA5: +case 0x1CA5: +case 0x1EA5: +case 0x10A6: +case 0x12A6: +case 0x14A6: +case 0x16A6: +case 0x18A6: +case 0x1AA6: +case 0x1CA6: +case 0x1EA6: + +// MOVEB +case 0x10A0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7]; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(14) +case 0x12E0: +case 0x14E0: +case 0x16E0: +case 0x18E0: +case 0x1AE0: +case 0x1CE0: +case 0x10E1: +case 0x12E1: +case 0x14E1: +case 0x16E1: +case 0x18E1: +case 0x1AE1: +case 0x1CE1: +case 0x10E2: +case 0x12E2: +case 0x14E2: +case 0x16E2: +case 0x18E2: +case 0x1AE2: +case 0x1CE2: +case 0x10E3: +case 0x12E3: +case 0x14E3: +case 0x16E3: +case 0x18E3: +case 0x1AE3: +case 0x1CE3: +case 0x10E4: +case 0x12E4: +case 0x14E4: +case 0x16E4: +case 0x18E4: +case 0x1AE4: +case 0x1CE4: +case 0x10E5: +case 0x12E5: +case 0x14E5: +case 0x16E5: +case 0x18E5: +case 0x1AE5: +case 0x1CE5: +case 0x10E6: +case 0x12E6: +case 0x14E6: +case 0x16E6: +case 0x18E6: +case 0x1AE6: +case 0x1CE6: + +// MOVEB +case 0x10E0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7]; + CPU->A[(Opcode >> 9) & 7] += 1; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(14) +case 0x1320: +case 0x1520: +case 0x1720: +case 0x1920: +case 0x1B20: +case 0x1D20: +case 0x1121: +case 0x1321: +case 0x1521: +case 0x1721: +case 0x1921: +case 0x1B21: +case 0x1D21: +case 0x1122: +case 0x1322: +case 0x1522: +case 0x1722: +case 0x1922: +case 0x1B22: +case 0x1D22: +case 0x1123: +case 0x1323: +case 0x1523: +case 0x1723: +case 0x1923: +case 0x1B23: +case 0x1D23: +case 0x1124: +case 0x1324: +case 0x1524: +case 0x1724: +case 0x1924: +case 0x1B24: +case 0x1D24: +case 0x1125: +case 0x1325: +case 0x1525: +case 0x1725: +case 0x1925: +case 0x1B25: +case 0x1D25: +case 0x1126: +case 0x1326: +case 0x1526: +case 0x1726: +case 0x1926: +case 0x1B26: +case 0x1D26: + +// MOVEB +case 0x1120: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7] - 1; + CPU->A[(Opcode >> 9) & 7] = adr; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(14) +case 0x1360: +case 0x1560: +case 0x1760: +case 0x1960: +case 0x1B60: +case 0x1D60: +case 0x1F60: +case 0x1161: +case 0x1361: +case 0x1561: +case 0x1761: +case 0x1961: +case 0x1B61: +case 0x1D61: +case 0x1F61: +case 0x1162: +case 0x1362: +case 0x1562: +case 0x1762: +case 0x1962: +case 0x1B62: +case 0x1D62: +case 0x1F62: +case 0x1163: +case 0x1363: +case 0x1563: +case 0x1763: +case 0x1963: +case 0x1B63: +case 0x1D63: +case 0x1F63: +case 0x1164: +case 0x1364: +case 0x1564: +case 0x1764: +case 0x1964: +case 0x1B64: +case 0x1D64: +case 0x1F64: +case 0x1165: +case 0x1365: +case 0x1565: +case 0x1765: +case 0x1965: +case 0x1B65: +case 0x1D65: +case 0x1F65: +case 0x1166: +case 0x1366: +case 0x1566: +case 0x1766: +case 0x1966: +case 0x1B66: +case 0x1D66: +case 0x1F66: + +// MOVEB +case 0x1160: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) +case 0x13A0: +case 0x15A0: +case 0x17A0: +case 0x19A0: +case 0x1BA0: +case 0x1DA0: +case 0x1FA0: +case 0x11A1: +case 0x13A1: +case 0x15A1: +case 0x17A1: +case 0x19A1: +case 0x1BA1: +case 0x1DA1: +case 0x1FA1: +case 0x11A2: +case 0x13A2: +case 0x15A2: +case 0x17A2: +case 0x19A2: +case 0x1BA2: +case 0x1DA2: +case 0x1FA2: +case 0x11A3: +case 0x13A3: +case 0x15A3: +case 0x17A3: +case 0x19A3: +case 0x1BA3: +case 0x1DA3: +case 0x1FA3: +case 0x11A4: +case 0x13A4: +case 0x15A4: +case 0x17A4: +case 0x19A4: +case 0x1BA4: +case 0x1DA4: +case 0x1FA4: +case 0x11A5: +case 0x13A5: +case 0x15A5: +case 0x17A5: +case 0x19A5: +case 0x1BA5: +case 0x1DA5: +case 0x1FA5: +case 0x11A6: +case 0x13A6: +case 0x15A6: +case 0x17A6: +case 0x19A6: +case 0x1BA6: +case 0x1DA6: +case 0x1FA6: + +// MOVEB +case 0x11A0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7]; + DECODE_EXT_WORD + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(20) +case 0x11E1: +case 0x11E2: +case 0x11E3: +case 0x11E4: +case 0x11E5: +case 0x11E6: + +// MOVEB +case 0x11E0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) +case 0x13E1: +case 0x13E2: +case 0x13E3: +case 0x13E4: +case 0x13E5: +case 0x13E6: + +// MOVEB +case 0x13E0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = (s32)FETCH_LONG; + PC += 4; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(22) +case 0x1EE1: +case 0x1EE2: +case 0x1EE3: +case 0x1EE4: +case 0x1EE5: +case 0x1EE6: + +// MOVEB +case 0x1EE0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[7]; + CPU->A[7] += 2; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(14) +case 0x1F21: +case 0x1F22: +case 0x1F23: +case 0x1F24: +case 0x1F25: +case 0x1F26: + +// MOVEB +case 0x1F20: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(14) +case 0x1228: +case 0x1428: +case 0x1628: +case 0x1828: +case 0x1A28: +case 0x1C28: +case 0x1E28: +case 0x1029: +case 0x1229: +case 0x1429: +case 0x1629: +case 0x1829: +case 0x1A29: +case 0x1C29: +case 0x1E29: +case 0x102A: +case 0x122A: +case 0x142A: +case 0x162A: +case 0x182A: +case 0x1A2A: +case 0x1C2A: +case 0x1E2A: +case 0x102B: +case 0x122B: +case 0x142B: +case 0x162B: +case 0x182B: +case 0x1A2B: +case 0x1C2B: +case 0x1E2B: +case 0x102C: +case 0x122C: +case 0x142C: +case 0x162C: +case 0x182C: +case 0x1A2C: +case 0x1C2C: +case 0x1E2C: +case 0x102D: +case 0x122D: +case 0x142D: +case 0x162D: +case 0x182D: +case 0x1A2D: +case 0x1C2D: +case 0x1E2D: +case 0x102E: +case 0x122E: +case 0x142E: +case 0x162E: +case 0x182E: +case 0x1A2E: +case 0x1C2E: +case 0x1E2E: +case 0x102F: +case 0x122F: +case 0x142F: +case 0x162F: +case 0x182F: +case 0x1A2F: +case 0x1C2F: +case 0x1E2F: + +// MOVEB +case 0x1028: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(12) +case 0x12A8: +case 0x14A8: +case 0x16A8: +case 0x18A8: +case 0x1AA8: +case 0x1CA8: +case 0x1EA8: +case 0x10A9: +case 0x12A9: +case 0x14A9: +case 0x16A9: +case 0x18A9: +case 0x1AA9: +case 0x1CA9: +case 0x1EA9: +case 0x10AA: +case 0x12AA: +case 0x14AA: +case 0x16AA: +case 0x18AA: +case 0x1AAA: +case 0x1CAA: +case 0x1EAA: +case 0x10AB: +case 0x12AB: +case 0x14AB: +case 0x16AB: +case 0x18AB: +case 0x1AAB: +case 0x1CAB: +case 0x1EAB: +case 0x10AC: +case 0x12AC: +case 0x14AC: +case 0x16AC: +case 0x18AC: +case 0x1AAC: +case 0x1CAC: +case 0x1EAC: +case 0x10AD: +case 0x12AD: +case 0x14AD: +case 0x16AD: +case 0x18AD: +case 0x1AAD: +case 0x1CAD: +case 0x1EAD: +case 0x10AE: +case 0x12AE: +case 0x14AE: +case 0x16AE: +case 0x18AE: +case 0x1AAE: +case 0x1CAE: +case 0x1EAE: +case 0x10AF: +case 0x12AF: +case 0x14AF: +case 0x16AF: +case 0x18AF: +case 0x1AAF: +case 0x1CAF: +case 0x1EAF: + +// MOVEB +case 0x10A8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7]; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0x12E8: +case 0x14E8: +case 0x16E8: +case 0x18E8: +case 0x1AE8: +case 0x1CE8: +case 0x10E9: +case 0x12E9: +case 0x14E9: +case 0x16E9: +case 0x18E9: +case 0x1AE9: +case 0x1CE9: +case 0x10EA: +case 0x12EA: +case 0x14EA: +case 0x16EA: +case 0x18EA: +case 0x1AEA: +case 0x1CEA: +case 0x10EB: +case 0x12EB: +case 0x14EB: +case 0x16EB: +case 0x18EB: +case 0x1AEB: +case 0x1CEB: +case 0x10EC: +case 0x12EC: +case 0x14EC: +case 0x16EC: +case 0x18EC: +case 0x1AEC: +case 0x1CEC: +case 0x10ED: +case 0x12ED: +case 0x14ED: +case 0x16ED: +case 0x18ED: +case 0x1AED: +case 0x1CED: +case 0x10EE: +case 0x12EE: +case 0x14EE: +case 0x16EE: +case 0x18EE: +case 0x1AEE: +case 0x1CEE: +case 0x10EF: +case 0x12EF: +case 0x14EF: +case 0x16EF: +case 0x18EF: +case 0x1AEF: +case 0x1CEF: + +// MOVEB +case 0x10E8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7]; + CPU->A[(Opcode >> 9) & 7] += 1; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0x1328: +case 0x1528: +case 0x1728: +case 0x1928: +case 0x1B28: +case 0x1D28: +case 0x1129: +case 0x1329: +case 0x1529: +case 0x1729: +case 0x1929: +case 0x1B29: +case 0x1D29: +case 0x112A: +case 0x132A: +case 0x152A: +case 0x172A: +case 0x192A: +case 0x1B2A: +case 0x1D2A: +case 0x112B: +case 0x132B: +case 0x152B: +case 0x172B: +case 0x192B: +case 0x1B2B: +case 0x1D2B: +case 0x112C: +case 0x132C: +case 0x152C: +case 0x172C: +case 0x192C: +case 0x1B2C: +case 0x1D2C: +case 0x112D: +case 0x132D: +case 0x152D: +case 0x172D: +case 0x192D: +case 0x1B2D: +case 0x1D2D: +case 0x112E: +case 0x132E: +case 0x152E: +case 0x172E: +case 0x192E: +case 0x1B2E: +case 0x1D2E: +case 0x112F: +case 0x132F: +case 0x152F: +case 0x172F: +case 0x192F: +case 0x1B2F: +case 0x1D2F: + +// MOVEB +case 0x1128: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7] - 1; + CPU->A[(Opcode >> 9) & 7] = adr; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0x1368: +case 0x1568: +case 0x1768: +case 0x1968: +case 0x1B68: +case 0x1D68: +case 0x1F68: +case 0x1169: +case 0x1369: +case 0x1569: +case 0x1769: +case 0x1969: +case 0x1B69: +case 0x1D69: +case 0x1F69: +case 0x116A: +case 0x136A: +case 0x156A: +case 0x176A: +case 0x196A: +case 0x1B6A: +case 0x1D6A: +case 0x1F6A: +case 0x116B: +case 0x136B: +case 0x156B: +case 0x176B: +case 0x196B: +case 0x1B6B: +case 0x1D6B: +case 0x1F6B: +case 0x116C: +case 0x136C: +case 0x156C: +case 0x176C: +case 0x196C: +case 0x1B6C: +case 0x1D6C: +case 0x1F6C: +case 0x116D: +case 0x136D: +case 0x156D: +case 0x176D: +case 0x196D: +case 0x1B6D: +case 0x1D6D: +case 0x1F6D: +case 0x116E: +case 0x136E: +case 0x156E: +case 0x176E: +case 0x196E: +case 0x1B6E: +case 0x1D6E: +case 0x1F6E: +case 0x116F: +case 0x136F: +case 0x156F: +case 0x176F: +case 0x196F: +case 0x1B6F: +case 0x1D6F: +case 0x1F6F: + +// MOVEB +case 0x1168: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(20) +case 0x13A8: +case 0x15A8: +case 0x17A8: +case 0x19A8: +case 0x1BA8: +case 0x1DA8: +case 0x1FA8: +case 0x11A9: +case 0x13A9: +case 0x15A9: +case 0x17A9: +case 0x19A9: +case 0x1BA9: +case 0x1DA9: +case 0x1FA9: +case 0x11AA: +case 0x13AA: +case 0x15AA: +case 0x17AA: +case 0x19AA: +case 0x1BAA: +case 0x1DAA: +case 0x1FAA: +case 0x11AB: +case 0x13AB: +case 0x15AB: +case 0x17AB: +case 0x19AB: +case 0x1BAB: +case 0x1DAB: +case 0x1FAB: +case 0x11AC: +case 0x13AC: +case 0x15AC: +case 0x17AC: +case 0x19AC: +case 0x1BAC: +case 0x1DAC: +case 0x1FAC: +case 0x11AD: +case 0x13AD: +case 0x15AD: +case 0x17AD: +case 0x19AD: +case 0x1BAD: +case 0x1DAD: +case 0x1FAD: +case 0x11AE: +case 0x13AE: +case 0x15AE: +case 0x17AE: +case 0x19AE: +case 0x1BAE: +case 0x1DAE: +case 0x1FAE: +case 0x11AF: +case 0x13AF: +case 0x15AF: +case 0x17AF: +case 0x19AF: +case 0x1BAF: +case 0x1DAF: +case 0x1FAF: + +// MOVEB +case 0x11A8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7]; + DECODE_EXT_WORD + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(22) +case 0x11E9: +case 0x11EA: +case 0x11EB: +case 0x11EC: +case 0x11ED: +case 0x11EE: +case 0x11EF: + +// MOVEB +case 0x11E8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(20) +case 0x13E9: +case 0x13EA: +case 0x13EB: +case 0x13EC: +case 0x13ED: +case 0x13EE: +case 0x13EF: + +// MOVEB +case 0x13E8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = (s32)FETCH_LONG; + PC += 4; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(24) +case 0x1EE9: +case 0x1EEA: +case 0x1EEB: +case 0x1EEC: +case 0x1EED: +case 0x1EEE: +case 0x1EEF: + +// MOVEB +case 0x1EE8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[7]; + CPU->A[7] += 2; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0x1F29: +case 0x1F2A: +case 0x1F2B: +case 0x1F2C: +case 0x1F2D: +case 0x1F2E: +case 0x1F2F: + +// MOVEB +case 0x1F28: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0x1230: +case 0x1430: +case 0x1630: +case 0x1830: +case 0x1A30: +case 0x1C30: +case 0x1E30: +case 0x1031: +case 0x1231: +case 0x1431: +case 0x1631: +case 0x1831: +case 0x1A31: +case 0x1C31: +case 0x1E31: +case 0x1032: +case 0x1232: +case 0x1432: +case 0x1632: +case 0x1832: +case 0x1A32: +case 0x1C32: +case 0x1E32: +case 0x1033: +case 0x1233: +case 0x1433: +case 0x1633: +case 0x1833: +case 0x1A33: +case 0x1C33: +case 0x1E33: +case 0x1034: +case 0x1234: +case 0x1434: +case 0x1634: +case 0x1834: +case 0x1A34: +case 0x1C34: +case 0x1E34: +case 0x1035: +case 0x1235: +case 0x1435: +case 0x1635: +case 0x1835: +case 0x1A35: +case 0x1C35: +case 0x1E35: +case 0x1036: +case 0x1236: +case 0x1436: +case 0x1636: +case 0x1836: +case 0x1A36: +case 0x1C36: +case 0x1E36: +case 0x1037: +case 0x1237: +case 0x1437: +case 0x1637: +case 0x1837: +case 0x1A37: +case 0x1C37: +case 0x1E37: + +// MOVEB +case 0x1030: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(14) +case 0x12B0: +case 0x14B0: +case 0x16B0: +case 0x18B0: +case 0x1AB0: +case 0x1CB0: +case 0x1EB0: +case 0x10B1: +case 0x12B1: +case 0x14B1: +case 0x16B1: +case 0x18B1: +case 0x1AB1: +case 0x1CB1: +case 0x1EB1: +case 0x10B2: +case 0x12B2: +case 0x14B2: +case 0x16B2: +case 0x18B2: +case 0x1AB2: +case 0x1CB2: +case 0x1EB2: +case 0x10B3: +case 0x12B3: +case 0x14B3: +case 0x16B3: +case 0x18B3: +case 0x1AB3: +case 0x1CB3: +case 0x1EB3: +case 0x10B4: +case 0x12B4: +case 0x14B4: +case 0x16B4: +case 0x18B4: +case 0x1AB4: +case 0x1CB4: +case 0x1EB4: +case 0x10B5: +case 0x12B5: +case 0x14B5: +case 0x16B5: +case 0x18B5: +case 0x1AB5: +case 0x1CB5: +case 0x1EB5: +case 0x10B6: +case 0x12B6: +case 0x14B6: +case 0x16B6: +case 0x18B6: +case 0x1AB6: +case 0x1CB6: +case 0x1EB6: +case 0x10B7: +case 0x12B7: +case 0x14B7: +case 0x16B7: +case 0x18B7: +case 0x1AB7: +case 0x1CB7: +case 0x1EB7: + +// MOVEB +case 0x10B0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7]; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) +case 0x12F0: +case 0x14F0: +case 0x16F0: +case 0x18F0: +case 0x1AF0: +case 0x1CF0: +case 0x10F1: +case 0x12F1: +case 0x14F1: +case 0x16F1: +case 0x18F1: +case 0x1AF1: +case 0x1CF1: +case 0x10F2: +case 0x12F2: +case 0x14F2: +case 0x16F2: +case 0x18F2: +case 0x1AF2: +case 0x1CF2: +case 0x10F3: +case 0x12F3: +case 0x14F3: +case 0x16F3: +case 0x18F3: +case 0x1AF3: +case 0x1CF3: +case 0x10F4: +case 0x12F4: +case 0x14F4: +case 0x16F4: +case 0x18F4: +case 0x1AF4: +case 0x1CF4: +case 0x10F5: +case 0x12F5: +case 0x14F5: +case 0x16F5: +case 0x18F5: +case 0x1AF5: +case 0x1CF5: +case 0x10F6: +case 0x12F6: +case 0x14F6: +case 0x16F6: +case 0x18F6: +case 0x1AF6: +case 0x1CF6: +case 0x10F7: +case 0x12F7: +case 0x14F7: +case 0x16F7: +case 0x18F7: +case 0x1AF7: +case 0x1CF7: + +// MOVEB +case 0x10F0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7]; + CPU->A[(Opcode >> 9) & 7] += 1; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) +case 0x1330: +case 0x1530: +case 0x1730: +case 0x1930: +case 0x1B30: +case 0x1D30: +case 0x1131: +case 0x1331: +case 0x1531: +case 0x1731: +case 0x1931: +case 0x1B31: +case 0x1D31: +case 0x1132: +case 0x1332: +case 0x1532: +case 0x1732: +case 0x1932: +case 0x1B32: +case 0x1D32: +case 0x1133: +case 0x1333: +case 0x1533: +case 0x1733: +case 0x1933: +case 0x1B33: +case 0x1D33: +case 0x1134: +case 0x1334: +case 0x1534: +case 0x1734: +case 0x1934: +case 0x1B34: +case 0x1D34: +case 0x1135: +case 0x1335: +case 0x1535: +case 0x1735: +case 0x1935: +case 0x1B35: +case 0x1D35: +case 0x1136: +case 0x1336: +case 0x1536: +case 0x1736: +case 0x1936: +case 0x1B36: +case 0x1D36: +case 0x1137: +case 0x1337: +case 0x1537: +case 0x1737: +case 0x1937: +case 0x1B37: +case 0x1D37: + +// MOVEB +case 0x1130: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7] - 1; + CPU->A[(Opcode >> 9) & 7] = adr; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) +case 0x1370: +case 0x1570: +case 0x1770: +case 0x1970: +case 0x1B70: +case 0x1D70: +case 0x1F70: +case 0x1171: +case 0x1371: +case 0x1571: +case 0x1771: +case 0x1971: +case 0x1B71: +case 0x1D71: +case 0x1F71: +case 0x1172: +case 0x1372: +case 0x1572: +case 0x1772: +case 0x1972: +case 0x1B72: +case 0x1D72: +case 0x1F72: +case 0x1173: +case 0x1373: +case 0x1573: +case 0x1773: +case 0x1973: +case 0x1B73: +case 0x1D73: +case 0x1F73: +case 0x1174: +case 0x1374: +case 0x1574: +case 0x1774: +case 0x1974: +case 0x1B74: +case 0x1D74: +case 0x1F74: +case 0x1175: +case 0x1375: +case 0x1575: +case 0x1775: +case 0x1975: +case 0x1B75: +case 0x1D75: +case 0x1F75: +case 0x1176: +case 0x1376: +case 0x1576: +case 0x1776: +case 0x1976: +case 0x1B76: +case 0x1D76: +case 0x1F76: +case 0x1177: +case 0x1377: +case 0x1577: +case 0x1777: +case 0x1977: +case 0x1B77: +case 0x1D77: +case 0x1F77: + +// MOVEB +case 0x1170: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(22) +case 0x13B0: +case 0x15B0: +case 0x17B0: +case 0x19B0: +case 0x1BB0: +case 0x1DB0: +case 0x1FB0: +case 0x11B1: +case 0x13B1: +case 0x15B1: +case 0x17B1: +case 0x19B1: +case 0x1BB1: +case 0x1DB1: +case 0x1FB1: +case 0x11B2: +case 0x13B2: +case 0x15B2: +case 0x17B2: +case 0x19B2: +case 0x1BB2: +case 0x1DB2: +case 0x1FB2: +case 0x11B3: +case 0x13B3: +case 0x15B3: +case 0x17B3: +case 0x19B3: +case 0x1BB3: +case 0x1DB3: +case 0x1FB3: +case 0x11B4: +case 0x13B4: +case 0x15B4: +case 0x17B4: +case 0x19B4: +case 0x1BB4: +case 0x1DB4: +case 0x1FB4: +case 0x11B5: +case 0x13B5: +case 0x15B5: +case 0x17B5: +case 0x19B5: +case 0x1BB5: +case 0x1DB5: +case 0x1FB5: +case 0x11B6: +case 0x13B6: +case 0x15B6: +case 0x17B6: +case 0x19B6: +case 0x1BB6: +case 0x1DB6: +case 0x1FB6: +case 0x11B7: +case 0x13B7: +case 0x15B7: +case 0x17B7: +case 0x19B7: +case 0x1BB7: +case 0x1DB7: +case 0x1FB7: + +// MOVEB +case 0x11B0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7]; + DECODE_EXT_WORD + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(24) +case 0x11F1: +case 0x11F2: +case 0x11F3: +case 0x11F4: +case 0x11F5: +case 0x11F6: +case 0x11F7: + +// MOVEB +case 0x11F0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(22) +case 0x13F1: +case 0x13F2: +case 0x13F3: +case 0x13F4: +case 0x13F5: +case 0x13F6: +case 0x13F7: + +// MOVEB +case 0x13F0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = (s32)FETCH_LONG; + PC += 4; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(26) +case 0x1EF1: +case 0x1EF2: +case 0x1EF3: +case 0x1EF4: +case 0x1EF5: +case 0x1EF6: +case 0x1EF7: + +// MOVEB +case 0x1EF0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[7]; + CPU->A[7] += 2; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) +case 0x1F31: +case 0x1F32: +case 0x1F33: +case 0x1F34: +case 0x1F35: +case 0x1F36: +case 0x1F37: + +// MOVEB +case 0x1F30: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) +case 0x1238: +case 0x1438: +case 0x1638: +case 0x1838: +case 0x1A38: +case 0x1C38: +case 0x1E38: + +// MOVEB +case 0x1038: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(12) +case 0x12B8: +case 0x14B8: +case 0x16B8: +case 0x18B8: +case 0x1AB8: +case 0x1CB8: +case 0x1EB8: + +// MOVEB +case 0x10B8: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7]; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0x12F8: +case 0x14F8: +case 0x16F8: +case 0x18F8: +case 0x1AF8: +case 0x1CF8: + +// MOVEB +case 0x10F8: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7]; + CPU->A[(Opcode >> 9) & 7] += 1; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0x1338: +case 0x1538: +case 0x1738: +case 0x1938: +case 0x1B38: +case 0x1D38: + +// MOVEB +case 0x1138: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7] - 1; + CPU->A[(Opcode >> 9) & 7] = adr; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0x1378: +case 0x1578: +case 0x1778: +case 0x1978: +case 0x1B78: +case 0x1D78: +case 0x1F78: + +// MOVEB +case 0x1178: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(20) +case 0x13B8: +case 0x15B8: +case 0x17B8: +case 0x19B8: +case 0x1BB8: +case 0x1DB8: +case 0x1FB8: + +// MOVEB +case 0x11B8: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7]; + DECODE_EXT_WORD + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(22) + +// MOVEB +case 0x11F8: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(20) + +// MOVEB +case 0x13F8: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = (s32)FETCH_LONG; + PC += 4; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(24) + +// MOVEB +case 0x1EF8: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[7]; + CPU->A[7] += 2; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) + +// MOVEB +case 0x1F38: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0x1239: +case 0x1439: +case 0x1639: +case 0x1839: +case 0x1A39: +case 0x1C39: +case 0x1E39: + +// MOVEB +case 0x1039: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(16) +case 0x12B9: +case 0x14B9: +case 0x16B9: +case 0x18B9: +case 0x1AB9: +case 0x1CB9: +case 0x1EB9: + +// MOVEB +case 0x10B9: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7]; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(20) +case 0x12F9: +case 0x14F9: +case 0x16F9: +case 0x18F9: +case 0x1AF9: +case 0x1CF9: + +// MOVEB +case 0x10F9: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7]; + CPU->A[(Opcode >> 9) & 7] += 1; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(20) +case 0x1339: +case 0x1539: +case 0x1739: +case 0x1939: +case 0x1B39: +case 0x1D39: + +// MOVEB +case 0x1139: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7] - 1; + CPU->A[(Opcode >> 9) & 7] = adr; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(20) +case 0x1379: +case 0x1579: +case 0x1779: +case 0x1979: +case 0x1B79: +case 0x1D79: +case 0x1F79: + +// MOVEB +case 0x1179: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(24) +case 0x13B9: +case 0x15B9: +case 0x17B9: +case 0x19B9: +case 0x1BB9: +case 0x1DB9: +case 0x1FB9: + +// MOVEB +case 0x11B9: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7]; + DECODE_EXT_WORD + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(26) + +// MOVEB +case 0x11F9: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(24) + +// MOVEB +case 0x13F9: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = (s32)FETCH_LONG; + PC += 4; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(28) + +// MOVEB +case 0x1EF9: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[7]; + CPU->A[7] += 2; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(20) + +// MOVEB +case 0x1F39: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(20) +case 0x123A: +case 0x143A: +case 0x163A: +case 0x183A: +case 0x1A3A: +case 0x1C3A: +case 0x1E3A: + +// MOVEB +case 0x103A: +{ + u32 adr; + u32 res; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(12) +case 0x12BA: +case 0x14BA: +case 0x16BA: +case 0x18BA: +case 0x1ABA: +case 0x1CBA: +case 0x1EBA: + +// MOVEB +case 0x10BA: +{ + u32 adr; + u32 res; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7]; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0x12FA: +case 0x14FA: +case 0x16FA: +case 0x18FA: +case 0x1AFA: +case 0x1CFA: + +// MOVEB +case 0x10FA: +{ + u32 adr; + u32 res; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7]; + CPU->A[(Opcode >> 9) & 7] += 1; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0x133A: +case 0x153A: +case 0x173A: +case 0x193A: +case 0x1B3A: +case 0x1D3A: + +// MOVEB +case 0x113A: +{ + u32 adr; + u32 res; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7] - 1; + CPU->A[(Opcode >> 9) & 7] = adr; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0x137A: +case 0x157A: +case 0x177A: +case 0x197A: +case 0x1B7A: +case 0x1D7A: +case 0x1F7A: + +// MOVEB +case 0x117A: +{ + u32 adr; + u32 res; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(20) +case 0x13BA: +case 0x15BA: +case 0x17BA: +case 0x19BA: +case 0x1BBA: +case 0x1DBA: +case 0x1FBA: + +// MOVEB +case 0x11BA: +{ + u32 adr; + u32 res; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7]; + DECODE_EXT_WORD + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(22) + +// MOVEB +case 0x11FA: +{ + u32 adr; + u32 res; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(20) + +// MOVEB +case 0x13FA: +{ + u32 adr; + u32 res; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = (s32)FETCH_LONG; + PC += 4; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(24) + +// MOVEB +case 0x1EFA: +{ + u32 adr; + u32 res; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[7]; + CPU->A[7] += 2; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) + +// MOVEB +case 0x1F3A: +{ + u32 adr; + u32 res; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0x123B: +case 0x143B: +case 0x163B: +case 0x183B: +case 0x1A3B: +case 0x1C3B: +case 0x1E3B: + +// MOVEB +case 0x103B: +{ + u32 adr; + u32 res; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(14) +case 0x12BB: +case 0x14BB: +case 0x16BB: +case 0x18BB: +case 0x1ABB: +case 0x1CBB: +case 0x1EBB: + +// MOVEB +case 0x10BB: +{ + u32 adr; + u32 res; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7]; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) +case 0x12FB: +case 0x14FB: +case 0x16FB: +case 0x18FB: +case 0x1AFB: +case 0x1CFB: + +// MOVEB +case 0x10FB: +{ + u32 adr; + u32 res; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7]; + CPU->A[(Opcode >> 9) & 7] += 1; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) +case 0x133B: +case 0x153B: +case 0x173B: +case 0x193B: +case 0x1B3B: +case 0x1D3B: + +// MOVEB +case 0x113B: +{ + u32 adr; + u32 res; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7] - 1; + CPU->A[(Opcode >> 9) & 7] = adr; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) +case 0x137B: +case 0x157B: +case 0x177B: +case 0x197B: +case 0x1B7B: +case 0x1D7B: +case 0x1F7B: + +// MOVEB +case 0x117B: +{ + u32 adr; + u32 res; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(22) +case 0x13BB: +case 0x15BB: +case 0x17BB: +case 0x19BB: +case 0x1BBB: +case 0x1DBB: +case 0x1FBB: + +// MOVEB +case 0x11BB: +{ + u32 adr; + u32 res; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7]; + DECODE_EXT_WORD + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(24) + +// MOVEB +case 0x11FB: +{ + u32 adr; + u32 res; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(22) + +// MOVEB +case 0x13FB: +{ + u32 adr; + u32 res; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = (s32)FETCH_LONG; + PC += 4; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(26) + +// MOVEB +case 0x1EFB: +{ + u32 adr; + u32 res; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[7]; + CPU->A[7] += 2; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) + +// MOVEB +case 0x1F3B: +{ + u32 adr; + u32 res; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) +case 0x123C: +case 0x143C: +case 0x163C: +case 0x183C: +case 0x1A3C: +case 0x1C3C: +case 0x1E3C: + +// MOVEB +case 0x103C: +{ + u32 res; + res = FETCH_BYTE; + PC += 2; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; +} +RET(8) +case 0x12BC: +case 0x14BC: +case 0x16BC: +case 0x18BC: +case 0x1ABC: +case 0x1CBC: +case 0x1EBC: + +// MOVEB +case 0x10BC: +{ + u32 adr; + u32 res; + res = FETCH_BYTE; + PC += 2; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7]; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0x12FC: +case 0x14FC: +case 0x16FC: +case 0x18FC: +case 0x1AFC: +case 0x1CFC: + +// MOVEB +case 0x10FC: +{ + u32 adr; + u32 res; + res = FETCH_BYTE; + PC += 2; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7]; + CPU->A[(Opcode >> 9) & 7] += 1; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0x133C: +case 0x153C: +case 0x173C: +case 0x193C: +case 0x1B3C: +case 0x1D3C: + +// MOVEB +case 0x113C: +{ + u32 adr; + u32 res; + res = FETCH_BYTE; + PC += 2; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7] - 1; + CPU->A[(Opcode >> 9) & 7] = adr; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0x137C: +case 0x157C: +case 0x177C: +case 0x197C: +case 0x1B7C: +case 0x1D7C: +case 0x1F7C: + +// MOVEB +case 0x117C: +{ + u32 adr; + u32 res; + res = FETCH_BYTE; + PC += 2; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0x13BC: +case 0x15BC: +case 0x17BC: +case 0x19BC: +case 0x1BBC: +case 0x1DBC: +case 0x1FBC: + +// MOVEB +case 0x11BC: +{ + u32 adr; + u32 res; + res = FETCH_BYTE; + PC += 2; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7]; + DECODE_EXT_WORD + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) + +// MOVEB +case 0x11FC: +{ + u32 adr; + u32 res; + res = FETCH_BYTE; + PC += 2; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) + +// MOVEB +case 0x13FC: +{ + u32 adr; + u32 res; + res = FETCH_BYTE; + PC += 2; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(20) + +// MOVEB +case 0x1EFC: +{ + u32 adr; + u32 res; + res = FETCH_BYTE; + PC += 2; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) + +// MOVEB +case 0x1F3C: +{ + u32 adr; + u32 res; + res = FETCH_BYTE; + PC += 2; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0x121F: +case 0x141F: +case 0x161F: +case 0x181F: +case 0x1A1F: +case 0x1C1F: +case 0x1E1F: + +// MOVEB +case 0x101F: +{ + u32 adr; + u32 res; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(8) +case 0x129F: +case 0x149F: +case 0x169F: +case 0x189F: +case 0x1A9F: +case 0x1C9F: +case 0x1E9F: + +// MOVEB +case 0x109F: +{ + u32 adr; + u32 res; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7]; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0x12DF: +case 0x14DF: +case 0x16DF: +case 0x18DF: +case 0x1ADF: +case 0x1CDF: + +// MOVEB +case 0x10DF: +{ + u32 adr; + u32 res; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7]; + CPU->A[(Opcode >> 9) & 7] += 1; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0x131F: +case 0x151F: +case 0x171F: +case 0x191F: +case 0x1B1F: +case 0x1D1F: + +// MOVEB +case 0x111F: +{ + u32 adr; + u32 res; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7] - 1; + CPU->A[(Opcode >> 9) & 7] = adr; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0x135F: +case 0x155F: +case 0x175F: +case 0x195F: +case 0x1B5F: +case 0x1D5F: +case 0x1F5F: + +// MOVEB +case 0x115F: +{ + u32 adr; + u32 res; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0x139F: +case 0x159F: +case 0x179F: +case 0x199F: +case 0x1B9F: +case 0x1D9F: +case 0x1F9F: + +// MOVEB +case 0x119F: +{ + u32 adr; + u32 res; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7]; + DECODE_EXT_WORD + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) + +// MOVEB +case 0x11DF: +{ + u32 adr; + u32 res; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) + +// MOVEB +case 0x13DF: +{ + u32 adr; + u32 res; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = (s32)FETCH_LONG; + PC += 4; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(20) + +// MOVEB +case 0x1EDF: +{ + u32 adr; + u32 res; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[7]; + CPU->A[7] += 2; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) + +// MOVEB +case 0x1F1F: +{ + u32 adr; + u32 res; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0x1227: +case 0x1427: +case 0x1627: +case 0x1827: +case 0x1A27: +case 0x1C27: +case 0x1E27: + +// MOVEB +case 0x1027: +{ + u32 adr; + u32 res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(10) +case 0x12A7: +case 0x14A7: +case 0x16A7: +case 0x18A7: +case 0x1AA7: +case 0x1CA7: +case 0x1EA7: + +// MOVEB +case 0x10A7: +{ + u32 adr; + u32 res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7]; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(14) +case 0x12E7: +case 0x14E7: +case 0x16E7: +case 0x18E7: +case 0x1AE7: +case 0x1CE7: + +// MOVEB +case 0x10E7: +{ + u32 adr; + u32 res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7]; + CPU->A[(Opcode >> 9) & 7] += 1; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(14) +case 0x1327: +case 0x1527: +case 0x1727: +case 0x1927: +case 0x1B27: +case 0x1D27: + +// MOVEB +case 0x1127: +{ + u32 adr; + u32 res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7] - 1; + CPU->A[(Opcode >> 9) & 7] = adr; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(14) +case 0x1367: +case 0x1567: +case 0x1767: +case 0x1967: +case 0x1B67: +case 0x1D67: +case 0x1F67: + +// MOVEB +case 0x1167: +{ + u32 adr; + u32 res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) +case 0x13A7: +case 0x15A7: +case 0x17A7: +case 0x19A7: +case 0x1BA7: +case 0x1DA7: +case 0x1FA7: + +// MOVEB +case 0x11A7: +{ + u32 adr; + u32 res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[(Opcode >> 9) & 7]; + DECODE_EXT_WORD + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(20) + +// MOVEB +case 0x11E7: +{ + u32 adr; + u32 res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) + +// MOVEB +case 0x13E7: +{ + u32 adr; + u32 res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = (s32)FETCH_LONG; + PC += 4; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(22) + +// MOVEB +case 0x1EE7: +{ + u32 adr; + u32 res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[7]; + CPU->A[7] += 2; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(14) + +// MOVEB +case 0x1F27: +{ + u32 adr; + u32 res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(14) diff --git a/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68k_op2.inc b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68k_op2.inc new file mode 100644 index 000000000..aaf2122df --- /dev/null +++ b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68k_op2.inc @@ -0,0 +1,6254 @@ +case 0x2200: +case 0x2400: +case 0x2600: +case 0x2800: +case 0x2A00: +case 0x2C00: +case 0x2E00: +case 0x2001: +case 0x2201: +case 0x2401: +case 0x2601: +case 0x2801: +case 0x2A01: +case 0x2C01: +case 0x2E01: +case 0x2002: +case 0x2202: +case 0x2402: +case 0x2602: +case 0x2802: +case 0x2A02: +case 0x2C02: +case 0x2E02: +case 0x2003: +case 0x2203: +case 0x2403: +case 0x2603: +case 0x2803: +case 0x2A03: +case 0x2C03: +case 0x2E03: +case 0x2004: +case 0x2204: +case 0x2404: +case 0x2604: +case 0x2804: +case 0x2A04: +case 0x2C04: +case 0x2E04: +case 0x2005: +case 0x2205: +case 0x2405: +case 0x2605: +case 0x2805: +case 0x2A05: +case 0x2C05: +case 0x2E05: +case 0x2006: +case 0x2206: +case 0x2406: +case 0x2606: +case 0x2806: +case 0x2A06: +case 0x2C06: +case 0x2E06: +case 0x2007: +case 0x2207: +case 0x2407: +case 0x2607: +case 0x2807: +case 0x2A07: +case 0x2C07: +case 0x2E07: + +// MOVEL +case 0x2000: +{ + u32 res; + res = (u32)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; +} +RET(4) +case 0x2280: +case 0x2480: +case 0x2680: +case 0x2880: +case 0x2A80: +case 0x2C80: +case 0x2E80: +case 0x2081: +case 0x2281: +case 0x2481: +case 0x2681: +case 0x2881: +case 0x2A81: +case 0x2C81: +case 0x2E81: +case 0x2082: +case 0x2282: +case 0x2482: +case 0x2682: +case 0x2882: +case 0x2A82: +case 0x2C82: +case 0x2E82: +case 0x2083: +case 0x2283: +case 0x2483: +case 0x2683: +case 0x2883: +case 0x2A83: +case 0x2C83: +case 0x2E83: +case 0x2084: +case 0x2284: +case 0x2484: +case 0x2684: +case 0x2884: +case 0x2A84: +case 0x2C84: +case 0x2E84: +case 0x2085: +case 0x2285: +case 0x2485: +case 0x2685: +case 0x2885: +case 0x2A85: +case 0x2C85: +case 0x2E85: +case 0x2086: +case 0x2286: +case 0x2486: +case 0x2686: +case 0x2886: +case 0x2A86: +case 0x2C86: +case 0x2E86: +case 0x2087: +case 0x2287: +case 0x2487: +case 0x2687: +case 0x2887: +case 0x2A87: +case 0x2C87: +case 0x2E87: + +// MOVEL +case 0x2080: +{ + u32 adr; + u32 res; + res = (u32)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7]; + PRE_IO + WRITE_LONG_F(adr, res) + POST_IO +} +RET(12) +case 0x22C0: +case 0x24C0: +case 0x26C0: +case 0x28C0: +case 0x2AC0: +case 0x2CC0: +case 0x20C1: +case 0x22C1: +case 0x24C1: +case 0x26C1: +case 0x28C1: +case 0x2AC1: +case 0x2CC1: +case 0x20C2: +case 0x22C2: +case 0x24C2: +case 0x26C2: +case 0x28C2: +case 0x2AC2: +case 0x2CC2: +case 0x20C3: +case 0x22C3: +case 0x24C3: +case 0x26C3: +case 0x28C3: +case 0x2AC3: +case 0x2CC3: +case 0x20C4: +case 0x22C4: +case 0x24C4: +case 0x26C4: +case 0x28C4: +case 0x2AC4: +case 0x2CC4: +case 0x20C5: +case 0x22C5: +case 0x24C5: +case 0x26C5: +case 0x28C5: +case 0x2AC5: +case 0x2CC5: +case 0x20C6: +case 0x22C6: +case 0x24C6: +case 0x26C6: +case 0x28C6: +case 0x2AC6: +case 0x2CC6: +case 0x20C7: +case 0x22C7: +case 0x24C7: +case 0x26C7: +case 0x28C7: +case 0x2AC7: +case 0x2CC7: + +// MOVEL +case 0x20C0: +{ + u32 adr; + u32 res; + res = (u32)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7]; + CPU->A[(Opcode >> 9) & 7] += 4; + PRE_IO + WRITE_LONG_F(adr, res) + POST_IO +} +RET(12) +case 0x2300: +case 0x2500: +case 0x2700: +case 0x2900: +case 0x2B00: +case 0x2D00: +case 0x2101: +case 0x2301: +case 0x2501: +case 0x2701: +case 0x2901: +case 0x2B01: +case 0x2D01: +case 0x2102: +case 0x2302: +case 0x2502: +case 0x2702: +case 0x2902: +case 0x2B02: +case 0x2D02: +case 0x2103: +case 0x2303: +case 0x2503: +case 0x2703: +case 0x2903: +case 0x2B03: +case 0x2D03: +case 0x2104: +case 0x2304: +case 0x2504: +case 0x2704: +case 0x2904: +case 0x2B04: +case 0x2D04: +case 0x2105: +case 0x2305: +case 0x2505: +case 0x2705: +case 0x2905: +case 0x2B05: +case 0x2D05: +case 0x2106: +case 0x2306: +case 0x2506: +case 0x2706: +case 0x2906: +case 0x2B06: +case 0x2D06: +case 0x2107: +case 0x2307: +case 0x2507: +case 0x2707: +case 0x2907: +case 0x2B07: +case 0x2D07: + +// MOVEL +case 0x2100: +{ + u32 adr; + u32 res; + res = (u32)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7] - 4; + CPU->A[(Opcode >> 9) & 7] = adr; + PRE_IO + WRITE_LONG_F(adr, res) + POST_IO +} +RET(12) +case 0x2340: +case 0x2540: +case 0x2740: +case 0x2940: +case 0x2B40: +case 0x2D40: +case 0x2F40: +case 0x2141: +case 0x2341: +case 0x2541: +case 0x2741: +case 0x2941: +case 0x2B41: +case 0x2D41: +case 0x2F41: +case 0x2142: +case 0x2342: +case 0x2542: +case 0x2742: +case 0x2942: +case 0x2B42: +case 0x2D42: +case 0x2F42: +case 0x2143: +case 0x2343: +case 0x2543: +case 0x2743: +case 0x2943: +case 0x2B43: +case 0x2D43: +case 0x2F43: +case 0x2144: +case 0x2344: +case 0x2544: +case 0x2744: +case 0x2944: +case 0x2B44: +case 0x2D44: +case 0x2F44: +case 0x2145: +case 0x2345: +case 0x2545: +case 0x2745: +case 0x2945: +case 0x2B45: +case 0x2D45: +case 0x2F45: +case 0x2146: +case 0x2346: +case 0x2546: +case 0x2746: +case 0x2946: +case 0x2B46: +case 0x2D46: +case 0x2F46: +case 0x2147: +case 0x2347: +case 0x2547: +case 0x2747: +case 0x2947: +case 0x2B47: +case 0x2D47: +case 0x2F47: + +// MOVEL +case 0x2140: +{ + u32 adr; + u32 res; + res = (u32)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + WRITE_LONG_F(adr, res) + POST_IO +} +RET(16) +case 0x2380: +case 0x2580: +case 0x2780: +case 0x2980: +case 0x2B80: +case 0x2D80: +case 0x2F80: +case 0x2181: +case 0x2381: +case 0x2581: +case 0x2781: +case 0x2981: +case 0x2B81: +case 0x2D81: +case 0x2F81: +case 0x2182: +case 0x2382: +case 0x2582: +case 0x2782: +case 0x2982: +case 0x2B82: +case 0x2D82: +case 0x2F82: +case 0x2183: +case 0x2383: +case 0x2583: +case 0x2783: +case 0x2983: +case 0x2B83: +case 0x2D83: +case 0x2F83: +case 0x2184: +case 0x2384: +case 0x2584: +case 0x2784: +case 0x2984: +case 0x2B84: +case 0x2D84: +case 0x2F84: +case 0x2185: +case 0x2385: +case 0x2585: +case 0x2785: +case 0x2985: +case 0x2B85: +case 0x2D85: +case 0x2F85: +case 0x2186: +case 0x2386: +case 0x2586: +case 0x2786: +case 0x2986: +case 0x2B86: +case 0x2D86: +case 0x2F86: +case 0x2187: +case 0x2387: +case 0x2587: +case 0x2787: +case 0x2987: +case 0x2B87: +case 0x2D87: +case 0x2F87: + +// MOVEL +case 0x2180: +{ + u32 adr; + u32 res; + res = (u32)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7]; + DECODE_EXT_WORD + PRE_IO + WRITE_LONG_F(adr, res) + POST_IO +} +RET(18) +case 0x21C1: +case 0x21C2: +case 0x21C3: +case 0x21C4: +case 0x21C5: +case 0x21C6: +case 0x21C7: + +// MOVEL +case 0x21C0: +{ + u32 adr; + u32 res; + res = (u32)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + WRITE_LONG_F(adr, res) + POST_IO +} +RET(16) +case 0x23C1: +case 0x23C2: +case 0x23C3: +case 0x23C4: +case 0x23C5: +case 0x23C6: +case 0x23C7: + +// MOVEL +case 0x23C0: +{ + u32 adr; + u32 res; + res = (u32)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + WRITE_LONG_F(adr, res) + POST_IO +} +RET(20) +case 0x2EC1: +case 0x2EC2: +case 0x2EC3: +case 0x2EC4: +case 0x2EC5: +case 0x2EC6: +case 0x2EC7: + +// MOVEL +case 0x2EC0: +{ + u32 adr; + u32 res; + res = (u32)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[7]; + CPU->A[7] += 4; + PRE_IO + WRITE_LONG_F(adr, res) + POST_IO +} +RET(12) +case 0x2F01: +case 0x2F02: +case 0x2F03: +case 0x2F04: +case 0x2F05: +case 0x2F06: +case 0x2F07: + +// MOVEL +case 0x2F00: +{ + u32 adr; + u32 res; + res = (u32)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + PRE_IO + WRITE_LONG_F(adr, res) + POST_IO +} +RET(12) +case 0x2208: +case 0x2408: +case 0x2608: +case 0x2808: +case 0x2A08: +case 0x2C08: +case 0x2E08: +case 0x2009: +case 0x2209: +case 0x2409: +case 0x2609: +case 0x2809: +case 0x2A09: +case 0x2C09: +case 0x2E09: +case 0x200A: +case 0x220A: +case 0x240A: +case 0x260A: +case 0x280A: +case 0x2A0A: +case 0x2C0A: +case 0x2E0A: +case 0x200B: +case 0x220B: +case 0x240B: +case 0x260B: +case 0x280B: +case 0x2A0B: +case 0x2C0B: +case 0x2E0B: +case 0x200C: +case 0x220C: +case 0x240C: +case 0x260C: +case 0x280C: +case 0x2A0C: +case 0x2C0C: +case 0x2E0C: +case 0x200D: +case 0x220D: +case 0x240D: +case 0x260D: +case 0x280D: +case 0x2A0D: +case 0x2C0D: +case 0x2E0D: +case 0x200E: +case 0x220E: +case 0x240E: +case 0x260E: +case 0x280E: +case 0x2A0E: +case 0x2C0E: +case 0x2E0E: +case 0x200F: +case 0x220F: +case 0x240F: +case 0x260F: +case 0x280F: +case 0x2A0F: +case 0x2C0F: +case 0x2E0F: + +// MOVEL +case 0x2008: +{ + u32 res; + res = (u32)CPU->A[(Opcode >> 0) & 7]; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; +} +RET(4) +case 0x2288: +case 0x2488: +case 0x2688: +case 0x2888: +case 0x2A88: +case 0x2C88: +case 0x2E88: +case 0x2089: +case 0x2289: +case 0x2489: +case 0x2689: +case 0x2889: +case 0x2A89: +case 0x2C89: +case 0x2E89: +case 0x208A: +case 0x228A: +case 0x248A: +case 0x268A: +case 0x288A: +case 0x2A8A: +case 0x2C8A: +case 0x2E8A: +case 0x208B: +case 0x228B: +case 0x248B: +case 0x268B: +case 0x288B: +case 0x2A8B: +case 0x2C8B: +case 0x2E8B: +case 0x208C: +case 0x228C: +case 0x248C: +case 0x268C: +case 0x288C: +case 0x2A8C: +case 0x2C8C: +case 0x2E8C: +case 0x208D: +case 0x228D: +case 0x248D: +case 0x268D: +case 0x288D: +case 0x2A8D: +case 0x2C8D: +case 0x2E8D: +case 0x208E: +case 0x228E: +case 0x248E: +case 0x268E: +case 0x288E: +case 0x2A8E: +case 0x2C8E: +case 0x2E8E: +case 0x208F: +case 0x228F: +case 0x248F: +case 0x268F: +case 0x288F: +case 0x2A8F: +case 0x2C8F: +case 0x2E8F: + +// MOVEL +case 0x2088: +{ + u32 adr; + u32 res; + res = (u32)CPU->A[(Opcode >> 0) & 7]; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7]; + PRE_IO + WRITE_LONG_F(adr, res) + POST_IO +} +RET(12) +case 0x22C8: +case 0x24C8: +case 0x26C8: +case 0x28C8: +case 0x2AC8: +case 0x2CC8: +case 0x20C9: +case 0x22C9: +case 0x24C9: +case 0x26C9: +case 0x28C9: +case 0x2AC9: +case 0x2CC9: +case 0x20CA: +case 0x22CA: +case 0x24CA: +case 0x26CA: +case 0x28CA: +case 0x2ACA: +case 0x2CCA: +case 0x20CB: +case 0x22CB: +case 0x24CB: +case 0x26CB: +case 0x28CB: +case 0x2ACB: +case 0x2CCB: +case 0x20CC: +case 0x22CC: +case 0x24CC: +case 0x26CC: +case 0x28CC: +case 0x2ACC: +case 0x2CCC: +case 0x20CD: +case 0x22CD: +case 0x24CD: +case 0x26CD: +case 0x28CD: +case 0x2ACD: +case 0x2CCD: +case 0x20CE: +case 0x22CE: +case 0x24CE: +case 0x26CE: +case 0x28CE: +case 0x2ACE: +case 0x2CCE: +case 0x20CF: +case 0x22CF: +case 0x24CF: +case 0x26CF: +case 0x28CF: +case 0x2ACF: +case 0x2CCF: + +// MOVEL +case 0x20C8: +{ + u32 adr; + u32 res; + res = (u32)CPU->A[(Opcode >> 0) & 7]; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7]; + CPU->A[(Opcode >> 9) & 7] += 4; + PRE_IO + WRITE_LONG_F(adr, res) + POST_IO +} +RET(12) +case 0x2308: +case 0x2508: +case 0x2708: +case 0x2908: +case 0x2B08: +case 0x2D08: +case 0x2109: +case 0x2309: +case 0x2509: +case 0x2709: +case 0x2909: +case 0x2B09: +case 0x2D09: +case 0x210A: +case 0x230A: +case 0x250A: +case 0x270A: +case 0x290A: +case 0x2B0A: +case 0x2D0A: +case 0x210B: +case 0x230B: +case 0x250B: +case 0x270B: +case 0x290B: +case 0x2B0B: +case 0x2D0B: +case 0x210C: +case 0x230C: +case 0x250C: +case 0x270C: +case 0x290C: +case 0x2B0C: +case 0x2D0C: +case 0x210D: +case 0x230D: +case 0x250D: +case 0x270D: +case 0x290D: +case 0x2B0D: +case 0x2D0D: +case 0x210E: +case 0x230E: +case 0x250E: +case 0x270E: +case 0x290E: +case 0x2B0E: +case 0x2D0E: +case 0x210F: +case 0x230F: +case 0x250F: +case 0x270F: +case 0x290F: +case 0x2B0F: +case 0x2D0F: + +// MOVEL +case 0x2108: +{ + u32 adr; + u32 res; + res = (u32)CPU->A[(Opcode >> 0) & 7]; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7] - 4; + CPU->A[(Opcode >> 9) & 7] = adr; + PRE_IO + WRITE_LONG_F(adr, res) + POST_IO +} +RET(12) +case 0x2348: +case 0x2548: +case 0x2748: +case 0x2948: +case 0x2B48: +case 0x2D48: +case 0x2F48: +case 0x2149: +case 0x2349: +case 0x2549: +case 0x2749: +case 0x2949: +case 0x2B49: +case 0x2D49: +case 0x2F49: +case 0x214A: +case 0x234A: +case 0x254A: +case 0x274A: +case 0x294A: +case 0x2B4A: +case 0x2D4A: +case 0x2F4A: +case 0x214B: +case 0x234B: +case 0x254B: +case 0x274B: +case 0x294B: +case 0x2B4B: +case 0x2D4B: +case 0x2F4B: +case 0x214C: +case 0x234C: +case 0x254C: +case 0x274C: +case 0x294C: +case 0x2B4C: +case 0x2D4C: +case 0x2F4C: +case 0x214D: +case 0x234D: +case 0x254D: +case 0x274D: +case 0x294D: +case 0x2B4D: +case 0x2D4D: +case 0x2F4D: +case 0x214E: +case 0x234E: +case 0x254E: +case 0x274E: +case 0x294E: +case 0x2B4E: +case 0x2D4E: +case 0x2F4E: +case 0x214F: +case 0x234F: +case 0x254F: +case 0x274F: +case 0x294F: +case 0x2B4F: +case 0x2D4F: +case 0x2F4F: + +// MOVEL +case 0x2148: +{ + u32 adr; + u32 res; + res = (u32)CPU->A[(Opcode >> 0) & 7]; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + WRITE_LONG_F(adr, res) + POST_IO +} +RET(16) +case 0x2388: +case 0x2588: +case 0x2788: +case 0x2988: +case 0x2B88: +case 0x2D88: +case 0x2F88: +case 0x2189: +case 0x2389: +case 0x2589: +case 0x2789: +case 0x2989: +case 0x2B89: +case 0x2D89: +case 0x2F89: +case 0x218A: +case 0x238A: +case 0x258A: +case 0x278A: +case 0x298A: +case 0x2B8A: +case 0x2D8A: +case 0x2F8A: +case 0x218B: +case 0x238B: +case 0x258B: +case 0x278B: +case 0x298B: +case 0x2B8B: +case 0x2D8B: +case 0x2F8B: +case 0x218C: +case 0x238C: +case 0x258C: +case 0x278C: +case 0x298C: +case 0x2B8C: +case 0x2D8C: +case 0x2F8C: +case 0x218D: +case 0x238D: +case 0x258D: +case 0x278D: +case 0x298D: +case 0x2B8D: +case 0x2D8D: +case 0x2F8D: +case 0x218E: +case 0x238E: +case 0x258E: +case 0x278E: +case 0x298E: +case 0x2B8E: +case 0x2D8E: +case 0x2F8E: +case 0x218F: +case 0x238F: +case 0x258F: +case 0x278F: +case 0x298F: +case 0x2B8F: +case 0x2D8F: +case 0x2F8F: + +// MOVEL +case 0x2188: +{ + u32 adr; + u32 res; + res = (u32)CPU->A[(Opcode >> 0) & 7]; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7]; + DECODE_EXT_WORD + PRE_IO + WRITE_LONG_F(adr, res) + POST_IO +} +RET(18) +case 0x21C9: +case 0x21CA: +case 0x21CB: +case 0x21CC: +case 0x21CD: +case 0x21CE: +case 0x21CF: + +// MOVEL +case 0x21C8: +{ + u32 adr; + u32 res; + res = (u32)CPU->A[(Opcode >> 0) & 7]; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + WRITE_LONG_F(adr, res) + POST_IO +} +RET(16) +case 0x23C9: +case 0x23CA: +case 0x23CB: +case 0x23CC: +case 0x23CD: +case 0x23CE: +case 0x23CF: + +// MOVEL +case 0x23C8: +{ + u32 adr; + u32 res; + res = (u32)CPU->A[(Opcode >> 0) & 7]; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + WRITE_LONG_F(adr, res) + POST_IO +} +RET(20) +case 0x2EC9: +case 0x2ECA: +case 0x2ECB: +case 0x2ECC: +case 0x2ECD: +case 0x2ECE: +case 0x2ECF: + +// MOVEL +case 0x2EC8: +{ + u32 adr; + u32 res; + res = (u32)CPU->A[(Opcode >> 0) & 7]; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[7]; + CPU->A[7] += 4; + PRE_IO + WRITE_LONG_F(adr, res) + POST_IO +} +RET(12) +case 0x2F09: +case 0x2F0A: +case 0x2F0B: +case 0x2F0C: +case 0x2F0D: +case 0x2F0E: +case 0x2F0F: + +// MOVEL +case 0x2F08: +{ + u32 adr; + u32 res; + res = (u32)CPU->A[(Opcode >> 0) & 7]; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + PRE_IO + WRITE_LONG_F(adr, res) + POST_IO +} +RET(12) +case 0x2210: +case 0x2410: +case 0x2610: +case 0x2810: +case 0x2A10: +case 0x2C10: +case 0x2E10: +case 0x2011: +case 0x2211: +case 0x2411: +case 0x2611: +case 0x2811: +case 0x2A11: +case 0x2C11: +case 0x2E11: +case 0x2012: +case 0x2212: +case 0x2412: +case 0x2612: +case 0x2812: +case 0x2A12: +case 0x2C12: +case 0x2E12: +case 0x2013: +case 0x2213: +case 0x2413: +case 0x2613: +case 0x2813: +case 0x2A13: +case 0x2C13: +case 0x2E13: +case 0x2014: +case 0x2214: +case 0x2414: +case 0x2614: +case 0x2814: +case 0x2A14: +case 0x2C14: +case 0x2E14: +case 0x2015: +case 0x2215: +case 0x2415: +case 0x2615: +case 0x2815: +case 0x2A15: +case 0x2C15: +case 0x2E15: +case 0x2016: +case 0x2216: +case 0x2416: +case 0x2616: +case 0x2816: +case 0x2A16: +case 0x2C16: +case 0x2E16: +case 0x2017: +case 0x2217: +case 0x2417: +case 0x2617: +case 0x2817: +case 0x2A17: +case 0x2C17: +case 0x2E17: + +// MOVEL +case 0x2010: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(12) +case 0x2290: +case 0x2490: +case 0x2690: +case 0x2890: +case 0x2A90: +case 0x2C90: +case 0x2E90: +case 0x2091: +case 0x2291: +case 0x2491: +case 0x2691: +case 0x2891: +case 0x2A91: +case 0x2C91: +case 0x2E91: +case 0x2092: +case 0x2292: +case 0x2492: +case 0x2692: +case 0x2892: +case 0x2A92: +case 0x2C92: +case 0x2E92: +case 0x2093: +case 0x2293: +case 0x2493: +case 0x2693: +case 0x2893: +case 0x2A93: +case 0x2C93: +case 0x2E93: +case 0x2094: +case 0x2294: +case 0x2494: +case 0x2694: +case 0x2894: +case 0x2A94: +case 0x2C94: +case 0x2E94: +case 0x2095: +case 0x2295: +case 0x2495: +case 0x2695: +case 0x2895: +case 0x2A95: +case 0x2C95: +case 0x2E95: +case 0x2096: +case 0x2296: +case 0x2496: +case 0x2696: +case 0x2896: +case 0x2A96: +case 0x2C96: +case 0x2E96: +case 0x2097: +case 0x2297: +case 0x2497: +case 0x2697: +case 0x2897: +case 0x2A97: +case 0x2C97: +case 0x2E97: + +// MOVEL +case 0x2090: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7]; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(20) +case 0x22D0: +case 0x24D0: +case 0x26D0: +case 0x28D0: +case 0x2AD0: +case 0x2CD0: +case 0x20D1: +case 0x22D1: +case 0x24D1: +case 0x26D1: +case 0x28D1: +case 0x2AD1: +case 0x2CD1: +case 0x20D2: +case 0x22D2: +case 0x24D2: +case 0x26D2: +case 0x28D2: +case 0x2AD2: +case 0x2CD2: +case 0x20D3: +case 0x22D3: +case 0x24D3: +case 0x26D3: +case 0x28D3: +case 0x2AD3: +case 0x2CD3: +case 0x20D4: +case 0x22D4: +case 0x24D4: +case 0x26D4: +case 0x28D4: +case 0x2AD4: +case 0x2CD4: +case 0x20D5: +case 0x22D5: +case 0x24D5: +case 0x26D5: +case 0x28D5: +case 0x2AD5: +case 0x2CD5: +case 0x20D6: +case 0x22D6: +case 0x24D6: +case 0x26D6: +case 0x28D6: +case 0x2AD6: +case 0x2CD6: +case 0x20D7: +case 0x22D7: +case 0x24D7: +case 0x26D7: +case 0x28D7: +case 0x2AD7: +case 0x2CD7: + +// MOVEL +case 0x20D0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7]; + CPU->A[(Opcode >> 9) & 7] += 4; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(20) +case 0x2310: +case 0x2510: +case 0x2710: +case 0x2910: +case 0x2B10: +case 0x2D10: +case 0x2111: +case 0x2311: +case 0x2511: +case 0x2711: +case 0x2911: +case 0x2B11: +case 0x2D11: +case 0x2112: +case 0x2312: +case 0x2512: +case 0x2712: +case 0x2912: +case 0x2B12: +case 0x2D12: +case 0x2113: +case 0x2313: +case 0x2513: +case 0x2713: +case 0x2913: +case 0x2B13: +case 0x2D13: +case 0x2114: +case 0x2314: +case 0x2514: +case 0x2714: +case 0x2914: +case 0x2B14: +case 0x2D14: +case 0x2115: +case 0x2315: +case 0x2515: +case 0x2715: +case 0x2915: +case 0x2B15: +case 0x2D15: +case 0x2116: +case 0x2316: +case 0x2516: +case 0x2716: +case 0x2916: +case 0x2B16: +case 0x2D16: +case 0x2117: +case 0x2317: +case 0x2517: +case 0x2717: +case 0x2917: +case 0x2B17: +case 0x2D17: + +// MOVEL +case 0x2110: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7] - 4; + CPU->A[(Opcode >> 9) & 7] = adr; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(20) +case 0x2350: +case 0x2550: +case 0x2750: +case 0x2950: +case 0x2B50: +case 0x2D50: +case 0x2F50: +case 0x2151: +case 0x2351: +case 0x2551: +case 0x2751: +case 0x2951: +case 0x2B51: +case 0x2D51: +case 0x2F51: +case 0x2152: +case 0x2352: +case 0x2552: +case 0x2752: +case 0x2952: +case 0x2B52: +case 0x2D52: +case 0x2F52: +case 0x2153: +case 0x2353: +case 0x2553: +case 0x2753: +case 0x2953: +case 0x2B53: +case 0x2D53: +case 0x2F53: +case 0x2154: +case 0x2354: +case 0x2554: +case 0x2754: +case 0x2954: +case 0x2B54: +case 0x2D54: +case 0x2F54: +case 0x2155: +case 0x2355: +case 0x2555: +case 0x2755: +case 0x2955: +case 0x2B55: +case 0x2D55: +case 0x2F55: +case 0x2156: +case 0x2356: +case 0x2556: +case 0x2756: +case 0x2956: +case 0x2B56: +case 0x2D56: +case 0x2F56: +case 0x2157: +case 0x2357: +case 0x2557: +case 0x2757: +case 0x2957: +case 0x2B57: +case 0x2D57: +case 0x2F57: + +// MOVEL +case 0x2150: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(24) +case 0x2390: +case 0x2590: +case 0x2790: +case 0x2990: +case 0x2B90: +case 0x2D90: +case 0x2F90: +case 0x2191: +case 0x2391: +case 0x2591: +case 0x2791: +case 0x2991: +case 0x2B91: +case 0x2D91: +case 0x2F91: +case 0x2192: +case 0x2392: +case 0x2592: +case 0x2792: +case 0x2992: +case 0x2B92: +case 0x2D92: +case 0x2F92: +case 0x2193: +case 0x2393: +case 0x2593: +case 0x2793: +case 0x2993: +case 0x2B93: +case 0x2D93: +case 0x2F93: +case 0x2194: +case 0x2394: +case 0x2594: +case 0x2794: +case 0x2994: +case 0x2B94: +case 0x2D94: +case 0x2F94: +case 0x2195: +case 0x2395: +case 0x2595: +case 0x2795: +case 0x2995: +case 0x2B95: +case 0x2D95: +case 0x2F95: +case 0x2196: +case 0x2396: +case 0x2596: +case 0x2796: +case 0x2996: +case 0x2B96: +case 0x2D96: +case 0x2F96: +case 0x2197: +case 0x2397: +case 0x2597: +case 0x2797: +case 0x2997: +case 0x2B97: +case 0x2D97: +case 0x2F97: + +// MOVEL +case 0x2190: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7]; + DECODE_EXT_WORD + WRITE_LONG_F(adr, res) + POST_IO +} +RET(26) +case 0x21D1: +case 0x21D2: +case 0x21D3: +case 0x21D4: +case 0x21D5: +case 0x21D6: +case 0x21D7: + +// MOVEL +case 0x21D0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(24) +case 0x23D1: +case 0x23D2: +case 0x23D3: +case 0x23D4: +case 0x23D5: +case 0x23D6: +case 0x23D7: + +// MOVEL +case 0x23D0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = (s32)FETCH_LONG; + PC += 4; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(28) +case 0x2ED1: +case 0x2ED2: +case 0x2ED3: +case 0x2ED4: +case 0x2ED5: +case 0x2ED6: +case 0x2ED7: + +// MOVEL +case 0x2ED0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[7]; + CPU->A[7] += 4; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(20) +case 0x2F11: +case 0x2F12: +case 0x2F13: +case 0x2F14: +case 0x2F15: +case 0x2F16: +case 0x2F17: + +// MOVEL +case 0x2F10: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(20) +case 0x2218: +case 0x2418: +case 0x2618: +case 0x2818: +case 0x2A18: +case 0x2C18: +case 0x2E18: +case 0x2019: +case 0x2219: +case 0x2419: +case 0x2619: +case 0x2819: +case 0x2A19: +case 0x2C19: +case 0x2E19: +case 0x201A: +case 0x221A: +case 0x241A: +case 0x261A: +case 0x281A: +case 0x2A1A: +case 0x2C1A: +case 0x2E1A: +case 0x201B: +case 0x221B: +case 0x241B: +case 0x261B: +case 0x281B: +case 0x2A1B: +case 0x2C1B: +case 0x2E1B: +case 0x201C: +case 0x221C: +case 0x241C: +case 0x261C: +case 0x281C: +case 0x2A1C: +case 0x2C1C: +case 0x2E1C: +case 0x201D: +case 0x221D: +case 0x241D: +case 0x261D: +case 0x281D: +case 0x2A1D: +case 0x2C1D: +case 0x2E1D: +case 0x201E: +case 0x221E: +case 0x241E: +case 0x261E: +case 0x281E: +case 0x2A1E: +case 0x2C1E: +case 0x2E1E: + +// MOVEL +case 0x2018: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 4; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(12) +case 0x2298: +case 0x2498: +case 0x2698: +case 0x2898: +case 0x2A98: +case 0x2C98: +case 0x2E98: +case 0x2099: +case 0x2299: +case 0x2499: +case 0x2699: +case 0x2899: +case 0x2A99: +case 0x2C99: +case 0x2E99: +case 0x209A: +case 0x229A: +case 0x249A: +case 0x269A: +case 0x289A: +case 0x2A9A: +case 0x2C9A: +case 0x2E9A: +case 0x209B: +case 0x229B: +case 0x249B: +case 0x269B: +case 0x289B: +case 0x2A9B: +case 0x2C9B: +case 0x2E9B: +case 0x209C: +case 0x229C: +case 0x249C: +case 0x269C: +case 0x289C: +case 0x2A9C: +case 0x2C9C: +case 0x2E9C: +case 0x209D: +case 0x229D: +case 0x249D: +case 0x269D: +case 0x289D: +case 0x2A9D: +case 0x2C9D: +case 0x2E9D: +case 0x209E: +case 0x229E: +case 0x249E: +case 0x269E: +case 0x289E: +case 0x2A9E: +case 0x2C9E: +case 0x2E9E: + +// MOVEL +case 0x2098: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 4; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7]; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(20) +case 0x22D8: +case 0x24D8: +case 0x26D8: +case 0x28D8: +case 0x2AD8: +case 0x2CD8: +case 0x20D9: +case 0x22D9: +case 0x24D9: +case 0x26D9: +case 0x28D9: +case 0x2AD9: +case 0x2CD9: +case 0x20DA: +case 0x22DA: +case 0x24DA: +case 0x26DA: +case 0x28DA: +case 0x2ADA: +case 0x2CDA: +case 0x20DB: +case 0x22DB: +case 0x24DB: +case 0x26DB: +case 0x28DB: +case 0x2ADB: +case 0x2CDB: +case 0x20DC: +case 0x22DC: +case 0x24DC: +case 0x26DC: +case 0x28DC: +case 0x2ADC: +case 0x2CDC: +case 0x20DD: +case 0x22DD: +case 0x24DD: +case 0x26DD: +case 0x28DD: +case 0x2ADD: +case 0x2CDD: +case 0x20DE: +case 0x22DE: +case 0x24DE: +case 0x26DE: +case 0x28DE: +case 0x2ADE: +case 0x2CDE: + +// MOVEL +case 0x20D8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 4; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7]; + CPU->A[(Opcode >> 9) & 7] += 4; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(20) +case 0x2318: +case 0x2518: +case 0x2718: +case 0x2918: +case 0x2B18: +case 0x2D18: +case 0x2119: +case 0x2319: +case 0x2519: +case 0x2719: +case 0x2919: +case 0x2B19: +case 0x2D19: +case 0x211A: +case 0x231A: +case 0x251A: +case 0x271A: +case 0x291A: +case 0x2B1A: +case 0x2D1A: +case 0x211B: +case 0x231B: +case 0x251B: +case 0x271B: +case 0x291B: +case 0x2B1B: +case 0x2D1B: +case 0x211C: +case 0x231C: +case 0x251C: +case 0x271C: +case 0x291C: +case 0x2B1C: +case 0x2D1C: +case 0x211D: +case 0x231D: +case 0x251D: +case 0x271D: +case 0x291D: +case 0x2B1D: +case 0x2D1D: +case 0x211E: +case 0x231E: +case 0x251E: +case 0x271E: +case 0x291E: +case 0x2B1E: +case 0x2D1E: + +// MOVEL +case 0x2118: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 4; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7] - 4; + CPU->A[(Opcode >> 9) & 7] = adr; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(20) +case 0x2358: +case 0x2558: +case 0x2758: +case 0x2958: +case 0x2B58: +case 0x2D58: +case 0x2F58: +case 0x2159: +case 0x2359: +case 0x2559: +case 0x2759: +case 0x2959: +case 0x2B59: +case 0x2D59: +case 0x2F59: +case 0x215A: +case 0x235A: +case 0x255A: +case 0x275A: +case 0x295A: +case 0x2B5A: +case 0x2D5A: +case 0x2F5A: +case 0x215B: +case 0x235B: +case 0x255B: +case 0x275B: +case 0x295B: +case 0x2B5B: +case 0x2D5B: +case 0x2F5B: +case 0x215C: +case 0x235C: +case 0x255C: +case 0x275C: +case 0x295C: +case 0x2B5C: +case 0x2D5C: +case 0x2F5C: +case 0x215D: +case 0x235D: +case 0x255D: +case 0x275D: +case 0x295D: +case 0x2B5D: +case 0x2D5D: +case 0x2F5D: +case 0x215E: +case 0x235E: +case 0x255E: +case 0x275E: +case 0x295E: +case 0x2B5E: +case 0x2D5E: +case 0x2F5E: + +// MOVEL +case 0x2158: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 4; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(24) +case 0x2398: +case 0x2598: +case 0x2798: +case 0x2998: +case 0x2B98: +case 0x2D98: +case 0x2F98: +case 0x2199: +case 0x2399: +case 0x2599: +case 0x2799: +case 0x2999: +case 0x2B99: +case 0x2D99: +case 0x2F99: +case 0x219A: +case 0x239A: +case 0x259A: +case 0x279A: +case 0x299A: +case 0x2B9A: +case 0x2D9A: +case 0x2F9A: +case 0x219B: +case 0x239B: +case 0x259B: +case 0x279B: +case 0x299B: +case 0x2B9B: +case 0x2D9B: +case 0x2F9B: +case 0x219C: +case 0x239C: +case 0x259C: +case 0x279C: +case 0x299C: +case 0x2B9C: +case 0x2D9C: +case 0x2F9C: +case 0x219D: +case 0x239D: +case 0x259D: +case 0x279D: +case 0x299D: +case 0x2B9D: +case 0x2D9D: +case 0x2F9D: +case 0x219E: +case 0x239E: +case 0x259E: +case 0x279E: +case 0x299E: +case 0x2B9E: +case 0x2D9E: +case 0x2F9E: + +// MOVEL +case 0x2198: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 4; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7]; + DECODE_EXT_WORD + WRITE_LONG_F(adr, res) + POST_IO +} +RET(26) +case 0x21D9: +case 0x21DA: +case 0x21DB: +case 0x21DC: +case 0x21DD: +case 0x21DE: + +// MOVEL +case 0x21D8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 4; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(24) +case 0x23D9: +case 0x23DA: +case 0x23DB: +case 0x23DC: +case 0x23DD: +case 0x23DE: + +// MOVEL +case 0x23D8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 4; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = (s32)FETCH_LONG; + PC += 4; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(28) +case 0x2ED9: +case 0x2EDA: +case 0x2EDB: +case 0x2EDC: +case 0x2EDD: +case 0x2EDE: + +// MOVEL +case 0x2ED8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 4; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[7]; + CPU->A[7] += 4; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(20) +case 0x2F19: +case 0x2F1A: +case 0x2F1B: +case 0x2F1C: +case 0x2F1D: +case 0x2F1E: + +// MOVEL +case 0x2F18: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 4; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(20) +case 0x2220: +case 0x2420: +case 0x2620: +case 0x2820: +case 0x2A20: +case 0x2C20: +case 0x2E20: +case 0x2021: +case 0x2221: +case 0x2421: +case 0x2621: +case 0x2821: +case 0x2A21: +case 0x2C21: +case 0x2E21: +case 0x2022: +case 0x2222: +case 0x2422: +case 0x2622: +case 0x2822: +case 0x2A22: +case 0x2C22: +case 0x2E22: +case 0x2023: +case 0x2223: +case 0x2423: +case 0x2623: +case 0x2823: +case 0x2A23: +case 0x2C23: +case 0x2E23: +case 0x2024: +case 0x2224: +case 0x2424: +case 0x2624: +case 0x2824: +case 0x2A24: +case 0x2C24: +case 0x2E24: +case 0x2025: +case 0x2225: +case 0x2425: +case 0x2625: +case 0x2825: +case 0x2A25: +case 0x2C25: +case 0x2E25: +case 0x2026: +case 0x2226: +case 0x2426: +case 0x2626: +case 0x2826: +case 0x2A26: +case 0x2C26: +case 0x2E26: + +// MOVEL +case 0x2020: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] - 4; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(14) +case 0x22A0: +case 0x24A0: +case 0x26A0: +case 0x28A0: +case 0x2AA0: +case 0x2CA0: +case 0x2EA0: +case 0x20A1: +case 0x22A1: +case 0x24A1: +case 0x26A1: +case 0x28A1: +case 0x2AA1: +case 0x2CA1: +case 0x2EA1: +case 0x20A2: +case 0x22A2: +case 0x24A2: +case 0x26A2: +case 0x28A2: +case 0x2AA2: +case 0x2CA2: +case 0x2EA2: +case 0x20A3: +case 0x22A3: +case 0x24A3: +case 0x26A3: +case 0x28A3: +case 0x2AA3: +case 0x2CA3: +case 0x2EA3: +case 0x20A4: +case 0x22A4: +case 0x24A4: +case 0x26A4: +case 0x28A4: +case 0x2AA4: +case 0x2CA4: +case 0x2EA4: +case 0x20A5: +case 0x22A5: +case 0x24A5: +case 0x26A5: +case 0x28A5: +case 0x2AA5: +case 0x2CA5: +case 0x2EA5: +case 0x20A6: +case 0x22A6: +case 0x24A6: +case 0x26A6: +case 0x28A6: +case 0x2AA6: +case 0x2CA6: +case 0x2EA6: + +// MOVEL +case 0x20A0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] - 4; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7]; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(22) +case 0x22E0: +case 0x24E0: +case 0x26E0: +case 0x28E0: +case 0x2AE0: +case 0x2CE0: +case 0x20E1: +case 0x22E1: +case 0x24E1: +case 0x26E1: +case 0x28E1: +case 0x2AE1: +case 0x2CE1: +case 0x20E2: +case 0x22E2: +case 0x24E2: +case 0x26E2: +case 0x28E2: +case 0x2AE2: +case 0x2CE2: +case 0x20E3: +case 0x22E3: +case 0x24E3: +case 0x26E3: +case 0x28E3: +case 0x2AE3: +case 0x2CE3: +case 0x20E4: +case 0x22E4: +case 0x24E4: +case 0x26E4: +case 0x28E4: +case 0x2AE4: +case 0x2CE4: +case 0x20E5: +case 0x22E5: +case 0x24E5: +case 0x26E5: +case 0x28E5: +case 0x2AE5: +case 0x2CE5: +case 0x20E6: +case 0x22E6: +case 0x24E6: +case 0x26E6: +case 0x28E6: +case 0x2AE6: +case 0x2CE6: + +// MOVEL +case 0x20E0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] - 4; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7]; + CPU->A[(Opcode >> 9) & 7] += 4; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(22) +case 0x2320: +case 0x2520: +case 0x2720: +case 0x2920: +case 0x2B20: +case 0x2D20: +case 0x2121: +case 0x2321: +case 0x2521: +case 0x2721: +case 0x2921: +case 0x2B21: +case 0x2D21: +case 0x2122: +case 0x2322: +case 0x2522: +case 0x2722: +case 0x2922: +case 0x2B22: +case 0x2D22: +case 0x2123: +case 0x2323: +case 0x2523: +case 0x2723: +case 0x2923: +case 0x2B23: +case 0x2D23: +case 0x2124: +case 0x2324: +case 0x2524: +case 0x2724: +case 0x2924: +case 0x2B24: +case 0x2D24: +case 0x2125: +case 0x2325: +case 0x2525: +case 0x2725: +case 0x2925: +case 0x2B25: +case 0x2D25: +case 0x2126: +case 0x2326: +case 0x2526: +case 0x2726: +case 0x2926: +case 0x2B26: +case 0x2D26: + +// MOVEL +case 0x2120: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] - 4; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7] - 4; + CPU->A[(Opcode >> 9) & 7] = adr; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(22) +case 0x2360: +case 0x2560: +case 0x2760: +case 0x2960: +case 0x2B60: +case 0x2D60: +case 0x2F60: +case 0x2161: +case 0x2361: +case 0x2561: +case 0x2761: +case 0x2961: +case 0x2B61: +case 0x2D61: +case 0x2F61: +case 0x2162: +case 0x2362: +case 0x2562: +case 0x2762: +case 0x2962: +case 0x2B62: +case 0x2D62: +case 0x2F62: +case 0x2163: +case 0x2363: +case 0x2563: +case 0x2763: +case 0x2963: +case 0x2B63: +case 0x2D63: +case 0x2F63: +case 0x2164: +case 0x2364: +case 0x2564: +case 0x2764: +case 0x2964: +case 0x2B64: +case 0x2D64: +case 0x2F64: +case 0x2165: +case 0x2365: +case 0x2565: +case 0x2765: +case 0x2965: +case 0x2B65: +case 0x2D65: +case 0x2F65: +case 0x2166: +case 0x2366: +case 0x2566: +case 0x2766: +case 0x2966: +case 0x2B66: +case 0x2D66: +case 0x2F66: + +// MOVEL +case 0x2160: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] - 4; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(26) +case 0x23A0: +case 0x25A0: +case 0x27A0: +case 0x29A0: +case 0x2BA0: +case 0x2DA0: +case 0x2FA0: +case 0x21A1: +case 0x23A1: +case 0x25A1: +case 0x27A1: +case 0x29A1: +case 0x2BA1: +case 0x2DA1: +case 0x2FA1: +case 0x21A2: +case 0x23A2: +case 0x25A2: +case 0x27A2: +case 0x29A2: +case 0x2BA2: +case 0x2DA2: +case 0x2FA2: +case 0x21A3: +case 0x23A3: +case 0x25A3: +case 0x27A3: +case 0x29A3: +case 0x2BA3: +case 0x2DA3: +case 0x2FA3: +case 0x21A4: +case 0x23A4: +case 0x25A4: +case 0x27A4: +case 0x29A4: +case 0x2BA4: +case 0x2DA4: +case 0x2FA4: +case 0x21A5: +case 0x23A5: +case 0x25A5: +case 0x27A5: +case 0x29A5: +case 0x2BA5: +case 0x2DA5: +case 0x2FA5: +case 0x21A6: +case 0x23A6: +case 0x25A6: +case 0x27A6: +case 0x29A6: +case 0x2BA6: +case 0x2DA6: +case 0x2FA6: + +// MOVEL +case 0x21A0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] - 4; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7]; + DECODE_EXT_WORD + WRITE_LONG_F(adr, res) + POST_IO +} +RET(28) +case 0x21E1: +case 0x21E2: +case 0x21E3: +case 0x21E4: +case 0x21E5: +case 0x21E6: + +// MOVEL +case 0x21E0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] - 4; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(26) +case 0x23E1: +case 0x23E2: +case 0x23E3: +case 0x23E4: +case 0x23E5: +case 0x23E6: + +// MOVEL +case 0x23E0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] - 4; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = (s32)FETCH_LONG; + PC += 4; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(30) +case 0x2EE1: +case 0x2EE2: +case 0x2EE3: +case 0x2EE4: +case 0x2EE5: +case 0x2EE6: + +// MOVEL +case 0x2EE0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] - 4; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[7]; + CPU->A[7] += 4; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(22) +case 0x2F21: +case 0x2F22: +case 0x2F23: +case 0x2F24: +case 0x2F25: +case 0x2F26: + +// MOVEL +case 0x2F20: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] - 4; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(22) +case 0x2228: +case 0x2428: +case 0x2628: +case 0x2828: +case 0x2A28: +case 0x2C28: +case 0x2E28: +case 0x2029: +case 0x2229: +case 0x2429: +case 0x2629: +case 0x2829: +case 0x2A29: +case 0x2C29: +case 0x2E29: +case 0x202A: +case 0x222A: +case 0x242A: +case 0x262A: +case 0x282A: +case 0x2A2A: +case 0x2C2A: +case 0x2E2A: +case 0x202B: +case 0x222B: +case 0x242B: +case 0x262B: +case 0x282B: +case 0x2A2B: +case 0x2C2B: +case 0x2E2B: +case 0x202C: +case 0x222C: +case 0x242C: +case 0x262C: +case 0x282C: +case 0x2A2C: +case 0x2C2C: +case 0x2E2C: +case 0x202D: +case 0x222D: +case 0x242D: +case 0x262D: +case 0x282D: +case 0x2A2D: +case 0x2C2D: +case 0x2E2D: +case 0x202E: +case 0x222E: +case 0x242E: +case 0x262E: +case 0x282E: +case 0x2A2E: +case 0x2C2E: +case 0x2E2E: +case 0x202F: +case 0x222F: +case 0x242F: +case 0x262F: +case 0x282F: +case 0x2A2F: +case 0x2C2F: +case 0x2E2F: + +// MOVEL +case 0x2028: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(16) +case 0x22A8: +case 0x24A8: +case 0x26A8: +case 0x28A8: +case 0x2AA8: +case 0x2CA8: +case 0x2EA8: +case 0x20A9: +case 0x22A9: +case 0x24A9: +case 0x26A9: +case 0x28A9: +case 0x2AA9: +case 0x2CA9: +case 0x2EA9: +case 0x20AA: +case 0x22AA: +case 0x24AA: +case 0x26AA: +case 0x28AA: +case 0x2AAA: +case 0x2CAA: +case 0x2EAA: +case 0x20AB: +case 0x22AB: +case 0x24AB: +case 0x26AB: +case 0x28AB: +case 0x2AAB: +case 0x2CAB: +case 0x2EAB: +case 0x20AC: +case 0x22AC: +case 0x24AC: +case 0x26AC: +case 0x28AC: +case 0x2AAC: +case 0x2CAC: +case 0x2EAC: +case 0x20AD: +case 0x22AD: +case 0x24AD: +case 0x26AD: +case 0x28AD: +case 0x2AAD: +case 0x2CAD: +case 0x2EAD: +case 0x20AE: +case 0x22AE: +case 0x24AE: +case 0x26AE: +case 0x28AE: +case 0x2AAE: +case 0x2CAE: +case 0x2EAE: +case 0x20AF: +case 0x22AF: +case 0x24AF: +case 0x26AF: +case 0x28AF: +case 0x2AAF: +case 0x2CAF: +case 0x2EAF: + +// MOVEL +case 0x20A8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7]; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(24) +case 0x22E8: +case 0x24E8: +case 0x26E8: +case 0x28E8: +case 0x2AE8: +case 0x2CE8: +case 0x20E9: +case 0x22E9: +case 0x24E9: +case 0x26E9: +case 0x28E9: +case 0x2AE9: +case 0x2CE9: +case 0x20EA: +case 0x22EA: +case 0x24EA: +case 0x26EA: +case 0x28EA: +case 0x2AEA: +case 0x2CEA: +case 0x20EB: +case 0x22EB: +case 0x24EB: +case 0x26EB: +case 0x28EB: +case 0x2AEB: +case 0x2CEB: +case 0x20EC: +case 0x22EC: +case 0x24EC: +case 0x26EC: +case 0x28EC: +case 0x2AEC: +case 0x2CEC: +case 0x20ED: +case 0x22ED: +case 0x24ED: +case 0x26ED: +case 0x28ED: +case 0x2AED: +case 0x2CED: +case 0x20EE: +case 0x22EE: +case 0x24EE: +case 0x26EE: +case 0x28EE: +case 0x2AEE: +case 0x2CEE: +case 0x20EF: +case 0x22EF: +case 0x24EF: +case 0x26EF: +case 0x28EF: +case 0x2AEF: +case 0x2CEF: + +// MOVEL +case 0x20E8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7]; + CPU->A[(Opcode >> 9) & 7] += 4; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(24) +case 0x2328: +case 0x2528: +case 0x2728: +case 0x2928: +case 0x2B28: +case 0x2D28: +case 0x2129: +case 0x2329: +case 0x2529: +case 0x2729: +case 0x2929: +case 0x2B29: +case 0x2D29: +case 0x212A: +case 0x232A: +case 0x252A: +case 0x272A: +case 0x292A: +case 0x2B2A: +case 0x2D2A: +case 0x212B: +case 0x232B: +case 0x252B: +case 0x272B: +case 0x292B: +case 0x2B2B: +case 0x2D2B: +case 0x212C: +case 0x232C: +case 0x252C: +case 0x272C: +case 0x292C: +case 0x2B2C: +case 0x2D2C: +case 0x212D: +case 0x232D: +case 0x252D: +case 0x272D: +case 0x292D: +case 0x2B2D: +case 0x2D2D: +case 0x212E: +case 0x232E: +case 0x252E: +case 0x272E: +case 0x292E: +case 0x2B2E: +case 0x2D2E: +case 0x212F: +case 0x232F: +case 0x252F: +case 0x272F: +case 0x292F: +case 0x2B2F: +case 0x2D2F: + +// MOVEL +case 0x2128: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7] - 4; + CPU->A[(Opcode >> 9) & 7] = adr; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(24) +case 0x2368: +case 0x2568: +case 0x2768: +case 0x2968: +case 0x2B68: +case 0x2D68: +case 0x2F68: +case 0x2169: +case 0x2369: +case 0x2569: +case 0x2769: +case 0x2969: +case 0x2B69: +case 0x2D69: +case 0x2F69: +case 0x216A: +case 0x236A: +case 0x256A: +case 0x276A: +case 0x296A: +case 0x2B6A: +case 0x2D6A: +case 0x2F6A: +case 0x216B: +case 0x236B: +case 0x256B: +case 0x276B: +case 0x296B: +case 0x2B6B: +case 0x2D6B: +case 0x2F6B: +case 0x216C: +case 0x236C: +case 0x256C: +case 0x276C: +case 0x296C: +case 0x2B6C: +case 0x2D6C: +case 0x2F6C: +case 0x216D: +case 0x236D: +case 0x256D: +case 0x276D: +case 0x296D: +case 0x2B6D: +case 0x2D6D: +case 0x2F6D: +case 0x216E: +case 0x236E: +case 0x256E: +case 0x276E: +case 0x296E: +case 0x2B6E: +case 0x2D6E: +case 0x2F6E: +case 0x216F: +case 0x236F: +case 0x256F: +case 0x276F: +case 0x296F: +case 0x2B6F: +case 0x2D6F: +case 0x2F6F: + +// MOVEL +case 0x2168: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(28) +case 0x23A8: +case 0x25A8: +case 0x27A8: +case 0x29A8: +case 0x2BA8: +case 0x2DA8: +case 0x2FA8: +case 0x21A9: +case 0x23A9: +case 0x25A9: +case 0x27A9: +case 0x29A9: +case 0x2BA9: +case 0x2DA9: +case 0x2FA9: +case 0x21AA: +case 0x23AA: +case 0x25AA: +case 0x27AA: +case 0x29AA: +case 0x2BAA: +case 0x2DAA: +case 0x2FAA: +case 0x21AB: +case 0x23AB: +case 0x25AB: +case 0x27AB: +case 0x29AB: +case 0x2BAB: +case 0x2DAB: +case 0x2FAB: +case 0x21AC: +case 0x23AC: +case 0x25AC: +case 0x27AC: +case 0x29AC: +case 0x2BAC: +case 0x2DAC: +case 0x2FAC: +case 0x21AD: +case 0x23AD: +case 0x25AD: +case 0x27AD: +case 0x29AD: +case 0x2BAD: +case 0x2DAD: +case 0x2FAD: +case 0x21AE: +case 0x23AE: +case 0x25AE: +case 0x27AE: +case 0x29AE: +case 0x2BAE: +case 0x2DAE: +case 0x2FAE: +case 0x21AF: +case 0x23AF: +case 0x25AF: +case 0x27AF: +case 0x29AF: +case 0x2BAF: +case 0x2DAF: +case 0x2FAF: + +// MOVEL +case 0x21A8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7]; + DECODE_EXT_WORD + WRITE_LONG_F(adr, res) + POST_IO +} +RET(30) +case 0x21E9: +case 0x21EA: +case 0x21EB: +case 0x21EC: +case 0x21ED: +case 0x21EE: +case 0x21EF: + +// MOVEL +case 0x21E8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(28) +case 0x23E9: +case 0x23EA: +case 0x23EB: +case 0x23EC: +case 0x23ED: +case 0x23EE: +case 0x23EF: + +// MOVEL +case 0x23E8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = (s32)FETCH_LONG; + PC += 4; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(32) +case 0x2EE9: +case 0x2EEA: +case 0x2EEB: +case 0x2EEC: +case 0x2EED: +case 0x2EEE: +case 0x2EEF: + +// MOVEL +case 0x2EE8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[7]; + CPU->A[7] += 4; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(24) +case 0x2F29: +case 0x2F2A: +case 0x2F2B: +case 0x2F2C: +case 0x2F2D: +case 0x2F2E: +case 0x2F2F: + +// MOVEL +case 0x2F28: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(24) +case 0x2230: +case 0x2430: +case 0x2630: +case 0x2830: +case 0x2A30: +case 0x2C30: +case 0x2E30: +case 0x2031: +case 0x2231: +case 0x2431: +case 0x2631: +case 0x2831: +case 0x2A31: +case 0x2C31: +case 0x2E31: +case 0x2032: +case 0x2232: +case 0x2432: +case 0x2632: +case 0x2832: +case 0x2A32: +case 0x2C32: +case 0x2E32: +case 0x2033: +case 0x2233: +case 0x2433: +case 0x2633: +case 0x2833: +case 0x2A33: +case 0x2C33: +case 0x2E33: +case 0x2034: +case 0x2234: +case 0x2434: +case 0x2634: +case 0x2834: +case 0x2A34: +case 0x2C34: +case 0x2E34: +case 0x2035: +case 0x2235: +case 0x2435: +case 0x2635: +case 0x2835: +case 0x2A35: +case 0x2C35: +case 0x2E35: +case 0x2036: +case 0x2236: +case 0x2436: +case 0x2636: +case 0x2836: +case 0x2A36: +case 0x2C36: +case 0x2E36: +case 0x2037: +case 0x2237: +case 0x2437: +case 0x2637: +case 0x2837: +case 0x2A37: +case 0x2C37: +case 0x2E37: + +// MOVEL +case 0x2030: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(18) +case 0x22B0: +case 0x24B0: +case 0x26B0: +case 0x28B0: +case 0x2AB0: +case 0x2CB0: +case 0x2EB0: +case 0x20B1: +case 0x22B1: +case 0x24B1: +case 0x26B1: +case 0x28B1: +case 0x2AB1: +case 0x2CB1: +case 0x2EB1: +case 0x20B2: +case 0x22B2: +case 0x24B2: +case 0x26B2: +case 0x28B2: +case 0x2AB2: +case 0x2CB2: +case 0x2EB2: +case 0x20B3: +case 0x22B3: +case 0x24B3: +case 0x26B3: +case 0x28B3: +case 0x2AB3: +case 0x2CB3: +case 0x2EB3: +case 0x20B4: +case 0x22B4: +case 0x24B4: +case 0x26B4: +case 0x28B4: +case 0x2AB4: +case 0x2CB4: +case 0x2EB4: +case 0x20B5: +case 0x22B5: +case 0x24B5: +case 0x26B5: +case 0x28B5: +case 0x2AB5: +case 0x2CB5: +case 0x2EB5: +case 0x20B6: +case 0x22B6: +case 0x24B6: +case 0x26B6: +case 0x28B6: +case 0x2AB6: +case 0x2CB6: +case 0x2EB6: +case 0x20B7: +case 0x22B7: +case 0x24B7: +case 0x26B7: +case 0x28B7: +case 0x2AB7: +case 0x2CB7: +case 0x2EB7: + +// MOVEL +case 0x20B0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7]; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(26) +case 0x22F0: +case 0x24F0: +case 0x26F0: +case 0x28F0: +case 0x2AF0: +case 0x2CF0: +case 0x20F1: +case 0x22F1: +case 0x24F1: +case 0x26F1: +case 0x28F1: +case 0x2AF1: +case 0x2CF1: +case 0x20F2: +case 0x22F2: +case 0x24F2: +case 0x26F2: +case 0x28F2: +case 0x2AF2: +case 0x2CF2: +case 0x20F3: +case 0x22F3: +case 0x24F3: +case 0x26F3: +case 0x28F3: +case 0x2AF3: +case 0x2CF3: +case 0x20F4: +case 0x22F4: +case 0x24F4: +case 0x26F4: +case 0x28F4: +case 0x2AF4: +case 0x2CF4: +case 0x20F5: +case 0x22F5: +case 0x24F5: +case 0x26F5: +case 0x28F5: +case 0x2AF5: +case 0x2CF5: +case 0x20F6: +case 0x22F6: +case 0x24F6: +case 0x26F6: +case 0x28F6: +case 0x2AF6: +case 0x2CF6: +case 0x20F7: +case 0x22F7: +case 0x24F7: +case 0x26F7: +case 0x28F7: +case 0x2AF7: +case 0x2CF7: + +// MOVEL +case 0x20F0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7]; + CPU->A[(Opcode >> 9) & 7] += 4; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(26) +case 0x2330: +case 0x2530: +case 0x2730: +case 0x2930: +case 0x2B30: +case 0x2D30: +case 0x2131: +case 0x2331: +case 0x2531: +case 0x2731: +case 0x2931: +case 0x2B31: +case 0x2D31: +case 0x2132: +case 0x2332: +case 0x2532: +case 0x2732: +case 0x2932: +case 0x2B32: +case 0x2D32: +case 0x2133: +case 0x2333: +case 0x2533: +case 0x2733: +case 0x2933: +case 0x2B33: +case 0x2D33: +case 0x2134: +case 0x2334: +case 0x2534: +case 0x2734: +case 0x2934: +case 0x2B34: +case 0x2D34: +case 0x2135: +case 0x2335: +case 0x2535: +case 0x2735: +case 0x2935: +case 0x2B35: +case 0x2D35: +case 0x2136: +case 0x2336: +case 0x2536: +case 0x2736: +case 0x2936: +case 0x2B36: +case 0x2D36: +case 0x2137: +case 0x2337: +case 0x2537: +case 0x2737: +case 0x2937: +case 0x2B37: +case 0x2D37: + +// MOVEL +case 0x2130: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7] - 4; + CPU->A[(Opcode >> 9) & 7] = adr; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(26) +case 0x2370: +case 0x2570: +case 0x2770: +case 0x2970: +case 0x2B70: +case 0x2D70: +case 0x2F70: +case 0x2171: +case 0x2371: +case 0x2571: +case 0x2771: +case 0x2971: +case 0x2B71: +case 0x2D71: +case 0x2F71: +case 0x2172: +case 0x2372: +case 0x2572: +case 0x2772: +case 0x2972: +case 0x2B72: +case 0x2D72: +case 0x2F72: +case 0x2173: +case 0x2373: +case 0x2573: +case 0x2773: +case 0x2973: +case 0x2B73: +case 0x2D73: +case 0x2F73: +case 0x2174: +case 0x2374: +case 0x2574: +case 0x2774: +case 0x2974: +case 0x2B74: +case 0x2D74: +case 0x2F74: +case 0x2175: +case 0x2375: +case 0x2575: +case 0x2775: +case 0x2975: +case 0x2B75: +case 0x2D75: +case 0x2F75: +case 0x2176: +case 0x2376: +case 0x2576: +case 0x2776: +case 0x2976: +case 0x2B76: +case 0x2D76: +case 0x2F76: +case 0x2177: +case 0x2377: +case 0x2577: +case 0x2777: +case 0x2977: +case 0x2B77: +case 0x2D77: +case 0x2F77: + +// MOVEL +case 0x2170: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(30) +case 0x23B0: +case 0x25B0: +case 0x27B0: +case 0x29B0: +case 0x2BB0: +case 0x2DB0: +case 0x2FB0: +case 0x21B1: +case 0x23B1: +case 0x25B1: +case 0x27B1: +case 0x29B1: +case 0x2BB1: +case 0x2DB1: +case 0x2FB1: +case 0x21B2: +case 0x23B2: +case 0x25B2: +case 0x27B2: +case 0x29B2: +case 0x2BB2: +case 0x2DB2: +case 0x2FB2: +case 0x21B3: +case 0x23B3: +case 0x25B3: +case 0x27B3: +case 0x29B3: +case 0x2BB3: +case 0x2DB3: +case 0x2FB3: +case 0x21B4: +case 0x23B4: +case 0x25B4: +case 0x27B4: +case 0x29B4: +case 0x2BB4: +case 0x2DB4: +case 0x2FB4: +case 0x21B5: +case 0x23B5: +case 0x25B5: +case 0x27B5: +case 0x29B5: +case 0x2BB5: +case 0x2DB5: +case 0x2FB5: +case 0x21B6: +case 0x23B6: +case 0x25B6: +case 0x27B6: +case 0x29B6: +case 0x2BB6: +case 0x2DB6: +case 0x2FB6: +case 0x21B7: +case 0x23B7: +case 0x25B7: +case 0x27B7: +case 0x29B7: +case 0x2BB7: +case 0x2DB7: +case 0x2FB7: + +// MOVEL +case 0x21B0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7]; + DECODE_EXT_WORD + WRITE_LONG_F(adr, res) + POST_IO +} +RET(32) +case 0x21F1: +case 0x21F2: +case 0x21F3: +case 0x21F4: +case 0x21F5: +case 0x21F6: +case 0x21F7: + +// MOVEL +case 0x21F0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(30) +case 0x23F1: +case 0x23F2: +case 0x23F3: +case 0x23F4: +case 0x23F5: +case 0x23F6: +case 0x23F7: + +// MOVEL +case 0x23F0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = (s32)FETCH_LONG; + PC += 4; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(34) +case 0x2EF1: +case 0x2EF2: +case 0x2EF3: +case 0x2EF4: +case 0x2EF5: +case 0x2EF6: +case 0x2EF7: + +// MOVEL +case 0x2EF0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[7]; + CPU->A[7] += 4; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(26) +case 0x2F31: +case 0x2F32: +case 0x2F33: +case 0x2F34: +case 0x2F35: +case 0x2F36: +case 0x2F37: + +// MOVEL +case 0x2F30: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(26) +case 0x2238: +case 0x2438: +case 0x2638: +case 0x2838: +case 0x2A38: +case 0x2C38: +case 0x2E38: + +// MOVEL +case 0x2038: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(16) +case 0x22B8: +case 0x24B8: +case 0x26B8: +case 0x28B8: +case 0x2AB8: +case 0x2CB8: +case 0x2EB8: + +// MOVEL +case 0x20B8: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7]; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(24) +case 0x22F8: +case 0x24F8: +case 0x26F8: +case 0x28F8: +case 0x2AF8: +case 0x2CF8: + +// MOVEL +case 0x20F8: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7]; + CPU->A[(Opcode >> 9) & 7] += 4; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(24) +case 0x2338: +case 0x2538: +case 0x2738: +case 0x2938: +case 0x2B38: +case 0x2D38: + +// MOVEL +case 0x2138: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7] - 4; + CPU->A[(Opcode >> 9) & 7] = adr; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(24) +case 0x2378: +case 0x2578: +case 0x2778: +case 0x2978: +case 0x2B78: +case 0x2D78: +case 0x2F78: + +// MOVEL +case 0x2178: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(28) +case 0x23B8: +case 0x25B8: +case 0x27B8: +case 0x29B8: +case 0x2BB8: +case 0x2DB8: +case 0x2FB8: + +// MOVEL +case 0x21B8: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7]; + DECODE_EXT_WORD + WRITE_LONG_F(adr, res) + POST_IO +} +RET(30) + +// MOVEL +case 0x21F8: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(28) + +// MOVEL +case 0x23F8: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = (s32)FETCH_LONG; + PC += 4; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(32) + +// MOVEL +case 0x2EF8: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[7]; + CPU->A[7] += 4; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(24) + +// MOVEL +case 0x2F38: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(24) +case 0x2239: +case 0x2439: +case 0x2639: +case 0x2839: +case 0x2A39: +case 0x2C39: +case 0x2E39: + +// MOVEL +case 0x2039: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(20) +case 0x22B9: +case 0x24B9: +case 0x26B9: +case 0x28B9: +case 0x2AB9: +case 0x2CB9: +case 0x2EB9: + +// MOVEL +case 0x20B9: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7]; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(28) +case 0x22F9: +case 0x24F9: +case 0x26F9: +case 0x28F9: +case 0x2AF9: +case 0x2CF9: + +// MOVEL +case 0x20F9: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7]; + CPU->A[(Opcode >> 9) & 7] += 4; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(28) +case 0x2339: +case 0x2539: +case 0x2739: +case 0x2939: +case 0x2B39: +case 0x2D39: + +// MOVEL +case 0x2139: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7] - 4; + CPU->A[(Opcode >> 9) & 7] = adr; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(28) +case 0x2379: +case 0x2579: +case 0x2779: +case 0x2979: +case 0x2B79: +case 0x2D79: +case 0x2F79: + +// MOVEL +case 0x2179: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(32) +case 0x23B9: +case 0x25B9: +case 0x27B9: +case 0x29B9: +case 0x2BB9: +case 0x2DB9: +case 0x2FB9: + +// MOVEL +case 0x21B9: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7]; + DECODE_EXT_WORD + WRITE_LONG_F(adr, res) + POST_IO +} +RET(34) + +// MOVEL +case 0x21F9: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(32) + +// MOVEL +case 0x23F9: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = (s32)FETCH_LONG; + PC += 4; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(36) + +// MOVEL +case 0x2EF9: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[7]; + CPU->A[7] += 4; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(28) + +// MOVEL +case 0x2F39: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(28) +case 0x223A: +case 0x243A: +case 0x263A: +case 0x283A: +case 0x2A3A: +case 0x2C3A: +case 0x2E3A: + +// MOVEL +case 0x203A: +{ + u32 adr; + u32 res; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(16) +case 0x22BA: +case 0x24BA: +case 0x26BA: +case 0x28BA: +case 0x2ABA: +case 0x2CBA: +case 0x2EBA: + +// MOVEL +case 0x20BA: +{ + u32 adr; + u32 res; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7]; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(24) +case 0x22FA: +case 0x24FA: +case 0x26FA: +case 0x28FA: +case 0x2AFA: +case 0x2CFA: + +// MOVEL +case 0x20FA: +{ + u32 adr; + u32 res; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7]; + CPU->A[(Opcode >> 9) & 7] += 4; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(24) +case 0x233A: +case 0x253A: +case 0x273A: +case 0x293A: +case 0x2B3A: +case 0x2D3A: + +// MOVEL +case 0x213A: +{ + u32 adr; + u32 res; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7] - 4; + CPU->A[(Opcode >> 9) & 7] = adr; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(24) +case 0x237A: +case 0x257A: +case 0x277A: +case 0x297A: +case 0x2B7A: +case 0x2D7A: +case 0x2F7A: + +// MOVEL +case 0x217A: +{ + u32 adr; + u32 res; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(28) +case 0x23BA: +case 0x25BA: +case 0x27BA: +case 0x29BA: +case 0x2BBA: +case 0x2DBA: +case 0x2FBA: + +// MOVEL +case 0x21BA: +{ + u32 adr; + u32 res; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7]; + DECODE_EXT_WORD + WRITE_LONG_F(adr, res) + POST_IO +} +RET(30) + +// MOVEL +case 0x21FA: +{ + u32 adr; + u32 res; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(28) + +// MOVEL +case 0x23FA: +{ + u32 adr; + u32 res; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = (s32)FETCH_LONG; + PC += 4; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(32) + +// MOVEL +case 0x2EFA: +{ + u32 adr; + u32 res; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[7]; + CPU->A[7] += 4; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(24) + +// MOVEL +case 0x2F3A: +{ + u32 adr; + u32 res; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(24) +case 0x223B: +case 0x243B: +case 0x263B: +case 0x283B: +case 0x2A3B: +case 0x2C3B: +case 0x2E3B: + +// MOVEL +case 0x203B: +{ + u32 adr; + u32 res; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(18) +case 0x22BB: +case 0x24BB: +case 0x26BB: +case 0x28BB: +case 0x2ABB: +case 0x2CBB: +case 0x2EBB: + +// MOVEL +case 0x20BB: +{ + u32 adr; + u32 res; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7]; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(26) +case 0x22FB: +case 0x24FB: +case 0x26FB: +case 0x28FB: +case 0x2AFB: +case 0x2CFB: + +// MOVEL +case 0x20FB: +{ + u32 adr; + u32 res; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7]; + CPU->A[(Opcode >> 9) & 7] += 4; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(26) +case 0x233B: +case 0x253B: +case 0x273B: +case 0x293B: +case 0x2B3B: +case 0x2D3B: + +// MOVEL +case 0x213B: +{ + u32 adr; + u32 res; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7] - 4; + CPU->A[(Opcode >> 9) & 7] = adr; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(26) +case 0x237B: +case 0x257B: +case 0x277B: +case 0x297B: +case 0x2B7B: +case 0x2D7B: +case 0x2F7B: + +// MOVEL +case 0x217B: +{ + u32 adr; + u32 res; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(30) +case 0x23BB: +case 0x25BB: +case 0x27BB: +case 0x29BB: +case 0x2BBB: +case 0x2DBB: +case 0x2FBB: + +// MOVEL +case 0x21BB: +{ + u32 adr; + u32 res; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7]; + DECODE_EXT_WORD + WRITE_LONG_F(adr, res) + POST_IO +} +RET(32) + +// MOVEL +case 0x21FB: +{ + u32 adr; + u32 res; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(30) + +// MOVEL +case 0x23FB: +{ + u32 adr; + u32 res; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = (s32)FETCH_LONG; + PC += 4; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(34) + +// MOVEL +case 0x2EFB: +{ + u32 adr; + u32 res; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[7]; + CPU->A[7] += 4; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(26) + +// MOVEL +case 0x2F3B: +{ + u32 adr; + u32 res; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(26) +case 0x223C: +case 0x243C: +case 0x263C: +case 0x283C: +case 0x2A3C: +case 0x2C3C: +case 0x2E3C: + +// MOVEL +case 0x203C: +{ + u32 res; + res = FETCH_LONG; + PC += 4; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; +} +RET(12) +case 0x22BC: +case 0x24BC: +case 0x26BC: +case 0x28BC: +case 0x2ABC: +case 0x2CBC: +case 0x2EBC: + +// MOVEL +case 0x20BC: +{ + u32 adr; + u32 res; + res = FETCH_LONG; + PC += 4; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7]; + PRE_IO + WRITE_LONG_F(adr, res) + POST_IO +} +RET(20) +case 0x22FC: +case 0x24FC: +case 0x26FC: +case 0x28FC: +case 0x2AFC: +case 0x2CFC: + +// MOVEL +case 0x20FC: +{ + u32 adr; + u32 res; + res = FETCH_LONG; + PC += 4; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7]; + CPU->A[(Opcode >> 9) & 7] += 4; + PRE_IO + WRITE_LONG_F(adr, res) + POST_IO +} +RET(20) +case 0x233C: +case 0x253C: +case 0x273C: +case 0x293C: +case 0x2B3C: +case 0x2D3C: + +// MOVEL +case 0x213C: +{ + u32 adr; + u32 res; + res = FETCH_LONG; + PC += 4; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7] - 4; + CPU->A[(Opcode >> 9) & 7] = adr; + PRE_IO + WRITE_LONG_F(adr, res) + POST_IO +} +RET(20) +case 0x237C: +case 0x257C: +case 0x277C: +case 0x297C: +case 0x2B7C: +case 0x2D7C: +case 0x2F7C: + +// MOVEL +case 0x217C: +{ + u32 adr; + u32 res; + res = FETCH_LONG; + PC += 4; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + WRITE_LONG_F(adr, res) + POST_IO +} +RET(24) +case 0x23BC: +case 0x25BC: +case 0x27BC: +case 0x29BC: +case 0x2BBC: +case 0x2DBC: +case 0x2FBC: + +// MOVEL +case 0x21BC: +{ + u32 adr; + u32 res; + res = FETCH_LONG; + PC += 4; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7]; + DECODE_EXT_WORD + PRE_IO + WRITE_LONG_F(adr, res) + POST_IO +} +RET(26) + +// MOVEL +case 0x21FC: +{ + u32 adr; + u32 res; + res = FETCH_LONG; + PC += 4; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + WRITE_LONG_F(adr, res) + POST_IO +} +RET(24) + +// MOVEL +case 0x23FC: +{ + u32 adr; + u32 res; + res = FETCH_LONG; + PC += 4; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + WRITE_LONG_F(adr, res) + POST_IO +} +RET(28) + +// MOVEL +case 0x2EFC: +{ + u32 adr; + u32 res; + res = FETCH_LONG; + PC += 4; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[7]; + CPU->A[7] += 4; + PRE_IO + WRITE_LONG_F(adr, res) + POST_IO +} +RET(20) + +// MOVEL +case 0x2F3C: +{ + u32 adr; + u32 res; + res = FETCH_LONG; + PC += 4; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + PRE_IO + WRITE_LONG_F(adr, res) + POST_IO +} +RET(20) +case 0x221F: +case 0x241F: +case 0x261F: +case 0x281F: +case 0x2A1F: +case 0x2C1F: +case 0x2E1F: + +// MOVEL +case 0x201F: +{ + u32 adr; + u32 res; + adr = CPU->A[7]; + CPU->A[7] += 4; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(12) +case 0x229F: +case 0x249F: +case 0x269F: +case 0x289F: +case 0x2A9F: +case 0x2C9F: +case 0x2E9F: + +// MOVEL +case 0x209F: +{ + u32 adr; + u32 res; + adr = CPU->A[7]; + CPU->A[7] += 4; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7]; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(20) +case 0x22DF: +case 0x24DF: +case 0x26DF: +case 0x28DF: +case 0x2ADF: +case 0x2CDF: + +// MOVEL +case 0x20DF: +{ + u32 adr; + u32 res; + adr = CPU->A[7]; + CPU->A[7] += 4; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7]; + CPU->A[(Opcode >> 9) & 7] += 4; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(20) +case 0x231F: +case 0x251F: +case 0x271F: +case 0x291F: +case 0x2B1F: +case 0x2D1F: + +// MOVEL +case 0x211F: +{ + u32 adr; + u32 res; + adr = CPU->A[7]; + CPU->A[7] += 4; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7] - 4; + CPU->A[(Opcode >> 9) & 7] = adr; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(20) +case 0x235F: +case 0x255F: +case 0x275F: +case 0x295F: +case 0x2B5F: +case 0x2D5F: +case 0x2F5F: + +// MOVEL +case 0x215F: +{ + u32 adr; + u32 res; + adr = CPU->A[7]; + CPU->A[7] += 4; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(24) +case 0x239F: +case 0x259F: +case 0x279F: +case 0x299F: +case 0x2B9F: +case 0x2D9F: +case 0x2F9F: + +// MOVEL +case 0x219F: +{ + u32 adr; + u32 res; + adr = CPU->A[7]; + CPU->A[7] += 4; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7]; + DECODE_EXT_WORD + WRITE_LONG_F(adr, res) + POST_IO +} +RET(26) + +// MOVEL +case 0x21DF: +{ + u32 adr; + u32 res; + adr = CPU->A[7]; + CPU->A[7] += 4; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(24) + +// MOVEL +case 0x23DF: +{ + u32 adr; + u32 res; + adr = CPU->A[7]; + CPU->A[7] += 4; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = (s32)FETCH_LONG; + PC += 4; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(28) + +// MOVEL +case 0x2EDF: +{ + u32 adr; + u32 res; + adr = CPU->A[7]; + CPU->A[7] += 4; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[7]; + CPU->A[7] += 4; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(20) + +// MOVEL +case 0x2F1F: +{ + u32 adr; + u32 res; + adr = CPU->A[7]; + CPU->A[7] += 4; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(20) +case 0x2227: +case 0x2427: +case 0x2627: +case 0x2827: +case 0x2A27: +case 0x2C27: +case 0x2E27: + +// MOVEL +case 0x2027: +{ + u32 adr; + u32 res; + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(14) +case 0x22A7: +case 0x24A7: +case 0x26A7: +case 0x28A7: +case 0x2AA7: +case 0x2CA7: +case 0x2EA7: + +// MOVEL +case 0x20A7: +{ + u32 adr; + u32 res; + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7]; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(22) +case 0x22E7: +case 0x24E7: +case 0x26E7: +case 0x28E7: +case 0x2AE7: +case 0x2CE7: + +// MOVEL +case 0x20E7: +{ + u32 adr; + u32 res; + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7]; + CPU->A[(Opcode >> 9) & 7] += 4; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(22) +case 0x2327: +case 0x2527: +case 0x2727: +case 0x2927: +case 0x2B27: +case 0x2D27: + +// MOVEL +case 0x2127: +{ + u32 adr; + u32 res; + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7] - 4; + CPU->A[(Opcode >> 9) & 7] = adr; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(22) +case 0x2367: +case 0x2567: +case 0x2767: +case 0x2967: +case 0x2B67: +case 0x2D67: +case 0x2F67: + +// MOVEL +case 0x2167: +{ + u32 adr; + u32 res; + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(26) +case 0x23A7: +case 0x25A7: +case 0x27A7: +case 0x29A7: +case 0x2BA7: +case 0x2DA7: +case 0x2FA7: + +// MOVEL +case 0x21A7: +{ + u32 adr; + u32 res; + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[(Opcode >> 9) & 7]; + DECODE_EXT_WORD + WRITE_LONG_F(adr, res) + POST_IO +} +RET(28) + +// MOVEL +case 0x21E7: +{ + u32 adr; + u32 res; + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(26) + +// MOVEL +case 0x23E7: +{ + u32 adr; + u32 res; + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = (s32)FETCH_LONG; + PC += 4; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(30) + +// MOVEL +case 0x2EE7: +{ + u32 adr; + u32 res; + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[7]; + CPU->A[7] += 4; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(22) + +// MOVEL +case 0x2F27: +{ + u32 adr; + u32 res; + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(22) +case 0x2240: +case 0x2440: +case 0x2640: +case 0x2840: +case 0x2A40: +case 0x2C40: +case 0x2E40: +case 0x2041: +case 0x2241: +case 0x2441: +case 0x2641: +case 0x2841: +case 0x2A41: +case 0x2C41: +case 0x2E41: +case 0x2042: +case 0x2242: +case 0x2442: +case 0x2642: +case 0x2842: +case 0x2A42: +case 0x2C42: +case 0x2E42: +case 0x2043: +case 0x2243: +case 0x2443: +case 0x2643: +case 0x2843: +case 0x2A43: +case 0x2C43: +case 0x2E43: +case 0x2044: +case 0x2244: +case 0x2444: +case 0x2644: +case 0x2844: +case 0x2A44: +case 0x2C44: +case 0x2E44: +case 0x2045: +case 0x2245: +case 0x2445: +case 0x2645: +case 0x2845: +case 0x2A45: +case 0x2C45: +case 0x2E45: +case 0x2046: +case 0x2246: +case 0x2446: +case 0x2646: +case 0x2846: +case 0x2A46: +case 0x2C46: +case 0x2E46: +case 0x2047: +case 0x2247: +case 0x2447: +case 0x2647: +case 0x2847: +case 0x2A47: +case 0x2C47: +case 0x2E47: + +// MOVEAL +case 0x2040: +{ + u32 res; + res = (s32)(s32)CPU->D[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 9) & 7] = res; +} +RET(4) +case 0x2248: +case 0x2448: +case 0x2648: +case 0x2848: +case 0x2A48: +case 0x2C48: +case 0x2E48: +case 0x2049: +case 0x2249: +case 0x2449: +case 0x2649: +case 0x2849: +case 0x2A49: +case 0x2C49: +case 0x2E49: +case 0x204A: +case 0x224A: +case 0x244A: +case 0x264A: +case 0x284A: +case 0x2A4A: +case 0x2C4A: +case 0x2E4A: +case 0x204B: +case 0x224B: +case 0x244B: +case 0x264B: +case 0x284B: +case 0x2A4B: +case 0x2C4B: +case 0x2E4B: +case 0x204C: +case 0x224C: +case 0x244C: +case 0x264C: +case 0x284C: +case 0x2A4C: +case 0x2C4C: +case 0x2E4C: +case 0x204D: +case 0x224D: +case 0x244D: +case 0x264D: +case 0x284D: +case 0x2A4D: +case 0x2C4D: +case 0x2E4D: +case 0x204E: +case 0x224E: +case 0x244E: +case 0x264E: +case 0x284E: +case 0x2A4E: +case 0x2C4E: +case 0x2E4E: +case 0x204F: +case 0x224F: +case 0x244F: +case 0x264F: +case 0x284F: +case 0x2A4F: +case 0x2C4F: +case 0x2E4F: + +// MOVEAL +case 0x2048: +{ + u32 res; + res = (s32)(s32)CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 9) & 7] = res; +} +RET(4) +case 0x2250: +case 0x2450: +case 0x2650: +case 0x2850: +case 0x2A50: +case 0x2C50: +case 0x2E50: +case 0x2051: +case 0x2251: +case 0x2451: +case 0x2651: +case 0x2851: +case 0x2A51: +case 0x2C51: +case 0x2E51: +case 0x2052: +case 0x2252: +case 0x2452: +case 0x2652: +case 0x2852: +case 0x2A52: +case 0x2C52: +case 0x2E52: +case 0x2053: +case 0x2253: +case 0x2453: +case 0x2653: +case 0x2853: +case 0x2A53: +case 0x2C53: +case 0x2E53: +case 0x2054: +case 0x2254: +case 0x2454: +case 0x2654: +case 0x2854: +case 0x2A54: +case 0x2C54: +case 0x2E54: +case 0x2055: +case 0x2255: +case 0x2455: +case 0x2655: +case 0x2855: +case 0x2A55: +case 0x2C55: +case 0x2E55: +case 0x2056: +case 0x2256: +case 0x2456: +case 0x2656: +case 0x2856: +case 0x2A56: +case 0x2C56: +case 0x2E56: +case 0x2057: +case 0x2257: +case 0x2457: +case 0x2657: +case 0x2857: +case 0x2A57: +case 0x2C57: +case 0x2E57: + +// MOVEAL +case 0x2050: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READSX_LONG_F(adr, res) + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(12) +case 0x2258: +case 0x2458: +case 0x2658: +case 0x2858: +case 0x2A58: +case 0x2C58: +case 0x2E58: +case 0x2059: +case 0x2259: +case 0x2459: +case 0x2659: +case 0x2859: +case 0x2A59: +case 0x2C59: +case 0x2E59: +case 0x205A: +case 0x225A: +case 0x245A: +case 0x265A: +case 0x285A: +case 0x2A5A: +case 0x2C5A: +case 0x2E5A: +case 0x205B: +case 0x225B: +case 0x245B: +case 0x265B: +case 0x285B: +case 0x2A5B: +case 0x2C5B: +case 0x2E5B: +case 0x205C: +case 0x225C: +case 0x245C: +case 0x265C: +case 0x285C: +case 0x2A5C: +case 0x2C5C: +case 0x2E5C: +case 0x205D: +case 0x225D: +case 0x245D: +case 0x265D: +case 0x285D: +case 0x2A5D: +case 0x2C5D: +case 0x2E5D: +case 0x205E: +case 0x225E: +case 0x245E: +case 0x265E: +case 0x285E: +case 0x2A5E: +case 0x2C5E: +case 0x2E5E: + +// MOVEAL +case 0x2058: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 4; + PRE_IO + READSX_LONG_F(adr, res) + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(12) +case 0x2260: +case 0x2460: +case 0x2660: +case 0x2860: +case 0x2A60: +case 0x2C60: +case 0x2E60: +case 0x2061: +case 0x2261: +case 0x2461: +case 0x2661: +case 0x2861: +case 0x2A61: +case 0x2C61: +case 0x2E61: +case 0x2062: +case 0x2262: +case 0x2462: +case 0x2662: +case 0x2862: +case 0x2A62: +case 0x2C62: +case 0x2E62: +case 0x2063: +case 0x2263: +case 0x2463: +case 0x2663: +case 0x2863: +case 0x2A63: +case 0x2C63: +case 0x2E63: +case 0x2064: +case 0x2264: +case 0x2464: +case 0x2664: +case 0x2864: +case 0x2A64: +case 0x2C64: +case 0x2E64: +case 0x2065: +case 0x2265: +case 0x2465: +case 0x2665: +case 0x2865: +case 0x2A65: +case 0x2C65: +case 0x2E65: +case 0x2066: +case 0x2266: +case 0x2466: +case 0x2666: +case 0x2866: +case 0x2A66: +case 0x2C66: +case 0x2E66: + +// MOVEAL +case 0x2060: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] - 4; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READSX_LONG_F(adr, res) + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(14) +case 0x2268: +case 0x2468: +case 0x2668: +case 0x2868: +case 0x2A68: +case 0x2C68: +case 0x2E68: +case 0x2069: +case 0x2269: +case 0x2469: +case 0x2669: +case 0x2869: +case 0x2A69: +case 0x2C69: +case 0x2E69: +case 0x206A: +case 0x226A: +case 0x246A: +case 0x266A: +case 0x286A: +case 0x2A6A: +case 0x2C6A: +case 0x2E6A: +case 0x206B: +case 0x226B: +case 0x246B: +case 0x266B: +case 0x286B: +case 0x2A6B: +case 0x2C6B: +case 0x2E6B: +case 0x206C: +case 0x226C: +case 0x246C: +case 0x266C: +case 0x286C: +case 0x2A6C: +case 0x2C6C: +case 0x2E6C: +case 0x206D: +case 0x226D: +case 0x246D: +case 0x266D: +case 0x286D: +case 0x2A6D: +case 0x2C6D: +case 0x2E6D: +case 0x206E: +case 0x226E: +case 0x246E: +case 0x266E: +case 0x286E: +case 0x2A6E: +case 0x2C6E: +case 0x2E6E: +case 0x206F: +case 0x226F: +case 0x246F: +case 0x266F: +case 0x286F: +case 0x2A6F: +case 0x2C6F: +case 0x2E6F: + +// MOVEAL +case 0x2068: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READSX_LONG_F(adr, res) + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(16) +case 0x2270: +case 0x2470: +case 0x2670: +case 0x2870: +case 0x2A70: +case 0x2C70: +case 0x2E70: +case 0x2071: +case 0x2271: +case 0x2471: +case 0x2671: +case 0x2871: +case 0x2A71: +case 0x2C71: +case 0x2E71: +case 0x2072: +case 0x2272: +case 0x2472: +case 0x2672: +case 0x2872: +case 0x2A72: +case 0x2C72: +case 0x2E72: +case 0x2073: +case 0x2273: +case 0x2473: +case 0x2673: +case 0x2873: +case 0x2A73: +case 0x2C73: +case 0x2E73: +case 0x2074: +case 0x2274: +case 0x2474: +case 0x2674: +case 0x2874: +case 0x2A74: +case 0x2C74: +case 0x2E74: +case 0x2075: +case 0x2275: +case 0x2475: +case 0x2675: +case 0x2875: +case 0x2A75: +case 0x2C75: +case 0x2E75: +case 0x2076: +case 0x2276: +case 0x2476: +case 0x2676: +case 0x2876: +case 0x2A76: +case 0x2C76: +case 0x2E76: +case 0x2077: +case 0x2277: +case 0x2477: +case 0x2677: +case 0x2877: +case 0x2A77: +case 0x2C77: +case 0x2E77: + +// MOVEAL +case 0x2070: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READSX_LONG_F(adr, res) + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(18) +case 0x2278: +case 0x2478: +case 0x2678: +case 0x2878: +case 0x2A78: +case 0x2C78: +case 0x2E78: + +// MOVEAL +case 0x2078: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READSX_LONG_F(adr, res) + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(16) +case 0x2279: +case 0x2479: +case 0x2679: +case 0x2879: +case 0x2A79: +case 0x2C79: +case 0x2E79: + +// MOVEAL +case 0x2079: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READSX_LONG_F(adr, res) + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(20) +case 0x227A: +case 0x247A: +case 0x267A: +case 0x287A: +case 0x2A7A: +case 0x2C7A: +case 0x2E7A: + +// MOVEAL +case 0x207A: +{ + u32 adr; + u32 res; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READSX_LONG_F(adr, res) + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(16) +case 0x227B: +case 0x247B: +case 0x267B: +case 0x287B: +case 0x2A7B: +case 0x2C7B: +case 0x2E7B: + +// MOVEAL +case 0x207B: +{ + u32 adr; + u32 res; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READSX_LONG_F(adr, res) + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(18) +case 0x227C: +case 0x247C: +case 0x267C: +case 0x287C: +case 0x2A7C: +case 0x2C7C: +case 0x2E7C: + +// MOVEAL +case 0x207C: +{ + u32 res; + res = (s32)(s32)FETCH_LONG; + PC += 4; + CPU->A[(Opcode >> 9) & 7] = res; +} +RET(12) +case 0x225F: +case 0x245F: +case 0x265F: +case 0x285F: +case 0x2A5F: +case 0x2C5F: +case 0x2E5F: + +// MOVEAL +case 0x205F: +{ + u32 adr; + u32 res; + adr = CPU->A[7]; + CPU->A[7] += 4; + PRE_IO + READSX_LONG_F(adr, res) + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(12) +case 0x2267: +case 0x2467: +case 0x2667: +case 0x2867: +case 0x2A67: +case 0x2C67: +case 0x2E67: + +// MOVEAL +case 0x2067: +{ + u32 adr; + u32 res; + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + PRE_IO + READSX_LONG_F(adr, res) + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(14) diff --git a/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68k_op3.inc b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68k_op3.inc new file mode 100644 index 000000000..5756c59dd --- /dev/null +++ b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68k_op3.inc @@ -0,0 +1,6254 @@ +case 0x3200: +case 0x3400: +case 0x3600: +case 0x3800: +case 0x3A00: +case 0x3C00: +case 0x3E00: +case 0x3001: +case 0x3201: +case 0x3401: +case 0x3601: +case 0x3801: +case 0x3A01: +case 0x3C01: +case 0x3E01: +case 0x3002: +case 0x3202: +case 0x3402: +case 0x3602: +case 0x3802: +case 0x3A02: +case 0x3C02: +case 0x3E02: +case 0x3003: +case 0x3203: +case 0x3403: +case 0x3603: +case 0x3803: +case 0x3A03: +case 0x3C03: +case 0x3E03: +case 0x3004: +case 0x3204: +case 0x3404: +case 0x3604: +case 0x3804: +case 0x3A04: +case 0x3C04: +case 0x3E04: +case 0x3005: +case 0x3205: +case 0x3405: +case 0x3605: +case 0x3805: +case 0x3A05: +case 0x3C05: +case 0x3E05: +case 0x3006: +case 0x3206: +case 0x3406: +case 0x3606: +case 0x3806: +case 0x3A06: +case 0x3C06: +case 0x3E06: +case 0x3007: +case 0x3207: +case 0x3407: +case 0x3607: +case 0x3807: +case 0x3A07: +case 0x3C07: +case 0x3E07: + +// MOVEW +case 0x3000: +{ + u32 res; + res = (u16)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; +} +RET(4) +case 0x3280: +case 0x3480: +case 0x3680: +case 0x3880: +case 0x3A80: +case 0x3C80: +case 0x3E80: +case 0x3081: +case 0x3281: +case 0x3481: +case 0x3681: +case 0x3881: +case 0x3A81: +case 0x3C81: +case 0x3E81: +case 0x3082: +case 0x3282: +case 0x3482: +case 0x3682: +case 0x3882: +case 0x3A82: +case 0x3C82: +case 0x3E82: +case 0x3083: +case 0x3283: +case 0x3483: +case 0x3683: +case 0x3883: +case 0x3A83: +case 0x3C83: +case 0x3E83: +case 0x3084: +case 0x3284: +case 0x3484: +case 0x3684: +case 0x3884: +case 0x3A84: +case 0x3C84: +case 0x3E84: +case 0x3085: +case 0x3285: +case 0x3485: +case 0x3685: +case 0x3885: +case 0x3A85: +case 0x3C85: +case 0x3E85: +case 0x3086: +case 0x3286: +case 0x3486: +case 0x3686: +case 0x3886: +case 0x3A86: +case 0x3C86: +case 0x3E86: +case 0x3087: +case 0x3287: +case 0x3487: +case 0x3687: +case 0x3887: +case 0x3A87: +case 0x3C87: +case 0x3E87: + +// MOVEW +case 0x3080: +{ + u32 adr; + u32 res; + res = (u16)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7]; + PRE_IO + WRITE_WORD_F(adr, res) + POST_IO +} +RET(8) +case 0x32C0: +case 0x34C0: +case 0x36C0: +case 0x38C0: +case 0x3AC0: +case 0x3CC0: +case 0x30C1: +case 0x32C1: +case 0x34C1: +case 0x36C1: +case 0x38C1: +case 0x3AC1: +case 0x3CC1: +case 0x30C2: +case 0x32C2: +case 0x34C2: +case 0x36C2: +case 0x38C2: +case 0x3AC2: +case 0x3CC2: +case 0x30C3: +case 0x32C3: +case 0x34C3: +case 0x36C3: +case 0x38C3: +case 0x3AC3: +case 0x3CC3: +case 0x30C4: +case 0x32C4: +case 0x34C4: +case 0x36C4: +case 0x38C4: +case 0x3AC4: +case 0x3CC4: +case 0x30C5: +case 0x32C5: +case 0x34C5: +case 0x36C5: +case 0x38C5: +case 0x3AC5: +case 0x3CC5: +case 0x30C6: +case 0x32C6: +case 0x34C6: +case 0x36C6: +case 0x38C6: +case 0x3AC6: +case 0x3CC6: +case 0x30C7: +case 0x32C7: +case 0x34C7: +case 0x36C7: +case 0x38C7: +case 0x3AC7: +case 0x3CC7: + +// MOVEW +case 0x30C0: +{ + u32 adr; + u32 res; + res = (u16)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7]; + CPU->A[(Opcode >> 9) & 7] += 2; + PRE_IO + WRITE_WORD_F(adr, res) + POST_IO +} +RET(8) +case 0x3300: +case 0x3500: +case 0x3700: +case 0x3900: +case 0x3B00: +case 0x3D00: +case 0x3101: +case 0x3301: +case 0x3501: +case 0x3701: +case 0x3901: +case 0x3B01: +case 0x3D01: +case 0x3102: +case 0x3302: +case 0x3502: +case 0x3702: +case 0x3902: +case 0x3B02: +case 0x3D02: +case 0x3103: +case 0x3303: +case 0x3503: +case 0x3703: +case 0x3903: +case 0x3B03: +case 0x3D03: +case 0x3104: +case 0x3304: +case 0x3504: +case 0x3704: +case 0x3904: +case 0x3B04: +case 0x3D04: +case 0x3105: +case 0x3305: +case 0x3505: +case 0x3705: +case 0x3905: +case 0x3B05: +case 0x3D05: +case 0x3106: +case 0x3306: +case 0x3506: +case 0x3706: +case 0x3906: +case 0x3B06: +case 0x3D06: +case 0x3107: +case 0x3307: +case 0x3507: +case 0x3707: +case 0x3907: +case 0x3B07: +case 0x3D07: + +// MOVEW +case 0x3100: +{ + u32 adr; + u32 res; + res = (u16)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7] - 2; + CPU->A[(Opcode >> 9) & 7] = adr; + PRE_IO + WRITE_WORD_F(adr, res) + POST_IO +} +RET(8) +case 0x3340: +case 0x3540: +case 0x3740: +case 0x3940: +case 0x3B40: +case 0x3D40: +case 0x3F40: +case 0x3141: +case 0x3341: +case 0x3541: +case 0x3741: +case 0x3941: +case 0x3B41: +case 0x3D41: +case 0x3F41: +case 0x3142: +case 0x3342: +case 0x3542: +case 0x3742: +case 0x3942: +case 0x3B42: +case 0x3D42: +case 0x3F42: +case 0x3143: +case 0x3343: +case 0x3543: +case 0x3743: +case 0x3943: +case 0x3B43: +case 0x3D43: +case 0x3F43: +case 0x3144: +case 0x3344: +case 0x3544: +case 0x3744: +case 0x3944: +case 0x3B44: +case 0x3D44: +case 0x3F44: +case 0x3145: +case 0x3345: +case 0x3545: +case 0x3745: +case 0x3945: +case 0x3B45: +case 0x3D45: +case 0x3F45: +case 0x3146: +case 0x3346: +case 0x3546: +case 0x3746: +case 0x3946: +case 0x3B46: +case 0x3D46: +case 0x3F46: +case 0x3147: +case 0x3347: +case 0x3547: +case 0x3747: +case 0x3947: +case 0x3B47: +case 0x3D47: +case 0x3F47: + +// MOVEW +case 0x3140: +{ + u32 adr; + u32 res; + res = (u16)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0x3380: +case 0x3580: +case 0x3780: +case 0x3980: +case 0x3B80: +case 0x3D80: +case 0x3F80: +case 0x3181: +case 0x3381: +case 0x3581: +case 0x3781: +case 0x3981: +case 0x3B81: +case 0x3D81: +case 0x3F81: +case 0x3182: +case 0x3382: +case 0x3582: +case 0x3782: +case 0x3982: +case 0x3B82: +case 0x3D82: +case 0x3F82: +case 0x3183: +case 0x3383: +case 0x3583: +case 0x3783: +case 0x3983: +case 0x3B83: +case 0x3D83: +case 0x3F83: +case 0x3184: +case 0x3384: +case 0x3584: +case 0x3784: +case 0x3984: +case 0x3B84: +case 0x3D84: +case 0x3F84: +case 0x3185: +case 0x3385: +case 0x3585: +case 0x3785: +case 0x3985: +case 0x3B85: +case 0x3D85: +case 0x3F85: +case 0x3186: +case 0x3386: +case 0x3586: +case 0x3786: +case 0x3986: +case 0x3B86: +case 0x3D86: +case 0x3F86: +case 0x3187: +case 0x3387: +case 0x3587: +case 0x3787: +case 0x3987: +case 0x3B87: +case 0x3D87: +case 0x3F87: + +// MOVEW +case 0x3180: +{ + u32 adr; + u32 res; + res = (u16)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7]; + DECODE_EXT_WORD + PRE_IO + WRITE_WORD_F(adr, res) + POST_IO +} +RET(14) +case 0x31C1: +case 0x31C2: +case 0x31C3: +case 0x31C4: +case 0x31C5: +case 0x31C6: +case 0x31C7: + +// MOVEW +case 0x31C0: +{ + u32 adr; + u32 res; + res = (u16)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0x33C1: +case 0x33C2: +case 0x33C3: +case 0x33C4: +case 0x33C5: +case 0x33C6: +case 0x33C7: + +// MOVEW +case 0x33C0: +{ + u32 adr; + u32 res; + res = (u16)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0x3EC1: +case 0x3EC2: +case 0x3EC3: +case 0x3EC4: +case 0x3EC5: +case 0x3EC6: +case 0x3EC7: + +// MOVEW +case 0x3EC0: +{ + u32 adr; + u32 res; + res = (u16)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + WRITE_WORD_F(adr, res) + POST_IO +} +RET(8) +case 0x3F01: +case 0x3F02: +case 0x3F03: +case 0x3F04: +case 0x3F05: +case 0x3F06: +case 0x3F07: + +// MOVEW +case 0x3F00: +{ + u32 adr; + u32 res; + res = (u16)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + WRITE_WORD_F(adr, res) + POST_IO +} +RET(8) +case 0x3208: +case 0x3408: +case 0x3608: +case 0x3808: +case 0x3A08: +case 0x3C08: +case 0x3E08: +case 0x3009: +case 0x3209: +case 0x3409: +case 0x3609: +case 0x3809: +case 0x3A09: +case 0x3C09: +case 0x3E09: +case 0x300A: +case 0x320A: +case 0x340A: +case 0x360A: +case 0x380A: +case 0x3A0A: +case 0x3C0A: +case 0x3E0A: +case 0x300B: +case 0x320B: +case 0x340B: +case 0x360B: +case 0x380B: +case 0x3A0B: +case 0x3C0B: +case 0x3E0B: +case 0x300C: +case 0x320C: +case 0x340C: +case 0x360C: +case 0x380C: +case 0x3A0C: +case 0x3C0C: +case 0x3E0C: +case 0x300D: +case 0x320D: +case 0x340D: +case 0x360D: +case 0x380D: +case 0x3A0D: +case 0x3C0D: +case 0x3E0D: +case 0x300E: +case 0x320E: +case 0x340E: +case 0x360E: +case 0x380E: +case 0x3A0E: +case 0x3C0E: +case 0x3E0E: +case 0x300F: +case 0x320F: +case 0x340F: +case 0x360F: +case 0x380F: +case 0x3A0F: +case 0x3C0F: +case 0x3E0F: + +// MOVEW +case 0x3008: +{ + u32 res; + res = (u16)CPU->A[(Opcode >> 0) & 7]; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; +} +RET(4) +case 0x3288: +case 0x3488: +case 0x3688: +case 0x3888: +case 0x3A88: +case 0x3C88: +case 0x3E88: +case 0x3089: +case 0x3289: +case 0x3489: +case 0x3689: +case 0x3889: +case 0x3A89: +case 0x3C89: +case 0x3E89: +case 0x308A: +case 0x328A: +case 0x348A: +case 0x368A: +case 0x388A: +case 0x3A8A: +case 0x3C8A: +case 0x3E8A: +case 0x308B: +case 0x328B: +case 0x348B: +case 0x368B: +case 0x388B: +case 0x3A8B: +case 0x3C8B: +case 0x3E8B: +case 0x308C: +case 0x328C: +case 0x348C: +case 0x368C: +case 0x388C: +case 0x3A8C: +case 0x3C8C: +case 0x3E8C: +case 0x308D: +case 0x328D: +case 0x348D: +case 0x368D: +case 0x388D: +case 0x3A8D: +case 0x3C8D: +case 0x3E8D: +case 0x308E: +case 0x328E: +case 0x348E: +case 0x368E: +case 0x388E: +case 0x3A8E: +case 0x3C8E: +case 0x3E8E: +case 0x308F: +case 0x328F: +case 0x348F: +case 0x368F: +case 0x388F: +case 0x3A8F: +case 0x3C8F: +case 0x3E8F: + +// MOVEW +case 0x3088: +{ + u32 adr; + u32 res; + res = (u16)CPU->A[(Opcode >> 0) & 7]; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7]; + PRE_IO + WRITE_WORD_F(adr, res) + POST_IO +} +RET(8) +case 0x32C8: +case 0x34C8: +case 0x36C8: +case 0x38C8: +case 0x3AC8: +case 0x3CC8: +case 0x30C9: +case 0x32C9: +case 0x34C9: +case 0x36C9: +case 0x38C9: +case 0x3AC9: +case 0x3CC9: +case 0x30CA: +case 0x32CA: +case 0x34CA: +case 0x36CA: +case 0x38CA: +case 0x3ACA: +case 0x3CCA: +case 0x30CB: +case 0x32CB: +case 0x34CB: +case 0x36CB: +case 0x38CB: +case 0x3ACB: +case 0x3CCB: +case 0x30CC: +case 0x32CC: +case 0x34CC: +case 0x36CC: +case 0x38CC: +case 0x3ACC: +case 0x3CCC: +case 0x30CD: +case 0x32CD: +case 0x34CD: +case 0x36CD: +case 0x38CD: +case 0x3ACD: +case 0x3CCD: +case 0x30CE: +case 0x32CE: +case 0x34CE: +case 0x36CE: +case 0x38CE: +case 0x3ACE: +case 0x3CCE: +case 0x30CF: +case 0x32CF: +case 0x34CF: +case 0x36CF: +case 0x38CF: +case 0x3ACF: +case 0x3CCF: + +// MOVEW +case 0x30C8: +{ + u32 adr; + u32 res; + res = (u16)CPU->A[(Opcode >> 0) & 7]; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7]; + CPU->A[(Opcode >> 9) & 7] += 2; + PRE_IO + WRITE_WORD_F(adr, res) + POST_IO +} +RET(8) +case 0x3308: +case 0x3508: +case 0x3708: +case 0x3908: +case 0x3B08: +case 0x3D08: +case 0x3109: +case 0x3309: +case 0x3509: +case 0x3709: +case 0x3909: +case 0x3B09: +case 0x3D09: +case 0x310A: +case 0x330A: +case 0x350A: +case 0x370A: +case 0x390A: +case 0x3B0A: +case 0x3D0A: +case 0x310B: +case 0x330B: +case 0x350B: +case 0x370B: +case 0x390B: +case 0x3B0B: +case 0x3D0B: +case 0x310C: +case 0x330C: +case 0x350C: +case 0x370C: +case 0x390C: +case 0x3B0C: +case 0x3D0C: +case 0x310D: +case 0x330D: +case 0x350D: +case 0x370D: +case 0x390D: +case 0x3B0D: +case 0x3D0D: +case 0x310E: +case 0x330E: +case 0x350E: +case 0x370E: +case 0x390E: +case 0x3B0E: +case 0x3D0E: +case 0x310F: +case 0x330F: +case 0x350F: +case 0x370F: +case 0x390F: +case 0x3B0F: +case 0x3D0F: + +// MOVEW +case 0x3108: +{ + u32 adr; + u32 res; + res = (u16)CPU->A[(Opcode >> 0) & 7]; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7] - 2; + CPU->A[(Opcode >> 9) & 7] = adr; + PRE_IO + WRITE_WORD_F(adr, res) + POST_IO +} +RET(8) +case 0x3348: +case 0x3548: +case 0x3748: +case 0x3948: +case 0x3B48: +case 0x3D48: +case 0x3F48: +case 0x3149: +case 0x3349: +case 0x3549: +case 0x3749: +case 0x3949: +case 0x3B49: +case 0x3D49: +case 0x3F49: +case 0x314A: +case 0x334A: +case 0x354A: +case 0x374A: +case 0x394A: +case 0x3B4A: +case 0x3D4A: +case 0x3F4A: +case 0x314B: +case 0x334B: +case 0x354B: +case 0x374B: +case 0x394B: +case 0x3B4B: +case 0x3D4B: +case 0x3F4B: +case 0x314C: +case 0x334C: +case 0x354C: +case 0x374C: +case 0x394C: +case 0x3B4C: +case 0x3D4C: +case 0x3F4C: +case 0x314D: +case 0x334D: +case 0x354D: +case 0x374D: +case 0x394D: +case 0x3B4D: +case 0x3D4D: +case 0x3F4D: +case 0x314E: +case 0x334E: +case 0x354E: +case 0x374E: +case 0x394E: +case 0x3B4E: +case 0x3D4E: +case 0x3F4E: +case 0x314F: +case 0x334F: +case 0x354F: +case 0x374F: +case 0x394F: +case 0x3B4F: +case 0x3D4F: +case 0x3F4F: + +// MOVEW +case 0x3148: +{ + u32 adr; + u32 res; + res = (u16)CPU->A[(Opcode >> 0) & 7]; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0x3388: +case 0x3588: +case 0x3788: +case 0x3988: +case 0x3B88: +case 0x3D88: +case 0x3F88: +case 0x3189: +case 0x3389: +case 0x3589: +case 0x3789: +case 0x3989: +case 0x3B89: +case 0x3D89: +case 0x3F89: +case 0x318A: +case 0x338A: +case 0x358A: +case 0x378A: +case 0x398A: +case 0x3B8A: +case 0x3D8A: +case 0x3F8A: +case 0x318B: +case 0x338B: +case 0x358B: +case 0x378B: +case 0x398B: +case 0x3B8B: +case 0x3D8B: +case 0x3F8B: +case 0x318C: +case 0x338C: +case 0x358C: +case 0x378C: +case 0x398C: +case 0x3B8C: +case 0x3D8C: +case 0x3F8C: +case 0x318D: +case 0x338D: +case 0x358D: +case 0x378D: +case 0x398D: +case 0x3B8D: +case 0x3D8D: +case 0x3F8D: +case 0x318E: +case 0x338E: +case 0x358E: +case 0x378E: +case 0x398E: +case 0x3B8E: +case 0x3D8E: +case 0x3F8E: +case 0x318F: +case 0x338F: +case 0x358F: +case 0x378F: +case 0x398F: +case 0x3B8F: +case 0x3D8F: +case 0x3F8F: + +// MOVEW +case 0x3188: +{ + u32 adr; + u32 res; + res = (u16)CPU->A[(Opcode >> 0) & 7]; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7]; + DECODE_EXT_WORD + PRE_IO + WRITE_WORD_F(adr, res) + POST_IO +} +RET(14) +case 0x31C9: +case 0x31CA: +case 0x31CB: +case 0x31CC: +case 0x31CD: +case 0x31CE: +case 0x31CF: + +// MOVEW +case 0x31C8: +{ + u32 adr; + u32 res; + res = (u16)CPU->A[(Opcode >> 0) & 7]; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0x33C9: +case 0x33CA: +case 0x33CB: +case 0x33CC: +case 0x33CD: +case 0x33CE: +case 0x33CF: + +// MOVEW +case 0x33C8: +{ + u32 adr; + u32 res; + res = (u16)CPU->A[(Opcode >> 0) & 7]; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0x3EC9: +case 0x3ECA: +case 0x3ECB: +case 0x3ECC: +case 0x3ECD: +case 0x3ECE: +case 0x3ECF: + +// MOVEW +case 0x3EC8: +{ + u32 adr; + u32 res; + res = (u16)CPU->A[(Opcode >> 0) & 7]; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + WRITE_WORD_F(adr, res) + POST_IO +} +RET(8) +case 0x3F09: +case 0x3F0A: +case 0x3F0B: +case 0x3F0C: +case 0x3F0D: +case 0x3F0E: +case 0x3F0F: + +// MOVEW +case 0x3F08: +{ + u32 adr; + u32 res; + res = (u16)CPU->A[(Opcode >> 0) & 7]; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + WRITE_WORD_F(adr, res) + POST_IO +} +RET(8) +case 0x3210: +case 0x3410: +case 0x3610: +case 0x3810: +case 0x3A10: +case 0x3C10: +case 0x3E10: +case 0x3011: +case 0x3211: +case 0x3411: +case 0x3611: +case 0x3811: +case 0x3A11: +case 0x3C11: +case 0x3E11: +case 0x3012: +case 0x3212: +case 0x3412: +case 0x3612: +case 0x3812: +case 0x3A12: +case 0x3C12: +case 0x3E12: +case 0x3013: +case 0x3213: +case 0x3413: +case 0x3613: +case 0x3813: +case 0x3A13: +case 0x3C13: +case 0x3E13: +case 0x3014: +case 0x3214: +case 0x3414: +case 0x3614: +case 0x3814: +case 0x3A14: +case 0x3C14: +case 0x3E14: +case 0x3015: +case 0x3215: +case 0x3415: +case 0x3615: +case 0x3815: +case 0x3A15: +case 0x3C15: +case 0x3E15: +case 0x3016: +case 0x3216: +case 0x3416: +case 0x3616: +case 0x3816: +case 0x3A16: +case 0x3C16: +case 0x3E16: +case 0x3017: +case 0x3217: +case 0x3417: +case 0x3617: +case 0x3817: +case 0x3A17: +case 0x3C17: +case 0x3E17: + +// MOVEW +case 0x3010: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(8) +case 0x3290: +case 0x3490: +case 0x3690: +case 0x3890: +case 0x3A90: +case 0x3C90: +case 0x3E90: +case 0x3091: +case 0x3291: +case 0x3491: +case 0x3691: +case 0x3891: +case 0x3A91: +case 0x3C91: +case 0x3E91: +case 0x3092: +case 0x3292: +case 0x3492: +case 0x3692: +case 0x3892: +case 0x3A92: +case 0x3C92: +case 0x3E92: +case 0x3093: +case 0x3293: +case 0x3493: +case 0x3693: +case 0x3893: +case 0x3A93: +case 0x3C93: +case 0x3E93: +case 0x3094: +case 0x3294: +case 0x3494: +case 0x3694: +case 0x3894: +case 0x3A94: +case 0x3C94: +case 0x3E94: +case 0x3095: +case 0x3295: +case 0x3495: +case 0x3695: +case 0x3895: +case 0x3A95: +case 0x3C95: +case 0x3E95: +case 0x3096: +case 0x3296: +case 0x3496: +case 0x3696: +case 0x3896: +case 0x3A96: +case 0x3C96: +case 0x3E96: +case 0x3097: +case 0x3297: +case 0x3497: +case 0x3697: +case 0x3897: +case 0x3A97: +case 0x3C97: +case 0x3E97: + +// MOVEW +case 0x3090: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7]; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0x32D0: +case 0x34D0: +case 0x36D0: +case 0x38D0: +case 0x3AD0: +case 0x3CD0: +case 0x30D1: +case 0x32D1: +case 0x34D1: +case 0x36D1: +case 0x38D1: +case 0x3AD1: +case 0x3CD1: +case 0x30D2: +case 0x32D2: +case 0x34D2: +case 0x36D2: +case 0x38D2: +case 0x3AD2: +case 0x3CD2: +case 0x30D3: +case 0x32D3: +case 0x34D3: +case 0x36D3: +case 0x38D3: +case 0x3AD3: +case 0x3CD3: +case 0x30D4: +case 0x32D4: +case 0x34D4: +case 0x36D4: +case 0x38D4: +case 0x3AD4: +case 0x3CD4: +case 0x30D5: +case 0x32D5: +case 0x34D5: +case 0x36D5: +case 0x38D5: +case 0x3AD5: +case 0x3CD5: +case 0x30D6: +case 0x32D6: +case 0x34D6: +case 0x36D6: +case 0x38D6: +case 0x3AD6: +case 0x3CD6: +case 0x30D7: +case 0x32D7: +case 0x34D7: +case 0x36D7: +case 0x38D7: +case 0x3AD7: +case 0x3CD7: + +// MOVEW +case 0x30D0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7]; + CPU->A[(Opcode >> 9) & 7] += 2; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0x3310: +case 0x3510: +case 0x3710: +case 0x3910: +case 0x3B10: +case 0x3D10: +case 0x3111: +case 0x3311: +case 0x3511: +case 0x3711: +case 0x3911: +case 0x3B11: +case 0x3D11: +case 0x3112: +case 0x3312: +case 0x3512: +case 0x3712: +case 0x3912: +case 0x3B12: +case 0x3D12: +case 0x3113: +case 0x3313: +case 0x3513: +case 0x3713: +case 0x3913: +case 0x3B13: +case 0x3D13: +case 0x3114: +case 0x3314: +case 0x3514: +case 0x3714: +case 0x3914: +case 0x3B14: +case 0x3D14: +case 0x3115: +case 0x3315: +case 0x3515: +case 0x3715: +case 0x3915: +case 0x3B15: +case 0x3D15: +case 0x3116: +case 0x3316: +case 0x3516: +case 0x3716: +case 0x3916: +case 0x3B16: +case 0x3D16: +case 0x3117: +case 0x3317: +case 0x3517: +case 0x3717: +case 0x3917: +case 0x3B17: +case 0x3D17: + +// MOVEW +case 0x3110: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7] - 2; + CPU->A[(Opcode >> 9) & 7] = adr; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0x3350: +case 0x3550: +case 0x3750: +case 0x3950: +case 0x3B50: +case 0x3D50: +case 0x3F50: +case 0x3151: +case 0x3351: +case 0x3551: +case 0x3751: +case 0x3951: +case 0x3B51: +case 0x3D51: +case 0x3F51: +case 0x3152: +case 0x3352: +case 0x3552: +case 0x3752: +case 0x3952: +case 0x3B52: +case 0x3D52: +case 0x3F52: +case 0x3153: +case 0x3353: +case 0x3553: +case 0x3753: +case 0x3953: +case 0x3B53: +case 0x3D53: +case 0x3F53: +case 0x3154: +case 0x3354: +case 0x3554: +case 0x3754: +case 0x3954: +case 0x3B54: +case 0x3D54: +case 0x3F54: +case 0x3155: +case 0x3355: +case 0x3555: +case 0x3755: +case 0x3955: +case 0x3B55: +case 0x3D55: +case 0x3F55: +case 0x3156: +case 0x3356: +case 0x3556: +case 0x3756: +case 0x3956: +case 0x3B56: +case 0x3D56: +case 0x3F56: +case 0x3157: +case 0x3357: +case 0x3557: +case 0x3757: +case 0x3957: +case 0x3B57: +case 0x3D57: +case 0x3F57: + +// MOVEW +case 0x3150: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0x3390: +case 0x3590: +case 0x3790: +case 0x3990: +case 0x3B90: +case 0x3D90: +case 0x3F90: +case 0x3191: +case 0x3391: +case 0x3591: +case 0x3791: +case 0x3991: +case 0x3B91: +case 0x3D91: +case 0x3F91: +case 0x3192: +case 0x3392: +case 0x3592: +case 0x3792: +case 0x3992: +case 0x3B92: +case 0x3D92: +case 0x3F92: +case 0x3193: +case 0x3393: +case 0x3593: +case 0x3793: +case 0x3993: +case 0x3B93: +case 0x3D93: +case 0x3F93: +case 0x3194: +case 0x3394: +case 0x3594: +case 0x3794: +case 0x3994: +case 0x3B94: +case 0x3D94: +case 0x3F94: +case 0x3195: +case 0x3395: +case 0x3595: +case 0x3795: +case 0x3995: +case 0x3B95: +case 0x3D95: +case 0x3F95: +case 0x3196: +case 0x3396: +case 0x3596: +case 0x3796: +case 0x3996: +case 0x3B96: +case 0x3D96: +case 0x3F96: +case 0x3197: +case 0x3397: +case 0x3597: +case 0x3797: +case 0x3997: +case 0x3B97: +case 0x3D97: +case 0x3F97: + +// MOVEW +case 0x3190: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7]; + DECODE_EXT_WORD + WRITE_WORD_F(adr, res) + POST_IO +} +RET(18) +case 0x31D1: +case 0x31D2: +case 0x31D3: +case 0x31D4: +case 0x31D5: +case 0x31D6: +case 0x31D7: + +// MOVEW +case 0x31D0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0x33D1: +case 0x33D2: +case 0x33D3: +case 0x33D4: +case 0x33D5: +case 0x33D6: +case 0x33D7: + +// MOVEW +case 0x33D0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = (s32)FETCH_LONG; + PC += 4; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(20) +case 0x3ED1: +case 0x3ED2: +case 0x3ED3: +case 0x3ED4: +case 0x3ED5: +case 0x3ED6: +case 0x3ED7: + +// MOVEW +case 0x3ED0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[7]; + CPU->A[7] += 2; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0x3F11: +case 0x3F12: +case 0x3F13: +case 0x3F14: +case 0x3F15: +case 0x3F16: +case 0x3F17: + +// MOVEW +case 0x3F10: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0x3218: +case 0x3418: +case 0x3618: +case 0x3818: +case 0x3A18: +case 0x3C18: +case 0x3E18: +case 0x3019: +case 0x3219: +case 0x3419: +case 0x3619: +case 0x3819: +case 0x3A19: +case 0x3C19: +case 0x3E19: +case 0x301A: +case 0x321A: +case 0x341A: +case 0x361A: +case 0x381A: +case 0x3A1A: +case 0x3C1A: +case 0x3E1A: +case 0x301B: +case 0x321B: +case 0x341B: +case 0x361B: +case 0x381B: +case 0x3A1B: +case 0x3C1B: +case 0x3E1B: +case 0x301C: +case 0x321C: +case 0x341C: +case 0x361C: +case 0x381C: +case 0x3A1C: +case 0x3C1C: +case 0x3E1C: +case 0x301D: +case 0x321D: +case 0x341D: +case 0x361D: +case 0x381D: +case 0x3A1D: +case 0x3C1D: +case 0x3E1D: +case 0x301E: +case 0x321E: +case 0x341E: +case 0x361E: +case 0x381E: +case 0x3A1E: +case 0x3C1E: +case 0x3E1E: + +// MOVEW +case 0x3018: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 2; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(8) +case 0x3298: +case 0x3498: +case 0x3698: +case 0x3898: +case 0x3A98: +case 0x3C98: +case 0x3E98: +case 0x3099: +case 0x3299: +case 0x3499: +case 0x3699: +case 0x3899: +case 0x3A99: +case 0x3C99: +case 0x3E99: +case 0x309A: +case 0x329A: +case 0x349A: +case 0x369A: +case 0x389A: +case 0x3A9A: +case 0x3C9A: +case 0x3E9A: +case 0x309B: +case 0x329B: +case 0x349B: +case 0x369B: +case 0x389B: +case 0x3A9B: +case 0x3C9B: +case 0x3E9B: +case 0x309C: +case 0x329C: +case 0x349C: +case 0x369C: +case 0x389C: +case 0x3A9C: +case 0x3C9C: +case 0x3E9C: +case 0x309D: +case 0x329D: +case 0x349D: +case 0x369D: +case 0x389D: +case 0x3A9D: +case 0x3C9D: +case 0x3E9D: +case 0x309E: +case 0x329E: +case 0x349E: +case 0x369E: +case 0x389E: +case 0x3A9E: +case 0x3C9E: +case 0x3E9E: + +// MOVEW +case 0x3098: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 2; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7]; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0x32D8: +case 0x34D8: +case 0x36D8: +case 0x38D8: +case 0x3AD8: +case 0x3CD8: +case 0x30D9: +case 0x32D9: +case 0x34D9: +case 0x36D9: +case 0x38D9: +case 0x3AD9: +case 0x3CD9: +case 0x30DA: +case 0x32DA: +case 0x34DA: +case 0x36DA: +case 0x38DA: +case 0x3ADA: +case 0x3CDA: +case 0x30DB: +case 0x32DB: +case 0x34DB: +case 0x36DB: +case 0x38DB: +case 0x3ADB: +case 0x3CDB: +case 0x30DC: +case 0x32DC: +case 0x34DC: +case 0x36DC: +case 0x38DC: +case 0x3ADC: +case 0x3CDC: +case 0x30DD: +case 0x32DD: +case 0x34DD: +case 0x36DD: +case 0x38DD: +case 0x3ADD: +case 0x3CDD: +case 0x30DE: +case 0x32DE: +case 0x34DE: +case 0x36DE: +case 0x38DE: +case 0x3ADE: +case 0x3CDE: + +// MOVEW +case 0x30D8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 2; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7]; + CPU->A[(Opcode >> 9) & 7] += 2; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0x3318: +case 0x3518: +case 0x3718: +case 0x3918: +case 0x3B18: +case 0x3D18: +case 0x3119: +case 0x3319: +case 0x3519: +case 0x3719: +case 0x3919: +case 0x3B19: +case 0x3D19: +case 0x311A: +case 0x331A: +case 0x351A: +case 0x371A: +case 0x391A: +case 0x3B1A: +case 0x3D1A: +case 0x311B: +case 0x331B: +case 0x351B: +case 0x371B: +case 0x391B: +case 0x3B1B: +case 0x3D1B: +case 0x311C: +case 0x331C: +case 0x351C: +case 0x371C: +case 0x391C: +case 0x3B1C: +case 0x3D1C: +case 0x311D: +case 0x331D: +case 0x351D: +case 0x371D: +case 0x391D: +case 0x3B1D: +case 0x3D1D: +case 0x311E: +case 0x331E: +case 0x351E: +case 0x371E: +case 0x391E: +case 0x3B1E: +case 0x3D1E: + +// MOVEW +case 0x3118: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 2; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7] - 2; + CPU->A[(Opcode >> 9) & 7] = adr; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0x3358: +case 0x3558: +case 0x3758: +case 0x3958: +case 0x3B58: +case 0x3D58: +case 0x3F58: +case 0x3159: +case 0x3359: +case 0x3559: +case 0x3759: +case 0x3959: +case 0x3B59: +case 0x3D59: +case 0x3F59: +case 0x315A: +case 0x335A: +case 0x355A: +case 0x375A: +case 0x395A: +case 0x3B5A: +case 0x3D5A: +case 0x3F5A: +case 0x315B: +case 0x335B: +case 0x355B: +case 0x375B: +case 0x395B: +case 0x3B5B: +case 0x3D5B: +case 0x3F5B: +case 0x315C: +case 0x335C: +case 0x355C: +case 0x375C: +case 0x395C: +case 0x3B5C: +case 0x3D5C: +case 0x3F5C: +case 0x315D: +case 0x335D: +case 0x355D: +case 0x375D: +case 0x395D: +case 0x3B5D: +case 0x3D5D: +case 0x3F5D: +case 0x315E: +case 0x335E: +case 0x355E: +case 0x375E: +case 0x395E: +case 0x3B5E: +case 0x3D5E: +case 0x3F5E: + +// MOVEW +case 0x3158: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 2; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0x3398: +case 0x3598: +case 0x3798: +case 0x3998: +case 0x3B98: +case 0x3D98: +case 0x3F98: +case 0x3199: +case 0x3399: +case 0x3599: +case 0x3799: +case 0x3999: +case 0x3B99: +case 0x3D99: +case 0x3F99: +case 0x319A: +case 0x339A: +case 0x359A: +case 0x379A: +case 0x399A: +case 0x3B9A: +case 0x3D9A: +case 0x3F9A: +case 0x319B: +case 0x339B: +case 0x359B: +case 0x379B: +case 0x399B: +case 0x3B9B: +case 0x3D9B: +case 0x3F9B: +case 0x319C: +case 0x339C: +case 0x359C: +case 0x379C: +case 0x399C: +case 0x3B9C: +case 0x3D9C: +case 0x3F9C: +case 0x319D: +case 0x339D: +case 0x359D: +case 0x379D: +case 0x399D: +case 0x3B9D: +case 0x3D9D: +case 0x3F9D: +case 0x319E: +case 0x339E: +case 0x359E: +case 0x379E: +case 0x399E: +case 0x3B9E: +case 0x3D9E: +case 0x3F9E: + +// MOVEW +case 0x3198: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 2; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7]; + DECODE_EXT_WORD + WRITE_WORD_F(adr, res) + POST_IO +} +RET(18) +case 0x31D9: +case 0x31DA: +case 0x31DB: +case 0x31DC: +case 0x31DD: +case 0x31DE: + +// MOVEW +case 0x31D8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 2; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0x33D9: +case 0x33DA: +case 0x33DB: +case 0x33DC: +case 0x33DD: +case 0x33DE: + +// MOVEW +case 0x33D8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 2; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = (s32)FETCH_LONG; + PC += 4; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(20) +case 0x3ED9: +case 0x3EDA: +case 0x3EDB: +case 0x3EDC: +case 0x3EDD: +case 0x3EDE: + +// MOVEW +case 0x3ED8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 2; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[7]; + CPU->A[7] += 2; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0x3F19: +case 0x3F1A: +case 0x3F1B: +case 0x3F1C: +case 0x3F1D: +case 0x3F1E: + +// MOVEW +case 0x3F18: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 2; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0x3220: +case 0x3420: +case 0x3620: +case 0x3820: +case 0x3A20: +case 0x3C20: +case 0x3E20: +case 0x3021: +case 0x3221: +case 0x3421: +case 0x3621: +case 0x3821: +case 0x3A21: +case 0x3C21: +case 0x3E21: +case 0x3022: +case 0x3222: +case 0x3422: +case 0x3622: +case 0x3822: +case 0x3A22: +case 0x3C22: +case 0x3E22: +case 0x3023: +case 0x3223: +case 0x3423: +case 0x3623: +case 0x3823: +case 0x3A23: +case 0x3C23: +case 0x3E23: +case 0x3024: +case 0x3224: +case 0x3424: +case 0x3624: +case 0x3824: +case 0x3A24: +case 0x3C24: +case 0x3E24: +case 0x3025: +case 0x3225: +case 0x3425: +case 0x3625: +case 0x3825: +case 0x3A25: +case 0x3C25: +case 0x3E25: +case 0x3026: +case 0x3226: +case 0x3426: +case 0x3626: +case 0x3826: +case 0x3A26: +case 0x3C26: +case 0x3E26: + +// MOVEW +case 0x3020: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] - 2; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(10) +case 0x32A0: +case 0x34A0: +case 0x36A0: +case 0x38A0: +case 0x3AA0: +case 0x3CA0: +case 0x3EA0: +case 0x30A1: +case 0x32A1: +case 0x34A1: +case 0x36A1: +case 0x38A1: +case 0x3AA1: +case 0x3CA1: +case 0x3EA1: +case 0x30A2: +case 0x32A2: +case 0x34A2: +case 0x36A2: +case 0x38A2: +case 0x3AA2: +case 0x3CA2: +case 0x3EA2: +case 0x30A3: +case 0x32A3: +case 0x34A3: +case 0x36A3: +case 0x38A3: +case 0x3AA3: +case 0x3CA3: +case 0x3EA3: +case 0x30A4: +case 0x32A4: +case 0x34A4: +case 0x36A4: +case 0x38A4: +case 0x3AA4: +case 0x3CA4: +case 0x3EA4: +case 0x30A5: +case 0x32A5: +case 0x34A5: +case 0x36A5: +case 0x38A5: +case 0x3AA5: +case 0x3CA5: +case 0x3EA5: +case 0x30A6: +case 0x32A6: +case 0x34A6: +case 0x36A6: +case 0x38A6: +case 0x3AA6: +case 0x3CA6: +case 0x3EA6: + +// MOVEW +case 0x30A0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] - 2; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7]; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(14) +case 0x32E0: +case 0x34E0: +case 0x36E0: +case 0x38E0: +case 0x3AE0: +case 0x3CE0: +case 0x30E1: +case 0x32E1: +case 0x34E1: +case 0x36E1: +case 0x38E1: +case 0x3AE1: +case 0x3CE1: +case 0x30E2: +case 0x32E2: +case 0x34E2: +case 0x36E2: +case 0x38E2: +case 0x3AE2: +case 0x3CE2: +case 0x30E3: +case 0x32E3: +case 0x34E3: +case 0x36E3: +case 0x38E3: +case 0x3AE3: +case 0x3CE3: +case 0x30E4: +case 0x32E4: +case 0x34E4: +case 0x36E4: +case 0x38E4: +case 0x3AE4: +case 0x3CE4: +case 0x30E5: +case 0x32E5: +case 0x34E5: +case 0x36E5: +case 0x38E5: +case 0x3AE5: +case 0x3CE5: +case 0x30E6: +case 0x32E6: +case 0x34E6: +case 0x36E6: +case 0x38E6: +case 0x3AE6: +case 0x3CE6: + +// MOVEW +case 0x30E0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] - 2; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7]; + CPU->A[(Opcode >> 9) & 7] += 2; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(14) +case 0x3320: +case 0x3520: +case 0x3720: +case 0x3920: +case 0x3B20: +case 0x3D20: +case 0x3121: +case 0x3321: +case 0x3521: +case 0x3721: +case 0x3921: +case 0x3B21: +case 0x3D21: +case 0x3122: +case 0x3322: +case 0x3522: +case 0x3722: +case 0x3922: +case 0x3B22: +case 0x3D22: +case 0x3123: +case 0x3323: +case 0x3523: +case 0x3723: +case 0x3923: +case 0x3B23: +case 0x3D23: +case 0x3124: +case 0x3324: +case 0x3524: +case 0x3724: +case 0x3924: +case 0x3B24: +case 0x3D24: +case 0x3125: +case 0x3325: +case 0x3525: +case 0x3725: +case 0x3925: +case 0x3B25: +case 0x3D25: +case 0x3126: +case 0x3326: +case 0x3526: +case 0x3726: +case 0x3926: +case 0x3B26: +case 0x3D26: + +// MOVEW +case 0x3120: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] - 2; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7] - 2; + CPU->A[(Opcode >> 9) & 7] = adr; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(14) +case 0x3360: +case 0x3560: +case 0x3760: +case 0x3960: +case 0x3B60: +case 0x3D60: +case 0x3F60: +case 0x3161: +case 0x3361: +case 0x3561: +case 0x3761: +case 0x3961: +case 0x3B61: +case 0x3D61: +case 0x3F61: +case 0x3162: +case 0x3362: +case 0x3562: +case 0x3762: +case 0x3962: +case 0x3B62: +case 0x3D62: +case 0x3F62: +case 0x3163: +case 0x3363: +case 0x3563: +case 0x3763: +case 0x3963: +case 0x3B63: +case 0x3D63: +case 0x3F63: +case 0x3164: +case 0x3364: +case 0x3564: +case 0x3764: +case 0x3964: +case 0x3B64: +case 0x3D64: +case 0x3F64: +case 0x3165: +case 0x3365: +case 0x3565: +case 0x3765: +case 0x3965: +case 0x3B65: +case 0x3D65: +case 0x3F65: +case 0x3166: +case 0x3366: +case 0x3566: +case 0x3766: +case 0x3966: +case 0x3B66: +case 0x3D66: +case 0x3F66: + +// MOVEW +case 0x3160: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] - 2; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(18) +case 0x33A0: +case 0x35A0: +case 0x37A0: +case 0x39A0: +case 0x3BA0: +case 0x3DA0: +case 0x3FA0: +case 0x31A1: +case 0x33A1: +case 0x35A1: +case 0x37A1: +case 0x39A1: +case 0x3BA1: +case 0x3DA1: +case 0x3FA1: +case 0x31A2: +case 0x33A2: +case 0x35A2: +case 0x37A2: +case 0x39A2: +case 0x3BA2: +case 0x3DA2: +case 0x3FA2: +case 0x31A3: +case 0x33A3: +case 0x35A3: +case 0x37A3: +case 0x39A3: +case 0x3BA3: +case 0x3DA3: +case 0x3FA3: +case 0x31A4: +case 0x33A4: +case 0x35A4: +case 0x37A4: +case 0x39A4: +case 0x3BA4: +case 0x3DA4: +case 0x3FA4: +case 0x31A5: +case 0x33A5: +case 0x35A5: +case 0x37A5: +case 0x39A5: +case 0x3BA5: +case 0x3DA5: +case 0x3FA5: +case 0x31A6: +case 0x33A6: +case 0x35A6: +case 0x37A6: +case 0x39A6: +case 0x3BA6: +case 0x3DA6: +case 0x3FA6: + +// MOVEW +case 0x31A0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] - 2; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7]; + DECODE_EXT_WORD + WRITE_WORD_F(adr, res) + POST_IO +} +RET(20) +case 0x31E1: +case 0x31E2: +case 0x31E3: +case 0x31E4: +case 0x31E5: +case 0x31E6: + +// MOVEW +case 0x31E0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] - 2; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(18) +case 0x33E1: +case 0x33E2: +case 0x33E3: +case 0x33E4: +case 0x33E5: +case 0x33E6: + +// MOVEW +case 0x33E0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] - 2; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = (s32)FETCH_LONG; + PC += 4; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(22) +case 0x3EE1: +case 0x3EE2: +case 0x3EE3: +case 0x3EE4: +case 0x3EE5: +case 0x3EE6: + +// MOVEW +case 0x3EE0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] - 2; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[7]; + CPU->A[7] += 2; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(14) +case 0x3F21: +case 0x3F22: +case 0x3F23: +case 0x3F24: +case 0x3F25: +case 0x3F26: + +// MOVEW +case 0x3F20: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] - 2; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(14) +case 0x3228: +case 0x3428: +case 0x3628: +case 0x3828: +case 0x3A28: +case 0x3C28: +case 0x3E28: +case 0x3029: +case 0x3229: +case 0x3429: +case 0x3629: +case 0x3829: +case 0x3A29: +case 0x3C29: +case 0x3E29: +case 0x302A: +case 0x322A: +case 0x342A: +case 0x362A: +case 0x382A: +case 0x3A2A: +case 0x3C2A: +case 0x3E2A: +case 0x302B: +case 0x322B: +case 0x342B: +case 0x362B: +case 0x382B: +case 0x3A2B: +case 0x3C2B: +case 0x3E2B: +case 0x302C: +case 0x322C: +case 0x342C: +case 0x362C: +case 0x382C: +case 0x3A2C: +case 0x3C2C: +case 0x3E2C: +case 0x302D: +case 0x322D: +case 0x342D: +case 0x362D: +case 0x382D: +case 0x3A2D: +case 0x3C2D: +case 0x3E2D: +case 0x302E: +case 0x322E: +case 0x342E: +case 0x362E: +case 0x382E: +case 0x3A2E: +case 0x3C2E: +case 0x3E2E: +case 0x302F: +case 0x322F: +case 0x342F: +case 0x362F: +case 0x382F: +case 0x3A2F: +case 0x3C2F: +case 0x3E2F: + +// MOVEW +case 0x3028: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(12) +case 0x32A8: +case 0x34A8: +case 0x36A8: +case 0x38A8: +case 0x3AA8: +case 0x3CA8: +case 0x3EA8: +case 0x30A9: +case 0x32A9: +case 0x34A9: +case 0x36A9: +case 0x38A9: +case 0x3AA9: +case 0x3CA9: +case 0x3EA9: +case 0x30AA: +case 0x32AA: +case 0x34AA: +case 0x36AA: +case 0x38AA: +case 0x3AAA: +case 0x3CAA: +case 0x3EAA: +case 0x30AB: +case 0x32AB: +case 0x34AB: +case 0x36AB: +case 0x38AB: +case 0x3AAB: +case 0x3CAB: +case 0x3EAB: +case 0x30AC: +case 0x32AC: +case 0x34AC: +case 0x36AC: +case 0x38AC: +case 0x3AAC: +case 0x3CAC: +case 0x3EAC: +case 0x30AD: +case 0x32AD: +case 0x34AD: +case 0x36AD: +case 0x38AD: +case 0x3AAD: +case 0x3CAD: +case 0x3EAD: +case 0x30AE: +case 0x32AE: +case 0x34AE: +case 0x36AE: +case 0x38AE: +case 0x3AAE: +case 0x3CAE: +case 0x3EAE: +case 0x30AF: +case 0x32AF: +case 0x34AF: +case 0x36AF: +case 0x38AF: +case 0x3AAF: +case 0x3CAF: +case 0x3EAF: + +// MOVEW +case 0x30A8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7]; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0x32E8: +case 0x34E8: +case 0x36E8: +case 0x38E8: +case 0x3AE8: +case 0x3CE8: +case 0x30E9: +case 0x32E9: +case 0x34E9: +case 0x36E9: +case 0x38E9: +case 0x3AE9: +case 0x3CE9: +case 0x30EA: +case 0x32EA: +case 0x34EA: +case 0x36EA: +case 0x38EA: +case 0x3AEA: +case 0x3CEA: +case 0x30EB: +case 0x32EB: +case 0x34EB: +case 0x36EB: +case 0x38EB: +case 0x3AEB: +case 0x3CEB: +case 0x30EC: +case 0x32EC: +case 0x34EC: +case 0x36EC: +case 0x38EC: +case 0x3AEC: +case 0x3CEC: +case 0x30ED: +case 0x32ED: +case 0x34ED: +case 0x36ED: +case 0x38ED: +case 0x3AED: +case 0x3CED: +case 0x30EE: +case 0x32EE: +case 0x34EE: +case 0x36EE: +case 0x38EE: +case 0x3AEE: +case 0x3CEE: +case 0x30EF: +case 0x32EF: +case 0x34EF: +case 0x36EF: +case 0x38EF: +case 0x3AEF: +case 0x3CEF: + +// MOVEW +case 0x30E8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7]; + CPU->A[(Opcode >> 9) & 7] += 2; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0x3328: +case 0x3528: +case 0x3728: +case 0x3928: +case 0x3B28: +case 0x3D28: +case 0x3129: +case 0x3329: +case 0x3529: +case 0x3729: +case 0x3929: +case 0x3B29: +case 0x3D29: +case 0x312A: +case 0x332A: +case 0x352A: +case 0x372A: +case 0x392A: +case 0x3B2A: +case 0x3D2A: +case 0x312B: +case 0x332B: +case 0x352B: +case 0x372B: +case 0x392B: +case 0x3B2B: +case 0x3D2B: +case 0x312C: +case 0x332C: +case 0x352C: +case 0x372C: +case 0x392C: +case 0x3B2C: +case 0x3D2C: +case 0x312D: +case 0x332D: +case 0x352D: +case 0x372D: +case 0x392D: +case 0x3B2D: +case 0x3D2D: +case 0x312E: +case 0x332E: +case 0x352E: +case 0x372E: +case 0x392E: +case 0x3B2E: +case 0x3D2E: +case 0x312F: +case 0x332F: +case 0x352F: +case 0x372F: +case 0x392F: +case 0x3B2F: +case 0x3D2F: + +// MOVEW +case 0x3128: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7] - 2; + CPU->A[(Opcode >> 9) & 7] = adr; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0x3368: +case 0x3568: +case 0x3768: +case 0x3968: +case 0x3B68: +case 0x3D68: +case 0x3F68: +case 0x3169: +case 0x3369: +case 0x3569: +case 0x3769: +case 0x3969: +case 0x3B69: +case 0x3D69: +case 0x3F69: +case 0x316A: +case 0x336A: +case 0x356A: +case 0x376A: +case 0x396A: +case 0x3B6A: +case 0x3D6A: +case 0x3F6A: +case 0x316B: +case 0x336B: +case 0x356B: +case 0x376B: +case 0x396B: +case 0x3B6B: +case 0x3D6B: +case 0x3F6B: +case 0x316C: +case 0x336C: +case 0x356C: +case 0x376C: +case 0x396C: +case 0x3B6C: +case 0x3D6C: +case 0x3F6C: +case 0x316D: +case 0x336D: +case 0x356D: +case 0x376D: +case 0x396D: +case 0x3B6D: +case 0x3D6D: +case 0x3F6D: +case 0x316E: +case 0x336E: +case 0x356E: +case 0x376E: +case 0x396E: +case 0x3B6E: +case 0x3D6E: +case 0x3F6E: +case 0x316F: +case 0x336F: +case 0x356F: +case 0x376F: +case 0x396F: +case 0x3B6F: +case 0x3D6F: +case 0x3F6F: + +// MOVEW +case 0x3168: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(20) +case 0x33A8: +case 0x35A8: +case 0x37A8: +case 0x39A8: +case 0x3BA8: +case 0x3DA8: +case 0x3FA8: +case 0x31A9: +case 0x33A9: +case 0x35A9: +case 0x37A9: +case 0x39A9: +case 0x3BA9: +case 0x3DA9: +case 0x3FA9: +case 0x31AA: +case 0x33AA: +case 0x35AA: +case 0x37AA: +case 0x39AA: +case 0x3BAA: +case 0x3DAA: +case 0x3FAA: +case 0x31AB: +case 0x33AB: +case 0x35AB: +case 0x37AB: +case 0x39AB: +case 0x3BAB: +case 0x3DAB: +case 0x3FAB: +case 0x31AC: +case 0x33AC: +case 0x35AC: +case 0x37AC: +case 0x39AC: +case 0x3BAC: +case 0x3DAC: +case 0x3FAC: +case 0x31AD: +case 0x33AD: +case 0x35AD: +case 0x37AD: +case 0x39AD: +case 0x3BAD: +case 0x3DAD: +case 0x3FAD: +case 0x31AE: +case 0x33AE: +case 0x35AE: +case 0x37AE: +case 0x39AE: +case 0x3BAE: +case 0x3DAE: +case 0x3FAE: +case 0x31AF: +case 0x33AF: +case 0x35AF: +case 0x37AF: +case 0x39AF: +case 0x3BAF: +case 0x3DAF: +case 0x3FAF: + +// MOVEW +case 0x31A8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7]; + DECODE_EXT_WORD + WRITE_WORD_F(adr, res) + POST_IO +} +RET(22) +case 0x31E9: +case 0x31EA: +case 0x31EB: +case 0x31EC: +case 0x31ED: +case 0x31EE: +case 0x31EF: + +// MOVEW +case 0x31E8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(20) +case 0x33E9: +case 0x33EA: +case 0x33EB: +case 0x33EC: +case 0x33ED: +case 0x33EE: +case 0x33EF: + +// MOVEW +case 0x33E8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = (s32)FETCH_LONG; + PC += 4; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(24) +case 0x3EE9: +case 0x3EEA: +case 0x3EEB: +case 0x3EEC: +case 0x3EED: +case 0x3EEE: +case 0x3EEF: + +// MOVEW +case 0x3EE8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[7]; + CPU->A[7] += 2; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0x3F29: +case 0x3F2A: +case 0x3F2B: +case 0x3F2C: +case 0x3F2D: +case 0x3F2E: +case 0x3F2F: + +// MOVEW +case 0x3F28: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0x3230: +case 0x3430: +case 0x3630: +case 0x3830: +case 0x3A30: +case 0x3C30: +case 0x3E30: +case 0x3031: +case 0x3231: +case 0x3431: +case 0x3631: +case 0x3831: +case 0x3A31: +case 0x3C31: +case 0x3E31: +case 0x3032: +case 0x3232: +case 0x3432: +case 0x3632: +case 0x3832: +case 0x3A32: +case 0x3C32: +case 0x3E32: +case 0x3033: +case 0x3233: +case 0x3433: +case 0x3633: +case 0x3833: +case 0x3A33: +case 0x3C33: +case 0x3E33: +case 0x3034: +case 0x3234: +case 0x3434: +case 0x3634: +case 0x3834: +case 0x3A34: +case 0x3C34: +case 0x3E34: +case 0x3035: +case 0x3235: +case 0x3435: +case 0x3635: +case 0x3835: +case 0x3A35: +case 0x3C35: +case 0x3E35: +case 0x3036: +case 0x3236: +case 0x3436: +case 0x3636: +case 0x3836: +case 0x3A36: +case 0x3C36: +case 0x3E36: +case 0x3037: +case 0x3237: +case 0x3437: +case 0x3637: +case 0x3837: +case 0x3A37: +case 0x3C37: +case 0x3E37: + +// MOVEW +case 0x3030: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(14) +case 0x32B0: +case 0x34B0: +case 0x36B0: +case 0x38B0: +case 0x3AB0: +case 0x3CB0: +case 0x3EB0: +case 0x30B1: +case 0x32B1: +case 0x34B1: +case 0x36B1: +case 0x38B1: +case 0x3AB1: +case 0x3CB1: +case 0x3EB1: +case 0x30B2: +case 0x32B2: +case 0x34B2: +case 0x36B2: +case 0x38B2: +case 0x3AB2: +case 0x3CB2: +case 0x3EB2: +case 0x30B3: +case 0x32B3: +case 0x34B3: +case 0x36B3: +case 0x38B3: +case 0x3AB3: +case 0x3CB3: +case 0x3EB3: +case 0x30B4: +case 0x32B4: +case 0x34B4: +case 0x36B4: +case 0x38B4: +case 0x3AB4: +case 0x3CB4: +case 0x3EB4: +case 0x30B5: +case 0x32B5: +case 0x34B5: +case 0x36B5: +case 0x38B5: +case 0x3AB5: +case 0x3CB5: +case 0x3EB5: +case 0x30B6: +case 0x32B6: +case 0x34B6: +case 0x36B6: +case 0x38B6: +case 0x3AB6: +case 0x3CB6: +case 0x3EB6: +case 0x30B7: +case 0x32B7: +case 0x34B7: +case 0x36B7: +case 0x38B7: +case 0x3AB7: +case 0x3CB7: +case 0x3EB7: + +// MOVEW +case 0x30B0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7]; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(18) +case 0x32F0: +case 0x34F0: +case 0x36F0: +case 0x38F0: +case 0x3AF0: +case 0x3CF0: +case 0x30F1: +case 0x32F1: +case 0x34F1: +case 0x36F1: +case 0x38F1: +case 0x3AF1: +case 0x3CF1: +case 0x30F2: +case 0x32F2: +case 0x34F2: +case 0x36F2: +case 0x38F2: +case 0x3AF2: +case 0x3CF2: +case 0x30F3: +case 0x32F3: +case 0x34F3: +case 0x36F3: +case 0x38F3: +case 0x3AF3: +case 0x3CF3: +case 0x30F4: +case 0x32F4: +case 0x34F4: +case 0x36F4: +case 0x38F4: +case 0x3AF4: +case 0x3CF4: +case 0x30F5: +case 0x32F5: +case 0x34F5: +case 0x36F5: +case 0x38F5: +case 0x3AF5: +case 0x3CF5: +case 0x30F6: +case 0x32F6: +case 0x34F6: +case 0x36F6: +case 0x38F6: +case 0x3AF6: +case 0x3CF6: +case 0x30F7: +case 0x32F7: +case 0x34F7: +case 0x36F7: +case 0x38F7: +case 0x3AF7: +case 0x3CF7: + +// MOVEW +case 0x30F0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7]; + CPU->A[(Opcode >> 9) & 7] += 2; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(18) +case 0x3330: +case 0x3530: +case 0x3730: +case 0x3930: +case 0x3B30: +case 0x3D30: +case 0x3131: +case 0x3331: +case 0x3531: +case 0x3731: +case 0x3931: +case 0x3B31: +case 0x3D31: +case 0x3132: +case 0x3332: +case 0x3532: +case 0x3732: +case 0x3932: +case 0x3B32: +case 0x3D32: +case 0x3133: +case 0x3333: +case 0x3533: +case 0x3733: +case 0x3933: +case 0x3B33: +case 0x3D33: +case 0x3134: +case 0x3334: +case 0x3534: +case 0x3734: +case 0x3934: +case 0x3B34: +case 0x3D34: +case 0x3135: +case 0x3335: +case 0x3535: +case 0x3735: +case 0x3935: +case 0x3B35: +case 0x3D35: +case 0x3136: +case 0x3336: +case 0x3536: +case 0x3736: +case 0x3936: +case 0x3B36: +case 0x3D36: +case 0x3137: +case 0x3337: +case 0x3537: +case 0x3737: +case 0x3937: +case 0x3B37: +case 0x3D37: + +// MOVEW +case 0x3130: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7] - 2; + CPU->A[(Opcode >> 9) & 7] = adr; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(18) +case 0x3370: +case 0x3570: +case 0x3770: +case 0x3970: +case 0x3B70: +case 0x3D70: +case 0x3F70: +case 0x3171: +case 0x3371: +case 0x3571: +case 0x3771: +case 0x3971: +case 0x3B71: +case 0x3D71: +case 0x3F71: +case 0x3172: +case 0x3372: +case 0x3572: +case 0x3772: +case 0x3972: +case 0x3B72: +case 0x3D72: +case 0x3F72: +case 0x3173: +case 0x3373: +case 0x3573: +case 0x3773: +case 0x3973: +case 0x3B73: +case 0x3D73: +case 0x3F73: +case 0x3174: +case 0x3374: +case 0x3574: +case 0x3774: +case 0x3974: +case 0x3B74: +case 0x3D74: +case 0x3F74: +case 0x3175: +case 0x3375: +case 0x3575: +case 0x3775: +case 0x3975: +case 0x3B75: +case 0x3D75: +case 0x3F75: +case 0x3176: +case 0x3376: +case 0x3576: +case 0x3776: +case 0x3976: +case 0x3B76: +case 0x3D76: +case 0x3F76: +case 0x3177: +case 0x3377: +case 0x3577: +case 0x3777: +case 0x3977: +case 0x3B77: +case 0x3D77: +case 0x3F77: + +// MOVEW +case 0x3170: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(22) +case 0x33B0: +case 0x35B0: +case 0x37B0: +case 0x39B0: +case 0x3BB0: +case 0x3DB0: +case 0x3FB0: +case 0x31B1: +case 0x33B1: +case 0x35B1: +case 0x37B1: +case 0x39B1: +case 0x3BB1: +case 0x3DB1: +case 0x3FB1: +case 0x31B2: +case 0x33B2: +case 0x35B2: +case 0x37B2: +case 0x39B2: +case 0x3BB2: +case 0x3DB2: +case 0x3FB2: +case 0x31B3: +case 0x33B3: +case 0x35B3: +case 0x37B3: +case 0x39B3: +case 0x3BB3: +case 0x3DB3: +case 0x3FB3: +case 0x31B4: +case 0x33B4: +case 0x35B4: +case 0x37B4: +case 0x39B4: +case 0x3BB4: +case 0x3DB4: +case 0x3FB4: +case 0x31B5: +case 0x33B5: +case 0x35B5: +case 0x37B5: +case 0x39B5: +case 0x3BB5: +case 0x3DB5: +case 0x3FB5: +case 0x31B6: +case 0x33B6: +case 0x35B6: +case 0x37B6: +case 0x39B6: +case 0x3BB6: +case 0x3DB6: +case 0x3FB6: +case 0x31B7: +case 0x33B7: +case 0x35B7: +case 0x37B7: +case 0x39B7: +case 0x3BB7: +case 0x3DB7: +case 0x3FB7: + +// MOVEW +case 0x31B0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7]; + DECODE_EXT_WORD + WRITE_WORD_F(adr, res) + POST_IO +} +RET(24) +case 0x31F1: +case 0x31F2: +case 0x31F3: +case 0x31F4: +case 0x31F5: +case 0x31F6: +case 0x31F7: + +// MOVEW +case 0x31F0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(22) +case 0x33F1: +case 0x33F2: +case 0x33F3: +case 0x33F4: +case 0x33F5: +case 0x33F6: +case 0x33F7: + +// MOVEW +case 0x33F0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = (s32)FETCH_LONG; + PC += 4; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(26) +case 0x3EF1: +case 0x3EF2: +case 0x3EF3: +case 0x3EF4: +case 0x3EF5: +case 0x3EF6: +case 0x3EF7: + +// MOVEW +case 0x3EF0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[7]; + CPU->A[7] += 2; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(18) +case 0x3F31: +case 0x3F32: +case 0x3F33: +case 0x3F34: +case 0x3F35: +case 0x3F36: +case 0x3F37: + +// MOVEW +case 0x3F30: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(18) +case 0x3238: +case 0x3438: +case 0x3638: +case 0x3838: +case 0x3A38: +case 0x3C38: +case 0x3E38: + +// MOVEW +case 0x3038: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(12) +case 0x32B8: +case 0x34B8: +case 0x36B8: +case 0x38B8: +case 0x3AB8: +case 0x3CB8: +case 0x3EB8: + +// MOVEW +case 0x30B8: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7]; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0x32F8: +case 0x34F8: +case 0x36F8: +case 0x38F8: +case 0x3AF8: +case 0x3CF8: + +// MOVEW +case 0x30F8: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7]; + CPU->A[(Opcode >> 9) & 7] += 2; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0x3338: +case 0x3538: +case 0x3738: +case 0x3938: +case 0x3B38: +case 0x3D38: + +// MOVEW +case 0x3138: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7] - 2; + CPU->A[(Opcode >> 9) & 7] = adr; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0x3378: +case 0x3578: +case 0x3778: +case 0x3978: +case 0x3B78: +case 0x3D78: +case 0x3F78: + +// MOVEW +case 0x3178: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(20) +case 0x33B8: +case 0x35B8: +case 0x37B8: +case 0x39B8: +case 0x3BB8: +case 0x3DB8: +case 0x3FB8: + +// MOVEW +case 0x31B8: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7]; + DECODE_EXT_WORD + WRITE_WORD_F(adr, res) + POST_IO +} +RET(22) + +// MOVEW +case 0x31F8: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(20) + +// MOVEW +case 0x33F8: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = (s32)FETCH_LONG; + PC += 4; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(24) + +// MOVEW +case 0x3EF8: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[7]; + CPU->A[7] += 2; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) + +// MOVEW +case 0x3F38: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0x3239: +case 0x3439: +case 0x3639: +case 0x3839: +case 0x3A39: +case 0x3C39: +case 0x3E39: + +// MOVEW +case 0x3039: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(16) +case 0x32B9: +case 0x34B9: +case 0x36B9: +case 0x38B9: +case 0x3AB9: +case 0x3CB9: +case 0x3EB9: + +// MOVEW +case 0x30B9: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7]; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(20) +case 0x32F9: +case 0x34F9: +case 0x36F9: +case 0x38F9: +case 0x3AF9: +case 0x3CF9: + +// MOVEW +case 0x30F9: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7]; + CPU->A[(Opcode >> 9) & 7] += 2; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(20) +case 0x3339: +case 0x3539: +case 0x3739: +case 0x3939: +case 0x3B39: +case 0x3D39: + +// MOVEW +case 0x3139: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7] - 2; + CPU->A[(Opcode >> 9) & 7] = adr; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(20) +case 0x3379: +case 0x3579: +case 0x3779: +case 0x3979: +case 0x3B79: +case 0x3D79: +case 0x3F79: + +// MOVEW +case 0x3179: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(24) +case 0x33B9: +case 0x35B9: +case 0x37B9: +case 0x39B9: +case 0x3BB9: +case 0x3DB9: +case 0x3FB9: + +// MOVEW +case 0x31B9: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7]; + DECODE_EXT_WORD + WRITE_WORD_F(adr, res) + POST_IO +} +RET(26) + +// MOVEW +case 0x31F9: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(24) + +// MOVEW +case 0x33F9: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = (s32)FETCH_LONG; + PC += 4; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(28) + +// MOVEW +case 0x3EF9: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[7]; + CPU->A[7] += 2; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(20) + +// MOVEW +case 0x3F39: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(20) +case 0x323A: +case 0x343A: +case 0x363A: +case 0x383A: +case 0x3A3A: +case 0x3C3A: +case 0x3E3A: + +// MOVEW +case 0x303A: +{ + u32 adr; + u32 res; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(12) +case 0x32BA: +case 0x34BA: +case 0x36BA: +case 0x38BA: +case 0x3ABA: +case 0x3CBA: +case 0x3EBA: + +// MOVEW +case 0x30BA: +{ + u32 adr; + u32 res; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7]; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0x32FA: +case 0x34FA: +case 0x36FA: +case 0x38FA: +case 0x3AFA: +case 0x3CFA: + +// MOVEW +case 0x30FA: +{ + u32 adr; + u32 res; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7]; + CPU->A[(Opcode >> 9) & 7] += 2; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0x333A: +case 0x353A: +case 0x373A: +case 0x393A: +case 0x3B3A: +case 0x3D3A: + +// MOVEW +case 0x313A: +{ + u32 adr; + u32 res; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7] - 2; + CPU->A[(Opcode >> 9) & 7] = adr; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0x337A: +case 0x357A: +case 0x377A: +case 0x397A: +case 0x3B7A: +case 0x3D7A: +case 0x3F7A: + +// MOVEW +case 0x317A: +{ + u32 adr; + u32 res; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(20) +case 0x33BA: +case 0x35BA: +case 0x37BA: +case 0x39BA: +case 0x3BBA: +case 0x3DBA: +case 0x3FBA: + +// MOVEW +case 0x31BA: +{ + u32 adr; + u32 res; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7]; + DECODE_EXT_WORD + WRITE_WORD_F(adr, res) + POST_IO +} +RET(22) + +// MOVEW +case 0x31FA: +{ + u32 adr; + u32 res; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(20) + +// MOVEW +case 0x33FA: +{ + u32 adr; + u32 res; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = (s32)FETCH_LONG; + PC += 4; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(24) + +// MOVEW +case 0x3EFA: +{ + u32 adr; + u32 res; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[7]; + CPU->A[7] += 2; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) + +// MOVEW +case 0x3F3A: +{ + u32 adr; + u32 res; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0x323B: +case 0x343B: +case 0x363B: +case 0x383B: +case 0x3A3B: +case 0x3C3B: +case 0x3E3B: + +// MOVEW +case 0x303B: +{ + u32 adr; + u32 res; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(14) +case 0x32BB: +case 0x34BB: +case 0x36BB: +case 0x38BB: +case 0x3ABB: +case 0x3CBB: +case 0x3EBB: + +// MOVEW +case 0x30BB: +{ + u32 adr; + u32 res; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7]; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(18) +case 0x32FB: +case 0x34FB: +case 0x36FB: +case 0x38FB: +case 0x3AFB: +case 0x3CFB: + +// MOVEW +case 0x30FB: +{ + u32 adr; + u32 res; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7]; + CPU->A[(Opcode >> 9) & 7] += 2; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(18) +case 0x333B: +case 0x353B: +case 0x373B: +case 0x393B: +case 0x3B3B: +case 0x3D3B: + +// MOVEW +case 0x313B: +{ + u32 adr; + u32 res; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7] - 2; + CPU->A[(Opcode >> 9) & 7] = adr; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(18) +case 0x337B: +case 0x357B: +case 0x377B: +case 0x397B: +case 0x3B7B: +case 0x3D7B: +case 0x3F7B: + +// MOVEW +case 0x317B: +{ + u32 adr; + u32 res; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(22) +case 0x33BB: +case 0x35BB: +case 0x37BB: +case 0x39BB: +case 0x3BBB: +case 0x3DBB: +case 0x3FBB: + +// MOVEW +case 0x31BB: +{ + u32 adr; + u32 res; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7]; + DECODE_EXT_WORD + WRITE_WORD_F(adr, res) + POST_IO +} +RET(24) + +// MOVEW +case 0x31FB: +{ + u32 adr; + u32 res; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(22) + +// MOVEW +case 0x33FB: +{ + u32 adr; + u32 res; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = (s32)FETCH_LONG; + PC += 4; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(26) + +// MOVEW +case 0x3EFB: +{ + u32 adr; + u32 res; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[7]; + CPU->A[7] += 2; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(18) + +// MOVEW +case 0x3F3B: +{ + u32 adr; + u32 res; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(18) +case 0x323C: +case 0x343C: +case 0x363C: +case 0x383C: +case 0x3A3C: +case 0x3C3C: +case 0x3E3C: + +// MOVEW +case 0x303C: +{ + u32 res; + res = FETCH_WORD; + PC += 2; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; +} +RET(8) +case 0x32BC: +case 0x34BC: +case 0x36BC: +case 0x38BC: +case 0x3ABC: +case 0x3CBC: +case 0x3EBC: + +// MOVEW +case 0x30BC: +{ + u32 adr; + u32 res; + res = FETCH_WORD; + PC += 2; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7]; + PRE_IO + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0x32FC: +case 0x34FC: +case 0x36FC: +case 0x38FC: +case 0x3AFC: +case 0x3CFC: + +// MOVEW +case 0x30FC: +{ + u32 adr; + u32 res; + res = FETCH_WORD; + PC += 2; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7]; + CPU->A[(Opcode >> 9) & 7] += 2; + PRE_IO + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0x333C: +case 0x353C: +case 0x373C: +case 0x393C: +case 0x3B3C: +case 0x3D3C: + +// MOVEW +case 0x313C: +{ + u32 adr; + u32 res; + res = FETCH_WORD; + PC += 2; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7] - 2; + CPU->A[(Opcode >> 9) & 7] = adr; + PRE_IO + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0x337C: +case 0x357C: +case 0x377C: +case 0x397C: +case 0x3B7C: +case 0x3D7C: +case 0x3F7C: + +// MOVEW +case 0x317C: +{ + u32 adr; + u32 res; + res = FETCH_WORD; + PC += 2; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0x33BC: +case 0x35BC: +case 0x37BC: +case 0x39BC: +case 0x3BBC: +case 0x3DBC: +case 0x3FBC: + +// MOVEW +case 0x31BC: +{ + u32 adr; + u32 res; + res = FETCH_WORD; + PC += 2; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7]; + DECODE_EXT_WORD + PRE_IO + WRITE_WORD_F(adr, res) + POST_IO +} +RET(18) + +// MOVEW +case 0x31FC: +{ + u32 adr; + u32 res; + res = FETCH_WORD; + PC += 2; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) + +// MOVEW +case 0x33FC: +{ + u32 adr; + u32 res; + res = FETCH_WORD; + PC += 2; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + WRITE_WORD_F(adr, res) + POST_IO +} +RET(20) + +// MOVEW +case 0x3EFC: +{ + u32 adr; + u32 res; + res = FETCH_WORD; + PC += 2; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) + +// MOVEW +case 0x3F3C: +{ + u32 adr; + u32 res; + res = FETCH_WORD; + PC += 2; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0x321F: +case 0x341F: +case 0x361F: +case 0x381F: +case 0x3A1F: +case 0x3C1F: +case 0x3E1F: + +// MOVEW +case 0x301F: +{ + u32 adr; + u32 res; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(8) +case 0x329F: +case 0x349F: +case 0x369F: +case 0x389F: +case 0x3A9F: +case 0x3C9F: +case 0x3E9F: + +// MOVEW +case 0x309F: +{ + u32 adr; + u32 res; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7]; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0x32DF: +case 0x34DF: +case 0x36DF: +case 0x38DF: +case 0x3ADF: +case 0x3CDF: + +// MOVEW +case 0x30DF: +{ + u32 adr; + u32 res; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7]; + CPU->A[(Opcode >> 9) & 7] += 2; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0x331F: +case 0x351F: +case 0x371F: +case 0x391F: +case 0x3B1F: +case 0x3D1F: + +// MOVEW +case 0x311F: +{ + u32 adr; + u32 res; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7] - 2; + CPU->A[(Opcode >> 9) & 7] = adr; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0x335F: +case 0x355F: +case 0x375F: +case 0x395F: +case 0x3B5F: +case 0x3D5F: +case 0x3F5F: + +// MOVEW +case 0x315F: +{ + u32 adr; + u32 res; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0x339F: +case 0x359F: +case 0x379F: +case 0x399F: +case 0x3B9F: +case 0x3D9F: +case 0x3F9F: + +// MOVEW +case 0x319F: +{ + u32 adr; + u32 res; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7]; + DECODE_EXT_WORD + WRITE_WORD_F(adr, res) + POST_IO +} +RET(18) + +// MOVEW +case 0x31DF: +{ + u32 adr; + u32 res; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) + +// MOVEW +case 0x33DF: +{ + u32 adr; + u32 res; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = (s32)FETCH_LONG; + PC += 4; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(20) + +// MOVEW +case 0x3EDF: +{ + u32 adr; + u32 res; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[7]; + CPU->A[7] += 2; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) + +// MOVEW +case 0x3F1F: +{ + u32 adr; + u32 res; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0x3227: +case 0x3427: +case 0x3627: +case 0x3827: +case 0x3A27: +case 0x3C27: +case 0x3E27: + +// MOVEW +case 0x3027: +{ + u32 adr; + u32 res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(10) +case 0x32A7: +case 0x34A7: +case 0x36A7: +case 0x38A7: +case 0x3AA7: +case 0x3CA7: +case 0x3EA7: + +// MOVEW +case 0x30A7: +{ + u32 adr; + u32 res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7]; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(14) +case 0x32E7: +case 0x34E7: +case 0x36E7: +case 0x38E7: +case 0x3AE7: +case 0x3CE7: + +// MOVEW +case 0x30E7: +{ + u32 adr; + u32 res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7]; + CPU->A[(Opcode >> 9) & 7] += 2; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(14) +case 0x3327: +case 0x3527: +case 0x3727: +case 0x3927: +case 0x3B27: +case 0x3D27: + +// MOVEW +case 0x3127: +{ + u32 adr; + u32 res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7] - 2; + CPU->A[(Opcode >> 9) & 7] = adr; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(14) +case 0x3367: +case 0x3567: +case 0x3767: +case 0x3967: +case 0x3B67: +case 0x3D67: +case 0x3F67: + +// MOVEW +case 0x3167: +{ + u32 adr; + u32 res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(18) +case 0x33A7: +case 0x35A7: +case 0x37A7: +case 0x39A7: +case 0x3BA7: +case 0x3DA7: +case 0x3FA7: + +// MOVEW +case 0x31A7: +{ + u32 adr; + u32 res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[(Opcode >> 9) & 7]; + DECODE_EXT_WORD + WRITE_WORD_F(adr, res) + POST_IO +} +RET(20) + +// MOVEW +case 0x31E7: +{ + u32 adr; + u32 res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(18) + +// MOVEW +case 0x33E7: +{ + u32 adr; + u32 res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = (s32)FETCH_LONG; + PC += 4; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(22) + +// MOVEW +case 0x3EE7: +{ + u32 adr; + u32 res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[7]; + CPU->A[7] += 2; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(14) + +// MOVEW +case 0x3F27: +{ + u32 adr; + u32 res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(14) +case 0x3240: +case 0x3440: +case 0x3640: +case 0x3840: +case 0x3A40: +case 0x3C40: +case 0x3E40: +case 0x3041: +case 0x3241: +case 0x3441: +case 0x3641: +case 0x3841: +case 0x3A41: +case 0x3C41: +case 0x3E41: +case 0x3042: +case 0x3242: +case 0x3442: +case 0x3642: +case 0x3842: +case 0x3A42: +case 0x3C42: +case 0x3E42: +case 0x3043: +case 0x3243: +case 0x3443: +case 0x3643: +case 0x3843: +case 0x3A43: +case 0x3C43: +case 0x3E43: +case 0x3044: +case 0x3244: +case 0x3444: +case 0x3644: +case 0x3844: +case 0x3A44: +case 0x3C44: +case 0x3E44: +case 0x3045: +case 0x3245: +case 0x3445: +case 0x3645: +case 0x3845: +case 0x3A45: +case 0x3C45: +case 0x3E45: +case 0x3046: +case 0x3246: +case 0x3446: +case 0x3646: +case 0x3846: +case 0x3A46: +case 0x3C46: +case 0x3E46: +case 0x3047: +case 0x3247: +case 0x3447: +case 0x3647: +case 0x3847: +case 0x3A47: +case 0x3C47: +case 0x3E47: + +// MOVEAW +case 0x3040: +{ + u32 res; + res = (s32)(s16)CPU->D[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 9) & 7] = res; +} +RET(4) +case 0x3248: +case 0x3448: +case 0x3648: +case 0x3848: +case 0x3A48: +case 0x3C48: +case 0x3E48: +case 0x3049: +case 0x3249: +case 0x3449: +case 0x3649: +case 0x3849: +case 0x3A49: +case 0x3C49: +case 0x3E49: +case 0x304A: +case 0x324A: +case 0x344A: +case 0x364A: +case 0x384A: +case 0x3A4A: +case 0x3C4A: +case 0x3E4A: +case 0x304B: +case 0x324B: +case 0x344B: +case 0x364B: +case 0x384B: +case 0x3A4B: +case 0x3C4B: +case 0x3E4B: +case 0x304C: +case 0x324C: +case 0x344C: +case 0x364C: +case 0x384C: +case 0x3A4C: +case 0x3C4C: +case 0x3E4C: +case 0x304D: +case 0x324D: +case 0x344D: +case 0x364D: +case 0x384D: +case 0x3A4D: +case 0x3C4D: +case 0x3E4D: +case 0x304E: +case 0x324E: +case 0x344E: +case 0x364E: +case 0x384E: +case 0x3A4E: +case 0x3C4E: +case 0x3E4E: +case 0x304F: +case 0x324F: +case 0x344F: +case 0x364F: +case 0x384F: +case 0x3A4F: +case 0x3C4F: +case 0x3E4F: + +// MOVEAW +case 0x3048: +{ + u32 res; + res = (s32)(s16)CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 9) & 7] = res; +} +RET(4) +case 0x3250: +case 0x3450: +case 0x3650: +case 0x3850: +case 0x3A50: +case 0x3C50: +case 0x3E50: +case 0x3051: +case 0x3251: +case 0x3451: +case 0x3651: +case 0x3851: +case 0x3A51: +case 0x3C51: +case 0x3E51: +case 0x3052: +case 0x3252: +case 0x3452: +case 0x3652: +case 0x3852: +case 0x3A52: +case 0x3C52: +case 0x3E52: +case 0x3053: +case 0x3253: +case 0x3453: +case 0x3653: +case 0x3853: +case 0x3A53: +case 0x3C53: +case 0x3E53: +case 0x3054: +case 0x3254: +case 0x3454: +case 0x3654: +case 0x3854: +case 0x3A54: +case 0x3C54: +case 0x3E54: +case 0x3055: +case 0x3255: +case 0x3455: +case 0x3655: +case 0x3855: +case 0x3A55: +case 0x3C55: +case 0x3E55: +case 0x3056: +case 0x3256: +case 0x3456: +case 0x3656: +case 0x3856: +case 0x3A56: +case 0x3C56: +case 0x3E56: +case 0x3057: +case 0x3257: +case 0x3457: +case 0x3657: +case 0x3857: +case 0x3A57: +case 0x3C57: +case 0x3E57: + +// MOVEAW +case 0x3050: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READSX_WORD_F(adr, res) + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(8) +case 0x3258: +case 0x3458: +case 0x3658: +case 0x3858: +case 0x3A58: +case 0x3C58: +case 0x3E58: +case 0x3059: +case 0x3259: +case 0x3459: +case 0x3659: +case 0x3859: +case 0x3A59: +case 0x3C59: +case 0x3E59: +case 0x305A: +case 0x325A: +case 0x345A: +case 0x365A: +case 0x385A: +case 0x3A5A: +case 0x3C5A: +case 0x3E5A: +case 0x305B: +case 0x325B: +case 0x345B: +case 0x365B: +case 0x385B: +case 0x3A5B: +case 0x3C5B: +case 0x3E5B: +case 0x305C: +case 0x325C: +case 0x345C: +case 0x365C: +case 0x385C: +case 0x3A5C: +case 0x3C5C: +case 0x3E5C: +case 0x305D: +case 0x325D: +case 0x345D: +case 0x365D: +case 0x385D: +case 0x3A5D: +case 0x3C5D: +case 0x3E5D: +case 0x305E: +case 0x325E: +case 0x345E: +case 0x365E: +case 0x385E: +case 0x3A5E: +case 0x3C5E: +case 0x3E5E: + +// MOVEAW +case 0x3058: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 2; + PRE_IO + READSX_WORD_F(adr, res) + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(8) +case 0x3260: +case 0x3460: +case 0x3660: +case 0x3860: +case 0x3A60: +case 0x3C60: +case 0x3E60: +case 0x3061: +case 0x3261: +case 0x3461: +case 0x3661: +case 0x3861: +case 0x3A61: +case 0x3C61: +case 0x3E61: +case 0x3062: +case 0x3262: +case 0x3462: +case 0x3662: +case 0x3862: +case 0x3A62: +case 0x3C62: +case 0x3E62: +case 0x3063: +case 0x3263: +case 0x3463: +case 0x3663: +case 0x3863: +case 0x3A63: +case 0x3C63: +case 0x3E63: +case 0x3064: +case 0x3264: +case 0x3464: +case 0x3664: +case 0x3864: +case 0x3A64: +case 0x3C64: +case 0x3E64: +case 0x3065: +case 0x3265: +case 0x3465: +case 0x3665: +case 0x3865: +case 0x3A65: +case 0x3C65: +case 0x3E65: +case 0x3066: +case 0x3266: +case 0x3466: +case 0x3666: +case 0x3866: +case 0x3A66: +case 0x3C66: +case 0x3E66: + +// MOVEAW +case 0x3060: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] - 2; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READSX_WORD_F(adr, res) + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(10) +case 0x3268: +case 0x3468: +case 0x3668: +case 0x3868: +case 0x3A68: +case 0x3C68: +case 0x3E68: +case 0x3069: +case 0x3269: +case 0x3469: +case 0x3669: +case 0x3869: +case 0x3A69: +case 0x3C69: +case 0x3E69: +case 0x306A: +case 0x326A: +case 0x346A: +case 0x366A: +case 0x386A: +case 0x3A6A: +case 0x3C6A: +case 0x3E6A: +case 0x306B: +case 0x326B: +case 0x346B: +case 0x366B: +case 0x386B: +case 0x3A6B: +case 0x3C6B: +case 0x3E6B: +case 0x306C: +case 0x326C: +case 0x346C: +case 0x366C: +case 0x386C: +case 0x3A6C: +case 0x3C6C: +case 0x3E6C: +case 0x306D: +case 0x326D: +case 0x346D: +case 0x366D: +case 0x386D: +case 0x3A6D: +case 0x3C6D: +case 0x3E6D: +case 0x306E: +case 0x326E: +case 0x346E: +case 0x366E: +case 0x386E: +case 0x3A6E: +case 0x3C6E: +case 0x3E6E: +case 0x306F: +case 0x326F: +case 0x346F: +case 0x366F: +case 0x386F: +case 0x3A6F: +case 0x3C6F: +case 0x3E6F: + +// MOVEAW +case 0x3068: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READSX_WORD_F(adr, res) + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(12) +case 0x3270: +case 0x3470: +case 0x3670: +case 0x3870: +case 0x3A70: +case 0x3C70: +case 0x3E70: +case 0x3071: +case 0x3271: +case 0x3471: +case 0x3671: +case 0x3871: +case 0x3A71: +case 0x3C71: +case 0x3E71: +case 0x3072: +case 0x3272: +case 0x3472: +case 0x3672: +case 0x3872: +case 0x3A72: +case 0x3C72: +case 0x3E72: +case 0x3073: +case 0x3273: +case 0x3473: +case 0x3673: +case 0x3873: +case 0x3A73: +case 0x3C73: +case 0x3E73: +case 0x3074: +case 0x3274: +case 0x3474: +case 0x3674: +case 0x3874: +case 0x3A74: +case 0x3C74: +case 0x3E74: +case 0x3075: +case 0x3275: +case 0x3475: +case 0x3675: +case 0x3875: +case 0x3A75: +case 0x3C75: +case 0x3E75: +case 0x3076: +case 0x3276: +case 0x3476: +case 0x3676: +case 0x3876: +case 0x3A76: +case 0x3C76: +case 0x3E76: +case 0x3077: +case 0x3277: +case 0x3477: +case 0x3677: +case 0x3877: +case 0x3A77: +case 0x3C77: +case 0x3E77: + +// MOVEAW +case 0x3070: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READSX_WORD_F(adr, res) + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(14) +case 0x3278: +case 0x3478: +case 0x3678: +case 0x3878: +case 0x3A78: +case 0x3C78: +case 0x3E78: + +// MOVEAW +case 0x3078: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READSX_WORD_F(adr, res) + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(12) +case 0x3279: +case 0x3479: +case 0x3679: +case 0x3879: +case 0x3A79: +case 0x3C79: +case 0x3E79: + +// MOVEAW +case 0x3079: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READSX_WORD_F(adr, res) + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(16) +case 0x327A: +case 0x347A: +case 0x367A: +case 0x387A: +case 0x3A7A: +case 0x3C7A: +case 0x3E7A: + +// MOVEAW +case 0x307A: +{ + u32 adr; + u32 res; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READSX_WORD_F(adr, res) + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(12) +case 0x327B: +case 0x347B: +case 0x367B: +case 0x387B: +case 0x3A7B: +case 0x3C7B: +case 0x3E7B: + +// MOVEAW +case 0x307B: +{ + u32 adr; + u32 res; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READSX_WORD_F(adr, res) + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(14) +case 0x327C: +case 0x347C: +case 0x367C: +case 0x387C: +case 0x3A7C: +case 0x3C7C: +case 0x3E7C: + +// MOVEAW +case 0x307C: +{ + u32 res; + res = (s32)(s16)FETCH_WORD; + PC += 2; + CPU->A[(Opcode >> 9) & 7] = res; +} +RET(8) +case 0x325F: +case 0x345F: +case 0x365F: +case 0x385F: +case 0x3A5F: +case 0x3C5F: +case 0x3E5F: + +// MOVEAW +case 0x305F: +{ + u32 adr; + u32 res; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READSX_WORD_F(adr, res) + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(8) +case 0x3267: +case 0x3467: +case 0x3667: +case 0x3867: +case 0x3A67: +case 0x3C67: +case 0x3E67: + +// MOVEAW +case 0x3067: +{ + u32 adr; + u32 res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READSX_WORD_F(adr, res) + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(10) diff --git a/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68k_op4.inc b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68k_op4.inc new file mode 100644 index 000000000..a983b620a --- /dev/null +++ b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68k_op4.inc @@ -0,0 +1,7508 @@ +case 0x4001: +case 0x4002: +case 0x4003: +case 0x4004: +case 0x4005: +case 0x4006: +case 0x4007: + +// NEGX +case 0x4000: +{ + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 0) & 7]; + res = -src - ((CPU->flag_X >> 8) & 1); + CPU->flag_V = res & src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_notZ |= res & 0xFF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(4) +case 0x4011: +case 0x4012: +case 0x4013: +case 0x4014: +case 0x4015: +case 0x4016: +case 0x4017: + +// NEGX +case 0x4010: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_BYTE_F(adr, src) + res = -src - ((CPU->flag_X >> 8) & 1); + CPU->flag_V = res & src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_notZ |= res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0x4019: +case 0x401A: +case 0x401B: +case 0x401C: +case 0x401D: +case 0x401E: + +// NEGX +case 0x4018: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + PRE_IO + READ_BYTE_F(adr, src) + res = -src - ((CPU->flag_X >> 8) & 1); + CPU->flag_V = res & src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_notZ |= res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0x4021: +case 0x4022: +case 0x4023: +case 0x4024: +case 0x4025: +case 0x4026: + +// NEGX +case 0x4020: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_BYTE_F(adr, src) + res = -src - ((CPU->flag_X >> 8) & 1); + CPU->flag_V = res & src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_notZ |= res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(14) +case 0x4029: +case 0x402A: +case 0x402B: +case 0x402C: +case 0x402D: +case 0x402E: +case 0x402F: + +// NEGX +case 0x4028: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, src) + res = -src - ((CPU->flag_X >> 8) & 1); + CPU->flag_V = res & src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_notZ |= res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0x4031: +case 0x4032: +case 0x4033: +case 0x4034: +case 0x4035: +case 0x4036: +case 0x4037: + +// NEGX +case 0x4030: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, src) + res = -src - ((CPU->flag_X >> 8) & 1); + CPU->flag_V = res & src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_notZ |= res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) + +// NEGX +case 0x4038: +{ + u32 adr; + u32 res; + pointer src; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, src) + res = -src - ((CPU->flag_X >> 8) & 1); + CPU->flag_V = res & src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_notZ |= res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) + +// NEGX +case 0x4039: +{ + u32 adr; + u32 res; + pointer src; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_BYTE_F(adr, src) + res = -src - ((CPU->flag_X >> 8) & 1); + CPU->flag_V = res & src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_notZ |= res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(20) + +// NEGX +case 0x401F: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_BYTE_F(adr, src) + res = -src - ((CPU->flag_X >> 8) & 1); + CPU->flag_V = res & src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_notZ |= res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) + +// NEGX +case 0x4027: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_BYTE_F(adr, src) + res = -src - ((CPU->flag_X >> 8) & 1); + CPU->flag_V = res & src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_notZ |= res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(14) +case 0x4041: +case 0x4042: +case 0x4043: +case 0x4044: +case 0x4045: +case 0x4046: +case 0x4047: + +// NEGX +case 0x4040: +{ + u32 res; + pointer src; + src = (u16)CPU->D[(Opcode >> 0) & 7]; + res = -src - ((CPU->flag_X >> 8) & 1); + CPU->flag_V = (res & src) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ |= res & 0xFFFF; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(4) +case 0x4051: +case 0x4052: +case 0x4053: +case 0x4054: +case 0x4055: +case 0x4056: +case 0x4057: + +// NEGX +case 0x4050: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_WORD_F(adr, src) + res = -src - ((CPU->flag_X >> 8) & 1); + CPU->flag_V = (res & src) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ |= res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0x4059: +case 0x405A: +case 0x405B: +case 0x405C: +case 0x405D: +case 0x405E: + +// NEGX +case 0x4058: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 2; + PRE_IO + READ_WORD_F(adr, src) + res = -src - ((CPU->flag_X >> 8) & 1); + CPU->flag_V = (res & src) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ |= res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0x4061: +case 0x4062: +case 0x4063: +case 0x4064: +case 0x4065: +case 0x4066: + +// NEGX +case 0x4060: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 2; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_WORD_F(adr, src) + res = -src - ((CPU->flag_X >> 8) & 1); + CPU->flag_V = (res & src) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ |= res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(14) +case 0x4069: +case 0x406A: +case 0x406B: +case 0x406C: +case 0x406D: +case 0x406E: +case 0x406F: + +// NEGX +case 0x4068: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, src) + res = -src - ((CPU->flag_X >> 8) & 1); + CPU->flag_V = (res & src) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ |= res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0x4071: +case 0x4072: +case 0x4073: +case 0x4074: +case 0x4075: +case 0x4076: +case 0x4077: + +// NEGX +case 0x4070: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, src) + res = -src - ((CPU->flag_X >> 8) & 1); + CPU->flag_V = (res & src) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ |= res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(18) + +// NEGX +case 0x4078: +{ + u32 adr; + u32 res; + pointer src; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, src) + res = -src - ((CPU->flag_X >> 8) & 1); + CPU->flag_V = (res & src) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ |= res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) + +// NEGX +case 0x4079: +{ + u32 adr; + u32 res; + pointer src; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_WORD_F(adr, src) + res = -src - ((CPU->flag_X >> 8) & 1); + CPU->flag_V = (res & src) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ |= res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(20) + +// NEGX +case 0x405F: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_WORD_F(adr, src) + res = -src - ((CPU->flag_X >> 8) & 1); + CPU->flag_V = (res & src) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ |= res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) + +// NEGX +case 0x4067: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_WORD_F(adr, src) + res = -src - ((CPU->flag_X >> 8) & 1); + CPU->flag_V = (res & src) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ |= res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(14) +case 0x4081: +case 0x4082: +case 0x4083: +case 0x4084: +case 0x4085: +case 0x4086: +case 0x4087: + +// NEGX +case 0x4080: +{ + u32 res; + pointer src; + src = (u32)CPU->D[(Opcode >> 0) & 7]; + res = -src - ((CPU->flag_X >> 8) & 1); + CPU->flag_notZ |= res; + CPU->flag_V = (res & src) >> 24; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(6) +case 0x4091: +case 0x4092: +case 0x4093: +case 0x4094: +case 0x4095: +case 0x4096: +case 0x4097: + +// NEGX +case 0x4090: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_LONG_F(adr, src) + res = -src - ((CPU->flag_X >> 8) & 1); + CPU->flag_notZ |= res; + CPU->flag_V = (res & src) >> 24; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(20) +case 0x4099: +case 0x409A: +case 0x409B: +case 0x409C: +case 0x409D: +case 0x409E: + +// NEGX +case 0x4098: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 4; + PRE_IO + READ_LONG_F(adr, src) + res = -src - ((CPU->flag_X >> 8) & 1); + CPU->flag_notZ |= res; + CPU->flag_V = (res & src) >> 24; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(20) +case 0x40A1: +case 0x40A2: +case 0x40A3: +case 0x40A4: +case 0x40A5: +case 0x40A6: + +// NEGX +case 0x40A0: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 4; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_LONG_F(adr, src) + res = -src - ((CPU->flag_X >> 8) & 1); + CPU->flag_notZ |= res; + CPU->flag_V = (res & src) >> 24; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(22) +case 0x40A9: +case 0x40AA: +case 0x40AB: +case 0x40AC: +case 0x40AD: +case 0x40AE: +case 0x40AF: + +// NEGX +case 0x40A8: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, src) + res = -src - ((CPU->flag_X >> 8) & 1); + CPU->flag_notZ |= res; + CPU->flag_V = (res & src) >> 24; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(24) +case 0x40B1: +case 0x40B2: +case 0x40B3: +case 0x40B4: +case 0x40B5: +case 0x40B6: +case 0x40B7: + +// NEGX +case 0x40B0: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_LONG_F(adr, src) + res = -src - ((CPU->flag_X >> 8) & 1); + CPU->flag_notZ |= res; + CPU->flag_V = (res & src) >> 24; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(26) + +// NEGX +case 0x40B8: +{ + u32 adr; + u32 res; + pointer src; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, src) + res = -src - ((CPU->flag_X >> 8) & 1); + CPU->flag_notZ |= res; + CPU->flag_V = (res & src) >> 24; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(24) + +// NEGX +case 0x40B9: +{ + u32 adr; + u32 res; + pointer src; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_LONG_F(adr, src) + res = -src - ((CPU->flag_X >> 8) & 1); + CPU->flag_notZ |= res; + CPU->flag_V = (res & src) >> 24; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(28) + +// NEGX +case 0x409F: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[7]; + CPU->A[7] += 4; + PRE_IO + READ_LONG_F(adr, src) + res = -src - ((CPU->flag_X >> 8) & 1); + CPU->flag_notZ |= res; + CPU->flag_V = (res & src) >> 24; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(20) + +// NEGX +case 0x40A7: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + PRE_IO + READ_LONG_F(adr, src) + res = -src - ((CPU->flag_X >> 8) & 1); + CPU->flag_notZ |= res; + CPU->flag_V = (res & src) >> 24; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(22) +case 0x4201: +case 0x4202: +case 0x4203: +case 0x4204: +case 0x4205: +case 0x4206: +case 0x4207: + +// CLR +case 0x4200: +{ + u32 res; + res = 0; + CPU->flag_N = CPU->flag_notZ = CPU->flag_V = CPU->flag_C = 0; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(4) +case 0x4211: +case 0x4212: +case 0x4213: +case 0x4214: +case 0x4215: +case 0x4216: +case 0x4217: + +// CLR +case 0x4210: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + res = 0; + CPU->flag_N = CPU->flag_notZ = CPU->flag_V = CPU->flag_C = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0x4219: +case 0x421A: +case 0x421B: +case 0x421C: +case 0x421D: +case 0x421E: + +// CLR +case 0x4218: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + res = 0; + CPU->flag_N = CPU->flag_notZ = CPU->flag_V = CPU->flag_C = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0x4221: +case 0x4222: +case 0x4223: +case 0x4224: +case 0x4225: +case 0x4226: + +// CLR +case 0x4220: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + res = 0; + CPU->flag_N = CPU->flag_notZ = CPU->flag_V = CPU->flag_C = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(14) +case 0x4229: +case 0x422A: +case 0x422B: +case 0x422C: +case 0x422D: +case 0x422E: +case 0x422F: + +// CLR +case 0x4228: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + res = 0; + CPU->flag_N = CPU->flag_notZ = CPU->flag_V = CPU->flag_C = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0x4231: +case 0x4232: +case 0x4233: +case 0x4234: +case 0x4235: +case 0x4236: +case 0x4237: + +// CLR +case 0x4230: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + res = 0; + CPU->flag_N = CPU->flag_notZ = CPU->flag_V = CPU->flag_C = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) + +// CLR +case 0x4238: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + res = 0; + CPU->flag_N = CPU->flag_notZ = CPU->flag_V = CPU->flag_C = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) + +// CLR +case 0x4239: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + res = 0; + CPU->flag_N = CPU->flag_notZ = CPU->flag_V = CPU->flag_C = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(20) + +// CLR +case 0x421F: +{ + u32 adr; + u32 res; + adr = CPU->A[7]; + CPU->A[7] += 2; + res = 0; + CPU->flag_N = CPU->flag_notZ = CPU->flag_V = CPU->flag_C = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) + +// CLR +case 0x4227: +{ + u32 adr; + u32 res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + res = 0; + CPU->flag_N = CPU->flag_notZ = CPU->flag_V = CPU->flag_C = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(14) +case 0x4241: +case 0x4242: +case 0x4243: +case 0x4244: +case 0x4245: +case 0x4246: +case 0x4247: + +// CLR +case 0x4240: +{ + u32 res; + res = 0; + CPU->flag_N = CPU->flag_notZ = CPU->flag_V = CPU->flag_C = 0; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(4) +case 0x4251: +case 0x4252: +case 0x4253: +case 0x4254: +case 0x4255: +case 0x4256: +case 0x4257: + +// CLR +case 0x4250: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + res = 0; + CPU->flag_N = CPU->flag_notZ = CPU->flag_V = CPU->flag_C = 0; + PRE_IO + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0x4259: +case 0x425A: +case 0x425B: +case 0x425C: +case 0x425D: +case 0x425E: + +// CLR +case 0x4258: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 2; + res = 0; + CPU->flag_N = CPU->flag_notZ = CPU->flag_V = CPU->flag_C = 0; + PRE_IO + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0x4261: +case 0x4262: +case 0x4263: +case 0x4264: +case 0x4265: +case 0x4266: + +// CLR +case 0x4260: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] - 2; + CPU->A[(Opcode >> 0) & 7] = adr; + res = 0; + CPU->flag_N = CPU->flag_notZ = CPU->flag_V = CPU->flag_C = 0; + PRE_IO + WRITE_WORD_F(adr, res) + POST_IO +} +RET(14) +case 0x4269: +case 0x426A: +case 0x426B: +case 0x426C: +case 0x426D: +case 0x426E: +case 0x426F: + +// CLR +case 0x4268: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + res = 0; + CPU->flag_N = CPU->flag_notZ = CPU->flag_V = CPU->flag_C = 0; + PRE_IO + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0x4271: +case 0x4272: +case 0x4273: +case 0x4274: +case 0x4275: +case 0x4276: +case 0x4277: + +// CLR +case 0x4270: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + res = 0; + CPU->flag_N = CPU->flag_notZ = CPU->flag_V = CPU->flag_C = 0; + PRE_IO + WRITE_WORD_F(adr, res) + POST_IO +} +RET(18) + +// CLR +case 0x4278: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + res = 0; + CPU->flag_N = CPU->flag_notZ = CPU->flag_V = CPU->flag_C = 0; + PRE_IO + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) + +// CLR +case 0x4279: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + res = 0; + CPU->flag_N = CPU->flag_notZ = CPU->flag_V = CPU->flag_C = 0; + PRE_IO + WRITE_WORD_F(adr, res) + POST_IO +} +RET(20) + +// CLR +case 0x425F: +{ + u32 adr; + u32 res; + adr = CPU->A[7]; + CPU->A[7] += 2; + res = 0; + CPU->flag_N = CPU->flag_notZ = CPU->flag_V = CPU->flag_C = 0; + PRE_IO + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) + +// CLR +case 0x4267: +{ + u32 adr; + u32 res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + res = 0; + CPU->flag_N = CPU->flag_notZ = CPU->flag_V = CPU->flag_C = 0; + PRE_IO + WRITE_WORD_F(adr, res) + POST_IO +} +RET(14) +case 0x4281: +case 0x4282: +case 0x4283: +case 0x4284: +case 0x4285: +case 0x4286: +case 0x4287: + +// CLR +case 0x4280: +{ + u32 res; + res = 0; + CPU->flag_N = CPU->flag_notZ = CPU->flag_V = CPU->flag_C = 0; + *((u32*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(6) +case 0x4291: +case 0x4292: +case 0x4293: +case 0x4294: +case 0x4295: +case 0x4296: +case 0x4297: + +// CLR +case 0x4290: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + res = 0; + CPU->flag_N = CPU->flag_notZ = CPU->flag_V = CPU->flag_C = 0; + PRE_IO + WRITE_LONG_F(adr, res) + POST_IO +} +RET(20) +case 0x4299: +case 0x429A: +case 0x429B: +case 0x429C: +case 0x429D: +case 0x429E: + +// CLR +case 0x4298: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 4; + res = 0; + CPU->flag_N = CPU->flag_notZ = CPU->flag_V = CPU->flag_C = 0; + PRE_IO + WRITE_LONG_F(adr, res) + POST_IO +} +RET(20) +case 0x42A1: +case 0x42A2: +case 0x42A3: +case 0x42A4: +case 0x42A5: +case 0x42A6: + +// CLR +case 0x42A0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] - 4; + CPU->A[(Opcode >> 0) & 7] = adr; + res = 0; + CPU->flag_N = CPU->flag_notZ = CPU->flag_V = CPU->flag_C = 0; + PRE_IO + WRITE_LONG_F(adr, res) + POST_IO +} +RET(22) +case 0x42A9: +case 0x42AA: +case 0x42AB: +case 0x42AC: +case 0x42AD: +case 0x42AE: +case 0x42AF: + +// CLR +case 0x42A8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + res = 0; + CPU->flag_N = CPU->flag_notZ = CPU->flag_V = CPU->flag_C = 0; + PRE_IO + WRITE_LONG_F(adr, res) + POST_IO +} +RET(24) +case 0x42B1: +case 0x42B2: +case 0x42B3: +case 0x42B4: +case 0x42B5: +case 0x42B6: +case 0x42B7: + +// CLR +case 0x42B0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + res = 0; + CPU->flag_N = CPU->flag_notZ = CPU->flag_V = CPU->flag_C = 0; + PRE_IO + WRITE_LONG_F(adr, res) + POST_IO +} +RET(26) + +// CLR +case 0x42B8: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + res = 0; + CPU->flag_N = CPU->flag_notZ = CPU->flag_V = CPU->flag_C = 0; + PRE_IO + WRITE_LONG_F(adr, res) + POST_IO +} +RET(24) + +// CLR +case 0x42B9: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + res = 0; + CPU->flag_N = CPU->flag_notZ = CPU->flag_V = CPU->flag_C = 0; + PRE_IO + WRITE_LONG_F(adr, res) + POST_IO +} +RET(28) + +// CLR +case 0x429F: +{ + u32 adr; + u32 res; + adr = CPU->A[7]; + CPU->A[7] += 4; + res = 0; + CPU->flag_N = CPU->flag_notZ = CPU->flag_V = CPU->flag_C = 0; + PRE_IO + WRITE_LONG_F(adr, res) + POST_IO +} +RET(20) + +// CLR +case 0x42A7: +{ + u32 adr; + u32 res; + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + res = 0; + CPU->flag_N = CPU->flag_notZ = CPU->flag_V = CPU->flag_C = 0; + PRE_IO + WRITE_LONG_F(adr, res) + POST_IO +} +RET(22) +case 0x4401: +case 0x4402: +case 0x4403: +case 0x4404: +case 0x4405: +case 0x4406: +case 0x4407: + +// NEG +case 0x4400: +{ + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 0) & 7]; + res = -src; + CPU->flag_V = res & src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_notZ = res & 0xFF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(4) +case 0x4411: +case 0x4412: +case 0x4413: +case 0x4414: +case 0x4415: +case 0x4416: +case 0x4417: + +// NEG +case 0x4410: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_BYTE_F(adr, src) + res = -src; + CPU->flag_V = res & src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0x4419: +case 0x441A: +case 0x441B: +case 0x441C: +case 0x441D: +case 0x441E: + +// NEG +case 0x4418: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + PRE_IO + READ_BYTE_F(adr, src) + res = -src; + CPU->flag_V = res & src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0x4421: +case 0x4422: +case 0x4423: +case 0x4424: +case 0x4425: +case 0x4426: + +// NEG +case 0x4420: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_BYTE_F(adr, src) + res = -src; + CPU->flag_V = res & src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(14) +case 0x4429: +case 0x442A: +case 0x442B: +case 0x442C: +case 0x442D: +case 0x442E: +case 0x442F: + +// NEG +case 0x4428: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, src) + res = -src; + CPU->flag_V = res & src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0x4431: +case 0x4432: +case 0x4433: +case 0x4434: +case 0x4435: +case 0x4436: +case 0x4437: + +// NEG +case 0x4430: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, src) + res = -src; + CPU->flag_V = res & src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) + +// NEG +case 0x4438: +{ + u32 adr; + u32 res; + pointer src; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, src) + res = -src; + CPU->flag_V = res & src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) + +// NEG +case 0x4439: +{ + u32 adr; + u32 res; + pointer src; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_BYTE_F(adr, src) + res = -src; + CPU->flag_V = res & src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(20) + +// NEG +case 0x441F: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_BYTE_F(adr, src) + res = -src; + CPU->flag_V = res & src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) + +// NEG +case 0x4427: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_BYTE_F(adr, src) + res = -src; + CPU->flag_V = res & src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(14) +case 0x4441: +case 0x4442: +case 0x4443: +case 0x4444: +case 0x4445: +case 0x4446: +case 0x4447: + +// NEG +case 0x4440: +{ + u32 res; + pointer src; + src = (u16)CPU->D[(Opcode >> 0) & 7]; + res = -src; + CPU->flag_V = (res & src) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(4) +case 0x4451: +case 0x4452: +case 0x4453: +case 0x4454: +case 0x4455: +case 0x4456: +case 0x4457: + +// NEG +case 0x4450: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_WORD_F(adr, src) + res = -src; + CPU->flag_V = (res & src) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0x4459: +case 0x445A: +case 0x445B: +case 0x445C: +case 0x445D: +case 0x445E: + +// NEG +case 0x4458: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 2; + PRE_IO + READ_WORD_F(adr, src) + res = -src; + CPU->flag_V = (res & src) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0x4461: +case 0x4462: +case 0x4463: +case 0x4464: +case 0x4465: +case 0x4466: + +// NEG +case 0x4460: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 2; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_WORD_F(adr, src) + res = -src; + CPU->flag_V = (res & src) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(14) +case 0x4469: +case 0x446A: +case 0x446B: +case 0x446C: +case 0x446D: +case 0x446E: +case 0x446F: + +// NEG +case 0x4468: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, src) + res = -src; + CPU->flag_V = (res & src) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0x4471: +case 0x4472: +case 0x4473: +case 0x4474: +case 0x4475: +case 0x4476: +case 0x4477: + +// NEG +case 0x4470: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, src) + res = -src; + CPU->flag_V = (res & src) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(18) + +// NEG +case 0x4478: +{ + u32 adr; + u32 res; + pointer src; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, src) + res = -src; + CPU->flag_V = (res & src) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) + +// NEG +case 0x4479: +{ + u32 adr; + u32 res; + pointer src; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_WORD_F(adr, src) + res = -src; + CPU->flag_V = (res & src) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(20) + +// NEG +case 0x445F: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_WORD_F(adr, src) + res = -src; + CPU->flag_V = (res & src) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) + +// NEG +case 0x4467: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_WORD_F(adr, src) + res = -src; + CPU->flag_V = (res & src) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(14) +case 0x4481: +case 0x4482: +case 0x4483: +case 0x4484: +case 0x4485: +case 0x4486: +case 0x4487: + +// NEG +case 0x4480: +{ + u32 res; + pointer src; + src = (u32)CPU->D[(Opcode >> 0) & 7]; + res = -src; + CPU->flag_notZ = res; + CPU->flag_V = (res & src) >> 24; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(6) +case 0x4491: +case 0x4492: +case 0x4493: +case 0x4494: +case 0x4495: +case 0x4496: +case 0x4497: + +// NEG +case 0x4490: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_LONG_F(adr, src) + res = -src; + CPU->flag_notZ = res; + CPU->flag_V = (res & src) >> 24; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(20) +case 0x4499: +case 0x449A: +case 0x449B: +case 0x449C: +case 0x449D: +case 0x449E: + +// NEG +case 0x4498: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 4; + PRE_IO + READ_LONG_F(adr, src) + res = -src; + CPU->flag_notZ = res; + CPU->flag_V = (res & src) >> 24; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(20) +case 0x44A1: +case 0x44A2: +case 0x44A3: +case 0x44A4: +case 0x44A5: +case 0x44A6: + +// NEG +case 0x44A0: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 4; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_LONG_F(adr, src) + res = -src; + CPU->flag_notZ = res; + CPU->flag_V = (res & src) >> 24; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(22) +case 0x44A9: +case 0x44AA: +case 0x44AB: +case 0x44AC: +case 0x44AD: +case 0x44AE: +case 0x44AF: + +// NEG +case 0x44A8: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, src) + res = -src; + CPU->flag_notZ = res; + CPU->flag_V = (res & src) >> 24; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(24) +case 0x44B1: +case 0x44B2: +case 0x44B3: +case 0x44B4: +case 0x44B5: +case 0x44B6: +case 0x44B7: + +// NEG +case 0x44B0: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_LONG_F(adr, src) + res = -src; + CPU->flag_notZ = res; + CPU->flag_V = (res & src) >> 24; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(26) + +// NEG +case 0x44B8: +{ + u32 adr; + u32 res; + pointer src; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, src) + res = -src; + CPU->flag_notZ = res; + CPU->flag_V = (res & src) >> 24; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(24) + +// NEG +case 0x44B9: +{ + u32 adr; + u32 res; + pointer src; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_LONG_F(adr, src) + res = -src; + CPU->flag_notZ = res; + CPU->flag_V = (res & src) >> 24; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(28) + +// NEG +case 0x449F: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[7]; + CPU->A[7] += 4; + PRE_IO + READ_LONG_F(adr, src) + res = -src; + CPU->flag_notZ = res; + CPU->flag_V = (res & src) >> 24; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(20) + +// NEG +case 0x44A7: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + PRE_IO + READ_LONG_F(adr, src) + res = -src; + CPU->flag_notZ = res; + CPU->flag_V = (res & src) >> 24; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(22) +case 0x4601: +case 0x4602: +case 0x4603: +case 0x4604: +case 0x4605: +case 0x4606: +case 0x4607: + +// NOT +case 0x4600: +{ + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 0) & 7]; + res = ~src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_N = res; + CPU->flag_notZ = res & 0xFF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(4) +case 0x4611: +case 0x4612: +case 0x4613: +case 0x4614: +case 0x4615: +case 0x4616: +case 0x4617: + +// NOT +case 0x4610: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_BYTE_F(adr, src) + res = ~src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_N = res; + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0x4619: +case 0x461A: +case 0x461B: +case 0x461C: +case 0x461D: +case 0x461E: + +// NOT +case 0x4618: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + PRE_IO + READ_BYTE_F(adr, src) + res = ~src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_N = res; + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0x4621: +case 0x4622: +case 0x4623: +case 0x4624: +case 0x4625: +case 0x4626: + +// NOT +case 0x4620: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_BYTE_F(adr, src) + res = ~src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_N = res; + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(14) +case 0x4629: +case 0x462A: +case 0x462B: +case 0x462C: +case 0x462D: +case 0x462E: +case 0x462F: + +// NOT +case 0x4628: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, src) + res = ~src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_N = res; + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0x4631: +case 0x4632: +case 0x4633: +case 0x4634: +case 0x4635: +case 0x4636: +case 0x4637: + +// NOT +case 0x4630: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, src) + res = ~src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_N = res; + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) + +// NOT +case 0x4638: +{ + u32 adr; + u32 res; + pointer src; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, src) + res = ~src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_N = res; + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) + +// NOT +case 0x4639: +{ + u32 adr; + u32 res; + pointer src; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_BYTE_F(adr, src) + res = ~src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_N = res; + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(20) + +// NOT +case 0x461F: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_BYTE_F(adr, src) + res = ~src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_N = res; + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) + +// NOT +case 0x4627: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_BYTE_F(adr, src) + res = ~src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_N = res; + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(14) +case 0x4641: +case 0x4642: +case 0x4643: +case 0x4644: +case 0x4645: +case 0x4646: +case 0x4647: + +// NOT +case 0x4640: +{ + u32 res; + pointer src; + src = (u16)CPU->D[(Opcode >> 0) & 7]; + res = ~src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res & 0xFFFF; + CPU->flag_N = res >> 8; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(4) +case 0x4651: +case 0x4652: +case 0x4653: +case 0x4654: +case 0x4655: +case 0x4656: +case 0x4657: + +// NOT +case 0x4650: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_WORD_F(adr, src) + res = ~src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res & 0xFFFF; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0x4659: +case 0x465A: +case 0x465B: +case 0x465C: +case 0x465D: +case 0x465E: + +// NOT +case 0x4658: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 2; + PRE_IO + READ_WORD_F(adr, src) + res = ~src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res & 0xFFFF; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0x4661: +case 0x4662: +case 0x4663: +case 0x4664: +case 0x4665: +case 0x4666: + +// NOT +case 0x4660: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 2; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_WORD_F(adr, src) + res = ~src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res & 0xFFFF; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(14) +case 0x4669: +case 0x466A: +case 0x466B: +case 0x466C: +case 0x466D: +case 0x466E: +case 0x466F: + +// NOT +case 0x4668: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, src) + res = ~src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res & 0xFFFF; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0x4671: +case 0x4672: +case 0x4673: +case 0x4674: +case 0x4675: +case 0x4676: +case 0x4677: + +// NOT +case 0x4670: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, src) + res = ~src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res & 0xFFFF; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(18) + +// NOT +case 0x4678: +{ + u32 adr; + u32 res; + pointer src; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, src) + res = ~src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res & 0xFFFF; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) + +// NOT +case 0x4679: +{ + u32 adr; + u32 res; + pointer src; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_WORD_F(adr, src) + res = ~src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res & 0xFFFF; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(20) + +// NOT +case 0x465F: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_WORD_F(adr, src) + res = ~src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res & 0xFFFF; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) + +// NOT +case 0x4667: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_WORD_F(adr, src) + res = ~src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res & 0xFFFF; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(14) +case 0x4681: +case 0x4682: +case 0x4683: +case 0x4684: +case 0x4685: +case 0x4686: +case 0x4687: + +// NOT +case 0x4680: +{ + u32 res; + pointer src; + src = (u32)CPU->D[(Opcode >> 0) & 7]; + res = ~src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(6) +case 0x4691: +case 0x4692: +case 0x4693: +case 0x4694: +case 0x4695: +case 0x4696: +case 0x4697: + +// NOT +case 0x4690: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_LONG_F(adr, src) + res = ~src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(20) +case 0x4699: +case 0x469A: +case 0x469B: +case 0x469C: +case 0x469D: +case 0x469E: + +// NOT +case 0x4698: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 4; + PRE_IO + READ_LONG_F(adr, src) + res = ~src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(20) +case 0x46A1: +case 0x46A2: +case 0x46A3: +case 0x46A4: +case 0x46A5: +case 0x46A6: + +// NOT +case 0x46A0: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 4; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_LONG_F(adr, src) + res = ~src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(22) +case 0x46A9: +case 0x46AA: +case 0x46AB: +case 0x46AC: +case 0x46AD: +case 0x46AE: +case 0x46AF: + +// NOT +case 0x46A8: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, src) + res = ~src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(24) +case 0x46B1: +case 0x46B2: +case 0x46B3: +case 0x46B4: +case 0x46B5: +case 0x46B6: +case 0x46B7: + +// NOT +case 0x46B0: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_LONG_F(adr, src) + res = ~src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(26) + +// NOT +case 0x46B8: +{ + u32 adr; + u32 res; + pointer src; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, src) + res = ~src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(24) + +// NOT +case 0x46B9: +{ + u32 adr; + u32 res; + pointer src; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_LONG_F(adr, src) + res = ~src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(28) + +// NOT +case 0x469F: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[7]; + CPU->A[7] += 4; + PRE_IO + READ_LONG_F(adr, src) + res = ~src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(20) + +// NOT +case 0x46A7: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + PRE_IO + READ_LONG_F(adr, src) + res = ~src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(22) +case 0x40C1: +case 0x40C2: +case 0x40C3: +case 0x40C4: +case 0x40C5: +case 0x40C6: +case 0x40C7: + +// MOVESRa +case 0x40C0: +{ + u32 res; + res = GET_SR; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(6) +case 0x40D1: +case 0x40D2: +case 0x40D3: +case 0x40D4: +case 0x40D5: +case 0x40D6: +case 0x40D7: + +// MOVESRa +case 0x40D0: +{ + u32 adr; + u32 res; + res = GET_SR; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0x40D9: +case 0x40DA: +case 0x40DB: +case 0x40DC: +case 0x40DD: +case 0x40DE: + +// MOVESRa +case 0x40D8: +{ + u32 adr; + u32 res; + res = GET_SR; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 2; + PRE_IO + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0x40E1: +case 0x40E2: +case 0x40E3: +case 0x40E4: +case 0x40E5: +case 0x40E6: + +// MOVESRa +case 0x40E0: +{ + u32 adr; + u32 res; + res = GET_SR; + adr = CPU->A[(Opcode >> 0) & 7] - 2; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + WRITE_WORD_F(adr, res) + POST_IO +} +RET(14) +case 0x40E9: +case 0x40EA: +case 0x40EB: +case 0x40EC: +case 0x40ED: +case 0x40EE: +case 0x40EF: + +// MOVESRa +case 0x40E8: +{ + u32 adr; + u32 res; + res = GET_SR; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0x40F1: +case 0x40F2: +case 0x40F3: +case 0x40F4: +case 0x40F5: +case 0x40F6: +case 0x40F7: + +// MOVESRa +case 0x40F0: +{ + u32 adr; + u32 res; + res = GET_SR; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + WRITE_WORD_F(adr, res) + POST_IO +} +RET(18) + +// MOVESRa +case 0x40F8: +{ + u32 adr; + u32 res; + res = GET_SR; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) + +// MOVESRa +case 0x40F9: +{ + u32 adr; + u32 res; + res = GET_SR; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + WRITE_WORD_F(adr, res) + POST_IO +} +RET(20) + +// MOVESRa +case 0x40DF: +{ + u32 adr; + u32 res; + res = GET_SR; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) + +// MOVESRa +case 0x40E7: +{ + u32 adr; + u32 res; + res = GET_SR; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + WRITE_WORD_F(adr, res) + POST_IO +} +RET(14) +case 0x44C1: +case 0x44C2: +case 0x44C3: +case 0x44C4: +case 0x44C5: +case 0x44C6: +case 0x44C7: + +// MOVEaCCR +case 0x44C0: +{ + u32 res; + res = (u16)CPU->D[(Opcode >> 0) & 7]; + SET_CCR(res) +} +RET(12) +case 0x44D1: +case 0x44D2: +case 0x44D3: +case 0x44D4: +case 0x44D5: +case 0x44D6: +case 0x44D7: + +// MOVEaCCR +case 0x44D0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_WORD_F(adr, res) + SET_CCR(res) + POST_IO +} +RET(16) +case 0x44D9: +case 0x44DA: +case 0x44DB: +case 0x44DC: +case 0x44DD: +case 0x44DE: + +// MOVEaCCR +case 0x44D8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 2; + PRE_IO + READ_WORD_F(adr, res) + SET_CCR(res) + POST_IO +} +RET(16) +case 0x44E1: +case 0x44E2: +case 0x44E3: +case 0x44E4: +case 0x44E5: +case 0x44E6: + +// MOVEaCCR +case 0x44E0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] - 2; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_WORD_F(adr, res) + SET_CCR(res) + POST_IO +} +RET(18) +case 0x44E9: +case 0x44EA: +case 0x44EB: +case 0x44EC: +case 0x44ED: +case 0x44EE: +case 0x44EF: + +// MOVEaCCR +case 0x44E8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, res) + SET_CCR(res) + POST_IO +} +RET(20) +case 0x44F1: +case 0x44F2: +case 0x44F3: +case 0x44F4: +case 0x44F5: +case 0x44F6: +case 0x44F7: + +// MOVEaCCR +case 0x44F0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, res) + SET_CCR(res) + POST_IO +} +RET(22) + +// MOVEaCCR +case 0x44F8: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, res) + SET_CCR(res) + POST_IO +} +RET(20) + +// MOVEaCCR +case 0x44F9: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_WORD_F(adr, res) + SET_CCR(res) + POST_IO +} +RET(24) + +// MOVEaCCR +case 0x44FA: +{ + u32 adr; + u32 res; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, res) + SET_CCR(res) + POST_IO +} +RET(20) + +// MOVEaCCR +case 0x44FB: +{ + u32 adr; + u32 res; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, res) + SET_CCR(res) + POST_IO +} +RET(22) + +// MOVEaCCR +case 0x44FC: +{ + u32 res; + res = FETCH_WORD; + PC += 2; + SET_CCR(res) +} +RET(16) + +// MOVEaCCR +case 0x44DF: +{ + u32 adr; + u32 res; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_WORD_F(adr, res) + SET_CCR(res) + POST_IO +} +RET(16) + +// MOVEaCCR +case 0x44E7: +{ + u32 adr; + u32 res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_WORD_F(adr, res) + SET_CCR(res) + POST_IO +} +RET(18) +case 0x46C1: +case 0x46C2: +case 0x46C3: +case 0x46C4: +case 0x46C5: +case 0x46C6: +case 0x46C7: + +// MOVEaSR +case 0x46C0: +{ + u32 res; + if (CPU->flag_S) + { + res = (u16)CPU->D[(Opcode >> 0) & 7]; + SET_SR(res) + if (!CPU->flag_S) + { + res = CPU->A[7]; + CPU->A[7] = CPU->USP; + CPU->USP = res; + } + } + else + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + res = C68K_PRIVILEGE_VIOLATION_EX; + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + } +} +POST_IO +CCnt -= 12; +goto C68k_Exec_End; +case 0x46D1: +case 0x46D2: +case 0x46D3: +case 0x46D4: +case 0x46D5: +case 0x46D6: +case 0x46D7: + +// MOVEaSR +case 0x46D0: +{ + u32 adr; + u32 res; + if (CPU->flag_S) + { + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_WORD_F(adr, res) + SET_SR(res) + if (!CPU->flag_S) + { + res = CPU->A[7]; + CPU->A[7] = CPU->USP; + CPU->USP = res; + } + } + else + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + res = C68K_PRIVILEGE_VIOLATION_EX; + POST_IO + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + } +} +POST_IO +CCnt -= 16; +goto C68k_Exec_End; +case 0x46D9: +case 0x46DA: +case 0x46DB: +case 0x46DC: +case 0x46DD: +case 0x46DE: + +// MOVEaSR +case 0x46D8: +{ + u32 adr; + u32 res; + if (CPU->flag_S) + { + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 2; + PRE_IO + READ_WORD_F(adr, res) + SET_SR(res) + if (!CPU->flag_S) + { + res = CPU->A[7]; + CPU->A[7] = CPU->USP; + CPU->USP = res; + } + } + else + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + res = C68K_PRIVILEGE_VIOLATION_EX; + POST_IO + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + } +} +POST_IO +CCnt -= 16; +goto C68k_Exec_End; +case 0x46E1: +case 0x46E2: +case 0x46E3: +case 0x46E4: +case 0x46E5: +case 0x46E6: + +// MOVEaSR +case 0x46E0: +{ + u32 adr; + u32 res; + if (CPU->flag_S) + { + adr = CPU->A[(Opcode >> 0) & 7] - 2; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_WORD_F(adr, res) + SET_SR(res) + if (!CPU->flag_S) + { + res = CPU->A[7]; + CPU->A[7] = CPU->USP; + CPU->USP = res; + } + } + else + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + res = C68K_PRIVILEGE_VIOLATION_EX; + POST_IO + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + } +} +POST_IO +CCnt -= 18; +goto C68k_Exec_End; +case 0x46E9: +case 0x46EA: +case 0x46EB: +case 0x46EC: +case 0x46ED: +case 0x46EE: +case 0x46EF: + +// MOVEaSR +case 0x46E8: +{ + u32 adr; + u32 res; + if (CPU->flag_S) + { + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, res) + SET_SR(res) + if (!CPU->flag_S) + { + res = CPU->A[7]; + CPU->A[7] = CPU->USP; + CPU->USP = res; + } + } + else + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + res = C68K_PRIVILEGE_VIOLATION_EX; + POST_IO + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + } +} +POST_IO +CCnt -= 20; +goto C68k_Exec_End; +case 0x46F1: +case 0x46F2: +case 0x46F3: +case 0x46F4: +case 0x46F5: +case 0x46F6: +case 0x46F7: + +// MOVEaSR +case 0x46F0: +{ + u32 adr; + u32 res; + if (CPU->flag_S) + { + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, res) + SET_SR(res) + if (!CPU->flag_S) + { + res = CPU->A[7]; + CPU->A[7] = CPU->USP; + CPU->USP = res; + } + } + else + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + res = C68K_PRIVILEGE_VIOLATION_EX; + POST_IO + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + } +} +POST_IO +CCnt -= 22; +goto C68k_Exec_End; + +// MOVEaSR +case 0x46F8: +{ + u32 adr; + u32 res; + if (CPU->flag_S) + { + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, res) + SET_SR(res) + if (!CPU->flag_S) + { + res = CPU->A[7]; + CPU->A[7] = CPU->USP; + CPU->USP = res; + } + } + else + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + res = C68K_PRIVILEGE_VIOLATION_EX; + POST_IO + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + } +} +POST_IO +CCnt -= 20; +goto C68k_Exec_End; + +// MOVEaSR +case 0x46F9: +{ + u32 adr; + u32 res; + if (CPU->flag_S) + { + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_WORD_F(adr, res) + SET_SR(res) + if (!CPU->flag_S) + { + res = CPU->A[7]; + CPU->A[7] = CPU->USP; + CPU->USP = res; + } + } + else + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + res = C68K_PRIVILEGE_VIOLATION_EX; + POST_IO + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + } +} +POST_IO +CCnt -= 24; +goto C68k_Exec_End; + +// MOVEaSR +case 0x46FA: +{ + u32 adr; + u32 res; + if (CPU->flag_S) + { + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, res) + SET_SR(res) + if (!CPU->flag_S) + { + res = CPU->A[7]; + CPU->A[7] = CPU->USP; + CPU->USP = res; + } + } + else + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + res = C68K_PRIVILEGE_VIOLATION_EX; + POST_IO + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + } +} +POST_IO +CCnt -= 20; +goto C68k_Exec_End; + +// MOVEaSR +case 0x46FB: +{ + u32 adr; + u32 res; + if (CPU->flag_S) + { + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, res) + SET_SR(res) + if (!CPU->flag_S) + { + res = CPU->A[7]; + CPU->A[7] = CPU->USP; + CPU->USP = res; + } + } + else + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + res = C68K_PRIVILEGE_VIOLATION_EX; + POST_IO + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + } +} +POST_IO +CCnt -= 22; +goto C68k_Exec_End; + +// MOVEaSR +case 0x46FC: +{ + u32 res; + if (CPU->flag_S) + { + res = FETCH_WORD; + PC += 2; + SET_SR(res) + if (!CPU->flag_S) + { + res = CPU->A[7]; + CPU->A[7] = CPU->USP; + CPU->USP = res; + } + } + else + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + res = C68K_PRIVILEGE_VIOLATION_EX; + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + } +} +POST_IO +CCnt -= 16; +goto C68k_Exec_End; + +// MOVEaSR +case 0x46DF: +{ + u32 adr; + u32 res; + if (CPU->flag_S) + { + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_WORD_F(adr, res) + SET_SR(res) + if (!CPU->flag_S) + { + res = CPU->A[7]; + CPU->A[7] = CPU->USP; + CPU->USP = res; + } + } + else + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + res = C68K_PRIVILEGE_VIOLATION_EX; + POST_IO + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + } +} +POST_IO +CCnt -= 16; +goto C68k_Exec_End; + +// MOVEaSR +case 0x46E7: +{ + u32 adr; + u32 res; + if (CPU->flag_S) + { + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_WORD_F(adr, res) + SET_SR(res) + if (!CPU->flag_S) + { + res = CPU->A[7]; + CPU->A[7] = CPU->USP; + CPU->USP = res; + } + } + else + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + res = C68K_PRIVILEGE_VIOLATION_EX; + POST_IO + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + } +} +POST_IO +CCnt -= 18; +goto C68k_Exec_End; +case 0x4801: +case 0x4802: +case 0x4803: +case 0x4804: +case 0x4805: +case 0x4806: +case 0x4807: + +// NBCD +case 0x4800: +{ + u32 res; + res = (u8)CPU->D[(Opcode >> 0) & 7]; + res = 0x9a - res - ((CPU->flag_X >> C68K_SR_X_SFT) & 1); + + if (res != 0x9a) + { + if ((res & 0x0f) == 0xa) res = (res & 0xf0) + 0x10; + res &= 0xFF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; + CPU->flag_notZ |= res; + CPU->flag_X = CPU->flag_C = C68K_SR_C; + } + else CPU->flag_X = CPU->flag_C = 0; + CPU->flag_N = res; +} +RET(6) +case 0x4811: +case 0x4812: +case 0x4813: +case 0x4814: +case 0x4815: +case 0x4816: +case 0x4817: + +// NBCD +case 0x4810: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_BYTE_F(adr, res) + res = 0x9a - res - ((CPU->flag_X >> C68K_SR_X_SFT) & 1); + + if (res != 0x9a) + { + if ((res & 0x0f) == 0xa) res = (res & 0xf0) + 0x10; + res &= 0xFF; + WRITE_BYTE_F(adr, res) + CPU->flag_notZ |= res; + CPU->flag_X = CPU->flag_C = C68K_SR_C; + } + else CPU->flag_X = CPU->flag_C = 0; + CPU->flag_N = res; + POST_IO +} +RET(12) +case 0x4819: +case 0x481A: +case 0x481B: +case 0x481C: +case 0x481D: +case 0x481E: + +// NBCD +case 0x4818: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + PRE_IO + READ_BYTE_F(adr, res) + res = 0x9a - res - ((CPU->flag_X >> C68K_SR_X_SFT) & 1); + + if (res != 0x9a) + { + if ((res & 0x0f) == 0xa) res = (res & 0xf0) + 0x10; + res &= 0xFF; + WRITE_BYTE_F(adr, res) + CPU->flag_notZ |= res; + CPU->flag_X = CPU->flag_C = C68K_SR_C; + } + else CPU->flag_X = CPU->flag_C = 0; + CPU->flag_N = res; + POST_IO +} +RET(12) +case 0x4821: +case 0x4822: +case 0x4823: +case 0x4824: +case 0x4825: +case 0x4826: + +// NBCD +case 0x4820: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_BYTE_F(adr, res) + res = 0x9a - res - ((CPU->flag_X >> C68K_SR_X_SFT) & 1); + + if (res != 0x9a) + { + if ((res & 0x0f) == 0xa) res = (res & 0xf0) + 0x10; + res &= 0xFF; + WRITE_BYTE_F(adr, res) + CPU->flag_notZ |= res; + CPU->flag_X = CPU->flag_C = C68K_SR_C; + } + else CPU->flag_X = CPU->flag_C = 0; + CPU->flag_N = res; + POST_IO +} +RET(14) +case 0x4829: +case 0x482A: +case 0x482B: +case 0x482C: +case 0x482D: +case 0x482E: +case 0x482F: + +// NBCD +case 0x4828: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + res = 0x9a - res - ((CPU->flag_X >> C68K_SR_X_SFT) & 1); + + if (res != 0x9a) + { + if ((res & 0x0f) == 0xa) res = (res & 0xf0) + 0x10; + res &= 0xFF; + WRITE_BYTE_F(adr, res) + CPU->flag_notZ |= res; + CPU->flag_X = CPU->flag_C = C68K_SR_C; + } + else CPU->flag_X = CPU->flag_C = 0; + CPU->flag_N = res; + POST_IO +} +RET(16) +case 0x4831: +case 0x4832: +case 0x4833: +case 0x4834: +case 0x4835: +case 0x4836: +case 0x4837: + +// NBCD +case 0x4830: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, res) + res = 0x9a - res - ((CPU->flag_X >> C68K_SR_X_SFT) & 1); + + if (res != 0x9a) + { + if ((res & 0x0f) == 0xa) res = (res & 0xf0) + 0x10; + res &= 0xFF; + WRITE_BYTE_F(adr, res) + CPU->flag_notZ |= res; + CPU->flag_X = CPU->flag_C = C68K_SR_C; + } + else CPU->flag_X = CPU->flag_C = 0; + CPU->flag_N = res; + POST_IO +} +RET(18) + +// NBCD +case 0x4838: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + res = 0x9a - res - ((CPU->flag_X >> C68K_SR_X_SFT) & 1); + + if (res != 0x9a) + { + if ((res & 0x0f) == 0xa) res = (res & 0xf0) + 0x10; + res &= 0xFF; + WRITE_BYTE_F(adr, res) + CPU->flag_notZ |= res; + CPU->flag_X = CPU->flag_C = C68K_SR_C; + } + else CPU->flag_X = CPU->flag_C = 0; + CPU->flag_N = res; + POST_IO +} +RET(16) + +// NBCD +case 0x4839: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_BYTE_F(adr, res) + res = 0x9a - res - ((CPU->flag_X >> C68K_SR_X_SFT) & 1); + + if (res != 0x9a) + { + if ((res & 0x0f) == 0xa) res = (res & 0xf0) + 0x10; + res &= 0xFF; + WRITE_BYTE_F(adr, res) + CPU->flag_notZ |= res; + CPU->flag_X = CPU->flag_C = C68K_SR_C; + } + else CPU->flag_X = CPU->flag_C = 0; + CPU->flag_N = res; + POST_IO +} +RET(20) + +// NBCD +case 0x481F: +{ + u32 adr; + u32 res; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_BYTE_F(adr, res) + res = 0x9a - res - ((CPU->flag_X >> C68K_SR_X_SFT) & 1); + + if (res != 0x9a) + { + if ((res & 0x0f) == 0xa) res = (res & 0xf0) + 0x10; + res &= 0xFF; + WRITE_BYTE_F(adr, res) + CPU->flag_notZ |= res; + CPU->flag_X = CPU->flag_C = C68K_SR_C; + } + else CPU->flag_X = CPU->flag_C = 0; + CPU->flag_N = res; + POST_IO +} +RET(12) + +// NBCD +case 0x4827: +{ + u32 adr; + u32 res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_BYTE_F(adr, res) + res = 0x9a - res - ((CPU->flag_X >> C68K_SR_X_SFT) & 1); + + if (res != 0x9a) + { + if ((res & 0x0f) == 0xa) res = (res & 0xf0) + 0x10; + res &= 0xFF; + WRITE_BYTE_F(adr, res) + CPU->flag_notZ |= res; + CPU->flag_X = CPU->flag_C = C68K_SR_C; + } + else CPU->flag_X = CPU->flag_C = 0; + CPU->flag_N = res; + POST_IO +} +RET(14) +case 0x4851: +case 0x4852: +case 0x4853: +case 0x4854: +case 0x4855: +case 0x4856: +case 0x4857: + +// PEA +case 0x4850: +{ + u32 adr; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + PUSH_32_F(adr) + POST_IO +} +RET(12) +case 0x4869: +case 0x486A: +case 0x486B: +case 0x486C: +case 0x486D: +case 0x486E: +case 0x486F: + +// PEA +case 0x4868: +{ + u32 adr; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + PUSH_32_F(adr) + POST_IO +} +RET(16) +case 0x4871: +case 0x4872: +case 0x4873: +case 0x4874: +case 0x4875: +case 0x4876: +case 0x4877: + +// PEA +case 0x4870: +{ + u32 adr; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + PUSH_32_F(adr) + POST_IO +} +RET(20) + +// PEA +case 0x4878: +{ + u32 adr; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + PUSH_32_F(adr) + POST_IO +} +RET(16) + +// PEA +case 0x4879: +{ + u32 adr; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + PUSH_32_F(adr) + POST_IO +} +RET(20) + +// PEA +case 0x487A: +{ + u32 adr; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + PUSH_32_F(adr) + POST_IO +} +RET(16) + +// PEA +case 0x487B: +{ + u32 adr; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + PUSH_32_F(adr) + POST_IO +} +RET(20) +case 0x4841: +case 0x4842: +case 0x4843: +case 0x4844: +case 0x4845: +case 0x4846: +case 0x4847: + +// SWAP +case 0x4840: +{ + u32 res; + res = (u32)CPU->D[(Opcode >> 0) & 7]; + res = (res >> 16) | (res << 16); + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(4) +case 0x4891: +case 0x4892: +case 0x4893: +case 0x4894: +case 0x4895: +case 0x4896: +case 0x4897: + +// MOVEMRa +case 0x4890: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + res = FETCH_WORD; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7]; + src = (pointer)(&CPU->D[0]); + dst = adr; + PRE_IO + do + { + if (res & 1) + { + WRITE_WORD_F(adr, *(u16*)src) + adr += 2; + } + src += 4; + } while (res >>= 1); + POST_IO + CCnt -= (adr - dst) * 2; +} +RET(12) +case 0x48A1: +case 0x48A2: +case 0x48A3: +case 0x48A4: +case 0x48A5: +case 0x48A6: + +// MOVEMRa +case 0x48A0: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + res = FETCH_WORD; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7]; + src = (pointer)(&CPU->A[7]); + dst = adr; + PRE_IO + do + { + if (res & 1) + { + adr -= 2; + WRITE_WORD_F(adr, *(u16*)src) + } + src -= 4; + } while (res >>= 1); + CPU->A[(Opcode >> 0) & 7] = adr; + POST_IO + CCnt -= (dst - adr) * 2; +} +RET(8) +case 0x48A9: +case 0x48AA: +case 0x48AB: +case 0x48AC: +case 0x48AD: +case 0x48AE: +case 0x48AF: + +// MOVEMRa +case 0x48A8: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + res = FETCH_WORD; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + src = (pointer)(&CPU->D[0]); + dst = adr; + PRE_IO + do + { + if (res & 1) + { + WRITE_WORD_F(adr, *(u16*)src) + adr += 2; + } + src += 4; + } while (res >>= 1); + POST_IO + CCnt -= (adr - dst) * 2; +} +RET(20) +case 0x48B1: +case 0x48B2: +case 0x48B3: +case 0x48B4: +case 0x48B5: +case 0x48B6: +case 0x48B7: + +// MOVEMRa +case 0x48B0: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + res = FETCH_WORD; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + src = (pointer)(&CPU->D[0]); + dst = adr; + PRE_IO + do + { + if (res & 1) + { + WRITE_WORD_F(adr, *(u16*)src) + adr += 2; + } + src += 4; + } while (res >>= 1); + POST_IO + CCnt -= (adr - dst) * 2; +} +RET(24) + +// MOVEMRa +case 0x48B8: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + res = FETCH_WORD; + PC += 2; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + src = (pointer)(&CPU->D[0]); + dst = adr; + PRE_IO + do + { + if (res & 1) + { + WRITE_WORD_F(adr, *(u16*)src) + adr += 2; + } + src += 4; + } while (res >>= 1); + POST_IO + CCnt -= (adr - dst) * 2; +} +RET(20) + +// MOVEMRa +case 0x48B9: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + res = FETCH_WORD; + PC += 2; + adr = (s32)FETCH_LONG; + PC += 4; + src = (pointer)(&CPU->D[0]); + dst = adr; + PRE_IO + do + { + if (res & 1) + { + WRITE_WORD_F(adr, *(u16*)src) + adr += 2; + } + src += 4; + } while (res >>= 1); + POST_IO + CCnt -= (adr - dst) * 2; +} +RET(28) + +// MOVEMRa +case 0x48A7: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + res = FETCH_WORD; + PC += 2; + adr = CPU->A[7]; + src = (pointer)(&CPU->A[7]); + dst = adr; + PRE_IO + do + { + if (res & 1) + { + adr -= 2; + WRITE_WORD_F(adr, *(u16*)src) + } + src -= 4; + } while (res >>= 1); + CPU->A[7] = adr; + POST_IO + CCnt -= (dst - adr) * 2; +} +RET(8) +case 0x48D1: +case 0x48D2: +case 0x48D3: +case 0x48D4: +case 0x48D5: +case 0x48D6: +case 0x48D7: + +// MOVEMRa +case 0x48D0: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + res = FETCH_WORD; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7]; + src = (pointer)(&CPU->D[0]); + dst = adr; + PRE_IO + do + { + if (res & 1) + { + WRITE_LONG_F(adr, *(u32*)src) + adr += 4; + } + src += 4; + } while (res >>= 1); + POST_IO + CCnt -= (adr - dst) * 2; +} +RET(16) +case 0x48E1: +case 0x48E2: +case 0x48E3: +case 0x48E4: +case 0x48E5: +case 0x48E6: + +// MOVEMRa +case 0x48E0: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + res = FETCH_WORD; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7]; + src = (pointer)(&CPU->A[7]); + dst = adr; + PRE_IO + do + { + if (res & 1) + { + adr -= 4; + WRITE_LONG_DEC_F(adr, *(u32*)src) + } + src -= 4; + } while (res >>= 1); + CPU->A[(Opcode >> 0) & 7] = adr; + POST_IO + CCnt -= (dst - adr) * 2; +} +RET(8) +case 0x48E9: +case 0x48EA: +case 0x48EB: +case 0x48EC: +case 0x48ED: +case 0x48EE: +case 0x48EF: + +// MOVEMRa +case 0x48E8: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + res = FETCH_WORD; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + src = (pointer)(&CPU->D[0]); + dst = adr; + PRE_IO + do + { + if (res & 1) + { + WRITE_LONG_F(adr, *(u32*)src) + adr += 4; + } + src += 4; + } while (res >>= 1); + POST_IO + CCnt -= (adr - dst) * 2; +} +RET(24) +case 0x48F1: +case 0x48F2: +case 0x48F3: +case 0x48F4: +case 0x48F5: +case 0x48F6: +case 0x48F7: + +// MOVEMRa +case 0x48F0: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + res = FETCH_WORD; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + src = (pointer)(&CPU->D[0]); + dst = adr; + PRE_IO + do + { + if (res & 1) + { + WRITE_LONG_F(adr, *(u32*)src) + adr += 4; + } + src += 4; + } while (res >>= 1); + POST_IO + CCnt -= (adr - dst) * 2; +} +RET(28) + +// MOVEMRa +case 0x48F8: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + res = FETCH_WORD; + PC += 2; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + src = (pointer)(&CPU->D[0]); + dst = adr; + PRE_IO + do + { + if (res & 1) + { + WRITE_LONG_F(adr, *(u32*)src) + adr += 4; + } + src += 4; + } while (res >>= 1); + POST_IO + CCnt -= (adr - dst) * 2; +} +RET(24) + +// MOVEMRa +case 0x48F9: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + res = FETCH_WORD; + PC += 2; + adr = (s32)FETCH_LONG; + PC += 4; + src = (pointer)(&CPU->D[0]); + dst = adr; + PRE_IO + do + { + if (res & 1) + { + WRITE_LONG_F(adr, *(u32*)src) + adr += 4; + } + src += 4; + } while (res >>= 1); + POST_IO + CCnt -= (adr - dst) * 2; +} +RET(32) + +// MOVEMRa +case 0x48E7: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + res = FETCH_WORD; + PC += 2; + adr = CPU->A[7]; + src = (pointer)(&CPU->A[7]); + dst = adr; + PRE_IO + do + { + if (res & 1) + { + adr -= 4; + WRITE_LONG_DEC_F(adr, *(u32*)src) + } + src -= 4; + } while (res >>= 1); + CPU->A[7] = adr; + POST_IO + CCnt -= (dst - adr) * 2; +} +RET(8) +case 0x4881: +case 0x4882: +case 0x4883: +case 0x4884: +case 0x4885: +case 0x4886: +case 0x4887: + +// EXT +case 0x4880: +{ + u32 res; + res = (s32)(s8)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(4) +case 0x48C1: +case 0x48C2: +case 0x48C3: +case 0x48C4: +case 0x48C5: +case 0x48C6: +case 0x48C7: + +// EXT +case 0x48C0: +{ + u32 res; + res = (s32)(s16)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + *((u32*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(4) +case 0x4A01: +case 0x4A02: +case 0x4A03: +case 0x4A04: +case 0x4A05: +case 0x4A06: +case 0x4A07: + +// TST +case 0x4A00: +{ + u32 res; + res = (u8)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; +} +RET(4) +case 0x4A11: +case 0x4A12: +case 0x4A13: +case 0x4A14: +case 0x4A15: +case 0x4A16: +case 0x4A17: + +// TST +case 0x4A10: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + POST_IO +} +RET(8) +case 0x4A19: +case 0x4A1A: +case 0x4A1B: +case 0x4A1C: +case 0x4A1D: +case 0x4A1E: + +// TST +case 0x4A18: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + POST_IO +} +RET(8) +case 0x4A21: +case 0x4A22: +case 0x4A23: +case 0x4A24: +case 0x4A25: +case 0x4A26: + +// TST +case 0x4A20: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + POST_IO +} +RET(10) +case 0x4A29: +case 0x4A2A: +case 0x4A2B: +case 0x4A2C: +case 0x4A2D: +case 0x4A2E: +case 0x4A2F: + +// TST +case 0x4A28: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + POST_IO +} +RET(12) +case 0x4A31: +case 0x4A32: +case 0x4A33: +case 0x4A34: +case 0x4A35: +case 0x4A36: +case 0x4A37: + +// TST +case 0x4A30: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + POST_IO +} +RET(14) + +// TST +case 0x4A38: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + POST_IO +} +RET(12) + +// TST +case 0x4A39: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + POST_IO +} +RET(16) + +// TST +case 0x4A1F: +{ + u32 adr; + u32 res; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + POST_IO +} +RET(8) + +// TST +case 0x4A27: +{ + u32 adr; + u32 res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + POST_IO +} +RET(10) +case 0x4A41: +case 0x4A42: +case 0x4A43: +case 0x4A44: +case 0x4A45: +case 0x4A46: +case 0x4A47: + +// TST +case 0x4A40: +{ + u32 res; + res = (u16)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; +} +RET(4) +case 0x4A51: +case 0x4A52: +case 0x4A53: +case 0x4A54: +case 0x4A55: +case 0x4A56: +case 0x4A57: + +// TST +case 0x4A50: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + POST_IO +} +RET(8) +case 0x4A59: +case 0x4A5A: +case 0x4A5B: +case 0x4A5C: +case 0x4A5D: +case 0x4A5E: + +// TST +case 0x4A58: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 2; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + POST_IO +} +RET(8) +case 0x4A61: +case 0x4A62: +case 0x4A63: +case 0x4A64: +case 0x4A65: +case 0x4A66: + +// TST +case 0x4A60: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] - 2; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + POST_IO +} +RET(10) +case 0x4A69: +case 0x4A6A: +case 0x4A6B: +case 0x4A6C: +case 0x4A6D: +case 0x4A6E: +case 0x4A6F: + +// TST +case 0x4A68: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + POST_IO +} +RET(12) +case 0x4A71: +case 0x4A72: +case 0x4A73: +case 0x4A74: +case 0x4A75: +case 0x4A76: +case 0x4A77: + +// TST +case 0x4A70: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + POST_IO +} +RET(14) + +// TST +case 0x4A78: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + POST_IO +} +RET(12) + +// TST +case 0x4A79: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + POST_IO +} +RET(16) + +// TST +case 0x4A5F: +{ + u32 adr; + u32 res; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + POST_IO +} +RET(8) + +// TST +case 0x4A67: +{ + u32 adr; + u32 res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_WORD_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + POST_IO +} +RET(10) +case 0x4A81: +case 0x4A82: +case 0x4A83: +case 0x4A84: +case 0x4A85: +case 0x4A86: +case 0x4A87: + +// TST +case 0x4A80: +{ + u32 res; + res = (u32)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; +} +RET(4) +case 0x4A91: +case 0x4A92: +case 0x4A93: +case 0x4A94: +case 0x4A95: +case 0x4A96: +case 0x4A97: + +// TST +case 0x4A90: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + POST_IO +} +RET(12) +case 0x4A99: +case 0x4A9A: +case 0x4A9B: +case 0x4A9C: +case 0x4A9D: +case 0x4A9E: + +// TST +case 0x4A98: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 4; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + POST_IO +} +RET(12) +case 0x4AA1: +case 0x4AA2: +case 0x4AA3: +case 0x4AA4: +case 0x4AA5: +case 0x4AA6: + +// TST +case 0x4AA0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] - 4; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + POST_IO +} +RET(14) +case 0x4AA9: +case 0x4AAA: +case 0x4AAB: +case 0x4AAC: +case 0x4AAD: +case 0x4AAE: +case 0x4AAF: + +// TST +case 0x4AA8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + POST_IO +} +RET(16) +case 0x4AB1: +case 0x4AB2: +case 0x4AB3: +case 0x4AB4: +case 0x4AB5: +case 0x4AB6: +case 0x4AB7: + +// TST +case 0x4AB0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + POST_IO +} +RET(18) + +// TST +case 0x4AB8: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + POST_IO +} +RET(16) + +// TST +case 0x4AB9: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + POST_IO +} +RET(20) + +// TST +case 0x4A9F: +{ + u32 adr; + u32 res; + adr = CPU->A[7]; + CPU->A[7] += 4; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + POST_IO +} +RET(12) + +// TST +case 0x4AA7: +{ + u32 adr; + u32 res; + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + PRE_IO + READ_LONG_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + POST_IO +} +RET(14) +case 0x4AC1: +case 0x4AC2: +case 0x4AC3: +case 0x4AC4: +case 0x4AC5: +case 0x4AC6: +case 0x4AC7: + +// TAS +case 0x4AC0: +{ + u32 res; + res = (u8)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + res |= 0x80; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(4) +case 0x4AD1: +case 0x4AD2: +case 0x4AD3: +case 0x4AD4: +case 0x4AD5: +case 0x4AD6: +case 0x4AD7: + +// TAS +case 0x4AD0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + res |= 0x80; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(8) +case 0x4AD9: +case 0x4ADA: +case 0x4ADB: +case 0x4ADC: +case 0x4ADD: +case 0x4ADE: + +// TAS +case 0x4AD8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + res |= 0x80; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(8) +case 0x4AE1: +case 0x4AE2: +case 0x4AE3: +case 0x4AE4: +case 0x4AE5: +case 0x4AE6: + +// TAS +case 0x4AE0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + res |= 0x80; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(10) +case 0x4AE9: +case 0x4AEA: +case 0x4AEB: +case 0x4AEC: +case 0x4AED: +case 0x4AEE: +case 0x4AEF: + +// TAS +case 0x4AE8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + res |= 0x80; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0x4AF1: +case 0x4AF2: +case 0x4AF3: +case 0x4AF4: +case 0x4AF5: +case 0x4AF6: +case 0x4AF7: + +// TAS +case 0x4AF0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + res |= 0x80; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(14) + +// TAS +case 0x4AF8: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + res |= 0x80; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) + +// TAS +case 0x4AF9: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + res |= 0x80; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) + +// TAS +case 0x4ADF: +{ + u32 adr; + u32 res; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + res |= 0x80; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(8) + +// TAS +case 0x4AE7: +{ + u32 adr; + u32 res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_BYTE_F(adr, res) + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + res |= 0x80; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(10) + +// ILLEGAL +case 0x4AFC: +{ + u32 res; + if (!CPU->flag_S) + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + } + res = C68K_ILLEGAL_INSTRUCTION_EX; + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + POST_IO +} +RET(4) +case 0x4C91: +case 0x4C92: +case 0x4C93: +case 0x4C94: +case 0x4C95: +case 0x4C96: +case 0x4C97: + +// MOVEMaR +case 0x4C90: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + res = FETCH_WORD; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7]; + src = (pointer)(&CPU->D[0]); + dst = adr; + PRE_IO + do + { + if (res & 1) + { + READSX_WORD_F(adr, *(s32*)src) + adr += 2; + } + src += 4; + } while (res >>= 1); + POST_IO + CCnt -= (adr - dst) * 2; +} +RET(16) +case 0x4C99: +case 0x4C9A: +case 0x4C9B: +case 0x4C9C: +case 0x4C9D: +case 0x4C9E: + +// MOVEMaR +case 0x4C98: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + res = FETCH_WORD; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7]; + src = (pointer)(&CPU->D[0]); + dst = adr; + PRE_IO + do + { + if (res & 1) + { + READSX_WORD_F(adr, *(s32*)src) + adr += 2; + } + src += 4; + } while (res >>= 1); + CPU->A[(Opcode >> 0) & 7] = adr; + POST_IO + CCnt -= (adr - dst) * 2; +} +RET(12) +case 0x4CA9: +case 0x4CAA: +case 0x4CAB: +case 0x4CAC: +case 0x4CAD: +case 0x4CAE: +case 0x4CAF: + +// MOVEMaR +case 0x4CA8: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + res = FETCH_WORD; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + src = (pointer)(&CPU->D[0]); + dst = adr; + PRE_IO + do + { + if (res & 1) + { + READSX_WORD_F(adr, *(s32*)src) + adr += 2; + } + src += 4; + } while (res >>= 1); + POST_IO + CCnt -= (adr - dst) * 2; +} +RET(24) +case 0x4CB1: +case 0x4CB2: +case 0x4CB3: +case 0x4CB4: +case 0x4CB5: +case 0x4CB6: +case 0x4CB7: + +// MOVEMaR +case 0x4CB0: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + res = FETCH_WORD; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + src = (pointer)(&CPU->D[0]); + dst = adr; + PRE_IO + do + { + if (res & 1) + { + READSX_WORD_F(adr, *(s32*)src) + adr += 2; + } + src += 4; + } while (res >>= 1); + POST_IO + CCnt -= (adr - dst) * 2; +} +RET(28) + +// MOVEMaR +case 0x4CB8: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + res = FETCH_WORD; + PC += 2; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + src = (pointer)(&CPU->D[0]); + dst = adr; + PRE_IO + do + { + if (res & 1) + { + READSX_WORD_F(adr, *(s32*)src) + adr += 2; + } + src += 4; + } while (res >>= 1); + POST_IO + CCnt -= (adr - dst) * 2; +} +RET(24) + +// MOVEMaR +case 0x4CB9: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + res = FETCH_WORD; + PC += 2; + adr = (s32)FETCH_LONG; + PC += 4; + src = (pointer)(&CPU->D[0]); + dst = adr; + PRE_IO + do + { + if (res & 1) + { + READSX_WORD_F(adr, *(s32*)src) + adr += 2; + } + src += 4; + } while (res >>= 1); + POST_IO + CCnt -= (adr - dst) * 2; +} +RET(32) + +// MOVEMaR +case 0x4CBA: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + res = FETCH_WORD; + PC += 2; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + src = (pointer)(&CPU->D[0]); + dst = adr; + PRE_IO + do + { + if (res & 1) + { + READSX_WORD_F(adr, *(s32*)src) + adr += 2; + } + src += 4; + } while (res >>= 1); + POST_IO + CCnt -= (adr - dst) * 2; +} +RET(24) + +// MOVEMaR +case 0x4CBB: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + res = FETCH_WORD; + PC += 2; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + src = (pointer)(&CPU->D[0]); + dst = adr; + PRE_IO + do + { + if (res & 1) + { + READSX_WORD_F(adr, *(s32*)src) + adr += 2; + } + src += 4; + } while (res >>= 1); + POST_IO + CCnt -= (adr - dst) * 2; +} +RET(28) + +// MOVEMaR +case 0x4C9F: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + res = FETCH_WORD; + PC += 2; + adr = CPU->A[7]; + src = (pointer)(&CPU->D[0]); + dst = adr; + PRE_IO + do + { + if (res & 1) + { + READSX_WORD_F(adr, *(s32*)src) + adr += 2; + } + src += 4; + } while (res >>= 1); + CPU->A[7] = adr; + POST_IO + CCnt -= (adr - dst) * 2; +} +RET(12) +case 0x4CD1: +case 0x4CD2: +case 0x4CD3: +case 0x4CD4: +case 0x4CD5: +case 0x4CD6: +case 0x4CD7: + +// MOVEMaR +case 0x4CD0: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + res = FETCH_WORD; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7]; + src = (pointer)(&CPU->D[0]); + dst = adr; + PRE_IO + do + { + if (res & 1) + { + READ_LONG_F(adr, *(u32*)src) + adr += 4; + } + src += 4; + } while (res >>= 1); + POST_IO + CCnt -= (adr - dst) * 2; +} +RET(20) +case 0x4CD9: +case 0x4CDA: +case 0x4CDB: +case 0x4CDC: +case 0x4CDD: +case 0x4CDE: + +// MOVEMaR +case 0x4CD8: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + res = FETCH_WORD; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7]; + src = (pointer)(&CPU->D[0]); + dst = adr; + PRE_IO + do + { + if (res & 1) + { + READ_LONG_F(adr, *(u32*)src) + adr += 4; + } + src += 4; + } while (res >>= 1); + CPU->A[(Opcode >> 0) & 7] = adr; + POST_IO + CCnt -= (adr - dst) * 2; +} +RET(12) +case 0x4CE9: +case 0x4CEA: +case 0x4CEB: +case 0x4CEC: +case 0x4CED: +case 0x4CEE: +case 0x4CEF: + +// MOVEMaR +case 0x4CE8: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + res = FETCH_WORD; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + src = (pointer)(&CPU->D[0]); + dst = adr; + PRE_IO + do + { + if (res & 1) + { + READ_LONG_F(adr, *(u32*)src) + adr += 4; + } + src += 4; + } while (res >>= 1); + POST_IO + CCnt -= (adr - dst) * 2; +} +RET(28) +case 0x4CF1: +case 0x4CF2: +case 0x4CF3: +case 0x4CF4: +case 0x4CF5: +case 0x4CF6: +case 0x4CF7: + +// MOVEMaR +case 0x4CF0: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + res = FETCH_WORD; + PC += 2; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + src = (pointer)(&CPU->D[0]); + dst = adr; + PRE_IO + do + { + if (res & 1) + { + READ_LONG_F(adr, *(u32*)src) + adr += 4; + } + src += 4; + } while (res >>= 1); + POST_IO + CCnt -= (adr - dst) * 2; +} +RET(32) + +// MOVEMaR +case 0x4CF8: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + res = FETCH_WORD; + PC += 2; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + src = (pointer)(&CPU->D[0]); + dst = adr; + PRE_IO + do + { + if (res & 1) + { + READ_LONG_F(adr, *(u32*)src) + adr += 4; + } + src += 4; + } while (res >>= 1); + POST_IO + CCnt -= (adr - dst) * 2; +} +RET(28) + +// MOVEMaR +case 0x4CF9: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + res = FETCH_WORD; + PC += 2; + adr = (s32)FETCH_LONG; + PC += 4; + src = (pointer)(&CPU->D[0]); + dst = adr; + PRE_IO + do + { + if (res & 1) + { + READ_LONG_F(adr, *(u32*)src) + adr += 4; + } + src += 4; + } while (res >>= 1); + POST_IO + CCnt -= (adr - dst) * 2; +} +RET(36) + +// MOVEMaR +case 0x4CFA: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + res = FETCH_WORD; + PC += 2; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + src = (pointer)(&CPU->D[0]); + dst = adr; + PRE_IO + do + { + if (res & 1) + { + READ_LONG_F(adr, *(u32*)src) + adr += 4; + } + src += 4; + } while (res >>= 1); + POST_IO + CCnt -= (adr - dst) * 2; +} +RET(28) + +// MOVEMaR +case 0x4CFB: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + res = FETCH_WORD; + PC += 2; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + src = (pointer)(&CPU->D[0]); + dst = adr; + PRE_IO + do + { + if (res & 1) + { + READ_LONG_F(adr, *(u32*)src) + adr += 4; + } + src += 4; + } while (res >>= 1); + POST_IO + CCnt -= (adr - dst) * 2; +} +RET(32) + +// MOVEMaR +case 0x4CDF: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + res = FETCH_WORD; + PC += 2; + adr = CPU->A[7]; + src = (pointer)(&CPU->D[0]); + dst = adr; + PRE_IO + do + { + if (res & 1) + { + READ_LONG_F(adr, *(u32*)src) + adr += 4; + } + src += 4; + } while (res >>= 1); + CPU->A[7] = adr; + POST_IO + CCnt -= (adr - dst) * 2; +} +RET(12) +case 0x4E41: +case 0x4E42: +case 0x4E43: +case 0x4E44: +case 0x4E45: +case 0x4E46: +case 0x4E47: +case 0x4E48: +case 0x4E49: +case 0x4E4A: +case 0x4E4B: +case 0x4E4C: +case 0x4E4D: +case 0x4E4E: +case 0x4E4F: + +// TRAP +case 0x4E40: +{ + u32 res; + if (!CPU->flag_S) + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + } + res = C68K_TRAP_BASE_EX + (Opcode & 0xF); + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + POST_IO +} +RET(4) +case 0x4E51: +case 0x4E52: +case 0x4E53: +case 0x4E54: +case 0x4E55: +case 0x4E56: + +// LINK +case 0x4E50: +{ + u32 res; + res = (u32)CPU->A[(Opcode >> 0) & 7]; + PRE_IO + PUSH_32_F(res) + res = CPU->A[7]; + CPU->A[(Opcode >> 0) & 7] = res; + CPU->A[7] += (s32)(s16)FETCH_WORD; + PC += 2; + POST_IO +} +RET(16) + +// LINKA7 +case 0x4E57: +{ + CPU->A[7] -= 4; + PRE_IO + WRITE_LONG_DEC_F(CPU->A[7], CPU->A[7]) + CPU->A[7] += (s32)(s16)FETCH_WORD; + PC += 2; + POST_IO +} +RET(16) +case 0x4E59: +case 0x4E5A: +case 0x4E5B: +case 0x4E5C: +case 0x4E5D: +case 0x4E5E: + +// ULNK +case 0x4E58: +{ + u32 res; + pointer src; + src = (u32)CPU->A[(Opcode >> 0) & 7]; + CPU->A[7] = src + 4; + PRE_IO + READ_LONG_F(src, res) + CPU->A[(Opcode >> 0) & 7] = res; + POST_IO +} +RET(12) + +// ULNKA7 +case 0x4E5F: +{ + PRE_IO + READ_LONG_F(CPU->A[7], CPU->A[7]) + POST_IO +} +RET(12) +case 0x4E61: +case 0x4E62: +case 0x4E63: +case 0x4E64: +case 0x4E65: +case 0x4E66: +case 0x4E67: + +// MOVEAUSP +case 0x4E60: +{ + u32 res; + if (!CPU->flag_S) + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + res = C68K_PRIVILEGE_VIOLATION_EX; + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + POST_IO + RET(4) + } + res = (u32)CPU->A[(Opcode >> 0) & 7]; + CPU->USP = res; +} +RET(4) +case 0x4E69: +case 0x4E6A: +case 0x4E6B: +case 0x4E6C: +case 0x4E6D: +case 0x4E6E: +case 0x4E6F: + +// MOVEUSPA +case 0x4E68: +{ + u32 res; + if (!CPU->flag_S) + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + res = C68K_PRIVILEGE_VIOLATION_EX; + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + POST_IO + RET(4) + } + res = CPU->USP; + CPU->A[(Opcode >> 0) & 7] = res; +} +RET(4) + +// RESET +case 0x4E70: +{ + u32 res; + if (!CPU->flag_S) + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + res = C68K_PRIVILEGE_VIOLATION_EX; + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + POST_IO + RET(4) + } + PRE_IO + CPU->Reset_CallBack(CPU->Callback_Param); + POST_IO +} +RET(132) + +// NOP +case 0x4E71: +{ +} +RET(4) + +// STOP +case 0x4E72: +{ + u32 res; + if (!CPU->flag_S) + { + PC += 2; + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + res = C68K_PRIVILEGE_VIOLATION_EX; + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + POST_IO + RET(4) + } + res = FETCH_WORD & C68K_SR_MASK; + PC += 2; + SET_SR(res) + if (!CPU->flag_S) + { + res = CPU->A[7]; + CPU->A[7] = CPU->USP; + CPU->USP = res; + } + CPU->Status |= C68K_HALTED; + CCnt = 0; +} +CCnt -= 4; +goto C68k_Exec_End; + +// RTE +case 0x4E73: +{ + u32 res; + if (!CPU->flag_S) + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + res = C68K_PRIVILEGE_VIOLATION_EX; + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + POST_IO + RET(4) + } + PRE_IO + POP_16_F(res) + SET_SR(res) + POP_32_F(res) + SET_PC(res) + if (!CPU->flag_S) + { + res = CPU->A[7]; + CPU->A[7] = CPU->USP; + CPU->USP = res; + } +} +POST_IO +CCnt -= 20; +goto C68k_Exec_End; + +// RTS +case 0x4E75: +{ + u32 res; + PRE_IO + POP_32_F(res) + SET_PC(res) + POST_IO +} +RET(16) + +// TRAPV +case 0x4E76: +{ + u32 res; + if (CPU->flag_V & 0x80) + { + if (!CPU->flag_S) + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + } + res = C68K_TRAPV_EX; + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + } + POST_IO +} +RET(4) + +// RTR +case 0x4E77: +{ + u32 res; + PRE_IO + POP_16_F(res) + SET_CCR(res) + POP_32_F(res) + SET_PC(res) + POST_IO +} +RET(20) +case 0x4E91: +case 0x4E92: +case 0x4E93: +case 0x4E94: +case 0x4E95: +case 0x4E96: +case 0x4E97: + +// JSR +case 0x4E90: +{ + u32 adr; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + SET_PC(adr) + POST_IO +} +RET(16) +case 0x4EA9: +case 0x4EAA: +case 0x4EAB: +case 0x4EAC: +case 0x4EAD: +case 0x4EAE: +case 0x4EAF: + +// JSR +case 0x4EA8: +{ + u32 adr; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + SET_PC(adr) + POST_IO +} +RET(18) +case 0x4EB1: +case 0x4EB2: +case 0x4EB3: +case 0x4EB4: +case 0x4EB5: +case 0x4EB6: +case 0x4EB7: + +// JSR +case 0x4EB0: +{ + u32 adr; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + SET_PC(adr) + POST_IO +} +RET(22) + +// JSR +case 0x4EB8: +{ + u32 adr; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + SET_PC(adr) + POST_IO +} +RET(18) + +// JSR +case 0x4EB9: +{ + u32 adr; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + SET_PC(adr) + POST_IO +} +RET(20) + +// JSR +case 0x4EBA: +{ + u32 adr; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + SET_PC(adr) + POST_IO +} +RET(18) + +// JSR +case 0x4EBB: +{ + u32 adr; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + SET_PC(adr) + POST_IO +} +RET(22) +case 0x4ED1: +case 0x4ED2: +case 0x4ED3: +case 0x4ED4: +case 0x4ED5: +case 0x4ED6: +case 0x4ED7: + +// JMP +case 0x4ED0: +{ + u32 adr; + adr = CPU->A[(Opcode >> 0) & 7]; + SET_PC(adr) +} +RET(8) +case 0x4EE9: +case 0x4EEA: +case 0x4EEB: +case 0x4EEC: +case 0x4EED: +case 0x4EEE: +case 0x4EEF: + +// JMP +case 0x4EE8: +{ + u32 adr; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + SET_PC(adr) +} +RET(10) +case 0x4EF1: +case 0x4EF2: +case 0x4EF3: +case 0x4EF4: +case 0x4EF5: +case 0x4EF6: +case 0x4EF7: + +// JMP +case 0x4EF0: +{ + u32 adr; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + SET_PC(adr) +} +RET(14) + +// JMP +case 0x4EF8: +{ + u32 adr; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + SET_PC(adr) +} +RET(10) + +// JMP +case 0x4EF9: +{ + u32 adr; + adr = (s32)FETCH_LONG; + PC += 4; + SET_PC(adr) +} +RET(12) + +// JMP +case 0x4EFA: +{ + u32 adr; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + SET_PC(adr) +} +RET(10) + +// JMP +case 0x4EFB: +{ + u32 adr; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + SET_PC(adr) +} +RET(14) +case 0x4380: +case 0x4580: +case 0x4780: +case 0x4980: +case 0x4B80: +case 0x4D80: +case 0x4F80: +case 0x4181: +case 0x4381: +case 0x4581: +case 0x4781: +case 0x4981: +case 0x4B81: +case 0x4D81: +case 0x4F81: +case 0x4182: +case 0x4382: +case 0x4582: +case 0x4782: +case 0x4982: +case 0x4B82: +case 0x4D82: +case 0x4F82: +case 0x4183: +case 0x4383: +case 0x4583: +case 0x4783: +case 0x4983: +case 0x4B83: +case 0x4D83: +case 0x4F83: +case 0x4184: +case 0x4384: +case 0x4584: +case 0x4784: +case 0x4984: +case 0x4B84: +case 0x4D84: +case 0x4F84: +case 0x4185: +case 0x4385: +case 0x4585: +case 0x4785: +case 0x4985: +case 0x4B85: +case 0x4D85: +case 0x4F85: +case 0x4186: +case 0x4386: +case 0x4586: +case 0x4786: +case 0x4986: +case 0x4B86: +case 0x4D86: +case 0x4F86: +case 0x4187: +case 0x4387: +case 0x4587: +case 0x4787: +case 0x4987: +case 0x4B87: +case 0x4D87: +case 0x4F87: + +// CHK +case 0x4180: +{ + u32 res; + pointer src; + src = (u16)CPU->D[(Opcode >> 0) & 7]; + res = (u16)CPU->D[(Opcode >> 9) & 7]; + if (((s32)res < 0) || (res > src)) + { + CPU->flag_N = res >> 8; + if (!CPU->flag_S) + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + } + res = C68K_CHK_EX; + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + } + POST_IO +} +RET(10) +case 0x4390: +case 0x4590: +case 0x4790: +case 0x4990: +case 0x4B90: +case 0x4D90: +case 0x4F90: +case 0x4191: +case 0x4391: +case 0x4591: +case 0x4791: +case 0x4991: +case 0x4B91: +case 0x4D91: +case 0x4F91: +case 0x4192: +case 0x4392: +case 0x4592: +case 0x4792: +case 0x4992: +case 0x4B92: +case 0x4D92: +case 0x4F92: +case 0x4193: +case 0x4393: +case 0x4593: +case 0x4793: +case 0x4993: +case 0x4B93: +case 0x4D93: +case 0x4F93: +case 0x4194: +case 0x4394: +case 0x4594: +case 0x4794: +case 0x4994: +case 0x4B94: +case 0x4D94: +case 0x4F94: +case 0x4195: +case 0x4395: +case 0x4595: +case 0x4795: +case 0x4995: +case 0x4B95: +case 0x4D95: +case 0x4F95: +case 0x4196: +case 0x4396: +case 0x4596: +case 0x4796: +case 0x4996: +case 0x4B96: +case 0x4D96: +case 0x4F96: +case 0x4197: +case 0x4397: +case 0x4597: +case 0x4797: +case 0x4997: +case 0x4B97: +case 0x4D97: +case 0x4F97: + +// CHK +case 0x4190: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_WORD_F(adr, src) + res = (u16)CPU->D[(Opcode >> 9) & 7]; + if (((s32)res < 0) || (res > src)) + { + CPU->flag_N = res >> 8; + if (!CPU->flag_S) + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + } + res = C68K_CHK_EX; + POST_IO + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + } + POST_IO +} +RET(14) +case 0x4398: +case 0x4598: +case 0x4798: +case 0x4998: +case 0x4B98: +case 0x4D98: +case 0x4F98: +case 0x4199: +case 0x4399: +case 0x4599: +case 0x4799: +case 0x4999: +case 0x4B99: +case 0x4D99: +case 0x4F99: +case 0x419A: +case 0x439A: +case 0x459A: +case 0x479A: +case 0x499A: +case 0x4B9A: +case 0x4D9A: +case 0x4F9A: +case 0x419B: +case 0x439B: +case 0x459B: +case 0x479B: +case 0x499B: +case 0x4B9B: +case 0x4D9B: +case 0x4F9B: +case 0x419C: +case 0x439C: +case 0x459C: +case 0x479C: +case 0x499C: +case 0x4B9C: +case 0x4D9C: +case 0x4F9C: +case 0x419D: +case 0x439D: +case 0x459D: +case 0x479D: +case 0x499D: +case 0x4B9D: +case 0x4D9D: +case 0x4F9D: +case 0x419E: +case 0x439E: +case 0x459E: +case 0x479E: +case 0x499E: +case 0x4B9E: +case 0x4D9E: +case 0x4F9E: + +// CHK +case 0x4198: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 2; + PRE_IO + READ_WORD_F(adr, src) + res = (u16)CPU->D[(Opcode >> 9) & 7]; + if (((s32)res < 0) || (res > src)) + { + CPU->flag_N = res >> 8; + if (!CPU->flag_S) + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + } + res = C68K_CHK_EX; + POST_IO + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + } + POST_IO +} +RET(14) +case 0x43A0: +case 0x45A0: +case 0x47A0: +case 0x49A0: +case 0x4BA0: +case 0x4DA0: +case 0x4FA0: +case 0x41A1: +case 0x43A1: +case 0x45A1: +case 0x47A1: +case 0x49A1: +case 0x4BA1: +case 0x4DA1: +case 0x4FA1: +case 0x41A2: +case 0x43A2: +case 0x45A2: +case 0x47A2: +case 0x49A2: +case 0x4BA2: +case 0x4DA2: +case 0x4FA2: +case 0x41A3: +case 0x43A3: +case 0x45A3: +case 0x47A3: +case 0x49A3: +case 0x4BA3: +case 0x4DA3: +case 0x4FA3: +case 0x41A4: +case 0x43A4: +case 0x45A4: +case 0x47A4: +case 0x49A4: +case 0x4BA4: +case 0x4DA4: +case 0x4FA4: +case 0x41A5: +case 0x43A5: +case 0x45A5: +case 0x47A5: +case 0x49A5: +case 0x4BA5: +case 0x4DA5: +case 0x4FA5: +case 0x41A6: +case 0x43A6: +case 0x45A6: +case 0x47A6: +case 0x49A6: +case 0x4BA6: +case 0x4DA6: +case 0x4FA6: + +// CHK +case 0x41A0: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 2; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_WORD_F(adr, src) + res = (u16)CPU->D[(Opcode >> 9) & 7]; + if (((s32)res < 0) || (res > src)) + { + CPU->flag_N = res >> 8; + if (!CPU->flag_S) + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + } + res = C68K_CHK_EX; + POST_IO + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + } + POST_IO +} +RET(16) +case 0x43A8: +case 0x45A8: +case 0x47A8: +case 0x49A8: +case 0x4BA8: +case 0x4DA8: +case 0x4FA8: +case 0x41A9: +case 0x43A9: +case 0x45A9: +case 0x47A9: +case 0x49A9: +case 0x4BA9: +case 0x4DA9: +case 0x4FA9: +case 0x41AA: +case 0x43AA: +case 0x45AA: +case 0x47AA: +case 0x49AA: +case 0x4BAA: +case 0x4DAA: +case 0x4FAA: +case 0x41AB: +case 0x43AB: +case 0x45AB: +case 0x47AB: +case 0x49AB: +case 0x4BAB: +case 0x4DAB: +case 0x4FAB: +case 0x41AC: +case 0x43AC: +case 0x45AC: +case 0x47AC: +case 0x49AC: +case 0x4BAC: +case 0x4DAC: +case 0x4FAC: +case 0x41AD: +case 0x43AD: +case 0x45AD: +case 0x47AD: +case 0x49AD: +case 0x4BAD: +case 0x4DAD: +case 0x4FAD: +case 0x41AE: +case 0x43AE: +case 0x45AE: +case 0x47AE: +case 0x49AE: +case 0x4BAE: +case 0x4DAE: +case 0x4FAE: +case 0x41AF: +case 0x43AF: +case 0x45AF: +case 0x47AF: +case 0x49AF: +case 0x4BAF: +case 0x4DAF: +case 0x4FAF: + +// CHK +case 0x41A8: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, src) + res = (u16)CPU->D[(Opcode >> 9) & 7]; + if (((s32)res < 0) || (res > src)) + { + CPU->flag_N = res >> 8; + if (!CPU->flag_S) + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + } + res = C68K_CHK_EX; + POST_IO + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + } + POST_IO +} +RET(18) +case 0x43B0: +case 0x45B0: +case 0x47B0: +case 0x49B0: +case 0x4BB0: +case 0x4DB0: +case 0x4FB0: +case 0x41B1: +case 0x43B1: +case 0x45B1: +case 0x47B1: +case 0x49B1: +case 0x4BB1: +case 0x4DB1: +case 0x4FB1: +case 0x41B2: +case 0x43B2: +case 0x45B2: +case 0x47B2: +case 0x49B2: +case 0x4BB2: +case 0x4DB2: +case 0x4FB2: +case 0x41B3: +case 0x43B3: +case 0x45B3: +case 0x47B3: +case 0x49B3: +case 0x4BB3: +case 0x4DB3: +case 0x4FB3: +case 0x41B4: +case 0x43B4: +case 0x45B4: +case 0x47B4: +case 0x49B4: +case 0x4BB4: +case 0x4DB4: +case 0x4FB4: +case 0x41B5: +case 0x43B5: +case 0x45B5: +case 0x47B5: +case 0x49B5: +case 0x4BB5: +case 0x4DB5: +case 0x4FB5: +case 0x41B6: +case 0x43B6: +case 0x45B6: +case 0x47B6: +case 0x49B6: +case 0x4BB6: +case 0x4DB6: +case 0x4FB6: +case 0x41B7: +case 0x43B7: +case 0x45B7: +case 0x47B7: +case 0x49B7: +case 0x4BB7: +case 0x4DB7: +case 0x4FB7: + +// CHK +case 0x41B0: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, src) + res = (u16)CPU->D[(Opcode >> 9) & 7]; + if (((s32)res < 0) || (res > src)) + { + CPU->flag_N = res >> 8; + if (!CPU->flag_S) + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + } + res = C68K_CHK_EX; + POST_IO + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + } + POST_IO +} +RET(20) +case 0x43B8: +case 0x45B8: +case 0x47B8: +case 0x49B8: +case 0x4BB8: +case 0x4DB8: +case 0x4FB8: + +// CHK +case 0x41B8: +{ + u32 adr; + u32 res; + pointer src; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, src) + res = (u16)CPU->D[(Opcode >> 9) & 7]; + if (((s32)res < 0) || (res > src)) + { + CPU->flag_N = res >> 8; + if (!CPU->flag_S) + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + } + res = C68K_CHK_EX; + POST_IO + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + } + POST_IO +} +RET(18) +case 0x43B9: +case 0x45B9: +case 0x47B9: +case 0x49B9: +case 0x4BB9: +case 0x4DB9: +case 0x4FB9: + +// CHK +case 0x41B9: +{ + u32 adr; + u32 res; + pointer src; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_WORD_F(adr, src) + res = (u16)CPU->D[(Opcode >> 9) & 7]; + if (((s32)res < 0) || (res > src)) + { + CPU->flag_N = res >> 8; + if (!CPU->flag_S) + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + } + res = C68K_CHK_EX; + POST_IO + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + } + POST_IO +} +RET(22) +case 0x43BA: +case 0x45BA: +case 0x47BA: +case 0x49BA: +case 0x4BBA: +case 0x4DBA: +case 0x4FBA: + +// CHK +case 0x41BA: +{ + u32 adr; + u32 res; + pointer src; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, src) + res = (u16)CPU->D[(Opcode >> 9) & 7]; + if (((s32)res < 0) || (res > src)) + { + CPU->flag_N = res >> 8; + if (!CPU->flag_S) + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + } + res = C68K_CHK_EX; + POST_IO + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + } + POST_IO +} +RET(18) +case 0x43BB: +case 0x45BB: +case 0x47BB: +case 0x49BB: +case 0x4BBB: +case 0x4DBB: +case 0x4FBB: + +// CHK +case 0x41BB: +{ + u32 adr; + u32 res; + pointer src; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, src) + res = (u16)CPU->D[(Opcode >> 9) & 7]; + if (((s32)res < 0) || (res > src)) + { + CPU->flag_N = res >> 8; + if (!CPU->flag_S) + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + } + res = C68K_CHK_EX; + POST_IO + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + } + POST_IO +} +RET(20) +case 0x43BC: +case 0x45BC: +case 0x47BC: +case 0x49BC: +case 0x4BBC: +case 0x4DBC: +case 0x4FBC: + +// CHK +case 0x41BC: +{ + u32 res; + pointer src; + src = FETCH_WORD; + PC += 2; + res = (u16)CPU->D[(Opcode >> 9) & 7]; + if (((s32)res < 0) || (res > src)) + { + CPU->flag_N = res >> 8; + if (!CPU->flag_S) + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + } + res = C68K_CHK_EX; + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + } + POST_IO +} +RET(14) +case 0x439F: +case 0x459F: +case 0x479F: +case 0x499F: +case 0x4B9F: +case 0x4D9F: +case 0x4F9F: + +// CHK +case 0x419F: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_WORD_F(adr, src) + res = (u16)CPU->D[(Opcode >> 9) & 7]; + if (((s32)res < 0) || (res > src)) + { + CPU->flag_N = res >> 8; + if (!CPU->flag_S) + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + } + res = C68K_CHK_EX; + POST_IO + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + } + POST_IO +} +RET(14) +case 0x43A7: +case 0x45A7: +case 0x47A7: +case 0x49A7: +case 0x4BA7: +case 0x4DA7: +case 0x4FA7: + +// CHK +case 0x41A7: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_WORD_F(adr, src) + res = (u16)CPU->D[(Opcode >> 9) & 7]; + if (((s32)res < 0) || (res > src)) + { + CPU->flag_N = res >> 8; + if (!CPU->flag_S) + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + } + res = C68K_CHK_EX; + POST_IO + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + } + POST_IO +} +RET(16) +case 0x43D0: +case 0x45D0: +case 0x47D0: +case 0x49D0: +case 0x4BD0: +case 0x4DD0: +case 0x4FD0: +case 0x41D1: +case 0x43D1: +case 0x45D1: +case 0x47D1: +case 0x49D1: +case 0x4BD1: +case 0x4DD1: +case 0x4FD1: +case 0x41D2: +case 0x43D2: +case 0x45D2: +case 0x47D2: +case 0x49D2: +case 0x4BD2: +case 0x4DD2: +case 0x4FD2: +case 0x41D3: +case 0x43D3: +case 0x45D3: +case 0x47D3: +case 0x49D3: +case 0x4BD3: +case 0x4DD3: +case 0x4FD3: +case 0x41D4: +case 0x43D4: +case 0x45D4: +case 0x47D4: +case 0x49D4: +case 0x4BD4: +case 0x4DD4: +case 0x4FD4: +case 0x41D5: +case 0x43D5: +case 0x45D5: +case 0x47D5: +case 0x49D5: +case 0x4BD5: +case 0x4DD5: +case 0x4FD5: +case 0x41D6: +case 0x43D6: +case 0x45D6: +case 0x47D6: +case 0x49D6: +case 0x4BD6: +case 0x4DD6: +case 0x4FD6: +case 0x41D7: +case 0x43D7: +case 0x45D7: +case 0x47D7: +case 0x49D7: +case 0x4BD7: +case 0x4DD7: +case 0x4FD7: + +// LEA +case 0x41D0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + res = adr; + CPU->A[(Opcode >> 9) & 7] = res; +} +RET(4) +case 0x43E8: +case 0x45E8: +case 0x47E8: +case 0x49E8: +case 0x4BE8: +case 0x4DE8: +case 0x4FE8: +case 0x41E9: +case 0x43E9: +case 0x45E9: +case 0x47E9: +case 0x49E9: +case 0x4BE9: +case 0x4DE9: +case 0x4FE9: +case 0x41EA: +case 0x43EA: +case 0x45EA: +case 0x47EA: +case 0x49EA: +case 0x4BEA: +case 0x4DEA: +case 0x4FEA: +case 0x41EB: +case 0x43EB: +case 0x45EB: +case 0x47EB: +case 0x49EB: +case 0x4BEB: +case 0x4DEB: +case 0x4FEB: +case 0x41EC: +case 0x43EC: +case 0x45EC: +case 0x47EC: +case 0x49EC: +case 0x4BEC: +case 0x4DEC: +case 0x4FEC: +case 0x41ED: +case 0x43ED: +case 0x45ED: +case 0x47ED: +case 0x49ED: +case 0x4BED: +case 0x4DED: +case 0x4FED: +case 0x41EE: +case 0x43EE: +case 0x45EE: +case 0x47EE: +case 0x49EE: +case 0x4BEE: +case 0x4DEE: +case 0x4FEE: +case 0x41EF: +case 0x43EF: +case 0x45EF: +case 0x47EF: +case 0x49EF: +case 0x4BEF: +case 0x4DEF: +case 0x4FEF: + +// LEA +case 0x41E8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + res = adr; + CPU->A[(Opcode >> 9) & 7] = res; +} +RET(8) +case 0x43F0: +case 0x45F0: +case 0x47F0: +case 0x49F0: +case 0x4BF0: +case 0x4DF0: +case 0x4FF0: +case 0x41F1: +case 0x43F1: +case 0x45F1: +case 0x47F1: +case 0x49F1: +case 0x4BF1: +case 0x4DF1: +case 0x4FF1: +case 0x41F2: +case 0x43F2: +case 0x45F2: +case 0x47F2: +case 0x49F2: +case 0x4BF2: +case 0x4DF2: +case 0x4FF2: +case 0x41F3: +case 0x43F3: +case 0x45F3: +case 0x47F3: +case 0x49F3: +case 0x4BF3: +case 0x4DF3: +case 0x4FF3: +case 0x41F4: +case 0x43F4: +case 0x45F4: +case 0x47F4: +case 0x49F4: +case 0x4BF4: +case 0x4DF4: +case 0x4FF4: +case 0x41F5: +case 0x43F5: +case 0x45F5: +case 0x47F5: +case 0x49F5: +case 0x4BF5: +case 0x4DF5: +case 0x4FF5: +case 0x41F6: +case 0x43F6: +case 0x45F6: +case 0x47F6: +case 0x49F6: +case 0x4BF6: +case 0x4DF6: +case 0x4FF6: +case 0x41F7: +case 0x43F7: +case 0x45F7: +case 0x47F7: +case 0x49F7: +case 0x4BF7: +case 0x4DF7: +case 0x4FF7: + +// LEA +case 0x41F0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + res = adr; + CPU->A[(Opcode >> 9) & 7] = res; +} +RET(12) +case 0x43F8: +case 0x45F8: +case 0x47F8: +case 0x49F8: +case 0x4BF8: +case 0x4DF8: +case 0x4FF8: + +// LEA +case 0x41F8: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + res = adr; + CPU->A[(Opcode >> 9) & 7] = res; +} +RET(8) +case 0x43F9: +case 0x45F9: +case 0x47F9: +case 0x49F9: +case 0x4BF9: +case 0x4DF9: +case 0x4FF9: + +// LEA +case 0x41F9: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + res = adr; + CPU->A[(Opcode >> 9) & 7] = res; +} +RET(12) +case 0x43FA: +case 0x45FA: +case 0x47FA: +case 0x49FA: +case 0x4BFA: +case 0x4DFA: +case 0x4FFA: + +// LEA +case 0x41FA: +{ + u32 adr; + u32 res; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + res = adr; + CPU->A[(Opcode >> 9) & 7] = res; +} +RET(8) +case 0x43FB: +case 0x45FB: +case 0x47FB: +case 0x49FB: +case 0x4BFB: +case 0x4DFB: +case 0x4FFB: + +// LEA +case 0x41FB: +{ + u32 adr; + u32 res; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + res = adr; + CPU->A[(Opcode >> 9) & 7] = res; +} +RET(12) diff --git a/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68k_op5.inc b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68k_op5.inc new file mode 100644 index 000000000..2aab7d5d4 --- /dev/null +++ b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68k_op5.inc @@ -0,0 +1,8265 @@ +case 0x50C1: +case 0x50C2: +case 0x50C3: +case 0x50C4: +case 0x50C5: +case 0x50C6: +case 0x50C7: + +// STCC +case 0x50C0: +{ + u32 res; + res = 0xFF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(6) +} +case 0x51C1: +case 0x51C2: +case 0x51C3: +case 0x51C4: +case 0x51C5: +case 0x51C6: +case 0x51C7: + +// STCC +case 0x51C0: +{ + u32 res; + res = 0; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(4) +} +case 0x52C1: +case 0x52C2: +case 0x52C3: +case 0x52C4: +case 0x52C5: +case 0x52C6: +case 0x52C7: + +// STCC +case 0x52C0: +{ + u32 res; + if (CPU->flag_notZ && (!(CPU->flag_C & 0x100))) + { + res = 0xFF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(6) + } + res = 0; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(4) +} +case 0x53C1: +case 0x53C2: +case 0x53C3: +case 0x53C4: +case 0x53C5: +case 0x53C6: +case 0x53C7: + +// STCC +case 0x53C0: +{ + u32 res; + if ((!CPU->flag_notZ) || (CPU->flag_C & 0x100)) + { + res = 0xFF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(6) + } + res = 0; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(4) +} +case 0x54C1: +case 0x54C2: +case 0x54C3: +case 0x54C4: +case 0x54C5: +case 0x54C6: +case 0x54C7: + +// STCC +case 0x54C0: +{ + u32 res; + if (!(CPU->flag_C & 0x100)) + { + res = 0xFF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(6) + } + res = 0; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(4) +} +case 0x55C1: +case 0x55C2: +case 0x55C3: +case 0x55C4: +case 0x55C5: +case 0x55C6: +case 0x55C7: + +// STCC +case 0x55C0: +{ + u32 res; + if (CPU->flag_C & 0x100) + { + res = 0xFF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(6) + } + res = 0; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(4) +} +case 0x56C1: +case 0x56C2: +case 0x56C3: +case 0x56C4: +case 0x56C5: +case 0x56C6: +case 0x56C7: + +// STCC +case 0x56C0: +{ + u32 res; + if (CPU->flag_notZ) + { + res = 0xFF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(6) + } + res = 0; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(4) +} +case 0x57C1: +case 0x57C2: +case 0x57C3: +case 0x57C4: +case 0x57C5: +case 0x57C6: +case 0x57C7: + +// STCC +case 0x57C0: +{ + u32 res; + if (!CPU->flag_notZ) + { + res = 0xFF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(6) + } + res = 0; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(4) +} +case 0x58C1: +case 0x58C2: +case 0x58C3: +case 0x58C4: +case 0x58C5: +case 0x58C6: +case 0x58C7: + +// STCC +case 0x58C0: +{ + u32 res; + if (!(CPU->flag_V & 0x80)) + { + res = 0xFF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(6) + } + res = 0; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(4) +} +case 0x59C1: +case 0x59C2: +case 0x59C3: +case 0x59C4: +case 0x59C5: +case 0x59C6: +case 0x59C7: + +// STCC +case 0x59C0: +{ + u32 res; + if (CPU->flag_V & 0x80) + { + res = 0xFF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(6) + } + res = 0; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(4) +} +case 0x5AC1: +case 0x5AC2: +case 0x5AC3: +case 0x5AC4: +case 0x5AC5: +case 0x5AC6: +case 0x5AC7: + +// STCC +case 0x5AC0: +{ + u32 res; + if (!(CPU->flag_N & 0x80)) + { + res = 0xFF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(6) + } + res = 0; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(4) +} +case 0x5BC1: +case 0x5BC2: +case 0x5BC3: +case 0x5BC4: +case 0x5BC5: +case 0x5BC6: +case 0x5BC7: + +// STCC +case 0x5BC0: +{ + u32 res; + if (CPU->flag_N & 0x80) + { + res = 0xFF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(6) + } + res = 0; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(4) +} +case 0x5CC1: +case 0x5CC2: +case 0x5CC3: +case 0x5CC4: +case 0x5CC5: +case 0x5CC6: +case 0x5CC7: + +// STCC +case 0x5CC0: +{ + u32 res; + if (!((CPU->flag_N ^ CPU->flag_V) & 0x80)) + { + res = 0xFF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(6) + } + res = 0; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(4) +} +case 0x5DC1: +case 0x5DC2: +case 0x5DC3: +case 0x5DC4: +case 0x5DC5: +case 0x5DC6: +case 0x5DC7: + +// STCC +case 0x5DC0: +{ + u32 res; + if ((CPU->flag_N ^ CPU->flag_V) & 0x80) + { + res = 0xFF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(6) + } + res = 0; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(4) +} +case 0x5EC1: +case 0x5EC2: +case 0x5EC3: +case 0x5EC4: +case 0x5EC5: +case 0x5EC6: +case 0x5EC7: + +// STCC +case 0x5EC0: +{ + u32 res; + if (CPU->flag_notZ && (!((CPU->flag_N ^ CPU->flag_V) & 0x80))) + { + res = 0xFF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(6) + } + res = 0; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(4) +} +case 0x5FC1: +case 0x5FC2: +case 0x5FC3: +case 0x5FC4: +case 0x5FC5: +case 0x5FC6: +case 0x5FC7: + +// STCC +case 0x5FC0: +{ + u32 res; + if ((!CPU->flag_notZ) || ((CPU->flag_N ^ CPU->flag_V) & 0x80)) + { + res = 0xFF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(6) + } + res = 0; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(4) +} +case 0x50D1: +case 0x50D2: +case 0x50D3: +case 0x50D4: +case 0x50D5: +case 0x50D6: +case 0x50D7: + +// STCC +case 0x50D0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) +} +case 0x51D1: +case 0x51D2: +case 0x51D3: +case 0x51D4: +case 0x51D5: +case 0x51D6: +case 0x51D7: + +// STCC +case 0x51D0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) +} +case 0x52D1: +case 0x52D2: +case 0x52D3: +case 0x52D4: +case 0x52D5: +case 0x52D6: +case 0x52D7: + +// STCC +case 0x52D0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + if (CPU->flag_notZ && (!(CPU->flag_C & 0x100))) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) +} +case 0x53D1: +case 0x53D2: +case 0x53D3: +case 0x53D4: +case 0x53D5: +case 0x53D6: +case 0x53D7: + +// STCC +case 0x53D0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + if ((!CPU->flag_notZ) || (CPU->flag_C & 0x100)) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) +} +case 0x54D1: +case 0x54D2: +case 0x54D3: +case 0x54D4: +case 0x54D5: +case 0x54D6: +case 0x54D7: + +// STCC +case 0x54D0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + if (!(CPU->flag_C & 0x100)) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) +} +case 0x55D1: +case 0x55D2: +case 0x55D3: +case 0x55D4: +case 0x55D5: +case 0x55D6: +case 0x55D7: + +// STCC +case 0x55D0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + if (CPU->flag_C & 0x100) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) +} +case 0x56D1: +case 0x56D2: +case 0x56D3: +case 0x56D4: +case 0x56D5: +case 0x56D6: +case 0x56D7: + +// STCC +case 0x56D0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + if (CPU->flag_notZ) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) +} +case 0x57D1: +case 0x57D2: +case 0x57D3: +case 0x57D4: +case 0x57D5: +case 0x57D6: +case 0x57D7: + +// STCC +case 0x57D0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + if (!CPU->flag_notZ) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) +} +case 0x58D1: +case 0x58D2: +case 0x58D3: +case 0x58D4: +case 0x58D5: +case 0x58D6: +case 0x58D7: + +// STCC +case 0x58D0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + if (!(CPU->flag_V & 0x80)) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) +} +case 0x59D1: +case 0x59D2: +case 0x59D3: +case 0x59D4: +case 0x59D5: +case 0x59D6: +case 0x59D7: + +// STCC +case 0x59D0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + if (CPU->flag_V & 0x80) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) +} +case 0x5AD1: +case 0x5AD2: +case 0x5AD3: +case 0x5AD4: +case 0x5AD5: +case 0x5AD6: +case 0x5AD7: + +// STCC +case 0x5AD0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + if (!(CPU->flag_N & 0x80)) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) +} +case 0x5BD1: +case 0x5BD2: +case 0x5BD3: +case 0x5BD4: +case 0x5BD5: +case 0x5BD6: +case 0x5BD7: + +// STCC +case 0x5BD0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + if (CPU->flag_N & 0x80) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) +} +case 0x5CD1: +case 0x5CD2: +case 0x5CD3: +case 0x5CD4: +case 0x5CD5: +case 0x5CD6: +case 0x5CD7: + +// STCC +case 0x5CD0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + if (!((CPU->flag_N ^ CPU->flag_V) & 0x80)) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) +} +case 0x5DD1: +case 0x5DD2: +case 0x5DD3: +case 0x5DD4: +case 0x5DD5: +case 0x5DD6: +case 0x5DD7: + +// STCC +case 0x5DD0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + if ((CPU->flag_N ^ CPU->flag_V) & 0x80) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) +} +case 0x5ED1: +case 0x5ED2: +case 0x5ED3: +case 0x5ED4: +case 0x5ED5: +case 0x5ED6: +case 0x5ED7: + +// STCC +case 0x5ED0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + if (CPU->flag_notZ && (!((CPU->flag_N ^ CPU->flag_V) & 0x80))) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) +} +case 0x5FD1: +case 0x5FD2: +case 0x5FD3: +case 0x5FD4: +case 0x5FD5: +case 0x5FD6: +case 0x5FD7: + +// STCC +case 0x5FD0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + if ((!CPU->flag_notZ) || ((CPU->flag_N ^ CPU->flag_V) & 0x80)) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) +} +case 0x50D9: +case 0x50DA: +case 0x50DB: +case 0x50DC: +case 0x50DD: +case 0x50DE: + +// STCC +case 0x50D8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) +} +case 0x51D9: +case 0x51DA: +case 0x51DB: +case 0x51DC: +case 0x51DD: +case 0x51DE: + +// STCC +case 0x51D8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) +} +case 0x52D9: +case 0x52DA: +case 0x52DB: +case 0x52DC: +case 0x52DD: +case 0x52DE: + +// STCC +case 0x52D8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + if (CPU->flag_notZ && (!(CPU->flag_C & 0x100))) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) +} +case 0x53D9: +case 0x53DA: +case 0x53DB: +case 0x53DC: +case 0x53DD: +case 0x53DE: + +// STCC +case 0x53D8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + if ((!CPU->flag_notZ) || (CPU->flag_C & 0x100)) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) +} +case 0x54D9: +case 0x54DA: +case 0x54DB: +case 0x54DC: +case 0x54DD: +case 0x54DE: + +// STCC +case 0x54D8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + if (!(CPU->flag_C & 0x100)) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) +} +case 0x55D9: +case 0x55DA: +case 0x55DB: +case 0x55DC: +case 0x55DD: +case 0x55DE: + +// STCC +case 0x55D8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + if (CPU->flag_C & 0x100) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) +} +case 0x56D9: +case 0x56DA: +case 0x56DB: +case 0x56DC: +case 0x56DD: +case 0x56DE: + +// STCC +case 0x56D8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + if (CPU->flag_notZ) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) +} +case 0x57D9: +case 0x57DA: +case 0x57DB: +case 0x57DC: +case 0x57DD: +case 0x57DE: + +// STCC +case 0x57D8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + if (!CPU->flag_notZ) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) +} +case 0x58D9: +case 0x58DA: +case 0x58DB: +case 0x58DC: +case 0x58DD: +case 0x58DE: + +// STCC +case 0x58D8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + if (!(CPU->flag_V & 0x80)) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) +} +case 0x59D9: +case 0x59DA: +case 0x59DB: +case 0x59DC: +case 0x59DD: +case 0x59DE: + +// STCC +case 0x59D8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + if (CPU->flag_V & 0x80) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) +} +case 0x5AD9: +case 0x5ADA: +case 0x5ADB: +case 0x5ADC: +case 0x5ADD: +case 0x5ADE: + +// STCC +case 0x5AD8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + if (!(CPU->flag_N & 0x80)) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) +} +case 0x5BD9: +case 0x5BDA: +case 0x5BDB: +case 0x5BDC: +case 0x5BDD: +case 0x5BDE: + +// STCC +case 0x5BD8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + if (CPU->flag_N & 0x80) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) +} +case 0x5CD9: +case 0x5CDA: +case 0x5CDB: +case 0x5CDC: +case 0x5CDD: +case 0x5CDE: + +// STCC +case 0x5CD8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + if (!((CPU->flag_N ^ CPU->flag_V) & 0x80)) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) +} +case 0x5DD9: +case 0x5DDA: +case 0x5DDB: +case 0x5DDC: +case 0x5DDD: +case 0x5DDE: + +// STCC +case 0x5DD8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + if ((CPU->flag_N ^ CPU->flag_V) & 0x80) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) +} +case 0x5ED9: +case 0x5EDA: +case 0x5EDB: +case 0x5EDC: +case 0x5EDD: +case 0x5EDE: + +// STCC +case 0x5ED8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + if (CPU->flag_notZ && (!((CPU->flag_N ^ CPU->flag_V) & 0x80))) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) +} +case 0x5FD9: +case 0x5FDA: +case 0x5FDB: +case 0x5FDC: +case 0x5FDD: +case 0x5FDE: + +// STCC +case 0x5FD8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + if ((!CPU->flag_notZ) || ((CPU->flag_N ^ CPU->flag_V) & 0x80)) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) +} +case 0x50E1: +case 0x50E2: +case 0x50E3: +case 0x50E4: +case 0x50E5: +case 0x50E6: + +// STCC +case 0x50E0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) +} +case 0x51E1: +case 0x51E2: +case 0x51E3: +case 0x51E4: +case 0x51E5: +case 0x51E6: + +// STCC +case 0x51E0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) +} +case 0x52E1: +case 0x52E2: +case 0x52E3: +case 0x52E4: +case 0x52E5: +case 0x52E6: + +// STCC +case 0x52E0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + if (CPU->flag_notZ && (!(CPU->flag_C & 0x100))) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) +} +case 0x53E1: +case 0x53E2: +case 0x53E3: +case 0x53E4: +case 0x53E5: +case 0x53E6: + +// STCC +case 0x53E0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + if ((!CPU->flag_notZ) || (CPU->flag_C & 0x100)) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) +} +case 0x54E1: +case 0x54E2: +case 0x54E3: +case 0x54E4: +case 0x54E5: +case 0x54E6: + +// STCC +case 0x54E0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + if (!(CPU->flag_C & 0x100)) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) +} +case 0x55E1: +case 0x55E2: +case 0x55E3: +case 0x55E4: +case 0x55E5: +case 0x55E6: + +// STCC +case 0x55E0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + if (CPU->flag_C & 0x100) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) +} +case 0x56E1: +case 0x56E2: +case 0x56E3: +case 0x56E4: +case 0x56E5: +case 0x56E6: + +// STCC +case 0x56E0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + if (CPU->flag_notZ) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) +} +case 0x57E1: +case 0x57E2: +case 0x57E3: +case 0x57E4: +case 0x57E5: +case 0x57E6: + +// STCC +case 0x57E0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + if (!CPU->flag_notZ) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) +} +case 0x58E1: +case 0x58E2: +case 0x58E3: +case 0x58E4: +case 0x58E5: +case 0x58E6: + +// STCC +case 0x58E0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + if (!(CPU->flag_V & 0x80)) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) +} +case 0x59E1: +case 0x59E2: +case 0x59E3: +case 0x59E4: +case 0x59E5: +case 0x59E6: + +// STCC +case 0x59E0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + if (CPU->flag_V & 0x80) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) +} +case 0x5AE1: +case 0x5AE2: +case 0x5AE3: +case 0x5AE4: +case 0x5AE5: +case 0x5AE6: + +// STCC +case 0x5AE0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + if (!(CPU->flag_N & 0x80)) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) +} +case 0x5BE1: +case 0x5BE2: +case 0x5BE3: +case 0x5BE4: +case 0x5BE5: +case 0x5BE6: + +// STCC +case 0x5BE0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + if (CPU->flag_N & 0x80) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) +} +case 0x5CE1: +case 0x5CE2: +case 0x5CE3: +case 0x5CE4: +case 0x5CE5: +case 0x5CE6: + +// STCC +case 0x5CE0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + if (!((CPU->flag_N ^ CPU->flag_V) & 0x80)) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) +} +case 0x5DE1: +case 0x5DE2: +case 0x5DE3: +case 0x5DE4: +case 0x5DE5: +case 0x5DE6: + +// STCC +case 0x5DE0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + if ((CPU->flag_N ^ CPU->flag_V) & 0x80) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) +} +case 0x5EE1: +case 0x5EE2: +case 0x5EE3: +case 0x5EE4: +case 0x5EE5: +case 0x5EE6: + +// STCC +case 0x5EE0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + if (CPU->flag_notZ && (!((CPU->flag_N ^ CPU->flag_V) & 0x80))) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) +} +case 0x5FE1: +case 0x5FE2: +case 0x5FE3: +case 0x5FE4: +case 0x5FE5: +case 0x5FE6: + +// STCC +case 0x5FE0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + if ((!CPU->flag_notZ) || ((CPU->flag_N ^ CPU->flag_V) & 0x80)) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) +} +case 0x50E9: +case 0x50EA: +case 0x50EB: +case 0x50EC: +case 0x50ED: +case 0x50EE: +case 0x50EF: + +// STCC +case 0x50E8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) +} +case 0x51E9: +case 0x51EA: +case 0x51EB: +case 0x51EC: +case 0x51ED: +case 0x51EE: +case 0x51EF: + +// STCC +case 0x51E8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) +} +case 0x52E9: +case 0x52EA: +case 0x52EB: +case 0x52EC: +case 0x52ED: +case 0x52EE: +case 0x52EF: + +// STCC +case 0x52E8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + if (CPU->flag_notZ && (!(CPU->flag_C & 0x100))) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) +} +case 0x53E9: +case 0x53EA: +case 0x53EB: +case 0x53EC: +case 0x53ED: +case 0x53EE: +case 0x53EF: + +// STCC +case 0x53E8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + if ((!CPU->flag_notZ) || (CPU->flag_C & 0x100)) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) +} +case 0x54E9: +case 0x54EA: +case 0x54EB: +case 0x54EC: +case 0x54ED: +case 0x54EE: +case 0x54EF: + +// STCC +case 0x54E8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + if (!(CPU->flag_C & 0x100)) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) +} +case 0x55E9: +case 0x55EA: +case 0x55EB: +case 0x55EC: +case 0x55ED: +case 0x55EE: +case 0x55EF: + +// STCC +case 0x55E8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + if (CPU->flag_C & 0x100) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) +} +case 0x56E9: +case 0x56EA: +case 0x56EB: +case 0x56EC: +case 0x56ED: +case 0x56EE: +case 0x56EF: + +// STCC +case 0x56E8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + if (CPU->flag_notZ) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) +} +case 0x57E9: +case 0x57EA: +case 0x57EB: +case 0x57EC: +case 0x57ED: +case 0x57EE: +case 0x57EF: + +// STCC +case 0x57E8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + if (!CPU->flag_notZ) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) +} +case 0x58E9: +case 0x58EA: +case 0x58EB: +case 0x58EC: +case 0x58ED: +case 0x58EE: +case 0x58EF: + +// STCC +case 0x58E8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + if (!(CPU->flag_V & 0x80)) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) +} +case 0x59E9: +case 0x59EA: +case 0x59EB: +case 0x59EC: +case 0x59ED: +case 0x59EE: +case 0x59EF: + +// STCC +case 0x59E8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + if (CPU->flag_V & 0x80) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) +} +case 0x5AE9: +case 0x5AEA: +case 0x5AEB: +case 0x5AEC: +case 0x5AED: +case 0x5AEE: +case 0x5AEF: + +// STCC +case 0x5AE8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + if (!(CPU->flag_N & 0x80)) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) +} +case 0x5BE9: +case 0x5BEA: +case 0x5BEB: +case 0x5BEC: +case 0x5BED: +case 0x5BEE: +case 0x5BEF: + +// STCC +case 0x5BE8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + if (CPU->flag_N & 0x80) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) +} +case 0x5CE9: +case 0x5CEA: +case 0x5CEB: +case 0x5CEC: +case 0x5CED: +case 0x5CEE: +case 0x5CEF: + +// STCC +case 0x5CE8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + if (!((CPU->flag_N ^ CPU->flag_V) & 0x80)) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) +} +case 0x5DE9: +case 0x5DEA: +case 0x5DEB: +case 0x5DEC: +case 0x5DED: +case 0x5DEE: +case 0x5DEF: + +// STCC +case 0x5DE8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + if ((CPU->flag_N ^ CPU->flag_V) & 0x80) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) +} +case 0x5EE9: +case 0x5EEA: +case 0x5EEB: +case 0x5EEC: +case 0x5EED: +case 0x5EEE: +case 0x5EEF: + +// STCC +case 0x5EE8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + if (CPU->flag_notZ && (!((CPU->flag_N ^ CPU->flag_V) & 0x80))) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) +} +case 0x5FE9: +case 0x5FEA: +case 0x5FEB: +case 0x5FEC: +case 0x5FED: +case 0x5FEE: +case 0x5FEF: + +// STCC +case 0x5FE8: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + if ((!CPU->flag_notZ) || ((CPU->flag_N ^ CPU->flag_V) & 0x80)) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) +} +case 0x50F1: +case 0x50F2: +case 0x50F3: +case 0x50F4: +case 0x50F5: +case 0x50F6: +case 0x50F7: + +// STCC +case 0x50F0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(18) +} +case 0x51F1: +case 0x51F2: +case 0x51F3: +case 0x51F4: +case 0x51F5: +case 0x51F6: +case 0x51F7: + +// STCC +case 0x51F0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(18) +} +case 0x52F1: +case 0x52F2: +case 0x52F3: +case 0x52F4: +case 0x52F5: +case 0x52F6: +case 0x52F7: + +// STCC +case 0x52F0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + if (CPU->flag_notZ && (!(CPU->flag_C & 0x100))) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(18) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(18) +} +case 0x53F1: +case 0x53F2: +case 0x53F3: +case 0x53F4: +case 0x53F5: +case 0x53F6: +case 0x53F7: + +// STCC +case 0x53F0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + if ((!CPU->flag_notZ) || (CPU->flag_C & 0x100)) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(18) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(18) +} +case 0x54F1: +case 0x54F2: +case 0x54F3: +case 0x54F4: +case 0x54F5: +case 0x54F6: +case 0x54F7: + +// STCC +case 0x54F0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + if (!(CPU->flag_C & 0x100)) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(18) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(18) +} +case 0x55F1: +case 0x55F2: +case 0x55F3: +case 0x55F4: +case 0x55F5: +case 0x55F6: +case 0x55F7: + +// STCC +case 0x55F0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + if (CPU->flag_C & 0x100) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(18) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(18) +} +case 0x56F1: +case 0x56F2: +case 0x56F3: +case 0x56F4: +case 0x56F5: +case 0x56F6: +case 0x56F7: + +// STCC +case 0x56F0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + if (CPU->flag_notZ) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(18) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(18) +} +case 0x57F1: +case 0x57F2: +case 0x57F3: +case 0x57F4: +case 0x57F5: +case 0x57F6: +case 0x57F7: + +// STCC +case 0x57F0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + if (!CPU->flag_notZ) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(18) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(18) +} +case 0x58F1: +case 0x58F2: +case 0x58F3: +case 0x58F4: +case 0x58F5: +case 0x58F6: +case 0x58F7: + +// STCC +case 0x58F0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + if (!(CPU->flag_V & 0x80)) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(18) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(18) +} +case 0x59F1: +case 0x59F2: +case 0x59F3: +case 0x59F4: +case 0x59F5: +case 0x59F6: +case 0x59F7: + +// STCC +case 0x59F0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + if (CPU->flag_V & 0x80) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(18) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(18) +} +case 0x5AF1: +case 0x5AF2: +case 0x5AF3: +case 0x5AF4: +case 0x5AF5: +case 0x5AF6: +case 0x5AF7: + +// STCC +case 0x5AF0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + if (!(CPU->flag_N & 0x80)) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(18) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(18) +} +case 0x5BF1: +case 0x5BF2: +case 0x5BF3: +case 0x5BF4: +case 0x5BF5: +case 0x5BF6: +case 0x5BF7: + +// STCC +case 0x5BF0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + if (CPU->flag_N & 0x80) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(18) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(18) +} +case 0x5CF1: +case 0x5CF2: +case 0x5CF3: +case 0x5CF4: +case 0x5CF5: +case 0x5CF6: +case 0x5CF7: + +// STCC +case 0x5CF0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + if (!((CPU->flag_N ^ CPU->flag_V) & 0x80)) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(18) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(18) +} +case 0x5DF1: +case 0x5DF2: +case 0x5DF3: +case 0x5DF4: +case 0x5DF5: +case 0x5DF6: +case 0x5DF7: + +// STCC +case 0x5DF0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + if ((CPU->flag_N ^ CPU->flag_V) & 0x80) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(18) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(18) +} +case 0x5EF1: +case 0x5EF2: +case 0x5EF3: +case 0x5EF4: +case 0x5EF5: +case 0x5EF6: +case 0x5EF7: + +// STCC +case 0x5EF0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + if (CPU->flag_notZ && (!((CPU->flag_N ^ CPU->flag_V) & 0x80))) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(18) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(18) +} +case 0x5FF1: +case 0x5FF2: +case 0x5FF3: +case 0x5FF4: +case 0x5FF5: +case 0x5FF6: +case 0x5FF7: + +// STCC +case 0x5FF0: +{ + u32 adr; + u32 res; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + if ((!CPU->flag_notZ) || ((CPU->flag_N ^ CPU->flag_V) & 0x80)) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(18) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(18) +} + +// STCC +case 0x50F8: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) +} + +// STCC +case 0x51F8: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) +} + +// STCC +case 0x52F8: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + if (CPU->flag_notZ && (!(CPU->flag_C & 0x100))) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) +} + +// STCC +case 0x53F8: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + if ((!CPU->flag_notZ) || (CPU->flag_C & 0x100)) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) +} + +// STCC +case 0x54F8: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + if (!(CPU->flag_C & 0x100)) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) +} + +// STCC +case 0x55F8: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + if (CPU->flag_C & 0x100) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) +} + +// STCC +case 0x56F8: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + if (CPU->flag_notZ) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) +} + +// STCC +case 0x57F8: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + if (!CPU->flag_notZ) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) +} + +// STCC +case 0x58F8: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + if (!(CPU->flag_V & 0x80)) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) +} + +// STCC +case 0x59F8: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + if (CPU->flag_V & 0x80) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) +} + +// STCC +case 0x5AF8: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + if (!(CPU->flag_N & 0x80)) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) +} + +// STCC +case 0x5BF8: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + if (CPU->flag_N & 0x80) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) +} + +// STCC +case 0x5CF8: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + if (!((CPU->flag_N ^ CPU->flag_V) & 0x80)) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) +} + +// STCC +case 0x5DF8: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + if ((CPU->flag_N ^ CPU->flag_V) & 0x80) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) +} + +// STCC +case 0x5EF8: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + if (CPU->flag_notZ && (!((CPU->flag_N ^ CPU->flag_V) & 0x80))) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) +} + +// STCC +case 0x5FF8: +{ + u32 adr; + u32 res; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + if ((!CPU->flag_notZ) || ((CPU->flag_N ^ CPU->flag_V) & 0x80)) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(16) +} + +// STCC +case 0x50F9: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(20) +} + +// STCC +case 0x51F9: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(20) +} + +// STCC +case 0x52F9: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + if (CPU->flag_notZ && (!(CPU->flag_C & 0x100))) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(20) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(20) +} + +// STCC +case 0x53F9: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + if ((!CPU->flag_notZ) || (CPU->flag_C & 0x100)) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(20) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(20) +} + +// STCC +case 0x54F9: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + if (!(CPU->flag_C & 0x100)) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(20) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(20) +} + +// STCC +case 0x55F9: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + if (CPU->flag_C & 0x100) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(20) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(20) +} + +// STCC +case 0x56F9: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + if (CPU->flag_notZ) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(20) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(20) +} + +// STCC +case 0x57F9: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + if (!CPU->flag_notZ) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(20) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(20) +} + +// STCC +case 0x58F9: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + if (!(CPU->flag_V & 0x80)) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(20) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(20) +} + +// STCC +case 0x59F9: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + if (CPU->flag_V & 0x80) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(20) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(20) +} + +// STCC +case 0x5AF9: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + if (!(CPU->flag_N & 0x80)) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(20) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(20) +} + +// STCC +case 0x5BF9: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + if (CPU->flag_N & 0x80) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(20) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(20) +} + +// STCC +case 0x5CF9: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + if (!((CPU->flag_N ^ CPU->flag_V) & 0x80)) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(20) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(20) +} + +// STCC +case 0x5DF9: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + if ((CPU->flag_N ^ CPU->flag_V) & 0x80) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(20) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(20) +} + +// STCC +case 0x5EF9: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + if (CPU->flag_notZ && (!((CPU->flag_N ^ CPU->flag_V) & 0x80))) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(20) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(20) +} + +// STCC +case 0x5FF9: +{ + u32 adr; + u32 res; + adr = (s32)FETCH_LONG; + PC += 4; + if ((!CPU->flag_notZ) || ((CPU->flag_N ^ CPU->flag_V) & 0x80)) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(20) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(20) +} + +// STCC +case 0x50DF: +{ + u32 adr; + u32 res; + adr = CPU->A[7]; + CPU->A[7] += 2; + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) +} + +// STCC +case 0x51DF: +{ + u32 adr; + u32 res; + adr = CPU->A[7]; + CPU->A[7] += 2; + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) +} + +// STCC +case 0x52DF: +{ + u32 adr; + u32 res; + adr = CPU->A[7]; + CPU->A[7] += 2; + if (CPU->flag_notZ && (!(CPU->flag_C & 0x100))) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) +} + +// STCC +case 0x53DF: +{ + u32 adr; + u32 res; + adr = CPU->A[7]; + CPU->A[7] += 2; + if ((!CPU->flag_notZ) || (CPU->flag_C & 0x100)) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) +} + +// STCC +case 0x54DF: +{ + u32 adr; + u32 res; + adr = CPU->A[7]; + CPU->A[7] += 2; + if (!(CPU->flag_C & 0x100)) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) +} + +// STCC +case 0x55DF: +{ + u32 adr; + u32 res; + adr = CPU->A[7]; + CPU->A[7] += 2; + if (CPU->flag_C & 0x100) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) +} + +// STCC +case 0x56DF: +{ + u32 adr; + u32 res; + adr = CPU->A[7]; + CPU->A[7] += 2; + if (CPU->flag_notZ) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) +} + +// STCC +case 0x57DF: +{ + u32 adr; + u32 res; + adr = CPU->A[7]; + CPU->A[7] += 2; + if (!CPU->flag_notZ) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) +} + +// STCC +case 0x58DF: +{ + u32 adr; + u32 res; + adr = CPU->A[7]; + CPU->A[7] += 2; + if (!(CPU->flag_V & 0x80)) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) +} + +// STCC +case 0x59DF: +{ + u32 adr; + u32 res; + adr = CPU->A[7]; + CPU->A[7] += 2; + if (CPU->flag_V & 0x80) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) +} + +// STCC +case 0x5ADF: +{ + u32 adr; + u32 res; + adr = CPU->A[7]; + CPU->A[7] += 2; + if (!(CPU->flag_N & 0x80)) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) +} + +// STCC +case 0x5BDF: +{ + u32 adr; + u32 res; + adr = CPU->A[7]; + CPU->A[7] += 2; + if (CPU->flag_N & 0x80) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) +} + +// STCC +case 0x5CDF: +{ + u32 adr; + u32 res; + adr = CPU->A[7]; + CPU->A[7] += 2; + if (!((CPU->flag_N ^ CPU->flag_V) & 0x80)) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) +} + +// STCC +case 0x5DDF: +{ + u32 adr; + u32 res; + adr = CPU->A[7]; + CPU->A[7] += 2; + if ((CPU->flag_N ^ CPU->flag_V) & 0x80) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) +} + +// STCC +case 0x5EDF: +{ + u32 adr; + u32 res; + adr = CPU->A[7]; + CPU->A[7] += 2; + if (CPU->flag_notZ && (!((CPU->flag_N ^ CPU->flag_V) & 0x80))) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) +} + +// STCC +case 0x5FDF: +{ + u32 adr; + u32 res; + adr = CPU->A[7]; + CPU->A[7] += 2; + if ((!CPU->flag_notZ) || ((CPU->flag_N ^ CPU->flag_V) & 0x80)) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(12) +} + +// STCC +case 0x50E7: +{ + u32 adr; + u32 res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) +} + +// STCC +case 0x51E7: +{ + u32 adr; + u32 res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) +} + +// STCC +case 0x52E7: +{ + u32 adr; + u32 res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + if (CPU->flag_notZ && (!(CPU->flag_C & 0x100))) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) +} + +// STCC +case 0x53E7: +{ + u32 adr; + u32 res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + if ((!CPU->flag_notZ) || (CPU->flag_C & 0x100)) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) +} + +// STCC +case 0x54E7: +{ + u32 adr; + u32 res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + if (!(CPU->flag_C & 0x100)) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) +} + +// STCC +case 0x55E7: +{ + u32 adr; + u32 res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + if (CPU->flag_C & 0x100) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) +} + +// STCC +case 0x56E7: +{ + u32 adr; + u32 res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + if (CPU->flag_notZ) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) +} + +// STCC +case 0x57E7: +{ + u32 adr; + u32 res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + if (!CPU->flag_notZ) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) +} + +// STCC +case 0x58E7: +{ + u32 adr; + u32 res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + if (!(CPU->flag_V & 0x80)) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) +} + +// STCC +case 0x59E7: +{ + u32 adr; + u32 res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + if (CPU->flag_V & 0x80) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) +} + +// STCC +case 0x5AE7: +{ + u32 adr; + u32 res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + if (!(CPU->flag_N & 0x80)) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) +} + +// STCC +case 0x5BE7: +{ + u32 adr; + u32 res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + if (CPU->flag_N & 0x80) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) +} + +// STCC +case 0x5CE7: +{ + u32 adr; + u32 res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + if (!((CPU->flag_N ^ CPU->flag_V) & 0x80)) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) +} + +// STCC +case 0x5DE7: +{ + u32 adr; + u32 res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + if ((CPU->flag_N ^ CPU->flag_V) & 0x80) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) +} + +// STCC +case 0x5EE7: +{ + u32 adr; + u32 res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + if (CPU->flag_notZ && (!((CPU->flag_N ^ CPU->flag_V) & 0x80))) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) +} + +// STCC +case 0x5FE7: +{ + u32 adr; + u32 res; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + if ((!CPU->flag_notZ) || ((CPU->flag_N ^ CPU->flag_V) & 0x80)) + { + res = 0xFF; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) + } + res = 0; + PRE_IO + WRITE_BYTE_F(adr, res) + POST_IO + RET(14) +} +case 0x50C9: +case 0x50CA: +case 0x50CB: +case 0x50CC: +case 0x50CD: +case 0x50CE: +case 0x50CF: + +// DBCC +case 0x50C8: +{ + PC += 2; +} +RET(12) +case 0x51C9: +case 0x51CA: +case 0x51CB: +case 0x51CC: +case 0x51CD: +case 0x51CE: +case 0x51CF: + +// DBCC +case 0x51C8: +{ + u32 res; + res = (u16)CPU->D[(Opcode >> 0) & 7]; + res--; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 0) & 7])) = res; + if ((s32)res != -1) + { + PC += (s32)(s16)FETCH_WORD; + PC -= CPU->BasePC; + SET_PC(PC); + RET(10) + } + PC += 2; +} +RET(14) +case 0x52C9: +case 0x52CA: +case 0x52CB: +case 0x52CC: +case 0x52CD: +case 0x52CE: +case 0x52CF: + +// DBCC +case 0x52C8: +{ + u32 res; + if ((!CPU->flag_notZ) || (CPU->flag_C & 0x100)) + { + res = (u16)CPU->D[(Opcode >> 0) & 7]; + res--; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 0) & 7])) = res; + if ((s32)res != -1) + { + PC += (s32)(s16)FETCH_WORD; + PC -= CPU->BasePC; + SET_PC(PC); + RET(10) + } + } + else + { + PC += 2; + RET(12) + } + PC += 2; +} +RET(14) +case 0x53C9: +case 0x53CA: +case 0x53CB: +case 0x53CC: +case 0x53CD: +case 0x53CE: +case 0x53CF: + +// DBCC +case 0x53C8: +{ + u32 res; + if (CPU->flag_notZ && (!(CPU->flag_C & 0x100))) + { + res = (u16)CPU->D[(Opcode >> 0) & 7]; + res--; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 0) & 7])) = res; + if ((s32)res != -1) + { + PC += (s32)(s16)FETCH_WORD; + PC -= CPU->BasePC; + SET_PC(PC); + RET(10) + } + } + else + { + PC += 2; + RET(12) + } + PC += 2; +} +RET(14) +case 0x54C9: +case 0x54CA: +case 0x54CB: +case 0x54CC: +case 0x54CD: +case 0x54CE: +case 0x54CF: + +// DBCC +case 0x54C8: +{ + u32 res; + if (CPU->flag_C & 0x100) + { + res = (u16)CPU->D[(Opcode >> 0) & 7]; + res--; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 0) & 7])) = res; + if ((s32)res != -1) + { + PC += (s32)(s16)FETCH_WORD; + PC -= CPU->BasePC; + SET_PC(PC); + RET(10) + } + } + else + { + PC += 2; + RET(12) + } + PC += 2; +} +RET(14) +case 0x55C9: +case 0x55CA: +case 0x55CB: +case 0x55CC: +case 0x55CD: +case 0x55CE: +case 0x55CF: + +// DBCC +case 0x55C8: +{ + u32 res; + if (!(CPU->flag_C & 0x100)) + { + res = (u16)CPU->D[(Opcode >> 0) & 7]; + res--; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 0) & 7])) = res; + if ((s32)res != -1) + { + PC += (s32)(s16)FETCH_WORD; + PC -= CPU->BasePC; + SET_PC(PC); + RET(10) + } + } + else + { + PC += 2; + RET(12) + } + PC += 2; +} +RET(14) +case 0x56C9: +case 0x56CA: +case 0x56CB: +case 0x56CC: +case 0x56CD: +case 0x56CE: +case 0x56CF: + +// DBCC +case 0x56C8: +{ + u32 res; + if (!CPU->flag_notZ) + { + res = (u16)CPU->D[(Opcode >> 0) & 7]; + res--; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 0) & 7])) = res; + if ((s32)res != -1) + { + PC += (s32)(s16)FETCH_WORD; + PC -= CPU->BasePC; + SET_PC(PC); + RET(10) + } + } + else + { + PC += 2; + RET(12) + } + PC += 2; +} +RET(14) +case 0x57C9: +case 0x57CA: +case 0x57CB: +case 0x57CC: +case 0x57CD: +case 0x57CE: +case 0x57CF: + +// DBCC +case 0x57C8: +{ + u32 res; + if (CPU->flag_notZ) + { + res = (u16)CPU->D[(Opcode >> 0) & 7]; + res--; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 0) & 7])) = res; + if ((s32)res != -1) + { + PC += (s32)(s16)FETCH_WORD; + PC -= CPU->BasePC; + SET_PC(PC); + RET(10) + } + } + else + { + PC += 2; + RET(12) + } + PC += 2; +} +RET(14) +case 0x58C9: +case 0x58CA: +case 0x58CB: +case 0x58CC: +case 0x58CD: +case 0x58CE: +case 0x58CF: + +// DBCC +case 0x58C8: +{ + u32 res; + if (CPU->flag_V & 0x80) + { + res = (u16)CPU->D[(Opcode >> 0) & 7]; + res--; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 0) & 7])) = res; + if ((s32)res != -1) + { + PC += (s32)(s16)FETCH_WORD; + PC -= CPU->BasePC; + SET_PC(PC); + RET(10) + } + } + else + { + PC += 2; + RET(12) + } + PC += 2; +} +RET(14) +case 0x59C9: +case 0x59CA: +case 0x59CB: +case 0x59CC: +case 0x59CD: +case 0x59CE: +case 0x59CF: + +// DBCC +case 0x59C8: +{ + u32 res; + if (!(CPU->flag_V & 0x80)) + { + res = (u16)CPU->D[(Opcode >> 0) & 7]; + res--; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 0) & 7])) = res; + if ((s32)res != -1) + { + PC += (s32)(s16)FETCH_WORD; + PC -= CPU->BasePC; + SET_PC(PC); + RET(10) + } + } + else + { + PC += 2; + RET(12) + } + PC += 2; +} +RET(14) +case 0x5AC9: +case 0x5ACA: +case 0x5ACB: +case 0x5ACC: +case 0x5ACD: +case 0x5ACE: +case 0x5ACF: + +// DBCC +case 0x5AC8: +{ + u32 res; + if (CPU->flag_N & 0x80) + { + res = (u16)CPU->D[(Opcode >> 0) & 7]; + res--; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 0) & 7])) = res; + if ((s32)res != -1) + { + PC += (s32)(s16)FETCH_WORD; + PC -= CPU->BasePC; + SET_PC(PC); + RET(10) + } + } + else + { + PC += 2; + RET(12) + } + PC += 2; +} +RET(14) +case 0x5BC9: +case 0x5BCA: +case 0x5BCB: +case 0x5BCC: +case 0x5BCD: +case 0x5BCE: +case 0x5BCF: + +// DBCC +case 0x5BC8: +{ + u32 res; + if (!(CPU->flag_N & 0x80)) + { + res = (u16)CPU->D[(Opcode >> 0) & 7]; + res--; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 0) & 7])) = res; + if ((s32)res != -1) + { + PC += (s32)(s16)FETCH_WORD; + PC -= CPU->BasePC; + SET_PC(PC); + RET(10) + } + } + else + { + PC += 2; + RET(12) + } + PC += 2; +} +RET(14) +case 0x5CC9: +case 0x5CCA: +case 0x5CCB: +case 0x5CCC: +case 0x5CCD: +case 0x5CCE: +case 0x5CCF: + +// DBCC +case 0x5CC8: +{ + u32 res; + if ((CPU->flag_N ^ CPU->flag_V) & 0x80) + { + res = (u16)CPU->D[(Opcode >> 0) & 7]; + res--; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 0) & 7])) = res; + if ((s32)res != -1) + { + PC += (s32)(s16)FETCH_WORD; + PC -= CPU->BasePC; + SET_PC(PC); + RET(10) + } + } + else + { + PC += 2; + RET(12) + } + PC += 2; +} +RET(14) +case 0x5DC9: +case 0x5DCA: +case 0x5DCB: +case 0x5DCC: +case 0x5DCD: +case 0x5DCE: +case 0x5DCF: + +// DBCC +case 0x5DC8: +{ + u32 res; + if (!((CPU->flag_N ^ CPU->flag_V) & 0x80)) + { + res = (u16)CPU->D[(Opcode >> 0) & 7]; + res--; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 0) & 7])) = res; + if ((s32)res != -1) + { + PC += (s32)(s16)FETCH_WORD; + PC -= CPU->BasePC; + SET_PC(PC); + RET(10) + } + } + else + { + PC += 2; + RET(12) + } + PC += 2; +} +RET(14) +case 0x5EC9: +case 0x5ECA: +case 0x5ECB: +case 0x5ECC: +case 0x5ECD: +case 0x5ECE: +case 0x5ECF: + +// DBCC +case 0x5EC8: +{ + u32 res; + if ((!CPU->flag_notZ) || ((CPU->flag_N ^ CPU->flag_V) & 0x80)) + { + res = (u16)CPU->D[(Opcode >> 0) & 7]; + res--; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 0) & 7])) = res; + if ((s32)res != -1) + { + PC += (s32)(s16)FETCH_WORD; + PC -= CPU->BasePC; + SET_PC(PC); + RET(10) + } + } + else + { + PC += 2; + RET(12) + } + PC += 2; +} +RET(14) +case 0x5FC9: +case 0x5FCA: +case 0x5FCB: +case 0x5FCC: +case 0x5FCD: +case 0x5FCE: +case 0x5FCF: + +// DBCC +case 0x5FC8: +{ + u32 res; + if (CPU->flag_notZ && (!((CPU->flag_N ^ CPU->flag_V) & 0x80))) + { + res = (u16)CPU->D[(Opcode >> 0) & 7]; + res--; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 0) & 7])) = res; + if ((s32)res != -1) + { + PC += (s32)(s16)FETCH_WORD; + PC -= CPU->BasePC; + SET_PC(PC); + RET(10) + } + } + else + { + PC += 2; + RET(12) + } + PC += 2; +} +RET(14) +case 0x5200: +case 0x5400: +case 0x5600: +case 0x5800: +case 0x5A00: +case 0x5C00: +case 0x5E00: +case 0x5001: +case 0x5201: +case 0x5401: +case 0x5601: +case 0x5801: +case 0x5A01: +case 0x5C01: +case 0x5E01: +case 0x5002: +case 0x5202: +case 0x5402: +case 0x5602: +case 0x5802: +case 0x5A02: +case 0x5C02: +case 0x5E02: +case 0x5003: +case 0x5203: +case 0x5403: +case 0x5603: +case 0x5803: +case 0x5A03: +case 0x5C03: +case 0x5E03: +case 0x5004: +case 0x5204: +case 0x5404: +case 0x5604: +case 0x5804: +case 0x5A04: +case 0x5C04: +case 0x5E04: +case 0x5005: +case 0x5205: +case 0x5405: +case 0x5605: +case 0x5805: +case 0x5A05: +case 0x5C05: +case 0x5E05: +case 0x5006: +case 0x5206: +case 0x5406: +case 0x5606: +case 0x5806: +case 0x5A06: +case 0x5C06: +case 0x5E06: +case 0x5007: +case 0x5207: +case 0x5407: +case 0x5607: +case 0x5807: +case 0x5A07: +case 0x5C07: +case 0x5E07: + +// ADDQ +case 0x5000: +{ + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + dst = (u8)CPU->D[(Opcode >> 0) & 7]; + res = dst + src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ res) & (dst ^ res); + CPU->flag_notZ = res & 0xFF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(4) +case 0x5210: +case 0x5410: +case 0x5610: +case 0x5810: +case 0x5A10: +case 0x5C10: +case 0x5E10: +case 0x5011: +case 0x5211: +case 0x5411: +case 0x5611: +case 0x5811: +case 0x5A11: +case 0x5C11: +case 0x5E11: +case 0x5012: +case 0x5212: +case 0x5412: +case 0x5612: +case 0x5812: +case 0x5A12: +case 0x5C12: +case 0x5E12: +case 0x5013: +case 0x5213: +case 0x5413: +case 0x5613: +case 0x5813: +case 0x5A13: +case 0x5C13: +case 0x5E13: +case 0x5014: +case 0x5214: +case 0x5414: +case 0x5614: +case 0x5814: +case 0x5A14: +case 0x5C14: +case 0x5E14: +case 0x5015: +case 0x5215: +case 0x5415: +case 0x5615: +case 0x5815: +case 0x5A15: +case 0x5C15: +case 0x5E15: +case 0x5016: +case 0x5216: +case 0x5416: +case 0x5616: +case 0x5816: +case 0x5A16: +case 0x5C16: +case 0x5E16: +case 0x5017: +case 0x5217: +case 0x5417: +case 0x5617: +case 0x5817: +case 0x5A17: +case 0x5C17: +case 0x5E17: + +// ADDQ +case 0x5010: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_BYTE_F(adr, dst) + res = dst + src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ res) & (dst ^ res); + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0x5218: +case 0x5418: +case 0x5618: +case 0x5818: +case 0x5A18: +case 0x5C18: +case 0x5E18: +case 0x5019: +case 0x5219: +case 0x5419: +case 0x5619: +case 0x5819: +case 0x5A19: +case 0x5C19: +case 0x5E19: +case 0x501A: +case 0x521A: +case 0x541A: +case 0x561A: +case 0x581A: +case 0x5A1A: +case 0x5C1A: +case 0x5E1A: +case 0x501B: +case 0x521B: +case 0x541B: +case 0x561B: +case 0x581B: +case 0x5A1B: +case 0x5C1B: +case 0x5E1B: +case 0x501C: +case 0x521C: +case 0x541C: +case 0x561C: +case 0x581C: +case 0x5A1C: +case 0x5C1C: +case 0x5E1C: +case 0x501D: +case 0x521D: +case 0x541D: +case 0x561D: +case 0x581D: +case 0x5A1D: +case 0x5C1D: +case 0x5E1D: +case 0x501E: +case 0x521E: +case 0x541E: +case 0x561E: +case 0x581E: +case 0x5A1E: +case 0x5C1E: +case 0x5E1E: + +// ADDQ +case 0x5018: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + PRE_IO + READ_BYTE_F(adr, dst) + res = dst + src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ res) & (dst ^ res); + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0x5220: +case 0x5420: +case 0x5620: +case 0x5820: +case 0x5A20: +case 0x5C20: +case 0x5E20: +case 0x5021: +case 0x5221: +case 0x5421: +case 0x5621: +case 0x5821: +case 0x5A21: +case 0x5C21: +case 0x5E21: +case 0x5022: +case 0x5222: +case 0x5422: +case 0x5622: +case 0x5822: +case 0x5A22: +case 0x5C22: +case 0x5E22: +case 0x5023: +case 0x5223: +case 0x5423: +case 0x5623: +case 0x5823: +case 0x5A23: +case 0x5C23: +case 0x5E23: +case 0x5024: +case 0x5224: +case 0x5424: +case 0x5624: +case 0x5824: +case 0x5A24: +case 0x5C24: +case 0x5E24: +case 0x5025: +case 0x5225: +case 0x5425: +case 0x5625: +case 0x5825: +case 0x5A25: +case 0x5C25: +case 0x5E25: +case 0x5026: +case 0x5226: +case 0x5426: +case 0x5626: +case 0x5826: +case 0x5A26: +case 0x5C26: +case 0x5E26: + +// ADDQ +case 0x5020: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_BYTE_F(adr, dst) + res = dst + src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ res) & (dst ^ res); + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(14) +case 0x5228: +case 0x5428: +case 0x5628: +case 0x5828: +case 0x5A28: +case 0x5C28: +case 0x5E28: +case 0x5029: +case 0x5229: +case 0x5429: +case 0x5629: +case 0x5829: +case 0x5A29: +case 0x5C29: +case 0x5E29: +case 0x502A: +case 0x522A: +case 0x542A: +case 0x562A: +case 0x582A: +case 0x5A2A: +case 0x5C2A: +case 0x5E2A: +case 0x502B: +case 0x522B: +case 0x542B: +case 0x562B: +case 0x582B: +case 0x5A2B: +case 0x5C2B: +case 0x5E2B: +case 0x502C: +case 0x522C: +case 0x542C: +case 0x562C: +case 0x582C: +case 0x5A2C: +case 0x5C2C: +case 0x5E2C: +case 0x502D: +case 0x522D: +case 0x542D: +case 0x562D: +case 0x582D: +case 0x5A2D: +case 0x5C2D: +case 0x5E2D: +case 0x502E: +case 0x522E: +case 0x542E: +case 0x562E: +case 0x582E: +case 0x5A2E: +case 0x5C2E: +case 0x5E2E: +case 0x502F: +case 0x522F: +case 0x542F: +case 0x562F: +case 0x582F: +case 0x5A2F: +case 0x5C2F: +case 0x5E2F: + +// ADDQ +case 0x5028: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, dst) + res = dst + src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ res) & (dst ^ res); + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0x5230: +case 0x5430: +case 0x5630: +case 0x5830: +case 0x5A30: +case 0x5C30: +case 0x5E30: +case 0x5031: +case 0x5231: +case 0x5431: +case 0x5631: +case 0x5831: +case 0x5A31: +case 0x5C31: +case 0x5E31: +case 0x5032: +case 0x5232: +case 0x5432: +case 0x5632: +case 0x5832: +case 0x5A32: +case 0x5C32: +case 0x5E32: +case 0x5033: +case 0x5233: +case 0x5433: +case 0x5633: +case 0x5833: +case 0x5A33: +case 0x5C33: +case 0x5E33: +case 0x5034: +case 0x5234: +case 0x5434: +case 0x5634: +case 0x5834: +case 0x5A34: +case 0x5C34: +case 0x5E34: +case 0x5035: +case 0x5235: +case 0x5435: +case 0x5635: +case 0x5835: +case 0x5A35: +case 0x5C35: +case 0x5E35: +case 0x5036: +case 0x5236: +case 0x5436: +case 0x5636: +case 0x5836: +case 0x5A36: +case 0x5C36: +case 0x5E36: +case 0x5037: +case 0x5237: +case 0x5437: +case 0x5637: +case 0x5837: +case 0x5A37: +case 0x5C37: +case 0x5E37: + +// ADDQ +case 0x5030: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, dst) + res = dst + src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ res) & (dst ^ res); + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) +case 0x5238: +case 0x5438: +case 0x5638: +case 0x5838: +case 0x5A38: +case 0x5C38: +case 0x5E38: + +// ADDQ +case 0x5038: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, dst) + res = dst + src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ res) & (dst ^ res); + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0x5239: +case 0x5439: +case 0x5639: +case 0x5839: +case 0x5A39: +case 0x5C39: +case 0x5E39: + +// ADDQ +case 0x5039: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_BYTE_F(adr, dst) + res = dst + src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ res) & (dst ^ res); + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(20) +case 0x521F: +case 0x541F: +case 0x561F: +case 0x581F: +case 0x5A1F: +case 0x5C1F: +case 0x5E1F: + +// ADDQ +case 0x501F: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_BYTE_F(adr, dst) + res = dst + src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ res) & (dst ^ res); + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0x5227: +case 0x5427: +case 0x5627: +case 0x5827: +case 0x5A27: +case 0x5C27: +case 0x5E27: + +// ADDQ +case 0x5027: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_BYTE_F(adr, dst) + res = dst + src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ res) & (dst ^ res); + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(14) +case 0x5240: +case 0x5440: +case 0x5640: +case 0x5840: +case 0x5A40: +case 0x5C40: +case 0x5E40: +case 0x5041: +case 0x5241: +case 0x5441: +case 0x5641: +case 0x5841: +case 0x5A41: +case 0x5C41: +case 0x5E41: +case 0x5042: +case 0x5242: +case 0x5442: +case 0x5642: +case 0x5842: +case 0x5A42: +case 0x5C42: +case 0x5E42: +case 0x5043: +case 0x5243: +case 0x5443: +case 0x5643: +case 0x5843: +case 0x5A43: +case 0x5C43: +case 0x5E43: +case 0x5044: +case 0x5244: +case 0x5444: +case 0x5644: +case 0x5844: +case 0x5A44: +case 0x5C44: +case 0x5E44: +case 0x5045: +case 0x5245: +case 0x5445: +case 0x5645: +case 0x5845: +case 0x5A45: +case 0x5C45: +case 0x5E45: +case 0x5046: +case 0x5246: +case 0x5446: +case 0x5646: +case 0x5846: +case 0x5A46: +case 0x5C46: +case 0x5E46: +case 0x5047: +case 0x5247: +case 0x5447: +case 0x5647: +case 0x5847: +case 0x5A47: +case 0x5C47: +case 0x5E47: + +// ADDQ +case 0x5040: +{ + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + dst = (u16)CPU->D[(Opcode >> 0) & 7]; + res = dst + src; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(4) +case 0x5248: +case 0x5448: +case 0x5648: +case 0x5848: +case 0x5A48: +case 0x5C48: +case 0x5E48: +case 0x5049: +case 0x5249: +case 0x5449: +case 0x5649: +case 0x5849: +case 0x5A49: +case 0x5C49: +case 0x5E49: +case 0x504A: +case 0x524A: +case 0x544A: +case 0x564A: +case 0x584A: +case 0x5A4A: +case 0x5C4A: +case 0x5E4A: +case 0x504B: +case 0x524B: +case 0x544B: +case 0x564B: +case 0x584B: +case 0x5A4B: +case 0x5C4B: +case 0x5E4B: +case 0x504C: +case 0x524C: +case 0x544C: +case 0x564C: +case 0x584C: +case 0x5A4C: +case 0x5C4C: +case 0x5E4C: +case 0x504D: +case 0x524D: +case 0x544D: +case 0x564D: +case 0x584D: +case 0x5A4D: +case 0x5C4D: +case 0x5E4D: +case 0x504E: +case 0x524E: +case 0x544E: +case 0x564E: +case 0x584E: +case 0x5A4E: +case 0x5C4E: +case 0x5E4E: +case 0x504F: +case 0x524F: +case 0x544F: +case 0x564F: +case 0x584F: +case 0x5A4F: +case 0x5C4F: +case 0x5E4F: + +// ADDQ +case 0x5048: +{ + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + dst = (u32)CPU->A[(Opcode >> 0) & 7]; + res = dst + src; + CPU->A[(Opcode >> 0) & 7] = res; +} +RET(8) +case 0x5250: +case 0x5450: +case 0x5650: +case 0x5850: +case 0x5A50: +case 0x5C50: +case 0x5E50: +case 0x5051: +case 0x5251: +case 0x5451: +case 0x5651: +case 0x5851: +case 0x5A51: +case 0x5C51: +case 0x5E51: +case 0x5052: +case 0x5252: +case 0x5452: +case 0x5652: +case 0x5852: +case 0x5A52: +case 0x5C52: +case 0x5E52: +case 0x5053: +case 0x5253: +case 0x5453: +case 0x5653: +case 0x5853: +case 0x5A53: +case 0x5C53: +case 0x5E53: +case 0x5054: +case 0x5254: +case 0x5454: +case 0x5654: +case 0x5854: +case 0x5A54: +case 0x5C54: +case 0x5E54: +case 0x5055: +case 0x5255: +case 0x5455: +case 0x5655: +case 0x5855: +case 0x5A55: +case 0x5C55: +case 0x5E55: +case 0x5056: +case 0x5256: +case 0x5456: +case 0x5656: +case 0x5856: +case 0x5A56: +case 0x5C56: +case 0x5E56: +case 0x5057: +case 0x5257: +case 0x5457: +case 0x5657: +case 0x5857: +case 0x5A57: +case 0x5C57: +case 0x5E57: + +// ADDQ +case 0x5050: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_WORD_F(adr, dst) + res = dst + src; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0x5258: +case 0x5458: +case 0x5658: +case 0x5858: +case 0x5A58: +case 0x5C58: +case 0x5E58: +case 0x5059: +case 0x5259: +case 0x5459: +case 0x5659: +case 0x5859: +case 0x5A59: +case 0x5C59: +case 0x5E59: +case 0x505A: +case 0x525A: +case 0x545A: +case 0x565A: +case 0x585A: +case 0x5A5A: +case 0x5C5A: +case 0x5E5A: +case 0x505B: +case 0x525B: +case 0x545B: +case 0x565B: +case 0x585B: +case 0x5A5B: +case 0x5C5B: +case 0x5E5B: +case 0x505C: +case 0x525C: +case 0x545C: +case 0x565C: +case 0x585C: +case 0x5A5C: +case 0x5C5C: +case 0x5E5C: +case 0x505D: +case 0x525D: +case 0x545D: +case 0x565D: +case 0x585D: +case 0x5A5D: +case 0x5C5D: +case 0x5E5D: +case 0x505E: +case 0x525E: +case 0x545E: +case 0x565E: +case 0x585E: +case 0x5A5E: +case 0x5C5E: +case 0x5E5E: + +// ADDQ +case 0x5058: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 2; + PRE_IO + READ_WORD_F(adr, dst) + res = dst + src; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0x5260: +case 0x5460: +case 0x5660: +case 0x5860: +case 0x5A60: +case 0x5C60: +case 0x5E60: +case 0x5061: +case 0x5261: +case 0x5461: +case 0x5661: +case 0x5861: +case 0x5A61: +case 0x5C61: +case 0x5E61: +case 0x5062: +case 0x5262: +case 0x5462: +case 0x5662: +case 0x5862: +case 0x5A62: +case 0x5C62: +case 0x5E62: +case 0x5063: +case 0x5263: +case 0x5463: +case 0x5663: +case 0x5863: +case 0x5A63: +case 0x5C63: +case 0x5E63: +case 0x5064: +case 0x5264: +case 0x5464: +case 0x5664: +case 0x5864: +case 0x5A64: +case 0x5C64: +case 0x5E64: +case 0x5065: +case 0x5265: +case 0x5465: +case 0x5665: +case 0x5865: +case 0x5A65: +case 0x5C65: +case 0x5E65: +case 0x5066: +case 0x5266: +case 0x5466: +case 0x5666: +case 0x5866: +case 0x5A66: +case 0x5C66: +case 0x5E66: + +// ADDQ +case 0x5060: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = CPU->A[(Opcode >> 0) & 7] - 2; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_WORD_F(adr, dst) + res = dst + src; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(14) +case 0x5268: +case 0x5468: +case 0x5668: +case 0x5868: +case 0x5A68: +case 0x5C68: +case 0x5E68: +case 0x5069: +case 0x5269: +case 0x5469: +case 0x5669: +case 0x5869: +case 0x5A69: +case 0x5C69: +case 0x5E69: +case 0x506A: +case 0x526A: +case 0x546A: +case 0x566A: +case 0x586A: +case 0x5A6A: +case 0x5C6A: +case 0x5E6A: +case 0x506B: +case 0x526B: +case 0x546B: +case 0x566B: +case 0x586B: +case 0x5A6B: +case 0x5C6B: +case 0x5E6B: +case 0x506C: +case 0x526C: +case 0x546C: +case 0x566C: +case 0x586C: +case 0x5A6C: +case 0x5C6C: +case 0x5E6C: +case 0x506D: +case 0x526D: +case 0x546D: +case 0x566D: +case 0x586D: +case 0x5A6D: +case 0x5C6D: +case 0x5E6D: +case 0x506E: +case 0x526E: +case 0x546E: +case 0x566E: +case 0x586E: +case 0x5A6E: +case 0x5C6E: +case 0x5E6E: +case 0x506F: +case 0x526F: +case 0x546F: +case 0x566F: +case 0x586F: +case 0x5A6F: +case 0x5C6F: +case 0x5E6F: + +// ADDQ +case 0x5068: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, dst) + res = dst + src; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0x5270: +case 0x5470: +case 0x5670: +case 0x5870: +case 0x5A70: +case 0x5C70: +case 0x5E70: +case 0x5071: +case 0x5271: +case 0x5471: +case 0x5671: +case 0x5871: +case 0x5A71: +case 0x5C71: +case 0x5E71: +case 0x5072: +case 0x5272: +case 0x5472: +case 0x5672: +case 0x5872: +case 0x5A72: +case 0x5C72: +case 0x5E72: +case 0x5073: +case 0x5273: +case 0x5473: +case 0x5673: +case 0x5873: +case 0x5A73: +case 0x5C73: +case 0x5E73: +case 0x5074: +case 0x5274: +case 0x5474: +case 0x5674: +case 0x5874: +case 0x5A74: +case 0x5C74: +case 0x5E74: +case 0x5075: +case 0x5275: +case 0x5475: +case 0x5675: +case 0x5875: +case 0x5A75: +case 0x5C75: +case 0x5E75: +case 0x5076: +case 0x5276: +case 0x5476: +case 0x5676: +case 0x5876: +case 0x5A76: +case 0x5C76: +case 0x5E76: +case 0x5077: +case 0x5277: +case 0x5477: +case 0x5677: +case 0x5877: +case 0x5A77: +case 0x5C77: +case 0x5E77: + +// ADDQ +case 0x5070: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, dst) + res = dst + src; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(18) +case 0x5278: +case 0x5478: +case 0x5678: +case 0x5878: +case 0x5A78: +case 0x5C78: +case 0x5E78: + +// ADDQ +case 0x5078: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, dst) + res = dst + src; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0x5279: +case 0x5479: +case 0x5679: +case 0x5879: +case 0x5A79: +case 0x5C79: +case 0x5E79: + +// ADDQ +case 0x5079: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_WORD_F(adr, dst) + res = dst + src; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(20) +case 0x525F: +case 0x545F: +case 0x565F: +case 0x585F: +case 0x5A5F: +case 0x5C5F: +case 0x5E5F: + +// ADDQ +case 0x505F: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_WORD_F(adr, dst) + res = dst + src; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0x5267: +case 0x5467: +case 0x5667: +case 0x5867: +case 0x5A67: +case 0x5C67: +case 0x5E67: + +// ADDQ +case 0x5067: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_WORD_F(adr, dst) + res = dst + src; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(14) +case 0x5280: +case 0x5480: +case 0x5680: +case 0x5880: +case 0x5A80: +case 0x5C80: +case 0x5E80: +case 0x5081: +case 0x5281: +case 0x5481: +case 0x5681: +case 0x5881: +case 0x5A81: +case 0x5C81: +case 0x5E81: +case 0x5082: +case 0x5282: +case 0x5482: +case 0x5682: +case 0x5882: +case 0x5A82: +case 0x5C82: +case 0x5E82: +case 0x5083: +case 0x5283: +case 0x5483: +case 0x5683: +case 0x5883: +case 0x5A83: +case 0x5C83: +case 0x5E83: +case 0x5084: +case 0x5284: +case 0x5484: +case 0x5684: +case 0x5884: +case 0x5A84: +case 0x5C84: +case 0x5E84: +case 0x5085: +case 0x5285: +case 0x5485: +case 0x5685: +case 0x5885: +case 0x5A85: +case 0x5C85: +case 0x5E85: +case 0x5086: +case 0x5286: +case 0x5486: +case 0x5686: +case 0x5886: +case 0x5A86: +case 0x5C86: +case 0x5E86: +case 0x5087: +case 0x5287: +case 0x5487: +case 0x5687: +case 0x5887: +case 0x5A87: +case 0x5C87: +case 0x5E87: + +// ADDQ +case 0x5080: +{ + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + dst = (u32)CPU->D[(Opcode >> 0) & 7]; + res = dst + src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 24; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(8) +case 0x5288: +case 0x5488: +case 0x5688: +case 0x5888: +case 0x5A88: +case 0x5C88: +case 0x5E88: +case 0x5089: +case 0x5289: +case 0x5489: +case 0x5689: +case 0x5889: +case 0x5A89: +case 0x5C89: +case 0x5E89: +case 0x508A: +case 0x528A: +case 0x548A: +case 0x568A: +case 0x588A: +case 0x5A8A: +case 0x5C8A: +case 0x5E8A: +case 0x508B: +case 0x528B: +case 0x548B: +case 0x568B: +case 0x588B: +case 0x5A8B: +case 0x5C8B: +case 0x5E8B: +case 0x508C: +case 0x528C: +case 0x548C: +case 0x568C: +case 0x588C: +case 0x5A8C: +case 0x5C8C: +case 0x5E8C: +case 0x508D: +case 0x528D: +case 0x548D: +case 0x568D: +case 0x588D: +case 0x5A8D: +case 0x5C8D: +case 0x5E8D: +case 0x508E: +case 0x528E: +case 0x548E: +case 0x568E: +case 0x588E: +case 0x5A8E: +case 0x5C8E: +case 0x5E8E: +case 0x508F: +case 0x528F: +case 0x548F: +case 0x568F: +case 0x588F: +case 0x5A8F: +case 0x5C8F: +case 0x5E8F: + +// ADDQ +case 0x5088: +{ + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + dst = (u32)CPU->A[(Opcode >> 0) & 7]; + res = dst + src; + CPU->A[(Opcode >> 0) & 7] = res; +} +RET(8) +case 0x5290: +case 0x5490: +case 0x5690: +case 0x5890: +case 0x5A90: +case 0x5C90: +case 0x5E90: +case 0x5091: +case 0x5291: +case 0x5491: +case 0x5691: +case 0x5891: +case 0x5A91: +case 0x5C91: +case 0x5E91: +case 0x5092: +case 0x5292: +case 0x5492: +case 0x5692: +case 0x5892: +case 0x5A92: +case 0x5C92: +case 0x5E92: +case 0x5093: +case 0x5293: +case 0x5493: +case 0x5693: +case 0x5893: +case 0x5A93: +case 0x5C93: +case 0x5E93: +case 0x5094: +case 0x5294: +case 0x5494: +case 0x5694: +case 0x5894: +case 0x5A94: +case 0x5C94: +case 0x5E94: +case 0x5095: +case 0x5295: +case 0x5495: +case 0x5695: +case 0x5895: +case 0x5A95: +case 0x5C95: +case 0x5E95: +case 0x5096: +case 0x5296: +case 0x5496: +case 0x5696: +case 0x5896: +case 0x5A96: +case 0x5C96: +case 0x5E96: +case 0x5097: +case 0x5297: +case 0x5497: +case 0x5697: +case 0x5897: +case 0x5A97: +case 0x5C97: +case 0x5E97: + +// ADDQ +case 0x5090: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_LONG_F(adr, dst) + res = dst + src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(20) +case 0x5298: +case 0x5498: +case 0x5698: +case 0x5898: +case 0x5A98: +case 0x5C98: +case 0x5E98: +case 0x5099: +case 0x5299: +case 0x5499: +case 0x5699: +case 0x5899: +case 0x5A99: +case 0x5C99: +case 0x5E99: +case 0x509A: +case 0x529A: +case 0x549A: +case 0x569A: +case 0x589A: +case 0x5A9A: +case 0x5C9A: +case 0x5E9A: +case 0x509B: +case 0x529B: +case 0x549B: +case 0x569B: +case 0x589B: +case 0x5A9B: +case 0x5C9B: +case 0x5E9B: +case 0x509C: +case 0x529C: +case 0x549C: +case 0x569C: +case 0x589C: +case 0x5A9C: +case 0x5C9C: +case 0x5E9C: +case 0x509D: +case 0x529D: +case 0x549D: +case 0x569D: +case 0x589D: +case 0x5A9D: +case 0x5C9D: +case 0x5E9D: +case 0x509E: +case 0x529E: +case 0x549E: +case 0x569E: +case 0x589E: +case 0x5A9E: +case 0x5C9E: +case 0x5E9E: + +// ADDQ +case 0x5098: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 4; + PRE_IO + READ_LONG_F(adr, dst) + res = dst + src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(20) +case 0x52A0: +case 0x54A0: +case 0x56A0: +case 0x58A0: +case 0x5AA0: +case 0x5CA0: +case 0x5EA0: +case 0x50A1: +case 0x52A1: +case 0x54A1: +case 0x56A1: +case 0x58A1: +case 0x5AA1: +case 0x5CA1: +case 0x5EA1: +case 0x50A2: +case 0x52A2: +case 0x54A2: +case 0x56A2: +case 0x58A2: +case 0x5AA2: +case 0x5CA2: +case 0x5EA2: +case 0x50A3: +case 0x52A3: +case 0x54A3: +case 0x56A3: +case 0x58A3: +case 0x5AA3: +case 0x5CA3: +case 0x5EA3: +case 0x50A4: +case 0x52A4: +case 0x54A4: +case 0x56A4: +case 0x58A4: +case 0x5AA4: +case 0x5CA4: +case 0x5EA4: +case 0x50A5: +case 0x52A5: +case 0x54A5: +case 0x56A5: +case 0x58A5: +case 0x5AA5: +case 0x5CA5: +case 0x5EA5: +case 0x50A6: +case 0x52A6: +case 0x54A6: +case 0x56A6: +case 0x58A6: +case 0x5AA6: +case 0x5CA6: +case 0x5EA6: + +// ADDQ +case 0x50A0: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = CPU->A[(Opcode >> 0) & 7] - 4; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_LONG_F(adr, dst) + res = dst + src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(22) +case 0x52A8: +case 0x54A8: +case 0x56A8: +case 0x58A8: +case 0x5AA8: +case 0x5CA8: +case 0x5EA8: +case 0x50A9: +case 0x52A9: +case 0x54A9: +case 0x56A9: +case 0x58A9: +case 0x5AA9: +case 0x5CA9: +case 0x5EA9: +case 0x50AA: +case 0x52AA: +case 0x54AA: +case 0x56AA: +case 0x58AA: +case 0x5AAA: +case 0x5CAA: +case 0x5EAA: +case 0x50AB: +case 0x52AB: +case 0x54AB: +case 0x56AB: +case 0x58AB: +case 0x5AAB: +case 0x5CAB: +case 0x5EAB: +case 0x50AC: +case 0x52AC: +case 0x54AC: +case 0x56AC: +case 0x58AC: +case 0x5AAC: +case 0x5CAC: +case 0x5EAC: +case 0x50AD: +case 0x52AD: +case 0x54AD: +case 0x56AD: +case 0x58AD: +case 0x5AAD: +case 0x5CAD: +case 0x5EAD: +case 0x50AE: +case 0x52AE: +case 0x54AE: +case 0x56AE: +case 0x58AE: +case 0x5AAE: +case 0x5CAE: +case 0x5EAE: +case 0x50AF: +case 0x52AF: +case 0x54AF: +case 0x56AF: +case 0x58AF: +case 0x5AAF: +case 0x5CAF: +case 0x5EAF: + +// ADDQ +case 0x50A8: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, dst) + res = dst + src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(24) +case 0x52B0: +case 0x54B0: +case 0x56B0: +case 0x58B0: +case 0x5AB0: +case 0x5CB0: +case 0x5EB0: +case 0x50B1: +case 0x52B1: +case 0x54B1: +case 0x56B1: +case 0x58B1: +case 0x5AB1: +case 0x5CB1: +case 0x5EB1: +case 0x50B2: +case 0x52B2: +case 0x54B2: +case 0x56B2: +case 0x58B2: +case 0x5AB2: +case 0x5CB2: +case 0x5EB2: +case 0x50B3: +case 0x52B3: +case 0x54B3: +case 0x56B3: +case 0x58B3: +case 0x5AB3: +case 0x5CB3: +case 0x5EB3: +case 0x50B4: +case 0x52B4: +case 0x54B4: +case 0x56B4: +case 0x58B4: +case 0x5AB4: +case 0x5CB4: +case 0x5EB4: +case 0x50B5: +case 0x52B5: +case 0x54B5: +case 0x56B5: +case 0x58B5: +case 0x5AB5: +case 0x5CB5: +case 0x5EB5: +case 0x50B6: +case 0x52B6: +case 0x54B6: +case 0x56B6: +case 0x58B6: +case 0x5AB6: +case 0x5CB6: +case 0x5EB6: +case 0x50B7: +case 0x52B7: +case 0x54B7: +case 0x56B7: +case 0x58B7: +case 0x5AB7: +case 0x5CB7: +case 0x5EB7: + +// ADDQ +case 0x50B0: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_LONG_F(adr, dst) + res = dst + src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(26) +case 0x52B8: +case 0x54B8: +case 0x56B8: +case 0x58B8: +case 0x5AB8: +case 0x5CB8: +case 0x5EB8: + +// ADDQ +case 0x50B8: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, dst) + res = dst + src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(24) +case 0x52B9: +case 0x54B9: +case 0x56B9: +case 0x58B9: +case 0x5AB9: +case 0x5CB9: +case 0x5EB9: + +// ADDQ +case 0x50B9: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_LONG_F(adr, dst) + res = dst + src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(28) +case 0x529F: +case 0x549F: +case 0x569F: +case 0x589F: +case 0x5A9F: +case 0x5C9F: +case 0x5E9F: + +// ADDQ +case 0x509F: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = CPU->A[7]; + CPU->A[7] += 4; + PRE_IO + READ_LONG_F(adr, dst) + res = dst + src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(20) +case 0x52A7: +case 0x54A7: +case 0x56A7: +case 0x58A7: +case 0x5AA7: +case 0x5CA7: +case 0x5EA7: + +// ADDQ +case 0x50A7: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + PRE_IO + READ_LONG_F(adr, dst) + res = dst + src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(22) +case 0x5300: +case 0x5500: +case 0x5700: +case 0x5900: +case 0x5B00: +case 0x5D00: +case 0x5F00: +case 0x5101: +case 0x5301: +case 0x5501: +case 0x5701: +case 0x5901: +case 0x5B01: +case 0x5D01: +case 0x5F01: +case 0x5102: +case 0x5302: +case 0x5502: +case 0x5702: +case 0x5902: +case 0x5B02: +case 0x5D02: +case 0x5F02: +case 0x5103: +case 0x5303: +case 0x5503: +case 0x5703: +case 0x5903: +case 0x5B03: +case 0x5D03: +case 0x5F03: +case 0x5104: +case 0x5304: +case 0x5504: +case 0x5704: +case 0x5904: +case 0x5B04: +case 0x5D04: +case 0x5F04: +case 0x5105: +case 0x5305: +case 0x5505: +case 0x5705: +case 0x5905: +case 0x5B05: +case 0x5D05: +case 0x5F05: +case 0x5106: +case 0x5306: +case 0x5506: +case 0x5706: +case 0x5906: +case 0x5B06: +case 0x5D06: +case 0x5F06: +case 0x5107: +case 0x5307: +case 0x5507: +case 0x5707: +case 0x5907: +case 0x5B07: +case 0x5D07: +case 0x5F07: + +// SUBQ +case 0x5100: +{ + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + dst = (u8)CPU->D[(Opcode >> 0) & 7]; + res = dst - src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(4) +case 0x5310: +case 0x5510: +case 0x5710: +case 0x5910: +case 0x5B10: +case 0x5D10: +case 0x5F10: +case 0x5111: +case 0x5311: +case 0x5511: +case 0x5711: +case 0x5911: +case 0x5B11: +case 0x5D11: +case 0x5F11: +case 0x5112: +case 0x5312: +case 0x5512: +case 0x5712: +case 0x5912: +case 0x5B12: +case 0x5D12: +case 0x5F12: +case 0x5113: +case 0x5313: +case 0x5513: +case 0x5713: +case 0x5913: +case 0x5B13: +case 0x5D13: +case 0x5F13: +case 0x5114: +case 0x5314: +case 0x5514: +case 0x5714: +case 0x5914: +case 0x5B14: +case 0x5D14: +case 0x5F14: +case 0x5115: +case 0x5315: +case 0x5515: +case 0x5715: +case 0x5915: +case 0x5B15: +case 0x5D15: +case 0x5F15: +case 0x5116: +case 0x5316: +case 0x5516: +case 0x5716: +case 0x5916: +case 0x5B16: +case 0x5D16: +case 0x5F16: +case 0x5117: +case 0x5317: +case 0x5517: +case 0x5717: +case 0x5917: +case 0x5B17: +case 0x5D17: +case 0x5F17: + +// SUBQ +case 0x5110: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_BYTE_F(adr, dst) + res = dst - src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0x5318: +case 0x5518: +case 0x5718: +case 0x5918: +case 0x5B18: +case 0x5D18: +case 0x5F18: +case 0x5119: +case 0x5319: +case 0x5519: +case 0x5719: +case 0x5919: +case 0x5B19: +case 0x5D19: +case 0x5F19: +case 0x511A: +case 0x531A: +case 0x551A: +case 0x571A: +case 0x591A: +case 0x5B1A: +case 0x5D1A: +case 0x5F1A: +case 0x511B: +case 0x531B: +case 0x551B: +case 0x571B: +case 0x591B: +case 0x5B1B: +case 0x5D1B: +case 0x5F1B: +case 0x511C: +case 0x531C: +case 0x551C: +case 0x571C: +case 0x591C: +case 0x5B1C: +case 0x5D1C: +case 0x5F1C: +case 0x511D: +case 0x531D: +case 0x551D: +case 0x571D: +case 0x591D: +case 0x5B1D: +case 0x5D1D: +case 0x5F1D: +case 0x511E: +case 0x531E: +case 0x551E: +case 0x571E: +case 0x591E: +case 0x5B1E: +case 0x5D1E: +case 0x5F1E: + +// SUBQ +case 0x5118: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + PRE_IO + READ_BYTE_F(adr, dst) + res = dst - src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0x5320: +case 0x5520: +case 0x5720: +case 0x5920: +case 0x5B20: +case 0x5D20: +case 0x5F20: +case 0x5121: +case 0x5321: +case 0x5521: +case 0x5721: +case 0x5921: +case 0x5B21: +case 0x5D21: +case 0x5F21: +case 0x5122: +case 0x5322: +case 0x5522: +case 0x5722: +case 0x5922: +case 0x5B22: +case 0x5D22: +case 0x5F22: +case 0x5123: +case 0x5323: +case 0x5523: +case 0x5723: +case 0x5923: +case 0x5B23: +case 0x5D23: +case 0x5F23: +case 0x5124: +case 0x5324: +case 0x5524: +case 0x5724: +case 0x5924: +case 0x5B24: +case 0x5D24: +case 0x5F24: +case 0x5125: +case 0x5325: +case 0x5525: +case 0x5725: +case 0x5925: +case 0x5B25: +case 0x5D25: +case 0x5F25: +case 0x5126: +case 0x5326: +case 0x5526: +case 0x5726: +case 0x5926: +case 0x5B26: +case 0x5D26: +case 0x5F26: + +// SUBQ +case 0x5120: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_BYTE_F(adr, dst) + res = dst - src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(14) +case 0x5328: +case 0x5528: +case 0x5728: +case 0x5928: +case 0x5B28: +case 0x5D28: +case 0x5F28: +case 0x5129: +case 0x5329: +case 0x5529: +case 0x5729: +case 0x5929: +case 0x5B29: +case 0x5D29: +case 0x5F29: +case 0x512A: +case 0x532A: +case 0x552A: +case 0x572A: +case 0x592A: +case 0x5B2A: +case 0x5D2A: +case 0x5F2A: +case 0x512B: +case 0x532B: +case 0x552B: +case 0x572B: +case 0x592B: +case 0x5B2B: +case 0x5D2B: +case 0x5F2B: +case 0x512C: +case 0x532C: +case 0x552C: +case 0x572C: +case 0x592C: +case 0x5B2C: +case 0x5D2C: +case 0x5F2C: +case 0x512D: +case 0x532D: +case 0x552D: +case 0x572D: +case 0x592D: +case 0x5B2D: +case 0x5D2D: +case 0x5F2D: +case 0x512E: +case 0x532E: +case 0x552E: +case 0x572E: +case 0x592E: +case 0x5B2E: +case 0x5D2E: +case 0x5F2E: +case 0x512F: +case 0x532F: +case 0x552F: +case 0x572F: +case 0x592F: +case 0x5B2F: +case 0x5D2F: +case 0x5F2F: + +// SUBQ +case 0x5128: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, dst) + res = dst - src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0x5330: +case 0x5530: +case 0x5730: +case 0x5930: +case 0x5B30: +case 0x5D30: +case 0x5F30: +case 0x5131: +case 0x5331: +case 0x5531: +case 0x5731: +case 0x5931: +case 0x5B31: +case 0x5D31: +case 0x5F31: +case 0x5132: +case 0x5332: +case 0x5532: +case 0x5732: +case 0x5932: +case 0x5B32: +case 0x5D32: +case 0x5F32: +case 0x5133: +case 0x5333: +case 0x5533: +case 0x5733: +case 0x5933: +case 0x5B33: +case 0x5D33: +case 0x5F33: +case 0x5134: +case 0x5334: +case 0x5534: +case 0x5734: +case 0x5934: +case 0x5B34: +case 0x5D34: +case 0x5F34: +case 0x5135: +case 0x5335: +case 0x5535: +case 0x5735: +case 0x5935: +case 0x5B35: +case 0x5D35: +case 0x5F35: +case 0x5136: +case 0x5336: +case 0x5536: +case 0x5736: +case 0x5936: +case 0x5B36: +case 0x5D36: +case 0x5F36: +case 0x5137: +case 0x5337: +case 0x5537: +case 0x5737: +case 0x5937: +case 0x5B37: +case 0x5D37: +case 0x5F37: + +// SUBQ +case 0x5130: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, dst) + res = dst - src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) +case 0x5338: +case 0x5538: +case 0x5738: +case 0x5938: +case 0x5B38: +case 0x5D38: +case 0x5F38: + +// SUBQ +case 0x5138: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, dst) + res = dst - src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0x5339: +case 0x5539: +case 0x5739: +case 0x5939: +case 0x5B39: +case 0x5D39: +case 0x5F39: + +// SUBQ +case 0x5139: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_BYTE_F(adr, dst) + res = dst - src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(20) +case 0x531F: +case 0x551F: +case 0x571F: +case 0x591F: +case 0x5B1F: +case 0x5D1F: +case 0x5F1F: + +// SUBQ +case 0x511F: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_BYTE_F(adr, dst) + res = dst - src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0x5327: +case 0x5527: +case 0x5727: +case 0x5927: +case 0x5B27: +case 0x5D27: +case 0x5F27: + +// SUBQ +case 0x5127: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_BYTE_F(adr, dst) + res = dst - src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(14) +case 0x5340: +case 0x5540: +case 0x5740: +case 0x5940: +case 0x5B40: +case 0x5D40: +case 0x5F40: +case 0x5141: +case 0x5341: +case 0x5541: +case 0x5741: +case 0x5941: +case 0x5B41: +case 0x5D41: +case 0x5F41: +case 0x5142: +case 0x5342: +case 0x5542: +case 0x5742: +case 0x5942: +case 0x5B42: +case 0x5D42: +case 0x5F42: +case 0x5143: +case 0x5343: +case 0x5543: +case 0x5743: +case 0x5943: +case 0x5B43: +case 0x5D43: +case 0x5F43: +case 0x5144: +case 0x5344: +case 0x5544: +case 0x5744: +case 0x5944: +case 0x5B44: +case 0x5D44: +case 0x5F44: +case 0x5145: +case 0x5345: +case 0x5545: +case 0x5745: +case 0x5945: +case 0x5B45: +case 0x5D45: +case 0x5F45: +case 0x5146: +case 0x5346: +case 0x5546: +case 0x5746: +case 0x5946: +case 0x5B46: +case 0x5D46: +case 0x5F46: +case 0x5147: +case 0x5347: +case 0x5547: +case 0x5747: +case 0x5947: +case 0x5B47: +case 0x5D47: +case 0x5F47: + +// SUBQ +case 0x5140: +{ + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + dst = (u16)CPU->D[(Opcode >> 0) & 7]; + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(4) +case 0x5348: +case 0x5548: +case 0x5748: +case 0x5948: +case 0x5B48: +case 0x5D48: +case 0x5F48: +case 0x5149: +case 0x5349: +case 0x5549: +case 0x5749: +case 0x5949: +case 0x5B49: +case 0x5D49: +case 0x5F49: +case 0x514A: +case 0x534A: +case 0x554A: +case 0x574A: +case 0x594A: +case 0x5B4A: +case 0x5D4A: +case 0x5F4A: +case 0x514B: +case 0x534B: +case 0x554B: +case 0x574B: +case 0x594B: +case 0x5B4B: +case 0x5D4B: +case 0x5F4B: +case 0x514C: +case 0x534C: +case 0x554C: +case 0x574C: +case 0x594C: +case 0x5B4C: +case 0x5D4C: +case 0x5F4C: +case 0x514D: +case 0x534D: +case 0x554D: +case 0x574D: +case 0x594D: +case 0x5B4D: +case 0x5D4D: +case 0x5F4D: +case 0x514E: +case 0x534E: +case 0x554E: +case 0x574E: +case 0x594E: +case 0x5B4E: +case 0x5D4E: +case 0x5F4E: +case 0x514F: +case 0x534F: +case 0x554F: +case 0x574F: +case 0x594F: +case 0x5B4F: +case 0x5D4F: +case 0x5F4F: + +// SUBQ +case 0x5148: +{ + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + dst = (u32)CPU->A[(Opcode >> 0) & 7]; + res = dst - src; + CPU->A[(Opcode >> 0) & 7] = res; +} +RET(8) +case 0x5350: +case 0x5550: +case 0x5750: +case 0x5950: +case 0x5B50: +case 0x5D50: +case 0x5F50: +case 0x5151: +case 0x5351: +case 0x5551: +case 0x5751: +case 0x5951: +case 0x5B51: +case 0x5D51: +case 0x5F51: +case 0x5152: +case 0x5352: +case 0x5552: +case 0x5752: +case 0x5952: +case 0x5B52: +case 0x5D52: +case 0x5F52: +case 0x5153: +case 0x5353: +case 0x5553: +case 0x5753: +case 0x5953: +case 0x5B53: +case 0x5D53: +case 0x5F53: +case 0x5154: +case 0x5354: +case 0x5554: +case 0x5754: +case 0x5954: +case 0x5B54: +case 0x5D54: +case 0x5F54: +case 0x5155: +case 0x5355: +case 0x5555: +case 0x5755: +case 0x5955: +case 0x5B55: +case 0x5D55: +case 0x5F55: +case 0x5156: +case 0x5356: +case 0x5556: +case 0x5756: +case 0x5956: +case 0x5B56: +case 0x5D56: +case 0x5F56: +case 0x5157: +case 0x5357: +case 0x5557: +case 0x5757: +case 0x5957: +case 0x5B57: +case 0x5D57: +case 0x5F57: + +// SUBQ +case 0x5150: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_WORD_F(adr, dst) + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0x5358: +case 0x5558: +case 0x5758: +case 0x5958: +case 0x5B58: +case 0x5D58: +case 0x5F58: +case 0x5159: +case 0x5359: +case 0x5559: +case 0x5759: +case 0x5959: +case 0x5B59: +case 0x5D59: +case 0x5F59: +case 0x515A: +case 0x535A: +case 0x555A: +case 0x575A: +case 0x595A: +case 0x5B5A: +case 0x5D5A: +case 0x5F5A: +case 0x515B: +case 0x535B: +case 0x555B: +case 0x575B: +case 0x595B: +case 0x5B5B: +case 0x5D5B: +case 0x5F5B: +case 0x515C: +case 0x535C: +case 0x555C: +case 0x575C: +case 0x595C: +case 0x5B5C: +case 0x5D5C: +case 0x5F5C: +case 0x515D: +case 0x535D: +case 0x555D: +case 0x575D: +case 0x595D: +case 0x5B5D: +case 0x5D5D: +case 0x5F5D: +case 0x515E: +case 0x535E: +case 0x555E: +case 0x575E: +case 0x595E: +case 0x5B5E: +case 0x5D5E: +case 0x5F5E: + +// SUBQ +case 0x5158: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 2; + PRE_IO + READ_WORD_F(adr, dst) + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0x5360: +case 0x5560: +case 0x5760: +case 0x5960: +case 0x5B60: +case 0x5D60: +case 0x5F60: +case 0x5161: +case 0x5361: +case 0x5561: +case 0x5761: +case 0x5961: +case 0x5B61: +case 0x5D61: +case 0x5F61: +case 0x5162: +case 0x5362: +case 0x5562: +case 0x5762: +case 0x5962: +case 0x5B62: +case 0x5D62: +case 0x5F62: +case 0x5163: +case 0x5363: +case 0x5563: +case 0x5763: +case 0x5963: +case 0x5B63: +case 0x5D63: +case 0x5F63: +case 0x5164: +case 0x5364: +case 0x5564: +case 0x5764: +case 0x5964: +case 0x5B64: +case 0x5D64: +case 0x5F64: +case 0x5165: +case 0x5365: +case 0x5565: +case 0x5765: +case 0x5965: +case 0x5B65: +case 0x5D65: +case 0x5F65: +case 0x5166: +case 0x5366: +case 0x5566: +case 0x5766: +case 0x5966: +case 0x5B66: +case 0x5D66: +case 0x5F66: + +// SUBQ +case 0x5160: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = CPU->A[(Opcode >> 0) & 7] - 2; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_WORD_F(adr, dst) + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(14) +case 0x5368: +case 0x5568: +case 0x5768: +case 0x5968: +case 0x5B68: +case 0x5D68: +case 0x5F68: +case 0x5169: +case 0x5369: +case 0x5569: +case 0x5769: +case 0x5969: +case 0x5B69: +case 0x5D69: +case 0x5F69: +case 0x516A: +case 0x536A: +case 0x556A: +case 0x576A: +case 0x596A: +case 0x5B6A: +case 0x5D6A: +case 0x5F6A: +case 0x516B: +case 0x536B: +case 0x556B: +case 0x576B: +case 0x596B: +case 0x5B6B: +case 0x5D6B: +case 0x5F6B: +case 0x516C: +case 0x536C: +case 0x556C: +case 0x576C: +case 0x596C: +case 0x5B6C: +case 0x5D6C: +case 0x5F6C: +case 0x516D: +case 0x536D: +case 0x556D: +case 0x576D: +case 0x596D: +case 0x5B6D: +case 0x5D6D: +case 0x5F6D: +case 0x516E: +case 0x536E: +case 0x556E: +case 0x576E: +case 0x596E: +case 0x5B6E: +case 0x5D6E: +case 0x5F6E: +case 0x516F: +case 0x536F: +case 0x556F: +case 0x576F: +case 0x596F: +case 0x5B6F: +case 0x5D6F: +case 0x5F6F: + +// SUBQ +case 0x5168: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, dst) + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0x5370: +case 0x5570: +case 0x5770: +case 0x5970: +case 0x5B70: +case 0x5D70: +case 0x5F70: +case 0x5171: +case 0x5371: +case 0x5571: +case 0x5771: +case 0x5971: +case 0x5B71: +case 0x5D71: +case 0x5F71: +case 0x5172: +case 0x5372: +case 0x5572: +case 0x5772: +case 0x5972: +case 0x5B72: +case 0x5D72: +case 0x5F72: +case 0x5173: +case 0x5373: +case 0x5573: +case 0x5773: +case 0x5973: +case 0x5B73: +case 0x5D73: +case 0x5F73: +case 0x5174: +case 0x5374: +case 0x5574: +case 0x5774: +case 0x5974: +case 0x5B74: +case 0x5D74: +case 0x5F74: +case 0x5175: +case 0x5375: +case 0x5575: +case 0x5775: +case 0x5975: +case 0x5B75: +case 0x5D75: +case 0x5F75: +case 0x5176: +case 0x5376: +case 0x5576: +case 0x5776: +case 0x5976: +case 0x5B76: +case 0x5D76: +case 0x5F76: +case 0x5177: +case 0x5377: +case 0x5577: +case 0x5777: +case 0x5977: +case 0x5B77: +case 0x5D77: +case 0x5F77: + +// SUBQ +case 0x5170: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, dst) + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(18) +case 0x5378: +case 0x5578: +case 0x5778: +case 0x5978: +case 0x5B78: +case 0x5D78: +case 0x5F78: + +// SUBQ +case 0x5178: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, dst) + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0x5379: +case 0x5579: +case 0x5779: +case 0x5979: +case 0x5B79: +case 0x5D79: +case 0x5F79: + +// SUBQ +case 0x5179: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_WORD_F(adr, dst) + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(20) +case 0x535F: +case 0x555F: +case 0x575F: +case 0x595F: +case 0x5B5F: +case 0x5D5F: +case 0x5F5F: + +// SUBQ +case 0x515F: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_WORD_F(adr, dst) + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0x5367: +case 0x5567: +case 0x5767: +case 0x5967: +case 0x5B67: +case 0x5D67: +case 0x5F67: + +// SUBQ +case 0x5167: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_WORD_F(adr, dst) + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(14) +case 0x5380: +case 0x5580: +case 0x5780: +case 0x5980: +case 0x5B80: +case 0x5D80: +case 0x5F80: +case 0x5181: +case 0x5381: +case 0x5581: +case 0x5781: +case 0x5981: +case 0x5B81: +case 0x5D81: +case 0x5F81: +case 0x5182: +case 0x5382: +case 0x5582: +case 0x5782: +case 0x5982: +case 0x5B82: +case 0x5D82: +case 0x5F82: +case 0x5183: +case 0x5383: +case 0x5583: +case 0x5783: +case 0x5983: +case 0x5B83: +case 0x5D83: +case 0x5F83: +case 0x5184: +case 0x5384: +case 0x5584: +case 0x5784: +case 0x5984: +case 0x5B84: +case 0x5D84: +case 0x5F84: +case 0x5185: +case 0x5385: +case 0x5585: +case 0x5785: +case 0x5985: +case 0x5B85: +case 0x5D85: +case 0x5F85: +case 0x5186: +case 0x5386: +case 0x5586: +case 0x5786: +case 0x5986: +case 0x5B86: +case 0x5D86: +case 0x5F86: +case 0x5187: +case 0x5387: +case 0x5587: +case 0x5787: +case 0x5987: +case 0x5B87: +case 0x5D87: +case 0x5F87: + +// SUBQ +case 0x5180: +{ + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + dst = (u32)CPU->D[(Opcode >> 0) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(8) +case 0x5388: +case 0x5588: +case 0x5788: +case 0x5988: +case 0x5B88: +case 0x5D88: +case 0x5F88: +case 0x5189: +case 0x5389: +case 0x5589: +case 0x5789: +case 0x5989: +case 0x5B89: +case 0x5D89: +case 0x5F89: +case 0x518A: +case 0x538A: +case 0x558A: +case 0x578A: +case 0x598A: +case 0x5B8A: +case 0x5D8A: +case 0x5F8A: +case 0x518B: +case 0x538B: +case 0x558B: +case 0x578B: +case 0x598B: +case 0x5B8B: +case 0x5D8B: +case 0x5F8B: +case 0x518C: +case 0x538C: +case 0x558C: +case 0x578C: +case 0x598C: +case 0x5B8C: +case 0x5D8C: +case 0x5F8C: +case 0x518D: +case 0x538D: +case 0x558D: +case 0x578D: +case 0x598D: +case 0x5B8D: +case 0x5D8D: +case 0x5F8D: +case 0x518E: +case 0x538E: +case 0x558E: +case 0x578E: +case 0x598E: +case 0x5B8E: +case 0x5D8E: +case 0x5F8E: +case 0x518F: +case 0x538F: +case 0x558F: +case 0x578F: +case 0x598F: +case 0x5B8F: +case 0x5D8F: +case 0x5F8F: + +// SUBQ +case 0x5188: +{ + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + dst = (u32)CPU->A[(Opcode >> 0) & 7]; + res = dst - src; + CPU->A[(Opcode >> 0) & 7] = res; +} +RET(8) +case 0x5390: +case 0x5590: +case 0x5790: +case 0x5990: +case 0x5B90: +case 0x5D90: +case 0x5F90: +case 0x5191: +case 0x5391: +case 0x5591: +case 0x5791: +case 0x5991: +case 0x5B91: +case 0x5D91: +case 0x5F91: +case 0x5192: +case 0x5392: +case 0x5592: +case 0x5792: +case 0x5992: +case 0x5B92: +case 0x5D92: +case 0x5F92: +case 0x5193: +case 0x5393: +case 0x5593: +case 0x5793: +case 0x5993: +case 0x5B93: +case 0x5D93: +case 0x5F93: +case 0x5194: +case 0x5394: +case 0x5594: +case 0x5794: +case 0x5994: +case 0x5B94: +case 0x5D94: +case 0x5F94: +case 0x5195: +case 0x5395: +case 0x5595: +case 0x5795: +case 0x5995: +case 0x5B95: +case 0x5D95: +case 0x5F95: +case 0x5196: +case 0x5396: +case 0x5596: +case 0x5796: +case 0x5996: +case 0x5B96: +case 0x5D96: +case 0x5F96: +case 0x5197: +case 0x5397: +case 0x5597: +case 0x5797: +case 0x5997: +case 0x5B97: +case 0x5D97: +case 0x5F97: + +// SUBQ +case 0x5190: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_LONG_F(adr, dst) + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(20) +case 0x5398: +case 0x5598: +case 0x5798: +case 0x5998: +case 0x5B98: +case 0x5D98: +case 0x5F98: +case 0x5199: +case 0x5399: +case 0x5599: +case 0x5799: +case 0x5999: +case 0x5B99: +case 0x5D99: +case 0x5F99: +case 0x519A: +case 0x539A: +case 0x559A: +case 0x579A: +case 0x599A: +case 0x5B9A: +case 0x5D9A: +case 0x5F9A: +case 0x519B: +case 0x539B: +case 0x559B: +case 0x579B: +case 0x599B: +case 0x5B9B: +case 0x5D9B: +case 0x5F9B: +case 0x519C: +case 0x539C: +case 0x559C: +case 0x579C: +case 0x599C: +case 0x5B9C: +case 0x5D9C: +case 0x5F9C: +case 0x519D: +case 0x539D: +case 0x559D: +case 0x579D: +case 0x599D: +case 0x5B9D: +case 0x5D9D: +case 0x5F9D: +case 0x519E: +case 0x539E: +case 0x559E: +case 0x579E: +case 0x599E: +case 0x5B9E: +case 0x5D9E: +case 0x5F9E: + +// SUBQ +case 0x5198: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 4; + PRE_IO + READ_LONG_F(adr, dst) + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(20) +case 0x53A0: +case 0x55A0: +case 0x57A0: +case 0x59A0: +case 0x5BA0: +case 0x5DA0: +case 0x5FA0: +case 0x51A1: +case 0x53A1: +case 0x55A1: +case 0x57A1: +case 0x59A1: +case 0x5BA1: +case 0x5DA1: +case 0x5FA1: +case 0x51A2: +case 0x53A2: +case 0x55A2: +case 0x57A2: +case 0x59A2: +case 0x5BA2: +case 0x5DA2: +case 0x5FA2: +case 0x51A3: +case 0x53A3: +case 0x55A3: +case 0x57A3: +case 0x59A3: +case 0x5BA3: +case 0x5DA3: +case 0x5FA3: +case 0x51A4: +case 0x53A4: +case 0x55A4: +case 0x57A4: +case 0x59A4: +case 0x5BA4: +case 0x5DA4: +case 0x5FA4: +case 0x51A5: +case 0x53A5: +case 0x55A5: +case 0x57A5: +case 0x59A5: +case 0x5BA5: +case 0x5DA5: +case 0x5FA5: +case 0x51A6: +case 0x53A6: +case 0x55A6: +case 0x57A6: +case 0x59A6: +case 0x5BA6: +case 0x5DA6: +case 0x5FA6: + +// SUBQ +case 0x51A0: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = CPU->A[(Opcode >> 0) & 7] - 4; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_LONG_F(adr, dst) + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(22) +case 0x53A8: +case 0x55A8: +case 0x57A8: +case 0x59A8: +case 0x5BA8: +case 0x5DA8: +case 0x5FA8: +case 0x51A9: +case 0x53A9: +case 0x55A9: +case 0x57A9: +case 0x59A9: +case 0x5BA9: +case 0x5DA9: +case 0x5FA9: +case 0x51AA: +case 0x53AA: +case 0x55AA: +case 0x57AA: +case 0x59AA: +case 0x5BAA: +case 0x5DAA: +case 0x5FAA: +case 0x51AB: +case 0x53AB: +case 0x55AB: +case 0x57AB: +case 0x59AB: +case 0x5BAB: +case 0x5DAB: +case 0x5FAB: +case 0x51AC: +case 0x53AC: +case 0x55AC: +case 0x57AC: +case 0x59AC: +case 0x5BAC: +case 0x5DAC: +case 0x5FAC: +case 0x51AD: +case 0x53AD: +case 0x55AD: +case 0x57AD: +case 0x59AD: +case 0x5BAD: +case 0x5DAD: +case 0x5FAD: +case 0x51AE: +case 0x53AE: +case 0x55AE: +case 0x57AE: +case 0x59AE: +case 0x5BAE: +case 0x5DAE: +case 0x5FAE: +case 0x51AF: +case 0x53AF: +case 0x55AF: +case 0x57AF: +case 0x59AF: +case 0x5BAF: +case 0x5DAF: +case 0x5FAF: + +// SUBQ +case 0x51A8: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, dst) + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(24) +case 0x53B0: +case 0x55B0: +case 0x57B0: +case 0x59B0: +case 0x5BB0: +case 0x5DB0: +case 0x5FB0: +case 0x51B1: +case 0x53B1: +case 0x55B1: +case 0x57B1: +case 0x59B1: +case 0x5BB1: +case 0x5DB1: +case 0x5FB1: +case 0x51B2: +case 0x53B2: +case 0x55B2: +case 0x57B2: +case 0x59B2: +case 0x5BB2: +case 0x5DB2: +case 0x5FB2: +case 0x51B3: +case 0x53B3: +case 0x55B3: +case 0x57B3: +case 0x59B3: +case 0x5BB3: +case 0x5DB3: +case 0x5FB3: +case 0x51B4: +case 0x53B4: +case 0x55B4: +case 0x57B4: +case 0x59B4: +case 0x5BB4: +case 0x5DB4: +case 0x5FB4: +case 0x51B5: +case 0x53B5: +case 0x55B5: +case 0x57B5: +case 0x59B5: +case 0x5BB5: +case 0x5DB5: +case 0x5FB5: +case 0x51B6: +case 0x53B6: +case 0x55B6: +case 0x57B6: +case 0x59B6: +case 0x5BB6: +case 0x5DB6: +case 0x5FB6: +case 0x51B7: +case 0x53B7: +case 0x55B7: +case 0x57B7: +case 0x59B7: +case 0x5BB7: +case 0x5DB7: +case 0x5FB7: + +// SUBQ +case 0x51B0: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_LONG_F(adr, dst) + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(26) +case 0x53B8: +case 0x55B8: +case 0x57B8: +case 0x59B8: +case 0x5BB8: +case 0x5DB8: +case 0x5FB8: + +// SUBQ +case 0x51B8: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, dst) + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(24) +case 0x53B9: +case 0x55B9: +case 0x57B9: +case 0x59B9: +case 0x5BB9: +case 0x5DB9: +case 0x5FB9: + +// SUBQ +case 0x51B9: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_LONG_F(adr, dst) + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(28) +case 0x539F: +case 0x559F: +case 0x579F: +case 0x599F: +case 0x5B9F: +case 0x5D9F: +case 0x5F9F: + +// SUBQ +case 0x519F: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = CPU->A[7]; + CPU->A[7] += 4; + PRE_IO + READ_LONG_F(adr, dst) + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(20) +case 0x53A7: +case 0x55A7: +case 0x57A7: +case 0x59A7: +case 0x5BA7: +case 0x5DA7: +case 0x5FA7: + +// SUBQ +case 0x51A7: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (((Opcode >> 9) - 1) & 7) + 1; + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + PRE_IO + READ_LONG_F(adr, dst) + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(22) diff --git a/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68k_op6.inc b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68k_op6.inc new file mode 100644 index 000000000..244fd5db7 --- /dev/null +++ b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68k_op6.inc @@ -0,0 +1,4454 @@ +case 0x6202: +case 0x6203: +case 0x6204: +case 0x6205: +case 0x6206: +case 0x6207: +case 0x6208: +case 0x6209: +case 0x620A: +case 0x620B: +case 0x620C: +case 0x620D: +case 0x620E: +case 0x620F: +case 0x6210: +case 0x6211: +case 0x6212: +case 0x6213: +case 0x6214: +case 0x6215: +case 0x6216: +case 0x6217: +case 0x6218: +case 0x6219: +case 0x621A: +case 0x621B: +case 0x621C: +case 0x621D: +case 0x621E: +case 0x621F: +case 0x6220: +case 0x6221: +case 0x6222: +case 0x6223: +case 0x6224: +case 0x6225: +case 0x6226: +case 0x6227: +case 0x6228: +case 0x6229: +case 0x622A: +case 0x622B: +case 0x622C: +case 0x622D: +case 0x622E: +case 0x622F: +case 0x6230: +case 0x6231: +case 0x6232: +case 0x6233: +case 0x6234: +case 0x6235: +case 0x6236: +case 0x6237: +case 0x6238: +case 0x6239: +case 0x623A: +case 0x623B: +case 0x623C: +case 0x623D: +case 0x623E: +case 0x623F: +case 0x6240: +case 0x6241: +case 0x6242: +case 0x6243: +case 0x6244: +case 0x6245: +case 0x6246: +case 0x6247: +case 0x6248: +case 0x6249: +case 0x624A: +case 0x624B: +case 0x624C: +case 0x624D: +case 0x624E: +case 0x624F: +case 0x6250: +case 0x6251: +case 0x6252: +case 0x6253: +case 0x6254: +case 0x6255: +case 0x6256: +case 0x6257: +case 0x6258: +case 0x6259: +case 0x625A: +case 0x625B: +case 0x625C: +case 0x625D: +case 0x625E: +case 0x625F: +case 0x6260: +case 0x6261: +case 0x6262: +case 0x6263: +case 0x6264: +case 0x6265: +case 0x6266: +case 0x6267: +case 0x6268: +case 0x6269: +case 0x626A: +case 0x626B: +case 0x626C: +case 0x626D: +case 0x626E: +case 0x626F: +case 0x6270: +case 0x6271: +case 0x6272: +case 0x6273: +case 0x6274: +case 0x6275: +case 0x6276: +case 0x6277: +case 0x6278: +case 0x6279: +case 0x627A: +case 0x627B: +case 0x627C: +case 0x627D: +case 0x627E: +case 0x627F: +case 0x6280: +case 0x6281: +case 0x6282: +case 0x6283: +case 0x6284: +case 0x6285: +case 0x6286: +case 0x6287: +case 0x6288: +case 0x6289: +case 0x628A: +case 0x628B: +case 0x628C: +case 0x628D: +case 0x628E: +case 0x628F: +case 0x6290: +case 0x6291: +case 0x6292: +case 0x6293: +case 0x6294: +case 0x6295: +case 0x6296: +case 0x6297: +case 0x6298: +case 0x6299: +case 0x629A: +case 0x629B: +case 0x629C: +case 0x629D: +case 0x629E: +case 0x629F: +case 0x62A0: +case 0x62A1: +case 0x62A2: +case 0x62A3: +case 0x62A4: +case 0x62A5: +case 0x62A6: +case 0x62A7: +case 0x62A8: +case 0x62A9: +case 0x62AA: +case 0x62AB: +case 0x62AC: +case 0x62AD: +case 0x62AE: +case 0x62AF: +case 0x62B0: +case 0x62B1: +case 0x62B2: +case 0x62B3: +case 0x62B4: +case 0x62B5: +case 0x62B6: +case 0x62B7: +case 0x62B8: +case 0x62B9: +case 0x62BA: +case 0x62BB: +case 0x62BC: +case 0x62BD: +case 0x62BE: +case 0x62BF: +case 0x62C0: +case 0x62C1: +case 0x62C2: +case 0x62C3: +case 0x62C4: +case 0x62C5: +case 0x62C6: +case 0x62C7: +case 0x62C8: +case 0x62C9: +case 0x62CA: +case 0x62CB: +case 0x62CC: +case 0x62CD: +case 0x62CE: +case 0x62CF: +case 0x62D0: +case 0x62D1: +case 0x62D2: +case 0x62D3: +case 0x62D4: +case 0x62D5: +case 0x62D6: +case 0x62D7: +case 0x62D8: +case 0x62D9: +case 0x62DA: +case 0x62DB: +case 0x62DC: +case 0x62DD: +case 0x62DE: +case 0x62DF: +case 0x62E0: +case 0x62E1: +case 0x62E2: +case 0x62E3: +case 0x62E4: +case 0x62E5: +case 0x62E6: +case 0x62E7: +case 0x62E8: +case 0x62E9: +case 0x62EA: +case 0x62EB: +case 0x62EC: +case 0x62ED: +case 0x62EE: +case 0x62EF: +case 0x62F0: +case 0x62F1: +case 0x62F2: +case 0x62F3: +case 0x62F4: +case 0x62F5: +case 0x62F6: +case 0x62F7: +case 0x62F8: +case 0x62F9: +case 0x62FA: +case 0x62FB: +case 0x62FC: +case 0x62FD: +case 0x62FE: +case 0x62FF: + +// BCC +case 0x6201: +{ + if (CPU->flag_notZ && (!(CPU->flag_C & 0x100))) + { + PC += (s32)(s8)Opcode; + CCnt -= 2; + } +} +RET(8) +case 0x6302: +case 0x6303: +case 0x6304: +case 0x6305: +case 0x6306: +case 0x6307: +case 0x6308: +case 0x6309: +case 0x630A: +case 0x630B: +case 0x630C: +case 0x630D: +case 0x630E: +case 0x630F: +case 0x6310: +case 0x6311: +case 0x6312: +case 0x6313: +case 0x6314: +case 0x6315: +case 0x6316: +case 0x6317: +case 0x6318: +case 0x6319: +case 0x631A: +case 0x631B: +case 0x631C: +case 0x631D: +case 0x631E: +case 0x631F: +case 0x6320: +case 0x6321: +case 0x6322: +case 0x6323: +case 0x6324: +case 0x6325: +case 0x6326: +case 0x6327: +case 0x6328: +case 0x6329: +case 0x632A: +case 0x632B: +case 0x632C: +case 0x632D: +case 0x632E: +case 0x632F: +case 0x6330: +case 0x6331: +case 0x6332: +case 0x6333: +case 0x6334: +case 0x6335: +case 0x6336: +case 0x6337: +case 0x6338: +case 0x6339: +case 0x633A: +case 0x633B: +case 0x633C: +case 0x633D: +case 0x633E: +case 0x633F: +case 0x6340: +case 0x6341: +case 0x6342: +case 0x6343: +case 0x6344: +case 0x6345: +case 0x6346: +case 0x6347: +case 0x6348: +case 0x6349: +case 0x634A: +case 0x634B: +case 0x634C: +case 0x634D: +case 0x634E: +case 0x634F: +case 0x6350: +case 0x6351: +case 0x6352: +case 0x6353: +case 0x6354: +case 0x6355: +case 0x6356: +case 0x6357: +case 0x6358: +case 0x6359: +case 0x635A: +case 0x635B: +case 0x635C: +case 0x635D: +case 0x635E: +case 0x635F: +case 0x6360: +case 0x6361: +case 0x6362: +case 0x6363: +case 0x6364: +case 0x6365: +case 0x6366: +case 0x6367: +case 0x6368: +case 0x6369: +case 0x636A: +case 0x636B: +case 0x636C: +case 0x636D: +case 0x636E: +case 0x636F: +case 0x6370: +case 0x6371: +case 0x6372: +case 0x6373: +case 0x6374: +case 0x6375: +case 0x6376: +case 0x6377: +case 0x6378: +case 0x6379: +case 0x637A: +case 0x637B: +case 0x637C: +case 0x637D: +case 0x637E: +case 0x637F: +case 0x6380: +case 0x6381: +case 0x6382: +case 0x6383: +case 0x6384: +case 0x6385: +case 0x6386: +case 0x6387: +case 0x6388: +case 0x6389: +case 0x638A: +case 0x638B: +case 0x638C: +case 0x638D: +case 0x638E: +case 0x638F: +case 0x6390: +case 0x6391: +case 0x6392: +case 0x6393: +case 0x6394: +case 0x6395: +case 0x6396: +case 0x6397: +case 0x6398: +case 0x6399: +case 0x639A: +case 0x639B: +case 0x639C: +case 0x639D: +case 0x639E: +case 0x639F: +case 0x63A0: +case 0x63A1: +case 0x63A2: +case 0x63A3: +case 0x63A4: +case 0x63A5: +case 0x63A6: +case 0x63A7: +case 0x63A8: +case 0x63A9: +case 0x63AA: +case 0x63AB: +case 0x63AC: +case 0x63AD: +case 0x63AE: +case 0x63AF: +case 0x63B0: +case 0x63B1: +case 0x63B2: +case 0x63B3: +case 0x63B4: +case 0x63B5: +case 0x63B6: +case 0x63B7: +case 0x63B8: +case 0x63B9: +case 0x63BA: +case 0x63BB: +case 0x63BC: +case 0x63BD: +case 0x63BE: +case 0x63BF: +case 0x63C0: +case 0x63C1: +case 0x63C2: +case 0x63C3: +case 0x63C4: +case 0x63C5: +case 0x63C6: +case 0x63C7: +case 0x63C8: +case 0x63C9: +case 0x63CA: +case 0x63CB: +case 0x63CC: +case 0x63CD: +case 0x63CE: +case 0x63CF: +case 0x63D0: +case 0x63D1: +case 0x63D2: +case 0x63D3: +case 0x63D4: +case 0x63D5: +case 0x63D6: +case 0x63D7: +case 0x63D8: +case 0x63D9: +case 0x63DA: +case 0x63DB: +case 0x63DC: +case 0x63DD: +case 0x63DE: +case 0x63DF: +case 0x63E0: +case 0x63E1: +case 0x63E2: +case 0x63E3: +case 0x63E4: +case 0x63E5: +case 0x63E6: +case 0x63E7: +case 0x63E8: +case 0x63E9: +case 0x63EA: +case 0x63EB: +case 0x63EC: +case 0x63ED: +case 0x63EE: +case 0x63EF: +case 0x63F0: +case 0x63F1: +case 0x63F2: +case 0x63F3: +case 0x63F4: +case 0x63F5: +case 0x63F6: +case 0x63F7: +case 0x63F8: +case 0x63F9: +case 0x63FA: +case 0x63FB: +case 0x63FC: +case 0x63FD: +case 0x63FE: +case 0x63FF: + +// BCC +case 0x6301: +{ + if ((!CPU->flag_notZ) || (CPU->flag_C & 0x100)) + { + PC += (s32)(s8)Opcode; + CCnt -= 2; + } +} +RET(8) +case 0x6402: +case 0x6403: +case 0x6404: +case 0x6405: +case 0x6406: +case 0x6407: +case 0x6408: +case 0x6409: +case 0x640A: +case 0x640B: +case 0x640C: +case 0x640D: +case 0x640E: +case 0x640F: +case 0x6410: +case 0x6411: +case 0x6412: +case 0x6413: +case 0x6414: +case 0x6415: +case 0x6416: +case 0x6417: +case 0x6418: +case 0x6419: +case 0x641A: +case 0x641B: +case 0x641C: +case 0x641D: +case 0x641E: +case 0x641F: +case 0x6420: +case 0x6421: +case 0x6422: +case 0x6423: +case 0x6424: +case 0x6425: +case 0x6426: +case 0x6427: +case 0x6428: +case 0x6429: +case 0x642A: +case 0x642B: +case 0x642C: +case 0x642D: +case 0x642E: +case 0x642F: +case 0x6430: +case 0x6431: +case 0x6432: +case 0x6433: +case 0x6434: +case 0x6435: +case 0x6436: +case 0x6437: +case 0x6438: +case 0x6439: +case 0x643A: +case 0x643B: +case 0x643C: +case 0x643D: +case 0x643E: +case 0x643F: +case 0x6440: +case 0x6441: +case 0x6442: +case 0x6443: +case 0x6444: +case 0x6445: +case 0x6446: +case 0x6447: +case 0x6448: +case 0x6449: +case 0x644A: +case 0x644B: +case 0x644C: +case 0x644D: +case 0x644E: +case 0x644F: +case 0x6450: +case 0x6451: +case 0x6452: +case 0x6453: +case 0x6454: +case 0x6455: +case 0x6456: +case 0x6457: +case 0x6458: +case 0x6459: +case 0x645A: +case 0x645B: +case 0x645C: +case 0x645D: +case 0x645E: +case 0x645F: +case 0x6460: +case 0x6461: +case 0x6462: +case 0x6463: +case 0x6464: +case 0x6465: +case 0x6466: +case 0x6467: +case 0x6468: +case 0x6469: +case 0x646A: +case 0x646B: +case 0x646C: +case 0x646D: +case 0x646E: +case 0x646F: +case 0x6470: +case 0x6471: +case 0x6472: +case 0x6473: +case 0x6474: +case 0x6475: +case 0x6476: +case 0x6477: +case 0x6478: +case 0x6479: +case 0x647A: +case 0x647B: +case 0x647C: +case 0x647D: +case 0x647E: +case 0x647F: +case 0x6480: +case 0x6481: +case 0x6482: +case 0x6483: +case 0x6484: +case 0x6485: +case 0x6486: +case 0x6487: +case 0x6488: +case 0x6489: +case 0x648A: +case 0x648B: +case 0x648C: +case 0x648D: +case 0x648E: +case 0x648F: +case 0x6490: +case 0x6491: +case 0x6492: +case 0x6493: +case 0x6494: +case 0x6495: +case 0x6496: +case 0x6497: +case 0x6498: +case 0x6499: +case 0x649A: +case 0x649B: +case 0x649C: +case 0x649D: +case 0x649E: +case 0x649F: +case 0x64A0: +case 0x64A1: +case 0x64A2: +case 0x64A3: +case 0x64A4: +case 0x64A5: +case 0x64A6: +case 0x64A7: +case 0x64A8: +case 0x64A9: +case 0x64AA: +case 0x64AB: +case 0x64AC: +case 0x64AD: +case 0x64AE: +case 0x64AF: +case 0x64B0: +case 0x64B1: +case 0x64B2: +case 0x64B3: +case 0x64B4: +case 0x64B5: +case 0x64B6: +case 0x64B7: +case 0x64B8: +case 0x64B9: +case 0x64BA: +case 0x64BB: +case 0x64BC: +case 0x64BD: +case 0x64BE: +case 0x64BF: +case 0x64C0: +case 0x64C1: +case 0x64C2: +case 0x64C3: +case 0x64C4: +case 0x64C5: +case 0x64C6: +case 0x64C7: +case 0x64C8: +case 0x64C9: +case 0x64CA: +case 0x64CB: +case 0x64CC: +case 0x64CD: +case 0x64CE: +case 0x64CF: +case 0x64D0: +case 0x64D1: +case 0x64D2: +case 0x64D3: +case 0x64D4: +case 0x64D5: +case 0x64D6: +case 0x64D7: +case 0x64D8: +case 0x64D9: +case 0x64DA: +case 0x64DB: +case 0x64DC: +case 0x64DD: +case 0x64DE: +case 0x64DF: +case 0x64E0: +case 0x64E1: +case 0x64E2: +case 0x64E3: +case 0x64E4: +case 0x64E5: +case 0x64E6: +case 0x64E7: +case 0x64E8: +case 0x64E9: +case 0x64EA: +case 0x64EB: +case 0x64EC: +case 0x64ED: +case 0x64EE: +case 0x64EF: +case 0x64F0: +case 0x64F1: +case 0x64F2: +case 0x64F3: +case 0x64F4: +case 0x64F5: +case 0x64F6: +case 0x64F7: +case 0x64F8: +case 0x64F9: +case 0x64FA: +case 0x64FB: +case 0x64FC: +case 0x64FD: +case 0x64FE: +case 0x64FF: + +// BCC +case 0x6401: +{ + if (!(CPU->flag_C & 0x100)) + { + PC += (s32)(s8)Opcode; + CCnt -= 2; + } +} +RET(8) +case 0x6502: +case 0x6503: +case 0x6504: +case 0x6505: +case 0x6506: +case 0x6507: +case 0x6508: +case 0x6509: +case 0x650A: +case 0x650B: +case 0x650C: +case 0x650D: +case 0x650E: +case 0x650F: +case 0x6510: +case 0x6511: +case 0x6512: +case 0x6513: +case 0x6514: +case 0x6515: +case 0x6516: +case 0x6517: +case 0x6518: +case 0x6519: +case 0x651A: +case 0x651B: +case 0x651C: +case 0x651D: +case 0x651E: +case 0x651F: +case 0x6520: +case 0x6521: +case 0x6522: +case 0x6523: +case 0x6524: +case 0x6525: +case 0x6526: +case 0x6527: +case 0x6528: +case 0x6529: +case 0x652A: +case 0x652B: +case 0x652C: +case 0x652D: +case 0x652E: +case 0x652F: +case 0x6530: +case 0x6531: +case 0x6532: +case 0x6533: +case 0x6534: +case 0x6535: +case 0x6536: +case 0x6537: +case 0x6538: +case 0x6539: +case 0x653A: +case 0x653B: +case 0x653C: +case 0x653D: +case 0x653E: +case 0x653F: +case 0x6540: +case 0x6541: +case 0x6542: +case 0x6543: +case 0x6544: +case 0x6545: +case 0x6546: +case 0x6547: +case 0x6548: +case 0x6549: +case 0x654A: +case 0x654B: +case 0x654C: +case 0x654D: +case 0x654E: +case 0x654F: +case 0x6550: +case 0x6551: +case 0x6552: +case 0x6553: +case 0x6554: +case 0x6555: +case 0x6556: +case 0x6557: +case 0x6558: +case 0x6559: +case 0x655A: +case 0x655B: +case 0x655C: +case 0x655D: +case 0x655E: +case 0x655F: +case 0x6560: +case 0x6561: +case 0x6562: +case 0x6563: +case 0x6564: +case 0x6565: +case 0x6566: +case 0x6567: +case 0x6568: +case 0x6569: +case 0x656A: +case 0x656B: +case 0x656C: +case 0x656D: +case 0x656E: +case 0x656F: +case 0x6570: +case 0x6571: +case 0x6572: +case 0x6573: +case 0x6574: +case 0x6575: +case 0x6576: +case 0x6577: +case 0x6578: +case 0x6579: +case 0x657A: +case 0x657B: +case 0x657C: +case 0x657D: +case 0x657E: +case 0x657F: +case 0x6580: +case 0x6581: +case 0x6582: +case 0x6583: +case 0x6584: +case 0x6585: +case 0x6586: +case 0x6587: +case 0x6588: +case 0x6589: +case 0x658A: +case 0x658B: +case 0x658C: +case 0x658D: +case 0x658E: +case 0x658F: +case 0x6590: +case 0x6591: +case 0x6592: +case 0x6593: +case 0x6594: +case 0x6595: +case 0x6596: +case 0x6597: +case 0x6598: +case 0x6599: +case 0x659A: +case 0x659B: +case 0x659C: +case 0x659D: +case 0x659E: +case 0x659F: +case 0x65A0: +case 0x65A1: +case 0x65A2: +case 0x65A3: +case 0x65A4: +case 0x65A5: +case 0x65A6: +case 0x65A7: +case 0x65A8: +case 0x65A9: +case 0x65AA: +case 0x65AB: +case 0x65AC: +case 0x65AD: +case 0x65AE: +case 0x65AF: +case 0x65B0: +case 0x65B1: +case 0x65B2: +case 0x65B3: +case 0x65B4: +case 0x65B5: +case 0x65B6: +case 0x65B7: +case 0x65B8: +case 0x65B9: +case 0x65BA: +case 0x65BB: +case 0x65BC: +case 0x65BD: +case 0x65BE: +case 0x65BF: +case 0x65C0: +case 0x65C1: +case 0x65C2: +case 0x65C3: +case 0x65C4: +case 0x65C5: +case 0x65C6: +case 0x65C7: +case 0x65C8: +case 0x65C9: +case 0x65CA: +case 0x65CB: +case 0x65CC: +case 0x65CD: +case 0x65CE: +case 0x65CF: +case 0x65D0: +case 0x65D1: +case 0x65D2: +case 0x65D3: +case 0x65D4: +case 0x65D5: +case 0x65D6: +case 0x65D7: +case 0x65D8: +case 0x65D9: +case 0x65DA: +case 0x65DB: +case 0x65DC: +case 0x65DD: +case 0x65DE: +case 0x65DF: +case 0x65E0: +case 0x65E1: +case 0x65E2: +case 0x65E3: +case 0x65E4: +case 0x65E5: +case 0x65E6: +case 0x65E7: +case 0x65E8: +case 0x65E9: +case 0x65EA: +case 0x65EB: +case 0x65EC: +case 0x65ED: +case 0x65EE: +case 0x65EF: +case 0x65F0: +case 0x65F1: +case 0x65F2: +case 0x65F3: +case 0x65F4: +case 0x65F5: +case 0x65F6: +case 0x65F7: +case 0x65F8: +case 0x65F9: +case 0x65FA: +case 0x65FB: +case 0x65FC: +case 0x65FD: +case 0x65FE: +case 0x65FF: + +// BCC +case 0x6501: +{ + if (CPU->flag_C & 0x100) + { + PC += (s32)(s8)Opcode; + CCnt -= 2; + } +} +RET(8) +case 0x6602: +case 0x6603: +case 0x6604: +case 0x6605: +case 0x6606: +case 0x6607: +case 0x6608: +case 0x6609: +case 0x660A: +case 0x660B: +case 0x660C: +case 0x660D: +case 0x660E: +case 0x660F: +case 0x6610: +case 0x6611: +case 0x6612: +case 0x6613: +case 0x6614: +case 0x6615: +case 0x6616: +case 0x6617: +case 0x6618: +case 0x6619: +case 0x661A: +case 0x661B: +case 0x661C: +case 0x661D: +case 0x661E: +case 0x661F: +case 0x6620: +case 0x6621: +case 0x6622: +case 0x6623: +case 0x6624: +case 0x6625: +case 0x6626: +case 0x6627: +case 0x6628: +case 0x6629: +case 0x662A: +case 0x662B: +case 0x662C: +case 0x662D: +case 0x662E: +case 0x662F: +case 0x6630: +case 0x6631: +case 0x6632: +case 0x6633: +case 0x6634: +case 0x6635: +case 0x6636: +case 0x6637: +case 0x6638: +case 0x6639: +case 0x663A: +case 0x663B: +case 0x663C: +case 0x663D: +case 0x663E: +case 0x663F: +case 0x6640: +case 0x6641: +case 0x6642: +case 0x6643: +case 0x6644: +case 0x6645: +case 0x6646: +case 0x6647: +case 0x6648: +case 0x6649: +case 0x664A: +case 0x664B: +case 0x664C: +case 0x664D: +case 0x664E: +case 0x664F: +case 0x6650: +case 0x6651: +case 0x6652: +case 0x6653: +case 0x6654: +case 0x6655: +case 0x6656: +case 0x6657: +case 0x6658: +case 0x6659: +case 0x665A: +case 0x665B: +case 0x665C: +case 0x665D: +case 0x665E: +case 0x665F: +case 0x6660: +case 0x6661: +case 0x6662: +case 0x6663: +case 0x6664: +case 0x6665: +case 0x6666: +case 0x6667: +case 0x6668: +case 0x6669: +case 0x666A: +case 0x666B: +case 0x666C: +case 0x666D: +case 0x666E: +case 0x666F: +case 0x6670: +case 0x6671: +case 0x6672: +case 0x6673: +case 0x6674: +case 0x6675: +case 0x6676: +case 0x6677: +case 0x6678: +case 0x6679: +case 0x667A: +case 0x667B: +case 0x667C: +case 0x667D: +case 0x667E: +case 0x667F: +case 0x6680: +case 0x6681: +case 0x6682: +case 0x6683: +case 0x6684: +case 0x6685: +case 0x6686: +case 0x6687: +case 0x6688: +case 0x6689: +case 0x668A: +case 0x668B: +case 0x668C: +case 0x668D: +case 0x668E: +case 0x668F: +case 0x6690: +case 0x6691: +case 0x6692: +case 0x6693: +case 0x6694: +case 0x6695: +case 0x6696: +case 0x6697: +case 0x6698: +case 0x6699: +case 0x669A: +case 0x669B: +case 0x669C: +case 0x669D: +case 0x669E: +case 0x669F: +case 0x66A0: +case 0x66A1: +case 0x66A2: +case 0x66A3: +case 0x66A4: +case 0x66A5: +case 0x66A6: +case 0x66A7: +case 0x66A8: +case 0x66A9: +case 0x66AA: +case 0x66AB: +case 0x66AC: +case 0x66AD: +case 0x66AE: +case 0x66AF: +case 0x66B0: +case 0x66B1: +case 0x66B2: +case 0x66B3: +case 0x66B4: +case 0x66B5: +case 0x66B6: +case 0x66B7: +case 0x66B8: +case 0x66B9: +case 0x66BA: +case 0x66BB: +case 0x66BC: +case 0x66BD: +case 0x66BE: +case 0x66BF: +case 0x66C0: +case 0x66C1: +case 0x66C2: +case 0x66C3: +case 0x66C4: +case 0x66C5: +case 0x66C6: +case 0x66C7: +case 0x66C8: +case 0x66C9: +case 0x66CA: +case 0x66CB: +case 0x66CC: +case 0x66CD: +case 0x66CE: +case 0x66CF: +case 0x66D0: +case 0x66D1: +case 0x66D2: +case 0x66D3: +case 0x66D4: +case 0x66D5: +case 0x66D6: +case 0x66D7: +case 0x66D8: +case 0x66D9: +case 0x66DA: +case 0x66DB: +case 0x66DC: +case 0x66DD: +case 0x66DE: +case 0x66DF: +case 0x66E0: +case 0x66E1: +case 0x66E2: +case 0x66E3: +case 0x66E4: +case 0x66E5: +case 0x66E6: +case 0x66E7: +case 0x66E8: +case 0x66E9: +case 0x66EA: +case 0x66EB: +case 0x66EC: +case 0x66ED: +case 0x66EE: +case 0x66EF: +case 0x66F0: +case 0x66F1: +case 0x66F2: +case 0x66F3: +case 0x66F4: +case 0x66F5: +case 0x66F6: +case 0x66F7: +case 0x66F8: +case 0x66F9: +case 0x66FA: +case 0x66FB: +case 0x66FC: +case 0x66FD: +case 0x66FE: +case 0x66FF: + +// BCC +case 0x6601: +{ + if (CPU->flag_notZ) + { + PC += (s32)(s8)Opcode; + CCnt -= 2; + } +} +RET(8) +case 0x6702: +case 0x6703: +case 0x6704: +case 0x6705: +case 0x6706: +case 0x6707: +case 0x6708: +case 0x6709: +case 0x670A: +case 0x670B: +case 0x670C: +case 0x670D: +case 0x670E: +case 0x670F: +case 0x6710: +case 0x6711: +case 0x6712: +case 0x6713: +case 0x6714: +case 0x6715: +case 0x6716: +case 0x6717: +case 0x6718: +case 0x6719: +case 0x671A: +case 0x671B: +case 0x671C: +case 0x671D: +case 0x671E: +case 0x671F: +case 0x6720: +case 0x6721: +case 0x6722: +case 0x6723: +case 0x6724: +case 0x6725: +case 0x6726: +case 0x6727: +case 0x6728: +case 0x6729: +case 0x672A: +case 0x672B: +case 0x672C: +case 0x672D: +case 0x672E: +case 0x672F: +case 0x6730: +case 0x6731: +case 0x6732: +case 0x6733: +case 0x6734: +case 0x6735: +case 0x6736: +case 0x6737: +case 0x6738: +case 0x6739: +case 0x673A: +case 0x673B: +case 0x673C: +case 0x673D: +case 0x673E: +case 0x673F: +case 0x6740: +case 0x6741: +case 0x6742: +case 0x6743: +case 0x6744: +case 0x6745: +case 0x6746: +case 0x6747: +case 0x6748: +case 0x6749: +case 0x674A: +case 0x674B: +case 0x674C: +case 0x674D: +case 0x674E: +case 0x674F: +case 0x6750: +case 0x6751: +case 0x6752: +case 0x6753: +case 0x6754: +case 0x6755: +case 0x6756: +case 0x6757: +case 0x6758: +case 0x6759: +case 0x675A: +case 0x675B: +case 0x675C: +case 0x675D: +case 0x675E: +case 0x675F: +case 0x6760: +case 0x6761: +case 0x6762: +case 0x6763: +case 0x6764: +case 0x6765: +case 0x6766: +case 0x6767: +case 0x6768: +case 0x6769: +case 0x676A: +case 0x676B: +case 0x676C: +case 0x676D: +case 0x676E: +case 0x676F: +case 0x6770: +case 0x6771: +case 0x6772: +case 0x6773: +case 0x6774: +case 0x6775: +case 0x6776: +case 0x6777: +case 0x6778: +case 0x6779: +case 0x677A: +case 0x677B: +case 0x677C: +case 0x677D: +case 0x677E: +case 0x677F: +case 0x6780: +case 0x6781: +case 0x6782: +case 0x6783: +case 0x6784: +case 0x6785: +case 0x6786: +case 0x6787: +case 0x6788: +case 0x6789: +case 0x678A: +case 0x678B: +case 0x678C: +case 0x678D: +case 0x678E: +case 0x678F: +case 0x6790: +case 0x6791: +case 0x6792: +case 0x6793: +case 0x6794: +case 0x6795: +case 0x6796: +case 0x6797: +case 0x6798: +case 0x6799: +case 0x679A: +case 0x679B: +case 0x679C: +case 0x679D: +case 0x679E: +case 0x679F: +case 0x67A0: +case 0x67A1: +case 0x67A2: +case 0x67A3: +case 0x67A4: +case 0x67A5: +case 0x67A6: +case 0x67A7: +case 0x67A8: +case 0x67A9: +case 0x67AA: +case 0x67AB: +case 0x67AC: +case 0x67AD: +case 0x67AE: +case 0x67AF: +case 0x67B0: +case 0x67B1: +case 0x67B2: +case 0x67B3: +case 0x67B4: +case 0x67B5: +case 0x67B6: +case 0x67B7: +case 0x67B8: +case 0x67B9: +case 0x67BA: +case 0x67BB: +case 0x67BC: +case 0x67BD: +case 0x67BE: +case 0x67BF: +case 0x67C0: +case 0x67C1: +case 0x67C2: +case 0x67C3: +case 0x67C4: +case 0x67C5: +case 0x67C6: +case 0x67C7: +case 0x67C8: +case 0x67C9: +case 0x67CA: +case 0x67CB: +case 0x67CC: +case 0x67CD: +case 0x67CE: +case 0x67CF: +case 0x67D0: +case 0x67D1: +case 0x67D2: +case 0x67D3: +case 0x67D4: +case 0x67D5: +case 0x67D6: +case 0x67D7: +case 0x67D8: +case 0x67D9: +case 0x67DA: +case 0x67DB: +case 0x67DC: +case 0x67DD: +case 0x67DE: +case 0x67DF: +case 0x67E0: +case 0x67E1: +case 0x67E2: +case 0x67E3: +case 0x67E4: +case 0x67E5: +case 0x67E6: +case 0x67E7: +case 0x67E8: +case 0x67E9: +case 0x67EA: +case 0x67EB: +case 0x67EC: +case 0x67ED: +case 0x67EE: +case 0x67EF: +case 0x67F0: +case 0x67F1: +case 0x67F2: +case 0x67F3: +case 0x67F4: +case 0x67F5: +case 0x67F6: +case 0x67F7: +case 0x67F8: +case 0x67F9: +case 0x67FA: +case 0x67FB: +case 0x67FC: +case 0x67FD: +case 0x67FE: +case 0x67FF: + +// BCC +case 0x6701: +{ + if (!CPU->flag_notZ) + { + PC += (s32)(s8)Opcode; + CCnt -= 2; + } +} +RET(8) +case 0x6802: +case 0x6803: +case 0x6804: +case 0x6805: +case 0x6806: +case 0x6807: +case 0x6808: +case 0x6809: +case 0x680A: +case 0x680B: +case 0x680C: +case 0x680D: +case 0x680E: +case 0x680F: +case 0x6810: +case 0x6811: +case 0x6812: +case 0x6813: +case 0x6814: +case 0x6815: +case 0x6816: +case 0x6817: +case 0x6818: +case 0x6819: +case 0x681A: +case 0x681B: +case 0x681C: +case 0x681D: +case 0x681E: +case 0x681F: +case 0x6820: +case 0x6821: +case 0x6822: +case 0x6823: +case 0x6824: +case 0x6825: +case 0x6826: +case 0x6827: +case 0x6828: +case 0x6829: +case 0x682A: +case 0x682B: +case 0x682C: +case 0x682D: +case 0x682E: +case 0x682F: +case 0x6830: +case 0x6831: +case 0x6832: +case 0x6833: +case 0x6834: +case 0x6835: +case 0x6836: +case 0x6837: +case 0x6838: +case 0x6839: +case 0x683A: +case 0x683B: +case 0x683C: +case 0x683D: +case 0x683E: +case 0x683F: +case 0x6840: +case 0x6841: +case 0x6842: +case 0x6843: +case 0x6844: +case 0x6845: +case 0x6846: +case 0x6847: +case 0x6848: +case 0x6849: +case 0x684A: +case 0x684B: +case 0x684C: +case 0x684D: +case 0x684E: +case 0x684F: +case 0x6850: +case 0x6851: +case 0x6852: +case 0x6853: +case 0x6854: +case 0x6855: +case 0x6856: +case 0x6857: +case 0x6858: +case 0x6859: +case 0x685A: +case 0x685B: +case 0x685C: +case 0x685D: +case 0x685E: +case 0x685F: +case 0x6860: +case 0x6861: +case 0x6862: +case 0x6863: +case 0x6864: +case 0x6865: +case 0x6866: +case 0x6867: +case 0x6868: +case 0x6869: +case 0x686A: +case 0x686B: +case 0x686C: +case 0x686D: +case 0x686E: +case 0x686F: +case 0x6870: +case 0x6871: +case 0x6872: +case 0x6873: +case 0x6874: +case 0x6875: +case 0x6876: +case 0x6877: +case 0x6878: +case 0x6879: +case 0x687A: +case 0x687B: +case 0x687C: +case 0x687D: +case 0x687E: +case 0x687F: +case 0x6880: +case 0x6881: +case 0x6882: +case 0x6883: +case 0x6884: +case 0x6885: +case 0x6886: +case 0x6887: +case 0x6888: +case 0x6889: +case 0x688A: +case 0x688B: +case 0x688C: +case 0x688D: +case 0x688E: +case 0x688F: +case 0x6890: +case 0x6891: +case 0x6892: +case 0x6893: +case 0x6894: +case 0x6895: +case 0x6896: +case 0x6897: +case 0x6898: +case 0x6899: +case 0x689A: +case 0x689B: +case 0x689C: +case 0x689D: +case 0x689E: +case 0x689F: +case 0x68A0: +case 0x68A1: +case 0x68A2: +case 0x68A3: +case 0x68A4: +case 0x68A5: +case 0x68A6: +case 0x68A7: +case 0x68A8: +case 0x68A9: +case 0x68AA: +case 0x68AB: +case 0x68AC: +case 0x68AD: +case 0x68AE: +case 0x68AF: +case 0x68B0: +case 0x68B1: +case 0x68B2: +case 0x68B3: +case 0x68B4: +case 0x68B5: +case 0x68B6: +case 0x68B7: +case 0x68B8: +case 0x68B9: +case 0x68BA: +case 0x68BB: +case 0x68BC: +case 0x68BD: +case 0x68BE: +case 0x68BF: +case 0x68C0: +case 0x68C1: +case 0x68C2: +case 0x68C3: +case 0x68C4: +case 0x68C5: +case 0x68C6: +case 0x68C7: +case 0x68C8: +case 0x68C9: +case 0x68CA: +case 0x68CB: +case 0x68CC: +case 0x68CD: +case 0x68CE: +case 0x68CF: +case 0x68D0: +case 0x68D1: +case 0x68D2: +case 0x68D3: +case 0x68D4: +case 0x68D5: +case 0x68D6: +case 0x68D7: +case 0x68D8: +case 0x68D9: +case 0x68DA: +case 0x68DB: +case 0x68DC: +case 0x68DD: +case 0x68DE: +case 0x68DF: +case 0x68E0: +case 0x68E1: +case 0x68E2: +case 0x68E3: +case 0x68E4: +case 0x68E5: +case 0x68E6: +case 0x68E7: +case 0x68E8: +case 0x68E9: +case 0x68EA: +case 0x68EB: +case 0x68EC: +case 0x68ED: +case 0x68EE: +case 0x68EF: +case 0x68F0: +case 0x68F1: +case 0x68F2: +case 0x68F3: +case 0x68F4: +case 0x68F5: +case 0x68F6: +case 0x68F7: +case 0x68F8: +case 0x68F9: +case 0x68FA: +case 0x68FB: +case 0x68FC: +case 0x68FD: +case 0x68FE: +case 0x68FF: + +// BCC +case 0x6801: +{ + if (!(CPU->flag_V & 0x80)) + { + PC += (s32)(s8)Opcode; + CCnt -= 2; + } +} +RET(8) +case 0x6902: +case 0x6903: +case 0x6904: +case 0x6905: +case 0x6906: +case 0x6907: +case 0x6908: +case 0x6909: +case 0x690A: +case 0x690B: +case 0x690C: +case 0x690D: +case 0x690E: +case 0x690F: +case 0x6910: +case 0x6911: +case 0x6912: +case 0x6913: +case 0x6914: +case 0x6915: +case 0x6916: +case 0x6917: +case 0x6918: +case 0x6919: +case 0x691A: +case 0x691B: +case 0x691C: +case 0x691D: +case 0x691E: +case 0x691F: +case 0x6920: +case 0x6921: +case 0x6922: +case 0x6923: +case 0x6924: +case 0x6925: +case 0x6926: +case 0x6927: +case 0x6928: +case 0x6929: +case 0x692A: +case 0x692B: +case 0x692C: +case 0x692D: +case 0x692E: +case 0x692F: +case 0x6930: +case 0x6931: +case 0x6932: +case 0x6933: +case 0x6934: +case 0x6935: +case 0x6936: +case 0x6937: +case 0x6938: +case 0x6939: +case 0x693A: +case 0x693B: +case 0x693C: +case 0x693D: +case 0x693E: +case 0x693F: +case 0x6940: +case 0x6941: +case 0x6942: +case 0x6943: +case 0x6944: +case 0x6945: +case 0x6946: +case 0x6947: +case 0x6948: +case 0x6949: +case 0x694A: +case 0x694B: +case 0x694C: +case 0x694D: +case 0x694E: +case 0x694F: +case 0x6950: +case 0x6951: +case 0x6952: +case 0x6953: +case 0x6954: +case 0x6955: +case 0x6956: +case 0x6957: +case 0x6958: +case 0x6959: +case 0x695A: +case 0x695B: +case 0x695C: +case 0x695D: +case 0x695E: +case 0x695F: +case 0x6960: +case 0x6961: +case 0x6962: +case 0x6963: +case 0x6964: +case 0x6965: +case 0x6966: +case 0x6967: +case 0x6968: +case 0x6969: +case 0x696A: +case 0x696B: +case 0x696C: +case 0x696D: +case 0x696E: +case 0x696F: +case 0x6970: +case 0x6971: +case 0x6972: +case 0x6973: +case 0x6974: +case 0x6975: +case 0x6976: +case 0x6977: +case 0x6978: +case 0x6979: +case 0x697A: +case 0x697B: +case 0x697C: +case 0x697D: +case 0x697E: +case 0x697F: +case 0x6980: +case 0x6981: +case 0x6982: +case 0x6983: +case 0x6984: +case 0x6985: +case 0x6986: +case 0x6987: +case 0x6988: +case 0x6989: +case 0x698A: +case 0x698B: +case 0x698C: +case 0x698D: +case 0x698E: +case 0x698F: +case 0x6990: +case 0x6991: +case 0x6992: +case 0x6993: +case 0x6994: +case 0x6995: +case 0x6996: +case 0x6997: +case 0x6998: +case 0x6999: +case 0x699A: +case 0x699B: +case 0x699C: +case 0x699D: +case 0x699E: +case 0x699F: +case 0x69A0: +case 0x69A1: +case 0x69A2: +case 0x69A3: +case 0x69A4: +case 0x69A5: +case 0x69A6: +case 0x69A7: +case 0x69A8: +case 0x69A9: +case 0x69AA: +case 0x69AB: +case 0x69AC: +case 0x69AD: +case 0x69AE: +case 0x69AF: +case 0x69B0: +case 0x69B1: +case 0x69B2: +case 0x69B3: +case 0x69B4: +case 0x69B5: +case 0x69B6: +case 0x69B7: +case 0x69B8: +case 0x69B9: +case 0x69BA: +case 0x69BB: +case 0x69BC: +case 0x69BD: +case 0x69BE: +case 0x69BF: +case 0x69C0: +case 0x69C1: +case 0x69C2: +case 0x69C3: +case 0x69C4: +case 0x69C5: +case 0x69C6: +case 0x69C7: +case 0x69C8: +case 0x69C9: +case 0x69CA: +case 0x69CB: +case 0x69CC: +case 0x69CD: +case 0x69CE: +case 0x69CF: +case 0x69D0: +case 0x69D1: +case 0x69D2: +case 0x69D3: +case 0x69D4: +case 0x69D5: +case 0x69D6: +case 0x69D7: +case 0x69D8: +case 0x69D9: +case 0x69DA: +case 0x69DB: +case 0x69DC: +case 0x69DD: +case 0x69DE: +case 0x69DF: +case 0x69E0: +case 0x69E1: +case 0x69E2: +case 0x69E3: +case 0x69E4: +case 0x69E5: +case 0x69E6: +case 0x69E7: +case 0x69E8: +case 0x69E9: +case 0x69EA: +case 0x69EB: +case 0x69EC: +case 0x69ED: +case 0x69EE: +case 0x69EF: +case 0x69F0: +case 0x69F1: +case 0x69F2: +case 0x69F3: +case 0x69F4: +case 0x69F5: +case 0x69F6: +case 0x69F7: +case 0x69F8: +case 0x69F9: +case 0x69FA: +case 0x69FB: +case 0x69FC: +case 0x69FD: +case 0x69FE: +case 0x69FF: + +// BCC +case 0x6901: +{ + if (CPU->flag_V & 0x80) + { + PC += (s32)(s8)Opcode; + CCnt -= 2; + } +} +RET(8) +case 0x6A02: +case 0x6A03: +case 0x6A04: +case 0x6A05: +case 0x6A06: +case 0x6A07: +case 0x6A08: +case 0x6A09: +case 0x6A0A: +case 0x6A0B: +case 0x6A0C: +case 0x6A0D: +case 0x6A0E: +case 0x6A0F: +case 0x6A10: +case 0x6A11: +case 0x6A12: +case 0x6A13: +case 0x6A14: +case 0x6A15: +case 0x6A16: +case 0x6A17: +case 0x6A18: +case 0x6A19: +case 0x6A1A: +case 0x6A1B: +case 0x6A1C: +case 0x6A1D: +case 0x6A1E: +case 0x6A1F: +case 0x6A20: +case 0x6A21: +case 0x6A22: +case 0x6A23: +case 0x6A24: +case 0x6A25: +case 0x6A26: +case 0x6A27: +case 0x6A28: +case 0x6A29: +case 0x6A2A: +case 0x6A2B: +case 0x6A2C: +case 0x6A2D: +case 0x6A2E: +case 0x6A2F: +case 0x6A30: +case 0x6A31: +case 0x6A32: +case 0x6A33: +case 0x6A34: +case 0x6A35: +case 0x6A36: +case 0x6A37: +case 0x6A38: +case 0x6A39: +case 0x6A3A: +case 0x6A3B: +case 0x6A3C: +case 0x6A3D: +case 0x6A3E: +case 0x6A3F: +case 0x6A40: +case 0x6A41: +case 0x6A42: +case 0x6A43: +case 0x6A44: +case 0x6A45: +case 0x6A46: +case 0x6A47: +case 0x6A48: +case 0x6A49: +case 0x6A4A: +case 0x6A4B: +case 0x6A4C: +case 0x6A4D: +case 0x6A4E: +case 0x6A4F: +case 0x6A50: +case 0x6A51: +case 0x6A52: +case 0x6A53: +case 0x6A54: +case 0x6A55: +case 0x6A56: +case 0x6A57: +case 0x6A58: +case 0x6A59: +case 0x6A5A: +case 0x6A5B: +case 0x6A5C: +case 0x6A5D: +case 0x6A5E: +case 0x6A5F: +case 0x6A60: +case 0x6A61: +case 0x6A62: +case 0x6A63: +case 0x6A64: +case 0x6A65: +case 0x6A66: +case 0x6A67: +case 0x6A68: +case 0x6A69: +case 0x6A6A: +case 0x6A6B: +case 0x6A6C: +case 0x6A6D: +case 0x6A6E: +case 0x6A6F: +case 0x6A70: +case 0x6A71: +case 0x6A72: +case 0x6A73: +case 0x6A74: +case 0x6A75: +case 0x6A76: +case 0x6A77: +case 0x6A78: +case 0x6A79: +case 0x6A7A: +case 0x6A7B: +case 0x6A7C: +case 0x6A7D: +case 0x6A7E: +case 0x6A7F: +case 0x6A80: +case 0x6A81: +case 0x6A82: +case 0x6A83: +case 0x6A84: +case 0x6A85: +case 0x6A86: +case 0x6A87: +case 0x6A88: +case 0x6A89: +case 0x6A8A: +case 0x6A8B: +case 0x6A8C: +case 0x6A8D: +case 0x6A8E: +case 0x6A8F: +case 0x6A90: +case 0x6A91: +case 0x6A92: +case 0x6A93: +case 0x6A94: +case 0x6A95: +case 0x6A96: +case 0x6A97: +case 0x6A98: +case 0x6A99: +case 0x6A9A: +case 0x6A9B: +case 0x6A9C: +case 0x6A9D: +case 0x6A9E: +case 0x6A9F: +case 0x6AA0: +case 0x6AA1: +case 0x6AA2: +case 0x6AA3: +case 0x6AA4: +case 0x6AA5: +case 0x6AA6: +case 0x6AA7: +case 0x6AA8: +case 0x6AA9: +case 0x6AAA: +case 0x6AAB: +case 0x6AAC: +case 0x6AAD: +case 0x6AAE: +case 0x6AAF: +case 0x6AB0: +case 0x6AB1: +case 0x6AB2: +case 0x6AB3: +case 0x6AB4: +case 0x6AB5: +case 0x6AB6: +case 0x6AB7: +case 0x6AB8: +case 0x6AB9: +case 0x6ABA: +case 0x6ABB: +case 0x6ABC: +case 0x6ABD: +case 0x6ABE: +case 0x6ABF: +case 0x6AC0: +case 0x6AC1: +case 0x6AC2: +case 0x6AC3: +case 0x6AC4: +case 0x6AC5: +case 0x6AC6: +case 0x6AC7: +case 0x6AC8: +case 0x6AC9: +case 0x6ACA: +case 0x6ACB: +case 0x6ACC: +case 0x6ACD: +case 0x6ACE: +case 0x6ACF: +case 0x6AD0: +case 0x6AD1: +case 0x6AD2: +case 0x6AD3: +case 0x6AD4: +case 0x6AD5: +case 0x6AD6: +case 0x6AD7: +case 0x6AD8: +case 0x6AD9: +case 0x6ADA: +case 0x6ADB: +case 0x6ADC: +case 0x6ADD: +case 0x6ADE: +case 0x6ADF: +case 0x6AE0: +case 0x6AE1: +case 0x6AE2: +case 0x6AE3: +case 0x6AE4: +case 0x6AE5: +case 0x6AE6: +case 0x6AE7: +case 0x6AE8: +case 0x6AE9: +case 0x6AEA: +case 0x6AEB: +case 0x6AEC: +case 0x6AED: +case 0x6AEE: +case 0x6AEF: +case 0x6AF0: +case 0x6AF1: +case 0x6AF2: +case 0x6AF3: +case 0x6AF4: +case 0x6AF5: +case 0x6AF6: +case 0x6AF7: +case 0x6AF8: +case 0x6AF9: +case 0x6AFA: +case 0x6AFB: +case 0x6AFC: +case 0x6AFD: +case 0x6AFE: +case 0x6AFF: + +// BCC +case 0x6A01: +{ + if (!(CPU->flag_N & 0x80)) + { + PC += (s32)(s8)Opcode; + CCnt -= 2; + } +} +RET(8) +case 0x6B02: +case 0x6B03: +case 0x6B04: +case 0x6B05: +case 0x6B06: +case 0x6B07: +case 0x6B08: +case 0x6B09: +case 0x6B0A: +case 0x6B0B: +case 0x6B0C: +case 0x6B0D: +case 0x6B0E: +case 0x6B0F: +case 0x6B10: +case 0x6B11: +case 0x6B12: +case 0x6B13: +case 0x6B14: +case 0x6B15: +case 0x6B16: +case 0x6B17: +case 0x6B18: +case 0x6B19: +case 0x6B1A: +case 0x6B1B: +case 0x6B1C: +case 0x6B1D: +case 0x6B1E: +case 0x6B1F: +case 0x6B20: +case 0x6B21: +case 0x6B22: +case 0x6B23: +case 0x6B24: +case 0x6B25: +case 0x6B26: +case 0x6B27: +case 0x6B28: +case 0x6B29: +case 0x6B2A: +case 0x6B2B: +case 0x6B2C: +case 0x6B2D: +case 0x6B2E: +case 0x6B2F: +case 0x6B30: +case 0x6B31: +case 0x6B32: +case 0x6B33: +case 0x6B34: +case 0x6B35: +case 0x6B36: +case 0x6B37: +case 0x6B38: +case 0x6B39: +case 0x6B3A: +case 0x6B3B: +case 0x6B3C: +case 0x6B3D: +case 0x6B3E: +case 0x6B3F: +case 0x6B40: +case 0x6B41: +case 0x6B42: +case 0x6B43: +case 0x6B44: +case 0x6B45: +case 0x6B46: +case 0x6B47: +case 0x6B48: +case 0x6B49: +case 0x6B4A: +case 0x6B4B: +case 0x6B4C: +case 0x6B4D: +case 0x6B4E: +case 0x6B4F: +case 0x6B50: +case 0x6B51: +case 0x6B52: +case 0x6B53: +case 0x6B54: +case 0x6B55: +case 0x6B56: +case 0x6B57: +case 0x6B58: +case 0x6B59: +case 0x6B5A: +case 0x6B5B: +case 0x6B5C: +case 0x6B5D: +case 0x6B5E: +case 0x6B5F: +case 0x6B60: +case 0x6B61: +case 0x6B62: +case 0x6B63: +case 0x6B64: +case 0x6B65: +case 0x6B66: +case 0x6B67: +case 0x6B68: +case 0x6B69: +case 0x6B6A: +case 0x6B6B: +case 0x6B6C: +case 0x6B6D: +case 0x6B6E: +case 0x6B6F: +case 0x6B70: +case 0x6B71: +case 0x6B72: +case 0x6B73: +case 0x6B74: +case 0x6B75: +case 0x6B76: +case 0x6B77: +case 0x6B78: +case 0x6B79: +case 0x6B7A: +case 0x6B7B: +case 0x6B7C: +case 0x6B7D: +case 0x6B7E: +case 0x6B7F: +case 0x6B80: +case 0x6B81: +case 0x6B82: +case 0x6B83: +case 0x6B84: +case 0x6B85: +case 0x6B86: +case 0x6B87: +case 0x6B88: +case 0x6B89: +case 0x6B8A: +case 0x6B8B: +case 0x6B8C: +case 0x6B8D: +case 0x6B8E: +case 0x6B8F: +case 0x6B90: +case 0x6B91: +case 0x6B92: +case 0x6B93: +case 0x6B94: +case 0x6B95: +case 0x6B96: +case 0x6B97: +case 0x6B98: +case 0x6B99: +case 0x6B9A: +case 0x6B9B: +case 0x6B9C: +case 0x6B9D: +case 0x6B9E: +case 0x6B9F: +case 0x6BA0: +case 0x6BA1: +case 0x6BA2: +case 0x6BA3: +case 0x6BA4: +case 0x6BA5: +case 0x6BA6: +case 0x6BA7: +case 0x6BA8: +case 0x6BA9: +case 0x6BAA: +case 0x6BAB: +case 0x6BAC: +case 0x6BAD: +case 0x6BAE: +case 0x6BAF: +case 0x6BB0: +case 0x6BB1: +case 0x6BB2: +case 0x6BB3: +case 0x6BB4: +case 0x6BB5: +case 0x6BB6: +case 0x6BB7: +case 0x6BB8: +case 0x6BB9: +case 0x6BBA: +case 0x6BBB: +case 0x6BBC: +case 0x6BBD: +case 0x6BBE: +case 0x6BBF: +case 0x6BC0: +case 0x6BC1: +case 0x6BC2: +case 0x6BC3: +case 0x6BC4: +case 0x6BC5: +case 0x6BC6: +case 0x6BC7: +case 0x6BC8: +case 0x6BC9: +case 0x6BCA: +case 0x6BCB: +case 0x6BCC: +case 0x6BCD: +case 0x6BCE: +case 0x6BCF: +case 0x6BD0: +case 0x6BD1: +case 0x6BD2: +case 0x6BD3: +case 0x6BD4: +case 0x6BD5: +case 0x6BD6: +case 0x6BD7: +case 0x6BD8: +case 0x6BD9: +case 0x6BDA: +case 0x6BDB: +case 0x6BDC: +case 0x6BDD: +case 0x6BDE: +case 0x6BDF: +case 0x6BE0: +case 0x6BE1: +case 0x6BE2: +case 0x6BE3: +case 0x6BE4: +case 0x6BE5: +case 0x6BE6: +case 0x6BE7: +case 0x6BE8: +case 0x6BE9: +case 0x6BEA: +case 0x6BEB: +case 0x6BEC: +case 0x6BED: +case 0x6BEE: +case 0x6BEF: +case 0x6BF0: +case 0x6BF1: +case 0x6BF2: +case 0x6BF3: +case 0x6BF4: +case 0x6BF5: +case 0x6BF6: +case 0x6BF7: +case 0x6BF8: +case 0x6BF9: +case 0x6BFA: +case 0x6BFB: +case 0x6BFC: +case 0x6BFD: +case 0x6BFE: +case 0x6BFF: + +// BCC +case 0x6B01: +{ + if (CPU->flag_N & 0x80) + { + PC += (s32)(s8)Opcode; + CCnt -= 2; + } +} +RET(8) +case 0x6C02: +case 0x6C03: +case 0x6C04: +case 0x6C05: +case 0x6C06: +case 0x6C07: +case 0x6C08: +case 0x6C09: +case 0x6C0A: +case 0x6C0B: +case 0x6C0C: +case 0x6C0D: +case 0x6C0E: +case 0x6C0F: +case 0x6C10: +case 0x6C11: +case 0x6C12: +case 0x6C13: +case 0x6C14: +case 0x6C15: +case 0x6C16: +case 0x6C17: +case 0x6C18: +case 0x6C19: +case 0x6C1A: +case 0x6C1B: +case 0x6C1C: +case 0x6C1D: +case 0x6C1E: +case 0x6C1F: +case 0x6C20: +case 0x6C21: +case 0x6C22: +case 0x6C23: +case 0x6C24: +case 0x6C25: +case 0x6C26: +case 0x6C27: +case 0x6C28: +case 0x6C29: +case 0x6C2A: +case 0x6C2B: +case 0x6C2C: +case 0x6C2D: +case 0x6C2E: +case 0x6C2F: +case 0x6C30: +case 0x6C31: +case 0x6C32: +case 0x6C33: +case 0x6C34: +case 0x6C35: +case 0x6C36: +case 0x6C37: +case 0x6C38: +case 0x6C39: +case 0x6C3A: +case 0x6C3B: +case 0x6C3C: +case 0x6C3D: +case 0x6C3E: +case 0x6C3F: +case 0x6C40: +case 0x6C41: +case 0x6C42: +case 0x6C43: +case 0x6C44: +case 0x6C45: +case 0x6C46: +case 0x6C47: +case 0x6C48: +case 0x6C49: +case 0x6C4A: +case 0x6C4B: +case 0x6C4C: +case 0x6C4D: +case 0x6C4E: +case 0x6C4F: +case 0x6C50: +case 0x6C51: +case 0x6C52: +case 0x6C53: +case 0x6C54: +case 0x6C55: +case 0x6C56: +case 0x6C57: +case 0x6C58: +case 0x6C59: +case 0x6C5A: +case 0x6C5B: +case 0x6C5C: +case 0x6C5D: +case 0x6C5E: +case 0x6C5F: +case 0x6C60: +case 0x6C61: +case 0x6C62: +case 0x6C63: +case 0x6C64: +case 0x6C65: +case 0x6C66: +case 0x6C67: +case 0x6C68: +case 0x6C69: +case 0x6C6A: +case 0x6C6B: +case 0x6C6C: +case 0x6C6D: +case 0x6C6E: +case 0x6C6F: +case 0x6C70: +case 0x6C71: +case 0x6C72: +case 0x6C73: +case 0x6C74: +case 0x6C75: +case 0x6C76: +case 0x6C77: +case 0x6C78: +case 0x6C79: +case 0x6C7A: +case 0x6C7B: +case 0x6C7C: +case 0x6C7D: +case 0x6C7E: +case 0x6C7F: +case 0x6C80: +case 0x6C81: +case 0x6C82: +case 0x6C83: +case 0x6C84: +case 0x6C85: +case 0x6C86: +case 0x6C87: +case 0x6C88: +case 0x6C89: +case 0x6C8A: +case 0x6C8B: +case 0x6C8C: +case 0x6C8D: +case 0x6C8E: +case 0x6C8F: +case 0x6C90: +case 0x6C91: +case 0x6C92: +case 0x6C93: +case 0x6C94: +case 0x6C95: +case 0x6C96: +case 0x6C97: +case 0x6C98: +case 0x6C99: +case 0x6C9A: +case 0x6C9B: +case 0x6C9C: +case 0x6C9D: +case 0x6C9E: +case 0x6C9F: +case 0x6CA0: +case 0x6CA1: +case 0x6CA2: +case 0x6CA3: +case 0x6CA4: +case 0x6CA5: +case 0x6CA6: +case 0x6CA7: +case 0x6CA8: +case 0x6CA9: +case 0x6CAA: +case 0x6CAB: +case 0x6CAC: +case 0x6CAD: +case 0x6CAE: +case 0x6CAF: +case 0x6CB0: +case 0x6CB1: +case 0x6CB2: +case 0x6CB3: +case 0x6CB4: +case 0x6CB5: +case 0x6CB6: +case 0x6CB7: +case 0x6CB8: +case 0x6CB9: +case 0x6CBA: +case 0x6CBB: +case 0x6CBC: +case 0x6CBD: +case 0x6CBE: +case 0x6CBF: +case 0x6CC0: +case 0x6CC1: +case 0x6CC2: +case 0x6CC3: +case 0x6CC4: +case 0x6CC5: +case 0x6CC6: +case 0x6CC7: +case 0x6CC8: +case 0x6CC9: +case 0x6CCA: +case 0x6CCB: +case 0x6CCC: +case 0x6CCD: +case 0x6CCE: +case 0x6CCF: +case 0x6CD0: +case 0x6CD1: +case 0x6CD2: +case 0x6CD3: +case 0x6CD4: +case 0x6CD5: +case 0x6CD6: +case 0x6CD7: +case 0x6CD8: +case 0x6CD9: +case 0x6CDA: +case 0x6CDB: +case 0x6CDC: +case 0x6CDD: +case 0x6CDE: +case 0x6CDF: +case 0x6CE0: +case 0x6CE1: +case 0x6CE2: +case 0x6CE3: +case 0x6CE4: +case 0x6CE5: +case 0x6CE6: +case 0x6CE7: +case 0x6CE8: +case 0x6CE9: +case 0x6CEA: +case 0x6CEB: +case 0x6CEC: +case 0x6CED: +case 0x6CEE: +case 0x6CEF: +case 0x6CF0: +case 0x6CF1: +case 0x6CF2: +case 0x6CF3: +case 0x6CF4: +case 0x6CF5: +case 0x6CF6: +case 0x6CF7: +case 0x6CF8: +case 0x6CF9: +case 0x6CFA: +case 0x6CFB: +case 0x6CFC: +case 0x6CFD: +case 0x6CFE: +case 0x6CFF: + +// BCC +case 0x6C01: +{ + if (!((CPU->flag_N ^ CPU->flag_V) & 0x80)) + { + PC += (s32)(s8)Opcode; + CCnt -= 2; + } +} +RET(8) +case 0x6D02: +case 0x6D03: +case 0x6D04: +case 0x6D05: +case 0x6D06: +case 0x6D07: +case 0x6D08: +case 0x6D09: +case 0x6D0A: +case 0x6D0B: +case 0x6D0C: +case 0x6D0D: +case 0x6D0E: +case 0x6D0F: +case 0x6D10: +case 0x6D11: +case 0x6D12: +case 0x6D13: +case 0x6D14: +case 0x6D15: +case 0x6D16: +case 0x6D17: +case 0x6D18: +case 0x6D19: +case 0x6D1A: +case 0x6D1B: +case 0x6D1C: +case 0x6D1D: +case 0x6D1E: +case 0x6D1F: +case 0x6D20: +case 0x6D21: +case 0x6D22: +case 0x6D23: +case 0x6D24: +case 0x6D25: +case 0x6D26: +case 0x6D27: +case 0x6D28: +case 0x6D29: +case 0x6D2A: +case 0x6D2B: +case 0x6D2C: +case 0x6D2D: +case 0x6D2E: +case 0x6D2F: +case 0x6D30: +case 0x6D31: +case 0x6D32: +case 0x6D33: +case 0x6D34: +case 0x6D35: +case 0x6D36: +case 0x6D37: +case 0x6D38: +case 0x6D39: +case 0x6D3A: +case 0x6D3B: +case 0x6D3C: +case 0x6D3D: +case 0x6D3E: +case 0x6D3F: +case 0x6D40: +case 0x6D41: +case 0x6D42: +case 0x6D43: +case 0x6D44: +case 0x6D45: +case 0x6D46: +case 0x6D47: +case 0x6D48: +case 0x6D49: +case 0x6D4A: +case 0x6D4B: +case 0x6D4C: +case 0x6D4D: +case 0x6D4E: +case 0x6D4F: +case 0x6D50: +case 0x6D51: +case 0x6D52: +case 0x6D53: +case 0x6D54: +case 0x6D55: +case 0x6D56: +case 0x6D57: +case 0x6D58: +case 0x6D59: +case 0x6D5A: +case 0x6D5B: +case 0x6D5C: +case 0x6D5D: +case 0x6D5E: +case 0x6D5F: +case 0x6D60: +case 0x6D61: +case 0x6D62: +case 0x6D63: +case 0x6D64: +case 0x6D65: +case 0x6D66: +case 0x6D67: +case 0x6D68: +case 0x6D69: +case 0x6D6A: +case 0x6D6B: +case 0x6D6C: +case 0x6D6D: +case 0x6D6E: +case 0x6D6F: +case 0x6D70: +case 0x6D71: +case 0x6D72: +case 0x6D73: +case 0x6D74: +case 0x6D75: +case 0x6D76: +case 0x6D77: +case 0x6D78: +case 0x6D79: +case 0x6D7A: +case 0x6D7B: +case 0x6D7C: +case 0x6D7D: +case 0x6D7E: +case 0x6D7F: +case 0x6D80: +case 0x6D81: +case 0x6D82: +case 0x6D83: +case 0x6D84: +case 0x6D85: +case 0x6D86: +case 0x6D87: +case 0x6D88: +case 0x6D89: +case 0x6D8A: +case 0x6D8B: +case 0x6D8C: +case 0x6D8D: +case 0x6D8E: +case 0x6D8F: +case 0x6D90: +case 0x6D91: +case 0x6D92: +case 0x6D93: +case 0x6D94: +case 0x6D95: +case 0x6D96: +case 0x6D97: +case 0x6D98: +case 0x6D99: +case 0x6D9A: +case 0x6D9B: +case 0x6D9C: +case 0x6D9D: +case 0x6D9E: +case 0x6D9F: +case 0x6DA0: +case 0x6DA1: +case 0x6DA2: +case 0x6DA3: +case 0x6DA4: +case 0x6DA5: +case 0x6DA6: +case 0x6DA7: +case 0x6DA8: +case 0x6DA9: +case 0x6DAA: +case 0x6DAB: +case 0x6DAC: +case 0x6DAD: +case 0x6DAE: +case 0x6DAF: +case 0x6DB0: +case 0x6DB1: +case 0x6DB2: +case 0x6DB3: +case 0x6DB4: +case 0x6DB5: +case 0x6DB6: +case 0x6DB7: +case 0x6DB8: +case 0x6DB9: +case 0x6DBA: +case 0x6DBB: +case 0x6DBC: +case 0x6DBD: +case 0x6DBE: +case 0x6DBF: +case 0x6DC0: +case 0x6DC1: +case 0x6DC2: +case 0x6DC3: +case 0x6DC4: +case 0x6DC5: +case 0x6DC6: +case 0x6DC7: +case 0x6DC8: +case 0x6DC9: +case 0x6DCA: +case 0x6DCB: +case 0x6DCC: +case 0x6DCD: +case 0x6DCE: +case 0x6DCF: +case 0x6DD0: +case 0x6DD1: +case 0x6DD2: +case 0x6DD3: +case 0x6DD4: +case 0x6DD5: +case 0x6DD6: +case 0x6DD7: +case 0x6DD8: +case 0x6DD9: +case 0x6DDA: +case 0x6DDB: +case 0x6DDC: +case 0x6DDD: +case 0x6DDE: +case 0x6DDF: +case 0x6DE0: +case 0x6DE1: +case 0x6DE2: +case 0x6DE3: +case 0x6DE4: +case 0x6DE5: +case 0x6DE6: +case 0x6DE7: +case 0x6DE8: +case 0x6DE9: +case 0x6DEA: +case 0x6DEB: +case 0x6DEC: +case 0x6DED: +case 0x6DEE: +case 0x6DEF: +case 0x6DF0: +case 0x6DF1: +case 0x6DF2: +case 0x6DF3: +case 0x6DF4: +case 0x6DF5: +case 0x6DF6: +case 0x6DF7: +case 0x6DF8: +case 0x6DF9: +case 0x6DFA: +case 0x6DFB: +case 0x6DFC: +case 0x6DFD: +case 0x6DFE: +case 0x6DFF: + +// BCC +case 0x6D01: +{ + if ((CPU->flag_N ^ CPU->flag_V) & 0x80) + { + PC += (s32)(s8)Opcode; + CCnt -= 2; + } +} +RET(8) +case 0x6E02: +case 0x6E03: +case 0x6E04: +case 0x6E05: +case 0x6E06: +case 0x6E07: +case 0x6E08: +case 0x6E09: +case 0x6E0A: +case 0x6E0B: +case 0x6E0C: +case 0x6E0D: +case 0x6E0E: +case 0x6E0F: +case 0x6E10: +case 0x6E11: +case 0x6E12: +case 0x6E13: +case 0x6E14: +case 0x6E15: +case 0x6E16: +case 0x6E17: +case 0x6E18: +case 0x6E19: +case 0x6E1A: +case 0x6E1B: +case 0x6E1C: +case 0x6E1D: +case 0x6E1E: +case 0x6E1F: +case 0x6E20: +case 0x6E21: +case 0x6E22: +case 0x6E23: +case 0x6E24: +case 0x6E25: +case 0x6E26: +case 0x6E27: +case 0x6E28: +case 0x6E29: +case 0x6E2A: +case 0x6E2B: +case 0x6E2C: +case 0x6E2D: +case 0x6E2E: +case 0x6E2F: +case 0x6E30: +case 0x6E31: +case 0x6E32: +case 0x6E33: +case 0x6E34: +case 0x6E35: +case 0x6E36: +case 0x6E37: +case 0x6E38: +case 0x6E39: +case 0x6E3A: +case 0x6E3B: +case 0x6E3C: +case 0x6E3D: +case 0x6E3E: +case 0x6E3F: +case 0x6E40: +case 0x6E41: +case 0x6E42: +case 0x6E43: +case 0x6E44: +case 0x6E45: +case 0x6E46: +case 0x6E47: +case 0x6E48: +case 0x6E49: +case 0x6E4A: +case 0x6E4B: +case 0x6E4C: +case 0x6E4D: +case 0x6E4E: +case 0x6E4F: +case 0x6E50: +case 0x6E51: +case 0x6E52: +case 0x6E53: +case 0x6E54: +case 0x6E55: +case 0x6E56: +case 0x6E57: +case 0x6E58: +case 0x6E59: +case 0x6E5A: +case 0x6E5B: +case 0x6E5C: +case 0x6E5D: +case 0x6E5E: +case 0x6E5F: +case 0x6E60: +case 0x6E61: +case 0x6E62: +case 0x6E63: +case 0x6E64: +case 0x6E65: +case 0x6E66: +case 0x6E67: +case 0x6E68: +case 0x6E69: +case 0x6E6A: +case 0x6E6B: +case 0x6E6C: +case 0x6E6D: +case 0x6E6E: +case 0x6E6F: +case 0x6E70: +case 0x6E71: +case 0x6E72: +case 0x6E73: +case 0x6E74: +case 0x6E75: +case 0x6E76: +case 0x6E77: +case 0x6E78: +case 0x6E79: +case 0x6E7A: +case 0x6E7B: +case 0x6E7C: +case 0x6E7D: +case 0x6E7E: +case 0x6E7F: +case 0x6E80: +case 0x6E81: +case 0x6E82: +case 0x6E83: +case 0x6E84: +case 0x6E85: +case 0x6E86: +case 0x6E87: +case 0x6E88: +case 0x6E89: +case 0x6E8A: +case 0x6E8B: +case 0x6E8C: +case 0x6E8D: +case 0x6E8E: +case 0x6E8F: +case 0x6E90: +case 0x6E91: +case 0x6E92: +case 0x6E93: +case 0x6E94: +case 0x6E95: +case 0x6E96: +case 0x6E97: +case 0x6E98: +case 0x6E99: +case 0x6E9A: +case 0x6E9B: +case 0x6E9C: +case 0x6E9D: +case 0x6E9E: +case 0x6E9F: +case 0x6EA0: +case 0x6EA1: +case 0x6EA2: +case 0x6EA3: +case 0x6EA4: +case 0x6EA5: +case 0x6EA6: +case 0x6EA7: +case 0x6EA8: +case 0x6EA9: +case 0x6EAA: +case 0x6EAB: +case 0x6EAC: +case 0x6EAD: +case 0x6EAE: +case 0x6EAF: +case 0x6EB0: +case 0x6EB1: +case 0x6EB2: +case 0x6EB3: +case 0x6EB4: +case 0x6EB5: +case 0x6EB6: +case 0x6EB7: +case 0x6EB8: +case 0x6EB9: +case 0x6EBA: +case 0x6EBB: +case 0x6EBC: +case 0x6EBD: +case 0x6EBE: +case 0x6EBF: +case 0x6EC0: +case 0x6EC1: +case 0x6EC2: +case 0x6EC3: +case 0x6EC4: +case 0x6EC5: +case 0x6EC6: +case 0x6EC7: +case 0x6EC8: +case 0x6EC9: +case 0x6ECA: +case 0x6ECB: +case 0x6ECC: +case 0x6ECD: +case 0x6ECE: +case 0x6ECF: +case 0x6ED0: +case 0x6ED1: +case 0x6ED2: +case 0x6ED3: +case 0x6ED4: +case 0x6ED5: +case 0x6ED6: +case 0x6ED7: +case 0x6ED8: +case 0x6ED9: +case 0x6EDA: +case 0x6EDB: +case 0x6EDC: +case 0x6EDD: +case 0x6EDE: +case 0x6EDF: +case 0x6EE0: +case 0x6EE1: +case 0x6EE2: +case 0x6EE3: +case 0x6EE4: +case 0x6EE5: +case 0x6EE6: +case 0x6EE7: +case 0x6EE8: +case 0x6EE9: +case 0x6EEA: +case 0x6EEB: +case 0x6EEC: +case 0x6EED: +case 0x6EEE: +case 0x6EEF: +case 0x6EF0: +case 0x6EF1: +case 0x6EF2: +case 0x6EF3: +case 0x6EF4: +case 0x6EF5: +case 0x6EF6: +case 0x6EF7: +case 0x6EF8: +case 0x6EF9: +case 0x6EFA: +case 0x6EFB: +case 0x6EFC: +case 0x6EFD: +case 0x6EFE: +case 0x6EFF: + +// BCC +case 0x6E01: +{ + if (CPU->flag_notZ && (!((CPU->flag_N ^ CPU->flag_V) & 0x80))) + { + PC += (s32)(s8)Opcode; + CCnt -= 2; + } +} +RET(8) +case 0x6F02: +case 0x6F03: +case 0x6F04: +case 0x6F05: +case 0x6F06: +case 0x6F07: +case 0x6F08: +case 0x6F09: +case 0x6F0A: +case 0x6F0B: +case 0x6F0C: +case 0x6F0D: +case 0x6F0E: +case 0x6F0F: +case 0x6F10: +case 0x6F11: +case 0x6F12: +case 0x6F13: +case 0x6F14: +case 0x6F15: +case 0x6F16: +case 0x6F17: +case 0x6F18: +case 0x6F19: +case 0x6F1A: +case 0x6F1B: +case 0x6F1C: +case 0x6F1D: +case 0x6F1E: +case 0x6F1F: +case 0x6F20: +case 0x6F21: +case 0x6F22: +case 0x6F23: +case 0x6F24: +case 0x6F25: +case 0x6F26: +case 0x6F27: +case 0x6F28: +case 0x6F29: +case 0x6F2A: +case 0x6F2B: +case 0x6F2C: +case 0x6F2D: +case 0x6F2E: +case 0x6F2F: +case 0x6F30: +case 0x6F31: +case 0x6F32: +case 0x6F33: +case 0x6F34: +case 0x6F35: +case 0x6F36: +case 0x6F37: +case 0x6F38: +case 0x6F39: +case 0x6F3A: +case 0x6F3B: +case 0x6F3C: +case 0x6F3D: +case 0x6F3E: +case 0x6F3F: +case 0x6F40: +case 0x6F41: +case 0x6F42: +case 0x6F43: +case 0x6F44: +case 0x6F45: +case 0x6F46: +case 0x6F47: +case 0x6F48: +case 0x6F49: +case 0x6F4A: +case 0x6F4B: +case 0x6F4C: +case 0x6F4D: +case 0x6F4E: +case 0x6F4F: +case 0x6F50: +case 0x6F51: +case 0x6F52: +case 0x6F53: +case 0x6F54: +case 0x6F55: +case 0x6F56: +case 0x6F57: +case 0x6F58: +case 0x6F59: +case 0x6F5A: +case 0x6F5B: +case 0x6F5C: +case 0x6F5D: +case 0x6F5E: +case 0x6F5F: +case 0x6F60: +case 0x6F61: +case 0x6F62: +case 0x6F63: +case 0x6F64: +case 0x6F65: +case 0x6F66: +case 0x6F67: +case 0x6F68: +case 0x6F69: +case 0x6F6A: +case 0x6F6B: +case 0x6F6C: +case 0x6F6D: +case 0x6F6E: +case 0x6F6F: +case 0x6F70: +case 0x6F71: +case 0x6F72: +case 0x6F73: +case 0x6F74: +case 0x6F75: +case 0x6F76: +case 0x6F77: +case 0x6F78: +case 0x6F79: +case 0x6F7A: +case 0x6F7B: +case 0x6F7C: +case 0x6F7D: +case 0x6F7E: +case 0x6F7F: +case 0x6F80: +case 0x6F81: +case 0x6F82: +case 0x6F83: +case 0x6F84: +case 0x6F85: +case 0x6F86: +case 0x6F87: +case 0x6F88: +case 0x6F89: +case 0x6F8A: +case 0x6F8B: +case 0x6F8C: +case 0x6F8D: +case 0x6F8E: +case 0x6F8F: +case 0x6F90: +case 0x6F91: +case 0x6F92: +case 0x6F93: +case 0x6F94: +case 0x6F95: +case 0x6F96: +case 0x6F97: +case 0x6F98: +case 0x6F99: +case 0x6F9A: +case 0x6F9B: +case 0x6F9C: +case 0x6F9D: +case 0x6F9E: +case 0x6F9F: +case 0x6FA0: +case 0x6FA1: +case 0x6FA2: +case 0x6FA3: +case 0x6FA4: +case 0x6FA5: +case 0x6FA6: +case 0x6FA7: +case 0x6FA8: +case 0x6FA9: +case 0x6FAA: +case 0x6FAB: +case 0x6FAC: +case 0x6FAD: +case 0x6FAE: +case 0x6FAF: +case 0x6FB0: +case 0x6FB1: +case 0x6FB2: +case 0x6FB3: +case 0x6FB4: +case 0x6FB5: +case 0x6FB6: +case 0x6FB7: +case 0x6FB8: +case 0x6FB9: +case 0x6FBA: +case 0x6FBB: +case 0x6FBC: +case 0x6FBD: +case 0x6FBE: +case 0x6FBF: +case 0x6FC0: +case 0x6FC1: +case 0x6FC2: +case 0x6FC3: +case 0x6FC4: +case 0x6FC5: +case 0x6FC6: +case 0x6FC7: +case 0x6FC8: +case 0x6FC9: +case 0x6FCA: +case 0x6FCB: +case 0x6FCC: +case 0x6FCD: +case 0x6FCE: +case 0x6FCF: +case 0x6FD0: +case 0x6FD1: +case 0x6FD2: +case 0x6FD3: +case 0x6FD4: +case 0x6FD5: +case 0x6FD6: +case 0x6FD7: +case 0x6FD8: +case 0x6FD9: +case 0x6FDA: +case 0x6FDB: +case 0x6FDC: +case 0x6FDD: +case 0x6FDE: +case 0x6FDF: +case 0x6FE0: +case 0x6FE1: +case 0x6FE2: +case 0x6FE3: +case 0x6FE4: +case 0x6FE5: +case 0x6FE6: +case 0x6FE7: +case 0x6FE8: +case 0x6FE9: +case 0x6FEA: +case 0x6FEB: +case 0x6FEC: +case 0x6FED: +case 0x6FEE: +case 0x6FEF: +case 0x6FF0: +case 0x6FF1: +case 0x6FF2: +case 0x6FF3: +case 0x6FF4: +case 0x6FF5: +case 0x6FF6: +case 0x6FF7: +case 0x6FF8: +case 0x6FF9: +case 0x6FFA: +case 0x6FFB: +case 0x6FFC: +case 0x6FFD: +case 0x6FFE: +case 0x6FFF: + +// BCC +case 0x6F01: +{ + if ((!CPU->flag_notZ) || ((CPU->flag_N ^ CPU->flag_V) & 0x80)) + { + PC += (s32)(s8)Opcode; + CCnt -= 2; + } +} +RET(8) + +// BCC16 +case 0x6200: +{ + if (CPU->flag_notZ && (!(CPU->flag_C & 0x100))) + { + PC += (s32)(s16)FETCH_WORD; + PC -= CPU->BasePC; + SET_PC(PC); + RET(10) + } + PC += 2; +} +RET(12) + +// BCC16 +case 0x6300: +{ + if ((!CPU->flag_notZ) || (CPU->flag_C & 0x100)) + { + PC += (s32)(s16)FETCH_WORD; + PC -= CPU->BasePC; + SET_PC(PC); + RET(10) + } + PC += 2; +} +RET(12) + +// BCC16 +case 0x6400: +{ + if (!(CPU->flag_C & 0x100)) + { + PC += (s32)(s16)FETCH_WORD; + PC -= CPU->BasePC; + SET_PC(PC); + RET(10) + } + PC += 2; +} +RET(12) + +// BCC16 +case 0x6500: +{ + if (CPU->flag_C & 0x100) + { + PC += (s32)(s16)FETCH_WORD; + PC -= CPU->BasePC; + SET_PC(PC); + RET(10) + } + PC += 2; +} +RET(12) + +// BCC16 +case 0x6600: +{ + if (CPU->flag_notZ) + { + PC += (s32)(s16)FETCH_WORD; + PC -= CPU->BasePC; + SET_PC(PC); + RET(10) + } + PC += 2; +} +RET(12) + +// BCC16 +case 0x6700: +{ + if (!CPU->flag_notZ) + { + PC += (s32)(s16)FETCH_WORD; + PC -= CPU->BasePC; + SET_PC(PC); + RET(10) + } + PC += 2; +} +RET(12) + +// BCC16 +case 0x6800: +{ + if (!(CPU->flag_V & 0x80)) + { + PC += (s32)(s16)FETCH_WORD; + PC -= CPU->BasePC; + SET_PC(PC); + RET(10) + } + PC += 2; +} +RET(12) + +// BCC16 +case 0x6900: +{ + if (CPU->flag_V & 0x80) + { + PC += (s32)(s16)FETCH_WORD; + PC -= CPU->BasePC; + SET_PC(PC); + RET(10) + } + PC += 2; +} +RET(12) + +// BCC16 +case 0x6A00: +{ + if (!(CPU->flag_N & 0x80)) + { + PC += (s32)(s16)FETCH_WORD; + PC -= CPU->BasePC; + SET_PC(PC); + RET(10) + } + PC += 2; +} +RET(12) + +// BCC16 +case 0x6B00: +{ + if (CPU->flag_N & 0x80) + { + PC += (s32)(s16)FETCH_WORD; + PC -= CPU->BasePC; + SET_PC(PC); + RET(10) + } + PC += 2; +} +RET(12) + +// BCC16 +case 0x6C00: +{ + if (!((CPU->flag_N ^ CPU->flag_V) & 0x80)) + { + PC += (s32)(s16)FETCH_WORD; + PC -= CPU->BasePC; + SET_PC(PC); + RET(10) + } + PC += 2; +} +RET(12) + +// BCC16 +case 0x6D00: +{ + if ((CPU->flag_N ^ CPU->flag_V) & 0x80) + { + PC += (s32)(s16)FETCH_WORD; + PC -= CPU->BasePC; + SET_PC(PC); + RET(10) + } + PC += 2; +} +RET(12) + +// BCC16 +case 0x6E00: +{ + if (CPU->flag_notZ && (!((CPU->flag_N ^ CPU->flag_V) & 0x80))) + { + PC += (s32)(s16)FETCH_WORD; + PC -= CPU->BasePC; + SET_PC(PC); + RET(10) + } + PC += 2; +} +RET(12) + +// BCC16 +case 0x6F00: +{ + if ((!CPU->flag_notZ) || ((CPU->flag_N ^ CPU->flag_V) & 0x80)) + { + PC += (s32)(s16)FETCH_WORD; + PC -= CPU->BasePC; + SET_PC(PC); + RET(10) + } + PC += 2; +} +RET(12) +case 0x6002: +case 0x6003: +case 0x6004: +case 0x6005: +case 0x6006: +case 0x6007: +case 0x6008: +case 0x6009: +case 0x600A: +case 0x600B: +case 0x600C: +case 0x600D: +case 0x600E: +case 0x600F: +case 0x6010: +case 0x6011: +case 0x6012: +case 0x6013: +case 0x6014: +case 0x6015: +case 0x6016: +case 0x6017: +case 0x6018: +case 0x6019: +case 0x601A: +case 0x601B: +case 0x601C: +case 0x601D: +case 0x601E: +case 0x601F: +case 0x6020: +case 0x6021: +case 0x6022: +case 0x6023: +case 0x6024: +case 0x6025: +case 0x6026: +case 0x6027: +case 0x6028: +case 0x6029: +case 0x602A: +case 0x602B: +case 0x602C: +case 0x602D: +case 0x602E: +case 0x602F: +case 0x6030: +case 0x6031: +case 0x6032: +case 0x6033: +case 0x6034: +case 0x6035: +case 0x6036: +case 0x6037: +case 0x6038: +case 0x6039: +case 0x603A: +case 0x603B: +case 0x603C: +case 0x603D: +case 0x603E: +case 0x603F: +case 0x6040: +case 0x6041: +case 0x6042: +case 0x6043: +case 0x6044: +case 0x6045: +case 0x6046: +case 0x6047: +case 0x6048: +case 0x6049: +case 0x604A: +case 0x604B: +case 0x604C: +case 0x604D: +case 0x604E: +case 0x604F: +case 0x6050: +case 0x6051: +case 0x6052: +case 0x6053: +case 0x6054: +case 0x6055: +case 0x6056: +case 0x6057: +case 0x6058: +case 0x6059: +case 0x605A: +case 0x605B: +case 0x605C: +case 0x605D: +case 0x605E: +case 0x605F: +case 0x6060: +case 0x6061: +case 0x6062: +case 0x6063: +case 0x6064: +case 0x6065: +case 0x6066: +case 0x6067: +case 0x6068: +case 0x6069: +case 0x606A: +case 0x606B: +case 0x606C: +case 0x606D: +case 0x606E: +case 0x606F: +case 0x6070: +case 0x6071: +case 0x6072: +case 0x6073: +case 0x6074: +case 0x6075: +case 0x6076: +case 0x6077: +case 0x6078: +case 0x6079: +case 0x607A: +case 0x607B: +case 0x607C: +case 0x607D: +case 0x607E: +case 0x607F: +case 0x6080: +case 0x6081: +case 0x6082: +case 0x6083: +case 0x6084: +case 0x6085: +case 0x6086: +case 0x6087: +case 0x6088: +case 0x6089: +case 0x608A: +case 0x608B: +case 0x608C: +case 0x608D: +case 0x608E: +case 0x608F: +case 0x6090: +case 0x6091: +case 0x6092: +case 0x6093: +case 0x6094: +case 0x6095: +case 0x6096: +case 0x6097: +case 0x6098: +case 0x6099: +case 0x609A: +case 0x609B: +case 0x609C: +case 0x609D: +case 0x609E: +case 0x609F: +case 0x60A0: +case 0x60A1: +case 0x60A2: +case 0x60A3: +case 0x60A4: +case 0x60A5: +case 0x60A6: +case 0x60A7: +case 0x60A8: +case 0x60A9: +case 0x60AA: +case 0x60AB: +case 0x60AC: +case 0x60AD: +case 0x60AE: +case 0x60AF: +case 0x60B0: +case 0x60B1: +case 0x60B2: +case 0x60B3: +case 0x60B4: +case 0x60B5: +case 0x60B6: +case 0x60B7: +case 0x60B8: +case 0x60B9: +case 0x60BA: +case 0x60BB: +case 0x60BC: +case 0x60BD: +case 0x60BE: +case 0x60BF: +case 0x60C0: +case 0x60C1: +case 0x60C2: +case 0x60C3: +case 0x60C4: +case 0x60C5: +case 0x60C6: +case 0x60C7: +case 0x60C8: +case 0x60C9: +case 0x60CA: +case 0x60CB: +case 0x60CC: +case 0x60CD: +case 0x60CE: +case 0x60CF: +case 0x60D0: +case 0x60D1: +case 0x60D2: +case 0x60D3: +case 0x60D4: +case 0x60D5: +case 0x60D6: +case 0x60D7: +case 0x60D8: +case 0x60D9: +case 0x60DA: +case 0x60DB: +case 0x60DC: +case 0x60DD: +case 0x60DE: +case 0x60DF: +case 0x60E0: +case 0x60E1: +case 0x60E2: +case 0x60E3: +case 0x60E4: +case 0x60E5: +case 0x60E6: +case 0x60E7: +case 0x60E8: +case 0x60E9: +case 0x60EA: +case 0x60EB: +case 0x60EC: +case 0x60ED: +case 0x60EE: +case 0x60EF: +case 0x60F0: +case 0x60F1: +case 0x60F2: +case 0x60F3: +case 0x60F4: +case 0x60F5: +case 0x60F6: +case 0x60F7: +case 0x60F8: +case 0x60F9: +case 0x60FA: +case 0x60FB: +case 0x60FC: +case 0x60FD: +case 0x60FE: +case 0x60FF: + +// BRA +case 0x6001: +{ + PC += (s32)(s8)Opcode; +} +RET(10) + +// BRA16 +case 0x6000: +{ + PC += (s32)(s16)FETCH_WORD; + PC -= CPU->BasePC; + SET_PC(PC); +} +RET(10) +case 0x6102: +case 0x6103: +case 0x6104: +case 0x6105: +case 0x6106: +case 0x6107: +case 0x6108: +case 0x6109: +case 0x610A: +case 0x610B: +case 0x610C: +case 0x610D: +case 0x610E: +case 0x610F: +case 0x6110: +case 0x6111: +case 0x6112: +case 0x6113: +case 0x6114: +case 0x6115: +case 0x6116: +case 0x6117: +case 0x6118: +case 0x6119: +case 0x611A: +case 0x611B: +case 0x611C: +case 0x611D: +case 0x611E: +case 0x611F: +case 0x6120: +case 0x6121: +case 0x6122: +case 0x6123: +case 0x6124: +case 0x6125: +case 0x6126: +case 0x6127: +case 0x6128: +case 0x6129: +case 0x612A: +case 0x612B: +case 0x612C: +case 0x612D: +case 0x612E: +case 0x612F: +case 0x6130: +case 0x6131: +case 0x6132: +case 0x6133: +case 0x6134: +case 0x6135: +case 0x6136: +case 0x6137: +case 0x6138: +case 0x6139: +case 0x613A: +case 0x613B: +case 0x613C: +case 0x613D: +case 0x613E: +case 0x613F: +case 0x6140: +case 0x6141: +case 0x6142: +case 0x6143: +case 0x6144: +case 0x6145: +case 0x6146: +case 0x6147: +case 0x6148: +case 0x6149: +case 0x614A: +case 0x614B: +case 0x614C: +case 0x614D: +case 0x614E: +case 0x614F: +case 0x6150: +case 0x6151: +case 0x6152: +case 0x6153: +case 0x6154: +case 0x6155: +case 0x6156: +case 0x6157: +case 0x6158: +case 0x6159: +case 0x615A: +case 0x615B: +case 0x615C: +case 0x615D: +case 0x615E: +case 0x615F: +case 0x6160: +case 0x6161: +case 0x6162: +case 0x6163: +case 0x6164: +case 0x6165: +case 0x6166: +case 0x6167: +case 0x6168: +case 0x6169: +case 0x616A: +case 0x616B: +case 0x616C: +case 0x616D: +case 0x616E: +case 0x616F: +case 0x6170: +case 0x6171: +case 0x6172: +case 0x6173: +case 0x6174: +case 0x6175: +case 0x6176: +case 0x6177: +case 0x6178: +case 0x6179: +case 0x617A: +case 0x617B: +case 0x617C: +case 0x617D: +case 0x617E: +case 0x617F: +case 0x6180: +case 0x6181: +case 0x6182: +case 0x6183: +case 0x6184: +case 0x6185: +case 0x6186: +case 0x6187: +case 0x6188: +case 0x6189: +case 0x618A: +case 0x618B: +case 0x618C: +case 0x618D: +case 0x618E: +case 0x618F: +case 0x6190: +case 0x6191: +case 0x6192: +case 0x6193: +case 0x6194: +case 0x6195: +case 0x6196: +case 0x6197: +case 0x6198: +case 0x6199: +case 0x619A: +case 0x619B: +case 0x619C: +case 0x619D: +case 0x619E: +case 0x619F: +case 0x61A0: +case 0x61A1: +case 0x61A2: +case 0x61A3: +case 0x61A4: +case 0x61A5: +case 0x61A6: +case 0x61A7: +case 0x61A8: +case 0x61A9: +case 0x61AA: +case 0x61AB: +case 0x61AC: +case 0x61AD: +case 0x61AE: +case 0x61AF: +case 0x61B0: +case 0x61B1: +case 0x61B2: +case 0x61B3: +case 0x61B4: +case 0x61B5: +case 0x61B6: +case 0x61B7: +case 0x61B8: +case 0x61B9: +case 0x61BA: +case 0x61BB: +case 0x61BC: +case 0x61BD: +case 0x61BE: +case 0x61BF: +case 0x61C0: +case 0x61C1: +case 0x61C2: +case 0x61C3: +case 0x61C4: +case 0x61C5: +case 0x61C6: +case 0x61C7: +case 0x61C8: +case 0x61C9: +case 0x61CA: +case 0x61CB: +case 0x61CC: +case 0x61CD: +case 0x61CE: +case 0x61CF: +case 0x61D0: +case 0x61D1: +case 0x61D2: +case 0x61D3: +case 0x61D4: +case 0x61D5: +case 0x61D6: +case 0x61D7: +case 0x61D8: +case 0x61D9: +case 0x61DA: +case 0x61DB: +case 0x61DC: +case 0x61DD: +case 0x61DE: +case 0x61DF: +case 0x61E0: +case 0x61E1: +case 0x61E2: +case 0x61E3: +case 0x61E4: +case 0x61E5: +case 0x61E6: +case 0x61E7: +case 0x61E8: +case 0x61E9: +case 0x61EA: +case 0x61EB: +case 0x61EC: +case 0x61ED: +case 0x61EE: +case 0x61EF: +case 0x61F0: +case 0x61F1: +case 0x61F2: +case 0x61F3: +case 0x61F4: +case 0x61F5: +case 0x61F6: +case 0x61F7: +case 0x61F8: +case 0x61F9: +case 0x61FA: +case 0x61FB: +case 0x61FC: +case 0x61FD: +case 0x61FE: +case 0x61FF: + +// BSR +case 0x6101: +{ + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PC += (s32)(s8)Opcode; + POST_IO +} +RET(18) + +// BSR16 +case 0x6100: +{ + u32 res; + res = (s32)(s16)FETCH_WORD; + PC -= CPU->BasePC; + PRE_IO + PUSH_32_F(PC + 2) + PC += (s32) res; + SET_PC(PC); + POST_IO +} +RET(18) diff --git a/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68k_op7.inc b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68k_op7.inc new file mode 100644 index 000000000..0c2267b15 --- /dev/null +++ b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68k_op7.inc @@ -0,0 +1,2058 @@ +case 0x7001: +case 0x7002: +case 0x7003: +case 0x7004: +case 0x7005: +case 0x7006: +case 0x7007: +case 0x7008: +case 0x7009: +case 0x700A: +case 0x700B: +case 0x700C: +case 0x700D: +case 0x700E: +case 0x700F: +case 0x7010: +case 0x7011: +case 0x7012: +case 0x7013: +case 0x7014: +case 0x7015: +case 0x7016: +case 0x7017: +case 0x7018: +case 0x7019: +case 0x701A: +case 0x701B: +case 0x701C: +case 0x701D: +case 0x701E: +case 0x701F: +case 0x7020: +case 0x7021: +case 0x7022: +case 0x7023: +case 0x7024: +case 0x7025: +case 0x7026: +case 0x7027: +case 0x7028: +case 0x7029: +case 0x702A: +case 0x702B: +case 0x702C: +case 0x702D: +case 0x702E: +case 0x702F: +case 0x7030: +case 0x7031: +case 0x7032: +case 0x7033: +case 0x7034: +case 0x7035: +case 0x7036: +case 0x7037: +case 0x7038: +case 0x7039: +case 0x703A: +case 0x703B: +case 0x703C: +case 0x703D: +case 0x703E: +case 0x703F: +case 0x7040: +case 0x7041: +case 0x7042: +case 0x7043: +case 0x7044: +case 0x7045: +case 0x7046: +case 0x7047: +case 0x7048: +case 0x7049: +case 0x704A: +case 0x704B: +case 0x704C: +case 0x704D: +case 0x704E: +case 0x704F: +case 0x7050: +case 0x7051: +case 0x7052: +case 0x7053: +case 0x7054: +case 0x7055: +case 0x7056: +case 0x7057: +case 0x7058: +case 0x7059: +case 0x705A: +case 0x705B: +case 0x705C: +case 0x705D: +case 0x705E: +case 0x705F: +case 0x7060: +case 0x7061: +case 0x7062: +case 0x7063: +case 0x7064: +case 0x7065: +case 0x7066: +case 0x7067: +case 0x7068: +case 0x7069: +case 0x706A: +case 0x706B: +case 0x706C: +case 0x706D: +case 0x706E: +case 0x706F: +case 0x7070: +case 0x7071: +case 0x7072: +case 0x7073: +case 0x7074: +case 0x7075: +case 0x7076: +case 0x7077: +case 0x7078: +case 0x7079: +case 0x707A: +case 0x707B: +case 0x707C: +case 0x707D: +case 0x707E: +case 0x707F: +case 0x7080: +case 0x7081: +case 0x7082: +case 0x7083: +case 0x7084: +case 0x7085: +case 0x7086: +case 0x7087: +case 0x7088: +case 0x7089: +case 0x708A: +case 0x708B: +case 0x708C: +case 0x708D: +case 0x708E: +case 0x708F: +case 0x7090: +case 0x7091: +case 0x7092: +case 0x7093: +case 0x7094: +case 0x7095: +case 0x7096: +case 0x7097: +case 0x7098: +case 0x7099: +case 0x709A: +case 0x709B: +case 0x709C: +case 0x709D: +case 0x709E: +case 0x709F: +case 0x70A0: +case 0x70A1: +case 0x70A2: +case 0x70A3: +case 0x70A4: +case 0x70A5: +case 0x70A6: +case 0x70A7: +case 0x70A8: +case 0x70A9: +case 0x70AA: +case 0x70AB: +case 0x70AC: +case 0x70AD: +case 0x70AE: +case 0x70AF: +case 0x70B0: +case 0x70B1: +case 0x70B2: +case 0x70B3: +case 0x70B4: +case 0x70B5: +case 0x70B6: +case 0x70B7: +case 0x70B8: +case 0x70B9: +case 0x70BA: +case 0x70BB: +case 0x70BC: +case 0x70BD: +case 0x70BE: +case 0x70BF: +case 0x70C0: +case 0x70C1: +case 0x70C2: +case 0x70C3: +case 0x70C4: +case 0x70C5: +case 0x70C6: +case 0x70C7: +case 0x70C8: +case 0x70C9: +case 0x70CA: +case 0x70CB: +case 0x70CC: +case 0x70CD: +case 0x70CE: +case 0x70CF: +case 0x70D0: +case 0x70D1: +case 0x70D2: +case 0x70D3: +case 0x70D4: +case 0x70D5: +case 0x70D6: +case 0x70D7: +case 0x70D8: +case 0x70D9: +case 0x70DA: +case 0x70DB: +case 0x70DC: +case 0x70DD: +case 0x70DE: +case 0x70DF: +case 0x70E0: +case 0x70E1: +case 0x70E2: +case 0x70E3: +case 0x70E4: +case 0x70E5: +case 0x70E6: +case 0x70E7: +case 0x70E8: +case 0x70E9: +case 0x70EA: +case 0x70EB: +case 0x70EC: +case 0x70ED: +case 0x70EE: +case 0x70EF: +case 0x70F0: +case 0x70F1: +case 0x70F2: +case 0x70F3: +case 0x70F4: +case 0x70F5: +case 0x70F6: +case 0x70F7: +case 0x70F8: +case 0x70F9: +case 0x70FA: +case 0x70FB: +case 0x70FC: +case 0x70FD: +case 0x70FE: +case 0x70FF: +case 0x7200: +case 0x7201: +case 0x7202: +case 0x7203: +case 0x7204: +case 0x7205: +case 0x7206: +case 0x7207: +case 0x7208: +case 0x7209: +case 0x720A: +case 0x720B: +case 0x720C: +case 0x720D: +case 0x720E: +case 0x720F: +case 0x7210: +case 0x7211: +case 0x7212: +case 0x7213: +case 0x7214: +case 0x7215: +case 0x7216: +case 0x7217: +case 0x7218: +case 0x7219: +case 0x721A: +case 0x721B: +case 0x721C: +case 0x721D: +case 0x721E: +case 0x721F: +case 0x7220: +case 0x7221: +case 0x7222: +case 0x7223: +case 0x7224: +case 0x7225: +case 0x7226: +case 0x7227: +case 0x7228: +case 0x7229: +case 0x722A: +case 0x722B: +case 0x722C: +case 0x722D: +case 0x722E: +case 0x722F: +case 0x7230: +case 0x7231: +case 0x7232: +case 0x7233: +case 0x7234: +case 0x7235: +case 0x7236: +case 0x7237: +case 0x7238: +case 0x7239: +case 0x723A: +case 0x723B: +case 0x723C: +case 0x723D: +case 0x723E: +case 0x723F: +case 0x7240: +case 0x7241: +case 0x7242: +case 0x7243: +case 0x7244: +case 0x7245: +case 0x7246: +case 0x7247: +case 0x7248: +case 0x7249: +case 0x724A: +case 0x724B: +case 0x724C: +case 0x724D: +case 0x724E: +case 0x724F: +case 0x7250: +case 0x7251: +case 0x7252: +case 0x7253: +case 0x7254: +case 0x7255: +case 0x7256: +case 0x7257: +case 0x7258: +case 0x7259: +case 0x725A: +case 0x725B: +case 0x725C: +case 0x725D: +case 0x725E: +case 0x725F: +case 0x7260: +case 0x7261: +case 0x7262: +case 0x7263: +case 0x7264: +case 0x7265: +case 0x7266: +case 0x7267: +case 0x7268: +case 0x7269: +case 0x726A: +case 0x726B: +case 0x726C: +case 0x726D: +case 0x726E: +case 0x726F: +case 0x7270: +case 0x7271: +case 0x7272: +case 0x7273: +case 0x7274: +case 0x7275: +case 0x7276: +case 0x7277: +case 0x7278: +case 0x7279: +case 0x727A: +case 0x727B: +case 0x727C: +case 0x727D: +case 0x727E: +case 0x727F: +case 0x7280: +case 0x7281: +case 0x7282: +case 0x7283: +case 0x7284: +case 0x7285: +case 0x7286: +case 0x7287: +case 0x7288: +case 0x7289: +case 0x728A: +case 0x728B: +case 0x728C: +case 0x728D: +case 0x728E: +case 0x728F: +case 0x7290: +case 0x7291: +case 0x7292: +case 0x7293: +case 0x7294: +case 0x7295: +case 0x7296: +case 0x7297: +case 0x7298: +case 0x7299: +case 0x729A: +case 0x729B: +case 0x729C: +case 0x729D: +case 0x729E: +case 0x729F: +case 0x72A0: +case 0x72A1: +case 0x72A2: +case 0x72A3: +case 0x72A4: +case 0x72A5: +case 0x72A6: +case 0x72A7: +case 0x72A8: +case 0x72A9: +case 0x72AA: +case 0x72AB: +case 0x72AC: +case 0x72AD: +case 0x72AE: +case 0x72AF: +case 0x72B0: +case 0x72B1: +case 0x72B2: +case 0x72B3: +case 0x72B4: +case 0x72B5: +case 0x72B6: +case 0x72B7: +case 0x72B8: +case 0x72B9: +case 0x72BA: +case 0x72BB: +case 0x72BC: +case 0x72BD: +case 0x72BE: +case 0x72BF: +case 0x72C0: +case 0x72C1: +case 0x72C2: +case 0x72C3: +case 0x72C4: +case 0x72C5: +case 0x72C6: +case 0x72C7: +case 0x72C8: +case 0x72C9: +case 0x72CA: +case 0x72CB: +case 0x72CC: +case 0x72CD: +case 0x72CE: +case 0x72CF: +case 0x72D0: +case 0x72D1: +case 0x72D2: +case 0x72D3: +case 0x72D4: +case 0x72D5: +case 0x72D6: +case 0x72D7: +case 0x72D8: +case 0x72D9: +case 0x72DA: +case 0x72DB: +case 0x72DC: +case 0x72DD: +case 0x72DE: +case 0x72DF: +case 0x72E0: +case 0x72E1: +case 0x72E2: +case 0x72E3: +case 0x72E4: +case 0x72E5: +case 0x72E6: +case 0x72E7: +case 0x72E8: +case 0x72E9: +case 0x72EA: +case 0x72EB: +case 0x72EC: +case 0x72ED: +case 0x72EE: +case 0x72EF: +case 0x72F0: +case 0x72F1: +case 0x72F2: +case 0x72F3: +case 0x72F4: +case 0x72F5: +case 0x72F6: +case 0x72F7: +case 0x72F8: +case 0x72F9: +case 0x72FA: +case 0x72FB: +case 0x72FC: +case 0x72FD: +case 0x72FE: +case 0x72FF: +case 0x7400: +case 0x7401: +case 0x7402: +case 0x7403: +case 0x7404: +case 0x7405: +case 0x7406: +case 0x7407: +case 0x7408: +case 0x7409: +case 0x740A: +case 0x740B: +case 0x740C: +case 0x740D: +case 0x740E: +case 0x740F: +case 0x7410: +case 0x7411: +case 0x7412: +case 0x7413: +case 0x7414: +case 0x7415: +case 0x7416: +case 0x7417: +case 0x7418: +case 0x7419: +case 0x741A: +case 0x741B: +case 0x741C: +case 0x741D: +case 0x741E: +case 0x741F: +case 0x7420: +case 0x7421: +case 0x7422: +case 0x7423: +case 0x7424: +case 0x7425: +case 0x7426: +case 0x7427: +case 0x7428: +case 0x7429: +case 0x742A: +case 0x742B: +case 0x742C: +case 0x742D: +case 0x742E: +case 0x742F: +case 0x7430: +case 0x7431: +case 0x7432: +case 0x7433: +case 0x7434: +case 0x7435: +case 0x7436: +case 0x7437: +case 0x7438: +case 0x7439: +case 0x743A: +case 0x743B: +case 0x743C: +case 0x743D: +case 0x743E: +case 0x743F: +case 0x7440: +case 0x7441: +case 0x7442: +case 0x7443: +case 0x7444: +case 0x7445: +case 0x7446: +case 0x7447: +case 0x7448: +case 0x7449: +case 0x744A: +case 0x744B: +case 0x744C: +case 0x744D: +case 0x744E: +case 0x744F: +case 0x7450: +case 0x7451: +case 0x7452: +case 0x7453: +case 0x7454: +case 0x7455: +case 0x7456: +case 0x7457: +case 0x7458: +case 0x7459: +case 0x745A: +case 0x745B: +case 0x745C: +case 0x745D: +case 0x745E: +case 0x745F: +case 0x7460: +case 0x7461: +case 0x7462: +case 0x7463: +case 0x7464: +case 0x7465: +case 0x7466: +case 0x7467: +case 0x7468: +case 0x7469: +case 0x746A: +case 0x746B: +case 0x746C: +case 0x746D: +case 0x746E: +case 0x746F: +case 0x7470: +case 0x7471: +case 0x7472: +case 0x7473: +case 0x7474: +case 0x7475: +case 0x7476: +case 0x7477: +case 0x7478: +case 0x7479: +case 0x747A: +case 0x747B: +case 0x747C: +case 0x747D: +case 0x747E: +case 0x747F: +case 0x7480: +case 0x7481: +case 0x7482: +case 0x7483: +case 0x7484: +case 0x7485: +case 0x7486: +case 0x7487: +case 0x7488: +case 0x7489: +case 0x748A: +case 0x748B: +case 0x748C: +case 0x748D: +case 0x748E: +case 0x748F: +case 0x7490: +case 0x7491: +case 0x7492: +case 0x7493: +case 0x7494: +case 0x7495: +case 0x7496: +case 0x7497: +case 0x7498: +case 0x7499: +case 0x749A: +case 0x749B: +case 0x749C: +case 0x749D: +case 0x749E: +case 0x749F: +case 0x74A0: +case 0x74A1: +case 0x74A2: +case 0x74A3: +case 0x74A4: +case 0x74A5: +case 0x74A6: +case 0x74A7: +case 0x74A8: +case 0x74A9: +case 0x74AA: +case 0x74AB: +case 0x74AC: +case 0x74AD: +case 0x74AE: +case 0x74AF: +case 0x74B0: +case 0x74B1: +case 0x74B2: +case 0x74B3: +case 0x74B4: +case 0x74B5: +case 0x74B6: +case 0x74B7: +case 0x74B8: +case 0x74B9: +case 0x74BA: +case 0x74BB: +case 0x74BC: +case 0x74BD: +case 0x74BE: +case 0x74BF: +case 0x74C0: +case 0x74C1: +case 0x74C2: +case 0x74C3: +case 0x74C4: +case 0x74C5: +case 0x74C6: +case 0x74C7: +case 0x74C8: +case 0x74C9: +case 0x74CA: +case 0x74CB: +case 0x74CC: +case 0x74CD: +case 0x74CE: +case 0x74CF: +case 0x74D0: +case 0x74D1: +case 0x74D2: +case 0x74D3: +case 0x74D4: +case 0x74D5: +case 0x74D6: +case 0x74D7: +case 0x74D8: +case 0x74D9: +case 0x74DA: +case 0x74DB: +case 0x74DC: +case 0x74DD: +case 0x74DE: +case 0x74DF: +case 0x74E0: +case 0x74E1: +case 0x74E2: +case 0x74E3: +case 0x74E4: +case 0x74E5: +case 0x74E6: +case 0x74E7: +case 0x74E8: +case 0x74E9: +case 0x74EA: +case 0x74EB: +case 0x74EC: +case 0x74ED: +case 0x74EE: +case 0x74EF: +case 0x74F0: +case 0x74F1: +case 0x74F2: +case 0x74F3: +case 0x74F4: +case 0x74F5: +case 0x74F6: +case 0x74F7: +case 0x74F8: +case 0x74F9: +case 0x74FA: +case 0x74FB: +case 0x74FC: +case 0x74FD: +case 0x74FE: +case 0x74FF: +case 0x7600: +case 0x7601: +case 0x7602: +case 0x7603: +case 0x7604: +case 0x7605: +case 0x7606: +case 0x7607: +case 0x7608: +case 0x7609: +case 0x760A: +case 0x760B: +case 0x760C: +case 0x760D: +case 0x760E: +case 0x760F: +case 0x7610: +case 0x7611: +case 0x7612: +case 0x7613: +case 0x7614: +case 0x7615: +case 0x7616: +case 0x7617: +case 0x7618: +case 0x7619: +case 0x761A: +case 0x761B: +case 0x761C: +case 0x761D: +case 0x761E: +case 0x761F: +case 0x7620: +case 0x7621: +case 0x7622: +case 0x7623: +case 0x7624: +case 0x7625: +case 0x7626: +case 0x7627: +case 0x7628: +case 0x7629: +case 0x762A: +case 0x762B: +case 0x762C: +case 0x762D: +case 0x762E: +case 0x762F: +case 0x7630: +case 0x7631: +case 0x7632: +case 0x7633: +case 0x7634: +case 0x7635: +case 0x7636: +case 0x7637: +case 0x7638: +case 0x7639: +case 0x763A: +case 0x763B: +case 0x763C: +case 0x763D: +case 0x763E: +case 0x763F: +case 0x7640: +case 0x7641: +case 0x7642: +case 0x7643: +case 0x7644: +case 0x7645: +case 0x7646: +case 0x7647: +case 0x7648: +case 0x7649: +case 0x764A: +case 0x764B: +case 0x764C: +case 0x764D: +case 0x764E: +case 0x764F: +case 0x7650: +case 0x7651: +case 0x7652: +case 0x7653: +case 0x7654: +case 0x7655: +case 0x7656: +case 0x7657: +case 0x7658: +case 0x7659: +case 0x765A: +case 0x765B: +case 0x765C: +case 0x765D: +case 0x765E: +case 0x765F: +case 0x7660: +case 0x7661: +case 0x7662: +case 0x7663: +case 0x7664: +case 0x7665: +case 0x7666: +case 0x7667: +case 0x7668: +case 0x7669: +case 0x766A: +case 0x766B: +case 0x766C: +case 0x766D: +case 0x766E: +case 0x766F: +case 0x7670: +case 0x7671: +case 0x7672: +case 0x7673: +case 0x7674: +case 0x7675: +case 0x7676: +case 0x7677: +case 0x7678: +case 0x7679: +case 0x767A: +case 0x767B: +case 0x767C: +case 0x767D: +case 0x767E: +case 0x767F: +case 0x7680: +case 0x7681: +case 0x7682: +case 0x7683: +case 0x7684: +case 0x7685: +case 0x7686: +case 0x7687: +case 0x7688: +case 0x7689: +case 0x768A: +case 0x768B: +case 0x768C: +case 0x768D: +case 0x768E: +case 0x768F: +case 0x7690: +case 0x7691: +case 0x7692: +case 0x7693: +case 0x7694: +case 0x7695: +case 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0x7C5C: +case 0x7C5D: +case 0x7C5E: +case 0x7C5F: +case 0x7C60: +case 0x7C61: +case 0x7C62: +case 0x7C63: +case 0x7C64: +case 0x7C65: +case 0x7C66: +case 0x7C67: +case 0x7C68: +case 0x7C69: +case 0x7C6A: +case 0x7C6B: +case 0x7C6C: +case 0x7C6D: +case 0x7C6E: +case 0x7C6F: +case 0x7C70: +case 0x7C71: +case 0x7C72: +case 0x7C73: +case 0x7C74: +case 0x7C75: +case 0x7C76: +case 0x7C77: +case 0x7C78: +case 0x7C79: +case 0x7C7A: +case 0x7C7B: +case 0x7C7C: +case 0x7C7D: +case 0x7C7E: +case 0x7C7F: +case 0x7C80: +case 0x7C81: +case 0x7C82: +case 0x7C83: +case 0x7C84: +case 0x7C85: +case 0x7C86: +case 0x7C87: +case 0x7C88: +case 0x7C89: +case 0x7C8A: +case 0x7C8B: +case 0x7C8C: +case 0x7C8D: +case 0x7C8E: +case 0x7C8F: +case 0x7C90: +case 0x7C91: +case 0x7C92: +case 0x7C93: +case 0x7C94: +case 0x7C95: +case 0x7C96: +case 0x7C97: +case 0x7C98: +case 0x7C99: +case 0x7C9A: +case 0x7C9B: +case 0x7C9C: +case 0x7C9D: +case 0x7C9E: +case 0x7C9F: +case 0x7CA0: +case 0x7CA1: +case 0x7CA2: +case 0x7CA3: +case 0x7CA4: +case 0x7CA5: +case 0x7CA6: +case 0x7CA7: +case 0x7CA8: +case 0x7CA9: +case 0x7CAA: +case 0x7CAB: +case 0x7CAC: +case 0x7CAD: +case 0x7CAE: +case 0x7CAF: +case 0x7CB0: +case 0x7CB1: +case 0x7CB2: +case 0x7CB3: +case 0x7CB4: +case 0x7CB5: +case 0x7CB6: +case 0x7CB7: +case 0x7CB8: +case 0x7CB9: +case 0x7CBA: +case 0x7CBB: +case 0x7CBC: +case 0x7CBD: +case 0x7CBE: +case 0x7CBF: +case 0x7CC0: +case 0x7CC1: +case 0x7CC2: +case 0x7CC3: +case 0x7CC4: +case 0x7CC5: +case 0x7CC6: +case 0x7CC7: +case 0x7CC8: +case 0x7CC9: +case 0x7CCA: +case 0x7CCB: +case 0x7CCC: +case 0x7CCD: +case 0x7CCE: +case 0x7CCF: +case 0x7CD0: +case 0x7CD1: +case 0x7CD2: +case 0x7CD3: +case 0x7CD4: +case 0x7CD5: +case 0x7CD6: +case 0x7CD7: +case 0x7CD8: +case 0x7CD9: +case 0x7CDA: +case 0x7CDB: +case 0x7CDC: +case 0x7CDD: +case 0x7CDE: +case 0x7CDF: +case 0x7CE0: +case 0x7CE1: +case 0x7CE2: +case 0x7CE3: +case 0x7CE4: +case 0x7CE5: +case 0x7CE6: +case 0x7CE7: +case 0x7CE8: +case 0x7CE9: +case 0x7CEA: +case 0x7CEB: +case 0x7CEC: +case 0x7CED: +case 0x7CEE: +case 0x7CEF: +case 0x7CF0: +case 0x7CF1: +case 0x7CF2: +case 0x7CF3: +case 0x7CF4: +case 0x7CF5: +case 0x7CF6: +case 0x7CF7: +case 0x7CF8: +case 0x7CF9: +case 0x7CFA: +case 0x7CFB: +case 0x7CFC: +case 0x7CFD: +case 0x7CFE: +case 0x7CFF: +case 0x7E00: +case 0x7E01: +case 0x7E02: +case 0x7E03: +case 0x7E04: +case 0x7E05: +case 0x7E06: +case 0x7E07: +case 0x7E08: +case 0x7E09: +case 0x7E0A: +case 0x7E0B: +case 0x7E0C: +case 0x7E0D: +case 0x7E0E: +case 0x7E0F: +case 0x7E10: +case 0x7E11: +case 0x7E12: +case 0x7E13: +case 0x7E14: +case 0x7E15: +case 0x7E16: +case 0x7E17: +case 0x7E18: +case 0x7E19: +case 0x7E1A: +case 0x7E1B: +case 0x7E1C: +case 0x7E1D: +case 0x7E1E: +case 0x7E1F: +case 0x7E20: +case 0x7E21: +case 0x7E22: +case 0x7E23: +case 0x7E24: +case 0x7E25: +case 0x7E26: +case 0x7E27: +case 0x7E28: +case 0x7E29: +case 0x7E2A: +case 0x7E2B: +case 0x7E2C: +case 0x7E2D: +case 0x7E2E: +case 0x7E2F: +case 0x7E30: +case 0x7E31: +case 0x7E32: +case 0x7E33: +case 0x7E34: +case 0x7E35: +case 0x7E36: +case 0x7E37: +case 0x7E38: +case 0x7E39: +case 0x7E3A: +case 0x7E3B: +case 0x7E3C: +case 0x7E3D: +case 0x7E3E: +case 0x7E3F: +case 0x7E40: +case 0x7E41: +case 0x7E42: +case 0x7E43: +case 0x7E44: +case 0x7E45: +case 0x7E46: +case 0x7E47: +case 0x7E48: +case 0x7E49: +case 0x7E4A: +case 0x7E4B: +case 0x7E4C: +case 0x7E4D: +case 0x7E4E: +case 0x7E4F: +case 0x7E50: +case 0x7E51: +case 0x7E52: +case 0x7E53: +case 0x7E54: +case 0x7E55: +case 0x7E56: +case 0x7E57: +case 0x7E58: +case 0x7E59: +case 0x7E5A: +case 0x7E5B: +case 0x7E5C: +case 0x7E5D: +case 0x7E5E: +case 0x7E5F: +case 0x7E60: +case 0x7E61: +case 0x7E62: +case 0x7E63: +case 0x7E64: +case 0x7E65: +case 0x7E66: +case 0x7E67: +case 0x7E68: +case 0x7E69: +case 0x7E6A: +case 0x7E6B: +case 0x7E6C: +case 0x7E6D: +case 0x7E6E: +case 0x7E6F: +case 0x7E70: +case 0x7E71: +case 0x7E72: +case 0x7E73: +case 0x7E74: +case 0x7E75: +case 0x7E76: +case 0x7E77: +case 0x7E78: +case 0x7E79: +case 0x7E7A: +case 0x7E7B: +case 0x7E7C: +case 0x7E7D: +case 0x7E7E: +case 0x7E7F: +case 0x7E80: +case 0x7E81: +case 0x7E82: +case 0x7E83: +case 0x7E84: +case 0x7E85: +case 0x7E86: +case 0x7E87: +case 0x7E88: +case 0x7E89: +case 0x7E8A: +case 0x7E8B: +case 0x7E8C: +case 0x7E8D: +case 0x7E8E: +case 0x7E8F: +case 0x7E90: +case 0x7E91: +case 0x7E92: +case 0x7E93: +case 0x7E94: +case 0x7E95: +case 0x7E96: +case 0x7E97: +case 0x7E98: +case 0x7E99: +case 0x7E9A: +case 0x7E9B: +case 0x7E9C: +case 0x7E9D: +case 0x7E9E: +case 0x7E9F: +case 0x7EA0: +case 0x7EA1: +case 0x7EA2: +case 0x7EA3: +case 0x7EA4: +case 0x7EA5: +case 0x7EA6: +case 0x7EA7: +case 0x7EA8: +case 0x7EA9: +case 0x7EAA: +case 0x7EAB: +case 0x7EAC: +case 0x7EAD: +case 0x7EAE: +case 0x7EAF: +case 0x7EB0: +case 0x7EB1: +case 0x7EB2: +case 0x7EB3: +case 0x7EB4: +case 0x7EB5: +case 0x7EB6: +case 0x7EB7: +case 0x7EB8: +case 0x7EB9: +case 0x7EBA: +case 0x7EBB: +case 0x7EBC: +case 0x7EBD: +case 0x7EBE: +case 0x7EBF: +case 0x7EC0: +case 0x7EC1: +case 0x7EC2: +case 0x7EC3: +case 0x7EC4: +case 0x7EC5: +case 0x7EC6: +case 0x7EC7: +case 0x7EC8: +case 0x7EC9: +case 0x7ECA: +case 0x7ECB: +case 0x7ECC: +case 0x7ECD: +case 0x7ECE: +case 0x7ECF: +case 0x7ED0: +case 0x7ED1: +case 0x7ED2: +case 0x7ED3: +case 0x7ED4: +case 0x7ED5: +case 0x7ED6: +case 0x7ED7: +case 0x7ED8: +case 0x7ED9: +case 0x7EDA: +case 0x7EDB: +case 0x7EDC: +case 0x7EDD: +case 0x7EDE: +case 0x7EDF: +case 0x7EE0: +case 0x7EE1: +case 0x7EE2: +case 0x7EE3: +case 0x7EE4: +case 0x7EE5: +case 0x7EE6: +case 0x7EE7: +case 0x7EE8: +case 0x7EE9: +case 0x7EEA: +case 0x7EEB: +case 0x7EEC: +case 0x7EED: +case 0x7EEE: +case 0x7EEF: +case 0x7EF0: +case 0x7EF1: +case 0x7EF2: +case 0x7EF3: +case 0x7EF4: +case 0x7EF5: +case 0x7EF6: +case 0x7EF7: +case 0x7EF8: +case 0x7EF9: +case 0x7EFA: +case 0x7EFB: +case 0x7EFC: +case 0x7EFD: +case 0x7EFE: +case 0x7EFF: + +// MOVEQ +case 0x7000: +{ + u32 res; + res = (s32)(s8)Opcode; + CPU->flag_C = CPU->flag_V = 0; + CPU->flag_N = CPU->flag_notZ = res; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; +} +RET(4) diff --git a/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68k_op8.inc b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68k_op8.inc new file mode 100644 index 000000000..16a276116 --- /dev/null +++ b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68k_op8.inc @@ -0,0 +1,6117 @@ +case 0x8200: +case 0x8400: +case 0x8600: +case 0x8800: +case 0x8A00: +case 0x8C00: +case 0x8E00: +case 0x8001: +case 0x8201: +case 0x8401: +case 0x8601: +case 0x8801: +case 0x8A01: +case 0x8C01: +case 0x8E01: +case 0x8002: +case 0x8202: +case 0x8402: +case 0x8602: +case 0x8802: +case 0x8A02: +case 0x8C02: +case 0x8E02: +case 0x8003: +case 0x8203: +case 0x8403: +case 0x8603: +case 0x8803: +case 0x8A03: +case 0x8C03: +case 0x8E03: +case 0x8004: +case 0x8204: +case 0x8404: +case 0x8604: +case 0x8804: +case 0x8A04: +case 0x8C04: +case 0x8E04: +case 0x8005: +case 0x8205: +case 0x8405: +case 0x8605: +case 0x8805: +case 0x8A05: +case 0x8C05: +case 0x8E05: +case 0x8006: +case 0x8206: +case 0x8406: +case 0x8606: +case 0x8806: +case 0x8A06: +case 0x8C06: +case 0x8E06: +case 0x8007: +case 0x8207: +case 0x8407: +case 0x8607: +case 0x8807: +case 0x8A07: +case 0x8C07: +case 0x8E07: + +// ORaD +case 0x8000: +{ + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 0) & 7]; + res = (u8)CPU->D[(Opcode >> 9) & 7]; + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; +} +RET(4) +case 0x8210: +case 0x8410: +case 0x8610: +case 0x8810: +case 0x8A10: +case 0x8C10: +case 0x8E10: +case 0x8011: +case 0x8211: +case 0x8411: +case 0x8611: +case 0x8811: +case 0x8A11: +case 0x8C11: +case 0x8E11: +case 0x8012: +case 0x8212: +case 0x8412: +case 0x8612: +case 0x8812: +case 0x8A12: +case 0x8C12: +case 0x8E12: +case 0x8013: +case 0x8213: +case 0x8413: +case 0x8613: +case 0x8813: +case 0x8A13: +case 0x8C13: +case 0x8E13: +case 0x8014: +case 0x8214: +case 0x8414: +case 0x8614: +case 0x8814: +case 0x8A14: +case 0x8C14: +case 0x8E14: +case 0x8015: +case 0x8215: +case 0x8415: +case 0x8615: +case 0x8815: +case 0x8A15: +case 0x8C15: +case 0x8E15: +case 0x8016: +case 0x8216: +case 0x8416: +case 0x8616: +case 0x8816: +case 0x8A16: +case 0x8C16: +case 0x8E16: +case 0x8017: +case 0x8217: +case 0x8417: +case 0x8617: +case 0x8817: +case 0x8A17: +case 0x8C17: +case 0x8E17: + +// ORaD +case 0x8010: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_BYTE_F(adr, src) + res = (u8)CPU->D[(Opcode >> 9) & 7]; + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(8) +case 0x8218: +case 0x8418: +case 0x8618: +case 0x8818: +case 0x8A18: +case 0x8C18: +case 0x8E18: +case 0x8019: +case 0x8219: +case 0x8419: +case 0x8619: +case 0x8819: +case 0x8A19: +case 0x8C19: +case 0x8E19: +case 0x801A: +case 0x821A: +case 0x841A: +case 0x861A: +case 0x881A: +case 0x8A1A: +case 0x8C1A: +case 0x8E1A: +case 0x801B: +case 0x821B: +case 0x841B: +case 0x861B: +case 0x881B: +case 0x8A1B: +case 0x8C1B: +case 0x8E1B: +case 0x801C: +case 0x821C: +case 0x841C: +case 0x861C: +case 0x881C: +case 0x8A1C: +case 0x8C1C: +case 0x8E1C: +case 0x801D: +case 0x821D: +case 0x841D: +case 0x861D: +case 0x881D: +case 0x8A1D: +case 0x8C1D: +case 0x8E1D: +case 0x801E: +case 0x821E: +case 0x841E: +case 0x861E: +case 0x881E: +case 0x8A1E: +case 0x8C1E: +case 0x8E1E: + +// ORaD +case 0x8018: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + PRE_IO + READ_BYTE_F(adr, src) + res = (u8)CPU->D[(Opcode >> 9) & 7]; + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(8) +case 0x8220: +case 0x8420: +case 0x8620: +case 0x8820: +case 0x8A20: +case 0x8C20: +case 0x8E20: +case 0x8021: +case 0x8221: +case 0x8421: +case 0x8621: +case 0x8821: +case 0x8A21: +case 0x8C21: +case 0x8E21: +case 0x8022: +case 0x8222: +case 0x8422: +case 0x8622: +case 0x8822: +case 0x8A22: +case 0x8C22: +case 0x8E22: +case 0x8023: +case 0x8223: +case 0x8423: +case 0x8623: +case 0x8823: +case 0x8A23: +case 0x8C23: +case 0x8E23: +case 0x8024: +case 0x8224: +case 0x8424: +case 0x8624: +case 0x8824: +case 0x8A24: +case 0x8C24: +case 0x8E24: +case 0x8025: +case 0x8225: +case 0x8425: +case 0x8625: +case 0x8825: +case 0x8A25: +case 0x8C25: +case 0x8E25: +case 0x8026: +case 0x8226: +case 0x8426: +case 0x8626: +case 0x8826: +case 0x8A26: +case 0x8C26: +case 0x8E26: + +// ORaD +case 0x8020: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_BYTE_F(adr, src) + res = (u8)CPU->D[(Opcode >> 9) & 7]; + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(10) +case 0x8228: +case 0x8428: +case 0x8628: +case 0x8828: +case 0x8A28: +case 0x8C28: +case 0x8E28: +case 0x8029: +case 0x8229: +case 0x8429: +case 0x8629: +case 0x8829: +case 0x8A29: +case 0x8C29: +case 0x8E29: +case 0x802A: +case 0x822A: +case 0x842A: +case 0x862A: +case 0x882A: +case 0x8A2A: +case 0x8C2A: +case 0x8E2A: +case 0x802B: +case 0x822B: +case 0x842B: +case 0x862B: +case 0x882B: +case 0x8A2B: +case 0x8C2B: +case 0x8E2B: +case 0x802C: +case 0x822C: +case 0x842C: +case 0x862C: +case 0x882C: +case 0x8A2C: +case 0x8C2C: +case 0x8E2C: +case 0x802D: +case 0x822D: +case 0x842D: +case 0x862D: +case 0x882D: +case 0x8A2D: +case 0x8C2D: +case 0x8E2D: +case 0x802E: +case 0x822E: +case 0x842E: +case 0x862E: +case 0x882E: +case 0x8A2E: +case 0x8C2E: +case 0x8E2E: +case 0x802F: +case 0x822F: +case 0x842F: +case 0x862F: +case 0x882F: +case 0x8A2F: +case 0x8C2F: +case 0x8E2F: + +// ORaD +case 0x8028: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, src) + res = (u8)CPU->D[(Opcode >> 9) & 7]; + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(12) +case 0x8230: +case 0x8430: +case 0x8630: +case 0x8830: +case 0x8A30: +case 0x8C30: +case 0x8E30: +case 0x8031: +case 0x8231: +case 0x8431: +case 0x8631: +case 0x8831: +case 0x8A31: +case 0x8C31: +case 0x8E31: +case 0x8032: +case 0x8232: +case 0x8432: +case 0x8632: +case 0x8832: +case 0x8A32: +case 0x8C32: +case 0x8E32: +case 0x8033: +case 0x8233: +case 0x8433: +case 0x8633: +case 0x8833: +case 0x8A33: +case 0x8C33: +case 0x8E33: +case 0x8034: +case 0x8234: +case 0x8434: +case 0x8634: +case 0x8834: +case 0x8A34: +case 0x8C34: +case 0x8E34: +case 0x8035: +case 0x8235: +case 0x8435: +case 0x8635: +case 0x8835: +case 0x8A35: +case 0x8C35: +case 0x8E35: +case 0x8036: +case 0x8236: +case 0x8436: +case 0x8636: +case 0x8836: +case 0x8A36: +case 0x8C36: +case 0x8E36: +case 0x8037: +case 0x8237: +case 0x8437: +case 0x8637: +case 0x8837: +case 0x8A37: +case 0x8C37: +case 0x8E37: + +// ORaD +case 0x8030: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, src) + res = (u8)CPU->D[(Opcode >> 9) & 7]; + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(14) +case 0x8238: +case 0x8438: +case 0x8638: +case 0x8838: +case 0x8A38: +case 0x8C38: +case 0x8E38: + +// ORaD +case 0x8038: +{ + u32 adr; + u32 res; + pointer src; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, src) + res = (u8)CPU->D[(Opcode >> 9) & 7]; + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(12) +case 0x8239: +case 0x8439: +case 0x8639: +case 0x8839: +case 0x8A39: +case 0x8C39: +case 0x8E39: + +// ORaD +case 0x8039: +{ + u32 adr; + u32 res; + pointer src; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_BYTE_F(adr, src) + res = (u8)CPU->D[(Opcode >> 9) & 7]; + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(16) +case 0x823A: +case 0x843A: +case 0x863A: +case 0x883A: +case 0x8A3A: +case 0x8C3A: +case 0x8E3A: + +// ORaD +case 0x803A: +{ + u32 adr; + u32 res; + pointer src; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, src) + res = (u8)CPU->D[(Opcode >> 9) & 7]; + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(12) +case 0x823B: +case 0x843B: +case 0x863B: +case 0x883B: +case 0x8A3B: +case 0x8C3B: +case 0x8E3B: + +// ORaD +case 0x803B: +{ + u32 adr; + u32 res; + pointer src; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, src) + res = (u8)CPU->D[(Opcode >> 9) & 7]; + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(14) +case 0x823C: +case 0x843C: +case 0x863C: +case 0x883C: +case 0x8A3C: +case 0x8C3C: +case 0x8E3C: + +// ORaD +case 0x803C: +{ + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + res = (u8)CPU->D[(Opcode >> 9) & 7]; + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; +} +RET(8) +case 0x821F: +case 0x841F: +case 0x861F: +case 0x881F: +case 0x8A1F: +case 0x8C1F: +case 0x8E1F: + +// ORaD +case 0x801F: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_BYTE_F(adr, src) + res = (u8)CPU->D[(Opcode >> 9) & 7]; + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(8) +case 0x8227: +case 0x8427: +case 0x8627: +case 0x8827: +case 0x8A27: +case 0x8C27: +case 0x8E27: + +// ORaD +case 0x8027: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_BYTE_F(adr, src) + res = (u8)CPU->D[(Opcode >> 9) & 7]; + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(10) +case 0x8240: +case 0x8440: +case 0x8640: +case 0x8840: +case 0x8A40: +case 0x8C40: +case 0x8E40: +case 0x8041: +case 0x8241: +case 0x8441: +case 0x8641: +case 0x8841: +case 0x8A41: +case 0x8C41: +case 0x8E41: +case 0x8042: +case 0x8242: +case 0x8442: +case 0x8642: +case 0x8842: +case 0x8A42: +case 0x8C42: +case 0x8E42: +case 0x8043: +case 0x8243: +case 0x8443: +case 0x8643: +case 0x8843: +case 0x8A43: +case 0x8C43: +case 0x8E43: +case 0x8044: +case 0x8244: +case 0x8444: +case 0x8644: +case 0x8844: +case 0x8A44: +case 0x8C44: +case 0x8E44: +case 0x8045: +case 0x8245: +case 0x8445: +case 0x8645: +case 0x8845: +case 0x8A45: +case 0x8C45: +case 0x8E45: +case 0x8046: +case 0x8246: +case 0x8446: +case 0x8646: +case 0x8846: +case 0x8A46: +case 0x8C46: +case 0x8E46: +case 0x8047: +case 0x8247: +case 0x8447: +case 0x8647: +case 0x8847: +case 0x8A47: +case 0x8C47: +case 0x8E47: + +// ORaD +case 0x8040: +{ + u32 res; + pointer src; + src = (u16)CPU->D[(Opcode >> 0) & 7]; + res = (u16)CPU->D[(Opcode >> 9) & 7]; + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; +} +RET(4) +case 0x8250: +case 0x8450: +case 0x8650: +case 0x8850: +case 0x8A50: +case 0x8C50: +case 0x8E50: +case 0x8051: +case 0x8251: +case 0x8451: +case 0x8651: +case 0x8851: +case 0x8A51: +case 0x8C51: +case 0x8E51: +case 0x8052: +case 0x8252: +case 0x8452: +case 0x8652: +case 0x8852: +case 0x8A52: +case 0x8C52: +case 0x8E52: +case 0x8053: +case 0x8253: +case 0x8453: +case 0x8653: +case 0x8853: +case 0x8A53: +case 0x8C53: +case 0x8E53: +case 0x8054: +case 0x8254: +case 0x8454: +case 0x8654: +case 0x8854: +case 0x8A54: +case 0x8C54: +case 0x8E54: +case 0x8055: +case 0x8255: +case 0x8455: +case 0x8655: +case 0x8855: +case 0x8A55: +case 0x8C55: +case 0x8E55: +case 0x8056: +case 0x8256: +case 0x8456: +case 0x8656: +case 0x8856: +case 0x8A56: +case 0x8C56: +case 0x8E56: +case 0x8057: +case 0x8257: +case 0x8457: +case 0x8657: +case 0x8857: +case 0x8A57: +case 0x8C57: +case 0x8E57: + +// ORaD +case 0x8050: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_WORD_F(adr, src) + res = (u16)CPU->D[(Opcode >> 9) & 7]; + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(8) +case 0x8258: +case 0x8458: +case 0x8658: +case 0x8858: +case 0x8A58: +case 0x8C58: +case 0x8E58: +case 0x8059: +case 0x8259: +case 0x8459: +case 0x8659: +case 0x8859: +case 0x8A59: +case 0x8C59: +case 0x8E59: +case 0x805A: +case 0x825A: +case 0x845A: +case 0x865A: +case 0x885A: +case 0x8A5A: +case 0x8C5A: +case 0x8E5A: +case 0x805B: +case 0x825B: +case 0x845B: +case 0x865B: +case 0x885B: +case 0x8A5B: +case 0x8C5B: +case 0x8E5B: +case 0x805C: +case 0x825C: +case 0x845C: +case 0x865C: +case 0x885C: +case 0x8A5C: +case 0x8C5C: +case 0x8E5C: +case 0x805D: +case 0x825D: +case 0x845D: +case 0x865D: +case 0x885D: +case 0x8A5D: +case 0x8C5D: +case 0x8E5D: +case 0x805E: +case 0x825E: +case 0x845E: +case 0x865E: +case 0x885E: +case 0x8A5E: +case 0x8C5E: +case 0x8E5E: + +// ORaD +case 0x8058: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 2; + PRE_IO + READ_WORD_F(adr, src) + res = (u16)CPU->D[(Opcode >> 9) & 7]; + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(8) +case 0x8260: +case 0x8460: +case 0x8660: +case 0x8860: +case 0x8A60: +case 0x8C60: +case 0x8E60: +case 0x8061: +case 0x8261: +case 0x8461: +case 0x8661: +case 0x8861: +case 0x8A61: +case 0x8C61: +case 0x8E61: +case 0x8062: +case 0x8262: +case 0x8462: +case 0x8662: +case 0x8862: +case 0x8A62: +case 0x8C62: +case 0x8E62: +case 0x8063: +case 0x8263: +case 0x8463: +case 0x8663: +case 0x8863: +case 0x8A63: +case 0x8C63: +case 0x8E63: +case 0x8064: +case 0x8264: +case 0x8464: +case 0x8664: +case 0x8864: +case 0x8A64: +case 0x8C64: +case 0x8E64: +case 0x8065: +case 0x8265: +case 0x8465: +case 0x8665: +case 0x8865: +case 0x8A65: +case 0x8C65: +case 0x8E65: +case 0x8066: +case 0x8266: +case 0x8466: +case 0x8666: +case 0x8866: +case 0x8A66: +case 0x8C66: +case 0x8E66: + +// ORaD +case 0x8060: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 2; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_WORD_F(adr, src) + res = (u16)CPU->D[(Opcode >> 9) & 7]; + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(10) +case 0x8268: +case 0x8468: +case 0x8668: +case 0x8868: +case 0x8A68: +case 0x8C68: +case 0x8E68: +case 0x8069: +case 0x8269: +case 0x8469: +case 0x8669: +case 0x8869: +case 0x8A69: +case 0x8C69: +case 0x8E69: +case 0x806A: +case 0x826A: +case 0x846A: +case 0x866A: +case 0x886A: +case 0x8A6A: +case 0x8C6A: +case 0x8E6A: +case 0x806B: +case 0x826B: +case 0x846B: +case 0x866B: +case 0x886B: +case 0x8A6B: +case 0x8C6B: +case 0x8E6B: +case 0x806C: +case 0x826C: +case 0x846C: +case 0x866C: +case 0x886C: +case 0x8A6C: +case 0x8C6C: +case 0x8E6C: +case 0x806D: +case 0x826D: +case 0x846D: +case 0x866D: +case 0x886D: +case 0x8A6D: +case 0x8C6D: +case 0x8E6D: +case 0x806E: +case 0x826E: +case 0x846E: +case 0x866E: +case 0x886E: +case 0x8A6E: +case 0x8C6E: +case 0x8E6E: +case 0x806F: +case 0x826F: +case 0x846F: +case 0x866F: +case 0x886F: +case 0x8A6F: +case 0x8C6F: +case 0x8E6F: + +// ORaD +case 0x8068: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, src) + res = (u16)CPU->D[(Opcode >> 9) & 7]; + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(12) +case 0x8270: +case 0x8470: +case 0x8670: +case 0x8870: +case 0x8A70: +case 0x8C70: +case 0x8E70: +case 0x8071: +case 0x8271: +case 0x8471: +case 0x8671: +case 0x8871: +case 0x8A71: +case 0x8C71: +case 0x8E71: +case 0x8072: +case 0x8272: +case 0x8472: +case 0x8672: +case 0x8872: +case 0x8A72: +case 0x8C72: +case 0x8E72: +case 0x8073: +case 0x8273: +case 0x8473: +case 0x8673: +case 0x8873: +case 0x8A73: +case 0x8C73: +case 0x8E73: +case 0x8074: +case 0x8274: +case 0x8474: +case 0x8674: +case 0x8874: +case 0x8A74: +case 0x8C74: +case 0x8E74: +case 0x8075: +case 0x8275: +case 0x8475: +case 0x8675: +case 0x8875: +case 0x8A75: +case 0x8C75: +case 0x8E75: +case 0x8076: +case 0x8276: +case 0x8476: +case 0x8676: +case 0x8876: +case 0x8A76: +case 0x8C76: +case 0x8E76: +case 0x8077: +case 0x8277: +case 0x8477: +case 0x8677: +case 0x8877: +case 0x8A77: +case 0x8C77: +case 0x8E77: + +// ORaD +case 0x8070: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, src) + res = (u16)CPU->D[(Opcode >> 9) & 7]; + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(14) +case 0x8278: +case 0x8478: +case 0x8678: +case 0x8878: +case 0x8A78: +case 0x8C78: +case 0x8E78: + +// ORaD +case 0x8078: +{ + u32 adr; + u32 res; + pointer src; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, src) + res = (u16)CPU->D[(Opcode >> 9) & 7]; + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(12) +case 0x8279: +case 0x8479: +case 0x8679: +case 0x8879: +case 0x8A79: +case 0x8C79: +case 0x8E79: + +// ORaD +case 0x8079: +{ + u32 adr; + u32 res; + pointer src; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_WORD_F(adr, src) + res = (u16)CPU->D[(Opcode >> 9) & 7]; + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(16) +case 0x827A: +case 0x847A: +case 0x867A: +case 0x887A: +case 0x8A7A: +case 0x8C7A: +case 0x8E7A: + +// ORaD +case 0x807A: +{ + u32 adr; + u32 res; + pointer src; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, src) + res = (u16)CPU->D[(Opcode >> 9) & 7]; + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(12) +case 0x827B: +case 0x847B: +case 0x867B: +case 0x887B: +case 0x8A7B: +case 0x8C7B: +case 0x8E7B: + +// ORaD +case 0x807B: +{ + u32 adr; + u32 res; + pointer src; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, src) + res = (u16)CPU->D[(Opcode >> 9) & 7]; + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(14) +case 0x827C: +case 0x847C: +case 0x867C: +case 0x887C: +case 0x8A7C: +case 0x8C7C: +case 0x8E7C: + +// ORaD +case 0x807C: +{ + u32 res; + pointer src; + src = FETCH_WORD; + PC += 2; + res = (u16)CPU->D[(Opcode >> 9) & 7]; + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; +} +RET(8) +case 0x825F: +case 0x845F: +case 0x865F: +case 0x885F: +case 0x8A5F: +case 0x8C5F: +case 0x8E5F: + +// ORaD +case 0x805F: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_WORD_F(adr, src) + res = (u16)CPU->D[(Opcode >> 9) & 7]; + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(8) +case 0x8267: +case 0x8467: +case 0x8667: +case 0x8867: +case 0x8A67: +case 0x8C67: +case 0x8E67: + +// ORaD +case 0x8067: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_WORD_F(adr, src) + res = (u16)CPU->D[(Opcode >> 9) & 7]; + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(10) +case 0x8280: +case 0x8480: +case 0x8680: +case 0x8880: +case 0x8A80: +case 0x8C80: +case 0x8E80: +case 0x8081: +case 0x8281: +case 0x8481: +case 0x8681: +case 0x8881: +case 0x8A81: +case 0x8C81: +case 0x8E81: +case 0x8082: +case 0x8282: +case 0x8482: +case 0x8682: +case 0x8882: +case 0x8A82: +case 0x8C82: +case 0x8E82: +case 0x8083: +case 0x8283: +case 0x8483: +case 0x8683: +case 0x8883: +case 0x8A83: +case 0x8C83: +case 0x8E83: +case 0x8084: +case 0x8284: +case 0x8484: +case 0x8684: +case 0x8884: +case 0x8A84: +case 0x8C84: +case 0x8E84: +case 0x8085: +case 0x8285: +case 0x8485: +case 0x8685: +case 0x8885: +case 0x8A85: +case 0x8C85: +case 0x8E85: +case 0x8086: +case 0x8286: +case 0x8486: +case 0x8686: +case 0x8886: +case 0x8A86: +case 0x8C86: +case 0x8E86: +case 0x8087: +case 0x8287: +case 0x8487: +case 0x8687: +case 0x8887: +case 0x8A87: +case 0x8C87: +case 0x8E87: + +// ORaD +case 0x8080: +{ + u32 res; + pointer src; + src = (u32)CPU->D[(Opcode >> 0) & 7]; + res = (u32)CPU->D[(Opcode >> 9) & 7]; + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; +} +RET(6) +case 0x8290: +case 0x8490: +case 0x8690: +case 0x8890: +case 0x8A90: +case 0x8C90: +case 0x8E90: +case 0x8091: +case 0x8291: +case 0x8491: +case 0x8691: +case 0x8891: +case 0x8A91: +case 0x8C91: +case 0x8E91: +case 0x8092: +case 0x8292: +case 0x8492: +case 0x8692: +case 0x8892: +case 0x8A92: +case 0x8C92: +case 0x8E92: +case 0x8093: +case 0x8293: +case 0x8493: +case 0x8693: +case 0x8893: +case 0x8A93: +case 0x8C93: +case 0x8E93: +case 0x8094: +case 0x8294: +case 0x8494: +case 0x8694: +case 0x8894: +case 0x8A94: +case 0x8C94: +case 0x8E94: +case 0x8095: +case 0x8295: +case 0x8495: +case 0x8695: +case 0x8895: +case 0x8A95: +case 0x8C95: +case 0x8E95: +case 0x8096: +case 0x8296: +case 0x8496: +case 0x8696: +case 0x8896: +case 0x8A96: +case 0x8C96: +case 0x8E96: +case 0x8097: +case 0x8297: +case 0x8497: +case 0x8697: +case 0x8897: +case 0x8A97: +case 0x8C97: +case 0x8E97: + +// ORaD +case 0x8090: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_LONG_F(adr, src) + res = (u32)CPU->D[(Opcode >> 9) & 7]; + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(16) +case 0x8298: +case 0x8498: +case 0x8698: +case 0x8898: +case 0x8A98: +case 0x8C98: +case 0x8E98: +case 0x8099: +case 0x8299: +case 0x8499: +case 0x8699: +case 0x8899: +case 0x8A99: +case 0x8C99: +case 0x8E99: +case 0x809A: +case 0x829A: +case 0x849A: +case 0x869A: +case 0x889A: +case 0x8A9A: +case 0x8C9A: +case 0x8E9A: +case 0x809B: +case 0x829B: +case 0x849B: +case 0x869B: +case 0x889B: +case 0x8A9B: +case 0x8C9B: +case 0x8E9B: +case 0x809C: +case 0x829C: +case 0x849C: +case 0x869C: +case 0x889C: +case 0x8A9C: +case 0x8C9C: +case 0x8E9C: +case 0x809D: +case 0x829D: +case 0x849D: +case 0x869D: +case 0x889D: +case 0x8A9D: +case 0x8C9D: +case 0x8E9D: +case 0x809E: +case 0x829E: +case 0x849E: +case 0x869E: +case 0x889E: +case 0x8A9E: +case 0x8C9E: +case 0x8E9E: + +// ORaD +case 0x8098: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 4; + PRE_IO + READ_LONG_F(adr, src) + res = (u32)CPU->D[(Opcode >> 9) & 7]; + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(16) +case 0x82A0: +case 0x84A0: +case 0x86A0: +case 0x88A0: +case 0x8AA0: +case 0x8CA0: +case 0x8EA0: +case 0x80A1: +case 0x82A1: +case 0x84A1: +case 0x86A1: +case 0x88A1: +case 0x8AA1: +case 0x8CA1: +case 0x8EA1: +case 0x80A2: +case 0x82A2: +case 0x84A2: +case 0x86A2: +case 0x88A2: +case 0x8AA2: +case 0x8CA2: +case 0x8EA2: +case 0x80A3: +case 0x82A3: +case 0x84A3: +case 0x86A3: +case 0x88A3: +case 0x8AA3: +case 0x8CA3: +case 0x8EA3: +case 0x80A4: +case 0x82A4: +case 0x84A4: +case 0x86A4: +case 0x88A4: +case 0x8AA4: +case 0x8CA4: +case 0x8EA4: +case 0x80A5: +case 0x82A5: +case 0x84A5: +case 0x86A5: +case 0x88A5: +case 0x8AA5: +case 0x8CA5: +case 0x8EA5: +case 0x80A6: +case 0x82A6: +case 0x84A6: +case 0x86A6: +case 0x88A6: +case 0x8AA6: +case 0x8CA6: +case 0x8EA6: + +// ORaD +case 0x80A0: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 4; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_LONG_F(adr, src) + res = (u32)CPU->D[(Opcode >> 9) & 7]; + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(18) +case 0x82A8: +case 0x84A8: +case 0x86A8: +case 0x88A8: +case 0x8AA8: +case 0x8CA8: +case 0x8EA8: +case 0x80A9: +case 0x82A9: +case 0x84A9: +case 0x86A9: +case 0x88A9: +case 0x8AA9: +case 0x8CA9: +case 0x8EA9: +case 0x80AA: +case 0x82AA: +case 0x84AA: +case 0x86AA: +case 0x88AA: +case 0x8AAA: +case 0x8CAA: +case 0x8EAA: +case 0x80AB: +case 0x82AB: +case 0x84AB: +case 0x86AB: +case 0x88AB: +case 0x8AAB: +case 0x8CAB: +case 0x8EAB: +case 0x80AC: +case 0x82AC: +case 0x84AC: +case 0x86AC: +case 0x88AC: +case 0x8AAC: +case 0x8CAC: +case 0x8EAC: +case 0x80AD: +case 0x82AD: +case 0x84AD: +case 0x86AD: +case 0x88AD: +case 0x8AAD: +case 0x8CAD: +case 0x8EAD: +case 0x80AE: +case 0x82AE: +case 0x84AE: +case 0x86AE: +case 0x88AE: +case 0x8AAE: +case 0x8CAE: +case 0x8EAE: +case 0x80AF: +case 0x82AF: +case 0x84AF: +case 0x86AF: +case 0x88AF: +case 0x8AAF: +case 0x8CAF: +case 0x8EAF: + +// ORaD +case 0x80A8: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, src) + res = (u32)CPU->D[(Opcode >> 9) & 7]; + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(20) +case 0x82B0: +case 0x84B0: +case 0x86B0: +case 0x88B0: +case 0x8AB0: +case 0x8CB0: +case 0x8EB0: +case 0x80B1: +case 0x82B1: +case 0x84B1: +case 0x86B1: +case 0x88B1: +case 0x8AB1: +case 0x8CB1: +case 0x8EB1: +case 0x80B2: +case 0x82B2: +case 0x84B2: +case 0x86B2: +case 0x88B2: +case 0x8AB2: +case 0x8CB2: +case 0x8EB2: +case 0x80B3: +case 0x82B3: +case 0x84B3: +case 0x86B3: +case 0x88B3: +case 0x8AB3: +case 0x8CB3: +case 0x8EB3: +case 0x80B4: +case 0x82B4: +case 0x84B4: +case 0x86B4: +case 0x88B4: +case 0x8AB4: +case 0x8CB4: +case 0x8EB4: +case 0x80B5: +case 0x82B5: +case 0x84B5: +case 0x86B5: +case 0x88B5: +case 0x8AB5: +case 0x8CB5: +case 0x8EB5: +case 0x80B6: +case 0x82B6: +case 0x84B6: +case 0x86B6: +case 0x88B6: +case 0x8AB6: +case 0x8CB6: +case 0x8EB6: +case 0x80B7: +case 0x82B7: +case 0x84B7: +case 0x86B7: +case 0x88B7: +case 0x8AB7: +case 0x8CB7: +case 0x8EB7: + +// ORaD +case 0x80B0: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_LONG_F(adr, src) + res = (u32)CPU->D[(Opcode >> 9) & 7]; + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(22) +case 0x82B8: +case 0x84B8: +case 0x86B8: +case 0x88B8: +case 0x8AB8: +case 0x8CB8: +case 0x8EB8: + +// ORaD +case 0x80B8: +{ + u32 adr; + u32 res; + pointer src; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, src) + res = (u32)CPU->D[(Opcode >> 9) & 7]; + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(20) +case 0x82B9: +case 0x84B9: +case 0x86B9: +case 0x88B9: +case 0x8AB9: +case 0x8CB9: +case 0x8EB9: + +// ORaD +case 0x80B9: +{ + u32 adr; + u32 res; + pointer src; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_LONG_F(adr, src) + res = (u32)CPU->D[(Opcode >> 9) & 7]; + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(24) +case 0x82BA: +case 0x84BA: +case 0x86BA: +case 0x88BA: +case 0x8ABA: +case 0x8CBA: +case 0x8EBA: + +// ORaD +case 0x80BA: +{ + u32 adr; + u32 res; + pointer src; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, src) + res = (u32)CPU->D[(Opcode >> 9) & 7]; + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(20) +case 0x82BB: +case 0x84BB: +case 0x86BB: +case 0x88BB: +case 0x8ABB: +case 0x8CBB: +case 0x8EBB: + +// ORaD +case 0x80BB: +{ + u32 adr; + u32 res; + pointer src; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READ_LONG_F(adr, src) + res = (u32)CPU->D[(Opcode >> 9) & 7]; + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(22) +case 0x82BC: +case 0x84BC: +case 0x86BC: +case 0x88BC: +case 0x8ABC: +case 0x8CBC: +case 0x8EBC: + +// ORaD +case 0x80BC: +{ + u32 res; + pointer src; + src = FETCH_LONG; + PC += 4; + res = (u32)CPU->D[(Opcode >> 9) & 7]; + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; +} +RET(14) +case 0x829F: +case 0x849F: +case 0x869F: +case 0x889F: +case 0x8A9F: +case 0x8C9F: +case 0x8E9F: + +// ORaD +case 0x809F: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[7]; + CPU->A[7] += 4; + PRE_IO + READ_LONG_F(adr, src) + res = (u32)CPU->D[(Opcode >> 9) & 7]; + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(16) +case 0x82A7: +case 0x84A7: +case 0x86A7: +case 0x88A7: +case 0x8AA7: +case 0x8CA7: +case 0x8EA7: + +// ORaD +case 0x80A7: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + PRE_IO + READ_LONG_F(adr, src) + res = (u32)CPU->D[(Opcode >> 9) & 7]; + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(18) +case 0x8310: +case 0x8510: +case 0x8710: +case 0x8910: +case 0x8B10: +case 0x8D10: +case 0x8F10: +case 0x8111: +case 0x8311: +case 0x8511: +case 0x8711: +case 0x8911: +case 0x8B11: +case 0x8D11: +case 0x8F11: +case 0x8112: +case 0x8312: +case 0x8512: +case 0x8712: +case 0x8912: +case 0x8B12: +case 0x8D12: +case 0x8F12: +case 0x8113: +case 0x8313: +case 0x8513: +case 0x8713: +case 0x8913: +case 0x8B13: +case 0x8D13: +case 0x8F13: +case 0x8114: +case 0x8314: +case 0x8514: +case 0x8714: +case 0x8914: +case 0x8B14: +case 0x8D14: +case 0x8F14: +case 0x8115: +case 0x8315: +case 0x8515: +case 0x8715: +case 0x8915: +case 0x8B15: +case 0x8D15: +case 0x8F15: +case 0x8116: +case 0x8316: +case 0x8516: +case 0x8716: +case 0x8916: +case 0x8B16: +case 0x8D16: +case 0x8F16: +case 0x8117: +case 0x8317: +case 0x8517: +case 0x8717: +case 0x8917: +case 0x8B17: +case 0x8D17: +case 0x8F17: + +// ORDa +case 0x8110: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_BYTE_F(adr, res) + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0x8318: +case 0x8518: +case 0x8718: +case 0x8918: +case 0x8B18: +case 0x8D18: +case 0x8F18: +case 0x8119: +case 0x8319: +case 0x8519: +case 0x8719: +case 0x8919: +case 0x8B19: +case 0x8D19: +case 0x8F19: +case 0x811A: +case 0x831A: +case 0x851A: +case 0x871A: +case 0x891A: +case 0x8B1A: +case 0x8D1A: +case 0x8F1A: +case 0x811B: +case 0x831B: +case 0x851B: +case 0x871B: +case 0x891B: +case 0x8B1B: +case 0x8D1B: +case 0x8F1B: +case 0x811C: +case 0x831C: +case 0x851C: +case 0x871C: +case 0x891C: +case 0x8B1C: +case 0x8D1C: +case 0x8F1C: +case 0x811D: +case 0x831D: +case 0x851D: +case 0x871D: +case 0x891D: +case 0x8B1D: +case 0x8D1D: +case 0x8F1D: +case 0x811E: +case 0x831E: +case 0x851E: +case 0x871E: +case 0x891E: +case 0x8B1E: +case 0x8D1E: +case 0x8F1E: + +// ORDa +case 0x8118: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + PRE_IO + READ_BYTE_F(adr, res) + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0x8320: +case 0x8520: +case 0x8720: +case 0x8920: +case 0x8B20: +case 0x8D20: +case 0x8F20: +case 0x8121: +case 0x8321: +case 0x8521: +case 0x8721: +case 0x8921: +case 0x8B21: +case 0x8D21: +case 0x8F21: +case 0x8122: +case 0x8322: +case 0x8522: +case 0x8722: +case 0x8922: +case 0x8B22: +case 0x8D22: +case 0x8F22: +case 0x8123: +case 0x8323: +case 0x8523: +case 0x8723: +case 0x8923: +case 0x8B23: +case 0x8D23: +case 0x8F23: +case 0x8124: +case 0x8324: +case 0x8524: +case 0x8724: +case 0x8924: +case 0x8B24: +case 0x8D24: +case 0x8F24: +case 0x8125: +case 0x8325: +case 0x8525: +case 0x8725: +case 0x8925: +case 0x8B25: +case 0x8D25: +case 0x8F25: +case 0x8126: +case 0x8326: +case 0x8526: +case 0x8726: +case 0x8926: +case 0x8B26: +case 0x8D26: +case 0x8F26: + +// ORDa +case 0x8120: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_BYTE_F(adr, res) + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(14) +case 0x8328: +case 0x8528: +case 0x8728: +case 0x8928: +case 0x8B28: +case 0x8D28: +case 0x8F28: +case 0x8129: +case 0x8329: +case 0x8529: +case 0x8729: +case 0x8929: +case 0x8B29: +case 0x8D29: +case 0x8F29: +case 0x812A: +case 0x832A: +case 0x852A: +case 0x872A: +case 0x892A: +case 0x8B2A: +case 0x8D2A: +case 0x8F2A: +case 0x812B: +case 0x832B: +case 0x852B: +case 0x872B: +case 0x892B: +case 0x8B2B: +case 0x8D2B: +case 0x8F2B: +case 0x812C: +case 0x832C: +case 0x852C: +case 0x872C: +case 0x892C: +case 0x8B2C: +case 0x8D2C: +case 0x8F2C: +case 0x812D: +case 0x832D: +case 0x852D: +case 0x872D: +case 0x892D: +case 0x8B2D: +case 0x8D2D: +case 0x8F2D: +case 0x812E: +case 0x832E: +case 0x852E: +case 0x872E: +case 0x892E: +case 0x8B2E: +case 0x8D2E: +case 0x8F2E: +case 0x812F: +case 0x832F: +case 0x852F: +case 0x872F: +case 0x892F: +case 0x8B2F: +case 0x8D2F: +case 0x8F2F: + +// ORDa +case 0x8128: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0x8330: +case 0x8530: +case 0x8730: +case 0x8930: +case 0x8B30: +case 0x8D30: +case 0x8F30: +case 0x8131: +case 0x8331: +case 0x8531: +case 0x8731: +case 0x8931: +case 0x8B31: +case 0x8D31: +case 0x8F31: +case 0x8132: +case 0x8332: +case 0x8532: +case 0x8732: +case 0x8932: +case 0x8B32: +case 0x8D32: +case 0x8F32: +case 0x8133: +case 0x8333: +case 0x8533: +case 0x8733: +case 0x8933: +case 0x8B33: +case 0x8D33: +case 0x8F33: +case 0x8134: +case 0x8334: +case 0x8534: +case 0x8734: +case 0x8934: +case 0x8B34: +case 0x8D34: +case 0x8F34: +case 0x8135: +case 0x8335: +case 0x8535: +case 0x8735: +case 0x8935: +case 0x8B35: +case 0x8D35: +case 0x8F35: +case 0x8136: +case 0x8336: +case 0x8536: +case 0x8736: +case 0x8936: +case 0x8B36: +case 0x8D36: +case 0x8F36: +case 0x8137: +case 0x8337: +case 0x8537: +case 0x8737: +case 0x8937: +case 0x8B37: +case 0x8D37: +case 0x8F37: + +// ORDa +case 0x8130: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, res) + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) +case 0x8338: +case 0x8538: +case 0x8738: +case 0x8938: +case 0x8B38: +case 0x8D38: +case 0x8F38: + +// ORDa +case 0x8138: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0x8339: +case 0x8539: +case 0x8739: +case 0x8939: +case 0x8B39: +case 0x8D39: +case 0x8F39: + +// ORDa +case 0x8139: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_BYTE_F(adr, res) + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(20) +case 0x831F: +case 0x851F: +case 0x871F: +case 0x891F: +case 0x8B1F: +case 0x8D1F: +case 0x8F1F: + +// ORDa +case 0x811F: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_BYTE_F(adr, res) + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0x8327: +case 0x8527: +case 0x8727: +case 0x8927: +case 0x8B27: +case 0x8D27: +case 0x8F27: + +// ORDa +case 0x8127: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_BYTE_F(adr, res) + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(14) +case 0x8350: +case 0x8550: +case 0x8750: +case 0x8950: +case 0x8B50: +case 0x8D50: +case 0x8F50: +case 0x8151: +case 0x8351: +case 0x8551: +case 0x8751: +case 0x8951: +case 0x8B51: +case 0x8D51: +case 0x8F51: +case 0x8152: +case 0x8352: +case 0x8552: +case 0x8752: +case 0x8952: +case 0x8B52: +case 0x8D52: +case 0x8F52: +case 0x8153: +case 0x8353: +case 0x8553: +case 0x8753: +case 0x8953: +case 0x8B53: +case 0x8D53: +case 0x8F53: +case 0x8154: +case 0x8354: +case 0x8554: +case 0x8754: +case 0x8954: +case 0x8B54: +case 0x8D54: +case 0x8F54: +case 0x8155: +case 0x8355: +case 0x8555: +case 0x8755: +case 0x8955: +case 0x8B55: +case 0x8D55: +case 0x8F55: +case 0x8156: +case 0x8356: +case 0x8556: +case 0x8756: +case 0x8956: +case 0x8B56: +case 0x8D56: +case 0x8F56: +case 0x8157: +case 0x8357: +case 0x8557: +case 0x8757: +case 0x8957: +case 0x8B57: +case 0x8D57: +case 0x8F57: + +// ORDa +case 0x8150: +{ + u32 adr; + u32 res; + pointer src; + src = (u16)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_WORD_F(adr, res) + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0x8358: +case 0x8558: +case 0x8758: +case 0x8958: +case 0x8B58: +case 0x8D58: +case 0x8F58: +case 0x8159: +case 0x8359: +case 0x8559: +case 0x8759: +case 0x8959: +case 0x8B59: +case 0x8D59: +case 0x8F59: +case 0x815A: +case 0x835A: +case 0x855A: +case 0x875A: +case 0x895A: +case 0x8B5A: +case 0x8D5A: +case 0x8F5A: +case 0x815B: +case 0x835B: +case 0x855B: +case 0x875B: +case 0x895B: +case 0x8B5B: +case 0x8D5B: +case 0x8F5B: +case 0x815C: +case 0x835C: +case 0x855C: +case 0x875C: +case 0x895C: +case 0x8B5C: +case 0x8D5C: +case 0x8F5C: +case 0x815D: +case 0x835D: +case 0x855D: +case 0x875D: +case 0x895D: +case 0x8B5D: +case 0x8D5D: +case 0x8F5D: +case 0x815E: +case 0x835E: +case 0x855E: +case 0x875E: +case 0x895E: +case 0x8B5E: +case 0x8D5E: +case 0x8F5E: + +// ORDa +case 0x8158: +{ + u32 adr; + u32 res; + pointer src; + src = (u16)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 2; + PRE_IO + READ_WORD_F(adr, res) + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0x8360: +case 0x8560: +case 0x8760: +case 0x8960: +case 0x8B60: +case 0x8D60: +case 0x8F60: +case 0x8161: +case 0x8361: +case 0x8561: +case 0x8761: +case 0x8961: +case 0x8B61: +case 0x8D61: +case 0x8F61: +case 0x8162: +case 0x8362: +case 0x8562: +case 0x8762: +case 0x8962: +case 0x8B62: +case 0x8D62: +case 0x8F62: +case 0x8163: +case 0x8363: +case 0x8563: +case 0x8763: +case 0x8963: +case 0x8B63: +case 0x8D63: +case 0x8F63: +case 0x8164: +case 0x8364: +case 0x8564: +case 0x8764: +case 0x8964: +case 0x8B64: +case 0x8D64: +case 0x8F64: +case 0x8165: +case 0x8365: +case 0x8565: +case 0x8765: +case 0x8965: +case 0x8B65: +case 0x8D65: +case 0x8F65: +case 0x8166: +case 0x8366: +case 0x8566: +case 0x8766: +case 0x8966: +case 0x8B66: +case 0x8D66: +case 0x8F66: + +// ORDa +case 0x8160: +{ + u32 adr; + u32 res; + pointer src; + src = (u16)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7] - 2; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_WORD_F(adr, res) + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(14) +case 0x8368: +case 0x8568: +case 0x8768: +case 0x8968: +case 0x8B68: +case 0x8D68: +case 0x8F68: +case 0x8169: +case 0x8369: +case 0x8569: +case 0x8769: +case 0x8969: +case 0x8B69: +case 0x8D69: +case 0x8F69: +case 0x816A: +case 0x836A: +case 0x856A: +case 0x876A: +case 0x896A: +case 0x8B6A: +case 0x8D6A: +case 0x8F6A: +case 0x816B: +case 0x836B: +case 0x856B: +case 0x876B: +case 0x896B: +case 0x8B6B: +case 0x8D6B: +case 0x8F6B: +case 0x816C: +case 0x836C: +case 0x856C: +case 0x876C: +case 0x896C: +case 0x8B6C: +case 0x8D6C: +case 0x8F6C: +case 0x816D: +case 0x836D: +case 0x856D: +case 0x876D: +case 0x896D: +case 0x8B6D: +case 0x8D6D: +case 0x8F6D: +case 0x816E: +case 0x836E: +case 0x856E: +case 0x876E: +case 0x896E: +case 0x8B6E: +case 0x8D6E: +case 0x8F6E: +case 0x816F: +case 0x836F: +case 0x856F: +case 0x876F: +case 0x896F: +case 0x8B6F: +case 0x8D6F: +case 0x8F6F: + +// ORDa +case 0x8168: +{ + u32 adr; + u32 res; + pointer src; + src = (u16)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, res) + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0x8370: +case 0x8570: +case 0x8770: +case 0x8970: +case 0x8B70: +case 0x8D70: +case 0x8F70: +case 0x8171: +case 0x8371: +case 0x8571: +case 0x8771: +case 0x8971: +case 0x8B71: +case 0x8D71: +case 0x8F71: +case 0x8172: +case 0x8372: +case 0x8572: +case 0x8772: +case 0x8972: +case 0x8B72: +case 0x8D72: +case 0x8F72: +case 0x8173: +case 0x8373: +case 0x8573: +case 0x8773: +case 0x8973: +case 0x8B73: +case 0x8D73: +case 0x8F73: +case 0x8174: +case 0x8374: +case 0x8574: +case 0x8774: +case 0x8974: +case 0x8B74: +case 0x8D74: +case 0x8F74: +case 0x8175: +case 0x8375: +case 0x8575: +case 0x8775: +case 0x8975: +case 0x8B75: +case 0x8D75: +case 0x8F75: +case 0x8176: +case 0x8376: +case 0x8576: +case 0x8776: +case 0x8976: +case 0x8B76: +case 0x8D76: +case 0x8F76: +case 0x8177: +case 0x8377: +case 0x8577: +case 0x8777: +case 0x8977: +case 0x8B77: +case 0x8D77: +case 0x8F77: + +// ORDa +case 0x8170: +{ + u32 adr; + u32 res; + pointer src; + src = (u16)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, res) + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(18) +case 0x8378: +case 0x8578: +case 0x8778: +case 0x8978: +case 0x8B78: +case 0x8D78: +case 0x8F78: + +// ORDa +case 0x8178: +{ + u32 adr; + u32 res; + pointer src; + src = (u16)CPU->D[(Opcode >> 9) & 7]; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, res) + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0x8379: +case 0x8579: +case 0x8779: +case 0x8979: +case 0x8B79: +case 0x8D79: +case 0x8F79: + +// ORDa +case 0x8179: +{ + u32 adr; + u32 res; + pointer src; + src = (u16)CPU->D[(Opcode >> 9) & 7]; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_WORD_F(adr, res) + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(20) +case 0x835F: +case 0x855F: +case 0x875F: +case 0x895F: +case 0x8B5F: +case 0x8D5F: +case 0x8F5F: + +// ORDa +case 0x815F: +{ + u32 adr; + u32 res; + pointer src; + src = (u16)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_WORD_F(adr, res) + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0x8367: +case 0x8567: +case 0x8767: +case 0x8967: +case 0x8B67: +case 0x8D67: +case 0x8F67: + +// ORDa +case 0x8167: +{ + u32 adr; + u32 res; + pointer src; + src = (u16)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_WORD_F(adr, res) + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(14) +case 0x8390: +case 0x8590: +case 0x8790: +case 0x8990: +case 0x8B90: +case 0x8D90: +case 0x8F90: +case 0x8191: +case 0x8391: +case 0x8591: +case 0x8791: +case 0x8991: +case 0x8B91: +case 0x8D91: +case 0x8F91: +case 0x8192: +case 0x8392: +case 0x8592: +case 0x8792: +case 0x8992: +case 0x8B92: +case 0x8D92: +case 0x8F92: +case 0x8193: +case 0x8393: +case 0x8593: +case 0x8793: +case 0x8993: +case 0x8B93: +case 0x8D93: +case 0x8F93: +case 0x8194: +case 0x8394: +case 0x8594: +case 0x8794: +case 0x8994: +case 0x8B94: +case 0x8D94: +case 0x8F94: +case 0x8195: +case 0x8395: +case 0x8595: +case 0x8795: +case 0x8995: +case 0x8B95: +case 0x8D95: +case 0x8F95: +case 0x8196: +case 0x8396: +case 0x8596: +case 0x8796: +case 0x8996: +case 0x8B96: +case 0x8D96: +case 0x8F96: +case 0x8197: +case 0x8397: +case 0x8597: +case 0x8797: +case 0x8997: +case 0x8B97: +case 0x8D97: +case 0x8F97: + +// ORDa +case 0x8190: +{ + u32 adr; + u32 res; + pointer src; + src = (u32)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_LONG_F(adr, res) + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(20) +case 0x8398: +case 0x8598: +case 0x8798: +case 0x8998: +case 0x8B98: +case 0x8D98: +case 0x8F98: +case 0x8199: +case 0x8399: +case 0x8599: +case 0x8799: +case 0x8999: +case 0x8B99: +case 0x8D99: +case 0x8F99: +case 0x819A: +case 0x839A: +case 0x859A: +case 0x879A: +case 0x899A: +case 0x8B9A: +case 0x8D9A: +case 0x8F9A: +case 0x819B: +case 0x839B: +case 0x859B: +case 0x879B: +case 0x899B: +case 0x8B9B: +case 0x8D9B: +case 0x8F9B: +case 0x819C: +case 0x839C: +case 0x859C: +case 0x879C: +case 0x899C: +case 0x8B9C: +case 0x8D9C: +case 0x8F9C: +case 0x819D: +case 0x839D: +case 0x859D: +case 0x879D: +case 0x899D: +case 0x8B9D: +case 0x8D9D: +case 0x8F9D: +case 0x819E: +case 0x839E: +case 0x859E: +case 0x879E: +case 0x899E: +case 0x8B9E: +case 0x8D9E: +case 0x8F9E: + +// ORDa +case 0x8198: +{ + u32 adr; + u32 res; + pointer src; + src = (u32)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 4; + PRE_IO + READ_LONG_F(adr, res) + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(20) +case 0x83A0: +case 0x85A0: +case 0x87A0: +case 0x89A0: +case 0x8BA0: +case 0x8DA0: +case 0x8FA0: +case 0x81A1: +case 0x83A1: +case 0x85A1: +case 0x87A1: +case 0x89A1: +case 0x8BA1: +case 0x8DA1: +case 0x8FA1: +case 0x81A2: +case 0x83A2: +case 0x85A2: +case 0x87A2: +case 0x89A2: +case 0x8BA2: +case 0x8DA2: +case 0x8FA2: +case 0x81A3: +case 0x83A3: +case 0x85A3: +case 0x87A3: +case 0x89A3: +case 0x8BA3: +case 0x8DA3: +case 0x8FA3: +case 0x81A4: +case 0x83A4: +case 0x85A4: +case 0x87A4: +case 0x89A4: +case 0x8BA4: +case 0x8DA4: +case 0x8FA4: +case 0x81A5: +case 0x83A5: +case 0x85A5: +case 0x87A5: +case 0x89A5: +case 0x8BA5: +case 0x8DA5: +case 0x8FA5: +case 0x81A6: +case 0x83A6: +case 0x85A6: +case 0x87A6: +case 0x89A6: +case 0x8BA6: +case 0x8DA6: +case 0x8FA6: + +// ORDa +case 0x81A0: +{ + u32 adr; + u32 res; + pointer src; + src = (u32)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7] - 4; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_LONG_F(adr, res) + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(22) +case 0x83A8: +case 0x85A8: +case 0x87A8: +case 0x89A8: +case 0x8BA8: +case 0x8DA8: +case 0x8FA8: +case 0x81A9: +case 0x83A9: +case 0x85A9: +case 0x87A9: +case 0x89A9: +case 0x8BA9: +case 0x8DA9: +case 0x8FA9: +case 0x81AA: +case 0x83AA: +case 0x85AA: +case 0x87AA: +case 0x89AA: +case 0x8BAA: +case 0x8DAA: +case 0x8FAA: +case 0x81AB: +case 0x83AB: +case 0x85AB: +case 0x87AB: +case 0x89AB: +case 0x8BAB: +case 0x8DAB: +case 0x8FAB: +case 0x81AC: +case 0x83AC: +case 0x85AC: +case 0x87AC: +case 0x89AC: +case 0x8BAC: +case 0x8DAC: +case 0x8FAC: +case 0x81AD: +case 0x83AD: +case 0x85AD: +case 0x87AD: +case 0x89AD: +case 0x8BAD: +case 0x8DAD: +case 0x8FAD: +case 0x81AE: +case 0x83AE: +case 0x85AE: +case 0x87AE: +case 0x89AE: +case 0x8BAE: +case 0x8DAE: +case 0x8FAE: +case 0x81AF: +case 0x83AF: +case 0x85AF: +case 0x87AF: +case 0x89AF: +case 0x8BAF: +case 0x8DAF: +case 0x8FAF: + +// ORDa +case 0x81A8: +{ + u32 adr; + u32 res; + pointer src; + src = (u32)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, res) + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(24) +case 0x83B0: +case 0x85B0: +case 0x87B0: +case 0x89B0: +case 0x8BB0: +case 0x8DB0: +case 0x8FB0: +case 0x81B1: +case 0x83B1: +case 0x85B1: +case 0x87B1: +case 0x89B1: +case 0x8BB1: +case 0x8DB1: +case 0x8FB1: +case 0x81B2: +case 0x83B2: +case 0x85B2: +case 0x87B2: +case 0x89B2: +case 0x8BB2: +case 0x8DB2: +case 0x8FB2: +case 0x81B3: +case 0x83B3: +case 0x85B3: +case 0x87B3: +case 0x89B3: +case 0x8BB3: +case 0x8DB3: +case 0x8FB3: +case 0x81B4: +case 0x83B4: +case 0x85B4: +case 0x87B4: +case 0x89B4: +case 0x8BB4: +case 0x8DB4: +case 0x8FB4: +case 0x81B5: +case 0x83B5: +case 0x85B5: +case 0x87B5: +case 0x89B5: +case 0x8BB5: +case 0x8DB5: +case 0x8FB5: +case 0x81B6: +case 0x83B6: +case 0x85B6: +case 0x87B6: +case 0x89B6: +case 0x8BB6: +case 0x8DB6: +case 0x8FB6: +case 0x81B7: +case 0x83B7: +case 0x85B7: +case 0x87B7: +case 0x89B7: +case 0x8BB7: +case 0x8DB7: +case 0x8FB7: + +// ORDa +case 0x81B0: +{ + u32 adr; + u32 res; + pointer src; + src = (u32)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_LONG_F(adr, res) + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(26) +case 0x83B8: +case 0x85B8: +case 0x87B8: +case 0x89B8: +case 0x8BB8: +case 0x8DB8: +case 0x8FB8: + +// ORDa +case 0x81B8: +{ + u32 adr; + u32 res; + pointer src; + src = (u32)CPU->D[(Opcode >> 9) & 7]; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, res) + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(24) +case 0x83B9: +case 0x85B9: +case 0x87B9: +case 0x89B9: +case 0x8BB9: +case 0x8DB9: +case 0x8FB9: + +// ORDa +case 0x81B9: +{ + u32 adr; + u32 res; + pointer src; + src = (u32)CPU->D[(Opcode >> 9) & 7]; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_LONG_F(adr, res) + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(28) +case 0x839F: +case 0x859F: +case 0x879F: +case 0x899F: +case 0x8B9F: +case 0x8D9F: +case 0x8F9F: + +// ORDa +case 0x819F: +{ + u32 adr; + u32 res; + pointer src; + src = (u32)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[7]; + CPU->A[7] += 4; + PRE_IO + READ_LONG_F(adr, res) + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(20) +case 0x83A7: +case 0x85A7: +case 0x87A7: +case 0x89A7: +case 0x8BA7: +case 0x8DA7: +case 0x8FA7: + +// ORDa +case 0x81A7: +{ + u32 adr; + u32 res; + pointer src; + src = (u32)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + PRE_IO + READ_LONG_F(adr, res) + res |= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(22) +case 0x8300: +case 0x8500: +case 0x8700: +case 0x8900: +case 0x8B00: +case 0x8D00: +case 0x8F00: +case 0x8101: +case 0x8301: +case 0x8501: +case 0x8701: +case 0x8901: +case 0x8B01: +case 0x8D01: +case 0x8F01: +case 0x8102: +case 0x8302: +case 0x8502: +case 0x8702: +case 0x8902: +case 0x8B02: +case 0x8D02: +case 0x8F02: +case 0x8103: +case 0x8303: +case 0x8503: +case 0x8703: +case 0x8903: +case 0x8B03: +case 0x8D03: +case 0x8F03: +case 0x8104: +case 0x8304: +case 0x8504: +case 0x8704: +case 0x8904: +case 0x8B04: +case 0x8D04: +case 0x8F04: +case 0x8105: +case 0x8305: +case 0x8505: +case 0x8705: +case 0x8905: +case 0x8B05: +case 0x8D05: +case 0x8F05: +case 0x8106: +case 0x8306: +case 0x8506: +case 0x8706: +case 0x8906: +case 0x8B06: +case 0x8D06: +case 0x8F06: +case 0x8107: +case 0x8307: +case 0x8507: +case 0x8707: +case 0x8907: +case 0x8B07: +case 0x8D07: +case 0x8F07: + +// SBCD +case 0x8100: +{ + u32 res; + pointer dst; + pointer src; + src = (u8)CPU->D[(Opcode >> 0) & 7]; + dst = (u8)CPU->D[(Opcode >> 9) & 7]; + res = (dst & 0xF) - (src & 0xF) - ((CPU->flag_X >> C68K_SR_X_SFT) & 1); + if (res > 9) res -= 6; + res += (dst & 0xF0) - (src & 0xF0); + if (res > 0x99) + { + res += 0xA0; + CPU->flag_X = CPU->flag_C = C68K_SR_C; + } + else CPU->flag_X = CPU->flag_C = 0; + CPU->flag_notZ |= res & 0xFF; + CPU->flag_N = res; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; +} +RET(6) +case 0x8308: +case 0x8508: +case 0x8708: +case 0x8908: +case 0x8B08: +case 0x8D08: +case 0x8109: +case 0x8309: +case 0x8509: +case 0x8709: +case 0x8909: +case 0x8B09: +case 0x8D09: +case 0x810A: +case 0x830A: +case 0x850A: +case 0x870A: +case 0x890A: +case 0x8B0A: +case 0x8D0A: +case 0x810B: +case 0x830B: +case 0x850B: +case 0x870B: +case 0x890B: +case 0x8B0B: +case 0x8D0B: +case 0x810C: +case 0x830C: +case 0x850C: +case 0x870C: +case 0x890C: +case 0x8B0C: +case 0x8D0C: +case 0x810D: +case 0x830D: +case 0x850D: +case 0x870D: +case 0x890D: +case 0x8B0D: +case 0x8D0D: +case 0x810E: +case 0x830E: +case 0x850E: +case 0x870E: +case 0x890E: +case 0x8B0E: +case 0x8D0E: + +// SBCDM +case 0x8108: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_BYTE_F(adr, src) + adr = CPU->A[(Opcode >> 9) & 7] - 1; + CPU->A[(Opcode >> 9) & 7] = adr; + READ_BYTE_F(adr, dst) + res = (dst & 0xF) - (src & 0xF) - ((CPU->flag_X >> C68K_SR_X_SFT) & 1); + if (res > 9) res -= 6; + res += (dst & 0xF0) - (src & 0xF0); + if (res > 0x99) + { + res += 0xA0; + CPU->flag_X = CPU->flag_C = C68K_SR_C; + } + else CPU->flag_X = CPU->flag_C = 0; + CPU->flag_notZ |= res & 0xFF; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) +case 0x830F: +case 0x850F: +case 0x870F: +case 0x890F: +case 0x8B0F: +case 0x8D0F: + +// SBCD7M +case 0x810F: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_BYTE_F(adr, src) + adr = CPU->A[(Opcode >> 9) & 7] - 1; + CPU->A[(Opcode >> 9) & 7] = adr; + READ_BYTE_F(adr, dst) + res = (dst & 0xF) - (src & 0xF) - ((CPU->flag_X >> C68K_SR_X_SFT) & 1); + if (res > 9) res -= 6; + res += (dst & 0xF0) - (src & 0xF0); + if (res > 0x99) + { + res += 0xA0; + CPU->flag_X = CPU->flag_C = C68K_SR_C; + } + else CPU->flag_X = CPU->flag_C = 0; + CPU->flag_notZ |= res & 0xFF; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) +case 0x8F09: +case 0x8F0A: +case 0x8F0B: +case 0x8F0C: +case 0x8F0D: +case 0x8F0E: + +// SBCDM7 +case 0x8F08: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_BYTE_F(adr, src) + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + READ_BYTE_F(adr, dst) + res = (dst & 0xF) - (src & 0xF) - ((CPU->flag_X >> C68K_SR_X_SFT) & 1); + if (res > 9) res -= 6; + res += (dst & 0xF0) - (src & 0xF0); + if (res > 0x99) + { + res += 0xA0; + CPU->flag_X = CPU->flag_C = C68K_SR_C; + } + else CPU->flag_X = CPU->flag_C = 0; + CPU->flag_notZ |= res & 0xFF; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) + +// SBCD7M7 +case 0x8F0F: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_BYTE_F(adr, src) + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + READ_BYTE_F(adr, dst) + res = (dst & 0xF) - (src & 0xF) - ((CPU->flag_X >> C68K_SR_X_SFT) & 1); + if (res > 9) res -= 6; + res += (dst & 0xF0) - (src & 0xF0); + if (res > 0x99) + { + res += 0xA0; + CPU->flag_X = CPU->flag_C = C68K_SR_C; + } + else CPU->flag_X = CPU->flag_C = 0; + CPU->flag_notZ |= res & 0xFF; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) +case 0x82C0: +case 0x84C0: +case 0x86C0: +case 0x88C0: +case 0x8AC0: +case 0x8CC0: +case 0x8EC0: +case 0x80C1: +case 0x82C1: +case 0x84C1: +case 0x86C1: +case 0x88C1: +case 0x8AC1: +case 0x8CC1: +case 0x8EC1: +case 0x80C2: +case 0x82C2: +case 0x84C2: +case 0x86C2: +case 0x88C2: +case 0x8AC2: +case 0x8CC2: +case 0x8EC2: +case 0x80C3: +case 0x82C3: +case 0x84C3: +case 0x86C3: +case 0x88C3: +case 0x8AC3: +case 0x8CC3: +case 0x8EC3: +case 0x80C4: +case 0x82C4: +case 0x84C4: +case 0x86C4: +case 0x88C4: +case 0x8AC4: +case 0x8CC4: +case 0x8EC4: +case 0x80C5: +case 0x82C5: +case 0x84C5: +case 0x86C5: +case 0x88C5: +case 0x8AC5: +case 0x8CC5: +case 0x8EC5: +case 0x80C6: +case 0x82C6: +case 0x84C6: +case 0x86C6: +case 0x88C6: +case 0x8AC6: +case 0x8CC6: +case 0x8EC6: +case 0x80C7: +case 0x82C7: +case 0x84C7: +case 0x86C7: +case 0x88C7: +case 0x8AC7: +case 0x8CC7: +case 0x8EC7: + +// DIVU +case 0x80C0: +{ + u32 res; + pointer dst; + pointer src; + src = (u16)CPU->D[(Opcode >> 0) & 7]; + if (src == 0) + { + if (!CPU->flag_S) + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + } + res = C68K_ZERO_DIVIDE_EX; + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + POST_IO + RET(10) + } + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + { + u32 q, r; + + q = dst / src; + r = dst % src; + + if (q & 0xFFFF0000) + { + CPU->flag_V = C68K_SR_V; + RET(70) + } + q &= 0x0000FFFF; + CPU->flag_notZ = q; + CPU->flag_N = q >> 8; + CPU->flag_V = CPU->flag_C = 0; + res = q | (r << 16); + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + } +} +RET(90) +case 0x82D0: +case 0x84D0: +case 0x86D0: +case 0x88D0: +case 0x8AD0: +case 0x8CD0: +case 0x8ED0: +case 0x80D1: +case 0x82D1: +case 0x84D1: +case 0x86D1: +case 0x88D1: +case 0x8AD1: +case 0x8CD1: +case 0x8ED1: +case 0x80D2: +case 0x82D2: +case 0x84D2: +case 0x86D2: +case 0x88D2: +case 0x8AD2: +case 0x8CD2: +case 0x8ED2: +case 0x80D3: +case 0x82D3: +case 0x84D3: +case 0x86D3: +case 0x88D3: +case 0x8AD3: +case 0x8CD3: +case 0x8ED3: +case 0x80D4: +case 0x82D4: +case 0x84D4: +case 0x86D4: +case 0x88D4: +case 0x8AD4: +case 0x8CD4: +case 0x8ED4: +case 0x80D5: +case 0x82D5: +case 0x84D5: +case 0x86D5: +case 0x88D5: +case 0x8AD5: +case 0x8CD5: +case 0x8ED5: +case 0x80D6: +case 0x82D6: +case 0x84D6: +case 0x86D6: +case 0x88D6: +case 0x8AD6: +case 0x8CD6: +case 0x8ED6: +case 0x80D7: +case 0x82D7: +case 0x84D7: +case 0x86D7: +case 0x88D7: +case 0x8AD7: +case 0x8CD7: +case 0x8ED7: + +// DIVU +case 0x80D0: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_WORD_F(adr, src) + if (src == 0) + { + if (!CPU->flag_S) + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + } + res = C68K_ZERO_DIVIDE_EX; + POST_IO + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + POST_IO + RET(14) + } + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + { + u32 q, r; + + q = dst / src; + r = dst % src; + + if (q & 0xFFFF0000) + { + CPU->flag_V = C68K_SR_V; + RET(74) + } + q &= 0x0000FFFF; + CPU->flag_notZ = q; + CPU->flag_N = q >> 8; + CPU->flag_V = CPU->flag_C = 0; + res = q | (r << 16); + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + } +} +RET(94) +case 0x82D8: +case 0x84D8: +case 0x86D8: +case 0x88D8: +case 0x8AD8: +case 0x8CD8: +case 0x8ED8: +case 0x80D9: +case 0x82D9: +case 0x84D9: +case 0x86D9: +case 0x88D9: +case 0x8AD9: +case 0x8CD9: +case 0x8ED9: +case 0x80DA: +case 0x82DA: +case 0x84DA: +case 0x86DA: +case 0x88DA: +case 0x8ADA: +case 0x8CDA: +case 0x8EDA: +case 0x80DB: +case 0x82DB: +case 0x84DB: +case 0x86DB: +case 0x88DB: +case 0x8ADB: +case 0x8CDB: +case 0x8EDB: +case 0x80DC: +case 0x82DC: +case 0x84DC: +case 0x86DC: +case 0x88DC: +case 0x8ADC: +case 0x8CDC: +case 0x8EDC: +case 0x80DD: +case 0x82DD: +case 0x84DD: +case 0x86DD: +case 0x88DD: +case 0x8ADD: +case 0x8CDD: +case 0x8EDD: +case 0x80DE: +case 0x82DE: +case 0x84DE: +case 0x86DE: +case 0x88DE: +case 0x8ADE: +case 0x8CDE: +case 0x8EDE: + +// DIVU +case 0x80D8: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 2; + PRE_IO + READ_WORD_F(adr, src) + if (src == 0) + { + if (!CPU->flag_S) + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + } + res = C68K_ZERO_DIVIDE_EX; + POST_IO + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + POST_IO + RET(14) + } + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + { + u32 q, r; + + q = dst / src; + r = dst % src; + + if (q & 0xFFFF0000) + { + CPU->flag_V = C68K_SR_V; + RET(74) + } + q &= 0x0000FFFF; + CPU->flag_notZ = q; + CPU->flag_N = q >> 8; + CPU->flag_V = CPU->flag_C = 0; + res = q | (r << 16); + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + } +} +RET(94) +case 0x82E0: +case 0x84E0: +case 0x86E0: +case 0x88E0: +case 0x8AE0: +case 0x8CE0: +case 0x8EE0: +case 0x80E1: +case 0x82E1: +case 0x84E1: +case 0x86E1: +case 0x88E1: +case 0x8AE1: +case 0x8CE1: +case 0x8EE1: +case 0x80E2: +case 0x82E2: +case 0x84E2: +case 0x86E2: +case 0x88E2: +case 0x8AE2: +case 0x8CE2: +case 0x8EE2: +case 0x80E3: +case 0x82E3: +case 0x84E3: +case 0x86E3: +case 0x88E3: +case 0x8AE3: +case 0x8CE3: +case 0x8EE3: +case 0x80E4: +case 0x82E4: +case 0x84E4: +case 0x86E4: +case 0x88E4: +case 0x8AE4: +case 0x8CE4: +case 0x8EE4: +case 0x80E5: +case 0x82E5: +case 0x84E5: +case 0x86E5: +case 0x88E5: +case 0x8AE5: +case 0x8CE5: +case 0x8EE5: +case 0x80E6: +case 0x82E6: +case 0x84E6: +case 0x86E6: +case 0x88E6: +case 0x8AE6: +case 0x8CE6: +case 0x8EE6: + +// DIVU +case 0x80E0: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 2; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_WORD_F(adr, src) + if (src == 0) + { + if (!CPU->flag_S) + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + } + res = C68K_ZERO_DIVIDE_EX; + POST_IO + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + POST_IO + RET(16) + } + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + { + u32 q, r; + + q = dst / src; + r = dst % src; + + if (q & 0xFFFF0000) + { + CPU->flag_V = C68K_SR_V; + RET(76) + } + q &= 0x0000FFFF; + CPU->flag_notZ = q; + CPU->flag_N = q >> 8; + CPU->flag_V = CPU->flag_C = 0; + res = q | (r << 16); + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + } +} +RET(96) +case 0x82E8: +case 0x84E8: +case 0x86E8: +case 0x88E8: +case 0x8AE8: +case 0x8CE8: +case 0x8EE8: +case 0x80E9: +case 0x82E9: +case 0x84E9: +case 0x86E9: +case 0x88E9: +case 0x8AE9: +case 0x8CE9: +case 0x8EE9: +case 0x80EA: +case 0x82EA: +case 0x84EA: +case 0x86EA: +case 0x88EA: +case 0x8AEA: +case 0x8CEA: +case 0x8EEA: +case 0x80EB: +case 0x82EB: +case 0x84EB: +case 0x86EB: +case 0x88EB: +case 0x8AEB: +case 0x8CEB: +case 0x8EEB: +case 0x80EC: +case 0x82EC: +case 0x84EC: +case 0x86EC: +case 0x88EC: +case 0x8AEC: +case 0x8CEC: +case 0x8EEC: +case 0x80ED: +case 0x82ED: +case 0x84ED: +case 0x86ED: +case 0x88ED: +case 0x8AED: +case 0x8CED: +case 0x8EED: +case 0x80EE: +case 0x82EE: +case 0x84EE: +case 0x86EE: +case 0x88EE: +case 0x8AEE: +case 0x8CEE: +case 0x8EEE: +case 0x80EF: +case 0x82EF: +case 0x84EF: +case 0x86EF: +case 0x88EF: +case 0x8AEF: +case 0x8CEF: +case 0x8EEF: + +// DIVU +case 0x80E8: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, src) + if (src == 0) + { + if (!CPU->flag_S) + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + } + res = C68K_ZERO_DIVIDE_EX; + POST_IO + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + POST_IO + RET(18) + } + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + { + u32 q, r; + + q = dst / src; + r = dst % src; + + if (q & 0xFFFF0000) + { + CPU->flag_V = C68K_SR_V; + RET(78) + } + q &= 0x0000FFFF; + CPU->flag_notZ = q; + CPU->flag_N = q >> 8; + CPU->flag_V = CPU->flag_C = 0; + res = q | (r << 16); + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + } +} +RET(98) +case 0x82F0: +case 0x84F0: +case 0x86F0: +case 0x88F0: +case 0x8AF0: +case 0x8CF0: +case 0x8EF0: +case 0x80F1: +case 0x82F1: +case 0x84F1: +case 0x86F1: +case 0x88F1: +case 0x8AF1: +case 0x8CF1: +case 0x8EF1: +case 0x80F2: +case 0x82F2: +case 0x84F2: +case 0x86F2: +case 0x88F2: +case 0x8AF2: +case 0x8CF2: +case 0x8EF2: +case 0x80F3: +case 0x82F3: +case 0x84F3: +case 0x86F3: +case 0x88F3: +case 0x8AF3: +case 0x8CF3: +case 0x8EF3: +case 0x80F4: +case 0x82F4: +case 0x84F4: +case 0x86F4: +case 0x88F4: +case 0x8AF4: +case 0x8CF4: +case 0x8EF4: +case 0x80F5: +case 0x82F5: +case 0x84F5: +case 0x86F5: +case 0x88F5: +case 0x8AF5: +case 0x8CF5: +case 0x8EF5: +case 0x80F6: +case 0x82F6: +case 0x84F6: +case 0x86F6: +case 0x88F6: +case 0x8AF6: +case 0x8CF6: +case 0x8EF6: +case 0x80F7: +case 0x82F7: +case 0x84F7: +case 0x86F7: +case 0x88F7: +case 0x8AF7: +case 0x8CF7: +case 0x8EF7: + +// DIVU +case 0x80F0: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, src) + if (src == 0) + { + if (!CPU->flag_S) + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + } + res = C68K_ZERO_DIVIDE_EX; + POST_IO + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + POST_IO + RET(20) + } + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + { + u32 q, r; + + q = dst / src; + r = dst % src; + + if (q & 0xFFFF0000) + { + CPU->flag_V = C68K_SR_V; + RET(80) + } + q &= 0x0000FFFF; + CPU->flag_notZ = q; + CPU->flag_N = q >> 8; + CPU->flag_V = CPU->flag_C = 0; + res = q | (r << 16); + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + } +} +RET(100) +case 0x82F8: +case 0x84F8: +case 0x86F8: +case 0x88F8: +case 0x8AF8: +case 0x8CF8: +case 0x8EF8: + +// DIVU +case 0x80F8: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, src) + if (src == 0) + { + if (!CPU->flag_S) + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + } + res = C68K_ZERO_DIVIDE_EX; + POST_IO + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + POST_IO + RET(18) + } + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + { + u32 q, r; + + q = dst / src; + r = dst % src; + + if (q & 0xFFFF0000) + { + CPU->flag_V = C68K_SR_V; + RET(78) + } + q &= 0x0000FFFF; + CPU->flag_notZ = q; + CPU->flag_N = q >> 8; + CPU->flag_V = CPU->flag_C = 0; + res = q | (r << 16); + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + } +} +RET(98) +case 0x82F9: +case 0x84F9: +case 0x86F9: +case 0x88F9: +case 0x8AF9: +case 0x8CF9: +case 0x8EF9: + +// DIVU +case 0x80F9: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_WORD_F(adr, src) + if (src == 0) + { + if (!CPU->flag_S) + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + } + res = C68K_ZERO_DIVIDE_EX; + POST_IO + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + POST_IO + RET(22) + } + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + { + u32 q, r; + + q = dst / src; + r = dst % src; + + if (q & 0xFFFF0000) + { + CPU->flag_V = C68K_SR_V; + RET(82) + } + q &= 0x0000FFFF; + CPU->flag_notZ = q; + CPU->flag_N = q >> 8; + CPU->flag_V = CPU->flag_C = 0; + res = q | (r << 16); + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + } +} +RET(102) +case 0x82FA: +case 0x84FA: +case 0x86FA: +case 0x88FA: +case 0x8AFA: +case 0x8CFA: +case 0x8EFA: + +// DIVU +case 0x80FA: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, src) + if (src == 0) + { + if (!CPU->flag_S) + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + } + res = C68K_ZERO_DIVIDE_EX; + POST_IO + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + POST_IO + RET(18) + } + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + { + u32 q, r; + + q = dst / src; + r = dst % src; + + if (q & 0xFFFF0000) + { + CPU->flag_V = C68K_SR_V; + RET(78) + } + q &= 0x0000FFFF; + CPU->flag_notZ = q; + CPU->flag_N = q >> 8; + CPU->flag_V = CPU->flag_C = 0; + res = q | (r << 16); + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + } +} +RET(98) +case 0x82FB: +case 0x84FB: +case 0x86FB: +case 0x88FB: +case 0x8AFB: +case 0x8CFB: +case 0x8EFB: + +// DIVU +case 0x80FB: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, src) + if (src == 0) + { + if (!CPU->flag_S) + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + } + res = C68K_ZERO_DIVIDE_EX; + POST_IO + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + POST_IO + RET(20) + } + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + { + u32 q, r; + + q = dst / src; + r = dst % src; + + if (q & 0xFFFF0000) + { + CPU->flag_V = C68K_SR_V; + RET(80) + } + q &= 0x0000FFFF; + CPU->flag_notZ = q; + CPU->flag_N = q >> 8; + CPU->flag_V = CPU->flag_C = 0; + res = q | (r << 16); + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + } +} +RET(100) +case 0x82FC: +case 0x84FC: +case 0x86FC: +case 0x88FC: +case 0x8AFC: +case 0x8CFC: +case 0x8EFC: + +// DIVU +case 0x80FC: +{ + u32 res; + pointer dst; + pointer src; + src = FETCH_WORD; + PC += 2; + if (src == 0) + { + if (!CPU->flag_S) + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + } + res = C68K_ZERO_DIVIDE_EX; + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + POST_IO + RET(14) + } + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + { + u32 q, r; + + q = dst / src; + r = dst % src; + + if (q & 0xFFFF0000) + { + CPU->flag_V = C68K_SR_V; + RET(74) + } + q &= 0x0000FFFF; + CPU->flag_notZ = q; + CPU->flag_N = q >> 8; + CPU->flag_V = CPU->flag_C = 0; + res = q | (r << 16); + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + } +} +RET(94) +case 0x82DF: +case 0x84DF: +case 0x86DF: +case 0x88DF: +case 0x8ADF: +case 0x8CDF: +case 0x8EDF: + +// DIVU +case 0x80DF: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_WORD_F(adr, src) + if (src == 0) + { + if (!CPU->flag_S) + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + } + res = C68K_ZERO_DIVIDE_EX; + POST_IO + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + POST_IO + RET(14) + } + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + { + u32 q, r; + + q = dst / src; + r = dst % src; + + if (q & 0xFFFF0000) + { + CPU->flag_V = C68K_SR_V; + RET(74) + } + q &= 0x0000FFFF; + CPU->flag_notZ = q; + CPU->flag_N = q >> 8; + CPU->flag_V = CPU->flag_C = 0; + res = q | (r << 16); + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + } +} +RET(94) +case 0x82E7: +case 0x84E7: +case 0x86E7: +case 0x88E7: +case 0x8AE7: +case 0x8CE7: +case 0x8EE7: + +// DIVU +case 0x80E7: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_WORD_F(adr, src) + if (src == 0) + { + if (!CPU->flag_S) + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + } + res = C68K_ZERO_DIVIDE_EX; + POST_IO + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + POST_IO + RET(16) + } + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + { + u32 q, r; + + q = dst / src; + r = dst % src; + + if (q & 0xFFFF0000) + { + CPU->flag_V = C68K_SR_V; + RET(76) + } + q &= 0x0000FFFF; + CPU->flag_notZ = q; + CPU->flag_N = q >> 8; + CPU->flag_V = CPU->flag_C = 0; + res = q | (r << 16); + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + } +} +RET(96) +case 0x83C0: +case 0x85C0: +case 0x87C0: +case 0x89C0: +case 0x8BC0: +case 0x8DC0: +case 0x8FC0: +case 0x81C1: +case 0x83C1: +case 0x85C1: +case 0x87C1: +case 0x89C1: +case 0x8BC1: +case 0x8DC1: +case 0x8FC1: +case 0x81C2: +case 0x83C2: +case 0x85C2: +case 0x87C2: +case 0x89C2: +case 0x8BC2: +case 0x8DC2: +case 0x8FC2: +case 0x81C3: +case 0x83C3: +case 0x85C3: +case 0x87C3: +case 0x89C3: +case 0x8BC3: +case 0x8DC3: +case 0x8FC3: +case 0x81C4: +case 0x83C4: +case 0x85C4: +case 0x87C4: +case 0x89C4: +case 0x8BC4: +case 0x8DC4: +case 0x8FC4: +case 0x81C5: +case 0x83C5: +case 0x85C5: +case 0x87C5: +case 0x89C5: +case 0x8BC5: +case 0x8DC5: +case 0x8FC5: +case 0x81C6: +case 0x83C6: +case 0x85C6: +case 0x87C6: +case 0x89C6: +case 0x8BC6: +case 0x8DC6: +case 0x8FC6: +case 0x81C7: +case 0x83C7: +case 0x85C7: +case 0x87C7: +case 0x89C7: +case 0x8BC7: +case 0x8DC7: +case 0x8FC7: + +// DIVS +case 0x81C0: +{ + u32 res; + pointer dst; + pointer src; + src = (s32)(s16)CPU->D[(Opcode >> 0) & 7]; + if (src == 0) + { + if (!CPU->flag_S) + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + } + res = C68K_ZERO_DIVIDE_EX; + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + POST_IO + RET(10) + } + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + if ((dst == 0x80000000) && (src == -1)) + { + CPU->flag_notZ = CPU->flag_N = 0; + CPU->flag_V = CPU->flag_C = 0; + res = 0; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + RET(50) + } + { + s32 q, r; + + q = (s32)dst / (s32)src; + r = (s32)dst % (s32)src; + + if ((q > 0x7FFF) || (q < -0x8000)) + { + CPU->flag_V = C68K_SR_V; + RET(80) + } + q &= 0x0000FFFF; + CPU->flag_notZ = q; + CPU->flag_N = q >> 8; + CPU->flag_V = CPU->flag_C = 0; + res = q | (r << 16); + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + } +} +RET(108) +case 0x83D0: +case 0x85D0: +case 0x87D0: +case 0x89D0: +case 0x8BD0: +case 0x8DD0: +case 0x8FD0: +case 0x81D1: +case 0x83D1: +case 0x85D1: +case 0x87D1: +case 0x89D1: +case 0x8BD1: +case 0x8DD1: +case 0x8FD1: +case 0x81D2: +case 0x83D2: +case 0x85D2: +case 0x87D2: +case 0x89D2: +case 0x8BD2: +case 0x8DD2: +case 0x8FD2: +case 0x81D3: +case 0x83D3: +case 0x85D3: +case 0x87D3: +case 0x89D3: +case 0x8BD3: +case 0x8DD3: +case 0x8FD3: +case 0x81D4: +case 0x83D4: +case 0x85D4: +case 0x87D4: +case 0x89D4: +case 0x8BD4: +case 0x8DD4: +case 0x8FD4: +case 0x81D5: +case 0x83D5: +case 0x85D5: +case 0x87D5: +case 0x89D5: +case 0x8BD5: +case 0x8DD5: +case 0x8FD5: +case 0x81D6: +case 0x83D6: +case 0x85D6: +case 0x87D6: +case 0x89D6: +case 0x8BD6: +case 0x8DD6: +case 0x8FD6: +case 0x81D7: +case 0x83D7: +case 0x85D7: +case 0x87D7: +case 0x89D7: +case 0x8BD7: +case 0x8DD7: +case 0x8FD7: + +// DIVS +case 0x81D0: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READSX_WORD_F(adr, src) + if (src == 0) + { + if (!CPU->flag_S) + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + } + res = C68K_ZERO_DIVIDE_EX; + POST_IO + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + POST_IO + RET(14) + } + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + if ((dst == 0x80000000) && (src == -1)) + { + CPU->flag_notZ = CPU->flag_N = 0; + CPU->flag_V = CPU->flag_C = 0; + res = 0; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + RET(54) + } + { + s32 q, r; + + q = (s32)dst / (s32)src; + r = (s32)dst % (s32)src; + + if ((q > 0x7FFF) || (q < -0x8000)) + { + CPU->flag_V = C68K_SR_V; + RET(84) + } + q &= 0x0000FFFF; + CPU->flag_notZ = q; + CPU->flag_N = q >> 8; + CPU->flag_V = CPU->flag_C = 0; + res = q | (r << 16); + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + } +} +RET(112) +case 0x83D8: +case 0x85D8: +case 0x87D8: +case 0x89D8: +case 0x8BD8: +case 0x8DD8: +case 0x8FD8: +case 0x81D9: +case 0x83D9: +case 0x85D9: +case 0x87D9: +case 0x89D9: +case 0x8BD9: +case 0x8DD9: +case 0x8FD9: +case 0x81DA: +case 0x83DA: +case 0x85DA: +case 0x87DA: +case 0x89DA: +case 0x8BDA: +case 0x8DDA: +case 0x8FDA: +case 0x81DB: +case 0x83DB: +case 0x85DB: +case 0x87DB: +case 0x89DB: +case 0x8BDB: +case 0x8DDB: +case 0x8FDB: +case 0x81DC: +case 0x83DC: +case 0x85DC: +case 0x87DC: +case 0x89DC: +case 0x8BDC: +case 0x8DDC: +case 0x8FDC: +case 0x81DD: +case 0x83DD: +case 0x85DD: +case 0x87DD: +case 0x89DD: +case 0x8BDD: +case 0x8DDD: +case 0x8FDD: +case 0x81DE: +case 0x83DE: +case 0x85DE: +case 0x87DE: +case 0x89DE: +case 0x8BDE: +case 0x8DDE: +case 0x8FDE: + +// DIVS +case 0x81D8: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 2; + PRE_IO + READSX_WORD_F(adr, src) + if (src == 0) + { + if (!CPU->flag_S) + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + } + res = C68K_ZERO_DIVIDE_EX; + POST_IO + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + POST_IO + RET(14) + } + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + if ((dst == 0x80000000) && (src == -1)) + { + CPU->flag_notZ = CPU->flag_N = 0; + CPU->flag_V = CPU->flag_C = 0; + res = 0; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + RET(54) + } + { + s32 q, r; + + q = (s32)dst / (s32)src; + r = (s32)dst % (s32)src; + + if ((q > 0x7FFF) || (q < -0x8000)) + { + CPU->flag_V = C68K_SR_V; + RET(84) + } + q &= 0x0000FFFF; + CPU->flag_notZ = q; + CPU->flag_N = q >> 8; + CPU->flag_V = CPU->flag_C = 0; + res = q | (r << 16); + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + } +} +RET(112) +case 0x83E0: +case 0x85E0: +case 0x87E0: +case 0x89E0: +case 0x8BE0: +case 0x8DE0: +case 0x8FE0: +case 0x81E1: +case 0x83E1: +case 0x85E1: +case 0x87E1: +case 0x89E1: +case 0x8BE1: +case 0x8DE1: +case 0x8FE1: +case 0x81E2: +case 0x83E2: +case 0x85E2: +case 0x87E2: +case 0x89E2: +case 0x8BE2: +case 0x8DE2: +case 0x8FE2: +case 0x81E3: +case 0x83E3: +case 0x85E3: +case 0x87E3: +case 0x89E3: +case 0x8BE3: +case 0x8DE3: +case 0x8FE3: +case 0x81E4: +case 0x83E4: +case 0x85E4: +case 0x87E4: +case 0x89E4: +case 0x8BE4: +case 0x8DE4: +case 0x8FE4: +case 0x81E5: +case 0x83E5: +case 0x85E5: +case 0x87E5: +case 0x89E5: +case 0x8BE5: +case 0x8DE5: +case 0x8FE5: +case 0x81E6: +case 0x83E6: +case 0x85E6: +case 0x87E6: +case 0x89E6: +case 0x8BE6: +case 0x8DE6: +case 0x8FE6: + +// DIVS +case 0x81E0: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 2; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READSX_WORD_F(adr, src) + if (src == 0) + { + if (!CPU->flag_S) + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + } + res = C68K_ZERO_DIVIDE_EX; + POST_IO + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + POST_IO + RET(16) + } + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + if ((dst == 0x80000000) && (src == -1)) + { + CPU->flag_notZ = CPU->flag_N = 0; + CPU->flag_V = CPU->flag_C = 0; + res = 0; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + RET(56) + } + { + s32 q, r; + + q = (s32)dst / (s32)src; + r = (s32)dst % (s32)src; + + if ((q > 0x7FFF) || (q < -0x8000)) + { + CPU->flag_V = C68K_SR_V; + RET(86) + } + q &= 0x0000FFFF; + CPU->flag_notZ = q; + CPU->flag_N = q >> 8; + CPU->flag_V = CPU->flag_C = 0; + res = q | (r << 16); + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + } +} +RET(114) +case 0x83E8: +case 0x85E8: +case 0x87E8: +case 0x89E8: +case 0x8BE8: +case 0x8DE8: +case 0x8FE8: +case 0x81E9: +case 0x83E9: +case 0x85E9: +case 0x87E9: +case 0x89E9: +case 0x8BE9: +case 0x8DE9: +case 0x8FE9: +case 0x81EA: +case 0x83EA: +case 0x85EA: +case 0x87EA: +case 0x89EA: +case 0x8BEA: +case 0x8DEA: +case 0x8FEA: +case 0x81EB: +case 0x83EB: +case 0x85EB: +case 0x87EB: +case 0x89EB: +case 0x8BEB: +case 0x8DEB: +case 0x8FEB: +case 0x81EC: +case 0x83EC: +case 0x85EC: +case 0x87EC: +case 0x89EC: +case 0x8BEC: +case 0x8DEC: +case 0x8FEC: +case 0x81ED: +case 0x83ED: +case 0x85ED: +case 0x87ED: +case 0x89ED: +case 0x8BED: +case 0x8DED: +case 0x8FED: +case 0x81EE: +case 0x83EE: +case 0x85EE: +case 0x87EE: +case 0x89EE: +case 0x8BEE: +case 0x8DEE: +case 0x8FEE: +case 0x81EF: +case 0x83EF: +case 0x85EF: +case 0x87EF: +case 0x89EF: +case 0x8BEF: +case 0x8DEF: +case 0x8FEF: + +// DIVS +case 0x81E8: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READSX_WORD_F(adr, src) + if (src == 0) + { + if (!CPU->flag_S) + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + } + res = C68K_ZERO_DIVIDE_EX; + POST_IO + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + POST_IO + RET(18) + } + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + if ((dst == 0x80000000) && (src == -1)) + { + CPU->flag_notZ = CPU->flag_N = 0; + CPU->flag_V = CPU->flag_C = 0; + res = 0; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + RET(58) + } + { + s32 q, r; + + q = (s32)dst / (s32)src; + r = (s32)dst % (s32)src; + + if ((q > 0x7FFF) || (q < -0x8000)) + { + CPU->flag_V = C68K_SR_V; + RET(88) + } + q &= 0x0000FFFF; + CPU->flag_notZ = q; + CPU->flag_N = q >> 8; + CPU->flag_V = CPU->flag_C = 0; + res = q | (r << 16); + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + } +} +RET(116) +case 0x83F0: +case 0x85F0: +case 0x87F0: +case 0x89F0: +case 0x8BF0: +case 0x8DF0: +case 0x8FF0: +case 0x81F1: +case 0x83F1: +case 0x85F1: +case 0x87F1: +case 0x89F1: +case 0x8BF1: +case 0x8DF1: +case 0x8FF1: +case 0x81F2: +case 0x83F2: +case 0x85F2: +case 0x87F2: +case 0x89F2: +case 0x8BF2: +case 0x8DF2: +case 0x8FF2: +case 0x81F3: +case 0x83F3: +case 0x85F3: +case 0x87F3: +case 0x89F3: +case 0x8BF3: +case 0x8DF3: +case 0x8FF3: +case 0x81F4: +case 0x83F4: +case 0x85F4: +case 0x87F4: +case 0x89F4: +case 0x8BF4: +case 0x8DF4: +case 0x8FF4: +case 0x81F5: +case 0x83F5: +case 0x85F5: +case 0x87F5: +case 0x89F5: +case 0x8BF5: +case 0x8DF5: +case 0x8FF5: +case 0x81F6: +case 0x83F6: +case 0x85F6: +case 0x87F6: +case 0x89F6: +case 0x8BF6: +case 0x8DF6: +case 0x8FF6: +case 0x81F7: +case 0x83F7: +case 0x85F7: +case 0x87F7: +case 0x89F7: +case 0x8BF7: +case 0x8DF7: +case 0x8FF7: + +// DIVS +case 0x81F0: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READSX_WORD_F(adr, src) + if (src == 0) + { + if (!CPU->flag_S) + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + } + res = C68K_ZERO_DIVIDE_EX; + POST_IO + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + POST_IO + RET(20) + } + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + if ((dst == 0x80000000) && (src == -1)) + { + CPU->flag_notZ = CPU->flag_N = 0; + CPU->flag_V = CPU->flag_C = 0; + res = 0; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + RET(60) + } + { + s32 q, r; + + q = (s32)dst / (s32)src; + r = (s32)dst % (s32)src; + + if ((q > 0x7FFF) || (q < -0x8000)) + { + CPU->flag_V = C68K_SR_V; + RET(90) + } + q &= 0x0000FFFF; + CPU->flag_notZ = q; + CPU->flag_N = q >> 8; + CPU->flag_V = CPU->flag_C = 0; + res = q | (r << 16); + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + } +} +RET(118) +case 0x83F8: +case 0x85F8: +case 0x87F8: +case 0x89F8: +case 0x8BF8: +case 0x8DF8: +case 0x8FF8: + +// DIVS +case 0x81F8: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READSX_WORD_F(adr, src) + if (src == 0) + { + if (!CPU->flag_S) + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + } + res = C68K_ZERO_DIVIDE_EX; + POST_IO + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + POST_IO + RET(18) + } + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + if ((dst == 0x80000000) && (src == -1)) + { + CPU->flag_notZ = CPU->flag_N = 0; + CPU->flag_V = CPU->flag_C = 0; + res = 0; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + RET(58) + } + { + s32 q, r; + + q = (s32)dst / (s32)src; + r = (s32)dst % (s32)src; + + if ((q > 0x7FFF) || (q < -0x8000)) + { + CPU->flag_V = C68K_SR_V; + RET(88) + } + q &= 0x0000FFFF; + CPU->flag_notZ = q; + CPU->flag_N = q >> 8; + CPU->flag_V = CPU->flag_C = 0; + res = q | (r << 16); + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + } +} +RET(116) +case 0x83F9: +case 0x85F9: +case 0x87F9: +case 0x89F9: +case 0x8BF9: +case 0x8DF9: +case 0x8FF9: + +// DIVS +case 0x81F9: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READSX_WORD_F(adr, src) + if (src == 0) + { + if (!CPU->flag_S) + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + } + res = C68K_ZERO_DIVIDE_EX; + POST_IO + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + POST_IO + RET(22) + } + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + if ((dst == 0x80000000) && (src == -1)) + { + CPU->flag_notZ = CPU->flag_N = 0; + CPU->flag_V = CPU->flag_C = 0; + res = 0; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + RET(62) + } + { + s32 q, r; + + q = (s32)dst / (s32)src; + r = (s32)dst % (s32)src; + + if ((q > 0x7FFF) || (q < -0x8000)) + { + CPU->flag_V = C68K_SR_V; + RET(92) + } + q &= 0x0000FFFF; + CPU->flag_notZ = q; + CPU->flag_N = q >> 8; + CPU->flag_V = CPU->flag_C = 0; + res = q | (r << 16); + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + } +} +RET(120) +case 0x83FA: +case 0x85FA: +case 0x87FA: +case 0x89FA: +case 0x8BFA: +case 0x8DFA: +case 0x8FFA: + +// DIVS +case 0x81FA: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READSX_WORD_F(adr, src) + if (src == 0) + { + if (!CPU->flag_S) + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + } + res = C68K_ZERO_DIVIDE_EX; + POST_IO + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + POST_IO + RET(18) + } + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + if ((dst == 0x80000000) && (src == -1)) + { + CPU->flag_notZ = CPU->flag_N = 0; + CPU->flag_V = CPU->flag_C = 0; + res = 0; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + RET(58) + } + { + s32 q, r; + + q = (s32)dst / (s32)src; + r = (s32)dst % (s32)src; + + if ((q > 0x7FFF) || (q < -0x8000)) + { + CPU->flag_V = C68K_SR_V; + RET(88) + } + q &= 0x0000FFFF; + CPU->flag_notZ = q; + CPU->flag_N = q >> 8; + CPU->flag_V = CPU->flag_C = 0; + res = q | (r << 16); + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + } +} +RET(116) +case 0x83FB: +case 0x85FB: +case 0x87FB: +case 0x89FB: +case 0x8BFB: +case 0x8DFB: +case 0x8FFB: + +// DIVS +case 0x81FB: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READSX_WORD_F(adr, src) + if (src == 0) + { + if (!CPU->flag_S) + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + } + res = C68K_ZERO_DIVIDE_EX; + POST_IO + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + POST_IO + RET(20) + } + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + if ((dst == 0x80000000) && (src == -1)) + { + CPU->flag_notZ = CPU->flag_N = 0; + CPU->flag_V = CPU->flag_C = 0; + res = 0; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + RET(60) + } + { + s32 q, r; + + q = (s32)dst / (s32)src; + r = (s32)dst % (s32)src; + + if ((q > 0x7FFF) || (q < -0x8000)) + { + CPU->flag_V = C68K_SR_V; + RET(90) + } + q &= 0x0000FFFF; + CPU->flag_notZ = q; + CPU->flag_N = q >> 8; + CPU->flag_V = CPU->flag_C = 0; + res = q | (r << 16); + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + } +} +RET(118) +case 0x83FC: +case 0x85FC: +case 0x87FC: +case 0x89FC: +case 0x8BFC: +case 0x8DFC: +case 0x8FFC: + +// DIVS +case 0x81FC: +{ + u32 res; + pointer dst; + pointer src; + src = (s32)(s16)FETCH_WORD; + PC += 2; + if (src == 0) + { + if (!CPU->flag_S) + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + } + res = C68K_ZERO_DIVIDE_EX; + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + POST_IO + RET(14) + } + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + if ((dst == 0x80000000) && (src == -1)) + { + CPU->flag_notZ = CPU->flag_N = 0; + CPU->flag_V = CPU->flag_C = 0; + res = 0; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + RET(54) + } + { + s32 q, r; + + q = (s32)dst / (s32)src; + r = (s32)dst % (s32)src; + + if ((q > 0x7FFF) || (q < -0x8000)) + { + CPU->flag_V = C68K_SR_V; + RET(84) + } + q &= 0x0000FFFF; + CPU->flag_notZ = q; + CPU->flag_N = q >> 8; + CPU->flag_V = CPU->flag_C = 0; + res = q | (r << 16); + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + } +} +RET(112) +case 0x83DF: +case 0x85DF: +case 0x87DF: +case 0x89DF: +case 0x8BDF: +case 0x8DDF: +case 0x8FDF: + +// DIVS +case 0x81DF: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READSX_WORD_F(adr, src) + if (src == 0) + { + if (!CPU->flag_S) + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + } + res = C68K_ZERO_DIVIDE_EX; + POST_IO + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + POST_IO + RET(14) + } + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + if ((dst == 0x80000000) && (src == -1)) + { + CPU->flag_notZ = CPU->flag_N = 0; + CPU->flag_V = CPU->flag_C = 0; + res = 0; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + RET(54) + } + { + s32 q, r; + + q = (s32)dst / (s32)src; + r = (s32)dst % (s32)src; + + if ((q > 0x7FFF) || (q < -0x8000)) + { + CPU->flag_V = C68K_SR_V; + RET(84) + } + q &= 0x0000FFFF; + CPU->flag_notZ = q; + CPU->flag_N = q >> 8; + CPU->flag_V = CPU->flag_C = 0; + res = q | (r << 16); + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + } +} +RET(112) +case 0x83E7: +case 0x85E7: +case 0x87E7: +case 0x89E7: +case 0x8BE7: +case 0x8DE7: +case 0x8FE7: + +// DIVS +case 0x81E7: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READSX_WORD_F(adr, src) + if (src == 0) + { + if (!CPU->flag_S) + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + } + res = C68K_ZERO_DIVIDE_EX; + POST_IO + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + POST_IO + RET(16) + } + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + if ((dst == 0x80000000) && (src == -1)) + { + CPU->flag_notZ = CPU->flag_N = 0; + CPU->flag_V = CPU->flag_C = 0; + res = 0; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + RET(56) + } + { + s32 q, r; + + q = (s32)dst / (s32)src; + r = (s32)dst % (s32)src; + + if ((q > 0x7FFF) || (q < -0x8000)) + { + CPU->flag_V = C68K_SR_V; + RET(86) + } + q &= 0x0000FFFF; + CPU->flag_notZ = q; + CPU->flag_N = q >> 8; + CPU->flag_V = CPU->flag_C = 0; + res = q | (r << 16); + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + } +} +RET(114) diff --git a/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68k_op9.inc b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68k_op9.inc new file mode 100644 index 000000000..a35bc4ca2 --- /dev/null +++ b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68k_op9.inc @@ -0,0 +1,5950 @@ +case 0x9200: +case 0x9400: +case 0x9600: +case 0x9800: +case 0x9A00: +case 0x9C00: +case 0x9E00: +case 0x9001: +case 0x9201: +case 0x9401: +case 0x9601: +case 0x9801: +case 0x9A01: +case 0x9C01: +case 0x9E01: +case 0x9002: +case 0x9202: +case 0x9402: +case 0x9602: +case 0x9802: +case 0x9A02: +case 0x9C02: +case 0x9E02: +case 0x9003: +case 0x9203: +case 0x9403: +case 0x9603: +case 0x9803: +case 0x9A03: +case 0x9C03: +case 0x9E03: +case 0x9004: +case 0x9204: +case 0x9404: +case 0x9604: +case 0x9804: +case 0x9A04: +case 0x9C04: +case 0x9E04: +case 0x9005: +case 0x9205: +case 0x9405: +case 0x9605: +case 0x9805: +case 0x9A05: +case 0x9C05: +case 0x9E05: +case 0x9006: +case 0x9206: +case 0x9406: +case 0x9606: +case 0x9806: +case 0x9A06: +case 0x9C06: +case 0x9E06: +case 0x9007: +case 0x9207: +case 0x9407: +case 0x9607: +case 0x9807: +case 0x9A07: +case 0x9C07: +case 0x9E07: + +// SUBaD +case 0x9000: +{ + u32 res; + pointer dst; + pointer src; + src = (u8)CPU->D[(Opcode >> 0) & 7]; + dst = (u8)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; +} +RET(4) +case 0x9208: +case 0x9408: +case 0x9608: +case 0x9808: +case 0x9A08: +case 0x9C08: +case 0x9E08: +case 0x9009: +case 0x9209: +case 0x9409: +case 0x9609: +case 0x9809: +case 0x9A09: +case 0x9C09: +case 0x9E09: +case 0x900A: +case 0x920A: +case 0x940A: +case 0x960A: +case 0x980A: +case 0x9A0A: +case 0x9C0A: +case 0x9E0A: +case 0x900B: +case 0x920B: +case 0x940B: +case 0x960B: +case 0x980B: +case 0x9A0B: +case 0x9C0B: +case 0x9E0B: +case 0x900C: +case 0x920C: +case 0x940C: +case 0x960C: +case 0x980C: +case 0x9A0C: +case 0x9C0C: +case 0x9E0C: +case 0x900D: +case 0x920D: +case 0x940D: +case 0x960D: +case 0x980D: +case 0x9A0D: +case 0x9C0D: +case 0x9E0D: +case 0x900E: +case 0x920E: +case 0x940E: +case 0x960E: +case 0x980E: +case 0x9A0E: +case 0x9C0E: +case 0x9E0E: +case 0x900F: +case 0x920F: +case 0x940F: +case 0x960F: +case 0x980F: +case 0x9A0F: +case 0x9C0F: +case 0x9E0F: + +// SUBaD +case 0x9008: +{ + u32 res; + pointer dst; + pointer src; + // can't read byte from Ax registers ! + CPU->Status |= C68K_FAULTED; + CCnt = 0; + goto C68k_Exec_Really_End; + dst = (u8)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; +} +RET(4) +case 0x9210: +case 0x9410: +case 0x9610: +case 0x9810: +case 0x9A10: +case 0x9C10: +case 0x9E10: +case 0x9011: +case 0x9211: +case 0x9411: +case 0x9611: +case 0x9811: +case 0x9A11: +case 0x9C11: +case 0x9E11: +case 0x9012: +case 0x9212: +case 0x9412: +case 0x9612: +case 0x9812: +case 0x9A12: +case 0x9C12: +case 0x9E12: +case 0x9013: +case 0x9213: +case 0x9413: +case 0x9613: +case 0x9813: +case 0x9A13: +case 0x9C13: +case 0x9E13: +case 0x9014: +case 0x9214: +case 0x9414: +case 0x9614: +case 0x9814: +case 0x9A14: +case 0x9C14: +case 0x9E14: +case 0x9015: +case 0x9215: +case 0x9415: +case 0x9615: +case 0x9815: +case 0x9A15: +case 0x9C15: +case 0x9E15: +case 0x9016: +case 0x9216: +case 0x9416: +case 0x9616: +case 0x9816: +case 0x9A16: +case 0x9C16: +case 0x9E16: +case 0x9017: +case 0x9217: +case 0x9417: +case 0x9617: +case 0x9817: +case 0x9A17: +case 0x9C17: +case 0x9E17: + +// SUBaD +case 0x9010: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_BYTE_F(adr, src) + dst = (u8)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(8) +case 0x9218: +case 0x9418: +case 0x9618: +case 0x9818: +case 0x9A18: +case 0x9C18: +case 0x9E18: +case 0x9019: +case 0x9219: +case 0x9419: +case 0x9619: +case 0x9819: +case 0x9A19: +case 0x9C19: +case 0x9E19: +case 0x901A: +case 0x921A: +case 0x941A: +case 0x961A: +case 0x981A: +case 0x9A1A: +case 0x9C1A: +case 0x9E1A: +case 0x901B: +case 0x921B: +case 0x941B: +case 0x961B: +case 0x981B: +case 0x9A1B: +case 0x9C1B: +case 0x9E1B: +case 0x901C: +case 0x921C: +case 0x941C: +case 0x961C: +case 0x981C: +case 0x9A1C: +case 0x9C1C: +case 0x9E1C: +case 0x901D: +case 0x921D: +case 0x941D: +case 0x961D: +case 0x981D: +case 0x9A1D: +case 0x9C1D: +case 0x9E1D: +case 0x901E: +case 0x921E: +case 0x941E: +case 0x961E: +case 0x981E: +case 0x9A1E: +case 0x9C1E: +case 0x9E1E: + +// SUBaD +case 0x9018: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + PRE_IO + READ_BYTE_F(adr, src) + dst = (u8)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(8) +case 0x9220: +case 0x9420: +case 0x9620: +case 0x9820: +case 0x9A20: +case 0x9C20: +case 0x9E20: +case 0x9021: +case 0x9221: +case 0x9421: +case 0x9621: +case 0x9821: +case 0x9A21: +case 0x9C21: +case 0x9E21: +case 0x9022: +case 0x9222: +case 0x9422: +case 0x9622: +case 0x9822: +case 0x9A22: +case 0x9C22: +case 0x9E22: +case 0x9023: +case 0x9223: +case 0x9423: +case 0x9623: +case 0x9823: +case 0x9A23: +case 0x9C23: +case 0x9E23: +case 0x9024: +case 0x9224: +case 0x9424: +case 0x9624: +case 0x9824: +case 0x9A24: +case 0x9C24: +case 0x9E24: +case 0x9025: +case 0x9225: +case 0x9425: +case 0x9625: +case 0x9825: +case 0x9A25: +case 0x9C25: +case 0x9E25: +case 0x9026: +case 0x9226: +case 0x9426: +case 0x9626: +case 0x9826: +case 0x9A26: +case 0x9C26: +case 0x9E26: + +// SUBaD +case 0x9020: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_BYTE_F(adr, src) + dst = (u8)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(10) +case 0x9228: +case 0x9428: +case 0x9628: +case 0x9828: +case 0x9A28: +case 0x9C28: +case 0x9E28: +case 0x9029: +case 0x9229: +case 0x9429: +case 0x9629: +case 0x9829: +case 0x9A29: +case 0x9C29: +case 0x9E29: +case 0x902A: +case 0x922A: +case 0x942A: +case 0x962A: +case 0x982A: +case 0x9A2A: +case 0x9C2A: +case 0x9E2A: +case 0x902B: +case 0x922B: +case 0x942B: +case 0x962B: +case 0x982B: +case 0x9A2B: +case 0x9C2B: +case 0x9E2B: +case 0x902C: +case 0x922C: +case 0x942C: +case 0x962C: +case 0x982C: +case 0x9A2C: +case 0x9C2C: +case 0x9E2C: +case 0x902D: +case 0x922D: +case 0x942D: +case 0x962D: +case 0x982D: +case 0x9A2D: +case 0x9C2D: +case 0x9E2D: +case 0x902E: +case 0x922E: +case 0x942E: +case 0x962E: +case 0x982E: +case 0x9A2E: +case 0x9C2E: +case 0x9E2E: +case 0x902F: +case 0x922F: +case 0x942F: +case 0x962F: +case 0x982F: +case 0x9A2F: +case 0x9C2F: +case 0x9E2F: + +// SUBaD +case 0x9028: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, src) + dst = (u8)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(12) +case 0x9230: +case 0x9430: +case 0x9630: +case 0x9830: +case 0x9A30: +case 0x9C30: +case 0x9E30: +case 0x9031: +case 0x9231: +case 0x9431: +case 0x9631: +case 0x9831: +case 0x9A31: +case 0x9C31: +case 0x9E31: +case 0x9032: +case 0x9232: +case 0x9432: +case 0x9632: +case 0x9832: +case 0x9A32: +case 0x9C32: +case 0x9E32: +case 0x9033: +case 0x9233: +case 0x9433: +case 0x9633: +case 0x9833: +case 0x9A33: +case 0x9C33: +case 0x9E33: +case 0x9034: +case 0x9234: +case 0x9434: +case 0x9634: +case 0x9834: +case 0x9A34: +case 0x9C34: +case 0x9E34: +case 0x9035: +case 0x9235: +case 0x9435: +case 0x9635: +case 0x9835: +case 0x9A35: +case 0x9C35: +case 0x9E35: +case 0x9036: +case 0x9236: +case 0x9436: +case 0x9636: +case 0x9836: +case 0x9A36: +case 0x9C36: +case 0x9E36: +case 0x9037: +case 0x9237: +case 0x9437: +case 0x9637: +case 0x9837: +case 0x9A37: +case 0x9C37: +case 0x9E37: + +// SUBaD +case 0x9030: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, src) + dst = (u8)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(14) +case 0x9238: +case 0x9438: +case 0x9638: +case 0x9838: +case 0x9A38: +case 0x9C38: +case 0x9E38: + +// SUBaD +case 0x9038: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, src) + dst = (u8)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(12) +case 0x9239: +case 0x9439: +case 0x9639: +case 0x9839: +case 0x9A39: +case 0x9C39: +case 0x9E39: + +// SUBaD +case 0x9039: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_BYTE_F(adr, src) + dst = (u8)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(16) +case 0x923A: +case 0x943A: +case 0x963A: +case 0x983A: +case 0x9A3A: +case 0x9C3A: +case 0x9E3A: + +// SUBaD +case 0x903A: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, src) + dst = (u8)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(12) +case 0x923B: +case 0x943B: +case 0x963B: +case 0x983B: +case 0x9A3B: +case 0x9C3B: +case 0x9E3B: + +// SUBaD +case 0x903B: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, src) + dst = (u8)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(14) +case 0x923C: +case 0x943C: +case 0x963C: +case 0x983C: +case 0x9A3C: +case 0x9C3C: +case 0x9E3C: + +// SUBaD +case 0x903C: +{ + u32 res; + pointer dst; + pointer src; + src = FETCH_BYTE; + PC += 2; + dst = (u8)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; +} +RET(8) +case 0x921F: +case 0x941F: +case 0x961F: +case 0x981F: +case 0x9A1F: +case 0x9C1F: +case 0x9E1F: + +// SUBaD +case 0x901F: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_BYTE_F(adr, src) + dst = (u8)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(8) +case 0x9227: +case 0x9427: +case 0x9627: +case 0x9827: +case 0x9A27: +case 0x9C27: +case 0x9E27: + +// SUBaD +case 0x9027: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_BYTE_F(adr, src) + dst = (u8)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(10) +case 0x9240: +case 0x9440: +case 0x9640: +case 0x9840: +case 0x9A40: +case 0x9C40: +case 0x9E40: +case 0x9041: +case 0x9241: +case 0x9441: +case 0x9641: +case 0x9841: +case 0x9A41: +case 0x9C41: +case 0x9E41: +case 0x9042: +case 0x9242: +case 0x9442: +case 0x9642: +case 0x9842: +case 0x9A42: +case 0x9C42: +case 0x9E42: +case 0x9043: +case 0x9243: +case 0x9443: +case 0x9643: +case 0x9843: +case 0x9A43: +case 0x9C43: +case 0x9E43: +case 0x9044: +case 0x9244: +case 0x9444: +case 0x9644: +case 0x9844: +case 0x9A44: +case 0x9C44: +case 0x9E44: +case 0x9045: +case 0x9245: +case 0x9445: +case 0x9645: +case 0x9845: +case 0x9A45: +case 0x9C45: +case 0x9E45: +case 0x9046: +case 0x9246: +case 0x9446: +case 0x9646: +case 0x9846: +case 0x9A46: +case 0x9C46: +case 0x9E46: +case 0x9047: +case 0x9247: +case 0x9447: +case 0x9647: +case 0x9847: +case 0x9A47: +case 0x9C47: +case 0x9E47: + +// SUBaD +case 0x9040: +{ + u32 res; + pointer dst; + pointer src; + src = (u16)CPU->D[(Opcode >> 0) & 7]; + dst = (u16)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; +} +RET(4) +case 0x9248: +case 0x9448: +case 0x9648: +case 0x9848: +case 0x9A48: +case 0x9C48: +case 0x9E48: +case 0x9049: +case 0x9249: +case 0x9449: +case 0x9649: +case 0x9849: +case 0x9A49: +case 0x9C49: +case 0x9E49: +case 0x904A: +case 0x924A: +case 0x944A: +case 0x964A: +case 0x984A: +case 0x9A4A: +case 0x9C4A: +case 0x9E4A: +case 0x904B: +case 0x924B: +case 0x944B: +case 0x964B: +case 0x984B: +case 0x9A4B: +case 0x9C4B: +case 0x9E4B: +case 0x904C: +case 0x924C: +case 0x944C: +case 0x964C: +case 0x984C: +case 0x9A4C: +case 0x9C4C: +case 0x9E4C: +case 0x904D: +case 0x924D: +case 0x944D: +case 0x964D: +case 0x984D: +case 0x9A4D: +case 0x9C4D: +case 0x9E4D: +case 0x904E: +case 0x924E: +case 0x944E: +case 0x964E: +case 0x984E: +case 0x9A4E: +case 0x9C4E: +case 0x9E4E: +case 0x904F: +case 0x924F: +case 0x944F: +case 0x964F: +case 0x984F: +case 0x9A4F: +case 0x9C4F: +case 0x9E4F: + +// SUBaD +case 0x9048: +{ + u32 res; + pointer dst; + pointer src; + src = (u16)CPU->A[(Opcode >> 0) & 7]; + dst = (u16)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; +} +RET(4) +case 0x9250: +case 0x9450: +case 0x9650: +case 0x9850: +case 0x9A50: +case 0x9C50: +case 0x9E50: +case 0x9051: +case 0x9251: +case 0x9451: +case 0x9651: +case 0x9851: +case 0x9A51: +case 0x9C51: +case 0x9E51: +case 0x9052: +case 0x9252: +case 0x9452: +case 0x9652: +case 0x9852: +case 0x9A52: +case 0x9C52: +case 0x9E52: +case 0x9053: +case 0x9253: +case 0x9453: +case 0x9653: +case 0x9853: +case 0x9A53: +case 0x9C53: +case 0x9E53: +case 0x9054: +case 0x9254: +case 0x9454: +case 0x9654: +case 0x9854: +case 0x9A54: +case 0x9C54: +case 0x9E54: +case 0x9055: +case 0x9255: +case 0x9455: +case 0x9655: +case 0x9855: +case 0x9A55: +case 0x9C55: +case 0x9E55: +case 0x9056: +case 0x9256: +case 0x9456: +case 0x9656: +case 0x9856: +case 0x9A56: +case 0x9C56: +case 0x9E56: +case 0x9057: +case 0x9257: +case 0x9457: +case 0x9657: +case 0x9857: +case 0x9A57: +case 0x9C57: +case 0x9E57: + +// SUBaD +case 0x9050: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_WORD_F(adr, src) + dst = (u16)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(8) +case 0x9258: +case 0x9458: +case 0x9658: +case 0x9858: +case 0x9A58: +case 0x9C58: +case 0x9E58: +case 0x9059: +case 0x9259: +case 0x9459: +case 0x9659: +case 0x9859: +case 0x9A59: +case 0x9C59: +case 0x9E59: +case 0x905A: +case 0x925A: +case 0x945A: +case 0x965A: +case 0x985A: +case 0x9A5A: +case 0x9C5A: +case 0x9E5A: +case 0x905B: +case 0x925B: +case 0x945B: +case 0x965B: +case 0x985B: +case 0x9A5B: +case 0x9C5B: +case 0x9E5B: +case 0x905C: +case 0x925C: +case 0x945C: +case 0x965C: +case 0x985C: +case 0x9A5C: +case 0x9C5C: +case 0x9E5C: +case 0x905D: +case 0x925D: +case 0x945D: +case 0x965D: +case 0x985D: +case 0x9A5D: +case 0x9C5D: +case 0x9E5D: +case 0x905E: +case 0x925E: +case 0x945E: +case 0x965E: +case 0x985E: +case 0x9A5E: +case 0x9C5E: +case 0x9E5E: + +// SUBaD +case 0x9058: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 2; + PRE_IO + READ_WORD_F(adr, src) + dst = (u16)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(8) +case 0x9260: +case 0x9460: +case 0x9660: +case 0x9860: +case 0x9A60: +case 0x9C60: +case 0x9E60: +case 0x9061: +case 0x9261: +case 0x9461: +case 0x9661: +case 0x9861: +case 0x9A61: +case 0x9C61: +case 0x9E61: +case 0x9062: +case 0x9262: +case 0x9462: +case 0x9662: +case 0x9862: +case 0x9A62: +case 0x9C62: +case 0x9E62: +case 0x9063: +case 0x9263: +case 0x9463: +case 0x9663: +case 0x9863: +case 0x9A63: +case 0x9C63: +case 0x9E63: +case 0x9064: +case 0x9264: +case 0x9464: +case 0x9664: +case 0x9864: +case 0x9A64: +case 0x9C64: +case 0x9E64: +case 0x9065: +case 0x9265: +case 0x9465: +case 0x9665: +case 0x9865: +case 0x9A65: +case 0x9C65: +case 0x9E65: +case 0x9066: +case 0x9266: +case 0x9466: +case 0x9666: +case 0x9866: +case 0x9A66: +case 0x9C66: +case 0x9E66: + +// SUBaD +case 0x9060: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 2; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_WORD_F(adr, src) + dst = (u16)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(10) +case 0x9268: +case 0x9468: +case 0x9668: +case 0x9868: +case 0x9A68: +case 0x9C68: +case 0x9E68: +case 0x9069: +case 0x9269: +case 0x9469: +case 0x9669: +case 0x9869: +case 0x9A69: +case 0x9C69: +case 0x9E69: +case 0x906A: +case 0x926A: +case 0x946A: +case 0x966A: +case 0x986A: +case 0x9A6A: +case 0x9C6A: +case 0x9E6A: +case 0x906B: +case 0x926B: +case 0x946B: +case 0x966B: +case 0x986B: +case 0x9A6B: +case 0x9C6B: +case 0x9E6B: +case 0x906C: +case 0x926C: +case 0x946C: +case 0x966C: +case 0x986C: +case 0x9A6C: +case 0x9C6C: +case 0x9E6C: +case 0x906D: +case 0x926D: +case 0x946D: +case 0x966D: +case 0x986D: +case 0x9A6D: +case 0x9C6D: +case 0x9E6D: +case 0x906E: +case 0x926E: +case 0x946E: +case 0x966E: +case 0x986E: +case 0x9A6E: +case 0x9C6E: +case 0x9E6E: +case 0x906F: +case 0x926F: +case 0x946F: +case 0x966F: +case 0x986F: +case 0x9A6F: +case 0x9C6F: +case 0x9E6F: + +// SUBaD +case 0x9068: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, src) + dst = (u16)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(12) +case 0x9270: +case 0x9470: +case 0x9670: +case 0x9870: +case 0x9A70: +case 0x9C70: +case 0x9E70: +case 0x9071: +case 0x9271: +case 0x9471: +case 0x9671: +case 0x9871: +case 0x9A71: +case 0x9C71: +case 0x9E71: +case 0x9072: +case 0x9272: +case 0x9472: +case 0x9672: +case 0x9872: +case 0x9A72: +case 0x9C72: +case 0x9E72: +case 0x9073: +case 0x9273: +case 0x9473: +case 0x9673: +case 0x9873: +case 0x9A73: +case 0x9C73: +case 0x9E73: +case 0x9074: +case 0x9274: +case 0x9474: +case 0x9674: +case 0x9874: +case 0x9A74: +case 0x9C74: +case 0x9E74: +case 0x9075: +case 0x9275: +case 0x9475: +case 0x9675: +case 0x9875: +case 0x9A75: +case 0x9C75: +case 0x9E75: +case 0x9076: +case 0x9276: +case 0x9476: +case 0x9676: +case 0x9876: +case 0x9A76: +case 0x9C76: +case 0x9E76: +case 0x9077: +case 0x9277: +case 0x9477: +case 0x9677: +case 0x9877: +case 0x9A77: +case 0x9C77: +case 0x9E77: + +// SUBaD +case 0x9070: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, src) + dst = (u16)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(14) +case 0x9278: +case 0x9478: +case 0x9678: +case 0x9878: +case 0x9A78: +case 0x9C78: +case 0x9E78: + +// SUBaD +case 0x9078: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, src) + dst = (u16)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(12) +case 0x9279: +case 0x9479: +case 0x9679: +case 0x9879: +case 0x9A79: +case 0x9C79: +case 0x9E79: + +// SUBaD +case 0x9079: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_WORD_F(adr, src) + dst = (u16)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(16) +case 0x927A: +case 0x947A: +case 0x967A: +case 0x987A: +case 0x9A7A: +case 0x9C7A: +case 0x9E7A: + +// SUBaD +case 0x907A: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, src) + dst = (u16)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(12) +case 0x927B: +case 0x947B: +case 0x967B: +case 0x987B: +case 0x9A7B: +case 0x9C7B: +case 0x9E7B: + +// SUBaD +case 0x907B: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, src) + dst = (u16)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(14) +case 0x927C: +case 0x947C: +case 0x967C: +case 0x987C: +case 0x9A7C: +case 0x9C7C: +case 0x9E7C: + +// SUBaD +case 0x907C: +{ + u32 res; + pointer dst; + pointer src; + src = FETCH_WORD; + PC += 2; + dst = (u16)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; +} +RET(8) +case 0x925F: +case 0x945F: +case 0x965F: +case 0x985F: +case 0x9A5F: +case 0x9C5F: +case 0x9E5F: + +// SUBaD +case 0x905F: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_WORD_F(adr, src) + dst = (u16)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(8) +case 0x9267: +case 0x9467: +case 0x9667: +case 0x9867: +case 0x9A67: +case 0x9C67: +case 0x9E67: + +// SUBaD +case 0x9067: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_WORD_F(adr, src) + dst = (u16)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(10) +case 0x9280: +case 0x9480: +case 0x9680: +case 0x9880: +case 0x9A80: +case 0x9C80: +case 0x9E80: +case 0x9081: +case 0x9281: +case 0x9481: +case 0x9681: +case 0x9881: +case 0x9A81: +case 0x9C81: +case 0x9E81: +case 0x9082: +case 0x9282: +case 0x9482: +case 0x9682: +case 0x9882: +case 0x9A82: +case 0x9C82: +case 0x9E82: +case 0x9083: +case 0x9283: +case 0x9483: +case 0x9683: +case 0x9883: +case 0x9A83: +case 0x9C83: +case 0x9E83: +case 0x9084: +case 0x9284: +case 0x9484: +case 0x9684: +case 0x9884: +case 0x9A84: +case 0x9C84: +case 0x9E84: +case 0x9085: +case 0x9285: +case 0x9485: +case 0x9685: +case 0x9885: +case 0x9A85: +case 0x9C85: +case 0x9E85: +case 0x9086: +case 0x9286: +case 0x9486: +case 0x9686: +case 0x9886: +case 0x9A86: +case 0x9C86: +case 0x9E86: +case 0x9087: +case 0x9287: +case 0x9487: +case 0x9687: +case 0x9887: +case 0x9A87: +case 0x9C87: +case 0x9E87: + +// SUBaD +case 0x9080: +{ + u32 res; + pointer dst; + pointer src; + src = (u32)CPU->D[(Opcode >> 0) & 7]; + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; +} +RET(6) +case 0x9288: +case 0x9488: +case 0x9688: +case 0x9888: +case 0x9A88: +case 0x9C88: +case 0x9E88: +case 0x9089: +case 0x9289: +case 0x9489: +case 0x9689: +case 0x9889: +case 0x9A89: +case 0x9C89: +case 0x9E89: +case 0x908A: +case 0x928A: +case 0x948A: +case 0x968A: +case 0x988A: +case 0x9A8A: +case 0x9C8A: +case 0x9E8A: +case 0x908B: +case 0x928B: +case 0x948B: +case 0x968B: +case 0x988B: +case 0x9A8B: +case 0x9C8B: +case 0x9E8B: +case 0x908C: +case 0x928C: +case 0x948C: +case 0x968C: +case 0x988C: +case 0x9A8C: +case 0x9C8C: +case 0x9E8C: +case 0x908D: +case 0x928D: +case 0x948D: +case 0x968D: +case 0x988D: +case 0x9A8D: +case 0x9C8D: +case 0x9E8D: +case 0x908E: +case 0x928E: +case 0x948E: +case 0x968E: +case 0x988E: +case 0x9A8E: +case 0x9C8E: +case 0x9E8E: +case 0x908F: +case 0x928F: +case 0x948F: +case 0x968F: +case 0x988F: +case 0x9A8F: +case 0x9C8F: +case 0x9E8F: + +// SUBaD +case 0x9088: +{ + u32 res; + pointer dst; + pointer src; + src = (u32)CPU->A[(Opcode >> 0) & 7]; + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; +} +RET(6) +case 0x9290: +case 0x9490: +case 0x9690: +case 0x9890: +case 0x9A90: +case 0x9C90: +case 0x9E90: +case 0x9091: +case 0x9291: +case 0x9491: +case 0x9691: +case 0x9891: +case 0x9A91: +case 0x9C91: +case 0x9E91: +case 0x9092: +case 0x9292: +case 0x9492: +case 0x9692: +case 0x9892: +case 0x9A92: +case 0x9C92: +case 0x9E92: +case 0x9093: +case 0x9293: +case 0x9493: +case 0x9693: +case 0x9893: +case 0x9A93: +case 0x9C93: +case 0x9E93: +case 0x9094: +case 0x9294: +case 0x9494: +case 0x9694: +case 0x9894: +case 0x9A94: +case 0x9C94: +case 0x9E94: +case 0x9095: +case 0x9295: +case 0x9495: +case 0x9695: +case 0x9895: +case 0x9A95: +case 0x9C95: +case 0x9E95: +case 0x9096: +case 0x9296: +case 0x9496: +case 0x9696: +case 0x9896: +case 0x9A96: +case 0x9C96: +case 0x9E96: +case 0x9097: +case 0x9297: +case 0x9497: +case 0x9697: +case 0x9897: +case 0x9A97: +case 0x9C97: +case 0x9E97: + +// SUBaD +case 0x9090: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_LONG_F(adr, src) + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(16) +case 0x9298: +case 0x9498: +case 0x9698: +case 0x9898: +case 0x9A98: +case 0x9C98: +case 0x9E98: +case 0x9099: +case 0x9299: +case 0x9499: +case 0x9699: +case 0x9899: +case 0x9A99: +case 0x9C99: +case 0x9E99: +case 0x909A: +case 0x929A: +case 0x949A: +case 0x969A: +case 0x989A: +case 0x9A9A: +case 0x9C9A: +case 0x9E9A: +case 0x909B: +case 0x929B: +case 0x949B: +case 0x969B: +case 0x989B: +case 0x9A9B: +case 0x9C9B: +case 0x9E9B: +case 0x909C: +case 0x929C: +case 0x949C: +case 0x969C: +case 0x989C: +case 0x9A9C: +case 0x9C9C: +case 0x9E9C: +case 0x909D: +case 0x929D: +case 0x949D: +case 0x969D: +case 0x989D: +case 0x9A9D: +case 0x9C9D: +case 0x9E9D: +case 0x909E: +case 0x929E: +case 0x949E: +case 0x969E: +case 0x989E: +case 0x9A9E: +case 0x9C9E: +case 0x9E9E: + +// SUBaD +case 0x9098: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 4; + PRE_IO + READ_LONG_F(adr, src) + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(16) +case 0x92A0: +case 0x94A0: +case 0x96A0: +case 0x98A0: +case 0x9AA0: +case 0x9CA0: +case 0x9EA0: +case 0x90A1: +case 0x92A1: +case 0x94A1: +case 0x96A1: +case 0x98A1: +case 0x9AA1: +case 0x9CA1: +case 0x9EA1: +case 0x90A2: +case 0x92A2: +case 0x94A2: +case 0x96A2: +case 0x98A2: +case 0x9AA2: +case 0x9CA2: +case 0x9EA2: +case 0x90A3: +case 0x92A3: +case 0x94A3: +case 0x96A3: +case 0x98A3: +case 0x9AA3: +case 0x9CA3: +case 0x9EA3: +case 0x90A4: +case 0x92A4: +case 0x94A4: +case 0x96A4: +case 0x98A4: +case 0x9AA4: +case 0x9CA4: +case 0x9EA4: +case 0x90A5: +case 0x92A5: +case 0x94A5: +case 0x96A5: +case 0x98A5: +case 0x9AA5: +case 0x9CA5: +case 0x9EA5: +case 0x90A6: +case 0x92A6: +case 0x94A6: +case 0x96A6: +case 0x98A6: +case 0x9AA6: +case 0x9CA6: +case 0x9EA6: + +// SUBaD +case 0x90A0: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 4; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_LONG_F(adr, src) + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(18) +case 0x92A8: +case 0x94A8: +case 0x96A8: +case 0x98A8: +case 0x9AA8: +case 0x9CA8: +case 0x9EA8: +case 0x90A9: +case 0x92A9: +case 0x94A9: +case 0x96A9: +case 0x98A9: +case 0x9AA9: +case 0x9CA9: +case 0x9EA9: +case 0x90AA: +case 0x92AA: +case 0x94AA: +case 0x96AA: +case 0x98AA: +case 0x9AAA: +case 0x9CAA: +case 0x9EAA: +case 0x90AB: +case 0x92AB: +case 0x94AB: +case 0x96AB: +case 0x98AB: +case 0x9AAB: +case 0x9CAB: +case 0x9EAB: +case 0x90AC: +case 0x92AC: +case 0x94AC: +case 0x96AC: +case 0x98AC: +case 0x9AAC: +case 0x9CAC: +case 0x9EAC: +case 0x90AD: +case 0x92AD: +case 0x94AD: +case 0x96AD: +case 0x98AD: +case 0x9AAD: +case 0x9CAD: +case 0x9EAD: +case 0x90AE: +case 0x92AE: +case 0x94AE: +case 0x96AE: +case 0x98AE: +case 0x9AAE: +case 0x9CAE: +case 0x9EAE: +case 0x90AF: +case 0x92AF: +case 0x94AF: +case 0x96AF: +case 0x98AF: +case 0x9AAF: +case 0x9CAF: +case 0x9EAF: + +// SUBaD +case 0x90A8: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, src) + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(20) +case 0x92B0: +case 0x94B0: +case 0x96B0: +case 0x98B0: +case 0x9AB0: +case 0x9CB0: +case 0x9EB0: +case 0x90B1: +case 0x92B1: +case 0x94B1: +case 0x96B1: +case 0x98B1: +case 0x9AB1: +case 0x9CB1: +case 0x9EB1: +case 0x90B2: +case 0x92B2: +case 0x94B2: +case 0x96B2: +case 0x98B2: +case 0x9AB2: +case 0x9CB2: +case 0x9EB2: +case 0x90B3: +case 0x92B3: +case 0x94B3: +case 0x96B3: +case 0x98B3: +case 0x9AB3: +case 0x9CB3: +case 0x9EB3: +case 0x90B4: +case 0x92B4: +case 0x94B4: +case 0x96B4: +case 0x98B4: +case 0x9AB4: +case 0x9CB4: +case 0x9EB4: +case 0x90B5: +case 0x92B5: +case 0x94B5: +case 0x96B5: +case 0x98B5: +case 0x9AB5: +case 0x9CB5: +case 0x9EB5: +case 0x90B6: +case 0x92B6: +case 0x94B6: +case 0x96B6: +case 0x98B6: +case 0x9AB6: +case 0x9CB6: +case 0x9EB6: +case 0x90B7: +case 0x92B7: +case 0x94B7: +case 0x96B7: +case 0x98B7: +case 0x9AB7: +case 0x9CB7: +case 0x9EB7: + +// SUBaD +case 0x90B0: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_LONG_F(adr, src) + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(22) +case 0x92B8: +case 0x94B8: +case 0x96B8: +case 0x98B8: +case 0x9AB8: +case 0x9CB8: +case 0x9EB8: + +// SUBaD +case 0x90B8: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, src) + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(20) +case 0x92B9: +case 0x94B9: +case 0x96B9: +case 0x98B9: +case 0x9AB9: +case 0x9CB9: +case 0x9EB9: + +// SUBaD +case 0x90B9: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_LONG_F(adr, src) + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(24) +case 0x92BA: +case 0x94BA: +case 0x96BA: +case 0x98BA: +case 0x9ABA: +case 0x9CBA: +case 0x9EBA: + +// SUBaD +case 0x90BA: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, src) + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(20) +case 0x92BB: +case 0x94BB: +case 0x96BB: +case 0x98BB: +case 0x9ABB: +case 0x9CBB: +case 0x9EBB: + +// SUBaD +case 0x90BB: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READ_LONG_F(adr, src) + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(22) +case 0x92BC: +case 0x94BC: +case 0x96BC: +case 0x98BC: +case 0x9ABC: +case 0x9CBC: +case 0x9EBC: + +// SUBaD +case 0x90BC: +{ + u32 res; + pointer dst; + pointer src; + src = FETCH_LONG; + PC += 4; + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; +} +RET(14) +case 0x929F: +case 0x949F: +case 0x969F: +case 0x989F: +case 0x9A9F: +case 0x9C9F: +case 0x9E9F: + +// SUBaD +case 0x909F: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[7]; + CPU->A[7] += 4; + PRE_IO + READ_LONG_F(adr, src) + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(16) +case 0x92A7: +case 0x94A7: +case 0x96A7: +case 0x98A7: +case 0x9AA7: +case 0x9CA7: +case 0x9EA7: + +// SUBaD +case 0x90A7: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + PRE_IO + READ_LONG_F(adr, src) + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(18) +case 0x9310: +case 0x9510: +case 0x9710: +case 0x9910: +case 0x9B10: +case 0x9D10: +case 0x9F10: +case 0x9111: +case 0x9311: +case 0x9511: +case 0x9711: +case 0x9911: +case 0x9B11: +case 0x9D11: +case 0x9F11: +case 0x9112: +case 0x9312: +case 0x9512: +case 0x9712: +case 0x9912: +case 0x9B12: +case 0x9D12: +case 0x9F12: +case 0x9113: +case 0x9313: +case 0x9513: +case 0x9713: +case 0x9913: +case 0x9B13: +case 0x9D13: +case 0x9F13: +case 0x9114: +case 0x9314: +case 0x9514: +case 0x9714: +case 0x9914: +case 0x9B14: +case 0x9D14: +case 0x9F14: +case 0x9115: +case 0x9315: +case 0x9515: +case 0x9715: +case 0x9915: +case 0x9B15: +case 0x9D15: +case 0x9F15: +case 0x9116: +case 0x9316: +case 0x9516: +case 0x9716: +case 0x9916: +case 0x9B16: +case 0x9D16: +case 0x9F16: +case 0x9117: +case 0x9317: +case 0x9517: +case 0x9717: +case 0x9917: +case 0x9B17: +case 0x9D17: +case 0x9F17: + +// SUBDa +case 0x9110: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_BYTE_F(adr, dst) + res = dst - src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0x9318: +case 0x9518: +case 0x9718: +case 0x9918: +case 0x9B18: +case 0x9D18: +case 0x9F18: +case 0x9119: +case 0x9319: +case 0x9519: +case 0x9719: +case 0x9919: +case 0x9B19: +case 0x9D19: +case 0x9F19: +case 0x911A: +case 0x931A: +case 0x951A: +case 0x971A: +case 0x991A: +case 0x9B1A: +case 0x9D1A: +case 0x9F1A: +case 0x911B: +case 0x931B: +case 0x951B: +case 0x971B: +case 0x991B: +case 0x9B1B: +case 0x9D1B: +case 0x9F1B: +case 0x911C: +case 0x931C: +case 0x951C: +case 0x971C: +case 0x991C: +case 0x9B1C: +case 0x9D1C: +case 0x9F1C: +case 0x911D: +case 0x931D: +case 0x951D: +case 0x971D: +case 0x991D: +case 0x9B1D: +case 0x9D1D: +case 0x9F1D: +case 0x911E: +case 0x931E: +case 0x951E: +case 0x971E: +case 0x991E: +case 0x9B1E: +case 0x9D1E: +case 0x9F1E: + +// SUBDa +case 0x9118: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + PRE_IO + READ_BYTE_F(adr, dst) + res = dst - src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0x9320: +case 0x9520: +case 0x9720: +case 0x9920: +case 0x9B20: +case 0x9D20: +case 0x9F20: +case 0x9121: +case 0x9321: +case 0x9521: +case 0x9721: +case 0x9921: +case 0x9B21: +case 0x9D21: +case 0x9F21: +case 0x9122: +case 0x9322: +case 0x9522: +case 0x9722: +case 0x9922: +case 0x9B22: +case 0x9D22: +case 0x9F22: +case 0x9123: +case 0x9323: +case 0x9523: +case 0x9723: +case 0x9923: +case 0x9B23: +case 0x9D23: +case 0x9F23: +case 0x9124: +case 0x9324: +case 0x9524: +case 0x9724: +case 0x9924: +case 0x9B24: +case 0x9D24: +case 0x9F24: +case 0x9125: +case 0x9325: +case 0x9525: +case 0x9725: +case 0x9925: +case 0x9B25: +case 0x9D25: +case 0x9F25: +case 0x9126: +case 0x9326: +case 0x9526: +case 0x9726: +case 0x9926: +case 0x9B26: +case 0x9D26: +case 0x9F26: + +// SUBDa +case 0x9120: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_BYTE_F(adr, dst) + res = dst - src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(14) +case 0x9328: +case 0x9528: +case 0x9728: +case 0x9928: +case 0x9B28: +case 0x9D28: +case 0x9F28: +case 0x9129: +case 0x9329: +case 0x9529: +case 0x9729: +case 0x9929: +case 0x9B29: +case 0x9D29: +case 0x9F29: +case 0x912A: +case 0x932A: +case 0x952A: +case 0x972A: +case 0x992A: +case 0x9B2A: +case 0x9D2A: +case 0x9F2A: +case 0x912B: +case 0x932B: +case 0x952B: +case 0x972B: +case 0x992B: +case 0x9B2B: +case 0x9D2B: +case 0x9F2B: +case 0x912C: +case 0x932C: +case 0x952C: +case 0x972C: +case 0x992C: +case 0x9B2C: +case 0x9D2C: +case 0x9F2C: +case 0x912D: +case 0x932D: +case 0x952D: +case 0x972D: +case 0x992D: +case 0x9B2D: +case 0x9D2D: +case 0x9F2D: +case 0x912E: +case 0x932E: +case 0x952E: +case 0x972E: +case 0x992E: +case 0x9B2E: +case 0x9D2E: +case 0x9F2E: +case 0x912F: +case 0x932F: +case 0x952F: +case 0x972F: +case 0x992F: +case 0x9B2F: +case 0x9D2F: +case 0x9F2F: + +// SUBDa +case 0x9128: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, dst) + res = dst - src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0x9330: +case 0x9530: +case 0x9730: +case 0x9930: +case 0x9B30: +case 0x9D30: +case 0x9F30: +case 0x9131: +case 0x9331: +case 0x9531: +case 0x9731: +case 0x9931: +case 0x9B31: +case 0x9D31: +case 0x9F31: +case 0x9132: +case 0x9332: +case 0x9532: +case 0x9732: +case 0x9932: +case 0x9B32: +case 0x9D32: +case 0x9F32: +case 0x9133: +case 0x9333: +case 0x9533: +case 0x9733: +case 0x9933: +case 0x9B33: +case 0x9D33: +case 0x9F33: +case 0x9134: +case 0x9334: +case 0x9534: +case 0x9734: +case 0x9934: +case 0x9B34: +case 0x9D34: +case 0x9F34: +case 0x9135: +case 0x9335: +case 0x9535: +case 0x9735: +case 0x9935: +case 0x9B35: +case 0x9D35: +case 0x9F35: +case 0x9136: +case 0x9336: +case 0x9536: +case 0x9736: +case 0x9936: +case 0x9B36: +case 0x9D36: +case 0x9F36: +case 0x9137: +case 0x9337: +case 0x9537: +case 0x9737: +case 0x9937: +case 0x9B37: +case 0x9D37: +case 0x9F37: + +// SUBDa +case 0x9130: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, dst) + res = dst - src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) +case 0x9338: +case 0x9538: +case 0x9738: +case 0x9938: +case 0x9B38: +case 0x9D38: +case 0x9F38: + +// SUBDa +case 0x9138: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, dst) + res = dst - src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0x9339: +case 0x9539: +case 0x9739: +case 0x9939: +case 0x9B39: +case 0x9D39: +case 0x9F39: + +// SUBDa +case 0x9139: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_BYTE_F(adr, dst) + res = dst - src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(20) +case 0x931F: +case 0x951F: +case 0x971F: +case 0x991F: +case 0x9B1F: +case 0x9D1F: +case 0x9F1F: + +// SUBDa +case 0x911F: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_BYTE_F(adr, dst) + res = dst - src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0x9327: +case 0x9527: +case 0x9727: +case 0x9927: +case 0x9B27: +case 0x9D27: +case 0x9F27: + +// SUBDa +case 0x9127: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_BYTE_F(adr, dst) + res = dst - src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(14) +case 0x9350: +case 0x9550: +case 0x9750: +case 0x9950: +case 0x9B50: +case 0x9D50: +case 0x9F50: +case 0x9151: +case 0x9351: +case 0x9551: +case 0x9751: +case 0x9951: +case 0x9B51: +case 0x9D51: +case 0x9F51: +case 0x9152: +case 0x9352: +case 0x9552: +case 0x9752: +case 0x9952: +case 0x9B52: +case 0x9D52: +case 0x9F52: +case 0x9153: +case 0x9353: +case 0x9553: +case 0x9753: +case 0x9953: +case 0x9B53: +case 0x9D53: +case 0x9F53: +case 0x9154: +case 0x9354: +case 0x9554: +case 0x9754: +case 0x9954: +case 0x9B54: +case 0x9D54: +case 0x9F54: +case 0x9155: +case 0x9355: +case 0x9555: +case 0x9755: +case 0x9955: +case 0x9B55: +case 0x9D55: +case 0x9F55: +case 0x9156: +case 0x9356: +case 0x9556: +case 0x9756: +case 0x9956: +case 0x9B56: +case 0x9D56: +case 0x9F56: +case 0x9157: +case 0x9357: +case 0x9557: +case 0x9757: +case 0x9957: +case 0x9B57: +case 0x9D57: +case 0x9F57: + +// SUBDa +case 0x9150: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (u16)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_WORD_F(adr, dst) + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0x9358: +case 0x9558: +case 0x9758: +case 0x9958: +case 0x9B58: +case 0x9D58: +case 0x9F58: +case 0x9159: +case 0x9359: +case 0x9559: +case 0x9759: +case 0x9959: +case 0x9B59: +case 0x9D59: +case 0x9F59: +case 0x915A: +case 0x935A: +case 0x955A: +case 0x975A: +case 0x995A: +case 0x9B5A: +case 0x9D5A: +case 0x9F5A: +case 0x915B: +case 0x935B: +case 0x955B: +case 0x975B: +case 0x995B: +case 0x9B5B: +case 0x9D5B: +case 0x9F5B: +case 0x915C: +case 0x935C: +case 0x955C: +case 0x975C: +case 0x995C: +case 0x9B5C: +case 0x9D5C: +case 0x9F5C: +case 0x915D: +case 0x935D: +case 0x955D: +case 0x975D: +case 0x995D: +case 0x9B5D: +case 0x9D5D: +case 0x9F5D: +case 0x915E: +case 0x935E: +case 0x955E: +case 0x975E: +case 0x995E: +case 0x9B5E: +case 0x9D5E: +case 0x9F5E: + +// SUBDa +case 0x9158: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (u16)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 2; + PRE_IO + READ_WORD_F(adr, dst) + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0x9360: +case 0x9560: +case 0x9760: +case 0x9960: +case 0x9B60: +case 0x9D60: +case 0x9F60: +case 0x9161: +case 0x9361: +case 0x9561: +case 0x9761: +case 0x9961: +case 0x9B61: +case 0x9D61: +case 0x9F61: +case 0x9162: +case 0x9362: +case 0x9562: +case 0x9762: +case 0x9962: +case 0x9B62: +case 0x9D62: +case 0x9F62: +case 0x9163: +case 0x9363: +case 0x9563: +case 0x9763: +case 0x9963: +case 0x9B63: +case 0x9D63: +case 0x9F63: +case 0x9164: +case 0x9364: +case 0x9564: +case 0x9764: +case 0x9964: +case 0x9B64: +case 0x9D64: +case 0x9F64: +case 0x9165: +case 0x9365: +case 0x9565: +case 0x9765: +case 0x9965: +case 0x9B65: +case 0x9D65: +case 0x9F65: +case 0x9166: +case 0x9366: +case 0x9566: +case 0x9766: +case 0x9966: +case 0x9B66: +case 0x9D66: +case 0x9F66: + +// SUBDa +case 0x9160: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (u16)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7] - 2; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_WORD_F(adr, dst) + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(14) +case 0x9368: +case 0x9568: +case 0x9768: +case 0x9968: +case 0x9B68: +case 0x9D68: +case 0x9F68: +case 0x9169: +case 0x9369: +case 0x9569: +case 0x9769: +case 0x9969: +case 0x9B69: +case 0x9D69: +case 0x9F69: +case 0x916A: +case 0x936A: +case 0x956A: +case 0x976A: +case 0x996A: +case 0x9B6A: +case 0x9D6A: +case 0x9F6A: +case 0x916B: +case 0x936B: +case 0x956B: +case 0x976B: +case 0x996B: +case 0x9B6B: +case 0x9D6B: +case 0x9F6B: +case 0x916C: +case 0x936C: +case 0x956C: +case 0x976C: +case 0x996C: +case 0x9B6C: +case 0x9D6C: +case 0x9F6C: +case 0x916D: +case 0x936D: +case 0x956D: +case 0x976D: +case 0x996D: +case 0x9B6D: +case 0x9D6D: +case 0x9F6D: +case 0x916E: +case 0x936E: +case 0x956E: +case 0x976E: +case 0x996E: +case 0x9B6E: +case 0x9D6E: +case 0x9F6E: +case 0x916F: +case 0x936F: +case 0x956F: +case 0x976F: +case 0x996F: +case 0x9B6F: +case 0x9D6F: +case 0x9F6F: + +// SUBDa +case 0x9168: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (u16)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, dst) + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0x9370: +case 0x9570: +case 0x9770: +case 0x9970: +case 0x9B70: +case 0x9D70: +case 0x9F70: +case 0x9171: +case 0x9371: +case 0x9571: +case 0x9771: +case 0x9971: +case 0x9B71: +case 0x9D71: +case 0x9F71: +case 0x9172: +case 0x9372: +case 0x9572: +case 0x9772: +case 0x9972: +case 0x9B72: +case 0x9D72: +case 0x9F72: +case 0x9173: +case 0x9373: +case 0x9573: +case 0x9773: +case 0x9973: +case 0x9B73: +case 0x9D73: +case 0x9F73: +case 0x9174: +case 0x9374: +case 0x9574: +case 0x9774: +case 0x9974: +case 0x9B74: +case 0x9D74: +case 0x9F74: +case 0x9175: +case 0x9375: +case 0x9575: +case 0x9775: +case 0x9975: +case 0x9B75: +case 0x9D75: +case 0x9F75: +case 0x9176: +case 0x9376: +case 0x9576: +case 0x9776: +case 0x9976: +case 0x9B76: +case 0x9D76: +case 0x9F76: +case 0x9177: +case 0x9377: +case 0x9577: +case 0x9777: +case 0x9977: +case 0x9B77: +case 0x9D77: +case 0x9F77: + +// SUBDa +case 0x9170: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (u16)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, dst) + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(18) +case 0x9378: +case 0x9578: +case 0x9778: +case 0x9978: +case 0x9B78: +case 0x9D78: +case 0x9F78: + +// SUBDa +case 0x9178: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (u16)CPU->D[(Opcode >> 9) & 7]; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, dst) + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0x9379: +case 0x9579: +case 0x9779: +case 0x9979: +case 0x9B79: +case 0x9D79: +case 0x9F79: + +// SUBDa +case 0x9179: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (u16)CPU->D[(Opcode >> 9) & 7]; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_WORD_F(adr, dst) + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(20) +case 0x935F: +case 0x955F: +case 0x975F: +case 0x995F: +case 0x9B5F: +case 0x9D5F: +case 0x9F5F: + +// SUBDa +case 0x915F: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (u16)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_WORD_F(adr, dst) + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0x9367: +case 0x9567: +case 0x9767: +case 0x9967: +case 0x9B67: +case 0x9D67: +case 0x9F67: + +// SUBDa +case 0x9167: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (u16)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_WORD_F(adr, dst) + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(14) +case 0x9390: +case 0x9590: +case 0x9790: +case 0x9990: +case 0x9B90: +case 0x9D90: +case 0x9F90: +case 0x9191: +case 0x9391: +case 0x9591: +case 0x9791: +case 0x9991: +case 0x9B91: +case 0x9D91: +case 0x9F91: +case 0x9192: +case 0x9392: +case 0x9592: +case 0x9792: +case 0x9992: +case 0x9B92: +case 0x9D92: +case 0x9F92: +case 0x9193: +case 0x9393: +case 0x9593: +case 0x9793: +case 0x9993: +case 0x9B93: +case 0x9D93: +case 0x9F93: +case 0x9194: +case 0x9394: +case 0x9594: +case 0x9794: +case 0x9994: +case 0x9B94: +case 0x9D94: +case 0x9F94: +case 0x9195: +case 0x9395: +case 0x9595: +case 0x9795: +case 0x9995: +case 0x9B95: +case 0x9D95: +case 0x9F95: +case 0x9196: +case 0x9396: +case 0x9596: +case 0x9796: +case 0x9996: +case 0x9B96: +case 0x9D96: +case 0x9F96: +case 0x9197: +case 0x9397: +case 0x9597: +case 0x9797: +case 0x9997: +case 0x9B97: +case 0x9D97: +case 0x9F97: + +// SUBDa +case 0x9190: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (u32)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_LONG_F(adr, dst) + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(20) +case 0x9398: +case 0x9598: +case 0x9798: +case 0x9998: +case 0x9B98: +case 0x9D98: +case 0x9F98: +case 0x9199: +case 0x9399: +case 0x9599: +case 0x9799: +case 0x9999: +case 0x9B99: +case 0x9D99: +case 0x9F99: +case 0x919A: +case 0x939A: +case 0x959A: +case 0x979A: +case 0x999A: +case 0x9B9A: +case 0x9D9A: +case 0x9F9A: +case 0x919B: +case 0x939B: +case 0x959B: +case 0x979B: +case 0x999B: +case 0x9B9B: +case 0x9D9B: +case 0x9F9B: +case 0x919C: +case 0x939C: +case 0x959C: +case 0x979C: +case 0x999C: +case 0x9B9C: +case 0x9D9C: +case 0x9F9C: +case 0x919D: +case 0x939D: +case 0x959D: +case 0x979D: +case 0x999D: +case 0x9B9D: +case 0x9D9D: +case 0x9F9D: +case 0x919E: +case 0x939E: +case 0x959E: +case 0x979E: +case 0x999E: +case 0x9B9E: +case 0x9D9E: +case 0x9F9E: + +// SUBDa +case 0x9198: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (u32)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 4; + PRE_IO + READ_LONG_F(adr, dst) + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(20) +case 0x93A0: +case 0x95A0: +case 0x97A0: +case 0x99A0: +case 0x9BA0: +case 0x9DA0: +case 0x9FA0: +case 0x91A1: +case 0x93A1: +case 0x95A1: +case 0x97A1: +case 0x99A1: +case 0x9BA1: +case 0x9DA1: +case 0x9FA1: +case 0x91A2: +case 0x93A2: +case 0x95A2: +case 0x97A2: +case 0x99A2: +case 0x9BA2: +case 0x9DA2: +case 0x9FA2: +case 0x91A3: +case 0x93A3: +case 0x95A3: +case 0x97A3: +case 0x99A3: +case 0x9BA3: +case 0x9DA3: +case 0x9FA3: +case 0x91A4: +case 0x93A4: +case 0x95A4: +case 0x97A4: +case 0x99A4: +case 0x9BA4: +case 0x9DA4: +case 0x9FA4: +case 0x91A5: +case 0x93A5: +case 0x95A5: +case 0x97A5: +case 0x99A5: +case 0x9BA5: +case 0x9DA5: +case 0x9FA5: +case 0x91A6: +case 0x93A6: +case 0x95A6: +case 0x97A6: +case 0x99A6: +case 0x9BA6: +case 0x9DA6: +case 0x9FA6: + +// SUBDa +case 0x91A0: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (u32)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7] - 4; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_LONG_F(adr, dst) + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(22) +case 0x93A8: +case 0x95A8: +case 0x97A8: +case 0x99A8: +case 0x9BA8: +case 0x9DA8: +case 0x9FA8: +case 0x91A9: +case 0x93A9: +case 0x95A9: +case 0x97A9: +case 0x99A9: +case 0x9BA9: +case 0x9DA9: +case 0x9FA9: +case 0x91AA: +case 0x93AA: +case 0x95AA: +case 0x97AA: +case 0x99AA: +case 0x9BAA: +case 0x9DAA: +case 0x9FAA: +case 0x91AB: +case 0x93AB: +case 0x95AB: +case 0x97AB: +case 0x99AB: +case 0x9BAB: +case 0x9DAB: +case 0x9FAB: +case 0x91AC: +case 0x93AC: +case 0x95AC: +case 0x97AC: +case 0x99AC: +case 0x9BAC: +case 0x9DAC: +case 0x9FAC: +case 0x91AD: +case 0x93AD: +case 0x95AD: +case 0x97AD: +case 0x99AD: +case 0x9BAD: +case 0x9DAD: +case 0x9FAD: +case 0x91AE: +case 0x93AE: +case 0x95AE: +case 0x97AE: +case 0x99AE: +case 0x9BAE: +case 0x9DAE: +case 0x9FAE: +case 0x91AF: +case 0x93AF: +case 0x95AF: +case 0x97AF: +case 0x99AF: +case 0x9BAF: +case 0x9DAF: +case 0x9FAF: + +// SUBDa +case 0x91A8: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (u32)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, dst) + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(24) +case 0x93B0: +case 0x95B0: +case 0x97B0: +case 0x99B0: +case 0x9BB0: +case 0x9DB0: +case 0x9FB0: +case 0x91B1: +case 0x93B1: +case 0x95B1: +case 0x97B1: +case 0x99B1: +case 0x9BB1: +case 0x9DB1: +case 0x9FB1: +case 0x91B2: +case 0x93B2: +case 0x95B2: +case 0x97B2: +case 0x99B2: +case 0x9BB2: +case 0x9DB2: +case 0x9FB2: +case 0x91B3: +case 0x93B3: +case 0x95B3: +case 0x97B3: +case 0x99B3: +case 0x9BB3: +case 0x9DB3: +case 0x9FB3: +case 0x91B4: +case 0x93B4: +case 0x95B4: +case 0x97B4: +case 0x99B4: +case 0x9BB4: +case 0x9DB4: +case 0x9FB4: +case 0x91B5: +case 0x93B5: +case 0x95B5: +case 0x97B5: +case 0x99B5: +case 0x9BB5: +case 0x9DB5: +case 0x9FB5: +case 0x91B6: +case 0x93B6: +case 0x95B6: +case 0x97B6: +case 0x99B6: +case 0x9BB6: +case 0x9DB6: +case 0x9FB6: +case 0x91B7: +case 0x93B7: +case 0x95B7: +case 0x97B7: +case 0x99B7: +case 0x9BB7: +case 0x9DB7: +case 0x9FB7: + +// SUBDa +case 0x91B0: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (u32)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_LONG_F(adr, dst) + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(26) +case 0x93B8: +case 0x95B8: +case 0x97B8: +case 0x99B8: +case 0x9BB8: +case 0x9DB8: +case 0x9FB8: + +// SUBDa +case 0x91B8: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (u32)CPU->D[(Opcode >> 9) & 7]; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, dst) + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(24) +case 0x93B9: +case 0x95B9: +case 0x97B9: +case 0x99B9: +case 0x9BB9: +case 0x9DB9: +case 0x9FB9: + +// SUBDa +case 0x91B9: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (u32)CPU->D[(Opcode >> 9) & 7]; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_LONG_F(adr, dst) + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(28) +case 0x939F: +case 0x959F: +case 0x979F: +case 0x999F: +case 0x9B9F: +case 0x9D9F: +case 0x9F9F: + +// SUBDa +case 0x919F: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (u32)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[7]; + CPU->A[7] += 4; + PRE_IO + READ_LONG_F(adr, dst) + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(20) +case 0x93A7: +case 0x95A7: +case 0x97A7: +case 0x99A7: +case 0x9BA7: +case 0x9DA7: +case 0x9FA7: + +// SUBDa +case 0x91A7: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (u32)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + PRE_IO + READ_LONG_F(adr, dst) + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(22) +case 0x9300: +case 0x9500: +case 0x9700: +case 0x9900: +case 0x9B00: +case 0x9D00: +case 0x9F00: +case 0x9101: +case 0x9301: +case 0x9501: +case 0x9701: +case 0x9901: +case 0x9B01: +case 0x9D01: +case 0x9F01: +case 0x9102: +case 0x9302: +case 0x9502: +case 0x9702: +case 0x9902: +case 0x9B02: +case 0x9D02: +case 0x9F02: +case 0x9103: +case 0x9303: +case 0x9503: +case 0x9703: +case 0x9903: +case 0x9B03: +case 0x9D03: +case 0x9F03: +case 0x9104: +case 0x9304: +case 0x9504: +case 0x9704: +case 0x9904: +case 0x9B04: +case 0x9D04: +case 0x9F04: +case 0x9105: +case 0x9305: +case 0x9505: +case 0x9705: +case 0x9905: +case 0x9B05: +case 0x9D05: +case 0x9F05: +case 0x9106: +case 0x9306: +case 0x9506: +case 0x9706: +case 0x9906: +case 0x9B06: +case 0x9D06: +case 0x9F06: +case 0x9107: +case 0x9307: +case 0x9507: +case 0x9707: +case 0x9907: +case 0x9B07: +case 0x9D07: +case 0x9F07: + +// SUBX +case 0x9100: +{ + u32 res; + pointer dst; + pointer src; + src = (u8)CPU->D[(Opcode >> 0) & 7]; + dst = (u8)CPU->D[(Opcode >> 9) & 7]; + res = dst - src - ((CPU->flag_X >> 8) & 1); + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ |= res & 0xFF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; +} +RET(4) +case 0x9340: +case 0x9540: +case 0x9740: +case 0x9940: +case 0x9B40: +case 0x9D40: +case 0x9F40: +case 0x9141: +case 0x9341: +case 0x9541: +case 0x9741: +case 0x9941: +case 0x9B41: +case 0x9D41: +case 0x9F41: +case 0x9142: +case 0x9342: +case 0x9542: +case 0x9742: +case 0x9942: +case 0x9B42: +case 0x9D42: +case 0x9F42: +case 0x9143: +case 0x9343: +case 0x9543: +case 0x9743: +case 0x9943: +case 0x9B43: +case 0x9D43: +case 0x9F43: +case 0x9144: +case 0x9344: +case 0x9544: +case 0x9744: +case 0x9944: +case 0x9B44: +case 0x9D44: +case 0x9F44: +case 0x9145: +case 0x9345: +case 0x9545: +case 0x9745: +case 0x9945: +case 0x9B45: +case 0x9D45: +case 0x9F45: +case 0x9146: +case 0x9346: +case 0x9546: +case 0x9746: +case 0x9946: +case 0x9B46: +case 0x9D46: +case 0x9F46: +case 0x9147: +case 0x9347: +case 0x9547: +case 0x9747: +case 0x9947: +case 0x9B47: +case 0x9D47: +case 0x9F47: + +// SUBX +case 0x9140: +{ + u32 res; + pointer dst; + pointer src; + src = (u16)CPU->D[(Opcode >> 0) & 7]; + dst = (u16)CPU->D[(Opcode >> 9) & 7]; + res = dst - src - ((CPU->flag_X >> 8) & 1); + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ |= res & 0xFFFF; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; +} +RET(4) +case 0x9380: +case 0x9580: +case 0x9780: +case 0x9980: +case 0x9B80: +case 0x9D80: +case 0x9F80: +case 0x9181: +case 0x9381: +case 0x9581: +case 0x9781: +case 0x9981: +case 0x9B81: +case 0x9D81: +case 0x9F81: +case 0x9182: +case 0x9382: +case 0x9582: +case 0x9782: +case 0x9982: +case 0x9B82: +case 0x9D82: +case 0x9F82: +case 0x9183: +case 0x9383: +case 0x9583: +case 0x9783: +case 0x9983: +case 0x9B83: +case 0x9D83: +case 0x9F83: +case 0x9184: +case 0x9384: +case 0x9584: +case 0x9784: +case 0x9984: +case 0x9B84: +case 0x9D84: +case 0x9F84: +case 0x9185: +case 0x9385: +case 0x9585: +case 0x9785: +case 0x9985: +case 0x9B85: +case 0x9D85: +case 0x9F85: +case 0x9186: +case 0x9386: +case 0x9586: +case 0x9786: +case 0x9986: +case 0x9B86: +case 0x9D86: +case 0x9F86: +case 0x9187: +case 0x9387: +case 0x9587: +case 0x9787: +case 0x9987: +case 0x9B87: +case 0x9D87: +case 0x9F87: + +// SUBX +case 0x9180: +{ + u32 res; + pointer dst; + pointer src; + src = (u32)CPU->D[(Opcode >> 0) & 7]; + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + res = dst - src - ((CPU->flag_X >> 8) & 1); + CPU->flag_notZ |= res; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; +} +RET(8) +case 0x9308: +case 0x9508: +case 0x9708: +case 0x9908: +case 0x9B08: +case 0x9D08: +case 0x9109: +case 0x9309: +case 0x9509: +case 0x9709: +case 0x9909: +case 0x9B09: +case 0x9D09: +case 0x910A: +case 0x930A: +case 0x950A: +case 0x970A: +case 0x990A: +case 0x9B0A: +case 0x9D0A: +case 0x910B: +case 0x930B: +case 0x950B: +case 0x970B: +case 0x990B: +case 0x9B0B: +case 0x9D0B: +case 0x910C: +case 0x930C: +case 0x950C: +case 0x970C: +case 0x990C: +case 0x9B0C: +case 0x9D0C: +case 0x910D: +case 0x930D: +case 0x950D: +case 0x970D: +case 0x990D: +case 0x9B0D: +case 0x9D0D: +case 0x910E: +case 0x930E: +case 0x950E: +case 0x970E: +case 0x990E: +case 0x9B0E: +case 0x9D0E: + +// SUBXM +case 0x9108: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_BYTE_F(adr, src) + adr = CPU->A[(Opcode >> 9) & 7] - 1; + CPU->A[(Opcode >> 9) & 7] = adr; + READ_BYTE_F(adr, dst) + res = dst - src - ((CPU->flag_X >> 8) & 1); + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ |= res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) +case 0x9348: +case 0x9548: +case 0x9748: +case 0x9948: +case 0x9B48: +case 0x9D48: +case 0x9149: +case 0x9349: +case 0x9549: +case 0x9749: +case 0x9949: +case 0x9B49: +case 0x9D49: +case 0x914A: +case 0x934A: +case 0x954A: +case 0x974A: +case 0x994A: +case 0x9B4A: +case 0x9D4A: +case 0x914B: +case 0x934B: +case 0x954B: +case 0x974B: +case 0x994B: +case 0x9B4B: +case 0x9D4B: +case 0x914C: +case 0x934C: +case 0x954C: +case 0x974C: +case 0x994C: +case 0x9B4C: +case 0x9D4C: +case 0x914D: +case 0x934D: +case 0x954D: +case 0x974D: +case 0x994D: +case 0x9B4D: +case 0x9D4D: +case 0x914E: +case 0x934E: +case 0x954E: +case 0x974E: +case 0x994E: +case 0x9B4E: +case 0x9D4E: + +// SUBXM +case 0x9148: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 2; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_WORD_F(adr, src) + adr = CPU->A[(Opcode >> 9) & 7] - 2; + CPU->A[(Opcode >> 9) & 7] = adr; + READ_WORD_F(adr, dst) + res = dst - src - ((CPU->flag_X >> 8) & 1); + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ |= res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(18) +case 0x9388: +case 0x9588: +case 0x9788: +case 0x9988: +case 0x9B88: +case 0x9D88: +case 0x9189: +case 0x9389: +case 0x9589: +case 0x9789: +case 0x9989: +case 0x9B89: +case 0x9D89: +case 0x918A: +case 0x938A: +case 0x958A: +case 0x978A: +case 0x998A: +case 0x9B8A: +case 0x9D8A: +case 0x918B: +case 0x938B: +case 0x958B: +case 0x978B: +case 0x998B: +case 0x9B8B: +case 0x9D8B: +case 0x918C: +case 0x938C: +case 0x958C: +case 0x978C: +case 0x998C: +case 0x9B8C: +case 0x9D8C: +case 0x918D: +case 0x938D: +case 0x958D: +case 0x978D: +case 0x998D: +case 0x9B8D: +case 0x9D8D: +case 0x918E: +case 0x938E: +case 0x958E: +case 0x978E: +case 0x998E: +case 0x9B8E: +case 0x9D8E: + +// SUBXM +case 0x9188: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 4; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_LONG_F(adr, src) + adr = CPU->A[(Opcode >> 9) & 7] - 4; + CPU->A[(Opcode >> 9) & 7] = adr; + READ_LONG_F(adr, dst) + res = dst - src - ((CPU->flag_X >> 8) & 1); + CPU->flag_notZ |= res; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(30) +case 0x930F: +case 0x950F: +case 0x970F: +case 0x990F: +case 0x9B0F: +case 0x9D0F: + +// SUBX7M +case 0x910F: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_BYTE_F(adr, src) + adr = CPU->A[(Opcode >> 9) & 7] - 1; + CPU->A[(Opcode >> 9) & 7] = adr; + READ_BYTE_F(adr, dst) + res = dst - src - ((CPU->flag_X >> 8) & 1); + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ |= res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) +case 0x934F: +case 0x954F: +case 0x974F: +case 0x994F: +case 0x9B4F: +case 0x9D4F: + +// SUBX7M +case 0x914F: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_WORD_F(adr, src) + adr = CPU->A[(Opcode >> 9) & 7] - 2; + CPU->A[(Opcode >> 9) & 7] = adr; + READ_WORD_F(adr, dst) + res = dst - src - ((CPU->flag_X >> 8) & 1); + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ |= res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(18) +case 0x938F: +case 0x958F: +case 0x978F: +case 0x998F: +case 0x9B8F: +case 0x9D8F: + +// SUBX7M +case 0x918F: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + PRE_IO + READ_LONG_F(adr, src) + adr = CPU->A[(Opcode >> 9) & 7] - 4; + CPU->A[(Opcode >> 9) & 7] = adr; + READ_LONG_F(adr, dst) + res = dst - src - ((CPU->flag_X >> 8) & 1); + CPU->flag_notZ |= res; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(30) +case 0x9F09: +case 0x9F0A: +case 0x9F0B: +case 0x9F0C: +case 0x9F0D: +case 0x9F0E: + +// SUBXM7 +case 0x9F08: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_BYTE_F(adr, src) + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + READ_BYTE_F(adr, dst) + res = dst - src - ((CPU->flag_X >> 8) & 1); + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ |= res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) +case 0x9F49: +case 0x9F4A: +case 0x9F4B: +case 0x9F4C: +case 0x9F4D: +case 0x9F4E: + +// SUBXM7 +case 0x9F48: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 2; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_WORD_F(adr, src) + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + READ_WORD_F(adr, dst) + res = dst - src - ((CPU->flag_X >> 8) & 1); + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ |= res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(18) +case 0x9F89: +case 0x9F8A: +case 0x9F8B: +case 0x9F8C: +case 0x9F8D: +case 0x9F8E: + +// SUBXM7 +case 0x9F88: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 4; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_LONG_F(adr, src) + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + READ_LONG_F(adr, dst) + res = dst - src - ((CPU->flag_X >> 8) & 1); + CPU->flag_notZ |= res; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(30) + +// SUBX7M7 +case 0x9F0F: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_BYTE_F(adr, src) + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + READ_BYTE_F(adr, dst) + res = dst - src - ((CPU->flag_X >> 8) & 1); + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ |= res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) + +// SUBX7M7 +case 0x9F4F: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_WORD_F(adr, src) + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + READ_WORD_F(adr, dst) + res = dst - src - ((CPU->flag_X >> 8) & 1); + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ |= res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(18) + +// SUBX7M7 +case 0x9F8F: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + PRE_IO + READ_LONG_F(adr, src) + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + READ_LONG_F(adr, dst) + res = dst - src - ((CPU->flag_X >> 8) & 1); + CPU->flag_notZ |= res; + CPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(30) +case 0x92C0: +case 0x94C0: +case 0x96C0: +case 0x98C0: +case 0x9AC0: +case 0x9CC0: +case 0x9EC0: +case 0x90C1: +case 0x92C1: +case 0x94C1: +case 0x96C1: +case 0x98C1: +case 0x9AC1: +case 0x9CC1: +case 0x9EC1: +case 0x90C2: +case 0x92C2: +case 0x94C2: +case 0x96C2: +case 0x98C2: +case 0x9AC2: +case 0x9CC2: +case 0x9EC2: +case 0x90C3: +case 0x92C3: +case 0x94C3: +case 0x96C3: +case 0x98C3: +case 0x9AC3: +case 0x9CC3: +case 0x9EC3: +case 0x90C4: +case 0x92C4: +case 0x94C4: +case 0x96C4: +case 0x98C4: +case 0x9AC4: +case 0x9CC4: +case 0x9EC4: +case 0x90C5: +case 0x92C5: +case 0x94C5: +case 0x96C5: +case 0x98C5: +case 0x9AC5: +case 0x9CC5: +case 0x9EC5: +case 0x90C6: +case 0x92C6: +case 0x94C6: +case 0x96C6: +case 0x98C6: +case 0x9AC6: +case 0x9CC6: +case 0x9EC6: +case 0x90C7: +case 0x92C7: +case 0x94C7: +case 0x96C7: +case 0x98C7: +case 0x9AC7: +case 0x9CC7: +case 0x9EC7: + +// SUBA +case 0x90C0: +{ + u32 res; + pointer dst; + pointer src; + src = (s32)(s16)CPU->D[(Opcode >> 0) & 7]; + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst - src; + CPU->A[(Opcode >> 9) & 7] = res; +} +RET(8) +case 0x92C8: +case 0x94C8: +case 0x96C8: +case 0x98C8: +case 0x9AC8: +case 0x9CC8: +case 0x9EC8: +case 0x90C9: +case 0x92C9: +case 0x94C9: +case 0x96C9: +case 0x98C9: +case 0x9AC9: +case 0x9CC9: +case 0x9EC9: +case 0x90CA: +case 0x92CA: +case 0x94CA: +case 0x96CA: +case 0x98CA: +case 0x9ACA: +case 0x9CCA: +case 0x9ECA: +case 0x90CB: +case 0x92CB: +case 0x94CB: +case 0x96CB: +case 0x98CB: +case 0x9ACB: +case 0x9CCB: +case 0x9ECB: +case 0x90CC: +case 0x92CC: +case 0x94CC: +case 0x96CC: +case 0x98CC: +case 0x9ACC: +case 0x9CCC: +case 0x9ECC: +case 0x90CD: +case 0x92CD: +case 0x94CD: +case 0x96CD: +case 0x98CD: +case 0x9ACD: +case 0x9CCD: +case 0x9ECD: +case 0x90CE: +case 0x92CE: +case 0x94CE: +case 0x96CE: +case 0x98CE: +case 0x9ACE: +case 0x9CCE: +case 0x9ECE: +case 0x90CF: +case 0x92CF: +case 0x94CF: +case 0x96CF: +case 0x98CF: +case 0x9ACF: +case 0x9CCF: +case 0x9ECF: + +// SUBA +case 0x90C8: +{ + u32 res; + pointer dst; + pointer src; + src = (s32)(s16)CPU->A[(Opcode >> 0) & 7]; + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst - src; + CPU->A[(Opcode >> 9) & 7] = res; +} +RET(8) +case 0x92D0: +case 0x94D0: +case 0x96D0: +case 0x98D0: +case 0x9AD0: +case 0x9CD0: +case 0x9ED0: +case 0x90D1: +case 0x92D1: +case 0x94D1: +case 0x96D1: +case 0x98D1: +case 0x9AD1: +case 0x9CD1: +case 0x9ED1: +case 0x90D2: +case 0x92D2: +case 0x94D2: +case 0x96D2: +case 0x98D2: +case 0x9AD2: +case 0x9CD2: +case 0x9ED2: +case 0x90D3: +case 0x92D3: +case 0x94D3: +case 0x96D3: +case 0x98D3: +case 0x9AD3: +case 0x9CD3: +case 0x9ED3: +case 0x90D4: +case 0x92D4: +case 0x94D4: +case 0x96D4: +case 0x98D4: +case 0x9AD4: +case 0x9CD4: +case 0x9ED4: +case 0x90D5: +case 0x92D5: +case 0x94D5: +case 0x96D5: +case 0x98D5: +case 0x9AD5: +case 0x9CD5: +case 0x9ED5: +case 0x90D6: +case 0x92D6: +case 0x94D6: +case 0x96D6: +case 0x98D6: +case 0x9AD6: +case 0x9CD6: +case 0x9ED6: +case 0x90D7: +case 0x92D7: +case 0x94D7: +case 0x96D7: +case 0x98D7: +case 0x9AD7: +case 0x9CD7: +case 0x9ED7: + +// SUBA +case 0x90D0: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READSX_WORD_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst - src; + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(12) +case 0x92D8: +case 0x94D8: +case 0x96D8: +case 0x98D8: +case 0x9AD8: +case 0x9CD8: +case 0x9ED8: +case 0x90D9: +case 0x92D9: +case 0x94D9: +case 0x96D9: +case 0x98D9: +case 0x9AD9: +case 0x9CD9: +case 0x9ED9: +case 0x90DA: +case 0x92DA: +case 0x94DA: +case 0x96DA: +case 0x98DA: +case 0x9ADA: +case 0x9CDA: +case 0x9EDA: +case 0x90DB: +case 0x92DB: +case 0x94DB: +case 0x96DB: +case 0x98DB: +case 0x9ADB: +case 0x9CDB: +case 0x9EDB: +case 0x90DC: +case 0x92DC: +case 0x94DC: +case 0x96DC: +case 0x98DC: +case 0x9ADC: +case 0x9CDC: +case 0x9EDC: +case 0x90DD: +case 0x92DD: +case 0x94DD: +case 0x96DD: +case 0x98DD: +case 0x9ADD: +case 0x9CDD: +case 0x9EDD: +case 0x90DE: +case 0x92DE: +case 0x94DE: +case 0x96DE: +case 0x98DE: +case 0x9ADE: +case 0x9CDE: +case 0x9EDE: + +// SUBA +case 0x90D8: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 2; + PRE_IO + READSX_WORD_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst - src; + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(12) +case 0x92E0: +case 0x94E0: +case 0x96E0: +case 0x98E0: +case 0x9AE0: +case 0x9CE0: +case 0x9EE0: +case 0x90E1: +case 0x92E1: +case 0x94E1: +case 0x96E1: +case 0x98E1: +case 0x9AE1: +case 0x9CE1: +case 0x9EE1: +case 0x90E2: +case 0x92E2: +case 0x94E2: +case 0x96E2: +case 0x98E2: +case 0x9AE2: +case 0x9CE2: +case 0x9EE2: +case 0x90E3: +case 0x92E3: +case 0x94E3: +case 0x96E3: +case 0x98E3: +case 0x9AE3: +case 0x9CE3: +case 0x9EE3: +case 0x90E4: +case 0x92E4: +case 0x94E4: +case 0x96E4: +case 0x98E4: +case 0x9AE4: +case 0x9CE4: +case 0x9EE4: +case 0x90E5: +case 0x92E5: +case 0x94E5: +case 0x96E5: +case 0x98E5: +case 0x9AE5: +case 0x9CE5: +case 0x9EE5: +case 0x90E6: +case 0x92E6: +case 0x94E6: +case 0x96E6: +case 0x98E6: +case 0x9AE6: +case 0x9CE6: +case 0x9EE6: + +// SUBA +case 0x90E0: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 2; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READSX_WORD_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst - src; + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(14) +case 0x92E8: +case 0x94E8: +case 0x96E8: +case 0x98E8: +case 0x9AE8: +case 0x9CE8: +case 0x9EE8: +case 0x90E9: +case 0x92E9: +case 0x94E9: +case 0x96E9: +case 0x98E9: +case 0x9AE9: +case 0x9CE9: +case 0x9EE9: +case 0x90EA: +case 0x92EA: +case 0x94EA: +case 0x96EA: +case 0x98EA: +case 0x9AEA: +case 0x9CEA: +case 0x9EEA: +case 0x90EB: +case 0x92EB: +case 0x94EB: +case 0x96EB: +case 0x98EB: +case 0x9AEB: +case 0x9CEB: +case 0x9EEB: +case 0x90EC: +case 0x92EC: +case 0x94EC: +case 0x96EC: +case 0x98EC: +case 0x9AEC: +case 0x9CEC: +case 0x9EEC: +case 0x90ED: +case 0x92ED: +case 0x94ED: +case 0x96ED: +case 0x98ED: +case 0x9AED: +case 0x9CED: +case 0x9EED: +case 0x90EE: +case 0x92EE: +case 0x94EE: +case 0x96EE: +case 0x98EE: +case 0x9AEE: +case 0x9CEE: +case 0x9EEE: +case 0x90EF: +case 0x92EF: +case 0x94EF: +case 0x96EF: +case 0x98EF: +case 0x9AEF: +case 0x9CEF: +case 0x9EEF: + +// SUBA +case 0x90E8: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READSX_WORD_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst - src; + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(16) +case 0x92F0: +case 0x94F0: +case 0x96F0: +case 0x98F0: +case 0x9AF0: +case 0x9CF0: +case 0x9EF0: +case 0x90F1: +case 0x92F1: +case 0x94F1: +case 0x96F1: +case 0x98F1: +case 0x9AF1: +case 0x9CF1: +case 0x9EF1: +case 0x90F2: +case 0x92F2: +case 0x94F2: +case 0x96F2: +case 0x98F2: +case 0x9AF2: +case 0x9CF2: +case 0x9EF2: +case 0x90F3: +case 0x92F3: +case 0x94F3: +case 0x96F3: +case 0x98F3: +case 0x9AF3: +case 0x9CF3: +case 0x9EF3: +case 0x90F4: +case 0x92F4: +case 0x94F4: +case 0x96F4: +case 0x98F4: +case 0x9AF4: +case 0x9CF4: +case 0x9EF4: +case 0x90F5: +case 0x92F5: +case 0x94F5: +case 0x96F5: +case 0x98F5: +case 0x9AF5: +case 0x9CF5: +case 0x9EF5: +case 0x90F6: +case 0x92F6: +case 0x94F6: +case 0x96F6: +case 0x98F6: +case 0x9AF6: +case 0x9CF6: +case 0x9EF6: +case 0x90F7: +case 0x92F7: +case 0x94F7: +case 0x96F7: +case 0x98F7: +case 0x9AF7: +case 0x9CF7: +case 0x9EF7: + +// SUBA +case 0x90F0: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READSX_WORD_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst - src; + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(18) +case 0x92F8: +case 0x94F8: +case 0x96F8: +case 0x98F8: +case 0x9AF8: +case 0x9CF8: +case 0x9EF8: + +// SUBA +case 0x90F8: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READSX_WORD_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst - src; + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(16) +case 0x92F9: +case 0x94F9: +case 0x96F9: +case 0x98F9: +case 0x9AF9: +case 0x9CF9: +case 0x9EF9: + +// SUBA +case 0x90F9: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READSX_WORD_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst - src; + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(20) +case 0x92FA: +case 0x94FA: +case 0x96FA: +case 0x98FA: +case 0x9AFA: +case 0x9CFA: +case 0x9EFA: + +// SUBA +case 0x90FA: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READSX_WORD_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst - src; + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(16) +case 0x92FB: +case 0x94FB: +case 0x96FB: +case 0x98FB: +case 0x9AFB: +case 0x9CFB: +case 0x9EFB: + +// SUBA +case 0x90FB: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READSX_WORD_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst - src; + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(18) +case 0x92FC: +case 0x94FC: +case 0x96FC: +case 0x98FC: +case 0x9AFC: +case 0x9CFC: +case 0x9EFC: + +// SUBA +case 0x90FC: +{ + u32 res; + pointer dst; + pointer src; + src = (s32)(s16)FETCH_WORD; + PC += 2; + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst - src; + CPU->A[(Opcode >> 9) & 7] = res; +} +RET(12) +case 0x92DF: +case 0x94DF: +case 0x96DF: +case 0x98DF: +case 0x9ADF: +case 0x9CDF: +case 0x9EDF: + +// SUBA +case 0x90DF: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READSX_WORD_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst - src; + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(12) +case 0x92E7: +case 0x94E7: +case 0x96E7: +case 0x98E7: +case 0x9AE7: +case 0x9CE7: +case 0x9EE7: + +// SUBA +case 0x90E7: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READSX_WORD_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst - src; + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(14) +case 0x93C0: +case 0x95C0: +case 0x97C0: +case 0x99C0: +case 0x9BC0: +case 0x9DC0: +case 0x9FC0: +case 0x91C1: +case 0x93C1: +case 0x95C1: +case 0x97C1: +case 0x99C1: +case 0x9BC1: +case 0x9DC1: +case 0x9FC1: +case 0x91C2: +case 0x93C2: +case 0x95C2: +case 0x97C2: +case 0x99C2: +case 0x9BC2: +case 0x9DC2: +case 0x9FC2: +case 0x91C3: +case 0x93C3: +case 0x95C3: +case 0x97C3: +case 0x99C3: +case 0x9BC3: +case 0x9DC3: +case 0x9FC3: +case 0x91C4: +case 0x93C4: +case 0x95C4: +case 0x97C4: +case 0x99C4: +case 0x9BC4: +case 0x9DC4: +case 0x9FC4: +case 0x91C5: +case 0x93C5: +case 0x95C5: +case 0x97C5: +case 0x99C5: +case 0x9BC5: +case 0x9DC5: +case 0x9FC5: +case 0x91C6: +case 0x93C6: +case 0x95C6: +case 0x97C6: +case 0x99C6: +case 0x9BC6: +case 0x9DC6: +case 0x9FC6: +case 0x91C7: +case 0x93C7: +case 0x95C7: +case 0x97C7: +case 0x99C7: +case 0x9BC7: +case 0x9DC7: +case 0x9FC7: + +// SUBA +case 0x91C0: +{ + u32 res; + pointer dst; + pointer src; + src = (s32)(s32)CPU->D[(Opcode >> 0) & 7]; + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst - src; + CPU->A[(Opcode >> 9) & 7] = res; +} +RET(6) +case 0x93C8: +case 0x95C8: +case 0x97C8: +case 0x99C8: +case 0x9BC8: +case 0x9DC8: +case 0x9FC8: +case 0x91C9: +case 0x93C9: +case 0x95C9: +case 0x97C9: +case 0x99C9: +case 0x9BC9: +case 0x9DC9: +case 0x9FC9: +case 0x91CA: +case 0x93CA: +case 0x95CA: +case 0x97CA: +case 0x99CA: +case 0x9BCA: +case 0x9DCA: +case 0x9FCA: +case 0x91CB: +case 0x93CB: +case 0x95CB: +case 0x97CB: +case 0x99CB: +case 0x9BCB: +case 0x9DCB: +case 0x9FCB: +case 0x91CC: +case 0x93CC: +case 0x95CC: +case 0x97CC: +case 0x99CC: +case 0x9BCC: +case 0x9DCC: +case 0x9FCC: +case 0x91CD: +case 0x93CD: +case 0x95CD: +case 0x97CD: +case 0x99CD: +case 0x9BCD: +case 0x9DCD: +case 0x9FCD: +case 0x91CE: +case 0x93CE: +case 0x95CE: +case 0x97CE: +case 0x99CE: +case 0x9BCE: +case 0x9DCE: +case 0x9FCE: +case 0x91CF: +case 0x93CF: +case 0x95CF: +case 0x97CF: +case 0x99CF: +case 0x9BCF: +case 0x9DCF: +case 0x9FCF: + +// SUBA +case 0x91C8: +{ + u32 res; + pointer dst; + pointer src; + src = (s32)(s32)CPU->A[(Opcode >> 0) & 7]; + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst - src; + CPU->A[(Opcode >> 9) & 7] = res; +} +RET(6) +case 0x93D0: +case 0x95D0: +case 0x97D0: +case 0x99D0: +case 0x9BD0: +case 0x9DD0: +case 0x9FD0: +case 0x91D1: +case 0x93D1: +case 0x95D1: +case 0x97D1: +case 0x99D1: +case 0x9BD1: +case 0x9DD1: +case 0x9FD1: +case 0x91D2: +case 0x93D2: +case 0x95D2: +case 0x97D2: +case 0x99D2: +case 0x9BD2: +case 0x9DD2: +case 0x9FD2: +case 0x91D3: +case 0x93D3: +case 0x95D3: +case 0x97D3: +case 0x99D3: +case 0x9BD3: +case 0x9DD3: +case 0x9FD3: +case 0x91D4: +case 0x93D4: +case 0x95D4: +case 0x97D4: +case 0x99D4: +case 0x9BD4: +case 0x9DD4: +case 0x9FD4: +case 0x91D5: +case 0x93D5: +case 0x95D5: +case 0x97D5: +case 0x99D5: +case 0x9BD5: +case 0x9DD5: +case 0x9FD5: +case 0x91D6: +case 0x93D6: +case 0x95D6: +case 0x97D6: +case 0x99D6: +case 0x9BD6: +case 0x9DD6: +case 0x9FD6: +case 0x91D7: +case 0x93D7: +case 0x95D7: +case 0x97D7: +case 0x99D7: +case 0x9BD7: +case 0x9DD7: +case 0x9FD7: + +// SUBA +case 0x91D0: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READSX_LONG_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst - src; + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(16) +case 0x93D8: +case 0x95D8: +case 0x97D8: +case 0x99D8: +case 0x9BD8: +case 0x9DD8: +case 0x9FD8: +case 0x91D9: +case 0x93D9: +case 0x95D9: +case 0x97D9: +case 0x99D9: +case 0x9BD9: +case 0x9DD9: +case 0x9FD9: +case 0x91DA: +case 0x93DA: +case 0x95DA: +case 0x97DA: +case 0x99DA: +case 0x9BDA: +case 0x9DDA: +case 0x9FDA: +case 0x91DB: +case 0x93DB: +case 0x95DB: +case 0x97DB: +case 0x99DB: +case 0x9BDB: +case 0x9DDB: +case 0x9FDB: +case 0x91DC: +case 0x93DC: +case 0x95DC: +case 0x97DC: +case 0x99DC: +case 0x9BDC: +case 0x9DDC: +case 0x9FDC: +case 0x91DD: +case 0x93DD: +case 0x95DD: +case 0x97DD: +case 0x99DD: +case 0x9BDD: +case 0x9DDD: +case 0x9FDD: +case 0x91DE: +case 0x93DE: +case 0x95DE: +case 0x97DE: +case 0x99DE: +case 0x9BDE: +case 0x9DDE: +case 0x9FDE: + +// SUBA +case 0x91D8: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 4; + PRE_IO + READSX_LONG_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst - src; + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(16) +case 0x93E0: +case 0x95E0: +case 0x97E0: +case 0x99E0: +case 0x9BE0: +case 0x9DE0: +case 0x9FE0: +case 0x91E1: +case 0x93E1: +case 0x95E1: +case 0x97E1: +case 0x99E1: +case 0x9BE1: +case 0x9DE1: +case 0x9FE1: +case 0x91E2: +case 0x93E2: +case 0x95E2: +case 0x97E2: +case 0x99E2: +case 0x9BE2: +case 0x9DE2: +case 0x9FE2: +case 0x91E3: +case 0x93E3: +case 0x95E3: +case 0x97E3: +case 0x99E3: +case 0x9BE3: +case 0x9DE3: +case 0x9FE3: +case 0x91E4: +case 0x93E4: +case 0x95E4: +case 0x97E4: +case 0x99E4: +case 0x9BE4: +case 0x9DE4: +case 0x9FE4: +case 0x91E5: +case 0x93E5: +case 0x95E5: +case 0x97E5: +case 0x99E5: +case 0x9BE5: +case 0x9DE5: +case 0x9FE5: +case 0x91E6: +case 0x93E6: +case 0x95E6: +case 0x97E6: +case 0x99E6: +case 0x9BE6: +case 0x9DE6: +case 0x9FE6: + +// SUBA +case 0x91E0: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 4; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READSX_LONG_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst - src; + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(18) +case 0x93E8: +case 0x95E8: +case 0x97E8: +case 0x99E8: +case 0x9BE8: +case 0x9DE8: +case 0x9FE8: +case 0x91E9: +case 0x93E9: +case 0x95E9: +case 0x97E9: +case 0x99E9: +case 0x9BE9: +case 0x9DE9: +case 0x9FE9: +case 0x91EA: +case 0x93EA: +case 0x95EA: +case 0x97EA: +case 0x99EA: +case 0x9BEA: +case 0x9DEA: +case 0x9FEA: +case 0x91EB: +case 0x93EB: +case 0x95EB: +case 0x97EB: +case 0x99EB: +case 0x9BEB: +case 0x9DEB: +case 0x9FEB: +case 0x91EC: +case 0x93EC: +case 0x95EC: +case 0x97EC: +case 0x99EC: +case 0x9BEC: +case 0x9DEC: +case 0x9FEC: +case 0x91ED: +case 0x93ED: +case 0x95ED: +case 0x97ED: +case 0x99ED: +case 0x9BED: +case 0x9DED: +case 0x9FED: +case 0x91EE: +case 0x93EE: +case 0x95EE: +case 0x97EE: +case 0x99EE: +case 0x9BEE: +case 0x9DEE: +case 0x9FEE: +case 0x91EF: +case 0x93EF: +case 0x95EF: +case 0x97EF: +case 0x99EF: +case 0x9BEF: +case 0x9DEF: +case 0x9FEF: + +// SUBA +case 0x91E8: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READSX_LONG_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst - src; + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(20) +case 0x93F0: +case 0x95F0: +case 0x97F0: +case 0x99F0: +case 0x9BF0: +case 0x9DF0: +case 0x9FF0: +case 0x91F1: +case 0x93F1: +case 0x95F1: +case 0x97F1: +case 0x99F1: +case 0x9BF1: +case 0x9DF1: +case 0x9FF1: +case 0x91F2: +case 0x93F2: +case 0x95F2: +case 0x97F2: +case 0x99F2: +case 0x9BF2: +case 0x9DF2: +case 0x9FF2: +case 0x91F3: +case 0x93F3: +case 0x95F3: +case 0x97F3: +case 0x99F3: +case 0x9BF3: +case 0x9DF3: +case 0x9FF3: +case 0x91F4: +case 0x93F4: +case 0x95F4: +case 0x97F4: +case 0x99F4: +case 0x9BF4: +case 0x9DF4: +case 0x9FF4: +case 0x91F5: +case 0x93F5: +case 0x95F5: +case 0x97F5: +case 0x99F5: +case 0x9BF5: +case 0x9DF5: +case 0x9FF5: +case 0x91F6: +case 0x93F6: +case 0x95F6: +case 0x97F6: +case 0x99F6: +case 0x9BF6: +case 0x9DF6: +case 0x9FF6: +case 0x91F7: +case 0x93F7: +case 0x95F7: +case 0x97F7: +case 0x99F7: +case 0x9BF7: +case 0x9DF7: +case 0x9FF7: + +// SUBA +case 0x91F0: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READSX_LONG_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst - src; + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(22) +case 0x93F8: +case 0x95F8: +case 0x97F8: +case 0x99F8: +case 0x9BF8: +case 0x9DF8: +case 0x9FF8: + +// SUBA +case 0x91F8: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READSX_LONG_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst - src; + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(20) +case 0x93F9: +case 0x95F9: +case 0x97F9: +case 0x99F9: +case 0x9BF9: +case 0x9DF9: +case 0x9FF9: + +// SUBA +case 0x91F9: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READSX_LONG_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst - src; + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(24) +case 0x93FA: +case 0x95FA: +case 0x97FA: +case 0x99FA: +case 0x9BFA: +case 0x9DFA: +case 0x9FFA: + +// SUBA +case 0x91FA: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READSX_LONG_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst - src; + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(20) +case 0x93FB: +case 0x95FB: +case 0x97FB: +case 0x99FB: +case 0x9BFB: +case 0x9DFB: +case 0x9FFB: + +// SUBA +case 0x91FB: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READSX_LONG_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst - src; + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(22) +case 0x93FC: +case 0x95FC: +case 0x97FC: +case 0x99FC: +case 0x9BFC: +case 0x9DFC: +case 0x9FFC: + +// SUBA +case 0x91FC: +{ + u32 res; + pointer dst; + pointer src; + src = (s32)(s32)FETCH_LONG; + PC += 4; + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst - src; + CPU->A[(Opcode >> 9) & 7] = res; +} +RET(14) +case 0x93DF: +case 0x95DF: +case 0x97DF: +case 0x99DF: +case 0x9BDF: +case 0x9DDF: +case 0x9FDF: + +// SUBA +case 0x91DF: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[7]; + CPU->A[7] += 4; + PRE_IO + READSX_LONG_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst - src; + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(16) +case 0x93E7: +case 0x95E7: +case 0x97E7: +case 0x99E7: +case 0x9BE7: +case 0x9DE7: +case 0x9FE7: + +// SUBA +case 0x91E7: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + PRE_IO + READSX_LONG_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst - src; + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(18) diff --git a/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68k_opA.inc b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68k_opA.inc new file mode 100644 index 000000000..24d51979a --- /dev/null +++ b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68k_opA.inc @@ -0,0 +1,4118 @@ +case 0xA001: +case 0xA002: +case 0xA003: +case 0xA004: +case 0xA005: +case 0xA006: +case 0xA007: +case 0xA008: +case 0xA009: +case 0xA00A: +case 0xA00B: +case 0xA00C: +case 0xA00D: +case 0xA00E: +case 0xA00F: +case 0xA010: +case 0xA011: +case 0xA012: +case 0xA013: +case 0xA014: +case 0xA015: +case 0xA016: +case 0xA017: +case 0xA018: +case 0xA019: +case 0xA01A: +case 0xA01B: +case 0xA01C: +case 0xA01D: +case 0xA01E: +case 0xA01F: +case 0xA020: +case 0xA021: +case 0xA022: +case 0xA023: +case 0xA024: +case 0xA025: +case 0xA026: +case 0xA027: +case 0xA028: +case 0xA029: +case 0xA02A: +case 0xA02B: +case 0xA02C: +case 0xA02D: +case 0xA02E: +case 0xA02F: +case 0xA030: +case 0xA031: +case 0xA032: +case 0xA033: +case 0xA034: +case 0xA035: +case 0xA036: +case 0xA037: +case 0xA038: +case 0xA039: +case 0xA03A: +case 0xA03B: +case 0xA03C: +case 0xA03D: +case 0xA03E: +case 0xA03F: +case 0xA040: +case 0xA041: +case 0xA042: +case 0xA043: +case 0xA044: +case 0xA045: +case 0xA046: +case 0xA047: +case 0xA048: +case 0xA049: +case 0xA04A: +case 0xA04B: +case 0xA04C: +case 0xA04D: +case 0xA04E: +case 0xA04F: +case 0xA050: +case 0xA051: +case 0xA052: +case 0xA053: +case 0xA054: +case 0xA055: +case 0xA056: +case 0xA057: +case 0xA058: +case 0xA059: +case 0xA05A: +case 0xA05B: +case 0xA05C: +case 0xA05D: +case 0xA05E: +case 0xA05F: +case 0xA060: +case 0xA061: +case 0xA062: +case 0xA063: +case 0xA064: +case 0xA065: +case 0xA066: +case 0xA067: +case 0xA068: +case 0xA069: +case 0xA06A: +case 0xA06B: +case 0xA06C: +case 0xA06D: +case 0xA06E: +case 0xA06F: +case 0xA070: +case 0xA071: +case 0xA072: +case 0xA073: +case 0xA074: +case 0xA075: +case 0xA076: +case 0xA077: +case 0xA078: +case 0xA079: +case 0xA07A: +case 0xA07B: +case 0xA07C: +case 0xA07D: +case 0xA07E: +case 0xA07F: +case 0xA080: +case 0xA081: +case 0xA082: +case 0xA083: +case 0xA084: +case 0xA085: +case 0xA086: +case 0xA087: +case 0xA088: +case 0xA089: +case 0xA08A: +case 0xA08B: +case 0xA08C: +case 0xA08D: +case 0xA08E: +case 0xA08F: +case 0xA090: +case 0xA091: +case 0xA092: +case 0xA093: +case 0xA094: +case 0xA095: +case 0xA096: +case 0xA097: +case 0xA098: +case 0xA099: +case 0xA09A: +case 0xA09B: +case 0xA09C: +case 0xA09D: +case 0xA09E: +case 0xA09F: +case 0xA0A0: +case 0xA0A1: +case 0xA0A2: +case 0xA0A3: +case 0xA0A4: +case 0xA0A5: +case 0xA0A6: +case 0xA0A7: +case 0xA0A8: +case 0xA0A9: +case 0xA0AA: +case 0xA0AB: +case 0xA0AC: +case 0xA0AD: +case 0xA0AE: +case 0xA0AF: +case 0xA0B0: +case 0xA0B1: +case 0xA0B2: +case 0xA0B3: +case 0xA0B4: +case 0xA0B5: +case 0xA0B6: +case 0xA0B7: +case 0xA0B8: +case 0xA0B9: +case 0xA0BA: +case 0xA0BB: +case 0xA0BC: +case 0xA0BD: +case 0xA0BE: +case 0xA0BF: +case 0xA0C0: +case 0xA0C1: +case 0xA0C2: +case 0xA0C3: +case 0xA0C4: +case 0xA0C5: +case 0xA0C6: +case 0xA0C7: +case 0xA0C8: +case 0xA0C9: +case 0xA0CA: +case 0xA0CB: +case 0xA0CC: +case 0xA0CD: +case 0xA0CE: +case 0xA0CF: +case 0xA0D0: +case 0xA0D1: +case 0xA0D2: +case 0xA0D3: +case 0xA0D4: +case 0xA0D5: +case 0xA0D6: +case 0xA0D7: +case 0xA0D8: +case 0xA0D9: +case 0xA0DA: +case 0xA0DB: +case 0xA0DC: +case 0xA0DD: +case 0xA0DE: +case 0xA0DF: +case 0xA0E0: +case 0xA0E1: +case 0xA0E2: +case 0xA0E3: +case 0xA0E4: +case 0xA0E5: +case 0xA0E6: +case 0xA0E7: +case 0xA0E8: +case 0xA0E9: +case 0xA0EA: +case 0xA0EB: +case 0xA0EC: +case 0xA0ED: +case 0xA0EE: +case 0xA0EF: +case 0xA0F0: +case 0xA0F1: +case 0xA0F2: +case 0xA0F3: +case 0xA0F4: +case 0xA0F5: +case 0xA0F6: +case 0xA0F7: +case 0xA0F8: +case 0xA0F9: +case 0xA0FA: +case 0xA0FB: +case 0xA0FC: +case 0xA0FD: +case 0xA0FE: +case 0xA0FF: +case 0xA100: +case 0xA101: +case 0xA102: +case 0xA103: +case 0xA104: +case 0xA105: +case 0xA106: +case 0xA107: +case 0xA108: +case 0xA109: +case 0xA10A: +case 0xA10B: +case 0xA10C: +case 0xA10D: +case 0xA10E: +case 0xA10F: +case 0xA110: +case 0xA111: +case 0xA112: +case 0xA113: +case 0xA114: +case 0xA115: +case 0xA116: +case 0xA117: +case 0xA118: +case 0xA119: +case 0xA11A: +case 0xA11B: +case 0xA11C: +case 0xA11D: +case 0xA11E: +case 0xA11F: +case 0xA120: +case 0xA121: +case 0xA122: +case 0xA123: +case 0xA124: +case 0xA125: +case 0xA126: +case 0xA127: +case 0xA128: +case 0xA129: +case 0xA12A: +case 0xA12B: +case 0xA12C: +case 0xA12D: +case 0xA12E: +case 0xA12F: +case 0xA130: +case 0xA131: +case 0xA132: +case 0xA133: +case 0xA134: +case 0xA135: +case 0xA136: +case 0xA137: +case 0xA138: +case 0xA139: +case 0xA13A: +case 0xA13B: +case 0xA13C: +case 0xA13D: +case 0xA13E: +case 0xA13F: +case 0xA140: +case 0xA141: +case 0xA142: +case 0xA143: +case 0xA144: +case 0xA145: +case 0xA146: +case 0xA147: +case 0xA148: +case 0xA149: +case 0xA14A: +case 0xA14B: +case 0xA14C: +case 0xA14D: +case 0xA14E: +case 0xA14F: +case 0xA150: +case 0xA151: +case 0xA152: +case 0xA153: +case 0xA154: +case 0xA155: +case 0xA156: +case 0xA157: +case 0xA158: +case 0xA159: +case 0xA15A: +case 0xA15B: +case 0xA15C: +case 0xA15D: +case 0xA15E: +case 0xA15F: +case 0xA160: +case 0xA161: +case 0xA162: +case 0xA163: +case 0xA164: +case 0xA165: +case 0xA166: +case 0xA167: +case 0xA168: +case 0xA169: +case 0xA16A: +case 0xA16B: +case 0xA16C: +case 0xA16D: +case 0xA16E: +case 0xA16F: +case 0xA170: +case 0xA171: +case 0xA172: +case 0xA173: +case 0xA174: +case 0xA175: +case 0xA176: +case 0xA177: +case 0xA178: +case 0xA179: +case 0xA17A: +case 0xA17B: +case 0xA17C: +case 0xA17D: +case 0xA17E: +case 0xA17F: +case 0xA180: +case 0xA181: +case 0xA182: +case 0xA183: +case 0xA184: +case 0xA185: +case 0xA186: +case 0xA187: +case 0xA188: +case 0xA189: +case 0xA18A: +case 0xA18B: +case 0xA18C: +case 0xA18D: +case 0xA18E: +case 0xA18F: +case 0xA190: +case 0xA191: +case 0xA192: +case 0xA193: +case 0xA194: +case 0xA195: +case 0xA196: +case 0xA197: +case 0xA198: +case 0xA199: +case 0xA19A: +case 0xA19B: +case 0xA19C: +case 0xA19D: +case 0xA19E: +case 0xA19F: +case 0xA1A0: +case 0xA1A1: +case 0xA1A2: +case 0xA1A3: +case 0xA1A4: +case 0xA1A5: +case 0xA1A6: +case 0xA1A7: +case 0xA1A8: +case 0xA1A9: +case 0xA1AA: +case 0xA1AB: +case 0xA1AC: +case 0xA1AD: +case 0xA1AE: +case 0xA1AF: +case 0xA1B0: +case 0xA1B1: +case 0xA1B2: +case 0xA1B3: +case 0xA1B4: +case 0xA1B5: +case 0xA1B6: +case 0xA1B7: +case 0xA1B8: +case 0xA1B9: +case 0xA1BA: +case 0xA1BB: +case 0xA1BC: +case 0xA1BD: +case 0xA1BE: +case 0xA1BF: +case 0xA1C0: +case 0xA1C1: +case 0xA1C2: +case 0xA1C3: +case 0xA1C4: +case 0xA1C5: +case 0xA1C6: +case 0xA1C7: +case 0xA1C8: +case 0xA1C9: +case 0xA1CA: +case 0xA1CB: +case 0xA1CC: +case 0xA1CD: +case 0xA1CE: +case 0xA1CF: +case 0xA1D0: +case 0xA1D1: +case 0xA1D2: +case 0xA1D3: +case 0xA1D4: +case 0xA1D5: +case 0xA1D6: +case 0xA1D7: +case 0xA1D8: +case 0xA1D9: +case 0xA1DA: +case 0xA1DB: +case 0xA1DC: +case 0xA1DD: +case 0xA1DE: +case 0xA1DF: +case 0xA1E0: +case 0xA1E1: +case 0xA1E2: +case 0xA1E3: +case 0xA1E4: +case 0xA1E5: +case 0xA1E6: +case 0xA1E7: +case 0xA1E8: +case 0xA1E9: +case 0xA1EA: +case 0xA1EB: +case 0xA1EC: +case 0xA1ED: +case 0xA1EE: +case 0xA1EF: +case 0xA1F0: +case 0xA1F1: +case 0xA1F2: +case 0xA1F3: +case 0xA1F4: +case 0xA1F5: +case 0xA1F6: +case 0xA1F7: +case 0xA1F8: +case 0xA1F9: +case 0xA1FA: +case 0xA1FB: +case 0xA1FC: +case 0xA1FD: +case 0xA1FE: +case 0xA1FF: +case 0xA200: +case 0xA201: +case 0xA202: +case 0xA203: +case 0xA204: +case 0xA205: +case 0xA206: +case 0xA207: +case 0xA208: +case 0xA209: +case 0xA20A: +case 0xA20B: +case 0xA20C: +case 0xA20D: +case 0xA20E: +case 0xA20F: +case 0xA210: +case 0xA211: +case 0xA212: +case 0xA213: +case 0xA214: +case 0xA215: +case 0xA216: +case 0xA217: +case 0xA218: +case 0xA219: +case 0xA21A: +case 0xA21B: +case 0xA21C: +case 0xA21D: +case 0xA21E: +case 0xA21F: +case 0xA220: +case 0xA221: +case 0xA222: +case 0xA223: +case 0xA224: +case 0xA225: +case 0xA226: +case 0xA227: +case 0xA228: +case 0xA229: +case 0xA22A: +case 0xA22B: +case 0xA22C: +case 0xA22D: +case 0xA22E: +case 0xA22F: +case 0xA230: +case 0xA231: +case 0xA232: +case 0xA233: +case 0xA234: +case 0xA235: +case 0xA236: +case 0xA237: +case 0xA238: +case 0xA239: +case 0xA23A: +case 0xA23B: +case 0xA23C: +case 0xA23D: +case 0xA23E: +case 0xA23F: +case 0xA240: +case 0xA241: +case 0xA242: +case 0xA243: +case 0xA244: +case 0xA245: +case 0xA246: +case 0xA247: +case 0xA248: +case 0xA249: +case 0xA24A: +case 0xA24B: +case 0xA24C: +case 0xA24D: +case 0xA24E: +case 0xA24F: +case 0xA250: +case 0xA251: +case 0xA252: +case 0xA253: +case 0xA254: +case 0xA255: +case 0xA256: +case 0xA257: +case 0xA258: +case 0xA259: +case 0xA25A: +case 0xA25B: +case 0xA25C: +case 0xA25D: +case 0xA25E: +case 0xA25F: +case 0xA260: +case 0xA261: +case 0xA262: +case 0xA263: +case 0xA264: +case 0xA265: +case 0xA266: +case 0xA267: +case 0xA268: +case 0xA269: +case 0xA26A: +case 0xA26B: +case 0xA26C: +case 0xA26D: +case 0xA26E: +case 0xA26F: +case 0xA270: +case 0xA271: +case 0xA272: +case 0xA273: +case 0xA274: +case 0xA275: +case 0xA276: +case 0xA277: +case 0xA278: +case 0xA279: +case 0xA27A: +case 0xA27B: +case 0xA27C: +case 0xA27D: +case 0xA27E: +case 0xA27F: +case 0xA280: +case 0xA281: +case 0xA282: +case 0xA283: +case 0xA284: +case 0xA285: +case 0xA286: +case 0xA287: +case 0xA288: +case 0xA289: +case 0xA28A: +case 0xA28B: +case 0xA28C: +case 0xA28D: +case 0xA28E: +case 0xA28F: +case 0xA290: +case 0xA291: +case 0xA292: +case 0xA293: +case 0xA294: +case 0xA295: +case 0xA296: +case 0xA297: +case 0xA298: +case 0xA299: +case 0xA29A: +case 0xA29B: +case 0xA29C: +case 0xA29D: +case 0xA29E: +case 0xA29F: +case 0xA2A0: +case 0xA2A1: +case 0xA2A2: +case 0xA2A3: +case 0xA2A4: +case 0xA2A5: +case 0xA2A6: +case 0xA2A7: +case 0xA2A8: +case 0xA2A9: +case 0xA2AA: +case 0xA2AB: +case 0xA2AC: +case 0xA2AD: +case 0xA2AE: +case 0xA2AF: +case 0xA2B0: +case 0xA2B1: +case 0xA2B2: +case 0xA2B3: +case 0xA2B4: +case 0xA2B5: +case 0xA2B6: +case 0xA2B7: +case 0xA2B8: +case 0xA2B9: +case 0xA2BA: +case 0xA2BB: +case 0xA2BC: +case 0xA2BD: +case 0xA2BE: +case 0xA2BF: +case 0xA2C0: +case 0xA2C1: +case 0xA2C2: +case 0xA2C3: +case 0xA2C4: +case 0xA2C5: +case 0xA2C6: +case 0xA2C7: +case 0xA2C8: +case 0xA2C9: +case 0xA2CA: +case 0xA2CB: +case 0xA2CC: +case 0xA2CD: +case 0xA2CE: +case 0xA2CF: +case 0xA2D0: +case 0xA2D1: +case 0xA2D2: +case 0xA2D3: +case 0xA2D4: +case 0xA2D5: +case 0xA2D6: +case 0xA2D7: +case 0xA2D8: +case 0xA2D9: +case 0xA2DA: +case 0xA2DB: +case 0xA2DC: +case 0xA2DD: +case 0xA2DE: +case 0xA2DF: +case 0xA2E0: +case 0xA2E1: +case 0xA2E2: +case 0xA2E3: +case 0xA2E4: +case 0xA2E5: +case 0xA2E6: +case 0xA2E7: +case 0xA2E8: +case 0xA2E9: +case 0xA2EA: +case 0xA2EB: +case 0xA2EC: +case 0xA2ED: +case 0xA2EE: +case 0xA2EF: +case 0xA2F0: +case 0xA2F1: +case 0xA2F2: +case 0xA2F3: +case 0xA2F4: +case 0xA2F5: +case 0xA2F6: +case 0xA2F7: +case 0xA2F8: +case 0xA2F9: +case 0xA2FA: +case 0xA2FB: +case 0xA2FC: +case 0xA2FD: +case 0xA2FE: +case 0xA2FF: +case 0xA300: +case 0xA301: +case 0xA302: +case 0xA303: +case 0xA304: +case 0xA305: +case 0xA306: +case 0xA307: +case 0xA308: +case 0xA309: +case 0xA30A: +case 0xA30B: +case 0xA30C: +case 0xA30D: +case 0xA30E: +case 0xA30F: +case 0xA310: +case 0xA311: +case 0xA312: +case 0xA313: +case 0xA314: +case 0xA315: +case 0xA316: +case 0xA317: +case 0xA318: +case 0xA319: +case 0xA31A: +case 0xA31B: +case 0xA31C: +case 0xA31D: +case 0xA31E: +case 0xA31F: +case 0xA320: +case 0xA321: +case 0xA322: +case 0xA323: +case 0xA324: +case 0xA325: +case 0xA326: +case 0xA327: +case 0xA328: +case 0xA329: +case 0xA32A: +case 0xA32B: +case 0xA32C: +case 0xA32D: +case 0xA32E: +case 0xA32F: +case 0xA330: +case 0xA331: +case 0xA332: +case 0xA333: +case 0xA334: +case 0xA335: +case 0xA336: +case 0xA337: +case 0xA338: +case 0xA339: +case 0xA33A: +case 0xA33B: +case 0xA33C: +case 0xA33D: +case 0xA33E: +case 0xA33F: +case 0xA340: +case 0xA341: +case 0xA342: +case 0xA343: +case 0xA344: +case 0xA345: +case 0xA346: +case 0xA347: +case 0xA348: +case 0xA349: +case 0xA34A: +case 0xA34B: +case 0xA34C: +case 0xA34D: +case 0xA34E: +case 0xA34F: +case 0xA350: +case 0xA351: +case 0xA352: +case 0xA353: +case 0xA354: +case 0xA355: +case 0xA356: +case 0xA357: +case 0xA358: +case 0xA359: +case 0xA35A: +case 0xA35B: +case 0xA35C: +case 0xA35D: +case 0xA35E: +case 0xA35F: +case 0xA360: +case 0xA361: +case 0xA362: +case 0xA363: +case 0xA364: +case 0xA365: +case 0xA366: +case 0xA367: +case 0xA368: +case 0xA369: +case 0xA36A: +case 0xA36B: +case 0xA36C: +case 0xA36D: +case 0xA36E: +case 0xA36F: +case 0xA370: +case 0xA371: +case 0xA372: +case 0xA373: +case 0xA374: +case 0xA375: +case 0xA376: +case 0xA377: +case 0xA378: +case 0xA379: +case 0xA37A: +case 0xA37B: +case 0xA37C: +case 0xA37D: +case 0xA37E: +case 0xA37F: +case 0xA380: +case 0xA381: +case 0xA382: +case 0xA383: +case 0xA384: +case 0xA385: +case 0xA386: +case 0xA387: +case 0xA388: +case 0xA389: +case 0xA38A: +case 0xA38B: +case 0xA38C: +case 0xA38D: +case 0xA38E: +case 0xA38F: +case 0xA390: +case 0xA391: +case 0xA392: +case 0xA393: +case 0xA394: +case 0xA395: +case 0xA396: +case 0xA397: +case 0xA398: +case 0xA399: +case 0xA39A: +case 0xA39B: +case 0xA39C: +case 0xA39D: +case 0xA39E: +case 0xA39F: +case 0xA3A0: +case 0xA3A1: +case 0xA3A2: +case 0xA3A3: +case 0xA3A4: +case 0xA3A5: +case 0xA3A6: +case 0xA3A7: +case 0xA3A8: +case 0xA3A9: +case 0xA3AA: +case 0xA3AB: +case 0xA3AC: +case 0xA3AD: +case 0xA3AE: +case 0xA3AF: +case 0xA3B0: +case 0xA3B1: +case 0xA3B2: +case 0xA3B3: +case 0xA3B4: +case 0xA3B5: +case 0xA3B6: +case 0xA3B7: +case 0xA3B8: +case 0xA3B9: +case 0xA3BA: +case 0xA3BB: +case 0xA3BC: +case 0xA3BD: +case 0xA3BE: +case 0xA3BF: +case 0xA3C0: +case 0xA3C1: +case 0xA3C2: +case 0xA3C3: +case 0xA3C4: +case 0xA3C5: +case 0xA3C6: +case 0xA3C7: +case 0xA3C8: +case 0xA3C9: +case 0xA3CA: +case 0xA3CB: +case 0xA3CC: +case 0xA3CD: +case 0xA3CE: +case 0xA3CF: +case 0xA3D0: +case 0xA3D1: +case 0xA3D2: +case 0xA3D3: +case 0xA3D4: +case 0xA3D5: +case 0xA3D6: +case 0xA3D7: +case 0xA3D8: +case 0xA3D9: +case 0xA3DA: +case 0xA3DB: +case 0xA3DC: +case 0xA3DD: +case 0xA3DE: +case 0xA3DF: +case 0xA3E0: +case 0xA3E1: +case 0xA3E2: +case 0xA3E3: +case 0xA3E4: +case 0xA3E5: +case 0xA3E6: +case 0xA3E7: +case 0xA3E8: +case 0xA3E9: +case 0xA3EA: +case 0xA3EB: +case 0xA3EC: +case 0xA3ED: +case 0xA3EE: +case 0xA3EF: +case 0xA3F0: +case 0xA3F1: +case 0xA3F2: +case 0xA3F3: +case 0xA3F4: +case 0xA3F5: +case 0xA3F6: +case 0xA3F7: +case 0xA3F8: +case 0xA3F9: +case 0xA3FA: +case 0xA3FB: +case 0xA3FC: +case 0xA3FD: +case 0xA3FE: +case 0xA3FF: +case 0xA400: +case 0xA401: +case 0xA402: +case 0xA403: +case 0xA404: +case 0xA405: +case 0xA406: +case 0xA407: +case 0xA408: +case 0xA409: +case 0xA40A: +case 0xA40B: +case 0xA40C: +case 0xA40D: +case 0xA40E: +case 0xA40F: +case 0xA410: +case 0xA411: +case 0xA412: +case 0xA413: +case 0xA414: +case 0xA415: +case 0xA416: +case 0xA417: +case 0xA418: +case 0xA419: +case 0xA41A: +case 0xA41B: +case 0xA41C: +case 0xA41D: +case 0xA41E: +case 0xA41F: +case 0xA420: +case 0xA421: +case 0xA422: +case 0xA423: +case 0xA424: +case 0xA425: +case 0xA426: +case 0xA427: +case 0xA428: +case 0xA429: +case 0xA42A: +case 0xA42B: +case 0xA42C: +case 0xA42D: +case 0xA42E: +case 0xA42F: +case 0xA430: +case 0xA431: +case 0xA432: +case 0xA433: +case 0xA434: +case 0xA435: +case 0xA436: +case 0xA437: +case 0xA438: +case 0xA439: +case 0xA43A: +case 0xA43B: +case 0xA43C: +case 0xA43D: +case 0xA43E: +case 0xA43F: +case 0xA440: +case 0xA441: +case 0xA442: +case 0xA443: +case 0xA444: +case 0xA445: +case 0xA446: +case 0xA447: +case 0xA448: +case 0xA449: +case 0xA44A: +case 0xA44B: +case 0xA44C: +case 0xA44D: +case 0xA44E: +case 0xA44F: +case 0xA450: +case 0xA451: +case 0xA452: +case 0xA453: +case 0xA454: +case 0xA455: +case 0xA456: +case 0xA457: +case 0xA458: +case 0xA459: +case 0xA45A: +case 0xA45B: +case 0xA45C: +case 0xA45D: +case 0xA45E: +case 0xA45F: +case 0xA460: +case 0xA461: +case 0xA462: +case 0xA463: +case 0xA464: +case 0xA465: +case 0xA466: +case 0xA467: +case 0xA468: +case 0xA469: +case 0xA46A: +case 0xA46B: +case 0xA46C: +case 0xA46D: +case 0xA46E: +case 0xA46F: +case 0xA470: +case 0xA471: +case 0xA472: +case 0xA473: +case 0xA474: +case 0xA475: +case 0xA476: +case 0xA477: +case 0xA478: +case 0xA479: +case 0xA47A: +case 0xA47B: +case 0xA47C: +case 0xA47D: +case 0xA47E: +case 0xA47F: +case 0xA480: +case 0xA481: +case 0xA482: +case 0xA483: +case 0xA484: +case 0xA485: +case 0xA486: +case 0xA487: +case 0xA488: +case 0xA489: +case 0xA48A: +case 0xA48B: +case 0xA48C: +case 0xA48D: +case 0xA48E: +case 0xA48F: +case 0xA490: +case 0xA491: +case 0xA492: +case 0xA493: +case 0xA494: +case 0xA495: +case 0xA496: +case 0xA497: +case 0xA498: +case 0xA499: +case 0xA49A: +case 0xA49B: +case 0xA49C: +case 0xA49D: +case 0xA49E: +case 0xA49F: +case 0xA4A0: +case 0xA4A1: +case 0xA4A2: +case 0xA4A3: +case 0xA4A4: +case 0xA4A5: +case 0xA4A6: +case 0xA4A7: +case 0xA4A8: +case 0xA4A9: +case 0xA4AA: +case 0xA4AB: +case 0xA4AC: +case 0xA4AD: +case 0xA4AE: +case 0xA4AF: +case 0xA4B0: +case 0xA4B1: +case 0xA4B2: +case 0xA4B3: +case 0xA4B4: +case 0xA4B5: +case 0xA4B6: +case 0xA4B7: +case 0xA4B8: +case 0xA4B9: +case 0xA4BA: +case 0xA4BB: +case 0xA4BC: +case 0xA4BD: +case 0xA4BE: +case 0xA4BF: +case 0xA4C0: +case 0xA4C1: +case 0xA4C2: +case 0xA4C3: +case 0xA4C4: +case 0xA4C5: +case 0xA4C6: +case 0xA4C7: +case 0xA4C8: +case 0xA4C9: +case 0xA4CA: +case 0xA4CB: +case 0xA4CC: +case 0xA4CD: +case 0xA4CE: +case 0xA4CF: +case 0xA4D0: +case 0xA4D1: +case 0xA4D2: +case 0xA4D3: +case 0xA4D4: +case 0xA4D5: +case 0xA4D6: +case 0xA4D7: +case 0xA4D8: +case 0xA4D9: +case 0xA4DA: +case 0xA4DB: +case 0xA4DC: +case 0xA4DD: +case 0xA4DE: +case 0xA4DF: +case 0xA4E0: +case 0xA4E1: +case 0xA4E2: +case 0xA4E3: +case 0xA4E4: +case 0xA4E5: +case 0xA4E6: +case 0xA4E7: +case 0xA4E8: +case 0xA4E9: +case 0xA4EA: +case 0xA4EB: +case 0xA4EC: +case 0xA4ED: +case 0xA4EE: +case 0xA4EF: +case 0xA4F0: +case 0xA4F1: +case 0xA4F2: +case 0xA4F3: +case 0xA4F4: +case 0xA4F5: +case 0xA4F6: +case 0xA4F7: +case 0xA4F8: +case 0xA4F9: +case 0xA4FA: +case 0xA4FB: +case 0xA4FC: +case 0xA4FD: +case 0xA4FE: +case 0xA4FF: +case 0xA500: +case 0xA501: +case 0xA502: +case 0xA503: +case 0xA504: +case 0xA505: +case 0xA506: +case 0xA507: +case 0xA508: +case 0xA509: +case 0xA50A: +case 0xA50B: +case 0xA50C: +case 0xA50D: +case 0xA50E: +case 0xA50F: +case 0xA510: +case 0xA511: +case 0xA512: +case 0xA513: +case 0xA514: +case 0xA515: +case 0xA516: +case 0xA517: +case 0xA518: +case 0xA519: +case 0xA51A: +case 0xA51B: +case 0xA51C: +case 0xA51D: +case 0xA51E: +case 0xA51F: +case 0xA520: +case 0xA521: +case 0xA522: +case 0xA523: +case 0xA524: +case 0xA525: +case 0xA526: +case 0xA527: +case 0xA528: +case 0xA529: +case 0xA52A: +case 0xA52B: +case 0xA52C: +case 0xA52D: +case 0xA52E: +case 0xA52F: +case 0xA530: +case 0xA531: +case 0xA532: +case 0xA533: +case 0xA534: +case 0xA535: +case 0xA536: +case 0xA537: +case 0xA538: +case 0xA539: +case 0xA53A: +case 0xA53B: +case 0xA53C: +case 0xA53D: +case 0xA53E: +case 0xA53F: +case 0xA540: +case 0xA541: +case 0xA542: +case 0xA543: +case 0xA544: +case 0xA545: +case 0xA546: +case 0xA547: +case 0xA548: +case 0xA549: +case 0xA54A: +case 0xA54B: +case 0xA54C: +case 0xA54D: +case 0xA54E: +case 0xA54F: +case 0xA550: +case 0xA551: +case 0xA552: +case 0xA553: +case 0xA554: +case 0xA555: +case 0xA556: +case 0xA557: +case 0xA558: +case 0xA559: +case 0xA55A: +case 0xA55B: +case 0xA55C: +case 0xA55D: +case 0xA55E: +case 0xA55F: +case 0xA560: +case 0xA561: +case 0xA562: +case 0xA563: +case 0xA564: +case 0xA565: +case 0xA566: +case 0xA567: +case 0xA568: +case 0xA569: +case 0xA56A: +case 0xA56B: +case 0xA56C: +case 0xA56D: +case 0xA56E: +case 0xA56F: +case 0xA570: +case 0xA571: +case 0xA572: +case 0xA573: +case 0xA574: +case 0xA575: +case 0xA576: +case 0xA577: +case 0xA578: +case 0xA579: +case 0xA57A: +case 0xA57B: +case 0xA57C: +case 0xA57D: +case 0xA57E: +case 0xA57F: +case 0xA580: +case 0xA581: +case 0xA582: +case 0xA583: +case 0xA584: +case 0xA585: +case 0xA586: +case 0xA587: +case 0xA588: +case 0xA589: +case 0xA58A: +case 0xA58B: +case 0xA58C: +case 0xA58D: +case 0xA58E: +case 0xA58F: +case 0xA590: +case 0xA591: +case 0xA592: +case 0xA593: +case 0xA594: +case 0xA595: +case 0xA596: +case 0xA597: +case 0xA598: +case 0xA599: +case 0xA59A: +case 0xA59B: +case 0xA59C: +case 0xA59D: +case 0xA59E: +case 0xA59F: +case 0xA5A0: +case 0xA5A1: +case 0xA5A2: +case 0xA5A3: +case 0xA5A4: +case 0xA5A5: +case 0xA5A6: +case 0xA5A7: +case 0xA5A8: +case 0xA5A9: +case 0xA5AA: +case 0xA5AB: +case 0xA5AC: +case 0xA5AD: +case 0xA5AE: +case 0xA5AF: +case 0xA5B0: +case 0xA5B1: +case 0xA5B2: +case 0xA5B3: +case 0xA5B4: +case 0xA5B5: +case 0xA5B6: +case 0xA5B7: +case 0xA5B8: +case 0xA5B9: +case 0xA5BA: +case 0xA5BB: +case 0xA5BC: +case 0xA5BD: +case 0xA5BE: +case 0xA5BF: +case 0xA5C0: +case 0xA5C1: +case 0xA5C2: +case 0xA5C3: +case 0xA5C4: +case 0xA5C5: +case 0xA5C6: +case 0xA5C7: +case 0xA5C8: +case 0xA5C9: +case 0xA5CA: +case 0xA5CB: +case 0xA5CC: +case 0xA5CD: +case 0xA5CE: +case 0xA5CF: +case 0xA5D0: +case 0xA5D1: +case 0xA5D2: +case 0xA5D3: +case 0xA5D4: +case 0xA5D5: +case 0xA5D6: +case 0xA5D7: +case 0xA5D8: +case 0xA5D9: +case 0xA5DA: +case 0xA5DB: +case 0xA5DC: +case 0xA5DD: +case 0xA5DE: +case 0xA5DF: +case 0xA5E0: +case 0xA5E1: +case 0xA5E2: +case 0xA5E3: +case 0xA5E4: +case 0xA5E5: +case 0xA5E6: +case 0xA5E7: +case 0xA5E8: +case 0xA5E9: +case 0xA5EA: +case 0xA5EB: +case 0xA5EC: +case 0xA5ED: +case 0xA5EE: +case 0xA5EF: +case 0xA5F0: +case 0xA5F1: +case 0xA5F2: +case 0xA5F3: +case 0xA5F4: +case 0xA5F5: +case 0xA5F6: +case 0xA5F7: +case 0xA5F8: +case 0xA5F9: +case 0xA5FA: +case 0xA5FB: +case 0xA5FC: +case 0xA5FD: +case 0xA5FE: +case 0xA5FF: +case 0xA600: +case 0xA601: +case 0xA602: +case 0xA603: +case 0xA604: +case 0xA605: +case 0xA606: +case 0xA607: +case 0xA608: +case 0xA609: +case 0xA60A: +case 0xA60B: +case 0xA60C: +case 0xA60D: +case 0xA60E: +case 0xA60F: +case 0xA610: +case 0xA611: +case 0xA612: +case 0xA613: +case 0xA614: +case 0xA615: +case 0xA616: +case 0xA617: +case 0xA618: +case 0xA619: +case 0xA61A: +case 0xA61B: +case 0xA61C: +case 0xA61D: +case 0xA61E: +case 0xA61F: +case 0xA620: +case 0xA621: +case 0xA622: +case 0xA623: +case 0xA624: +case 0xA625: +case 0xA626: +case 0xA627: +case 0xA628: +case 0xA629: +case 0xA62A: +case 0xA62B: +case 0xA62C: +case 0xA62D: +case 0xA62E: +case 0xA62F: +case 0xA630: +case 0xA631: +case 0xA632: +case 0xA633: +case 0xA634: +case 0xA635: +case 0xA636: +case 0xA637: +case 0xA638: +case 0xA639: +case 0xA63A: +case 0xA63B: +case 0xA63C: +case 0xA63D: +case 0xA63E: +case 0xA63F: +case 0xA640: +case 0xA641: +case 0xA642: +case 0xA643: +case 0xA644: +case 0xA645: +case 0xA646: +case 0xA647: +case 0xA648: +case 0xA649: +case 0xA64A: +case 0xA64B: +case 0xA64C: +case 0xA64D: +case 0xA64E: +case 0xA64F: +case 0xA650: +case 0xA651: +case 0xA652: +case 0xA653: +case 0xA654: +case 0xA655: +case 0xA656: +case 0xA657: +case 0xA658: +case 0xA659: +case 0xA65A: +case 0xA65B: +case 0xA65C: +case 0xA65D: +case 0xA65E: +case 0xA65F: +case 0xA660: +case 0xA661: +case 0xA662: +case 0xA663: +case 0xA664: +case 0xA665: +case 0xA666: +case 0xA667: +case 0xA668: +case 0xA669: +case 0xA66A: +case 0xA66B: +case 0xA66C: +case 0xA66D: +case 0xA66E: +case 0xA66F: +case 0xA670: +case 0xA671: +case 0xA672: +case 0xA673: +case 0xA674: +case 0xA675: +case 0xA676: +case 0xA677: +case 0xA678: +case 0xA679: +case 0xA67A: +case 0xA67B: +case 0xA67C: +case 0xA67D: +case 0xA67E: +case 0xA67F: +case 0xA680: +case 0xA681: +case 0xA682: +case 0xA683: +case 0xA684: +case 0xA685: +case 0xA686: +case 0xA687: +case 0xA688: +case 0xA689: +case 0xA68A: +case 0xA68B: +case 0xA68C: +case 0xA68D: +case 0xA68E: +case 0xA68F: +case 0xA690: +case 0xA691: +case 0xA692: +case 0xA693: +case 0xA694: +case 0xA695: +case 0xA696: +case 0xA697: +case 0xA698: +case 0xA699: +case 0xA69A: +case 0xA69B: +case 0xA69C: +case 0xA69D: +case 0xA69E: +case 0xA69F: +case 0xA6A0: +case 0xA6A1: +case 0xA6A2: +case 0xA6A3: +case 0xA6A4: +case 0xA6A5: +case 0xA6A6: +case 0xA6A7: +case 0xA6A8: +case 0xA6A9: +case 0xA6AA: +case 0xA6AB: +case 0xA6AC: +case 0xA6AD: +case 0xA6AE: +case 0xA6AF: +case 0xA6B0: +case 0xA6B1: +case 0xA6B2: +case 0xA6B3: +case 0xA6B4: +case 0xA6B5: +case 0xA6B6: +case 0xA6B7: +case 0xA6B8: +case 0xA6B9: +case 0xA6BA: +case 0xA6BB: +case 0xA6BC: +case 0xA6BD: +case 0xA6BE: +case 0xA6BF: +case 0xA6C0: +case 0xA6C1: +case 0xA6C2: +case 0xA6C3: +case 0xA6C4: +case 0xA6C5: +case 0xA6C6: +case 0xA6C7: +case 0xA6C8: +case 0xA6C9: +case 0xA6CA: +case 0xA6CB: +case 0xA6CC: +case 0xA6CD: +case 0xA6CE: +case 0xA6CF: +case 0xA6D0: +case 0xA6D1: +case 0xA6D2: +case 0xA6D3: +case 0xA6D4: +case 0xA6D5: +case 0xA6D6: +case 0xA6D7: +case 0xA6D8: +case 0xA6D9: +case 0xA6DA: +case 0xA6DB: +case 0xA6DC: +case 0xA6DD: +case 0xA6DE: +case 0xA6DF: +case 0xA6E0: +case 0xA6E1: +case 0xA6E2: +case 0xA6E3: +case 0xA6E4: +case 0xA6E5: +case 0xA6E6: +case 0xA6E7: +case 0xA6E8: +case 0xA6E9: +case 0xA6EA: +case 0xA6EB: +case 0xA6EC: +case 0xA6ED: +case 0xA6EE: +case 0xA6EF: +case 0xA6F0: +case 0xA6F1: +case 0xA6F2: +case 0xA6F3: +case 0xA6F4: +case 0xA6F5: +case 0xA6F6: +case 0xA6F7: +case 0xA6F8: +case 0xA6F9: +case 0xA6FA: +case 0xA6FB: +case 0xA6FC: +case 0xA6FD: +case 0xA6FE: +case 0xA6FF: +case 0xA700: +case 0xA701: +case 0xA702: +case 0xA703: +case 0xA704: +case 0xA705: +case 0xA706: +case 0xA707: +case 0xA708: +case 0xA709: +case 0xA70A: +case 0xA70B: +case 0xA70C: +case 0xA70D: +case 0xA70E: +case 0xA70F: +case 0xA710: +case 0xA711: +case 0xA712: +case 0xA713: +case 0xA714: +case 0xA715: +case 0xA716: +case 0xA717: +case 0xA718: +case 0xA719: +case 0xA71A: +case 0xA71B: +case 0xA71C: +case 0xA71D: +case 0xA71E: +case 0xA71F: +case 0xA720: +case 0xA721: +case 0xA722: +case 0xA723: +case 0xA724: +case 0xA725: +case 0xA726: +case 0xA727: +case 0xA728: +case 0xA729: +case 0xA72A: +case 0xA72B: +case 0xA72C: +case 0xA72D: +case 0xA72E: +case 0xA72F: +case 0xA730: +case 0xA731: +case 0xA732: +case 0xA733: +case 0xA734: +case 0xA735: +case 0xA736: +case 0xA737: +case 0xA738: +case 0xA739: +case 0xA73A: +case 0xA73B: +case 0xA73C: +case 0xA73D: +case 0xA73E: +case 0xA73F: +case 0xA740: +case 0xA741: +case 0xA742: +case 0xA743: +case 0xA744: +case 0xA745: +case 0xA746: +case 0xA747: +case 0xA748: +case 0xA749: +case 0xA74A: +case 0xA74B: +case 0xA74C: +case 0xA74D: +case 0xA74E: +case 0xA74F: +case 0xA750: +case 0xA751: +case 0xA752: +case 0xA753: +case 0xA754: +case 0xA755: +case 0xA756: +case 0xA757: +case 0xA758: +case 0xA759: +case 0xA75A: +case 0xA75B: +case 0xA75C: +case 0xA75D: +case 0xA75E: +case 0xA75F: +case 0xA760: +case 0xA761: +case 0xA762: +case 0xA763: +case 0xA764: +case 0xA765: +case 0xA766: +case 0xA767: +case 0xA768: +case 0xA769: +case 0xA76A: +case 0xA76B: +case 0xA76C: +case 0xA76D: +case 0xA76E: +case 0xA76F: +case 0xA770: +case 0xA771: +case 0xA772: +case 0xA773: +case 0xA774: +case 0xA775: +case 0xA776: +case 0xA777: +case 0xA778: +case 0xA779: +case 0xA77A: +case 0xA77B: +case 0xA77C: +case 0xA77D: +case 0xA77E: +case 0xA77F: +case 0xA780: +case 0xA781: +case 0xA782: +case 0xA783: +case 0xA784: +case 0xA785: +case 0xA786: +case 0xA787: +case 0xA788: +case 0xA789: +case 0xA78A: +case 0xA78B: +case 0xA78C: +case 0xA78D: +case 0xA78E: +case 0xA78F: +case 0xA790: +case 0xA791: +case 0xA792: +case 0xA793: +case 0xA794: +case 0xA795: +case 0xA796: +case 0xA797: +case 0xA798: +case 0xA799: +case 0xA79A: +case 0xA79B: +case 0xA79C: +case 0xA79D: +case 0xA79E: +case 0xA79F: +case 0xA7A0: +case 0xA7A1: +case 0xA7A2: +case 0xA7A3: +case 0xA7A4: +case 0xA7A5: +case 0xA7A6: +case 0xA7A7: +case 0xA7A8: +case 0xA7A9: +case 0xA7AA: +case 0xA7AB: +case 0xA7AC: +case 0xA7AD: +case 0xA7AE: +case 0xA7AF: +case 0xA7B0: +case 0xA7B1: +case 0xA7B2: +case 0xA7B3: +case 0xA7B4: +case 0xA7B5: +case 0xA7B6: +case 0xA7B7: +case 0xA7B8: +case 0xA7B9: +case 0xA7BA: +case 0xA7BB: +case 0xA7BC: +case 0xA7BD: +case 0xA7BE: +case 0xA7BF: +case 0xA7C0: +case 0xA7C1: +case 0xA7C2: +case 0xA7C3: +case 0xA7C4: +case 0xA7C5: +case 0xA7C6: +case 0xA7C7: +case 0xA7C8: +case 0xA7C9: +case 0xA7CA: +case 0xA7CB: +case 0xA7CC: +case 0xA7CD: +case 0xA7CE: +case 0xA7CF: +case 0xA7D0: +case 0xA7D1: +case 0xA7D2: +case 0xA7D3: +case 0xA7D4: +case 0xA7D5: +case 0xA7D6: +case 0xA7D7: +case 0xA7D8: +case 0xA7D9: +case 0xA7DA: +case 0xA7DB: +case 0xA7DC: +case 0xA7DD: +case 0xA7DE: +case 0xA7DF: +case 0xA7E0: +case 0xA7E1: +case 0xA7E2: +case 0xA7E3: +case 0xA7E4: +case 0xA7E5: +case 0xA7E6: +case 0xA7E7: +case 0xA7E8: +case 0xA7E9: +case 0xA7EA: +case 0xA7EB: +case 0xA7EC: +case 0xA7ED: +case 0xA7EE: +case 0xA7EF: +case 0xA7F0: +case 0xA7F1: +case 0xA7F2: +case 0xA7F3: +case 0xA7F4: +case 0xA7F5: +case 0xA7F6: +case 0xA7F7: +case 0xA7F8: +case 0xA7F9: +case 0xA7FA: +case 0xA7FB: +case 0xA7FC: +case 0xA7FD: +case 0xA7FE: +case 0xA7FF: +case 0xA800: +case 0xA801: +case 0xA802: +case 0xA803: +case 0xA804: +case 0xA805: +case 0xA806: +case 0xA807: +case 0xA808: +case 0xA809: +case 0xA80A: +case 0xA80B: +case 0xA80C: +case 0xA80D: +case 0xA80E: +case 0xA80F: +case 0xA810: +case 0xA811: +case 0xA812: +case 0xA813: +case 0xA814: +case 0xA815: +case 0xA816: +case 0xA817: +case 0xA818: +case 0xA819: +case 0xA81A: +case 0xA81B: +case 0xA81C: +case 0xA81D: +case 0xA81E: +case 0xA81F: +case 0xA820: +case 0xA821: +case 0xA822: +case 0xA823: +case 0xA824: +case 0xA825: +case 0xA826: +case 0xA827: +case 0xA828: +case 0xA829: +case 0xA82A: +case 0xA82B: +case 0xA82C: +case 0xA82D: +case 0xA82E: +case 0xA82F: +case 0xA830: +case 0xA831: +case 0xA832: +case 0xA833: +case 0xA834: +case 0xA835: +case 0xA836: +case 0xA837: +case 0xA838: +case 0xA839: +case 0xA83A: +case 0xA83B: +case 0xA83C: +case 0xA83D: +case 0xA83E: +case 0xA83F: +case 0xA840: +case 0xA841: +case 0xA842: +case 0xA843: +case 0xA844: +case 0xA845: +case 0xA846: +case 0xA847: +case 0xA848: +case 0xA849: +case 0xA84A: +case 0xA84B: +case 0xA84C: +case 0xA84D: +case 0xA84E: +case 0xA84F: +case 0xA850: +case 0xA851: +case 0xA852: +case 0xA853: +case 0xA854: +case 0xA855: +case 0xA856: +case 0xA857: +case 0xA858: +case 0xA859: +case 0xA85A: +case 0xA85B: +case 0xA85C: +case 0xA85D: +case 0xA85E: +case 0xA85F: +case 0xA860: +case 0xA861: +case 0xA862: +case 0xA863: +case 0xA864: +case 0xA865: +case 0xA866: +case 0xA867: +case 0xA868: +case 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0xA985: +case 0xA986: +case 0xA987: +case 0xA988: +case 0xA989: +case 0xA98A: +case 0xA98B: +case 0xA98C: +case 0xA98D: +case 0xA98E: +case 0xA98F: +case 0xA990: +case 0xA991: +case 0xA992: +case 0xA993: +case 0xA994: +case 0xA995: +case 0xA996: +case 0xA997: +case 0xA998: +case 0xA999: +case 0xA99A: +case 0xA99B: +case 0xA99C: +case 0xA99D: +case 0xA99E: +case 0xA99F: +case 0xA9A0: +case 0xA9A1: +case 0xA9A2: +case 0xA9A3: +case 0xA9A4: +case 0xA9A5: +case 0xA9A6: +case 0xA9A7: +case 0xA9A8: +case 0xA9A9: +case 0xA9AA: +case 0xA9AB: +case 0xA9AC: +case 0xA9AD: +case 0xA9AE: +case 0xA9AF: +case 0xA9B0: +case 0xA9B1: +case 0xA9B2: +case 0xA9B3: +case 0xA9B4: +case 0xA9B5: +case 0xA9B6: +case 0xA9B7: +case 0xA9B8: +case 0xA9B9: +case 0xA9BA: +case 0xA9BB: +case 0xA9BC: +case 0xA9BD: +case 0xA9BE: +case 0xA9BF: +case 0xA9C0: +case 0xA9C1: +case 0xA9C2: +case 0xA9C3: +case 0xA9C4: +case 0xA9C5: +case 0xA9C6: +case 0xA9C7: +case 0xA9C8: +case 0xA9C9: +case 0xA9CA: +case 0xA9CB: +case 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0xAD67: +case 0xAD68: +case 0xAD69: +case 0xAD6A: +case 0xAD6B: +case 0xAD6C: +case 0xAD6D: +case 0xAD6E: +case 0xAD6F: +case 0xAD70: +case 0xAD71: +case 0xAD72: +case 0xAD73: +case 0xAD74: +case 0xAD75: +case 0xAD76: +case 0xAD77: +case 0xAD78: +case 0xAD79: +case 0xAD7A: +case 0xAD7B: +case 0xAD7C: +case 0xAD7D: +case 0xAD7E: +case 0xAD7F: +case 0xAD80: +case 0xAD81: +case 0xAD82: +case 0xAD83: +case 0xAD84: +case 0xAD85: +case 0xAD86: +case 0xAD87: +case 0xAD88: +case 0xAD89: +case 0xAD8A: +case 0xAD8B: +case 0xAD8C: +case 0xAD8D: +case 0xAD8E: +case 0xAD8F: +case 0xAD90: +case 0xAD91: +case 0xAD92: +case 0xAD93: +case 0xAD94: +case 0xAD95: +case 0xAD96: +case 0xAD97: +case 0xAD98: +case 0xAD99: +case 0xAD9A: +case 0xAD9B: +case 0xAD9C: +case 0xAD9D: +case 0xAD9E: +case 0xAD9F: +case 0xADA0: +case 0xADA1: +case 0xADA2: +case 0xADA3: +case 0xADA4: +case 0xADA5: +case 0xADA6: +case 0xADA7: +case 0xADA8: +case 0xADA9: +case 0xADAA: +case 0xADAB: +case 0xADAC: +case 0xADAD: +case 0xADAE: +case 0xADAF: +case 0xADB0: +case 0xADB1: +case 0xADB2: +case 0xADB3: +case 0xADB4: +case 0xADB5: +case 0xADB6: +case 0xADB7: +case 0xADB8: +case 0xADB9: +case 0xADBA: +case 0xADBB: +case 0xADBC: +case 0xADBD: +case 0xADBE: +case 0xADBF: +case 0xADC0: +case 0xADC1: +case 0xADC2: +case 0xADC3: +case 0xADC4: +case 0xADC5: +case 0xADC6: +case 0xADC7: +case 0xADC8: +case 0xADC9: +case 0xADCA: +case 0xADCB: +case 0xADCC: +case 0xADCD: +case 0xADCE: +case 0xADCF: +case 0xADD0: +case 0xADD1: +case 0xADD2: +case 0xADD3: +case 0xADD4: +case 0xADD5: +case 0xADD6: +case 0xADD7: +case 0xADD8: +case 0xADD9: +case 0xADDA: +case 0xADDB: +case 0xADDC: +case 0xADDD: +case 0xADDE: +case 0xADDF: +case 0xADE0: +case 0xADE1: +case 0xADE2: +case 0xADE3: +case 0xADE4: +case 0xADE5: +case 0xADE6: +case 0xADE7: +case 0xADE8: +case 0xADE9: +case 0xADEA: +case 0xADEB: +case 0xADEC: +case 0xADED: +case 0xADEE: +case 0xADEF: +case 0xADF0: +case 0xADF1: +case 0xADF2: +case 0xADF3: +case 0xADF4: +case 0xADF5: +case 0xADF6: +case 0xADF7: +case 0xADF8: +case 0xADF9: +case 0xADFA: +case 0xADFB: +case 0xADFC: +case 0xADFD: +case 0xADFE: +case 0xADFF: +case 0xAE00: +case 0xAE01: +case 0xAE02: +case 0xAE03: +case 0xAE04: +case 0xAE05: +case 0xAE06: +case 0xAE07: +case 0xAE08: +case 0xAE09: +case 0xAE0A: +case 0xAE0B: +case 0xAE0C: +case 0xAE0D: +case 0xAE0E: +case 0xAE0F: +case 0xAE10: +case 0xAE11: +case 0xAE12: +case 0xAE13: +case 0xAE14: +case 0xAE15: +case 0xAE16: +case 0xAE17: +case 0xAE18: +case 0xAE19: +case 0xAE1A: +case 0xAE1B: +case 0xAE1C: +case 0xAE1D: +case 0xAE1E: +case 0xAE1F: +case 0xAE20: +case 0xAE21: +case 0xAE22: +case 0xAE23: +case 0xAE24: +case 0xAE25: +case 0xAE26: +case 0xAE27: +case 0xAE28: +case 0xAE29: +case 0xAE2A: +case 0xAE2B: +case 0xAE2C: +case 0xAE2D: +case 0xAE2E: +case 0xAE2F: +case 0xAE30: +case 0xAE31: +case 0xAE32: +case 0xAE33: +case 0xAE34: +case 0xAE35: +case 0xAE36: +case 0xAE37: +case 0xAE38: +case 0xAE39: +case 0xAE3A: +case 0xAE3B: +case 0xAE3C: +case 0xAE3D: +case 0xAE3E: +case 0xAE3F: +case 0xAE40: +case 0xAE41: +case 0xAE42: +case 0xAE43: +case 0xAE44: +case 0xAE45: +case 0xAE46: +case 0xAE47: +case 0xAE48: +case 0xAE49: +case 0xAE4A: +case 0xAE4B: +case 0xAE4C: +case 0xAE4D: +case 0xAE4E: +case 0xAE4F: +case 0xAE50: +case 0xAE51: +case 0xAE52: +case 0xAE53: +case 0xAE54: +case 0xAE55: +case 0xAE56: +case 0xAE57: +case 0xAE58: +case 0xAE59: +case 0xAE5A: +case 0xAE5B: +case 0xAE5C: +case 0xAE5D: +case 0xAE5E: +case 0xAE5F: +case 0xAE60: +case 0xAE61: +case 0xAE62: +case 0xAE63: +case 0xAE64: +case 0xAE65: +case 0xAE66: +case 0xAE67: +case 0xAE68: +case 0xAE69: +case 0xAE6A: +case 0xAE6B: +case 0xAE6C: +case 0xAE6D: +case 0xAE6E: +case 0xAE6F: +case 0xAE70: +case 0xAE71: +case 0xAE72: +case 0xAE73: +case 0xAE74: +case 0xAE75: +case 0xAE76: +case 0xAE77: +case 0xAE78: +case 0xAE79: +case 0xAE7A: +case 0xAE7B: +case 0xAE7C: +case 0xAE7D: +case 0xAE7E: +case 0xAE7F: +case 0xAE80: +case 0xAE81: +case 0xAE82: +case 0xAE83: +case 0xAE84: +case 0xAE85: +case 0xAE86: +case 0xAE87: +case 0xAE88: +case 0xAE89: +case 0xAE8A: +case 0xAE8B: +case 0xAE8C: +case 0xAE8D: +case 0xAE8E: +case 0xAE8F: +case 0xAE90: +case 0xAE91: +case 0xAE92: +case 0xAE93: +case 0xAE94: +case 0xAE95: +case 0xAE96: +case 0xAE97: +case 0xAE98: +case 0xAE99: +case 0xAE9A: +case 0xAE9B: +case 0xAE9C: +case 0xAE9D: +case 0xAE9E: +case 0xAE9F: +case 0xAEA0: +case 0xAEA1: +case 0xAEA2: +case 0xAEA3: +case 0xAEA4: +case 0xAEA5: +case 0xAEA6: +case 0xAEA7: +case 0xAEA8: +case 0xAEA9: +case 0xAEAA: +case 0xAEAB: +case 0xAEAC: +case 0xAEAD: +case 0xAEAE: +case 0xAEAF: +case 0xAEB0: +case 0xAEB1: +case 0xAEB2: +case 0xAEB3: +case 0xAEB4: +case 0xAEB5: +case 0xAEB6: +case 0xAEB7: +case 0xAEB8: +case 0xAEB9: +case 0xAEBA: +case 0xAEBB: +case 0xAEBC: +case 0xAEBD: +case 0xAEBE: +case 0xAEBF: +case 0xAEC0: +case 0xAEC1: +case 0xAEC2: +case 0xAEC3: +case 0xAEC4: +case 0xAEC5: +case 0xAEC6: +case 0xAEC7: +case 0xAEC8: +case 0xAEC9: +case 0xAECA: +case 0xAECB: +case 0xAECC: +case 0xAECD: +case 0xAECE: +case 0xAECF: +case 0xAED0: +case 0xAED1: +case 0xAED2: +case 0xAED3: +case 0xAED4: +case 0xAED5: +case 0xAED6: +case 0xAED7: +case 0xAED8: +case 0xAED9: +case 0xAEDA: +case 0xAEDB: +case 0xAEDC: +case 0xAEDD: +case 0xAEDE: +case 0xAEDF: +case 0xAEE0: +case 0xAEE1: +case 0xAEE2: +case 0xAEE3: +case 0xAEE4: +case 0xAEE5: +case 0xAEE6: +case 0xAEE7: +case 0xAEE8: +case 0xAEE9: +case 0xAEEA: +case 0xAEEB: +case 0xAEEC: +case 0xAEED: +case 0xAEEE: +case 0xAEEF: +case 0xAEF0: +case 0xAEF1: +case 0xAEF2: +case 0xAEF3: +case 0xAEF4: +case 0xAEF5: +case 0xAEF6: +case 0xAEF7: +case 0xAEF8: +case 0xAEF9: +case 0xAEFA: +case 0xAEFB: +case 0xAEFC: +case 0xAEFD: +case 0xAEFE: +case 0xAEFF: +case 0xAF00: +case 0xAF01: +case 0xAF02: +case 0xAF03: +case 0xAF04: +case 0xAF05: +case 0xAF06: +case 0xAF07: +case 0xAF08: +case 0xAF09: +case 0xAF0A: +case 0xAF0B: +case 0xAF0C: +case 0xAF0D: +case 0xAF0E: +case 0xAF0F: +case 0xAF10: +case 0xAF11: +case 0xAF12: +case 0xAF13: +case 0xAF14: +case 0xAF15: +case 0xAF16: +case 0xAF17: +case 0xAF18: +case 0xAF19: +case 0xAF1A: +case 0xAF1B: +case 0xAF1C: +case 0xAF1D: +case 0xAF1E: +case 0xAF1F: +case 0xAF20: +case 0xAF21: +case 0xAF22: +case 0xAF23: +case 0xAF24: +case 0xAF25: +case 0xAF26: +case 0xAF27: +case 0xAF28: +case 0xAF29: +case 0xAF2A: +case 0xAF2B: +case 0xAF2C: +case 0xAF2D: +case 0xAF2E: +case 0xAF2F: +case 0xAF30: +case 0xAF31: +case 0xAF32: +case 0xAF33: +case 0xAF34: +case 0xAF35: +case 0xAF36: +case 0xAF37: +case 0xAF38: +case 0xAF39: +case 0xAF3A: +case 0xAF3B: +case 0xAF3C: +case 0xAF3D: +case 0xAF3E: +case 0xAF3F: +case 0xAF40: +case 0xAF41: +case 0xAF42: +case 0xAF43: +case 0xAF44: +case 0xAF45: +case 0xAF46: +case 0xAF47: +case 0xAF48: +case 0xAF49: +case 0xAF4A: +case 0xAF4B: +case 0xAF4C: +case 0xAF4D: +case 0xAF4E: +case 0xAF4F: +case 0xAF50: +case 0xAF51: +case 0xAF52: +case 0xAF53: +case 0xAF54: +case 0xAF55: +case 0xAF56: +case 0xAF57: +case 0xAF58: +case 0xAF59: +case 0xAF5A: +case 0xAF5B: +case 0xAF5C: +case 0xAF5D: +case 0xAF5E: +case 0xAF5F: +case 0xAF60: +case 0xAF61: +case 0xAF62: +case 0xAF63: +case 0xAF64: +case 0xAF65: +case 0xAF66: +case 0xAF67: +case 0xAF68: +case 0xAF69: +case 0xAF6A: +case 0xAF6B: +case 0xAF6C: +case 0xAF6D: +case 0xAF6E: +case 0xAF6F: +case 0xAF70: +case 0xAF71: +case 0xAF72: +case 0xAF73: +case 0xAF74: +case 0xAF75: +case 0xAF76: +case 0xAF77: +case 0xAF78: +case 0xAF79: +case 0xAF7A: +case 0xAF7B: +case 0xAF7C: +case 0xAF7D: +case 0xAF7E: +case 0xAF7F: +case 0xAF80: +case 0xAF81: +case 0xAF82: +case 0xAF83: +case 0xAF84: +case 0xAF85: +case 0xAF86: +case 0xAF87: +case 0xAF88: +case 0xAF89: +case 0xAF8A: +case 0xAF8B: +case 0xAF8C: +case 0xAF8D: +case 0xAF8E: +case 0xAF8F: +case 0xAF90: +case 0xAF91: +case 0xAF92: +case 0xAF93: +case 0xAF94: +case 0xAF95: +case 0xAF96: +case 0xAF97: +case 0xAF98: +case 0xAF99: +case 0xAF9A: +case 0xAF9B: +case 0xAF9C: +case 0xAF9D: +case 0xAF9E: +case 0xAF9F: +case 0xAFA0: +case 0xAFA1: +case 0xAFA2: +case 0xAFA3: +case 0xAFA4: +case 0xAFA5: +case 0xAFA6: +case 0xAFA7: +case 0xAFA8: +case 0xAFA9: +case 0xAFAA: +case 0xAFAB: +case 0xAFAC: +case 0xAFAD: +case 0xAFAE: +case 0xAFAF: +case 0xAFB0: +case 0xAFB1: +case 0xAFB2: +case 0xAFB3: +case 0xAFB4: +case 0xAFB5: +case 0xAFB6: +case 0xAFB7: +case 0xAFB8: +case 0xAFB9: +case 0xAFBA: +case 0xAFBB: +case 0xAFBC: +case 0xAFBD: +case 0xAFBE: +case 0xAFBF: +case 0xAFC0: +case 0xAFC1: +case 0xAFC2: +case 0xAFC3: +case 0xAFC4: +case 0xAFC5: +case 0xAFC6: +case 0xAFC7: +case 0xAFC8: +case 0xAFC9: +case 0xAFCA: +case 0xAFCB: +case 0xAFCC: +case 0xAFCD: +case 0xAFCE: +case 0xAFCF: +case 0xAFD0: +case 0xAFD1: +case 0xAFD2: +case 0xAFD3: +case 0xAFD4: +case 0xAFD5: +case 0xAFD6: +case 0xAFD7: +case 0xAFD8: +case 0xAFD9: +case 0xAFDA: +case 0xAFDB: +case 0xAFDC: +case 0xAFDD: +case 0xAFDE: +case 0xAFDF: +case 0xAFE0: +case 0xAFE1: +case 0xAFE2: +case 0xAFE3: +case 0xAFE4: +case 0xAFE5: +case 0xAFE6: +case 0xAFE7: +case 0xAFE8: +case 0xAFE9: +case 0xAFEA: +case 0xAFEB: +case 0xAFEC: +case 0xAFED: +case 0xAFEE: +case 0xAFEF: +case 0xAFF0: +case 0xAFF1: +case 0xAFF2: +case 0xAFF3: +case 0xAFF4: +case 0xAFF5: +case 0xAFF6: +case 0xAFF7: +case 0xAFF8: +case 0xAFF9: +case 0xAFFA: +case 0xAFFB: +case 0xAFFC: +case 0xAFFD: +case 0xAFFE: +case 0xAFFF: + +// 1010 +case 0xA000: +{ + u32 res; + PC -= 2; + if (!CPU->flag_S) + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + } + res = C68K_1010_EX; + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + POST_IO +} +RET(4) diff --git a/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68k_opB.inc b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68k_opB.inc new file mode 100644 index 000000000..17c9477ec --- /dev/null +++ b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68k_opB.inc @@ -0,0 +1,5970 @@ +case 0xB200: +case 0xB400: +case 0xB600: +case 0xB800: +case 0xBA00: +case 0xBC00: +case 0xBE00: +case 0xB001: +case 0xB201: +case 0xB401: +case 0xB601: +case 0xB801: +case 0xBA01: +case 0xBC01: +case 0xBE01: +case 0xB002: +case 0xB202: +case 0xB402: +case 0xB602: +case 0xB802: +case 0xBA02: +case 0xBC02: +case 0xBE02: +case 0xB003: +case 0xB203: +case 0xB403: +case 0xB603: +case 0xB803: +case 0xBA03: +case 0xBC03: +case 0xBE03: +case 0xB004: +case 0xB204: +case 0xB404: +case 0xB604: +case 0xB804: +case 0xBA04: +case 0xBC04: +case 0xBE04: +case 0xB005: +case 0xB205: +case 0xB405: +case 0xB605: +case 0xB805: +case 0xBA05: +case 0xBC05: +case 0xBE05: +case 0xB006: +case 0xB206: +case 0xB406: +case 0xB606: +case 0xB806: +case 0xBA06: +case 0xBC06: +case 0xBE06: +case 0xB007: +case 0xB207: +case 0xB407: +case 0xB607: +case 0xB807: +case 0xBA07: +case 0xBC07: +case 0xBE07: + +// CMP +case 0xB000: +{ + u32 res; + pointer dst; + pointer src; + src = (u8)CPU->D[(Opcode >> 0) & 7]; + dst = (u8)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_N = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; +} +RET(4) +case 0xB208: +case 0xB408: +case 0xB608: +case 0xB808: +case 0xBA08: +case 0xBC08: +case 0xBE08: +case 0xB009: +case 0xB209: +case 0xB409: +case 0xB609: +case 0xB809: +case 0xBA09: +case 0xBC09: +case 0xBE09: +case 0xB00A: +case 0xB20A: +case 0xB40A: +case 0xB60A: +case 0xB80A: +case 0xBA0A: +case 0xBC0A: +case 0xBE0A: +case 0xB00B: +case 0xB20B: +case 0xB40B: +case 0xB60B: +case 0xB80B: +case 0xBA0B: +case 0xBC0B: +case 0xBE0B: +case 0xB00C: +case 0xB20C: +case 0xB40C: +case 0xB60C: +case 0xB80C: +case 0xBA0C: +case 0xBC0C: +case 0xBE0C: +case 0xB00D: +case 0xB20D: +case 0xB40D: +case 0xB60D: +case 0xB80D: +case 0xBA0D: +case 0xBC0D: +case 0xBE0D: +case 0xB00E: +case 0xB20E: +case 0xB40E: +case 0xB60E: +case 0xB80E: +case 0xBA0E: +case 0xBC0E: +case 0xBE0E: +case 0xB00F: +case 0xB20F: +case 0xB40F: +case 0xB60F: +case 0xB80F: +case 0xBA0F: +case 0xBC0F: +case 0xBE0F: + +// CMP +case 0xB008: +{ + u32 res; + pointer dst; + pointer src; + // can't read byte from Ax registers ! + CPU->Status |= C68K_FAULTED; + CCnt = 0; + goto C68k_Exec_Really_End; + dst = (u8)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_N = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; +} +RET(4) +case 0xB210: +case 0xB410: +case 0xB610: +case 0xB810: +case 0xBA10: +case 0xBC10: +case 0xBE10: +case 0xB011: +case 0xB211: +case 0xB411: +case 0xB611: +case 0xB811: +case 0xBA11: +case 0xBC11: +case 0xBE11: +case 0xB012: +case 0xB212: +case 0xB412: +case 0xB612: +case 0xB812: +case 0xBA12: +case 0xBC12: +case 0xBE12: +case 0xB013: +case 0xB213: +case 0xB413: +case 0xB613: +case 0xB813: +case 0xBA13: +case 0xBC13: +case 0xBE13: +case 0xB014: +case 0xB214: +case 0xB414: +case 0xB614: +case 0xB814: +case 0xBA14: +case 0xBC14: +case 0xBE14: +case 0xB015: +case 0xB215: +case 0xB415: +case 0xB615: +case 0xB815: +case 0xBA15: +case 0xBC15: +case 0xBE15: +case 0xB016: +case 0xB216: +case 0xB416: +case 0xB616: +case 0xB816: +case 0xBA16: +case 0xBC16: +case 0xBE16: +case 0xB017: +case 0xB217: +case 0xB417: +case 0xB617: +case 0xB817: +case 0xBA17: +case 0xBC17: +case 0xBE17: + +// CMP +case 0xB010: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_BYTE_F(adr, src) + dst = (u8)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_N = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + POST_IO +} +RET(8) +case 0xB218: +case 0xB418: +case 0xB618: +case 0xB818: +case 0xBA18: +case 0xBC18: +case 0xBE18: +case 0xB019: +case 0xB219: +case 0xB419: +case 0xB619: +case 0xB819: +case 0xBA19: +case 0xBC19: +case 0xBE19: +case 0xB01A: +case 0xB21A: +case 0xB41A: +case 0xB61A: +case 0xB81A: +case 0xBA1A: +case 0xBC1A: +case 0xBE1A: +case 0xB01B: +case 0xB21B: +case 0xB41B: +case 0xB61B: +case 0xB81B: +case 0xBA1B: +case 0xBC1B: +case 0xBE1B: +case 0xB01C: +case 0xB21C: +case 0xB41C: +case 0xB61C: +case 0xB81C: +case 0xBA1C: +case 0xBC1C: +case 0xBE1C: +case 0xB01D: +case 0xB21D: +case 0xB41D: +case 0xB61D: +case 0xB81D: +case 0xBA1D: +case 0xBC1D: +case 0xBE1D: +case 0xB01E: +case 0xB21E: +case 0xB41E: +case 0xB61E: +case 0xB81E: +case 0xBA1E: +case 0xBC1E: +case 0xBE1E: + +// CMP +case 0xB018: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + PRE_IO + READ_BYTE_F(adr, src) + dst = (u8)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_N = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + POST_IO +} +RET(8) +case 0xB220: +case 0xB420: +case 0xB620: +case 0xB820: +case 0xBA20: +case 0xBC20: +case 0xBE20: +case 0xB021: +case 0xB221: +case 0xB421: +case 0xB621: +case 0xB821: +case 0xBA21: +case 0xBC21: +case 0xBE21: +case 0xB022: +case 0xB222: +case 0xB422: +case 0xB622: +case 0xB822: +case 0xBA22: +case 0xBC22: +case 0xBE22: +case 0xB023: +case 0xB223: +case 0xB423: +case 0xB623: +case 0xB823: +case 0xBA23: +case 0xBC23: +case 0xBE23: +case 0xB024: +case 0xB224: +case 0xB424: +case 0xB624: +case 0xB824: +case 0xBA24: +case 0xBC24: +case 0xBE24: +case 0xB025: +case 0xB225: +case 0xB425: +case 0xB625: +case 0xB825: +case 0xBA25: +case 0xBC25: +case 0xBE25: +case 0xB026: +case 0xB226: +case 0xB426: +case 0xB626: +case 0xB826: +case 0xBA26: +case 0xBC26: +case 0xBE26: + +// CMP +case 0xB020: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_BYTE_F(adr, src) + dst = (u8)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_N = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + POST_IO +} +RET(10) +case 0xB228: +case 0xB428: +case 0xB628: +case 0xB828: +case 0xBA28: +case 0xBC28: +case 0xBE28: +case 0xB029: +case 0xB229: +case 0xB429: +case 0xB629: +case 0xB829: +case 0xBA29: +case 0xBC29: +case 0xBE29: +case 0xB02A: +case 0xB22A: +case 0xB42A: +case 0xB62A: +case 0xB82A: +case 0xBA2A: +case 0xBC2A: +case 0xBE2A: +case 0xB02B: +case 0xB22B: +case 0xB42B: +case 0xB62B: +case 0xB82B: +case 0xBA2B: +case 0xBC2B: +case 0xBE2B: +case 0xB02C: +case 0xB22C: +case 0xB42C: +case 0xB62C: +case 0xB82C: +case 0xBA2C: +case 0xBC2C: +case 0xBE2C: +case 0xB02D: +case 0xB22D: +case 0xB42D: +case 0xB62D: +case 0xB82D: +case 0xBA2D: +case 0xBC2D: +case 0xBE2D: +case 0xB02E: +case 0xB22E: +case 0xB42E: +case 0xB62E: +case 0xB82E: +case 0xBA2E: +case 0xBC2E: +case 0xBE2E: +case 0xB02F: +case 0xB22F: +case 0xB42F: +case 0xB62F: +case 0xB82F: +case 0xBA2F: +case 0xBC2F: +case 0xBE2F: + +// CMP +case 0xB028: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, src) + dst = (u8)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_N = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + POST_IO +} +RET(12) +case 0xB230: +case 0xB430: +case 0xB630: +case 0xB830: +case 0xBA30: +case 0xBC30: +case 0xBE30: +case 0xB031: +case 0xB231: +case 0xB431: +case 0xB631: +case 0xB831: +case 0xBA31: +case 0xBC31: +case 0xBE31: +case 0xB032: +case 0xB232: +case 0xB432: +case 0xB632: +case 0xB832: +case 0xBA32: +case 0xBC32: +case 0xBE32: +case 0xB033: +case 0xB233: +case 0xB433: +case 0xB633: +case 0xB833: +case 0xBA33: +case 0xBC33: +case 0xBE33: +case 0xB034: +case 0xB234: +case 0xB434: +case 0xB634: +case 0xB834: +case 0xBA34: +case 0xBC34: +case 0xBE34: +case 0xB035: +case 0xB235: +case 0xB435: +case 0xB635: +case 0xB835: +case 0xBA35: +case 0xBC35: +case 0xBE35: +case 0xB036: +case 0xB236: +case 0xB436: +case 0xB636: +case 0xB836: +case 0xBA36: +case 0xBC36: +case 0xBE36: +case 0xB037: +case 0xB237: +case 0xB437: +case 0xB637: +case 0xB837: +case 0xBA37: +case 0xBC37: +case 0xBE37: + +// CMP +case 0xB030: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, src) + dst = (u8)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_N = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + POST_IO +} +RET(14) +case 0xB238: +case 0xB438: +case 0xB638: +case 0xB838: +case 0xBA38: +case 0xBC38: +case 0xBE38: + +// CMP +case 0xB038: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, src) + dst = (u8)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_N = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + POST_IO +} +RET(12) +case 0xB239: +case 0xB439: +case 0xB639: +case 0xB839: +case 0xBA39: +case 0xBC39: +case 0xBE39: + +// CMP +case 0xB039: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_BYTE_F(adr, src) + dst = (u8)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_N = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + POST_IO +} +RET(16) +case 0xB23A: +case 0xB43A: +case 0xB63A: +case 0xB83A: +case 0xBA3A: +case 0xBC3A: +case 0xBE3A: + +// CMP +case 0xB03A: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, src) + dst = (u8)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_N = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + POST_IO +} +RET(12) +case 0xB23B: +case 0xB43B: +case 0xB63B: +case 0xB83B: +case 0xBA3B: +case 0xBC3B: +case 0xBE3B: + +// CMP +case 0xB03B: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, src) + dst = (u8)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_N = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + POST_IO +} +RET(14) +case 0xB23C: +case 0xB43C: +case 0xB63C: +case 0xB83C: +case 0xBA3C: +case 0xBC3C: +case 0xBE3C: + +// CMP +case 0xB03C: +{ + u32 res; + pointer dst; + pointer src; + src = FETCH_BYTE; + PC += 2; + dst = (u8)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_N = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; +} +RET(8) +case 0xB21F: +case 0xB41F: +case 0xB61F: +case 0xB81F: +case 0xBA1F: +case 0xBC1F: +case 0xBE1F: + +// CMP +case 0xB01F: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_BYTE_F(adr, src) + dst = (u8)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_N = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + POST_IO +} +RET(8) +case 0xB227: +case 0xB427: +case 0xB627: +case 0xB827: +case 0xBA27: +case 0xBC27: +case 0xBE27: + +// CMP +case 0xB027: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_BYTE_F(adr, src) + dst = (u8)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_N = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + POST_IO +} +RET(10) +case 0xB240: +case 0xB440: +case 0xB640: +case 0xB840: +case 0xBA40: +case 0xBC40: +case 0xBE40: +case 0xB041: +case 0xB241: +case 0xB441: +case 0xB641: +case 0xB841: +case 0xBA41: +case 0xBC41: +case 0xBE41: +case 0xB042: +case 0xB242: +case 0xB442: +case 0xB642: +case 0xB842: +case 0xBA42: +case 0xBC42: +case 0xBE42: +case 0xB043: +case 0xB243: +case 0xB443: +case 0xB643: +case 0xB843: +case 0xBA43: +case 0xBC43: +case 0xBE43: +case 0xB044: +case 0xB244: +case 0xB444: +case 0xB644: +case 0xB844: +case 0xBA44: +case 0xBC44: +case 0xBE44: +case 0xB045: +case 0xB245: +case 0xB445: +case 0xB645: +case 0xB845: +case 0xBA45: +case 0xBC45: +case 0xBE45: +case 0xB046: +case 0xB246: +case 0xB446: +case 0xB646: +case 0xB846: +case 0xBA46: +case 0xBC46: +case 0xBE46: +case 0xB047: +case 0xB247: +case 0xB447: +case 0xB647: +case 0xB847: +case 0xBA47: +case 0xBC47: +case 0xBE47: + +// CMP +case 0xB040: +{ + u32 res; + pointer dst; + pointer src; + src = (u16)CPU->D[(Opcode >> 0) & 7]; + dst = (u16)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; +} +RET(4) +case 0xB248: +case 0xB448: +case 0xB648: +case 0xB848: +case 0xBA48: +case 0xBC48: +case 0xBE48: +case 0xB049: +case 0xB249: +case 0xB449: +case 0xB649: +case 0xB849: +case 0xBA49: +case 0xBC49: +case 0xBE49: +case 0xB04A: +case 0xB24A: +case 0xB44A: +case 0xB64A: +case 0xB84A: +case 0xBA4A: +case 0xBC4A: +case 0xBE4A: +case 0xB04B: +case 0xB24B: +case 0xB44B: +case 0xB64B: +case 0xB84B: +case 0xBA4B: +case 0xBC4B: +case 0xBE4B: +case 0xB04C: +case 0xB24C: +case 0xB44C: +case 0xB64C: +case 0xB84C: +case 0xBA4C: +case 0xBC4C: +case 0xBE4C: +case 0xB04D: +case 0xB24D: +case 0xB44D: +case 0xB64D: +case 0xB84D: +case 0xBA4D: +case 0xBC4D: +case 0xBE4D: +case 0xB04E: +case 0xB24E: +case 0xB44E: +case 0xB64E: +case 0xB84E: +case 0xBA4E: +case 0xBC4E: +case 0xBE4E: +case 0xB04F: +case 0xB24F: +case 0xB44F: +case 0xB64F: +case 0xB84F: +case 0xBA4F: +case 0xBC4F: +case 0xBE4F: + +// CMP +case 0xB048: +{ + u32 res; + pointer dst; + pointer src; + src = (u16)CPU->A[(Opcode >> 0) & 7]; + dst = (u16)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; +} +RET(4) +case 0xB250: +case 0xB450: +case 0xB650: +case 0xB850: +case 0xBA50: +case 0xBC50: +case 0xBE50: +case 0xB051: +case 0xB251: +case 0xB451: +case 0xB651: +case 0xB851: +case 0xBA51: +case 0xBC51: +case 0xBE51: +case 0xB052: +case 0xB252: +case 0xB452: +case 0xB652: +case 0xB852: +case 0xBA52: +case 0xBC52: +case 0xBE52: +case 0xB053: +case 0xB253: +case 0xB453: +case 0xB653: +case 0xB853: +case 0xBA53: +case 0xBC53: +case 0xBE53: +case 0xB054: +case 0xB254: +case 0xB454: +case 0xB654: +case 0xB854: +case 0xBA54: +case 0xBC54: +case 0xBE54: +case 0xB055: +case 0xB255: +case 0xB455: +case 0xB655: +case 0xB855: +case 0xBA55: +case 0xBC55: +case 0xBE55: +case 0xB056: +case 0xB256: +case 0xB456: +case 0xB656: +case 0xB856: +case 0xBA56: +case 0xBC56: +case 0xBE56: +case 0xB057: +case 0xB257: +case 0xB457: +case 0xB657: +case 0xB857: +case 0xBA57: +case 0xBC57: +case 0xBE57: + +// CMP +case 0xB050: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_WORD_F(adr, src) + dst = (u16)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + POST_IO +} +RET(8) +case 0xB258: +case 0xB458: +case 0xB658: +case 0xB858: +case 0xBA58: +case 0xBC58: +case 0xBE58: +case 0xB059: +case 0xB259: +case 0xB459: +case 0xB659: +case 0xB859: +case 0xBA59: +case 0xBC59: +case 0xBE59: +case 0xB05A: +case 0xB25A: +case 0xB45A: +case 0xB65A: +case 0xB85A: +case 0xBA5A: +case 0xBC5A: +case 0xBE5A: +case 0xB05B: +case 0xB25B: +case 0xB45B: +case 0xB65B: +case 0xB85B: +case 0xBA5B: +case 0xBC5B: +case 0xBE5B: +case 0xB05C: +case 0xB25C: +case 0xB45C: +case 0xB65C: +case 0xB85C: +case 0xBA5C: +case 0xBC5C: +case 0xBE5C: +case 0xB05D: +case 0xB25D: +case 0xB45D: +case 0xB65D: +case 0xB85D: +case 0xBA5D: +case 0xBC5D: +case 0xBE5D: +case 0xB05E: +case 0xB25E: +case 0xB45E: +case 0xB65E: +case 0xB85E: +case 0xBA5E: +case 0xBC5E: +case 0xBE5E: + +// CMP +case 0xB058: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 2; + PRE_IO + READ_WORD_F(adr, src) + dst = (u16)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + POST_IO +} +RET(8) +case 0xB260: +case 0xB460: +case 0xB660: +case 0xB860: +case 0xBA60: +case 0xBC60: +case 0xBE60: +case 0xB061: +case 0xB261: +case 0xB461: +case 0xB661: +case 0xB861: +case 0xBA61: +case 0xBC61: +case 0xBE61: +case 0xB062: +case 0xB262: +case 0xB462: +case 0xB662: +case 0xB862: +case 0xBA62: +case 0xBC62: +case 0xBE62: +case 0xB063: +case 0xB263: +case 0xB463: +case 0xB663: +case 0xB863: +case 0xBA63: +case 0xBC63: +case 0xBE63: +case 0xB064: +case 0xB264: +case 0xB464: +case 0xB664: +case 0xB864: +case 0xBA64: +case 0xBC64: +case 0xBE64: +case 0xB065: +case 0xB265: +case 0xB465: +case 0xB665: +case 0xB865: +case 0xBA65: +case 0xBC65: +case 0xBE65: +case 0xB066: +case 0xB266: +case 0xB466: +case 0xB666: +case 0xB866: +case 0xBA66: +case 0xBC66: +case 0xBE66: + +// CMP +case 0xB060: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 2; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_WORD_F(adr, src) + dst = (u16)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + POST_IO +} +RET(10) +case 0xB268: +case 0xB468: +case 0xB668: +case 0xB868: +case 0xBA68: +case 0xBC68: +case 0xBE68: +case 0xB069: +case 0xB269: +case 0xB469: +case 0xB669: +case 0xB869: +case 0xBA69: +case 0xBC69: +case 0xBE69: +case 0xB06A: +case 0xB26A: +case 0xB46A: +case 0xB66A: +case 0xB86A: +case 0xBA6A: +case 0xBC6A: +case 0xBE6A: +case 0xB06B: +case 0xB26B: +case 0xB46B: +case 0xB66B: +case 0xB86B: +case 0xBA6B: +case 0xBC6B: +case 0xBE6B: +case 0xB06C: +case 0xB26C: +case 0xB46C: +case 0xB66C: +case 0xB86C: +case 0xBA6C: +case 0xBC6C: +case 0xBE6C: +case 0xB06D: +case 0xB26D: +case 0xB46D: +case 0xB66D: +case 0xB86D: +case 0xBA6D: +case 0xBC6D: +case 0xBE6D: +case 0xB06E: +case 0xB26E: +case 0xB46E: +case 0xB66E: +case 0xB86E: +case 0xBA6E: +case 0xBC6E: +case 0xBE6E: +case 0xB06F: +case 0xB26F: +case 0xB46F: +case 0xB66F: +case 0xB86F: +case 0xBA6F: +case 0xBC6F: +case 0xBE6F: + +// CMP +case 0xB068: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, src) + dst = (u16)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + POST_IO +} +RET(12) +case 0xB270: +case 0xB470: +case 0xB670: +case 0xB870: +case 0xBA70: +case 0xBC70: +case 0xBE70: +case 0xB071: +case 0xB271: +case 0xB471: +case 0xB671: +case 0xB871: +case 0xBA71: +case 0xBC71: +case 0xBE71: +case 0xB072: +case 0xB272: +case 0xB472: +case 0xB672: +case 0xB872: +case 0xBA72: +case 0xBC72: +case 0xBE72: +case 0xB073: +case 0xB273: +case 0xB473: +case 0xB673: +case 0xB873: +case 0xBA73: +case 0xBC73: +case 0xBE73: +case 0xB074: +case 0xB274: +case 0xB474: +case 0xB674: +case 0xB874: +case 0xBA74: +case 0xBC74: +case 0xBE74: +case 0xB075: +case 0xB275: +case 0xB475: +case 0xB675: +case 0xB875: +case 0xBA75: +case 0xBC75: +case 0xBE75: +case 0xB076: +case 0xB276: +case 0xB476: +case 0xB676: +case 0xB876: +case 0xBA76: +case 0xBC76: +case 0xBE76: +case 0xB077: +case 0xB277: +case 0xB477: +case 0xB677: +case 0xB877: +case 0xBA77: +case 0xBC77: +case 0xBE77: + +// CMP +case 0xB070: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, src) + dst = (u16)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + POST_IO +} +RET(14) +case 0xB278: +case 0xB478: +case 0xB678: +case 0xB878: +case 0xBA78: +case 0xBC78: +case 0xBE78: + +// CMP +case 0xB078: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, src) + dst = (u16)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + POST_IO +} +RET(12) +case 0xB279: +case 0xB479: +case 0xB679: +case 0xB879: +case 0xBA79: +case 0xBC79: +case 0xBE79: + +// CMP +case 0xB079: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_WORD_F(adr, src) + dst = (u16)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + POST_IO +} +RET(16) +case 0xB27A: +case 0xB47A: +case 0xB67A: +case 0xB87A: +case 0xBA7A: +case 0xBC7A: +case 0xBE7A: + +// CMP +case 0xB07A: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, src) + dst = (u16)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + POST_IO +} +RET(12) +case 0xB27B: +case 0xB47B: +case 0xB67B: +case 0xB87B: +case 0xBA7B: +case 0xBC7B: +case 0xBE7B: + +// CMP +case 0xB07B: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, src) + dst = (u16)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + POST_IO +} +RET(14) +case 0xB27C: +case 0xB47C: +case 0xB67C: +case 0xB87C: +case 0xBA7C: +case 0xBC7C: +case 0xBE7C: + +// CMP +case 0xB07C: +{ + u32 res; + pointer dst; + pointer src; + src = FETCH_WORD; + PC += 2; + dst = (u16)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; +} +RET(8) +case 0xB25F: +case 0xB45F: +case 0xB65F: +case 0xB85F: +case 0xBA5F: +case 0xBC5F: +case 0xBE5F: + +// CMP +case 0xB05F: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_WORD_F(adr, src) + dst = (u16)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + POST_IO +} +RET(8) +case 0xB267: +case 0xB467: +case 0xB667: +case 0xB867: +case 0xBA67: +case 0xBC67: +case 0xBE67: + +// CMP +case 0xB067: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_WORD_F(adr, src) + dst = (u16)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + POST_IO +} +RET(10) +case 0xB280: +case 0xB480: +case 0xB680: +case 0xB880: +case 0xBA80: +case 0xBC80: +case 0xBE80: +case 0xB081: +case 0xB281: +case 0xB481: +case 0xB681: +case 0xB881: +case 0xBA81: +case 0xBC81: +case 0xBE81: +case 0xB082: +case 0xB282: +case 0xB482: +case 0xB682: +case 0xB882: +case 0xBA82: +case 0xBC82: +case 0xBE82: +case 0xB083: +case 0xB283: +case 0xB483: +case 0xB683: +case 0xB883: +case 0xBA83: +case 0xBC83: +case 0xBE83: +case 0xB084: +case 0xB284: +case 0xB484: +case 0xB684: +case 0xB884: +case 0xBA84: +case 0xBC84: +case 0xBE84: +case 0xB085: +case 0xB285: +case 0xB485: +case 0xB685: +case 0xB885: +case 0xBA85: +case 0xBC85: +case 0xBE85: +case 0xB086: +case 0xB286: +case 0xB486: +case 0xB686: +case 0xB886: +case 0xBA86: +case 0xBC86: +case 0xBE86: +case 0xB087: +case 0xB287: +case 0xB487: +case 0xB687: +case 0xB887: +case 0xBA87: +case 0xBC87: +case 0xBE87: + +// CMP +case 0xB080: +{ + u32 res; + pointer dst; + pointer src; + src = (u32)CPU->D[(Opcode >> 0) & 7]; + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; +} +RET(6) +case 0xB288: +case 0xB488: +case 0xB688: +case 0xB888: +case 0xBA88: +case 0xBC88: +case 0xBE88: +case 0xB089: +case 0xB289: +case 0xB489: +case 0xB689: +case 0xB889: +case 0xBA89: +case 0xBC89: +case 0xBE89: +case 0xB08A: +case 0xB28A: +case 0xB48A: +case 0xB68A: +case 0xB88A: +case 0xBA8A: +case 0xBC8A: +case 0xBE8A: +case 0xB08B: +case 0xB28B: +case 0xB48B: +case 0xB68B: +case 0xB88B: +case 0xBA8B: +case 0xBC8B: +case 0xBE8B: +case 0xB08C: +case 0xB28C: +case 0xB48C: +case 0xB68C: +case 0xB88C: +case 0xBA8C: +case 0xBC8C: +case 0xBE8C: +case 0xB08D: +case 0xB28D: +case 0xB48D: +case 0xB68D: +case 0xB88D: +case 0xBA8D: +case 0xBC8D: +case 0xBE8D: +case 0xB08E: +case 0xB28E: +case 0xB48E: +case 0xB68E: +case 0xB88E: +case 0xBA8E: +case 0xBC8E: +case 0xBE8E: +case 0xB08F: +case 0xB28F: +case 0xB48F: +case 0xB68F: +case 0xB88F: +case 0xBA8F: +case 0xBC8F: +case 0xBE8F: + +// CMP +case 0xB088: +{ + u32 res; + pointer dst; + pointer src; + src = (u32)CPU->A[(Opcode >> 0) & 7]; + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; +} +RET(6) +case 0xB290: +case 0xB490: +case 0xB690: +case 0xB890: +case 0xBA90: +case 0xBC90: +case 0xBE90: +case 0xB091: +case 0xB291: +case 0xB491: +case 0xB691: +case 0xB891: +case 0xBA91: +case 0xBC91: +case 0xBE91: +case 0xB092: +case 0xB292: +case 0xB492: +case 0xB692: +case 0xB892: +case 0xBA92: +case 0xBC92: +case 0xBE92: +case 0xB093: +case 0xB293: +case 0xB493: +case 0xB693: +case 0xB893: +case 0xBA93: +case 0xBC93: +case 0xBE93: +case 0xB094: +case 0xB294: +case 0xB494: +case 0xB694: +case 0xB894: +case 0xBA94: +case 0xBC94: +case 0xBE94: +case 0xB095: +case 0xB295: +case 0xB495: +case 0xB695: +case 0xB895: +case 0xBA95: +case 0xBC95: +case 0xBE95: +case 0xB096: +case 0xB296: +case 0xB496: +case 0xB696: +case 0xB896: +case 0xBA96: +case 0xBC96: +case 0xBE96: +case 0xB097: +case 0xB297: +case 0xB497: +case 0xB697: +case 0xB897: +case 0xBA97: +case 0xBC97: +case 0xBE97: + +// CMP +case 0xB090: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_LONG_F(adr, src) + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + POST_IO +} +RET(16) +case 0xB298: +case 0xB498: +case 0xB698: +case 0xB898: +case 0xBA98: +case 0xBC98: +case 0xBE98: +case 0xB099: +case 0xB299: +case 0xB499: +case 0xB699: +case 0xB899: +case 0xBA99: +case 0xBC99: +case 0xBE99: +case 0xB09A: +case 0xB29A: +case 0xB49A: +case 0xB69A: +case 0xB89A: +case 0xBA9A: +case 0xBC9A: +case 0xBE9A: +case 0xB09B: +case 0xB29B: +case 0xB49B: +case 0xB69B: +case 0xB89B: +case 0xBA9B: +case 0xBC9B: +case 0xBE9B: +case 0xB09C: +case 0xB29C: +case 0xB49C: +case 0xB69C: +case 0xB89C: +case 0xBA9C: +case 0xBC9C: +case 0xBE9C: +case 0xB09D: +case 0xB29D: +case 0xB49D: +case 0xB69D: +case 0xB89D: +case 0xBA9D: +case 0xBC9D: +case 0xBE9D: +case 0xB09E: +case 0xB29E: +case 0xB49E: +case 0xB69E: +case 0xB89E: +case 0xBA9E: +case 0xBC9E: +case 0xBE9E: + +// CMP +case 0xB098: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 4; + PRE_IO + READ_LONG_F(adr, src) + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + POST_IO +} +RET(16) +case 0xB2A0: +case 0xB4A0: +case 0xB6A0: +case 0xB8A0: +case 0xBAA0: +case 0xBCA0: +case 0xBEA0: +case 0xB0A1: +case 0xB2A1: +case 0xB4A1: +case 0xB6A1: +case 0xB8A1: +case 0xBAA1: +case 0xBCA1: +case 0xBEA1: +case 0xB0A2: +case 0xB2A2: +case 0xB4A2: +case 0xB6A2: +case 0xB8A2: +case 0xBAA2: +case 0xBCA2: +case 0xBEA2: +case 0xB0A3: +case 0xB2A3: +case 0xB4A3: +case 0xB6A3: +case 0xB8A3: +case 0xBAA3: +case 0xBCA3: +case 0xBEA3: +case 0xB0A4: +case 0xB2A4: +case 0xB4A4: +case 0xB6A4: +case 0xB8A4: +case 0xBAA4: +case 0xBCA4: +case 0xBEA4: +case 0xB0A5: +case 0xB2A5: +case 0xB4A5: +case 0xB6A5: +case 0xB8A5: +case 0xBAA5: +case 0xBCA5: +case 0xBEA5: +case 0xB0A6: +case 0xB2A6: +case 0xB4A6: +case 0xB6A6: +case 0xB8A6: +case 0xBAA6: +case 0xBCA6: +case 0xBEA6: + +// CMP +case 0xB0A0: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 4; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_LONG_F(adr, src) + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + POST_IO +} +RET(18) +case 0xB2A8: +case 0xB4A8: +case 0xB6A8: +case 0xB8A8: +case 0xBAA8: +case 0xBCA8: +case 0xBEA8: +case 0xB0A9: +case 0xB2A9: +case 0xB4A9: +case 0xB6A9: +case 0xB8A9: +case 0xBAA9: +case 0xBCA9: +case 0xBEA9: +case 0xB0AA: +case 0xB2AA: +case 0xB4AA: +case 0xB6AA: +case 0xB8AA: +case 0xBAAA: +case 0xBCAA: +case 0xBEAA: +case 0xB0AB: +case 0xB2AB: +case 0xB4AB: +case 0xB6AB: +case 0xB8AB: +case 0xBAAB: +case 0xBCAB: +case 0xBEAB: +case 0xB0AC: +case 0xB2AC: +case 0xB4AC: +case 0xB6AC: +case 0xB8AC: +case 0xBAAC: +case 0xBCAC: +case 0xBEAC: +case 0xB0AD: +case 0xB2AD: +case 0xB4AD: +case 0xB6AD: +case 0xB8AD: +case 0xBAAD: +case 0xBCAD: +case 0xBEAD: +case 0xB0AE: +case 0xB2AE: +case 0xB4AE: +case 0xB6AE: +case 0xB8AE: +case 0xBAAE: +case 0xBCAE: +case 0xBEAE: +case 0xB0AF: +case 0xB2AF: +case 0xB4AF: +case 0xB6AF: +case 0xB8AF: +case 0xBAAF: +case 0xBCAF: +case 0xBEAF: + +// CMP +case 0xB0A8: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, src) + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + POST_IO +} +RET(20) +case 0xB2B0: +case 0xB4B0: +case 0xB6B0: +case 0xB8B0: +case 0xBAB0: +case 0xBCB0: +case 0xBEB0: +case 0xB0B1: +case 0xB2B1: +case 0xB4B1: +case 0xB6B1: +case 0xB8B1: +case 0xBAB1: +case 0xBCB1: +case 0xBEB1: +case 0xB0B2: +case 0xB2B2: +case 0xB4B2: +case 0xB6B2: +case 0xB8B2: +case 0xBAB2: +case 0xBCB2: +case 0xBEB2: +case 0xB0B3: +case 0xB2B3: +case 0xB4B3: +case 0xB6B3: +case 0xB8B3: +case 0xBAB3: +case 0xBCB3: +case 0xBEB3: +case 0xB0B4: +case 0xB2B4: +case 0xB4B4: +case 0xB6B4: +case 0xB8B4: +case 0xBAB4: +case 0xBCB4: +case 0xBEB4: +case 0xB0B5: +case 0xB2B5: +case 0xB4B5: +case 0xB6B5: +case 0xB8B5: +case 0xBAB5: +case 0xBCB5: +case 0xBEB5: +case 0xB0B6: +case 0xB2B6: +case 0xB4B6: +case 0xB6B6: +case 0xB8B6: +case 0xBAB6: +case 0xBCB6: +case 0xBEB6: +case 0xB0B7: +case 0xB2B7: +case 0xB4B7: +case 0xB6B7: +case 0xB8B7: +case 0xBAB7: +case 0xBCB7: +case 0xBEB7: + +// CMP +case 0xB0B0: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_LONG_F(adr, src) + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + POST_IO +} +RET(22) +case 0xB2B8: +case 0xB4B8: +case 0xB6B8: +case 0xB8B8: +case 0xBAB8: +case 0xBCB8: +case 0xBEB8: + +// CMP +case 0xB0B8: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, src) + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + POST_IO +} +RET(20) +case 0xB2B9: +case 0xB4B9: +case 0xB6B9: +case 0xB8B9: +case 0xBAB9: +case 0xBCB9: +case 0xBEB9: + +// CMP +case 0xB0B9: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_LONG_F(adr, src) + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + POST_IO +} +RET(24) +case 0xB2BA: +case 0xB4BA: +case 0xB6BA: +case 0xB8BA: +case 0xBABA: +case 0xBCBA: +case 0xBEBA: + +// CMP +case 0xB0BA: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, src) + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + POST_IO +} +RET(20) +case 0xB2BB: +case 0xB4BB: +case 0xB6BB: +case 0xB8BB: +case 0xBABB: +case 0xBCBB: +case 0xBEBB: + +// CMP +case 0xB0BB: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READ_LONG_F(adr, src) + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + POST_IO +} +RET(22) +case 0xB2BC: +case 0xB4BC: +case 0xB6BC: +case 0xB8BC: +case 0xBABC: +case 0xBCBC: +case 0xBEBC: + +// CMP +case 0xB0BC: +{ + u32 res; + pointer dst; + pointer src; + src = FETCH_LONG; + PC += 4; + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; +} +RET(14) +case 0xB29F: +case 0xB49F: +case 0xB69F: +case 0xB89F: +case 0xBA9F: +case 0xBC9F: +case 0xBE9F: + +// CMP +case 0xB09F: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[7]; + CPU->A[7] += 4; + PRE_IO + READ_LONG_F(adr, src) + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + POST_IO +} +RET(16) +case 0xB2A7: +case 0xB4A7: +case 0xB6A7: +case 0xB8A7: +case 0xBAA7: +case 0xBCA7: +case 0xBEA7: + +// CMP +case 0xB0A7: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + PRE_IO + READ_LONG_F(adr, src) + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + POST_IO +} +RET(18) +case 0xB308: +case 0xB508: +case 0xB708: +case 0xB908: +case 0xBB08: +case 0xBD08: +case 0xB109: +case 0xB309: +case 0xB509: +case 0xB709: +case 0xB909: +case 0xBB09: +case 0xBD09: +case 0xB10A: +case 0xB30A: +case 0xB50A: +case 0xB70A: +case 0xB90A: +case 0xBB0A: +case 0xBD0A: +case 0xB10B: +case 0xB30B: +case 0xB50B: +case 0xB70B: +case 0xB90B: +case 0xBB0B: +case 0xBD0B: +case 0xB10C: +case 0xB30C: +case 0xB50C: +case 0xB70C: +case 0xB90C: +case 0xBB0C: +case 0xBD0C: +case 0xB10D: +case 0xB30D: +case 0xB50D: +case 0xB70D: +case 0xB90D: +case 0xBB0D: +case 0xBD0D: +case 0xB10E: +case 0xB30E: +case 0xB50E: +case 0xB70E: +case 0xB90E: +case 0xBB0E: +case 0xBD0E: + +// CMPM +case 0xB108: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + PRE_IO + READ_BYTE_F(adr, src) + adr = CPU->A[(Opcode >> 9) & 7]; + CPU->A[(Opcode >> 9) & 7] += 1; + READ_BYTE_F(adr, dst) + res = dst - src; + CPU->flag_N = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + POST_IO +} +RET(12) +case 0xB348: +case 0xB548: +case 0xB748: +case 0xB948: +case 0xBB48: +case 0xBD48: +case 0xB149: +case 0xB349: +case 0xB549: +case 0xB749: +case 0xB949: +case 0xBB49: +case 0xBD49: +case 0xB14A: +case 0xB34A: +case 0xB54A: +case 0xB74A: +case 0xB94A: +case 0xBB4A: +case 0xBD4A: +case 0xB14B: +case 0xB34B: +case 0xB54B: +case 0xB74B: +case 0xB94B: +case 0xBB4B: +case 0xBD4B: +case 0xB14C: +case 0xB34C: +case 0xB54C: +case 0xB74C: +case 0xB94C: +case 0xBB4C: +case 0xBD4C: +case 0xB14D: +case 0xB34D: +case 0xB54D: +case 0xB74D: +case 0xB94D: +case 0xBB4D: +case 0xBD4D: +case 0xB14E: +case 0xB34E: +case 0xB54E: +case 0xB74E: +case 0xB94E: +case 0xBB4E: +case 0xBD4E: + +// CMPM +case 0xB148: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 2; + PRE_IO + READ_WORD_F(adr, src) + adr = CPU->A[(Opcode >> 9) & 7]; + CPU->A[(Opcode >> 9) & 7] += 2; + READ_WORD_F(adr, dst) + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + POST_IO +} +RET(12) +case 0xB388: +case 0xB588: +case 0xB788: +case 0xB988: +case 0xBB88: +case 0xBD88: +case 0xB189: +case 0xB389: +case 0xB589: +case 0xB789: +case 0xB989: +case 0xBB89: +case 0xBD89: +case 0xB18A: +case 0xB38A: +case 0xB58A: +case 0xB78A: +case 0xB98A: +case 0xBB8A: +case 0xBD8A: +case 0xB18B: +case 0xB38B: +case 0xB58B: +case 0xB78B: +case 0xB98B: +case 0xBB8B: +case 0xBD8B: +case 0xB18C: +case 0xB38C: +case 0xB58C: +case 0xB78C: +case 0xB98C: +case 0xBB8C: +case 0xBD8C: +case 0xB18D: +case 0xB38D: +case 0xB58D: +case 0xB78D: +case 0xB98D: +case 0xBB8D: +case 0xBD8D: +case 0xB18E: +case 0xB38E: +case 0xB58E: +case 0xB78E: +case 0xB98E: +case 0xBB8E: +case 0xBD8E: + +// CMPM +case 0xB188: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 4; + PRE_IO + READ_LONG_F(adr, src) + adr = CPU->A[(Opcode >> 9) & 7]; + CPU->A[(Opcode >> 9) & 7] += 4; + READ_LONG_F(adr, dst) + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + POST_IO +} +RET(20) +case 0xB30F: +case 0xB50F: +case 0xB70F: +case 0xB90F: +case 0xBB0F: +case 0xBD0F: + +// CMP7M +case 0xB10F: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_BYTE_F(adr, src) + adr = CPU->A[(Opcode >> 9) & 7]; + CPU->A[(Opcode >> 9) & 7] += 1; + READ_BYTE_F(adr, dst) + res = dst - src; + CPU->flag_N = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + POST_IO +} +RET(12) +case 0xB34F: +case 0xB54F: +case 0xB74F: +case 0xB94F: +case 0xBB4F: +case 0xBD4F: + +// CMP7M +case 0xB14F: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_WORD_F(adr, src) + adr = CPU->A[(Opcode >> 9) & 7]; + CPU->A[(Opcode >> 9) & 7] += 2; + READ_WORD_F(adr, dst) + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + POST_IO +} +RET(12) +case 0xB38F: +case 0xB58F: +case 0xB78F: +case 0xB98F: +case 0xBB8F: +case 0xBD8F: + +// CMP7M +case 0xB18F: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[7]; + CPU->A[7] += 4; + PRE_IO + READ_LONG_F(adr, src) + adr = CPU->A[(Opcode >> 9) & 7]; + CPU->A[(Opcode >> 9) & 7] += 4; + READ_LONG_F(adr, dst) + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + POST_IO +} +RET(20) +case 0xBF09: +case 0xBF0A: +case 0xBF0B: +case 0xBF0C: +case 0xBF0D: +case 0xBF0E: + +// CMPM7 +case 0xBF08: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + PRE_IO + READ_BYTE_F(adr, src) + adr = CPU->A[7]; + CPU->A[7] += 2; + READ_BYTE_F(adr, dst) + res = dst - src; + CPU->flag_N = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + POST_IO +} +RET(12) +case 0xBF49: +case 0xBF4A: +case 0xBF4B: +case 0xBF4C: +case 0xBF4D: +case 0xBF4E: + +// CMPM7 +case 0xBF48: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 2; + PRE_IO + READ_WORD_F(adr, src) + adr = CPU->A[7]; + CPU->A[7] += 2; + READ_WORD_F(adr, dst) + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + POST_IO +} +RET(12) +case 0xBF89: +case 0xBF8A: +case 0xBF8B: +case 0xBF8C: +case 0xBF8D: +case 0xBF8E: + +// CMPM7 +case 0xBF88: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 4; + PRE_IO + READ_LONG_F(adr, src) + adr = CPU->A[7]; + CPU->A[7] += 4; + READ_LONG_F(adr, dst) + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + POST_IO +} +RET(20) + +// CMP7M7 +case 0xBF0F: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_BYTE_F(adr, src) + adr = CPU->A[7]; + CPU->A[7] += 2; + READ_BYTE_F(adr, dst) + res = dst - src; + CPU->flag_N = CPU->flag_C = res; + CPU->flag_V = (src ^ dst) & (res ^ dst); + CPU->flag_notZ = res & 0xFF; + POST_IO +} +RET(12) + +// CMP7M7 +case 0xBF4F: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_WORD_F(adr, src) + adr = CPU->A[7]; + CPU->A[7] += 2; + READ_WORD_F(adr, dst) + res = dst - src; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8; + CPU->flag_N = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + POST_IO +} +RET(12) + +// CMP7M7 +case 0xBF8F: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[7]; + CPU->A[7] += 4; + PRE_IO + READ_LONG_F(adr, src) + adr = CPU->A[7]; + CPU->A[7] += 4; + READ_LONG_F(adr, dst) + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + POST_IO +} +RET(20) +case 0xB300: +case 0xB500: +case 0xB700: +case 0xB900: +case 0xBB00: +case 0xBD00: +case 0xBF00: +case 0xB101: +case 0xB301: +case 0xB501: +case 0xB701: +case 0xB901: +case 0xBB01: +case 0xBD01: +case 0xBF01: +case 0xB102: +case 0xB302: +case 0xB502: +case 0xB702: +case 0xB902: +case 0xBB02: +case 0xBD02: +case 0xBF02: +case 0xB103: +case 0xB303: +case 0xB503: +case 0xB703: +case 0xB903: +case 0xBB03: +case 0xBD03: +case 0xBF03: +case 0xB104: +case 0xB304: +case 0xB504: +case 0xB704: +case 0xB904: +case 0xBB04: +case 0xBD04: +case 0xBF04: +case 0xB105: +case 0xB305: +case 0xB505: +case 0xB705: +case 0xB905: +case 0xBB05: +case 0xBD05: +case 0xBF05: +case 0xB106: +case 0xB306: +case 0xB506: +case 0xB706: +case 0xB906: +case 0xBB06: +case 0xBD06: +case 0xBF06: +case 0xB107: +case 0xB307: +case 0xB507: +case 0xB707: +case 0xB907: +case 0xBB07: +case 0xBD07: +case 0xBF07: + +// EORDa +case 0xB100: +{ + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + res = (u8)CPU->D[(Opcode >> 0) & 7]; + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(4) +case 0xB310: +case 0xB510: +case 0xB710: +case 0xB910: +case 0xBB10: +case 0xBD10: +case 0xBF10: +case 0xB111: +case 0xB311: +case 0xB511: +case 0xB711: +case 0xB911: +case 0xBB11: +case 0xBD11: +case 0xBF11: +case 0xB112: +case 0xB312: +case 0xB512: +case 0xB712: +case 0xB912: +case 0xBB12: +case 0xBD12: +case 0xBF12: +case 0xB113: +case 0xB313: +case 0xB513: +case 0xB713: +case 0xB913: +case 0xBB13: +case 0xBD13: +case 0xBF13: +case 0xB114: +case 0xB314: +case 0xB514: +case 0xB714: +case 0xB914: +case 0xBB14: +case 0xBD14: +case 0xBF14: +case 0xB115: +case 0xB315: +case 0xB515: +case 0xB715: +case 0xB915: +case 0xBB15: +case 0xBD15: +case 0xBF15: +case 0xB116: +case 0xB316: +case 0xB516: +case 0xB716: +case 0xB916: +case 0xBB16: +case 0xBD16: +case 0xBF16: +case 0xB117: +case 0xB317: +case 0xB517: +case 0xB717: +case 0xB917: +case 0xBB17: +case 0xBD17: +case 0xBF17: + +// EORDa +case 0xB110: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_BYTE_F(adr, res) + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0xB318: +case 0xB518: +case 0xB718: +case 0xB918: +case 0xBB18: +case 0xBD18: +case 0xBF18: +case 0xB119: +case 0xB319: +case 0xB519: +case 0xB719: +case 0xB919: +case 0xBB19: +case 0xBD19: +case 0xBF19: +case 0xB11A: +case 0xB31A: +case 0xB51A: +case 0xB71A: +case 0xB91A: +case 0xBB1A: +case 0xBD1A: +case 0xBF1A: +case 0xB11B: +case 0xB31B: +case 0xB51B: +case 0xB71B: +case 0xB91B: +case 0xBB1B: +case 0xBD1B: +case 0xBF1B: +case 0xB11C: +case 0xB31C: +case 0xB51C: +case 0xB71C: +case 0xB91C: +case 0xBB1C: +case 0xBD1C: +case 0xBF1C: +case 0xB11D: +case 0xB31D: +case 0xB51D: +case 0xB71D: +case 0xB91D: +case 0xBB1D: +case 0xBD1D: +case 0xBF1D: +case 0xB11E: +case 0xB31E: +case 0xB51E: +case 0xB71E: +case 0xB91E: +case 0xBB1E: +case 0xBD1E: +case 0xBF1E: + +// EORDa +case 0xB118: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + PRE_IO + READ_BYTE_F(adr, res) + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0xB320: +case 0xB520: +case 0xB720: +case 0xB920: +case 0xBB20: +case 0xBD20: +case 0xBF20: +case 0xB121: +case 0xB321: +case 0xB521: +case 0xB721: +case 0xB921: +case 0xBB21: +case 0xBD21: +case 0xBF21: +case 0xB122: +case 0xB322: +case 0xB522: +case 0xB722: +case 0xB922: +case 0xBB22: +case 0xBD22: +case 0xBF22: +case 0xB123: +case 0xB323: +case 0xB523: +case 0xB723: +case 0xB923: +case 0xBB23: +case 0xBD23: +case 0xBF23: +case 0xB124: +case 0xB324: +case 0xB524: +case 0xB724: +case 0xB924: +case 0xBB24: +case 0xBD24: +case 0xBF24: +case 0xB125: +case 0xB325: +case 0xB525: +case 0xB725: +case 0xB925: +case 0xBB25: +case 0xBD25: +case 0xBF25: +case 0xB126: +case 0xB326: +case 0xB526: +case 0xB726: +case 0xB926: +case 0xBB26: +case 0xBD26: +case 0xBF26: + +// EORDa +case 0xB120: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_BYTE_F(adr, res) + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(14) +case 0xB328: +case 0xB528: +case 0xB728: +case 0xB928: +case 0xBB28: +case 0xBD28: +case 0xBF28: +case 0xB129: +case 0xB329: +case 0xB529: +case 0xB729: +case 0xB929: +case 0xBB29: +case 0xBD29: +case 0xBF29: +case 0xB12A: +case 0xB32A: +case 0xB52A: +case 0xB72A: +case 0xB92A: +case 0xBB2A: +case 0xBD2A: +case 0xBF2A: +case 0xB12B: +case 0xB32B: +case 0xB52B: +case 0xB72B: +case 0xB92B: +case 0xBB2B: +case 0xBD2B: +case 0xBF2B: +case 0xB12C: +case 0xB32C: +case 0xB52C: +case 0xB72C: +case 0xB92C: +case 0xBB2C: +case 0xBD2C: +case 0xBF2C: +case 0xB12D: +case 0xB32D: +case 0xB52D: +case 0xB72D: +case 0xB92D: +case 0xBB2D: +case 0xBD2D: +case 0xBF2D: +case 0xB12E: +case 0xB32E: +case 0xB52E: +case 0xB72E: +case 0xB92E: +case 0xBB2E: +case 0xBD2E: +case 0xBF2E: +case 0xB12F: +case 0xB32F: +case 0xB52F: +case 0xB72F: +case 0xB92F: +case 0xBB2F: +case 0xBD2F: +case 0xBF2F: + +// EORDa +case 0xB128: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0xB330: +case 0xB530: +case 0xB730: +case 0xB930: +case 0xBB30: +case 0xBD30: +case 0xBF30: +case 0xB131: +case 0xB331: +case 0xB531: +case 0xB731: +case 0xB931: +case 0xBB31: +case 0xBD31: +case 0xBF31: +case 0xB132: +case 0xB332: +case 0xB532: +case 0xB732: +case 0xB932: +case 0xBB32: +case 0xBD32: +case 0xBF32: +case 0xB133: +case 0xB333: +case 0xB533: +case 0xB733: +case 0xB933: +case 0xBB33: +case 0xBD33: +case 0xBF33: +case 0xB134: +case 0xB334: +case 0xB534: +case 0xB734: +case 0xB934: +case 0xBB34: +case 0xBD34: +case 0xBF34: +case 0xB135: +case 0xB335: +case 0xB535: +case 0xB735: +case 0xB935: +case 0xBB35: +case 0xBD35: +case 0xBF35: +case 0xB136: +case 0xB336: +case 0xB536: +case 0xB736: +case 0xB936: +case 0xBB36: +case 0xBD36: +case 0xBF36: +case 0xB137: +case 0xB337: +case 0xB537: +case 0xB737: +case 0xB937: +case 0xBB37: +case 0xBD37: +case 0xBF37: + +// EORDa +case 0xB130: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, res) + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) +case 0xB338: +case 0xB538: +case 0xB738: +case 0xB938: +case 0xBB38: +case 0xBD38: +case 0xBF38: + +// EORDa +case 0xB138: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0xB339: +case 0xB539: +case 0xB739: +case 0xB939: +case 0xBB39: +case 0xBD39: +case 0xBF39: + +// EORDa +case 0xB139: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_BYTE_F(adr, res) + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(20) +case 0xB31F: +case 0xB51F: +case 0xB71F: +case 0xB91F: +case 0xBB1F: +case 0xBD1F: +case 0xBF1F: + +// EORDa +case 0xB11F: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_BYTE_F(adr, res) + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0xB327: +case 0xB527: +case 0xB727: +case 0xB927: +case 0xBB27: +case 0xBD27: +case 0xBF27: + +// EORDa +case 0xB127: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_BYTE_F(adr, res) + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(14) +case 0xB340: +case 0xB540: +case 0xB740: +case 0xB940: +case 0xBB40: +case 0xBD40: +case 0xBF40: +case 0xB141: +case 0xB341: +case 0xB541: +case 0xB741: +case 0xB941: +case 0xBB41: +case 0xBD41: +case 0xBF41: +case 0xB142: +case 0xB342: +case 0xB542: +case 0xB742: +case 0xB942: +case 0xBB42: +case 0xBD42: +case 0xBF42: +case 0xB143: +case 0xB343: +case 0xB543: +case 0xB743: +case 0xB943: +case 0xBB43: +case 0xBD43: +case 0xBF43: +case 0xB144: +case 0xB344: +case 0xB544: +case 0xB744: +case 0xB944: +case 0xBB44: +case 0xBD44: +case 0xBF44: +case 0xB145: +case 0xB345: +case 0xB545: +case 0xB745: +case 0xB945: +case 0xBB45: +case 0xBD45: +case 0xBF45: +case 0xB146: +case 0xB346: +case 0xB546: +case 0xB746: +case 0xB946: +case 0xBB46: +case 0xBD46: +case 0xBF46: +case 0xB147: +case 0xB347: +case 0xB547: +case 0xB747: +case 0xB947: +case 0xBB47: +case 0xBD47: +case 0xBF47: + +// EORDa +case 0xB140: +{ + u32 res; + pointer src; + src = (u16)CPU->D[(Opcode >> 9) & 7]; + res = (u16)CPU->D[(Opcode >> 0) & 7]; + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(4) +case 0xB350: +case 0xB550: +case 0xB750: +case 0xB950: +case 0xBB50: +case 0xBD50: +case 0xBF50: +case 0xB151: +case 0xB351: +case 0xB551: +case 0xB751: +case 0xB951: +case 0xBB51: +case 0xBD51: +case 0xBF51: +case 0xB152: +case 0xB352: +case 0xB552: +case 0xB752: +case 0xB952: +case 0xBB52: +case 0xBD52: +case 0xBF52: +case 0xB153: +case 0xB353: +case 0xB553: +case 0xB753: +case 0xB953: +case 0xBB53: +case 0xBD53: +case 0xBF53: +case 0xB154: +case 0xB354: +case 0xB554: +case 0xB754: +case 0xB954: +case 0xBB54: +case 0xBD54: +case 0xBF54: +case 0xB155: +case 0xB355: +case 0xB555: +case 0xB755: +case 0xB955: +case 0xBB55: +case 0xBD55: +case 0xBF55: +case 0xB156: +case 0xB356: +case 0xB556: +case 0xB756: +case 0xB956: +case 0xBB56: +case 0xBD56: +case 0xBF56: +case 0xB157: +case 0xB357: +case 0xB557: +case 0xB757: +case 0xB957: +case 0xBB57: +case 0xBD57: +case 0xBF57: + +// EORDa +case 0xB150: +{ + u32 adr; + u32 res; + pointer src; + src = (u16)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_WORD_F(adr, res) + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0xB358: +case 0xB558: +case 0xB758: +case 0xB958: +case 0xBB58: +case 0xBD58: +case 0xBF58: +case 0xB159: +case 0xB359: +case 0xB559: +case 0xB759: +case 0xB959: +case 0xBB59: +case 0xBD59: +case 0xBF59: +case 0xB15A: +case 0xB35A: +case 0xB55A: +case 0xB75A: +case 0xB95A: +case 0xBB5A: +case 0xBD5A: +case 0xBF5A: +case 0xB15B: +case 0xB35B: +case 0xB55B: +case 0xB75B: +case 0xB95B: +case 0xBB5B: +case 0xBD5B: +case 0xBF5B: +case 0xB15C: +case 0xB35C: +case 0xB55C: +case 0xB75C: +case 0xB95C: +case 0xBB5C: +case 0xBD5C: +case 0xBF5C: +case 0xB15D: +case 0xB35D: +case 0xB55D: +case 0xB75D: +case 0xB95D: +case 0xBB5D: +case 0xBD5D: +case 0xBF5D: +case 0xB15E: +case 0xB35E: +case 0xB55E: +case 0xB75E: +case 0xB95E: +case 0xBB5E: +case 0xBD5E: +case 0xBF5E: + +// EORDa +case 0xB158: +{ + u32 adr; + u32 res; + pointer src; + src = (u16)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 2; + PRE_IO + READ_WORD_F(adr, res) + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0xB360: +case 0xB560: +case 0xB760: +case 0xB960: +case 0xBB60: +case 0xBD60: +case 0xBF60: +case 0xB161: +case 0xB361: +case 0xB561: +case 0xB761: +case 0xB961: +case 0xBB61: +case 0xBD61: +case 0xBF61: +case 0xB162: +case 0xB362: +case 0xB562: +case 0xB762: +case 0xB962: +case 0xBB62: +case 0xBD62: +case 0xBF62: +case 0xB163: +case 0xB363: +case 0xB563: +case 0xB763: +case 0xB963: +case 0xBB63: +case 0xBD63: +case 0xBF63: +case 0xB164: +case 0xB364: +case 0xB564: +case 0xB764: +case 0xB964: +case 0xBB64: +case 0xBD64: +case 0xBF64: +case 0xB165: +case 0xB365: +case 0xB565: +case 0xB765: +case 0xB965: +case 0xBB65: +case 0xBD65: +case 0xBF65: +case 0xB166: +case 0xB366: +case 0xB566: +case 0xB766: +case 0xB966: +case 0xBB66: +case 0xBD66: +case 0xBF66: + +// EORDa +case 0xB160: +{ + u32 adr; + u32 res; + pointer src; + src = (u16)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7] - 2; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_WORD_F(adr, res) + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(14) +case 0xB368: +case 0xB568: +case 0xB768: +case 0xB968: +case 0xBB68: +case 0xBD68: +case 0xBF68: +case 0xB169: +case 0xB369: +case 0xB569: +case 0xB769: +case 0xB969: +case 0xBB69: +case 0xBD69: +case 0xBF69: +case 0xB16A: +case 0xB36A: +case 0xB56A: +case 0xB76A: +case 0xB96A: +case 0xBB6A: +case 0xBD6A: +case 0xBF6A: +case 0xB16B: +case 0xB36B: +case 0xB56B: +case 0xB76B: +case 0xB96B: +case 0xBB6B: +case 0xBD6B: +case 0xBF6B: +case 0xB16C: +case 0xB36C: +case 0xB56C: +case 0xB76C: +case 0xB96C: +case 0xBB6C: +case 0xBD6C: +case 0xBF6C: +case 0xB16D: +case 0xB36D: +case 0xB56D: +case 0xB76D: +case 0xB96D: +case 0xBB6D: +case 0xBD6D: +case 0xBF6D: +case 0xB16E: +case 0xB36E: +case 0xB56E: +case 0xB76E: +case 0xB96E: +case 0xBB6E: +case 0xBD6E: +case 0xBF6E: +case 0xB16F: +case 0xB36F: +case 0xB56F: +case 0xB76F: +case 0xB96F: +case 0xBB6F: +case 0xBD6F: +case 0xBF6F: + +// EORDa +case 0xB168: +{ + u32 adr; + u32 res; + pointer src; + src = (u16)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, res) + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0xB370: +case 0xB570: +case 0xB770: +case 0xB970: +case 0xBB70: +case 0xBD70: +case 0xBF70: +case 0xB171: +case 0xB371: +case 0xB571: +case 0xB771: +case 0xB971: +case 0xBB71: +case 0xBD71: +case 0xBF71: +case 0xB172: +case 0xB372: +case 0xB572: +case 0xB772: +case 0xB972: +case 0xBB72: +case 0xBD72: +case 0xBF72: +case 0xB173: +case 0xB373: +case 0xB573: +case 0xB773: +case 0xB973: +case 0xBB73: +case 0xBD73: +case 0xBF73: +case 0xB174: +case 0xB374: +case 0xB574: +case 0xB774: +case 0xB974: +case 0xBB74: +case 0xBD74: +case 0xBF74: +case 0xB175: +case 0xB375: +case 0xB575: +case 0xB775: +case 0xB975: +case 0xBB75: +case 0xBD75: +case 0xBF75: +case 0xB176: +case 0xB376: +case 0xB576: +case 0xB776: +case 0xB976: +case 0xBB76: +case 0xBD76: +case 0xBF76: +case 0xB177: +case 0xB377: +case 0xB577: +case 0xB777: +case 0xB977: +case 0xBB77: +case 0xBD77: +case 0xBF77: + +// EORDa +case 0xB170: +{ + u32 adr; + u32 res; + pointer src; + src = (u16)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, res) + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(18) +case 0xB378: +case 0xB578: +case 0xB778: +case 0xB978: +case 0xBB78: +case 0xBD78: +case 0xBF78: + +// EORDa +case 0xB178: +{ + u32 adr; + u32 res; + pointer src; + src = (u16)CPU->D[(Opcode >> 9) & 7]; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, res) + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0xB379: +case 0xB579: +case 0xB779: +case 0xB979: +case 0xBB79: +case 0xBD79: +case 0xBF79: + +// EORDa +case 0xB179: +{ + u32 adr; + u32 res; + pointer src; + src = (u16)CPU->D[(Opcode >> 9) & 7]; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_WORD_F(adr, res) + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(20) +case 0xB35F: +case 0xB55F: +case 0xB75F: +case 0xB95F: +case 0xBB5F: +case 0xBD5F: +case 0xBF5F: + +// EORDa +case 0xB15F: +{ + u32 adr; + u32 res; + pointer src; + src = (u16)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_WORD_F(adr, res) + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0xB367: +case 0xB567: +case 0xB767: +case 0xB967: +case 0xBB67: +case 0xBD67: +case 0xBF67: + +// EORDa +case 0xB167: +{ + u32 adr; + u32 res; + pointer src; + src = (u16)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_WORD_F(adr, res) + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(14) +case 0xB380: +case 0xB580: +case 0xB780: +case 0xB980: +case 0xBB80: +case 0xBD80: +case 0xBF80: +case 0xB181: +case 0xB381: +case 0xB581: +case 0xB781: +case 0xB981: +case 0xBB81: +case 0xBD81: +case 0xBF81: +case 0xB182: +case 0xB382: +case 0xB582: +case 0xB782: +case 0xB982: +case 0xBB82: +case 0xBD82: +case 0xBF82: +case 0xB183: +case 0xB383: +case 0xB583: +case 0xB783: +case 0xB983: +case 0xBB83: +case 0xBD83: +case 0xBF83: +case 0xB184: +case 0xB384: +case 0xB584: +case 0xB784: +case 0xB984: +case 0xBB84: +case 0xBD84: +case 0xBF84: +case 0xB185: +case 0xB385: +case 0xB585: +case 0xB785: +case 0xB985: +case 0xBB85: +case 0xBD85: +case 0xBF85: +case 0xB186: +case 0xB386: +case 0xB586: +case 0xB786: +case 0xB986: +case 0xBB86: +case 0xBD86: +case 0xBF86: +case 0xB187: +case 0xB387: +case 0xB587: +case 0xB787: +case 0xB987: +case 0xBB87: +case 0xBD87: +case 0xBF87: + +// EORDa +case 0xB180: +{ + u32 res; + pointer src; + src = (u32)CPU->D[(Opcode >> 9) & 7]; + res = (u32)CPU->D[(Opcode >> 0) & 7]; + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(8) +case 0xB390: +case 0xB590: +case 0xB790: +case 0xB990: +case 0xBB90: +case 0xBD90: +case 0xBF90: +case 0xB191: +case 0xB391: +case 0xB591: +case 0xB791: +case 0xB991: +case 0xBB91: +case 0xBD91: +case 0xBF91: +case 0xB192: +case 0xB392: +case 0xB592: +case 0xB792: +case 0xB992: +case 0xBB92: +case 0xBD92: +case 0xBF92: +case 0xB193: +case 0xB393: +case 0xB593: +case 0xB793: +case 0xB993: +case 0xBB93: +case 0xBD93: +case 0xBF93: +case 0xB194: +case 0xB394: +case 0xB594: +case 0xB794: +case 0xB994: +case 0xBB94: +case 0xBD94: +case 0xBF94: +case 0xB195: +case 0xB395: +case 0xB595: +case 0xB795: +case 0xB995: +case 0xBB95: +case 0xBD95: +case 0xBF95: +case 0xB196: +case 0xB396: +case 0xB596: +case 0xB796: +case 0xB996: +case 0xBB96: +case 0xBD96: +case 0xBF96: +case 0xB197: +case 0xB397: +case 0xB597: +case 0xB797: +case 0xB997: +case 0xBB97: +case 0xBD97: +case 0xBF97: + +// EORDa +case 0xB190: +{ + u32 adr; + u32 res; + pointer src; + src = (u32)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_LONG_F(adr, res) + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(20) +case 0xB398: +case 0xB598: +case 0xB798: +case 0xB998: +case 0xBB98: +case 0xBD98: +case 0xBF98: +case 0xB199: +case 0xB399: +case 0xB599: +case 0xB799: +case 0xB999: +case 0xBB99: +case 0xBD99: +case 0xBF99: +case 0xB19A: +case 0xB39A: +case 0xB59A: +case 0xB79A: +case 0xB99A: +case 0xBB9A: +case 0xBD9A: +case 0xBF9A: +case 0xB19B: +case 0xB39B: +case 0xB59B: +case 0xB79B: +case 0xB99B: +case 0xBB9B: +case 0xBD9B: +case 0xBF9B: +case 0xB19C: +case 0xB39C: +case 0xB59C: +case 0xB79C: +case 0xB99C: +case 0xBB9C: +case 0xBD9C: +case 0xBF9C: +case 0xB19D: +case 0xB39D: +case 0xB59D: +case 0xB79D: +case 0xB99D: +case 0xBB9D: +case 0xBD9D: +case 0xBF9D: +case 0xB19E: +case 0xB39E: +case 0xB59E: +case 0xB79E: +case 0xB99E: +case 0xBB9E: +case 0xBD9E: +case 0xBF9E: + +// EORDa +case 0xB198: +{ + u32 adr; + u32 res; + pointer src; + src = (u32)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 4; + PRE_IO + READ_LONG_F(adr, res) + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(20) +case 0xB3A0: +case 0xB5A0: +case 0xB7A0: +case 0xB9A0: +case 0xBBA0: +case 0xBDA0: +case 0xBFA0: +case 0xB1A1: +case 0xB3A1: +case 0xB5A1: +case 0xB7A1: +case 0xB9A1: +case 0xBBA1: +case 0xBDA1: +case 0xBFA1: +case 0xB1A2: +case 0xB3A2: +case 0xB5A2: +case 0xB7A2: +case 0xB9A2: +case 0xBBA2: +case 0xBDA2: +case 0xBFA2: +case 0xB1A3: +case 0xB3A3: +case 0xB5A3: +case 0xB7A3: +case 0xB9A3: +case 0xBBA3: +case 0xBDA3: +case 0xBFA3: +case 0xB1A4: +case 0xB3A4: +case 0xB5A4: +case 0xB7A4: +case 0xB9A4: +case 0xBBA4: +case 0xBDA4: +case 0xBFA4: +case 0xB1A5: +case 0xB3A5: +case 0xB5A5: +case 0xB7A5: +case 0xB9A5: +case 0xBBA5: +case 0xBDA5: +case 0xBFA5: +case 0xB1A6: +case 0xB3A6: +case 0xB5A6: +case 0xB7A6: +case 0xB9A6: +case 0xBBA6: +case 0xBDA6: +case 0xBFA6: + +// EORDa +case 0xB1A0: +{ + u32 adr; + u32 res; + pointer src; + src = (u32)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7] - 4; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_LONG_F(adr, res) + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(22) +case 0xB3A8: +case 0xB5A8: +case 0xB7A8: +case 0xB9A8: +case 0xBBA8: +case 0xBDA8: +case 0xBFA8: +case 0xB1A9: +case 0xB3A9: +case 0xB5A9: +case 0xB7A9: +case 0xB9A9: +case 0xBBA9: +case 0xBDA9: +case 0xBFA9: +case 0xB1AA: +case 0xB3AA: +case 0xB5AA: +case 0xB7AA: +case 0xB9AA: +case 0xBBAA: +case 0xBDAA: +case 0xBFAA: +case 0xB1AB: +case 0xB3AB: +case 0xB5AB: +case 0xB7AB: +case 0xB9AB: +case 0xBBAB: +case 0xBDAB: +case 0xBFAB: +case 0xB1AC: +case 0xB3AC: +case 0xB5AC: +case 0xB7AC: +case 0xB9AC: +case 0xBBAC: +case 0xBDAC: +case 0xBFAC: +case 0xB1AD: +case 0xB3AD: +case 0xB5AD: +case 0xB7AD: +case 0xB9AD: +case 0xBBAD: +case 0xBDAD: +case 0xBFAD: +case 0xB1AE: +case 0xB3AE: +case 0xB5AE: +case 0xB7AE: +case 0xB9AE: +case 0xBBAE: +case 0xBDAE: +case 0xBFAE: +case 0xB1AF: +case 0xB3AF: +case 0xB5AF: +case 0xB7AF: +case 0xB9AF: +case 0xBBAF: +case 0xBDAF: +case 0xBFAF: + +// EORDa +case 0xB1A8: +{ + u32 adr; + u32 res; + pointer src; + src = (u32)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, res) + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(24) +case 0xB3B0: +case 0xB5B0: +case 0xB7B0: +case 0xB9B0: +case 0xBBB0: +case 0xBDB0: +case 0xBFB0: +case 0xB1B1: +case 0xB3B1: +case 0xB5B1: +case 0xB7B1: +case 0xB9B1: +case 0xBBB1: +case 0xBDB1: +case 0xBFB1: +case 0xB1B2: +case 0xB3B2: +case 0xB5B2: +case 0xB7B2: +case 0xB9B2: +case 0xBBB2: +case 0xBDB2: +case 0xBFB2: +case 0xB1B3: +case 0xB3B3: +case 0xB5B3: +case 0xB7B3: +case 0xB9B3: +case 0xBBB3: +case 0xBDB3: +case 0xBFB3: +case 0xB1B4: +case 0xB3B4: +case 0xB5B4: +case 0xB7B4: +case 0xB9B4: +case 0xBBB4: +case 0xBDB4: +case 0xBFB4: +case 0xB1B5: +case 0xB3B5: +case 0xB5B5: +case 0xB7B5: +case 0xB9B5: +case 0xBBB5: +case 0xBDB5: +case 0xBFB5: +case 0xB1B6: +case 0xB3B6: +case 0xB5B6: +case 0xB7B6: +case 0xB9B6: +case 0xBBB6: +case 0xBDB6: +case 0xBFB6: +case 0xB1B7: +case 0xB3B7: +case 0xB5B7: +case 0xB7B7: +case 0xB9B7: +case 0xBBB7: +case 0xBDB7: +case 0xBFB7: + +// EORDa +case 0xB1B0: +{ + u32 adr; + u32 res; + pointer src; + src = (u32)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_LONG_F(adr, res) + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(26) +case 0xB3B8: +case 0xB5B8: +case 0xB7B8: +case 0xB9B8: +case 0xBBB8: +case 0xBDB8: +case 0xBFB8: + +// EORDa +case 0xB1B8: +{ + u32 adr; + u32 res; + pointer src; + src = (u32)CPU->D[(Opcode >> 9) & 7]; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, res) + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(24) +case 0xB3B9: +case 0xB5B9: +case 0xB7B9: +case 0xB9B9: +case 0xBBB9: +case 0xBDB9: +case 0xBFB9: + +// EORDa +case 0xB1B9: +{ + u32 adr; + u32 res; + pointer src; + src = (u32)CPU->D[(Opcode >> 9) & 7]; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_LONG_F(adr, res) + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(28) +case 0xB39F: +case 0xB59F: +case 0xB79F: +case 0xB99F: +case 0xBB9F: +case 0xBD9F: +case 0xBF9F: + +// EORDa +case 0xB19F: +{ + u32 adr; + u32 res; + pointer src; + src = (u32)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[7]; + CPU->A[7] += 4; + PRE_IO + READ_LONG_F(adr, res) + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(20) +case 0xB3A7: +case 0xB5A7: +case 0xB7A7: +case 0xB9A7: +case 0xBBA7: +case 0xBDA7: +case 0xBFA7: + +// EORDa +case 0xB1A7: +{ + u32 adr; + u32 res; + pointer src; + src = (u32)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + PRE_IO + READ_LONG_F(adr, res) + res ^= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(22) +case 0xB2C0: +case 0xB4C0: +case 0xB6C0: +case 0xB8C0: +case 0xBAC0: +case 0xBCC0: +case 0xBEC0: +case 0xB0C1: +case 0xB2C1: +case 0xB4C1: +case 0xB6C1: +case 0xB8C1: +case 0xBAC1: +case 0xBCC1: +case 0xBEC1: +case 0xB0C2: +case 0xB2C2: +case 0xB4C2: +case 0xB6C2: +case 0xB8C2: +case 0xBAC2: +case 0xBCC2: +case 0xBEC2: +case 0xB0C3: +case 0xB2C3: +case 0xB4C3: +case 0xB6C3: +case 0xB8C3: +case 0xBAC3: +case 0xBCC3: +case 0xBEC3: +case 0xB0C4: +case 0xB2C4: +case 0xB4C4: +case 0xB6C4: +case 0xB8C4: +case 0xBAC4: +case 0xBCC4: +case 0xBEC4: +case 0xB0C5: +case 0xB2C5: +case 0xB4C5: +case 0xB6C5: +case 0xB8C5: +case 0xBAC5: +case 0xBCC5: +case 0xBEC5: +case 0xB0C6: +case 0xB2C6: +case 0xB4C6: +case 0xB6C6: +case 0xB8C6: +case 0xBAC6: +case 0xBCC6: +case 0xBEC6: +case 0xB0C7: +case 0xB2C7: +case 0xB4C7: +case 0xB6C7: +case 0xB8C7: +case 0xBAC7: +case 0xBCC7: +case 0xBEC7: + +// CMPA +case 0xB0C0: +{ + u32 res; + pointer dst; + pointer src; + src = (s32)(s16)CPU->D[(Opcode >> 0) & 7]; + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; +} +RET(6) +case 0xB2C8: +case 0xB4C8: +case 0xB6C8: +case 0xB8C8: +case 0xBAC8: +case 0xBCC8: +case 0xBEC8: +case 0xB0C9: +case 0xB2C9: +case 0xB4C9: +case 0xB6C9: +case 0xB8C9: +case 0xBAC9: +case 0xBCC9: +case 0xBEC9: +case 0xB0CA: +case 0xB2CA: +case 0xB4CA: +case 0xB6CA: +case 0xB8CA: +case 0xBACA: +case 0xBCCA: +case 0xBECA: +case 0xB0CB: +case 0xB2CB: +case 0xB4CB: +case 0xB6CB: +case 0xB8CB: +case 0xBACB: +case 0xBCCB: +case 0xBECB: +case 0xB0CC: +case 0xB2CC: +case 0xB4CC: +case 0xB6CC: +case 0xB8CC: +case 0xBACC: +case 0xBCCC: +case 0xBECC: +case 0xB0CD: +case 0xB2CD: +case 0xB4CD: +case 0xB6CD: +case 0xB8CD: +case 0xBACD: +case 0xBCCD: +case 0xBECD: +case 0xB0CE: +case 0xB2CE: +case 0xB4CE: +case 0xB6CE: +case 0xB8CE: +case 0xBACE: +case 0xBCCE: +case 0xBECE: +case 0xB0CF: +case 0xB2CF: +case 0xB4CF: +case 0xB6CF: +case 0xB8CF: +case 0xBACF: +case 0xBCCF: +case 0xBECF: + +// CMPA +case 0xB0C8: +{ + u32 res; + pointer dst; + pointer src; + src = (s32)(s16)CPU->A[(Opcode >> 0) & 7]; + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; +} +RET(6) +case 0xB2D0: +case 0xB4D0: +case 0xB6D0: +case 0xB8D0: +case 0xBAD0: +case 0xBCD0: +case 0xBED0: +case 0xB0D1: +case 0xB2D1: +case 0xB4D1: +case 0xB6D1: +case 0xB8D1: +case 0xBAD1: +case 0xBCD1: +case 0xBED1: +case 0xB0D2: +case 0xB2D2: +case 0xB4D2: +case 0xB6D2: +case 0xB8D2: +case 0xBAD2: +case 0xBCD2: +case 0xBED2: +case 0xB0D3: +case 0xB2D3: +case 0xB4D3: +case 0xB6D3: +case 0xB8D3: +case 0xBAD3: +case 0xBCD3: +case 0xBED3: +case 0xB0D4: +case 0xB2D4: +case 0xB4D4: +case 0xB6D4: +case 0xB8D4: +case 0xBAD4: +case 0xBCD4: +case 0xBED4: +case 0xB0D5: +case 0xB2D5: +case 0xB4D5: +case 0xB6D5: +case 0xB8D5: +case 0xBAD5: +case 0xBCD5: +case 0xBED5: +case 0xB0D6: +case 0xB2D6: +case 0xB4D6: +case 0xB6D6: +case 0xB8D6: +case 0xBAD6: +case 0xBCD6: +case 0xBED6: +case 0xB0D7: +case 0xB2D7: +case 0xB4D7: +case 0xB6D7: +case 0xB8D7: +case 0xBAD7: +case 0xBCD7: +case 0xBED7: + +// CMPA +case 0xB0D0: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READSX_WORD_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + POST_IO +} +RET(10) +case 0xB2D8: +case 0xB4D8: +case 0xB6D8: +case 0xB8D8: +case 0xBAD8: +case 0xBCD8: +case 0xBED8: +case 0xB0D9: +case 0xB2D9: +case 0xB4D9: +case 0xB6D9: +case 0xB8D9: +case 0xBAD9: +case 0xBCD9: +case 0xBED9: +case 0xB0DA: +case 0xB2DA: +case 0xB4DA: +case 0xB6DA: +case 0xB8DA: +case 0xBADA: +case 0xBCDA: +case 0xBEDA: +case 0xB0DB: +case 0xB2DB: +case 0xB4DB: +case 0xB6DB: +case 0xB8DB: +case 0xBADB: +case 0xBCDB: +case 0xBEDB: +case 0xB0DC: +case 0xB2DC: +case 0xB4DC: +case 0xB6DC: +case 0xB8DC: +case 0xBADC: +case 0xBCDC: +case 0xBEDC: +case 0xB0DD: +case 0xB2DD: +case 0xB4DD: +case 0xB6DD: +case 0xB8DD: +case 0xBADD: +case 0xBCDD: +case 0xBEDD: +case 0xB0DE: +case 0xB2DE: +case 0xB4DE: +case 0xB6DE: +case 0xB8DE: +case 0xBADE: +case 0xBCDE: +case 0xBEDE: + +// CMPA +case 0xB0D8: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 2; + PRE_IO + READSX_WORD_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + POST_IO +} +RET(10) +case 0xB2E0: +case 0xB4E0: +case 0xB6E0: +case 0xB8E0: +case 0xBAE0: +case 0xBCE0: +case 0xBEE0: +case 0xB0E1: +case 0xB2E1: +case 0xB4E1: +case 0xB6E1: +case 0xB8E1: +case 0xBAE1: +case 0xBCE1: +case 0xBEE1: +case 0xB0E2: +case 0xB2E2: +case 0xB4E2: +case 0xB6E2: +case 0xB8E2: +case 0xBAE2: +case 0xBCE2: +case 0xBEE2: +case 0xB0E3: +case 0xB2E3: +case 0xB4E3: +case 0xB6E3: +case 0xB8E3: +case 0xBAE3: +case 0xBCE3: +case 0xBEE3: +case 0xB0E4: +case 0xB2E4: +case 0xB4E4: +case 0xB6E4: +case 0xB8E4: +case 0xBAE4: +case 0xBCE4: +case 0xBEE4: +case 0xB0E5: +case 0xB2E5: +case 0xB4E5: +case 0xB6E5: +case 0xB8E5: +case 0xBAE5: +case 0xBCE5: +case 0xBEE5: +case 0xB0E6: +case 0xB2E6: +case 0xB4E6: +case 0xB6E6: +case 0xB8E6: +case 0xBAE6: +case 0xBCE6: +case 0xBEE6: + +// CMPA +case 0xB0E0: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 2; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READSX_WORD_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + POST_IO +} +RET(12) +case 0xB2E8: +case 0xB4E8: +case 0xB6E8: +case 0xB8E8: +case 0xBAE8: +case 0xBCE8: +case 0xBEE8: +case 0xB0E9: +case 0xB2E9: +case 0xB4E9: +case 0xB6E9: +case 0xB8E9: +case 0xBAE9: +case 0xBCE9: +case 0xBEE9: +case 0xB0EA: +case 0xB2EA: +case 0xB4EA: +case 0xB6EA: +case 0xB8EA: +case 0xBAEA: +case 0xBCEA: +case 0xBEEA: +case 0xB0EB: +case 0xB2EB: +case 0xB4EB: +case 0xB6EB: +case 0xB8EB: +case 0xBAEB: +case 0xBCEB: +case 0xBEEB: +case 0xB0EC: +case 0xB2EC: +case 0xB4EC: +case 0xB6EC: +case 0xB8EC: +case 0xBAEC: +case 0xBCEC: +case 0xBEEC: +case 0xB0ED: +case 0xB2ED: +case 0xB4ED: +case 0xB6ED: +case 0xB8ED: +case 0xBAED: +case 0xBCED: +case 0xBEED: +case 0xB0EE: +case 0xB2EE: +case 0xB4EE: +case 0xB6EE: +case 0xB8EE: +case 0xBAEE: +case 0xBCEE: +case 0xBEEE: +case 0xB0EF: +case 0xB2EF: +case 0xB4EF: +case 0xB6EF: +case 0xB8EF: +case 0xBAEF: +case 0xBCEF: +case 0xBEEF: + +// CMPA +case 0xB0E8: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READSX_WORD_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + POST_IO +} +RET(14) +case 0xB2F0: +case 0xB4F0: +case 0xB6F0: +case 0xB8F0: +case 0xBAF0: +case 0xBCF0: +case 0xBEF0: +case 0xB0F1: +case 0xB2F1: +case 0xB4F1: +case 0xB6F1: +case 0xB8F1: +case 0xBAF1: +case 0xBCF1: +case 0xBEF1: +case 0xB0F2: +case 0xB2F2: +case 0xB4F2: +case 0xB6F2: +case 0xB8F2: +case 0xBAF2: +case 0xBCF2: +case 0xBEF2: +case 0xB0F3: +case 0xB2F3: +case 0xB4F3: +case 0xB6F3: +case 0xB8F3: +case 0xBAF3: +case 0xBCF3: +case 0xBEF3: +case 0xB0F4: +case 0xB2F4: +case 0xB4F4: +case 0xB6F4: +case 0xB8F4: +case 0xBAF4: +case 0xBCF4: +case 0xBEF4: +case 0xB0F5: +case 0xB2F5: +case 0xB4F5: +case 0xB6F5: +case 0xB8F5: +case 0xBAF5: +case 0xBCF5: +case 0xBEF5: +case 0xB0F6: +case 0xB2F6: +case 0xB4F6: +case 0xB6F6: +case 0xB8F6: +case 0xBAF6: +case 0xBCF6: +case 0xBEF6: +case 0xB0F7: +case 0xB2F7: +case 0xB4F7: +case 0xB6F7: +case 0xB8F7: +case 0xBAF7: +case 0xBCF7: +case 0xBEF7: + +// CMPA +case 0xB0F0: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READSX_WORD_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + POST_IO +} +RET(16) +case 0xB2F8: +case 0xB4F8: +case 0xB6F8: +case 0xB8F8: +case 0xBAF8: +case 0xBCF8: +case 0xBEF8: + +// CMPA +case 0xB0F8: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READSX_WORD_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + POST_IO +} +RET(14) +case 0xB2F9: +case 0xB4F9: +case 0xB6F9: +case 0xB8F9: +case 0xBAF9: +case 0xBCF9: +case 0xBEF9: + +// CMPA +case 0xB0F9: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READSX_WORD_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + POST_IO +} +RET(18) +case 0xB2FA: +case 0xB4FA: +case 0xB6FA: +case 0xB8FA: +case 0xBAFA: +case 0xBCFA: +case 0xBEFA: + +// CMPA +case 0xB0FA: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READSX_WORD_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + POST_IO +} +RET(14) +case 0xB2FB: +case 0xB4FB: +case 0xB6FB: +case 0xB8FB: +case 0xBAFB: +case 0xBCFB: +case 0xBEFB: + +// CMPA +case 0xB0FB: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READSX_WORD_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + POST_IO +} +RET(16) +case 0xB2FC: +case 0xB4FC: +case 0xB6FC: +case 0xB8FC: +case 0xBAFC: +case 0xBCFC: +case 0xBEFC: + +// CMPA +case 0xB0FC: +{ + u32 res; + pointer dst; + pointer src; + src = (s32)(s16)FETCH_WORD; + PC += 2; + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; +} +RET(10) +case 0xB2DF: +case 0xB4DF: +case 0xB6DF: +case 0xB8DF: +case 0xBADF: +case 0xBCDF: +case 0xBEDF: + +// CMPA +case 0xB0DF: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READSX_WORD_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + POST_IO +} +RET(10) +case 0xB2E7: +case 0xB4E7: +case 0xB6E7: +case 0xB8E7: +case 0xBAE7: +case 0xBCE7: +case 0xBEE7: + +// CMPA +case 0xB0E7: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READSX_WORD_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + POST_IO +} +RET(12) +case 0xB3C0: +case 0xB5C0: +case 0xB7C0: +case 0xB9C0: +case 0xBBC0: +case 0xBDC0: +case 0xBFC0: +case 0xB1C1: +case 0xB3C1: +case 0xB5C1: +case 0xB7C1: +case 0xB9C1: +case 0xBBC1: +case 0xBDC1: +case 0xBFC1: +case 0xB1C2: +case 0xB3C2: +case 0xB5C2: +case 0xB7C2: +case 0xB9C2: +case 0xBBC2: +case 0xBDC2: +case 0xBFC2: +case 0xB1C3: +case 0xB3C3: +case 0xB5C3: +case 0xB7C3: +case 0xB9C3: +case 0xBBC3: +case 0xBDC3: +case 0xBFC3: +case 0xB1C4: +case 0xB3C4: +case 0xB5C4: +case 0xB7C4: +case 0xB9C4: +case 0xBBC4: +case 0xBDC4: +case 0xBFC4: +case 0xB1C5: +case 0xB3C5: +case 0xB5C5: +case 0xB7C5: +case 0xB9C5: +case 0xBBC5: +case 0xBDC5: +case 0xBFC5: +case 0xB1C6: +case 0xB3C6: +case 0xB5C6: +case 0xB7C6: +case 0xB9C6: +case 0xBBC6: +case 0xBDC6: +case 0xBFC6: +case 0xB1C7: +case 0xB3C7: +case 0xB5C7: +case 0xB7C7: +case 0xB9C7: +case 0xBBC7: +case 0xBDC7: +case 0xBFC7: + +// CMPA +case 0xB1C0: +{ + u32 res; + pointer dst; + pointer src; + src = (s32)(s32)CPU->D[(Opcode >> 0) & 7]; + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; +} +RET(6) +case 0xB3C8: +case 0xB5C8: +case 0xB7C8: +case 0xB9C8: +case 0xBBC8: +case 0xBDC8: +case 0xBFC8: +case 0xB1C9: +case 0xB3C9: +case 0xB5C9: +case 0xB7C9: +case 0xB9C9: +case 0xBBC9: +case 0xBDC9: +case 0xBFC9: +case 0xB1CA: +case 0xB3CA: +case 0xB5CA: +case 0xB7CA: +case 0xB9CA: +case 0xBBCA: +case 0xBDCA: +case 0xBFCA: +case 0xB1CB: +case 0xB3CB: +case 0xB5CB: +case 0xB7CB: +case 0xB9CB: +case 0xBBCB: +case 0xBDCB: +case 0xBFCB: +case 0xB1CC: +case 0xB3CC: +case 0xB5CC: +case 0xB7CC: +case 0xB9CC: +case 0xBBCC: +case 0xBDCC: +case 0xBFCC: +case 0xB1CD: +case 0xB3CD: +case 0xB5CD: +case 0xB7CD: +case 0xB9CD: +case 0xBBCD: +case 0xBDCD: +case 0xBFCD: +case 0xB1CE: +case 0xB3CE: +case 0xB5CE: +case 0xB7CE: +case 0xB9CE: +case 0xBBCE: +case 0xBDCE: +case 0xBFCE: +case 0xB1CF: +case 0xB3CF: +case 0xB5CF: +case 0xB7CF: +case 0xB9CF: +case 0xBBCF: +case 0xBDCF: +case 0xBFCF: + +// CMPA +case 0xB1C8: +{ + u32 res; + pointer dst; + pointer src; + src = (s32)(s32)CPU->A[(Opcode >> 0) & 7]; + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; +} +RET(6) +case 0xB3D0: +case 0xB5D0: +case 0xB7D0: +case 0xB9D0: +case 0xBBD0: +case 0xBDD0: +case 0xBFD0: +case 0xB1D1: +case 0xB3D1: +case 0xB5D1: +case 0xB7D1: +case 0xB9D1: +case 0xBBD1: +case 0xBDD1: +case 0xBFD1: +case 0xB1D2: +case 0xB3D2: +case 0xB5D2: +case 0xB7D2: +case 0xB9D2: +case 0xBBD2: +case 0xBDD2: +case 0xBFD2: +case 0xB1D3: +case 0xB3D3: +case 0xB5D3: +case 0xB7D3: +case 0xB9D3: +case 0xBBD3: +case 0xBDD3: +case 0xBFD3: +case 0xB1D4: +case 0xB3D4: +case 0xB5D4: +case 0xB7D4: +case 0xB9D4: +case 0xBBD4: +case 0xBDD4: +case 0xBFD4: +case 0xB1D5: +case 0xB3D5: +case 0xB5D5: +case 0xB7D5: +case 0xB9D5: +case 0xBBD5: +case 0xBDD5: +case 0xBFD5: +case 0xB1D6: +case 0xB3D6: +case 0xB5D6: +case 0xB7D6: +case 0xB9D6: +case 0xBBD6: +case 0xBDD6: +case 0xBFD6: +case 0xB1D7: +case 0xB3D7: +case 0xB5D7: +case 0xB7D7: +case 0xB9D7: +case 0xBBD7: +case 0xBDD7: +case 0xBFD7: + +// CMPA +case 0xB1D0: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READSX_LONG_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + POST_IO +} +RET(14) +case 0xB3D8: +case 0xB5D8: +case 0xB7D8: +case 0xB9D8: +case 0xBBD8: +case 0xBDD8: +case 0xBFD8: +case 0xB1D9: +case 0xB3D9: +case 0xB5D9: +case 0xB7D9: +case 0xB9D9: +case 0xBBD9: +case 0xBDD9: +case 0xBFD9: +case 0xB1DA: +case 0xB3DA: +case 0xB5DA: +case 0xB7DA: +case 0xB9DA: +case 0xBBDA: +case 0xBDDA: +case 0xBFDA: +case 0xB1DB: +case 0xB3DB: +case 0xB5DB: +case 0xB7DB: +case 0xB9DB: +case 0xBBDB: +case 0xBDDB: +case 0xBFDB: +case 0xB1DC: +case 0xB3DC: +case 0xB5DC: +case 0xB7DC: +case 0xB9DC: +case 0xBBDC: +case 0xBDDC: +case 0xBFDC: +case 0xB1DD: +case 0xB3DD: +case 0xB5DD: +case 0xB7DD: +case 0xB9DD: +case 0xBBDD: +case 0xBDDD: +case 0xBFDD: +case 0xB1DE: +case 0xB3DE: +case 0xB5DE: +case 0xB7DE: +case 0xB9DE: +case 0xBBDE: +case 0xBDDE: +case 0xBFDE: + +// CMPA +case 0xB1D8: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 4; + PRE_IO + READSX_LONG_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + POST_IO +} +RET(14) +case 0xB3E0: +case 0xB5E0: +case 0xB7E0: +case 0xB9E0: +case 0xBBE0: +case 0xBDE0: +case 0xBFE0: +case 0xB1E1: +case 0xB3E1: +case 0xB5E1: +case 0xB7E1: +case 0xB9E1: +case 0xBBE1: +case 0xBDE1: +case 0xBFE1: +case 0xB1E2: +case 0xB3E2: +case 0xB5E2: +case 0xB7E2: +case 0xB9E2: +case 0xBBE2: +case 0xBDE2: +case 0xBFE2: +case 0xB1E3: +case 0xB3E3: +case 0xB5E3: +case 0xB7E3: +case 0xB9E3: +case 0xBBE3: +case 0xBDE3: +case 0xBFE3: +case 0xB1E4: +case 0xB3E4: +case 0xB5E4: +case 0xB7E4: +case 0xB9E4: +case 0xBBE4: +case 0xBDE4: +case 0xBFE4: +case 0xB1E5: +case 0xB3E5: +case 0xB5E5: +case 0xB7E5: +case 0xB9E5: +case 0xBBE5: +case 0xBDE5: +case 0xBFE5: +case 0xB1E6: +case 0xB3E6: +case 0xB5E6: +case 0xB7E6: +case 0xB9E6: +case 0xBBE6: +case 0xBDE6: +case 0xBFE6: + +// CMPA +case 0xB1E0: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 4; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READSX_LONG_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + POST_IO +} +RET(16) +case 0xB3E8: +case 0xB5E8: +case 0xB7E8: +case 0xB9E8: +case 0xBBE8: +case 0xBDE8: +case 0xBFE8: +case 0xB1E9: +case 0xB3E9: +case 0xB5E9: +case 0xB7E9: +case 0xB9E9: +case 0xBBE9: +case 0xBDE9: +case 0xBFE9: +case 0xB1EA: +case 0xB3EA: +case 0xB5EA: +case 0xB7EA: +case 0xB9EA: +case 0xBBEA: +case 0xBDEA: +case 0xBFEA: +case 0xB1EB: +case 0xB3EB: +case 0xB5EB: +case 0xB7EB: +case 0xB9EB: +case 0xBBEB: +case 0xBDEB: +case 0xBFEB: +case 0xB1EC: +case 0xB3EC: +case 0xB5EC: +case 0xB7EC: +case 0xB9EC: +case 0xBBEC: +case 0xBDEC: +case 0xBFEC: +case 0xB1ED: +case 0xB3ED: +case 0xB5ED: +case 0xB7ED: +case 0xB9ED: +case 0xBBED: +case 0xBDED: +case 0xBFED: +case 0xB1EE: +case 0xB3EE: +case 0xB5EE: +case 0xB7EE: +case 0xB9EE: +case 0xBBEE: +case 0xBDEE: +case 0xBFEE: +case 0xB1EF: +case 0xB3EF: +case 0xB5EF: +case 0xB7EF: +case 0xB9EF: +case 0xBBEF: +case 0xBDEF: +case 0xBFEF: + +// CMPA +case 0xB1E8: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READSX_LONG_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + POST_IO +} +RET(18) +case 0xB3F0: +case 0xB5F0: +case 0xB7F0: +case 0xB9F0: +case 0xBBF0: +case 0xBDF0: +case 0xBFF0: +case 0xB1F1: +case 0xB3F1: +case 0xB5F1: +case 0xB7F1: +case 0xB9F1: +case 0xBBF1: +case 0xBDF1: +case 0xBFF1: +case 0xB1F2: +case 0xB3F2: +case 0xB5F2: +case 0xB7F2: +case 0xB9F2: +case 0xBBF2: +case 0xBDF2: +case 0xBFF2: +case 0xB1F3: +case 0xB3F3: +case 0xB5F3: +case 0xB7F3: +case 0xB9F3: +case 0xBBF3: +case 0xBDF3: +case 0xBFF3: +case 0xB1F4: +case 0xB3F4: +case 0xB5F4: +case 0xB7F4: +case 0xB9F4: +case 0xBBF4: +case 0xBDF4: +case 0xBFF4: +case 0xB1F5: +case 0xB3F5: +case 0xB5F5: +case 0xB7F5: +case 0xB9F5: +case 0xBBF5: +case 0xBDF5: +case 0xBFF5: +case 0xB1F6: +case 0xB3F6: +case 0xB5F6: +case 0xB7F6: +case 0xB9F6: +case 0xBBF6: +case 0xBDF6: +case 0xBFF6: +case 0xB1F7: +case 0xB3F7: +case 0xB5F7: +case 0xB7F7: +case 0xB9F7: +case 0xBBF7: +case 0xBDF7: +case 0xBFF7: + +// CMPA +case 0xB1F0: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READSX_LONG_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + POST_IO +} +RET(20) +case 0xB3F8: +case 0xB5F8: +case 0xB7F8: +case 0xB9F8: +case 0xBBF8: +case 0xBDF8: +case 0xBFF8: + +// CMPA +case 0xB1F8: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READSX_LONG_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + POST_IO +} +RET(18) +case 0xB3F9: +case 0xB5F9: +case 0xB7F9: +case 0xB9F9: +case 0xBBF9: +case 0xBDF9: +case 0xBFF9: + +// CMPA +case 0xB1F9: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READSX_LONG_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + POST_IO +} +RET(22) +case 0xB3FA: +case 0xB5FA: +case 0xB7FA: +case 0xB9FA: +case 0xBBFA: +case 0xBDFA: +case 0xBFFA: + +// CMPA +case 0xB1FA: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READSX_LONG_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + POST_IO +} +RET(18) +case 0xB3FB: +case 0xB5FB: +case 0xB7FB: +case 0xB9FB: +case 0xBBFB: +case 0xBDFB: +case 0xBFFB: + +// CMPA +case 0xB1FB: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READSX_LONG_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + POST_IO +} +RET(20) +case 0xB3FC: +case 0xB5FC: +case 0xB7FC: +case 0xB9FC: +case 0xBBFC: +case 0xBDFC: +case 0xBFFC: + +// CMPA +case 0xB1FC: +{ + u32 res; + pointer dst; + pointer src; + src = (s32)(s32)FETCH_LONG; + PC += 4; + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; +} +RET(14) +case 0xB3DF: +case 0xB5DF: +case 0xB7DF: +case 0xB9DF: +case 0xBBDF: +case 0xBDDF: +case 0xBFDF: + +// CMPA +case 0xB1DF: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[7]; + CPU->A[7] += 4; + PRE_IO + READSX_LONG_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + POST_IO +} +RET(14) +case 0xB3E7: +case 0xB5E7: +case 0xB7E7: +case 0xB9E7: +case 0xBBE7: +case 0xBDE7: +case 0xBFE7: + +// CMPA +case 0xB1E7: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + PRE_IO + READSX_LONG_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst - src; + CPU->flag_notZ = res; + CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23; + CPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24; + CPU->flag_N = res >> 24; + POST_IO +} +RET(16) diff --git a/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68k_opC.inc b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68k_opC.inc new file mode 100644 index 000000000..f582fad81 --- /dev/null +++ b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68k_opC.inc @@ -0,0 +1,5383 @@ +case 0xC200: +case 0xC400: +case 0xC600: +case 0xC800: +case 0xCA00: +case 0xCC00: +case 0xCE00: +case 0xC001: +case 0xC201: +case 0xC401: +case 0xC601: +case 0xC801: +case 0xCA01: +case 0xCC01: +case 0xCE01: +case 0xC002: +case 0xC202: +case 0xC402: +case 0xC602: +case 0xC802: +case 0xCA02: +case 0xCC02: +case 0xCE02: +case 0xC003: +case 0xC203: +case 0xC403: +case 0xC603: +case 0xC803: +case 0xCA03: +case 0xCC03: +case 0xCE03: +case 0xC004: +case 0xC204: +case 0xC404: +case 0xC604: +case 0xC804: +case 0xCA04: +case 0xCC04: +case 0xCE04: +case 0xC005: +case 0xC205: +case 0xC405: +case 0xC605: +case 0xC805: +case 0xCA05: +case 0xCC05: +case 0xCE05: +case 0xC006: +case 0xC206: +case 0xC406: +case 0xC606: +case 0xC806: +case 0xCA06: +case 0xCC06: +case 0xCE06: +case 0xC007: +case 0xC207: +case 0xC407: +case 0xC607: +case 0xC807: +case 0xCA07: +case 0xCC07: +case 0xCE07: + +// ANDaD +case 0xC000: +{ + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 0) & 7]; + res = (u8)CPU->D[(Opcode >> 9) & 7]; + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; +} +RET(4) +case 0xC210: +case 0xC410: +case 0xC610: +case 0xC810: +case 0xCA10: +case 0xCC10: +case 0xCE10: +case 0xC011: +case 0xC211: +case 0xC411: +case 0xC611: +case 0xC811: +case 0xCA11: +case 0xCC11: +case 0xCE11: +case 0xC012: +case 0xC212: +case 0xC412: +case 0xC612: +case 0xC812: +case 0xCA12: +case 0xCC12: +case 0xCE12: +case 0xC013: +case 0xC213: +case 0xC413: +case 0xC613: +case 0xC813: +case 0xCA13: +case 0xCC13: +case 0xCE13: +case 0xC014: +case 0xC214: +case 0xC414: +case 0xC614: +case 0xC814: +case 0xCA14: +case 0xCC14: +case 0xCE14: +case 0xC015: +case 0xC215: +case 0xC415: +case 0xC615: +case 0xC815: +case 0xCA15: +case 0xCC15: +case 0xCE15: +case 0xC016: +case 0xC216: +case 0xC416: +case 0xC616: +case 0xC816: +case 0xCA16: +case 0xCC16: +case 0xCE16: +case 0xC017: +case 0xC217: +case 0xC417: +case 0xC617: +case 0xC817: +case 0xCA17: +case 0xCC17: +case 0xCE17: + +// ANDaD +case 0xC010: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_BYTE_F(adr, src) + res = (u8)CPU->D[(Opcode >> 9) & 7]; + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(8) +case 0xC218: +case 0xC418: +case 0xC618: +case 0xC818: +case 0xCA18: +case 0xCC18: +case 0xCE18: +case 0xC019: +case 0xC219: +case 0xC419: +case 0xC619: +case 0xC819: +case 0xCA19: +case 0xCC19: +case 0xCE19: +case 0xC01A: +case 0xC21A: +case 0xC41A: +case 0xC61A: +case 0xC81A: +case 0xCA1A: +case 0xCC1A: +case 0xCE1A: +case 0xC01B: +case 0xC21B: +case 0xC41B: +case 0xC61B: +case 0xC81B: +case 0xCA1B: +case 0xCC1B: +case 0xCE1B: +case 0xC01C: +case 0xC21C: +case 0xC41C: +case 0xC61C: +case 0xC81C: +case 0xCA1C: +case 0xCC1C: +case 0xCE1C: +case 0xC01D: +case 0xC21D: +case 0xC41D: +case 0xC61D: +case 0xC81D: +case 0xCA1D: +case 0xCC1D: +case 0xCE1D: +case 0xC01E: +case 0xC21E: +case 0xC41E: +case 0xC61E: +case 0xC81E: +case 0xCA1E: +case 0xCC1E: +case 0xCE1E: + +// ANDaD +case 0xC018: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + PRE_IO + READ_BYTE_F(adr, src) + res = (u8)CPU->D[(Opcode >> 9) & 7]; + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(8) +case 0xC220: +case 0xC420: +case 0xC620: +case 0xC820: +case 0xCA20: +case 0xCC20: +case 0xCE20: +case 0xC021: +case 0xC221: +case 0xC421: +case 0xC621: +case 0xC821: +case 0xCA21: +case 0xCC21: +case 0xCE21: +case 0xC022: +case 0xC222: +case 0xC422: +case 0xC622: +case 0xC822: +case 0xCA22: +case 0xCC22: +case 0xCE22: +case 0xC023: +case 0xC223: +case 0xC423: +case 0xC623: +case 0xC823: +case 0xCA23: +case 0xCC23: +case 0xCE23: +case 0xC024: +case 0xC224: +case 0xC424: +case 0xC624: +case 0xC824: +case 0xCA24: +case 0xCC24: +case 0xCE24: +case 0xC025: +case 0xC225: +case 0xC425: +case 0xC625: +case 0xC825: +case 0xCA25: +case 0xCC25: +case 0xCE25: +case 0xC026: +case 0xC226: +case 0xC426: +case 0xC626: +case 0xC826: +case 0xCA26: +case 0xCC26: +case 0xCE26: + +// ANDaD +case 0xC020: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_BYTE_F(adr, src) + res = (u8)CPU->D[(Opcode >> 9) & 7]; + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(10) +case 0xC228: +case 0xC428: +case 0xC628: +case 0xC828: +case 0xCA28: +case 0xCC28: +case 0xCE28: +case 0xC029: +case 0xC229: +case 0xC429: +case 0xC629: +case 0xC829: +case 0xCA29: +case 0xCC29: +case 0xCE29: +case 0xC02A: +case 0xC22A: +case 0xC42A: +case 0xC62A: +case 0xC82A: +case 0xCA2A: +case 0xCC2A: +case 0xCE2A: +case 0xC02B: +case 0xC22B: +case 0xC42B: +case 0xC62B: +case 0xC82B: +case 0xCA2B: +case 0xCC2B: +case 0xCE2B: +case 0xC02C: +case 0xC22C: +case 0xC42C: +case 0xC62C: +case 0xC82C: +case 0xCA2C: +case 0xCC2C: +case 0xCE2C: +case 0xC02D: +case 0xC22D: +case 0xC42D: +case 0xC62D: +case 0xC82D: +case 0xCA2D: +case 0xCC2D: +case 0xCE2D: +case 0xC02E: +case 0xC22E: +case 0xC42E: +case 0xC62E: +case 0xC82E: +case 0xCA2E: +case 0xCC2E: +case 0xCE2E: +case 0xC02F: +case 0xC22F: +case 0xC42F: +case 0xC62F: +case 0xC82F: +case 0xCA2F: +case 0xCC2F: +case 0xCE2F: + +// ANDaD +case 0xC028: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, src) + res = (u8)CPU->D[(Opcode >> 9) & 7]; + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(12) +case 0xC230: +case 0xC430: +case 0xC630: +case 0xC830: +case 0xCA30: +case 0xCC30: +case 0xCE30: +case 0xC031: +case 0xC231: +case 0xC431: +case 0xC631: +case 0xC831: +case 0xCA31: +case 0xCC31: +case 0xCE31: +case 0xC032: +case 0xC232: +case 0xC432: +case 0xC632: +case 0xC832: +case 0xCA32: +case 0xCC32: +case 0xCE32: +case 0xC033: +case 0xC233: +case 0xC433: +case 0xC633: +case 0xC833: +case 0xCA33: +case 0xCC33: +case 0xCE33: +case 0xC034: +case 0xC234: +case 0xC434: +case 0xC634: +case 0xC834: +case 0xCA34: +case 0xCC34: +case 0xCE34: +case 0xC035: +case 0xC235: +case 0xC435: +case 0xC635: +case 0xC835: +case 0xCA35: +case 0xCC35: +case 0xCE35: +case 0xC036: +case 0xC236: +case 0xC436: +case 0xC636: +case 0xC836: +case 0xCA36: +case 0xCC36: +case 0xCE36: +case 0xC037: +case 0xC237: +case 0xC437: +case 0xC637: +case 0xC837: +case 0xCA37: +case 0xCC37: +case 0xCE37: + +// ANDaD +case 0xC030: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, src) + res = (u8)CPU->D[(Opcode >> 9) & 7]; + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(14) +case 0xC238: +case 0xC438: +case 0xC638: +case 0xC838: +case 0xCA38: +case 0xCC38: +case 0xCE38: + +// ANDaD +case 0xC038: +{ + u32 adr; + u32 res; + pointer src; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, src) + res = (u8)CPU->D[(Opcode >> 9) & 7]; + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(12) +case 0xC239: +case 0xC439: +case 0xC639: +case 0xC839: +case 0xCA39: +case 0xCC39: +case 0xCE39: + +// ANDaD +case 0xC039: +{ + u32 adr; + u32 res; + pointer src; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_BYTE_F(adr, src) + res = (u8)CPU->D[(Opcode >> 9) & 7]; + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(16) +case 0xC23A: +case 0xC43A: +case 0xC63A: +case 0xC83A: +case 0xCA3A: +case 0xCC3A: +case 0xCE3A: + +// ANDaD +case 0xC03A: +{ + u32 adr; + u32 res; + pointer src; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, src) + res = (u8)CPU->D[(Opcode >> 9) & 7]; + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(12) +case 0xC23B: +case 0xC43B: +case 0xC63B: +case 0xC83B: +case 0xCA3B: +case 0xCC3B: +case 0xCE3B: + +// ANDaD +case 0xC03B: +{ + u32 adr; + u32 res; + pointer src; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, src) + res = (u8)CPU->D[(Opcode >> 9) & 7]; + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(14) +case 0xC23C: +case 0xC43C: +case 0xC63C: +case 0xC83C: +case 0xCA3C: +case 0xCC3C: +case 0xCE3C: + +// ANDaD +case 0xC03C: +{ + u32 res; + pointer src; + src = FETCH_BYTE; + PC += 2; + res = (u8)CPU->D[(Opcode >> 9) & 7]; + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; +} +RET(8) +case 0xC21F: +case 0xC41F: +case 0xC61F: +case 0xC81F: +case 0xCA1F: +case 0xCC1F: +case 0xCE1F: + +// ANDaD +case 0xC01F: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_BYTE_F(adr, src) + res = (u8)CPU->D[(Opcode >> 9) & 7]; + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(8) +case 0xC227: +case 0xC427: +case 0xC627: +case 0xC827: +case 0xCA27: +case 0xCC27: +case 0xCE27: + +// ANDaD +case 0xC027: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_BYTE_F(adr, src) + res = (u8)CPU->D[(Opcode >> 9) & 7]; + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(10) +case 0xC240: +case 0xC440: +case 0xC640: +case 0xC840: +case 0xCA40: +case 0xCC40: +case 0xCE40: +case 0xC041: +case 0xC241: +case 0xC441: +case 0xC641: +case 0xC841: +case 0xCA41: +case 0xCC41: +case 0xCE41: +case 0xC042: +case 0xC242: +case 0xC442: +case 0xC642: +case 0xC842: +case 0xCA42: +case 0xCC42: +case 0xCE42: +case 0xC043: +case 0xC243: +case 0xC443: +case 0xC643: +case 0xC843: +case 0xCA43: +case 0xCC43: +case 0xCE43: +case 0xC044: +case 0xC244: +case 0xC444: +case 0xC644: +case 0xC844: +case 0xCA44: +case 0xCC44: +case 0xCE44: +case 0xC045: +case 0xC245: +case 0xC445: +case 0xC645: +case 0xC845: +case 0xCA45: +case 0xCC45: +case 0xCE45: +case 0xC046: +case 0xC246: +case 0xC446: +case 0xC646: +case 0xC846: +case 0xCA46: +case 0xCC46: +case 0xCE46: +case 0xC047: +case 0xC247: +case 0xC447: +case 0xC647: +case 0xC847: +case 0xCA47: +case 0xCC47: +case 0xCE47: + +// ANDaD +case 0xC040: +{ + u32 res; + pointer src; + src = (u16)CPU->D[(Opcode >> 0) & 7]; + res = (u16)CPU->D[(Opcode >> 9) & 7]; + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; +} +RET(4) +case 0xC250: +case 0xC450: +case 0xC650: +case 0xC850: +case 0xCA50: +case 0xCC50: +case 0xCE50: +case 0xC051: +case 0xC251: +case 0xC451: +case 0xC651: +case 0xC851: +case 0xCA51: +case 0xCC51: +case 0xCE51: +case 0xC052: +case 0xC252: +case 0xC452: +case 0xC652: +case 0xC852: +case 0xCA52: +case 0xCC52: +case 0xCE52: +case 0xC053: +case 0xC253: +case 0xC453: +case 0xC653: +case 0xC853: +case 0xCA53: +case 0xCC53: +case 0xCE53: +case 0xC054: +case 0xC254: +case 0xC454: +case 0xC654: +case 0xC854: +case 0xCA54: +case 0xCC54: +case 0xCE54: +case 0xC055: +case 0xC255: +case 0xC455: +case 0xC655: +case 0xC855: +case 0xCA55: +case 0xCC55: +case 0xCE55: +case 0xC056: +case 0xC256: +case 0xC456: +case 0xC656: +case 0xC856: +case 0xCA56: +case 0xCC56: +case 0xCE56: +case 0xC057: +case 0xC257: +case 0xC457: +case 0xC657: +case 0xC857: +case 0xCA57: +case 0xCC57: +case 0xCE57: + +// ANDaD +case 0xC050: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_WORD_F(adr, src) + res = (u16)CPU->D[(Opcode >> 9) & 7]; + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(8) +case 0xC258: +case 0xC458: +case 0xC658: +case 0xC858: +case 0xCA58: +case 0xCC58: +case 0xCE58: +case 0xC059: +case 0xC259: +case 0xC459: +case 0xC659: +case 0xC859: +case 0xCA59: +case 0xCC59: +case 0xCE59: +case 0xC05A: +case 0xC25A: +case 0xC45A: +case 0xC65A: +case 0xC85A: +case 0xCA5A: +case 0xCC5A: +case 0xCE5A: +case 0xC05B: +case 0xC25B: +case 0xC45B: +case 0xC65B: +case 0xC85B: +case 0xCA5B: +case 0xCC5B: +case 0xCE5B: +case 0xC05C: +case 0xC25C: +case 0xC45C: +case 0xC65C: +case 0xC85C: +case 0xCA5C: +case 0xCC5C: +case 0xCE5C: +case 0xC05D: +case 0xC25D: +case 0xC45D: +case 0xC65D: +case 0xC85D: +case 0xCA5D: +case 0xCC5D: +case 0xCE5D: +case 0xC05E: +case 0xC25E: +case 0xC45E: +case 0xC65E: +case 0xC85E: +case 0xCA5E: +case 0xCC5E: +case 0xCE5E: + +// ANDaD +case 0xC058: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 2; + PRE_IO + READ_WORD_F(adr, src) + res = (u16)CPU->D[(Opcode >> 9) & 7]; + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(8) +case 0xC260: +case 0xC460: +case 0xC660: +case 0xC860: +case 0xCA60: +case 0xCC60: +case 0xCE60: +case 0xC061: +case 0xC261: +case 0xC461: +case 0xC661: +case 0xC861: +case 0xCA61: +case 0xCC61: +case 0xCE61: +case 0xC062: +case 0xC262: +case 0xC462: +case 0xC662: +case 0xC862: +case 0xCA62: +case 0xCC62: +case 0xCE62: +case 0xC063: +case 0xC263: +case 0xC463: +case 0xC663: +case 0xC863: +case 0xCA63: +case 0xCC63: +case 0xCE63: +case 0xC064: +case 0xC264: +case 0xC464: +case 0xC664: +case 0xC864: +case 0xCA64: +case 0xCC64: +case 0xCE64: +case 0xC065: +case 0xC265: +case 0xC465: +case 0xC665: +case 0xC865: +case 0xCA65: +case 0xCC65: +case 0xCE65: +case 0xC066: +case 0xC266: +case 0xC466: +case 0xC666: +case 0xC866: +case 0xCA66: +case 0xCC66: +case 0xCE66: + +// ANDaD +case 0xC060: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 2; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_WORD_F(adr, src) + res = (u16)CPU->D[(Opcode >> 9) & 7]; + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(10) +case 0xC268: +case 0xC468: +case 0xC668: +case 0xC868: +case 0xCA68: +case 0xCC68: +case 0xCE68: +case 0xC069: +case 0xC269: +case 0xC469: +case 0xC669: +case 0xC869: +case 0xCA69: +case 0xCC69: +case 0xCE69: +case 0xC06A: +case 0xC26A: +case 0xC46A: +case 0xC66A: +case 0xC86A: +case 0xCA6A: +case 0xCC6A: +case 0xCE6A: +case 0xC06B: +case 0xC26B: +case 0xC46B: +case 0xC66B: +case 0xC86B: +case 0xCA6B: +case 0xCC6B: +case 0xCE6B: +case 0xC06C: +case 0xC26C: +case 0xC46C: +case 0xC66C: +case 0xC86C: +case 0xCA6C: +case 0xCC6C: +case 0xCE6C: +case 0xC06D: +case 0xC26D: +case 0xC46D: +case 0xC66D: +case 0xC86D: +case 0xCA6D: +case 0xCC6D: +case 0xCE6D: +case 0xC06E: +case 0xC26E: +case 0xC46E: +case 0xC66E: +case 0xC86E: +case 0xCA6E: +case 0xCC6E: +case 0xCE6E: +case 0xC06F: +case 0xC26F: +case 0xC46F: +case 0xC66F: +case 0xC86F: +case 0xCA6F: +case 0xCC6F: +case 0xCE6F: + +// ANDaD +case 0xC068: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, src) + res = (u16)CPU->D[(Opcode >> 9) & 7]; + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(12) +case 0xC270: +case 0xC470: +case 0xC670: +case 0xC870: +case 0xCA70: +case 0xCC70: +case 0xCE70: +case 0xC071: +case 0xC271: +case 0xC471: +case 0xC671: +case 0xC871: +case 0xCA71: +case 0xCC71: +case 0xCE71: +case 0xC072: +case 0xC272: +case 0xC472: +case 0xC672: +case 0xC872: +case 0xCA72: +case 0xCC72: +case 0xCE72: +case 0xC073: +case 0xC273: +case 0xC473: +case 0xC673: +case 0xC873: +case 0xCA73: +case 0xCC73: +case 0xCE73: +case 0xC074: +case 0xC274: +case 0xC474: +case 0xC674: +case 0xC874: +case 0xCA74: +case 0xCC74: +case 0xCE74: +case 0xC075: +case 0xC275: +case 0xC475: +case 0xC675: +case 0xC875: +case 0xCA75: +case 0xCC75: +case 0xCE75: +case 0xC076: +case 0xC276: +case 0xC476: +case 0xC676: +case 0xC876: +case 0xCA76: +case 0xCC76: +case 0xCE76: +case 0xC077: +case 0xC277: +case 0xC477: +case 0xC677: +case 0xC877: +case 0xCA77: +case 0xCC77: +case 0xCE77: + +// ANDaD +case 0xC070: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, src) + res = (u16)CPU->D[(Opcode >> 9) & 7]; + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(14) +case 0xC278: +case 0xC478: +case 0xC678: +case 0xC878: +case 0xCA78: +case 0xCC78: +case 0xCE78: + +// ANDaD +case 0xC078: +{ + u32 adr; + u32 res; + pointer src; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, src) + res = (u16)CPU->D[(Opcode >> 9) & 7]; + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(12) +case 0xC279: +case 0xC479: +case 0xC679: +case 0xC879: +case 0xCA79: +case 0xCC79: +case 0xCE79: + +// ANDaD +case 0xC079: +{ + u32 adr; + u32 res; + pointer src; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_WORD_F(adr, src) + res = (u16)CPU->D[(Opcode >> 9) & 7]; + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(16) +case 0xC27A: +case 0xC47A: +case 0xC67A: +case 0xC87A: +case 0xCA7A: +case 0xCC7A: +case 0xCE7A: + +// ANDaD +case 0xC07A: +{ + u32 adr; + u32 res; + pointer src; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, src) + res = (u16)CPU->D[(Opcode >> 9) & 7]; + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(12) +case 0xC27B: +case 0xC47B: +case 0xC67B: +case 0xC87B: +case 0xCA7B: +case 0xCC7B: +case 0xCE7B: + +// ANDaD +case 0xC07B: +{ + u32 adr; + u32 res; + pointer src; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, src) + res = (u16)CPU->D[(Opcode >> 9) & 7]; + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(14) +case 0xC27C: +case 0xC47C: +case 0xC67C: +case 0xC87C: +case 0xCA7C: +case 0xCC7C: +case 0xCE7C: + +// ANDaD +case 0xC07C: +{ + u32 res; + pointer src; + src = FETCH_WORD; + PC += 2; + res = (u16)CPU->D[(Opcode >> 9) & 7]; + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; +} +RET(8) +case 0xC25F: +case 0xC45F: +case 0xC65F: +case 0xC85F: +case 0xCA5F: +case 0xCC5F: +case 0xCE5F: + +// ANDaD +case 0xC05F: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_WORD_F(adr, src) + res = (u16)CPU->D[(Opcode >> 9) & 7]; + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(8) +case 0xC267: +case 0xC467: +case 0xC667: +case 0xC867: +case 0xCA67: +case 0xCC67: +case 0xCE67: + +// ANDaD +case 0xC067: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_WORD_F(adr, src) + res = (u16)CPU->D[(Opcode >> 9) & 7]; + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(10) +case 0xC280: +case 0xC480: +case 0xC680: +case 0xC880: +case 0xCA80: +case 0xCC80: +case 0xCE80: +case 0xC081: +case 0xC281: +case 0xC481: +case 0xC681: +case 0xC881: +case 0xCA81: +case 0xCC81: +case 0xCE81: +case 0xC082: +case 0xC282: +case 0xC482: +case 0xC682: +case 0xC882: +case 0xCA82: +case 0xCC82: +case 0xCE82: +case 0xC083: +case 0xC283: +case 0xC483: +case 0xC683: +case 0xC883: +case 0xCA83: +case 0xCC83: +case 0xCE83: +case 0xC084: +case 0xC284: +case 0xC484: +case 0xC684: +case 0xC884: +case 0xCA84: +case 0xCC84: +case 0xCE84: +case 0xC085: +case 0xC285: +case 0xC485: +case 0xC685: +case 0xC885: +case 0xCA85: +case 0xCC85: +case 0xCE85: +case 0xC086: +case 0xC286: +case 0xC486: +case 0xC686: +case 0xC886: +case 0xCA86: +case 0xCC86: +case 0xCE86: +case 0xC087: +case 0xC287: +case 0xC487: +case 0xC687: +case 0xC887: +case 0xCA87: +case 0xCC87: +case 0xCE87: + +// ANDaD +case 0xC080: +{ + u32 res; + pointer src; + src = (u32)CPU->D[(Opcode >> 0) & 7]; + res = (u32)CPU->D[(Opcode >> 9) & 7]; + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; +} +RET(6) +case 0xC290: +case 0xC490: +case 0xC690: +case 0xC890: +case 0xCA90: +case 0xCC90: +case 0xCE90: +case 0xC091: +case 0xC291: +case 0xC491: +case 0xC691: +case 0xC891: +case 0xCA91: +case 0xCC91: +case 0xCE91: +case 0xC092: +case 0xC292: +case 0xC492: +case 0xC692: +case 0xC892: +case 0xCA92: +case 0xCC92: +case 0xCE92: +case 0xC093: +case 0xC293: +case 0xC493: +case 0xC693: +case 0xC893: +case 0xCA93: +case 0xCC93: +case 0xCE93: +case 0xC094: +case 0xC294: +case 0xC494: +case 0xC694: +case 0xC894: +case 0xCA94: +case 0xCC94: +case 0xCE94: +case 0xC095: +case 0xC295: +case 0xC495: +case 0xC695: +case 0xC895: +case 0xCA95: +case 0xCC95: +case 0xCE95: +case 0xC096: +case 0xC296: +case 0xC496: +case 0xC696: +case 0xC896: +case 0xCA96: +case 0xCC96: +case 0xCE96: +case 0xC097: +case 0xC297: +case 0xC497: +case 0xC697: +case 0xC897: +case 0xCA97: +case 0xCC97: +case 0xCE97: + +// ANDaD +case 0xC090: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_LONG_F(adr, src) + res = (u32)CPU->D[(Opcode >> 9) & 7]; + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(16) +case 0xC298: +case 0xC498: +case 0xC698: +case 0xC898: +case 0xCA98: +case 0xCC98: +case 0xCE98: +case 0xC099: +case 0xC299: +case 0xC499: +case 0xC699: +case 0xC899: +case 0xCA99: +case 0xCC99: +case 0xCE99: +case 0xC09A: +case 0xC29A: +case 0xC49A: +case 0xC69A: +case 0xC89A: +case 0xCA9A: +case 0xCC9A: +case 0xCE9A: +case 0xC09B: +case 0xC29B: +case 0xC49B: +case 0xC69B: +case 0xC89B: +case 0xCA9B: +case 0xCC9B: +case 0xCE9B: +case 0xC09C: +case 0xC29C: +case 0xC49C: +case 0xC69C: +case 0xC89C: +case 0xCA9C: +case 0xCC9C: +case 0xCE9C: +case 0xC09D: +case 0xC29D: +case 0xC49D: +case 0xC69D: +case 0xC89D: +case 0xCA9D: +case 0xCC9D: +case 0xCE9D: +case 0xC09E: +case 0xC29E: +case 0xC49E: +case 0xC69E: +case 0xC89E: +case 0xCA9E: +case 0xCC9E: +case 0xCE9E: + +// ANDaD +case 0xC098: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 4; + PRE_IO + READ_LONG_F(adr, src) + res = (u32)CPU->D[(Opcode >> 9) & 7]; + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(16) +case 0xC2A0: +case 0xC4A0: +case 0xC6A0: +case 0xC8A0: +case 0xCAA0: +case 0xCCA0: +case 0xCEA0: +case 0xC0A1: +case 0xC2A1: +case 0xC4A1: +case 0xC6A1: +case 0xC8A1: +case 0xCAA1: +case 0xCCA1: +case 0xCEA1: +case 0xC0A2: +case 0xC2A2: +case 0xC4A2: +case 0xC6A2: +case 0xC8A2: +case 0xCAA2: +case 0xCCA2: +case 0xCEA2: +case 0xC0A3: +case 0xC2A3: +case 0xC4A3: +case 0xC6A3: +case 0xC8A3: +case 0xCAA3: +case 0xCCA3: +case 0xCEA3: +case 0xC0A4: +case 0xC2A4: +case 0xC4A4: +case 0xC6A4: +case 0xC8A4: +case 0xCAA4: +case 0xCCA4: +case 0xCEA4: +case 0xC0A5: +case 0xC2A5: +case 0xC4A5: +case 0xC6A5: +case 0xC8A5: +case 0xCAA5: +case 0xCCA5: +case 0xCEA5: +case 0xC0A6: +case 0xC2A6: +case 0xC4A6: +case 0xC6A6: +case 0xC8A6: +case 0xCAA6: +case 0xCCA6: +case 0xCEA6: + +// ANDaD +case 0xC0A0: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 4; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_LONG_F(adr, src) + res = (u32)CPU->D[(Opcode >> 9) & 7]; + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(18) +case 0xC2A8: +case 0xC4A8: +case 0xC6A8: +case 0xC8A8: +case 0xCAA8: +case 0xCCA8: +case 0xCEA8: +case 0xC0A9: +case 0xC2A9: +case 0xC4A9: +case 0xC6A9: +case 0xC8A9: +case 0xCAA9: +case 0xCCA9: +case 0xCEA9: +case 0xC0AA: +case 0xC2AA: +case 0xC4AA: +case 0xC6AA: +case 0xC8AA: +case 0xCAAA: +case 0xCCAA: +case 0xCEAA: +case 0xC0AB: +case 0xC2AB: +case 0xC4AB: +case 0xC6AB: +case 0xC8AB: +case 0xCAAB: +case 0xCCAB: +case 0xCEAB: +case 0xC0AC: +case 0xC2AC: +case 0xC4AC: +case 0xC6AC: +case 0xC8AC: +case 0xCAAC: +case 0xCCAC: +case 0xCEAC: +case 0xC0AD: +case 0xC2AD: +case 0xC4AD: +case 0xC6AD: +case 0xC8AD: +case 0xCAAD: +case 0xCCAD: +case 0xCEAD: +case 0xC0AE: +case 0xC2AE: +case 0xC4AE: +case 0xC6AE: +case 0xC8AE: +case 0xCAAE: +case 0xCCAE: +case 0xCEAE: +case 0xC0AF: +case 0xC2AF: +case 0xC4AF: +case 0xC6AF: +case 0xC8AF: +case 0xCAAF: +case 0xCCAF: +case 0xCEAF: + +// ANDaD +case 0xC0A8: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, src) + res = (u32)CPU->D[(Opcode >> 9) & 7]; + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(20) +case 0xC2B0: +case 0xC4B0: +case 0xC6B0: +case 0xC8B0: +case 0xCAB0: +case 0xCCB0: +case 0xCEB0: +case 0xC0B1: +case 0xC2B1: +case 0xC4B1: +case 0xC6B1: +case 0xC8B1: +case 0xCAB1: +case 0xCCB1: +case 0xCEB1: +case 0xC0B2: +case 0xC2B2: +case 0xC4B2: +case 0xC6B2: +case 0xC8B2: +case 0xCAB2: +case 0xCCB2: +case 0xCEB2: +case 0xC0B3: +case 0xC2B3: +case 0xC4B3: +case 0xC6B3: +case 0xC8B3: +case 0xCAB3: +case 0xCCB3: +case 0xCEB3: +case 0xC0B4: +case 0xC2B4: +case 0xC4B4: +case 0xC6B4: +case 0xC8B4: +case 0xCAB4: +case 0xCCB4: +case 0xCEB4: +case 0xC0B5: +case 0xC2B5: +case 0xC4B5: +case 0xC6B5: +case 0xC8B5: +case 0xCAB5: +case 0xCCB5: +case 0xCEB5: +case 0xC0B6: +case 0xC2B6: +case 0xC4B6: +case 0xC6B6: +case 0xC8B6: +case 0xCAB6: +case 0xCCB6: +case 0xCEB6: +case 0xC0B7: +case 0xC2B7: +case 0xC4B7: +case 0xC6B7: +case 0xC8B7: +case 0xCAB7: +case 0xCCB7: +case 0xCEB7: + +// ANDaD +case 0xC0B0: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_LONG_F(adr, src) + res = (u32)CPU->D[(Opcode >> 9) & 7]; + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(22) +case 0xC2B8: +case 0xC4B8: +case 0xC6B8: +case 0xC8B8: +case 0xCAB8: +case 0xCCB8: +case 0xCEB8: + +// ANDaD +case 0xC0B8: +{ + u32 adr; + u32 res; + pointer src; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, src) + res = (u32)CPU->D[(Opcode >> 9) & 7]; + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(20) +case 0xC2B9: +case 0xC4B9: +case 0xC6B9: +case 0xC8B9: +case 0xCAB9: +case 0xCCB9: +case 0xCEB9: + +// ANDaD +case 0xC0B9: +{ + u32 adr; + u32 res; + pointer src; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_LONG_F(adr, src) + res = (u32)CPU->D[(Opcode >> 9) & 7]; + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(24) +case 0xC2BA: +case 0xC4BA: +case 0xC6BA: +case 0xC8BA: +case 0xCABA: +case 0xCCBA: +case 0xCEBA: + +// ANDaD +case 0xC0BA: +{ + u32 adr; + u32 res; + pointer src; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, src) + res = (u32)CPU->D[(Opcode >> 9) & 7]; + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(20) +case 0xC2BB: +case 0xC4BB: +case 0xC6BB: +case 0xC8BB: +case 0xCABB: +case 0xCCBB: +case 0xCEBB: + +// ANDaD +case 0xC0BB: +{ + u32 adr; + u32 res; + pointer src; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READ_LONG_F(adr, src) + res = (u32)CPU->D[(Opcode >> 9) & 7]; + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(22) +case 0xC2BC: +case 0xC4BC: +case 0xC6BC: +case 0xC8BC: +case 0xCABC: +case 0xCCBC: +case 0xCEBC: + +// ANDaD +case 0xC0BC: +{ + u32 res; + pointer src; + src = FETCH_LONG; + PC += 4; + res = (u32)CPU->D[(Opcode >> 9) & 7]; + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; +} +RET(14) +case 0xC29F: +case 0xC49F: +case 0xC69F: +case 0xC89F: +case 0xCA9F: +case 0xCC9F: +case 0xCE9F: + +// ANDaD +case 0xC09F: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[7]; + CPU->A[7] += 4; + PRE_IO + READ_LONG_F(adr, src) + res = (u32)CPU->D[(Opcode >> 9) & 7]; + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(16) +case 0xC2A7: +case 0xC4A7: +case 0xC6A7: +case 0xC8A7: +case 0xCAA7: +case 0xCCA7: +case 0xCEA7: + +// ANDaD +case 0xC0A7: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + PRE_IO + READ_LONG_F(adr, src) + res = (u32)CPU->D[(Opcode >> 9) & 7]; + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(18) +case 0xC310: +case 0xC510: +case 0xC710: +case 0xC910: +case 0xCB10: +case 0xCD10: +case 0xCF10: +case 0xC111: +case 0xC311: +case 0xC511: +case 0xC711: +case 0xC911: +case 0xCB11: +case 0xCD11: +case 0xCF11: +case 0xC112: +case 0xC312: +case 0xC512: +case 0xC712: +case 0xC912: +case 0xCB12: +case 0xCD12: +case 0xCF12: +case 0xC113: +case 0xC313: +case 0xC513: +case 0xC713: +case 0xC913: +case 0xCB13: +case 0xCD13: +case 0xCF13: +case 0xC114: +case 0xC314: +case 0xC514: +case 0xC714: +case 0xC914: +case 0xCB14: +case 0xCD14: +case 0xCF14: +case 0xC115: +case 0xC315: +case 0xC515: +case 0xC715: +case 0xC915: +case 0xCB15: +case 0xCD15: +case 0xCF15: +case 0xC116: +case 0xC316: +case 0xC516: +case 0xC716: +case 0xC916: +case 0xCB16: +case 0xCD16: +case 0xCF16: +case 0xC117: +case 0xC317: +case 0xC517: +case 0xC717: +case 0xC917: +case 0xCB17: +case 0xCD17: +case 0xCF17: + +// ANDDa +case 0xC110: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_BYTE_F(adr, res) + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0xC318: +case 0xC518: +case 0xC718: +case 0xC918: +case 0xCB18: +case 0xCD18: +case 0xCF18: +case 0xC119: +case 0xC319: +case 0xC519: +case 0xC719: +case 0xC919: +case 0xCB19: +case 0xCD19: +case 0xCF19: +case 0xC11A: +case 0xC31A: +case 0xC51A: +case 0xC71A: +case 0xC91A: +case 0xCB1A: +case 0xCD1A: +case 0xCF1A: +case 0xC11B: +case 0xC31B: +case 0xC51B: +case 0xC71B: +case 0xC91B: +case 0xCB1B: +case 0xCD1B: +case 0xCF1B: +case 0xC11C: +case 0xC31C: +case 0xC51C: +case 0xC71C: +case 0xC91C: +case 0xCB1C: +case 0xCD1C: +case 0xCF1C: +case 0xC11D: +case 0xC31D: +case 0xC51D: +case 0xC71D: +case 0xC91D: +case 0xCB1D: +case 0xCD1D: +case 0xCF1D: +case 0xC11E: +case 0xC31E: +case 0xC51E: +case 0xC71E: +case 0xC91E: +case 0xCB1E: +case 0xCD1E: +case 0xCF1E: + +// ANDDa +case 0xC118: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + PRE_IO + READ_BYTE_F(adr, res) + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0xC320: +case 0xC520: +case 0xC720: +case 0xC920: +case 0xCB20: +case 0xCD20: +case 0xCF20: +case 0xC121: +case 0xC321: +case 0xC521: +case 0xC721: +case 0xC921: +case 0xCB21: +case 0xCD21: +case 0xCF21: +case 0xC122: +case 0xC322: +case 0xC522: +case 0xC722: +case 0xC922: +case 0xCB22: +case 0xCD22: +case 0xCF22: +case 0xC123: +case 0xC323: +case 0xC523: +case 0xC723: +case 0xC923: +case 0xCB23: +case 0xCD23: +case 0xCF23: +case 0xC124: +case 0xC324: +case 0xC524: +case 0xC724: +case 0xC924: +case 0xCB24: +case 0xCD24: +case 0xCF24: +case 0xC125: +case 0xC325: +case 0xC525: +case 0xC725: +case 0xC925: +case 0xCB25: +case 0xCD25: +case 0xCF25: +case 0xC126: +case 0xC326: +case 0xC526: +case 0xC726: +case 0xC926: +case 0xCB26: +case 0xCD26: +case 0xCF26: + +// ANDDa +case 0xC120: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_BYTE_F(adr, res) + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(14) +case 0xC328: +case 0xC528: +case 0xC728: +case 0xC928: +case 0xCB28: +case 0xCD28: +case 0xCF28: +case 0xC129: +case 0xC329: +case 0xC529: +case 0xC729: +case 0xC929: +case 0xCB29: +case 0xCD29: +case 0xCF29: +case 0xC12A: +case 0xC32A: +case 0xC52A: +case 0xC72A: +case 0xC92A: +case 0xCB2A: +case 0xCD2A: +case 0xCF2A: +case 0xC12B: +case 0xC32B: +case 0xC52B: +case 0xC72B: +case 0xC92B: +case 0xCB2B: +case 0xCD2B: +case 0xCF2B: +case 0xC12C: +case 0xC32C: +case 0xC52C: +case 0xC72C: +case 0xC92C: +case 0xCB2C: +case 0xCD2C: +case 0xCF2C: +case 0xC12D: +case 0xC32D: +case 0xC52D: +case 0xC72D: +case 0xC92D: +case 0xCB2D: +case 0xCD2D: +case 0xCF2D: +case 0xC12E: +case 0xC32E: +case 0xC52E: +case 0xC72E: +case 0xC92E: +case 0xCB2E: +case 0xCD2E: +case 0xCF2E: +case 0xC12F: +case 0xC32F: +case 0xC52F: +case 0xC72F: +case 0xC92F: +case 0xCB2F: +case 0xCD2F: +case 0xCF2F: + +// ANDDa +case 0xC128: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0xC330: +case 0xC530: +case 0xC730: +case 0xC930: +case 0xCB30: +case 0xCD30: +case 0xCF30: +case 0xC131: +case 0xC331: +case 0xC531: +case 0xC731: +case 0xC931: +case 0xCB31: +case 0xCD31: +case 0xCF31: +case 0xC132: +case 0xC332: +case 0xC532: +case 0xC732: +case 0xC932: +case 0xCB32: +case 0xCD32: +case 0xCF32: +case 0xC133: +case 0xC333: +case 0xC533: +case 0xC733: +case 0xC933: +case 0xCB33: +case 0xCD33: +case 0xCF33: +case 0xC134: +case 0xC334: +case 0xC534: +case 0xC734: +case 0xC934: +case 0xCB34: +case 0xCD34: +case 0xCF34: +case 0xC135: +case 0xC335: +case 0xC535: +case 0xC735: +case 0xC935: +case 0xCB35: +case 0xCD35: +case 0xCF35: +case 0xC136: +case 0xC336: +case 0xC536: +case 0xC736: +case 0xC936: +case 0xCB36: +case 0xCD36: +case 0xCF36: +case 0xC137: +case 0xC337: +case 0xC537: +case 0xC737: +case 0xC937: +case 0xCB37: +case 0xCD37: +case 0xCF37: + +// ANDDa +case 0xC130: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, res) + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) +case 0xC338: +case 0xC538: +case 0xC738: +case 0xC938: +case 0xCB38: +case 0xCD38: +case 0xCF38: + +// ANDDa +case 0xC138: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, res) + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0xC339: +case 0xC539: +case 0xC739: +case 0xC939: +case 0xCB39: +case 0xCD39: +case 0xCF39: + +// ANDDa +case 0xC139: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_BYTE_F(adr, res) + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(20) +case 0xC31F: +case 0xC51F: +case 0xC71F: +case 0xC91F: +case 0xCB1F: +case 0xCD1F: +case 0xCF1F: + +// ANDDa +case 0xC11F: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_BYTE_F(adr, res) + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0xC327: +case 0xC527: +case 0xC727: +case 0xC927: +case 0xCB27: +case 0xCD27: +case 0xCF27: + +// ANDDa +case 0xC127: +{ + u32 adr; + u32 res; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_BYTE_F(adr, res) + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(14) +case 0xC350: +case 0xC550: +case 0xC750: +case 0xC950: +case 0xCB50: +case 0xCD50: +case 0xCF50: +case 0xC151: +case 0xC351: +case 0xC551: +case 0xC751: +case 0xC951: +case 0xCB51: +case 0xCD51: +case 0xCF51: +case 0xC152: +case 0xC352: +case 0xC552: +case 0xC752: +case 0xC952: +case 0xCB52: +case 0xCD52: +case 0xCF52: +case 0xC153: +case 0xC353: +case 0xC553: +case 0xC753: +case 0xC953: +case 0xCB53: +case 0xCD53: +case 0xCF53: +case 0xC154: +case 0xC354: +case 0xC554: +case 0xC754: +case 0xC954: +case 0xCB54: +case 0xCD54: +case 0xCF54: +case 0xC155: +case 0xC355: +case 0xC555: +case 0xC755: +case 0xC955: +case 0xCB55: +case 0xCD55: +case 0xCF55: +case 0xC156: +case 0xC356: +case 0xC556: +case 0xC756: +case 0xC956: +case 0xCB56: +case 0xCD56: +case 0xCF56: +case 0xC157: +case 0xC357: +case 0xC557: +case 0xC757: +case 0xC957: +case 0xCB57: +case 0xCD57: +case 0xCF57: + +// ANDDa +case 0xC150: +{ + u32 adr; + u32 res; + pointer src; + src = (u16)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_WORD_F(adr, res) + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0xC358: +case 0xC558: +case 0xC758: +case 0xC958: +case 0xCB58: +case 0xCD58: +case 0xCF58: +case 0xC159: +case 0xC359: +case 0xC559: +case 0xC759: +case 0xC959: +case 0xCB59: +case 0xCD59: +case 0xCF59: +case 0xC15A: +case 0xC35A: +case 0xC55A: +case 0xC75A: +case 0xC95A: +case 0xCB5A: +case 0xCD5A: +case 0xCF5A: +case 0xC15B: +case 0xC35B: +case 0xC55B: +case 0xC75B: +case 0xC95B: +case 0xCB5B: +case 0xCD5B: +case 0xCF5B: +case 0xC15C: +case 0xC35C: +case 0xC55C: +case 0xC75C: +case 0xC95C: +case 0xCB5C: +case 0xCD5C: +case 0xCF5C: +case 0xC15D: +case 0xC35D: +case 0xC55D: +case 0xC75D: +case 0xC95D: +case 0xCB5D: +case 0xCD5D: +case 0xCF5D: +case 0xC15E: +case 0xC35E: +case 0xC55E: +case 0xC75E: +case 0xC95E: +case 0xCB5E: +case 0xCD5E: +case 0xCF5E: + +// ANDDa +case 0xC158: +{ + u32 adr; + u32 res; + pointer src; + src = (u16)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 2; + PRE_IO + READ_WORD_F(adr, res) + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0xC360: +case 0xC560: +case 0xC760: +case 0xC960: +case 0xCB60: +case 0xCD60: +case 0xCF60: +case 0xC161: +case 0xC361: +case 0xC561: +case 0xC761: +case 0xC961: +case 0xCB61: +case 0xCD61: +case 0xCF61: +case 0xC162: +case 0xC362: +case 0xC562: +case 0xC762: +case 0xC962: +case 0xCB62: +case 0xCD62: +case 0xCF62: +case 0xC163: +case 0xC363: +case 0xC563: +case 0xC763: +case 0xC963: +case 0xCB63: +case 0xCD63: +case 0xCF63: +case 0xC164: +case 0xC364: +case 0xC564: +case 0xC764: +case 0xC964: +case 0xCB64: +case 0xCD64: +case 0xCF64: +case 0xC165: +case 0xC365: +case 0xC565: +case 0xC765: +case 0xC965: +case 0xCB65: +case 0xCD65: +case 0xCF65: +case 0xC166: +case 0xC366: +case 0xC566: +case 0xC766: +case 0xC966: +case 0xCB66: +case 0xCD66: +case 0xCF66: + +// ANDDa +case 0xC160: +{ + u32 adr; + u32 res; + pointer src; + src = (u16)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7] - 2; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_WORD_F(adr, res) + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(14) +case 0xC368: +case 0xC568: +case 0xC768: +case 0xC968: +case 0xCB68: +case 0xCD68: +case 0xCF68: +case 0xC169: +case 0xC369: +case 0xC569: +case 0xC769: +case 0xC969: +case 0xCB69: +case 0xCD69: +case 0xCF69: +case 0xC16A: +case 0xC36A: +case 0xC56A: +case 0xC76A: +case 0xC96A: +case 0xCB6A: +case 0xCD6A: +case 0xCF6A: +case 0xC16B: +case 0xC36B: +case 0xC56B: +case 0xC76B: +case 0xC96B: +case 0xCB6B: +case 0xCD6B: +case 0xCF6B: +case 0xC16C: +case 0xC36C: +case 0xC56C: +case 0xC76C: +case 0xC96C: +case 0xCB6C: +case 0xCD6C: +case 0xCF6C: +case 0xC16D: +case 0xC36D: +case 0xC56D: +case 0xC76D: +case 0xC96D: +case 0xCB6D: +case 0xCD6D: +case 0xCF6D: +case 0xC16E: +case 0xC36E: +case 0xC56E: +case 0xC76E: +case 0xC96E: +case 0xCB6E: +case 0xCD6E: +case 0xCF6E: +case 0xC16F: +case 0xC36F: +case 0xC56F: +case 0xC76F: +case 0xC96F: +case 0xCB6F: +case 0xCD6F: +case 0xCF6F: + +// ANDDa +case 0xC168: +{ + u32 adr; + u32 res; + pointer src; + src = (u16)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, res) + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0xC370: +case 0xC570: +case 0xC770: +case 0xC970: +case 0xCB70: +case 0xCD70: +case 0xCF70: +case 0xC171: +case 0xC371: +case 0xC571: +case 0xC771: +case 0xC971: +case 0xCB71: +case 0xCD71: +case 0xCF71: +case 0xC172: +case 0xC372: +case 0xC572: +case 0xC772: +case 0xC972: +case 0xCB72: +case 0xCD72: +case 0xCF72: +case 0xC173: +case 0xC373: +case 0xC573: +case 0xC773: +case 0xC973: +case 0xCB73: +case 0xCD73: +case 0xCF73: +case 0xC174: +case 0xC374: +case 0xC574: +case 0xC774: +case 0xC974: +case 0xCB74: +case 0xCD74: +case 0xCF74: +case 0xC175: +case 0xC375: +case 0xC575: +case 0xC775: +case 0xC975: +case 0xCB75: +case 0xCD75: +case 0xCF75: +case 0xC176: +case 0xC376: +case 0xC576: +case 0xC776: +case 0xC976: +case 0xCB76: +case 0xCD76: +case 0xCF76: +case 0xC177: +case 0xC377: +case 0xC577: +case 0xC777: +case 0xC977: +case 0xCB77: +case 0xCD77: +case 0xCF77: + +// ANDDa +case 0xC170: +{ + u32 adr; + u32 res; + pointer src; + src = (u16)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, res) + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(18) +case 0xC378: +case 0xC578: +case 0xC778: +case 0xC978: +case 0xCB78: +case 0xCD78: +case 0xCF78: + +// ANDDa +case 0xC178: +{ + u32 adr; + u32 res; + pointer src; + src = (u16)CPU->D[(Opcode >> 9) & 7]; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, res) + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0xC379: +case 0xC579: +case 0xC779: +case 0xC979: +case 0xCB79: +case 0xCD79: +case 0xCF79: + +// ANDDa +case 0xC179: +{ + u32 adr; + u32 res; + pointer src; + src = (u16)CPU->D[(Opcode >> 9) & 7]; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_WORD_F(adr, res) + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(20) +case 0xC35F: +case 0xC55F: +case 0xC75F: +case 0xC95F: +case 0xCB5F: +case 0xCD5F: +case 0xCF5F: + +// ANDDa +case 0xC15F: +{ + u32 adr; + u32 res; + pointer src; + src = (u16)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_WORD_F(adr, res) + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0xC367: +case 0xC567: +case 0xC767: +case 0xC967: +case 0xCB67: +case 0xCD67: +case 0xCF67: + +// ANDDa +case 0xC167: +{ + u32 adr; + u32 res; + pointer src; + src = (u16)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_WORD_F(adr, res) + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 8; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(14) +case 0xC390: +case 0xC590: +case 0xC790: +case 0xC990: +case 0xCB90: +case 0xCD90: +case 0xCF90: +case 0xC191: +case 0xC391: +case 0xC591: +case 0xC791: +case 0xC991: +case 0xCB91: +case 0xCD91: +case 0xCF91: +case 0xC192: +case 0xC392: +case 0xC592: +case 0xC792: +case 0xC992: +case 0xCB92: +case 0xCD92: +case 0xCF92: +case 0xC193: +case 0xC393: +case 0xC593: +case 0xC793: +case 0xC993: +case 0xCB93: +case 0xCD93: +case 0xCF93: +case 0xC194: +case 0xC394: +case 0xC594: +case 0xC794: +case 0xC994: +case 0xCB94: +case 0xCD94: +case 0xCF94: +case 0xC195: +case 0xC395: +case 0xC595: +case 0xC795: +case 0xC995: +case 0xCB95: +case 0xCD95: +case 0xCF95: +case 0xC196: +case 0xC396: +case 0xC596: +case 0xC796: +case 0xC996: +case 0xCB96: +case 0xCD96: +case 0xCF96: +case 0xC197: +case 0xC397: +case 0xC597: +case 0xC797: +case 0xC997: +case 0xCB97: +case 0xCD97: +case 0xCF97: + +// ANDDa +case 0xC190: +{ + u32 adr; + u32 res; + pointer src; + src = (u32)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_LONG_F(adr, res) + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(20) +case 0xC398: +case 0xC598: +case 0xC798: +case 0xC998: +case 0xCB98: +case 0xCD98: +case 0xCF98: +case 0xC199: +case 0xC399: +case 0xC599: +case 0xC799: +case 0xC999: +case 0xCB99: +case 0xCD99: +case 0xCF99: +case 0xC19A: +case 0xC39A: +case 0xC59A: +case 0xC79A: +case 0xC99A: +case 0xCB9A: +case 0xCD9A: +case 0xCF9A: +case 0xC19B: +case 0xC39B: +case 0xC59B: +case 0xC79B: +case 0xC99B: +case 0xCB9B: +case 0xCD9B: +case 0xCF9B: +case 0xC19C: +case 0xC39C: +case 0xC59C: +case 0xC79C: +case 0xC99C: +case 0xCB9C: +case 0xCD9C: +case 0xCF9C: +case 0xC19D: +case 0xC39D: +case 0xC59D: +case 0xC79D: +case 0xC99D: +case 0xCB9D: +case 0xCD9D: +case 0xCF9D: +case 0xC19E: +case 0xC39E: +case 0xC59E: +case 0xC79E: +case 0xC99E: +case 0xCB9E: +case 0xCD9E: +case 0xCF9E: + +// ANDDa +case 0xC198: +{ + u32 adr; + u32 res; + pointer src; + src = (u32)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 4; + PRE_IO + READ_LONG_F(adr, res) + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(20) +case 0xC3A0: +case 0xC5A0: +case 0xC7A0: +case 0xC9A0: +case 0xCBA0: +case 0xCDA0: +case 0xCFA0: +case 0xC1A1: +case 0xC3A1: +case 0xC5A1: +case 0xC7A1: +case 0xC9A1: +case 0xCBA1: +case 0xCDA1: +case 0xCFA1: +case 0xC1A2: +case 0xC3A2: +case 0xC5A2: +case 0xC7A2: +case 0xC9A2: +case 0xCBA2: +case 0xCDA2: +case 0xCFA2: +case 0xC1A3: +case 0xC3A3: +case 0xC5A3: +case 0xC7A3: +case 0xC9A3: +case 0xCBA3: +case 0xCDA3: +case 0xCFA3: +case 0xC1A4: +case 0xC3A4: +case 0xC5A4: +case 0xC7A4: +case 0xC9A4: +case 0xCBA4: +case 0xCDA4: +case 0xCFA4: +case 0xC1A5: +case 0xC3A5: +case 0xC5A5: +case 0xC7A5: +case 0xC9A5: +case 0xCBA5: +case 0xCDA5: +case 0xCFA5: +case 0xC1A6: +case 0xC3A6: +case 0xC5A6: +case 0xC7A6: +case 0xC9A6: +case 0xCBA6: +case 0xCDA6: +case 0xCFA6: + +// ANDDa +case 0xC1A0: +{ + u32 adr; + u32 res; + pointer src; + src = (u32)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7] - 4; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_LONG_F(adr, res) + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(22) +case 0xC3A8: +case 0xC5A8: +case 0xC7A8: +case 0xC9A8: +case 0xCBA8: +case 0xCDA8: +case 0xCFA8: +case 0xC1A9: +case 0xC3A9: +case 0xC5A9: +case 0xC7A9: +case 0xC9A9: +case 0xCBA9: +case 0xCDA9: +case 0xCFA9: +case 0xC1AA: +case 0xC3AA: +case 0xC5AA: +case 0xC7AA: +case 0xC9AA: +case 0xCBAA: +case 0xCDAA: +case 0xCFAA: +case 0xC1AB: +case 0xC3AB: +case 0xC5AB: +case 0xC7AB: +case 0xC9AB: +case 0xCBAB: +case 0xCDAB: +case 0xCFAB: +case 0xC1AC: +case 0xC3AC: +case 0xC5AC: +case 0xC7AC: +case 0xC9AC: +case 0xCBAC: +case 0xCDAC: +case 0xCFAC: +case 0xC1AD: +case 0xC3AD: +case 0xC5AD: +case 0xC7AD: +case 0xC9AD: +case 0xCBAD: +case 0xCDAD: +case 0xCFAD: +case 0xC1AE: +case 0xC3AE: +case 0xC5AE: +case 0xC7AE: +case 0xC9AE: +case 0xCBAE: +case 0xCDAE: +case 0xCFAE: +case 0xC1AF: +case 0xC3AF: +case 0xC5AF: +case 0xC7AF: +case 0xC9AF: +case 0xCBAF: +case 0xCDAF: +case 0xCFAF: + +// ANDDa +case 0xC1A8: +{ + u32 adr; + u32 res; + pointer src; + src = (u32)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, res) + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(24) +case 0xC3B0: +case 0xC5B0: +case 0xC7B0: +case 0xC9B0: +case 0xCBB0: +case 0xCDB0: +case 0xCFB0: +case 0xC1B1: +case 0xC3B1: +case 0xC5B1: +case 0xC7B1: +case 0xC9B1: +case 0xCBB1: +case 0xCDB1: +case 0xCFB1: +case 0xC1B2: +case 0xC3B2: +case 0xC5B2: +case 0xC7B2: +case 0xC9B2: +case 0xCBB2: +case 0xCDB2: +case 0xCFB2: +case 0xC1B3: +case 0xC3B3: +case 0xC5B3: +case 0xC7B3: +case 0xC9B3: +case 0xCBB3: +case 0xCDB3: +case 0xCFB3: +case 0xC1B4: +case 0xC3B4: +case 0xC5B4: +case 0xC7B4: +case 0xC9B4: +case 0xCBB4: +case 0xCDB4: +case 0xCFB4: +case 0xC1B5: +case 0xC3B5: +case 0xC5B5: +case 0xC7B5: +case 0xC9B5: +case 0xCBB5: +case 0xCDB5: +case 0xCFB5: +case 0xC1B6: +case 0xC3B6: +case 0xC5B6: +case 0xC7B6: +case 0xC9B6: +case 0xCBB6: +case 0xCDB6: +case 0xCFB6: +case 0xC1B7: +case 0xC3B7: +case 0xC5B7: +case 0xC7B7: +case 0xC9B7: +case 0xCBB7: +case 0xCDB7: +case 0xCFB7: + +// ANDDa +case 0xC1B0: +{ + u32 adr; + u32 res; + pointer src; + src = (u32)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_LONG_F(adr, res) + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(26) +case 0xC3B8: +case 0xC5B8: +case 0xC7B8: +case 0xC9B8: +case 0xCBB8: +case 0xCDB8: +case 0xCFB8: + +// ANDDa +case 0xC1B8: +{ + u32 adr; + u32 res; + pointer src; + src = (u32)CPU->D[(Opcode >> 9) & 7]; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, res) + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(24) +case 0xC3B9: +case 0xC5B9: +case 0xC7B9: +case 0xC9B9: +case 0xCBB9: +case 0xCDB9: +case 0xCFB9: + +// ANDDa +case 0xC1B9: +{ + u32 adr; + u32 res; + pointer src; + src = (u32)CPU->D[(Opcode >> 9) & 7]; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_LONG_F(adr, res) + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(28) +case 0xC39F: +case 0xC59F: +case 0xC79F: +case 0xC99F: +case 0xCB9F: +case 0xCD9F: +case 0xCF9F: + +// ANDDa +case 0xC19F: +{ + u32 adr; + u32 res; + pointer src; + src = (u32)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[7]; + CPU->A[7] += 4; + PRE_IO + READ_LONG_F(adr, res) + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(20) +case 0xC3A7: +case 0xC5A7: +case 0xC7A7: +case 0xC9A7: +case 0xCBA7: +case 0xCDA7: +case 0xCFA7: + +// ANDDa +case 0xC1A7: +{ + u32 adr; + u32 res; + pointer src; + src = (u32)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + PRE_IO + READ_LONG_F(adr, res) + res &= src; + CPU->flag_C = 0; + CPU->flag_V = 0; + CPU->flag_notZ = res; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(22) +case 0xC300: +case 0xC500: +case 0xC700: +case 0xC900: +case 0xCB00: +case 0xCD00: +case 0xCF00: +case 0xC101: +case 0xC301: +case 0xC501: +case 0xC701: +case 0xC901: +case 0xCB01: +case 0xCD01: +case 0xCF01: +case 0xC102: +case 0xC302: +case 0xC502: +case 0xC702: +case 0xC902: +case 0xCB02: +case 0xCD02: +case 0xCF02: +case 0xC103: +case 0xC303: +case 0xC503: +case 0xC703: +case 0xC903: +case 0xCB03: +case 0xCD03: +case 0xCF03: +case 0xC104: +case 0xC304: +case 0xC504: +case 0xC704: +case 0xC904: +case 0xCB04: +case 0xCD04: +case 0xCF04: +case 0xC105: +case 0xC305: +case 0xC505: +case 0xC705: +case 0xC905: +case 0xCB05: +case 0xCD05: +case 0xCF05: +case 0xC106: +case 0xC306: +case 0xC506: +case 0xC706: +case 0xC906: +case 0xCB06: +case 0xCD06: +case 0xCF06: +case 0xC107: +case 0xC307: +case 0xC507: +case 0xC707: +case 0xC907: +case 0xCB07: +case 0xCD07: +case 0xCF07: + +// ABCD +case 0xC100: +{ + u32 res; + pointer dst; + pointer src; + src = (u8)CPU->D[(Opcode >> 0) & 7]; + dst = (u8)CPU->D[(Opcode >> 9) & 7]; + res = (dst & 0xF) + (src & 0xF) + ((CPU->flag_X >> C68K_SR_X_SFT) & 1); + if (res > 9) res += 6; + res += (dst & 0xF0) + (src & 0xF0); + if (res > 0x99) + { + res -= 0xA0; + CPU->flag_X = CPU->flag_C = C68K_SR_C; + } + else CPU->flag_X = CPU->flag_C = 0; + CPU->flag_notZ |= res & 0xFF; + CPU->flag_N = res; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; +} +RET(6) +case 0xC308: +case 0xC508: +case 0xC708: +case 0xC908: +case 0xCB08: +case 0xCD08: +case 0xC109: +case 0xC309: +case 0xC509: +case 0xC709: +case 0xC909: +case 0xCB09: +case 0xCD09: +case 0xC10A: +case 0xC30A: +case 0xC50A: +case 0xC70A: +case 0xC90A: +case 0xCB0A: +case 0xCD0A: +case 0xC10B: +case 0xC30B: +case 0xC50B: +case 0xC70B: +case 0xC90B: +case 0xCB0B: +case 0xCD0B: +case 0xC10C: +case 0xC30C: +case 0xC50C: +case 0xC70C: +case 0xC90C: +case 0xCB0C: +case 0xCD0C: +case 0xC10D: +case 0xC30D: +case 0xC50D: +case 0xC70D: +case 0xC90D: +case 0xCB0D: +case 0xCD0D: +case 0xC10E: +case 0xC30E: +case 0xC50E: +case 0xC70E: +case 0xC90E: +case 0xCB0E: +case 0xCD0E: + +// ABCDM +case 0xC108: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_BYTE_F(adr, src) + adr = CPU->A[(Opcode >> 9) & 7] - 1; + CPU->A[(Opcode >> 9) & 7] = adr; + READ_BYTE_F(adr, dst) + res = (dst & 0xF) + (src & 0xF) + ((CPU->flag_X >> C68K_SR_X_SFT) & 1); + if (res > 9) res += 6; + res += (dst & 0xF0) + (src & 0xF0); + if (res > 0x99) + { + res -= 0xA0; + CPU->flag_X = CPU->flag_C = C68K_SR_C; + } + else CPU->flag_X = CPU->flag_C = 0; + CPU->flag_notZ |= res & 0xFF; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) +case 0xC30F: +case 0xC50F: +case 0xC70F: +case 0xC90F: +case 0xCB0F: +case 0xCD0F: + +// ABCD7M +case 0xC10F: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_BYTE_F(adr, src) + adr = CPU->A[(Opcode >> 9) & 7] - 1; + CPU->A[(Opcode >> 9) & 7] = adr; + READ_BYTE_F(adr, dst) + res = (dst & 0xF) + (src & 0xF) + ((CPU->flag_X >> C68K_SR_X_SFT) & 1); + if (res > 9) res += 6; + res += (dst & 0xF0) + (src & 0xF0); + if (res > 0x99) + { + res -= 0xA0; + CPU->flag_X = CPU->flag_C = C68K_SR_C; + } + else CPU->flag_X = CPU->flag_C = 0; + CPU->flag_notZ |= res & 0xFF; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) +case 0xCF09: +case 0xCF0A: +case 0xCF0B: +case 0xCF0C: +case 0xCF0D: +case 0xCF0E: + +// ABCDM7 +case 0xCF08: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_BYTE_F(adr, src) + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + READ_BYTE_F(adr, dst) + res = (dst & 0xF) + (src & 0xF) + ((CPU->flag_X >> C68K_SR_X_SFT) & 1); + if (res > 9) res += 6; + res += (dst & 0xF0) + (src & 0xF0); + if (res > 0x99) + { + res -= 0xA0; + CPU->flag_X = CPU->flag_C = C68K_SR_C; + } + else CPU->flag_X = CPU->flag_C = 0; + CPU->flag_notZ |= res & 0xFF; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) + +// ABCD7M7 +case 0xCF0F: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_BYTE_F(adr, src) + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + READ_BYTE_F(adr, dst) + res = (dst & 0xF) + (src & 0xF) + ((CPU->flag_X >> C68K_SR_X_SFT) & 1); + if (res > 9) res += 6; + res += (dst & 0xF0) + (src & 0xF0); + if (res > 0x99) + { + res -= 0xA0; + CPU->flag_X = CPU->flag_C = C68K_SR_C; + } + else CPU->flag_X = CPU->flag_C = 0; + CPU->flag_notZ |= res & 0xFF; + CPU->flag_N = res; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) +case 0xC2C0: +case 0xC4C0: +case 0xC6C0: +case 0xC8C0: +case 0xCAC0: +case 0xCCC0: +case 0xCEC0: +case 0xC0C1: +case 0xC2C1: +case 0xC4C1: +case 0xC6C1: +case 0xC8C1: +case 0xCAC1: +case 0xCCC1: +case 0xCEC1: +case 0xC0C2: +case 0xC2C2: +case 0xC4C2: +case 0xC6C2: +case 0xC8C2: +case 0xCAC2: +case 0xCCC2: +case 0xCEC2: +case 0xC0C3: +case 0xC2C3: +case 0xC4C3: +case 0xC6C3: +case 0xC8C3: +case 0xCAC3: +case 0xCCC3: +case 0xCEC3: +case 0xC0C4: +case 0xC2C4: +case 0xC4C4: +case 0xC6C4: +case 0xC8C4: +case 0xCAC4: +case 0xCCC4: +case 0xCEC4: +case 0xC0C5: +case 0xC2C5: +case 0xC4C5: +case 0xC6C5: +case 0xC8C5: +case 0xCAC5: +case 0xCCC5: +case 0xCEC5: +case 0xC0C6: +case 0xC2C6: +case 0xC4C6: +case 0xC6C6: +case 0xC8C6: +case 0xCAC6: +case 0xCCC6: +case 0xCEC6: +case 0xC0C7: +case 0xC2C7: +case 0xC4C7: +case 0xC6C7: +case 0xC8C7: +case 0xCAC7: +case 0xCCC7: +case 0xCEC7: + +// MULU +case 0xC0C0: +{ + u32 res; + pointer src; + src = (u16)CPU->D[(Opcode >> 0) & 7]; + res = (u16)CPU->D[(Opcode >> 9) & 7]; + res *= src; + CPU->flag_N = res >> 24; + CPU->flag_notZ = res; + CPU->flag_V = CPU->flag_C = 0; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; +} +RET(50) +case 0xC2D0: +case 0xC4D0: +case 0xC6D0: +case 0xC8D0: +case 0xCAD0: +case 0xCCD0: +case 0xCED0: +case 0xC0D1: +case 0xC2D1: +case 0xC4D1: +case 0xC6D1: +case 0xC8D1: +case 0xCAD1: +case 0xCCD1: +case 0xCED1: +case 0xC0D2: +case 0xC2D2: +case 0xC4D2: +case 0xC6D2: +case 0xC8D2: +case 0xCAD2: +case 0xCCD2: +case 0xCED2: +case 0xC0D3: +case 0xC2D3: +case 0xC4D3: +case 0xC6D3: +case 0xC8D3: +case 0xCAD3: +case 0xCCD3: +case 0xCED3: +case 0xC0D4: +case 0xC2D4: +case 0xC4D4: +case 0xC6D4: +case 0xC8D4: +case 0xCAD4: +case 0xCCD4: +case 0xCED4: +case 0xC0D5: +case 0xC2D5: +case 0xC4D5: +case 0xC6D5: +case 0xC8D5: +case 0xCAD5: +case 0xCCD5: +case 0xCED5: +case 0xC0D6: +case 0xC2D6: +case 0xC4D6: +case 0xC6D6: +case 0xC8D6: +case 0xCAD6: +case 0xCCD6: +case 0xCED6: +case 0xC0D7: +case 0xC2D7: +case 0xC4D7: +case 0xC6D7: +case 0xC8D7: +case 0xCAD7: +case 0xCCD7: +case 0xCED7: + +// MULU +case 0xC0D0: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_WORD_F(adr, src) + res = (u16)CPU->D[(Opcode >> 9) & 7]; + res *= src; + CPU->flag_N = res >> 24; + CPU->flag_notZ = res; + CPU->flag_V = CPU->flag_C = 0; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(54) +case 0xC2D8: +case 0xC4D8: +case 0xC6D8: +case 0xC8D8: +case 0xCAD8: +case 0xCCD8: +case 0xCED8: +case 0xC0D9: +case 0xC2D9: +case 0xC4D9: +case 0xC6D9: +case 0xC8D9: +case 0xCAD9: +case 0xCCD9: +case 0xCED9: +case 0xC0DA: +case 0xC2DA: +case 0xC4DA: +case 0xC6DA: +case 0xC8DA: +case 0xCADA: +case 0xCCDA: +case 0xCEDA: +case 0xC0DB: +case 0xC2DB: +case 0xC4DB: +case 0xC6DB: +case 0xC8DB: +case 0xCADB: +case 0xCCDB: +case 0xCEDB: +case 0xC0DC: +case 0xC2DC: +case 0xC4DC: +case 0xC6DC: +case 0xC8DC: +case 0xCADC: +case 0xCCDC: +case 0xCEDC: +case 0xC0DD: +case 0xC2DD: +case 0xC4DD: +case 0xC6DD: +case 0xC8DD: +case 0xCADD: +case 0xCCDD: +case 0xCEDD: +case 0xC0DE: +case 0xC2DE: +case 0xC4DE: +case 0xC6DE: +case 0xC8DE: +case 0xCADE: +case 0xCCDE: +case 0xCEDE: + +// MULU +case 0xC0D8: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 2; + PRE_IO + READ_WORD_F(adr, src) + res = (u16)CPU->D[(Opcode >> 9) & 7]; + res *= src; + CPU->flag_N = res >> 24; + CPU->flag_notZ = res; + CPU->flag_V = CPU->flag_C = 0; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(54) +case 0xC2E0: +case 0xC4E0: +case 0xC6E0: +case 0xC8E0: +case 0xCAE0: +case 0xCCE0: +case 0xCEE0: +case 0xC0E1: +case 0xC2E1: +case 0xC4E1: +case 0xC6E1: +case 0xC8E1: +case 0xCAE1: +case 0xCCE1: +case 0xCEE1: +case 0xC0E2: +case 0xC2E2: +case 0xC4E2: +case 0xC6E2: +case 0xC8E2: +case 0xCAE2: +case 0xCCE2: +case 0xCEE2: +case 0xC0E3: +case 0xC2E3: +case 0xC4E3: +case 0xC6E3: +case 0xC8E3: +case 0xCAE3: +case 0xCCE3: +case 0xCEE3: +case 0xC0E4: +case 0xC2E4: +case 0xC4E4: +case 0xC6E4: +case 0xC8E4: +case 0xCAE4: +case 0xCCE4: +case 0xCEE4: +case 0xC0E5: +case 0xC2E5: +case 0xC4E5: +case 0xC6E5: +case 0xC8E5: +case 0xCAE5: +case 0xCCE5: +case 0xCEE5: +case 0xC0E6: +case 0xC2E6: +case 0xC4E6: +case 0xC6E6: +case 0xC8E6: +case 0xCAE6: +case 0xCCE6: +case 0xCEE6: + +// MULU +case 0xC0E0: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 2; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_WORD_F(adr, src) + res = (u16)CPU->D[(Opcode >> 9) & 7]; + res *= src; + CPU->flag_N = res >> 24; + CPU->flag_notZ = res; + CPU->flag_V = CPU->flag_C = 0; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(56) +case 0xC2E8: +case 0xC4E8: +case 0xC6E8: +case 0xC8E8: +case 0xCAE8: +case 0xCCE8: +case 0xCEE8: +case 0xC0E9: +case 0xC2E9: +case 0xC4E9: +case 0xC6E9: +case 0xC8E9: +case 0xCAE9: +case 0xCCE9: +case 0xCEE9: +case 0xC0EA: +case 0xC2EA: +case 0xC4EA: +case 0xC6EA: +case 0xC8EA: +case 0xCAEA: +case 0xCCEA: +case 0xCEEA: +case 0xC0EB: +case 0xC2EB: +case 0xC4EB: +case 0xC6EB: +case 0xC8EB: +case 0xCAEB: +case 0xCCEB: +case 0xCEEB: +case 0xC0EC: +case 0xC2EC: +case 0xC4EC: +case 0xC6EC: +case 0xC8EC: +case 0xCAEC: +case 0xCCEC: +case 0xCEEC: +case 0xC0ED: +case 0xC2ED: +case 0xC4ED: +case 0xC6ED: +case 0xC8ED: +case 0xCAED: +case 0xCCED: +case 0xCEED: +case 0xC0EE: +case 0xC2EE: +case 0xC4EE: +case 0xC6EE: +case 0xC8EE: +case 0xCAEE: +case 0xCCEE: +case 0xCEEE: +case 0xC0EF: +case 0xC2EF: +case 0xC4EF: +case 0xC6EF: +case 0xC8EF: +case 0xCAEF: +case 0xCCEF: +case 0xCEEF: + +// MULU +case 0xC0E8: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, src) + res = (u16)CPU->D[(Opcode >> 9) & 7]; + res *= src; + CPU->flag_N = res >> 24; + CPU->flag_notZ = res; + CPU->flag_V = CPU->flag_C = 0; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(58) +case 0xC2F0: +case 0xC4F0: +case 0xC6F0: +case 0xC8F0: +case 0xCAF0: +case 0xCCF0: +case 0xCEF0: +case 0xC0F1: +case 0xC2F1: +case 0xC4F1: +case 0xC6F1: +case 0xC8F1: +case 0xCAF1: +case 0xCCF1: +case 0xCEF1: +case 0xC0F2: +case 0xC2F2: +case 0xC4F2: +case 0xC6F2: +case 0xC8F2: +case 0xCAF2: +case 0xCCF2: +case 0xCEF2: +case 0xC0F3: +case 0xC2F3: +case 0xC4F3: +case 0xC6F3: +case 0xC8F3: +case 0xCAF3: +case 0xCCF3: +case 0xCEF3: +case 0xC0F4: +case 0xC2F4: +case 0xC4F4: +case 0xC6F4: +case 0xC8F4: +case 0xCAF4: +case 0xCCF4: +case 0xCEF4: +case 0xC0F5: +case 0xC2F5: +case 0xC4F5: +case 0xC6F5: +case 0xC8F5: +case 0xCAF5: +case 0xCCF5: +case 0xCEF5: +case 0xC0F6: +case 0xC2F6: +case 0xC4F6: +case 0xC6F6: +case 0xC8F6: +case 0xCAF6: +case 0xCCF6: +case 0xCEF6: +case 0xC0F7: +case 0xC2F7: +case 0xC4F7: +case 0xC6F7: +case 0xC8F7: +case 0xCAF7: +case 0xCCF7: +case 0xCEF7: + +// MULU +case 0xC0F0: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, src) + res = (u16)CPU->D[(Opcode >> 9) & 7]; + res *= src; + CPU->flag_N = res >> 24; + CPU->flag_notZ = res; + CPU->flag_V = CPU->flag_C = 0; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(60) +case 0xC2F8: +case 0xC4F8: +case 0xC6F8: +case 0xC8F8: +case 0xCAF8: +case 0xCCF8: +case 0xCEF8: + +// MULU +case 0xC0F8: +{ + u32 adr; + u32 res; + pointer src; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, src) + res = (u16)CPU->D[(Opcode >> 9) & 7]; + res *= src; + CPU->flag_N = res >> 24; + CPU->flag_notZ = res; + CPU->flag_V = CPU->flag_C = 0; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(58) +case 0xC2F9: +case 0xC4F9: +case 0xC6F9: +case 0xC8F9: +case 0xCAF9: +case 0xCCF9: +case 0xCEF9: + +// MULU +case 0xC0F9: +{ + u32 adr; + u32 res; + pointer src; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_WORD_F(adr, src) + res = (u16)CPU->D[(Opcode >> 9) & 7]; + res *= src; + CPU->flag_N = res >> 24; + CPU->flag_notZ = res; + CPU->flag_V = CPU->flag_C = 0; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(62) +case 0xC2FA: +case 0xC4FA: +case 0xC6FA: +case 0xC8FA: +case 0xCAFA: +case 0xCCFA: +case 0xCEFA: + +// MULU +case 0xC0FA: +{ + u32 adr; + u32 res; + pointer src; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, src) + res = (u16)CPU->D[(Opcode >> 9) & 7]; + res *= src; + CPU->flag_N = res >> 24; + CPU->flag_notZ = res; + CPU->flag_V = CPU->flag_C = 0; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(58) +case 0xC2FB: +case 0xC4FB: +case 0xC6FB: +case 0xC8FB: +case 0xCAFB: +case 0xCCFB: +case 0xCEFB: + +// MULU +case 0xC0FB: +{ + u32 adr; + u32 res; + pointer src; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, src) + res = (u16)CPU->D[(Opcode >> 9) & 7]; + res *= src; + CPU->flag_N = res >> 24; + CPU->flag_notZ = res; + CPU->flag_V = CPU->flag_C = 0; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(60) +case 0xC2FC: +case 0xC4FC: +case 0xC6FC: +case 0xC8FC: +case 0xCAFC: +case 0xCCFC: +case 0xCEFC: + +// MULU +case 0xC0FC: +{ + u32 res; + pointer src; + src = FETCH_WORD; + PC += 2; + res = (u16)CPU->D[(Opcode >> 9) & 7]; + res *= src; + CPU->flag_N = res >> 24; + CPU->flag_notZ = res; + CPU->flag_V = CPU->flag_C = 0; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; +} +RET(54) +case 0xC2DF: +case 0xC4DF: +case 0xC6DF: +case 0xC8DF: +case 0xCADF: +case 0xCCDF: +case 0xCEDF: + +// MULU +case 0xC0DF: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_WORD_F(adr, src) + res = (u16)CPU->D[(Opcode >> 9) & 7]; + res *= src; + CPU->flag_N = res >> 24; + CPU->flag_notZ = res; + CPU->flag_V = CPU->flag_C = 0; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(54) +case 0xC2E7: +case 0xC4E7: +case 0xC6E7: +case 0xC8E7: +case 0xCAE7: +case 0xCCE7: +case 0xCEE7: + +// MULU +case 0xC0E7: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_WORD_F(adr, src) + res = (u16)CPU->D[(Opcode >> 9) & 7]; + res *= src; + CPU->flag_N = res >> 24; + CPU->flag_notZ = res; + CPU->flag_V = CPU->flag_C = 0; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(56) +case 0xC3C0: +case 0xC5C0: +case 0xC7C0: +case 0xC9C0: +case 0xCBC0: +case 0xCDC0: +case 0xCFC0: +case 0xC1C1: +case 0xC3C1: +case 0xC5C1: +case 0xC7C1: +case 0xC9C1: +case 0xCBC1: +case 0xCDC1: +case 0xCFC1: +case 0xC1C2: +case 0xC3C2: +case 0xC5C2: +case 0xC7C2: +case 0xC9C2: +case 0xCBC2: +case 0xCDC2: +case 0xCFC2: +case 0xC1C3: +case 0xC3C3: +case 0xC5C3: +case 0xC7C3: +case 0xC9C3: +case 0xCBC3: +case 0xCDC3: +case 0xCFC3: +case 0xC1C4: +case 0xC3C4: +case 0xC5C4: +case 0xC7C4: +case 0xC9C4: +case 0xCBC4: +case 0xCDC4: +case 0xCFC4: +case 0xC1C5: +case 0xC3C5: +case 0xC5C5: +case 0xC7C5: +case 0xC9C5: +case 0xCBC5: +case 0xCDC5: +case 0xCFC5: +case 0xC1C6: +case 0xC3C6: +case 0xC5C6: +case 0xC7C6: +case 0xC9C6: +case 0xCBC6: +case 0xCDC6: +case 0xCFC6: +case 0xC1C7: +case 0xC3C7: +case 0xC5C7: +case 0xC7C7: +case 0xC9C7: +case 0xCBC7: +case 0xCDC7: +case 0xCFC7: + +// MULS +case 0xC1C0: +{ + u32 res; + pointer src; + src = (s32)(s16)CPU->D[(Opcode >> 0) & 7]; + res = (s32)(s16)CPU->D[(Opcode >> 9) & 7]; + res *= (s32)src; + CPU->flag_N = res >> 24; + CPU->flag_notZ = res; + CPU->flag_V = CPU->flag_C = 0; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; +} +RET(50) +case 0xC3D0: +case 0xC5D0: +case 0xC7D0: +case 0xC9D0: +case 0xCBD0: +case 0xCDD0: +case 0xCFD0: +case 0xC1D1: +case 0xC3D1: +case 0xC5D1: +case 0xC7D1: +case 0xC9D1: +case 0xCBD1: +case 0xCDD1: +case 0xCFD1: +case 0xC1D2: +case 0xC3D2: +case 0xC5D2: +case 0xC7D2: +case 0xC9D2: +case 0xCBD2: +case 0xCDD2: +case 0xCFD2: +case 0xC1D3: +case 0xC3D3: +case 0xC5D3: +case 0xC7D3: +case 0xC9D3: +case 0xCBD3: +case 0xCDD3: +case 0xCFD3: +case 0xC1D4: +case 0xC3D4: +case 0xC5D4: +case 0xC7D4: +case 0xC9D4: +case 0xCBD4: +case 0xCDD4: +case 0xCFD4: +case 0xC1D5: +case 0xC3D5: +case 0xC5D5: +case 0xC7D5: +case 0xC9D5: +case 0xCBD5: +case 0xCDD5: +case 0xCFD5: +case 0xC1D6: +case 0xC3D6: +case 0xC5D6: +case 0xC7D6: +case 0xC9D6: +case 0xCBD6: +case 0xCDD6: +case 0xCFD6: +case 0xC1D7: +case 0xC3D7: +case 0xC5D7: +case 0xC7D7: +case 0xC9D7: +case 0xCBD7: +case 0xCDD7: +case 0xCFD7: + +// MULS +case 0xC1D0: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READSX_WORD_F(adr, src) + res = (s32)(s16)CPU->D[(Opcode >> 9) & 7]; + res *= (s32)src; + CPU->flag_N = res >> 24; + CPU->flag_notZ = res; + CPU->flag_V = CPU->flag_C = 0; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(54) +case 0xC3D8: +case 0xC5D8: +case 0xC7D8: +case 0xC9D8: +case 0xCBD8: +case 0xCDD8: +case 0xCFD8: +case 0xC1D9: +case 0xC3D9: +case 0xC5D9: +case 0xC7D9: +case 0xC9D9: +case 0xCBD9: +case 0xCDD9: +case 0xCFD9: +case 0xC1DA: +case 0xC3DA: +case 0xC5DA: +case 0xC7DA: +case 0xC9DA: +case 0xCBDA: +case 0xCDDA: +case 0xCFDA: +case 0xC1DB: +case 0xC3DB: +case 0xC5DB: +case 0xC7DB: +case 0xC9DB: +case 0xCBDB: +case 0xCDDB: +case 0xCFDB: +case 0xC1DC: +case 0xC3DC: +case 0xC5DC: +case 0xC7DC: +case 0xC9DC: +case 0xCBDC: +case 0xCDDC: +case 0xCFDC: +case 0xC1DD: +case 0xC3DD: +case 0xC5DD: +case 0xC7DD: +case 0xC9DD: +case 0xCBDD: +case 0xCDDD: +case 0xCFDD: +case 0xC1DE: +case 0xC3DE: +case 0xC5DE: +case 0xC7DE: +case 0xC9DE: +case 0xCBDE: +case 0xCDDE: +case 0xCFDE: + +// MULS +case 0xC1D8: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 2; + PRE_IO + READSX_WORD_F(adr, src) + res = (s32)(s16)CPU->D[(Opcode >> 9) & 7]; + res *= (s32)src; + CPU->flag_N = res >> 24; + CPU->flag_notZ = res; + CPU->flag_V = CPU->flag_C = 0; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(54) +case 0xC3E0: +case 0xC5E0: +case 0xC7E0: +case 0xC9E0: +case 0xCBE0: +case 0xCDE0: +case 0xCFE0: +case 0xC1E1: +case 0xC3E1: +case 0xC5E1: +case 0xC7E1: +case 0xC9E1: +case 0xCBE1: +case 0xCDE1: +case 0xCFE1: +case 0xC1E2: +case 0xC3E2: +case 0xC5E2: +case 0xC7E2: +case 0xC9E2: +case 0xCBE2: +case 0xCDE2: +case 0xCFE2: +case 0xC1E3: +case 0xC3E3: +case 0xC5E3: +case 0xC7E3: +case 0xC9E3: +case 0xCBE3: +case 0xCDE3: +case 0xCFE3: +case 0xC1E4: +case 0xC3E4: +case 0xC5E4: +case 0xC7E4: +case 0xC9E4: +case 0xCBE4: +case 0xCDE4: +case 0xCFE4: +case 0xC1E5: +case 0xC3E5: +case 0xC5E5: +case 0xC7E5: +case 0xC9E5: +case 0xCBE5: +case 0xCDE5: +case 0xCFE5: +case 0xC1E6: +case 0xC3E6: +case 0xC5E6: +case 0xC7E6: +case 0xC9E6: +case 0xCBE6: +case 0xCDE6: +case 0xCFE6: + +// MULS +case 0xC1E0: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 2; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READSX_WORD_F(adr, src) + res = (s32)(s16)CPU->D[(Opcode >> 9) & 7]; + res *= (s32)src; + CPU->flag_N = res >> 24; + CPU->flag_notZ = res; + CPU->flag_V = CPU->flag_C = 0; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(56) +case 0xC3E8: +case 0xC5E8: +case 0xC7E8: +case 0xC9E8: +case 0xCBE8: +case 0xCDE8: +case 0xCFE8: +case 0xC1E9: +case 0xC3E9: +case 0xC5E9: +case 0xC7E9: +case 0xC9E9: +case 0xCBE9: +case 0xCDE9: +case 0xCFE9: +case 0xC1EA: +case 0xC3EA: +case 0xC5EA: +case 0xC7EA: +case 0xC9EA: +case 0xCBEA: +case 0xCDEA: +case 0xCFEA: +case 0xC1EB: +case 0xC3EB: +case 0xC5EB: +case 0xC7EB: +case 0xC9EB: +case 0xCBEB: +case 0xCDEB: +case 0xCFEB: +case 0xC1EC: +case 0xC3EC: +case 0xC5EC: +case 0xC7EC: +case 0xC9EC: +case 0xCBEC: +case 0xCDEC: +case 0xCFEC: +case 0xC1ED: +case 0xC3ED: +case 0xC5ED: +case 0xC7ED: +case 0xC9ED: +case 0xCBED: +case 0xCDED: +case 0xCFED: +case 0xC1EE: +case 0xC3EE: +case 0xC5EE: +case 0xC7EE: +case 0xC9EE: +case 0xCBEE: +case 0xCDEE: +case 0xCFEE: +case 0xC1EF: +case 0xC3EF: +case 0xC5EF: +case 0xC7EF: +case 0xC9EF: +case 0xCBEF: +case 0xCDEF: +case 0xCFEF: + +// MULS +case 0xC1E8: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READSX_WORD_F(adr, src) + res = (s32)(s16)CPU->D[(Opcode >> 9) & 7]; + res *= (s32)src; + CPU->flag_N = res >> 24; + CPU->flag_notZ = res; + CPU->flag_V = CPU->flag_C = 0; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(58) +case 0xC3F0: +case 0xC5F0: +case 0xC7F0: +case 0xC9F0: +case 0xCBF0: +case 0xCDF0: +case 0xCFF0: +case 0xC1F1: +case 0xC3F1: +case 0xC5F1: +case 0xC7F1: +case 0xC9F1: +case 0xCBF1: +case 0xCDF1: +case 0xCFF1: +case 0xC1F2: +case 0xC3F2: +case 0xC5F2: +case 0xC7F2: +case 0xC9F2: +case 0xCBF2: +case 0xCDF2: +case 0xCFF2: +case 0xC1F3: +case 0xC3F3: +case 0xC5F3: +case 0xC7F3: +case 0xC9F3: +case 0xCBF3: +case 0xCDF3: +case 0xCFF3: +case 0xC1F4: +case 0xC3F4: +case 0xC5F4: +case 0xC7F4: +case 0xC9F4: +case 0xCBF4: +case 0xCDF4: +case 0xCFF4: +case 0xC1F5: +case 0xC3F5: +case 0xC5F5: +case 0xC7F5: +case 0xC9F5: +case 0xCBF5: +case 0xCDF5: +case 0xCFF5: +case 0xC1F6: +case 0xC3F6: +case 0xC5F6: +case 0xC7F6: +case 0xC9F6: +case 0xCBF6: +case 0xCDF6: +case 0xCFF6: +case 0xC1F7: +case 0xC3F7: +case 0xC5F7: +case 0xC7F7: +case 0xC9F7: +case 0xCBF7: +case 0xCDF7: +case 0xCFF7: + +// MULS +case 0xC1F0: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READSX_WORD_F(adr, src) + res = (s32)(s16)CPU->D[(Opcode >> 9) & 7]; + res *= (s32)src; + CPU->flag_N = res >> 24; + CPU->flag_notZ = res; + CPU->flag_V = CPU->flag_C = 0; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(60) +case 0xC3F8: +case 0xC5F8: +case 0xC7F8: +case 0xC9F8: +case 0xCBF8: +case 0xCDF8: +case 0xCFF8: + +// MULS +case 0xC1F8: +{ + u32 adr; + u32 res; + pointer src; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READSX_WORD_F(adr, src) + res = (s32)(s16)CPU->D[(Opcode >> 9) & 7]; + res *= (s32)src; + CPU->flag_N = res >> 24; + CPU->flag_notZ = res; + CPU->flag_V = CPU->flag_C = 0; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(58) +case 0xC3F9: +case 0xC5F9: +case 0xC7F9: +case 0xC9F9: +case 0xCBF9: +case 0xCDF9: +case 0xCFF9: + +// MULS +case 0xC1F9: +{ + u32 adr; + u32 res; + pointer src; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READSX_WORD_F(adr, src) + res = (s32)(s16)CPU->D[(Opcode >> 9) & 7]; + res *= (s32)src; + CPU->flag_N = res >> 24; + CPU->flag_notZ = res; + CPU->flag_V = CPU->flag_C = 0; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(62) +case 0xC3FA: +case 0xC5FA: +case 0xC7FA: +case 0xC9FA: +case 0xCBFA: +case 0xCDFA: +case 0xCFFA: + +// MULS +case 0xC1FA: +{ + u32 adr; + u32 res; + pointer src; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READSX_WORD_F(adr, src) + res = (s32)(s16)CPU->D[(Opcode >> 9) & 7]; + res *= (s32)src; + CPU->flag_N = res >> 24; + CPU->flag_notZ = res; + CPU->flag_V = CPU->flag_C = 0; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(58) +case 0xC3FB: +case 0xC5FB: +case 0xC7FB: +case 0xC9FB: +case 0xCBFB: +case 0xCDFB: +case 0xCFFB: + +// MULS +case 0xC1FB: +{ + u32 adr; + u32 res; + pointer src; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READSX_WORD_F(adr, src) + res = (s32)(s16)CPU->D[(Opcode >> 9) & 7]; + res *= (s32)src; + CPU->flag_N = res >> 24; + CPU->flag_notZ = res; + CPU->flag_V = CPU->flag_C = 0; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(60) +case 0xC3FC: +case 0xC5FC: +case 0xC7FC: +case 0xC9FC: +case 0xCBFC: +case 0xCDFC: +case 0xCFFC: + +// MULS +case 0xC1FC: +{ + u32 res; + pointer src; + src = (s32)(s16)FETCH_WORD; + PC += 2; + res = (s32)(s16)CPU->D[(Opcode >> 9) & 7]; + res *= (s32)src; + CPU->flag_N = res >> 24; + CPU->flag_notZ = res; + CPU->flag_V = CPU->flag_C = 0; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; +} +RET(54) +case 0xC3DF: +case 0xC5DF: +case 0xC7DF: +case 0xC9DF: +case 0xCBDF: +case 0xCDDF: +case 0xCFDF: + +// MULS +case 0xC1DF: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READSX_WORD_F(adr, src) + res = (s32)(s16)CPU->D[(Opcode >> 9) & 7]; + res *= (s32)src; + CPU->flag_N = res >> 24; + CPU->flag_notZ = res; + CPU->flag_V = CPU->flag_C = 0; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(54) +case 0xC3E7: +case 0xC5E7: +case 0xC7E7: +case 0xC9E7: +case 0xCBE7: +case 0xCDE7: +case 0xCFE7: + +// MULS +case 0xC1E7: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READSX_WORD_F(adr, src) + res = (s32)(s16)CPU->D[(Opcode >> 9) & 7]; + res *= (s32)src; + CPU->flag_N = res >> 24; + CPU->flag_notZ = res; + CPU->flag_V = CPU->flag_C = 0; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(56) +case 0xC340: +case 0xC540: +case 0xC740: +case 0xC940: +case 0xCB40: +case 0xCD40: +case 0xCF40: +case 0xC141: +case 0xC341: +case 0xC541: +case 0xC741: +case 0xC941: +case 0xCB41: +case 0xCD41: +case 0xCF41: +case 0xC142: +case 0xC342: +case 0xC542: +case 0xC742: +case 0xC942: +case 0xCB42: +case 0xCD42: +case 0xCF42: +case 0xC143: +case 0xC343: +case 0xC543: +case 0xC743: +case 0xC943: +case 0xCB43: +case 0xCD43: +case 0xCF43: +case 0xC144: +case 0xC344: +case 0xC544: +case 0xC744: +case 0xC944: +case 0xCB44: +case 0xCD44: +case 0xCF44: +case 0xC145: +case 0xC345: +case 0xC545: +case 0xC745: +case 0xC945: +case 0xCB45: +case 0xCD45: +case 0xCF45: +case 0xC146: +case 0xC346: +case 0xC546: +case 0xC746: +case 0xC946: +case 0xCB46: +case 0xCD46: +case 0xCF46: +case 0xC147: +case 0xC347: +case 0xC547: +case 0xC747: +case 0xC947: +case 0xCB47: +case 0xCD47: +case 0xCF47: + +// EXGDD +case 0xC140: +{ + u32 res; + pointer src; + res = (u32)CPU->D[(Opcode >> 0) & 7]; + src = (u32)CPU->D[(Opcode >> 9) & 7]; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + res = src; + *((u32*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(6) +case 0xC348: +case 0xC548: +case 0xC748: +case 0xC948: +case 0xCB48: +case 0xCD48: +case 0xCF48: +case 0xC149: +case 0xC349: +case 0xC549: +case 0xC749: +case 0xC949: +case 0xCB49: +case 0xCD49: +case 0xCF49: +case 0xC14A: +case 0xC34A: +case 0xC54A: +case 0xC74A: +case 0xC94A: +case 0xCB4A: +case 0xCD4A: +case 0xCF4A: +case 0xC14B: +case 0xC34B: +case 0xC54B: +case 0xC74B: +case 0xC94B: +case 0xCB4B: +case 0xCD4B: +case 0xCF4B: +case 0xC14C: +case 0xC34C: +case 0xC54C: +case 0xC74C: +case 0xC94C: +case 0xCB4C: +case 0xCD4C: +case 0xCF4C: +case 0xC14D: +case 0xC34D: +case 0xC54D: +case 0xC74D: +case 0xC94D: +case 0xCB4D: +case 0xCD4D: +case 0xCF4D: +case 0xC14E: +case 0xC34E: +case 0xC54E: +case 0xC74E: +case 0xC94E: +case 0xCB4E: +case 0xCD4E: +case 0xCF4E: +case 0xC14F: +case 0xC34F: +case 0xC54F: +case 0xC74F: +case 0xC94F: +case 0xCB4F: +case 0xCD4F: +case 0xCF4F: + +// EXGAA +case 0xC148: +{ + u32 res; + pointer src; + res = (u32)CPU->A[(Opcode >> 0) & 7]; + src = (u32)CPU->A[(Opcode >> 9) & 7]; + CPU->A[(Opcode >> 9) & 7] = res; + res = src; + CPU->A[(Opcode >> 0) & 7] = res; +} +RET(6) +case 0xC388: +case 0xC588: +case 0xC788: +case 0xC988: +case 0xCB88: +case 0xCD88: +case 0xCF88: +case 0xC189: +case 0xC389: +case 0xC589: +case 0xC789: +case 0xC989: +case 0xCB89: +case 0xCD89: +case 0xCF89: +case 0xC18A: +case 0xC38A: +case 0xC58A: +case 0xC78A: +case 0xC98A: +case 0xCB8A: +case 0xCD8A: +case 0xCF8A: +case 0xC18B: +case 0xC38B: +case 0xC58B: +case 0xC78B: +case 0xC98B: +case 0xCB8B: +case 0xCD8B: +case 0xCF8B: +case 0xC18C: +case 0xC38C: +case 0xC58C: +case 0xC78C: +case 0xC98C: +case 0xCB8C: +case 0xCD8C: +case 0xCF8C: +case 0xC18D: +case 0xC38D: +case 0xC58D: +case 0xC78D: +case 0xC98D: +case 0xCB8D: +case 0xCD8D: +case 0xCF8D: +case 0xC18E: +case 0xC38E: +case 0xC58E: +case 0xC78E: +case 0xC98E: +case 0xCB8E: +case 0xCD8E: +case 0xCF8E: +case 0xC18F: +case 0xC38F: +case 0xC58F: +case 0xC78F: +case 0xC98F: +case 0xCB8F: +case 0xCD8F: +case 0xCF8F: + +// EXGAD +case 0xC188: +{ + u32 res; + pointer src; + res = (u32)CPU->A[(Opcode >> 0) & 7]; + src = (u32)CPU->D[(Opcode >> 9) & 7]; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + res = src; + CPU->A[(Opcode >> 0) & 7] = res; +} +RET(6) diff --git a/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68k_opD.inc b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68k_opD.inc new file mode 100644 index 000000000..a589c7f02 --- /dev/null +++ b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68k_opD.inc @@ -0,0 +1,5950 @@ +case 0xD200: +case 0xD400: +case 0xD600: +case 0xD800: +case 0xDA00: +case 0xDC00: +case 0xDE00: +case 0xD001: +case 0xD201: +case 0xD401: +case 0xD601: +case 0xD801: +case 0xDA01: +case 0xDC01: +case 0xDE01: +case 0xD002: +case 0xD202: +case 0xD402: +case 0xD602: +case 0xD802: +case 0xDA02: +case 0xDC02: +case 0xDE02: +case 0xD003: +case 0xD203: +case 0xD403: +case 0xD603: +case 0xD803: +case 0xDA03: +case 0xDC03: +case 0xDE03: +case 0xD004: +case 0xD204: +case 0xD404: +case 0xD604: +case 0xD804: +case 0xDA04: +case 0xDC04: +case 0xDE04: +case 0xD005: +case 0xD205: +case 0xD405: +case 0xD605: +case 0xD805: +case 0xDA05: +case 0xDC05: +case 0xDE05: +case 0xD006: +case 0xD206: +case 0xD406: +case 0xD606: +case 0xD806: +case 0xDA06: +case 0xDC06: +case 0xDE06: +case 0xD007: +case 0xD207: +case 0xD407: +case 0xD607: +case 0xD807: +case 0xDA07: +case 0xDC07: +case 0xDE07: + +// ADDaD +case 0xD000: +{ + u32 res; + pointer dst; + pointer src; + src = (u8)CPU->D[(Opcode >> 0) & 7]; + dst = (u8)CPU->D[(Opcode >> 9) & 7]; + res = dst + src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ res) & (dst ^ res); + CPU->flag_notZ = res & 0xFF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; +} +RET(4) +case 0xD208: +case 0xD408: +case 0xD608: +case 0xD808: +case 0xDA08: +case 0xDC08: +case 0xDE08: +case 0xD009: +case 0xD209: +case 0xD409: +case 0xD609: +case 0xD809: +case 0xDA09: +case 0xDC09: +case 0xDE09: +case 0xD00A: +case 0xD20A: +case 0xD40A: +case 0xD60A: +case 0xD80A: +case 0xDA0A: +case 0xDC0A: +case 0xDE0A: +case 0xD00B: +case 0xD20B: +case 0xD40B: +case 0xD60B: +case 0xD80B: +case 0xDA0B: +case 0xDC0B: +case 0xDE0B: +case 0xD00C: +case 0xD20C: +case 0xD40C: +case 0xD60C: +case 0xD80C: +case 0xDA0C: +case 0xDC0C: +case 0xDE0C: +case 0xD00D: +case 0xD20D: +case 0xD40D: +case 0xD60D: +case 0xD80D: +case 0xDA0D: +case 0xDC0D: +case 0xDE0D: +case 0xD00E: +case 0xD20E: +case 0xD40E: +case 0xD60E: +case 0xD80E: +case 0xDA0E: +case 0xDC0E: +case 0xDE0E: +case 0xD00F: +case 0xD20F: +case 0xD40F: +case 0xD60F: +case 0xD80F: +case 0xDA0F: +case 0xDC0F: +case 0xDE0F: + +// ADDaD +case 0xD008: +{ + u32 res; + pointer dst; + pointer src; + // can't read byte from Ax registers ! + CPU->Status |= C68K_FAULTED; + CCnt = 0; + goto C68k_Exec_Really_End; + dst = (u8)CPU->D[(Opcode >> 9) & 7]; + res = dst + src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ res) & (dst ^ res); + CPU->flag_notZ = res & 0xFF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; +} +RET(4) +case 0xD210: +case 0xD410: +case 0xD610: +case 0xD810: +case 0xDA10: +case 0xDC10: +case 0xDE10: +case 0xD011: +case 0xD211: +case 0xD411: +case 0xD611: +case 0xD811: +case 0xDA11: +case 0xDC11: +case 0xDE11: +case 0xD012: +case 0xD212: +case 0xD412: +case 0xD612: +case 0xD812: +case 0xDA12: +case 0xDC12: +case 0xDE12: +case 0xD013: +case 0xD213: +case 0xD413: +case 0xD613: +case 0xD813: +case 0xDA13: +case 0xDC13: +case 0xDE13: +case 0xD014: +case 0xD214: +case 0xD414: +case 0xD614: +case 0xD814: +case 0xDA14: +case 0xDC14: +case 0xDE14: +case 0xD015: +case 0xD215: +case 0xD415: +case 0xD615: +case 0xD815: +case 0xDA15: +case 0xDC15: +case 0xDE15: +case 0xD016: +case 0xD216: +case 0xD416: +case 0xD616: +case 0xD816: +case 0xDA16: +case 0xDC16: +case 0xDE16: +case 0xD017: +case 0xD217: +case 0xD417: +case 0xD617: +case 0xD817: +case 0xDA17: +case 0xDC17: +case 0xDE17: + +// ADDaD +case 0xD010: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_BYTE_F(adr, src) + dst = (u8)CPU->D[(Opcode >> 9) & 7]; + res = dst + src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ res) & (dst ^ res); + CPU->flag_notZ = res & 0xFF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(8) +case 0xD218: +case 0xD418: +case 0xD618: +case 0xD818: +case 0xDA18: +case 0xDC18: +case 0xDE18: +case 0xD019: +case 0xD219: +case 0xD419: +case 0xD619: +case 0xD819: +case 0xDA19: +case 0xDC19: +case 0xDE19: +case 0xD01A: +case 0xD21A: +case 0xD41A: +case 0xD61A: +case 0xD81A: +case 0xDA1A: +case 0xDC1A: +case 0xDE1A: +case 0xD01B: +case 0xD21B: +case 0xD41B: +case 0xD61B: +case 0xD81B: +case 0xDA1B: +case 0xDC1B: +case 0xDE1B: +case 0xD01C: +case 0xD21C: +case 0xD41C: +case 0xD61C: +case 0xD81C: +case 0xDA1C: +case 0xDC1C: +case 0xDE1C: +case 0xD01D: +case 0xD21D: +case 0xD41D: +case 0xD61D: +case 0xD81D: +case 0xDA1D: +case 0xDC1D: +case 0xDE1D: +case 0xD01E: +case 0xD21E: +case 0xD41E: +case 0xD61E: +case 0xD81E: +case 0xDA1E: +case 0xDC1E: +case 0xDE1E: + +// ADDaD +case 0xD018: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + PRE_IO + READ_BYTE_F(adr, src) + dst = (u8)CPU->D[(Opcode >> 9) & 7]; + res = dst + src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ res) & (dst ^ res); + CPU->flag_notZ = res & 0xFF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(8) +case 0xD220: +case 0xD420: +case 0xD620: +case 0xD820: +case 0xDA20: +case 0xDC20: +case 0xDE20: +case 0xD021: +case 0xD221: +case 0xD421: +case 0xD621: +case 0xD821: +case 0xDA21: +case 0xDC21: +case 0xDE21: +case 0xD022: +case 0xD222: +case 0xD422: +case 0xD622: +case 0xD822: +case 0xDA22: +case 0xDC22: +case 0xDE22: +case 0xD023: +case 0xD223: +case 0xD423: +case 0xD623: +case 0xD823: +case 0xDA23: +case 0xDC23: +case 0xDE23: +case 0xD024: +case 0xD224: +case 0xD424: +case 0xD624: +case 0xD824: +case 0xDA24: +case 0xDC24: +case 0xDE24: +case 0xD025: +case 0xD225: +case 0xD425: +case 0xD625: +case 0xD825: +case 0xDA25: +case 0xDC25: +case 0xDE25: +case 0xD026: +case 0xD226: +case 0xD426: +case 0xD626: +case 0xD826: +case 0xDA26: +case 0xDC26: +case 0xDE26: + +// ADDaD +case 0xD020: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_BYTE_F(adr, src) + dst = (u8)CPU->D[(Opcode >> 9) & 7]; + res = dst + src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ res) & (dst ^ res); + CPU->flag_notZ = res & 0xFF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(10) +case 0xD228: +case 0xD428: +case 0xD628: +case 0xD828: +case 0xDA28: +case 0xDC28: +case 0xDE28: +case 0xD029: +case 0xD229: +case 0xD429: +case 0xD629: +case 0xD829: +case 0xDA29: +case 0xDC29: +case 0xDE29: +case 0xD02A: +case 0xD22A: +case 0xD42A: +case 0xD62A: +case 0xD82A: +case 0xDA2A: +case 0xDC2A: +case 0xDE2A: +case 0xD02B: +case 0xD22B: +case 0xD42B: +case 0xD62B: +case 0xD82B: +case 0xDA2B: +case 0xDC2B: +case 0xDE2B: +case 0xD02C: +case 0xD22C: +case 0xD42C: +case 0xD62C: +case 0xD82C: +case 0xDA2C: +case 0xDC2C: +case 0xDE2C: +case 0xD02D: +case 0xD22D: +case 0xD42D: +case 0xD62D: +case 0xD82D: +case 0xDA2D: +case 0xDC2D: +case 0xDE2D: +case 0xD02E: +case 0xD22E: +case 0xD42E: +case 0xD62E: +case 0xD82E: +case 0xDA2E: +case 0xDC2E: +case 0xDE2E: +case 0xD02F: +case 0xD22F: +case 0xD42F: +case 0xD62F: +case 0xD82F: +case 0xDA2F: +case 0xDC2F: +case 0xDE2F: + +// ADDaD +case 0xD028: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, src) + dst = (u8)CPU->D[(Opcode >> 9) & 7]; + res = dst + src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ res) & (dst ^ res); + CPU->flag_notZ = res & 0xFF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(12) +case 0xD230: +case 0xD430: +case 0xD630: +case 0xD830: +case 0xDA30: +case 0xDC30: +case 0xDE30: +case 0xD031: +case 0xD231: +case 0xD431: +case 0xD631: +case 0xD831: +case 0xDA31: +case 0xDC31: +case 0xDE31: +case 0xD032: +case 0xD232: +case 0xD432: +case 0xD632: +case 0xD832: +case 0xDA32: +case 0xDC32: +case 0xDE32: +case 0xD033: +case 0xD233: +case 0xD433: +case 0xD633: +case 0xD833: +case 0xDA33: +case 0xDC33: +case 0xDE33: +case 0xD034: +case 0xD234: +case 0xD434: +case 0xD634: +case 0xD834: +case 0xDA34: +case 0xDC34: +case 0xDE34: +case 0xD035: +case 0xD235: +case 0xD435: +case 0xD635: +case 0xD835: +case 0xDA35: +case 0xDC35: +case 0xDE35: +case 0xD036: +case 0xD236: +case 0xD436: +case 0xD636: +case 0xD836: +case 0xDA36: +case 0xDC36: +case 0xDE36: +case 0xD037: +case 0xD237: +case 0xD437: +case 0xD637: +case 0xD837: +case 0xDA37: +case 0xDC37: +case 0xDE37: + +// ADDaD +case 0xD030: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, src) + dst = (u8)CPU->D[(Opcode >> 9) & 7]; + res = dst + src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ res) & (dst ^ res); + CPU->flag_notZ = res & 0xFF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(14) +case 0xD238: +case 0xD438: +case 0xD638: +case 0xD838: +case 0xDA38: +case 0xDC38: +case 0xDE38: + +// ADDaD +case 0xD038: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, src) + dst = (u8)CPU->D[(Opcode >> 9) & 7]; + res = dst + src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ res) & (dst ^ res); + CPU->flag_notZ = res & 0xFF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(12) +case 0xD239: +case 0xD439: +case 0xD639: +case 0xD839: +case 0xDA39: +case 0xDC39: +case 0xDE39: + +// ADDaD +case 0xD039: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_BYTE_F(adr, src) + dst = (u8)CPU->D[(Opcode >> 9) & 7]; + res = dst + src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ res) & (dst ^ res); + CPU->flag_notZ = res & 0xFF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(16) +case 0xD23A: +case 0xD43A: +case 0xD63A: +case 0xD83A: +case 0xDA3A: +case 0xDC3A: +case 0xDE3A: + +// ADDaD +case 0xD03A: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, src) + dst = (u8)CPU->D[(Opcode >> 9) & 7]; + res = dst + src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ res) & (dst ^ res); + CPU->flag_notZ = res & 0xFF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(12) +case 0xD23B: +case 0xD43B: +case 0xD63B: +case 0xD83B: +case 0xDA3B: +case 0xDC3B: +case 0xDE3B: + +// ADDaD +case 0xD03B: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, src) + dst = (u8)CPU->D[(Opcode >> 9) & 7]; + res = dst + src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ res) & (dst ^ res); + CPU->flag_notZ = res & 0xFF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(14) +case 0xD23C: +case 0xD43C: +case 0xD63C: +case 0xD83C: +case 0xDA3C: +case 0xDC3C: +case 0xDE3C: + +// ADDaD +case 0xD03C: +{ + u32 res; + pointer dst; + pointer src; + src = FETCH_BYTE; + PC += 2; + dst = (u8)CPU->D[(Opcode >> 9) & 7]; + res = dst + src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ res) & (dst ^ res); + CPU->flag_notZ = res & 0xFF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; +} +RET(8) +case 0xD21F: +case 0xD41F: +case 0xD61F: +case 0xD81F: +case 0xDA1F: +case 0xDC1F: +case 0xDE1F: + +// ADDaD +case 0xD01F: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_BYTE_F(adr, src) + dst = (u8)CPU->D[(Opcode >> 9) & 7]; + res = dst + src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ res) & (dst ^ res); + CPU->flag_notZ = res & 0xFF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(8) +case 0xD227: +case 0xD427: +case 0xD627: +case 0xD827: +case 0xDA27: +case 0xDC27: +case 0xDE27: + +// ADDaD +case 0xD027: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_BYTE_F(adr, src) + dst = (u8)CPU->D[(Opcode >> 9) & 7]; + res = dst + src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ res) & (dst ^ res); + CPU->flag_notZ = res & 0xFF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(10) +case 0xD240: +case 0xD440: +case 0xD640: +case 0xD840: +case 0xDA40: +case 0xDC40: +case 0xDE40: +case 0xD041: +case 0xD241: +case 0xD441: +case 0xD641: +case 0xD841: +case 0xDA41: +case 0xDC41: +case 0xDE41: +case 0xD042: +case 0xD242: +case 0xD442: +case 0xD642: +case 0xD842: +case 0xDA42: +case 0xDC42: +case 0xDE42: +case 0xD043: +case 0xD243: +case 0xD443: +case 0xD643: +case 0xD843: +case 0xDA43: +case 0xDC43: +case 0xDE43: +case 0xD044: +case 0xD244: +case 0xD444: +case 0xD644: +case 0xD844: +case 0xDA44: +case 0xDC44: +case 0xDE44: +case 0xD045: +case 0xD245: +case 0xD445: +case 0xD645: +case 0xD845: +case 0xDA45: +case 0xDC45: +case 0xDE45: +case 0xD046: +case 0xD246: +case 0xD446: +case 0xD646: +case 0xD846: +case 0xDA46: +case 0xDC46: +case 0xDE46: +case 0xD047: +case 0xD247: +case 0xD447: +case 0xD647: +case 0xD847: +case 0xDA47: +case 0xDC47: +case 0xDE47: + +// ADDaD +case 0xD040: +{ + u32 res; + pointer dst; + pointer src; + src = (u16)CPU->D[(Opcode >> 0) & 7]; + dst = (u16)CPU->D[(Opcode >> 9) & 7]; + res = dst + src; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; +} +RET(4) +case 0xD248: +case 0xD448: +case 0xD648: +case 0xD848: +case 0xDA48: +case 0xDC48: +case 0xDE48: +case 0xD049: +case 0xD249: +case 0xD449: +case 0xD649: +case 0xD849: +case 0xDA49: +case 0xDC49: +case 0xDE49: +case 0xD04A: +case 0xD24A: +case 0xD44A: +case 0xD64A: +case 0xD84A: +case 0xDA4A: +case 0xDC4A: +case 0xDE4A: +case 0xD04B: +case 0xD24B: +case 0xD44B: +case 0xD64B: +case 0xD84B: +case 0xDA4B: +case 0xDC4B: +case 0xDE4B: +case 0xD04C: +case 0xD24C: +case 0xD44C: +case 0xD64C: +case 0xD84C: +case 0xDA4C: +case 0xDC4C: +case 0xDE4C: +case 0xD04D: +case 0xD24D: +case 0xD44D: +case 0xD64D: +case 0xD84D: +case 0xDA4D: +case 0xDC4D: +case 0xDE4D: +case 0xD04E: +case 0xD24E: +case 0xD44E: +case 0xD64E: +case 0xD84E: +case 0xDA4E: +case 0xDC4E: +case 0xDE4E: +case 0xD04F: +case 0xD24F: +case 0xD44F: +case 0xD64F: +case 0xD84F: +case 0xDA4F: +case 0xDC4F: +case 0xDE4F: + +// ADDaD +case 0xD048: +{ + u32 res; + pointer dst; + pointer src; + src = (u16)CPU->A[(Opcode >> 0) & 7]; + dst = (u16)CPU->D[(Opcode >> 9) & 7]; + res = dst + src; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; +} +RET(4) +case 0xD250: +case 0xD450: +case 0xD650: +case 0xD850: +case 0xDA50: +case 0xDC50: +case 0xDE50: +case 0xD051: +case 0xD251: +case 0xD451: +case 0xD651: +case 0xD851: +case 0xDA51: +case 0xDC51: +case 0xDE51: +case 0xD052: +case 0xD252: +case 0xD452: +case 0xD652: +case 0xD852: +case 0xDA52: +case 0xDC52: +case 0xDE52: +case 0xD053: +case 0xD253: +case 0xD453: +case 0xD653: +case 0xD853: +case 0xDA53: +case 0xDC53: +case 0xDE53: +case 0xD054: +case 0xD254: +case 0xD454: +case 0xD654: +case 0xD854: +case 0xDA54: +case 0xDC54: +case 0xDE54: +case 0xD055: +case 0xD255: +case 0xD455: +case 0xD655: +case 0xD855: +case 0xDA55: +case 0xDC55: +case 0xDE55: +case 0xD056: +case 0xD256: +case 0xD456: +case 0xD656: +case 0xD856: +case 0xDA56: +case 0xDC56: +case 0xDE56: +case 0xD057: +case 0xD257: +case 0xD457: +case 0xD657: +case 0xD857: +case 0xDA57: +case 0xDC57: +case 0xDE57: + +// ADDaD +case 0xD050: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_WORD_F(adr, src) + dst = (u16)CPU->D[(Opcode >> 9) & 7]; + res = dst + src; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(8) +case 0xD258: +case 0xD458: +case 0xD658: +case 0xD858: +case 0xDA58: +case 0xDC58: +case 0xDE58: +case 0xD059: +case 0xD259: +case 0xD459: +case 0xD659: +case 0xD859: +case 0xDA59: +case 0xDC59: +case 0xDE59: +case 0xD05A: +case 0xD25A: +case 0xD45A: +case 0xD65A: +case 0xD85A: +case 0xDA5A: +case 0xDC5A: +case 0xDE5A: +case 0xD05B: +case 0xD25B: +case 0xD45B: +case 0xD65B: +case 0xD85B: +case 0xDA5B: +case 0xDC5B: +case 0xDE5B: +case 0xD05C: +case 0xD25C: +case 0xD45C: +case 0xD65C: +case 0xD85C: +case 0xDA5C: +case 0xDC5C: +case 0xDE5C: +case 0xD05D: +case 0xD25D: +case 0xD45D: +case 0xD65D: +case 0xD85D: +case 0xDA5D: +case 0xDC5D: +case 0xDE5D: +case 0xD05E: +case 0xD25E: +case 0xD45E: +case 0xD65E: +case 0xD85E: +case 0xDA5E: +case 0xDC5E: +case 0xDE5E: + +// ADDaD +case 0xD058: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 2; + PRE_IO + READ_WORD_F(adr, src) + dst = (u16)CPU->D[(Opcode >> 9) & 7]; + res = dst + src; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(8) +case 0xD260: +case 0xD460: +case 0xD660: +case 0xD860: +case 0xDA60: +case 0xDC60: +case 0xDE60: +case 0xD061: +case 0xD261: +case 0xD461: +case 0xD661: +case 0xD861: +case 0xDA61: +case 0xDC61: +case 0xDE61: +case 0xD062: +case 0xD262: +case 0xD462: +case 0xD662: +case 0xD862: +case 0xDA62: +case 0xDC62: +case 0xDE62: +case 0xD063: +case 0xD263: +case 0xD463: +case 0xD663: +case 0xD863: +case 0xDA63: +case 0xDC63: +case 0xDE63: +case 0xD064: +case 0xD264: +case 0xD464: +case 0xD664: +case 0xD864: +case 0xDA64: +case 0xDC64: +case 0xDE64: +case 0xD065: +case 0xD265: +case 0xD465: +case 0xD665: +case 0xD865: +case 0xDA65: +case 0xDC65: +case 0xDE65: +case 0xD066: +case 0xD266: +case 0xD466: +case 0xD666: +case 0xD866: +case 0xDA66: +case 0xDC66: +case 0xDE66: + +// ADDaD +case 0xD060: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 2; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_WORD_F(adr, src) + dst = (u16)CPU->D[(Opcode >> 9) & 7]; + res = dst + src; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(10) +case 0xD268: +case 0xD468: +case 0xD668: +case 0xD868: +case 0xDA68: +case 0xDC68: +case 0xDE68: +case 0xD069: +case 0xD269: +case 0xD469: +case 0xD669: +case 0xD869: +case 0xDA69: +case 0xDC69: +case 0xDE69: +case 0xD06A: +case 0xD26A: +case 0xD46A: +case 0xD66A: +case 0xD86A: +case 0xDA6A: +case 0xDC6A: +case 0xDE6A: +case 0xD06B: +case 0xD26B: +case 0xD46B: +case 0xD66B: +case 0xD86B: +case 0xDA6B: +case 0xDC6B: +case 0xDE6B: +case 0xD06C: +case 0xD26C: +case 0xD46C: +case 0xD66C: +case 0xD86C: +case 0xDA6C: +case 0xDC6C: +case 0xDE6C: +case 0xD06D: +case 0xD26D: +case 0xD46D: +case 0xD66D: +case 0xD86D: +case 0xDA6D: +case 0xDC6D: +case 0xDE6D: +case 0xD06E: +case 0xD26E: +case 0xD46E: +case 0xD66E: +case 0xD86E: +case 0xDA6E: +case 0xDC6E: +case 0xDE6E: +case 0xD06F: +case 0xD26F: +case 0xD46F: +case 0xD66F: +case 0xD86F: +case 0xDA6F: +case 0xDC6F: +case 0xDE6F: + +// ADDaD +case 0xD068: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, src) + dst = (u16)CPU->D[(Opcode >> 9) & 7]; + res = dst + src; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(12) +case 0xD270: +case 0xD470: +case 0xD670: +case 0xD870: +case 0xDA70: +case 0xDC70: +case 0xDE70: +case 0xD071: +case 0xD271: +case 0xD471: +case 0xD671: +case 0xD871: +case 0xDA71: +case 0xDC71: +case 0xDE71: +case 0xD072: +case 0xD272: +case 0xD472: +case 0xD672: +case 0xD872: +case 0xDA72: +case 0xDC72: +case 0xDE72: +case 0xD073: +case 0xD273: +case 0xD473: +case 0xD673: +case 0xD873: +case 0xDA73: +case 0xDC73: +case 0xDE73: +case 0xD074: +case 0xD274: +case 0xD474: +case 0xD674: +case 0xD874: +case 0xDA74: +case 0xDC74: +case 0xDE74: +case 0xD075: +case 0xD275: +case 0xD475: +case 0xD675: +case 0xD875: +case 0xDA75: +case 0xDC75: +case 0xDE75: +case 0xD076: +case 0xD276: +case 0xD476: +case 0xD676: +case 0xD876: +case 0xDA76: +case 0xDC76: +case 0xDE76: +case 0xD077: +case 0xD277: +case 0xD477: +case 0xD677: +case 0xD877: +case 0xDA77: +case 0xDC77: +case 0xDE77: + +// ADDaD +case 0xD070: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, src) + dst = (u16)CPU->D[(Opcode >> 9) & 7]; + res = dst + src; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(14) +case 0xD278: +case 0xD478: +case 0xD678: +case 0xD878: +case 0xDA78: +case 0xDC78: +case 0xDE78: + +// ADDaD +case 0xD078: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, src) + dst = (u16)CPU->D[(Opcode >> 9) & 7]; + res = dst + src; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(12) +case 0xD279: +case 0xD479: +case 0xD679: +case 0xD879: +case 0xDA79: +case 0xDC79: +case 0xDE79: + +// ADDaD +case 0xD079: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_WORD_F(adr, src) + dst = (u16)CPU->D[(Opcode >> 9) & 7]; + res = dst + src; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(16) +case 0xD27A: +case 0xD47A: +case 0xD67A: +case 0xD87A: +case 0xDA7A: +case 0xDC7A: +case 0xDE7A: + +// ADDaD +case 0xD07A: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, src) + dst = (u16)CPU->D[(Opcode >> 9) & 7]; + res = dst + src; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(12) +case 0xD27B: +case 0xD47B: +case 0xD67B: +case 0xD87B: +case 0xDA7B: +case 0xDC7B: +case 0xDE7B: + +// ADDaD +case 0xD07B: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, src) + dst = (u16)CPU->D[(Opcode >> 9) & 7]; + res = dst + src; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(14) +case 0xD27C: +case 0xD47C: +case 0xD67C: +case 0xD87C: +case 0xDA7C: +case 0xDC7C: +case 0xDE7C: + +// ADDaD +case 0xD07C: +{ + u32 res; + pointer dst; + pointer src; + src = FETCH_WORD; + PC += 2; + dst = (u16)CPU->D[(Opcode >> 9) & 7]; + res = dst + src; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; +} +RET(8) +case 0xD25F: +case 0xD45F: +case 0xD65F: +case 0xD85F: +case 0xDA5F: +case 0xDC5F: +case 0xDE5F: + +// ADDaD +case 0xD05F: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_WORD_F(adr, src) + dst = (u16)CPU->D[(Opcode >> 9) & 7]; + res = dst + src; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(8) +case 0xD267: +case 0xD467: +case 0xD667: +case 0xD867: +case 0xDA67: +case 0xDC67: +case 0xDE67: + +// ADDaD +case 0xD067: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_WORD_F(adr, src) + dst = (u16)CPU->D[(Opcode >> 9) & 7]; + res = dst + src; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(10) +case 0xD280: +case 0xD480: +case 0xD680: +case 0xD880: +case 0xDA80: +case 0xDC80: +case 0xDE80: +case 0xD081: +case 0xD281: +case 0xD481: +case 0xD681: +case 0xD881: +case 0xDA81: +case 0xDC81: +case 0xDE81: +case 0xD082: +case 0xD282: +case 0xD482: +case 0xD682: +case 0xD882: +case 0xDA82: +case 0xDC82: +case 0xDE82: +case 0xD083: +case 0xD283: +case 0xD483: +case 0xD683: +case 0xD883: +case 0xDA83: +case 0xDC83: +case 0xDE83: +case 0xD084: +case 0xD284: +case 0xD484: +case 0xD684: +case 0xD884: +case 0xDA84: +case 0xDC84: +case 0xDE84: +case 0xD085: +case 0xD285: +case 0xD485: +case 0xD685: +case 0xD885: +case 0xDA85: +case 0xDC85: +case 0xDE85: +case 0xD086: +case 0xD286: +case 0xD486: +case 0xD686: +case 0xD886: +case 0xDA86: +case 0xDC86: +case 0xDE86: +case 0xD087: +case 0xD287: +case 0xD487: +case 0xD687: +case 0xD887: +case 0xDA87: +case 0xDC87: +case 0xDE87: + +// ADDaD +case 0xD080: +{ + u32 res; + pointer dst; + pointer src; + src = (u32)CPU->D[(Opcode >> 0) & 7]; + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + res = dst + src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 24; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; +} +RET(6) +case 0xD288: +case 0xD488: +case 0xD688: +case 0xD888: +case 0xDA88: +case 0xDC88: +case 0xDE88: +case 0xD089: +case 0xD289: +case 0xD489: +case 0xD689: +case 0xD889: +case 0xDA89: +case 0xDC89: +case 0xDE89: +case 0xD08A: +case 0xD28A: +case 0xD48A: +case 0xD68A: +case 0xD88A: +case 0xDA8A: +case 0xDC8A: +case 0xDE8A: +case 0xD08B: +case 0xD28B: +case 0xD48B: +case 0xD68B: +case 0xD88B: +case 0xDA8B: +case 0xDC8B: +case 0xDE8B: +case 0xD08C: +case 0xD28C: +case 0xD48C: +case 0xD68C: +case 0xD88C: +case 0xDA8C: +case 0xDC8C: +case 0xDE8C: +case 0xD08D: +case 0xD28D: +case 0xD48D: +case 0xD68D: +case 0xD88D: +case 0xDA8D: +case 0xDC8D: +case 0xDE8D: +case 0xD08E: +case 0xD28E: +case 0xD48E: +case 0xD68E: +case 0xD88E: +case 0xDA8E: +case 0xDC8E: +case 0xDE8E: +case 0xD08F: +case 0xD28F: +case 0xD48F: +case 0xD68F: +case 0xD88F: +case 0xDA8F: +case 0xDC8F: +case 0xDE8F: + +// ADDaD +case 0xD088: +{ + u32 res; + pointer dst; + pointer src; + src = (u32)CPU->A[(Opcode >> 0) & 7]; + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + res = dst + src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 24; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; +} +RET(6) +case 0xD290: +case 0xD490: +case 0xD690: +case 0xD890: +case 0xDA90: +case 0xDC90: +case 0xDE90: +case 0xD091: +case 0xD291: +case 0xD491: +case 0xD691: +case 0xD891: +case 0xDA91: +case 0xDC91: +case 0xDE91: +case 0xD092: +case 0xD292: +case 0xD492: +case 0xD692: +case 0xD892: +case 0xDA92: +case 0xDC92: +case 0xDE92: +case 0xD093: +case 0xD293: +case 0xD493: +case 0xD693: +case 0xD893: +case 0xDA93: +case 0xDC93: +case 0xDE93: +case 0xD094: +case 0xD294: +case 0xD494: +case 0xD694: +case 0xD894: +case 0xDA94: +case 0xDC94: +case 0xDE94: +case 0xD095: +case 0xD295: +case 0xD495: +case 0xD695: +case 0xD895: +case 0xDA95: +case 0xDC95: +case 0xDE95: +case 0xD096: +case 0xD296: +case 0xD496: +case 0xD696: +case 0xD896: +case 0xDA96: +case 0xDC96: +case 0xDE96: +case 0xD097: +case 0xD297: +case 0xD497: +case 0xD697: +case 0xD897: +case 0xDA97: +case 0xDC97: +case 0xDE97: + +// ADDaD +case 0xD090: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_LONG_F(adr, src) + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + res = dst + src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 24; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(16) +case 0xD298: +case 0xD498: +case 0xD698: +case 0xD898: +case 0xDA98: +case 0xDC98: +case 0xDE98: +case 0xD099: +case 0xD299: +case 0xD499: +case 0xD699: +case 0xD899: +case 0xDA99: +case 0xDC99: +case 0xDE99: +case 0xD09A: +case 0xD29A: +case 0xD49A: +case 0xD69A: +case 0xD89A: +case 0xDA9A: +case 0xDC9A: +case 0xDE9A: +case 0xD09B: +case 0xD29B: +case 0xD49B: +case 0xD69B: +case 0xD89B: +case 0xDA9B: +case 0xDC9B: +case 0xDE9B: +case 0xD09C: +case 0xD29C: +case 0xD49C: +case 0xD69C: +case 0xD89C: +case 0xDA9C: +case 0xDC9C: +case 0xDE9C: +case 0xD09D: +case 0xD29D: +case 0xD49D: +case 0xD69D: +case 0xD89D: +case 0xDA9D: +case 0xDC9D: +case 0xDE9D: +case 0xD09E: +case 0xD29E: +case 0xD49E: +case 0xD69E: +case 0xD89E: +case 0xDA9E: +case 0xDC9E: +case 0xDE9E: + +// ADDaD +case 0xD098: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 4; + PRE_IO + READ_LONG_F(adr, src) + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + res = dst + src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 24; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(16) +case 0xD2A0: +case 0xD4A0: +case 0xD6A0: +case 0xD8A0: +case 0xDAA0: +case 0xDCA0: +case 0xDEA0: +case 0xD0A1: +case 0xD2A1: +case 0xD4A1: +case 0xD6A1: +case 0xD8A1: +case 0xDAA1: +case 0xDCA1: +case 0xDEA1: +case 0xD0A2: +case 0xD2A2: +case 0xD4A2: +case 0xD6A2: +case 0xD8A2: +case 0xDAA2: +case 0xDCA2: +case 0xDEA2: +case 0xD0A3: +case 0xD2A3: +case 0xD4A3: +case 0xD6A3: +case 0xD8A3: +case 0xDAA3: +case 0xDCA3: +case 0xDEA3: +case 0xD0A4: +case 0xD2A4: +case 0xD4A4: +case 0xD6A4: +case 0xD8A4: +case 0xDAA4: +case 0xDCA4: +case 0xDEA4: +case 0xD0A5: +case 0xD2A5: +case 0xD4A5: +case 0xD6A5: +case 0xD8A5: +case 0xDAA5: +case 0xDCA5: +case 0xDEA5: +case 0xD0A6: +case 0xD2A6: +case 0xD4A6: +case 0xD6A6: +case 0xD8A6: +case 0xDAA6: +case 0xDCA6: +case 0xDEA6: + +// ADDaD +case 0xD0A0: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 4; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_LONG_F(adr, src) + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + res = dst + src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 24; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(18) +case 0xD2A8: +case 0xD4A8: +case 0xD6A8: +case 0xD8A8: +case 0xDAA8: +case 0xDCA8: +case 0xDEA8: +case 0xD0A9: +case 0xD2A9: +case 0xD4A9: +case 0xD6A9: +case 0xD8A9: +case 0xDAA9: +case 0xDCA9: +case 0xDEA9: +case 0xD0AA: +case 0xD2AA: +case 0xD4AA: +case 0xD6AA: +case 0xD8AA: +case 0xDAAA: +case 0xDCAA: +case 0xDEAA: +case 0xD0AB: +case 0xD2AB: +case 0xD4AB: +case 0xD6AB: +case 0xD8AB: +case 0xDAAB: +case 0xDCAB: +case 0xDEAB: +case 0xD0AC: +case 0xD2AC: +case 0xD4AC: +case 0xD6AC: +case 0xD8AC: +case 0xDAAC: +case 0xDCAC: +case 0xDEAC: +case 0xD0AD: +case 0xD2AD: +case 0xD4AD: +case 0xD6AD: +case 0xD8AD: +case 0xDAAD: +case 0xDCAD: +case 0xDEAD: +case 0xD0AE: +case 0xD2AE: +case 0xD4AE: +case 0xD6AE: +case 0xD8AE: +case 0xDAAE: +case 0xDCAE: +case 0xDEAE: +case 0xD0AF: +case 0xD2AF: +case 0xD4AF: +case 0xD6AF: +case 0xD8AF: +case 0xDAAF: +case 0xDCAF: +case 0xDEAF: + +// ADDaD +case 0xD0A8: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, src) + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + res = dst + src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 24; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(20) +case 0xD2B0: +case 0xD4B0: +case 0xD6B0: +case 0xD8B0: +case 0xDAB0: +case 0xDCB0: +case 0xDEB0: +case 0xD0B1: +case 0xD2B1: +case 0xD4B1: +case 0xD6B1: +case 0xD8B1: +case 0xDAB1: +case 0xDCB1: +case 0xDEB1: +case 0xD0B2: +case 0xD2B2: +case 0xD4B2: +case 0xD6B2: +case 0xD8B2: +case 0xDAB2: +case 0xDCB2: +case 0xDEB2: +case 0xD0B3: +case 0xD2B3: +case 0xD4B3: +case 0xD6B3: +case 0xD8B3: +case 0xDAB3: +case 0xDCB3: +case 0xDEB3: +case 0xD0B4: +case 0xD2B4: +case 0xD4B4: +case 0xD6B4: +case 0xD8B4: +case 0xDAB4: +case 0xDCB4: +case 0xDEB4: +case 0xD0B5: +case 0xD2B5: +case 0xD4B5: +case 0xD6B5: +case 0xD8B5: +case 0xDAB5: +case 0xDCB5: +case 0xDEB5: +case 0xD0B6: +case 0xD2B6: +case 0xD4B6: +case 0xD6B6: +case 0xD8B6: +case 0xDAB6: +case 0xDCB6: +case 0xDEB6: +case 0xD0B7: +case 0xD2B7: +case 0xD4B7: +case 0xD6B7: +case 0xD8B7: +case 0xDAB7: +case 0xDCB7: +case 0xDEB7: + +// ADDaD +case 0xD0B0: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_LONG_F(adr, src) + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + res = dst + src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 24; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(22) +case 0xD2B8: +case 0xD4B8: +case 0xD6B8: +case 0xD8B8: +case 0xDAB8: +case 0xDCB8: +case 0xDEB8: + +// ADDaD +case 0xD0B8: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, src) + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + res = dst + src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 24; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(20) +case 0xD2B9: +case 0xD4B9: +case 0xD6B9: +case 0xD8B9: +case 0xDAB9: +case 0xDCB9: +case 0xDEB9: + +// ADDaD +case 0xD0B9: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_LONG_F(adr, src) + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + res = dst + src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 24; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(24) +case 0xD2BA: +case 0xD4BA: +case 0xD6BA: +case 0xD8BA: +case 0xDABA: +case 0xDCBA: +case 0xDEBA: + +// ADDaD +case 0xD0BA: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, src) + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + res = dst + src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 24; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(20) +case 0xD2BB: +case 0xD4BB: +case 0xD6BB: +case 0xD8BB: +case 0xDABB: +case 0xDCBB: +case 0xDEBB: + +// ADDaD +case 0xD0BB: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READ_LONG_F(adr, src) + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + res = dst + src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 24; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(22) +case 0xD2BC: +case 0xD4BC: +case 0xD6BC: +case 0xD8BC: +case 0xDABC: +case 0xDCBC: +case 0xDEBC: + +// ADDaD +case 0xD0BC: +{ + u32 res; + pointer dst; + pointer src; + src = FETCH_LONG; + PC += 4; + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + res = dst + src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 24; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; +} +RET(14) +case 0xD29F: +case 0xD49F: +case 0xD69F: +case 0xD89F: +case 0xDA9F: +case 0xDC9F: +case 0xDE9F: + +// ADDaD +case 0xD09F: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[7]; + CPU->A[7] += 4; + PRE_IO + READ_LONG_F(adr, src) + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + res = dst + src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 24; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(16) +case 0xD2A7: +case 0xD4A7: +case 0xD6A7: +case 0xD8A7: +case 0xDAA7: +case 0xDCA7: +case 0xDEA7: + +// ADDaD +case 0xD0A7: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + PRE_IO + READ_LONG_F(adr, src) + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + res = dst + src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 24; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; + POST_IO +} +RET(18) +case 0xD310: +case 0xD510: +case 0xD710: +case 0xD910: +case 0xDB10: +case 0xDD10: +case 0xDF10: +case 0xD111: +case 0xD311: +case 0xD511: +case 0xD711: +case 0xD911: +case 0xDB11: +case 0xDD11: +case 0xDF11: +case 0xD112: +case 0xD312: +case 0xD512: +case 0xD712: +case 0xD912: +case 0xDB12: +case 0xDD12: +case 0xDF12: +case 0xD113: +case 0xD313: +case 0xD513: +case 0xD713: +case 0xD913: +case 0xDB13: +case 0xDD13: +case 0xDF13: +case 0xD114: +case 0xD314: +case 0xD514: +case 0xD714: +case 0xD914: +case 0xDB14: +case 0xDD14: +case 0xDF14: +case 0xD115: +case 0xD315: +case 0xD515: +case 0xD715: +case 0xD915: +case 0xDB15: +case 0xDD15: +case 0xDF15: +case 0xD116: +case 0xD316: +case 0xD516: +case 0xD716: +case 0xD916: +case 0xDB16: +case 0xDD16: +case 0xDF16: +case 0xD117: +case 0xD317: +case 0xD517: +case 0xD717: +case 0xD917: +case 0xDB17: +case 0xDD17: +case 0xDF17: + +// ADDDa +case 0xD110: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_BYTE_F(adr, dst) + res = dst + src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ res) & (dst ^ res); + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0xD318: +case 0xD518: +case 0xD718: +case 0xD918: +case 0xDB18: +case 0xDD18: +case 0xDF18: +case 0xD119: +case 0xD319: +case 0xD519: +case 0xD719: +case 0xD919: +case 0xDB19: +case 0xDD19: +case 0xDF19: +case 0xD11A: +case 0xD31A: +case 0xD51A: +case 0xD71A: +case 0xD91A: +case 0xDB1A: +case 0xDD1A: +case 0xDF1A: +case 0xD11B: +case 0xD31B: +case 0xD51B: +case 0xD71B: +case 0xD91B: +case 0xDB1B: +case 0xDD1B: +case 0xDF1B: +case 0xD11C: +case 0xD31C: +case 0xD51C: +case 0xD71C: +case 0xD91C: +case 0xDB1C: +case 0xDD1C: +case 0xDF1C: +case 0xD11D: +case 0xD31D: +case 0xD51D: +case 0xD71D: +case 0xD91D: +case 0xDB1D: +case 0xDD1D: +case 0xDF1D: +case 0xD11E: +case 0xD31E: +case 0xD51E: +case 0xD71E: +case 0xD91E: +case 0xDB1E: +case 0xDD1E: +case 0xDF1E: + +// ADDDa +case 0xD118: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 1; + PRE_IO + READ_BYTE_F(adr, dst) + res = dst + src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ res) & (dst ^ res); + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0xD320: +case 0xD520: +case 0xD720: +case 0xD920: +case 0xDB20: +case 0xDD20: +case 0xDF20: +case 0xD121: +case 0xD321: +case 0xD521: +case 0xD721: +case 0xD921: +case 0xDB21: +case 0xDD21: +case 0xDF21: +case 0xD122: +case 0xD322: +case 0xD522: +case 0xD722: +case 0xD922: +case 0xDB22: +case 0xDD22: +case 0xDF22: +case 0xD123: +case 0xD323: +case 0xD523: +case 0xD723: +case 0xD923: +case 0xDB23: +case 0xDD23: +case 0xDF23: +case 0xD124: +case 0xD324: +case 0xD524: +case 0xD724: +case 0xD924: +case 0xDB24: +case 0xDD24: +case 0xDF24: +case 0xD125: +case 0xD325: +case 0xD525: +case 0xD725: +case 0xD925: +case 0xDB25: +case 0xDD25: +case 0xDF25: +case 0xD126: +case 0xD326: +case 0xD526: +case 0xD726: +case 0xD926: +case 0xDB26: +case 0xDD26: +case 0xDF26: + +// ADDDa +case 0xD120: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_BYTE_F(adr, dst) + res = dst + src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ res) & (dst ^ res); + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(14) +case 0xD328: +case 0xD528: +case 0xD728: +case 0xD928: +case 0xDB28: +case 0xDD28: +case 0xDF28: +case 0xD129: +case 0xD329: +case 0xD529: +case 0xD729: +case 0xD929: +case 0xDB29: +case 0xDD29: +case 0xDF29: +case 0xD12A: +case 0xD32A: +case 0xD52A: +case 0xD72A: +case 0xD92A: +case 0xDB2A: +case 0xDD2A: +case 0xDF2A: +case 0xD12B: +case 0xD32B: +case 0xD52B: +case 0xD72B: +case 0xD92B: +case 0xDB2B: +case 0xDD2B: +case 0xDF2B: +case 0xD12C: +case 0xD32C: +case 0xD52C: +case 0xD72C: +case 0xD92C: +case 0xDB2C: +case 0xDD2C: +case 0xDF2C: +case 0xD12D: +case 0xD32D: +case 0xD52D: +case 0xD72D: +case 0xD92D: +case 0xDB2D: +case 0xDD2D: +case 0xDF2D: +case 0xD12E: +case 0xD32E: +case 0xD52E: +case 0xD72E: +case 0xD92E: +case 0xDB2E: +case 0xDD2E: +case 0xDF2E: +case 0xD12F: +case 0xD32F: +case 0xD52F: +case 0xD72F: +case 0xD92F: +case 0xDB2F: +case 0xDD2F: +case 0xDF2F: + +// ADDDa +case 0xD128: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, dst) + res = dst + src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ res) & (dst ^ res); + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0xD330: +case 0xD530: +case 0xD730: +case 0xD930: +case 0xDB30: +case 0xDD30: +case 0xDF30: +case 0xD131: +case 0xD331: +case 0xD531: +case 0xD731: +case 0xD931: +case 0xDB31: +case 0xDD31: +case 0xDF31: +case 0xD132: +case 0xD332: +case 0xD532: +case 0xD732: +case 0xD932: +case 0xDB32: +case 0xDD32: +case 0xDF32: +case 0xD133: +case 0xD333: +case 0xD533: +case 0xD733: +case 0xD933: +case 0xDB33: +case 0xDD33: +case 0xDF33: +case 0xD134: +case 0xD334: +case 0xD534: +case 0xD734: +case 0xD934: +case 0xDB34: +case 0xDD34: +case 0xDF34: +case 0xD135: +case 0xD335: +case 0xD535: +case 0xD735: +case 0xD935: +case 0xDB35: +case 0xDD35: +case 0xDF35: +case 0xD136: +case 0xD336: +case 0xD536: +case 0xD736: +case 0xD936: +case 0xDB36: +case 0xDD36: +case 0xDF36: +case 0xD137: +case 0xD337: +case 0xD537: +case 0xD737: +case 0xD937: +case 0xDB37: +case 0xDD37: +case 0xDF37: + +// ADDDa +case 0xD130: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_BYTE_F(adr, dst) + res = dst + src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ res) & (dst ^ res); + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) +case 0xD338: +case 0xD538: +case 0xD738: +case 0xD938: +case 0xDB38: +case 0xDD38: +case 0xDF38: + +// ADDDa +case 0xD138: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_BYTE_F(adr, dst) + res = dst + src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ res) & (dst ^ res); + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(16) +case 0xD339: +case 0xD539: +case 0xD739: +case 0xD939: +case 0xDB39: +case 0xDD39: +case 0xDF39: + +// ADDDa +case 0xD139: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_BYTE_F(adr, dst) + res = dst + src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ res) & (dst ^ res); + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(20) +case 0xD31F: +case 0xD51F: +case 0xD71F: +case 0xD91F: +case 0xDB1F: +case 0xDD1F: +case 0xDF1F: + +// ADDDa +case 0xD11F: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_BYTE_F(adr, dst) + res = dst + src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ res) & (dst ^ res); + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(12) +case 0xD327: +case 0xD527: +case 0xD727: +case 0xD927: +case 0xDB27: +case 0xDD27: +case 0xDF27: + +// ADDDa +case 0xD127: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (u8)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_BYTE_F(adr, dst) + res = dst + src; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ res) & (dst ^ res); + CPU->flag_notZ = res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(14) +case 0xD350: +case 0xD550: +case 0xD750: +case 0xD950: +case 0xDB50: +case 0xDD50: +case 0xDF50: +case 0xD151: +case 0xD351: +case 0xD551: +case 0xD751: +case 0xD951: +case 0xDB51: +case 0xDD51: +case 0xDF51: +case 0xD152: +case 0xD352: +case 0xD552: +case 0xD752: +case 0xD952: +case 0xDB52: +case 0xDD52: +case 0xDF52: +case 0xD153: +case 0xD353: +case 0xD553: +case 0xD753: +case 0xD953: +case 0xDB53: +case 0xDD53: +case 0xDF53: +case 0xD154: +case 0xD354: +case 0xD554: +case 0xD754: +case 0xD954: +case 0xDB54: +case 0xDD54: +case 0xDF54: +case 0xD155: +case 0xD355: +case 0xD555: +case 0xD755: +case 0xD955: +case 0xDB55: +case 0xDD55: +case 0xDF55: +case 0xD156: +case 0xD356: +case 0xD556: +case 0xD756: +case 0xD956: +case 0xDB56: +case 0xDD56: +case 0xDF56: +case 0xD157: +case 0xD357: +case 0xD557: +case 0xD757: +case 0xD957: +case 0xDB57: +case 0xDD57: +case 0xDF57: + +// ADDDa +case 0xD150: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (u16)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_WORD_F(adr, dst) + res = dst + src; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0xD358: +case 0xD558: +case 0xD758: +case 0xD958: +case 0xDB58: +case 0xDD58: +case 0xDF58: +case 0xD159: +case 0xD359: +case 0xD559: +case 0xD759: +case 0xD959: +case 0xDB59: +case 0xDD59: +case 0xDF59: +case 0xD15A: +case 0xD35A: +case 0xD55A: +case 0xD75A: +case 0xD95A: +case 0xDB5A: +case 0xDD5A: +case 0xDF5A: +case 0xD15B: +case 0xD35B: +case 0xD55B: +case 0xD75B: +case 0xD95B: +case 0xDB5B: +case 0xDD5B: +case 0xDF5B: +case 0xD15C: +case 0xD35C: +case 0xD55C: +case 0xD75C: +case 0xD95C: +case 0xDB5C: +case 0xDD5C: +case 0xDF5C: +case 0xD15D: +case 0xD35D: +case 0xD55D: +case 0xD75D: +case 0xD95D: +case 0xDB5D: +case 0xDD5D: +case 0xDF5D: +case 0xD15E: +case 0xD35E: +case 0xD55E: +case 0xD75E: +case 0xD95E: +case 0xDB5E: +case 0xDD5E: +case 0xDF5E: + +// ADDDa +case 0xD158: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (u16)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 2; + PRE_IO + READ_WORD_F(adr, dst) + res = dst + src; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0xD360: +case 0xD560: +case 0xD760: +case 0xD960: +case 0xDB60: +case 0xDD60: +case 0xDF60: +case 0xD161: +case 0xD361: +case 0xD561: +case 0xD761: +case 0xD961: +case 0xDB61: +case 0xDD61: +case 0xDF61: +case 0xD162: +case 0xD362: +case 0xD562: +case 0xD762: +case 0xD962: +case 0xDB62: +case 0xDD62: +case 0xDF62: +case 0xD163: +case 0xD363: +case 0xD563: +case 0xD763: +case 0xD963: +case 0xDB63: +case 0xDD63: +case 0xDF63: +case 0xD164: +case 0xD364: +case 0xD564: +case 0xD764: +case 0xD964: +case 0xDB64: +case 0xDD64: +case 0xDF64: +case 0xD165: +case 0xD365: +case 0xD565: +case 0xD765: +case 0xD965: +case 0xDB65: +case 0xDD65: +case 0xDF65: +case 0xD166: +case 0xD366: +case 0xD566: +case 0xD766: +case 0xD966: +case 0xDB66: +case 0xDD66: +case 0xDF66: + +// ADDDa +case 0xD160: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (u16)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7] - 2; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_WORD_F(adr, dst) + res = dst + src; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(14) +case 0xD368: +case 0xD568: +case 0xD768: +case 0xD968: +case 0xDB68: +case 0xDD68: +case 0xDF68: +case 0xD169: +case 0xD369: +case 0xD569: +case 0xD769: +case 0xD969: +case 0xDB69: +case 0xDD69: +case 0xDF69: +case 0xD16A: +case 0xD36A: +case 0xD56A: +case 0xD76A: +case 0xD96A: +case 0xDB6A: +case 0xDD6A: +case 0xDF6A: +case 0xD16B: +case 0xD36B: +case 0xD56B: +case 0xD76B: +case 0xD96B: +case 0xDB6B: +case 0xDD6B: +case 0xDF6B: +case 0xD16C: +case 0xD36C: +case 0xD56C: +case 0xD76C: +case 0xD96C: +case 0xDB6C: +case 0xDD6C: +case 0xDF6C: +case 0xD16D: +case 0xD36D: +case 0xD56D: +case 0xD76D: +case 0xD96D: +case 0xDB6D: +case 0xDD6D: +case 0xDF6D: +case 0xD16E: +case 0xD36E: +case 0xD56E: +case 0xD76E: +case 0xD96E: +case 0xDB6E: +case 0xDD6E: +case 0xDF6E: +case 0xD16F: +case 0xD36F: +case 0xD56F: +case 0xD76F: +case 0xD96F: +case 0xDB6F: +case 0xDD6F: +case 0xDF6F: + +// ADDDa +case 0xD168: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (u16)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, dst) + res = dst + src; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0xD370: +case 0xD570: +case 0xD770: +case 0xD970: +case 0xDB70: +case 0xDD70: +case 0xDF70: +case 0xD171: +case 0xD371: +case 0xD571: +case 0xD771: +case 0xD971: +case 0xDB71: +case 0xDD71: +case 0xDF71: +case 0xD172: +case 0xD372: +case 0xD572: +case 0xD772: +case 0xD972: +case 0xDB72: +case 0xDD72: +case 0xDF72: +case 0xD173: +case 0xD373: +case 0xD573: +case 0xD773: +case 0xD973: +case 0xDB73: +case 0xDD73: +case 0xDF73: +case 0xD174: +case 0xD374: +case 0xD574: +case 0xD774: +case 0xD974: +case 0xDB74: +case 0xDD74: +case 0xDF74: +case 0xD175: +case 0xD375: +case 0xD575: +case 0xD775: +case 0xD975: +case 0xDB75: +case 0xDD75: +case 0xDF75: +case 0xD176: +case 0xD376: +case 0xD576: +case 0xD776: +case 0xD976: +case 0xDB76: +case 0xDD76: +case 0xDF76: +case 0xD177: +case 0xD377: +case 0xD577: +case 0xD777: +case 0xD977: +case 0xDB77: +case 0xDD77: +case 0xDF77: + +// ADDDa +case 0xD170: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (u16)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, dst) + res = dst + src; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(18) +case 0xD378: +case 0xD578: +case 0xD778: +case 0xD978: +case 0xDB78: +case 0xDD78: +case 0xDF78: + +// ADDDa +case 0xD178: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (u16)CPU->D[(Opcode >> 9) & 7]; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, dst) + res = dst + src; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0xD379: +case 0xD579: +case 0xD779: +case 0xD979: +case 0xDB79: +case 0xDD79: +case 0xDF79: + +// ADDDa +case 0xD179: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (u16)CPU->D[(Opcode >> 9) & 7]; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_WORD_F(adr, dst) + res = dst + src; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(20) +case 0xD35F: +case 0xD55F: +case 0xD75F: +case 0xD95F: +case 0xDB5F: +case 0xDD5F: +case 0xDF5F: + +// ADDDa +case 0xD15F: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (u16)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_WORD_F(adr, dst) + res = dst + src; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0xD367: +case 0xD567: +case 0xD767: +case 0xD967: +case 0xDB67: +case 0xDD67: +case 0xDF67: + +// ADDDa +case 0xD167: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (u16)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_WORD_F(adr, dst) + res = dst + src; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ = res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(14) +case 0xD390: +case 0xD590: +case 0xD790: +case 0xD990: +case 0xDB90: +case 0xDD90: +case 0xDF90: +case 0xD191: +case 0xD391: +case 0xD591: +case 0xD791: +case 0xD991: +case 0xDB91: +case 0xDD91: +case 0xDF91: +case 0xD192: +case 0xD392: +case 0xD592: +case 0xD792: +case 0xD992: +case 0xDB92: +case 0xDD92: +case 0xDF92: +case 0xD193: +case 0xD393: +case 0xD593: +case 0xD793: +case 0xD993: +case 0xDB93: +case 0xDD93: +case 0xDF93: +case 0xD194: +case 0xD394: +case 0xD594: +case 0xD794: +case 0xD994: +case 0xDB94: +case 0xDD94: +case 0xDF94: +case 0xD195: +case 0xD395: +case 0xD595: +case 0xD795: +case 0xD995: +case 0xDB95: +case 0xDD95: +case 0xDF95: +case 0xD196: +case 0xD396: +case 0xD596: +case 0xD796: +case 0xD996: +case 0xDB96: +case 0xDD96: +case 0xDF96: +case 0xD197: +case 0xD397: +case 0xD597: +case 0xD797: +case 0xD997: +case 0xDB97: +case 0xDD97: +case 0xDF97: + +// ADDDa +case 0xD190: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (u32)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_LONG_F(adr, dst) + res = dst + src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(20) +case 0xD398: +case 0xD598: +case 0xD798: +case 0xD998: +case 0xDB98: +case 0xDD98: +case 0xDF98: +case 0xD199: +case 0xD399: +case 0xD599: +case 0xD799: +case 0xD999: +case 0xDB99: +case 0xDD99: +case 0xDF99: +case 0xD19A: +case 0xD39A: +case 0xD59A: +case 0xD79A: +case 0xD99A: +case 0xDB9A: +case 0xDD9A: +case 0xDF9A: +case 0xD19B: +case 0xD39B: +case 0xD59B: +case 0xD79B: +case 0xD99B: +case 0xDB9B: +case 0xDD9B: +case 0xDF9B: +case 0xD19C: +case 0xD39C: +case 0xD59C: +case 0xD79C: +case 0xD99C: +case 0xDB9C: +case 0xDD9C: +case 0xDF9C: +case 0xD19D: +case 0xD39D: +case 0xD59D: +case 0xD79D: +case 0xD99D: +case 0xDB9D: +case 0xDD9D: +case 0xDF9D: +case 0xD19E: +case 0xD39E: +case 0xD59E: +case 0xD79E: +case 0xD99E: +case 0xDB9E: +case 0xDD9E: +case 0xDF9E: + +// ADDDa +case 0xD198: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (u32)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 4; + PRE_IO + READ_LONG_F(adr, dst) + res = dst + src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(20) +case 0xD3A0: +case 0xD5A0: +case 0xD7A0: +case 0xD9A0: +case 0xDBA0: +case 0xDDA0: +case 0xDFA0: +case 0xD1A1: +case 0xD3A1: +case 0xD5A1: +case 0xD7A1: +case 0xD9A1: +case 0xDBA1: +case 0xDDA1: +case 0xDFA1: +case 0xD1A2: +case 0xD3A2: +case 0xD5A2: +case 0xD7A2: +case 0xD9A2: +case 0xDBA2: +case 0xDDA2: +case 0xDFA2: +case 0xD1A3: +case 0xD3A3: +case 0xD5A3: +case 0xD7A3: +case 0xD9A3: +case 0xDBA3: +case 0xDDA3: +case 0xDFA3: +case 0xD1A4: +case 0xD3A4: +case 0xD5A4: +case 0xD7A4: +case 0xD9A4: +case 0xDBA4: +case 0xDDA4: +case 0xDFA4: +case 0xD1A5: +case 0xD3A5: +case 0xD5A5: +case 0xD7A5: +case 0xD9A5: +case 0xDBA5: +case 0xDDA5: +case 0xDFA5: +case 0xD1A6: +case 0xD3A6: +case 0xD5A6: +case 0xD7A6: +case 0xD9A6: +case 0xDBA6: +case 0xDDA6: +case 0xDFA6: + +// ADDDa +case 0xD1A0: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (u32)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7] - 4; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_LONG_F(adr, dst) + res = dst + src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(22) +case 0xD3A8: +case 0xD5A8: +case 0xD7A8: +case 0xD9A8: +case 0xDBA8: +case 0xDDA8: +case 0xDFA8: +case 0xD1A9: +case 0xD3A9: +case 0xD5A9: +case 0xD7A9: +case 0xD9A9: +case 0xDBA9: +case 0xDDA9: +case 0xDFA9: +case 0xD1AA: +case 0xD3AA: +case 0xD5AA: +case 0xD7AA: +case 0xD9AA: +case 0xDBAA: +case 0xDDAA: +case 0xDFAA: +case 0xD1AB: +case 0xD3AB: +case 0xD5AB: +case 0xD7AB: +case 0xD9AB: +case 0xDBAB: +case 0xDDAB: +case 0xDFAB: +case 0xD1AC: +case 0xD3AC: +case 0xD5AC: +case 0xD7AC: +case 0xD9AC: +case 0xDBAC: +case 0xDDAC: +case 0xDFAC: +case 0xD1AD: +case 0xD3AD: +case 0xD5AD: +case 0xD7AD: +case 0xD9AD: +case 0xDBAD: +case 0xDDAD: +case 0xDFAD: +case 0xD1AE: +case 0xD3AE: +case 0xD5AE: +case 0xD7AE: +case 0xD9AE: +case 0xDBAE: +case 0xDDAE: +case 0xDFAE: +case 0xD1AF: +case 0xD3AF: +case 0xD5AF: +case 0xD7AF: +case 0xD9AF: +case 0xDBAF: +case 0xDDAF: +case 0xDFAF: + +// ADDDa +case 0xD1A8: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (u32)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, dst) + res = dst + src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(24) +case 0xD3B0: +case 0xD5B0: +case 0xD7B0: +case 0xD9B0: +case 0xDBB0: +case 0xDDB0: +case 0xDFB0: +case 0xD1B1: +case 0xD3B1: +case 0xD5B1: +case 0xD7B1: +case 0xD9B1: +case 0xDBB1: +case 0xDDB1: +case 0xDFB1: +case 0xD1B2: +case 0xD3B2: +case 0xD5B2: +case 0xD7B2: +case 0xD9B2: +case 0xDBB2: +case 0xDDB2: +case 0xDFB2: +case 0xD1B3: +case 0xD3B3: +case 0xD5B3: +case 0xD7B3: +case 0xD9B3: +case 0xDBB3: +case 0xDDB3: +case 0xDFB3: +case 0xD1B4: +case 0xD3B4: +case 0xD5B4: +case 0xD7B4: +case 0xD9B4: +case 0xDBB4: +case 0xDDB4: +case 0xDFB4: +case 0xD1B5: +case 0xD3B5: +case 0xD5B5: +case 0xD7B5: +case 0xD9B5: +case 0xDBB5: +case 0xDDB5: +case 0xDFB5: +case 0xD1B6: +case 0xD3B6: +case 0xD5B6: +case 0xD7B6: +case 0xD9B6: +case 0xDBB6: +case 0xDDB6: +case 0xDFB6: +case 0xD1B7: +case 0xD3B7: +case 0xD5B7: +case 0xD7B7: +case 0xD9B7: +case 0xDBB7: +case 0xDDB7: +case 0xDFB7: + +// ADDDa +case 0xD1B0: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (u32)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_LONG_F(adr, dst) + res = dst + src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(26) +case 0xD3B8: +case 0xD5B8: +case 0xD7B8: +case 0xD9B8: +case 0xDBB8: +case 0xDDB8: +case 0xDFB8: + +// ADDDa +case 0xD1B8: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (u32)CPU->D[(Opcode >> 9) & 7]; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_LONG_F(adr, dst) + res = dst + src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(24) +case 0xD3B9: +case 0xD5B9: +case 0xD7B9: +case 0xD9B9: +case 0xDBB9: +case 0xDDB9: +case 0xDFB9: + +// ADDDa +case 0xD1B9: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (u32)CPU->D[(Opcode >> 9) & 7]; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_LONG_F(adr, dst) + res = dst + src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(28) +case 0xD39F: +case 0xD59F: +case 0xD79F: +case 0xD99F: +case 0xDB9F: +case 0xDD9F: +case 0xDF9F: + +// ADDDa +case 0xD19F: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (u32)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[7]; + CPU->A[7] += 4; + PRE_IO + READ_LONG_F(adr, dst) + res = dst + src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(20) +case 0xD3A7: +case 0xD5A7: +case 0xD7A7: +case 0xD9A7: +case 0xDBA7: +case 0xDDA7: +case 0xDFA7: + +// ADDDa +case 0xD1A7: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + src = (u32)CPU->D[(Opcode >> 9) & 7]; + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + PRE_IO + READ_LONG_F(adr, dst) + res = dst + src; + CPU->flag_notZ = res; + CPU->flag_X = CPU->flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(22) +case 0xD300: +case 0xD500: +case 0xD700: +case 0xD900: +case 0xDB00: +case 0xDD00: +case 0xDF00: +case 0xD101: +case 0xD301: +case 0xD501: +case 0xD701: +case 0xD901: +case 0xDB01: +case 0xDD01: +case 0xDF01: +case 0xD102: +case 0xD302: +case 0xD502: +case 0xD702: +case 0xD902: +case 0xDB02: +case 0xDD02: +case 0xDF02: +case 0xD103: +case 0xD303: +case 0xD503: +case 0xD703: +case 0xD903: +case 0xDB03: +case 0xDD03: +case 0xDF03: +case 0xD104: +case 0xD304: +case 0xD504: +case 0xD704: +case 0xD904: +case 0xDB04: +case 0xDD04: +case 0xDF04: +case 0xD105: +case 0xD305: +case 0xD505: +case 0xD705: +case 0xD905: +case 0xDB05: +case 0xDD05: +case 0xDF05: +case 0xD106: +case 0xD306: +case 0xD506: +case 0xD706: +case 0xD906: +case 0xDB06: +case 0xDD06: +case 0xDF06: +case 0xD107: +case 0xD307: +case 0xD507: +case 0xD707: +case 0xD907: +case 0xDB07: +case 0xDD07: +case 0xDF07: + +// ADDX +case 0xD100: +{ + u32 res; + pointer dst; + pointer src; + src = (u8)CPU->D[(Opcode >> 0) & 7]; + dst = (u8)CPU->D[(Opcode >> 9) & 7]; + res = dst + src + ((CPU->flag_X >> 8) & 1); + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ res) & (dst ^ res); + CPU->flag_notZ |= res & 0xFF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 9) & 7])) = res; +} +RET(4) +case 0xD340: +case 0xD540: +case 0xD740: +case 0xD940: +case 0xDB40: +case 0xDD40: +case 0xDF40: +case 0xD141: +case 0xD341: +case 0xD541: +case 0xD741: +case 0xD941: +case 0xDB41: +case 0xDD41: +case 0xDF41: +case 0xD142: +case 0xD342: +case 0xD542: +case 0xD742: +case 0xD942: +case 0xDB42: +case 0xDD42: +case 0xDF42: +case 0xD143: +case 0xD343: +case 0xD543: +case 0xD743: +case 0xD943: +case 0xDB43: +case 0xDD43: +case 0xDF43: +case 0xD144: +case 0xD344: +case 0xD544: +case 0xD744: +case 0xD944: +case 0xDB44: +case 0xDD44: +case 0xDF44: +case 0xD145: +case 0xD345: +case 0xD545: +case 0xD745: +case 0xD945: +case 0xDB45: +case 0xDD45: +case 0xDF45: +case 0xD146: +case 0xD346: +case 0xD546: +case 0xD746: +case 0xD946: +case 0xDB46: +case 0xDD46: +case 0xDF46: +case 0xD147: +case 0xD347: +case 0xD547: +case 0xD747: +case 0xD947: +case 0xDB47: +case 0xDD47: +case 0xDF47: + +// ADDX +case 0xD140: +{ + u32 res; + pointer dst; + pointer src; + src = (u16)CPU->D[(Opcode >> 0) & 7]; + dst = (u16)CPU->D[(Opcode >> 9) & 7]; + res = dst + src + ((CPU->flag_X >> 8) & 1); + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ |= res & 0xFFFF; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 9) & 7])) = res; +} +RET(4) +case 0xD380: +case 0xD580: +case 0xD780: +case 0xD980: +case 0xDB80: +case 0xDD80: +case 0xDF80: +case 0xD181: +case 0xD381: +case 0xD581: +case 0xD781: +case 0xD981: +case 0xDB81: +case 0xDD81: +case 0xDF81: +case 0xD182: +case 0xD382: +case 0xD582: +case 0xD782: +case 0xD982: +case 0xDB82: +case 0xDD82: +case 0xDF82: +case 0xD183: +case 0xD383: +case 0xD583: +case 0xD783: +case 0xD983: +case 0xDB83: +case 0xDD83: +case 0xDF83: +case 0xD184: +case 0xD384: +case 0xD584: +case 0xD784: +case 0xD984: +case 0xDB84: +case 0xDD84: +case 0xDF84: +case 0xD185: +case 0xD385: +case 0xD585: +case 0xD785: +case 0xD985: +case 0xDB85: +case 0xDD85: +case 0xDF85: +case 0xD186: +case 0xD386: +case 0xD586: +case 0xD786: +case 0xD986: +case 0xDB86: +case 0xDD86: +case 0xDF86: +case 0xD187: +case 0xD387: +case 0xD587: +case 0xD787: +case 0xD987: +case 0xDB87: +case 0xDD87: +case 0xDF87: + +// ADDX +case 0xD180: +{ + u32 res; + pointer dst; + pointer src; + src = (u32)CPU->D[(Opcode >> 0) & 7]; + dst = (u32)CPU->D[(Opcode >> 9) & 7]; + res = dst + src + ((CPU->flag_X >> 8) & 1); + CPU->flag_notZ |= res; + CPU->flag_X = CPU->flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 24; + CPU->flag_N = res >> 24; + *((u32*)(&CPU->D[(Opcode >> 9) & 7])) = res; +} +RET(8) +case 0xD308: +case 0xD508: +case 0xD708: +case 0xD908: +case 0xDB08: +case 0xDD08: +case 0xD109: +case 0xD309: +case 0xD509: +case 0xD709: +case 0xD909: +case 0xDB09: +case 0xDD09: +case 0xD10A: +case 0xD30A: +case 0xD50A: +case 0xD70A: +case 0xD90A: +case 0xDB0A: +case 0xDD0A: +case 0xD10B: +case 0xD30B: +case 0xD50B: +case 0xD70B: +case 0xD90B: +case 0xDB0B: +case 0xDD0B: +case 0xD10C: +case 0xD30C: +case 0xD50C: +case 0xD70C: +case 0xD90C: +case 0xDB0C: +case 0xDD0C: +case 0xD10D: +case 0xD30D: +case 0xD50D: +case 0xD70D: +case 0xD90D: +case 0xDB0D: +case 0xDD0D: +case 0xD10E: +case 0xD30E: +case 0xD50E: +case 0xD70E: +case 0xD90E: +case 0xDB0E: +case 0xDD0E: + +// ADDXM +case 0xD108: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_BYTE_F(adr, src) + adr = CPU->A[(Opcode >> 9) & 7] - 1; + CPU->A[(Opcode >> 9) & 7] = adr; + READ_BYTE_F(adr, dst) + res = dst + src + ((CPU->flag_X >> 8) & 1); + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ res) & (dst ^ res); + CPU->flag_notZ |= res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) +case 0xD348: +case 0xD548: +case 0xD748: +case 0xD948: +case 0xDB48: +case 0xDD48: +case 0xD149: +case 0xD349: +case 0xD549: +case 0xD749: +case 0xD949: +case 0xDB49: +case 0xDD49: +case 0xD14A: +case 0xD34A: +case 0xD54A: +case 0xD74A: +case 0xD94A: +case 0xDB4A: +case 0xDD4A: +case 0xD14B: +case 0xD34B: +case 0xD54B: +case 0xD74B: +case 0xD94B: +case 0xDB4B: +case 0xDD4B: +case 0xD14C: +case 0xD34C: +case 0xD54C: +case 0xD74C: +case 0xD94C: +case 0xDB4C: +case 0xDD4C: +case 0xD14D: +case 0xD34D: +case 0xD54D: +case 0xD74D: +case 0xD94D: +case 0xDB4D: +case 0xDD4D: +case 0xD14E: +case 0xD34E: +case 0xD54E: +case 0xD74E: +case 0xD94E: +case 0xDB4E: +case 0xDD4E: + +// ADDXM +case 0xD148: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 2; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_WORD_F(adr, src) + adr = CPU->A[(Opcode >> 9) & 7] - 2; + CPU->A[(Opcode >> 9) & 7] = adr; + READ_WORD_F(adr, dst) + res = dst + src + ((CPU->flag_X >> 8) & 1); + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ |= res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(18) +case 0xD388: +case 0xD588: +case 0xD788: +case 0xD988: +case 0xDB88: +case 0xDD88: +case 0xD189: +case 0xD389: +case 0xD589: +case 0xD789: +case 0xD989: +case 0xDB89: +case 0xDD89: +case 0xD18A: +case 0xD38A: +case 0xD58A: +case 0xD78A: +case 0xD98A: +case 0xDB8A: +case 0xDD8A: +case 0xD18B: +case 0xD38B: +case 0xD58B: +case 0xD78B: +case 0xD98B: +case 0xDB8B: +case 0xDD8B: +case 0xD18C: +case 0xD38C: +case 0xD58C: +case 0xD78C: +case 0xD98C: +case 0xDB8C: +case 0xDD8C: +case 0xD18D: +case 0xD38D: +case 0xD58D: +case 0xD78D: +case 0xD98D: +case 0xDB8D: +case 0xDD8D: +case 0xD18E: +case 0xD38E: +case 0xD58E: +case 0xD78E: +case 0xD98E: +case 0xDB8E: +case 0xDD8E: + +// ADDXM +case 0xD188: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 4; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_LONG_F(adr, src) + adr = CPU->A[(Opcode >> 9) & 7] - 4; + CPU->A[(Opcode >> 9) & 7] = adr; + READ_LONG_F(adr, dst) + res = dst + src + ((CPU->flag_X >> 8) & 1); + CPU->flag_notZ |= res; + CPU->flag_X = CPU->flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(30) +case 0xD30F: +case 0xD50F: +case 0xD70F: +case 0xD90F: +case 0xDB0F: +case 0xDD0F: + +// ADDX7M +case 0xD10F: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_BYTE_F(adr, src) + adr = CPU->A[(Opcode >> 9) & 7] - 1; + CPU->A[(Opcode >> 9) & 7] = adr; + READ_BYTE_F(adr, dst) + res = dst + src + ((CPU->flag_X >> 8) & 1); + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ res) & (dst ^ res); + CPU->flag_notZ |= res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) +case 0xD34F: +case 0xD54F: +case 0xD74F: +case 0xD94F: +case 0xDB4F: +case 0xDD4F: + +// ADDX7M +case 0xD14F: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_WORD_F(adr, src) + adr = CPU->A[(Opcode >> 9) & 7] - 2; + CPU->A[(Opcode >> 9) & 7] = adr; + READ_WORD_F(adr, dst) + res = dst + src + ((CPU->flag_X >> 8) & 1); + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ |= res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(18) +case 0xD38F: +case 0xD58F: +case 0xD78F: +case 0xD98F: +case 0xDB8F: +case 0xDD8F: + +// ADDX7M +case 0xD18F: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + PRE_IO + READ_LONG_F(adr, src) + adr = CPU->A[(Opcode >> 9) & 7] - 4; + CPU->A[(Opcode >> 9) & 7] = adr; + READ_LONG_F(adr, dst) + res = dst + src + ((CPU->flag_X >> 8) & 1); + CPU->flag_notZ |= res; + CPU->flag_X = CPU->flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(30) +case 0xDF09: +case 0xDF0A: +case 0xDF0B: +case 0xDF0C: +case 0xDF0D: +case 0xDF0E: + +// ADDXM7 +case 0xDF08: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 1; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_BYTE_F(adr, src) + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + READ_BYTE_F(adr, dst) + res = dst + src + ((CPU->flag_X >> 8) & 1); + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ res) & (dst ^ res); + CPU->flag_notZ |= res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) +case 0xDF49: +case 0xDF4A: +case 0xDF4B: +case 0xDF4C: +case 0xDF4D: +case 0xDF4E: + +// ADDXM7 +case 0xDF48: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 2; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_WORD_F(adr, src) + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + READ_WORD_F(adr, dst) + res = dst + src + ((CPU->flag_X >> 8) & 1); + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ |= res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(18) +case 0xDF89: +case 0xDF8A: +case 0xDF8B: +case 0xDF8C: +case 0xDF8D: +case 0xDF8E: + +// ADDXM7 +case 0xDF88: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 4; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_LONG_F(adr, src) + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + READ_LONG_F(adr, dst) + res = dst + src + ((CPU->flag_X >> 8) & 1); + CPU->flag_notZ |= res; + CPU->flag_X = CPU->flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(30) + +// ADDX7M7 +case 0xDF0F: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_BYTE_F(adr, src) + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + READ_BYTE_F(adr, dst) + res = dst + src + ((CPU->flag_X >> 8) & 1); + CPU->flag_N = CPU->flag_X = CPU->flag_C = res; + CPU->flag_V = (src ^ res) & (dst ^ res); + CPU->flag_notZ |= res & 0xFF; + WRITE_BYTE_F(adr, res) + POST_IO +} +RET(18) + +// ADDX7M7 +case 0xDF4F: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_WORD_F(adr, src) + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + READ_WORD_F(adr, dst) + res = dst + src + ((CPU->flag_X >> 8) & 1); + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 8; + CPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_notZ |= res & 0xFFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(18) + +// ADDX7M7 +case 0xDF8F: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + PRE_IO + READ_LONG_F(adr, src) + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + READ_LONG_F(adr, dst) + res = dst + src + ((CPU->flag_X >> 8) & 1); + CPU->flag_notZ |= res; + CPU->flag_X = CPU->flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23; + CPU->flag_V = ((src ^ res) & (dst ^ res)) >> 24; + CPU->flag_N = res >> 24; + WRITE_LONG_F(adr, res) + POST_IO +} +RET(30) +case 0xD2C0: +case 0xD4C0: +case 0xD6C0: +case 0xD8C0: +case 0xDAC0: +case 0xDCC0: +case 0xDEC0: +case 0xD0C1: +case 0xD2C1: +case 0xD4C1: +case 0xD6C1: +case 0xD8C1: +case 0xDAC1: +case 0xDCC1: +case 0xDEC1: +case 0xD0C2: +case 0xD2C2: +case 0xD4C2: +case 0xD6C2: +case 0xD8C2: +case 0xDAC2: +case 0xDCC2: +case 0xDEC2: +case 0xD0C3: +case 0xD2C3: +case 0xD4C3: +case 0xD6C3: +case 0xD8C3: +case 0xDAC3: +case 0xDCC3: +case 0xDEC3: +case 0xD0C4: +case 0xD2C4: +case 0xD4C4: +case 0xD6C4: +case 0xD8C4: +case 0xDAC4: +case 0xDCC4: +case 0xDEC4: +case 0xD0C5: +case 0xD2C5: +case 0xD4C5: +case 0xD6C5: +case 0xD8C5: +case 0xDAC5: +case 0xDCC5: +case 0xDEC5: +case 0xD0C6: +case 0xD2C6: +case 0xD4C6: +case 0xD6C6: +case 0xD8C6: +case 0xDAC6: +case 0xDCC6: +case 0xDEC6: +case 0xD0C7: +case 0xD2C7: +case 0xD4C7: +case 0xD6C7: +case 0xD8C7: +case 0xDAC7: +case 0xDCC7: +case 0xDEC7: + +// ADDA +case 0xD0C0: +{ + u32 res; + pointer dst; + pointer src; + src = (s32)(s16)CPU->D[(Opcode >> 0) & 7]; + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst + src; + CPU->A[(Opcode >> 9) & 7] = res; +} +RET(8) +case 0xD2C8: +case 0xD4C8: +case 0xD6C8: +case 0xD8C8: +case 0xDAC8: +case 0xDCC8: +case 0xDEC8: +case 0xD0C9: +case 0xD2C9: +case 0xD4C9: +case 0xD6C9: +case 0xD8C9: +case 0xDAC9: +case 0xDCC9: +case 0xDEC9: +case 0xD0CA: +case 0xD2CA: +case 0xD4CA: +case 0xD6CA: +case 0xD8CA: +case 0xDACA: +case 0xDCCA: +case 0xDECA: +case 0xD0CB: +case 0xD2CB: +case 0xD4CB: +case 0xD6CB: +case 0xD8CB: +case 0xDACB: +case 0xDCCB: +case 0xDECB: +case 0xD0CC: +case 0xD2CC: +case 0xD4CC: +case 0xD6CC: +case 0xD8CC: +case 0xDACC: +case 0xDCCC: +case 0xDECC: +case 0xD0CD: +case 0xD2CD: +case 0xD4CD: +case 0xD6CD: +case 0xD8CD: +case 0xDACD: +case 0xDCCD: +case 0xDECD: +case 0xD0CE: +case 0xD2CE: +case 0xD4CE: +case 0xD6CE: +case 0xD8CE: +case 0xDACE: +case 0xDCCE: +case 0xDECE: +case 0xD0CF: +case 0xD2CF: +case 0xD4CF: +case 0xD6CF: +case 0xD8CF: +case 0xDACF: +case 0xDCCF: +case 0xDECF: + +// ADDA +case 0xD0C8: +{ + u32 res; + pointer dst; + pointer src; + src = (s32)(s16)CPU->A[(Opcode >> 0) & 7]; + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst + src; + CPU->A[(Opcode >> 9) & 7] = res; +} +RET(8) +case 0xD2D0: +case 0xD4D0: +case 0xD6D0: +case 0xD8D0: +case 0xDAD0: +case 0xDCD0: +case 0xDED0: +case 0xD0D1: +case 0xD2D1: +case 0xD4D1: +case 0xD6D1: +case 0xD8D1: +case 0xDAD1: +case 0xDCD1: +case 0xDED1: +case 0xD0D2: +case 0xD2D2: +case 0xD4D2: +case 0xD6D2: +case 0xD8D2: +case 0xDAD2: +case 0xDCD2: +case 0xDED2: +case 0xD0D3: +case 0xD2D3: +case 0xD4D3: +case 0xD6D3: +case 0xD8D3: +case 0xDAD3: +case 0xDCD3: +case 0xDED3: +case 0xD0D4: +case 0xD2D4: +case 0xD4D4: +case 0xD6D4: +case 0xD8D4: +case 0xDAD4: +case 0xDCD4: +case 0xDED4: +case 0xD0D5: +case 0xD2D5: +case 0xD4D5: +case 0xD6D5: +case 0xD8D5: +case 0xDAD5: +case 0xDCD5: +case 0xDED5: +case 0xD0D6: +case 0xD2D6: +case 0xD4D6: +case 0xD6D6: +case 0xD8D6: +case 0xDAD6: +case 0xDCD6: +case 0xDED6: +case 0xD0D7: +case 0xD2D7: +case 0xD4D7: +case 0xD6D7: +case 0xD8D7: +case 0xDAD7: +case 0xDCD7: +case 0xDED7: + +// ADDA +case 0xD0D0: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READSX_WORD_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst + src; + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(12) +case 0xD2D8: +case 0xD4D8: +case 0xD6D8: +case 0xD8D8: +case 0xDAD8: +case 0xDCD8: +case 0xDED8: +case 0xD0D9: +case 0xD2D9: +case 0xD4D9: +case 0xD6D9: +case 0xD8D9: +case 0xDAD9: +case 0xDCD9: +case 0xDED9: +case 0xD0DA: +case 0xD2DA: +case 0xD4DA: +case 0xD6DA: +case 0xD8DA: +case 0xDADA: +case 0xDCDA: +case 0xDEDA: +case 0xD0DB: +case 0xD2DB: +case 0xD4DB: +case 0xD6DB: +case 0xD8DB: +case 0xDADB: +case 0xDCDB: +case 0xDEDB: +case 0xD0DC: +case 0xD2DC: +case 0xD4DC: +case 0xD6DC: +case 0xD8DC: +case 0xDADC: +case 0xDCDC: +case 0xDEDC: +case 0xD0DD: +case 0xD2DD: +case 0xD4DD: +case 0xD6DD: +case 0xD8DD: +case 0xDADD: +case 0xDCDD: +case 0xDEDD: +case 0xD0DE: +case 0xD2DE: +case 0xD4DE: +case 0xD6DE: +case 0xD8DE: +case 0xDADE: +case 0xDCDE: +case 0xDEDE: + +// ADDA +case 0xD0D8: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 2; + PRE_IO + READSX_WORD_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst + src; + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(12) +case 0xD2E0: +case 0xD4E0: +case 0xD6E0: +case 0xD8E0: +case 0xDAE0: +case 0xDCE0: +case 0xDEE0: +case 0xD0E1: +case 0xD2E1: +case 0xD4E1: +case 0xD6E1: +case 0xD8E1: +case 0xDAE1: +case 0xDCE1: +case 0xDEE1: +case 0xD0E2: +case 0xD2E2: +case 0xD4E2: +case 0xD6E2: +case 0xD8E2: +case 0xDAE2: +case 0xDCE2: +case 0xDEE2: +case 0xD0E3: +case 0xD2E3: +case 0xD4E3: +case 0xD6E3: +case 0xD8E3: +case 0xDAE3: +case 0xDCE3: +case 0xDEE3: +case 0xD0E4: +case 0xD2E4: +case 0xD4E4: +case 0xD6E4: +case 0xD8E4: +case 0xDAE4: +case 0xDCE4: +case 0xDEE4: +case 0xD0E5: +case 0xD2E5: +case 0xD4E5: +case 0xD6E5: +case 0xD8E5: +case 0xDAE5: +case 0xDCE5: +case 0xDEE5: +case 0xD0E6: +case 0xD2E6: +case 0xD4E6: +case 0xD6E6: +case 0xD8E6: +case 0xDAE6: +case 0xDCE6: +case 0xDEE6: + +// ADDA +case 0xD0E0: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 2; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READSX_WORD_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst + src; + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(14) +case 0xD2E8: +case 0xD4E8: +case 0xD6E8: +case 0xD8E8: +case 0xDAE8: +case 0xDCE8: +case 0xDEE8: +case 0xD0E9: +case 0xD2E9: +case 0xD4E9: +case 0xD6E9: +case 0xD8E9: +case 0xDAE9: +case 0xDCE9: +case 0xDEE9: +case 0xD0EA: +case 0xD2EA: +case 0xD4EA: +case 0xD6EA: +case 0xD8EA: +case 0xDAEA: +case 0xDCEA: +case 0xDEEA: +case 0xD0EB: +case 0xD2EB: +case 0xD4EB: +case 0xD6EB: +case 0xD8EB: +case 0xDAEB: +case 0xDCEB: +case 0xDEEB: +case 0xD0EC: +case 0xD2EC: +case 0xD4EC: +case 0xD6EC: +case 0xD8EC: +case 0xDAEC: +case 0xDCEC: +case 0xDEEC: +case 0xD0ED: +case 0xD2ED: +case 0xD4ED: +case 0xD6ED: +case 0xD8ED: +case 0xDAED: +case 0xDCED: +case 0xDEED: +case 0xD0EE: +case 0xD2EE: +case 0xD4EE: +case 0xD6EE: +case 0xD8EE: +case 0xDAEE: +case 0xDCEE: +case 0xDEEE: +case 0xD0EF: +case 0xD2EF: +case 0xD4EF: +case 0xD6EF: +case 0xD8EF: +case 0xDAEF: +case 0xDCEF: +case 0xDEEF: + +// ADDA +case 0xD0E8: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READSX_WORD_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst + src; + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(16) +case 0xD2F0: +case 0xD4F0: +case 0xD6F0: +case 0xD8F0: +case 0xDAF0: +case 0xDCF0: +case 0xDEF0: +case 0xD0F1: +case 0xD2F1: +case 0xD4F1: +case 0xD6F1: +case 0xD8F1: +case 0xDAF1: +case 0xDCF1: +case 0xDEF1: +case 0xD0F2: +case 0xD2F2: +case 0xD4F2: +case 0xD6F2: +case 0xD8F2: +case 0xDAF2: +case 0xDCF2: +case 0xDEF2: +case 0xD0F3: +case 0xD2F3: +case 0xD4F3: +case 0xD6F3: +case 0xD8F3: +case 0xDAF3: +case 0xDCF3: +case 0xDEF3: +case 0xD0F4: +case 0xD2F4: +case 0xD4F4: +case 0xD6F4: +case 0xD8F4: +case 0xDAF4: +case 0xDCF4: +case 0xDEF4: +case 0xD0F5: +case 0xD2F5: +case 0xD4F5: +case 0xD6F5: +case 0xD8F5: +case 0xDAF5: +case 0xDCF5: +case 0xDEF5: +case 0xD0F6: +case 0xD2F6: +case 0xD4F6: +case 0xD6F6: +case 0xD8F6: +case 0xDAF6: +case 0xDCF6: +case 0xDEF6: +case 0xD0F7: +case 0xD2F7: +case 0xD4F7: +case 0xD6F7: +case 0xD8F7: +case 0xDAF7: +case 0xDCF7: +case 0xDEF7: + +// ADDA +case 0xD0F0: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READSX_WORD_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst + src; + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(18) +case 0xD2F8: +case 0xD4F8: +case 0xD6F8: +case 0xD8F8: +case 0xDAF8: +case 0xDCF8: +case 0xDEF8: + +// ADDA +case 0xD0F8: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READSX_WORD_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst + src; + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(16) +case 0xD2F9: +case 0xD4F9: +case 0xD6F9: +case 0xD8F9: +case 0xDAF9: +case 0xDCF9: +case 0xDEF9: + +// ADDA +case 0xD0F9: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READSX_WORD_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst + src; + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(20) +case 0xD2FA: +case 0xD4FA: +case 0xD6FA: +case 0xD8FA: +case 0xDAFA: +case 0xDCFA: +case 0xDEFA: + +// ADDA +case 0xD0FA: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READSX_WORD_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst + src; + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(16) +case 0xD2FB: +case 0xD4FB: +case 0xD6FB: +case 0xD8FB: +case 0xDAFB: +case 0xDCFB: +case 0xDEFB: + +// ADDA +case 0xD0FB: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READSX_WORD_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst + src; + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(18) +case 0xD2FC: +case 0xD4FC: +case 0xD6FC: +case 0xD8FC: +case 0xDAFC: +case 0xDCFC: +case 0xDEFC: + +// ADDA +case 0xD0FC: +{ + u32 res; + pointer dst; + pointer src; + src = (s32)(s16)FETCH_WORD; + PC += 2; + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst + src; + CPU->A[(Opcode >> 9) & 7] = res; +} +RET(12) +case 0xD2DF: +case 0xD4DF: +case 0xD6DF: +case 0xD8DF: +case 0xDADF: +case 0xDCDF: +case 0xDEDF: + +// ADDA +case 0xD0DF: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READSX_WORD_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst + src; + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(12) +case 0xD2E7: +case 0xD4E7: +case 0xD6E7: +case 0xD8E7: +case 0xDAE7: +case 0xDCE7: +case 0xDEE7: + +// ADDA +case 0xD0E7: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READSX_WORD_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst + src; + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(14) +case 0xD3C0: +case 0xD5C0: +case 0xD7C0: +case 0xD9C0: +case 0xDBC0: +case 0xDDC0: +case 0xDFC0: +case 0xD1C1: +case 0xD3C1: +case 0xD5C1: +case 0xD7C1: +case 0xD9C1: +case 0xDBC1: +case 0xDDC1: +case 0xDFC1: +case 0xD1C2: +case 0xD3C2: +case 0xD5C2: +case 0xD7C2: +case 0xD9C2: +case 0xDBC2: +case 0xDDC2: +case 0xDFC2: +case 0xD1C3: +case 0xD3C3: +case 0xD5C3: +case 0xD7C3: +case 0xD9C3: +case 0xDBC3: +case 0xDDC3: +case 0xDFC3: +case 0xD1C4: +case 0xD3C4: +case 0xD5C4: +case 0xD7C4: +case 0xD9C4: +case 0xDBC4: +case 0xDDC4: +case 0xDFC4: +case 0xD1C5: +case 0xD3C5: +case 0xD5C5: +case 0xD7C5: +case 0xD9C5: +case 0xDBC5: +case 0xDDC5: +case 0xDFC5: +case 0xD1C6: +case 0xD3C6: +case 0xD5C6: +case 0xD7C6: +case 0xD9C6: +case 0xDBC6: +case 0xDDC6: +case 0xDFC6: +case 0xD1C7: +case 0xD3C7: +case 0xD5C7: +case 0xD7C7: +case 0xD9C7: +case 0xDBC7: +case 0xDDC7: +case 0xDFC7: + +// ADDA +case 0xD1C0: +{ + u32 res; + pointer dst; + pointer src; + src = (s32)(s32)CPU->D[(Opcode >> 0) & 7]; + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst + src; + CPU->A[(Opcode >> 9) & 7] = res; +} +RET(6) +case 0xD3C8: +case 0xD5C8: +case 0xD7C8: +case 0xD9C8: +case 0xDBC8: +case 0xDDC8: +case 0xDFC8: +case 0xD1C9: +case 0xD3C9: +case 0xD5C9: +case 0xD7C9: +case 0xD9C9: +case 0xDBC9: +case 0xDDC9: +case 0xDFC9: +case 0xD1CA: +case 0xD3CA: +case 0xD5CA: +case 0xD7CA: +case 0xD9CA: +case 0xDBCA: +case 0xDDCA: +case 0xDFCA: +case 0xD1CB: +case 0xD3CB: +case 0xD5CB: +case 0xD7CB: +case 0xD9CB: +case 0xDBCB: +case 0xDDCB: +case 0xDFCB: +case 0xD1CC: +case 0xD3CC: +case 0xD5CC: +case 0xD7CC: +case 0xD9CC: +case 0xDBCC: +case 0xDDCC: +case 0xDFCC: +case 0xD1CD: +case 0xD3CD: +case 0xD5CD: +case 0xD7CD: +case 0xD9CD: +case 0xDBCD: +case 0xDDCD: +case 0xDFCD: +case 0xD1CE: +case 0xD3CE: +case 0xD5CE: +case 0xD7CE: +case 0xD9CE: +case 0xDBCE: +case 0xDDCE: +case 0xDFCE: +case 0xD1CF: +case 0xD3CF: +case 0xD5CF: +case 0xD7CF: +case 0xD9CF: +case 0xDBCF: +case 0xDDCF: +case 0xDFCF: + +// ADDA +case 0xD1C8: +{ + u32 res; + pointer dst; + pointer src; + src = (s32)(s32)CPU->A[(Opcode >> 0) & 7]; + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst + src; + CPU->A[(Opcode >> 9) & 7] = res; +} +RET(6) +case 0xD3D0: +case 0xD5D0: +case 0xD7D0: +case 0xD9D0: +case 0xDBD0: +case 0xDDD0: +case 0xDFD0: +case 0xD1D1: +case 0xD3D1: +case 0xD5D1: +case 0xD7D1: +case 0xD9D1: +case 0xDBD1: +case 0xDDD1: +case 0xDFD1: +case 0xD1D2: +case 0xD3D2: +case 0xD5D2: +case 0xD7D2: +case 0xD9D2: +case 0xDBD2: +case 0xDDD2: +case 0xDFD2: +case 0xD1D3: +case 0xD3D3: +case 0xD5D3: +case 0xD7D3: +case 0xD9D3: +case 0xDBD3: +case 0xDDD3: +case 0xDFD3: +case 0xD1D4: +case 0xD3D4: +case 0xD5D4: +case 0xD7D4: +case 0xD9D4: +case 0xDBD4: +case 0xDDD4: +case 0xDFD4: +case 0xD1D5: +case 0xD3D5: +case 0xD5D5: +case 0xD7D5: +case 0xD9D5: +case 0xDBD5: +case 0xDDD5: +case 0xDFD5: +case 0xD1D6: +case 0xD3D6: +case 0xD5D6: +case 0xD7D6: +case 0xD9D6: +case 0xDBD6: +case 0xDDD6: +case 0xDFD6: +case 0xD1D7: +case 0xD3D7: +case 0xD5D7: +case 0xD7D7: +case 0xD9D7: +case 0xDBD7: +case 0xDDD7: +case 0xDFD7: + +// ADDA +case 0xD1D0: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READSX_LONG_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst + src; + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(16) +case 0xD3D8: +case 0xD5D8: +case 0xD7D8: +case 0xD9D8: +case 0xDBD8: +case 0xDDD8: +case 0xDFD8: +case 0xD1D9: +case 0xD3D9: +case 0xD5D9: +case 0xD7D9: +case 0xD9D9: +case 0xDBD9: +case 0xDDD9: +case 0xDFD9: +case 0xD1DA: +case 0xD3DA: +case 0xD5DA: +case 0xD7DA: +case 0xD9DA: +case 0xDBDA: +case 0xDDDA: +case 0xDFDA: +case 0xD1DB: +case 0xD3DB: +case 0xD5DB: +case 0xD7DB: +case 0xD9DB: +case 0xDBDB: +case 0xDDDB: +case 0xDFDB: +case 0xD1DC: +case 0xD3DC: +case 0xD5DC: +case 0xD7DC: +case 0xD9DC: +case 0xDBDC: +case 0xDDDC: +case 0xDFDC: +case 0xD1DD: +case 0xD3DD: +case 0xD5DD: +case 0xD7DD: +case 0xD9DD: +case 0xDBDD: +case 0xDDDD: +case 0xDFDD: +case 0xD1DE: +case 0xD3DE: +case 0xD5DE: +case 0xD7DE: +case 0xD9DE: +case 0xDBDE: +case 0xDDDE: +case 0xDFDE: + +// ADDA +case 0xD1D8: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 4; + PRE_IO + READSX_LONG_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst + src; + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(16) +case 0xD3E0: +case 0xD5E0: +case 0xD7E0: +case 0xD9E0: +case 0xDBE0: +case 0xDDE0: +case 0xDFE0: +case 0xD1E1: +case 0xD3E1: +case 0xD5E1: +case 0xD7E1: +case 0xD9E1: +case 0xDBE1: +case 0xDDE1: +case 0xDFE1: +case 0xD1E2: +case 0xD3E2: +case 0xD5E2: +case 0xD7E2: +case 0xD9E2: +case 0xDBE2: +case 0xDDE2: +case 0xDFE2: +case 0xD1E3: +case 0xD3E3: +case 0xD5E3: +case 0xD7E3: +case 0xD9E3: +case 0xDBE3: +case 0xDDE3: +case 0xDFE3: +case 0xD1E4: +case 0xD3E4: +case 0xD5E4: +case 0xD7E4: +case 0xD9E4: +case 0xDBE4: +case 0xDDE4: +case 0xDFE4: +case 0xD1E5: +case 0xD3E5: +case 0xD5E5: +case 0xD7E5: +case 0xD9E5: +case 0xDBE5: +case 0xDDE5: +case 0xDFE5: +case 0xD1E6: +case 0xD3E6: +case 0xD5E6: +case 0xD7E6: +case 0xD9E6: +case 0xDBE6: +case 0xDDE6: +case 0xDFE6: + +// ADDA +case 0xD1E0: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 4; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READSX_LONG_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst + src; + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(18) +case 0xD3E8: +case 0xD5E8: +case 0xD7E8: +case 0xD9E8: +case 0xDBE8: +case 0xDDE8: +case 0xDFE8: +case 0xD1E9: +case 0xD3E9: +case 0xD5E9: +case 0xD7E9: +case 0xD9E9: +case 0xDBE9: +case 0xDDE9: +case 0xDFE9: +case 0xD1EA: +case 0xD3EA: +case 0xD5EA: +case 0xD7EA: +case 0xD9EA: +case 0xDBEA: +case 0xDDEA: +case 0xDFEA: +case 0xD1EB: +case 0xD3EB: +case 0xD5EB: +case 0xD7EB: +case 0xD9EB: +case 0xDBEB: +case 0xDDEB: +case 0xDFEB: +case 0xD1EC: +case 0xD3EC: +case 0xD5EC: +case 0xD7EC: +case 0xD9EC: +case 0xDBEC: +case 0xDDEC: +case 0xDFEC: +case 0xD1ED: +case 0xD3ED: +case 0xD5ED: +case 0xD7ED: +case 0xD9ED: +case 0xDBED: +case 0xDDED: +case 0xDFED: +case 0xD1EE: +case 0xD3EE: +case 0xD5EE: +case 0xD7EE: +case 0xD9EE: +case 0xDBEE: +case 0xDDEE: +case 0xDFEE: +case 0xD1EF: +case 0xD3EF: +case 0xD5EF: +case 0xD7EF: +case 0xD9EF: +case 0xDBEF: +case 0xDDEF: +case 0xDFEF: + +// ADDA +case 0xD1E8: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READSX_LONG_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst + src; + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(20) +case 0xD3F0: +case 0xD5F0: +case 0xD7F0: +case 0xD9F0: +case 0xDBF0: +case 0xDDF0: +case 0xDFF0: +case 0xD1F1: +case 0xD3F1: +case 0xD5F1: +case 0xD7F1: +case 0xD9F1: +case 0xDBF1: +case 0xDDF1: +case 0xDFF1: +case 0xD1F2: +case 0xD3F2: +case 0xD5F2: +case 0xD7F2: +case 0xD9F2: +case 0xDBF2: +case 0xDDF2: +case 0xDFF2: +case 0xD1F3: +case 0xD3F3: +case 0xD5F3: +case 0xD7F3: +case 0xD9F3: +case 0xDBF3: +case 0xDDF3: +case 0xDFF3: +case 0xD1F4: +case 0xD3F4: +case 0xD5F4: +case 0xD7F4: +case 0xD9F4: +case 0xDBF4: +case 0xDDF4: +case 0xDFF4: +case 0xD1F5: +case 0xD3F5: +case 0xD5F5: +case 0xD7F5: +case 0xD9F5: +case 0xDBF5: +case 0xDDF5: +case 0xDFF5: +case 0xD1F6: +case 0xD3F6: +case 0xD5F6: +case 0xD7F6: +case 0xD9F6: +case 0xDBF6: +case 0xDDF6: +case 0xDFF6: +case 0xD1F7: +case 0xD3F7: +case 0xD5F7: +case 0xD7F7: +case 0xD9F7: +case 0xDBF7: +case 0xDDF7: +case 0xDFF7: + +// ADDA +case 0xD1F0: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READSX_LONG_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst + src; + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(22) +case 0xD3F8: +case 0xD5F8: +case 0xD7F8: +case 0xD9F8: +case 0xDBF8: +case 0xDDF8: +case 0xDFF8: + +// ADDA +case 0xD1F8: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READSX_LONG_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst + src; + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(20) +case 0xD3F9: +case 0xD5F9: +case 0xD7F9: +case 0xD9F9: +case 0xDBF9: +case 0xDDF9: +case 0xDFF9: + +// ADDA +case 0xD1F9: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READSX_LONG_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst + src; + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(24) +case 0xD3FA: +case 0xD5FA: +case 0xD7FA: +case 0xD9FA: +case 0xDBFA: +case 0xDDFA: +case 0xDFFA: + +// ADDA +case 0xD1FA: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READSX_LONG_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst + src; + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(20) +case 0xD3FB: +case 0xD5FB: +case 0xD7FB: +case 0xD9FB: +case 0xDBFB: +case 0xDDFB: +case 0xDFFB: + +// ADDA +case 0xD1FB: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = PC - CPU->BasePC; + DECODE_EXT_WORD + PRE_IO + READSX_LONG_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst + src; + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(22) +case 0xD3FC: +case 0xD5FC: +case 0xD7FC: +case 0xD9FC: +case 0xDBFC: +case 0xDDFC: +case 0xDFFC: + +// ADDA +case 0xD1FC: +{ + u32 res; + pointer dst; + pointer src; + src = (s32)(s32)FETCH_LONG; + PC += 4; + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst + src; + CPU->A[(Opcode >> 9) & 7] = res; +} +RET(14) +case 0xD3DF: +case 0xD5DF: +case 0xD7DF: +case 0xD9DF: +case 0xDBDF: +case 0xDDDF: +case 0xDFDF: + +// ADDA +case 0xD1DF: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[7]; + CPU->A[7] += 4; + PRE_IO + READSX_LONG_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst + src; + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(16) +case 0xD3E7: +case 0xD5E7: +case 0xD7E7: +case 0xD9E7: +case 0xDBE7: +case 0xDDE7: +case 0xDFE7: + +// ADDA +case 0xD1E7: +{ + u32 adr; + u32 res; + pointer dst; + pointer src; + adr = CPU->A[7] - 4; + CPU->A[7] = adr; + PRE_IO + READSX_LONG_F(adr, src) + dst = (u32)CPU->A[(Opcode >> 9) & 7]; + res = dst + src; + CPU->A[(Opcode >> 9) & 7] = res; + POST_IO +} +RET(18) diff --git a/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68k_opE.inc b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68k_opE.inc new file mode 100644 index 000000000..b7f6a11a4 --- /dev/null +++ b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68k_opE.inc @@ -0,0 +1,6130 @@ +case 0xE200: +case 0xE400: +case 0xE600: +case 0xE800: +case 0xEA00: +case 0xEC00: +case 0xEE00: +case 0xE001: +case 0xE201: +case 0xE401: +case 0xE601: +case 0xE801: +case 0xEA01: +case 0xEC01: +case 0xEE01: +case 0xE002: +case 0xE202: +case 0xE402: +case 0xE602: +case 0xE802: +case 0xEA02: +case 0xEC02: +case 0xEE02: +case 0xE003: +case 0xE203: +case 0xE403: +case 0xE603: +case 0xE803: +case 0xEA03: +case 0xEC03: +case 0xEE03: +case 0xE004: +case 0xE204: +case 0xE404: +case 0xE604: +case 0xE804: +case 0xEA04: +case 0xEC04: +case 0xEE04: +case 0xE005: +case 0xE205: +case 0xE405: +case 0xE605: +case 0xE805: +case 0xEA05: +case 0xEC05: +case 0xEE05: +case 0xE006: +case 0xE206: +case 0xE406: +case 0xE606: +case 0xE806: +case 0xEA06: +case 0xEC06: +case 0xEE06: +case 0xE007: +case 0xE207: +case 0xE407: +case 0xE607: +case 0xE807: +case 0xEA07: +case 0xEC07: +case 0xEE07: + +// ASRk +case 0xE000: +{ + u32 res; + pointer src; + u32 sft; + + sft = (((Opcode >> 9) - 1) & 7) + 1; + CCnt -= sft * 2; + src = (s32)(s8)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_V = 0; + CPU->flag_X = CPU->flag_C = src << ((C68K_SR_C_SFT + 1) - sft); + res = ((s32)src) >> sft; + CPU->flag_N = res >> 0; + CPU->flag_notZ = res; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(6) +case 0xE240: +case 0xE440: +case 0xE640: +case 0xE840: +case 0xEA40: +case 0xEC40: +case 0xEE40: +case 0xE041: +case 0xE241: +case 0xE441: +case 0xE641: +case 0xE841: +case 0xEA41: +case 0xEC41: +case 0xEE41: +case 0xE042: +case 0xE242: +case 0xE442: +case 0xE642: +case 0xE842: +case 0xEA42: +case 0xEC42: +case 0xEE42: +case 0xE043: +case 0xE243: +case 0xE443: +case 0xE643: +case 0xE843: +case 0xEA43: +case 0xEC43: +case 0xEE43: +case 0xE044: +case 0xE244: +case 0xE444: +case 0xE644: +case 0xE844: +case 0xEA44: +case 0xEC44: +case 0xEE44: +case 0xE045: +case 0xE245: +case 0xE445: +case 0xE645: +case 0xE845: +case 0xEA45: +case 0xEC45: +case 0xEE45: +case 0xE046: +case 0xE246: +case 0xE446: +case 0xE646: +case 0xE846: +case 0xEA46: +case 0xEC46: +case 0xEE46: +case 0xE047: +case 0xE247: +case 0xE447: +case 0xE647: +case 0xE847: +case 0xEA47: +case 0xEC47: +case 0xEE47: + +// ASRk +case 0xE040: +{ + u32 res; + pointer src; + u32 sft; + + sft = (((Opcode >> 9) - 1) & 7) + 1; + CCnt -= sft * 2; + src = (s32)(s16)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_V = 0; + CPU->flag_X = CPU->flag_C = src << ((C68K_SR_C_SFT + 1) - sft); + res = ((s32)src) >> sft; + CPU->flag_N = res >> 8; + CPU->flag_notZ = res; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(6) +case 0xE280: +case 0xE480: +case 0xE680: +case 0xE880: +case 0xEA80: +case 0xEC80: +case 0xEE80: +case 0xE081: +case 0xE281: +case 0xE481: +case 0xE681: +case 0xE881: +case 0xEA81: +case 0xEC81: +case 0xEE81: +case 0xE082: +case 0xE282: +case 0xE482: +case 0xE682: +case 0xE882: +case 0xEA82: +case 0xEC82: +case 0xEE82: +case 0xE083: +case 0xE283: +case 0xE483: +case 0xE683: +case 0xE883: +case 0xEA83: +case 0xEC83: +case 0xEE83: +case 0xE084: +case 0xE284: +case 0xE484: +case 0xE684: +case 0xE884: +case 0xEA84: +case 0xEC84: +case 0xEE84: +case 0xE085: +case 0xE285: +case 0xE485: +case 0xE685: +case 0xE885: +case 0xEA85: +case 0xEC85: +case 0xEE85: +case 0xE086: +case 0xE286: +case 0xE486: +case 0xE686: +case 0xE886: +case 0xEA86: +case 0xEC86: +case 0xEE86: +case 0xE087: +case 0xE287: +case 0xE487: +case 0xE687: +case 0xE887: +case 0xEA87: +case 0xEC87: +case 0xEE87: + +// ASRk +case 0xE080: +{ + u32 res; + pointer src; + u32 sft; + + sft = (((Opcode >> 9) - 1) & 7) + 1; + CCnt -= sft * 2; + src = (s32)(s32)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_V = 0; + CPU->flag_X = CPU->flag_C = src << ((C68K_SR_C_SFT + 1) - sft); + res = ((s32)src) >> sft; + CPU->flag_N = res >> 24; + CPU->flag_notZ = res; + *((u32*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(8) +case 0xE208: +case 0xE408: +case 0xE608: +case 0xE808: +case 0xEA08: +case 0xEC08: +case 0xEE08: +case 0xE009: +case 0xE209: +case 0xE409: +case 0xE609: +case 0xE809: +case 0xEA09: +case 0xEC09: +case 0xEE09: +case 0xE00A: +case 0xE20A: +case 0xE40A: +case 0xE60A: +case 0xE80A: +case 0xEA0A: +case 0xEC0A: +case 0xEE0A: +case 0xE00B: +case 0xE20B: +case 0xE40B: +case 0xE60B: +case 0xE80B: +case 0xEA0B: +case 0xEC0B: +case 0xEE0B: +case 0xE00C: +case 0xE20C: +case 0xE40C: +case 0xE60C: +case 0xE80C: +case 0xEA0C: +case 0xEC0C: +case 0xEE0C: +case 0xE00D: +case 0xE20D: +case 0xE40D: +case 0xE60D: +case 0xE80D: +case 0xEA0D: +case 0xEC0D: +case 0xEE0D: +case 0xE00E: +case 0xE20E: +case 0xE40E: +case 0xE60E: +case 0xE80E: +case 0xEA0E: +case 0xEC0E: +case 0xEE0E: +case 0xE00F: +case 0xE20F: +case 0xE40F: +case 0xE60F: +case 0xE80F: +case 0xEA0F: +case 0xEC0F: +case 0xEE0F: + +// LSRk +case 0xE008: +{ + u32 res; + pointer src; + u32 sft; + + sft = (((Opcode >> 9) - 1) & 7) + 1; + CCnt -= sft * 2; + src = (u8)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_N = CPU->flag_V = 0; + CPU->flag_X = CPU->flag_C = src << ((C68K_SR_C_SFT + 1) - sft); + res = src >> sft; + CPU->flag_notZ = res; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(6) +case 0xE248: +case 0xE448: +case 0xE648: +case 0xE848: +case 0xEA48: +case 0xEC48: +case 0xEE48: +case 0xE049: +case 0xE249: +case 0xE449: +case 0xE649: +case 0xE849: +case 0xEA49: +case 0xEC49: +case 0xEE49: +case 0xE04A: +case 0xE24A: +case 0xE44A: +case 0xE64A: +case 0xE84A: +case 0xEA4A: +case 0xEC4A: +case 0xEE4A: +case 0xE04B: +case 0xE24B: +case 0xE44B: +case 0xE64B: +case 0xE84B: +case 0xEA4B: +case 0xEC4B: +case 0xEE4B: +case 0xE04C: +case 0xE24C: +case 0xE44C: +case 0xE64C: +case 0xE84C: +case 0xEA4C: +case 0xEC4C: +case 0xEE4C: +case 0xE04D: +case 0xE24D: +case 0xE44D: +case 0xE64D: +case 0xE84D: +case 0xEA4D: +case 0xEC4D: +case 0xEE4D: +case 0xE04E: +case 0xE24E: +case 0xE44E: +case 0xE64E: +case 0xE84E: +case 0xEA4E: +case 0xEC4E: +case 0xEE4E: +case 0xE04F: +case 0xE24F: +case 0xE44F: +case 0xE64F: +case 0xE84F: +case 0xEA4F: +case 0xEC4F: +case 0xEE4F: + +// LSRk +case 0xE048: +{ + u32 res; + pointer src; + u32 sft; + + sft = (((Opcode >> 9) - 1) & 7) + 1; + CCnt -= sft * 2; + src = (u16)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_N = CPU->flag_V = 0; + CPU->flag_X = CPU->flag_C = src << ((C68K_SR_C_SFT + 1) - sft); + res = src >> sft; + CPU->flag_notZ = res; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(6) +case 0xE288: +case 0xE488: +case 0xE688: +case 0xE888: +case 0xEA88: +case 0xEC88: +case 0xEE88: +case 0xE089: +case 0xE289: +case 0xE489: +case 0xE689: +case 0xE889: +case 0xEA89: +case 0xEC89: +case 0xEE89: +case 0xE08A: +case 0xE28A: +case 0xE48A: +case 0xE68A: +case 0xE88A: +case 0xEA8A: +case 0xEC8A: +case 0xEE8A: +case 0xE08B: +case 0xE28B: +case 0xE48B: +case 0xE68B: +case 0xE88B: +case 0xEA8B: +case 0xEC8B: +case 0xEE8B: +case 0xE08C: +case 0xE28C: +case 0xE48C: +case 0xE68C: +case 0xE88C: +case 0xEA8C: +case 0xEC8C: +case 0xEE8C: +case 0xE08D: +case 0xE28D: +case 0xE48D: +case 0xE68D: +case 0xE88D: +case 0xEA8D: +case 0xEC8D: +case 0xEE8D: +case 0xE08E: +case 0xE28E: +case 0xE48E: +case 0xE68E: +case 0xE88E: +case 0xEA8E: +case 0xEC8E: +case 0xEE8E: +case 0xE08F: +case 0xE28F: +case 0xE48F: +case 0xE68F: +case 0xE88F: +case 0xEA8F: +case 0xEC8F: +case 0xEE8F: + +// LSRk +case 0xE088: +{ + u32 res; + pointer src; + u32 sft; + + sft = (((Opcode >> 9) - 1) & 7) + 1; + CCnt -= sft * 2; + src = (u32)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_N = CPU->flag_V = 0; + CPU->flag_X = CPU->flag_C = src << ((C68K_SR_C_SFT + 1) - sft); + res = src >> sft; + CPU->flag_notZ = res; + *((u32*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(8) +case 0xE210: +case 0xE410: +case 0xE610: +case 0xE810: +case 0xEA10: +case 0xEC10: +case 0xEE10: +case 0xE011: +case 0xE211: +case 0xE411: +case 0xE611: +case 0xE811: +case 0xEA11: +case 0xEC11: +case 0xEE11: +case 0xE012: +case 0xE212: +case 0xE412: +case 0xE612: +case 0xE812: +case 0xEA12: +case 0xEC12: +case 0xEE12: +case 0xE013: +case 0xE213: +case 0xE413: +case 0xE613: +case 0xE813: +case 0xEA13: +case 0xEC13: +case 0xEE13: +case 0xE014: +case 0xE214: +case 0xE414: +case 0xE614: +case 0xE814: +case 0xEA14: +case 0xEC14: +case 0xEE14: +case 0xE015: +case 0xE215: +case 0xE415: +case 0xE615: +case 0xE815: +case 0xEA15: +case 0xEC15: +case 0xEE15: +case 0xE016: +case 0xE216: +case 0xE416: +case 0xE616: +case 0xE816: +case 0xEA16: +case 0xEC16: +case 0xEE16: +case 0xE017: +case 0xE217: +case 0xE417: +case 0xE617: +case 0xE817: +case 0xEA17: +case 0xEC17: +case 0xEE17: + +// ROXRk +case 0xE010: +{ + u32 res; + pointer src; + u32 sft; + + sft = (((Opcode >> 9) - 1) & 7) + 1; + CCnt -= sft * 2; + src = (u8)CPU->D[(Opcode >> 0) & 7]; + src |= (CPU->flag_X & C68K_SR_X) << 0; + res = (src >> sft) | (src << (9 - sft)); + CPU->flag_X = CPU->flag_C = res >> 0; + CPU->flag_V = 0; + CPU->flag_N = res >> 0; + CPU->flag_notZ = res & 0x000000FF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(6) +case 0xE250: +case 0xE450: +case 0xE650: +case 0xE850: +case 0xEA50: +case 0xEC50: +case 0xEE50: +case 0xE051: +case 0xE251: +case 0xE451: +case 0xE651: +case 0xE851: +case 0xEA51: +case 0xEC51: +case 0xEE51: +case 0xE052: +case 0xE252: +case 0xE452: +case 0xE652: +case 0xE852: +case 0xEA52: +case 0xEC52: +case 0xEE52: +case 0xE053: +case 0xE253: +case 0xE453: +case 0xE653: +case 0xE853: +case 0xEA53: +case 0xEC53: +case 0xEE53: +case 0xE054: +case 0xE254: +case 0xE454: +case 0xE654: +case 0xE854: +case 0xEA54: +case 0xEC54: +case 0xEE54: +case 0xE055: +case 0xE255: +case 0xE455: +case 0xE655: +case 0xE855: +case 0xEA55: +case 0xEC55: +case 0xEE55: +case 0xE056: +case 0xE256: +case 0xE456: +case 0xE656: +case 0xE856: +case 0xEA56: +case 0xEC56: +case 0xEE56: +case 0xE057: +case 0xE257: +case 0xE457: +case 0xE657: +case 0xE857: +case 0xEA57: +case 0xEC57: +case 0xEE57: + +// ROXRk +case 0xE050: +{ + u32 res; + pointer src; + u32 sft; + + sft = (((Opcode >> 9) - 1) & 7) + 1; + CCnt -= sft * 2; + src = (u16)CPU->D[(Opcode >> 0) & 7]; + src |= (CPU->flag_X & C68K_SR_X) << 8; + res = (src >> sft) | (src << (17 - sft)); + CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_V = 0; + CPU->flag_N = res >> 8; + CPU->flag_notZ = res & 0x0000FFFF; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(6) +case 0xE290: +case 0xE490: +case 0xE690: +case 0xE890: +case 0xEA90: +case 0xEC90: +case 0xEE90: +case 0xE091: +case 0xE291: +case 0xE491: +case 0xE691: +case 0xE891: +case 0xEA91: +case 0xEC91: +case 0xEE91: +case 0xE092: +case 0xE292: +case 0xE492: +case 0xE692: +case 0xE892: +case 0xEA92: +case 0xEC92: +case 0xEE92: +case 0xE093: +case 0xE293: +case 0xE493: +case 0xE693: +case 0xE893: +case 0xEA93: +case 0xEC93: +case 0xEE93: +case 0xE094: +case 0xE294: +case 0xE494: +case 0xE694: +case 0xE894: +case 0xEA94: +case 0xEC94: +case 0xEE94: +case 0xE095: +case 0xE295: +case 0xE495: +case 0xE695: +case 0xE895: +case 0xEA95: +case 0xEC95: +case 0xEE95: +case 0xE096: +case 0xE296: +case 0xE496: +case 0xE696: +case 0xE896: +case 0xEA96: +case 0xEC96: +case 0xEE96: +case 0xE097: +case 0xE297: +case 0xE497: +case 0xE697: +case 0xE897: +case 0xEA97: +case 0xEC97: +case 0xEE97: + +// ROXRk +case 0xE090: +{ + u32 res; + pointer src; + u32 sft; + + sft = (((Opcode >> 9) - 1) & 7) + 1; + CCnt -= sft * 2; + src = (u32)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_C = src << ((C68K_SR_C_SFT + 1) - sft); + if (sft == 1) res = (src >> 1) | ((CPU->flag_X & C68K_SR_X) << (32 - (C68K_SR_X_SFT + 1))); + else res = (src >> sft) | (src << (33 - sft)) | ((CPU->flag_X & C68K_SR_X) << (32 - (C68K_SR_X_SFT + sft))); + CPU->flag_X = CPU->flag_C; + CPU->flag_V = 0; + CPU->flag_N = res >> 24; + CPU->flag_notZ = res; + *((u32*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(8) +case 0xE218: +case 0xE418: +case 0xE618: +case 0xE818: +case 0xEA18: +case 0xEC18: +case 0xEE18: +case 0xE019: +case 0xE219: +case 0xE419: +case 0xE619: +case 0xE819: +case 0xEA19: +case 0xEC19: +case 0xEE19: +case 0xE01A: +case 0xE21A: +case 0xE41A: +case 0xE61A: +case 0xE81A: +case 0xEA1A: +case 0xEC1A: +case 0xEE1A: +case 0xE01B: +case 0xE21B: +case 0xE41B: +case 0xE61B: +case 0xE81B: +case 0xEA1B: +case 0xEC1B: +case 0xEE1B: +case 0xE01C: +case 0xE21C: +case 0xE41C: +case 0xE61C: +case 0xE81C: +case 0xEA1C: +case 0xEC1C: +case 0xEE1C: +case 0xE01D: +case 0xE21D: +case 0xE41D: +case 0xE61D: +case 0xE81D: +case 0xEA1D: +case 0xEC1D: +case 0xEE1D: +case 0xE01E: +case 0xE21E: +case 0xE41E: +case 0xE61E: +case 0xE81E: +case 0xEA1E: +case 0xEC1E: +case 0xEE1E: +case 0xE01F: +case 0xE21F: +case 0xE41F: +case 0xE61F: +case 0xE81F: +case 0xEA1F: +case 0xEC1F: +case 0xEE1F: + +// RORk +case 0xE018: +{ + u32 res; + pointer src; + u32 sft; + + sft = (((Opcode >> 9) - 1) & 7) + 1; + CCnt -= sft * 2; + src = (u8)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_V = 0; + CPU->flag_C = src << ((C68K_SR_C_SFT + 1) - sft); + res = (src >> sft) | (src << (8 - sft)); + CPU->flag_N = res >> 0; + CPU->flag_notZ = res & 0x000000FF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(6) +case 0xE258: +case 0xE458: +case 0xE658: +case 0xE858: +case 0xEA58: +case 0xEC58: +case 0xEE58: +case 0xE059: +case 0xE259: +case 0xE459: +case 0xE659: +case 0xE859: +case 0xEA59: +case 0xEC59: +case 0xEE59: +case 0xE05A: +case 0xE25A: +case 0xE45A: +case 0xE65A: +case 0xE85A: +case 0xEA5A: +case 0xEC5A: +case 0xEE5A: +case 0xE05B: +case 0xE25B: +case 0xE45B: +case 0xE65B: +case 0xE85B: +case 0xEA5B: +case 0xEC5B: +case 0xEE5B: +case 0xE05C: +case 0xE25C: +case 0xE45C: +case 0xE65C: +case 0xE85C: +case 0xEA5C: +case 0xEC5C: +case 0xEE5C: +case 0xE05D: +case 0xE25D: +case 0xE45D: +case 0xE65D: +case 0xE85D: +case 0xEA5D: +case 0xEC5D: +case 0xEE5D: +case 0xE05E: +case 0xE25E: +case 0xE45E: +case 0xE65E: +case 0xE85E: +case 0xEA5E: +case 0xEC5E: +case 0xEE5E: +case 0xE05F: +case 0xE25F: +case 0xE45F: +case 0xE65F: +case 0xE85F: +case 0xEA5F: +case 0xEC5F: +case 0xEE5F: + +// RORk +case 0xE058: +{ + u32 res; + pointer src; + u32 sft; + + sft = (((Opcode >> 9) - 1) & 7) + 1; + CCnt -= sft * 2; + src = (u16)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_V = 0; + CPU->flag_C = src << ((C68K_SR_C_SFT + 1) - sft); + res = (src >> sft) | (src << (16 - sft)); + CPU->flag_N = res >> 8; + CPU->flag_notZ = res & 0x0000FFFF; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(6) +case 0xE298: +case 0xE498: +case 0xE698: +case 0xE898: +case 0xEA98: +case 0xEC98: +case 0xEE98: +case 0xE099: +case 0xE299: +case 0xE499: +case 0xE699: +case 0xE899: +case 0xEA99: +case 0xEC99: +case 0xEE99: +case 0xE09A: +case 0xE29A: +case 0xE49A: +case 0xE69A: +case 0xE89A: +case 0xEA9A: +case 0xEC9A: +case 0xEE9A: +case 0xE09B: +case 0xE29B: +case 0xE49B: +case 0xE69B: +case 0xE89B: +case 0xEA9B: +case 0xEC9B: +case 0xEE9B: +case 0xE09C: +case 0xE29C: +case 0xE49C: +case 0xE69C: +case 0xE89C: +case 0xEA9C: +case 0xEC9C: +case 0xEE9C: +case 0xE09D: +case 0xE29D: +case 0xE49D: +case 0xE69D: +case 0xE89D: +case 0xEA9D: +case 0xEC9D: +case 0xEE9D: +case 0xE09E: +case 0xE29E: +case 0xE49E: +case 0xE69E: +case 0xE89E: +case 0xEA9E: +case 0xEC9E: +case 0xEE9E: +case 0xE09F: +case 0xE29F: +case 0xE49F: +case 0xE69F: +case 0xE89F: +case 0xEA9F: +case 0xEC9F: +case 0xEE9F: + +// RORk +case 0xE098: +{ + u32 res; + pointer src; + u32 sft; + + sft = (((Opcode >> 9) - 1) & 7) + 1; + CCnt -= sft * 2; + src = (u32)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_V = 0; + CPU->flag_C = src << ((C68K_SR_C_SFT + 1) - sft); + res = (src >> sft) | (src << (32 - sft)); + CPU->flag_N = res >> 24; + CPU->flag_notZ = res; + *((u32*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(8) +case 0xE300: +case 0xE500: +case 0xE700: +case 0xE900: +case 0xEB00: +case 0xED00: +case 0xEF00: +case 0xE101: +case 0xE301: +case 0xE501: +case 0xE701: +case 0xE901: +case 0xEB01: +case 0xED01: +case 0xEF01: +case 0xE102: +case 0xE302: +case 0xE502: +case 0xE702: +case 0xE902: +case 0xEB02: +case 0xED02: +case 0xEF02: +case 0xE103: +case 0xE303: +case 0xE503: +case 0xE703: +case 0xE903: +case 0xEB03: +case 0xED03: +case 0xEF03: +case 0xE104: +case 0xE304: +case 0xE504: +case 0xE704: +case 0xE904: +case 0xEB04: +case 0xED04: +case 0xEF04: +case 0xE105: +case 0xE305: +case 0xE505: +case 0xE705: +case 0xE905: +case 0xEB05: +case 0xED05: +case 0xEF05: +case 0xE106: +case 0xE306: +case 0xE506: +case 0xE706: +case 0xE906: +case 0xEB06: +case 0xED06: +case 0xEF06: +case 0xE107: +case 0xE307: +case 0xE507: +case 0xE707: +case 0xE907: +case 0xEB07: +case 0xED07: +case 0xEF07: + +// ASLk +case 0xE100: +{ + u32 res; + pointer src; + u32 sft; + + sft = (((Opcode >> 9) - 1) & 7) + 1; + CCnt -= sft * 2; + src = (u8)CPU->D[(Opcode >> 0) & 7]; + if (sft < 8) + { + CPU->flag_X = CPU->flag_C = src << (0 + sft); + res = src << sft; + CPU->flag_N = res >> 0; + CPU->flag_notZ = res & 0x000000FF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; + CPU->flag_V = 0; + if ((sft > 7) && (src)) CPU->flag_V = C68K_SR_V; + else + { + u32 msk = (((s32)0x80000000) >> (sft + 24)) & 0x000000FF; + src &= msk; + if ((src) && (src != msk)) CPU->flag_V = C68K_SR_V; + } + RET(6) + } + + if (src) CPU->flag_V = C68K_SR_V; + else CPU->flag_V = 0; + CPU->flag_X = CPU->flag_C = src << C68K_SR_C_SFT; + res = 0; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; + CPU->flag_N = 0; + CPU->flag_notZ = 0; +} +RET(6) +case 0xE340: +case 0xE540: +case 0xE740: +case 0xE940: +case 0xEB40: +case 0xED40: +case 0xEF40: +case 0xE141: +case 0xE341: +case 0xE541: +case 0xE741: +case 0xE941: +case 0xEB41: +case 0xED41: +case 0xEF41: +case 0xE142: +case 0xE342: +case 0xE542: +case 0xE742: +case 0xE942: +case 0xEB42: +case 0xED42: +case 0xEF42: +case 0xE143: +case 0xE343: +case 0xE543: +case 0xE743: +case 0xE943: +case 0xEB43: +case 0xED43: +case 0xEF43: +case 0xE144: +case 0xE344: +case 0xE544: +case 0xE744: +case 0xE944: +case 0xEB44: +case 0xED44: +case 0xEF44: +case 0xE145: +case 0xE345: +case 0xE545: +case 0xE745: +case 0xE945: +case 0xEB45: +case 0xED45: +case 0xEF45: +case 0xE146: +case 0xE346: +case 0xE546: +case 0xE746: +case 0xE946: +case 0xEB46: +case 0xED46: +case 0xEF46: +case 0xE147: +case 0xE347: +case 0xE547: +case 0xE747: +case 0xE947: +case 0xEB47: +case 0xED47: +case 0xEF47: + +// ASLk +case 0xE140: +{ + u32 res; + pointer src; + u32 sft; + + sft = (((Opcode >> 9) - 1) & 7) + 1; + CCnt -= sft * 2; + src = (u16)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_X = CPU->flag_C = src >> (8 - sft); + res = src << sft; + CPU->flag_N = res >> 8; + CPU->flag_notZ = res & 0x0000FFFF; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 0) & 7])) = res; + CPU->flag_V = 0; + { + u32 msk = (((s32)0x80000000) >> (sft + 16)) & 0x0000FFFF; + src &= msk; + if ((src) && (src != msk)) CPU->flag_V = C68K_SR_V; + } +} +RET(6) +case 0xE380: +case 0xE580: +case 0xE780: +case 0xE980: +case 0xEB80: +case 0xED80: +case 0xEF80: +case 0xE181: +case 0xE381: +case 0xE581: +case 0xE781: +case 0xE981: +case 0xEB81: +case 0xED81: +case 0xEF81: +case 0xE182: +case 0xE382: +case 0xE582: +case 0xE782: +case 0xE982: +case 0xEB82: +case 0xED82: +case 0xEF82: +case 0xE183: +case 0xE383: +case 0xE583: +case 0xE783: +case 0xE983: +case 0xEB83: +case 0xED83: +case 0xEF83: +case 0xE184: +case 0xE384: +case 0xE584: +case 0xE784: +case 0xE984: +case 0xEB84: +case 0xED84: +case 0xEF84: +case 0xE185: +case 0xE385: +case 0xE585: +case 0xE785: +case 0xE985: +case 0xEB85: +case 0xED85: +case 0xEF85: +case 0xE186: +case 0xE386: +case 0xE586: +case 0xE786: +case 0xE986: +case 0xEB86: +case 0xED86: +case 0xEF86: +case 0xE187: +case 0xE387: +case 0xE587: +case 0xE787: +case 0xE987: +case 0xEB87: +case 0xED87: +case 0xEF87: + +// ASLk +case 0xE180: +{ + u32 res; + pointer src; + u32 sft; + + sft = (((Opcode >> 9) - 1) & 7) + 1; + CCnt -= sft * 2; + src = (u32)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_X = CPU->flag_C = src >> (24 - sft); + res = src << sft; + CPU->flag_N = res >> 24; + CPU->flag_notZ = res & 0xFFFFFFFF; + *((u32*)(&CPU->D[(Opcode >> 0) & 7])) = res; + CPU->flag_V = 0; + { + u32 msk = (((s32)0x80000000) >> (sft + 0)) & 0xFFFFFFFF; + src &= msk; + if ((src) && (src != msk)) CPU->flag_V = C68K_SR_V; + } +} +RET(8) +case 0xE308: +case 0xE508: +case 0xE708: +case 0xE908: +case 0xEB08: +case 0xED08: +case 0xEF08: +case 0xE109: +case 0xE309: +case 0xE509: +case 0xE709: +case 0xE909: +case 0xEB09: +case 0xED09: +case 0xEF09: +case 0xE10A: +case 0xE30A: +case 0xE50A: +case 0xE70A: +case 0xE90A: +case 0xEB0A: +case 0xED0A: +case 0xEF0A: +case 0xE10B: +case 0xE30B: +case 0xE50B: +case 0xE70B: +case 0xE90B: +case 0xEB0B: +case 0xED0B: +case 0xEF0B: +case 0xE10C: +case 0xE30C: +case 0xE50C: +case 0xE70C: +case 0xE90C: +case 0xEB0C: +case 0xED0C: +case 0xEF0C: +case 0xE10D: +case 0xE30D: +case 0xE50D: +case 0xE70D: +case 0xE90D: +case 0xEB0D: +case 0xED0D: +case 0xEF0D: +case 0xE10E: +case 0xE30E: +case 0xE50E: +case 0xE70E: +case 0xE90E: +case 0xEB0E: +case 0xED0E: +case 0xEF0E: +case 0xE10F: +case 0xE30F: +case 0xE50F: +case 0xE70F: +case 0xE90F: +case 0xEB0F: +case 0xED0F: +case 0xEF0F: + +// LSLk +case 0xE108: +{ + u32 res; + pointer src; + u32 sft; + + sft = (((Opcode >> 9) - 1) & 7) + 1; + CCnt -= sft * 2; + src = (u8)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_V = 0; + CPU->flag_X = CPU->flag_C = src << (0 + sft); + res = src << sft; + CPU->flag_N = res >> 0; + CPU->flag_notZ = res & 0x000000FF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(6) +case 0xE348: +case 0xE548: +case 0xE748: +case 0xE948: +case 0xEB48: +case 0xED48: +case 0xEF48: +case 0xE149: +case 0xE349: +case 0xE549: +case 0xE749: +case 0xE949: +case 0xEB49: +case 0xED49: +case 0xEF49: +case 0xE14A: +case 0xE34A: +case 0xE54A: +case 0xE74A: +case 0xE94A: +case 0xEB4A: +case 0xED4A: +case 0xEF4A: +case 0xE14B: +case 0xE34B: +case 0xE54B: +case 0xE74B: +case 0xE94B: +case 0xEB4B: +case 0xED4B: +case 0xEF4B: +case 0xE14C: +case 0xE34C: +case 0xE54C: +case 0xE74C: +case 0xE94C: +case 0xEB4C: +case 0xED4C: +case 0xEF4C: +case 0xE14D: +case 0xE34D: +case 0xE54D: +case 0xE74D: +case 0xE94D: +case 0xEB4D: +case 0xED4D: +case 0xEF4D: +case 0xE14E: +case 0xE34E: +case 0xE54E: +case 0xE74E: +case 0xE94E: +case 0xEB4E: +case 0xED4E: +case 0xEF4E: +case 0xE14F: +case 0xE34F: +case 0xE54F: +case 0xE74F: +case 0xE94F: +case 0xEB4F: +case 0xED4F: +case 0xEF4F: + +// LSLk +case 0xE148: +{ + u32 res; + pointer src; + u32 sft; + + sft = (((Opcode >> 9) - 1) & 7) + 1; + CCnt -= sft * 2; + src = (u16)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_V = 0; + CPU->flag_X = CPU->flag_C = src >> (8 - sft); + res = src << sft; + CPU->flag_N = res >> 8; + CPU->flag_notZ = res & 0x0000FFFF; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(6) +case 0xE388: +case 0xE588: +case 0xE788: +case 0xE988: +case 0xEB88: +case 0xED88: +case 0xEF88: +case 0xE189: +case 0xE389: +case 0xE589: +case 0xE789: +case 0xE989: +case 0xEB89: +case 0xED89: +case 0xEF89: +case 0xE18A: +case 0xE38A: +case 0xE58A: +case 0xE78A: +case 0xE98A: +case 0xEB8A: +case 0xED8A: +case 0xEF8A: +case 0xE18B: +case 0xE38B: +case 0xE58B: +case 0xE78B: +case 0xE98B: +case 0xEB8B: +case 0xED8B: +case 0xEF8B: +case 0xE18C: +case 0xE38C: +case 0xE58C: +case 0xE78C: +case 0xE98C: +case 0xEB8C: +case 0xED8C: +case 0xEF8C: +case 0xE18D: +case 0xE38D: +case 0xE58D: +case 0xE78D: +case 0xE98D: +case 0xEB8D: +case 0xED8D: +case 0xEF8D: +case 0xE18E: +case 0xE38E: +case 0xE58E: +case 0xE78E: +case 0xE98E: +case 0xEB8E: +case 0xED8E: +case 0xEF8E: +case 0xE18F: +case 0xE38F: +case 0xE58F: +case 0xE78F: +case 0xE98F: +case 0xEB8F: +case 0xED8F: +case 0xEF8F: + +// LSLk +case 0xE188: +{ + u32 res; + pointer src; + u32 sft; + + sft = (((Opcode >> 9) - 1) & 7) + 1; + CCnt -= sft * 2; + src = (u32)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_V = 0; + CPU->flag_X = CPU->flag_C = src >> (24 - sft); + res = src << sft; + CPU->flag_N = res >> 24; + CPU->flag_notZ = res & 0xFFFFFFFF; + *((u32*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(8) +case 0xE310: +case 0xE510: +case 0xE710: +case 0xE910: +case 0xEB10: +case 0xED10: +case 0xEF10: +case 0xE111: +case 0xE311: +case 0xE511: +case 0xE711: +case 0xE911: +case 0xEB11: +case 0xED11: +case 0xEF11: +case 0xE112: +case 0xE312: +case 0xE512: +case 0xE712: +case 0xE912: +case 0xEB12: +case 0xED12: +case 0xEF12: +case 0xE113: +case 0xE313: +case 0xE513: +case 0xE713: +case 0xE913: +case 0xEB13: +case 0xED13: +case 0xEF13: +case 0xE114: +case 0xE314: +case 0xE514: +case 0xE714: +case 0xE914: +case 0xEB14: +case 0xED14: +case 0xEF14: +case 0xE115: +case 0xE315: +case 0xE515: +case 0xE715: +case 0xE915: +case 0xEB15: +case 0xED15: +case 0xEF15: +case 0xE116: +case 0xE316: +case 0xE516: +case 0xE716: +case 0xE916: +case 0xEB16: +case 0xED16: +case 0xEF16: +case 0xE117: +case 0xE317: +case 0xE517: +case 0xE717: +case 0xE917: +case 0xEB17: +case 0xED17: +case 0xEF17: + +// ROXLk +case 0xE110: +{ + u32 res; + pointer src; + u32 sft; + + sft = (((Opcode >> 9) - 1) & 7) + 1; + CCnt -= sft * 2; + src = (u8)CPU->D[(Opcode >> 0) & 7]; + src |= (CPU->flag_X & C68K_SR_X) << 0; + res = (src << sft) | (src >> (9 - sft)); + CPU->flag_X = CPU->flag_C = res >> 0; + CPU->flag_V = 0; + CPU->flag_N = res >> 0; + CPU->flag_notZ = res & 0x000000FF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(6) +case 0xE350: +case 0xE550: +case 0xE750: +case 0xE950: +case 0xEB50: +case 0xED50: +case 0xEF50: +case 0xE151: +case 0xE351: +case 0xE551: +case 0xE751: +case 0xE951: +case 0xEB51: +case 0xED51: +case 0xEF51: +case 0xE152: +case 0xE352: +case 0xE552: +case 0xE752: +case 0xE952: +case 0xEB52: +case 0xED52: +case 0xEF52: +case 0xE153: +case 0xE353: +case 0xE553: +case 0xE753: +case 0xE953: +case 0xEB53: +case 0xED53: +case 0xEF53: +case 0xE154: +case 0xE354: +case 0xE554: +case 0xE754: +case 0xE954: +case 0xEB54: +case 0xED54: +case 0xEF54: +case 0xE155: +case 0xE355: +case 0xE555: +case 0xE755: +case 0xE955: +case 0xEB55: +case 0xED55: +case 0xEF55: +case 0xE156: +case 0xE356: +case 0xE556: +case 0xE756: +case 0xE956: +case 0xEB56: +case 0xED56: +case 0xEF56: +case 0xE157: +case 0xE357: +case 0xE557: +case 0xE757: +case 0xE957: +case 0xEB57: +case 0xED57: +case 0xEF57: + +// ROXLk +case 0xE150: +{ + u32 res; + pointer src; + u32 sft; + + sft = (((Opcode >> 9) - 1) & 7) + 1; + CCnt -= sft * 2; + src = (u16)CPU->D[(Opcode >> 0) & 7]; + src |= (CPU->flag_X & C68K_SR_X) << 8; + res = (src << sft) | (src >> (17 - sft)); + CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_V = 0; + CPU->flag_N = res >> 8; + CPU->flag_notZ = res & 0x0000FFFF; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(6) +case 0xE390: +case 0xE590: +case 0xE790: +case 0xE990: +case 0xEB90: +case 0xED90: +case 0xEF90: +case 0xE191: +case 0xE391: +case 0xE591: +case 0xE791: +case 0xE991: +case 0xEB91: +case 0xED91: +case 0xEF91: +case 0xE192: +case 0xE392: +case 0xE592: +case 0xE792: +case 0xE992: +case 0xEB92: +case 0xED92: +case 0xEF92: +case 0xE193: +case 0xE393: +case 0xE593: +case 0xE793: +case 0xE993: +case 0xEB93: +case 0xED93: +case 0xEF93: +case 0xE194: +case 0xE394: +case 0xE594: +case 0xE794: +case 0xE994: +case 0xEB94: +case 0xED94: +case 0xEF94: +case 0xE195: +case 0xE395: +case 0xE595: +case 0xE795: +case 0xE995: +case 0xEB95: +case 0xED95: +case 0xEF95: +case 0xE196: +case 0xE396: +case 0xE596: +case 0xE796: +case 0xE996: +case 0xEB96: +case 0xED96: +case 0xEF96: +case 0xE197: +case 0xE397: +case 0xE597: +case 0xE797: +case 0xE997: +case 0xEB97: +case 0xED97: +case 0xEF97: + +// ROXLk +case 0xE190: +{ + u32 res; + pointer src; + u32 sft; + + sft = (((Opcode >> 9) - 1) & 7) + 1; + CCnt -= sft * 2; + src = (u32)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_C = src >> ((32 - C68K_SR_C_SFT) - sft); + if (sft == 1) res = (src << 1) | ((CPU->flag_X & C68K_SR_X) >> ((C68K_SR_X_SFT + 1) - 1)); + else res = (src << sft) | (src >> (33 - sft)) | ((CPU->flag_X & C68K_SR_X) >> ((C68K_SR_X_SFT + 1) - sft)); + CPU->flag_X = CPU->flag_C; + CPU->flag_V = 0; + CPU->flag_N = res >> 24; + CPU->flag_notZ = res; + *((u32*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(8) +case 0xE318: +case 0xE518: +case 0xE718: +case 0xE918: +case 0xEB18: +case 0xED18: +case 0xEF18: +case 0xE119: +case 0xE319: +case 0xE519: +case 0xE719: +case 0xE919: +case 0xEB19: +case 0xED19: +case 0xEF19: +case 0xE11A: +case 0xE31A: +case 0xE51A: +case 0xE71A: +case 0xE91A: +case 0xEB1A: +case 0xED1A: +case 0xEF1A: +case 0xE11B: +case 0xE31B: +case 0xE51B: +case 0xE71B: +case 0xE91B: +case 0xEB1B: +case 0xED1B: +case 0xEF1B: +case 0xE11C: +case 0xE31C: +case 0xE51C: +case 0xE71C: +case 0xE91C: +case 0xEB1C: +case 0xED1C: +case 0xEF1C: +case 0xE11D: +case 0xE31D: +case 0xE51D: +case 0xE71D: +case 0xE91D: +case 0xEB1D: +case 0xED1D: +case 0xEF1D: +case 0xE11E: +case 0xE31E: +case 0xE51E: +case 0xE71E: +case 0xE91E: +case 0xEB1E: +case 0xED1E: +case 0xEF1E: +case 0xE11F: +case 0xE31F: +case 0xE51F: +case 0xE71F: +case 0xE91F: +case 0xEB1F: +case 0xED1F: +case 0xEF1F: + +// ROLk +case 0xE118: +{ + u32 res; + pointer src; + u32 sft; + + sft = (((Opcode >> 9) - 1) & 7) + 1; + CCnt -= sft * 2; + src = (u8)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_V = 0; + CPU->flag_C = src << (0 + sft); + res = (src << sft) | (src >> (8 - sft)); + CPU->flag_N = res >> 0; + CPU->flag_notZ = res & 0x000000FF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(6) +case 0xE358: +case 0xE558: +case 0xE758: +case 0xE958: +case 0xEB58: +case 0xED58: +case 0xEF58: +case 0xE159: +case 0xE359: +case 0xE559: +case 0xE759: +case 0xE959: +case 0xEB59: +case 0xED59: +case 0xEF59: +case 0xE15A: +case 0xE35A: +case 0xE55A: +case 0xE75A: +case 0xE95A: +case 0xEB5A: +case 0xED5A: +case 0xEF5A: +case 0xE15B: +case 0xE35B: +case 0xE55B: +case 0xE75B: +case 0xE95B: +case 0xEB5B: +case 0xED5B: +case 0xEF5B: +case 0xE15C: +case 0xE35C: +case 0xE55C: +case 0xE75C: +case 0xE95C: +case 0xEB5C: +case 0xED5C: +case 0xEF5C: +case 0xE15D: +case 0xE35D: +case 0xE55D: +case 0xE75D: +case 0xE95D: +case 0xEB5D: +case 0xED5D: +case 0xEF5D: +case 0xE15E: +case 0xE35E: +case 0xE55E: +case 0xE75E: +case 0xE95E: +case 0xEB5E: +case 0xED5E: +case 0xEF5E: +case 0xE15F: +case 0xE35F: +case 0xE55F: +case 0xE75F: +case 0xE95F: +case 0xEB5F: +case 0xED5F: +case 0xEF5F: + +// ROLk +case 0xE158: +{ + u32 res; + pointer src; + u32 sft; + + sft = (((Opcode >> 9) - 1) & 7) + 1; + CCnt -= sft * 2; + src = (u16)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_V = 0; + CPU->flag_C = src >> (8 - sft); + res = (src << sft) | (src >> (16 - sft)); + CPU->flag_N = res >> 8; + CPU->flag_notZ = res & 0x0000FFFF; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(6) +case 0xE398: +case 0xE598: +case 0xE798: +case 0xE998: +case 0xEB98: +case 0xED98: +case 0xEF98: +case 0xE199: +case 0xE399: +case 0xE599: +case 0xE799: +case 0xE999: +case 0xEB99: +case 0xED99: +case 0xEF99: +case 0xE19A: +case 0xE39A: +case 0xE59A: +case 0xE79A: +case 0xE99A: +case 0xEB9A: +case 0xED9A: +case 0xEF9A: +case 0xE19B: +case 0xE39B: +case 0xE59B: +case 0xE79B: +case 0xE99B: +case 0xEB9B: +case 0xED9B: +case 0xEF9B: +case 0xE19C: +case 0xE39C: +case 0xE59C: +case 0xE79C: +case 0xE99C: +case 0xEB9C: +case 0xED9C: +case 0xEF9C: +case 0xE19D: +case 0xE39D: +case 0xE59D: +case 0xE79D: +case 0xE99D: +case 0xEB9D: +case 0xED9D: +case 0xEF9D: +case 0xE19E: +case 0xE39E: +case 0xE59E: +case 0xE79E: +case 0xE99E: +case 0xEB9E: +case 0xED9E: +case 0xEF9E: +case 0xE19F: +case 0xE39F: +case 0xE59F: +case 0xE79F: +case 0xE99F: +case 0xEB9F: +case 0xED9F: +case 0xEF9F: + +// ROLk +case 0xE198: +{ + u32 res; + pointer src; + u32 sft; + + sft = (((Opcode >> 9) - 1) & 7) + 1; + CCnt -= sft * 2; + src = (u32)CPU->D[(Opcode >> 0) & 7]; + CPU->flag_V = 0; + CPU->flag_C = src >> (24 - sft); + res = (src << sft) | (src >> (32 - sft)); + CPU->flag_N = res >> 24; + CPU->flag_notZ = res; + *((u32*)(&CPU->D[(Opcode >> 0) & 7])) = res; +} +RET(8) +case 0xE220: +case 0xE420: +case 0xE620: +case 0xE820: +case 0xEA20: +case 0xEC20: +case 0xEE20: +case 0xE021: +case 0xE221: +case 0xE421: +case 0xE621: +case 0xE821: +case 0xEA21: +case 0xEC21: +case 0xEE21: +case 0xE022: +case 0xE222: +case 0xE422: +case 0xE622: +case 0xE822: +case 0xEA22: +case 0xEC22: +case 0xEE22: +case 0xE023: +case 0xE223: +case 0xE423: +case 0xE623: +case 0xE823: +case 0xEA23: +case 0xEC23: +case 0xEE23: +case 0xE024: +case 0xE224: +case 0xE424: +case 0xE624: +case 0xE824: +case 0xEA24: +case 0xEC24: +case 0xEE24: +case 0xE025: +case 0xE225: +case 0xE425: +case 0xE625: +case 0xE825: +case 0xEA25: +case 0xEC25: +case 0xEE25: +case 0xE026: +case 0xE226: +case 0xE426: +case 0xE626: +case 0xE826: +case 0xEA26: +case 0xEC26: +case 0xEE26: +case 0xE027: +case 0xE227: +case 0xE427: +case 0xE627: +case 0xE827: +case 0xEA27: +case 0xEC27: +case 0xEE27: + +// ASRD +case 0xE020: +{ + u32 res; + pointer src; + u32 sft; + + sft = CPU->D[(Opcode >> 9) & 7] & 0x3F; + src = (s32)(s8)CPU->D[(Opcode >> 0) & 7]; + if (sft) + { + CCnt -= sft * 2; + if (sft < 8) + { + CPU->flag_V = 0; + CPU->flag_X = CPU->flag_C = src << ((C68K_SR_C_SFT + 1) - sft); + res = ((s32)src) >> sft; + CPU->flag_N = res >> 0; + CPU->flag_notZ = res; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(6) + } + + if (src & (1 << 7)) + { + CPU->flag_N = C68K_SR_N; + CPU->flag_notZ = 1; + CPU->flag_V = 0; + CPU->flag_C = C68K_SR_C; + CPU->flag_X = C68K_SR_X; + res = 0x000000FF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(6) + } + + CPU->flag_N = 0; + CPU->flag_notZ = 0; + CPU->flag_V = 0; + CPU->flag_C = 0; + CPU->flag_X = 0; + res = 0; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(6) + } + + CPU->flag_V = 0; + CPU->flag_C = 0; + CPU->flag_N = src >> 0; + CPU->flag_notZ = src; +} +RET(6) +case 0xE260: +case 0xE460: +case 0xE660: +case 0xE860: +case 0xEA60: +case 0xEC60: +case 0xEE60: +case 0xE061: +case 0xE261: +case 0xE461: +case 0xE661: +case 0xE861: +case 0xEA61: +case 0xEC61: +case 0xEE61: +case 0xE062: +case 0xE262: +case 0xE462: +case 0xE662: +case 0xE862: +case 0xEA62: +case 0xEC62: +case 0xEE62: +case 0xE063: +case 0xE263: +case 0xE463: +case 0xE663: +case 0xE863: +case 0xEA63: +case 0xEC63: +case 0xEE63: +case 0xE064: +case 0xE264: +case 0xE464: +case 0xE664: +case 0xE864: +case 0xEA64: +case 0xEC64: +case 0xEE64: +case 0xE065: +case 0xE265: +case 0xE465: +case 0xE665: +case 0xE865: +case 0xEA65: +case 0xEC65: +case 0xEE65: +case 0xE066: +case 0xE266: +case 0xE466: +case 0xE666: +case 0xE866: +case 0xEA66: +case 0xEC66: +case 0xEE66: +case 0xE067: +case 0xE267: +case 0xE467: +case 0xE667: +case 0xE867: +case 0xEA67: +case 0xEC67: +case 0xEE67: + +// ASRD +case 0xE060: +{ + u32 res; + pointer src; + u32 sft; + + sft = CPU->D[(Opcode >> 9) & 7] & 0x3F; + src = (s32)(s16)CPU->D[(Opcode >> 0) & 7]; + if (sft) + { + CCnt -= sft * 2; + if (sft < 16) + { + CPU->flag_V = 0; + CPU->flag_X = CPU->flag_C = (src >> (sft - 1)) << C68K_SR_C_SFT; + res = ((s32)src) >> sft; + CPU->flag_N = res >> 8; + CPU->flag_notZ = res; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(6) + } + + if (src & (1 << 15)) + { + CPU->flag_N = C68K_SR_N; + CPU->flag_notZ = 1; + CPU->flag_V = 0; + CPU->flag_C = C68K_SR_C; + CPU->flag_X = C68K_SR_X; + res = 0x0000FFFF; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(6) + } + + CPU->flag_N = 0; + CPU->flag_notZ = 0; + CPU->flag_V = 0; + CPU->flag_C = 0; + CPU->flag_X = 0; + res = 0; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(6) + } + + CPU->flag_V = 0; + CPU->flag_C = 0; + CPU->flag_N = src >> 8; + CPU->flag_notZ = src; +} +RET(6) +case 0xE2A0: +case 0xE4A0: +case 0xE6A0: +case 0xE8A0: +case 0xEAA0: +case 0xECA0: +case 0xEEA0: +case 0xE0A1: +case 0xE2A1: +case 0xE4A1: +case 0xE6A1: +case 0xE8A1: +case 0xEAA1: +case 0xECA1: +case 0xEEA1: +case 0xE0A2: +case 0xE2A2: +case 0xE4A2: +case 0xE6A2: +case 0xE8A2: +case 0xEAA2: +case 0xECA2: +case 0xEEA2: +case 0xE0A3: +case 0xE2A3: +case 0xE4A3: +case 0xE6A3: +case 0xE8A3: +case 0xEAA3: +case 0xECA3: +case 0xEEA3: +case 0xE0A4: +case 0xE2A4: +case 0xE4A4: +case 0xE6A4: +case 0xE8A4: +case 0xEAA4: +case 0xECA4: +case 0xEEA4: +case 0xE0A5: +case 0xE2A5: +case 0xE4A5: +case 0xE6A5: +case 0xE8A5: +case 0xEAA5: +case 0xECA5: +case 0xEEA5: +case 0xE0A6: +case 0xE2A6: +case 0xE4A6: +case 0xE6A6: +case 0xE8A6: +case 0xEAA6: +case 0xECA6: +case 0xEEA6: +case 0xE0A7: +case 0xE2A7: +case 0xE4A7: +case 0xE6A7: +case 0xE8A7: +case 0xEAA7: +case 0xECA7: +case 0xEEA7: + +// ASRD +case 0xE0A0: +{ + u32 res; + pointer src; + u32 sft; + + sft = CPU->D[(Opcode >> 9) & 7] & 0x3F; + src = (s32)(s32)CPU->D[(Opcode >> 0) & 7]; + if (sft) + { + CCnt -= sft * 2; + if (sft < 32) + { + CPU->flag_V = 0; + CPU->flag_X = CPU->flag_C = (src >> (sft - 1)) << C68K_SR_C_SFT; + res = ((s32)src) >> sft; + CPU->flag_N = res >> 24; + CPU->flag_notZ = res; + *((u32*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(8) + } + + if (src & (1 << 31)) + { + CPU->flag_N = C68K_SR_N; + CPU->flag_notZ = 1; + CPU->flag_V = 0; + CPU->flag_C = C68K_SR_C; + CPU->flag_X = C68K_SR_X; + res = 0xFFFFFFFF; + *((u32*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(8) + } + + CPU->flag_N = 0; + CPU->flag_notZ = 0; + CPU->flag_V = 0; + CPU->flag_C = 0; + CPU->flag_X = 0; + res = 0; + *((u32*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(8) + } + + CPU->flag_V = 0; + CPU->flag_C = 0; + CPU->flag_N = src >> 24; + CPU->flag_notZ = src; +} +RET(8) +case 0xE228: +case 0xE428: +case 0xE628: +case 0xE828: +case 0xEA28: +case 0xEC28: +case 0xEE28: +case 0xE029: +case 0xE229: +case 0xE429: +case 0xE629: +case 0xE829: +case 0xEA29: +case 0xEC29: +case 0xEE29: +case 0xE02A: +case 0xE22A: +case 0xE42A: +case 0xE62A: +case 0xE82A: +case 0xEA2A: +case 0xEC2A: +case 0xEE2A: +case 0xE02B: +case 0xE22B: +case 0xE42B: +case 0xE62B: +case 0xE82B: +case 0xEA2B: +case 0xEC2B: +case 0xEE2B: +case 0xE02C: +case 0xE22C: +case 0xE42C: +case 0xE62C: +case 0xE82C: +case 0xEA2C: +case 0xEC2C: +case 0xEE2C: +case 0xE02D: +case 0xE22D: +case 0xE42D: +case 0xE62D: +case 0xE82D: +case 0xEA2D: +case 0xEC2D: +case 0xEE2D: +case 0xE02E: +case 0xE22E: +case 0xE42E: +case 0xE62E: +case 0xE82E: +case 0xEA2E: +case 0xEC2E: +case 0xEE2E: +case 0xE02F: +case 0xE22F: +case 0xE42F: +case 0xE62F: +case 0xE82F: +case 0xEA2F: +case 0xEC2F: +case 0xEE2F: + +// LSRD +case 0xE028: +{ + u32 res; + pointer src; + u32 sft; + + sft = CPU->D[(Opcode >> 9) & 7] & 0x3F; + src = (u8)CPU->D[(Opcode >> 0) & 7]; + if (sft) + { + CCnt -= sft * 2; + if (sft <= 8) + { + CPU->flag_N = CPU->flag_V = 0; + CPU->flag_X = CPU->flag_C = src << ((C68K_SR_C_SFT + 1) - sft); + res = src >> sft; + CPU->flag_notZ = res; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(6) + } + + CPU->flag_X = CPU->flag_C = 0; + CPU->flag_N = 0; + CPU->flag_notZ = 0; + CPU->flag_V = 0; + res = 0; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(6) + } + + CPU->flag_V = 0; + CPU->flag_C = 0; + CPU->flag_N = src >> 0; + CPU->flag_notZ = src; +} +RET(6) +case 0xE268: +case 0xE468: +case 0xE668: +case 0xE868: +case 0xEA68: +case 0xEC68: +case 0xEE68: +case 0xE069: +case 0xE269: +case 0xE469: +case 0xE669: +case 0xE869: +case 0xEA69: +case 0xEC69: +case 0xEE69: +case 0xE06A: +case 0xE26A: +case 0xE46A: +case 0xE66A: +case 0xE86A: +case 0xEA6A: +case 0xEC6A: +case 0xEE6A: +case 0xE06B: +case 0xE26B: +case 0xE46B: +case 0xE66B: +case 0xE86B: +case 0xEA6B: +case 0xEC6B: +case 0xEE6B: +case 0xE06C: +case 0xE26C: +case 0xE46C: +case 0xE66C: +case 0xE86C: +case 0xEA6C: +case 0xEC6C: +case 0xEE6C: +case 0xE06D: +case 0xE26D: +case 0xE46D: +case 0xE66D: +case 0xE86D: +case 0xEA6D: +case 0xEC6D: +case 0xEE6D: +case 0xE06E: +case 0xE26E: +case 0xE46E: +case 0xE66E: +case 0xE86E: +case 0xEA6E: +case 0xEC6E: +case 0xEE6E: +case 0xE06F: +case 0xE26F: +case 0xE46F: +case 0xE66F: +case 0xE86F: +case 0xEA6F: +case 0xEC6F: +case 0xEE6F: + +// LSRD +case 0xE068: +{ + u32 res; + pointer src; + u32 sft; + + sft = CPU->D[(Opcode >> 9) & 7] & 0x3F; + src = (u16)CPU->D[(Opcode >> 0) & 7]; + if (sft) + { + CCnt -= sft * 2; + if (sft <= 16) + { + CPU->flag_N = CPU->flag_V = 0; + CPU->flag_X = CPU->flag_C = (src >> (sft - 1)) << C68K_SR_C_SFT; + res = src >> sft; + CPU->flag_notZ = res; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(6) + } + + CPU->flag_X = CPU->flag_C = 0; + CPU->flag_N = 0; + CPU->flag_notZ = 0; + CPU->flag_V = 0; + res = 0; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(6) + } + + CPU->flag_V = 0; + CPU->flag_C = 0; + CPU->flag_N = src >> 8; + CPU->flag_notZ = src; +} +RET(6) +case 0xE2A8: +case 0xE4A8: +case 0xE6A8: +case 0xE8A8: +case 0xEAA8: +case 0xECA8: +case 0xEEA8: +case 0xE0A9: +case 0xE2A9: +case 0xE4A9: +case 0xE6A9: +case 0xE8A9: +case 0xEAA9: +case 0xECA9: +case 0xEEA9: +case 0xE0AA: +case 0xE2AA: +case 0xE4AA: +case 0xE6AA: +case 0xE8AA: +case 0xEAAA: +case 0xECAA: +case 0xEEAA: +case 0xE0AB: +case 0xE2AB: +case 0xE4AB: +case 0xE6AB: +case 0xE8AB: +case 0xEAAB: +case 0xECAB: +case 0xEEAB: +case 0xE0AC: +case 0xE2AC: +case 0xE4AC: +case 0xE6AC: +case 0xE8AC: +case 0xEAAC: +case 0xECAC: +case 0xEEAC: +case 0xE0AD: +case 0xE2AD: +case 0xE4AD: +case 0xE6AD: +case 0xE8AD: +case 0xEAAD: +case 0xECAD: +case 0xEEAD: +case 0xE0AE: +case 0xE2AE: +case 0xE4AE: +case 0xE6AE: +case 0xE8AE: +case 0xEAAE: +case 0xECAE: +case 0xEEAE: +case 0xE0AF: +case 0xE2AF: +case 0xE4AF: +case 0xE6AF: +case 0xE8AF: +case 0xEAAF: +case 0xECAF: +case 0xEEAF: + +// LSRD +case 0xE0A8: +{ + u32 res; + pointer src; + u32 sft; + + sft = CPU->D[(Opcode >> 9) & 7] & 0x3F; + src = (u32)CPU->D[(Opcode >> 0) & 7]; + if (sft) + { + CCnt -= sft * 2; + if (sft < 32) + { + CPU->flag_N = CPU->flag_V = 0; + CPU->flag_X = CPU->flag_C = (src >> (sft - 1)) << C68K_SR_C_SFT; + res = src >> sft; + CPU->flag_notZ = res; + *((u32*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(8) + } + + if (sft == 32) CPU->flag_C = src >> (31 - C68K_SR_C_SFT); + else CPU->flag_C = 0; + CPU->flag_X = CPU->flag_C; + CPU->flag_N = 0; + CPU->flag_notZ = 0; + CPU->flag_V = 0; + res = 0; + *((u32*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(8) + } + + CPU->flag_V = 0; + CPU->flag_C = 0; + CPU->flag_N = src >> 24; + CPU->flag_notZ = src; +} +RET(8) +case 0xE230: +case 0xE430: +case 0xE630: +case 0xE830: +case 0xEA30: +case 0xEC30: +case 0xEE30: +case 0xE031: +case 0xE231: +case 0xE431: +case 0xE631: +case 0xE831: +case 0xEA31: +case 0xEC31: +case 0xEE31: +case 0xE032: +case 0xE232: +case 0xE432: +case 0xE632: +case 0xE832: +case 0xEA32: +case 0xEC32: +case 0xEE32: +case 0xE033: +case 0xE233: +case 0xE433: +case 0xE633: +case 0xE833: +case 0xEA33: +case 0xEC33: +case 0xEE33: +case 0xE034: +case 0xE234: +case 0xE434: +case 0xE634: +case 0xE834: +case 0xEA34: +case 0xEC34: +case 0xEE34: +case 0xE035: +case 0xE235: +case 0xE435: +case 0xE635: +case 0xE835: +case 0xEA35: +case 0xEC35: +case 0xEE35: +case 0xE036: +case 0xE236: +case 0xE436: +case 0xE636: +case 0xE836: +case 0xEA36: +case 0xEC36: +case 0xEE36: +case 0xE037: +case 0xE237: +case 0xE437: +case 0xE637: +case 0xE837: +case 0xEA37: +case 0xEC37: +case 0xEE37: + +// ROXRD +case 0xE030: +{ + u32 res; + pointer src; + u32 sft; + + sft = CPU->D[(Opcode >> 9) & 7] & 0x3F; + src = (u8)CPU->D[(Opcode >> 0) & 7]; + if (sft) + { + CCnt -= sft * 2; + sft %= 9; + + src |= (CPU->flag_X & C68K_SR_X) << 0; + res = (src >> sft) | (src << (9 - sft)); + CPU->flag_X = CPU->flag_C = res >> 0; + CPU->flag_V = 0; + CPU->flag_N = res >> 0; + CPU->flag_notZ = res & 0x000000FF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(6) + } + + CPU->flag_V = 0; + CPU->flag_C = CPU->flag_X; + CPU->flag_N = src >> 0; + CPU->flag_notZ = src; +} +RET(6) +case 0xE270: +case 0xE470: +case 0xE670: +case 0xE870: +case 0xEA70: +case 0xEC70: +case 0xEE70: +case 0xE071: +case 0xE271: +case 0xE471: +case 0xE671: +case 0xE871: +case 0xEA71: +case 0xEC71: +case 0xEE71: +case 0xE072: +case 0xE272: +case 0xE472: +case 0xE672: +case 0xE872: +case 0xEA72: +case 0xEC72: +case 0xEE72: +case 0xE073: +case 0xE273: +case 0xE473: +case 0xE673: +case 0xE873: +case 0xEA73: +case 0xEC73: +case 0xEE73: +case 0xE074: +case 0xE274: +case 0xE474: +case 0xE674: +case 0xE874: +case 0xEA74: +case 0xEC74: +case 0xEE74: +case 0xE075: +case 0xE275: +case 0xE475: +case 0xE675: +case 0xE875: +case 0xEA75: +case 0xEC75: +case 0xEE75: +case 0xE076: +case 0xE276: +case 0xE476: +case 0xE676: +case 0xE876: +case 0xEA76: +case 0xEC76: +case 0xEE76: +case 0xE077: +case 0xE277: +case 0xE477: +case 0xE677: +case 0xE877: +case 0xEA77: +case 0xEC77: +case 0xEE77: + +// ROXRD +case 0xE070: +{ + u32 res; + pointer src; + u32 sft; + + sft = CPU->D[(Opcode >> 9) & 7] & 0x3F; + src = (u16)CPU->D[(Opcode >> 0) & 7]; + if (sft) + { + CCnt -= sft * 2; + sft %= 17; + + src |= (CPU->flag_X & C68K_SR_X) << 8; + res = (src >> sft) | (src << (17 - sft)); + CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_V = 0; + CPU->flag_N = res >> 8; + CPU->flag_notZ = res & 0x0000FFFF; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(6) + } + + CPU->flag_V = 0; + CPU->flag_C = CPU->flag_X; + CPU->flag_N = src >> 8; + CPU->flag_notZ = src; +} +RET(6) +case 0xE2B0: +case 0xE4B0: +case 0xE6B0: +case 0xE8B0: +case 0xEAB0: +case 0xECB0: +case 0xEEB0: +case 0xE0B1: +case 0xE2B1: +case 0xE4B1: +case 0xE6B1: +case 0xE8B1: +case 0xEAB1: +case 0xECB1: +case 0xEEB1: +case 0xE0B2: +case 0xE2B2: +case 0xE4B2: +case 0xE6B2: +case 0xE8B2: +case 0xEAB2: +case 0xECB2: +case 0xEEB2: +case 0xE0B3: +case 0xE2B3: +case 0xE4B3: +case 0xE6B3: +case 0xE8B3: +case 0xEAB3: +case 0xECB3: +case 0xEEB3: +case 0xE0B4: +case 0xE2B4: +case 0xE4B4: +case 0xE6B4: +case 0xE8B4: +case 0xEAB4: +case 0xECB4: +case 0xEEB4: +case 0xE0B5: +case 0xE2B5: +case 0xE4B5: +case 0xE6B5: +case 0xE8B5: +case 0xEAB5: +case 0xECB5: +case 0xEEB5: +case 0xE0B6: +case 0xE2B6: +case 0xE4B6: +case 0xE6B6: +case 0xE8B6: +case 0xEAB6: +case 0xECB6: +case 0xEEB6: +case 0xE0B7: +case 0xE2B7: +case 0xE4B7: +case 0xE6B7: +case 0xE8B7: +case 0xEAB7: +case 0xECB7: +case 0xEEB7: + +// ROXRD +case 0xE0B0: +{ + u32 res; + pointer src; + u32 sft; + + sft = CPU->D[(Opcode >> 9) & 7] & 0x3F; + src = (u32)CPU->D[(Opcode >> 0) & 7]; + if (sft) + { + CCnt -= sft * 2; + sft %= 33; + + if (sft != 0) + { + if (sft == 1) res = (src >> 1) | ((CPU->flag_X & C68K_SR_X) << (32 - (C68K_SR_X_SFT + 1))); + else res = (src >> sft) | (src << (33 - sft)) | (((CPU->flag_X & C68K_SR_X) << (32 - (C68K_SR_X_SFT + 1))) >> (sft - 1)); + CPU->flag_X = (src >> (32 - sft)) << C68K_SR_X_SFT; + } + else res = src; + CPU->flag_C = CPU->flag_X; + CPU->flag_V = 0; + CPU->flag_N = res >> 24; + CPU->flag_notZ = res; + *((u32*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(8) + } + + CPU->flag_V = 0; + CPU->flag_C = CPU->flag_X; + CPU->flag_N = src >> 24; + CPU->flag_notZ = src; +} +RET(8) +case 0xE238: +case 0xE438: +case 0xE638: +case 0xE838: +case 0xEA38: +case 0xEC38: +case 0xEE38: +case 0xE039: +case 0xE239: +case 0xE439: +case 0xE639: +case 0xE839: +case 0xEA39: +case 0xEC39: +case 0xEE39: +case 0xE03A: +case 0xE23A: +case 0xE43A: +case 0xE63A: +case 0xE83A: +case 0xEA3A: +case 0xEC3A: +case 0xEE3A: +case 0xE03B: +case 0xE23B: +case 0xE43B: +case 0xE63B: +case 0xE83B: +case 0xEA3B: +case 0xEC3B: +case 0xEE3B: +case 0xE03C: +case 0xE23C: +case 0xE43C: +case 0xE63C: +case 0xE83C: +case 0xEA3C: +case 0xEC3C: +case 0xEE3C: +case 0xE03D: +case 0xE23D: +case 0xE43D: +case 0xE63D: +case 0xE83D: +case 0xEA3D: +case 0xEC3D: +case 0xEE3D: +case 0xE03E: +case 0xE23E: +case 0xE43E: +case 0xE63E: +case 0xE83E: +case 0xEA3E: +case 0xEC3E: +case 0xEE3E: +case 0xE03F: +case 0xE23F: +case 0xE43F: +case 0xE63F: +case 0xE83F: +case 0xEA3F: +case 0xEC3F: +case 0xEE3F: + +// RORD +case 0xE038: +{ + u32 res; + pointer src; + u32 sft; + + sft = CPU->D[(Opcode >> 9) & 7] & 0x3F; + src = (u8)CPU->D[(Opcode >> 0) & 7]; + if (sft) + { + CCnt -= sft * 2; + sft &= 0x07; + + CPU->flag_C = src << (C68K_SR_C_SFT - ((sft - 1) & 7)); + res = (src >> sft) | (src << (8 - sft)); + CPU->flag_V = 0; + CPU->flag_N = res >> 0; + CPU->flag_notZ = res & 0x000000FF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(6) + } + + CPU->flag_V = 0; + CPU->flag_C = 0; + CPU->flag_N = src >> 0; + CPU->flag_notZ = src; +} +RET(6) +case 0xE278: +case 0xE478: +case 0xE678: +case 0xE878: +case 0xEA78: +case 0xEC78: +case 0xEE78: +case 0xE079: +case 0xE279: +case 0xE479: +case 0xE679: +case 0xE879: +case 0xEA79: +case 0xEC79: +case 0xEE79: +case 0xE07A: +case 0xE27A: +case 0xE47A: +case 0xE67A: +case 0xE87A: +case 0xEA7A: +case 0xEC7A: +case 0xEE7A: +case 0xE07B: +case 0xE27B: +case 0xE47B: +case 0xE67B: +case 0xE87B: +case 0xEA7B: +case 0xEC7B: +case 0xEE7B: +case 0xE07C: +case 0xE27C: +case 0xE47C: +case 0xE67C: +case 0xE87C: +case 0xEA7C: +case 0xEC7C: +case 0xEE7C: +case 0xE07D: +case 0xE27D: +case 0xE47D: +case 0xE67D: +case 0xE87D: +case 0xEA7D: +case 0xEC7D: +case 0xEE7D: +case 0xE07E: +case 0xE27E: +case 0xE47E: +case 0xE67E: +case 0xE87E: +case 0xEA7E: +case 0xEC7E: +case 0xEE7E: +case 0xE07F: +case 0xE27F: +case 0xE47F: +case 0xE67F: +case 0xE87F: +case 0xEA7F: +case 0xEC7F: +case 0xEE7F: + +// RORD +case 0xE078: +{ + u32 res; + pointer src; + u32 sft; + + sft = CPU->D[(Opcode >> 9) & 7] & 0x3F; + src = (u16)CPU->D[(Opcode >> 0) & 7]; + if (sft) + { + CCnt -= sft * 2; + sft &= 0x0F; + + CPU->flag_C = (src >> ((sft - 1) & 15)) << C68K_SR_C_SFT; + res = (src >> sft) | (src << (16 - sft)); + CPU->flag_V = 0; + CPU->flag_N = res >> 8; + CPU->flag_notZ = res & 0x0000FFFF; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(6) + } + + CPU->flag_V = 0; + CPU->flag_C = 0; + CPU->flag_N = src >> 8; + CPU->flag_notZ = src; +} +RET(6) +case 0xE2B8: +case 0xE4B8: +case 0xE6B8: +case 0xE8B8: +case 0xEAB8: +case 0xECB8: +case 0xEEB8: +case 0xE0B9: +case 0xE2B9: +case 0xE4B9: +case 0xE6B9: +case 0xE8B9: +case 0xEAB9: +case 0xECB9: +case 0xEEB9: +case 0xE0BA: +case 0xE2BA: +case 0xE4BA: +case 0xE6BA: +case 0xE8BA: +case 0xEABA: +case 0xECBA: +case 0xEEBA: +case 0xE0BB: +case 0xE2BB: +case 0xE4BB: +case 0xE6BB: +case 0xE8BB: +case 0xEABB: +case 0xECBB: +case 0xEEBB: +case 0xE0BC: +case 0xE2BC: +case 0xE4BC: +case 0xE6BC: +case 0xE8BC: +case 0xEABC: +case 0xECBC: +case 0xEEBC: +case 0xE0BD: +case 0xE2BD: +case 0xE4BD: +case 0xE6BD: +case 0xE8BD: +case 0xEABD: +case 0xECBD: +case 0xEEBD: +case 0xE0BE: +case 0xE2BE: +case 0xE4BE: +case 0xE6BE: +case 0xE8BE: +case 0xEABE: +case 0xECBE: +case 0xEEBE: +case 0xE0BF: +case 0xE2BF: +case 0xE4BF: +case 0xE6BF: +case 0xE8BF: +case 0xEABF: +case 0xECBF: +case 0xEEBF: + +// RORD +case 0xE0B8: +{ + u32 res; + pointer src; + u32 sft; + + sft = CPU->D[(Opcode >> 9) & 7] & 0x3F; + src = (u32)CPU->D[(Opcode >> 0) & 7]; + if (sft) + { + CCnt -= sft * 2; + sft &= 0x1F; + + CPU->flag_C = (src >> ((sft - 1) & 31)) << C68K_SR_C_SFT; + res = (src >> sft) | (src << (32 - sft)); + CPU->flag_V = 0; + CPU->flag_N = res >> 24; + CPU->flag_notZ = res; + *((u32*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(8) + } + + CPU->flag_V = 0; + CPU->flag_C = 0; + CPU->flag_N = src >> 24; + CPU->flag_notZ = src; +} +RET(8) +case 0xE320: +case 0xE520: +case 0xE720: +case 0xE920: +case 0xEB20: +case 0xED20: +case 0xEF20: +case 0xE121: +case 0xE321: +case 0xE521: +case 0xE721: +case 0xE921: +case 0xEB21: +case 0xED21: +case 0xEF21: +case 0xE122: +case 0xE322: +case 0xE522: +case 0xE722: +case 0xE922: +case 0xEB22: +case 0xED22: +case 0xEF22: +case 0xE123: +case 0xE323: +case 0xE523: +case 0xE723: +case 0xE923: +case 0xEB23: +case 0xED23: +case 0xEF23: +case 0xE124: +case 0xE324: +case 0xE524: +case 0xE724: +case 0xE924: +case 0xEB24: +case 0xED24: +case 0xEF24: +case 0xE125: +case 0xE325: +case 0xE525: +case 0xE725: +case 0xE925: +case 0xEB25: +case 0xED25: +case 0xEF25: +case 0xE126: +case 0xE326: +case 0xE526: +case 0xE726: +case 0xE926: +case 0xEB26: +case 0xED26: +case 0xEF26: +case 0xE127: +case 0xE327: +case 0xE527: +case 0xE727: +case 0xE927: +case 0xEB27: +case 0xED27: +case 0xEF27: + +// ASLD +case 0xE120: +{ + u32 res; + pointer src; + u32 sft; + + sft = CPU->D[(Opcode >> 9) & 7] & 0x3F; + src = (u8)CPU->D[(Opcode >> 0) & 7]; + if (sft) + { + CCnt -= sft * 2; + if (sft < 8) + { + CPU->flag_X = CPU->flag_C = (src << sft) >> 0; + res = (src << sft) & 0x000000FF; + CPU->flag_N = res >> 0; + CPU->flag_notZ = res; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; + CPU->flag_V = 0; + { + u32 msk = (((s32)0x80000000) >> (sft + 24)) & 0x000000FF; + src &= msk; + if ((src) && (src != msk)) CPU->flag_V = C68K_SR_V; + } + RET(6) + } + + if (sft == 256) CPU->flag_C = src << C68K_SR_C_SFT; + else CPU->flag_C = 0; + CPU->flag_X = CPU->flag_C; + if (src) CPU->flag_V = C68K_SR_V; + else CPU->flag_V = 0; + res = 0; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; + CPU->flag_N = 0; + CPU->flag_notZ = 0; + RET(6) + } + + CPU->flag_V = 0; + CPU->flag_C = 0; + CPU->flag_N = src >> 0; + CPU->flag_notZ = src; +} +RET(6) +case 0xE360: +case 0xE560: +case 0xE760: +case 0xE960: +case 0xEB60: +case 0xED60: +case 0xEF60: +case 0xE161: +case 0xE361: +case 0xE561: +case 0xE761: +case 0xE961: +case 0xEB61: +case 0xED61: +case 0xEF61: +case 0xE162: +case 0xE362: +case 0xE562: +case 0xE762: +case 0xE962: +case 0xEB62: +case 0xED62: +case 0xEF62: +case 0xE163: +case 0xE363: +case 0xE563: +case 0xE763: +case 0xE963: +case 0xEB63: +case 0xED63: +case 0xEF63: +case 0xE164: +case 0xE364: +case 0xE564: +case 0xE764: +case 0xE964: +case 0xEB64: +case 0xED64: +case 0xEF64: +case 0xE165: +case 0xE365: +case 0xE565: +case 0xE765: +case 0xE965: +case 0xEB65: +case 0xED65: +case 0xEF65: +case 0xE166: +case 0xE366: +case 0xE566: +case 0xE766: +case 0xE966: +case 0xEB66: +case 0xED66: +case 0xEF66: +case 0xE167: +case 0xE367: +case 0xE567: +case 0xE767: +case 0xE967: +case 0xEB67: +case 0xED67: +case 0xEF67: + +// ASLD +case 0xE160: +{ + u32 res; + pointer src; + u32 sft; + + sft = CPU->D[(Opcode >> 9) & 7] & 0x3F; + src = (u16)CPU->D[(Opcode >> 0) & 7]; + if (sft) + { + CCnt -= sft * 2; + if (sft < 16) + { + CPU->flag_X = CPU->flag_C = (src << sft) >> 8; + res = (src << sft) & 0x0000FFFF; + CPU->flag_N = res >> 8; + CPU->flag_notZ = res; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 0) & 7])) = res; + CPU->flag_V = 0; + { + u32 msk = (((s32)0x80000000) >> (sft + 16)) & 0x0000FFFF; + src &= msk; + if ((src) && (src != msk)) CPU->flag_V = C68K_SR_V; + } + RET(6) + } + + if (sft == 65536) CPU->flag_C = src << C68K_SR_C_SFT; + else CPU->flag_C = 0; + CPU->flag_X = CPU->flag_C; + if (src) CPU->flag_V = C68K_SR_V; + else CPU->flag_V = 0; + res = 0; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 0) & 7])) = res; + CPU->flag_N = 0; + CPU->flag_notZ = 0; + RET(6) + } + + CPU->flag_V = 0; + CPU->flag_C = 0; + CPU->flag_N = src >> 8; + CPU->flag_notZ = src; +} +RET(6) +case 0xE3A0: +case 0xE5A0: +case 0xE7A0: +case 0xE9A0: +case 0xEBA0: +case 0xEDA0: +case 0xEFA0: +case 0xE1A1: +case 0xE3A1: +case 0xE5A1: +case 0xE7A1: +case 0xE9A1: +case 0xEBA1: +case 0xEDA1: +case 0xEFA1: +case 0xE1A2: +case 0xE3A2: +case 0xE5A2: +case 0xE7A2: +case 0xE9A2: +case 0xEBA2: +case 0xEDA2: +case 0xEFA2: +case 0xE1A3: +case 0xE3A3: +case 0xE5A3: +case 0xE7A3: +case 0xE9A3: +case 0xEBA3: +case 0xEDA3: +case 0xEFA3: +case 0xE1A4: +case 0xE3A4: +case 0xE5A4: +case 0xE7A4: +case 0xE9A4: +case 0xEBA4: +case 0xEDA4: +case 0xEFA4: +case 0xE1A5: +case 0xE3A5: +case 0xE5A5: +case 0xE7A5: +case 0xE9A5: +case 0xEBA5: +case 0xEDA5: +case 0xEFA5: +case 0xE1A6: +case 0xE3A6: +case 0xE5A6: +case 0xE7A6: +case 0xE9A6: +case 0xEBA6: +case 0xEDA6: +case 0xEFA6: +case 0xE1A7: +case 0xE3A7: +case 0xE5A7: +case 0xE7A7: +case 0xE9A7: +case 0xEBA7: +case 0xEDA7: +case 0xEFA7: + +// ASLD +case 0xE1A0: +{ + u32 res; + pointer src; + u32 sft; + + sft = CPU->D[(Opcode >> 9) & 7] & 0x3F; + src = (u32)CPU->D[(Opcode >> 0) & 7]; + if (sft) + { + CCnt -= sft * 2; + if (sft < 32) + { + CPU->flag_X = CPU->flag_C = (src >> (32 - sft)) << C68K_SR_C_SFT; + res = src << sft; + CPU->flag_N = res >> 24; + CPU->flag_notZ = res; + *((u32*)(&CPU->D[(Opcode >> 0) & 7])) = res; + CPU->flag_V = 0; + { + u32 msk = (((s32)0x80000000) >> (sft + 0)) & 0xFFFFFFFF; + src &= msk; + if ((src) && (src != msk)) CPU->flag_V = C68K_SR_V; + } + RET(8) + } + + if (sft == 0) CPU->flag_C = src << C68K_SR_C_SFT; + else CPU->flag_C = 0; + CPU->flag_X = CPU->flag_C; + if (src) CPU->flag_V = C68K_SR_V; + else CPU->flag_V = 0; + res = 0; + *((u32*)(&CPU->D[(Opcode >> 0) & 7])) = res; + CPU->flag_N = 0; + CPU->flag_notZ = 0; + RET(8) + } + + CPU->flag_V = 0; + CPU->flag_C = 0; + CPU->flag_N = src >> 24; + CPU->flag_notZ = src; +} +RET(8) +case 0xE328: +case 0xE528: +case 0xE728: +case 0xE928: +case 0xEB28: +case 0xED28: +case 0xEF28: +case 0xE129: +case 0xE329: +case 0xE529: +case 0xE729: +case 0xE929: +case 0xEB29: +case 0xED29: +case 0xEF29: +case 0xE12A: +case 0xE32A: +case 0xE52A: +case 0xE72A: +case 0xE92A: +case 0xEB2A: +case 0xED2A: +case 0xEF2A: +case 0xE12B: +case 0xE32B: +case 0xE52B: +case 0xE72B: +case 0xE92B: +case 0xEB2B: +case 0xED2B: +case 0xEF2B: +case 0xE12C: +case 0xE32C: +case 0xE52C: +case 0xE72C: +case 0xE92C: +case 0xEB2C: +case 0xED2C: +case 0xEF2C: +case 0xE12D: +case 0xE32D: +case 0xE52D: +case 0xE72D: +case 0xE92D: +case 0xEB2D: +case 0xED2D: +case 0xEF2D: +case 0xE12E: +case 0xE32E: +case 0xE52E: +case 0xE72E: +case 0xE92E: +case 0xEB2E: +case 0xED2E: +case 0xEF2E: +case 0xE12F: +case 0xE32F: +case 0xE52F: +case 0xE72F: +case 0xE92F: +case 0xEB2F: +case 0xED2F: +case 0xEF2F: + +// LSLD +case 0xE128: +{ + u32 res; + pointer src; + u32 sft; + + sft = CPU->D[(Opcode >> 9) & 7] & 0x3F; + src = (u8)CPU->D[(Opcode >> 0) & 7]; + if (sft) + { + CCnt -= sft * 2; + if (sft <= 8) + { + CPU->flag_X = CPU->flag_C = (src << sft) >> 0; + res = (src << sft) & 0x000000FF; + CPU->flag_V = 0; + CPU->flag_N = res >> 0; + CPU->flag_notZ = res; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(6) + } + + CPU->flag_X = CPU->flag_C = 0; + CPU->flag_N = 0; + CPU->flag_notZ = 0; + CPU->flag_V = 0; + res = 0; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(6) + } + + CPU->flag_V = 0; + CPU->flag_C = 0; + CPU->flag_N = src >> 0; + CPU->flag_notZ = src; +} +RET(6) +case 0xE368: +case 0xE568: +case 0xE768: +case 0xE968: +case 0xEB68: +case 0xED68: +case 0xEF68: +case 0xE169: +case 0xE369: +case 0xE569: +case 0xE769: +case 0xE969: +case 0xEB69: +case 0xED69: +case 0xEF69: +case 0xE16A: +case 0xE36A: +case 0xE56A: +case 0xE76A: +case 0xE96A: +case 0xEB6A: +case 0xED6A: +case 0xEF6A: +case 0xE16B: +case 0xE36B: +case 0xE56B: +case 0xE76B: +case 0xE96B: +case 0xEB6B: +case 0xED6B: +case 0xEF6B: +case 0xE16C: +case 0xE36C: +case 0xE56C: +case 0xE76C: +case 0xE96C: +case 0xEB6C: +case 0xED6C: +case 0xEF6C: +case 0xE16D: +case 0xE36D: +case 0xE56D: +case 0xE76D: +case 0xE96D: +case 0xEB6D: +case 0xED6D: +case 0xEF6D: +case 0xE16E: +case 0xE36E: +case 0xE56E: +case 0xE76E: +case 0xE96E: +case 0xEB6E: +case 0xED6E: +case 0xEF6E: +case 0xE16F: +case 0xE36F: +case 0xE56F: +case 0xE76F: +case 0xE96F: +case 0xEB6F: +case 0xED6F: +case 0xEF6F: + +// LSLD +case 0xE168: +{ + u32 res; + pointer src; + u32 sft; + + sft = CPU->D[(Opcode >> 9) & 7] & 0x3F; + src = (u16)CPU->D[(Opcode >> 0) & 7]; + if (sft) + { + CCnt -= sft * 2; + if (sft <= 16) + { + CPU->flag_X = CPU->flag_C = (src << sft) >> 8; + res = (src << sft) & 0x0000FFFF; + CPU->flag_V = 0; + CPU->flag_N = res >> 8; + CPU->flag_notZ = res; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(6) + } + + CPU->flag_X = CPU->flag_C = 0; + CPU->flag_N = 0; + CPU->flag_notZ = 0; + CPU->flag_V = 0; + res = 0; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(6) + } + + CPU->flag_V = 0; + CPU->flag_C = 0; + CPU->flag_N = src >> 8; + CPU->flag_notZ = src; +} +RET(6) +case 0xE3A8: +case 0xE5A8: +case 0xE7A8: +case 0xE9A8: +case 0xEBA8: +case 0xEDA8: +case 0xEFA8: +case 0xE1A9: +case 0xE3A9: +case 0xE5A9: +case 0xE7A9: +case 0xE9A9: +case 0xEBA9: +case 0xEDA9: +case 0xEFA9: +case 0xE1AA: +case 0xE3AA: +case 0xE5AA: +case 0xE7AA: +case 0xE9AA: +case 0xEBAA: +case 0xEDAA: +case 0xEFAA: +case 0xE1AB: +case 0xE3AB: +case 0xE5AB: +case 0xE7AB: +case 0xE9AB: +case 0xEBAB: +case 0xEDAB: +case 0xEFAB: +case 0xE1AC: +case 0xE3AC: +case 0xE5AC: +case 0xE7AC: +case 0xE9AC: +case 0xEBAC: +case 0xEDAC: +case 0xEFAC: +case 0xE1AD: +case 0xE3AD: +case 0xE5AD: +case 0xE7AD: +case 0xE9AD: +case 0xEBAD: +case 0xEDAD: +case 0xEFAD: +case 0xE1AE: +case 0xE3AE: +case 0xE5AE: +case 0xE7AE: +case 0xE9AE: +case 0xEBAE: +case 0xEDAE: +case 0xEFAE: +case 0xE1AF: +case 0xE3AF: +case 0xE5AF: +case 0xE7AF: +case 0xE9AF: +case 0xEBAF: +case 0xEDAF: +case 0xEFAF: + +// LSLD +case 0xE1A8: +{ + u32 res; + pointer src; + u32 sft; + + sft = CPU->D[(Opcode >> 9) & 7] & 0x3F; + src = (u32)CPU->D[(Opcode >> 0) & 7]; + if (sft) + { + CCnt -= sft * 2; + if (sft < 32) + { + CPU->flag_X = CPU->flag_C = (src >> (32 - sft)) << C68K_SR_C_SFT; + res = src << sft; + CPU->flag_V = 0; + CPU->flag_N = res >> 24; + CPU->flag_notZ = res; + *((u32*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(8) + } + + if (sft == 32) CPU->flag_C = src << C68K_SR_C_SFT; + else CPU->flag_C = 0; + CPU->flag_X = CPU->flag_C; + CPU->flag_N = 0; + CPU->flag_notZ = 0; + CPU->flag_V = 0; + res = 0; + *((u32*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(8) + } + + CPU->flag_V = 0; + CPU->flag_C = 0; + CPU->flag_N = src >> 24; + CPU->flag_notZ = src; +} +RET(8) +case 0xE330: +case 0xE530: +case 0xE730: +case 0xE930: +case 0xEB30: +case 0xED30: +case 0xEF30: +case 0xE131: +case 0xE331: +case 0xE531: +case 0xE731: +case 0xE931: +case 0xEB31: +case 0xED31: +case 0xEF31: +case 0xE132: +case 0xE332: +case 0xE532: +case 0xE732: +case 0xE932: +case 0xEB32: +case 0xED32: +case 0xEF32: +case 0xE133: +case 0xE333: +case 0xE533: +case 0xE733: +case 0xE933: +case 0xEB33: +case 0xED33: +case 0xEF33: +case 0xE134: +case 0xE334: +case 0xE534: +case 0xE734: +case 0xE934: +case 0xEB34: +case 0xED34: +case 0xEF34: +case 0xE135: +case 0xE335: +case 0xE535: +case 0xE735: +case 0xE935: +case 0xEB35: +case 0xED35: +case 0xEF35: +case 0xE136: +case 0xE336: +case 0xE536: +case 0xE736: +case 0xE936: +case 0xEB36: +case 0xED36: +case 0xEF36: +case 0xE137: +case 0xE337: +case 0xE537: +case 0xE737: +case 0xE937: +case 0xEB37: +case 0xED37: +case 0xEF37: + +// ROXLD +case 0xE130: +{ + u32 res; + pointer src; + u32 sft; + + sft = CPU->D[(Opcode >> 9) & 7] & 0x3F; + src = (u8)CPU->D[(Opcode >> 0) & 7]; + if (sft) + { + CCnt -= sft * 2; + sft %= 9; + + src |= (CPU->flag_X & C68K_SR_X) << 0; + res = (src << sft) | (src >> (9 - sft)); + CPU->flag_X = CPU->flag_C = res >> 0; + CPU->flag_V = 0; + CPU->flag_N = res >> 0; + CPU->flag_notZ = res & 0x000000FF; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(6) + } + + CPU->flag_V = 0; + CPU->flag_C = CPU->flag_X; + CPU->flag_N = src >> 0; + CPU->flag_notZ = src; +} +RET(6) +case 0xE370: +case 0xE570: +case 0xE770: +case 0xE970: +case 0xEB70: +case 0xED70: +case 0xEF70: +case 0xE171: +case 0xE371: +case 0xE571: +case 0xE771: +case 0xE971: +case 0xEB71: +case 0xED71: +case 0xEF71: +case 0xE172: +case 0xE372: +case 0xE572: +case 0xE772: +case 0xE972: +case 0xEB72: +case 0xED72: +case 0xEF72: +case 0xE173: +case 0xE373: +case 0xE573: +case 0xE773: +case 0xE973: +case 0xEB73: +case 0xED73: +case 0xEF73: +case 0xE174: +case 0xE374: +case 0xE574: +case 0xE774: +case 0xE974: +case 0xEB74: +case 0xED74: +case 0xEF74: +case 0xE175: +case 0xE375: +case 0xE575: +case 0xE775: +case 0xE975: +case 0xEB75: +case 0xED75: +case 0xEF75: +case 0xE176: +case 0xE376: +case 0xE576: +case 0xE776: +case 0xE976: +case 0xEB76: +case 0xED76: +case 0xEF76: +case 0xE177: +case 0xE377: +case 0xE577: +case 0xE777: +case 0xE977: +case 0xEB77: +case 0xED77: +case 0xEF77: + +// ROXLD +case 0xE170: +{ + u32 res; + pointer src; + u32 sft; + + sft = CPU->D[(Opcode >> 9) & 7] & 0x3F; + src = (u16)CPU->D[(Opcode >> 0) & 7]; + if (sft) + { + CCnt -= sft * 2; + sft %= 17; + + src |= (CPU->flag_X & C68K_SR_X) << 8; + res = (src << sft) | (src >> (17 - sft)); + CPU->flag_X = CPU->flag_C = res >> 8; + CPU->flag_V = 0; + CPU->flag_N = res >> 8; + CPU->flag_notZ = res & 0x0000FFFF; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(6) + } + + CPU->flag_V = 0; + CPU->flag_C = CPU->flag_X; + CPU->flag_N = src >> 8; + CPU->flag_notZ = src; +} +RET(6) +case 0xE3B0: +case 0xE5B0: +case 0xE7B0: +case 0xE9B0: +case 0xEBB0: +case 0xEDB0: +case 0xEFB0: +case 0xE1B1: +case 0xE3B1: +case 0xE5B1: +case 0xE7B1: +case 0xE9B1: +case 0xEBB1: +case 0xEDB1: +case 0xEFB1: +case 0xE1B2: +case 0xE3B2: +case 0xE5B2: +case 0xE7B2: +case 0xE9B2: +case 0xEBB2: +case 0xEDB2: +case 0xEFB2: +case 0xE1B3: +case 0xE3B3: +case 0xE5B3: +case 0xE7B3: +case 0xE9B3: +case 0xEBB3: +case 0xEDB3: +case 0xEFB3: +case 0xE1B4: +case 0xE3B4: +case 0xE5B4: +case 0xE7B4: +case 0xE9B4: +case 0xEBB4: +case 0xEDB4: +case 0xEFB4: +case 0xE1B5: +case 0xE3B5: +case 0xE5B5: +case 0xE7B5: +case 0xE9B5: +case 0xEBB5: +case 0xEDB5: +case 0xEFB5: +case 0xE1B6: +case 0xE3B6: +case 0xE5B6: +case 0xE7B6: +case 0xE9B6: +case 0xEBB6: +case 0xEDB6: +case 0xEFB6: +case 0xE1B7: +case 0xE3B7: +case 0xE5B7: +case 0xE7B7: +case 0xE9B7: +case 0xEBB7: +case 0xEDB7: +case 0xEFB7: + +// ROXLD +case 0xE1B0: +{ + u32 res; + pointer src; + u32 sft; + + sft = CPU->D[(Opcode >> 9) & 7] & 0x3F; + src = (u32)CPU->D[(Opcode >> 0) & 7]; + if (sft) + { + CCnt -= sft * 2; + sft %= 33; + + if (sft != 0) + { + if (sft == 1) res = (src << 1) | ((CPU->flag_X >> ((C68K_SR_X_SFT + 1) - 1)) & 1); + else res = (src << sft) | (src >> (33 - sft)) | (((CPU->flag_X >> ((C68K_SR_X_SFT + 1) - 1)) & 1) << (sft - 1)); + CPU->flag_X = (src >> (32 - sft)) << C68K_SR_X_SFT; + } + else res = src; + CPU->flag_C = CPU->flag_X; + CPU->flag_V = 0; + CPU->flag_N = res >> 24; + CPU->flag_notZ = res; + *((u32*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(8) + } + + CPU->flag_V = 0; + CPU->flag_C = CPU->flag_X; + CPU->flag_N = src >> 24; + CPU->flag_notZ = src; +} +RET(8) +case 0xE338: +case 0xE538: +case 0xE738: +case 0xE938: +case 0xEB38: +case 0xED38: +case 0xEF38: +case 0xE139: +case 0xE339: +case 0xE539: +case 0xE739: +case 0xE939: +case 0xEB39: +case 0xED39: +case 0xEF39: +case 0xE13A: +case 0xE33A: +case 0xE53A: +case 0xE73A: +case 0xE93A: +case 0xEB3A: +case 0xED3A: +case 0xEF3A: +case 0xE13B: +case 0xE33B: +case 0xE53B: +case 0xE73B: +case 0xE93B: +case 0xEB3B: +case 0xED3B: +case 0xEF3B: +case 0xE13C: +case 0xE33C: +case 0xE53C: +case 0xE73C: +case 0xE93C: +case 0xEB3C: +case 0xED3C: +case 0xEF3C: +case 0xE13D: +case 0xE33D: +case 0xE53D: +case 0xE73D: +case 0xE93D: +case 0xEB3D: +case 0xED3D: +case 0xEF3D: +case 0xE13E: +case 0xE33E: +case 0xE53E: +case 0xE73E: +case 0xE93E: +case 0xEB3E: +case 0xED3E: +case 0xEF3E: +case 0xE13F: +case 0xE33F: +case 0xE53F: +case 0xE73F: +case 0xE93F: +case 0xEB3F: +case 0xED3F: +case 0xEF3F: + +// ROLD +case 0xE138: +{ + u32 res; + pointer src; + u32 sft; + + sft = CPU->D[(Opcode >> 9) & 7] & 0x3F; + src = (u8)CPU->D[(Opcode >> 0) & 7]; + if (sft) + { + CCnt -= sft * 2; + if (sft &= 0x07) + { + CPU->flag_C = (src << sft) >> 0; + res = ((src << sft) | (src >> (8 - sft))) & 0x000000FF; + CPU->flag_V = 0; + CPU->flag_N = res >> 0; + CPU->flag_notZ = res; + *(BYTE_OFF + (u8*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(6) + } + + CPU->flag_V = 0; + CPU->flag_C = src << C68K_SR_C_SFT; + CPU->flag_N = src >> 0; + CPU->flag_notZ = src; + RET(6) + } + + CPU->flag_V = 0; + CPU->flag_C = 0; + CPU->flag_N = src >> 0; + CPU->flag_notZ = src; +} +RET(6) +case 0xE378: +case 0xE578: +case 0xE778: +case 0xE978: +case 0xEB78: +case 0xED78: +case 0xEF78: +case 0xE179: +case 0xE379: +case 0xE579: +case 0xE779: +case 0xE979: +case 0xEB79: +case 0xED79: +case 0xEF79: +case 0xE17A: +case 0xE37A: +case 0xE57A: +case 0xE77A: +case 0xE97A: +case 0xEB7A: +case 0xED7A: +case 0xEF7A: +case 0xE17B: +case 0xE37B: +case 0xE57B: +case 0xE77B: +case 0xE97B: +case 0xEB7B: +case 0xED7B: +case 0xEF7B: +case 0xE17C: +case 0xE37C: +case 0xE57C: +case 0xE77C: +case 0xE97C: +case 0xEB7C: +case 0xED7C: +case 0xEF7C: +case 0xE17D: +case 0xE37D: +case 0xE57D: +case 0xE77D: +case 0xE97D: +case 0xEB7D: +case 0xED7D: +case 0xEF7D: +case 0xE17E: +case 0xE37E: +case 0xE57E: +case 0xE77E: +case 0xE97E: +case 0xEB7E: +case 0xED7E: +case 0xEF7E: +case 0xE17F: +case 0xE37F: +case 0xE57F: +case 0xE77F: +case 0xE97F: +case 0xEB7F: +case 0xED7F: +case 0xEF7F: + +// ROLD +case 0xE178: +{ + u32 res; + pointer src; + u32 sft; + + sft = CPU->D[(Opcode >> 9) & 7] & 0x3F; + src = (u16)CPU->D[(Opcode >> 0) & 7]; + if (sft) + { + CCnt -= sft * 2; + if (sft &= 0x0F) + { + CPU->flag_C = (src << sft) >> 8; + res = ((src << sft) | (src >> (16 - sft))) & 0x0000FFFF; + CPU->flag_V = 0; + CPU->flag_N = res >> 8; + CPU->flag_notZ = res; + *(WORD_OFF + (u16*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(6) + } + + CPU->flag_V = 0; + CPU->flag_C = src << C68K_SR_C_SFT; + CPU->flag_N = src >> 8; + CPU->flag_notZ = src; + RET(6) + } + + CPU->flag_V = 0; + CPU->flag_C = 0; + CPU->flag_N = src >> 8; + CPU->flag_notZ = src; +} +RET(6) +case 0xE3B8: +case 0xE5B8: +case 0xE7B8: +case 0xE9B8: +case 0xEBB8: +case 0xEDB8: +case 0xEFB8: +case 0xE1B9: +case 0xE3B9: +case 0xE5B9: +case 0xE7B9: +case 0xE9B9: +case 0xEBB9: +case 0xEDB9: +case 0xEFB9: +case 0xE1BA: +case 0xE3BA: +case 0xE5BA: +case 0xE7BA: +case 0xE9BA: +case 0xEBBA: +case 0xEDBA: +case 0xEFBA: +case 0xE1BB: +case 0xE3BB: +case 0xE5BB: +case 0xE7BB: +case 0xE9BB: +case 0xEBBB: +case 0xEDBB: +case 0xEFBB: +case 0xE1BC: +case 0xE3BC: +case 0xE5BC: +case 0xE7BC: +case 0xE9BC: +case 0xEBBC: +case 0xEDBC: +case 0xEFBC: +case 0xE1BD: +case 0xE3BD: +case 0xE5BD: +case 0xE7BD: +case 0xE9BD: +case 0xEBBD: +case 0xEDBD: +case 0xEFBD: +case 0xE1BE: +case 0xE3BE: +case 0xE5BE: +case 0xE7BE: +case 0xE9BE: +case 0xEBBE: +case 0xEDBE: +case 0xEFBE: +case 0xE1BF: +case 0xE3BF: +case 0xE5BF: +case 0xE7BF: +case 0xE9BF: +case 0xEBBF: +case 0xEDBF: +case 0xEFBF: + +// ROLD +case 0xE1B8: +{ + u32 res; + pointer src; + u32 sft; + + sft = CPU->D[(Opcode >> 9) & 7] & 0x3F; + src = (u32)CPU->D[(Opcode >> 0) & 7]; + if (sft) + { + CCnt -= sft * 2; + if (sft &= 0x1F) + { + CPU->flag_C = (src >> (32 - sft)) << C68K_SR_C_SFT; + res = (src << sft) | (src >> (32 - sft)); + CPU->flag_V = 0; + CPU->flag_N = res >> 24; + CPU->flag_notZ = res; + *((u32*)(&CPU->D[(Opcode >> 0) & 7])) = res; + RET(8) + } + + CPU->flag_V = 0; + CPU->flag_C = src << C68K_SR_C_SFT; + CPU->flag_N = src >> 24; + CPU->flag_notZ = src; + RET(8) + } + + CPU->flag_V = 0; + CPU->flag_C = 0; + CPU->flag_N = src >> 24; + CPU->flag_notZ = src; +} +RET(8) +case 0xE0D1: +case 0xE0D2: +case 0xE0D3: +case 0xE0D4: +case 0xE0D5: +case 0xE0D6: +case 0xE0D7: + +// ASR +case 0xE0D0: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_V = 0; + CPU->flag_X = CPU->flag_C = src << C68K_SR_C_SFT; + res = (src >> 1) | (src & (1 << 15)); + CPU->flag_N = res >> 8; + CPU->flag_notZ = res; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0xE0D9: +case 0xE0DA: +case 0xE0DB: +case 0xE0DC: +case 0xE0DD: +case 0xE0DE: + +// ASR +case 0xE0D8: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 2; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_V = 0; + CPU->flag_X = CPU->flag_C = src << C68K_SR_C_SFT; + res = (src >> 1) | (src & (1 << 15)); + CPU->flag_N = res >> 8; + CPU->flag_notZ = res; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0xE0E1: +case 0xE0E2: +case 0xE0E3: +case 0xE0E4: +case 0xE0E5: +case 0xE0E6: + +// ASR +case 0xE0E0: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 2; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_V = 0; + CPU->flag_X = CPU->flag_C = src << C68K_SR_C_SFT; + res = (src >> 1) | (src & (1 << 15)); + CPU->flag_N = res >> 8; + CPU->flag_notZ = res; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(14) +case 0xE0E9: +case 0xE0EA: +case 0xE0EB: +case 0xE0EC: +case 0xE0ED: +case 0xE0EE: +case 0xE0EF: + +// ASR +case 0xE0E8: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_V = 0; + CPU->flag_X = CPU->flag_C = src << C68K_SR_C_SFT; + res = (src >> 1) | (src & (1 << 15)); + CPU->flag_N = res >> 8; + CPU->flag_notZ = res; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0xE0F1: +case 0xE0F2: +case 0xE0F3: +case 0xE0F4: +case 0xE0F5: +case 0xE0F6: +case 0xE0F7: + +// ASR +case 0xE0F0: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_V = 0; + CPU->flag_X = CPU->flag_C = src << C68K_SR_C_SFT; + res = (src >> 1) | (src & (1 << 15)); + CPU->flag_N = res >> 8; + CPU->flag_notZ = res; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(18) + +// ASR +case 0xE0F8: +{ + u32 adr; + u32 res; + pointer src; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_V = 0; + CPU->flag_X = CPU->flag_C = src << C68K_SR_C_SFT; + res = (src >> 1) | (src & (1 << 15)); + CPU->flag_N = res >> 8; + CPU->flag_notZ = res; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) + +// ASR +case 0xE0F9: +{ + u32 adr; + u32 res; + pointer src; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_V = 0; + CPU->flag_X = CPU->flag_C = src << C68K_SR_C_SFT; + res = (src >> 1) | (src & (1 << 15)); + CPU->flag_N = res >> 8; + CPU->flag_notZ = res; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(20) + +// ASR +case 0xE0DF: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_V = 0; + CPU->flag_X = CPU->flag_C = src << C68K_SR_C_SFT; + res = (src >> 1) | (src & (1 << 15)); + CPU->flag_N = res >> 8; + CPU->flag_notZ = res; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) + +// ASR +case 0xE0E7: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_V = 0; + CPU->flag_X = CPU->flag_C = src << C68K_SR_C_SFT; + res = (src >> 1) | (src & (1 << 15)); + CPU->flag_N = res >> 8; + CPU->flag_notZ = res; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(14) +case 0xE2D1: +case 0xE2D2: +case 0xE2D3: +case 0xE2D4: +case 0xE2D5: +case 0xE2D6: +case 0xE2D7: + +// LSR +case 0xE2D0: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_N = CPU->flag_V = 0; + CPU->flag_X = CPU->flag_C = src << C68K_SR_C_SFT; + res = src >> 1; + CPU->flag_notZ = res; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0xE2D9: +case 0xE2DA: +case 0xE2DB: +case 0xE2DC: +case 0xE2DD: +case 0xE2DE: + +// LSR +case 0xE2D8: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 2; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_N = CPU->flag_V = 0; + CPU->flag_X = CPU->flag_C = src << C68K_SR_C_SFT; + res = src >> 1; + CPU->flag_notZ = res; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0xE2E1: +case 0xE2E2: +case 0xE2E3: +case 0xE2E4: +case 0xE2E5: +case 0xE2E6: + +// LSR +case 0xE2E0: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 2; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_N = CPU->flag_V = 0; + CPU->flag_X = CPU->flag_C = src << C68K_SR_C_SFT; + res = src >> 1; + CPU->flag_notZ = res; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(14) +case 0xE2E9: +case 0xE2EA: +case 0xE2EB: +case 0xE2EC: +case 0xE2ED: +case 0xE2EE: +case 0xE2EF: + +// LSR +case 0xE2E8: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_N = CPU->flag_V = 0; + CPU->flag_X = CPU->flag_C = src << C68K_SR_C_SFT; + res = src >> 1; + CPU->flag_notZ = res; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0xE2F1: +case 0xE2F2: +case 0xE2F3: +case 0xE2F4: +case 0xE2F5: +case 0xE2F6: +case 0xE2F7: + +// LSR +case 0xE2F0: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_N = CPU->flag_V = 0; + CPU->flag_X = CPU->flag_C = src << C68K_SR_C_SFT; + res = src >> 1; + CPU->flag_notZ = res; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(18) + +// LSR +case 0xE2F8: +{ + u32 adr; + u32 res; + pointer src; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_N = CPU->flag_V = 0; + CPU->flag_X = CPU->flag_C = src << C68K_SR_C_SFT; + res = src >> 1; + CPU->flag_notZ = res; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) + +// LSR +case 0xE2F9: +{ + u32 adr; + u32 res; + pointer src; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_N = CPU->flag_V = 0; + CPU->flag_X = CPU->flag_C = src << C68K_SR_C_SFT; + res = src >> 1; + CPU->flag_notZ = res; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(20) + +// LSR +case 0xE2DF: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_N = CPU->flag_V = 0; + CPU->flag_X = CPU->flag_C = src << C68K_SR_C_SFT; + res = src >> 1; + CPU->flag_notZ = res; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) + +// LSR +case 0xE2E7: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_N = CPU->flag_V = 0; + CPU->flag_X = CPU->flag_C = src << C68K_SR_C_SFT; + res = src >> 1; + CPU->flag_notZ = res; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(14) +case 0xE4D1: +case 0xE4D2: +case 0xE4D3: +case 0xE4D4: +case 0xE4D5: +case 0xE4D6: +case 0xE4D7: + +// ROXR +case 0xE4D0: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_V = 0; + res = (src >> 1) | ((CPU->flag_X & C68K_SR_X) << 7); + CPU->flag_C = CPU->flag_X = src << C68K_SR_C_SFT; + CPU->flag_N = res >> 8; + CPU->flag_notZ = res; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0xE4D9: +case 0xE4DA: +case 0xE4DB: +case 0xE4DC: +case 0xE4DD: +case 0xE4DE: + +// ROXR +case 0xE4D8: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 2; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_V = 0; + res = (src >> 1) | ((CPU->flag_X & C68K_SR_X) << 7); + CPU->flag_C = CPU->flag_X = src << C68K_SR_C_SFT; + CPU->flag_N = res >> 8; + CPU->flag_notZ = res; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0xE4E1: +case 0xE4E2: +case 0xE4E3: +case 0xE4E4: +case 0xE4E5: +case 0xE4E6: + +// ROXR +case 0xE4E0: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 2; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_V = 0; + res = (src >> 1) | ((CPU->flag_X & C68K_SR_X) << 7); + CPU->flag_C = CPU->flag_X = src << C68K_SR_C_SFT; + CPU->flag_N = res >> 8; + CPU->flag_notZ = res; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(14) +case 0xE4E9: +case 0xE4EA: +case 0xE4EB: +case 0xE4EC: +case 0xE4ED: +case 0xE4EE: +case 0xE4EF: + +// ROXR +case 0xE4E8: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_V = 0; + res = (src >> 1) | ((CPU->flag_X & C68K_SR_X) << 7); + CPU->flag_C = CPU->flag_X = src << C68K_SR_C_SFT; + CPU->flag_N = res >> 8; + CPU->flag_notZ = res; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0xE4F1: +case 0xE4F2: +case 0xE4F3: +case 0xE4F4: +case 0xE4F5: +case 0xE4F6: +case 0xE4F7: + +// ROXR +case 0xE4F0: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_V = 0; + res = (src >> 1) | ((CPU->flag_X & C68K_SR_X) << 7); + CPU->flag_C = CPU->flag_X = src << C68K_SR_C_SFT; + CPU->flag_N = res >> 8; + CPU->flag_notZ = res; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(18) + +// ROXR +case 0xE4F8: +{ + u32 adr; + u32 res; + pointer src; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_V = 0; + res = (src >> 1) | ((CPU->flag_X & C68K_SR_X) << 7); + CPU->flag_C = CPU->flag_X = src << C68K_SR_C_SFT; + CPU->flag_N = res >> 8; + CPU->flag_notZ = res; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) + +// ROXR +case 0xE4F9: +{ + u32 adr; + u32 res; + pointer src; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_V = 0; + res = (src >> 1) | ((CPU->flag_X & C68K_SR_X) << 7); + CPU->flag_C = CPU->flag_X = src << C68K_SR_C_SFT; + CPU->flag_N = res >> 8; + CPU->flag_notZ = res; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(20) + +// ROXR +case 0xE4DF: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_V = 0; + res = (src >> 1) | ((CPU->flag_X & C68K_SR_X) << 7); + CPU->flag_C = CPU->flag_X = src << C68K_SR_C_SFT; + CPU->flag_N = res >> 8; + CPU->flag_notZ = res; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) + +// ROXR +case 0xE4E7: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_V = 0; + res = (src >> 1) | ((CPU->flag_X & C68K_SR_X) << 7); + CPU->flag_C = CPU->flag_X = src << C68K_SR_C_SFT; + CPU->flag_N = res >> 8; + CPU->flag_notZ = res; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(14) +case 0xE6D1: +case 0xE6D2: +case 0xE6D3: +case 0xE6D4: +case 0xE6D5: +case 0xE6D6: +case 0xE6D7: + +// ROR +case 0xE6D0: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_V = 0; + CPU->flag_C = src << C68K_SR_C_SFT; + res = (src >> 1) | (src << 15); + CPU->flag_N = res >> 8; + CPU->flag_notZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0xE6D9: +case 0xE6DA: +case 0xE6DB: +case 0xE6DC: +case 0xE6DD: +case 0xE6DE: + +// ROR +case 0xE6D8: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 2; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_V = 0; + CPU->flag_C = src << C68K_SR_C_SFT; + res = (src >> 1) | (src << 15); + CPU->flag_N = res >> 8; + CPU->flag_notZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0xE6E1: +case 0xE6E2: +case 0xE6E3: +case 0xE6E4: +case 0xE6E5: +case 0xE6E6: + +// ROR +case 0xE6E0: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 2; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_V = 0; + CPU->flag_C = src << C68K_SR_C_SFT; + res = (src >> 1) | (src << 15); + CPU->flag_N = res >> 8; + CPU->flag_notZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(14) +case 0xE6E9: +case 0xE6EA: +case 0xE6EB: +case 0xE6EC: +case 0xE6ED: +case 0xE6EE: +case 0xE6EF: + +// ROR +case 0xE6E8: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_V = 0; + CPU->flag_C = src << C68K_SR_C_SFT; + res = (src >> 1) | (src << 15); + CPU->flag_N = res >> 8; + CPU->flag_notZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0xE6F1: +case 0xE6F2: +case 0xE6F3: +case 0xE6F4: +case 0xE6F5: +case 0xE6F6: +case 0xE6F7: + +// ROR +case 0xE6F0: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_V = 0; + CPU->flag_C = src << C68K_SR_C_SFT; + res = (src >> 1) | (src << 15); + CPU->flag_N = res >> 8; + CPU->flag_notZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(18) + +// ROR +case 0xE6F8: +{ + u32 adr; + u32 res; + pointer src; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_V = 0; + CPU->flag_C = src << C68K_SR_C_SFT; + res = (src >> 1) | (src << 15); + CPU->flag_N = res >> 8; + CPU->flag_notZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) + +// ROR +case 0xE6F9: +{ + u32 adr; + u32 res; + pointer src; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_V = 0; + CPU->flag_C = src << C68K_SR_C_SFT; + res = (src >> 1) | (src << 15); + CPU->flag_N = res >> 8; + CPU->flag_notZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(20) + +// ROR +case 0xE6DF: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_V = 0; + CPU->flag_C = src << C68K_SR_C_SFT; + res = (src >> 1) | (src << 15); + CPU->flag_N = res >> 8; + CPU->flag_notZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) + +// ROR +case 0xE6E7: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_V = 0; + CPU->flag_C = src << C68K_SR_C_SFT; + res = (src >> 1) | (src << 15); + CPU->flag_N = res >> 8; + CPU->flag_notZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(14) +case 0xE1D1: +case 0xE1D2: +case 0xE1D3: +case 0xE1D4: +case 0xE1D5: +case 0xE1D6: +case 0xE1D7: + +// ASL +case 0xE1D0: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_X = CPU->flag_C = src >> 7; + res = src << 1; + CPU->flag_V = (src ^ res) >> 8; + CPU->flag_N = res >> 8; + CPU->flag_notZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0xE1D9: +case 0xE1DA: +case 0xE1DB: +case 0xE1DC: +case 0xE1DD: +case 0xE1DE: + +// ASL +case 0xE1D8: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 2; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_X = CPU->flag_C = src >> 7; + res = src << 1; + CPU->flag_V = (src ^ res) >> 8; + CPU->flag_N = res >> 8; + CPU->flag_notZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0xE1E1: +case 0xE1E2: +case 0xE1E3: +case 0xE1E4: +case 0xE1E5: +case 0xE1E6: + +// ASL +case 0xE1E0: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 2; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_X = CPU->flag_C = src >> 7; + res = src << 1; + CPU->flag_V = (src ^ res) >> 8; + CPU->flag_N = res >> 8; + CPU->flag_notZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(14) +case 0xE1E9: +case 0xE1EA: +case 0xE1EB: +case 0xE1EC: +case 0xE1ED: +case 0xE1EE: +case 0xE1EF: + +// ASL +case 0xE1E8: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_X = CPU->flag_C = src >> 7; + res = src << 1; + CPU->flag_V = (src ^ res) >> 8; + CPU->flag_N = res >> 8; + CPU->flag_notZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0xE1F1: +case 0xE1F2: +case 0xE1F3: +case 0xE1F4: +case 0xE1F5: +case 0xE1F6: +case 0xE1F7: + +// ASL +case 0xE1F0: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_X = CPU->flag_C = src >> 7; + res = src << 1; + CPU->flag_V = (src ^ res) >> 8; + CPU->flag_N = res >> 8; + CPU->flag_notZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(18) + +// ASL +case 0xE1F8: +{ + u32 adr; + u32 res; + pointer src; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_X = CPU->flag_C = src >> 7; + res = src << 1; + CPU->flag_V = (src ^ res) >> 8; + CPU->flag_N = res >> 8; + CPU->flag_notZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) + +// ASL +case 0xE1F9: +{ + u32 adr; + u32 res; + pointer src; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_X = CPU->flag_C = src >> 7; + res = src << 1; + CPU->flag_V = (src ^ res) >> 8; + CPU->flag_N = res >> 8; + CPU->flag_notZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(20) + +// ASL +case 0xE1DF: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_X = CPU->flag_C = src >> 7; + res = src << 1; + CPU->flag_V = (src ^ res) >> 8; + CPU->flag_N = res >> 8; + CPU->flag_notZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) + +// ASL +case 0xE1E7: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_X = CPU->flag_C = src >> 7; + res = src << 1; + CPU->flag_V = (src ^ res) >> 8; + CPU->flag_N = res >> 8; + CPU->flag_notZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(14) +case 0xE3D1: +case 0xE3D2: +case 0xE3D3: +case 0xE3D4: +case 0xE3D5: +case 0xE3D6: +case 0xE3D7: + +// LSL +case 0xE3D0: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_V = 0; + CPU->flag_X = CPU->flag_C = src >> 7; + res = src << 1; + CPU->flag_N = res >> 8; + CPU->flag_notZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0xE3D9: +case 0xE3DA: +case 0xE3DB: +case 0xE3DC: +case 0xE3DD: +case 0xE3DE: + +// LSL +case 0xE3D8: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 2; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_V = 0; + CPU->flag_X = CPU->flag_C = src >> 7; + res = src << 1; + CPU->flag_N = res >> 8; + CPU->flag_notZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0xE3E1: +case 0xE3E2: +case 0xE3E3: +case 0xE3E4: +case 0xE3E5: +case 0xE3E6: + +// LSL +case 0xE3E0: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 2; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_V = 0; + CPU->flag_X = CPU->flag_C = src >> 7; + res = src << 1; + CPU->flag_N = res >> 8; + CPU->flag_notZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(14) +case 0xE3E9: +case 0xE3EA: +case 0xE3EB: +case 0xE3EC: +case 0xE3ED: +case 0xE3EE: +case 0xE3EF: + +// LSL +case 0xE3E8: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_V = 0; + CPU->flag_X = CPU->flag_C = src >> 7; + res = src << 1; + CPU->flag_N = res >> 8; + CPU->flag_notZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0xE3F1: +case 0xE3F2: +case 0xE3F3: +case 0xE3F4: +case 0xE3F5: +case 0xE3F6: +case 0xE3F7: + +// LSL +case 0xE3F0: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_V = 0; + CPU->flag_X = CPU->flag_C = src >> 7; + res = src << 1; + CPU->flag_N = res >> 8; + CPU->flag_notZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(18) + +// LSL +case 0xE3F8: +{ + u32 adr; + u32 res; + pointer src; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_V = 0; + CPU->flag_X = CPU->flag_C = src >> 7; + res = src << 1; + CPU->flag_N = res >> 8; + CPU->flag_notZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) + +// LSL +case 0xE3F9: +{ + u32 adr; + u32 res; + pointer src; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_V = 0; + CPU->flag_X = CPU->flag_C = src >> 7; + res = src << 1; + CPU->flag_N = res >> 8; + CPU->flag_notZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(20) + +// LSL +case 0xE3DF: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_V = 0; + CPU->flag_X = CPU->flag_C = src >> 7; + res = src << 1; + CPU->flag_N = res >> 8; + CPU->flag_notZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) + +// LSL +case 0xE3E7: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_V = 0; + CPU->flag_X = CPU->flag_C = src >> 7; + res = src << 1; + CPU->flag_N = res >> 8; + CPU->flag_notZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(14) +case 0xE5D1: +case 0xE5D2: +case 0xE5D3: +case 0xE5D4: +case 0xE5D5: +case 0xE5D6: +case 0xE5D7: + +// ROXL +case 0xE5D0: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_V = 0; + res = (src << 1) | ((CPU->flag_X & C68K_SR_X) >> 8); + CPU->flag_X = CPU->flag_C = src >> 7; + CPU->flag_N = res >> 8; + CPU->flag_notZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0xE5D9: +case 0xE5DA: +case 0xE5DB: +case 0xE5DC: +case 0xE5DD: +case 0xE5DE: + +// ROXL +case 0xE5D8: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 2; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_V = 0; + res = (src << 1) | ((CPU->flag_X & C68K_SR_X) >> 8); + CPU->flag_X = CPU->flag_C = src >> 7; + CPU->flag_N = res >> 8; + CPU->flag_notZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0xE5E1: +case 0xE5E2: +case 0xE5E3: +case 0xE5E4: +case 0xE5E5: +case 0xE5E6: + +// ROXL +case 0xE5E0: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 2; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_V = 0; + res = (src << 1) | ((CPU->flag_X & C68K_SR_X) >> 8); + CPU->flag_X = CPU->flag_C = src >> 7; + CPU->flag_N = res >> 8; + CPU->flag_notZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(14) +case 0xE5E9: +case 0xE5EA: +case 0xE5EB: +case 0xE5EC: +case 0xE5ED: +case 0xE5EE: +case 0xE5EF: + +// ROXL +case 0xE5E8: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_V = 0; + res = (src << 1) | ((CPU->flag_X & C68K_SR_X) >> 8); + CPU->flag_X = CPU->flag_C = src >> 7; + CPU->flag_N = res >> 8; + CPU->flag_notZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0xE5F1: +case 0xE5F2: +case 0xE5F3: +case 0xE5F4: +case 0xE5F5: +case 0xE5F6: +case 0xE5F7: + +// ROXL +case 0xE5F0: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_V = 0; + res = (src << 1) | ((CPU->flag_X & C68K_SR_X) >> 8); + CPU->flag_X = CPU->flag_C = src >> 7; + CPU->flag_N = res >> 8; + CPU->flag_notZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(18) + +// ROXL +case 0xE5F8: +{ + u32 adr; + u32 res; + pointer src; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_V = 0; + res = (src << 1) | ((CPU->flag_X & C68K_SR_X) >> 8); + CPU->flag_X = CPU->flag_C = src >> 7; + CPU->flag_N = res >> 8; + CPU->flag_notZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) + +// ROXL +case 0xE5F9: +{ + u32 adr; + u32 res; + pointer src; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_V = 0; + res = (src << 1) | ((CPU->flag_X & C68K_SR_X) >> 8); + CPU->flag_X = CPU->flag_C = src >> 7; + CPU->flag_N = res >> 8; + CPU->flag_notZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(20) + +// ROXL +case 0xE5DF: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_V = 0; + res = (src << 1) | ((CPU->flag_X & C68K_SR_X) >> 8); + CPU->flag_X = CPU->flag_C = src >> 7; + CPU->flag_N = res >> 8; + CPU->flag_notZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) + +// ROXL +case 0xE5E7: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_V = 0; + res = (src << 1) | ((CPU->flag_X & C68K_SR_X) >> 8); + CPU->flag_X = CPU->flag_C = src >> 7; + CPU->flag_N = res >> 8; + CPU->flag_notZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(14) +case 0xE7D1: +case 0xE7D2: +case 0xE7D3: +case 0xE7D4: +case 0xE7D5: +case 0xE7D6: +case 0xE7D7: + +// ROL +case 0xE7D0: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_V = 0; + CPU->flag_C = src >> 7; + res = (src << 1) | (src >> 15); + CPU->flag_N = res >> 8; + CPU->flag_notZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0xE7D9: +case 0xE7DA: +case 0xE7DB: +case 0xE7DC: +case 0xE7DD: +case 0xE7DE: + +// ROL +case 0xE7D8: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + CPU->A[(Opcode >> 0) & 7] += 2; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_V = 0; + CPU->flag_C = src >> 7; + res = (src << 1) | (src >> 15); + CPU->flag_N = res >> 8; + CPU->flag_notZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) +case 0xE7E1: +case 0xE7E2: +case 0xE7E3: +case 0xE7E4: +case 0xE7E5: +case 0xE7E6: + +// ROL +case 0xE7E0: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] - 2; + CPU->A[(Opcode >> 0) & 7] = adr; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_V = 0; + CPU->flag_C = src >> 7; + res = (src << 1) | (src >> 15); + CPU->flag_N = res >> 8; + CPU->flag_notZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(14) +case 0xE7E9: +case 0xE7EA: +case 0xE7EB: +case 0xE7EC: +case 0xE7ED: +case 0xE7EE: +case 0xE7EF: + +// ROL +case 0xE7E8: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7] + (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_V = 0; + CPU->flag_C = src >> 7; + res = (src << 1) | (src >> 15); + CPU->flag_N = res >> 8; + CPU->flag_notZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) +case 0xE7F1: +case 0xE7F2: +case 0xE7F3: +case 0xE7F4: +case 0xE7F5: +case 0xE7F6: +case 0xE7F7: + +// ROL +case 0xE7F0: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[(Opcode >> 0) & 7]; + DECODE_EXT_WORD + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_V = 0; + CPU->flag_C = src >> 7; + res = (src << 1) | (src >> 15); + CPU->flag_N = res >> 8; + CPU->flag_notZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(18) + +// ROL +case 0xE7F8: +{ + u32 adr; + u32 res; + pointer src; + adr = (s32)(s16)FETCH_WORD; + PC += 2; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_V = 0; + CPU->flag_C = src >> 7; + res = (src << 1) | (src >> 15); + CPU->flag_N = res >> 8; + CPU->flag_notZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(16) + +// ROL +case 0xE7F9: +{ + u32 adr; + u32 res; + pointer src; + adr = (s32)FETCH_LONG; + PC += 4; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_V = 0; + CPU->flag_C = src >> 7; + res = (src << 1) | (src >> 15); + CPU->flag_N = res >> 8; + CPU->flag_notZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(20) + +// ROL +case 0xE7DF: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[7]; + CPU->A[7] += 2; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_V = 0; + CPU->flag_C = src >> 7; + res = (src << 1) | (src >> 15); + CPU->flag_N = res >> 8; + CPU->flag_notZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(12) + +// ROL +case 0xE7E7: +{ + u32 adr; + u32 res; + pointer src; + adr = CPU->A[7] - 2; + CPU->A[7] = adr; + PRE_IO + READ_WORD_F(adr, src) + CPU->flag_V = 0; + CPU->flag_C = src >> 7; + res = (src << 1) | (src >> 15); + CPU->flag_N = res >> 8; + CPU->flag_notZ = res & 0x0000FFFF; + WRITE_WORD_F(adr, res) + POST_IO +} +RET(14) diff --git a/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68k_opF.inc b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68k_opF.inc new file mode 100644 index 000000000..df3f1b6de --- /dev/null +++ b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68k_opF.inc @@ -0,0 +1,4118 @@ +case 0xF001: +case 0xF002: +case 0xF003: +case 0xF004: +case 0xF005: +case 0xF006: +case 0xF007: +case 0xF008: +case 0xF009: +case 0xF00A: +case 0xF00B: +case 0xF00C: +case 0xF00D: +case 0xF00E: +case 0xF00F: +case 0xF010: +case 0xF011: +case 0xF012: +case 0xF013: +case 0xF014: +case 0xF015: +case 0xF016: +case 0xF017: +case 0xF018: +case 0xF019: +case 0xF01A: +case 0xF01B: +case 0xF01C: +case 0xF01D: +case 0xF01E: +case 0xF01F: +case 0xF020: +case 0xF021: +case 0xF022: +case 0xF023: +case 0xF024: +case 0xF025: +case 0xF026: +case 0xF027: +case 0xF028: +case 0xF029: +case 0xF02A: +case 0xF02B: +case 0xF02C: +case 0xF02D: +case 0xF02E: +case 0xF02F: +case 0xF030: +case 0xF031: +case 0xF032: +case 0xF033: +case 0xF034: +case 0xF035: +case 0xF036: +case 0xF037: +case 0xF038: +case 0xF039: +case 0xF03A: +case 0xF03B: +case 0xF03C: +case 0xF03D: +case 0xF03E: +case 0xF03F: +case 0xF040: +case 0xF041: +case 0xF042: +case 0xF043: +case 0xF044: +case 0xF045: +case 0xF046: +case 0xF047: +case 0xF048: +case 0xF049: +case 0xF04A: +case 0xF04B: +case 0xF04C: +case 0xF04D: +case 0xF04E: +case 0xF04F: +case 0xF050: +case 0xF051: +case 0xF052: +case 0xF053: +case 0xF054: +case 0xF055: +case 0xF056: +case 0xF057: +case 0xF058: +case 0xF059: +case 0xF05A: +case 0xF05B: +case 0xF05C: +case 0xF05D: +case 0xF05E: +case 0xF05F: +case 0xF060: +case 0xF061: +case 0xF062: +case 0xF063: +case 0xF064: +case 0xF065: +case 0xF066: +case 0xF067: +case 0xF068: +case 0xF069: +case 0xF06A: +case 0xF06B: +case 0xF06C: +case 0xF06D: +case 0xF06E: +case 0xF06F: +case 0xF070: +case 0xF071: +case 0xF072: +case 0xF073: +case 0xF074: +case 0xF075: +case 0xF076: +case 0xF077: +case 0xF078: +case 0xF079: +case 0xF07A: +case 0xF07B: +case 0xF07C: +case 0xF07D: +case 0xF07E: +case 0xF07F: +case 0xF080: +case 0xF081: +case 0xF082: +case 0xF083: +case 0xF084: +case 0xF085: +case 0xF086: +case 0xF087: +case 0xF088: +case 0xF089: +case 0xF08A: +case 0xF08B: +case 0xF08C: +case 0xF08D: +case 0xF08E: +case 0xF08F: +case 0xF090: +case 0xF091: +case 0xF092: +case 0xF093: +case 0xF094: +case 0xF095: +case 0xF096: +case 0xF097: +case 0xF098: +case 0xF099: +case 0xF09A: +case 0xF09B: +case 0xF09C: +case 0xF09D: +case 0xF09E: +case 0xF09F: +case 0xF0A0: +case 0xF0A1: +case 0xF0A2: +case 0xF0A3: +case 0xF0A4: +case 0xF0A5: +case 0xF0A6: +case 0xF0A7: +case 0xF0A8: +case 0xF0A9: +case 0xF0AA: +case 0xF0AB: +case 0xF0AC: +case 0xF0AD: +case 0xF0AE: +case 0xF0AF: +case 0xF0B0: +case 0xF0B1: +case 0xF0B2: +case 0xF0B3: +case 0xF0B4: +case 0xF0B5: +case 0xF0B6: +case 0xF0B7: +case 0xF0B8: +case 0xF0B9: +case 0xF0BA: +case 0xF0BB: +case 0xF0BC: +case 0xF0BD: +case 0xF0BE: +case 0xF0BF: +case 0xF0C0: +case 0xF0C1: +case 0xF0C2: +case 0xF0C3: +case 0xF0C4: +case 0xF0C5: +case 0xF0C6: +case 0xF0C7: +case 0xF0C8: +case 0xF0C9: +case 0xF0CA: +case 0xF0CB: +case 0xF0CC: +case 0xF0CD: +case 0xF0CE: +case 0xF0CF: +case 0xF0D0: +case 0xF0D1: +case 0xF0D2: +case 0xF0D3: +case 0xF0D4: +case 0xF0D5: +case 0xF0D6: +case 0xF0D7: +case 0xF0D8: +case 0xF0D9: +case 0xF0DA: +case 0xF0DB: +case 0xF0DC: +case 0xF0DD: +case 0xF0DE: +case 0xF0DF: +case 0xF0E0: +case 0xF0E1: +case 0xF0E2: +case 0xF0E3: +case 0xF0E4: +case 0xF0E5: +case 0xF0E6: +case 0xF0E7: +case 0xF0E8: +case 0xF0E9: +case 0xF0EA: +case 0xF0EB: +case 0xF0EC: +case 0xF0ED: +case 0xF0EE: +case 0xF0EF: +case 0xF0F0: +case 0xF0F1: +case 0xF0F2: +case 0xF0F3: +case 0xF0F4: +case 0xF0F5: +case 0xF0F6: +case 0xF0F7: +case 0xF0F8: +case 0xF0F9: +case 0xF0FA: +case 0xF0FB: +case 0xF0FC: +case 0xF0FD: +case 0xF0FE: +case 0xF0FF: +case 0xF100: +case 0xF101: +case 0xF102: +case 0xF103: +case 0xF104: +case 0xF105: +case 0xF106: +case 0xF107: +case 0xF108: +case 0xF109: +case 0xF10A: +case 0xF10B: +case 0xF10C: +case 0xF10D: +case 0xF10E: +case 0xF10F: +case 0xF110: +case 0xF111: +case 0xF112: +case 0xF113: +case 0xF114: +case 0xF115: +case 0xF116: +case 0xF117: +case 0xF118: +case 0xF119: +case 0xF11A: +case 0xF11B: +case 0xF11C: +case 0xF11D: +case 0xF11E: +case 0xF11F: +case 0xF120: +case 0xF121: +case 0xF122: +case 0xF123: +case 0xF124: +case 0xF125: +case 0xF126: +case 0xF127: +case 0xF128: +case 0xF129: +case 0xF12A: +case 0xF12B: +case 0xF12C: +case 0xF12D: +case 0xF12E: +case 0xF12F: +case 0xF130: +case 0xF131: +case 0xF132: +case 0xF133: +case 0xF134: +case 0xF135: +case 0xF136: +case 0xF137: +case 0xF138: +case 0xF139: +case 0xF13A: +case 0xF13B: +case 0xF13C: +case 0xF13D: +case 0xF13E: +case 0xF13F: +case 0xF140: +case 0xF141: +case 0xF142: +case 0xF143: +case 0xF144: +case 0xF145: +case 0xF146: +case 0xF147: +case 0xF148: +case 0xF149: +case 0xF14A: +case 0xF14B: +case 0xF14C: +case 0xF14D: +case 0xF14E: +case 0xF14F: +case 0xF150: +case 0xF151: +case 0xF152: +case 0xF153: +case 0xF154: +case 0xF155: +case 0xF156: +case 0xF157: +case 0xF158: +case 0xF159: +case 0xF15A: +case 0xF15B: +case 0xF15C: +case 0xF15D: +case 0xF15E: +case 0xF15F: +case 0xF160: +case 0xF161: +case 0xF162: +case 0xF163: +case 0xF164: +case 0xF165: +case 0xF166: +case 0xF167: +case 0xF168: +case 0xF169: +case 0xF16A: +case 0xF16B: +case 0xF16C: +case 0xF16D: +case 0xF16E: +case 0xF16F: +case 0xF170: +case 0xF171: +case 0xF172: +case 0xF173: +case 0xF174: +case 0xF175: +case 0xF176: +case 0xF177: +case 0xF178: +case 0xF179: +case 0xF17A: +case 0xF17B: +case 0xF17C: +case 0xF17D: +case 0xF17E: +case 0xF17F: +case 0xF180: +case 0xF181: +case 0xF182: +case 0xF183: +case 0xF184: +case 0xF185: +case 0xF186: +case 0xF187: +case 0xF188: +case 0xF189: +case 0xF18A: +case 0xF18B: +case 0xF18C: +case 0xF18D: +case 0xF18E: +case 0xF18F: +case 0xF190: +case 0xF191: +case 0xF192: +case 0xF193: +case 0xF194: +case 0xF195: +case 0xF196: +case 0xF197: +case 0xF198: +case 0xF199: +case 0xF19A: +case 0xF19B: +case 0xF19C: +case 0xF19D: +case 0xF19E: +case 0xF19F: +case 0xF1A0: +case 0xF1A1: +case 0xF1A2: +case 0xF1A3: +case 0xF1A4: +case 0xF1A5: +case 0xF1A6: +case 0xF1A7: +case 0xF1A8: +case 0xF1A9: +case 0xF1AA: +case 0xF1AB: +case 0xF1AC: +case 0xF1AD: +case 0xF1AE: +case 0xF1AF: +case 0xF1B0: +case 0xF1B1: +case 0xF1B2: +case 0xF1B3: +case 0xF1B4: +case 0xF1B5: +case 0xF1B6: +case 0xF1B7: +case 0xF1B8: +case 0xF1B9: +case 0xF1BA: +case 0xF1BB: +case 0xF1BC: +case 0xF1BD: +case 0xF1BE: +case 0xF1BF: +case 0xF1C0: +case 0xF1C1: +case 0xF1C2: +case 0xF1C3: +case 0xF1C4: +case 0xF1C5: +case 0xF1C6: +case 0xF1C7: +case 0xF1C8: +case 0xF1C9: +case 0xF1CA: +case 0xF1CB: +case 0xF1CC: +case 0xF1CD: +case 0xF1CE: +case 0xF1CF: +case 0xF1D0: +case 0xF1D1: +case 0xF1D2: +case 0xF1D3: +case 0xF1D4: +case 0xF1D5: +case 0xF1D6: +case 0xF1D7: +case 0xF1D8: +case 0xF1D9: +case 0xF1DA: +case 0xF1DB: +case 0xF1DC: +case 0xF1DD: +case 0xF1DE: +case 0xF1DF: +case 0xF1E0: +case 0xF1E1: +case 0xF1E2: +case 0xF1E3: +case 0xF1E4: +case 0xF1E5: +case 0xF1E6: +case 0xF1E7: +case 0xF1E8: +case 0xF1E9: +case 0xF1EA: +case 0xF1EB: +case 0xF1EC: +case 0xF1ED: +case 0xF1EE: +case 0xF1EF: +case 0xF1F0: +case 0xF1F1: +case 0xF1F2: +case 0xF1F3: +case 0xF1F4: +case 0xF1F5: +case 0xF1F6: +case 0xF1F7: +case 0xF1F8: +case 0xF1F9: +case 0xF1FA: +case 0xF1FB: +case 0xF1FC: +case 0xF1FD: +case 0xF1FE: +case 0xF1FF: +case 0xF200: +case 0xF201: +case 0xF202: +case 0xF203: +case 0xF204: +case 0xF205: +case 0xF206: +case 0xF207: +case 0xF208: +case 0xF209: +case 0xF20A: +case 0xF20B: +case 0xF20C: +case 0xF20D: +case 0xF20E: +case 0xF20F: +case 0xF210: +case 0xF211: +case 0xF212: +case 0xF213: +case 0xF214: +case 0xF215: +case 0xF216: +case 0xF217: +case 0xF218: +case 0xF219: +case 0xF21A: +case 0xF21B: +case 0xF21C: +case 0xF21D: +case 0xF21E: +case 0xF21F: +case 0xF220: +case 0xF221: +case 0xF222: +case 0xF223: +case 0xF224: +case 0xF225: +case 0xF226: +case 0xF227: +case 0xF228: +case 0xF229: +case 0xF22A: +case 0xF22B: +case 0xF22C: +case 0xF22D: +case 0xF22E: +case 0xF22F: +case 0xF230: +case 0xF231: +case 0xF232: +case 0xF233: +case 0xF234: +case 0xF235: +case 0xF236: +case 0xF237: +case 0xF238: +case 0xF239: +case 0xF23A: +case 0xF23B: +case 0xF23C: +case 0xF23D: +case 0xF23E: +case 0xF23F: +case 0xF240: +case 0xF241: +case 0xF242: +case 0xF243: +case 0xF244: +case 0xF245: +case 0xF246: +case 0xF247: +case 0xF248: +case 0xF249: +case 0xF24A: +case 0xF24B: +case 0xF24C: +case 0xF24D: +case 0xF24E: +case 0xF24F: +case 0xF250: +case 0xF251: +case 0xF252: +case 0xF253: +case 0xF254: +case 0xF255: +case 0xF256: +case 0xF257: +case 0xF258: +case 0xF259: +case 0xF25A: +case 0xF25B: +case 0xF25C: +case 0xF25D: +case 0xF25E: +case 0xF25F: +case 0xF260: +case 0xF261: +case 0xF262: +case 0xF263: +case 0xF264: +case 0xF265: +case 0xF266: +case 0xF267: +case 0xF268: +case 0xF269: +case 0xF26A: +case 0xF26B: +case 0xF26C: +case 0xF26D: +case 0xF26E: +case 0xF26F: +case 0xF270: +case 0xF271: +case 0xF272: +case 0xF273: +case 0xF274: +case 0xF275: +case 0xF276: +case 0xF277: +case 0xF278: +case 0xF279: +case 0xF27A: +case 0xF27B: +case 0xF27C: +case 0xF27D: +case 0xF27E: +case 0xF27F: +case 0xF280: +case 0xF281: +case 0xF282: +case 0xF283: +case 0xF284: +case 0xF285: +case 0xF286: +case 0xF287: +case 0xF288: +case 0xF289: +case 0xF28A: +case 0xF28B: +case 0xF28C: +case 0xF28D: +case 0xF28E: +case 0xF28F: +case 0xF290: +case 0xF291: +case 0xF292: +case 0xF293: +case 0xF294: +case 0xF295: +case 0xF296: +case 0xF297: +case 0xF298: +case 0xF299: +case 0xF29A: +case 0xF29B: +case 0xF29C: +case 0xF29D: +case 0xF29E: +case 0xF29F: +case 0xF2A0: +case 0xF2A1: +case 0xF2A2: +case 0xF2A3: +case 0xF2A4: +case 0xF2A5: +case 0xF2A6: +case 0xF2A7: +case 0xF2A8: +case 0xF2A9: +case 0xF2AA: +case 0xF2AB: +case 0xF2AC: +case 0xF2AD: +case 0xF2AE: +case 0xF2AF: +case 0xF2B0: +case 0xF2B1: +case 0xF2B2: +case 0xF2B3: +case 0xF2B4: +case 0xF2B5: +case 0xF2B6: +case 0xF2B7: +case 0xF2B8: +case 0xF2B9: +case 0xF2BA: +case 0xF2BB: +case 0xF2BC: +case 0xF2BD: +case 0xF2BE: +case 0xF2BF: +case 0xF2C0: +case 0xF2C1: +case 0xF2C2: +case 0xF2C3: +case 0xF2C4: +case 0xF2C5: +case 0xF2C6: +case 0xF2C7: +case 0xF2C8: +case 0xF2C9: +case 0xF2CA: +case 0xF2CB: +case 0xF2CC: +case 0xF2CD: +case 0xF2CE: +case 0xF2CF: +case 0xF2D0: +case 0xF2D1: +case 0xF2D2: +case 0xF2D3: +case 0xF2D4: +case 0xF2D5: +case 0xF2D6: +case 0xF2D7: +case 0xF2D8: +case 0xF2D9: +case 0xF2DA: +case 0xF2DB: +case 0xF2DC: +case 0xF2DD: +case 0xF2DE: +case 0xF2DF: +case 0xF2E0: +case 0xF2E1: +case 0xF2E2: +case 0xF2E3: +case 0xF2E4: +case 0xF2E5: +case 0xF2E6: +case 0xF2E7: +case 0xF2E8: +case 0xF2E9: +case 0xF2EA: +case 0xF2EB: +case 0xF2EC: +case 0xF2ED: +case 0xF2EE: +case 0xF2EF: +case 0xF2F0: +case 0xF2F1: +case 0xF2F2: +case 0xF2F3: +case 0xF2F4: +case 0xF2F5: +case 0xF2F6: +case 0xF2F7: +case 0xF2F8: +case 0xF2F9: +case 0xF2FA: +case 0xF2FB: +case 0xF2FC: +case 0xF2FD: +case 0xF2FE: +case 0xF2FF: +case 0xF300: +case 0xF301: +case 0xF302: +case 0xF303: +case 0xF304: +case 0xF305: +case 0xF306: +case 0xF307: +case 0xF308: +case 0xF309: +case 0xF30A: +case 0xF30B: +case 0xF30C: +case 0xF30D: +case 0xF30E: +case 0xF30F: +case 0xF310: +case 0xF311: +case 0xF312: +case 0xF313: +case 0xF314: +case 0xF315: +case 0xF316: +case 0xF317: +case 0xF318: +case 0xF319: +case 0xF31A: +case 0xF31B: +case 0xF31C: +case 0xF31D: +case 0xF31E: +case 0xF31F: +case 0xF320: +case 0xF321: +case 0xF322: +case 0xF323: +case 0xF324: +case 0xF325: +case 0xF326: +case 0xF327: +case 0xF328: +case 0xF329: +case 0xF32A: +case 0xF32B: +case 0xF32C: +case 0xF32D: +case 0xF32E: +case 0xF32F: +case 0xF330: +case 0xF331: +case 0xF332: +case 0xF333: +case 0xF334: +case 0xF335: +case 0xF336: +case 0xF337: +case 0xF338: +case 0xF339: +case 0xF33A: +case 0xF33B: +case 0xF33C: +case 0xF33D: +case 0xF33E: +case 0xF33F: +case 0xF340: +case 0xF341: +case 0xF342: +case 0xF343: +case 0xF344: +case 0xF345: +case 0xF346: +case 0xF347: +case 0xF348: +case 0xF349: +case 0xF34A: +case 0xF34B: +case 0xF34C: +case 0xF34D: +case 0xF34E: +case 0xF34F: +case 0xF350: +case 0xF351: +case 0xF352: +case 0xF353: +case 0xF354: +case 0xF355: +case 0xF356: +case 0xF357: +case 0xF358: +case 0xF359: +case 0xF35A: +case 0xF35B: +case 0xF35C: +case 0xF35D: +case 0xF35E: +case 0xF35F: +case 0xF360: +case 0xF361: +case 0xF362: +case 0xF363: +case 0xF364: +case 0xF365: +case 0xF366: +case 0xF367: +case 0xF368: +case 0xF369: +case 0xF36A: +case 0xF36B: +case 0xF36C: +case 0xF36D: +case 0xF36E: +case 0xF36F: +case 0xF370: +case 0xF371: +case 0xF372: +case 0xF373: +case 0xF374: +case 0xF375: +case 0xF376: +case 0xF377: +case 0xF378: +case 0xF379: +case 0xF37A: +case 0xF37B: +case 0xF37C: +case 0xF37D: +case 0xF37E: +case 0xF37F: +case 0xF380: +case 0xF381: +case 0xF382: +case 0xF383: +case 0xF384: +case 0xF385: +case 0xF386: +case 0xF387: +case 0xF388: +case 0xF389: +case 0xF38A: +case 0xF38B: +case 0xF38C: +case 0xF38D: +case 0xF38E: +case 0xF38F: +case 0xF390: +case 0xF391: +case 0xF392: +case 0xF393: +case 0xF394: +case 0xF395: +case 0xF396: +case 0xF397: +case 0xF398: +case 0xF399: +case 0xF39A: +case 0xF39B: +case 0xF39C: +case 0xF39D: +case 0xF39E: +case 0xF39F: +case 0xF3A0: +case 0xF3A1: +case 0xF3A2: +case 0xF3A3: +case 0xF3A4: +case 0xF3A5: +case 0xF3A6: +case 0xF3A7: +case 0xF3A8: +case 0xF3A9: +case 0xF3AA: +case 0xF3AB: +case 0xF3AC: +case 0xF3AD: +case 0xF3AE: +case 0xF3AF: +case 0xF3B0: +case 0xF3B1: +case 0xF3B2: +case 0xF3B3: +case 0xF3B4: +case 0xF3B5: +case 0xF3B6: +case 0xF3B7: +case 0xF3B8: +case 0xF3B9: +case 0xF3BA: +case 0xF3BB: +case 0xF3BC: +case 0xF3BD: +case 0xF3BE: +case 0xF3BF: +case 0xF3C0: +case 0xF3C1: +case 0xF3C2: +case 0xF3C3: +case 0xF3C4: +case 0xF3C5: +case 0xF3C6: +case 0xF3C7: +case 0xF3C8: +case 0xF3C9: +case 0xF3CA: +case 0xF3CB: +case 0xF3CC: +case 0xF3CD: +case 0xF3CE: +case 0xF3CF: +case 0xF3D0: +case 0xF3D1: +case 0xF3D2: +case 0xF3D3: +case 0xF3D4: +case 0xF3D5: +case 0xF3D6: +case 0xF3D7: +case 0xF3D8: +case 0xF3D9: +case 0xF3DA: +case 0xF3DB: +case 0xF3DC: +case 0xF3DD: +case 0xF3DE: +case 0xF3DF: +case 0xF3E0: +case 0xF3E1: +case 0xF3E2: +case 0xF3E3: +case 0xF3E4: +case 0xF3E5: +case 0xF3E6: +case 0xF3E7: +case 0xF3E8: +case 0xF3E9: +case 0xF3EA: +case 0xF3EB: +case 0xF3EC: +case 0xF3ED: +case 0xF3EE: +case 0xF3EF: +case 0xF3F0: +case 0xF3F1: +case 0xF3F2: +case 0xF3F3: +case 0xF3F4: +case 0xF3F5: +case 0xF3F6: +case 0xF3F7: +case 0xF3F8: +case 0xF3F9: +case 0xF3FA: +case 0xF3FB: +case 0xF3FC: +case 0xF3FD: +case 0xF3FE: +case 0xF3FF: +case 0xF400: +case 0xF401: +case 0xF402: +case 0xF403: +case 0xF404: +case 0xF405: +case 0xF406: +case 0xF407: +case 0xF408: +case 0xF409: +case 0xF40A: +case 0xF40B: +case 0xF40C: +case 0xF40D: +case 0xF40E: +case 0xF40F: +case 0xF410: +case 0xF411: +case 0xF412: +case 0xF413: +case 0xF414: +case 0xF415: +case 0xF416: +case 0xF417: +case 0xF418: +case 0xF419: +case 0xF41A: +case 0xF41B: +case 0xF41C: +case 0xF41D: +case 0xF41E: +case 0xF41F: +case 0xF420: +case 0xF421: +case 0xF422: +case 0xF423: +case 0xF424: +case 0xF425: +case 0xF426: +case 0xF427: +case 0xF428: +case 0xF429: +case 0xF42A: +case 0xF42B: +case 0xF42C: +case 0xF42D: +case 0xF42E: +case 0xF42F: +case 0xF430: +case 0xF431: +case 0xF432: +case 0xF433: +case 0xF434: +case 0xF435: +case 0xF436: +case 0xF437: +case 0xF438: +case 0xF439: +case 0xF43A: +case 0xF43B: +case 0xF43C: +case 0xF43D: +case 0xF43E: +case 0xF43F: +case 0xF440: +case 0xF441: +case 0xF442: +case 0xF443: +case 0xF444: +case 0xF445: +case 0xF446: +case 0xF447: +case 0xF448: +case 0xF449: +case 0xF44A: +case 0xF44B: +case 0xF44C: +case 0xF44D: +case 0xF44E: +case 0xF44F: +case 0xF450: +case 0xF451: +case 0xF452: +case 0xF453: +case 0xF454: +case 0xF455: +case 0xF456: +case 0xF457: +case 0xF458: +case 0xF459: +case 0xF45A: +case 0xF45B: +case 0xF45C: +case 0xF45D: +case 0xF45E: +case 0xF45F: +case 0xF460: +case 0xF461: +case 0xF462: +case 0xF463: +case 0xF464: +case 0xF465: +case 0xF466: +case 0xF467: +case 0xF468: +case 0xF469: +case 0xF46A: +case 0xF46B: +case 0xF46C: +case 0xF46D: +case 0xF46E: +case 0xF46F: +case 0xF470: +case 0xF471: +case 0xF472: +case 0xF473: +case 0xF474: +case 0xF475: +case 0xF476: +case 0xF477: +case 0xF478: +case 0xF479: +case 0xF47A: +case 0xF47B: +case 0xF47C: +case 0xF47D: +case 0xF47E: +case 0xF47F: +case 0xF480: +case 0xF481: +case 0xF482: +case 0xF483: +case 0xF484: +case 0xF485: +case 0xF486: +case 0xF487: +case 0xF488: +case 0xF489: +case 0xF48A: +case 0xF48B: +case 0xF48C: +case 0xF48D: +case 0xF48E: +case 0xF48F: +case 0xF490: +case 0xF491: +case 0xF492: +case 0xF493: +case 0xF494: +case 0xF495: +case 0xF496: +case 0xF497: +case 0xF498: +case 0xF499: +case 0xF49A: +case 0xF49B: +case 0xF49C: +case 0xF49D: +case 0xF49E: +case 0xF49F: +case 0xF4A0: +case 0xF4A1: +case 0xF4A2: +case 0xF4A3: +case 0xF4A4: +case 0xF4A5: +case 0xF4A6: +case 0xF4A7: +case 0xF4A8: +case 0xF4A9: +case 0xF4AA: +case 0xF4AB: +case 0xF4AC: +case 0xF4AD: +case 0xF4AE: +case 0xF4AF: +case 0xF4B0: +case 0xF4B1: +case 0xF4B2: +case 0xF4B3: +case 0xF4B4: +case 0xF4B5: +case 0xF4B6: +case 0xF4B7: +case 0xF4B8: +case 0xF4B9: +case 0xF4BA: +case 0xF4BB: +case 0xF4BC: +case 0xF4BD: +case 0xF4BE: +case 0xF4BF: +case 0xF4C0: +case 0xF4C1: +case 0xF4C2: +case 0xF4C3: +case 0xF4C4: +case 0xF4C5: +case 0xF4C6: +case 0xF4C7: +case 0xF4C8: +case 0xF4C9: +case 0xF4CA: +case 0xF4CB: +case 0xF4CC: +case 0xF4CD: +case 0xF4CE: +case 0xF4CF: +case 0xF4D0: +case 0xF4D1: +case 0xF4D2: +case 0xF4D3: +case 0xF4D4: +case 0xF4D5: +case 0xF4D6: +case 0xF4D7: +case 0xF4D8: +case 0xF4D9: +case 0xF4DA: +case 0xF4DB: +case 0xF4DC: +case 0xF4DD: +case 0xF4DE: +case 0xF4DF: +case 0xF4E0: +case 0xF4E1: +case 0xF4E2: +case 0xF4E3: +case 0xF4E4: +case 0xF4E5: +case 0xF4E6: +case 0xF4E7: +case 0xF4E8: +case 0xF4E9: +case 0xF4EA: +case 0xF4EB: +case 0xF4EC: +case 0xF4ED: +case 0xF4EE: +case 0xF4EF: +case 0xF4F0: +case 0xF4F1: +case 0xF4F2: +case 0xF4F3: +case 0xF4F4: +case 0xF4F5: +case 0xF4F6: +case 0xF4F7: +case 0xF4F8: +case 0xF4F9: +case 0xF4FA: +case 0xF4FB: +case 0xF4FC: +case 0xF4FD: +case 0xF4FE: +case 0xF4FF: +case 0xF500: +case 0xF501: +case 0xF502: +case 0xF503: +case 0xF504: +case 0xF505: +case 0xF506: +case 0xF507: +case 0xF508: +case 0xF509: +case 0xF50A: +case 0xF50B: +case 0xF50C: +case 0xF50D: +case 0xF50E: +case 0xF50F: +case 0xF510: +case 0xF511: +case 0xF512: +case 0xF513: +case 0xF514: +case 0xF515: +case 0xF516: +case 0xF517: +case 0xF518: +case 0xF519: +case 0xF51A: +case 0xF51B: +case 0xF51C: +case 0xF51D: +case 0xF51E: +case 0xF51F: +case 0xF520: +case 0xF521: +case 0xF522: +case 0xF523: +case 0xF524: +case 0xF525: +case 0xF526: +case 0xF527: +case 0xF528: +case 0xF529: +case 0xF52A: +case 0xF52B: +case 0xF52C: +case 0xF52D: +case 0xF52E: +case 0xF52F: +case 0xF530: +case 0xF531: +case 0xF532: +case 0xF533: +case 0xF534: +case 0xF535: +case 0xF536: +case 0xF537: +case 0xF538: +case 0xF539: +case 0xF53A: +case 0xF53B: +case 0xF53C: +case 0xF53D: +case 0xF53E: +case 0xF53F: +case 0xF540: +case 0xF541: +case 0xF542: +case 0xF543: +case 0xF544: +case 0xF545: +case 0xF546: +case 0xF547: +case 0xF548: +case 0xF549: +case 0xF54A: +case 0xF54B: +case 0xF54C: +case 0xF54D: +case 0xF54E: +case 0xF54F: +case 0xF550: +case 0xF551: +case 0xF552: +case 0xF553: +case 0xF554: +case 0xF555: +case 0xF556: +case 0xF557: +case 0xF558: +case 0xF559: +case 0xF55A: +case 0xF55B: +case 0xF55C: +case 0xF55D: +case 0xF55E: +case 0xF55F: +case 0xF560: +case 0xF561: +case 0xF562: +case 0xF563: +case 0xF564: +case 0xF565: +case 0xF566: +case 0xF567: +case 0xF568: +case 0xF569: +case 0xF56A: +case 0xF56B: +case 0xF56C: +case 0xF56D: +case 0xF56E: +case 0xF56F: +case 0xF570: +case 0xF571: +case 0xF572: +case 0xF573: +case 0xF574: +case 0xF575: +case 0xF576: +case 0xF577: +case 0xF578: +case 0xF579: +case 0xF57A: +case 0xF57B: +case 0xF57C: +case 0xF57D: +case 0xF57E: +case 0xF57F: +case 0xF580: +case 0xF581: +case 0xF582: +case 0xF583: +case 0xF584: +case 0xF585: +case 0xF586: +case 0xF587: +case 0xF588: +case 0xF589: +case 0xF58A: +case 0xF58B: +case 0xF58C: +case 0xF58D: +case 0xF58E: +case 0xF58F: +case 0xF590: +case 0xF591: +case 0xF592: +case 0xF593: +case 0xF594: +case 0xF595: +case 0xF596: +case 0xF597: +case 0xF598: +case 0xF599: +case 0xF59A: +case 0xF59B: +case 0xF59C: +case 0xF59D: +case 0xF59E: +case 0xF59F: +case 0xF5A0: +case 0xF5A1: +case 0xF5A2: +case 0xF5A3: +case 0xF5A4: +case 0xF5A5: +case 0xF5A6: +case 0xF5A7: +case 0xF5A8: +case 0xF5A9: +case 0xF5AA: +case 0xF5AB: +case 0xF5AC: +case 0xF5AD: +case 0xF5AE: +case 0xF5AF: +case 0xF5B0: +case 0xF5B1: +case 0xF5B2: +case 0xF5B3: +case 0xF5B4: +case 0xF5B5: +case 0xF5B6: +case 0xF5B7: +case 0xF5B8: +case 0xF5B9: +case 0xF5BA: +case 0xF5BB: +case 0xF5BC: +case 0xF5BD: +case 0xF5BE: +case 0xF5BF: +case 0xF5C0: +case 0xF5C1: +case 0xF5C2: +case 0xF5C3: +case 0xF5C4: +case 0xF5C5: +case 0xF5C6: +case 0xF5C7: +case 0xF5C8: +case 0xF5C9: +case 0xF5CA: +case 0xF5CB: +case 0xF5CC: +case 0xF5CD: +case 0xF5CE: +case 0xF5CF: +case 0xF5D0: +case 0xF5D1: +case 0xF5D2: +case 0xF5D3: +case 0xF5D4: +case 0xF5D5: +case 0xF5D6: +case 0xF5D7: +case 0xF5D8: +case 0xF5D9: +case 0xF5DA: +case 0xF5DB: +case 0xF5DC: +case 0xF5DD: +case 0xF5DE: +case 0xF5DF: +case 0xF5E0: +case 0xF5E1: +case 0xF5E2: +case 0xF5E3: +case 0xF5E4: +case 0xF5E5: +case 0xF5E6: +case 0xF5E7: +case 0xF5E8: +case 0xF5E9: +case 0xF5EA: +case 0xF5EB: +case 0xF5EC: +case 0xF5ED: +case 0xF5EE: +case 0xF5EF: +case 0xF5F0: +case 0xF5F1: +case 0xF5F2: +case 0xF5F3: +case 0xF5F4: +case 0xF5F5: +case 0xF5F6: +case 0xF5F7: +case 0xF5F8: +case 0xF5F9: +case 0xF5FA: +case 0xF5FB: +case 0xF5FC: +case 0xF5FD: +case 0xF5FE: +case 0xF5FF: +case 0xF600: +case 0xF601: +case 0xF602: +case 0xF603: +case 0xF604: +case 0xF605: +case 0xF606: +case 0xF607: +case 0xF608: +case 0xF609: +case 0xF60A: +case 0xF60B: +case 0xF60C: +case 0xF60D: +case 0xF60E: +case 0xF60F: +case 0xF610: +case 0xF611: +case 0xF612: +case 0xF613: +case 0xF614: +case 0xF615: +case 0xF616: +case 0xF617: +case 0xF618: +case 0xF619: +case 0xF61A: +case 0xF61B: +case 0xF61C: +case 0xF61D: +case 0xF61E: +case 0xF61F: +case 0xF620: +case 0xF621: +case 0xF622: +case 0xF623: +case 0xF624: +case 0xF625: +case 0xF626: +case 0xF627: +case 0xF628: +case 0xF629: +case 0xF62A: +case 0xF62B: +case 0xF62C: +case 0xF62D: +case 0xF62E: +case 0xF62F: +case 0xF630: +case 0xF631: +case 0xF632: +case 0xF633: +case 0xF634: +case 0xF635: +case 0xF636: +case 0xF637: +case 0xF638: +case 0xF639: +case 0xF63A: +case 0xF63B: +case 0xF63C: +case 0xF63D: +case 0xF63E: +case 0xF63F: +case 0xF640: +case 0xF641: +case 0xF642: +case 0xF643: +case 0xF644: +case 0xF645: +case 0xF646: +case 0xF647: +case 0xF648: +case 0xF649: +case 0xF64A: +case 0xF64B: +case 0xF64C: +case 0xF64D: +case 0xF64E: +case 0xF64F: +case 0xF650: +case 0xF651: +case 0xF652: +case 0xF653: +case 0xF654: +case 0xF655: +case 0xF656: +case 0xF657: +case 0xF658: +case 0xF659: +case 0xF65A: +case 0xF65B: +case 0xF65C: +case 0xF65D: +case 0xF65E: +case 0xF65F: +case 0xF660: +case 0xF661: +case 0xF662: +case 0xF663: +case 0xF664: +case 0xF665: +case 0xF666: +case 0xF667: +case 0xF668: +case 0xF669: +case 0xF66A: +case 0xF66B: +case 0xF66C: +case 0xF66D: +case 0xF66E: +case 0xF66F: +case 0xF670: +case 0xF671: +case 0xF672: +case 0xF673: +case 0xF674: +case 0xF675: +case 0xF676: +case 0xF677: +case 0xF678: +case 0xF679: +case 0xF67A: +case 0xF67B: +case 0xF67C: +case 0xF67D: +case 0xF67E: +case 0xF67F: +case 0xF680: +case 0xF681: +case 0xF682: +case 0xF683: +case 0xF684: +case 0xF685: +case 0xF686: +case 0xF687: +case 0xF688: +case 0xF689: +case 0xF68A: +case 0xF68B: +case 0xF68C: +case 0xF68D: +case 0xF68E: +case 0xF68F: +case 0xF690: +case 0xF691: +case 0xF692: +case 0xF693: +case 0xF694: +case 0xF695: +case 0xF696: +case 0xF697: +case 0xF698: +case 0xF699: +case 0xF69A: +case 0xF69B: +case 0xF69C: +case 0xF69D: +case 0xF69E: +case 0xF69F: +case 0xF6A0: +case 0xF6A1: +case 0xF6A2: +case 0xF6A3: +case 0xF6A4: +case 0xF6A5: +case 0xF6A6: +case 0xF6A7: +case 0xF6A8: +case 0xF6A9: +case 0xF6AA: +case 0xF6AB: +case 0xF6AC: +case 0xF6AD: +case 0xF6AE: +case 0xF6AF: +case 0xF6B0: +case 0xF6B1: +case 0xF6B2: +case 0xF6B3: +case 0xF6B4: +case 0xF6B5: +case 0xF6B6: +case 0xF6B7: +case 0xF6B8: +case 0xF6B9: +case 0xF6BA: +case 0xF6BB: +case 0xF6BC: +case 0xF6BD: +case 0xF6BE: +case 0xF6BF: +case 0xF6C0: +case 0xF6C1: +case 0xF6C2: +case 0xF6C3: +case 0xF6C4: +case 0xF6C5: +case 0xF6C6: +case 0xF6C7: +case 0xF6C8: +case 0xF6C9: +case 0xF6CA: +case 0xF6CB: +case 0xF6CC: +case 0xF6CD: +case 0xF6CE: +case 0xF6CF: +case 0xF6D0: +case 0xF6D1: +case 0xF6D2: +case 0xF6D3: +case 0xF6D4: +case 0xF6D5: +case 0xF6D6: +case 0xF6D7: +case 0xF6D8: +case 0xF6D9: +case 0xF6DA: +case 0xF6DB: +case 0xF6DC: +case 0xF6DD: +case 0xF6DE: +case 0xF6DF: +case 0xF6E0: +case 0xF6E1: +case 0xF6E2: +case 0xF6E3: +case 0xF6E4: +case 0xF6E5: +case 0xF6E6: +case 0xF6E7: +case 0xF6E8: +case 0xF6E9: +case 0xF6EA: +case 0xF6EB: +case 0xF6EC: +case 0xF6ED: +case 0xF6EE: +case 0xF6EF: +case 0xF6F0: +case 0xF6F1: +case 0xF6F2: +case 0xF6F3: +case 0xF6F4: +case 0xF6F5: +case 0xF6F6: +case 0xF6F7: +case 0xF6F8: +case 0xF6F9: +case 0xF6FA: +case 0xF6FB: +case 0xF6FC: +case 0xF6FD: +case 0xF6FE: +case 0xF6FF: +case 0xF700: +case 0xF701: +case 0xF702: +case 0xF703: +case 0xF704: +case 0xF705: +case 0xF706: +case 0xF707: +case 0xF708: +case 0xF709: +case 0xF70A: +case 0xF70B: +case 0xF70C: +case 0xF70D: +case 0xF70E: +case 0xF70F: +case 0xF710: +case 0xF711: +case 0xF712: +case 0xF713: +case 0xF714: +case 0xF715: +case 0xF716: +case 0xF717: +case 0xF718: +case 0xF719: +case 0xF71A: +case 0xF71B: +case 0xF71C: +case 0xF71D: +case 0xF71E: +case 0xF71F: +case 0xF720: +case 0xF721: +case 0xF722: +case 0xF723: +case 0xF724: +case 0xF725: +case 0xF726: +case 0xF727: +case 0xF728: +case 0xF729: +case 0xF72A: +case 0xF72B: +case 0xF72C: +case 0xF72D: +case 0xF72E: +case 0xF72F: +case 0xF730: +case 0xF731: +case 0xF732: +case 0xF733: +case 0xF734: +case 0xF735: +case 0xF736: +case 0xF737: +case 0xF738: +case 0xF739: +case 0xF73A: +case 0xF73B: +case 0xF73C: +case 0xF73D: +case 0xF73E: +case 0xF73F: +case 0xF740: +case 0xF741: +case 0xF742: +case 0xF743: +case 0xF744: +case 0xF745: +case 0xF746: +case 0xF747: +case 0xF748: +case 0xF749: +case 0xF74A: +case 0xF74B: +case 0xF74C: +case 0xF74D: +case 0xF74E: +case 0xF74F: +case 0xF750: +case 0xF751: +case 0xF752: +case 0xF753: +case 0xF754: +case 0xF755: +case 0xF756: +case 0xF757: +case 0xF758: +case 0xF759: +case 0xF75A: +case 0xF75B: +case 0xF75C: +case 0xF75D: +case 0xF75E: +case 0xF75F: +case 0xF760: +case 0xF761: +case 0xF762: +case 0xF763: +case 0xF764: +case 0xF765: +case 0xF766: +case 0xF767: +case 0xF768: +case 0xF769: +case 0xF76A: +case 0xF76B: +case 0xF76C: +case 0xF76D: +case 0xF76E: +case 0xF76F: +case 0xF770: +case 0xF771: +case 0xF772: +case 0xF773: +case 0xF774: +case 0xF775: +case 0xF776: +case 0xF777: +case 0xF778: +case 0xF779: +case 0xF77A: +case 0xF77B: +case 0xF77C: +case 0xF77D: +case 0xF77E: +case 0xF77F: +case 0xF780: +case 0xF781: +case 0xF782: +case 0xF783: +case 0xF784: +case 0xF785: +case 0xF786: +case 0xF787: +case 0xF788: +case 0xF789: +case 0xF78A: +case 0xF78B: +case 0xF78C: +case 0xF78D: +case 0xF78E: +case 0xF78F: +case 0xF790: +case 0xF791: +case 0xF792: +case 0xF793: +case 0xF794: +case 0xF795: +case 0xF796: +case 0xF797: +case 0xF798: +case 0xF799: +case 0xF79A: +case 0xF79B: +case 0xF79C: +case 0xF79D: +case 0xF79E: +case 0xF79F: +case 0xF7A0: +case 0xF7A1: +case 0xF7A2: +case 0xF7A3: +case 0xF7A4: +case 0xF7A5: +case 0xF7A6: +case 0xF7A7: +case 0xF7A8: +case 0xF7A9: +case 0xF7AA: +case 0xF7AB: +case 0xF7AC: +case 0xF7AD: +case 0xF7AE: +case 0xF7AF: +case 0xF7B0: +case 0xF7B1: +case 0xF7B2: +case 0xF7B3: +case 0xF7B4: +case 0xF7B5: +case 0xF7B6: +case 0xF7B7: +case 0xF7B8: +case 0xF7B9: +case 0xF7BA: +case 0xF7BB: +case 0xF7BC: +case 0xF7BD: +case 0xF7BE: +case 0xF7BF: +case 0xF7C0: +case 0xF7C1: +case 0xF7C2: +case 0xF7C3: +case 0xF7C4: +case 0xF7C5: +case 0xF7C6: +case 0xF7C7: +case 0xF7C8: +case 0xF7C9: +case 0xF7CA: +case 0xF7CB: +case 0xF7CC: +case 0xF7CD: +case 0xF7CE: +case 0xF7CF: +case 0xF7D0: +case 0xF7D1: +case 0xF7D2: +case 0xF7D3: +case 0xF7D4: +case 0xF7D5: +case 0xF7D6: +case 0xF7D7: +case 0xF7D8: +case 0xF7D9: +case 0xF7DA: +case 0xF7DB: +case 0xF7DC: +case 0xF7DD: +case 0xF7DE: +case 0xF7DF: +case 0xF7E0: +case 0xF7E1: +case 0xF7E2: +case 0xF7E3: +case 0xF7E4: +case 0xF7E5: +case 0xF7E6: +case 0xF7E7: +case 0xF7E8: +case 0xF7E9: +case 0xF7EA: +case 0xF7EB: +case 0xF7EC: +case 0xF7ED: +case 0xF7EE: +case 0xF7EF: +case 0xF7F0: +case 0xF7F1: +case 0xF7F2: +case 0xF7F3: +case 0xF7F4: +case 0xF7F5: +case 0xF7F6: +case 0xF7F7: +case 0xF7F8: +case 0xF7F9: +case 0xF7FA: +case 0xF7FB: +case 0xF7FC: +case 0xF7FD: +case 0xF7FE: +case 0xF7FF: +case 0xF800: +case 0xF801: +case 0xF802: +case 0xF803: +case 0xF804: +case 0xF805: +case 0xF806: +case 0xF807: +case 0xF808: +case 0xF809: +case 0xF80A: +case 0xF80B: +case 0xF80C: +case 0xF80D: +case 0xF80E: +case 0xF80F: +case 0xF810: +case 0xF811: +case 0xF812: +case 0xF813: +case 0xF814: +case 0xF815: +case 0xF816: +case 0xF817: +case 0xF818: +case 0xF819: +case 0xF81A: +case 0xF81B: +case 0xF81C: +case 0xF81D: +case 0xF81E: +case 0xF81F: +case 0xF820: +case 0xF821: +case 0xF822: +case 0xF823: +case 0xF824: +case 0xF825: +case 0xF826: +case 0xF827: +case 0xF828: +case 0xF829: +case 0xF82A: +case 0xF82B: +case 0xF82C: +case 0xF82D: +case 0xF82E: +case 0xF82F: +case 0xF830: +case 0xF831: +case 0xF832: +case 0xF833: +case 0xF834: +case 0xF835: +case 0xF836: +case 0xF837: +case 0xF838: +case 0xF839: +case 0xF83A: +case 0xF83B: +case 0xF83C: +case 0xF83D: +case 0xF83E: +case 0xF83F: +case 0xF840: +case 0xF841: +case 0xF842: +case 0xF843: +case 0xF844: +case 0xF845: +case 0xF846: +case 0xF847: +case 0xF848: +case 0xF849: +case 0xF84A: +case 0xF84B: +case 0xF84C: +case 0xF84D: +case 0xF84E: +case 0xF84F: +case 0xF850: +case 0xF851: +case 0xF852: +case 0xF853: +case 0xF854: +case 0xF855: +case 0xF856: +case 0xF857: +case 0xF858: +case 0xF859: +case 0xF85A: +case 0xF85B: +case 0xF85C: +case 0xF85D: +case 0xF85E: +case 0xF85F: +case 0xF860: +case 0xF861: +case 0xF862: +case 0xF863: +case 0xF864: +case 0xF865: +case 0xF866: +case 0xF867: +case 0xF868: +case 0xF869: +case 0xF86A: +case 0xF86B: +case 0xF86C: +case 0xF86D: +case 0xF86E: +case 0xF86F: +case 0xF870: +case 0xF871: +case 0xF872: +case 0xF873: +case 0xF874: +case 0xF875: +case 0xF876: +case 0xF877: +case 0xF878: +case 0xF879: +case 0xF87A: +case 0xF87B: +case 0xF87C: +case 0xF87D: +case 0xF87E: +case 0xF87F: +case 0xF880: +case 0xF881: +case 0xF882: +case 0xF883: +case 0xF884: +case 0xF885: +case 0xF886: +case 0xF887: +case 0xF888: +case 0xF889: +case 0xF88A: +case 0xF88B: +case 0xF88C: +case 0xF88D: +case 0xF88E: +case 0xF88F: +case 0xF890: +case 0xF891: +case 0xF892: +case 0xF893: +case 0xF894: +case 0xF895: +case 0xF896: +case 0xF897: +case 0xF898: +case 0xF899: +case 0xF89A: +case 0xF89B: +case 0xF89C: +case 0xF89D: +case 0xF89E: +case 0xF89F: +case 0xF8A0: +case 0xF8A1: +case 0xF8A2: +case 0xF8A3: +case 0xF8A4: +case 0xF8A5: +case 0xF8A6: +case 0xF8A7: +case 0xF8A8: +case 0xF8A9: +case 0xF8AA: +case 0xF8AB: +case 0xF8AC: +case 0xF8AD: +case 0xF8AE: +case 0xF8AF: +case 0xF8B0: +case 0xF8B1: +case 0xF8B2: +case 0xF8B3: +case 0xF8B4: +case 0xF8B5: +case 0xF8B6: +case 0xF8B7: +case 0xF8B8: +case 0xF8B9: +case 0xF8BA: +case 0xF8BB: +case 0xF8BC: +case 0xF8BD: +case 0xF8BE: +case 0xF8BF: +case 0xF8C0: +case 0xF8C1: +case 0xF8C2: +case 0xF8C3: +case 0xF8C4: +case 0xF8C5: +case 0xF8C6: +case 0xF8C7: +case 0xF8C8: +case 0xF8C9: +case 0xF8CA: +case 0xF8CB: +case 0xF8CC: +case 0xF8CD: +case 0xF8CE: +case 0xF8CF: +case 0xF8D0: +case 0xF8D1: +case 0xF8D2: +case 0xF8D3: +case 0xF8D4: +case 0xF8D5: +case 0xF8D6: +case 0xF8D7: +case 0xF8D8: +case 0xF8D9: +case 0xF8DA: +case 0xF8DB: +case 0xF8DC: +case 0xF8DD: +case 0xF8DE: +case 0xF8DF: +case 0xF8E0: +case 0xF8E1: +case 0xF8E2: +case 0xF8E3: +case 0xF8E4: +case 0xF8E5: +case 0xF8E6: +case 0xF8E7: +case 0xF8E8: +case 0xF8E9: +case 0xF8EA: +case 0xF8EB: +case 0xF8EC: +case 0xF8ED: +case 0xF8EE: +case 0xF8EF: +case 0xF8F0: +case 0xF8F1: +case 0xF8F2: +case 0xF8F3: +case 0xF8F4: +case 0xF8F5: +case 0xF8F6: +case 0xF8F7: +case 0xF8F8: +case 0xF8F9: +case 0xF8FA: +case 0xF8FB: +case 0xF8FC: +case 0xF8FD: +case 0xF8FE: +case 0xF8FF: +case 0xF900: +case 0xF901: +case 0xF902: +case 0xF903: +case 0xF904: +case 0xF905: +case 0xF906: +case 0xF907: +case 0xF908: +case 0xF909: +case 0xF90A: +case 0xF90B: +case 0xF90C: +case 0xF90D: +case 0xF90E: +case 0xF90F: +case 0xF910: +case 0xF911: +case 0xF912: +case 0xF913: +case 0xF914: +case 0xF915: +case 0xF916: +case 0xF917: +case 0xF918: +case 0xF919: +case 0xF91A: +case 0xF91B: +case 0xF91C: +case 0xF91D: +case 0xF91E: +case 0xF91F: +case 0xF920: +case 0xF921: +case 0xF922: +case 0xF923: +case 0xF924: +case 0xF925: +case 0xF926: +case 0xF927: +case 0xF928: +case 0xF929: +case 0xF92A: +case 0xF92B: +case 0xF92C: +case 0xF92D: +case 0xF92E: +case 0xF92F: +case 0xF930: +case 0xF931: +case 0xF932: +case 0xF933: +case 0xF934: +case 0xF935: +case 0xF936: +case 0xF937: +case 0xF938: +case 0xF939: +case 0xF93A: +case 0xF93B: +case 0xF93C: +case 0xF93D: +case 0xF93E: +case 0xF93F: +case 0xF940: +case 0xF941: +case 0xF942: +case 0xF943: +case 0xF944: +case 0xF945: +case 0xF946: +case 0xF947: +case 0xF948: +case 0xF949: +case 0xF94A: +case 0xF94B: +case 0xF94C: +case 0xF94D: +case 0xF94E: +case 0xF94F: +case 0xF950: +case 0xF951: +case 0xF952: +case 0xF953: +case 0xF954: +case 0xF955: +case 0xF956: +case 0xF957: +case 0xF958: +case 0xF959: +case 0xF95A: +case 0xF95B: +case 0xF95C: +case 0xF95D: +case 0xF95E: +case 0xF95F: +case 0xF960: +case 0xF961: +case 0xF962: +case 0xF963: +case 0xF964: +case 0xF965: +case 0xF966: +case 0xF967: +case 0xF968: +case 0xF969: +case 0xF96A: +case 0xF96B: +case 0xF96C: +case 0xF96D: +case 0xF96E: +case 0xF96F: +case 0xF970: +case 0xF971: +case 0xF972: +case 0xF973: +case 0xF974: +case 0xF975: +case 0xF976: +case 0xF977: +case 0xF978: +case 0xF979: +case 0xF97A: +case 0xF97B: +case 0xF97C: +case 0xF97D: +case 0xF97E: +case 0xF97F: +case 0xF980: +case 0xF981: +case 0xF982: +case 0xF983: +case 0xF984: +case 0xF985: +case 0xF986: +case 0xF987: +case 0xF988: +case 0xF989: +case 0xF98A: +case 0xF98B: +case 0xF98C: +case 0xF98D: +case 0xF98E: +case 0xF98F: +case 0xF990: +case 0xF991: +case 0xF992: +case 0xF993: +case 0xF994: +case 0xF995: +case 0xF996: +case 0xF997: +case 0xF998: +case 0xF999: +case 0xF99A: +case 0xF99B: +case 0xF99C: +case 0xF99D: +case 0xF99E: +case 0xF99F: +case 0xF9A0: +case 0xF9A1: +case 0xF9A2: +case 0xF9A3: +case 0xF9A4: +case 0xF9A5: +case 0xF9A6: +case 0xF9A7: +case 0xF9A8: +case 0xF9A9: +case 0xF9AA: +case 0xF9AB: +case 0xF9AC: +case 0xF9AD: +case 0xF9AE: +case 0xF9AF: +case 0xF9B0: +case 0xF9B1: +case 0xF9B2: +case 0xF9B3: +case 0xF9B4: +case 0xF9B5: +case 0xF9B6: +case 0xF9B7: +case 0xF9B8: +case 0xF9B9: +case 0xF9BA: +case 0xF9BB: +case 0xF9BC: +case 0xF9BD: +case 0xF9BE: +case 0xF9BF: +case 0xF9C0: +case 0xF9C1: +case 0xF9C2: +case 0xF9C3: +case 0xF9C4: +case 0xF9C5: +case 0xF9C6: +case 0xF9C7: +case 0xF9C8: +case 0xF9C9: +case 0xF9CA: +case 0xF9CB: +case 0xF9CC: +case 0xF9CD: +case 0xF9CE: +case 0xF9CF: +case 0xF9D0: +case 0xF9D1: +case 0xF9D2: +case 0xF9D3: +case 0xF9D4: +case 0xF9D5: +case 0xF9D6: +case 0xF9D7: +case 0xF9D8: +case 0xF9D9: +case 0xF9DA: +case 0xF9DB: +case 0xF9DC: +case 0xF9DD: +case 0xF9DE: +case 0xF9DF: +case 0xF9E0: +case 0xF9E1: +case 0xF9E2: +case 0xF9E3: +case 0xF9E4: +case 0xF9E5: +case 0xF9E6: +case 0xF9E7: +case 0xF9E8: +case 0xF9E9: +case 0xF9EA: +case 0xF9EB: +case 0xF9EC: +case 0xF9ED: +case 0xF9EE: +case 0xF9EF: +case 0xF9F0: +case 0xF9F1: +case 0xF9F2: +case 0xF9F3: +case 0xF9F4: +case 0xF9F5: +case 0xF9F6: +case 0xF9F7: +case 0xF9F8: +case 0xF9F9: +case 0xF9FA: +case 0xF9FB: +case 0xF9FC: +case 0xF9FD: +case 0xF9FE: +case 0xF9FF: +case 0xFA00: +case 0xFA01: +case 0xFA02: +case 0xFA03: +case 0xFA04: +case 0xFA05: +case 0xFA06: +case 0xFA07: +case 0xFA08: +case 0xFA09: +case 0xFA0A: +case 0xFA0B: +case 0xFA0C: +case 0xFA0D: +case 0xFA0E: +case 0xFA0F: +case 0xFA10: +case 0xFA11: +case 0xFA12: +case 0xFA13: +case 0xFA14: +case 0xFA15: +case 0xFA16: +case 0xFA17: +case 0xFA18: +case 0xFA19: +case 0xFA1A: +case 0xFA1B: +case 0xFA1C: +case 0xFA1D: +case 0xFA1E: +case 0xFA1F: +case 0xFA20: +case 0xFA21: +case 0xFA22: +case 0xFA23: +case 0xFA24: +case 0xFA25: +case 0xFA26: +case 0xFA27: +case 0xFA28: +case 0xFA29: +case 0xFA2A: +case 0xFA2B: +case 0xFA2C: +case 0xFA2D: +case 0xFA2E: +case 0xFA2F: +case 0xFA30: +case 0xFA31: +case 0xFA32: +case 0xFA33: +case 0xFA34: +case 0xFA35: +case 0xFA36: +case 0xFA37: +case 0xFA38: +case 0xFA39: +case 0xFA3A: +case 0xFA3B: +case 0xFA3C: +case 0xFA3D: +case 0xFA3E: +case 0xFA3F: +case 0xFA40: +case 0xFA41: +case 0xFA42: +case 0xFA43: +case 0xFA44: +case 0xFA45: +case 0xFA46: +case 0xFA47: +case 0xFA48: +case 0xFA49: +case 0xFA4A: +case 0xFA4B: +case 0xFA4C: +case 0xFA4D: +case 0xFA4E: +case 0xFA4F: +case 0xFA50: +case 0xFA51: +case 0xFA52: +case 0xFA53: +case 0xFA54: +case 0xFA55: +case 0xFA56: +case 0xFA57: +case 0xFA58: +case 0xFA59: +case 0xFA5A: +case 0xFA5B: +case 0xFA5C: +case 0xFA5D: +case 0xFA5E: +case 0xFA5F: +case 0xFA60: +case 0xFA61: +case 0xFA62: +case 0xFA63: +case 0xFA64: +case 0xFA65: +case 0xFA66: +case 0xFA67: +case 0xFA68: +case 0xFA69: +case 0xFA6A: +case 0xFA6B: +case 0xFA6C: +case 0xFA6D: +case 0xFA6E: +case 0xFA6F: +case 0xFA70: +case 0xFA71: +case 0xFA72: +case 0xFA73: +case 0xFA74: +case 0xFA75: +case 0xFA76: +case 0xFA77: +case 0xFA78: +case 0xFA79: +case 0xFA7A: +case 0xFA7B: +case 0xFA7C: +case 0xFA7D: +case 0xFA7E: +case 0xFA7F: +case 0xFA80: +case 0xFA81: +case 0xFA82: +case 0xFA83: +case 0xFA84: +case 0xFA85: +case 0xFA86: +case 0xFA87: +case 0xFA88: +case 0xFA89: +case 0xFA8A: +case 0xFA8B: +case 0xFA8C: +case 0xFA8D: +case 0xFA8E: +case 0xFA8F: +case 0xFA90: +case 0xFA91: +case 0xFA92: +case 0xFA93: +case 0xFA94: +case 0xFA95: +case 0xFA96: +case 0xFA97: +case 0xFA98: +case 0xFA99: +case 0xFA9A: +case 0xFA9B: +case 0xFA9C: +case 0xFA9D: +case 0xFA9E: +case 0xFA9F: +case 0xFAA0: +case 0xFAA1: +case 0xFAA2: +case 0xFAA3: +case 0xFAA4: +case 0xFAA5: +case 0xFAA6: +case 0xFAA7: +case 0xFAA8: +case 0xFAA9: +case 0xFAAA: +case 0xFAAB: +case 0xFAAC: +case 0xFAAD: +case 0xFAAE: +case 0xFAAF: +case 0xFAB0: +case 0xFAB1: +case 0xFAB2: +case 0xFAB3: +case 0xFAB4: +case 0xFAB5: +case 0xFAB6: +case 0xFAB7: +case 0xFAB8: +case 0xFAB9: +case 0xFABA: +case 0xFABB: +case 0xFABC: +case 0xFABD: +case 0xFABE: +case 0xFABF: +case 0xFAC0: +case 0xFAC1: +case 0xFAC2: +case 0xFAC3: +case 0xFAC4: +case 0xFAC5: +case 0xFAC6: +case 0xFAC7: +case 0xFAC8: +case 0xFAC9: +case 0xFACA: +case 0xFACB: +case 0xFACC: +case 0xFACD: +case 0xFACE: +case 0xFACF: +case 0xFAD0: +case 0xFAD1: +case 0xFAD2: +case 0xFAD3: +case 0xFAD4: +case 0xFAD5: +case 0xFAD6: +case 0xFAD7: +case 0xFAD8: +case 0xFAD9: +case 0xFADA: +case 0xFADB: +case 0xFADC: +case 0xFADD: +case 0xFADE: +case 0xFADF: +case 0xFAE0: +case 0xFAE1: +case 0xFAE2: +case 0xFAE3: +case 0xFAE4: +case 0xFAE5: +case 0xFAE6: +case 0xFAE7: +case 0xFAE8: +case 0xFAE9: +case 0xFAEA: +case 0xFAEB: +case 0xFAEC: +case 0xFAED: +case 0xFAEE: +case 0xFAEF: +case 0xFAF0: +case 0xFAF1: +case 0xFAF2: +case 0xFAF3: +case 0xFAF4: +case 0xFAF5: +case 0xFAF6: +case 0xFAF7: +case 0xFAF8: +case 0xFAF9: +case 0xFAFA: +case 0xFAFB: +case 0xFAFC: +case 0xFAFD: +case 0xFAFE: +case 0xFAFF: +case 0xFB00: +case 0xFB01: +case 0xFB02: +case 0xFB03: +case 0xFB04: +case 0xFB05: +case 0xFB06: +case 0xFB07: +case 0xFB08: +case 0xFB09: +case 0xFB0A: +case 0xFB0B: +case 0xFB0C: +case 0xFB0D: +case 0xFB0E: +case 0xFB0F: +case 0xFB10: +case 0xFB11: +case 0xFB12: +case 0xFB13: +case 0xFB14: +case 0xFB15: +case 0xFB16: +case 0xFB17: +case 0xFB18: +case 0xFB19: +case 0xFB1A: +case 0xFB1B: +case 0xFB1C: +case 0xFB1D: +case 0xFB1E: +case 0xFB1F: +case 0xFB20: +case 0xFB21: +case 0xFB22: +case 0xFB23: +case 0xFB24: +case 0xFB25: +case 0xFB26: +case 0xFB27: +case 0xFB28: +case 0xFB29: +case 0xFB2A: +case 0xFB2B: +case 0xFB2C: +case 0xFB2D: +case 0xFB2E: +case 0xFB2F: +case 0xFB30: +case 0xFB31: +case 0xFB32: +case 0xFB33: +case 0xFB34: +case 0xFB35: +case 0xFB36: +case 0xFB37: +case 0xFB38: +case 0xFB39: +case 0xFB3A: +case 0xFB3B: +case 0xFB3C: +case 0xFB3D: +case 0xFB3E: +case 0xFB3F: +case 0xFB40: +case 0xFB41: +case 0xFB42: +case 0xFB43: +case 0xFB44: +case 0xFB45: +case 0xFB46: +case 0xFB47: +case 0xFB48: +case 0xFB49: +case 0xFB4A: +case 0xFB4B: +case 0xFB4C: +case 0xFB4D: +case 0xFB4E: +case 0xFB4F: +case 0xFB50: +case 0xFB51: +case 0xFB52: +case 0xFB53: +case 0xFB54: +case 0xFB55: +case 0xFB56: +case 0xFB57: +case 0xFB58: +case 0xFB59: +case 0xFB5A: +case 0xFB5B: +case 0xFB5C: +case 0xFB5D: +case 0xFB5E: +case 0xFB5F: +case 0xFB60: +case 0xFB61: +case 0xFB62: +case 0xFB63: +case 0xFB64: +case 0xFB65: +case 0xFB66: +case 0xFB67: +case 0xFB68: +case 0xFB69: +case 0xFB6A: +case 0xFB6B: +case 0xFB6C: +case 0xFB6D: +case 0xFB6E: +case 0xFB6F: +case 0xFB70: +case 0xFB71: +case 0xFB72: +case 0xFB73: +case 0xFB74: +case 0xFB75: +case 0xFB76: +case 0xFB77: +case 0xFB78: +case 0xFB79: +case 0xFB7A: +case 0xFB7B: +case 0xFB7C: +case 0xFB7D: +case 0xFB7E: +case 0xFB7F: +case 0xFB80: +case 0xFB81: +case 0xFB82: +case 0xFB83: +case 0xFB84: +case 0xFB85: +case 0xFB86: +case 0xFB87: +case 0xFB88: +case 0xFB89: +case 0xFB8A: +case 0xFB8B: +case 0xFB8C: +case 0xFB8D: +case 0xFB8E: +case 0xFB8F: +case 0xFB90: +case 0xFB91: +case 0xFB92: +case 0xFB93: +case 0xFB94: +case 0xFB95: +case 0xFB96: +case 0xFB97: +case 0xFB98: +case 0xFB99: +case 0xFB9A: +case 0xFB9B: +case 0xFB9C: +case 0xFB9D: +case 0xFB9E: +case 0xFB9F: +case 0xFBA0: +case 0xFBA1: +case 0xFBA2: +case 0xFBA3: +case 0xFBA4: +case 0xFBA5: +case 0xFBA6: +case 0xFBA7: +case 0xFBA8: +case 0xFBA9: +case 0xFBAA: +case 0xFBAB: +case 0xFBAC: +case 0xFBAD: +case 0xFBAE: +case 0xFBAF: +case 0xFBB0: +case 0xFBB1: +case 0xFBB2: +case 0xFBB3: +case 0xFBB4: +case 0xFBB5: +case 0xFBB6: +case 0xFBB7: +case 0xFBB8: +case 0xFBB9: +case 0xFBBA: +case 0xFBBB: +case 0xFBBC: +case 0xFBBD: +case 0xFBBE: +case 0xFBBF: +case 0xFBC0: +case 0xFBC1: +case 0xFBC2: +case 0xFBC3: +case 0xFBC4: +case 0xFBC5: +case 0xFBC6: +case 0xFBC7: +case 0xFBC8: +case 0xFBC9: +case 0xFBCA: +case 0xFBCB: +case 0xFBCC: +case 0xFBCD: +case 0xFBCE: +case 0xFBCF: +case 0xFBD0: +case 0xFBD1: +case 0xFBD2: +case 0xFBD3: +case 0xFBD4: +case 0xFBD5: +case 0xFBD6: +case 0xFBD7: +case 0xFBD8: +case 0xFBD9: +case 0xFBDA: +case 0xFBDB: +case 0xFBDC: +case 0xFBDD: +case 0xFBDE: +case 0xFBDF: +case 0xFBE0: +case 0xFBE1: +case 0xFBE2: +case 0xFBE3: +case 0xFBE4: +case 0xFBE5: +case 0xFBE6: +case 0xFBE7: +case 0xFBE8: +case 0xFBE9: +case 0xFBEA: +case 0xFBEB: +case 0xFBEC: +case 0xFBED: +case 0xFBEE: +case 0xFBEF: +case 0xFBF0: +case 0xFBF1: +case 0xFBF2: +case 0xFBF3: +case 0xFBF4: +case 0xFBF5: +case 0xFBF6: +case 0xFBF7: +case 0xFBF8: +case 0xFBF9: +case 0xFBFA: +case 0xFBFB: +case 0xFBFC: +case 0xFBFD: +case 0xFBFE: +case 0xFBFF: +case 0xFC00: +case 0xFC01: +case 0xFC02: +case 0xFC03: +case 0xFC04: +case 0xFC05: +case 0xFC06: +case 0xFC07: +case 0xFC08: +case 0xFC09: +case 0xFC0A: +case 0xFC0B: +case 0xFC0C: +case 0xFC0D: +case 0xFC0E: +case 0xFC0F: +case 0xFC10: +case 0xFC11: +case 0xFC12: +case 0xFC13: +case 0xFC14: +case 0xFC15: +case 0xFC16: +case 0xFC17: +case 0xFC18: +case 0xFC19: +case 0xFC1A: +case 0xFC1B: +case 0xFC1C: +case 0xFC1D: +case 0xFC1E: +case 0xFC1F: +case 0xFC20: +case 0xFC21: +case 0xFC22: +case 0xFC23: +case 0xFC24: +case 0xFC25: +case 0xFC26: +case 0xFC27: +case 0xFC28: +case 0xFC29: +case 0xFC2A: +case 0xFC2B: +case 0xFC2C: +case 0xFC2D: +case 0xFC2E: +case 0xFC2F: +case 0xFC30: +case 0xFC31: +case 0xFC32: +case 0xFC33: +case 0xFC34: +case 0xFC35: +case 0xFC36: +case 0xFC37: +case 0xFC38: +case 0xFC39: +case 0xFC3A: +case 0xFC3B: +case 0xFC3C: +case 0xFC3D: +case 0xFC3E: +case 0xFC3F: +case 0xFC40: +case 0xFC41: +case 0xFC42: +case 0xFC43: +case 0xFC44: +case 0xFC45: +case 0xFC46: +case 0xFC47: +case 0xFC48: +case 0xFC49: +case 0xFC4A: +case 0xFC4B: +case 0xFC4C: +case 0xFC4D: +case 0xFC4E: +case 0xFC4F: +case 0xFC50: +case 0xFC51: +case 0xFC52: +case 0xFC53: +case 0xFC54: +case 0xFC55: +case 0xFC56: +case 0xFC57: +case 0xFC58: +case 0xFC59: +case 0xFC5A: +case 0xFC5B: +case 0xFC5C: +case 0xFC5D: +case 0xFC5E: +case 0xFC5F: +case 0xFC60: +case 0xFC61: +case 0xFC62: +case 0xFC63: +case 0xFC64: +case 0xFC65: +case 0xFC66: +case 0xFC67: +case 0xFC68: +case 0xFC69: +case 0xFC6A: +case 0xFC6B: +case 0xFC6C: +case 0xFC6D: +case 0xFC6E: +case 0xFC6F: +case 0xFC70: +case 0xFC71: +case 0xFC72: +case 0xFC73: +case 0xFC74: +case 0xFC75: +case 0xFC76: +case 0xFC77: +case 0xFC78: +case 0xFC79: +case 0xFC7A: +case 0xFC7B: +case 0xFC7C: +case 0xFC7D: +case 0xFC7E: +case 0xFC7F: +case 0xFC80: +case 0xFC81: +case 0xFC82: +case 0xFC83: +case 0xFC84: +case 0xFC85: +case 0xFC86: +case 0xFC87: +case 0xFC88: +case 0xFC89: +case 0xFC8A: +case 0xFC8B: +case 0xFC8C: +case 0xFC8D: +case 0xFC8E: +case 0xFC8F: +case 0xFC90: +case 0xFC91: +case 0xFC92: +case 0xFC93: +case 0xFC94: +case 0xFC95: +case 0xFC96: +case 0xFC97: +case 0xFC98: +case 0xFC99: +case 0xFC9A: +case 0xFC9B: +case 0xFC9C: +case 0xFC9D: +case 0xFC9E: +case 0xFC9F: +case 0xFCA0: +case 0xFCA1: +case 0xFCA2: +case 0xFCA3: +case 0xFCA4: +case 0xFCA5: +case 0xFCA6: +case 0xFCA7: +case 0xFCA8: +case 0xFCA9: +case 0xFCAA: +case 0xFCAB: +case 0xFCAC: +case 0xFCAD: +case 0xFCAE: +case 0xFCAF: +case 0xFCB0: +case 0xFCB1: +case 0xFCB2: +case 0xFCB3: +case 0xFCB4: +case 0xFCB5: +case 0xFCB6: +case 0xFCB7: +case 0xFCB8: +case 0xFCB9: +case 0xFCBA: +case 0xFCBB: +case 0xFCBC: +case 0xFCBD: +case 0xFCBE: +case 0xFCBF: +case 0xFCC0: +case 0xFCC1: +case 0xFCC2: +case 0xFCC3: +case 0xFCC4: +case 0xFCC5: +case 0xFCC6: +case 0xFCC7: +case 0xFCC8: +case 0xFCC9: +case 0xFCCA: +case 0xFCCB: +case 0xFCCC: +case 0xFCCD: +case 0xFCCE: +case 0xFCCF: +case 0xFCD0: +case 0xFCD1: +case 0xFCD2: +case 0xFCD3: +case 0xFCD4: +case 0xFCD5: +case 0xFCD6: +case 0xFCD7: +case 0xFCD8: +case 0xFCD9: +case 0xFCDA: +case 0xFCDB: +case 0xFCDC: +case 0xFCDD: +case 0xFCDE: +case 0xFCDF: +case 0xFCE0: +case 0xFCE1: +case 0xFCE2: +case 0xFCE3: +case 0xFCE4: +case 0xFCE5: +case 0xFCE6: +case 0xFCE7: +case 0xFCE8: +case 0xFCE9: +case 0xFCEA: +case 0xFCEB: +case 0xFCEC: +case 0xFCED: +case 0xFCEE: +case 0xFCEF: +case 0xFCF0: +case 0xFCF1: +case 0xFCF2: +case 0xFCF3: +case 0xFCF4: +case 0xFCF5: +case 0xFCF6: +case 0xFCF7: +case 0xFCF8: +case 0xFCF9: +case 0xFCFA: +case 0xFCFB: +case 0xFCFC: +case 0xFCFD: +case 0xFCFE: +case 0xFCFF: +case 0xFD00: +case 0xFD01: +case 0xFD02: +case 0xFD03: +case 0xFD04: +case 0xFD05: +case 0xFD06: +case 0xFD07: +case 0xFD08: +case 0xFD09: +case 0xFD0A: +case 0xFD0B: +case 0xFD0C: +case 0xFD0D: +case 0xFD0E: +case 0xFD0F: +case 0xFD10: +case 0xFD11: +case 0xFD12: +case 0xFD13: +case 0xFD14: +case 0xFD15: +case 0xFD16: +case 0xFD17: +case 0xFD18: +case 0xFD19: +case 0xFD1A: +case 0xFD1B: +case 0xFD1C: +case 0xFD1D: +case 0xFD1E: +case 0xFD1F: +case 0xFD20: +case 0xFD21: +case 0xFD22: +case 0xFD23: +case 0xFD24: +case 0xFD25: +case 0xFD26: +case 0xFD27: +case 0xFD28: +case 0xFD29: +case 0xFD2A: +case 0xFD2B: +case 0xFD2C: +case 0xFD2D: +case 0xFD2E: +case 0xFD2F: +case 0xFD30: +case 0xFD31: +case 0xFD32: +case 0xFD33: +case 0xFD34: +case 0xFD35: +case 0xFD36: +case 0xFD37: +case 0xFD38: +case 0xFD39: +case 0xFD3A: +case 0xFD3B: +case 0xFD3C: +case 0xFD3D: +case 0xFD3E: +case 0xFD3F: +case 0xFD40: +case 0xFD41: +case 0xFD42: +case 0xFD43: +case 0xFD44: +case 0xFD45: +case 0xFD46: +case 0xFD47: +case 0xFD48: +case 0xFD49: +case 0xFD4A: +case 0xFD4B: +case 0xFD4C: +case 0xFD4D: +case 0xFD4E: +case 0xFD4F: +case 0xFD50: +case 0xFD51: +case 0xFD52: +case 0xFD53: +case 0xFD54: +case 0xFD55: +case 0xFD56: +case 0xFD57: +case 0xFD58: +case 0xFD59: +case 0xFD5A: +case 0xFD5B: +case 0xFD5C: +case 0xFD5D: +case 0xFD5E: +case 0xFD5F: +case 0xFD60: +case 0xFD61: +case 0xFD62: +case 0xFD63: +case 0xFD64: +case 0xFD65: +case 0xFD66: +case 0xFD67: +case 0xFD68: +case 0xFD69: +case 0xFD6A: +case 0xFD6B: +case 0xFD6C: +case 0xFD6D: +case 0xFD6E: +case 0xFD6F: +case 0xFD70: +case 0xFD71: +case 0xFD72: +case 0xFD73: +case 0xFD74: +case 0xFD75: +case 0xFD76: +case 0xFD77: +case 0xFD78: +case 0xFD79: +case 0xFD7A: +case 0xFD7B: +case 0xFD7C: +case 0xFD7D: +case 0xFD7E: +case 0xFD7F: +case 0xFD80: +case 0xFD81: +case 0xFD82: +case 0xFD83: +case 0xFD84: +case 0xFD85: +case 0xFD86: +case 0xFD87: +case 0xFD88: +case 0xFD89: +case 0xFD8A: +case 0xFD8B: +case 0xFD8C: +case 0xFD8D: +case 0xFD8E: +case 0xFD8F: +case 0xFD90: +case 0xFD91: +case 0xFD92: +case 0xFD93: +case 0xFD94: +case 0xFD95: +case 0xFD96: +case 0xFD97: +case 0xFD98: +case 0xFD99: +case 0xFD9A: +case 0xFD9B: +case 0xFD9C: +case 0xFD9D: +case 0xFD9E: +case 0xFD9F: +case 0xFDA0: +case 0xFDA1: +case 0xFDA2: +case 0xFDA3: +case 0xFDA4: +case 0xFDA5: +case 0xFDA6: +case 0xFDA7: +case 0xFDA8: +case 0xFDA9: +case 0xFDAA: +case 0xFDAB: +case 0xFDAC: +case 0xFDAD: +case 0xFDAE: +case 0xFDAF: +case 0xFDB0: +case 0xFDB1: +case 0xFDB2: +case 0xFDB3: +case 0xFDB4: +case 0xFDB5: +case 0xFDB6: +case 0xFDB7: +case 0xFDB8: +case 0xFDB9: +case 0xFDBA: +case 0xFDBB: +case 0xFDBC: +case 0xFDBD: +case 0xFDBE: +case 0xFDBF: +case 0xFDC0: +case 0xFDC1: +case 0xFDC2: +case 0xFDC3: +case 0xFDC4: +case 0xFDC5: +case 0xFDC6: +case 0xFDC7: +case 0xFDC8: +case 0xFDC9: +case 0xFDCA: +case 0xFDCB: +case 0xFDCC: +case 0xFDCD: +case 0xFDCE: +case 0xFDCF: +case 0xFDD0: +case 0xFDD1: +case 0xFDD2: +case 0xFDD3: +case 0xFDD4: +case 0xFDD5: +case 0xFDD6: +case 0xFDD7: +case 0xFDD8: +case 0xFDD9: +case 0xFDDA: +case 0xFDDB: +case 0xFDDC: +case 0xFDDD: +case 0xFDDE: +case 0xFDDF: +case 0xFDE0: +case 0xFDE1: +case 0xFDE2: +case 0xFDE3: +case 0xFDE4: +case 0xFDE5: +case 0xFDE6: +case 0xFDE7: +case 0xFDE8: +case 0xFDE9: +case 0xFDEA: +case 0xFDEB: +case 0xFDEC: +case 0xFDED: +case 0xFDEE: +case 0xFDEF: +case 0xFDF0: +case 0xFDF1: +case 0xFDF2: +case 0xFDF3: +case 0xFDF4: +case 0xFDF5: +case 0xFDF6: +case 0xFDF7: +case 0xFDF8: +case 0xFDF9: +case 0xFDFA: +case 0xFDFB: +case 0xFDFC: +case 0xFDFD: +case 0xFDFE: +case 0xFDFF: +case 0xFE00: +case 0xFE01: +case 0xFE02: +case 0xFE03: +case 0xFE04: +case 0xFE05: +case 0xFE06: +case 0xFE07: +case 0xFE08: +case 0xFE09: +case 0xFE0A: +case 0xFE0B: +case 0xFE0C: +case 0xFE0D: +case 0xFE0E: +case 0xFE0F: +case 0xFE10: +case 0xFE11: +case 0xFE12: +case 0xFE13: +case 0xFE14: +case 0xFE15: +case 0xFE16: +case 0xFE17: +case 0xFE18: +case 0xFE19: +case 0xFE1A: +case 0xFE1B: +case 0xFE1C: +case 0xFE1D: +case 0xFE1E: +case 0xFE1F: +case 0xFE20: +case 0xFE21: +case 0xFE22: +case 0xFE23: +case 0xFE24: +case 0xFE25: +case 0xFE26: +case 0xFE27: +case 0xFE28: +case 0xFE29: +case 0xFE2A: +case 0xFE2B: +case 0xFE2C: +case 0xFE2D: +case 0xFE2E: +case 0xFE2F: +case 0xFE30: +case 0xFE31: +case 0xFE32: +case 0xFE33: +case 0xFE34: +case 0xFE35: +case 0xFE36: +case 0xFE37: +case 0xFE38: +case 0xFE39: +case 0xFE3A: +case 0xFE3B: +case 0xFE3C: +case 0xFE3D: +case 0xFE3E: +case 0xFE3F: +case 0xFE40: +case 0xFE41: +case 0xFE42: +case 0xFE43: +case 0xFE44: +case 0xFE45: +case 0xFE46: +case 0xFE47: +case 0xFE48: +case 0xFE49: +case 0xFE4A: +case 0xFE4B: +case 0xFE4C: +case 0xFE4D: +case 0xFE4E: +case 0xFE4F: +case 0xFE50: +case 0xFE51: +case 0xFE52: +case 0xFE53: +case 0xFE54: +case 0xFE55: +case 0xFE56: +case 0xFE57: +case 0xFE58: +case 0xFE59: +case 0xFE5A: +case 0xFE5B: +case 0xFE5C: +case 0xFE5D: +case 0xFE5E: +case 0xFE5F: +case 0xFE60: +case 0xFE61: +case 0xFE62: +case 0xFE63: +case 0xFE64: +case 0xFE65: +case 0xFE66: +case 0xFE67: +case 0xFE68: +case 0xFE69: +case 0xFE6A: +case 0xFE6B: +case 0xFE6C: +case 0xFE6D: +case 0xFE6E: +case 0xFE6F: +case 0xFE70: +case 0xFE71: +case 0xFE72: +case 0xFE73: +case 0xFE74: +case 0xFE75: +case 0xFE76: +case 0xFE77: +case 0xFE78: +case 0xFE79: +case 0xFE7A: +case 0xFE7B: +case 0xFE7C: +case 0xFE7D: +case 0xFE7E: +case 0xFE7F: +case 0xFE80: +case 0xFE81: +case 0xFE82: +case 0xFE83: +case 0xFE84: +case 0xFE85: +case 0xFE86: +case 0xFE87: +case 0xFE88: +case 0xFE89: +case 0xFE8A: +case 0xFE8B: +case 0xFE8C: +case 0xFE8D: +case 0xFE8E: +case 0xFE8F: +case 0xFE90: +case 0xFE91: +case 0xFE92: +case 0xFE93: +case 0xFE94: +case 0xFE95: +case 0xFE96: +case 0xFE97: +case 0xFE98: +case 0xFE99: +case 0xFE9A: +case 0xFE9B: +case 0xFE9C: +case 0xFE9D: +case 0xFE9E: +case 0xFE9F: +case 0xFEA0: +case 0xFEA1: +case 0xFEA2: +case 0xFEA3: +case 0xFEA4: +case 0xFEA5: +case 0xFEA6: +case 0xFEA7: +case 0xFEA8: +case 0xFEA9: +case 0xFEAA: +case 0xFEAB: +case 0xFEAC: +case 0xFEAD: +case 0xFEAE: +case 0xFEAF: +case 0xFEB0: +case 0xFEB1: +case 0xFEB2: +case 0xFEB3: +case 0xFEB4: +case 0xFEB5: +case 0xFEB6: +case 0xFEB7: +case 0xFEB8: +case 0xFEB9: +case 0xFEBA: +case 0xFEBB: +case 0xFEBC: +case 0xFEBD: +case 0xFEBE: +case 0xFEBF: +case 0xFEC0: +case 0xFEC1: +case 0xFEC2: +case 0xFEC3: +case 0xFEC4: +case 0xFEC5: +case 0xFEC6: +case 0xFEC7: +case 0xFEC8: +case 0xFEC9: +case 0xFECA: +case 0xFECB: +case 0xFECC: +case 0xFECD: +case 0xFECE: +case 0xFECF: +case 0xFED0: +case 0xFED1: +case 0xFED2: +case 0xFED3: +case 0xFED4: +case 0xFED5: +case 0xFED6: +case 0xFED7: +case 0xFED8: +case 0xFED9: +case 0xFEDA: +case 0xFEDB: +case 0xFEDC: +case 0xFEDD: +case 0xFEDE: +case 0xFEDF: +case 0xFEE0: +case 0xFEE1: +case 0xFEE2: +case 0xFEE3: +case 0xFEE4: +case 0xFEE5: +case 0xFEE6: +case 0xFEE7: +case 0xFEE8: +case 0xFEE9: +case 0xFEEA: +case 0xFEEB: +case 0xFEEC: +case 0xFEED: +case 0xFEEE: +case 0xFEEF: +case 0xFEF0: +case 0xFEF1: +case 0xFEF2: +case 0xFEF3: +case 0xFEF4: +case 0xFEF5: +case 0xFEF6: +case 0xFEF7: +case 0xFEF8: +case 0xFEF9: +case 0xFEFA: +case 0xFEFB: +case 0xFEFC: +case 0xFEFD: +case 0xFEFE: +case 0xFEFF: +case 0xFF00: +case 0xFF01: +case 0xFF02: +case 0xFF03: +case 0xFF04: +case 0xFF05: +case 0xFF06: +case 0xFF07: +case 0xFF08: +case 0xFF09: +case 0xFF0A: +case 0xFF0B: +case 0xFF0C: +case 0xFF0D: +case 0xFF0E: +case 0xFF0F: +case 0xFF10: +case 0xFF11: +case 0xFF12: +case 0xFF13: +case 0xFF14: +case 0xFF15: +case 0xFF16: +case 0xFF17: +case 0xFF18: +case 0xFF19: +case 0xFF1A: +case 0xFF1B: +case 0xFF1C: +case 0xFF1D: +case 0xFF1E: +case 0xFF1F: +case 0xFF20: +case 0xFF21: +case 0xFF22: +case 0xFF23: +case 0xFF24: +case 0xFF25: +case 0xFF26: +case 0xFF27: +case 0xFF28: +case 0xFF29: +case 0xFF2A: +case 0xFF2B: +case 0xFF2C: +case 0xFF2D: +case 0xFF2E: +case 0xFF2F: +case 0xFF30: +case 0xFF31: +case 0xFF32: +case 0xFF33: +case 0xFF34: +case 0xFF35: +case 0xFF36: +case 0xFF37: +case 0xFF38: +case 0xFF39: +case 0xFF3A: +case 0xFF3B: +case 0xFF3C: +case 0xFF3D: +case 0xFF3E: +case 0xFF3F: +case 0xFF40: +case 0xFF41: +case 0xFF42: +case 0xFF43: +case 0xFF44: +case 0xFF45: +case 0xFF46: +case 0xFF47: +case 0xFF48: +case 0xFF49: +case 0xFF4A: +case 0xFF4B: +case 0xFF4C: +case 0xFF4D: +case 0xFF4E: +case 0xFF4F: +case 0xFF50: +case 0xFF51: +case 0xFF52: +case 0xFF53: +case 0xFF54: +case 0xFF55: +case 0xFF56: +case 0xFF57: +case 0xFF58: +case 0xFF59: +case 0xFF5A: +case 0xFF5B: +case 0xFF5C: +case 0xFF5D: +case 0xFF5E: +case 0xFF5F: +case 0xFF60: +case 0xFF61: +case 0xFF62: +case 0xFF63: +case 0xFF64: +case 0xFF65: +case 0xFF66: +case 0xFF67: +case 0xFF68: +case 0xFF69: +case 0xFF6A: +case 0xFF6B: +case 0xFF6C: +case 0xFF6D: +case 0xFF6E: +case 0xFF6F: +case 0xFF70: +case 0xFF71: +case 0xFF72: +case 0xFF73: +case 0xFF74: +case 0xFF75: +case 0xFF76: +case 0xFF77: +case 0xFF78: +case 0xFF79: +case 0xFF7A: +case 0xFF7B: +case 0xFF7C: +case 0xFF7D: +case 0xFF7E: +case 0xFF7F: +case 0xFF80: +case 0xFF81: +case 0xFF82: +case 0xFF83: +case 0xFF84: +case 0xFF85: +case 0xFF86: +case 0xFF87: +case 0xFF88: +case 0xFF89: +case 0xFF8A: +case 0xFF8B: +case 0xFF8C: +case 0xFF8D: +case 0xFF8E: +case 0xFF8F: +case 0xFF90: +case 0xFF91: +case 0xFF92: +case 0xFF93: +case 0xFF94: +case 0xFF95: +case 0xFF96: +case 0xFF97: +case 0xFF98: +case 0xFF99: +case 0xFF9A: +case 0xFF9B: +case 0xFF9C: +case 0xFF9D: +case 0xFF9E: +case 0xFF9F: +case 0xFFA0: +case 0xFFA1: +case 0xFFA2: +case 0xFFA3: +case 0xFFA4: +case 0xFFA5: +case 0xFFA6: +case 0xFFA7: +case 0xFFA8: +case 0xFFA9: +case 0xFFAA: +case 0xFFAB: +case 0xFFAC: +case 0xFFAD: +case 0xFFAE: +case 0xFFAF: +case 0xFFB0: +case 0xFFB1: +case 0xFFB2: +case 0xFFB3: +case 0xFFB4: +case 0xFFB5: +case 0xFFB6: +case 0xFFB7: +case 0xFFB8: +case 0xFFB9: +case 0xFFBA: +case 0xFFBB: +case 0xFFBC: +case 0xFFBD: +case 0xFFBE: +case 0xFFBF: +case 0xFFC0: +case 0xFFC1: +case 0xFFC2: +case 0xFFC3: +case 0xFFC4: +case 0xFFC5: +case 0xFFC6: +case 0xFFC7: +case 0xFFC8: +case 0xFFC9: +case 0xFFCA: +case 0xFFCB: +case 0xFFCC: +case 0xFFCD: +case 0xFFCE: +case 0xFFCF: +case 0xFFD0: +case 0xFFD1: +case 0xFFD2: +case 0xFFD3: +case 0xFFD4: +case 0xFFD5: +case 0xFFD6: +case 0xFFD7: +case 0xFFD8: +case 0xFFD9: +case 0xFFDA: +case 0xFFDB: +case 0xFFDC: +case 0xFFDD: +case 0xFFDE: +case 0xFFDF: +case 0xFFE0: +case 0xFFE1: +case 0xFFE2: +case 0xFFE3: +case 0xFFE4: +case 0xFFE5: +case 0xFFE6: +case 0xFFE7: +case 0xFFE8: +case 0xFFE9: +case 0xFFEA: +case 0xFFEB: +case 0xFFEC: +case 0xFFED: +case 0xFFEE: +case 0xFFEF: +case 0xFFF0: +case 0xFFF1: +case 0xFFF2: +case 0xFFF3: +case 0xFFF4: +case 0xFFF5: +case 0xFFF6: +case 0xFFF7: +case 0xFFF8: +case 0xFFF9: +case 0xFFFA: +case 0xFFFB: +case 0xFFFC: +case 0xFFFD: +case 0xFFFE: +case 0xFFFF: + +// 1111 +case 0xF000: +{ + u32 res; + PC -= 2; + if (!CPU->flag_S) + { + res = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = res; + } + res = C68K_1111_EX; + CCnt -= c68k_exception_cycle_table[res]; + PRE_IO + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + CPU->flag_S = C68K_SR_S; + READ_LONG_F(res * 4, PC) + SET_PC(PC) + POST_IO +} +RET(4) diff --git a/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68kexec.c b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68kexec.c new file mode 100644 index 000000000..ccdaa4b75 --- /dev/null +++ b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68kexec.c @@ -0,0 +1,343 @@ +/* Copyright 2003-2004 Stephane Dallongeville + + This file is part of Yabause. + + Yabause is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + Yabause is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with Yabause; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#include "core.h" +#include "c68k.h" + +// #define TRACE_WITH_Q68 // Define to use Q68 tracing code to trace insns + // (requires Q68 built in, of course) + +#ifdef NEOCD_HLE +void cdrom_load_files(void); +void neogeo_cdda_control(void); +void neogeo_prio_switch(void); +void neogeo_upload(void); +#endif + +// exception cycle table (taken from musashi core) +static const s32 c68k_exception_cycle_table[256] = +{ + 4, // 0: Reset - Initial Stack Pointer + 4, // 1: Reset - Initial Program Counter + 50, // 2: Bus Error + 50, // 3: Address Error + 34, // 4: Illegal Instruction + 38, // 5: Divide by Zero + 40, // 6: CHK + 34, // 7: TRAPV + 34, // 8: Privilege Violation + 34, // 9: Trace + 4, // 10: + 4, // 11: + 4, // 12: RESERVED + 4, // 13: Coprocessor Protocol Violation + 4, // 14: Format Error + 44, // 15: Uninitialized Interrupt + 4, // 16: RESERVED + 4, // 17: RESERVED + 4, // 18: RESERVED + 4, // 19: RESERVED + 4, // 20: RESERVED + 4, // 21: RESERVED + 4, // 22: RESERVED + 4, // 23: RESERVED + 44, // 24: Spurious Interrupt + 44, // 25: Level 1 Interrupt Autovector + 44, // 26: Level 2 Interrupt Autovector + 44, // 27: Level 3 Interrupt Autovector + 44, // 28: Level 4 Interrupt Autovector + 44, // 29: Level 5 Interrupt Autovector + 44, // 30: Level 6 Interrupt Autovector + 44, // 31: Level 7 Interrupt Autovector + 34, // 32: TRAP #0 + 34, // 33: TRAP #1 + 34, // 34: TRAP #2 + 34, // 35: TRAP #3 + 34, // 36: TRAP #4 + 34, // 37: TRAP #5 + 34, // 38: TRAP #6 + 34, // 39: TRAP #7 + 34, // 40: TRAP #8 + 34, // 41: TRAP #9 + 34, // 42: TRAP #10 + 34, // 43: TRAP #11 + 34, // 44: TRAP #12 + 34, // 45: TRAP #13 + 34, // 46: TRAP #14 + 34, // 47: TRAP #15 + 4, // 48: FP Branch or Set on Unknown Condition + 4, // 49: FP Inexact Result + 4, // 50: FP Divide by Zero + 4, // 51: FP Underflow + 4, // 52: FP Operand Error + 4, // 53: FP Overflow + 4, // 54: FP Signaling NAN + 4, // 55: FP Unimplemented Data Type + 4, // 56: MMU Configuration Error + 4, // 57: MMU Illegal Operation Error + 4, // 58: MMU Access Level Violation Error + 4, // 59: RESERVED + 4, // 60: RESERVED + 4, // 61: RESERVED + 4, // 62: RESERVED + 4, // 63: RESERVED + // 64-255: User Defined + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4, + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4, + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4, + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4, + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4, + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4 +}; + +// global variable +/////////////////// + +#ifndef C68K_GEN + +#ifndef C68K_NO_JUMP_TABLE +#ifndef C68K_CONST_JUMP_TABLE +static void *JumpTable[0x10000]; +#endif +#endif + +static u32 C68k_Initialised = 0; + +#endif // C68K_GEN + +#ifdef NEOCD_HLE +extern int img_display; +#endif + +// include macro file +////////////////////// + +#include "c68kmac.inc" + +#ifndef C68K_GEN +# ifdef TRACE_WITH_Q68 +#include "../q68/q68.h" +static c68k_struc *TRACE_CPU; +static uint32_t readw(uint32_t address) { + return TRACE_CPU->Read_Word(address); +} +/* Make our own version of the structure to avoid the overhead of dozens of + * function calls every instruction */ +static struct { + u32 D[8], A[8], PC, SR, USP, SSP, dummy[7]; + void *readb, *readw, *writeb, *writew; +} state = {.readw = readw}; +void TRACE(int PC,c68k_struc *CPU,int Opcode,int CCnt) { + static FILE *f; + if (!f) f = fopen("c68k.log", "w"); + TRACE_CPU = CPU; + memcpy(state.D, CPU->D, 16*4); + state.PC = PC - 2 - CPU->BasePC; + state.SR = GET_SR; + if (f) q68_trace((Q68State *)&state, f, + CPU->CycleToDo - CCnt, CPU->CycleToDo); +} +# endif // TRACE_WITH_Q68 +#endif // !C68K_GEN + +// main exec function +////////////////////// + +#if defined(SCSP_LOG) +extern unsigned char ** scsp_pc; +#endif + +s32 FASTCALL C68k_Exec(c68k_struc *cpu, s32 cycle) +{ +#ifndef C68K_GEN +#if 0 + register c68k_struc *CPU asm ("ebx"); + register pointer PC asm ("esi"); + register s32 CCnt asm ("edi"); +// register u32 Opcode asm ("edi"); +// c68k_struc *CPU; +// u32 PC; +// s32 CCnt; + u32 Opcode; +#else +// register c68k_struc *CPU asm ("r10"); +// register u32 PC asm ("r11"); +// register s32 CCnt asm ("r12"); +// register u32 Opcode asm ("r13"); + c68k_struc *CPU; + pointer PC; + s32 CCnt; + u32 Opcode; +#endif +#endif + +#if defined(SCSP_LOG) + scsp_pc = &PC; +#endif + +#ifndef C68K_GEN + +#ifndef C68K_NO_JUMP_TABLE +#ifdef C68K_CONST_JUMP_TABLE + #include "c68k_ini.inc" +#endif +#else + C68k_Initialised = 1; +#endif + + CPU = cpu; + PC = CPU->PC; + + if (CPU->Status & (C68K_RUNNING | C68K_DISABLE | C68K_FAULTED)) + { +#ifndef C68K_NO_JUMP_TABLE +#ifndef C68K_CONST_JUMP_TABLE + if (!C68k_Initialised) goto C68k_Init; +#endif +#endif + return (CPU->Status | 0x80000000); + } + + if (cycle <= 0) return -cycle; + + CPU->CycleToDo = CCnt = cycle; + +#ifndef C68K_DEBUG + CHECK_INT +#else + { + s32 line, vect; + + line = CPU->IRQLine; + + if ((line == 7) || (line > CPU->flag_I)) + { + PRE_IO + + /* get vector */ + CPU->IRQLine = 0; + vect = CPU->Interrupt_CallBack(line); + if (vect == C68K_INT_ACK_AUTOVECTOR) + vect = C68K_INTERRUPT_AUTOVECTOR_EX + (line & 7); + + /* adjust CCnt */ + CCnt -= c68k_exception_cycle_table[vect]; + + /* swap A7 and USP */ + if (!CPU->flag_S) + { + u32 tmpSP; + + tmpSP = CPU->USP; + CPU->USP = CPU->A[7]; + CPU->A[7] = tmpSP; + } + + /* push PC and SR */ + PUSH_32_F(PC - CPU->BasePC) + PUSH_16_F(GET_SR) + + /* adjust SR */ + CPU->flag_S = C68K_SR_S; + CPU->flag_I = line; + + /* fetch new PC */ + READ_LONG_F(vect * 4, PC) + SET_PC(PC) + + POST_IO + } + } +#endif + + if (CPU->Status & (C68K_HALTED | C68K_WAITING)) return CPU->CycleToDo; + + CPU->CycleSup = 0; + CPU->Status |= C68K_RUNNING; + +#ifndef C68K_DEBUG + NEXT +#else +#ifdef C68K_NO_JUMP_TABLE + NEXT +#else + Opcode = FETCH_WORD; + PC += 2; + goto *JumpTable[Opcode]; +#endif +#endif + +#ifdef C68K_NO_JUMP_TABLE +SwitchTable: + switch(Opcode) + { +#endif + #include "c68k_op0.inc" + #include "c68k_op1.inc" + #include "c68k_op2.inc" + #include "c68k_op3.inc" + #include "c68k_op4.inc" + #include "c68k_op5.inc" + #include "c68k_op6.inc" + #include "c68k_op7.inc" + #include "c68k_op8.inc" + #include "c68k_op9.inc" + #include "c68k_opA.inc" + #include "c68k_opB.inc" + #include "c68k_opC.inc" + #include "c68k_opD.inc" + #include "c68k_opE.inc" + #include "c68k_opF.inc" +#ifdef C68K_NO_JUMP_TABLE + } +#endif + +C68k_Exec_End: + CHECK_INT + if ((CCnt += CPU->CycleSup) > 0) + { + CPU->CycleSup = 0; + NEXT; + } + +C68k_Exec_Really_End: + CPU->Status &= ~C68K_RUNNING; + CPU->PC = PC; + + return (CPU->CycleToDo - CCnt); + +#ifndef C68K_CONST_JUMP_TABLE +#ifndef C68K_NO_JUMP_TABLE +C68k_Init: + { + u32 i, j; + + #include "c68k_ini.inc" + + C68k_Initialised = 1; + } + + return 0; +#endif +#endif +#else + return 0; +#endif +} + diff --git a/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68kmac.inc b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68kmac.inc new file mode 100644 index 000000000..bfcf0a27f --- /dev/null +++ b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/c68kmac.inc @@ -0,0 +1,307 @@ +/* Copyright 2003-2004 Stephane Dallongeville + + This file is part of Yabause. + + Yabause is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + Yabause is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with Yabause; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +// internals core macros +///////////////////////// + +#define LSL(A, C) ((A) << (C)) +#define LSR(A, C) ((A) >> (C)) + +#define LSR_32(A, C) ((C) < 32 ? (A) >> (C) : 0) +#define LSL_32(A, C) ((C) < 32 ? (A) << (C) : 0) + +#define ROL_8(A, C) (LSL(A, C) | LSR(A, 8-(C))) +#define ROL_9(A, C) (LSL(A, C) | LSR(A, 9-(C))) +#define ROL_16(A, C) (LSL(A, C) | LSR(A, 16-(C))) +#define ROL_17(A, C) (LSL(A, C) | LSR(A, 17-(C))) +#define ROL_32(A, C) (LSL_32(A, C) | LSR_32(A, 32-(C))) +#define ROL_33(A, C) (LSL_32(A, C) | LSR_32(A, 33-(C))) + +#define ROR_8(A, C) (LSR(A, C) | LSL(A, 8-(C))) +#define ROR_9(A, C) (LSR(A, C) | LSL(A, 9-(C))) +#define ROR_16(A, C) (LSR(A, C) | LSL(A, 16-(C))) +#define ROR_17(A, C) (LSR(A, C) | LSL(A, 17-(C))) +#define ROR_32(A, C) (LSR_32(A, C) | LSL_32(A, 32-(C))) +#define ROR_33(A, C) (LSR_32(A, C) | LSL_32(A, 33-(C))) + + +#ifdef TRACE_WITH_Q68 +extern void TRACE(int,c68k_struc*,int,int); +#else +# define TRACE(a,b,c,d) /*nothing*/ +#endif +#ifndef C68K_NO_JUMP_TABLE +#define NEXT \ + PRE_IO \ + Opcode = FETCH_WORD; \ + PC += 2; \ + TRACE(PC, CPU, Opcode, CCnt); \ + goto *JumpTable[Opcode]; +#else +#define NEXT \ + PRE_IO \ + Opcode = FETCH_WORD; \ + PC += 2; \ + TRACE(PC, CPU, Opcode, CCnt); \ + goto SwitchTable; +#endif + +#define RET(A) \ + CCnt -= (A); \ + if (CCnt <= 0) goto C68k_Exec_End; \ + NEXT + +#define SET_PC(A) \ + CPU->BasePC = CPU->Fetch[((A) >> C68K_FETCH_SFT) & C68K_FETCH_MASK]; \ + CPU->BasePC -= (A) & 0xFF000000; \ + PC = (A) + CPU->BasePC; + +#define PRE_IO \ + CPU->CycleIO = CCnt; + +#define POST_IO \ + CCnt = CPU->CycleIO; + +#define READ_BYTE_F(A, D) \ + D = CPU->Read_Byte(CPU->Callback_Param, A) & 0xFF; + +#define READ_WORD_F(A, D) \ + D = CPU->Read_Word(CPU->Callback_Param, A) & 0xFFFF; + +#ifdef C68K_BIG_ENDIAN + #define READ_LONG_F(A, D) \ + D = CPU->Read_Word(CPU->Callback_Param, (A)) << 16; \ + D |= CPU->Read_Word(CPU->Callback_Param, (A) + 2) & 0xFFFF; + + #define READ_LONG_DEC_F(A, D) \ + D = CPU->Read_Word(CPU->Callback_Param, (A) + 2) & 0xFFFF; \ + D |= CPU->Read_Word(CPU->Callback_Param, (A)) << 16; +#else + #define READ_LONG_F(A, D) \ + D = CPU->Read_Word(CPU->Callback_Param, (A)) << 16; \ + D |= CPU->Read_Word(CPU->Callback_Param, (A) + 2) & 0xFFFF; + + #define READ_LONG_DEC_F(A, D) \ + D = CPU->Read_Word(CPU->Callback_Param, (A) + 2) & 0xFFFF; \ + D |= CPU->Read_Word(CPU->Callback_Param, (A)) << 16; +#endif + +#define READSX_BYTE_F(A, D) \ + D = (s32)(s8)CPU->Read_Byte(CPU->Callback_Param, A); + +#define READSX_WORD_F(A, D) \ + D = (s32)(s16)CPU->Read_Word(CPU->Callback_Param, A); + +#ifdef C68K_BIG_ENDIAN + #define READSX_LONG_F(A, D) \ + D = CPU->Read_Word(CPU->Callback_Param, (A)) << 16; \ + D |= CPU->Read_Word(CPU->Callback_Param, (A) + 2) & 0xFFFF; + + #define READSX_LONG_DEC_F(A, D) \ + D = CPU->Read_Word(CPU->Callback_Param, (A) + 2) & 0xFFFF; \ + D |= CPU->Read_Word(CPU->Callback_Param, (A)) << 16; +#else + #define READSX_LONG_F(A, D) \ + D = CPU->Read_Word(CPU->Callback_Param, (A)) << 16; \ + D |= CPU->Read_Word(CPU->Callback_Param, (A) + 2) & 0xFFFF; + + #define READSX_LONG_DEC_F(A, D) \ + D = CPU->Read_Word(CPU->Callback_Param, (A) + 2) & 0xFFFF; \ + D |= CPU->Read_Word(CPU->Callback_Param, (A)) << 16; +#endif + +#define WRITE_BYTE_F(A, D) \ + CPU->Write_Byte(CPU->Callback_Param, A, D); + +#define WRITE_WORD_F(A, D) \ + CPU->Write_Word(CPU->Callback_Param, A, D); + +#ifdef C68K_BIG_ENDIAN + #define WRITE_LONG_F(A, D) \ + CPU->Write_Word(CPU->Callback_Param, (A), (D) >> 16); \ + CPU->Write_Word(CPU->Callback_Param, (A) + 2, (D) & 0xFFFF); + + #define WRITE_LONG_DEC_F(A, D) \ + CPU->Write_Word(CPU->Callback_Param, (A) + 2, (D) & 0xFFFF); \ + CPU->Write_Word(CPU->Callback_Param, (A), (D) >> 16); +#else + #define WRITE_LONG_F(A, D) \ + CPU->Write_Word(CPU->Callback_Param, (A), (D) >> 16); \ + CPU->Write_Word(CPU->Callback_Param, (A) + 2, (D) & 0xFFFF); + + #define WRITE_LONG_DEC_F(A, D) \ + CPU->Write_Word(CPU->Callback_Param, (A) + 2, (D) & 0xFFFF); \ + CPU->Write_Word(CPU->Callback_Param, (A), (D) >> 16); +#endif + +#define PUSH_16_F(D) \ + CPU->Write_Word(CPU->Callback_Param, CPU->A[7] -= 2, D); \ + +#define POP_16_F(D) \ + D = (u16)CPU->Read_Word(CPU->Callback_Param, CPU->A[7]); \ + CPU->A[7] += 2; + +#ifdef C68K_BIG_ENDIAN + #define PUSH_32_F(D) \ + CPU->A[7] -= 4; \ + CPU->Write_Word(CPU->Callback_Param, CPU->A[7] + 2, (D) & 0xFFFF); \ + CPU->Write_Word(CPU->Callback_Param, CPU->A[7], (D) >> 16); + + #define POP_32_F(D) \ + D = CPU->Read_Word(CPU->Callback_Param, CPU->A[7]) << 16; \ + D |= CPU->Read_Word(CPU->Callback_Param, CPU->A[7] + 2) & 0xFFFF; \ + CPU->A[7] += 4; +#else + #define PUSH_32_F(D) \ + CPU->A[7] -= 4; \ + CPU->Write_Word(CPU->Callback_Param, CPU->A[7] + 2, (D) & 0xFFFF); \ + CPU->Write_Word(CPU->Callback_Param, CPU->A[7], (D) >> 16); + + #define POP_32_F(D) \ + D = CPU->Read_Word(CPU->Callback_Param, CPU->A[7]) << 16; \ + D |= CPU->Read_Word(CPU->Callback_Param, CPU->A[7] + 2) & 0xFFFF; \ + CPU->A[7] += 4; +#endif + +#define FETCH_BYTE \ +((*(u16*)PC) & 0xFF) + +#define FETCH_WORD \ +(*(u16*)PC) + + +#define FETCH_LONG \ +(*(u32*)PC) + +#define DECODE_EXT_WORD \ +{ \ + u32 ext; \ + \ + ext = (*(u16*)PC); \ + PC += 2; \ + \ + adr += (s32)((s8)(ext)); \ + if (ext & 0x0800) adr += (s32) CPU->D[ext >> 12]; \ + else adr += (s32)((s16)(CPU->D[ext >> 12])); \ +} + +#ifndef C68K_BIG_ENDIAN +#ifdef C68K_BYTE_SWAP_OPT + #undef FETCH_LONG + #define FETCH_LONG \ + ((((u32)(*(u16*)PC)) << 16) | ((u32)(*(u16*)(PC + 2)))) +// ((((u32)(*(u8*)(PC + 2))) | (((u32)(*(u8*)(PC + 3))) << 8) | (((u32)(*(u8*)PC)) << 16) | (((u32)(*(u8*)(PC + 1))) << 24))) +#else + #undef FETCH_BYTE + #define FETCH_BYTE \ + (*(u16*)PC) >> 8) + + #undef FETCH_WORD + #define FETCH_WORD \ + ((((u16)(*(u8*)PC)) << 8) | ((u16)(*(u8*)(PC + 1)))) +// ((((u16)(*(u8*)(PC + 1))) | (((u16)(*(u8*)PC)) << 8))) + + #undef FETCH_LONG + #define FETCH_LONG \ + ((((u32)(*(u8*)PC)) << 24) | (((u32)(*(u8*)(PC + 1))) << 16) | (((u32)(*(u8*)(PC + 2))) << 8) | ((u32)(*(u8*)(PC + 3)))) +// ((((u32)(*(u8*)(PC + 3))) | (((u32)(*(u8*)(PC + 2))) << 8) | (((u32)(*(u8*)(PC + 1))) << 16) | (((u32)(*(u8*)PC)) << 24))) + + #undef DECODE_EXT_WORD + #define DECODE_EXT_WORD \ + { \ + u32 ext; \ + \ + ext = (*(u16*)PC); \ + PC += 2; \ + \ + adr += (s32)((s8)(ext >> 8)); \ + if (ext & 0x0008) adr += (s32) CPU->D[(ext >> 4) & 0x000F]; \ + else adr += (s32)((s16)(CPU->D[(ext >> 4) & 0x000F])); \ + } +#endif +#endif + +#define GET_CCR \ + (((CPU->flag_C >> (C68K_SR_C_SFT - 0)) & 1) | \ + ((CPU->flag_V >> (C68K_SR_V_SFT - 1)) & 2) | \ + (((!CPU->flag_notZ) & 1) << 2) | \ + ((CPU->flag_N >> (C68K_SR_N_SFT - 3)) & 8) | \ + ((CPU->flag_X >> (C68K_SR_X_SFT - 4)) & 0x10)) + +#define GET_SR \ + ((CPU->flag_S << 0) | \ + (CPU->flag_I << 8) | \ + GET_CCR) + +#define SET_CCR(A) \ + CPU->flag_C = (A) << (C68K_SR_C_SFT - 0); \ + CPU->flag_V = (A) << (C68K_SR_V_SFT - 1); \ + CPU->flag_notZ = ~(A) & 4; \ + CPU->flag_N = (A) << (C68K_SR_N_SFT - 3); \ + CPU->flag_X = (A) << (C68K_SR_X_SFT - 4); + +#define SET_SR(A) \ + SET_CCR(A) \ + CPU->flag_I = ((A) >> 8) & 7; \ + CPU->flag_S = (A) & C68K_SR_S; + +#define CHECK_INT \ + { \ + s32 line, vect; \ + \ + line = CPU->IRQLine; \ + \ + if ((line == 7) || (line > CPU->flag_I)) \ + { \ + /* get vector */ \ + CPU->IRQLine = 0; \ + vect = CPU->Interrupt_CallBack(CPU->Callback_Param, line); \ + if (vect == C68K_INT_ACK_AUTOVECTOR) \ + vect = C68K_INTERRUPT_AUTOVECTOR_EX + (line & 7); \ + \ + /* adjust CCnt */ \ + CCnt -= c68k_exception_cycle_table[vect]; \ + \ + /* swap A7 and USP */ \ + if (!CPU->flag_S) \ + { \ + u32 tmpSP; \ + \ + tmpSP = CPU->USP; \ + CPU->USP = CPU->A[7]; \ + CPU->A[7] = tmpSP; \ + } \ + \ + PRE_IO \ + \ + /* push PC and SR */ \ + PUSH_32_F(PC - CPU->BasePC) \ + PUSH_16_F(GET_SR) \ + \ + /* adjust SR */ \ + CPU->flag_S = C68K_SR_S; \ + CPU->flag_I = line; \ + \ + /* fetch new PC */ \ + READ_LONG_F(vect * 4, PC) \ + SET_PC(PC) \ + \ + POST_IO \ + } \ + } diff --git a/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/core.h b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/core.h new file mode 100644 index 000000000..ab59a828a --- /dev/null +++ b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/core.h @@ -0,0 +1,284 @@ +/* Copyright 2005 Guillaume Duhamel + Copyright 2005-2006 Theo Berkau + + This file is part of Yabause. + + Yabause is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + Yabause is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with Yabause; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#ifndef CORE_H +#define CORE_H + +#include +#include + +#ifndef ALIGNED +#ifdef _MSC_VER +#define ALIGNED(x) __declspec(align(x)) +#else +#define ALIGNED(x) __attribute__((aligned(x))) +#endif +#endif + +#ifndef STDCALL +#ifdef _MSC_VER +#define STDCALL __stdcall +#else +#define STDCALL +#endif +#endif + +#ifndef FASTCALL +#ifdef __MINGW32__ +#define FASTCALL __attribute__((fastcall)) +#elif defined (__i386__) +#define FASTCALL __attribute__((regparm(3))) +#elif defined (_MSC_VER) +#define FASTCALL __fastcall +#else +#define FASTCALL +#endif +#endif + +/* When building multiple arches on OS X you must use the compiler- + provided endian flags instead of the one provided by autoconf */ +#if defined(__BIG_ENDIAN__) || defined(__LITTLE_ENDIAN__) + #undef WORDS_BIGENDIAN + #ifdef __BIG_ENDIAN__ + #define WORDS_BIGENDIAN + #endif +#endif + + +#ifndef INLINE +#ifdef _MSC_VER +#define INLINE _inline +#else +#define INLINE inline +#endif +#endif + +#ifdef GEKKO +/* Wii have both stdint.h and "yabause" definitions of fixed +size types */ +#include +typedef unsigned long pointer; + +#else /* ! GEKKO */ + +#if _MSC_VER >= 1600 +#define HAVE_STDINT_H +#endif + +#ifdef HAVE_STDINT_H + +#include +typedef uint8_t u8; +typedef int8_t s8; +typedef uint16_t u16; +typedef int16_t s16; +typedef uint32_t u32; +typedef int32_t s32; +typedef uint64_t u64; +typedef int64_t s64; +typedef uintptr_t pointer; + +#else // !HAVE_STDINT_H + +typedef unsigned char u8; +typedef unsigned short u16; + +typedef signed char s8; +typedef signed short s16; + +#if defined(__LP64__) +// Generic 64-bit +typedef unsigned int u32; +typedef unsigned long u64; +typedef unsigned long pointer; + +typedef signed int s32; +typedef signed long s64; + +#elif defined(_MSC_VER) +typedef unsigned long u32; +typedef unsigned __int64 u64; +typedef unsigned long long u64; +#ifdef _WIN64 +typedef __int64 pointer; +#else +typedef unsigned long pointer; +#endif + +typedef signed long s32; +typedef __int64 s64; +typedef signed long long s64; + +#else +// 32-bit Linux GCC/MINGW/etc. +typedef unsigned long u32; +typedef unsigned long long u64; +typedef unsigned long pointer; + +typedef signed long s32; +typedef signed long long s64; +#endif + +#endif // !HAVE_STDINT_H + +#endif // !GEKKO + +typedef struct { + unsigned int size; + unsigned int done; +} IOCheck_struct; + +static INLINE void ywrite(IOCheck_struct * check, void * ptr, size_t size, size_t nmemb, FILE * stream) { + check->done += (unsigned int)fwrite(ptr, size, nmemb, stream); + check->size += (unsigned int)nmemb; +} + +static INLINE void yread(IOCheck_struct * check, void * ptr, size_t size, size_t nmemb, FILE * stream) { + check->done += (unsigned int)fread(ptr, size, nmemb, stream); + check->size += (unsigned int)nmemb; +} + +static INLINE int StateWriteHeader(FILE *fp, const char *name, int version) { + IOCheck_struct check; + fprintf(fp, "%s", name); + check.done = 0; + check.size = 0; + ywrite(&check, (void *)&version, sizeof(version), 1, fp); + ywrite(&check, (void *)&version, sizeof(version), 1, fp); // place holder for size + return (check.done == check.size) ? ftell(fp) : -1; +} + +static INLINE int StateFinishHeader(FILE *fp, int offset) { + IOCheck_struct check; + int size = 0; + size = ftell(fp) - offset; + fseek(fp, offset - 4, SEEK_SET); + check.done = 0; + check.size = 0; + ywrite(&check, (void *)&size, sizeof(size), 1, fp); // write true size + fseek(fp, 0, SEEK_END); + return (check.done == check.size) ? (size + 12) : -1; +} + +static INLINE int StateCheckRetrieveHeader(FILE *fp, const char *name, int *version, int *size) { + char id[4]; + size_t ret; + + if ((ret = fread((void *)id, 1, 4, fp)) != 4) + return -1; + + if (strncmp(name, id, 4) != 0) + return -2; + + if ((ret = fread((void *)version, 4, 1, fp)) != 1) + return -1; + + if (fread((void *)size, 4, 1, fp) != 1) + return -1; + + return 0; +} + +////////////////////////////////////////////////////////////////////////////// + +#ifdef HAVE_LIBMINI18N +#include "mini18n.h" +#else +#ifndef _ +#define _(a) (a) +#endif +#endif + +////////////////////////////////////////////////////////////////////////////// + +/* Minimum/maximum values */ + +#undef MIN +#undef MAX +#define MIN(a,b) ((a) < (b) ? (a) : (b)) +#define MAX(a,b) ((a) > (b) ? (a) : (b)) + +////////////////////////////////////////////////////////////////////////////// + +/* + * BSWAP16(x) swaps two bytes in a 16-bit value (AABB -> BBAA) or adjacent + * bytes in a 32-bit value (AABBCCDD -> BBAADDCC). + * + * BSWAP32(x) reverses four bytes in a 32-bit value (AABBCCDD -> DDCCBBAA). + * + * WSWAP32(x) swaps two 16-bit words in a 32-bit value (AABBCCDD -> CCDDAABB). + * + * Any of these can be left undefined if there is no platform-specific + * optimization for them; the defaults below will then be used instead. + */ + +#ifdef PSP +# define BSWAP16(x) ((typeof(x)) __builtin_allegrex_wsbh((x))) +# define BSWAP32(x) ((typeof(x)) __builtin_allegrex_wsbw((x))) +# define WSWAP32(x) ((typeof(x)) __builtin_allegrex_rotr((x), 16)) +#endif + +/* Defaults: */ + +#ifndef BSWAP16 +# define BSWAP16(x) (((u32)(x)>>8 & 0x00FF00FF) | ((u32)(x) & 0x00FF00FF) << 8) +#endif +#ifndef BSWAP32 +# define BSWAP32(x) ((u32)(x)>>24 | ((u32)(x)>>8 & 0xFF00) | ((u32)(x) & 0xFF00)<<8 | (u32)(x)<<24) +#endif +#ifndef WSWAP32 +# define WSWAP32(x) ((u32)(x)>>16 | (u32)(x)<<16) +#endif + +////////////////////////////////////////////////////////////////////////////// + +#ifdef __GNUC__ + +#define UNUSED __attribute ((unused)) + +#ifdef DEBUG +#define USED_IF_DEBUG +#else +#define USED_IF_DEBUG __attribute ((unused)) +#endif + +#ifdef SMPC_DEBUG +#define USED_IF_SMPC_DEBUG +#else +#define USED_IF_SMPC_DEBUG __attribute ((unused)) +#endif + +/* LIKELY(x) indicates that x is likely to be true (nonzero); + * UNLIKELY(x) indicates that x is likely to be false (zero). + * Use like: "if (UNLIKELY(a < b)) {...}" */ +#define LIKELY(x) (__builtin_expect(!!(x), 1)) +#define UNLIKELY(x) (__builtin_expect(!!(x), 0)) + +#else + +#define UNUSED +#define USED_IF_DEBUG +#define USED_IF_SMPC_DEBUG +#define LIKELY(x) (x) +#define UNLIKELY(x) (x) + +#endif + +#endif diff --git a/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/gen68k.c b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/gen68k.c new file mode 100644 index 000000000..ccbc979b7 --- /dev/null +++ b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/gen68k.c @@ -0,0 +1,3820 @@ +/* Copyright 2003-2004 Stephane Dallongeville + + This file is part of Yabause. + + Yabause is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + Yabause is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with Yabause; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +/********************************************************************************* + * GEN68K.C : + * + * C68K generator source file + * + ********************************************************************************/ + +#include +#ifdef __WIN32__ +#include +#endif + +#include "core.h" +#include "c68k.h" +#include "gen68k.h" + +#ifdef C68K_GEN + +#include "gen68k.inc" + +// to do : +// need accurate cycles calculations in MUL and DIV instruction +// some bugs to fix + +// opcode generation function +////////////////////////////// + +static void GenLogicI(char op) +{ + // generate jump table & opcode declaration + if ((current_ea == EA_AREG) || (current_ea == EA_DREG) || (current_ea == EA_IMM)) + start_all(GEN_RES | GEN_SRC); + else + start_all(GEN_ADR | GEN_RES | GEN_SRC); + + if (current_ea != EA_DREG) current_cycle += 4; + switch (current_size) + { + case SIZE_BYTE: + wf_op("\tsrc = FETCH_BYTE;\n"); + wf_op("\tPC += 2;\n"); + break; + + case SIZE_WORD: + wf_op("\tsrc = FETCH_WORD;\n"); + wf_op("\tPC += 2;\n"); + break; + + case SIZE_LONG: + wf_op("\tsrc = FETCH_LONG;\n"); + wf_op("\tPC += 4;\n"); + current_cycle += 8; + break; + } + + // read + _ea_calc(current_ea, current_op->reg_sft); + _ea_read(current_ea, current_op->reg_sft); + // op + wf_op("\tres %c= src;\n", op); + // flag calculation + set_logic_flag(); + // write + _ea_write(current_ea, current_op->reg_sft); + + terminate_op(8); +} + +static void GenLogicICCR(char op) +{ + // generate jump table & opcode declaration + start_all(GEN_RES); + + wf_op("\tres = FETCH_BYTE & C68K_CCR_MASK;\n"); + wf_op("\tPC += 2;\n"); + wf_op("\tres %c= GET_CCR;\n", op); + wf_op("\tSET_CCR(res)\n"); + + terminate_op(20); +} + +static void GenLogicISR(char op) +{ + // generate jump table & opcode declaration + start_all(GEN_RES); + + wf_op("\tif (CPU->flag_S)\n"); + wf_op("\t{\n"); + wf_op("\t\tres = FETCH_WORD & C68K_SR_MASK;\n"); + wf_op("\t\tPC += 2;\n"); + wf_op("\t\tres %c= GET_SR;\n", op); + wf_op("\t\tSET_SR(res)\n"); + if (op != '|') + { + wf_op("\t\tif (!CPU->flag_S)\n"); + wf_op("\t\t{\n"); + wf_op("\t\t\tres = CPU->A[7];\n"); + wf_op("\t\t\tCPU->A[7] = CPU->USP;\n"); + wf_op("\t\t\tCPU->USP = res;\n"); + wf_op("\t\t}\n"); + } + wf_op("\t}\n"); + wf_op("\telse\n"); + wf_op("\t{\n"); + gen_privilege_exception("\t\t"); + wf_op("\t}\n"); + + // check for interrupt + fterminate_op(20); +} + +static void GenORI() +{ + GenLogicI('|'); +} + +static void GenORICCR() +{ + GenLogicICCR('|'); +} + +static void GenORISR() +{ + GenLogicISR('|'); +} + +static void GenANDI() +{ + GenLogicI('&'); +} + +static void GenANDICCR() +{ + GenLogicICCR('&'); +} + +static void GenANDISR() +{ + GenLogicISR('&'); +} + +static void GenEORI() +{ + GenLogicI('^'); +} + +static void GenEORICCR() +{ + GenLogicICCR('^'); +} + +static void GenEORISR() +{ + GenLogicISR('^'); +} + +static void GenArithI(char op) +{ + // generate jump table & opcode declaration + if ((current_ea == EA_AREG) || (current_ea == EA_DREG) || (current_ea == EA_IMM)) + start_all(GEN_RES | GEN_SRC | GEN_DST); + else + start_all(GEN_ALL); + + if ((op != ' ') && (current_ea != EA_DREG)) current_cycle += 4; + switch (current_size) + { + case SIZE_BYTE: + wf_op("\tsrc = FETCH_BYTE;\n"); + wf_op("\tPC += 2;\n"); + break; + + case SIZE_WORD: + wf_op("\tsrc = FETCH_WORD;\n"); + wf_op("\tPC += 2;\n"); + break; + + case SIZE_LONG: + wf_op("\tsrc = FETCH_LONG;\n"); + wf_op("\tPC += 4;\n"); + if (op == ' ') + { + if (current_ea == EA_DREG) current_cycle += 6; + else current_cycle += 4; + } else current_cycle += 8; + break; + } + + // read + _ea_calc(current_ea, current_op->reg_sft); + _ea_read_dst(current_ea, current_op->reg_sft); + if (op == ' ') + { + // op + wf_op("\tres = dst - src;\n"); + // flag calculation + set_cmp_flag(); + } + else + { + // op + wf_op("\tres = dst %c src;\n", op); + // flag calculation + if (op == '+') set_add_flag(); + else set_sub_flag(); + // write + _ea_write(current_ea, current_op->reg_sft); + } + + terminate_op(8); +} + +static void GenSUBI() +{ + GenArithI('-'); +} + +static void GenADDI() +{ + GenArithI('+'); +} + +static void GenCMPI() +{ + GenArithI(' '); +} + +static void GenBitsOp(char op, u32 dyn) +{ + // generate jump table & opcode declaration + if (dyn) current_ea2 = EA_DREG; + if ((current_ea == EA_AREG) || (current_ea == EA_DREG) || (current_ea == EA_IMM)) + start_all(GEN_RES | GEN_SRC); + else + start_all(GEN_ADR | GEN_RES | GEN_SRC); + + if (current_ea == EA_DREG) + { + set_current_size(SIZE_LONG); + if ((op == 'c') || (op == ' ')) current_cycle += 2; + } + else set_current_size(SIZE_BYTE); + + // get shift value in src + if (dyn) + { + _ea_calc(current_ea2, current_op->reg2_sft); + _ea_read_src(current_ea2, current_op->reg2_sft); + } + else + { + wf_op("\tsrc = FETCH_BYTE;\n"); + wf_op("\tPC += 2;\n"); + current_cycle += 4; + } + wf_op("\tsrc = 1 << (src & %d);\n", current_sft_mask); + + // read + _ea_calc(current_ea, current_op->reg_sft); + _ea_read(current_ea, current_op->reg_sft); + // flag calculation + wf_op("\tCPU->flag_notZ = res & src;\n"); + // op + switch(op) + { + case 'c': + wf_op("\tres &= ~src;\n"); + break; + + case 'g': + wf_op("\tres ^= src;\n"); + break; + + case 's': + wf_op("\tres |= src;\n"); + break; + } + // write + if (op != ' ') + { + _ea_write(current_ea, current_op->reg_sft); + current_cycle += 4; + } + + terminate_op(4); +} + +static void GenBTSTn() +{ + GenBitsOp(' ', 0); +} + +static void GenBCHGn() +{ + GenBitsOp('g', 0); +} + +static void GenBCLRn() +{ + GenBitsOp('c', 0); +} + +static void GenBSETn() +{ + GenBitsOp('s', 0); +} + +static void GenBTST() +{ + GenBitsOp(' ', 1); +} + +static void GenBCHG() +{ + GenBitsOp('g', 1); +} + +static void GenBCLR() +{ + GenBitsOp('c', 1); +} + +static void GenBSET() +{ + GenBitsOp('s', 1); +} + +static void GenMOVEPWaD() +{ + // generate jump table & opcode declaration + current_ea = EA_D16A; + current_ea2 = EA_DREG; + start_all(GEN_ADR | GEN_RES | GEN_SRC); + + // read + set_current_size(SIZE_BYTE); + _ea_calc(current_ea, current_op->reg_sft); + mem_op("\tREAD_BYTE_F(adr + 0, res)\n"); + mem_op("\tREAD_BYTE_F(adr + 2, src)\n"); + // write + wf_op("\t*(u16*)(&CPU->D[(Opcode >> %d) & 7]) = (res << 8) | src;\n", current_op->reg2_sft); + + terminate_op(16); +} + +static void GenMOVEPLaD() +{ + // generate jump table & opcode declaration + current_ea = EA_D16A; + current_ea2 = EA_DREG; + start_all(GEN_ADR | GEN_RES | GEN_SRC); + + // read + set_current_size(SIZE_BYTE); + _ea_calc(EA_D16A, current_op->reg_sft); + mem_op("\tREAD_BYTE_F(adr, res)\n"); + wf_op("\tres <<= 24;\n"); + wf_op("\tadr += 2;\n"); + mem_op("\tREAD_BYTE_F(adr, src)\n"); + wf_op("\tres |= src << 16;\n"); + wf_op("\tadr += 2;\n"); + mem_op("\tREAD_BYTE_F(adr, src)\n"); + wf_op("\tres |= src << 8;\n"); + wf_op("\tadr += 2;\n"); + mem_op("\tREAD_BYTE_F(adr, src)\n"); + // write + wf_op("\tCPU->D[(Opcode >> %d) & 7] = res | src;\n", current_op->reg2_sft); + + terminate_op(24); +} + +static void GenMOVEPWDa() +{ + // generate jump table & opcode declaration + current_ea = EA_D16A; + current_ea2 = EA_DREG; + start_all(GEN_ADR | GEN_RES); + + // read + set_current_size(SIZE_LONG); + _ea_calc(current_ea2, current_op->reg2_sft); + _ea_read(current_ea2, current_op->reg2_sft); + // write + set_current_size(SIZE_BYTE); + _ea_calc(current_ea, current_op->reg_sft); + mem_op("\tWRITE_BYTE_F(adr + 0, res >> 8)\n"); + mem_op("\tWRITE_BYTE_F(adr + 2, res >> 0)\n"); + + terminate_op(16); +} + +static void GenMOVEPLDa() +{ + // generate jump table & opcode declaration + current_ea = EA_D16A; + current_ea2 = EA_DREG; + start_all(GEN_ADR | GEN_RES); + + // read + set_current_size(SIZE_LONG); + _ea_calc(current_ea2, current_op->reg2_sft); + _ea_read(current_ea2, current_op->reg2_sft); + // write + set_current_size(SIZE_BYTE); + _ea_calc(current_ea, current_op->reg_sft); + mem_op("\tWRITE_BYTE_F(adr, res >> 24)\n"); + wf_op("\tadr += 2;\n"); + mem_op("\tWRITE_BYTE_F(adr, res >> 16)\n"); + wf_op("\tadr += 2;\n"); + mem_op("\tWRITE_BYTE_F(adr, res >> 8)\n"); + wf_op("\tadr += 2;\n"); + mem_op("\tWRITE_BYTE_F(adr, res >> 0)\n"); + + terminate_op(24); +} + +static void GenMOVE(u32 size) +{ + set_current_size(size); + + // generate jump table & opcode declaration + if (((current_ea == EA_AREG) || (current_ea == EA_DREG) || (current_ea == EA_IMM)) && + ((current_ea2 == EA_AREG) || (current_ea2 == EA_DREG) || (current_ea2 == EA_IMM))) + start_all(GEN_RES); + else + start_all(GEN_ADR | GEN_RES); + + // read + _ea_calc(current_ea, current_op->reg_sft); + _ea_read(current_ea, current_op->reg_sft); + // flag calculation + set_logic_flag(); + if ((current_ea2 == EA_ADEC) || (current_ea2 == EA_ADEC7)) current_cycle -= 2; + // write + _ea_calc(current_ea2, current_op->reg2_sft); + _ea_write(current_ea2, current_op->reg2_sft); + + terminate_op(4); +} + +static void GenMOVEB() +{ + GenMOVE(SIZE_BYTE); +} + +static void GenMOVEW() +{ + GenMOVE(SIZE_WORD); +} + +static void GenMOVEL() +{ + GenMOVE(SIZE_LONG); +} + +static void GenMOVEA(u32 size) +{ + set_current_size(size); + + // generate jump table & opcode declaration + current_ea2 = EA_AREG; + if ((current_ea == EA_AREG) || (current_ea == EA_DREG) || (current_ea == EA_IMM)) + start_all(GEN_RES); + else + start_all(GEN_ADR | GEN_RES); + + // read + _ea_calc(current_ea, current_op->reg_sft); + _ea_read_sx(current_ea, current_op->reg_sft); + // write (dst = Ax) + _ea_calc(current_ea2, current_op->reg2_sft); + _ea_write(current_ea2, current_op->reg2_sft); + + terminate_op(4); +} + +static void GenMOVEAW() +{ + GenMOVEA(SIZE_WORD); +} + +static void GenMOVEAL() +{ + GenMOVEA(SIZE_LONG); +} + +static void GenMOVEQ() +{ + u32 base = get_current_opcode_base(); + + // generate jump table + current_ea = EA_DREG; + gen_opjumptable_ext(base, 0x00, 0xFF, 1, base); + + // generate label & declarations + start_op(base, GEN_RES); + + // read + set_current_size(SIZE_BYTE); + wf_op("\tres = (s32)(s8)Opcode;\n"); + // fast flag calculation for moveQ + wf_op("\tCPU->flag_C = CPU->flag_V = 0;\n"); + wf_op("\tCPU->flag_N = CPU->flag_notZ = res;\n"); + // write + set_current_size(SIZE_LONG); + _ea_calc(current_ea, current_op->reg_sft); + _ea_write(current_ea, current_op->reg_sft); + + terminate_op(4); +} + +static void GenSingle(char op) +{ + // generate jump table & opcode declaration + if ((current_ea == EA_AREG) || (current_ea == EA_DREG) || (current_ea == EA_IMM)) { + if (op == 'c') + start_all(GEN_RES); + else + start_all(GEN_RES | GEN_SRC); + } else { + if (op == 'c') + start_all(GEN_ADR | GEN_RES); + else + start_all(GEN_ADR | GEN_RES | GEN_SRC); + } + + if (current_size == SIZE_LONG) current_cycle = 6; + else current_cycle= 4; + if (is_ea_memory(current_ea)) current_cycle *= 2; + + // read + _ea_calc(current_ea, current_op->reg_sft); + if (op != 'c') _ea_read_src(current_ea, current_op->reg_sft); + // op + switch (op) + { + case 'x': // negx + wf_op("\tres = -src - ((CPU->flag_X >> 8) & 1);\n"); + break; + + case 'g': // neg + wf_op("\tres = -src;\n"); + break; + + case 'n': // not + wf_op("\tres = ~src;\n"); + break; + + case 'c': // clr + wf_op("\tres = 0;\n"); + break; + } + // flag calculation + switch (op) + { + case 'x': // negx + set_negx_flag(); + break; + + case 'g': // neg + set_neg_flag(); + break; + + case 'n': // not + set_logicl_flag(); + break; + + case 'c': // clr + wf_op("\tCPU->flag_N = CPU->flag_notZ = CPU->flag_V = CPU->flag_C = 0;\n"); + break; + } + // write + _ea_write(current_ea, current_op->reg_sft); + + terminate_op(0); +} + +static void GenCLR() +{ + GenSingle('c'); +} + +static void GenNEGX() +{ + GenSingle('x'); +} + +static void GenNEG() +{ + GenSingle('g'); +} + +static void GenNOT() +{ + GenSingle('n'); +} + +static void GenMOVESRa() +{ + // generate jump table & opcode declaration + if ((current_ea == EA_AREG) || (current_ea == EA_DREG) || (current_ea == EA_IMM)) + start_all(GEN_RES); + else + start_all(GEN_ADR | GEN_RES); + + // read + wf_op("\tres = GET_SR;\n"); + // write + set_current_size(SIZE_WORD); + if (is_ea_memory(current_ea)) current_cycle += 2; + _ea_calc(current_ea, current_op->reg_sft); + _ea_write(current_ea, current_op->reg_sft); + + terminate_op(6); +} + +static void GenMOVEaSR() +{ + // generate jump table & opcode declaration + if ((current_ea == EA_AREG) || (current_ea == EA_DREG) || (current_ea == EA_IMM)) + start_all(GEN_RES); + else + start_all(GEN_ADR | GEN_RES); + + wf_op("\tif (CPU->flag_S)\n"); + wf_op("\t{\n"); + // read + set_current_size(SIZE_WORD); + _ea_calc(current_ea, current_op->reg_sft); + _ea_read(current_ea, current_op->reg_sft); + wf_op("\t\tSET_SR(res)\n"); + wf_op("\t\tif (!CPU->flag_S)\n"); + wf_op("\t\t{\n"); + wf_op("\t\t\tres = CPU->A[7];\n"); + wf_op("\t\t\tCPU->A[7] = CPU->USP;\n"); + wf_op("\t\t\tCPU->USP = res;\n"); + wf_op("\t\t}\n"); + wf_op("\t}\n"); + wf_op("\telse\n"); + wf_op("\t{\n"); + gen_privilege_exception("\t\t"); + wf_op("\t}\n"); + + // force terminaison to check for interrupt + fterminate_op(12); +} + +static void GenMOVEaCCR() +{ + // generate jump table & opcode declaration + if ((current_ea == EA_AREG) || (current_ea == EA_DREG) || (current_ea == EA_IMM)) + start_all(GEN_RES); + else + start_all(GEN_ADR | GEN_RES); + + // read + set_current_size(SIZE_WORD); + _ea_calc(current_ea, current_op->reg_sft); + _ea_read(current_ea, current_op->reg_sft); + // write + wf_op("\tSET_CCR(res)\n"); + + terminate_op(12); +} + +static void GenMOVEAUSP() +{ + current_ea = EA_AREG; + + // generate jump table & opcode declaration + start_all(GEN_RES); + + wf_op("\tif (!CPU->flag_S)\n"); + wf_op("\t{\n"); + gen_privilege_exception("\t\t"); + quick_terminate_op(4); + wf_op("\t}\n"); + + // read + set_current_size(SIZE_LONG); + _ea_calc(current_ea, current_op->reg_sft); + _ea_read(current_ea, current_op->reg_sft); + // write + wf_op("\tCPU->USP = res;\n"); + + terminate_op(4); +} + +static void GenMOVEUSPA() +{ + current_ea = EA_AREG; + + // generate jump table & opcode declaration + start_all(GEN_RES); + + wf_op("\tif (!CPU->flag_S)\n"); + wf_op("\t{\n"); + gen_privilege_exception("\t\t"); + quick_terminate_op(4); + wf_op("\t}\n"); + + // read + wf_op("\tres = CPU->USP;\n"); + // write + set_current_size(SIZE_LONG); + _ea_calc(current_ea, current_op->reg_sft); + _ea_write(current_ea, current_op->reg_sft); + + terminate_op(4); +} + +static void GenPEA() +{ + set_current_size(SIZE_LONG); + // generate jump table & opcode declaration + if ((current_ea == EA_AREG) || (current_ea == EA_DREG) || (current_ea == EA_IMM)) + start_all(0); + else + start_all(GEN_ADR); + + _ea_calc_free(current_ea, current_op->reg_sft); + mem_op("\tPUSH_32_F(adr)\n"); + + terminate_op(lea_pea_cycle_table[current_ea] + 12); +} + +static void GenSWAP() +{ + current_ea = EA_DREG; + set_current_size(SIZE_LONG); + // generate jump table & opcode declaration + start_all(GEN_RES); + + // read + _ea_calc(current_ea, current_op->reg_sft); + _ea_read(current_ea, current_op->reg_sft); + // op + wf_op("\tres = (res >> 16) | (res << 16);\n"); + // flag calculation + set_logic_flag(); + // write + _ea_write(current_ea, current_op->reg_sft); + + terminate_op(4); +} + +static void GenMOVEMaR() +{ + // generate jump table & opcode declaration + start_all(GEN_ALL); + + // get register mask + wf_op("\tres = FETCH_WORD;\n"); + wf_op("\tPC += 2;\n"); + // get adr + if (current_ea == EA_AINC) wf_op("\tadr = CPU->A[(Opcode >> %d) & 7];\n", current_op->reg_sft); + else if (current_ea == EA_AINC7) wf_op("\tadr = CPU->A[7];\n"); + else _ea_calc(current_ea, current_op->reg_sft); + wf_op("\tsrc = (pointer)(&CPU->D[0]);\n"); + + wf_op("\tdst = adr;\n"); + do_pre_io(); + + wf_op("\tdo\n"); + wf_op("\t{\n"); + wf_op("\t\tif (res & 1)\n"); + wf_op("\t\t{\n"); + + if (current_size == SIZE_WORD) + { + wf_op("\t\t\tREADSX_WORD_F(adr, *(s32*)src)\n"); + wf_op("\t\t\tadr += 2;\n"); + } + else + { + wf_op("\t\t\tREAD_LONG_F(adr, *(u32*)src)\n"); + wf_op("\t\t\tadr += 4;\n"); + } + wf_op("\t\t}\n"); + wf_op("\t\tsrc += 4;\n"); + wf_op("\t} while (res >>= 1);\n"); + + if (current_ea == EA_AINC) wf_op("\tCPU->A[(Opcode >> %d) & 7] = adr;\n", current_op->reg_sft); + else if (current_ea == EA_AINC7) wf_op("\tCPU->A[7] = adr;\n"); + adds_CCnt("(adr - dst) * 2"); + + terminate_op(movem_cycle_table[current_ea] + 12); +} + +static void GenMOVEMRa() +{ + // generate jump table & opcode declaration + start_all(GEN_ALL); + + // get register mask + wf_op("\tres = FETCH_WORD;\n"); + wf_op("\tPC += 2;\n"); + // get adr + if (current_ea == EA_ADEC) wf_op("\tadr = CPU->A[(Opcode >> %d) & 7];\n", current_op->reg_sft); + else if (current_ea == EA_ADEC7) wf_op("\tadr = CPU->A[7];\n"); + else _ea_calc(current_ea, current_op->reg_sft); + if ((current_ea == EA_ADEC) || (current_ea == EA_ADEC7)) wf_op("\tsrc = (pointer)(&CPU->A[7]);\n"); + else wf_op("\tsrc = (pointer)(&CPU->D[0]);\n"); + + wf_op("\tdst = adr;\n"); + do_pre_io(); + + wf_op("\tdo\n"); + wf_op("\t{\n"); + wf_op("\t\tif (res & 1)\n"); + wf_op("\t\t{\n"); + + if (current_size == SIZE_WORD) + { + if ((current_ea == EA_ADEC) || (current_ea == EA_ADEC7)) wf_op("\t\t\tadr -= 2;\n"); + wf_op("\t\t\tWRITE_WORD_F(adr, *(u16*)src)\n"); + if (!((current_ea == EA_ADEC) || (current_ea == EA_ADEC7))) wf_op("\t\t\tadr += 2;\n"); + } + else + { + if ((current_ea == EA_ADEC) || (current_ea == EA_ADEC7)) + { + wf_op("\t\t\tadr -= 4;\n"); + wf_op("\t\t\tWRITE_LONG_DEC_F(adr, *(u32*)src)\n"); + } + else + { + wf_op("\t\t\tWRITE_LONG_F(adr, *(u32*)src)\n"); + wf_op("\t\t\tadr += 4;\n"); + } + } + wf_op("\t\t}\n"); + if ((current_ea == EA_ADEC) || (current_ea == EA_ADEC7)) wf_op("\t\tsrc -= 4;\n"); + else wf_op("\t\tsrc += 4;\n"); + wf_op("\t} while (res >>= 1);\n"); + + if (current_ea == EA_ADEC) wf_op("\tCPU->A[(Opcode >> %d) & 7] = adr;\n", current_op->reg_sft); + else if (current_ea == EA_ADEC7) wf_op("\tCPU->A[7] = adr;\n"); + if ((current_ea == EA_ADEC) || (current_ea == EA_ADEC7)) adds_CCnt("(dst - adr) * 2"); + else adds_CCnt("(adr - dst) * 2"); + + terminate_op(movem_cycle_table[current_ea] + 8); +} + +static void GenEXT() +{ + current_ea = EA_DREG; + // generate jump table & opcode declaration + start_all(GEN_RES); + + // read + set_current_size(current_size - 1); + _ea_calc(current_ea, current_op->reg_sft); + _ea_read_sx(current_ea, current_op->reg_sft); + // flag calculation + set_logic_flag(); + // write + set_current_size(current_size + 1); + _ea_write(current_ea, current_op->reg_sft); + + terminate_op(4); +} + +static void GenTST() +{ + // generate jump table & opcode declaration + if ((current_ea == EA_AREG) || (current_ea == EA_DREG) || (current_ea == EA_IMM)) + start_all(GEN_RES); + else + start_all(GEN_ADR | GEN_RES); + + // read + _ea_calc(current_ea, current_op->reg_sft); + _ea_read(current_ea, current_op->reg_sft); + // flag calculation + set_logic_flag(); + + terminate_op(4); +} + +static void GenTAS() +{ + set_current_size(SIZE_BYTE); + + if (is_ea_memory(current_ea)) current_cycle += 6; + + // generate jump table & opcode declaration + if ((current_ea == EA_AREG) || (current_ea == EA_DREG) || (current_ea == EA_IMM)) + start_all(GEN_RES); + else + start_all(GEN_ADR | GEN_RES); + + // read + _ea_calc(current_ea, current_op->reg_sft); + _ea_read(current_ea, current_op->reg_sft); + // flag calculation + set_logic_flag(); +#ifndef C68K_TAS_CAN_SET_MEMORY + if (current_ea < EA_AIND) + { +#endif + // flag calculation + wf_op("\tres |= 0x80;\n"); + // write + _ea_write(current_ea, current_op->reg_sft); +#ifndef C68K_TAS_CAN_SET_MEMORY + } +#endif + + terminate_op(4); +} + +static void GenTRAP() +{ + u32 base; + + base = get_current_opcode_base(); + + // generate jump table + gen_opjumptable_ext(base, (0 << 0), (15 << 0), (1 << 0), base); + + // generate label & declarations + start_op(base, GEN_RES); + + gen_exception("\t", "C68K_TRAP_BASE_EX + (Opcode & 0xF)"); + + terminate_op(4); +} + +static void GenTRAPV() +{ + // generate label & declarations + start_all(GEN_RES); + + wf_op("\tif %s\n", get_cond_as_cond(COND_VS, 0)); + wf_op("\t{\n"); + gen_exception("\t\t", "C68K_TRAPV_EX"); + wf_op("\t}\n"); + + terminate_op(4); +} + +static void GenLINK() +{ + current_ea = EA_AREG; + set_current_size(SIZE_LONG); + // generate jump table & opcode declaration + start_all(GEN_RES); + + // read + _ea_calc(current_ea, current_op->reg_sft); + _ea_read(current_ea, current_op->reg_sft); + // push + mem_op("\tPUSH_32_F(res)\n"); + wf_op("\tres = CPU->A[7];\n"); + // write + _ea_write(current_ea, current_op->reg_sft); + // update SP + wf_op("\tCPU->A[7] += (s32)(s16)FETCH_WORD;\n"); + wf_op("\tPC += 2;\n"); + + terminate_op(16); +} + +static void GenLINKA7() +{ + current_ea = EA_AREG; + set_current_size(SIZE_LONG); + // generate jump table & opcode declaration + start_all(0); + + // push A7 + wf_op("\tCPU->A[7] -= 4;\n"); + mem_op("\tWRITE_LONG_DEC_F(CPU->A[7], CPU->A[7])\n"); + // update A7 + wf_op("\tCPU->A[7] += (s32)(s16)FETCH_WORD;\n"); + wf_op("\tPC += 2;\n"); + + terminate_op(16); +} + +static void GenULNK() +{ + current_ea = EA_AREG; + set_current_size(SIZE_LONG); + // generate jump table & opcode declaration + start_all(GEN_RES | GEN_SRC); + + // read + _ea_calc(current_ea, current_op->reg_sft); + _ea_read_src(current_ea, current_op->reg_sft); + // pop + wf_op("\tCPU->A[7] = src + 4;\n"); + mem_op("\tREAD_LONG_F(src, res)\n"); + // write + _ea_write(current_ea, current_op->reg_sft); + + terminate_op(12); +} + +static void GenULNKA7() +{ + current_ea = EA_AREG; + set_current_size(SIZE_LONG); + // generate jump table & opcode declaration + start_all(0); + + mem_op("\tREAD_LONG_F(CPU->A[7], CPU->A[7])\n"); + + terminate_op(12); +} + +static void GenRESET() +{ + // generate jump table & opcode declaration + start_all(GEN_RES); + + wf_op("\tif (!CPU->flag_S)\n"); + wf_op("\t{\n"); + gen_privilege_exception("\t\t"); + quick_terminate_op(4); + wf_op("\t}\n"); + + // Reset callback function + mem_op("\tCPU->Reset_CallBack(CPU->Callback_Param);\n"); + + terminate_op(132); +} + +static void GenLEA() +{ + current_ea2 = EA_AREG; + set_current_size(SIZE_LONG); + // generate jump table & opcode declaration + start_all(GEN_ADR | GEN_RES); + + _ea_calc_free(current_ea, current_op->reg_sft); + wf_op("\tres = adr;\n"); + current_cycle = lea_pea_cycle_table[current_ea]; + _ea_calc(current_ea2, current_op->reg2_sft); + _ea_write(current_ea2, current_op->reg2_sft); + + terminate_op(4); +} + +static void GenNOP() +{ + start_all(0); + terminate_op(4); +} + +static void GenILLEGAL() +{ + start_all(GEN_RES); + + gen_exception("\t\t", "C68K_ILLEGAL_INSTRUCTION_EX"); + + terminate_op(4); +} + +static void GenCHK() +{ + current_ea2 = EA_DREG; + set_current_size(SIZE_WORD); + // generate jump table & opcode declaration + if ((current_ea == EA_AREG) || (current_ea == EA_DREG) || (current_ea == EA_IMM)) + start_all(GEN_RES | GEN_SRC); + else + start_all(GEN_ADR | GEN_RES | GEN_SRC); + + // read Src + _ea_calc(current_ea, current_op->reg_sft); + _ea_read_src(current_ea, current_op->reg_sft); + // read Dx + _ea_calc(current_ea2, current_op->reg2_sft); + _ea_read(current_ea2, current_op->reg2_sft); + + wf_op("\tif (((s32)res < 0) || (res > src))\n"); + wf_op("\t{\n"); + wf_op("\t\tCPU->flag_N = res >> %d;\n", current_sft_mask - C68K_SR_N_SFT); + gen_exception("\t\t", "C68K_CHK_EX"); + wf_op("\t}\n"); + + terminate_op(10); +} + +static void GenSTOP() +{ + // generate jump table & opcode declaration + start_all(GEN_RES); + + wf_op("\tif (!CPU->flag_S)\n"); + wf_op("\t{\n"); + wf_op("\t\tPC += 2;\n"); + gen_privilege_exception("\t\t"); + quick_terminate_op(4); + wf_op("\t}\n"); + + // read & set SR + wf_op("\tres = FETCH_WORD & C68K_SR_MASK;\n"); + wf_op("\tPC += 2;\n"); + wf_op("\tSET_SR(res)\n"); + + // if S flag not set --> we swap stack pointer + wf_op("\tif (!CPU->flag_S)\n"); + wf_op("\t{\n"); + wf_op("\t\tres = CPU->A[7];\n"); + wf_op("\t\tCPU->A[7] = CPU->USP;\n"); + wf_op("\t\tCPU->USP = res;\n"); + wf_op("\t}\n"); + + wf_op("\tCPU->Status |= C68K_HALTED;\n"); + wf_op("\tCCnt = 0;\n"); + + // force end execution + fterminate_op(4); +} + +static void GenRTE() +{ + start_all(GEN_RES); + + wf_op("\tif (!CPU->flag_S)\n"); + wf_op("\t{\n"); + gen_privilege_exception("\t\t"); + quick_terminate_op(4); + wf_op("\t}\n"); + + // restore SR and PC + mem_op("\tPOP_16_F(res)\n"); + wf_op("\tSET_SR(res)\n"); + mem_op("\tPOP_32_F(res)\n"); + wf_op("\tSET_PC(res)\n"); + + // if S flag not set --> we swap stack pointer + wf_op("\tif (!CPU->flag_S)\n"); + wf_op("\t{\n"); + wf_op("\t\tres = CPU->A[7];\n"); + wf_op("\t\tCPU->A[7] = CPU->USP;\n"); + wf_op("\t\tCPU->USP = res;\n"); + wf_op("\t}\n"); + + // check for interrupt + fterminate_op(20); +} + +static void GenRTS() +{ + start_all(GEN_RES); + + mem_op("\tPOP_32_F(res)\n"); + wf_op("\tSET_PC(res)\n"); + + terminate_op(16); +} + +static void GenRTR() +{ + start_all(GEN_RES); + + mem_op("\tPOP_16_F(res)\n"); + wf_op("\tSET_CCR(res)\n"); + mem_op("\tPOP_32_F(res)\n"); + wf_op("\tSET_PC(res)\n"); + + terminate_op(20); +} + +static void GenJSR() +{ + start_all(GEN_ADR); + + // get adr + _ea_calc_free(current_ea, current_op->reg_sft); + mem_op("\tPUSH_32_F(PC - CPU->BasePC)\n"); + wf_op("\tSET_PC(adr)\n"); + + terminate_op(jmp_jsr_cycle_table[current_ea] + 12); +} + +static void GenJMP() +{ + start_all(GEN_ADR); + + // get adr + _ea_calc_free(current_ea, current_op->reg_sft); + wf_op("\tSET_PC(adr)\n"); + + terminate_op(jmp_jsr_cycle_table[current_ea] + 4); +} + +static void GenSTCC() +{ + u32 base, cond; + + base = get_current_opcode_base(); + + for(cond = 0; cond < 0x10; cond++) + { + // generate jump table + gen_opjumptable(base + (cond << 8)); + // generate label & declarations + if ((current_ea == EA_AREG) || (current_ea == EA_DREG) || (current_ea == EA_IMM)) + start_op(base + (cond << 8), GEN_RES); + else + start_op(base + (cond << 8), GEN_ADR | GEN_RES); + + set_current_size(SIZE_BYTE); + + if (is_ea_memory(current_ea)) current_cycle += 4; + + // op + _ea_calc(current_ea, current_op->reg_sft); + if ((cond != COND_TR) && (cond != COND_FA)) + { + wf_op("\tif %s\n", get_cond_as_cond(cond, 0)); + wf_op("\t{\n"); + } + if (cond != COND_FA) + { + wf_op("\tres = 0xFF;\n"); + // write + _ea_write(current_ea, current_op->reg_sft); + if (!is_ea_memory(current_ea)) quick_terminate_op(6); + else quick_terminate_op(4); + } + if ((cond != COND_TR) && (cond != COND_FA)) + { + wf_op("\t}\n"); + } + if (cond != COND_TR) + { + wf_op("\tres = 0;\n"); + // write + _ea_write(current_ea, current_op->reg_sft); + quick_terminate_op(4); + } + + wf_op("}\n"); + } +} + +static void GenDBCC() +{ + u32 base, cond; + + base = get_current_opcode_base(); + + current_ea = EA_DREG; + set_current_size(SIZE_WORD); + + for(cond = 0; cond < 0x10; cond++) + { + // generate jump table + gen_opjumptable(base + (cond << 8)); + // generate label & declarations + start_op(base + (cond << 8), cond==COND_TR ? 0 : GEN_RES); + + if (cond != COND_TR) + { + if (cond != COND_FA) + { + wf_op("\tif %s\n", get_cond_as_cond(cond, 1)); + wf_op("\t{\n"); + } + + // read Dx + _ea_calc(current_ea, current_op->reg_sft); + _ea_read(current_ea, current_op->reg_sft); + // dec Dx + wf_op("\tres--;\n"); + // write Dx + _ea_write(current_ea, current_op->reg_sft); + wf_op("\tif ((s32)res != -1)\n"); + wf_op("\t{\n"); + wf_op("\t\tPC += (s32)(s16)FETCH_WORD;\n"); + // unbase PC + wf_op("\t\tPC -= CPU->BasePC;\n"); + // rebase PC + wf_op("\t\tSET_PC(PC);\n"); + quick_terminate_op(10); + wf_op("\t}\n"); + + if (cond != COND_FA) + { + wf_op("\t}\n"); + wf_op("\telse\n"); + wf_op("\t{\n"); + wf_op("\t\tPC += 2;\n"); + quick_terminate_op(12); + wf_op("\t}\n"); + } + } + + wf_op("\tPC += 2;\n"); + + if (cond == COND_TR) terminate_op(12); + else terminate_op(14); + } +} + +static void GenBCC() +{ + u32 base, cond; + + base = get_current_opcode_base(); + + for(cond = 2; cond < 0x10; cond++) + { + // generate jump table + gen_opjumptable_ext(base + (cond << 8), 0x01, 0xFF, 1, base + (cond << 8) + 0x01); + // generate label & declarations + start_op(base + (cond << 8) + 0x01, 0); + + // op + wf_op("\tif %s\n", get_cond_as_cond(cond, 0)); + wf_op("\t{\n"); + wf_op("\t\tPC += (s32)(s8)Opcode;\n"); // no rebase needed for 8 bits deplacement + add_CCnt(2); + wf_op("\t}\n"); + + terminate_op(8); + } +} + +static void GenBCC16() +{ + u32 base, cond; + + base = get_current_opcode_base(); + + for(cond = 2; cond < 0x10; cond++) + { + // generate jump table + gen_opjumptable(base + (cond << 8)); + // generate label & declarations + start_op(base + (cond << 8), 0); + + // op + wf_op("\tif %s\n", get_cond_as_cond(cond, 0)); + wf_op("\t{\n"); + wf_op("\t\tPC += (s32)(s16)FETCH_WORD;\n"); + // unbase PC + wf_op("\t\tPC -= CPU->BasePC;\n"); + // rebase PC + wf_op("\t\tSET_PC(PC);\n"); + quick_terminate_op(10); + wf_op("\t}\n"); + + wf_op("\tPC += 2;\n"); + + terminate_op(12); + } +} + +static void GenBRA() +{ + u32 base = get_current_opcode_base(); + + // generate jump table + gen_opjumptable_ext(base, 0x01, 0xFF, 1, base + 0x01); + // generate label & declarations + start_op(base + 0x01, 0); + + wf_op("\tPC += (s32)(s8)Opcode;\n"); // no rebase needed for 8 bits deplacement + + terminate_op(10); +} + +static void GenBRA16() +{ + u32 base = get_current_opcode_base(); + + // generate jump table + gen_opjumptable(base + 0x00); + // generate label & declarations + start_op(base + 0x00, 0); + + wf_op("\tPC += (s32)(s16)FETCH_WORD;\n"); + // unbase PC + wf_op("\tPC -= CPU->BasePC;\n"); + // rebase PC + wf_op("\tSET_PC(PC);\n"); + + terminate_op(10); +} + +static void GenBSR() +{ + u32 base = get_current_opcode_base(); + + // generate jump table + gen_opjumptable_ext(base, 0x01, 0xFF, 1, base + 0x01); + // generate label & declarations + start_op(base + 0x01, 0); + + mem_op("\tPUSH_32_F(PC - CPU->BasePC)\n"); + wf_op("\tPC += (s32)(s8)Opcode;\n"); // no rebase needed for 8 bits deplacement + + terminate_op(18); +} + +static void GenBSR16() +{ + u32 base = get_current_opcode_base(); + + // generate jump table + gen_opjumptable(base + 0x00); + // generate label & declarations + start_op(base + 0x00, GEN_RES); + + wf_op("\tres = (s32)(s16)FETCH_WORD;\n"); + // unbase PC + wf_op("\tPC -= CPU->BasePC;\n"); + mem_op("\tPUSH_32_F(PC + 2)\n"); + wf_op("\tPC += (s32) res;\n"); + // rebase PC for 16 bits deplacement + wf_op("\tSET_PC(PC);\n"); + + terminate_op(18); +} + +static void GenArithQ(char op) +{ + u32 base; + + if ((current_ea == EA_AREG) && (current_size == SIZE_BYTE)) return; + + base = get_current_opcode_base(); + + // generate jump table + gen_opjumptable_ext(base, (0 << 9), (7 << 9), (1 << 9), base); + + // generate label & declarations + if ((current_ea == EA_AREG) || (current_ea == EA_DREG) || (current_ea == EA_IMM)) + start_op(base, GEN_DST | GEN_RES | GEN_SRC); + else + start_op(base, GEN_ALL); + + if (current_ea == EA_AREG) set_current_size(SIZE_LONG); + + if (is_ea_memory(current_ea)) current_cycle += 4; + if (current_size == SIZE_LONG) current_cycle += 4; + + // read src + wf_op("\tsrc = (((Opcode >> 9) - 1) & 7) + 1;\n"); + // read dst + _ea_calc(current_ea, current_op->reg_sft); + _ea_read_dst(current_ea, current_op->reg_sft); + // op + wf_op("\tres = dst %c src;\n", op); + // flag calculation + if (current_ea != EA_AREG) + { + if (op == '+') set_add_flag(); + else set_sub_flag(); + } + // write dst + _ea_write(current_ea, current_op->reg_sft); + + terminate_op(4); +} + +static void GenADDQ() +{ + GenArithQ('+'); +} + +static void GenSUBQ() +{ + GenArithQ('-'); +} + +static void GenLogicaD(char op) +{ + // generate jump table & opcode declaration + current_ea2 = EA_DREG; + if ((current_ea == EA_AREG) || (current_ea == EA_DREG) || (current_ea == EA_IMM)) + start_all(GEN_RES | GEN_SRC); + else + start_all(GEN_ADR | GEN_RES | GEN_SRC); + + if (current_size == SIZE_LONG) + { + if (!is_ea_memory(current_ea)) current_cycle += 2; + else current_cycle += 4; + } + + // read src + _ea_calc(current_ea, current_op->reg_sft); + _ea_read_src(current_ea, current_op->reg_sft); + // read dst (Dx) + _ea_calc(current_ea2, current_op->reg2_sft); + _ea_read(current_ea2, current_op->reg2_sft); + // op + wf_op("\tres %c= src;\n", op); + // flag calculation + set_logic_flag(); + // write dst (Dx) + _ea_write(current_ea2, current_op->reg2_sft); + + terminate_op(4); +} + +static void GenLogicDa(char op) +{ + // generate jump table & opcode declaration + current_ea2 = EA_DREG; + if ((current_ea == EA_AREG) || (current_ea == EA_DREG) || (current_ea == EA_IMM)) + start_all(GEN_RES | GEN_SRC); + else + start_all(GEN_ADR | GEN_RES | GEN_SRC); + + if (current_size == SIZE_LONG) current_cycle += 4; + + // read src (Dx) + _ea_calc(current_ea2, current_op->reg2_sft); + _ea_read_src(current_ea2, current_op->reg2_sft); + // read dst + _ea_calc(current_ea, current_op->reg_sft); + _ea_read(current_ea, current_op->reg_sft); + // op + wf_op("\tres %c= src;\n", op); + // flag calculation + set_logic_flag(); + // write dst + _ea_write(current_ea, current_op->reg_sft); + + if (current_ea == EA_DREG) terminate_op(4); + else terminate_op(8); +} + +static void GenANDaD() +{ + GenLogicaD('&'); +} + +static void GenANDDa() +{ + GenLogicDa('&'); +} + +static void GenORaD() +{ + GenLogicaD('|'); +} + +static void GenORDa() +{ + GenLogicDa('|'); +} + +static void GenEORDa() +{ + GenLogicDa('^'); +} + +static void GenNBCD() +{ + set_current_size(SIZE_BYTE); + + // generate jump table & opcode declaration + if ((current_ea == EA_AREG) || (current_ea == EA_DREG) || (current_ea == EA_IMM)) + start_all(GEN_RES); + else + start_all(GEN_ADR | GEN_RES); + + if (is_ea_memory(current_ea)) current_cycle += 2; + + // read + _ea_calc(current_ea, current_op->reg_sft); + _ea_read(current_ea, current_op->reg_sft); + + // op + wf_op("\tres = 0x9a - res - ((CPU->flag_X >> C68K_SR_X_SFT) & 1);\n"); + wf_op("\n"); + wf_op("\tif (res != 0x9a)\n"); + wf_op("\t{\n"); + wf_op("\t\tif ((res & 0x0f) == 0xa) res = (res & 0xf0) + 0x10;\n"); + wf_op("\t\tres &= 0xFF;\n"); + + // write + _ea_write(current_ea, current_op->reg_sft); + + // flag calculation + wf_op("\t\tCPU->flag_notZ |= res;\n"); + wf_op("\t\tCPU->flag_X = CPU->flag_C = C68K_SR_C;\n"); + + wf_op("\t}\n"); + wf_op("\telse CPU->flag_X = CPU->flag_C = 0;\n"); + wf_op("\tCPU->flag_N = res;\n"); + + terminate_op(6); +} + +static void GenBCD(char op) +{ + // op + wf_op("\tres = (dst & 0xF) %c (src & 0xF) %c ((CPU->flag_X >> C68K_SR_X_SFT) & 1);\n", op, op); + wf_op("\tif (res > 9) res %c= 6;\n", op); + wf_op("\tres += (dst & 0xF0) %c (src & 0xF0);\n", op, op); + + // flag calculation + wf_op("\tif (res > 0x99)\n"); + wf_op("\t{\n"); + switch (op) + { + case '+': + wf_op("\t\tres -= 0xA0;\n"); + break; + + case '-': + wf_op("\t\tres += 0xA0;\n"); + break; + } + wf_op("\t\tCPU->flag_X = CPU->flag_C = C68K_SR_C;\n"); + wf_op("\t}\n"); + wf_op("\telse CPU->flag_X = CPU->flag_C = 0;\n"); + wf_op("\tCPU->flag_notZ |= res & 0xFF;\n"); + wf_op("\tCPU->flag_N = res;\n"); +} + +static void GenxBCD(char op) +{ + set_current_size(SIZE_BYTE); + + // generate jump table & opcode declaration + current_ea = EA_DREG; + current_ea2 = EA_DREG; + start_all(GEN_DST | GEN_RES | GEN_SRC); + + // read src (Dx) + _ea_calc(current_ea, current_op->reg_sft); + _ea_read_src(current_ea, current_op->reg_sft); + // read dst (Dx) + _ea_calc(current_ea2, current_op->reg2_sft); + _ea_read_dst(current_ea2, current_op->reg2_sft); + + // op & flag calculation + GenBCD(op); + + // write dst (Dx) + _ea_write(current_ea2, current_op->reg2_sft); + + terminate_op(6); +} + +static void GenxBCDM(char op) +{ + set_current_size(SIZE_BYTE); + + // generate jump table & opcode declaration + current_ea = EA_ADEC; + current_ea2 = EA_ADEC; + start_all(GEN_ALL); + + // read src (ADEC) + _ea_calc(current_ea, current_op->reg_sft); + _ea_read_src(current_ea, current_op->reg_sft); + // read dst (ADEC) + _ea_calc(current_ea2, current_op->reg2_sft); + _ea_read_dst(current_ea2, current_op->reg2_sft); + + // op & flag calculation + GenBCD(op); + + // write dst (ADEC) + _ea_write(current_ea2, current_op->reg2_sft); + + terminate_op(6); +} + +static void GenxBCD7M(char op) +{ + set_current_size(SIZE_BYTE); + + // generate jump table & opcode declaration + current_ea = EA_ADEC7; + current_ea2 = EA_ADEC; + start_all(GEN_ALL); + + // read src (ADEC7) + _ea_calc(current_ea, 0); + _ea_read_src(current_ea, 0); + // read dst (ADEC) + _ea_calc(current_ea2, current_op->reg2_sft); + _ea_read_dst(current_ea2, current_op->reg2_sft); + + // op & flag calculation + GenBCD(op); + + // write dst (ADEC) + _ea_write(current_ea2, current_op->reg2_sft); + + terminate_op(6); +} + +static void GenxBCDM7(char op) +{ + set_current_size(SIZE_BYTE); + + // generate jump table & opcode declaration + current_ea = EA_ADEC; + current_ea2 = EA_ADEC7; + start_all(GEN_ALL); + + // read src (ADEC) + _ea_calc(current_ea, current_op->reg_sft); + _ea_read_src(current_ea, current_op->reg_sft); + // read dst (ADEC7) + _ea_calc(current_ea2, 0); + _ea_read_dst(current_ea2, 0); + + // op & flag calculation + GenBCD(op); + + // write dst (ADEC7) + _ea_write(current_ea2, 0); + + terminate_op(6); +} + +static void GenxBCD7M7(char op) +{ + set_current_size(SIZE_BYTE); + + // generate jump table & opcode declaration + current_ea = EA_ADEC7; + current_ea2 = EA_ADEC7; + start_all(GEN_ALL); + + // read src (ADEC7) + _ea_calc(current_ea, 0); + _ea_read_src(current_ea, 0); + // read dst (ADEC7) + _ea_calc(current_ea2, 0); + _ea_read_dst(current_ea2, 0); + + // op & flag calculation + GenBCD(op); + + // write dst (ADEC7) + _ea_write(current_ea2, 0); + + terminate_op(6); +} + +static void GenABCD() +{ + GenxBCD('+'); +} + +static void GenABCDM() +{ + GenxBCDM('+'); +} + +static void GenABCD7M() +{ + GenxBCD7M('+'); +} + +static void GenABCDM7() +{ + GenxBCDM7('+'); +} + +static void GenABCD7M7() +{ + GenxBCD7M7('+'); +} + +static void GenSBCD() +{ + GenxBCD('-'); +} + +static void GenSBCDM() +{ + GenxBCDM('-'); +} + +static void GenSBCD7M() +{ + GenxBCD7M('-'); +} + +static void GenSBCDM7() +{ + GenxBCDM7('-'); +} + +static void GenSBCD7M7() +{ + GenxBCD7M7('-'); +} + +static void GenDIVU() +{ + // generate jump table & opcode declaration + current_ea2 = EA_DREG; + if ((current_ea == EA_AREG) || (current_ea == EA_DREG) || (current_ea == EA_IMM)) + start_all(GEN_DST | GEN_RES | GEN_SRC); + else + start_all(GEN_ALL); + + set_current_size(SIZE_WORD); + + // read src + _ea_calc(current_ea, current_op->reg_sft); + _ea_read_src(current_ea, current_op->reg_sft); + + // division by zero + wf_op("\tif (src == 0)\n"); + wf_op("\t{\n"); + gen_exception("\t\t", "C68K_ZERO_DIVIDE_EX"); + quick_terminate_op(10); + wf_op("\t}\n"); + + set_current_size(SIZE_LONG); + + // read dst (Dx) + _ea_calc(current_ea2, current_op->reg2_sft); + _ea_read_dst(current_ea2, current_op->reg2_sft); + + wf_op("\t{\n"); + wf_op("\t\tu32 q, r;\n"); + wf_op("\n"); + wf_op("\t\tq = dst / src;\n"); + wf_op("\t\tr = dst %% src;\n"); + wf_op("\n"); + + wf_op("\t\tif (q & 0xFFFF0000)\n"); + wf_op("\t\t{\n"); + // overflow occured + wf_op("\t\t\tCPU->flag_V = C68K_SR_V;\n"); + quick_terminate_op(70); + wf_op("\t\t}\n"); + + // quotient size = word + set_current_size(SIZE_WORD); + + wf_op("\t\tq &= 0x%.8X;\n", current_bits_mask); + wf_op("\t\tCPU->flag_notZ = q;\n"); + wf_op("\t\tCPU->flag_N = q >> %d;\n", current_sft_mask - C68K_SR_N_SFT); + wf_op("\t\tCPU->flag_V = CPU->flag_C = 0;\n"); + + wf_op("\t\tres = q | (r << 16);\n"); + + set_current_size(SIZE_LONG); + + // write dst (Dx) + _ea_write(current_ea2, current_op->reg2_sft); + wf_op("\t}\n"); + + // max cycle = 140 + terminate_op(140 - 50); +} + +static void GenDIVS() +{ + // generate jump table & opcode declaration + current_ea2 = EA_DREG; + if ((current_ea == EA_AREG) || (current_ea == EA_DREG) || (current_ea == EA_IMM)) + start_all(GEN_DST | GEN_RES | GEN_SRC); + else + start_all(GEN_ALL); + + set_current_size(SIZE_WORD); + + // read src + _ea_calc(current_ea, current_op->reg_sft); + _ea_read_src_sx(current_ea, current_op->reg_sft); + + // division by zero + wf_op("\tif (src == 0)\n"); + wf_op("\t{\n"); + gen_exception("\t\t", "C68K_ZERO_DIVIDE_EX"); + quick_terminate_op(10); + wf_op("\t}\n"); + + set_current_size(SIZE_LONG); + + // read dst (Dx) + _ea_calc(current_ea2, current_op->reg2_sft); + _ea_read_dst(current_ea2, current_op->reg2_sft); + + // division by zero + wf_op("\tif ((dst == 0x80000000) && (src == -1))\n"); + wf_op("\t{\n"); + wf_op("\t\tCPU->flag_notZ = CPU->flag_N = 0;\n"); + wf_op("\t\tCPU->flag_V = CPU->flag_C = 0;\n"); + wf_op("\t\tres = 0;\n"); + + // write dst (Dx) + _ea_write(current_ea2, current_op->reg2_sft); + + quick_terminate_op(50); + wf_op("\t}\n"); + + wf_op("\t{\n"); + wf_op("\t\ts32 q, r;\n"); + wf_op("\n"); + wf_op("\t\tq = (s32)dst / (s32)src;\n"); + wf_op("\t\tr = (s32)dst %% (s32)src;\n"); + wf_op("\n"); + + wf_op("\t\tif ((q > 0x7FFF) || (q < -0x8000))\n"); + wf_op("\t\t{\n"); + // overflow occured + wf_op("\t\t\tCPU->flag_V = C68K_SR_V;\n"); + quick_terminate_op(80); + wf_op("\t\t}\n"); + + // quotient size = word + set_current_size(SIZE_WORD); + + wf_op("\t\tq &= 0x%.8X;\n", current_bits_mask); + wf_op("\t\tCPU->flag_notZ = q;\n"); + wf_op("\t\tCPU->flag_N = q >> %d;\n", current_sft_mask - C68K_SR_N_SFT); + wf_op("\t\tCPU->flag_V = CPU->flag_C = 0;\n"); + + wf_op("\t\tres = q | (r << 16);\n"); + + set_current_size(SIZE_LONG); + + // write dst (Dx) + _ea_write(current_ea2, current_op->reg2_sft); + wf_op("\t}\n"); + + // max cycle = 158 + terminate_op(158 - 50); +} + +static void GenMULU() +{ + // generate jump table & opcode declaration + current_ea2 = EA_DREG; + if ((current_ea == EA_AREG) || (current_ea == EA_DREG) || (current_ea == EA_IMM)) + start_all(GEN_RES | GEN_SRC); + else + start_all(GEN_ADR | GEN_RES | GEN_SRC); + + set_current_size(SIZE_WORD); + + // read src + _ea_calc(current_ea, current_op->reg_sft); + _ea_read_src(current_ea, current_op->reg_sft); + // read dst (Dx) + _ea_calc(current_ea2, current_op->reg2_sft); + _ea_read(current_ea2, current_op->reg2_sft); + + set_current_size(SIZE_LONG); + // op + wf_op("\tres *= src;\n"); + + // flag calculation + wf_op("\tCPU->flag_N = res >> 24;\n"); + wf_op("\tCPU->flag_notZ = res;\n"); + wf_op("\tCPU->flag_V = CPU->flag_C = 0;\n"); + + // write dst (Dx) + _ea_write(current_ea2, current_op->reg2_sft); + + // min cycle = 38; max cycle = 70 + terminate_op(38 + (2 * 6)); +} + +static void GenMULS() +{ + // generate jump table & opcode declaration + current_ea2 = EA_DREG; + if ((current_ea == EA_AREG) || (current_ea == EA_DREG) || (current_ea == EA_IMM)) + start_all(GEN_RES | GEN_SRC); + else + start_all(GEN_ADR | GEN_RES | GEN_SRC); + + set_current_size(SIZE_WORD); + // read src signed + _ea_calc(current_ea, current_op->reg_sft); + _ea_read_src_sx(current_ea, current_op->reg_sft); + // read dst signed (Dx) + _ea_calc(current_ea2, current_op->reg2_sft); + _ea_read_sx(current_ea2, current_op->reg2_sft); + + set_current_size(SIZE_LONG); + // op + //wf_op("\t(s32)res *= (s32)src;\n"); + wf_op("\tres *= (s32)src;\n"); // antime fix + + // flag calculation + wf_op("\tCPU->flag_N = res >> 24;\n"); + wf_op("\tCPU->flag_notZ = res;\n"); + wf_op("\tCPU->flag_V = CPU->flag_C = 0;\n"); + + // write dst (Dx) + _ea_write(current_ea2, current_op->reg2_sft); + + // min cycle = 38; max cycle = 70 + terminate_op(38 + (2 * 6)); +} + +static void GenArithaD(char op) +{ + // generate jump table & opcode declaration + current_ea2 = EA_DREG; + if ((current_ea == EA_AREG) || (current_ea == EA_DREG) || (current_ea == EA_IMM)) + start_all(GEN_DST | GEN_RES | GEN_SRC); + else + start_all(GEN_ALL); + + if (current_size == SIZE_LONG) + { + if (!is_ea_memory(current_ea)) current_cycle += 2; + else current_cycle += 4; + } + + // read src + _ea_calc(current_ea, current_op->reg_sft); + _ea_read_src(current_ea, current_op->reg_sft); + // read dst (Dx) + _ea_calc(current_ea2, current_op->reg2_sft); + _ea_read_dst(current_ea2, current_op->reg2_sft); + if (op == ' ') + { + // op + wf_op("\tres = dst - src;\n"); + // flag calculation + set_cmp_flag(); + } + else + { + // op + wf_op("\tres = dst %c src;\n", op); + // flag calculation + if (op == '+') set_add_flag(); + else set_sub_flag(); + // write dst (Dx) + _ea_write(current_ea2, current_op->reg2_sft); + } + + terminate_op(4); +} + +static void GenArithDa(char op) +{ + // generate jump table & opcode declaration + current_ea2 = EA_DREG; + start_all(GEN_ALL); + + if (current_size == SIZE_LONG) current_cycle += 4; + + // read src (Dx) + _ea_calc(current_ea2, current_op->reg2_sft); + _ea_read_src(current_ea2, current_op->reg2_sft); + // read dst + _ea_calc(current_ea, current_op->reg_sft); + _ea_read_dst(current_ea, current_op->reg_sft); + // op + wf_op("\tres = dst %c src;\n", op); + // flag calculation + if (op == '+') set_add_flag(); + else set_sub_flag(); + // write dst + _ea_write(current_ea, current_op->reg_sft); + + terminate_op(8); +} + +static void GenArithA(char op) +{ + // generate jump table & opcode declaration + current_ea2 = EA_AREG; + if ((current_ea == EA_AREG) || (current_ea == EA_DREG) || (current_ea == EA_IMM)) + start_all(GEN_DST | GEN_RES | GEN_SRC); + else + start_all(GEN_ALL); + + if ((op != ' ') && ((current_size == SIZE_WORD) || (is_ea_memory(current_ea)))) current_cycle += 2; + + // read src + _ea_calc(current_ea, current_op->reg_sft); + _ea_read_src_sx(current_ea, current_op->reg_sft); + // read dst (Ax) + set_current_size(SIZE_LONG); + _ea_calc(current_ea2, current_op->reg2_sft); + _ea_read_dst(current_ea2, current_op->reg2_sft); + // op + if (op == ' ') + { + // op + wf_op("\tres = dst - src;\n"); + // flag calculation + set_cmp_flag(); + } + else + { + // op + wf_op("\tres = dst %c src;\n", op); + // write dst (Ax) + _ea_write(current_ea2, current_op->reg2_sft); + } + + terminate_op(6); +} + +static void GenArithX(char op) +{ + // generate jump table & opcode declaration + current_ea = EA_DREG; + current_ea2 = EA_DREG; + if ((current_ea == EA_AREG) || (current_ea == EA_DREG) || (current_ea == EA_IMM)) + start_all(GEN_DST | GEN_RES | GEN_SRC); + else + start_all(GEN_ALL); + + if (current_size == SIZE_LONG) current_cycle += 4; + + // read src (Dx) + _ea_calc(current_ea, current_op->reg_sft); + _ea_read_src(current_ea, current_op->reg_sft); + // read dst (Dx) + _ea_calc(current_ea2, current_op->reg2_sft); + _ea_read_dst(current_ea2, current_op->reg2_sft); + // op + wf_op("\tres = dst %c src %c ((CPU->flag_X >> 8) & 1);\n", op, op); + // flag calculation + if (op == '+') set_addx_flag(); + else set_subx_flag(); + // write dst (Dx) + _ea_write(current_ea2, current_op->reg2_sft); + + terminate_op(4); +} + +static void GenArithXM(char op) +{ + // generate jump table & opcode declaration + current_ea = EA_ADEC; + current_ea2 = EA_ADEC; + start_all(GEN_ALL); + + if (current_size == SIZE_LONG) current_cycle += 4; + + // read src (ADEC) + _ea_calc(current_ea, current_op->reg_sft); + _ea_read_src(current_ea, current_op->reg_sft); + // read dst (ADEC) + _ea_calc(current_ea2, current_op->reg2_sft); + _ea_read_dst(current_ea2, current_op->reg2_sft); + // op + wf_op("\tres = dst %c src %c ((CPU->flag_X >> 8) & 1);\n", op, op); + // flag calculation + if (op == '+') set_addx_flag(); + else set_subx_flag(); + // write dst (ADEC) + _ea_write(current_ea2, current_op->reg2_sft); + + terminate_op(6); +} + +static void GenArithX7M(char op) +{ + // generate jump table & opcode declaration + current_ea = EA_ADEC7; + current_ea2 = EA_ADEC; + start_all(GEN_ALL); + + if (current_size == SIZE_LONG) current_cycle += 4; + + // read src (ADEC7) + _ea_calc(current_ea, 0); + _ea_read_src(current_ea, 0); + // read dst (ADEC) + _ea_calc(current_ea2, current_op->reg2_sft); + _ea_read_dst(current_ea2, current_op->reg2_sft); + // op + wf_op("\tres = dst %c src %c ((CPU->flag_X >> 8) & 1);\n", op, op); + // flag calculation + if (op == '+') set_addx_flag(); + else set_subx_flag(); + // write dst (ADEC) + _ea_write(current_ea2, current_op->reg2_sft); + + terminate_op(6); +} + +static void GenArithXM7(char op) +{ + // generate jump table & opcode declaration + current_ea = EA_ADEC; + current_ea2 = EA_ADEC7; + start_all(GEN_ALL); + + if (current_size == SIZE_LONG) current_cycle += 4; + + // read src (ADEC) + _ea_calc(current_ea, current_op->reg_sft); + _ea_read_src(current_ea, current_op->reg_sft); + // read dst (ADEC7) + _ea_calc(current_ea2, 0); + _ea_read_dst(current_ea2, 0); + // op + wf_op("\tres = dst %c src %c ((CPU->flag_X >> 8) & 1);\n", op, op); + // flag calculation + if (op == '+') set_addx_flag(); + else set_subx_flag(); + // write dst (ADEC7) + _ea_write(current_ea2, 0); + + terminate_op(6); +} + +static void GenArithX7M7(char op) +{ + // generate jump table & opcode declaration + current_ea = EA_ADEC7; + current_ea2 = EA_ADEC7; + start_all(GEN_ALL); + + if (current_size == SIZE_LONG) current_cycle += 4; + + // read src (ADEC7) + _ea_calc(current_ea, 0); + _ea_read_src(current_ea, 0); + // read dst (ADEC7) + _ea_calc(current_ea2, 0); + _ea_read_dst(current_ea2, 0); + // op + wf_op("\tres = dst %c src %c ((CPU->flag_X >> 8) & 1);\n", op, op); + // flag calculation + if (op == '+') set_addx_flag(); + else set_subx_flag(); + // write dst (ADEC7) + _ea_write(current_ea2, 0); + + terminate_op(6); +} + +static void GenADDaD() +{ + GenArithaD('+'); +} + +static void GenADDDa() +{ + GenArithDa('+'); +} + +static void GenADDA() +{ + GenArithA('+'); +} + +static void GenADDX() +{ + GenArithX('+'); +} + +static void GenADDXM() +{ + GenArithXM('+'); +} + +static void GenADDX7M() +{ + GenArithX7M('+'); +} + +static void GenADDXM7() +{ + GenArithXM7('+'); +} + +static void GenADDX7M7() +{ + GenArithX7M7('+'); +} + +static void GenSUBaD() +{ + GenArithaD('-'); +} + +static void GenSUBDa() +{ + GenArithDa('-'); +} + +static void GenSUBA() +{ + GenArithA('-'); +} + +static void GenSUBX() +{ + GenArithX('-'); +} + +static void GenSUBXM() +{ + GenArithXM('-'); +} + +static void GenSUBX7M() +{ + GenArithX7M('-'); +} + +static void GenSUBXM7() +{ + GenArithXM7('-'); +} + +static void GenSUBX7M7() +{ + GenArithX7M7('-'); +} + +static void GenCMP() +{ + GenArithaD(' '); +} + +static void GenCMPA() +{ + GenArithA(' '); +} + +static void GenCMPM() +{ + // generate jump table & opcode declaration + current_ea = EA_AINC; + current_ea2 = EA_AINC; + start_all(GEN_ALL); + + // read src (ADEC) + _ea_calc(current_ea, current_op->reg_sft); + _ea_read_src(current_ea, current_op->reg_sft); + // read dst (ADEC) + _ea_calc(current_ea2, current_op->reg2_sft); + _ea_read_dst(current_ea2, current_op->reg2_sft); + // op + wf_op("\tres = dst - src;\n"); + // flag calculation + set_cmp_flag(); + + terminate_op(4); + +} + +static void GenCMP7M() +{ + // generate jump table & opcode declaration + current_ea = EA_AINC7; + current_ea2 = EA_AINC; + start_all(GEN_ALL); + + // read src (ADEC) + _ea_calc(current_ea, 0); + _ea_read_src(current_ea, 0); + // read dst (ADEC) + _ea_calc(current_ea2, current_op->reg2_sft); + _ea_read_dst(current_ea2, current_op->reg2_sft); + // op + wf_op("\tres = dst - src;\n"); + // flag calculation + set_cmp_flag(); + + terminate_op(4); + +} + +static void GenCMPM7() +{ + // generate jump table & opcode declaration + current_ea = EA_AINC; + current_ea2 = EA_AINC7; + start_all(GEN_ALL); + + // read src (ADEC) + _ea_calc(current_ea, current_op->reg_sft); + _ea_read_src(current_ea, current_op->reg_sft); + // read dst (ADEC) + _ea_calc(current_ea2, 0); + _ea_read_dst(current_ea2, 0); + // op + wf_op("\tres = dst - src;\n"); + // flag calculation + set_cmp_flag(); + + terminate_op(4); + +} + +static void GenCMP7M7() +{ + // generate jump table & opcode declaration + current_ea = EA_AINC7; + current_ea2 = EA_AINC7; + start_all(GEN_ALL); + + // read src (ADEC) + _ea_calc(current_ea, 0); + _ea_read_src(current_ea, 0); + // read dst (ADEC) + _ea_calc(current_ea2, 0); + _ea_read_dst(current_ea2, 0); + // op + wf_op("\tres = dst - src;\n"); + // flag calculation + set_cmp_flag(); + + terminate_op(4); + +} + +static void GenEXGDD() +{ + // generate jump table & opcode declaration + set_current_size(SIZE_LONG); + current_ea = EA_DREG; + current_ea2 = EA_DREG; + start_all(GEN_RES | GEN_SRC); + + // read R1 + _ea_calc(current_ea, current_op->reg_sft); + _ea_read(current_ea, current_op->reg_sft); + // read R2 + _ea_calc(current_ea2, current_op->reg2_sft); + _ea_read_src(current_ea2, current_op->reg2_sft); + // write R1 + _ea_write(current_ea2, current_op->reg2_sft); + wf_op("\tres = src;\n"); + // write R2 + _ea_write(current_ea, current_op->reg_sft); + + terminate_op(6); +} + +static void GenEXGAA() +{ + // generate jump table & opcode declaration + set_current_size(SIZE_LONG); + current_ea = EA_AREG; + current_ea2 = EA_AREG; + start_all(GEN_RES | GEN_SRC); + + // read R1 + _ea_calc(current_ea, current_op->reg_sft); + _ea_read(current_ea, current_op->reg_sft); + // read R2 + _ea_calc(current_ea2, current_op->reg2_sft); + _ea_read_src(current_ea2, current_op->reg2_sft); + // write R1 + _ea_write(current_ea2, current_op->reg2_sft); + wf_op("\tres = src;\n"); + // write R2 + _ea_write(current_ea, current_op->reg_sft); + + terminate_op(6); +} + +static void GenEXGAD() +{ + // generate jump table & opcode declaration + set_current_size(SIZE_LONG); + current_ea = EA_AREG; + current_ea2 = EA_DREG; + start_all(GEN_RES | GEN_SRC); + + // read R1 + _ea_calc(current_ea, current_op->reg_sft); + _ea_read(current_ea, current_op->reg_sft); + // read R2 + _ea_calc(current_ea2, current_op->reg2_sft); + _ea_read_src(current_ea2, current_op->reg2_sft); + // write R1 + _ea_write(current_ea2, current_op->reg2_sft); + wf_op("\tres = src;\n"); + // write R2 + _ea_write(current_ea, current_op->reg_sft); + + terminate_op(6); +} + +static void GenASRk() +{ + u32 base; + + current_ea = EA_DREG; // dst = Dx + + base = get_current_opcode_base(); + // generate jump table + gen_opjumptable_ext(base, 0x0000, 0x0E00, 0x0200, base); + // generate label & declarations + start_op(base, GEN_RES | GEN_SRC); + + if (current_size == SIZE_LONG) current_cycle += 2; + + wf_op("\tu32 sft;\n"); + wf_op("\n"); + wf_op("\tsft = (((Opcode >> 9) - 1) & 7) + 1;\n"); + adds_CCnt("sft * 2"); + + // read (sign extend) + _ea_calc(current_ea, current_op->reg_sft); + _ea_read_src_sx(current_ea, current_op->reg_sft); + + // op & flag calculation + wf_op("\tCPU->flag_V = 0;\n"); + wf_op("\tCPU->flag_X = CPU->flag_C = src << ((C68K_SR_C_SFT + 1) - sft);\n"); + wf_op("\tres = ((s32)src) >> sft;\n"); + wf_op("\tCPU->flag_N = res >> %d;\n", current_sft_mask - C68K_SR_N_SFT); + wf_op("\tCPU->flag_notZ = res;\n"); + + // write + _ea_write(current_ea, current_op->reg_sft); + + terminate_op(6); +} + +static void GenLSRk() +{ + u32 base; + + current_ea = EA_DREG; // dst = Dx + + base = get_current_opcode_base(); + // generate jump table + gen_opjumptable_ext(base, 0x0000, 0x0E00, 0x0200, base); + // generate label & declarations + start_op(base, GEN_RES | GEN_SRC); + + if (current_size == SIZE_LONG) current_cycle += 2; + + wf_op("\tu32 sft;\n"); + wf_op("\n"); + wf_op("\tsft = (((Opcode >> 9) - 1) & 7) + 1;\n"); + adds_CCnt("sft * 2"); + + // read + _ea_calc(current_ea, current_op->reg_sft); + _ea_read_src(current_ea, current_op->reg_sft); + + // op & flag calculation + wf_op("\tCPU->flag_N = CPU->flag_V = 0;\n"); + wf_op("\tCPU->flag_X = CPU->flag_C = src << ((C68K_SR_C_SFT + 1) - sft);\n"); + wf_op("\tres = src >> sft;\n"); + wf_op("\tCPU->flag_notZ = res;\n"); + + // write + _ea_write(current_ea, current_op->reg_sft); + + terminate_op(6); +} + +static void GenROXRk() +{ + u32 base; + + current_ea = EA_DREG; // dst = Dx + + base = get_current_opcode_base(); + // generate jump table + gen_opjumptable_ext(base, 0x0000, 0x0E00, 0x0200, base); + // generate label & declarations + start_op(base, GEN_RES | GEN_SRC); + + if (current_size == SIZE_LONG) current_cycle += 2; + + wf_op("\tu32 sft;\n"); + wf_op("\n"); + wf_op("\tsft = (((Opcode >> 9) - 1) & 7) + 1;\n"); + adds_CCnt("sft * 2"); + + // read + _ea_calc(current_ea, current_op->reg_sft); + _ea_read_src(current_ea, current_op->reg_sft); + + // op & C / X flags calculation + if (current_size != SIZE_LONG) + { + wf_op("\tsrc |= (CPU->flag_X & C68K_SR_X) << %d;\n", (current_sft_mask + 1) - C68K_SR_X_SFT); + wf_op("\tres = (src >> sft) | (src << (%d - sft));\n", current_sft_mask + 2); + wf_op("\tCPU->flag_X = CPU->flag_C = res >> %d;\n", (current_sft_mask + 1) - C68K_SR_X_SFT); + } + else + { + wf_op("\tCPU->flag_C = src << ((C68K_SR_C_SFT + 1) - sft);\n"); + wf_op("\tif (sft == 1) res = (src >> 1) | ((CPU->flag_X & C68K_SR_X) << (32 - (C68K_SR_X_SFT + 1)));\n"); + wf_op("\telse res = (src >> sft) | (src << (33 - sft)) | ((CPU->flag_X & C68K_SR_X) << (32 - (C68K_SR_X_SFT + sft)));\n"); + wf_op("\tCPU->flag_X = CPU->flag_C;\n"); + } + + // V / N / Z flags calculation + wf_op("\tCPU->flag_V = 0;\n"); + wf_op("\tCPU->flag_N = res >> %d;\n", current_sft_mask - C68K_SR_N_SFT); + if (current_size == SIZE_LONG) wf_op("\tCPU->flag_notZ = res;\n"); + else wf_op("\tCPU->flag_notZ = res & 0x%.8X;\n", current_bits_mask); + + // write + _ea_write(current_ea, current_op->reg_sft); + + terminate_op(6); +} + +static void GenRORk() +{ + u32 base; + + current_ea = EA_DREG; // dst = Dx + + base = get_current_opcode_base(); + // generate jump table + gen_opjumptable_ext(base, 0x0000, 0x0E00, 0x0200, base); + // generate label & declarations + start_op(base, GEN_RES | GEN_SRC); + + if (current_size == SIZE_LONG) current_cycle += 2; + + wf_op("\tu32 sft;\n"); + wf_op("\n"); + wf_op("\tsft = (((Opcode >> 9) - 1) & 7) + 1;\n"); + adds_CCnt("sft * 2"); + + // read + _ea_calc(current_ea, current_op->reg_sft); + _ea_read_src(current_ea, current_op->reg_sft); + + // op & flag calculation + wf_op("\tCPU->flag_V = 0;\n"); + wf_op("\tCPU->flag_C = src << ((C68K_SR_C_SFT + 1) - sft);\n"); + wf_op("\tres = (src >> sft) | (src << (%d - sft));\n", current_sft_mask + 1); + wf_op("\tCPU->flag_N = res >> %d;\n", current_sft_mask - C68K_SR_N_SFT); + if (current_size == SIZE_LONG) wf_op("\tCPU->flag_notZ = res;\n"); + else wf_op("\tCPU->flag_notZ = res & 0x%.8X;\n", current_bits_mask); + + // write + _ea_write(current_ea, current_op->reg_sft); + + terminate_op(6); +} + +static void GenASLk() +{ + u32 base; + + current_ea = EA_DREG; // dst = Dx + + base = get_current_opcode_base(); + // generate jump table + gen_opjumptable_ext(base, 0x0000, 0x0E00, 0x0200, base); + // generate label & declarations + start_op(base, GEN_RES | GEN_SRC); + + if (current_size == SIZE_LONG) current_cycle += 2; + + wf_op("\tu32 sft;\n"); + wf_op("\n"); + wf_op("\tsft = (((Opcode >> 9) - 1) & 7) + 1;\n"); + adds_CCnt("sft * 2"); + + // read + _ea_calc(current_ea, current_op->reg_sft); + _ea_read_src(current_ea, current_op->reg_sft); + + // if (shift < size op) ... only for BYTE here + if (current_size == SIZE_BYTE) + { + wf_op("\tif (sft < %d)\n", current_sft_mask + 1); + wf_op("\t{\n"); + } + + // op & flag X, C, N, Z calculation + if (((current_sft_mask + 1) - C68K_SR_C_SFT) < 8) + wf_op("\t\tCPU->flag_X = CPU->flag_C = src << (%d + sft);\n", current_sft_mask + 1 - C68K_SR_C_SFT); + else wf_op("\t\tCPU->flag_X = CPU->flag_C = src >> (%d - sft);\n", current_sft_mask + 1 - C68K_SR_C_SFT); + wf_op("\t\tres = src << sft;\n"); + wf_op("\t\tCPU->flag_N = res >> %d;\n", current_sft_mask - C68K_SR_N_SFT); + wf_op("\t\tCPU->flag_notZ = res & 0x%.8X;\n", current_bits_mask); + + // write + _ea_write(current_ea, current_op->reg_sft); + + // we do V flag calculation at end for a better register usage + wf_op("\t\tCPU->flag_V = 0;\n"); + if (current_size == SIZE_BYTE) + { + wf_op("\t\tif ((sft > %d) && (src)) CPU->flag_V = C68K_SR_V;\n", current_sft_mask); + wf_op("\t\telse\n"); + } + wf_op("\t\t{\n"); + wf_op("\t\t\tu32 msk = (((s32)0x80000000) >> (sft + %d)) & 0x%.8X;\n", 31 - current_sft_mask, current_bits_mask); + wf_op("\t\t\tsrc &= msk;\n"); + wf_op("\t\t\tif ((src) && (src != msk)) CPU->flag_V = C68K_SR_V;\n"); + wf_op("\t\t}\n"); + + if (current_size == SIZE_BYTE) + { + quick_terminate_op(6); + wf_op("\t}\n"); + wf_op("\n"); + + // special case of shift == size op (sft = 8 for byte operation) + wf_op("\tif (src) CPU->flag_V = C68K_SR_V;\n"); + wf_op("\telse CPU->flag_V = 0;\n"); + wf_op("\tCPU->flag_X = CPU->flag_C = src << C68K_SR_C_SFT;\n"); + + // write + wf_op("\tres = 0;\n"); + _ea_write(current_ea, current_op->reg_sft); + + // others flags + wf_op("\tCPU->flag_N = 0;\n"); + wf_op("\tCPU->flag_notZ = 0;\n"); + } + + terminate_op(6); +} + +static void GenLSLk() +{ + u32 base; + + current_ea = EA_DREG; // dst = Dx + + base = get_current_opcode_base(); + // generate jump table + gen_opjumptable_ext(base, 0x0000, 0x0E00, 0x0200, base); + // generate label & declarations + start_op(base, GEN_RES | GEN_SRC); + + if (current_size == SIZE_LONG) current_cycle += 2; + + wf_op("\tu32 sft;\n"); + wf_op("\n"); + wf_op("\tsft = (((Opcode >> 9) - 1) & 7) + 1;\n"); + adds_CCnt("sft * 2"); + + // read + _ea_calc(current_ea, current_op->reg_sft); + _ea_read_src(current_ea, current_op->reg_sft); + + // op & flag calculation + wf_op("\tCPU->flag_V = 0;\n"); + if (((current_sft_mask + 1) - C68K_SR_C_SFT) < 8) + wf_op("\tCPU->flag_X = CPU->flag_C = src << (%d + sft);\n", current_sft_mask + 1 - C68K_SR_C_SFT); + else wf_op("\tCPU->flag_X = CPU->flag_C = src >> (%d - sft);\n", current_sft_mask + 1 - C68K_SR_C_SFT); + wf_op("\tres = src << sft;\n"); + wf_op("\tCPU->flag_N = res >> %d;\n", current_sft_mask - C68K_SR_N_SFT); + wf_op("\tCPU->flag_notZ = res & 0x%.8X;\n", current_bits_mask); + + // write + _ea_write(current_ea, current_op->reg_sft); + + terminate_op(6); +} + +static void GenROXLk() +{ + u32 base; + + current_ea = EA_DREG; // dst = Dx + + base = get_current_opcode_base(); + // generate jump table + gen_opjumptable_ext(base, 0x0000, 0x0E00, 0x0200, base); + // generate label & declarations + start_op(base, GEN_RES | GEN_SRC); + + if (current_size == SIZE_LONG) current_cycle += 2; + + wf_op("\tu32 sft;\n"); + wf_op("\n"); + wf_op("\tsft = (((Opcode >> 9) - 1) & 7) + 1;\n"); + adds_CCnt("sft * 2"); + + // read + _ea_calc(current_ea, current_op->reg_sft); + _ea_read_src(current_ea, current_op->reg_sft); + + // op & C / X flags calculation + if (current_size != SIZE_LONG) + { + wf_op("\tsrc |= (CPU->flag_X & C68K_SR_X) << %d;\n", (current_sft_mask + 1) - C68K_SR_X_SFT); + wf_op("\tres = (src << sft) | (src >> (%d - sft));\n", current_sft_mask + 2); + wf_op("\tCPU->flag_X = CPU->flag_C = res >> %d;\n", (current_sft_mask + 1) - C68K_SR_X_SFT); + } + else + { + wf_op("\tCPU->flag_C = src >> ((32 - C68K_SR_C_SFT) - sft);\n"); + wf_op("\tif (sft == 1) res = (src << 1) | ((CPU->flag_X & C68K_SR_X) >> ((C68K_SR_X_SFT + 1) - 1));\n"); + wf_op("\telse res = (src << sft) | (src >> (33 - sft)) | ((CPU->flag_X & C68K_SR_X) >> ((C68K_SR_X_SFT + 1) - sft));\n"); + wf_op("\tCPU->flag_X = CPU->flag_C;\n"); + } + + // V / N / Z flags calculation + wf_op("\tCPU->flag_V = 0;\n"); + wf_op("\tCPU->flag_N = res >> %d;\n", current_sft_mask - C68K_SR_N_SFT); + if (current_size == SIZE_LONG) wf_op("\tCPU->flag_notZ = res;\n"); + else wf_op("\tCPU->flag_notZ = res & 0x%.8X;\n", current_bits_mask); + + // write + _ea_write(current_ea, current_op->reg_sft); + + terminate_op(6); +} + +static void GenROLk() +{ + u32 base; + + current_ea = EA_DREG; // dst = Dx + + base = get_current_opcode_base(); + // generate jump table + gen_opjumptable_ext(base, 0x0000, 0x0E00, 0x0200, base); + // generate label & declarations + start_op(base, GEN_RES | GEN_SRC); + + if (current_size == SIZE_LONG) current_cycle += 2; + + wf_op("\tu32 sft;\n"); + wf_op("\n"); + wf_op("\tsft = (((Opcode >> 9) - 1) & 7) + 1;\n"); + adds_CCnt("sft * 2"); + + // read + _ea_calc(current_ea, current_op->reg_sft); + _ea_read_src(current_ea, current_op->reg_sft); + + // op & flag calculation + wf_op("\tCPU->flag_V = 0;\n"); + if (((current_sft_mask + 1) - C68K_SR_C_SFT) < 8) + wf_op("\tCPU->flag_C = src << (%d + sft);\n", current_sft_mask + 1 - C68K_SR_C_SFT); + else wf_op("\tCPU->flag_C = src >> (%d - sft);\n", current_sft_mask + 1 - C68K_SR_C_SFT); + wf_op("\tres = (src << sft) | (src >> (%d - sft));\n", current_sft_mask + 1); + wf_op("\tCPU->flag_N = res >> %d;\n", current_sft_mask - C68K_SR_N_SFT); + if (current_size == SIZE_LONG) wf_op("\tCPU->flag_notZ = res;\n"); + else wf_op("\tCPU->flag_notZ = res & 0x%.8X;\n", current_bits_mask); + + // write + _ea_write(current_ea, current_op->reg_sft); + + terminate_op(6); +} + +static void GenASRD() +{ +// u32 base = get_current_opcode_base(); + + current_ea = EA_DREG; // dst = Dx + + start_all(GEN_RES | GEN_SRC); + + if (current_size == SIZE_LONG) current_cycle += 2; + + wf_op("\tu32 sft;\n"); + wf_op("\n"); + wf_op("\tsft = CPU->D[(Opcode >> %d) & 7] & 0x3F;\n", current_op->reg2_sft); + + // read (sign extend) + _ea_calc(current_ea, current_op->reg_sft); + _ea_read_src_sx(current_ea, current_op->reg_sft); + + // if (shift != 0) + wf_op("\tif (sft)\n"); + wf_op("\t{\n"); + + adds_CCnt("sft * 2"); + + // if (shift < size op) + wf_op("\t\tif (sft < %d)\n", current_sft_mask + 1); + wf_op("\t\t{\n"); + + // op & flag calculation + wf_op("\t\t\tCPU->flag_V = 0;\n"); + if (current_size == SIZE_BYTE) wf_op("\t\t\tCPU->flag_X = CPU->flag_C = src << ((C68K_SR_C_SFT + 1) - sft);\n"); + else wf_op("\t\t\tCPU->flag_X = CPU->flag_C = (src >> (sft - 1)) << C68K_SR_C_SFT;\n"); + wf_op("\t\t\tres = ((s32)src) >> sft;\n", szcs); + wf_op("\t\t\tCPU->flag_N = res >> %d;\n", current_sft_mask - C68K_SR_N_SFT); + wf_op("\t\t\tCPU->flag_notZ = res;\n"); + + // write + _ea_write(current_ea, current_op->reg_sft); + + quick_terminate_op(6); + wf_op("\t\t}\n"); + wf_op("\n"); + + // special case of shift >= size op + + // if signed + wf_op("\t\tif (src & (1 << %d))\n", current_sft_mask); + wf_op("\t\t{\n"); + + // op & flag calculation + wf_op("\t\t\tCPU->flag_N = C68K_SR_N;\n"); + wf_op("\t\t\tCPU->flag_notZ = 1;\n"); + wf_op("\t\t\tCPU->flag_V = 0;\n"); + wf_op("\t\t\tCPU->flag_C = C68K_SR_C;\n"); + wf_op("\t\t\tCPU->flag_X = C68K_SR_X;\n"); + wf_op("\t\t\tres = 0x%.8X;\n", current_bits_mask); + + // write + _ea_write(current_ea, current_op->reg_sft); + + quick_terminate_op(6); + wf_op("\t\t}\n"); + wf_op("\n"); + + // if not signed + wf_op("\t\tCPU->flag_N = 0;\n"); + wf_op("\t\tCPU->flag_notZ = 0;\n"); + wf_op("\t\tCPU->flag_V = 0;\n"); + wf_op("\t\tCPU->flag_C = 0;\n"); + wf_op("\t\tCPU->flag_X = 0;\n"); + wf_op("\t\tres = 0;\n"); + + // write + _ea_write(current_ea, current_op->reg_sft); + + quick_terminate_op(6); + wf_op("\t}\n"); + wf_op("\n"); + + // special case of (shift == 0) + wf_op("\tCPU->flag_V = 0;\n"); + wf_op("\tCPU->flag_C = 0;\n"); + wf_op("\tCPU->flag_N = src >> %d;\n", current_sft_mask - C68K_SR_N_SFT); + wf_op("\tCPU->flag_notZ = src;\n"); + + terminate_op(6); +} + +static void GenLSRD() +{ +// u32 base = get_current_opcode_base(); + + current_ea = EA_DREG; // dst = Dx + + start_all(GEN_RES | GEN_SRC); + + if (current_size == SIZE_LONG) current_cycle += 2; + + wf_op("\tu32 sft;\n"); + wf_op("\n"); + wf_op("\tsft = CPU->D[(Opcode >> %d) & 7] & 0x3F;\n", current_op->reg2_sft); + + // read + _ea_calc(current_ea, current_op->reg_sft); + _ea_read_src(current_ea, current_op->reg_sft); + + // if (shift != 0) + wf_op("\tif (sft)\n"); + wf_op("\t{\n"); + + adds_CCnt("sft * 2"); + + // if (shift <= size op) + if (current_size == SIZE_LONG) wf_op("\t\tif (sft < 32)\n"); + else wf_op("\t\tif (sft <= %d)\n", current_sft_mask + 1); + wf_op("\t\t{\n"); + + // op & flag calculation + wf_op("\t\t\tCPU->flag_N = CPU->flag_V = 0;\n"); + if (current_size == SIZE_BYTE) wf_op("\t\t\tCPU->flag_X = CPU->flag_C = src << ((C68K_SR_C_SFT + 1) - sft);\n"); + else wf_op("\t\t\tCPU->flag_X = CPU->flag_C = (src >> (sft - 1)) << C68K_SR_C_SFT;\n"); + wf_op("\t\t\tres = src >> sft;\n", szcs); + wf_op("\t\t\tCPU->flag_notZ = res;\n"); + + // write + _ea_write(current_ea, current_op->reg_sft); + + quick_terminate_op(6); + wf_op("\t\t}\n"); + wf_op("\n"); + + // special case of shift > size op + if (current_size == SIZE_LONG) + { + wf_op("\t\tif (sft == 32) CPU->flag_C = src >> (31 - C68K_SR_C_SFT);\n"); + wf_op("\t\telse CPU->flag_C = 0;\n"); + wf_op("\t\tCPU->flag_X = CPU->flag_C;\n"); + } + else wf_op("\t\tCPU->flag_X = CPU->flag_C = 0;\n"); + wf_op("\t\tCPU->flag_N = 0;\n"); + wf_op("\t\tCPU->flag_notZ = 0;\n"); + wf_op("\t\tCPU->flag_V = 0;\n"); + wf_op("\t\tres = 0;\n"); + + // write + _ea_write(current_ea, current_op->reg_sft); + + quick_terminate_op(6); + wf_op("\t}\n"); + wf_op("\n"); + + // special case of (shift == 0) + wf_op("\tCPU->flag_V = 0;\n"); + wf_op("\tCPU->flag_C = 0;\n"); + wf_op("\tCPU->flag_N = src >> %d;\n", current_sft_mask - C68K_SR_N_SFT); + wf_op("\tCPU->flag_notZ = src;\n"); + + terminate_op(6); +} + +static void GenROXRD() +{ +// u32 base = get_current_opcode_base(); + + current_ea = EA_DREG; // dst = Dx + + start_all(GEN_RES | GEN_SRC); + + if (current_size == SIZE_LONG) current_cycle += 2; + + wf_op("\tu32 sft;\n"); + wf_op("\n"); + wf_op("\tsft = CPU->D[(Opcode >> %d) & 7] & 0x3F;\n", current_op->reg2_sft); + + // read + _ea_calc(current_ea, current_op->reg_sft); + _ea_read_src(current_ea, current_op->reg_sft); + + // if (shift != 0) + wf_op("\tif (sft)\n"); + wf_op("\t{\n"); + + adds_CCnt("sft * 2"); + + wf_op("\t\tsft %%= %d;\n", current_sft_mask + 2); + wf_op("\n"); + + // op & C / X flag calculation + if (current_size != SIZE_LONG) + { + wf_op("\t\tsrc |= (CPU->flag_X & C68K_SR_X) << %d;\n", (current_sft_mask + 1) - C68K_SR_X_SFT); + wf_op("\t\tres = (src >> sft) | (src << (%d - sft));\n", current_sft_mask + 2); + wf_op("\t\tCPU->flag_X = CPU->flag_C = res >> %d;\n", (current_sft_mask + 1) - C68K_SR_X_SFT); + } + else + { + wf_op("\t\tif (sft != 0)\n"); + wf_op("\t\t{\n"); + wf_op("\t\t\tif (sft == 1) res = (src >> 1) | ((CPU->flag_X & C68K_SR_X) << (32 - (C68K_SR_X_SFT + 1)));\n"); + wf_op("\t\t\telse res = (src >> sft) | (src << (33 - sft)) | (((CPU->flag_X & C68K_SR_X) << (32 - (C68K_SR_X_SFT + 1))) >> (sft - 1));\n"); + wf_op("\t\t\tCPU->flag_X = (src >> (32 - sft)) << C68K_SR_X_SFT;\n"); + wf_op("\t\t}\n"); + wf_op("\t\telse res = src;\n"); + wf_op("\t\tCPU->flag_C = CPU->flag_X;\n"); + } + + // V / N / Z flag calculation + wf_op("\t\tCPU->flag_V = 0;\n"); + wf_op("\t\tCPU->flag_N = res >> %d;\n", current_sft_mask - C68K_SR_N_SFT); + if (current_size == SIZE_LONG) wf_op("\t\tCPU->flag_notZ = res;\n"); + else wf_op("\t\tCPU->flag_notZ = res & 0x%.8X;\n", current_bits_mask); + + // write + _ea_write(current_ea, current_op->reg_sft); + + quick_terminate_op(6); + wf_op("\t}\n"); + wf_op("\n"); + + // special case of (shift == 0) + wf_op("\tCPU->flag_V = 0;\n"); + wf_op("\tCPU->flag_C = CPU->flag_X;\n"); + wf_op("\tCPU->flag_N = src >> %d;\n", current_sft_mask - C68K_SR_N_SFT); + wf_op("\tCPU->flag_notZ = src;\n"); + + terminate_op(6); +} + +static void GenRORD() +{ +// u32 base = get_current_opcode_base(); + + current_ea = EA_DREG; // dst = Dx + + start_all(GEN_RES | GEN_SRC); + + if (current_size == SIZE_LONG) current_cycle += 2; + + wf_op("\tu32 sft;\n"); + wf_op("\n"); + wf_op("\tsft = CPU->D[(Opcode >> %d) & 7] & 0x3F;\n", current_op->reg2_sft); + + // read + _ea_calc(current_ea, current_op->reg_sft); + _ea_read_src(current_ea, current_op->reg_sft); + + // if (shift != 0) + wf_op("\tif (sft)\n"); + wf_op("\t{\n"); + + adds_CCnt("sft * 2"); + + wf_op("\t\tsft &= 0x%.2X;\n", current_sft_mask); + wf_op("\t\t\n"); + + // op & flag calculation + if (current_size == SIZE_BYTE) + wf_op("\t\tCPU->flag_C = src << (C68K_SR_C_SFT - ((sft - 1) & 7));\n"); + else + wf_op("\t\tCPU->flag_C = (src >> ((sft - 1) & %d)) << C68K_SR_C_SFT;\n", current_sft_mask); + wf_op("\t\tres = (src >> sft) | (src << (%d - sft));\n", current_sft_mask + 1); + wf_op("\t\tCPU->flag_V = 0;\n"); + wf_op("\t\tCPU->flag_N = res >> %d;\n", current_sft_mask - C68K_SR_N_SFT); + if (current_size == SIZE_LONG) wf_op("\t\tCPU->flag_notZ = res;\n"); + else wf_op("\t\tCPU->flag_notZ = res & 0x%.8X;\n", current_bits_mask); + + // write + _ea_write(current_ea, current_op->reg_sft); + + quick_terminate_op(6); + wf_op("\t}\n"); + wf_op("\n"); + + // special case of (shift == 0) + wf_op("\tCPU->flag_V = 0;\n"); + wf_op("\tCPU->flag_C = 0;\n"); + wf_op("\tCPU->flag_N = src >> %d;\n", current_sft_mask - C68K_SR_N_SFT); + wf_op("\tCPU->flag_notZ = src;\n"); + + terminate_op(6); +} + +static void GenASLD() +{ +// u32 base = get_current_opcode_base(); + + current_ea = EA_DREG; // dst = Dx + + start_all(GEN_RES | GEN_SRC); + + if (current_size == SIZE_LONG) current_cycle += 2; + + wf_op("\tu32 sft;\n"); + wf_op("\n"); + wf_op("\tsft = CPU->D[(Opcode >> %d) & 7] & 0x3F;\n", current_op->reg2_sft); + + // read + _ea_calc(current_ea, current_op->reg_sft); + _ea_read_src(current_ea, current_op->reg_sft); + + // if (shift != 0) + wf_op("\tif (sft)\n"); + wf_op("\t{\n"); + + adds_CCnt("sft * 2"); + + // if (shift < size op) + wf_op("\t\tif (sft < %d)\n", current_sft_mask + 1); + wf_op("\t\t{\n"); + + // op & flag calculation + if (current_size != SIZE_LONG) + { + wf_op("\t\t\tCPU->flag_X = CPU->flag_C = (src << sft) >> %d;\n", (current_sft_mask + 1) - C68K_SR_C_SFT); + wf_op("\t\t\tres = (src << sft) & 0x%.8X;\n", current_bits_mask); + } + else + { + wf_op("\t\t\tCPU->flag_X = CPU->flag_C = (src >> (32 - sft)) << C68K_SR_C_SFT;\n"); + wf_op("\t\t\tres = src << sft;\n"); + } + wf_op("\t\t\tCPU->flag_N = res >> %d;\n", current_sft_mask - C68K_SR_N_SFT); + wf_op("\t\t\tCPU->flag_notZ = res;\n", current_bits_mask); + + // write + _ea_write(current_ea, current_op->reg_sft); + + // we do V flag calculation at end for a better register usage + wf_op("\t\t\tCPU->flag_V = 0;\n"); + wf_op("\t\t\t{\n"); + wf_op("\t\t\t\tu32 msk = (((s32)0x80000000) >> (sft + %d)) & 0x%.8X;\n", 31 - current_sft_mask, current_bits_mask); + wf_op("\t\t\t\tsrc &= msk;\n"); + wf_op("\t\t\t\tif ((src) && (src != msk)) CPU->flag_V = C68K_SR_V;\n"); + wf_op("\t\t\t}\n"); + + quick_terminate_op(6); + wf_op("\t\t}\n"); + wf_op("\n"); + + // special case of shift >= size op + wf_op("\t\tif (sft == %d) CPU->flag_C = src << C68K_SR_C_SFT;\n", current_bits_mask + 1); + wf_op("\t\telse CPU->flag_C = 0;\n"); + wf_op("\t\tCPU->flag_X = CPU->flag_C;\n"); + wf_op("\t\tif (src) CPU->flag_V = C68K_SR_V;\n"); + wf_op("\t\telse CPU->flag_V = 0;\n"); + + wf_op("\t\tres = 0;\n"); + // write + _ea_write(current_ea, current_op->reg_sft); + + // others flags + wf_op("\t\tCPU->flag_N = 0;\n"); + wf_op("\t\tCPU->flag_notZ = 0;\n"); + + quick_terminate_op(6); + wf_op("\t}\n"); + wf_op("\n"); + + // special case of (shift == 0) + wf_op("\tCPU->flag_V = 0;\n"); + wf_op("\tCPU->flag_C = 0;\n"); + wf_op("\tCPU->flag_N = src >> %d;\n", current_sft_mask - C68K_SR_N_SFT); + wf_op("\tCPU->flag_notZ = src;\n"); + + terminate_op(6); +} + +static void GenLSLD() +{ +// u32 base = get_current_opcode_base(); + + current_ea = EA_DREG; // dst = Dx + + start_all(GEN_RES | GEN_SRC); + + if (current_size == SIZE_LONG) current_cycle += 2; + + wf_op("\tu32 sft;\n"); + wf_op("\n"); + wf_op("\tsft = CPU->D[(Opcode >> %d) & 7] & 0x3F;\n", current_op->reg2_sft); + + // read + _ea_calc(current_ea, current_op->reg_sft); + _ea_read_src(current_ea, current_op->reg_sft); + + // if (shift != 0) + wf_op("\tif (sft)\n"); + wf_op("\t{\n"); + + adds_CCnt("sft * 2"); + + // if (shift <= size op) + if (current_size == SIZE_LONG) wf_op("\t\tif (sft < 32)\n"); + else wf_op("\t\tif (sft <= %d)\n", current_sft_mask + 1); + wf_op("\t\t{\n"); + + // op & flag calculation + if (current_size != SIZE_LONG) + { + wf_op("\t\t\tCPU->flag_X = CPU->flag_C = (src << sft) >> %d;\n", (current_sft_mask + 1) - C68K_SR_C_SFT); + wf_op("\t\t\tres = (src << sft) & 0x%.8X;\n", current_bits_mask); + } + else + { + wf_op("\t\t\tCPU->flag_X = CPU->flag_C = (src >> (32 - sft)) << C68K_SR_C_SFT;\n"); + wf_op("\t\t\tres = src << sft;\n"); + } + wf_op("\t\t\tCPU->flag_V = 0;\n"); + wf_op("\t\t\tCPU->flag_N = res >> %d;\n", current_sft_mask - C68K_SR_N_SFT); + wf_op("\t\t\tCPU->flag_notZ = res;\n", current_bits_mask); + + // write + _ea_write(current_ea, current_op->reg_sft); + + quick_terminate_op(6); + wf_op("\t\t}\n"); + wf_op("\n"); + + // special case of shift > size op + if (current_size == SIZE_LONG) + { + wf_op("\t\tif (sft == 32) CPU->flag_C = src << C68K_SR_C_SFT;\n"); + wf_op("\t\telse CPU->flag_C = 0;\n"); + wf_op("\t\tCPU->flag_X = CPU->flag_C;\n"); + } + else wf_op("\t\tCPU->flag_X = CPU->flag_C = 0;\n"); + wf_op("\t\tCPU->flag_N = 0;\n"); + wf_op("\t\tCPU->flag_notZ = 0;\n"); + wf_op("\t\tCPU->flag_V = 0;\n"); + wf_op("\t\tres = 0;\n"); + + // write + _ea_write(current_ea, current_op->reg_sft); + + quick_terminate_op(6); + wf_op("\t}\n"); + wf_op("\n"); + + // special case of (shift == 0) + wf_op("\tCPU->flag_V = 0;\n"); + wf_op("\tCPU->flag_C = 0;\n"); + wf_op("\tCPU->flag_N = src >> %d;\n", current_sft_mask - C68K_SR_N_SFT); + wf_op("\tCPU->flag_notZ = src;\n"); + + terminate_op(6); +} + +static void GenROXLD() +{ +// u32 base = get_current_opcode_base(); + + current_ea = EA_DREG; // dst = Dx + + start_all(GEN_RES | GEN_SRC); + + if (current_size == SIZE_LONG) current_cycle += 2; + + wf_op("\tu32 sft;\n"); + wf_op("\n"); + wf_op("\tsft = CPU->D[(Opcode >> %d) & 7] & 0x3F;\n", current_op->reg2_sft); + + // read + _ea_calc(current_ea, current_op->reg_sft); + _ea_read_src(current_ea, current_op->reg_sft); + + // if (shift != 0) + wf_op("\tif (sft)\n"); + wf_op("\t{\n"); + + adds_CCnt("sft * 2"); + + wf_op("\t\tsft %%= %d;\n", current_sft_mask + 2); + wf_op("\n"); + + // op & C/X flags calculation + if (current_size != SIZE_LONG) + { + wf_op("\t\tsrc |= (CPU->flag_X & C68K_SR_X) << %d;\n", (current_sft_mask + 1) - C68K_SR_X_SFT); + wf_op("\t\tres = (src << sft) | (src >> (%d - sft));\n", current_sft_mask + 2); + wf_op("\t\tCPU->flag_X = CPU->flag_C = res >> %d;\n", (current_sft_mask + 1) - C68K_SR_X_SFT); + } + else + { + wf_op("\t\tif (sft != 0)\n"); + wf_op("\t\t{\n"); + wf_op("\t\t\tif (sft == 1) res = (src << 1) | ((CPU->flag_X >> ((C68K_SR_X_SFT + 1) - 1)) & 1);\n"); + wf_op("\t\t\telse res = (src << sft) | (src >> (33 - sft)) | (((CPU->flag_X >> ((C68K_SR_X_SFT + 1) - 1)) & 1) << (sft - 1));\n"); + wf_op("\t\t\tCPU->flag_X = (src >> (32 - sft)) << C68K_SR_X_SFT;\n"); + wf_op("\t\t}\n"); + wf_op("\t\telse res = src;\n"); + wf_op("\t\tCPU->flag_C = CPU->flag_X;\n"); + } + + // V / N / Z flags calculation + wf_op("\t\tCPU->flag_V = 0;\n"); + wf_op("\t\tCPU->flag_N = res >> %d;\n", current_sft_mask - C68K_SR_N_SFT); + if (current_size == SIZE_LONG) wf_op("\t\tCPU->flag_notZ = res;\n"); + else wf_op("\t\tCPU->flag_notZ = res & 0x%.8X;\n", current_bits_mask); + + // write + _ea_write(current_ea, current_op->reg_sft); + + quick_terminate_op(6); + wf_op("\t}\n"); + wf_op("\n"); + + // special case of (shift == 0) + wf_op("\tCPU->flag_V = 0;\n"); + wf_op("\tCPU->flag_C = CPU->flag_X;\n"); + wf_op("\tCPU->flag_N = src >> %d;\n", current_sft_mask - C68K_SR_N_SFT); + wf_op("\tCPU->flag_notZ = src;\n"); + + terminate_op(6); +} + +static void GenROLD() +{ +// u32 base = get_current_opcode_base(); + + current_ea = EA_DREG; // dst = Dx + + start_all(GEN_RES | GEN_SRC); + + if (current_size == SIZE_LONG) current_cycle += 2; + + wf_op("\tu32 sft;\n"); + wf_op("\n"); + wf_op("\tsft = CPU->D[(Opcode >> %d) & 7] & 0x3F;\n", current_op->reg2_sft); + + // read + _ea_calc(current_ea, current_op->reg_sft); + _ea_read_src(current_ea, current_op->reg_sft); + + // if (shift != 0) + wf_op("\tif (sft)\n"); + wf_op("\t{\n"); + + adds_CCnt("sft * 2"); + + // if ((shift & size op) != 0) + wf_op("\t\tif (sft &= 0x%.2X)\n", current_sft_mask); + wf_op("\t\t{\n"); + + // op & flag calculation + if (current_size != SIZE_LONG) + { + wf_op("\t\t\tCPU->flag_C = (src << sft) >> %d;\n", (current_sft_mask + 1) - C68K_SR_C_SFT); + wf_op("\t\t\tres = ((src << sft) | (src >> (%d - sft))) & 0x%.8X;\n", current_sft_mask + 1, current_bits_mask); + } + else + { + wf_op("\t\t\tCPU->flag_C = (src >> (32 - sft)) << C68K_SR_C_SFT;\n"); + wf_op("\t\t\tres = (src << sft) | (src >> (%d - sft));\n", current_sft_mask + 1); + } + wf_op("\t\t\tCPU->flag_V = 0;\n"); + wf_op("\t\t\tCPU->flag_N = res >> %d;\n", current_sft_mask - C68K_SR_N_SFT); + wf_op("\t\t\tCPU->flag_notZ = res;\n"); + + // write + _ea_write(current_ea, current_op->reg_sft); + + quick_terminate_op(6); + wf_op("\t\t}\n"); + wf_op("\n"); + + // special case of ((shift & size op) == 0) + wf_op("\t\tCPU->flag_V = 0;\n"); + wf_op("\t\tCPU->flag_C = src << C68K_SR_C_SFT;\n"); + wf_op("\t\tCPU->flag_N = src >> %d;\n", current_sft_mask - C68K_SR_N_SFT); + wf_op("\t\tCPU->flag_notZ = src;\n"); + + quick_terminate_op(6); + wf_op("\t}\n"); + wf_op("\n"); + + // special case of (shift == 0) + wf_op("\tCPU->flag_V = 0;\n"); + wf_op("\tCPU->flag_C = 0;\n"); + wf_op("\tCPU->flag_N = src >> %d;\n", current_sft_mask - C68K_SR_N_SFT); + wf_op("\tCPU->flag_notZ = src;\n"); + + terminate_op(6); +} + +static void GenASR() +{ + set_current_size(SIZE_WORD); // dst = mem (word operation) + start_all(GEN_ADR | GEN_RES | GEN_SRC); + + // read + _ea_calc(current_ea, current_op->reg_sft); + _ea_read_src(current_ea, current_op->reg_sft); + + // op & flag calculation + wf_op("\tCPU->flag_V = 0;\n"); + wf_op("\tCPU->flag_X = CPU->flag_C = src << C68K_SR_C_SFT;\n"); + wf_op("\tres = (src >> 1) | (src & (1 << %d));\n", current_sft_mask); + wf_op("\tCPU->flag_N = res >> %d;\n", current_sft_mask - C68K_SR_N_SFT); + wf_op("\tCPU->flag_notZ = res;\n"); + + // write + _ea_write(current_ea, current_op->reg_sft); + + terminate_op(8); +} + +static void GenLSR() +{ + set_current_size(SIZE_WORD); // dst = mem (word operation) + start_all(GEN_ADR | GEN_RES | GEN_SRC); + + // read + _ea_calc(current_ea, current_op->reg_sft); + _ea_read_src(current_ea, current_op->reg_sft); + + // op & flag calculation + wf_op("\tCPU->flag_N = CPU->flag_V = 0;\n"); + wf_op("\tCPU->flag_X = CPU->flag_C = src << C68K_SR_C_SFT;\n"); + wf_op("\tres = src >> 1;\n"); + wf_op("\tCPU->flag_notZ = res;\n"); + + // write + _ea_write(current_ea, current_op->reg_sft); + + terminate_op(8); +} + +static void GenROXR() +{ + set_current_size(SIZE_WORD); // dst = mem (word operation) + start_all(GEN_ADR | GEN_RES | GEN_SRC); + + // read + _ea_calc(current_ea, current_op->reg_sft); + _ea_read_src(current_ea, current_op->reg_sft); + + // op & flag calculation + wf_op("\tCPU->flag_V = 0;\n"); + wf_op("\tres = (src >> 1) | ((CPU->flag_X & C68K_SR_X) << %d);\n", current_sft_mask - C68K_SR_X_SFT); + wf_op("\tCPU->flag_C = CPU->flag_X = src << C68K_SR_C_SFT;\n"); + wf_op("\tCPU->flag_N = res >> %d;\n", current_sft_mask - C68K_SR_N_SFT); + wf_op("\tCPU->flag_notZ = res;\n"); + + // write + _ea_write(current_ea, current_op->reg_sft); + + terminate_op(8); +} + +static void GenROR() +{ + set_current_size(SIZE_WORD); // dst = mem (word operation) + start_all(GEN_ADR | GEN_RES | GEN_SRC); + + // read + _ea_calc(current_ea, current_op->reg_sft); + _ea_read_src(current_ea, current_op->reg_sft); + + // op & flag calculation + wf_op("\tCPU->flag_V = 0;\n"); + wf_op("\tCPU->flag_C = src << C68K_SR_C_SFT;\n"); + wf_op("\tres = (src >> 1) | (src << %d);\n", current_sft_mask); + wf_op("\tCPU->flag_N = res >> %d;\n", current_sft_mask - C68K_SR_N_SFT); + wf_op("\tCPU->flag_notZ = res & 0x%.8X;\n", current_bits_mask); + + // write + _ea_write(current_ea, current_op->reg_sft); + + terminate_op(8); +} + +static void GenASL() +{ + set_current_size(SIZE_WORD); // dst = mem (word operation) + start_all(GEN_ADR | GEN_RES | GEN_SRC); + + // read + _ea_calc(current_ea, current_op->reg_sft); + _ea_read_src(current_ea, current_op->reg_sft); + + // op & flag calculation + wf_op("\tCPU->flag_X = CPU->flag_C = src >> %d;\n", current_sft_mask - C68K_SR_C_SFT); + wf_op("\tres = src << 1;\n"); + wf_op("\tCPU->flag_V = (src ^ res) >> %d;\n", current_sft_mask - C68K_SR_V_SFT); + wf_op("\tCPU->flag_N = res >> %d;\n", current_sft_mask - C68K_SR_N_SFT); + wf_op("\tCPU->flag_notZ = res & 0x%.8X;\n", current_bits_mask); + + // write + _ea_write(current_ea, current_op->reg_sft); + + terminate_op(8); +} + +static void GenLSL() +{ + set_current_size(SIZE_WORD); // dst = mem (word operation) + start_all(GEN_ADR | GEN_RES | GEN_SRC); + + // read + _ea_calc(current_ea, current_op->reg_sft); + _ea_read_src(current_ea, current_op->reg_sft); + + // op & flag calculation + wf_op("\tCPU->flag_V = 0;\n"); + wf_op("\tCPU->flag_X = CPU->flag_C = src >> %d;\n", current_sft_mask - C68K_SR_C_SFT); + wf_op("\tres = src << 1;\n"); + wf_op("\tCPU->flag_N = res >> %d;\n", current_sft_mask - C68K_SR_N_SFT); + wf_op("\tCPU->flag_notZ = res & 0x%.8X;\n", current_bits_mask); + + // write + _ea_write(current_ea, current_op->reg_sft); + + terminate_op(8); +} + +static void GenROXL() +{ + set_current_size(SIZE_WORD); // dst = mem (word operation) + start_all(GEN_ADR | GEN_RES | GEN_SRC); + + // read + _ea_calc(current_ea, current_op->reg_sft); + _ea_read_src(current_ea, current_op->reg_sft); + + // op & flag calculation + wf_op("\tCPU->flag_V = 0;\n"); + wf_op("\tres = (src << 1) | ((CPU->flag_X & C68K_SR_X) >> %d);\n", C68K_SR_X_SFT); + wf_op("\tCPU->flag_X = CPU->flag_C = src >> %d;\n", current_sft_mask - C68K_SR_C_SFT); + wf_op("\tCPU->flag_N = res >> %d;\n", current_sft_mask - C68K_SR_N_SFT); + wf_op("\tCPU->flag_notZ = res & 0x%.8X;\n", current_bits_mask); + + // write + _ea_write(current_ea, current_op->reg_sft); + + terminate_op(8); +} + +static void GenROL() +{ + set_current_size(SIZE_WORD); // dst = mem (word operation) + start_all(GEN_ADR | GEN_RES | GEN_SRC); + + // read + _ea_calc(current_ea, current_op->reg_sft); + _ea_read_src(current_ea, current_op->reg_sft); + + // op & flag calculation + wf_op("\tCPU->flag_V = 0;\n"); + wf_op("\tCPU->flag_C = src >> %d;\n", current_sft_mask - C68K_SR_C_SFT); + wf_op("\tres = (src << 1) | (src >> %d);\n", current_sft_mask); + wf_op("\tCPU->flag_N = res >> %d;\n", current_sft_mask - C68K_SR_N_SFT); + wf_op("\tCPU->flag_notZ = res & 0x%.8X;\n", current_bits_mask); + + // write + _ea_write(current_ea, current_op->reg_sft); + + terminate_op(8); +} + +static void Gen1010() +{ + u32 base; + base = get_current_opcode_base(); + + // generate jump table + gen_opjumptable_ext(base, 0x0000, 0x0FFF, 0x1, base); + + // generate label & declarations + start_op(base, GEN_RES); + wf_op("\tPC -= 2;\n"); + gen_exception("\t", "C68K_1010_EX"); + terminate_op(4); +} + +static void Gen1111() +{ + u32 base; + base = get_current_opcode_base(); + + // generate jump table + gen_opjumptable_ext(base, 0x0000, 0x0FFF, 0x1, base); + + // generate label & declarations + start_op(base, GEN_RES); + wf_op("\tPC -= 2;\n"); + gen_exception("\t", "C68K_1111_EX"); + terminate_op(4); +} + +#ifdef NEOCD_HLE +static void Gen0xFABE() +{ + start_all(GEN_ALL); + + wf_op("\tneogeo_exit();\n"); + + terminate_op(0); +} + +static void Gen0xFABF() +{ + start_all(GEN_ALL); + + wf_op("\timg_display = 1;\n"); + wf_op("\tcdrom_load_files();\n"); + + terminate_op(0); +} + +static void Gen0xFAC0() +{ + start_all(GEN_ALL); + + wf_op("\timg_display = 0;\n"); + wf_op("\tcdrom_load_files();\n"); + + terminate_op(0); +} + +static void Gen0xFAC1() +{ + start_all(GEN_ALL); + + wf_op("\tneogeo_upload();\n"); + + terminate_op(0); +} + +static void Gen0xFAC2() +{ + start_all(GEN_ALL); + + wf_op("\tneogeo_prio_switch();\n"); + + terminate_op(0); +} + +static void Gen0xFAC3() +{ + start_all(GEN_ALL); + + wf_op("\tneogeo_cdda_control();\n"); + + terminate_op(0); +} +#endif + + +// main function +///////////////// +int main(void) +{ + u32 i; + u32 s; + u32 smax; + + // clear opcode files + for(i = 0; i < 0x10; i++) + { + char fn[16]; + + sprintf(fn, "c68k_op%.1X.inc", (int)i); + opcode_file = fopen(fn, "wt"); + if (opcode_file != NULL) + { + fclose(opcode_file); + opcode_file = NULL; + } + } + + // init opcode jump table + ini_file = fopen("c68k_ini.inc", "wt"); +#ifndef C68K_NO_JUMP_TABLE +#ifdef C68K_CONST_JUMP_TABLE + for(i = 0; i < 0x10000; i++) op_jump_table[i] = OP_ILLEGAL; +#else + // defaut ILLEGAL instruction + gen_jumptable(0x0000, 0x0000, 0xFFFF, 1, 0, 0, 0, 0, 0, 0, 0x4AFC); +#endif +#endif + // generate opcode files + for(i = 0; i < OP_INFO_TABLE_LEN; i++) + { + current_op = &(op_info_table[i]); + if (prepare_generate()) return 1; + + // s = size to start + current_size = 0; + smax = SIZE_LONG; + if (current_op->size_type == 0) smax = 0; + else if (current_op->size_type == 1) current_size = 1; + + for(s = current_size; s <= smax; s++) + { + if (current_op->eam_sft != -1) + { + for(current_ea = 0; current_ea <= EA_ADEC7; current_ea++) + { + if (!has_ea(current_ea)) continue; + current_eam = _ea_to_eamreg(current_ea) >> 3; + current_reg = _ea_to_eamreg(current_ea) & 7; + + if (op_info_table[i].eam2_sft != -1) + { + for(current_ea2 = 0; current_ea2 <= EA_ADEC7; current_ea2++) + { + if (!has_ea2(current_ea2)) continue; + current_eam2 = _ea_to_eamreg(current_ea2) >> 3; + current_reg2 = _ea_to_eamreg(current_ea2) & 7; + + set_current_size(s); + current_op->genfunc(); + } + } + else + { + current_reg2 = 0; + set_current_size(s); + current_op->genfunc(); + } + } + } + else + { + current_reg = 0; + set_current_size(s); + current_op->genfunc(); + } + } + } + + // generate jumptable file +#ifdef C68K_CONST_JUMP_TABLE + if (ini_file != NULL) + { + fprintf(ini_file, "\tstatic const void *JumpTable[0x10000] =\n"); + fprintf(ini_file, "\t{\n"); + + for(i = 0; i < (0x10000 - 4); i += 4) + fprintf(ini_file, "\t\t&&OP_0x%.4X, &&OP_0x%.4X, &&OP_0x%.4X, &&OP_0x%.4X,\n", op_jump_table[i + 0], op_jump_table[i + 1], op_jump_table[i + 2], op_jump_table[i + 3]); + fprintf(ini_file, "\t\t&&OP_0x%.4X, &&OP_0x%.4X, &&OP_0x%.4X, &&OP_0x%.4X\n", op_jump_table[0xFFFC], op_jump_table[0xFFFD], op_jump_table[0xFFFE], op_jump_table[0xFFFF]); + + fprintf(ini_file, "\t};\n\n"); + } +#endif + + // close handle + if (ini_file != NULL) fclose(ini_file); + if (opcode_file != NULL) fclose(opcode_file); + + return 0; +} +#endif diff --git a/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/gen68k.h b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/gen68k.h new file mode 100644 index 000000000..e8b71d83d --- /dev/null +++ b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/gen68k.h @@ -0,0 +1,68 @@ +/* Copyright 2003-2004 Stephane Dallongeville + Copyright 2004 Theo Berkau + + This file is part of Yabause. + + Yabause is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + Yabause is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with Yabause; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +/********************************************************************************* + * GEN68K.H : + * + * C68K generator include file + * + ********************************************************************************/ + +#ifndef _GEN68K_H_ +#define _GEN68K_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +// setting +/////////// + +// structure definition +//////////////////////// + +typedef struct { + u32 name; + u32 mask; + u32 match; +} c68k_ea_info_struc; + +typedef struct __c68k_op_info_struc { + s8 op_name[8 + 1]; + u16 op_base; + u16 op_mask; + s8 size_type; + s8 size_sft; + s8 eam_sft; + s8 reg_sft; + s8 eam2_sft; + s8 reg2_sft; + s8 ea_supported[12 + 1]; + s8 ea2_supported[12 + 1]; + void (*genfunc)(void); +} c68k_op_info_struc; + + +#ifdef __cplusplus +} +#endif + +#endif // _GEN68K_H_ + diff --git a/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/gen68k.inc b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/gen68k.inc new file mode 100644 index 000000000..483a4f7b0 --- /dev/null +++ b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/c68k/gen68k.inc @@ -0,0 +1,1649 @@ +/* Copyright 2003-2004 Stephane Dallongeville + + This file is part of Yabause. + + Yabause is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + Yabause is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with Yabause; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#include +#include + +#define EA_DREG 0 +#define EA_AREG 1 +#define EA_AIND 2 +#define EA_AINC 3 +#define EA_ADEC 4 +#define EA_D16A 5 +#define EA_D8AX 6 +#define EA_A16 7 +#define EA_A32 8 +#define EA_D16P 9 +#define EA_D8PX 10 +#define EA_IMM 11 +#define EA_AINC7 12 +#define EA_ADEC7 13 +#define EA_ILLEGAL 15 + +#define SIZE_BYTE 0 +#define SIZE_WORD 1 +#define SIZE_LONG 2 + +#define COND_TR 0 +#define COND_FA 1 +#define COND_HI 2 +#define COND_LS 3 +#define COND_CC 4 +#define COND_CS 5 +#define COND_NE 6 +#define COND_EQ 7 +#define COND_VC 8 +#define COND_VS 9 +#define COND_PL 10 +#define COND_MI 11 +#define COND_GE 12 +#define COND_LT 13 +#define COND_GT 14 +#define COND_LE 15 + +#define COND_NOT_TR COND_FA +#define COND_NOT_FA COND_TR +#define COND_NOT_HI COND_LS +#define COND_NOT_LS COND_HI +#define COND_NOT_CC COND_CS +#define COND_NOT_CS COND_CC +#define COND_NOT_NE COND_EQ +#define COND_NOT_EQ COND_NE +#define COND_NOT_VC COND_VS +#define COND_NOT_VS COND_VC +#define COND_NOT_PL COND_MI +#define COND_NOT_MI COND_PL +#define COND_NOT_GE COND_LT +#define COND_NOT_LT COND_GE +#define COND_NOT_GT COND_LE +#define COND_NOT_LE COND_GT + +#define OP_ILLEGAL 0x4AFC + +static void GenORI(void); +static void GenORICCR(void); +static void GenORISR(void); +static void GenANDI(void); +static void GenANDICCR(void); +static void GenANDISR(void); +static void GenEORI(void); +static void GenEORICCR(void); +static void GenEORISR(void); +static void GenSUBI(void); +static void GenADDI(void); +static void GenCMPI(void); +static void GenBTSTn(void); +static void GenBCHGn(void); +static void GenBCLRn(void); +static void GenBSETn(void); +static void GenBTST(void); +static void GenBCHG(void); +static void GenBCLR(void); +static void GenBSET(void); +static void GenMOVEPWaD(void); +static void GenMOVEPLaD(void); +static void GenMOVEPWDa(void); +static void GenMOVEPLDa(void); +static void GenMOVEB(void); +static void GenMOVEL(void); +static void GenMOVEW(void); +static void GenMOVEAL(void); +static void GenMOVEAW(void); +static void GenNEGX(void); +static void GenCLR(void); +static void GenNEG(void); +static void GenNOT(void); +static void GenMOVESRa(void); +static void GenMOVEaSR(void); +static void GenMOVEaCCR(void); +static void GenNBCD(void); +static void GenPEA(void); +static void GenSWAP(void); +static void GenMOVEMaR(void); +static void GenEXT(void); +static void GenTST(void); +static void GenTAS(void); +static void GenILLEGAL(void); +static void GenMOVEMRa(void); +static void GenTRAP(void); +static void GenLINK(void); +static void GenLINKA7(void); +static void GenULNK(void); +static void GenULNKA7(void); +static void GenMOVEAUSP(void); +static void GenMOVEUSPA(void); +static void GenRESET(void); +static void GenNOP(void); +static void GenSTOP(void); +static void GenRTE(void); +static void GenRTS(void); +static void GenTRAPV(void); +static void GenRTR(void); +static void GenJSR(void); +static void GenJMP(void); +static void GenCHK(void); +static void GenLEA(void); +static void GenSTCC(void); +static void GenDBCC(void); +static void GenADDQ(void); +static void GenSUBQ(void); +static void GenBCC(void); +static void GenBCC16(void); +static void GenBRA(void); +static void GenBRA16(void); +static void GenBSR(void); +static void GenBSR16(void); +static void GenMOVEQ(void); +static void GenORaD(void); +static void GenORDa(void); +static void GenSBCD(void); +static void GenSBCDM(void); +static void GenSBCD7M(void); +static void GenSBCDM7(void); +static void GenSBCD7M7(void); +static void GenDIVU(void); +static void GenDIVS(void); +static void GenSUBaD(void); +static void GenSUBDa(void); +static void GenSUBX(void); +static void GenSUBXM(void); +static void GenSUBX7M(void); +static void GenSUBXM7(void); +static void GenSUBX7M7(void); +static void GenSUBA(void); +static void GenCMP(void); +static void GenCMPM(void); +static void GenCMP7M(void); +static void GenCMPM7(void); +static void GenCMP7M7(void); +static void GenEORDa(void); +static void GenCMPA(void); +static void GenANDaD(void); +static void GenANDDa(void); +static void GenABCD(void); +static void GenABCDM(void); +static void GenABCD7M(void); +static void GenABCDM7(void); +static void GenABCD7M7(void); +static void GenMULU(void); +static void GenMULS(void); +static void GenEXGDD(void); +static void GenEXGAA(void); +static void GenEXGAD(void); +static void GenADDaD(void); +static void GenADDDa(void); +static void GenADDX(void); +static void GenADDXM(void); +static void GenADDX7M(void); +static void GenADDXM7(void); +static void GenADDX7M7(void); +static void GenADDA(void); +static void GenASRk(void); +static void GenLSRk(void); +static void GenROXRk(void); +static void GenRORk(void); +static void GenASLk(void); +static void GenLSLk(void); +static void GenROXLk(void); +static void GenROLk(void); +static void GenASRD(void); +static void GenLSRD(void); +static void GenROXRD(void); +static void GenRORD(void); +static void GenASLD(void); +static void GenLSLD(void); +static void GenROXLD(void); +static void GenROLD(void); +static void GenASR(void); +static void GenLSR(void); +static void GenROXR(void); +static void GenROR(void); +static void GenASL(void); +static void GenLSL(void); +static void GenROXL(void); +static void GenROL(void); +static void Gen1010(void); +static void Gen1111(void); +#ifdef NEOCD_HLE +static void Gen0xFABE(void); +static void Gen0xFABF(void); +static void Gen0xFAC0(void); +static void Gen0xFAC1(void); +static void Gen0xFAC2(void); +static void Gen0xFAC3(void); +#endif + +#ifdef NEOCD_HLE +#define OP_INFO_TABLE_LEN (142 + 6) +#else +#define OP_INFO_TABLE_LEN 144 +#endif + +static c68k_op_info_struc op_info_table[OP_INFO_TABLE_LEN] = +{ // DAAAAddaaddi DAAAAddaaddi + // iid181318m iid181318m + // siz siz eam ear eam ear nne6A626Pm nne6A626Pm + // opname opbase opmask typ sft 1 1 2 2 dccAX PX dccAX PX GenFunc + { "1010", 0xA000, 0xF000, 0, 0, -1, -1, -1, -1, "------------", "------------", Gen1010 }, + { "1111", 0xF000, 0xF000, 0, 0, -1, -1, -1, -1, "------------", "------------", Gen1111 }, + { "ORI", 0x0000, 0xFF00, 2, 6, 3, 0, -1, -1, "o-ooooooo---", "------------", GenORI }, + { "ORICCR", 0x003C, 0xFFFF, 0, 0, -1, -1, -1, -1, "------------", "------------", GenORICCR }, + { "ORISR", 0x007C, 0xFFFF, 0, 0, -1, -1, -1, -1, "------------", "------------", GenORISR }, + { "ANDI", 0x0200, 0xFF00, 2, 6, 3, 0, -1, -1, "o-ooooooo---", "------------", GenANDI }, + { "ANDICCR", 0x023C, 0xFFFF, 0, 0, -1, -1, -1, -1, "------------", "------------", GenANDICCR }, + { "ANDISR", 0x027C, 0xFFFF, 0, 0, -1, -1, -1, -1, "------------", "------------", GenANDISR }, + { "EORI", 0x0A00, 0xFF00, 2, 6, 3, 0, -1, -1, "o-ooooooo---", "------------", GenEORI }, + { "EORICCR", 0x0A3C, 0xFFFF, 0, 0, -1, -1, -1, -1, "------------", "------------", GenEORICCR }, + { "EORISR", 0x0A7C, 0xFFFF, 0, 0, -1, -1, -1, -1, "------------", "------------", GenEORISR }, + + { "SUBI", 0x0400, 0xFF00, 2, 6, 3, 0, -1, -1, "o-ooooooo---", "------------", GenSUBI }, + { "ADDI", 0x0600, 0xFF00, 2, 6, 3, 0, -1, -1, "o-ooooooo---", "------------", GenADDI }, + { "CMPI", 0x0C00, 0xFF00, 2, 6, 3, 0, -1, -1, "o-ooooooo---", "------------", GenCMPI }, + + { "BTSTn", 0x0800, 0xFFC0, 0, 0, 3, 0, -1, -1, "o-ooooooooo-", "------------", GenBTSTn }, + { "BCHGn", 0x0840, 0xFFC0, 0, 0, 3, 0, -1, -1, "o-ooooooo---", "------------", GenBCHGn }, + { "BCLRn", 0x0880, 0xFFC0, 0, 0, 3, 0, -1, -1, "o-ooooooo---", "------------", GenBCLRn }, + { "BSETn", 0x08C0, 0xFFC0, 0, 0, 3, 0, -1, -1, "o-ooooooo---", "------------", GenBSETn }, + + { "BTST", 0x0100, 0xF1C0, 0, 0, 3, 0, -1, 9, "o-oooooooooo", "------------", GenBTST }, + { "BCHG", 0x0140, 0xF1C0, 0, 0, 3, 0, -1, 9, "o-ooooooo---", "------------", GenBCHG }, + { "BCLR", 0x0180, 0xF1C0, 0, 0, 3, 0, -1, 9, "o-ooooooo---", "------------", GenBCLR }, + { "BSET", 0x01C0, 0xF1C0, 0, 0, 3, 0, -1, 9, "o-ooooooo---", "------------", GenBSET }, + + { "MOVEPWaD", 0x0108, 0xF1F8, 0, 0, -1, 0, -1, 9, "------------", "------------", GenMOVEPWaD }, + { "MOVEPLaD", 0x0148, 0xF1F8, 0, 0, -1, 0, -1, 9, "------------", "------------", GenMOVEPLaD }, + { "MOVEPWDa", 0x0188, 0xF1F8, 0, 0, -1, 0, -1, 9, "------------", "------------", GenMOVEPWDa }, + { "MOVEPLDa", 0x01C8, 0xF1F8, 0, 0, -1, 0, -1, 9, "------------", "------------", GenMOVEPLDa }, + + { "MOVEB", 0x1000, 0xF000, 0, 0, 3, 0, 6, 9, "oooooooooooo", "o-ooooooo---", GenMOVEB }, + { "MOVEL", 0x2000, 0xF000, 0, 0, 3, 0, 6, 9, "oooooooooooo", "o-ooooooo---", GenMOVEL }, + { "MOVEW", 0x3000, 0xF000, 0, 0, 3, 0, 6, 9, "oooooooooooo", "o-ooooooo---", GenMOVEW }, + { "MOVEAL", 0x2040, 0xF1C0, 0, 0, 3, 0, -1, 9, "oooooooooooo", "------------", GenMOVEAL }, + { "MOVEAW", 0x3040, 0xF1C0, 0, 0, 3, 0, -1, 9, "oooooooooooo", "------------", GenMOVEAW }, + + { "NEGX", 0x4000, 0xFF00, 2, 6, 3, 0, -1, -1, "o-ooooooo---", "------------", GenNEGX }, + { "CLR", 0x4200, 0xFF00, 2, 6, 3, 0, -1, -1, "o-ooooooo---", "------------", GenCLR }, + { "NEG", 0x4400, 0xFF00, 2, 6, 3, 0, -1, -1, "o-ooooooo---", "------------", GenNEG }, + { "NOT", 0x4600, 0xFF00, 2, 6, 3, 0, -1, -1, "o-ooooooo---", "------------", GenNOT }, + + { "MOVESRa", 0x40C0, 0xFFC0, 0, 0, 3, 0, -1, -1, "o-ooooooo---", "------------", GenMOVESRa }, + { "MOVEaCCR", 0x44C0, 0xFFC0, 0, 0, 3, 0, -1, -1, "o-oooooooooo", "------------", GenMOVEaCCR }, + { "MOVEaSR", 0x46C0, 0xFFC0, 0, 0, 3, 0, -1, -1, "o-oooooooooo", "------------", GenMOVEaSR }, + + { "NBCD", 0x4800, 0xFFC0, 0, 0, 3, 0, -1, -1, "o-ooooooo---", "------------", GenNBCD }, + { "PEA", 0x4840, 0xFFC0, 0, 0, 3, 0, -1, -1, "--o--oooooo-", "------------", GenPEA }, + { "SWAP", 0x4840, 0xFFF8, 0, 0, -1, 0, -1, -1, "------------", "------------", GenSWAP }, + + { "MOVEMRa", 0x4880, 0xFF80, 1, 6, 3, 0, -1, -1, "--o-ooooo---", "------------", GenMOVEMRa }, + { "EXT", 0x4880, 0xFFB8, 1, 6, -1, 0, -1, -1, "------------", "------------", GenEXT }, + { "TST", 0x4A00, 0xFF00, 2, 6, 3, 0, -1, -1, "o-ooooooo---", "------------", GenTST }, + { "TAS", 0x4AC0, 0xFFC0, 0, 0, 3, 0, -1, -1, "o-ooooooo---", "------------", GenTAS }, + { "ILLEGAL", 0x4AFC, 0xFFFF, 0, 0, -1, -1, -1, -1, "------------", "------------", GenILLEGAL }, + { "MOVEMaR", 0x4C80, 0xFF80, 1, 6, 3, 0, -1, -1, "--oo-oooooo-", "------------", GenMOVEMaR }, + + { "TRAP", 0x4E40, 0xFFF0, 0, 0, -1, -1, -1, -1, "------------", "------------", GenTRAP }, + { "LINK", 0x4E50, 0xFFF8, 0, 0, -1, 0, -1, -1, "------------", "------------", GenLINK }, + { "LINKA7", 0x4E57, 0xFFFF, 0, 0, -1, -1, -1, -1, "------------", "------------", GenLINKA7 }, + { "ULNK", 0x4E58, 0xFFF8, 0, 0, -1, 0, -1, -1, "------------", "------------", GenULNK }, + { "ULNKA7", 0x4E5F, 0xFFFF, 0, 0, -1, -1, -1, -1, "------------", "------------", GenULNKA7 }, + { "MOVEAUSP", 0x4E60, 0xFFF8, 0, 0, -1, 0, -1, -1, "------------", "------------", GenMOVEAUSP }, + { "MOVEUSPA", 0x4E68, 0xFFF8, 0, 0, -1, 0, -1, -1, "------------", "------------", GenMOVEUSPA }, + + { "RESET", 0x4E70, 0xFFFF, 0, 0, -1, -1, -1, -1, "------------", "------------", GenRESET }, + { "NOP", 0x4E71, 0xFFFF, 0, 0, -1, -1, -1, -1, "------------", "------------", GenNOP }, + { "STOP", 0x4E72, 0xFFFF, 0, 0, -1, -1, -1, -1, "------------", "------------", GenSTOP }, + { "RTE", 0x4E73, 0xFFFF, 0, 0, -1, -1, -1, -1, "------------", "------------", GenRTE }, + { "RTS", 0x4E75, 0xFFFF, 0, 0, -1, -1, -1, -1, "------------", "------------", GenRTS }, + { "TRAPV", 0x4E76, 0xFFFF, 0, 0, -1, -1, -1, -1, "------------", "------------", GenTRAPV }, + { "RTR", 0x4E77, 0xFFFF, 0, 0, -1, -1, -1, -1, "------------", "------------", GenRTR }, + + { "JSR", 0x4E80, 0xFFC0, 0, 0, 3, 0, -1, -1, "--o--oooooo-", "------------", GenJSR }, + { "JMP", 0x4EC0, 0xFFC0, 0, 0, 3, 0, -1, -1, "--o--oooooo-", "------------", GenJMP }, + + { "CHK", 0x4180, 0xF1C0, 0, 0, 3, 0, -1, 9, "o-oooooooooo", "------------", GenCHK }, + { "LEA", 0x41C0, 0xF1C0, 0, 0, 3, 0, -1, 9, "--o--oooooo-", "------------", GenLEA }, + + { "STCC", 0x50C0, 0xF0C0, 0, 0, 3, 0, -1, -1, "o-ooooooo---", "------------", GenSTCC }, + { "DBCC", 0x50C8, 0xF0F8, 0, 0, -1, 0, -1, -1, "------------", "------------", GenDBCC }, + + { "ADDQ", 0x5000, 0xF100, 2, 6, 3, 0, -1, -1, "ooooooooo---", "------------", GenADDQ }, + { "SUBQ", 0x5100, 0xF100, 2, 6, 3, 0, -1, -1, "ooooooooo---", "------------", GenSUBQ }, + + { "BCC", 0x6000, 0xF000, 0, 0, -1, -1, -1, -1, "------------", "------------", GenBCC }, + { "BCC16", 0x6000, 0xF0FF, 0, 0, -1, -1, -1, -1, "------------", "------------", GenBCC16 }, + { "BRA", 0x6000, 0xFF00, 0, 0, -1, -1, -1, -1, "------------", "------------", GenBRA }, + { "BRA16", 0x6000, 0xFFFF, 0, 0, -1, -1, -1, -1, "------------", "------------", GenBRA16 }, + { "BSR", 0x6100, 0xFF00, 0, 0, -1, -1, -1, -1, "------------", "------------", GenBSR }, + { "BSR16", 0x6100, 0xFFFF, 0, 0, -1, -1, -1, -1, "------------", "------------", GenBSR16 }, + + { "MOVEQ", 0x7000, 0xF100, 0, 0, -1, 9, -1, -1, "------------", "------------", GenMOVEQ }, + + { "ORaD", 0x8000, 0xF100, 2, 6, 3, 0, -1, 9, "o-oooooooooo", "------------", GenORaD }, + { "ORDa", 0x8100, 0xF100, 2, 6, 3, 0, -1, 9, "--ooooooo---", "------------", GenORDa }, + { "SBCD", 0x8100, 0xF1F8, 0, 0, -1, 0, -1, 9, "------------", "------------", GenSBCD }, + { "SBCDM", 0x8108, 0xF1F8, 0, 0, -1, 0, -1, 9, "------------", "------------", GenSBCDM }, + { "SBCD7M", 0x810F, 0xF1FF, 0, 0, -1, 0, -1, 9, "------------", "------------", GenSBCD7M }, + { "SBCDM7", 0x8F08, 0xFFF8, 0, 0, -1, 0, -1, 9, "------------", "------------", GenSBCDM7 }, + { "SBCD7M7", 0x8F0F, 0xFFFF, 0, 0, -1, 0, -1, 9, "------------", "------------", GenSBCD7M7 }, + { "DIVU", 0x80C0, 0xF1C0, 0, 0, 3, 0, -1, 9, "o-oooooooooo", "------------", GenDIVU }, + { "DIVS", 0x81C0, 0xF1C0, 0, 0, 3, 0, -1, 9, "o-oooooooooo", "------------", GenDIVS }, + + { "SUBaD", 0x9000, 0xF100, 2, 6, 3, 0, -1, 9, "oooooooooooo", "------------", GenSUBaD }, + { "SUBDa", 0x9100, 0xF100, 2, 6, 3, 0, -1, 9, "--ooooooo---", "------------", GenSUBDa }, + { "SUBX", 0x9100, 0xF138, 2, 6, -1, 0, -1, 9, "------------", "------------", GenSUBX }, + { "SUBXM", 0x9108, 0xF138, 2, 6, -1, 0, -1, 9, "------------", "------------", GenSUBXM }, + { "SUBX7M", 0x910F, 0xF13F, 2, 6, -1, -1, -1, 9, "------------", "------------", GenSUBX7M }, + { "SUBXM7", 0x9F08, 0xFF38, 2, 6, -1, 0, -1, -1, "------------", "------------", GenSUBXM7 }, + { "SUBX7M7", 0x9F0F, 0xFF3F, 2, 6, -1, -1, -1, -1, "------------", "------------", GenSUBX7M7 }, + { "SUBA", 0x90C0, 0xF0C0, 1, 8, 3, 0, -1, 9, "oooooooooooo", "------------", GenSUBA }, + + { "CMP", 0xB000, 0xF100, 2, 6, 3, 0, -1, 9, "oooooooooooo", "------------", GenCMP }, + { "CMPM", 0xB108, 0xF138, 2, 6, -1, 0, -1, 9, "------------", "------------", GenCMPM }, + { "CMP7M", 0xB10F, 0xF13F, 2, 6, -1, -1, -1, 9, "------------", "------------", GenCMP7M }, + { "CMPM7", 0xBF08, 0xFF38, 2, 6, -1, 0, -1, -1, "------------", "------------", GenCMPM7 }, + { "CMP7M7", 0xBF0F, 0xFF3F, 2, 6, -1, -1, -1, -1, "------------", "------------", GenCMP7M7 }, + { "EORDa", 0xB100, 0xF100, 2, 6, 3, 0, -1, 9, "o-ooooooo---", "------------", GenEORDa }, + { "CMPA", 0xB0C0, 0xF0C0, 1, 8, 3, 0, -1, 9, "oooooooooooo", "------------", GenCMPA }, + + { "ANDaD", 0xC000, 0xF100, 2, 6, 3, 0, -1, 9, "o-oooooooooo", "------------", GenANDaD }, + { "ANDDa", 0xC100, 0xF100, 2, 6, 3, 0, -1, 9, "--ooooooo---", "------------", GenANDDa }, + { "ABCD", 0xC100, 0xF1F8, 0, 0, -1, 0, -1, 9, "------------", "------------", GenABCD }, + { "ABCDM", 0xC108, 0xF1F8, 0, 0, -1, 0, -1, 9, "------------", "------------", GenABCDM }, + { "ABCD7M", 0xC10F, 0xF1FF, 0, 0, -1, -1, -1, 9, "------------", "------------", GenABCD7M }, + { "ABCDM7", 0xCF08, 0xFFF8, 0, 0, -1, 0, -1, -1, "------------", "------------", GenABCDM7 }, + { "ABCD7M7", 0xCF0F, 0xFFFF, 0, 0, -1, -1, -1, -1, "------------", "------------", GenABCD7M7 }, + { "MULU", 0xC0C0, 0xF1C0, 0, 0, 3, 0, -1, 9, "o-oooooooooo", "------------", GenMULU }, + { "MULS", 0xC1C0, 0xF1C0, 0, 0, 3, 0, -1, 9, "o-oooooooooo", "------------", GenMULS }, + { "EXGDD", 0xC140, 0xF1F8, 0, 0, -1, 0, -1, 9, "------------", "------------", GenEXGDD }, + { "EXGAA", 0xC148, 0xF1F8, 0, 0, -1, 0, -1, 9, "------------", "------------", GenEXGAA }, + { "EXGAD", 0xC188, 0xF1F8, 0, 0, -1, 0, -1, 9, "------------", "------------", GenEXGAD }, + + { "ADDaD", 0xD000, 0xF100, 2, 6, 3, 0, -1, 9, "oooooooooooo", "------------", GenADDaD }, + { "ADDDa", 0xD100, 0xF100, 2, 6, 3, 0, -1, 9, "--ooooooo---", "------------", GenADDDa }, + { "ADDX", 0xD100, 0xF138, 2, 6, -1, 0, -1, 9, "------------", "------------", GenADDX }, + { "ADDXM", 0xD108, 0xF138, 2, 6, -1, 0, -1, 9, "------------", "------------", GenADDXM }, + { "ADDX7M", 0xD10F, 0xF13F, 2, 6, -1, -1, -1, 9, "------------", "------------", GenADDX7M }, + { "ADDXM7", 0xDF08, 0xFF38, 2, 6, -1, 0, -1, -1, "------------", "------------", GenADDXM7 }, + { "ADDX7M7", 0xDF0F, 0xFF3F, 2, 6, -1, -1, -1, -1, "------------", "------------", GenADDX7M7 }, + { "ADDA", 0xD0C0, 0xF0C0, 1, 8, 3, 0, -1, 9, "oooooooooooo", "------------", GenADDA }, + + { "ASRk", 0xE000, 0xF138, 2, 6, -1, 0, -1, -1, "o-----------", "------------", GenASRk }, + { "LSRk", 0xE008, 0xF138, 2, 6, -1, 0, -1, -1, "o-----------", "------------", GenLSRk }, + { "ROXRk", 0xE010, 0xF138, 2, 6, -1, 0, -1, -1, "o-----------", "------------", GenROXRk }, + { "RORk", 0xE018, 0xF138, 2, 6, -1, 0, -1, -1, "o-----------", "------------", GenRORk }, + { "ASLk", 0xE100, 0xF138, 2, 6, -1, 0, -1, -1, "o-----------", "------------", GenASLk }, + { "LSLk", 0xE108, 0xF138, 2, 6, -1, 0, -1, -1, "o-----------", "------------", GenLSLk }, + { "ROXLk", 0xE110, 0xF138, 2, 6, -1, 0, -1, -1, "o-----------", "------------", GenROXLk }, + { "ROLk", 0xE118, 0xF138, 2, 6, -1, 0, -1, -1, "o-----------", "------------", GenROLk }, + + { "ASRD", 0xE020, 0xF138, 2, 6, -1, 0, -1, 9, "o-----------", "o-----------", GenASRD }, + { "LSRD", 0xE028, 0xF138, 2, 6, -1, 0, -1, 9, "o-----------", "o-----------", GenLSRD }, + { "ROXRD", 0xE030, 0xF138, 2, 6, -1, 0, -1, 9, "o-----------", "o-----------", GenROXRD }, + { "RORD", 0xE038, 0xF138, 2, 6, -1, 0, -1, 9, "o-----------", "o-----------", GenRORD }, + { "ASLD", 0xE120, 0xF138, 2, 6, -1, 0, -1, 9, "o-----------", "o-----------", GenASLD }, + { "LSLD", 0xE128, 0xF138, 2, 6, -1, 0, -1, 9, "o-----------", "o-----------", GenLSLD }, + { "ROXLD", 0xE130, 0xF138, 2, 6, -1, 0, -1, 9, "o-----------", "o-----------", GenROXLD }, + { "ROLD", 0xE138, 0xF138, 2, 6, -1, 0, -1, 9, "o-----------", "o-----------", GenROLD }, + + { "ASR", 0xE0C0, 0xFFC0, 0, 0, 3, 0, -1, -1, "--ooooooo---", "------------", GenASR }, + { "LSR", 0xE2C0, 0xFFC0, 0, 0, 3, 0, -1, -1, "--ooooooo---", "------------", GenLSR }, + { "ROXR", 0xE4C0, 0xFFC0, 0, 0, 3, 0, -1, -1, "--ooooooo---", "------------", GenROXR }, + { "ROR", 0xE6C0, 0xFFC0, 0, 0, 3, 0, -1, -1, "--ooooooo---", "------------", GenROR }, + { "ASL", 0xE1C0, 0xFFC0, 0, 0, 3, 0, -1, -1, "--ooooooo---", "------------", GenASL }, + { "LSL", 0xE3C0, 0xFFC0, 0, 0, 3, 0, -1, -1, "--ooooooo---", "------------", GenLSL }, + { "ROXL", 0xE5C0, 0xFFC0, 0, 0, 3, 0, -1, -1, "--ooooooo---", "------------", GenROXL }, + { "ROL", 0xE7C0, 0xFFC0, 0, 0, 3, 0, -1, -1, "--ooooooo---", "------------", GenROL } + +#ifdef NEOCD_HLE + , + { "0xFABE", 0xFABE, 0xFFFF, 0, 0, -1, -1, -1, -1, "------------", "------------", Gen0xFABE }, + { "0xFABF", 0xFABF, 0xFFFF, 0, 0, -1, -1, -1, -1, "------------", "------------", Gen0xFABF }, + { "0xFAC0", 0xFAC0, 0xFFFF, 0, 0, -1, -1, -1, -1, "------------", "------------", Gen0xFAC0 }, + { "0xFAC1", 0xFAC1, 0xFFFF, 0, 0, -1, -1, -1, -1, "------------", "------------", Gen0xFAC1 }, + { "0xFAC2", 0xFAC2, 0xFFFF, 0, 0, -1, -1, -1, -1, "------------", "------------", Gen0xFAC2 }, + { "0xFAC3", 0xFAC3, 0xFFFF, 0, 0, -1, -1, -1, -1, "------------", "------------", Gen0xFAC3 } +#endif +}; + +#ifndef C68K_NO_JUMP_TABLE +#ifdef C68K_CONST_JUMP_TABLE +static u16 op_jump_table[0x10000]; +#endif +#endif + +// files where code is generated +static FILE* ini_file = NULL; +static FILE* opcode_file = NULL; + +// current generated instruction infos +static c68k_op_info_struc *current_op; +static u32 current_ea; +static u32 current_eam; +static u32 current_reg; +static u32 current_ea2; +static u32 current_eam2; +static u32 current_reg2; +static u32 current_size; +static u32 current_cycle; +static u32 current_io_sav; + +static char current_cond_char[128]; + +static char szc[20]; +static char szcs[20]; +static char szcf[20]; +static char szcsf[20]; + +static u32 current_bits_mask; +static u8 current_sft_mask; + +#define EA_DREG 0 +#define EA_AREG 1 +#define EA_AIND 2 +#define EA_AINC 3 +#define EA_ADEC 4 +#define EA_D16A 5 +#define EA_D8AX 6 +#define EA_A16 7 +#define EA_A32 8 +#define EA_D16P 9 +#define EA_D8PX 10 +#define EA_IMM 11 +#define EA_AINC7 12 +#define EA_ADEC7 13 +#define EA_ILLEGAL 15 + +static const u32 jmp_jsr_cycle_table[16] = +{ + 0, 0, + 4, + 0, + 0, + 6, + 10, + 6, + 8, + 6, + 10, + 0, 0, 0, 0 +}; + +static const u32 lea_pea_cycle_table[16] = +{ + 0, 0, + 0, + 0, + 0, + 4, + 8, + 4, + 8, + 4, + 8, + 0, 0, 0, 0 +}; + +static const u32 movem_cycle_table[16] = +{ + 0, 0, + 0, + 0, + 0, + 4, + 6, + 4, + 8, + 4, + 6, + 0, 0, 0, 0 +}; + +// general emitter function +//////////////////////////// + +static u32 prepare_generate(void) +{ + char filename[32]; + + sprintf(filename, "c68k_op%.1X.inc", (current_op->op_base >> 12) & 0xF); + if (opcode_file != NULL) + { + fclose(opcode_file); + opcode_file = NULL; + } + opcode_file = fopen(filename, "at"); + if (opcode_file == NULL) + { + printf("Can't open %s\n", filename); + return 1; + } + return 0; +} + +static void wf_op(char* fmt, ...) +{ + va_list args; + + if (opcode_file == NULL) return; + + va_start(args, fmt); + vfprintf(opcode_file, fmt, args); + va_end(args); +} + +static void gen_jumptable(u32 base, u32 start1, u32 end1, u32 step1, u32 start2, u32 end2, u32 step2, u32 start3, u32 end3, u32 step3, u32 op) +{ +#ifdef C68K_CONST_JUMP_TABLE + u32 i, j, k; +#endif +#ifdef C68K_NO_JUMP_TABLE + u32 i, j, k; +#endif + + + base &= 0xFFFF; + start1 &= 0xFFFF; + end1 &= 0xFFFF; + step1 &= 0xFFFF; + if (end1 < start1) end1 = start1; + start2 &= 0xFFFF; + end2 &= 0xFFFF; + step2 &= 0xFFFF; + if (end2 < start2) end2 = start2; + op &= 0xFFFF; + +#ifndef C68K_NO_JUMP_TABLE +#ifdef C68K_CONST_JUMP_TABLE + if (step1 == 0) step1 = 1; + if (step2 == 0) step2 = 1; + if (step3 == 0) step3 = 1; + + for(i = start1; i <= end1; i += step1) + for(j = start2; j <= end2; j += step2) + for(k = start3; k <= end3; k += step3) + op_jump_table[base + i + j + k] = op; + +#else + if (ini_file == NULL) return; + + if (start1 != end1) + { + fprintf(ini_file, "\t\tfor(i = 0x%.4X; i <= 0x%.4X; i += 0x%.4X)\n", (int)start1, (int)end1, (int)step1); + if (start2 != end2) + { + fprintf(ini_file, "\t\t\tfor(j = 0x%.4X; j <= 0x%.4X; j += 0x%.4X)\n\t", (int)start2, (int)end2, (int)step2); + if (start3 != end3) + { + fprintf(ini_file, "\t\t\t\tfor(k = 0x%.4X; k <= 0x%.4X; k += 0x%.4X)\n\t", (int)start3, (int)end3, (int)step3); + fprintf(ini_file, "\t\t\t\t\tJumpTable[0x%.4X + i + j + k] = &&OP_0x%.4X;\n", (int)base, (int)op); + } + else fprintf(ini_file, "\t\t\t\tJumpTable[0x%.4X + i + j] = &&OP_0x%.4X;\n", (int)base, (int)op); + } + else fprintf(ini_file, "\t\t\tJumpTable[0x%.4X + i] = &&OP_0x%.4X;\n", (int)base, (int)op); + } + else fprintf(ini_file, "\t\tJumpTable[0x%.4X] = &&OP_0x%.4X;\n", (int)base, (int)op); +#endif +#else + if (step1 == 0) step1 = 1; + if (step2 == 0) step2 = 1; + if (step3 == 0) step3 = 1; + + for(i = start1; i <= end1; i += step1) + for(j = start2; j <= end2; j += step2) + for(k = start3; k <= end3; k += step3) + { + u32 temp=(base + i + j + k); + if (temp != op && temp != 0x4E57 && temp != 0x4E5F) + wf_op("case 0x%.4X:\n", base + i + j + k); + } +#endif +} + +static void gen_opjumptable_ext(u32 base, u32 start3, u32 end3, u32 step3, u32 op) +{ + u32 start1, end1, step1, start2, end2, step2; + + start1 = end1 = step1 = 0; + start2 = end2 = step2 = 0; + + if ((current_op->reg_sft != -1) && (current_ea < 7)) + { + if ((current_ea == EA_AINC) || (current_ea == EA_ADEC)) end1 = 6 << current_op->reg_sft; + else end1 = 7 << current_op->reg_sft; + step1 = 1 << current_op->reg_sft; + } + if ((current_op->reg2_sft != -1) && (current_ea2 < 7)) + { + if ((current_ea2 == EA_AINC) || (current_ea2 == EA_ADEC)) end2 = 6 << current_op->reg2_sft; + else end2 = 7 << current_op->reg2_sft; + step2 = 1 << current_op->reg2_sft; + } + + if (start1 != end1) + { + if (start2 != end2) gen_jumptable(base, start1, end1, step1, start2, end2, step2, start3, end3, step3, op); + else gen_jumptable(base, start1, end1, step1, start3, end3, step3, start2, end2, step2, op); + } + else if (start2 != end2) gen_jumptable(base, start2, end2, step2, start3, end3, step3, start1, end1, step1, op); + else gen_jumptable(base, start3, end3, step3, start2, end2, step2, start1, end1, step1, op); +} + +static void gen_opjumptable(u32 op) +{ + gen_opjumptable_ext(op, 0, 0, 0, op); +} + +#define GEN_ADR 1 +#define GEN_RES 2 +#define GEN_SRC 4 +#define GEN_DST 8 +#define GEN_ALL 15 + +static void start_op(u32 op, int v) +{ + current_io_sav = 0; + current_cycle = 0; + + wf_op("\n// %s\n", current_op->op_name); +#ifndef C68K_NO_JUMP_TABLE + wf_op("OP_0x%.4X:\n", op & 0xFFFF); +#else + wf_op("case 0x%.4X:\n", op & 0xFFFF); +#endif + wf_op("{\n"); + if (v & GEN_ADR) wf_op("\tu32 adr;\n"); + if (v & GEN_RES) wf_op("\tu32 res;\n"); + if (v & GEN_DST) wf_op("\tpointer dst;\n"); + if (v & GEN_SRC) wf_op("\tpointer src;\n"); +} + +static void add_CCnt(u32 cycle) +{ + if (current_io_sav) wf_op("\tPOST_IO\n"); + current_io_sav = 0; + wf_op("\tCCnt -= %d;\n", cycle); +} + +static void adds_CCnt(char *str) +{ + if (current_io_sav) wf_op("\tPOST_IO\n"); + current_io_sav = 0; + wf_op("\tCCnt -= %s;\n", str); +} + +#if 0 // FIXME: warning removal +static void sub_CCnt(u32 cycle) +{ + if (current_io_sav) wf_op("\tPOST_IO\n"); + current_io_sav = 0; + wf_op("\tCCnt += %d;\n", cycle); +} + +static void subs_CCnt(char *str) +{ + if (current_io_sav) wf_op("\tPOST_IO\n"); + current_io_sav = 0; + wf_op("\tCCnt += %s;\n", str); +} + +static void quick_fterminate_op(u32 cycle) +{ + if (current_io_sav) wf_op("\tPOST_IO\n"); + current_io_sav = 0; + wf_op("\tCCnt -= %d;\n", current_cycle + cycle); + wf_op("\tgoto C68k_Exec_End;\n"); +} +#endif + +static void fterminate_op(u32 cycle) +{ + wf_op("}\n"); + if (current_io_sav) wf_op("POST_IO\n"); + current_io_sav = 0; + wf_op("CCnt -= %d;\n", current_cycle + cycle); + wf_op("goto C68k_Exec_End;\n"); +} + +static void quick_terminate_op(u32 cycle) +{ + if (current_io_sav) wf_op("\tPOST_IO\n"); + current_io_sav = 0; + wf_op("\tRET(%d)\n", current_cycle + cycle); +} + +static void terminate_op(u32 cycle) +{ + if (current_io_sav) wf_op("\tPOST_IO\n"); + wf_op("}\n"); + current_io_sav = 0; + wf_op("RET(%d)\n", current_cycle + cycle); +} + +static void do_pre_io(void) +{ + if (!current_io_sav) fprintf(opcode_file, "\tPRE_IO\n"); + current_io_sav = 1; +} + +static void mem_op(char* fmt, ...) +{ + va_list args; + + if (opcode_file == NULL) return; + + do_pre_io(); + + va_start(args, fmt); + vfprintf(opcode_file, fmt, args); + va_end(args); +} + +// flag emitter function +///////////////////////// + +static void set_logic_flag(void) +{ + wf_op("\tCPU->flag_C = 0;\n"); + wf_op("\tCPU->flag_V = 0;\n"); + wf_op("\tCPU->flag_notZ = res;\n"); + switch(current_size) + { + case SIZE_BYTE: + wf_op("\tCPU->flag_N = res;\n"); + break; + + case SIZE_WORD: + wf_op("\tCPU->flag_N = res >> 8;\n"); + break; + + case SIZE_LONG: + wf_op("\tCPU->flag_N = res >> 24;\n"); + break; + } +} + +static void set_logicl_flag(void) +{ + wf_op("\tCPU->flag_C = 0;\n"); + wf_op("\tCPU->flag_V = 0;\n"); + switch(current_size) + { + case SIZE_BYTE: + wf_op("\tCPU->flag_N = res;\n"); + wf_op("\tCPU->flag_notZ = res & 0xFF;\n"); + break; + + case SIZE_WORD: + wf_op("\tCPU->flag_notZ = res & 0xFFFF;\n"); + wf_op("\tCPU->flag_N = res >> 8;\n"); + break; + + case SIZE_LONG: + wf_op("\tCPU->flag_notZ = res;\n"); + wf_op("\tCPU->flag_N = res >> 24;\n"); + break; + } +} + +static void set_add_flag(void) +{ + switch(current_size) + { + case SIZE_BYTE: + wf_op("\tCPU->flag_N = CPU->flag_X = CPU->flag_C = res;\n"); + wf_op("\tCPU->flag_V = (src ^ res) & (dst ^ res);\n"); + wf_op("\tCPU->flag_notZ = res & 0xFF;\n"); + break; + + case SIZE_WORD: + wf_op("\tCPU->flag_V = ((src ^ res) & (dst ^ res)) >> 8;\n"); + wf_op("\tCPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8;\n"); + wf_op("\tCPU->flag_notZ = res & 0xFFFF;\n"); + break; + + case SIZE_LONG: + wf_op("\tCPU->flag_notZ = res;\n"); + wf_op("\tCPU->flag_X = CPU->flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23;\n"); +// wf_op("\tCPU->flag_X = CPU->flag_C = ((src & dst) | (~res & (src | dst))) >> 23;\n"); + wf_op("\tCPU->flag_V = ((src ^ res) & (dst ^ res)) >> 24;\n"); + wf_op("\tCPU->flag_N = res >> 24;\n"); + break; + } +} + +static void set_addx_flag(void) +{ + switch(current_size) + { + case SIZE_BYTE: + wf_op("\tCPU->flag_N = CPU->flag_X = CPU->flag_C = res;\n"); + wf_op("\tCPU->flag_V = (src ^ res) & (dst ^ res);\n"); + wf_op("\tCPU->flag_notZ |= res & 0xFF;\n"); + break; + + case SIZE_WORD: + wf_op("\tCPU->flag_V = ((src ^ res) & (dst ^ res)) >> 8;\n"); + wf_op("\tCPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8;\n"); + wf_op("\tCPU->flag_notZ |= res & 0xFFFF;\n"); + break; + + case SIZE_LONG: + wf_op("\tCPU->flag_notZ |= res;\n"); + wf_op("\tCPU->flag_X = CPU->flag_C = ((src & dst & 1) + (src >> 1) + (dst >> 1)) >> 23;\n"); +// wf_op("\tCPU->flag_X = CPU->flag_C = ((src & dst) | (~res & (src | dst))) >> 23;\n"); + wf_op("\tCPU->flag_V = ((src ^ res) & (dst ^ res)) >> 24;\n"); + wf_op("\tCPU->flag_N = res >> 24;\n"); + break; + } +} + +static void set_sub_flag(void) +{ + switch(current_size) + { + case SIZE_BYTE: + wf_op("\tCPU->flag_N = CPU->flag_X = CPU->flag_C = res;\n"); + wf_op("\tCPU->flag_V = (src ^ dst) & (res ^ dst);\n"); + wf_op("\tCPU->flag_notZ = res & 0xFF;\n"); + break; + + case SIZE_WORD: + wf_op("\tCPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8;\n"); + wf_op("\tCPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8;\n"); + wf_op("\tCPU->flag_notZ = res & 0xFFFF;\n"); + break; + + case SIZE_LONG: + wf_op("\tCPU->flag_notZ = res;\n"); + wf_op("\tCPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23;\n"); +// wf_op("\tCPU->flag_X = CPU->flag_C = ((src & res) | (~dst & (src | res))) >> 23;\n"); + wf_op("\tCPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24;\n"); + wf_op("\tCPU->flag_N = res >> 24;\n"); + break; + } +} + +static void set_subx_flag(void) +{ + switch(current_size) + { + case SIZE_BYTE: + wf_op("\tCPU->flag_N = CPU->flag_X = CPU->flag_C = res;\n"); + wf_op("\tCPU->flag_V = (src ^ dst) & (res ^ dst);\n"); + wf_op("\tCPU->flag_notZ |= res & 0xFF;\n"); + break; + + case SIZE_WORD: + wf_op("\tCPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8;\n"); + wf_op("\tCPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8;\n"); + wf_op("\tCPU->flag_notZ |= res & 0xFFFF;\n"); + break; + + case SIZE_LONG: + wf_op("\tCPU->flag_notZ |= res;\n"); + wf_op("\tCPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23;\n"); +// wf_op("\tCPU->flag_X = CPU->flag_C = ((src & res) | (~dst & (src | res))) >> 23;\n"); + wf_op("\tCPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24;\n"); + wf_op("\tCPU->flag_N = res >> 24;\n"); + break; + } +} + +static void set_cmp_flag(void) +{ + switch(current_size) + { + case SIZE_BYTE: + wf_op("\tCPU->flag_N = CPU->flag_C = res;\n"); + wf_op("\tCPU->flag_V = (src ^ dst) & (res ^ dst);\n"); + wf_op("\tCPU->flag_notZ = res & 0xFF;\n"); + break; + + case SIZE_WORD: + wf_op("\tCPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 8;\n"); + wf_op("\tCPU->flag_N = CPU->flag_C = res >> 8;\n"); + wf_op("\tCPU->flag_notZ = res & 0xFFFF;\n"); + break; + + case SIZE_LONG: + wf_op("\tCPU->flag_notZ = res;\n"); + wf_op("\tCPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23;\n"); +// wf_op("\tCPU->flag_C = ((src & res) | (~dst & (src | res))) >> 23;\n"); + wf_op("\tCPU->flag_V = ((src ^ dst) & (res ^ dst)) >> 24;\n"); + wf_op("\tCPU->flag_N = res >> 24;\n"); + break; + } +} + +static void set_negx_flag(void) +{ + switch(current_size) + { + case SIZE_BYTE: + wf_op("\tCPU->flag_V = res & src;\n"); + wf_op("\tCPU->flag_N = CPU->flag_X = CPU->flag_C = res;\n"); + wf_op("\tCPU->flag_notZ |= res & 0xFF;\n"); + break; + + case SIZE_WORD: + wf_op("\tCPU->flag_V = (res & src) >> 8;\n"); + wf_op("\tCPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8;\n"); + wf_op("\tCPU->flag_notZ |= res & 0xFFFF;\n"); + break; + + case SIZE_LONG: + wf_op("\tCPU->flag_notZ |= res;\n"); + wf_op("\tCPU->flag_V = (res & src) >> 24;\n"); + wf_op("\tCPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23;\n"); +// wf_op("\tCPU->flag_X = CPU->flag_C = ((src & res) | (~dst & (src | res))) >> 23;\n"); + wf_op("\tCPU->flag_N = res >> 24;\n"); + break; + } +} + +static void set_neg_flag(void) +{ + switch(current_size) + { + case SIZE_BYTE: + wf_op("\tCPU->flag_V = res & src;\n"); + wf_op("\tCPU->flag_N = CPU->flag_X = CPU->flag_C = res;\n"); + wf_op("\tCPU->flag_notZ = res & 0xFF;\n"); + break; + + case SIZE_WORD: + wf_op("\tCPU->flag_V = (res & src) >> 8;\n"); + wf_op("\tCPU->flag_N = CPU->flag_X = CPU->flag_C = res >> 8;\n"); + wf_op("\tCPU->flag_notZ = res & 0xFFFF;\n"); + break; + + case SIZE_LONG: + wf_op("\tCPU->flag_notZ = res;\n"); + wf_op("\tCPU->flag_V = (res & src) >> 24;\n"); + wf_op("\tCPU->flag_X = CPU->flag_C = ((src & res & 1) + (src >> 1) + (res >> 1)) >> 23;\n"); +// wf_op("\tCPU->flag_X = CPU->flag_C = ((src & res) | (~dst & (src | res))) >> 23;\n"); + wf_op("\tCPU->flag_N = res >> 24;\n"); + break; + } +} + +static char* get_cond_as_cond(u32 cond, u32 notvar) +{ + if (notvar) cond ^= 1; + + switch(cond) + { + case COND_TR: + sprintf(current_cond_char, "(1)"); + break; + + case COND_FA: + sprintf(current_cond_char, "(0)"); + break; + + case COND_HI: + sprintf(current_cond_char, "(CPU->flag_notZ && (!(CPU->flag_C & 0x100)))"); + break; + + case COND_LS: + sprintf(current_cond_char, "((!CPU->flag_notZ) || (CPU->flag_C & 0x100))"); + break; + + case COND_CC: + sprintf(current_cond_char, "(!(CPU->flag_C & 0x100))"); + break; + + case COND_CS: + sprintf(current_cond_char, "(CPU->flag_C & 0x100)"); + break; + + case COND_NE: + sprintf(current_cond_char, "(CPU->flag_notZ)"); + break; + + case COND_EQ: + sprintf(current_cond_char, "(!CPU->flag_notZ)"); + break; + + case COND_VC: + sprintf(current_cond_char, "(!(CPU->flag_V & 0x80))"); + break; + + case COND_VS: + sprintf(current_cond_char, "(CPU->flag_V & 0x80)"); + break; + + case COND_PL: + sprintf(current_cond_char, "(!(CPU->flag_N & 0x80))"); + break; + + case COND_MI: + sprintf(current_cond_char, "(CPU->flag_N & 0x80)"); + break; + + case COND_GE: + sprintf(current_cond_char, "(!((CPU->flag_N ^ CPU->flag_V) & 0x80))"); + break; + + case COND_LT: + sprintf(current_cond_char, "((CPU->flag_N ^ CPU->flag_V) & 0x80)"); + break; + + case COND_GT: + sprintf(current_cond_char, "(CPU->flag_notZ && (!((CPU->flag_N ^ CPU->flag_V) & 0x80)))"); + break; + + case COND_LE: + sprintf(current_cond_char, "((!CPU->flag_notZ) || ((CPU->flag_N ^ CPU->flag_V) & 0x80))"); + break; + } + + return current_cond_char; +} + +// effective address related function +////////////////////////////////////// + +static u32 has_ea(u32 ea) +{ + if (ea == EA_AINC7) return (current_op->ea_supported[EA_AINC] == 'o'); + if (ea == EA_ADEC7) return (current_op->ea_supported[EA_ADEC] == 'o'); + if (ea <= EA_IMM) return (current_op->ea_supported[ea] == 'o'); + return 0; +} + +static u32 has_ea2(u32 ea) +{ + if (ea == EA_AINC7) return (current_op->ea2_supported[EA_AINC] == 'o'); + if (ea == EA_ADEC7) return (current_op->ea2_supported[EA_ADEC] == 'o'); + if (ea <= EA_IMM) return (current_op->ea2_supported[ea] == 'o'); + return 0; +} + +#if 0 // FIXME: warning removal +static u32 _eamreg_to_ea(u32 eam, u32 reg) +{ + if ((eam > 7) || (reg > 7)) return EA_ILLEGAL; + if ((eam == 3) && (reg == 7)) return EA_AINC7; + if ((eam == 4) && (reg == 7)) return EA_ADEC7; + if (eam != 7) return eam; + if (reg < 5) return (eam + reg); + return EA_ILLEGAL; +} +#endif + +static u32 _ea_to_eamreg(u32 ea) +{ + if (ea < 7) return (ea << 3) | 0; + if (ea == EA_AINC7) return (EA_AINC << 3) | 7; + if (ea == EA_ADEC7) return (EA_ADEC << 3) | 7; + if (ea <= EA_IMM) return (7 << 3) | (ea - 7); + return (7 << 3) | 7; +} + +static u32 is_ea_memory(u32 ea) +{ + if ((ea > EA_AREG) && (ea != EA_IMM)) return 1; + else return 0; +} + +static void _ea_calc_free(u32 ea, u32 rsft) +{ + u32 step; + + step = 0; + switch (current_size) + { + case SIZE_BYTE: + if ((ea == EA_AINC7) || (ea == EA_ADEC7)) step = 2; + else step = 1; + break; + + case SIZE_WORD: + step = 2; + break; + + case SIZE_LONG: + step = 4; + break; + } + + switch (ea) + { + case EA_DREG: +// wf_op("\tadr = (u32)(&CPU->D[(Opcode >> %d) & 7]);\n", rsft); + break; + + case EA_AREG: +// wf_op("\tadr = (u32)(&CPU->A[(Opcode >> %d) & 7]);\n", rsft); + break; + + case EA_AIND: + wf_op("\tadr = CPU->A[(Opcode >> %d) & 7];\n", rsft); + break; + + case EA_AINC: + wf_op("\tadr = CPU->A[(Opcode >> %d) & 7];\n", rsft); + wf_op("\tCPU->A[(Opcode >> %d) & 7] += %d;\n", rsft, step); + break; + + case EA_AINC7: + wf_op("\tadr = CPU->A[7];\n"); + wf_op("\tCPU->A[7] += %d;\n", step); + break; + + case EA_ADEC: + wf_op("\tadr = CPU->A[(Opcode >> %d) & 7] - %d;\n", rsft, step); + wf_op("\tCPU->A[(Opcode >> %d) & 7] = adr;\n", rsft); + break; + + case EA_ADEC7: + wf_op("\tadr = CPU->A[7] - %d;\n", step); + wf_op("\tCPU->A[7] = adr;\n"); + break; + + case EA_D16A: + wf_op("\tadr = CPU->A[(Opcode >> %d) & 7] + (s32)(s16)FETCH_WORD;\n", rsft); + wf_op("\tPC += 2;\n"); + break; + + case EA_D8AX: + wf_op("\tadr = CPU->A[(Opcode >> %d) & 7];\n", rsft); + wf_op("\tDECODE_EXT_WORD\n"); + break; + + case EA_A16: + wf_op("\tadr = (s32)(s16)FETCH_WORD;\n"); + wf_op("\tPC += 2;\n"); + break; + + case EA_A32: + wf_op("\tadr = (s32)FETCH_LONG;\n"); + wf_op("\tPC += 4;\n"); + break; + + case EA_D16P: + wf_op("\tadr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD;\n"); + wf_op("\tPC += 2;\n"); + break; + + case EA_D8PX: + wf_op("\tadr = PC - CPU->BasePC;\n"); + wf_op("\tDECODE_EXT_WORD\n"); + break; + } +} + +static void _ea_calc(u32 ea, u32 rsft) +{ + u32 step; + u32 cycle_sft; + + step = 0; + cycle_sft = 0; + switch (current_size) + { + case SIZE_BYTE: + if ((ea == EA_AINC7) || (ea == EA_ADEC7)) step = 2; + else step = 1; + break; + + case SIZE_WORD: + step = 2; + break; + + case SIZE_LONG: + cycle_sft = 1; + step = 4; + break; + } + + switch (ea) + { + case EA_DREG: +// wf_op("\tadr = (u32)(&CPU->D[(Opcode >> %d) & 7]);\n", rsft); + break; + + case EA_AREG: +// wf_op("\tadr = (u32)(&CPU->A[(Opcode >> %d) & 7]);\n", rsft); + break; + + case EA_IMM: + current_cycle += (4 << cycle_sft) + 0; + break; + + case EA_AIND: + current_cycle += (4 << cycle_sft) + 0; + wf_op("\tadr = CPU->A[(Opcode >> %d) & 7];\n", rsft); + break; + + case EA_AINC: + current_cycle += (4 << cycle_sft) + 0; + wf_op("\tadr = CPU->A[(Opcode >> %d) & 7];\n", rsft); + wf_op("\tCPU->A[(Opcode >> %d) & 7] += %d;\n", rsft, step); + break; + + case EA_AINC7: + current_cycle += (4 << cycle_sft) + 0; + wf_op("\tadr = CPU->A[7];\n"); + wf_op("\tCPU->A[7] += %d;\n", step); + break; + + case EA_ADEC: + current_cycle += (4 << cycle_sft) + 2; + wf_op("\tadr = CPU->A[(Opcode >> %d) & 7] - %d;\n", rsft, step); + wf_op("\tCPU->A[(Opcode >> %d) & 7] = adr;\n", rsft); + break; + + case EA_ADEC7: + current_cycle += (4 << cycle_sft) + 2; + wf_op("\tadr = CPU->A[7] - %d;\n", step); + wf_op("\tCPU->A[7] = adr;\n"); + break; + + case EA_D16A: + current_cycle += (4 << cycle_sft) + 4; + wf_op("\tadr = CPU->A[(Opcode >> %d) & 7] + (s32)(s16)FETCH_WORD;\n", rsft); + wf_op("\tPC += 2;\n"); + break; + + case EA_D8AX: + current_cycle += (4 << cycle_sft) + 6; + wf_op("\tadr = CPU->A[(Opcode >> %d) & 7];\n", rsft); + wf_op("\tDECODE_EXT_WORD\n"); + break; + + case EA_A16: + current_cycle += (4 << cycle_sft) + 4; + wf_op("\tadr = (s32)(s16)FETCH_WORD;\n"); + wf_op("\tPC += 2;\n"); + break; + + case EA_A32: + current_cycle += (4 << cycle_sft) + 8; + wf_op("\tadr = (s32)FETCH_LONG;\n"); + wf_op("\tPC += 4;\n"); + break; + + case EA_D16P: + current_cycle += (4 << cycle_sft) + 4; + wf_op("\tadr = (PC - CPU->BasePC) + (s32)(s16)FETCH_WORD;\n"); + wf_op("\tPC += 2;\n"); + break; + + case EA_D8PX: + current_cycle += (4 << cycle_sft) + 6; + wf_op("\tadr = PC - CPU->BasePC;\n"); + wf_op("\tDECODE_EXT_WORD\n"); + break; + } +} + +static void _ea_read_(u32 ea, u32 rsft, char dest[4]) +{ + char sz[8]; + + switch (current_size) + { + case SIZE_BYTE: + strcpy(sz, "BYTE"); + break; + + case SIZE_WORD: + strcpy(sz, "WORD"); + break; + + case SIZE_LONG: + strcpy(sz, "LONG"); + break; + } + + switch (ea) + { + case EA_DREG: + wf_op("\t%s = (%s)CPU->D[(Opcode >> %d) & 7];\n", dest, szc, rsft); + break; + + case EA_AREG: + if (current_size == SIZE_BYTE) + { + wf_op("\t// can't read byte from Ax registers !\n"); + wf_op("\tCPU->Status |= C68K_FAULTED;\n"); + wf_op("\tCCnt = 0;\n"); + wf_op("\tgoto C68k_Exec_Really_End;\n"); + } + else wf_op("\t%s = (%s)CPU->A[(Opcode >> %d) & 7];\n", dest, szc, rsft); + break; +/* + case EA_DREG: + case EA_AREG: + wf_op("\t%s = %s(adr);\n", dest, szcf); + break; +*/ + case EA_A32: + case EA_D8AX: + case EA_D8PX: + case EA_D16A: + case EA_D16P: + case EA_A16: + case EA_ADEC: + case EA_ADEC7: + case EA_AIND: + case EA_AINC: + case EA_AINC7: + mem_op("\tREAD_%s_F(adr, %s)\n", sz, dest); + break; + + case EA_IMM: + switch (current_size) + { + case SIZE_BYTE: + wf_op("\t%s = FETCH_BYTE;\n", dest); + wf_op("\tPC += 2;\n"); + break; + + case SIZE_WORD: + wf_op("\t%s = FETCH_WORD;\n", dest); + wf_op("\tPC += 2;\n"); + break; + + case SIZE_LONG: + wf_op("\t%s = FETCH_LONG;\n", dest); + wf_op("\tPC += 4;\n"); + break; + } + break; + } +} + +static void _ea_read(u32 ea, u32 rsft) +{ + _ea_read_(ea, rsft, "res"); +} + +static void _ea_read_src(u32 ea, u32 rsft) +{ + _ea_read_(ea, rsft, "src"); +} + +static void _ea_read_dst(u32 ea, u32 rsft) +{ + _ea_read_(ea, rsft, "dst"); +} + +static void _ea_read_sx_(u32 ea, u32 rsft, char dest[4]) +{ + char sz[8]; + + switch (current_size) + { + case SIZE_BYTE: + strcpy(sz, "BYTE"); + break; + + case SIZE_WORD: + strcpy(sz, "WORD"); + break; + + case SIZE_LONG: + strcpy(sz, "LONG"); + break; + } + + switch (ea) + { + case EA_DREG: + wf_op("\t%s = (s32)(%s)CPU->D[(Opcode >> %d) & 7];\n", dest, szcs, rsft); + break; + + case EA_AREG: + if (current_size == SIZE_BYTE) + { + wf_op("\t// can't read byte from Ax registers !\n"); + wf_op("\tCPU->Status |= C68K_FAULTED;\n"); + wf_op("\tCCnt = 0;\n"); + wf_op("\tgoto C68k_Exec_Really_End;\n"); + } + else wf_op("\t%s = (s32)(%s)CPU->A[(Opcode >> %d) & 7];\n", dest, szcs, rsft); + break; +/* + case EA_DREG: + case EA_AREG: + wf_op("\t%s = (s32)(%s(adr));\n", dest, szcsf); + break; +*/ + case EA_A32: + case EA_D8AX: + case EA_D8PX: + case EA_D16A: + case EA_D16P: + case EA_A16: + case EA_ADEC: + case EA_ADEC7: + case EA_AIND: + case EA_AINC: + case EA_AINC7: + mem_op("\tREADSX_%s_F(adr, %s)\n", sz, dest); + break; + + case EA_IMM: + switch (current_size) + { + case SIZE_BYTE: + wf_op("\t%s = (s32)(%s(PC)));\n", dest, szcsf); + wf_op("\tPC += 2;\n"); + break; + + case SIZE_WORD: + wf_op("\t%s = (s32)(%s)FETCH_WORD;\n", dest, szcs); + wf_op("\tPC += 2;\n"); + break; + + case SIZE_LONG: + wf_op("\t%s = (s32)(%s)FETCH_LONG;\n", dest, szcs); + wf_op("\tPC += 4;\n"); + break; + } + break; + } +} + +static void _ea_read_sx(u32 ea, u32 rsft) +{ + _ea_read_sx_(ea, rsft, "res"); +} + +static void _ea_read_src_sx(u32 ea, u32 rsft) +{ + _ea_read_sx_(ea, rsft, "src"); +} + +static void _ea_write(u32 ea, u32 rsft) +{ + char sz[8]; + + switch (current_size) + { + case SIZE_BYTE: + strcpy(sz, "BYTE"); + break; + + case SIZE_WORD: + strcpy(sz, "WORD"); + break; + + case SIZE_LONG: + strcpy(sz, "LONG"); + break; + } + + switch (ea) + { + case EA_DREG: + wf_op("\t%s(&CPU->D[(Opcode >> %d) & 7])) = res;\n", szcf, +rsft); + break; + + case EA_AREG: + // writes in Ax registers are always 32 bits sized + wf_op("\tCPU->A[(Opcode >> %d) & 7] = res;\n", rsft); + break; +/* + case EA_DREG: + case EA_AREG: + wf_op("\t%s(adr) = res;\n", szcf); + break; +*/ + case EA_A32: + case EA_D8AX: + case EA_D8PX: + case EA_D16A: + case EA_D16P: + case EA_A16: + case EA_ADEC: + case EA_ADEC7: + case EA_AIND: + case EA_AINC: + case EA_AINC7: + mem_op("\tWRITE_%s_F(adr, res)\n", sz); + break; + } +} + +// misc function +///////////////// + +static u32 get_current_opcode_base(void) +{ + u32 base; + + base = current_op->op_base; + if (current_op->eam_sft != -1) base += (current_eam & 7) << current_op->eam_sft; + if (current_op->reg_sft != -1) base += (current_reg & 7) << current_op->reg_sft; + if (current_op->eam2_sft != -1) base += (current_eam2 & 7) << current_op->eam2_sft; + if (current_op->reg2_sft != -1) base += (current_reg2 & 7) << current_op->reg2_sft; + if (current_op->size_type == 1) base += (current_size - 1) << current_op->size_sft; + else if (current_op->size_type == 2) base += (current_size & 3) << current_op->size_sft; + + return base; +} + +static void start_all(int v) +{ + u32 base; + + base = get_current_opcode_base(); + + // generate jump table + gen_opjumptable(base); + + // generate label & declarations + start_op(base, v); +} + +static void set_current_size(u32 sz) +{ + current_size = sz; + switch(current_size) + { + case SIZE_BYTE: + current_bits_mask = 0xFF; + current_sft_mask = 7; + strcpy(szc, "u8"); + strcpy(szcf, "*(BYTE_OFF + (u8*)"); + strcpy(szcs, "s8"); + strcpy(szcsf, "*(BYTE_OFF + (s8*)"); + break; + + case SIZE_WORD: + current_bits_mask = 0xFFFF; + current_sft_mask = 15; + strcpy(szc, "u16"); + strcpy(szcf, "*(WORD_OFF + (u16*)"); + strcpy(szcs, "s16"); + strcpy(szcsf, "*(WORD_OFF + (s16*)"); + break; + + case SIZE_LONG: + current_bits_mask = 0xFFFFFFFF; + current_sft_mask = 31; + strcpy(szc, "u32"); + strcpy(szcf, "*((u32*)"); + strcpy(szcs, "s32"); + strcpy(szcsf, "*((s32*)"); + break; + } +} + +// gen privilege exception (happen when S flag is not set) +static void gen_privilege_exception(char *pre) +{ + // swap A7 and USP (because S not set) + wf_op("%sres = CPU->USP;\n", pre); + wf_op("%sCPU->USP = CPU->A[7];\n", pre); + wf_op("%sCPU->A[7] = res;\n", pre); + + // get vector & add cycle + wf_op("%sres = C68K_PRIVILEGE_VIOLATION_EX;\n", pre); + adds_CCnt("c68k_exception_cycle_table[res]"); + + // we will do some mem/io access + do_pre_io(); + + // push PC and SR + mem_op("%sPUSH_32_F(PC - CPU->BasePC)\n", pre); + mem_op("%sPUSH_16_F(GET_SR)\n", pre); + + // adjust SR + wf_op("%sCPU->flag_S = C68K_SR_S;\n", pre); + + // fetch new PC + mem_op("%sREAD_LONG_F(res * 4, PC)\n", pre); + wf_op("%sSET_PC(PC)\n", pre); +} + +static void gen_exception(char *pre, char* exception) +{ + // swap A7 and USP if needed + wf_op("%sif (!CPU->flag_S)\n", pre); + wf_op("%s{\n", pre); + wf_op("%s\tres = CPU->USP;\n", pre); + wf_op("%s\tCPU->USP = CPU->A[7];\n", pre); + wf_op("%s\tCPU->A[7] = res;\n", pre); + wf_op("%s}\n", pre); + + // get vector & add cycle + wf_op("%sres = %s;\n", pre, exception); + adds_CCnt("c68k_exception_cycle_table[res]"); + + // we will do some mem/io access + do_pre_io(); + + // push PC and SR + mem_op("%sPUSH_32_F(PC - CPU->BasePC)\n", pre); + mem_op("%sPUSH_16_F(GET_SR)\n", pre); + + // adjust SR + wf_op("%sCPU->flag_S = C68K_SR_S;\n", pre); + + // fetch new PC + mem_op("%sREAD_LONG_F(res * 4, PC)\n", pre); + wf_op("%sSET_PC(PC)\n", pre); +} + diff --git a/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/dcsound.c b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/dcsound.c new file mode 100644 index 000000000..ae4fb3fba --- /dev/null +++ b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/dcsound.c @@ -0,0 +1,450 @@ +///////////////////////////////////////////////////////////////////////////// +// +// dcsound - Dreamcast sound system emulation +// +///////////////////////////////////////////////////////////////////////////// + +#ifndef EMU_COMPILE +#error "Hi I forgot to set EMU_COMPILE" +#endif + +#include "dcsound.h" + +#include "arm.h" +#include "yam.h" + +///////////////////////////////////////////////////////////////////////////// +// +// Static information +// +sint32 EMU_CALL dcsound_init(void) { return 0; } + +#define CYCLES_PER_SAMPLE (128) + +///////////////////////////////////////////////////////////////////////////// +// +// State information +// +struct DCSOUND_STATE { + struct DCSOUND_STATE *myself; // Pointer used to check location invariance + + uint32 offset_to_map_load; + uint32 offset_to_map_store; + uint32 offset_to_arm; + uint32 offset_to_yam; + uint32 offset_to_ram; + + uint32 sound_samples_remaining; + uint32 cycles_ahead_of_sound; + sint32 cycles_executed; + +// uint64 timetotal[3]; +// uint64 timelast[3]; +// sint32 timecur; +}; + +#define DCSOUNDSTATE ((struct DCSOUND_STATE*)(state)) +#define MAPLOAD ((void*)(((char*)(DCSOUNDSTATE))+(DCSOUNDSTATE->offset_to_map_load))) +#define MAPSTORE ((void*)(((char*)(DCSOUNDSTATE))+(DCSOUNDSTATE->offset_to_map_store))) +#define ARMSTATE ((void*)(((char*)(DCSOUNDSTATE))+(DCSOUNDSTATE->offset_to_arm))) +#define YAMSTATE ((void*)(((char*)(DCSOUNDSTATE))+(DCSOUNDSTATE->offset_to_yam))) +#define RAMBYTEPTR ((uint8*)(((char*)(DCSOUNDSTATE))+(DCSOUNDSTATE->offset_to_ram))) + +extern const uint32 dcsound_map_load_entries; +extern const uint32 dcsound_map_store_entries; + +uint32 EMU_CALL dcsound_get_state_size(void) { + uint32 offset = 0; + offset += sizeof(struct DCSOUND_STATE); + offset += sizeof(struct ARM_MEMORY_MAP) * dcsound_map_load_entries; + offset += sizeof(struct ARM_MEMORY_MAP) * dcsound_map_store_entries; + offset += arm_get_state_size(); + offset += yam_get_state_size(2); + offset += 0x800000; + return offset; +} + +static void recompute_memory_maps(struct DCSOUND_STATE *state); +static void EMU_CALL dcsound_advance(void *state, uint32 elapse); + +void EMU_CALL dcsound_clear_state(void *state) { + uint32 offset; + + // Clear local struct + memset(state, 0, sizeof(struct DCSOUND_STATE)); + + // Set up offsets + offset = sizeof(struct DCSOUND_STATE); + DCSOUNDSTATE->offset_to_map_load = offset; offset += sizeof(struct ARM_MEMORY_MAP) * dcsound_map_load_entries; + DCSOUNDSTATE->offset_to_map_store = offset; offset += sizeof(struct ARM_MEMORY_MAP) * dcsound_map_store_entries; + DCSOUNDSTATE->offset_to_arm = offset; offset += arm_get_state_size(); + DCSOUNDSTATE->offset_to_yam = offset; offset += yam_get_state_size(2); + DCSOUNDSTATE->offset_to_ram = offset; offset += 0x800000; + + // + // Take care of substructures + // + memset(RAMBYTEPTR, 0, 0x800000); + + recompute_memory_maps(DCSOUNDSTATE); + + arm_clear_state(ARMSTATE); + arm_set_advance_callback(ARMSTATE, dcsound_advance, DCSOUNDSTATE); + arm_set_memory_maps(ARMSTATE, MAPLOAD, MAPSTORE); + + yam_clear_state(YAMSTATE, 2); + yam_setram(YAMSTATE, (uint32*)(RAMBYTEPTR), 0x800000, EMU_ENDIAN_XOR(3), EMU_ENDIAN_XOR(2)); + // + // We want to initialize the Yamaha interrupt system here, because some + // homebrew DC stuff expects it'll start at the BIOS-initialized values + // + yam_aica_store_reg(YAMSTATE, 0x289C, 0x0040, 0xFFFF, NULL); + yam_aica_store_reg(YAMSTATE, 0x28A8, 0x0018, 0xFFFF, NULL); + yam_aica_store_reg(YAMSTATE, 0x28AC, 0x0050, 0xFFFF, NULL); + yam_aica_store_reg(YAMSTATE, 0x28B0, 0x0008, 0xFFFF, NULL); + + DCSOUNDSTATE->myself = DCSOUNDSTATE; + // Done +} + +///////////////////////////////////////////////////////////////////////////// +// +// Profiling +// +#define TIMEDCSOUND (0) +#define TIMEARM (1) +#define TIMEYAM (2) + +#define timeenter(x,y) +#define timeleave(x) +#define timeswitch(x,y) + +/* +static EMU_INLINE uint64 timerdtsc(void) { + uint64 r; + __asm { + rdtsc + mov dword ptr [r],eax + mov dword ptr [r+4],edx + } + return r; +} + +static EMU_INLINE void timeenter(struct DCSOUND_STATE *state, int n) { + state->timecur = n; state->timelast[n] = timerdtsc(); +} + +static EMU_INLINE void timeleave(struct DCSOUND_STATE *state) { + state->timetotal[state->timecur] += timerdtsc() - state->timelast[state->timecur]; +} + +static EMU_INLINE void timeswitch(struct DCSOUND_STATE *state, int n) { + timeleave(state); + timeenter(state, n); +} +*/ + +///////////////////////////////////////////////////////////////////////////// +// +// Check to see if this structure has moved, and if so, recompute +// +// This is currently ONLY done on dcsound_execute +// +static void location_check(struct DCSOUND_STATE *state) { + if(state->myself != state) { + recompute_memory_maps(state); + arm_set_advance_callback(ARMSTATE, dcsound_advance, DCSOUNDSTATE); + arm_set_memory_maps(ARMSTATE, MAPLOAD, MAPSTORE); + yam_setram(YAMSTATE, (uint32*)(RAMBYTEPTR), 0x800000, EMU_ENDIAN_XOR(3), EMU_ENDIAN_XOR(2)); + state->myself = state; + } +} + +///////////////////////////////////////////////////////////////////////////// +// +// Obtain substates +// +void* EMU_CALL dcsound_get_arm_state(void *state) { return ARMSTATE; } +void* EMU_CALL dcsound_get_yam_state(void *state) { return YAMSTATE; } + +///////////////////////////////////////////////////////////////////////////// +// +// Register loads/stores +// (CALLBACK) +// +static uint32 EMU_CALL dcsound_yam_lw(void *state, uint32 a, uint32 mask) { + uint16 d; + timeswitch(DCSOUNDSTATE, TIMEYAM); + d = yam_aica_load_reg(YAMSTATE, a, mask) & mask; + timeswitch(DCSOUNDSTATE, TIMEARM); + return d; +} + +static void EMU_CALL dcsound_yam_sw(void *state, uint32 a, uint32 d, uint32 mask) { + uint8 b = 0; + timeswitch(DCSOUNDSTATE, TIMEYAM); + yam_aica_store_reg(YAMSTATE, a, d, mask, &b); + timeswitch(DCSOUNDSTATE, TIMEARM); + if(b) arm_break(ARMSTATE); +} + +///////////////////////////////////////////////////////////////////////////// +// +// Sync Yamaha emulation with dcsound +// +static void sync_sound(struct DCSOUND_STATE *state) { + if(state->cycles_ahead_of_sound >= CYCLES_PER_SAMPLE) { + uint32 samples = (state->cycles_ahead_of_sound) / CYCLES_PER_SAMPLE; + // + // Avoid overflowing the number of samples remaining + // + if(samples > state->sound_samples_remaining) { + samples = state->sound_samples_remaining; + } + if(samples > 0) { + timeswitch(state, TIMEYAM); + yam_advance(YAMSTATE, samples); + timeswitch(state, TIMEDCSOUND); + state->cycles_ahead_of_sound -= CYCLES_PER_SAMPLE * samples; + state->sound_samples_remaining -= samples; + } + } +} + +///////////////////////////////////////////////////////////////////////////// +// +// Advance hardware activity by the given cycle count +// (CALLBACK) +// +static void EMU_CALL dcsound_advance(void *state, uint32 elapse) { + timeswitch(DCSOUNDSTATE, TIMEDCSOUND); + // + // Update cycles executed + // + DCSOUNDSTATE->cycles_executed += elapse; + DCSOUNDSTATE->cycles_ahead_of_sound += elapse; + // + // Synchronize the sound part + // + sync_sound(DCSOUNDSTATE); + + timeswitch(DCSOUNDSTATE, TIMEARM); +} + +///////////////////////////////////////////////////////////////////////////// +// +// Determine how many cycles until the next interrupt +// +// This is then used as an upper bound for how many cycles can be executed +// before checking for futher interrupts +// +static uint32 cycles_until_next_interrupt( + struct DCSOUND_STATE *state +) { + uint32 yamsamples; + uint32 yamcycles; + timeswitch(state, TIMEYAM); + yamsamples = yam_get_min_samples_until_interrupt(YAMSTATE); + timeswitch(state, TIMEDCSOUND); + if(yamsamples > 0x10000) { yamsamples = 0x10000; } + yamcycles = yamsamples * CYCLES_PER_SAMPLE; + if(yamcycles <= state->cycles_ahead_of_sound) return 1; + return yamcycles - state->cycles_ahead_of_sound; +} + +///////////////////////////////////////////////////////////////////////////// +// +// Invalid-address catchers +// (CALLBACK) +// +static uint32 EMU_CALL catcher_lw(void *state, uint32 a, uint32 mask) { return 0; } +static void EMU_CALL catcher_sw(void *state, uint32 a, uint32 d, uint32 mask) { } + +///////////////////////////////////////////////////////////////////////////// +// +// Static memory map structures +// + +static const struct ARM_MEMORY_MAP dcsound_map_load[] = { + { 0x00000000, 0x007FFFFF, { 0x007FFFFF, ARM_MAP_TYPE_POINTER , NULL } }, + { 0x00800000, 0x0080FFFF, { 0x0000FFFF, ARM_MAP_TYPE_CALLBACK, dcsound_yam_lw } }, + { 0x00000000, 0xFFFFFFFF, { 0xFFFFFFFF, ARM_MAP_TYPE_CALLBACK, catcher_lw } } +}; + +static const struct ARM_MEMORY_MAP dcsound_map_store[] = { + { 0x00000000, 0x007FFFFF, { 0x007FFFFF, ARM_MAP_TYPE_POINTER , NULL } }, + { 0x00800000, 0x0080FFFF, { 0x0000FFFF, ARM_MAP_TYPE_CALLBACK, dcsound_yam_sw } }, + { 0x00000000, 0xFFFFFFFF, { 0xFFFFFFFF, ARM_MAP_TYPE_CALLBACK, catcher_sw } } +}; + +#define DCSOUND_ARRAY_ENTRIES(x) (sizeof(x)/sizeof((x)[0])) + +const uint32 dcsound_map_load_entries = DCSOUND_ARRAY_ENTRIES(dcsound_map_load ); +const uint32 dcsound_map_store_entries = DCSOUND_ARRAY_ENTRIES(dcsound_map_store); + +//////////////////////////////////////////////////////////////////////////////// +// +// Memory map recomputation +// +// Necessary on structure location change or audit change +// + +// +// Recompute the memory maps. +// PERFORMS NO REGISTRATION with the actual ARM state. +// +static void recompute_memory_maps(struct DCSOUND_STATE *state) { + struct ARM_MEMORY_MAP *mapload = MAPLOAD; + struct ARM_MEMORY_MAP *mapstore = MAPSTORE; + // + // First, just copy from the static tables + // + memcpy(mapload , dcsound_map_load , sizeof(dcsound_map_load )); + memcpy(mapstore, dcsound_map_store, sizeof(dcsound_map_store)); + // + // Now perform state offsets on first entry in each map + // + mapload [0].type.p = RAMBYTEPTR; + mapstore[0].type.p = RAMBYTEPTR; +} + +///////////////////////////////////////////////////////////////////////////// +// +// Executes the given number of cycles or the given number of samples +// (whichever is less) +// +// Sets *sound_samples to the number of samples actually generated, +// which may be ZERO or LESS than the number requested, but never more. +// +// Return value: +// >= 0 The number of cycles actually executed, which may be ZERO, MORE, +// or LESS than the number requested +// <= -1 Unrecoverable error +// +sint32 EMU_CALL dcsound_execute( + void *state, + sint32 cycles, + sint16 *sound_buf, + uint32 *sound_samples +) { + sint32 error = 0; + uint8 *yamintptr; + // + // If we have a bogus cycle count, return error + // + if(cycles < 0) { return -1; } + // + // Begin profiling + // + timeenter(DCSOUNDSTATE, TIMEDCSOUND); + // + // Ensure location invariance + // + location_check(DCSOUNDSTATE); + // + // Cap to sane values to avoid overflow problems + // + if(cycles > 0x1000000) { cycles = 0x1000000; } + if((*sound_samples) > 0x10000) { (*sound_samples) = 0x10000; } + // + // Set up the buffer + // + timeswitch(DCSOUNDSTATE, TIMEYAM); + yam_beginbuffer(YAMSTATE, sound_buf); + timeswitch(DCSOUNDSTATE, TIMEDCSOUND); + DCSOUNDSTATE->sound_samples_remaining = *sound_samples; + // + // Get the interrupt pending pointer + // + timeswitch(DCSOUNDSTATE, TIMEYAM); + yamintptr = yam_get_interrupt_pending_ptr(YAMSTATE); + timeswitch(DCSOUNDSTATE, TIMEDCSOUND); + // + // Zero out these counters + // + DCSOUNDSTATE->cycles_executed = 0; + // + // Sync any pending samples from last time + // + sync_sound(DCSOUNDSTATE); + // + // Cap cycles depending on how many samples we have left to generate + // + { sint32 cap = CYCLES_PER_SAMPLE * DCSOUNDSTATE->sound_samples_remaining; + cap -= DCSOUNDSTATE->cycles_ahead_of_sound; + if(cap < 0) cap = 0; + if(cycles > cap) cycles = cap; + } + // + // Execution loop + // + while(DCSOUNDSTATE->cycles_executed < cycles) { + sint32 r; + uint32 remain = cycles - DCSOUNDSTATE->cycles_executed; + uint32 ci = cycles_until_next_interrupt(DCSOUNDSTATE); + if(remain > ci) { remain = ci; } + if(remain > 0x1000000) { remain = 0x1000000; } + timeswitch(DCSOUNDSTATE, TIMEARM); + r = arm_execute(ARMSTATE, remain, (*yamintptr) != 0); + timeswitch(DCSOUNDSTATE, TIMEDCSOUND); + if(r < 0) { error = -1; break; } + } + // + // Flush out actual sound rendering + // + timeswitch(DCSOUNDSTATE, TIMEYAM); + yam_flush(YAMSTATE); + timeswitch(DCSOUNDSTATE, TIMEDCSOUND); + // + // Adjust outgoing sample count + // + (*sound_samples) -= DCSOUNDSTATE->sound_samples_remaining; + // + // End profiling + // + timeleave(DCSOUNDSTATE); + // + // Done + // + if(error) return error; + return DCSOUNDSTATE->cycles_executed; +} + +///////////////////////////////////////////////////////////////////////////// +// +// Get / set memory words with no side effects +// +uint32 EMU_CALL dcsound_getword(void *state, uint32 a) { + return *((uint32*)(RAMBYTEPTR+(a&0x7FFFFC))); +} + +void EMU_CALL dcsound_setword(void *state, uint32 a, uint32 d) { + *((uint32*)(RAMBYTEPTR+(a&0x7FFFFC))) = d; +} + +///////////////////////////////////////////////////////////////////////////// +// +// Upload data to RAM, no side effects +// +void EMU_CALL dcsound_upload_to_ram( + void *state, + uint32 address, + void *src, + uint32 len +) { + uint32 i; + for(i = 0; i < len; i++) { + (RAMBYTEPTR)[((address+i)^(EMU_ENDIAN_XOR(3)))&0x7FFFFF] = + ((uint8*)src)[i]; + } +} + +///////////////////////////////////////////////////////////////////////////// +// +// Get the current program counter +// +uint32 EMU_CALL dcsound_get_pc(void *state) { + return arm_getreg(ARMSTATE, ARM_REG_GEN+15); +} + +///////////////////////////////////////////////////////////////////////////// diff --git a/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/dcsound.h b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/dcsound.h new file mode 100644 index 000000000..3993b3dce --- /dev/null +++ b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/dcsound.h @@ -0,0 +1,76 @@ +///////////////////////////////////////////////////////////////////////////// +// +// dcsound - Dreamcast sound system emulation +// +///////////////////////////////////////////////////////////////////////////// + +#ifndef __SEGA_DCSOUND_H__ +#define __SEGA_DCSOUND_H__ + +#include "emuconfig.h" + +///////////////////////////////////////////////////////////////////////////// + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Init / state +// +sint32 EMU_CALL dcsound_init(void); +uint32 EMU_CALL dcsound_get_state_size(void); +void EMU_CALL dcsound_clear_state(void *state); + +// +// Obtain substates +// +void* EMU_CALL dcsound_get_arm_state(void *state); +void* EMU_CALL dcsound_get_yam_state(void *state); + +// +// Get / set memory words with no side effects +// +uint32 EMU_CALL dcsound_getword(void *state, uint32 a); +void EMU_CALL dcsound_setword(void *state, uint32 a, uint32 d); + +// +// Uploads a section of data; only affects RAM +// +void EMU_CALL dcsound_upload_to_ram(void *state, uint32 address, void *src, uint32 len); + +///////////////////////////////////////////////////////////////////////////// +// +// Executes the given number of cycles or the given number of samples +// (whichever is less) +// +// Sets *sound_samples to the number of samples actually generated, +// which may be ZERO or LESS than the number requested, but never more. +// +// Return value: +// >= 0 The number of cycles actually executed, which may be ZERO, MORE, +// or LESS than the number requested +// <= -1 Unrecoverable error +// +sint32 EMU_CALL dcsound_execute( + void *state, + sint32 cycles, + sint16 *sound_buf, + uint32 *sound_samples +); + +///////////////////////////////////////////////////////////////////////////// +// +// Get the current program counter +// +uint32 EMU_CALL dcsound_get_pc(void *state); + +///////////////////////////////////////////////////////////////////////////// + +#ifdef __cplusplus +} +#endif + +///////////////////////////////////////////////////////////////////////////// + +#endif diff --git a/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/emuconfig.h b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/emuconfig.h new file mode 100644 index 000000000..57d06eeef --- /dev/null +++ b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/emuconfig.h @@ -0,0 +1,101 @@ +///////////////////////////////////////////////////////////////////////////// +// +// Configuration for emulation libraries +// +///////////////////////////////////////////////////////////////////////////// + +#ifndef __EMUCONFIG_H__ +#define __EMUCONFIG_H__ + +///////////////////////////////////////////////////////////////////////////// + +#include +#include +#include +#include + +///////////////////////////////////////////////////////////////////////////// +// +// One of these has to be defined when compiling the library. +// Shouldn't be necessary for using it. +// +#if defined(EMU_COMPILE) && !defined(EMU_BIG_ENDIAN) && !defined(EMU_LITTLE_ENDIAN) +#error "Hi I forgot to set EMU_x_ENDIAN" +#endif +#if defined(EMU_COMPILE) && defined(EMU_BIG_ENDIAN) && defined(EMU_LITTLE_ENDIAN) +#error "Both byte orders should not be defined" +#endif + +///////////////////////////////////////////////////////////////////////////// +// +// WIN32 native project definitions +// +///////////////////////////////////////////////////////////////////////////// +#if defined(WIN32) && !defined(__GNUC__) + +#define EMU_CALL __fastcall +#define EMU_CALL_ __cdecl +#define EMU_INLINE __inline + +#define uint8 unsigned char +#define uint16 unsigned short +#define uint32 unsigned int +#define uint64 unsigned __int64 +#define sint8 signed char +#define sint16 signed short +#define sint32 signed int +#define sint64 signed __int64 + +///////////////////////////////////////////////////////////////////////////// +// +// LINUX / other platform definitions +// +///////////////////////////////////////////////////////////////////////////// +#else + +//#if defined(__GNUC__) && defined(__i386__) +//#define EMU_CALL __attribute__((__regparm__(2))) +//#else +#define EMU_CALL +//#endif + +#define EMU_CALL_ +#define EMU_INLINE __inline + +#ifdef HAVE_STDINT_H +#include +#define uint8 uint8_t +#define uint16 uint16_t +#define uint32 uint32_t +#define uint64 uint64_t +#define sint8 int8_t +#define sint16 int16_t +#define sint32 int32_t +#define sint64 int64_t +#else +#define uint8 unsigned char +#define uint16 unsigned short +#define uint32 unsigned int +#define uint64 unsigned long long +#define sint8 signed char +#define sint16 signed short +#define sint32 signed int +#define sint64 signed long long +#endif + +#endif + +#ifdef EMU_BIG_ENDIAN +#define EMU_ENDIAN_XOR_L2H(x) (x) +#define EMU_ENDIAN_XOR_B2H(x) (0) +#else +#define EMU_ENDIAN_XOR_L2H(x) (0) +#define EMU_ENDIAN_XOR_B2H(x) (x) +#endif + +// deprecated +#define EMU_ENDIAN_XOR(x) EMU_ENDIAN_XOR_L2H(x) + +///////////////////////////////////////////////////////////////////////////// + +#endif diff --git a/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/m68k/m68k.h b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/m68k/m68k.h new file mode 100644 index 000000000..f12b85c54 --- /dev/null +++ b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/m68k/m68k.h @@ -0,0 +1,420 @@ +#ifndef M68K__HEADER +#define M68K__HEADER + +/* ======================================================================== */ +/* ========================= LICENSING & COPYRIGHT ======================== */ +/* ======================================================================== */ +/* + * MUSASHI + * Version 3.32 + * + * A portable Motorola M680x0 processor emulation engine. + * Copyright Karl Stenerud. All rights reserved. + * + * This code may be freely used for non-commercial purposes as long as this + * copyright notice remains unaltered in the source code and any binary files + * containing this code in compiled form. + * + * All other licensing terms must be negotiated with the author + * (Karl Stenerud). + * + * The latest version of this code can be obtained at: + * http://kstenerud.cjb.net + */ + + /* Modified by Eke-Eke for Genesis Plus GX: + + - removed unused stuff to reduce memory usage / optimize execution (multiple CPU types support, NMI support, ...) + - moved stuff to compile statically in a single object file + - implemented support for global cycle count (shared by 68k & Z80 CPU) + - added support for interrupt latency (Sesame's Street Counting Cafe, Fatal Rewind) + - added proper cycle use on reset + - added cycle accurate timings for MUL/DIV instructions (thanks to Jorge Cwik !) + - fixed undocumented flags for DIV instructions (Blood Shot) + - added MAIN-CPU & SUB-CPU support for Mega CD emulation + + */ + +/* ======================================================================== */ +/* ================================ INCLUDES ============================== */ +/* ======================================================================== */ + +#include "macros.h" + + +/* ======================================================================== */ +/* ==================== ARCHITECTURE-DEPENDANT DEFINES ==================== */ +/* ======================================================================== */ + +/* Check for > 32bit sizes */ +#if UINT_MAX > 0xffffffff + #define M68K_INT_GT_32_BIT 1 +#else + #define M68K_INT_GT_32_BIT 0 +#endif + +/* Data types used in this emulation core */ +#undef sint8 +#undef sint16 +#undef sint32 +#undef sint64 +#undef uint8 +#undef uint16 +#undef uint32 +#undef uint64 +#undef sint +#undef uint + +#define sint8 signed char /* ASG: changed from char to signed char */ +#define sint16 signed short +#define sint32 signed int /* AWJ: changed from long to int */ +#define uint8 unsigned char +#define uint16 unsigned short +#define uint32 unsigned int /* AWJ: changed from long to int */ + +/* signed and unsigned int must be at least 32 bits wide */ +#define sint signed int +#define uint unsigned int + + +#if M68K_USE_64_BIT +#define sint64 signed long long +#define uint64 unsigned long long +#else +#define sint64 sint32 +#define uint64 uint32 +#endif /* M68K_USE_64_BIT */ + + + +/* Allow for architectures that don't have 8-bit sizes */ +/*#if UCHAR_MAX == 0xff*/ + #define MAKE_INT_8(A) (sint8)(A) +/*#else + #undef sint8 + #define sint8 signed int + #undef uint8 + #define uint8 unsigned int + INLINE sint MAKE_INT_8(uint value) + { + return (value & 0x80) ? value | ~0xff : value & 0xff; + }*/ +/*#endif *//* UCHAR_MAX == 0xff */ + + +/* Allow for architectures that don't have 16-bit sizes */ +/*#if USHRT_MAX == 0xffff*/ + #define MAKE_INT_16(A) (sint16)(A) +/*#else + #undef sint16 + #define sint16 signed int + #undef uint16 + #define uint16 unsigned int + INLINE sint MAKE_INT_16(uint value) + { + return (value & 0x8000) ? value | ~0xffff : value & 0xffff; + }*/ +/*#endif *//* USHRT_MAX == 0xffff */ + + +/* Allow for architectures that don't have 32-bit sizes */ +/*#if UINT_MAX == 0xffffffff*/ + #define MAKE_INT_32(A) (sint32)(A) +/*#else + #undef sint32 + #define sint32 signed int + #undef uint32 + #define uint32 unsigned int + INLINE sint MAKE_INT_32(uint value) + { + return (value & 0x80000000) ? value | ~0xffffffff : value & 0xffffffff; + }*/ +/*#endif *//* UINT_MAX == 0xffffffff */ + + + +/* ======================================================================== */ +/* ============================ GENERAL DEFINES =========================== */ + +/* ======================================================================== */ + +/* There are 7 levels of interrupt to the 68K. + * A transition from < 7 to 7 will cause a non-maskable interrupt (NMI). + */ +#define M68K_IRQ_NONE 0 +#define M68K_IRQ_1 1 +#define M68K_IRQ_2 2 +#define M68K_IRQ_3 3 +#define M68K_IRQ_4 4 +#define M68K_IRQ_5 5 +#define M68K_IRQ_6 6 +#define M68K_IRQ_7 7 + + +/* Special interrupt acknowledge values. + * Use these as special returns from the interrupt acknowledge callback + * (specified later in this header). + */ + +/* Causes an interrupt autovector (0x18 + interrupt level) to be taken. + * This happens in a real 68K if VPA or AVEC is asserted during an interrupt + * acknowledge cycle instead of DTACK. + */ +#define M68K_INT_ACK_AUTOVECTOR 0xffffffff + +/* Causes the spurious interrupt vector (0x18) to be taken + * This happens in a real 68K if BERR is asserted during the interrupt + * acknowledge cycle (i.e. no devices responded to the acknowledge). + */ +#define M68K_INT_ACK_SPURIOUS 0xfffffffe + + +/* Registers used by m68k_get_reg() and m68k_set_reg() */ +typedef enum +{ + /* Real registers */ + M68K_REG_D0, /* Data registers */ + M68K_REG_D1, + M68K_REG_D2, + M68K_REG_D3, + M68K_REG_D4, + M68K_REG_D5, + M68K_REG_D6, + M68K_REG_D7, + M68K_REG_A0, /* Address registers */ + M68K_REG_A1, + M68K_REG_A2, + M68K_REG_A3, + M68K_REG_A4, + M68K_REG_A5, + M68K_REG_A6, + M68K_REG_A7, + M68K_REG_PC, /* Program Counter */ + M68K_REG_SR, /* Status Register */ + M68K_REG_SP, /* The current Stack Pointer (located in A7) */ + M68K_REG_USP, /* User Stack Pointer */ + M68K_REG_ISP, /* Interrupt Stack Pointer */ + +#if M68K_EMULATE_PREFETCH + /* Assumed registers */ + /* These are cheat registers which emulate the 1-longword prefetch + * present in the 68000 and 68010. + */ + M68K_REG_PREF_ADDR, /* Last prefetch address */ + M68K_REG_PREF_DATA, /* Last prefetch data */ +#endif + + /* Convenience registers */ + M68K_REG_IR /* Instruction register */ +} m68k_register_t; + + +/* 68k memory map structure */ +typedef struct +{ + void *param; + unsigned char *base; /* memory-based access (ROM, RAM) */ + unsigned int (*read8)(void *param, unsigned int address); /* I/O byte read access */ + unsigned int (*read16)(void *param, unsigned int address); /* I/O word read access */ + void (*write8)(void *param, unsigned int address, unsigned int data); /* I/O byte write access */ + void (*write16)(void *param, unsigned int address, unsigned int data); /* I/O word write access */ +} cpu_memory_map; + +/* 68k idle loop detection */ +typedef struct +{ + uint pc; + uint cycle; + uint detected; +} cpu_idle_t; + +typedef struct _m68ki_cpu_core +{ + cpu_memory_map memory_map[256]; /* memory mapping */ + + cpu_idle_t poll; /* polling detection */ + + uint irq_latency; + + uint dar[16]; /* Data and Address Registers */ + uint ppc; /* Previous program counter */ + uint pc; /* Program Counter */ + uint sp[7]; /* User and Interrupt Stack Pointers */ + uint vbr; /* Vector Base Register (m68010+) */ + uint sfc; /* Source Function Code Register (m68010+) */ + uint dfc; /* Destination Function Code Register (m68010+) */ + uint cacr; /* Cache Control Register (m68020, unemulated) */ + uint caar; /* Cache Address Register (m68020, unemulated) */ + uint ir; /* Instruction Register */ + uint t1_flag; /* Trace 1 */ + uint t0_flag; /* Trace 0 */ + uint s_flag; /* Supervisor */ + uint m_flag; /* Master/Interrupt state */ + uint x_flag; /* Extend */ + uint n_flag; /* Negative */ + uint not_z_flag; /* Zero, inverted for speedups */ + uint v_flag; /* Overflow */ + uint c_flag; /* Carry */ + uint int_mask; /* I0-I2 */ + uint int_level; /* State of interrupt pins IPL0-IPL2 -- ASG: changed from ints_pending */ + uint stopped; /* Stopped state */ +#if M68K_EMULATE_PREFETCH + uint pref_addr; /* Last prefetch address */ + uint pref_data; /* Data in the prefetch queue */ +#endif + uint sr_mask; /* Implemented status register bits */ +#if M68K_EMULATE_ADDRESS_ERROR + uint instr_mode; /* Stores whether we are in instruction mode or group 0/1 exception mode */ + uint run_mode; /* Stores whether we are processing a reset, bus error, address error, or something else */ + uint aerr_enabled; /* Enables/deisables address error checks at runtime */ + jmp_buf aerr_trap; /* Address error jump */ + uint aerr_address; /* Address error location */ + uint aerr_write_mode; /* Address error write mode */ + uint aerr_fc; /* Address error FC code */ +#endif +#if M68K_EMULATE_TRACE + uint tracing; /* Tracing enable flag */ +#endif +#if M68K_EMULATE_FC + uint address_space; /* Current FC code */ +#endif + /* Clocks required for instructions / exceptions */ + uint cyc_bcc_notake_b; + uint cyc_bcc_notake_w; + uint cyc_dbcc_f_noexp; + uint cyc_dbcc_f_exp; + uint cyc_scc_r_true; + uint cyc_movem_w; + uint cyc_movem_l; + uint cyc_shift; + uint cyc_reset; + + int initial_cycles; + int remaining_cycles; /* Number of clocks remaining */ + int reset_cycles; + + void *param; /* User parameter */ + + /* Virtual IRQ lines state */ + uint virq_state; + uint nmi_pending; + + const unsigned char* cyc_instruction; + const unsigned char* cyc_exception; + + /* Callbacks to host */ +#if M68K_EMULATE_INT_ACK + int (*int_ack_callback)(m68ki_cpu_core *cpu, int int_line); /* Interrupt Acknowledge */ +#endif +#if M68K_EMULATE_RESET + void (*reset_instr_callback)(m68ki_cpu_core *cpu); /* Called when a RESET instruction is encountered */ +#endif +#if M68K_TAS_HAS_CALLBACK + int (*tas_instr_callback)(m68ki_cpu_core *cpu); /* Called when a TAS instruction is encountered, allows / disallows writeback */ +#endif +#if M68K_EMULATE_FC + void (*set_fc_callback)(m68ki_cpu_core *cpu, unsigned int new_fc); /* Called when the CPU function code changes */ +#endif +} m68ki_cpu_core; + +/* ======================================================================== */ +/* ============================== CALLBACKS =============================== */ +/* ======================================================================== */ + +/* These functions allow you to set callbacks to the host when specific events + * occur. Note that you must enable the corresponding value in m68kconf.h + * in order for these to do anything useful. + * Note: I have defined default callbacks which are used if you have enabled + * the corresponding #define in m68kconf.h but either haven't assigned a + * callback or have assigned a callback of NULL. + */ + +#if M68K_EMULATE_INT_ACK == OPT_ON +/* Set the callback for an interrupt acknowledge. + * You must enable M68K_EMULATE_INT_ACK in m68kconf.h. + * The CPU will call the callback with the interrupt level being acknowledged. + * The host program must return either a vector from 0x02-0xff, or one of the + * special interrupt acknowledge values specified earlier in this header. + * If this is not implemented, the CPU will always assume an autovectored + * interrupt, and will automatically clear the interrupt request when it + * services the interrupt. + * Default behavior: return M68K_INT_ACK_AUTOVECTOR. + */ +void m68k_set_int_ack_callback(int (*callback)(void *param, int int_level)); +#endif + +#if M68K_EMULATE_RESET == OPT_ON +/* Set the callback for the RESET instruction. + * You must enable M68K_EMULATE_RESET in m68kconf.h. + * The CPU calls this callback every time it encounters a RESET instruction. + * Default behavior: do nothing. + */ +void m68k_set_reset_instr_callback(void (*callback)(void *param)); +#endif + +#if M68K_TAS_HAS_CALLBACK == OPT_ON +/* Set the callback for the TAS instruction. + * You must enable M68K_TAS_HAS_CALLBACK in m68kconf.h. + * The CPU calls this callback every time it encounters a TAS instruction. + * Default behavior: return 1, allow writeback. + */ +void m68k_set_tas_instr_callback(int (*callback)(void *param)); +#endif + +#if M68K_EMULATE_FC == OPT_ON +/* Set the callback for CPU function code changes. + * You must enable M68K_EMULATE_FC in m68kconf.h. + * The CPU calls this callback with the function code before every memory + * access to set the CPU's function code according to what kind of memory + * access it is (supervisor/user, program/data and such). + * Default behavior: do nothing. + */ +void m68k_set_fc_callback(void (*callback)(m68ki_cpu_core *cpu, unsigned int new_fc)); +#endif + + +/* ======================================================================== */ +/* ====================== FUNCTIONS TO ACCESS THE CPU ===================== */ +/* ======================================================================== */ + +/* Do whatever initialisations the core requires. Should be called + * at least once at init time. + */ +extern void m68k_init(m68ki_cpu_core *); + +/* Pulse the RESET pin on the CPU. + * You *MUST* reset the CPU at least once to initialize the emulation + */ +extern void m68k_pulse_reset(m68ki_cpu_core *); + +/* Run until given cycle count is reached */ +extern int m68k_execute(m68ki_cpu_core *, unsigned int cycles); + +/* Set the IPL0-IPL2 pins on the CPU (IRQ). + * A transition from < 7 to 7 will cause a non-maskable interrupt (NMI). + * Setting IRQ to 0 will clear an interrupt request. + */ +#define ASSERT_LINE 1 +#define RESET_LINE 0 +void m68k_set_irq(m68ki_cpu_core *m68k, int irqline, int state); + +/* Halt the CPU as if you pulsed the HALT pin. */ +extern void m68k_pulse_halt(m68ki_cpu_core *); +extern void m68k_clear_halt(m68ki_cpu_core *); + + +/* Peek at the internals of a CPU context. This can either be a context + * retrieved using m68k_get_context() or the currently running context. + * If context is NULL, the currently running CPU context will be used. + */ +extern unsigned int m68k_get_reg(m68ki_cpu_core *, m68k_register_t reg); + +/* Poke values into the internals of the currently running CPU context */ +extern void m68k_set_reg(m68ki_cpu_core *, m68k_register_t reg, unsigned int value); + + +/* ======================================================================== */ +/* ============================== END OF FILE ============================= */ +/* ======================================================================== */ + +#endif /* M68K__HEADER */ diff --git a/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/m68k/m68k_in.c b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/m68k/m68k_in.c new file mode 100644 index 000000000..cecb5385b --- /dev/null +++ b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/m68k/m68k_in.c @@ -0,0 +1,10174 @@ +/* +must fix: + callm + chk +*/ +/* ======================================================================== */ +/* ========================= LICENSING & COPYRIGHT ======================== */ +/* ======================================================================== */ +/* + * MUSASHI + * Version 3.32 + * + * A portable Motorola M680x0 processor emulation engine. + * Copyright Karl Stenerud. All rights reserved. + * + * This code may be freely used for non-commercial purposes as long as this + * copyright notice remains unaltered in the source code and any binary files + * containing this code in compiled form. + * + * All other licensing terms must be negotiated with the author + * (Karl Stenerud). + * + * The latest version of this code can be obtained at: + * http://kstenerud.cjb.net + */ + +/* Special thanks to Bart Trzynadlowski for his insight into the + * undocumented features of this chip: + * + * http://dynarec.com/~bart/files/68knotes.txt + */ + + +/* Input file for m68kmake + * ----------------------- + * + * All sections begin with 80 X's in a row followed by an end-of-line + * sequence. + * After this, m68kmake will expect to find one of the following section + * identifiers: + * M68KMAKE_PROTOTYPE_HEADER - header for opcode handler prototypes + * M68KMAKE_PROTOTYPE_FOOTER - footer for opcode handler prototypes + * M68KMAKE_TABLE_HEADER - header for opcode handler jumptable + * M68KMAKE_TABLE_FOOTER - footer for opcode handler jumptable + * M68KMAKE_TABLE_BODY - the table itself + * M68KMAKE_OPCODE_HANDLER_HEADER - header for opcode handler implementation + * M68KMAKE_OPCODE_HANDLER_FOOTER - footer for opcode handler implementation + * M68KMAKE_OPCODE_HANDLER_BODY - body section for opcode handler implementation + * + * NOTE: M68KMAKE_OPCODE_HANDLER_BODY must be last in the file and + * M68KMAKE_TABLE_BODY must be second last in the file. + * + * The M68KMAKE_OPHANDLER_BODY section contains the opcode handler + * primitives themselves. Each opcode handler begins with: + * M68KMAKE_OP(A, B, C, D) + * + * where A is the opcode handler name, B is the size of the operation, + * C denotes any special processing mode, and D denotes a specific + * addressing mode. + * For C and D where nothing is specified, use "." + * + * Example: + * M68KMAKE_OP(abcd, 8, rr, .) abcd, size 8, register to register, default EA + * M68KMAKE_OP(abcd, 8, mm, ax7) abcd, size 8, memory to memory, register X is A7 + * M68KMAKE_OP(tst, 16, ., pcix) tst, size 16, PCIX addressing + * + * All opcode handler primitives end with a closing curly brace "}" at column 1 + * + * NOTE: Do not place a M68KMAKE_OP() directive inside the opcode handler, + * and do not put a closing curly brace at column 1 unless it is + * marking the end of the handler! + * + * Inside the handler, m68kmake will recognize M68KMAKE_GET_OPER_xx_xx, + * M68KMAKE_GET_EA_xx_xx, and M68KMAKE_CC directives, and create multiple + * opcode handlers to handle variations in the opcode handler. + * Note: M68KMAKE_CC will only be interpreted in condition code opcodes. + * As well, M68KMAKE_GET_EA_xx_xx and M68KMAKE_GET_OPER_xx_xx will only + * be interpreted on instructions where the corresponding table entry + * specifies multiple effective addressing modes. + * Example: + * clr 32 . . 0100001010...... A+-DXWL... U U U 12 6 4 + * + * This table entry says that the clr.l opcde has 7 variations (A+-DXWL). + * It is run in user or supervisor mode for all CPUs, and uses 12 cycles for + * 68000, 6 cycles for 68010, and 4 cycles for 68020. + */ + +XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +M68KMAKE_PROTOTYPE_HEADER + +#ifndef M68KOPS__HEADER +#define M68KOPS__HEADER + +/* ======================================================================== */ +/* ============================ OPCODE HANDLERS =========================== */ +/* ======================================================================== */ + + + +XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +M68KMAKE_PROTOTYPE_FOOTER + + +/* Build the opcode handler table */ +void m68ki_build_opcode_table(void); + +extern void (*m68ki_instruction_jump_table[0x10000])(m68ki_cpu_core *m68k); /* opcode handler jump table */ +extern unsigned char m68ki_cycles[][0x10000]; + + +/* ======================================================================== */ +/* ============================== END OF FILE ============================= */ +/* ======================================================================== */ + +#endif /* M68KOPS__HEADER */ + + + +XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +M68KMAKE_TABLE_HEADER + +/* ======================================================================== */ +/* ========================= OPCODE TABLE BUILDER ========================= */ +/* ======================================================================== */ + +#include "m68kops.h" + +#define NUM_CPU_TYPES 5 + +void (*m68ki_instruction_jump_table[0x10000])(m68ki_cpu_core *m68k); /* opcode handler jump table */ +unsigned char m68ki_cycles[NUM_CPU_TYPES][0x10000]; /* Cycles used by CPU type */ + +/* This is used to generate the opcode handler jump table */ +typedef struct +{ + void (*opcode_handler)(m68ki_cpu_core *m68k); /* handler function */ + unsigned int mask; /* mask on opcode */ + unsigned int match; /* what to match after masking */ + unsigned char cycles[NUM_CPU_TYPES]; /* cycles each cpu type takes */ +} opcode_handler_struct; + + +/* Opcode handler table */ +static const opcode_handler_struct m68k_opcode_handler_table[] = +{ +/* function mask match 000 010 020 040 */ + + + +XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +M68KMAKE_TABLE_FOOTER + + {0, 0, 0, {0, 0, 0, 0, 0}} +}; + + +/* Build the opcode handler jump table */ +void m68ki_build_opcode_table(void) +{ + const opcode_handler_struct *ostruct; + int instr; + int i; + int j; + int k; + + for(i = 0; i < 0x10000; i++) + { + /* default to illegal */ + m68ki_instruction_jump_table[i] = m68k_op_illegal; + for(k=0;kmask != 0xff00) + { + for(i = 0;i < 0x10000;i++) + { + if((i & ostruct->mask) == ostruct->match) + { + m68ki_instruction_jump_table[i] = ostruct->opcode_handler; + for(k=0;kcycles[k]; + } + } + ostruct++; + } + while(ostruct->mask == 0xff00) + { + for(i = 0;i <= 0xff;i++) + { + m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler; + for(k=0;kmatch | i] = ostruct->cycles[k]; + } + ostruct++; + } + while(ostruct->mask == 0xf1f8) + { + for(i = 0;i < 8;i++) + { + for(j = 0;j < 8;j++) + { + instr = ostruct->match | (i << 9) | j; + m68ki_instruction_jump_table[instr] = ostruct->opcode_handler; + for(k=0;kcycles[k]; + } + } + ostruct++; + } + while(ostruct->mask == 0xfff0) + { + for(i = 0;i <= 0x0f;i++) + { + m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler; + for(k=0;kmatch | i] = ostruct->cycles[k]; + } + ostruct++; + } + while(ostruct->mask == 0xf1ff) + { + for(i = 0;i <= 0x07;i++) + { + m68ki_instruction_jump_table[ostruct->match | (i << 9)] = ostruct->opcode_handler; + for(k=0;kmatch | (i << 9)] = ostruct->cycles[k]; + } + ostruct++; + } + while(ostruct->mask == 0xfff8) + { + for(i = 0;i <= 0x07;i++) + { + m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler; + for(k=0;kmatch | i] = ostruct->cycles[k]; + } + ostruct++; + } + while(ostruct->mask == 0xffff) + { + m68ki_instruction_jump_table[ostruct->match] = ostruct->opcode_handler; + for(k=0;kmatch] = ostruct->cycles[k]; + ostruct++; + } +} + + +/* ======================================================================== */ +/* ============================== END OF FILE ============================= */ +/* ======================================================================== */ + + + +XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +M68KMAKE_OPCODE_HANDLER_HEADER + +#include "m68kcpu.h" +#include "mame.h" +extern void m68040_fpu_op0(m68ki_cpu_core *m68k); +extern void m68040_fpu_op1(m68ki_cpu_core *m68k); +extern void m68881_mmu_ops(m68ki_cpu_core *m68k); + +/* ======================================================================== */ +/* ========================= INSTRUCTION HANDLERS ========================= */ +/* ======================================================================== */ + + + +XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +M68KMAKE_OPCODE_HANDLER_FOOTER + +/* ======================================================================== */ +/* ============================== END OF FILE ============================= */ +/* ======================================================================== */ + + + +XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +M68KMAKE_TABLE_BODY +/* +The following table is arranged as follows: + +name: Opcode mnemonic + +size: Operation size + +spec proc: Special processing mode: + .: normal + s: static operand + r: register operand + rr: register to register + mm: memory to memory + er: effective address to register + re: register to effective address + dd: data register to data register + da: data register to address register + aa: address register to address register + cr: control register to register + rc: register to control register + toc: to condition code register + tos: to status register + tou: to user stack pointer + frc: from condition code register + frs: from status register + fru: from user stack pointer + * for move.x, the special processing mode is a specific + destination effective addressing mode. + +spec ea: Specific effective addressing mode: + .: normal + i: immediate + d: data register + a: address register + ai: address register indirect + pi: address register indirect with postincrement + pd: address register indirect with predecrement + di: address register indirect with displacement + ix: address register indirect with index + aw: absolute word address + al: absolute long address + pcdi: program counter relative with displacement + pcix: program counter relative with index + a7: register specified in instruction is A7 + ax7: register field X of instruction is A7 + ay7: register field Y of instruction is A7 + axy7: register fields X and Y of instruction are A7 + +bit pattern: Pattern to recognize this opcode. "." means don't care. + +allowed ea: List of allowed addressing modes: + .: not present + A: address register indirect + +: ARI (address register indirect) with postincrement + -: ARI with predecrement + D: ARI with displacement + X: ARI with index + W: absolute word address + L: absolute long address + d: program counter indirect with displacement + x: program counter indirect with index + I: immediate +mode: CPU operating mode for each cpu type. U = user or supervisor, + S = supervisor only, "." = opcode not present. + +cpu cycles: Base number of cycles required to execute this opcode on the + specified CPU type. + Use "." if CPU does not have this opcode. +*/ + + + spec spec allowed ea mode cpu cycles +name size proc ea bit pattern A+-DXWLdxI 0 1 2 3 4 000 010 020 030 040 comments +====== ==== ==== ==== ================ ========== = = = = = === === === === === ============= +M68KMAKE_TABLE_START +1010 0 . . 1010............ .......... U U U U U 4 4 4 4 4 +1111 0 . . 1111............ .......... U U U U U 4 4 4 4 4 +040fpu0 32 . . 11110010........ .......... . . . . U . . . . 0 +040fpu1 32 . . 11110011........ .......... . . . . U . . . . 0 +abcd 8 rr . 1100...100000... .......... U U U U U 6 6 4 4 4 +abcd 8 mm ax7 1100111100001... .......... U U U U U 18 18 16 16 16 +abcd 8 mm ay7 1100...100001111 .......... U U U U U 18 18 16 16 16 +abcd 8 mm axy7 1100111100001111 .......... U U U U U 18 18 16 16 16 +abcd 8 mm . 1100...100001... .......... U U U U U 18 18 16 16 16 +add 8 er d 1101...000000... .......... U U U U U 4 4 2 2 2 +add 8 er . 1101...000...... A+-DXWLdxI U U U U U 4 4 2 2 2 +add 16 er d 1101...001000... .......... U U U U U 4 4 2 2 2 +add 16 er a 1101...001001... .......... U U U U U 4 4 2 2 2 +add 16 er . 1101...001...... A+-DXWLdxI U U U U U 4 4 2 2 2 +add 32 er d 1101...010000... .......... U U U U U 6 6 2 2 2 +add 32 er a 1101...010001... .......... U U U U U 6 6 2 2 2 +add 32 er . 1101...010...... A+-DXWLdxI U U U U U 6 6 2 2 2 +add 8 re . 1101...100...... A+-DXWL... U U U U U 8 8 4 4 4 +add 16 re . 1101...101...... A+-DXWL... U U U U U 8 8 4 4 4 +add 32 re . 1101...110...... A+-DXWL... U U U U U 12 12 4 4 4 +adda 16 . d 1101...011000... .......... U U U U U 8 8 2 2 2 +adda 16 . a 1101...011001... .......... U U U U U 8 8 2 2 2 +adda 16 . . 1101...011...... A+-DXWLdxI U U U U U 8 8 2 2 2 +adda 32 . d 1101...111000... .......... U U U U U 6 6 2 2 2 +adda 32 . a 1101...111001... .......... U U U U U 6 6 2 2 2 +adda 32 . . 1101...111...... A+-DXWLdxI U U U U U 6 6 2 2 2 +addi 8 . d 0000011000000... .......... U U U U U 8 8 2 2 2 +addi 8 . . 0000011000...... A+-DXWL... U U U U U 12 12 4 4 4 +addi 16 . d 0000011001000... .......... U U U U U 8 8 2 2 2 +addi 16 . . 0000011001...... A+-DXWL... U U U U U 12 12 4 4 4 +addi 32 . d 0000011010000... .......... U U U U U 16 14 2 2 2 +addi 32 . . 0000011010...... A+-DXWL... U U U U U 20 20 4 4 4 +addq 8 . d 0101...000000... .......... U U U U U 4 4 2 2 2 +addq 8 . . 0101...000...... A+-DXWL... U U U U U 8 8 4 4 4 +addq 16 . d 0101...001000... .......... U U U U U 4 4 2 2 2 +addq 16 . a 0101...001001... .......... U U U U U 4 4 2 2 2 +addq 16 . . 0101...001...... A+-DXWL... U U U U U 8 8 4 4 4 +addq 32 . d 0101...010000... .......... U U U U U 8 8 2 2 2 +addq 32 . a 0101...010001... .......... U U U U U 8 8 2 2 2 +addq 32 . . 0101...010...... A+-DXWL... U U U U U 12 12 4 4 4 +addx 8 rr . 1101...100000... .......... U U U U U 4 4 2 2 2 +addx 16 rr . 1101...101000... .......... U U U U U 4 4 2 2 2 +addx 32 rr . 1101...110000... .......... U U U U U 8 6 2 2 2 +addx 8 mm ax7 1101111100001... .......... U U U U U 18 18 12 12 12 +addx 8 mm ay7 1101...100001111 .......... U U U U U 18 18 12 12 12 +addx 8 mm axy7 1101111100001111 .......... U U U U U 18 18 12 12 12 +addx 8 mm . 1101...100001... .......... U U U U U 18 18 12 12 12 +addx 16 mm . 1101...101001... .......... U U U U U 18 18 12 12 12 +addx 32 mm . 1101...110001... .......... U U U U U 30 30 12 12 12 +and 8 er d 1100...000000... .......... U U U U U 4 4 2 2 2 +and 8 er . 1100...000...... A+-DXWLdxI U U U U U 4 4 2 2 2 +and 16 er d 1100...001000... .......... U U U U U 4 4 2 2 2 +and 16 er . 1100...001...... A+-DXWLdxI U U U U U 4 4 2 2 2 +and 32 er d 1100...010000... .......... U U U U U 6 6 2 2 2 +and 32 er . 1100...010...... A+-DXWLdxI U U U U U 6 6 2 2 2 +and 8 re . 1100...100...... A+-DXWL... U U U U U 8 8 4 4 4 +and 16 re . 1100...101...... A+-DXWL... U U U U U 8 8 4 4 4 +and 32 re . 1100...110...... A+-DXWL... U U U U U 12 12 4 4 4 +andi 16 toc . 0000001000111100 .......... U U U U U 20 16 12 12 12 +andi 16 tos . 0000001001111100 .......... S S S S S 20 16 12 12 12 +andi 8 . d 0000001000000... .......... U U U U U 8 8 2 2 2 +andi 8 . . 0000001000...... A+-DXWL... U U U U U 12 12 4 4 4 +andi 16 . d 0000001001000... .......... U U U U U 8 8 2 2 2 +andi 16 . . 0000001001...... A+-DXWL... U U U U U 12 12 4 4 4 +andi 32 . d 0000001010000... .......... U U U U U 14 14 2 2 2 +andi 32 . . 0000001010...... A+-DXWL... U U U U U 20 20 4 4 4 +asr 8 s . 1110...000000... .......... U U U U U 6 6 6 6 6 +asr 16 s . 1110...001000... .......... U U U U U 6 6 6 6 6 +asr 32 s . 1110...010000... .......... U U U U U 8 8 6 6 6 +asr 8 r . 1110...000100... .......... U U U U U 6 6 6 6 6 +asr 16 r . 1110...001100... .......... U U U U U 6 6 6 6 6 +asr 32 r . 1110...010100... .......... U U U U U 8 8 6 6 6 +asr 16 . . 1110000011...... A+-DXWL... U U U U U 8 8 5 5 5 +asl 8 s . 1110...100000... .......... U U U U U 6 6 8 8 8 +asl 16 s . 1110...101000... .......... U U U U U 6 6 8 8 8 +asl 32 s . 1110...110000... .......... U U U U U 8 8 8 8 8 +asl 8 r . 1110...100100... .......... U U U U U 6 6 8 8 8 +asl 16 r . 1110...101100... .......... U U U U U 6 6 8 8 8 +asl 32 r . 1110...110100... .......... U U U U U 8 8 8 8 8 +asl 16 . . 1110000111...... A+-DXWL... U U U U U 8 8 6 6 6 +bcc 8 . . 0110............ .......... U U U U U 10 10 6 6 6 +bcc 16 . . 0110....00000000 .......... U U U U U 10 10 6 6 6 +bcc 32 . . 0110....11111111 .......... U U U U U 10 10 6 6 6 +bchg 8 r . 0000...101...... A+-DXWL... U U U U U 8 8 4 4 4 +bchg 32 r d 0000...101000... .......... U U U U U 8 8 4 4 4 +bchg 8 s . 0000100001...... A+-DXWL... U U U U U 12 12 4 4 4 +bchg 32 s d 0000100001000... .......... U U U U U 12 12 4 4 4 +bclr 8 r . 0000...110...... A+-DXWL... U U U U U 8 10 4 4 4 +bclr 32 r d 0000...110000... .......... U U U U U 10 10 4 4 4 +bclr 8 s . 0000100010...... A+-DXWL... U U U U U 12 12 4 4 4 +bclr 32 s d 0000100010000... .......... U U U U U 14 14 4 4 4 +bfchg 32 . d 1110101011000... .......... . . U U U . . 12 12 12 timing not quite correct +bfchg 32 . . 1110101011...... A..DXWL... . . U U U . . 20 20 20 +bfclr 32 . d 1110110011000... .......... . . U U U . . 12 12 12 +bfclr 32 . . 1110110011...... A..DXWL... . . U U U . . 20 20 20 +bfexts 32 . d 1110101111000... .......... . . U U U . . 8 8 8 +bfexts 32 . . 1110101111...... A..DXWLdx. . . U U U . . 15 15 15 +bfextu 32 . d 1110100111000... .......... . . U U U . . 8 8 8 +bfextu 32 . . 1110100111...... A..DXWLdx. . . U U U . . 15 15 15 +bfffo 32 . d 1110110111000... .......... . . U U U . . 18 18 18 +bfffo 32 . . 1110110111...... A..DXWLdx. . . U U U . . 28 28 28 +bfins 32 . d 1110111111000... .......... . . U U U . . 10 10 10 +bfins 32 . . 1110111111...... A..DXWL... . . U U U . . 17 17 17 +bfset 32 . d 1110111011000... .......... . . U U U . . 12 12 12 +bfset 32 . . 1110111011...... A..DXWL... . . U U U . . 20 20 20 +bftst 32 . d 1110100011000... .......... . . U U U . . 6 6 6 +bftst 32 . . 1110100011...... A..DXWLdx. . . U U U . . 13 13 13 +bkpt 0 . . 0100100001001... .......... . U U U U . 10 10 10 10 +bra 8 . . 01100000........ .......... U U U U U 10 10 10 10 10 +bra 16 . . 0110000000000000 .......... U U U U U 10 10 10 10 10 +bra 32 . . 0110000011111111 .......... U U U U U 10 10 10 10 10 +bset 32 r d 0000...111000... .......... U U U U U 8 8 4 4 4 +bset 8 r . 0000...111...... A+-DXWL... U U U U U 8 8 4 4 4 +bset 8 s . 0000100011...... A+-DXWL... U U U U U 12 12 4 4 4 +bset 32 s d 0000100011000... .......... U U U U U 12 12 4 4 4 +bsr 8 . . 01100001........ .......... U U U U U 18 18 7 7 7 +bsr 16 . . 0110000100000000 .......... U U U U U 18 18 7 7 7 +bsr 32 . . 0110000111111111 .......... U U U U U 18 18 7 7 7 +btst 8 r . 0000...100...... A+-DXWLdxI U U U U U 4 4 4 4 4 +btst 32 r d 0000...100000... .......... U U U U U 6 6 4 4 4 +btst 8 s . 0000100000...... A+-DXWLdx. U U U U U 8 8 4 4 4 +btst 32 s d 0000100000000... .......... U U U U U 10 10 4 4 4 +callm 32 . . 0000011011...... A..DXWLdx. . . U U U . . 60 60 60 not properly emulated +cas 8 . . 0000101011...... A+-DXWL... . . U U U . . 12 12 12 +cas 16 . . 0000110011...... A+-DXWL... . . U U U . . 12 12 12 +cas 32 . . 0000111011...... A+-DXWL... . . U U U . . 12 12 12 +cas2 16 . . 0000110011111100 .......... . . U U U . . 12 12 12 +cas2 32 . . 0000111011111100 .......... . . U U U . . 12 12 12 +chk 16 . d 0100...110000... .......... U U U U U 10 8 8 8 8 +chk 16 . . 0100...110...... A+-DXWLdxI U U U U U 10 8 8 8 8 +chk 32 . d 0100...100000... .......... . . U U U . . 8 8 8 +chk 32 . . 0100...100...... A+-DXWLdxI . . U U U . . 8 8 8 +chk2cmp2 8 . pcdi 0000000011111010 .......... . . U U U . . 23 23 23 +chk2cmp2 8 . pcix 0000000011111011 .......... . . U U U . . 23 23 23 +chk2cmp2 8 . . 0000000011...... A..DXWL... . . U U U . . 18 18 18 +chk2cmp2 16 . pcdi 0000001011111010 .......... . . U U U . . 23 23 23 +chk2cmp2 16 . pcix 0000001011111011 .......... . . U U U . . 23 23 23 +chk2cmp2 16 . . 0000001011...... A..DXWL... . . U U U . . 18 18 18 +chk2cmp2 32 . pcdi 0000010011111010 .......... . . U U U . . 23 23 23 +chk2cmp2 32 . pcix 0000010011111011 .......... . . U U U . . 23 23 23 +chk2cmp2 32 . . 0000010011...... A..DXWL... . . U U U . . 18 18 18 +clr 8 . d 0100001000000... .......... U U U U U 4 4 2 2 2 +clr 8 . . 0100001000...... A+-DXWL... U U U U U 8 4 4 4 4 +clr 16 . d 0100001001000... .......... U U U U U 4 4 2 2 2 +clr 16 . . 0100001001...... A+-DXWL... U U U U U 8 4 4 4 4 +clr 32 . d 0100001010000... .......... U U U U U 6 6 2 2 2 +clr 32 . . 0100001010...... A+-DXWL... U U U U U 12 6 4 4 4 +cmp 8 . d 1011...000000... .......... U U U U U 4 4 2 2 2 +cmp 8 . . 1011...000...... A+-DXWLdxI U U U U U 4 4 2 2 2 +cmp 16 . d 1011...001000... .......... U U U U U 4 4 2 2 2 +cmp 16 . a 1011...001001... .......... U U U U U 4 4 2 2 2 +cmp 16 . . 1011...001...... A+-DXWLdxI U U U U U 4 4 2 2 2 +cmp 32 . d 1011...010000... .......... U U U U U 6 6 2 2 2 +cmp 32 . a 1011...010001... .......... U U U U U 6 6 2 2 2 +cmp 32 . . 1011...010...... A+-DXWLdxI U U U U U 6 6 2 2 2 +cmpa 16 . d 1011...011000... .......... U U U U U 6 6 4 4 4 +cmpa 16 . a 1011...011001... .......... U U U U U 6 6 4 4 4 +cmpa 16 . . 1011...011...... A+-DXWLdxI U U U U U 6 6 4 4 4 +cmpa 32 . d 1011...111000... .......... U U U U U 6 6 4 4 4 +cmpa 32 . a 1011...111001... .......... U U U U U 6 6 4 4 4 +cmpa 32 . . 1011...111...... A+-DXWLdxI U U U U U 6 6 4 4 4 +cmpi 8 . d 0000110000000... .......... U U U U U 8 8 2 2 2 +cmpi 8 . . 0000110000...... A+-DXWL... U U U U U 8 8 2 2 2 +cmpi 8 . pcdi 0000110000111010 .......... . . U U U . . 7 7 7 +cmpi 8 . pcix 0000110000111011 .......... . . U U U . . 9 9 9 +cmpi 16 . d 0000110001000... .......... U U U U U 8 8 2 2 2 +cmpi 16 . . 0000110001...... A+-DXWL... U U U U U 8 8 2 2 2 +cmpi 16 . pcdi 0000110001111010 .......... . . U U U . . 7 7 7 +cmpi 16 . pcix 0000110001111011 .......... . . U U U . . 9 9 9 +cmpi 32 . d 0000110010000... .......... U U U U U 14 12 2 2 2 +cmpi 32 . . 0000110010...... A+-DXWL... U U U U U 12 12 2 2 2 +cmpi 32 . pcdi 0000110010111010 .......... . . U U U . . 7 7 7 +cmpi 32 . pcix 0000110010111011 .......... . . U U U . . 9 9 9 +cmpm 8 . ax7 1011111100001... .......... U U U U U 12 12 9 9 9 +cmpm 8 . ay7 1011...100001111 .......... U U U U U 12 12 9 9 9 +cmpm 8 . axy7 1011111100001111 .......... U U U U U 12 12 9 9 9 +cmpm 8 . . 1011...100001... .......... U U U U U 12 12 9 9 9 +cmpm 16 . . 1011...101001... .......... U U U U U 12 12 9 9 9 +cmpm 32 . . 1011...110001... .......... U U U U U 20 20 9 9 9 +cpbcc 32 . . 1111...01....... .......... . . U U . . . 4 4 . unemulated +cpdbcc 32 . . 1111...001001... .......... . . U U . . . 4 4 . unemulated +cpgen 32 . . 1111...000...... .......... . . U U . . . 4 4 . unemulated +cpscc 32 . . 1111...001...... .......... . . U U . . . 4 4 . unemulated +cptrapcc 32 . . 1111...001111... .......... . . U U . . . 4 4 . unemulated +dbt 16 . . 0101000011001... .......... U U U U U 12 12 6 6 6 +dbf 16 . . 0101000111001... .......... U U U U U 12 12 6 6 6 +dbcc 16 . . 0101....11001... .......... U U U U U 12 12 6 6 6 +divs 16 . d 1000...111000... .......... U U U U U 158 122 56 56 56 +divs 16 . . 1000...111...... A+-DXWLdxI U U U U U 158 122 56 56 56 +divu 16 . d 1000...011000... .......... U U U U U 140 108 44 44 44 +divu 16 . . 1000...011...... A+-DXWLdxI U U U U U 140 108 44 44 44 +divl 32 . d 0100110001000... .......... . . U U U . . 84 84 84 +divl 32 . . 0100110001...... A+-DXWLdxI . . U U U . . 84 84 84 +eor 8 . d 1011...100000... .......... U U U U U 4 4 2 2 2 +eor 8 . . 1011...100...... A+-DXWL... U U U U U 8 8 4 4 4 +eor 16 . d 1011...101000... .......... U U U U U 4 4 2 2 2 +eor 16 . . 1011...101...... A+-DXWL... U U U U U 8 8 4 4 4 +eor 32 . d 1011...110000... .......... U U U U U 8 6 2 2 2 +eor 32 . . 1011...110...... A+-DXWL... U U U U U 12 12 4 4 4 +eori 16 toc . 0000101000111100 .......... U U U U U 20 16 12 12 12 +eori 16 tos . 0000101001111100 .......... S S S S S 20 16 12 12 12 +eori 8 . d 0000101000000... .......... U U U U U 8 8 2 2 2 +eori 8 . . 0000101000...... A+-DXWL... U U U U U 12 12 4 4 4 +eori 16 . d 0000101001000... .......... U U U U U 8 8 2 2 2 +eori 16 . . 0000101001...... A+-DXWL... U U U U U 12 12 4 4 4 +eori 32 . d 0000101010000... .......... U U U U U 16 14 2 2 2 +eori 32 . . 0000101010...... A+-DXWL... U U U U U 20 20 4 4 4 +exg 32 dd . 1100...101000... .......... U U U U U 6 6 2 2 2 +exg 32 aa . 1100...101001... .......... U U U U U 6 6 2 2 2 +exg 32 da . 1100...110001... .......... U U U U U 6 6 2 2 2 +ext 16 . . 0100100010000... .......... U U U U U 4 4 4 4 4 +ext 32 . . 0100100011000... .......... U U U U U 4 4 4 4 4 +extb 32 . . 0100100111000... .......... . . U U U . . 4 4 4 +illegal 0 . . 0100101011111100 .......... U U U U U 4 4 4 4 4 +jmp 32 . . 0100111011...... A..DXWLdx. U U U U U 4 4 0 0 0 +jsr 32 . . 0100111010...... A..DXWLdx. U U U U U 12 12 0 0 0 +lea 32 . . 0100...111...... A..DXWLdx. U U U U U 0 0 2 2 2 +link 16 . a7 0100111001010111 .......... U U U U U 16 16 5 5 5 +link 16 . . 0100111001010... .......... U U U U U 16 16 5 5 5 +link 32 . a7 0100100000001111 .......... . . U U U . . 6 6 6 +link 32 . . 0100100000001... .......... . . U U U . . 6 6 6 +lsr 8 s . 1110...000001... .......... U U U U U 6 6 4 4 4 +lsr 16 s . 1110...001001... .......... U U U U U 6 6 4 4 4 +lsr 32 s . 1110...010001... .......... U U U U U 8 8 4 4 4 +lsr 8 r . 1110...000101... .......... U U U U U 6 6 6 6 6 +lsr 16 r . 1110...001101... .......... U U U U U 6 6 6 6 6 +lsr 32 r . 1110...010101... .......... U U U U U 8 8 6 6 6 +lsr 16 . . 1110001011...... A+-DXWL... U U U U U 8 8 5 5 5 +lsl 8 s . 1110...100001... .......... U U U U U 6 6 4 4 4 +lsl 16 s . 1110...101001... .......... U U U U U 6 6 4 4 4 +lsl 32 s . 1110...110001... .......... U U U U U 8 8 4 4 4 +lsl 8 r . 1110...100101... .......... U U U U U 6 6 6 6 6 +lsl 16 r . 1110...101101... .......... U U U U U 6 6 6 6 6 +lsl 32 r . 1110...110101... .......... U U U U U 8 8 6 6 6 +lsl 16 . . 1110001111...... A+-DXWL... U U U U U 8 8 5 5 5 +move 8 d d 0001...000000... .......... U U U U U 4 4 2 2 2 +move 8 d . 0001...000...... A+-DXWLdxI U U U U U 4 4 2 2 2 +move 8 ai d 0001...010000... .......... U U U U U 8 8 4 4 4 +move 8 ai . 0001...010...... A+-DXWLdxI U U U U U 8 8 4 4 4 +move 8 pi d 0001...011000... .......... U U U U U 8 8 4 4 4 +move 8 pi . 0001...011...... A+-DXWLdxI U U U U U 8 8 4 4 4 +move 8 pi7 d 0001111011000... .......... U U U U U 8 8 4 4 4 +move 8 pi7 . 0001111011...... A+-DXWLdxI U U U U U 8 8 4 4 4 +move 8 pd d 0001...100000... .......... U U U U U 8 8 5 5 5 +move 8 pd . 0001...100...... A+-DXWLdxI U U U U U 8 8 5 5 5 +move 8 pd7 d 0001111100000... .......... U U U U U 8 8 5 5 5 +move 8 pd7 . 0001111100...... A+-DXWLdxI U U U U U 8 8 5 5 5 +move 8 di d 0001...101000... .......... U U U U U 12 12 5 5 5 +move 8 di . 0001...101...... A+-DXWLdxI U U U U U 12 12 5 5 5 +move 8 ix d 0001...110000... .......... U U U U U 14 14 7 7 7 +move 8 ix . 0001...110...... A+-DXWLdxI U U U U U 14 14 7 7 7 +move 8 aw d 0001000111000... .......... U U U U U 12 12 4 4 4 +move 8 aw . 0001000111...... A+-DXWLdxI U U U U U 12 12 4 4 4 +move 8 al d 0001001111000... .......... U U U U U 16 16 6 6 6 +move 8 al . 0001001111...... A+-DXWLdxI U U U U U 16 16 6 6 6 +move 16 d d 0011...000000... .......... U U U U U 4 4 2 2 2 +move 16 d a 0011...000001... .......... U U U U U 4 4 2 2 2 +move 16 d . 0011...000...... A+-DXWLdxI U U U U U 4 4 2 2 2 +move 16 ai d 0011...010000... .......... U U U U U 8 8 4 4 4 +move 16 ai a 0011...010001... .......... U U U U U 8 8 4 4 4 +move 16 ai . 0011...010...... A+-DXWLdxI U U U U U 8 8 4 4 4 +move 16 pi d 0011...011000... .......... U U U U U 8 8 4 4 4 +move 16 pi a 0011...011001... .......... U U U U U 8 8 4 4 4 +move 16 pi . 0011...011...... A+-DXWLdxI U U U U U 8 8 4 4 4 +move 16 pd d 0011...100000... .......... U U U U U 8 8 5 5 5 +move 16 pd a 0011...100001... .......... U U U U U 8 8 5 5 5 +move 16 pd . 0011...100...... A+-DXWLdxI U U U U U 8 8 5 5 5 +move 16 di d 0011...101000... .......... U U U U U 12 12 5 5 5 +move 16 di a 0011...101001... .......... U U U U U 12 12 5 5 5 +move 16 di . 0011...101...... A+-DXWLdxI U U U U U 12 12 5 5 5 +move 16 ix d 0011...110000... .......... U U U U U 14 14 7 7 7 +move 16 ix a 0011...110001... .......... U U U U U 14 14 7 7 7 +move 16 ix . 0011...110...... A+-DXWLdxI U U U U U 14 14 7 7 7 +move 16 aw d 0011000111000... .......... U U U U U 12 12 4 4 4 +move 16 aw a 0011000111001... .......... U U U U U 12 12 4 4 4 +move 16 aw . 0011000111...... A+-DXWLdxI U U U U U 12 12 4 4 4 +move 16 al d 0011001111000... .......... U U U U U 16 16 6 6 6 +move 16 al a 0011001111001... .......... U U U U U 16 16 6 6 6 +move 16 al . 0011001111...... A+-DXWLdxI U U U U U 16 16 6 6 6 +move 32 d d 0010...000000... .......... U U U U U 4 4 2 2 2 +move 32 d a 0010...000001... .......... U U U U U 4 4 2 2 2 +move 32 d . 0010...000...... A+-DXWLdxI U U U U U 4 4 2 2 2 +move 32 ai d 0010...010000... .......... U U U U U 12 12 4 4 4 +move 32 ai a 0010...010001... .......... U U U U U 12 12 4 4 4 +move 32 ai . 0010...010...... A+-DXWLdxI U U U U U 12 12 4 4 4 +move 32 pi d 0010...011000... .......... U U U U U 12 12 4 4 4 +move 32 pi a 0010...011001... .......... U U U U U 12 12 4 4 4 +move 32 pi . 0010...011...... A+-DXWLdxI U U U U U 12 12 4 4 4 +move 32 pd d 0010...100000... .......... U U U U U 12 14 5 5 5 +move 32 pd a 0010...100001... .......... U U U U U 12 14 5 5 5 +move 32 pd . 0010...100...... A+-DXWLdxI U U U U U 12 14 5 5 5 +move 32 di d 0010...101000... .......... U U U U U 16 16 5 5 5 +move 32 di a 0010...101001... .......... U U U U U 16 16 5 5 5 +move 32 di . 0010...101...... A+-DXWLdxI U U U U U 16 16 5 5 5 +move 32 ix d 0010...110000... .......... U U U U U 18 18 7 7 7 +move 32 ix a 0010...110001... .......... U U U U U 18 18 7 7 7 +move 32 ix . 0010...110...... A+-DXWLdxI U U U U U 18 18 7 7 7 +move 32 aw d 0010000111000... .......... U U U U U 16 16 4 4 4 +move 32 aw a 0010000111001... .......... U U U U U 16 16 4 4 4 +move 32 aw . 0010000111...... A+-DXWLdxI U U U U U 16 16 4 4 4 +move 32 al d 0010001111000... .......... U U U U U 20 20 6 6 6 +move 32 al a 0010001111001... .......... U U U U U 20 20 6 6 6 +move 32 al . 0010001111...... A+-DXWLdxI U U U U U 20 20 6 6 6 +movea 16 . d 0011...001000... .......... U U U U U 4 4 2 2 2 +movea 16 . a 0011...001001... .......... U U U U U 4 4 2 2 2 +movea 16 . . 0011...001...... A+-DXWLdxI U U U U U 4 4 2 2 2 +movea 32 . d 0010...001000... .......... U U U U U 4 4 2 2 2 +movea 32 . a 0010...001001... .......... U U U U U 4 4 2 2 2 +movea 32 . . 0010...001...... A+-DXWLdxI U U U U U 4 4 2 2 2 +move 16 frc d 0100001011000... .......... . U U U U . 4 4 4 4 +move 16 frc . 0100001011...... A+-DXWL... . U U U U . 8 4 4 4 +move 16 toc d 0100010011000... .......... U U U U U 12 12 4 4 4 +move 16 toc . 0100010011...... A+-DXWLdxI U U U U U 12 12 4 4 4 +move 16 frs d 0100000011000... .......... U S S S S 6 4 8 8 8 U only for 000 +move 16 frs . 0100000011...... A+-DXWL... U S S S S 8 8 8 8 8 U only for 000 +move 16 tos d 0100011011000... .......... S S S S S 12 12 8 8 8 +move 16 tos . 0100011011...... A+-DXWLdxI S S S S S 12 12 8 8 8 +move 32 fru . 0100111001101... .......... S S S S S 4 6 2 2 2 +move 32 tou . 0100111001100... .......... S S S S S 4 6 2 2 2 +movec 32 cr . 0100111001111010 .......... . S S S S . 12 6 6 6 +movec 32 rc . 0100111001111011 .......... . S S S S . 10 12 12 12 +movem 16 re pd 0100100010100... .......... U U U U U 8 8 4 4 4 +movem 16 re . 0100100010...... A..DXWL... U U U U U 8 8 4 4 4 +movem 32 re pd 0100100011100... .......... U U U U U 8 8 4 4 4 +movem 32 re . 0100100011...... A..DXWL... U U U U U 8 8 4 4 4 +movem 16 er pi 0100110010011... .......... U U U U U 12 12 8 8 8 +movem 16 er pcdi 0100110010111010 .......... U U U U U 16 16 9 9 9 +movem 16 er pcix 0100110010111011 .......... U U U U U 18 18 11 11 11 +movem 16 er . 0100110010...... A..DXWL... U U U U U 12 12 8 8 8 +movem 32 er pi 0100110011011... .......... U U U U U 12 12 8 8 8 +movem 32 er pcdi 0100110011111010 .......... U U U U U 16 16 9 9 9 +movem 32 er pcix 0100110011111011 .......... U U U U U 18 18 11 11 11 +movem 32 er . 0100110011...... A..DXWL... U U U U U 12 12 8 8 8 +movep 16 er . 0000...100001... .......... U U U U U 16 16 12 12 12 +movep 32 er . 0000...101001... .......... U U U U U 24 24 18 18 18 +movep 16 re . 0000...110001... .......... U U U U U 16 16 11 11 11 +movep 32 re . 0000...111001... .......... U U U U U 24 24 17 17 17 +moveq 32 . . 0111...0........ .......... U U U U U 4 4 2 2 2 +moves 8 . . 0000111000...... A+-DXWL... . S S S S . 14 5 5 5 +moves 16 . . 0000111001...... A+-DXWL... . S S S S . 14 5 5 5 +moves 32 . . 0000111010...... A+-DXWL... . S S S S . 16 5 5 5 +move16 32 . . 1111011000100... .......... . . . . U . . . . 4 TODO: correct timing +muls 16 . d 1100...111000... .......... U U U U U 54 32 27 27 27 +muls 16 . . 1100...111...... A+-DXWLdxI U U U U U 54 32 27 27 27 +mulu 16 . d 1100...011000... .......... U U U U U 54 30 27 27 27 +mulu 16 . . 1100...011...... A+-DXWLdxI U U U U U 54 30 27 27 27 +mull 32 . d 0100110000000... .......... . . U U U . . 43 43 43 +mull 32 . . 0100110000...... A+-DXWLdxI . . U U U . . 43 43 43 +nbcd 8 . d 0100100000000... .......... U U U U U 6 6 6 6 6 +nbcd 8 . . 0100100000...... A+-DXWL... U U U U U 8 8 6 6 6 +neg 8 . d 0100010000000... .......... U U U U U 4 4 2 2 2 +neg 8 . . 0100010000...... A+-DXWL... U U U U U 8 8 4 4 4 +neg 16 . d 0100010001000... .......... U U U U U 4 4 2 2 2 +neg 16 . . 0100010001...... A+-DXWL... U U U U U 8 8 4 4 4 +neg 32 . d 0100010010000... .......... U U U U U 6 6 2 2 2 +neg 32 . . 0100010010...... A+-DXWL... U U U U U 12 12 4 4 4 +negx 8 . d 0100000000000... .......... U U U U U 4 4 2 2 2 +negx 8 . . 0100000000...... A+-DXWL... U U U U U 8 8 4 4 4 +negx 16 . d 0100000001000... .......... U U U U U 4 4 2 2 2 +negx 16 . . 0100000001...... A+-DXWL... U U U U U 8 8 4 4 4 +negx 32 . d 0100000010000... .......... U U U U U 6 6 2 2 2 +negx 32 . . 0100000010...... A+-DXWL... U U U U U 12 12 4 4 4 +nop 0 . . 0100111001110001 .......... U U U U U 4 4 2 2 2 +not 8 . d 0100011000000... .......... U U U U U 4 4 2 2 2 +not 8 . . 0100011000...... A+-DXWL... U U U U U 8 8 4 4 4 +not 16 . d 0100011001000... .......... U U U U U 4 4 2 2 2 +not 16 . . 0100011001...... A+-DXWL... U U U U U 8 8 4 4 4 +not 32 . d 0100011010000... .......... U U U U U 6 6 2 2 2 +not 32 . . 0100011010...... A+-DXWL... U U U U U 12 12 4 4 4 +or 8 er d 1000...000000... .......... U U U U U 4 4 2 2 2 +or 8 er . 1000...000...... A+-DXWLdxI U U U U U 4 4 2 2 2 +or 16 er d 1000...001000... .......... U U U U U 4 4 2 2 2 +or 16 er . 1000...001...... A+-DXWLdxI U U U U U 4 4 2 2 2 +or 32 er d 1000...010000... .......... U U U U U 6 6 2 2 2 +or 32 er . 1000...010...... A+-DXWLdxI U U U U U 6 6 2 2 2 +or 8 re . 1000...100...... A+-DXWL... U U U U U 8 8 4 4 4 +or 16 re . 1000...101...... A+-DXWL... U U U U U 8 8 4 4 4 +or 32 re . 1000...110...... A+-DXWL... U U U U U 12 12 4 4 4 +ori 16 toc . 0000000000111100 .......... U U U U U 20 16 12 12 12 +ori 16 tos . 0000000001111100 .......... S S S S S 20 16 12 12 12 +ori 8 . d 0000000000000... .......... U U U U U 8 8 2 2 2 +ori 8 . . 0000000000...... A+-DXWL... U U U U U 12 12 4 4 4 +ori 16 . d 0000000001000... .......... U U U U U 8 8 2 2 2 +ori 16 . . 0000000001...... A+-DXWL... U U U U U 12 12 4 4 4 +ori 32 . d 0000000010000... .......... U U U U U 16 14 2 2 2 +ori 32 . . 0000000010...... A+-DXWL... U U U U U 20 20 4 4 4 +pack 16 rr . 1000...101000... .......... . . U U U . . 6 6 6 +pack 16 mm ax7 1000111101001... .......... . . U U U . . 13 13 13 +pack 16 mm ay7 1000...101001111 .......... . . U U U . . 13 13 13 +pack 16 mm axy7 1000111101001111 .......... . . U U U . . 13 13 13 +pack 16 mm . 1000...101001... .......... . . U U U . . 13 13 13 +pea 32 . . 0100100001...... A..DXWLdx. U U U U U 6 6 5 5 5 +pflush 32 . . 1111010100011000 .......... . . . . S . . . . 4 TODO: correct timing +pmmu 32 . . 1111000......... .......... . . S S S . . 8 8 8 +reset 0 . . 0100111001110000 .......... S S S S S 0 0 0 0 0 +ror 8 s . 1110...000011... .......... U U U U U 6 6 8 8 8 +ror 16 s . 1110...001011... .......... U U U U U 6 6 8 8 8 +ror 32 s . 1110...010011... .......... U U U U U 8 8 8 8 8 +ror 8 r . 1110...000111... .......... U U U U U 6 6 8 8 8 +ror 16 r . 1110...001111... .......... U U U U U 6 6 8 8 8 +ror 32 r . 1110...010111... .......... U U U U U 8 8 8 8 8 +ror 16 . . 1110011011...... A+-DXWL... U U U U U 8 8 7 7 7 +rol 8 s . 1110...100011... .......... U U U U U 6 6 8 8 8 +rol 16 s . 1110...101011... .......... U U U U U 6 6 8 8 8 +rol 32 s . 1110...110011... .......... U U U U U 8 8 8 8 8 +rol 8 r . 1110...100111... .......... U U U U U 6 6 8 8 8 +rol 16 r . 1110...101111... .......... U U U U U 6 6 8 8 8 +rol 32 r . 1110...110111... .......... U U U U U 8 8 8 8 8 +rol 16 . . 1110011111...... A+-DXWL... U U U U U 8 8 7 7 7 +roxr 8 s . 1110...000010... .......... U U U U U 6 6 12 12 12 +roxr 16 s . 1110...001010... .......... U U U U U 6 6 12 12 12 +roxr 32 s . 1110...010010... .......... U U U U U 8 8 12 12 12 +roxr 8 r . 1110...000110... .......... U U U U U 6 6 12 12 12 +roxr 16 r . 1110...001110... .......... U U U U U 6 6 12 12 12 +roxr 32 r . 1110...010110... .......... U U U U U 8 8 12 12 12 +roxr 16 . . 1110010011...... A+-DXWL... U U U U U 8 8 5 5 5 +roxl 8 s . 1110...100010... .......... U U U U U 6 6 12 12 12 +roxl 16 s . 1110...101010... .......... U U U U U 6 6 12 12 12 +roxl 32 s . 1110...110010... .......... U U U U U 8 8 12 12 12 +roxl 8 r . 1110...100110... .......... U U U U U 6 6 12 12 12 +roxl 16 r . 1110...101110... .......... U U U U U 6 6 12 12 12 +roxl 32 r . 1110...110110... .......... U U U U U 8 8 12 12 12 +roxl 16 . . 1110010111...... A+-DXWL... U U U U U 8 8 5 5 5 +rtd 32 . . 0100111001110100 .......... . U U U U . 16 10 10 10 +rte 32 . . 0100111001110011 .......... S S S S S 20 24 20 20 20 bus fault not emulated +rtm 32 . . 000001101100.... .......... . . U U U . . 19 19 19 not properly emulated +rtr 32 . . 0100111001110111 .......... U U U U U 20 20 14 14 14 +rts 32 . . 0100111001110101 .......... U U U U U 16 16 10 10 10 +sbcd 8 rr . 1000...100000... .......... U U U U U 6 6 4 4 4 +sbcd 8 mm ax7 1000111100001... .......... U U U U U 18 18 16 16 16 +sbcd 8 mm ay7 1000...100001111 .......... U U U U U 18 18 16 16 16 +sbcd 8 mm axy7 1000111100001111 .......... U U U U U 18 18 16 16 16 +sbcd 8 mm . 1000...100001... .......... U U U U U 18 18 16 16 16 +st 8 . d 0101000011000... .......... U U U U U 6 4 4 4 4 +st 8 . . 0101000011...... A+-DXWL... U U U U U 8 8 6 6 6 +sf 8 . d 0101000111000... .......... U U U U U 4 4 4 4 4 +sf 8 . . 0101000111...... A+-DXWL... U U U U U 8 8 6 6 6 +scc 8 . d 0101....11000... .......... U U U U U 4 4 4 4 4 +scc 8 . . 0101....11...... A+-DXWL... U U U U U 8 8 6 6 6 +stop 0 . . 0100111001110010 .......... S S S S S 4 4 8 8 8 +sub 8 er d 1001...000000... .......... U U U U U 4 4 2 2 2 +sub 8 er . 1001...000...... A+-DXWLdxI U U U U U 4 4 2 2 2 +sub 16 er d 1001...001000... .......... U U U U U 4 4 2 2 2 +sub 16 er a 1001...001001... .......... U U U U U 4 4 2 2 2 +sub 16 er . 1001...001...... A+-DXWLdxI U U U U U 4 4 2 2 2 +sub 32 er d 1001...010000... .......... U U U U U 6 6 2 2 2 +sub 32 er a 1001...010001... .......... U U U U U 6 6 2 2 2 +sub 32 er . 1001...010...... A+-DXWLdxI U U U U U 6 6 2 2 2 +sub 8 re . 1001...100...... A+-DXWL... U U U U U 8 8 4 4 4 +sub 16 re . 1001...101...... A+-DXWL... U U U U U 8 8 4 4 4 +sub 32 re . 1001...110...... A+-DXWL... U U U U U 12 12 4 4 4 +suba 16 . d 1001...011000... .......... U U U U U 8 8 2 2 2 +suba 16 . a 1001...011001... .......... U U U U U 8 8 2 2 2 +suba 16 . . 1001...011...... A+-DXWLdxI U U U U U 8 8 2 2 2 +suba 32 . d 1001...111000... .......... U U U U U 6 6 2 2 2 +suba 32 . a 1001...111001... .......... U U U U U 6 6 2 2 2 +suba 32 . . 1001...111...... A+-DXWLdxI U U U U U 6 6 2 2 2 +subi 8 . d 0000010000000... .......... U U U U U 8 8 2 2 2 +subi 8 . . 0000010000...... A+-DXWL... U U U U U 12 12 4 4 4 +subi 16 . d 0000010001000... .......... U U U U U 8 8 2 2 2 +subi 16 . . 0000010001...... A+-DXWL... U U U U U 12 12 4 4 4 +subi 32 . d 0000010010000... .......... U U U U U 16 14 2 2 2 +subi 32 . . 0000010010...... A+-DXWL... U U U U U 20 20 4 4 4 +subq 8 . d 0101...100000... .......... U U U U U 4 4 2 2 2 +subq 8 . . 0101...100...... A+-DXWL... U U U U U 8 8 4 4 4 +subq 16 . d 0101...101000... .......... U U U U U 4 4 2 2 2 +subq 16 . a 0101...101001... .......... U U U U U 8 4 2 2 2 +subq 16 . . 0101...101...... A+-DXWL... U U U U U 8 8 4 4 4 +subq 32 . d 0101...110000... .......... U U U U U 8 8 2 2 2 +subq 32 . a 0101...110001... .......... U U U U U 8 8 2 2 2 +subq 32 . . 0101...110...... A+-DXWL... U U U U U 12 12 4 4 4 +subx 8 rr . 1001...100000... .......... U U U U U 4 4 2 2 2 +subx 16 rr . 1001...101000... .......... U U U U U 4 4 2 2 2 +subx 32 rr . 1001...110000... .......... U U U U U 8 6 2 2 2 +subx 8 mm ax7 1001111100001... .......... U U U U U 18 18 12 12 12 +subx 8 mm ay7 1001...100001111 .......... U U U U U 18 18 12 12 12 +subx 8 mm axy7 1001111100001111 .......... U U U U U 18 18 12 12 12 +subx 8 mm . 1001...100001... .......... U U U U U 18 18 12 12 12 +subx 16 mm . 1001...101001... .......... U U U U U 18 18 12 12 12 +subx 32 mm . 1001...110001... .......... U U U U U 30 30 12 12 12 +swap 32 . . 0100100001000... .......... U U U U U 4 4 4 4 4 +tas 8 . d 0100101011000... .......... U U U U U 4 4 4 4 4 +tas 8 . . 0100101011...... A+-DXWL... U U U U U 14 14 12 12 12 +trap 0 . . 010011100100.... .......... U U U U U 4 4 4 4 4 +trapt 0 . . 0101000011111100 .......... . . U U U . . 4 4 4 +trapt 16 . . 0101000011111010 .......... . . U U U . . 6 6 6 +trapt 32 . . 0101000011111011 .......... . . U U U . . 8 8 8 +trapf 0 . . 0101000111111100 .......... . . U U U . . 4 4 4 +trapf 16 . . 0101000111111010 .......... . . U U U . . 6 6 6 +trapf 32 . . 0101000111111011 .......... . . U U U . . 8 8 8 +trapcc 0 . . 0101....11111100 .......... . . U U U . . 4 4 4 +trapcc 16 . . 0101....11111010 .......... . . U U U . . 6 6 6 +trapcc 32 . . 0101....11111011 .......... . . U U U . . 8 8 8 +trapv 0 . . 0100111001110110 .......... U U U U U 4 4 4 4 4 +tst 8 . d 0100101000000... .......... U U U U U 4 4 2 2 2 +tst 8 . . 0100101000...... A+-DXWL... U U U U U 4 4 2 2 2 +tst 8 . pcdi 0100101000111010 .......... . . U U U . . 7 7 7 +tst 8 . pcix 0100101000111011 .......... . . U U U . . 9 9 9 +tst 8 . i 0100101000111100 .......... . . U U U . . 6 6 6 +tst 16 . d 0100101001000... .......... U U U U U 4 4 2 2 2 +tst 16 . a 0100101001001... .......... . . U U U . . 2 2 2 +tst 16 . . 0100101001...... A+-DXWL... U U U U U 4 4 2 2 2 +tst 16 . pcdi 0100101001111010 .......... . . U U U . . 7 7 7 +tst 16 . pcix 0100101001111011 .......... . . U U U . . 9 9 9 +tst 16 . i 0100101001111100 .......... . . U U U . . 6 6 6 +tst 32 . d 0100101010000... .......... U U U U U 4 4 2 2 2 +tst 32 . a 0100101010001... .......... . . U U U . . 2 2 2 +tst 32 . . 0100101010...... A+-DXWL... U U U U U 4 4 2 2 2 +tst 32 . pcdi 0100101010111010 .......... . . U U U . . 7 7 7 +tst 32 . pcix 0100101010111011 .......... . . U U U . . 9 9 9 +tst 32 . i 0100101010111100 .......... . . U U U . . 6 6 6 +unlk 32 . a7 0100111001011111 .......... U U U U U 12 12 6 6 6 +unlk 32 . . 0100111001011... .......... U U U U U 12 12 6 6 6 +unpk 16 rr . 1000...110000... .......... . . U U U . . 8 8 8 +unpk 16 mm ax7 1000111110001... .......... . . U U U . . 13 13 13 +unpk 16 mm ay7 1000...110001111 .......... . . U U U . . 13 13 13 +unpk 16 mm axy7 1000111110001111 .......... . . U U U . . 13 13 13 +unpk 16 mm . 1000...110001... .......... . . U U U . . 13 13 13 + + + +XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +M68KMAKE_OPCODE_HANDLER_BODY + +M68KMAKE_OP(1010, 0, ., .) +{ + m68ki_exception_1010(m68k); +} + + +M68KMAKE_OP(1111, 0, ., .) +{ + m68ki_exception_1111(m68k); +} + + +M68KMAKE_OP(040fpu0, 32, ., .) +{ + if(CPU_TYPE_IS_030_PLUS(m68k->cpu_type)) + { + m68040_fpu_op0(m68k); + return; + } + m68ki_exception_1111(m68k); +} + + +M68KMAKE_OP(040fpu1, 32, ., .) +{ + if(CPU_TYPE_IS_030_PLUS(m68k->cpu_type)) + { + m68040_fpu_op1(m68k); + return; + } + m68ki_exception_1111(m68k); +} + + + +M68KMAKE_OP(abcd, 8, rr, .) +{ + UINT32* r_dst = &DX; + UINT32 src = DY; + UINT32 dst = *r_dst; + UINT32 res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1(m68k); + + m68k->v_flag = ~res; /* Undefined V behavior */ + + if(res > 9) + res += 6; + res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst); + m68k->x_flag = m68k->c_flag = (res > 0x99) << 8; + if(m68k->c_flag) + res -= 0xa0; + + m68k->v_flag &= res; /* Undefined V behavior part II */ + m68k->n_flag = NFLAG_8(res); /* Undefined N behavior */ + + res = MASK_OUT_ABOVE_8(res); + m68k->not_z_flag |= res; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; +} + + +M68KMAKE_OP(abcd, 8, mm, ax7) +{ + UINT32 src = OPER_AY_PD_8(m68k); + UINT32 ea = EA_A7_PD_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1(m68k); + + m68k->v_flag = ~res; /* Undefined V behavior */ + + if(res > 9) + res += 6; + res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst); + m68k->x_flag = m68k->c_flag = (res > 0x99) << 8; + if(m68k->c_flag) + res -= 0xa0; + + m68k->v_flag &= res; /* Undefined V behavior part II */ + m68k->n_flag = NFLAG_8(res); /* Undefined N behavior */ + + res = MASK_OUT_ABOVE_8(res); + m68k->not_z_flag |= res; + + m68ki_write_8(m68k, ea, res); +} + + +M68KMAKE_OP(abcd, 8, mm, ay7) +{ + UINT32 src = OPER_A7_PD_8(m68k); + UINT32 ea = EA_AX_PD_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1(m68k); + + m68k->v_flag = ~res; /* Undefined V behavior */ + + if(res > 9) + res += 6; + res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst); + m68k->x_flag = m68k->c_flag = (res > 0x99) << 8; + if(m68k->c_flag) + res -= 0xa0; + + m68k->v_flag &= res; /* Undefined V behavior part II */ + m68k->n_flag = NFLAG_8(res); /* Undefined N behavior */ + + res = MASK_OUT_ABOVE_8(res); + m68k->not_z_flag |= res; + + m68ki_write_8(m68k, ea, res); +} + + +M68KMAKE_OP(abcd, 8, mm, axy7) +{ + UINT32 src = OPER_A7_PD_8(m68k); + UINT32 ea = EA_A7_PD_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1(m68k); + + m68k->v_flag = ~res; /* Undefined V behavior */ + + if(res > 9) + res += 6; + res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst); + m68k->x_flag = m68k->c_flag = (res > 0x99) << 8; + if(m68k->c_flag) + res -= 0xa0; + + m68k->v_flag &= res; /* Undefined V behavior part II */ + m68k->n_flag = NFLAG_8(res); /* Undefined N behavior */ + + res = MASK_OUT_ABOVE_8(res); + m68k->not_z_flag |= res; + + m68ki_write_8(m68k, ea, res); +} + + +M68KMAKE_OP(abcd, 8, mm, .) +{ + UINT32 src = OPER_AY_PD_8(m68k); + UINT32 ea = EA_AX_PD_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1(m68k); + + m68k->v_flag = ~res; /* Undefined V behavior */ + + if(res > 9) + res += 6; + res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst); + m68k->x_flag = m68k->c_flag = (res > 0x99) << 8; + if(m68k->c_flag) + res -= 0xa0; + + m68k->v_flag &= res; /* Undefined V behavior part II */ + m68k->n_flag = NFLAG_8(res); /* Undefined N behavior */ + + res = MASK_OUT_ABOVE_8(res); + m68k->not_z_flag |= res; + + m68ki_write_8(m68k, ea, res); +} + + +M68KMAKE_OP(add, 8, er, d) +{ + UINT32* r_dst = &DX; + UINT32 src = MASK_OUT_ABOVE_8(DY); + UINT32 dst = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | m68k->not_z_flag; +} + + +M68KMAKE_OP(add, 8, er, .) +{ + UINT32* r_dst = &DX; + UINT32 src = M68KMAKE_GET_OPER_AY_8; + UINT32 dst = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | m68k->not_z_flag; +} + + +M68KMAKE_OP(add, 16, er, d) +{ + UINT32* r_dst = &DX; + UINT32 src = MASK_OUT_ABOVE_16(DY); + UINT32 dst = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_16(res); + m68k->v_flag = VFLAG_ADD_16(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | m68k->not_z_flag; +} + + +M68KMAKE_OP(add, 16, er, a) +{ + UINT32* r_dst = &DX; + UINT32 src = MASK_OUT_ABOVE_16(AY); + UINT32 dst = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_16(res); + m68k->v_flag = VFLAG_ADD_16(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | m68k->not_z_flag; +} + + +M68KMAKE_OP(add, 16, er, .) +{ + UINT32* r_dst = &DX; + UINT32 src = M68KMAKE_GET_OPER_AY_16; + UINT32 dst = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_16(res); + m68k->v_flag = VFLAG_ADD_16(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | m68k->not_z_flag; +} + + +M68KMAKE_OP(add, 32, er, d) +{ + UINT32* r_dst = &DX; + UINT32 src = DY; + UINT32 dst = *r_dst; + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_ADD_32(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_ADD_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + *r_dst = m68k->not_z_flag; +} + + +M68KMAKE_OP(add, 32, er, a) +{ + UINT32* r_dst = &DX; + UINT32 src = AY; + UINT32 dst = *r_dst; + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_ADD_32(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_ADD_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + *r_dst = m68k->not_z_flag; +} + + +M68KMAKE_OP(add, 32, er, .) +{ + UINT32* r_dst = &DX; + UINT32 src = M68KMAKE_GET_OPER_AY_32; + UINT32 dst = *r_dst; + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_ADD_32(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_ADD_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + *r_dst = m68k->not_z_flag; +} + + +M68KMAKE_OP(add, 8, re, .) +{ + UINT32 ea = M68KMAKE_GET_EA_AY_8; + UINT32 src = MASK_OUT_ABOVE_8(DX); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +M68KMAKE_OP(add, 16, re, .) +{ + UINT32 ea = M68KMAKE_GET_EA_AY_16; + UINT32 src = MASK_OUT_ABOVE_16(DX); + UINT32 dst = m68ki_read_16(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_16(res); + m68k->v_flag = VFLAG_ADD_16(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +M68KMAKE_OP(add, 32, re, .) +{ + UINT32 ea = M68KMAKE_GET_EA_AY_32; + UINT32 src = DX; + UINT32 dst = m68ki_read_32(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_ADD_32(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_ADD_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(m68k, ea, m68k->not_z_flag); +} + + +M68KMAKE_OP(adda, 16, ., d) +{ + UINT32* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(DY)); +} + + +M68KMAKE_OP(adda, 16, ., a) +{ + UINT32* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(AY)); +} + + +M68KMAKE_OP(adda, 16, ., .) +{ + UINT32* r_dst = &AX; + UINT32 src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16); + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + src); +} + + +M68KMAKE_OP(adda, 32, ., d) +{ + UINT32* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + DY); +} + + +M68KMAKE_OP(adda, 32, ., a) +{ + UINT32* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + AY); +} + + +M68KMAKE_OP(adda, 32, ., .) +{ + UINT32* r_dst = &AX; + UINT32 src = M68KMAKE_GET_OPER_AY_32; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + src); +} + + +M68KMAKE_OP(addi, 8, ., d) +{ + UINT32* r_dst = &DY; + UINT32 src = OPER_I_8(m68k); + UINT32 dst = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | m68k->not_z_flag; +} + + +M68KMAKE_OP(addi, 8, ., .) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 ea = M68KMAKE_GET_EA_AY_8; + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +M68KMAKE_OP(addi, 16, ., d) +{ + UINT32* r_dst = &DY; + UINT32 src = OPER_I_16(m68k); + UINT32 dst = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_16(res); + m68k->v_flag = VFLAG_ADD_16(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | m68k->not_z_flag; +} + + +M68KMAKE_OP(addi, 16, ., .) +{ + UINT32 src = OPER_I_16(m68k); + UINT32 ea = M68KMAKE_GET_EA_AY_16; + UINT32 dst = m68ki_read_16(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_16(res); + m68k->v_flag = VFLAG_ADD_16(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +M68KMAKE_OP(addi, 32, ., d) +{ + UINT32* r_dst = &DY; + UINT32 src = OPER_I_32(m68k); + UINT32 dst = *r_dst; + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_ADD_32(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_ADD_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + *r_dst = m68k->not_z_flag; +} + + +M68KMAKE_OP(addi, 32, ., .) +{ + UINT32 src = OPER_I_32(m68k); + UINT32 ea = M68KMAKE_GET_EA_AY_32; + UINT32 dst = m68ki_read_32(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_ADD_32(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_ADD_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(m68k, ea, m68k->not_z_flag); +} + + +M68KMAKE_OP(addq, 8, ., d) +{ + UINT32* r_dst = &DY; + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 dst = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | m68k->not_z_flag; +} + + +M68KMAKE_OP(addq, 8, ., .) +{ + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 ea = M68KMAKE_GET_EA_AY_8; + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +M68KMAKE_OP(addq, 16, ., d) +{ + UINT32* r_dst = &DY; + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 dst = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_16(res); + m68k->v_flag = VFLAG_ADD_16(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | m68k->not_z_flag; +} + + +M68KMAKE_OP(addq, 16, ., a) +{ + UINT32* r_dst = &AY; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((m68k->ir >> 9) - 1) & 7) + 1); +} + + +M68KMAKE_OP(addq, 16, ., .) +{ + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 ea = M68KMAKE_GET_EA_AY_16; + UINT32 dst = m68ki_read_16(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_16(res); + m68k->v_flag = VFLAG_ADD_16(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +M68KMAKE_OP(addq, 32, ., d) +{ + UINT32* r_dst = &DY; + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 dst = *r_dst; + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_ADD_32(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_ADD_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + *r_dst = m68k->not_z_flag; +} + + +M68KMAKE_OP(addq, 32, ., a) +{ + UINT32* r_dst = &AY; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((m68k->ir >> 9) - 1) & 7) + 1); +} + + +M68KMAKE_OP(addq, 32, ., .) +{ + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 ea = M68KMAKE_GET_EA_AY_32; + UINT32 dst = m68ki_read_32(m68k, ea); + UINT32 res = src + dst; + + + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_ADD_32(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_ADD_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(m68k, ea, m68k->not_z_flag); +} + + +M68KMAKE_OP(addx, 8, rr, .) +{ + UINT32* r_dst = &DX; + UINT32 src = MASK_OUT_ABOVE_8(DY); + UINT32 dst = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = src + dst + XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + + res = MASK_OUT_ABOVE_8(res); + m68k->not_z_flag |= res; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; +} + + +M68KMAKE_OP(addx, 16, rr, .) +{ + UINT32* r_dst = &DX; + UINT32 src = MASK_OUT_ABOVE_16(DY); + UINT32 dst = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = src + dst + XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_16(res); + m68k->v_flag = VFLAG_ADD_16(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + + res = MASK_OUT_ABOVE_16(res); + m68k->not_z_flag |= res; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; +} + + +M68KMAKE_OP(addx, 32, rr, .) +{ + UINT32* r_dst = &DX; + UINT32 src = DY; + UINT32 dst = *r_dst; + UINT32 res = src + dst + XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_ADD_32(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_ADD_32(src, dst, res); + + res = MASK_OUT_ABOVE_32(res); + m68k->not_z_flag |= res; + + *r_dst = res; +} + + +M68KMAKE_OP(addx, 8, mm, ax7) +{ + UINT32 src = OPER_AY_PD_8(m68k); + UINT32 ea = EA_A7_PD_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = src + dst + XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + + res = MASK_OUT_ABOVE_8(res); + m68k->not_z_flag |= res; + + m68ki_write_8(m68k, ea, res); +} + + +M68KMAKE_OP(addx, 8, mm, ay7) +{ + UINT32 src = OPER_A7_PD_8(m68k); + UINT32 ea = EA_AX_PD_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = src + dst + XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + + res = MASK_OUT_ABOVE_8(res); + m68k->not_z_flag |= res; + + m68ki_write_8(m68k, ea, res); +} + + +M68KMAKE_OP(addx, 8, mm, axy7) +{ + UINT32 src = OPER_A7_PD_8(m68k); + UINT32 ea = EA_A7_PD_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = src + dst + XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + + res = MASK_OUT_ABOVE_8(res); + m68k->not_z_flag |= res; + + m68ki_write_8(m68k, ea, res); +} + + +M68KMAKE_OP(addx, 8, mm, .) +{ + UINT32 src = OPER_AY_PD_8(m68k); + UINT32 ea = EA_AX_PD_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = src + dst + XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + + res = MASK_OUT_ABOVE_8(res); + m68k->not_z_flag |= res; + + m68ki_write_8(m68k, ea, res); +} + + +M68KMAKE_OP(addx, 16, mm, .) +{ + UINT32 src = OPER_AY_PD_16(m68k); + UINT32 ea = EA_AX_PD_16(m68k); + UINT32 dst = m68ki_read_16(m68k, ea); + UINT32 res = src + dst + XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_16(res); + m68k->v_flag = VFLAG_ADD_16(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + + res = MASK_OUT_ABOVE_16(res); + m68k->not_z_flag |= res; + + m68ki_write_16(m68k, ea, res); +} + + +M68KMAKE_OP(addx, 32, mm, .) +{ + UINT32 src = OPER_AY_PD_32(m68k); + UINT32 ea = EA_AX_PD_32(m68k); + UINT32 dst = m68ki_read_32(m68k, ea); + UINT32 res = src + dst + XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_ADD_32(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_ADD_32(src, dst, res); + + res = MASK_OUT_ABOVE_32(res); + m68k->not_z_flag |= res; + + m68ki_write_32(m68k, ea, res); +} + + +M68KMAKE_OP(and, 8, er, d) +{ + m68k->not_z_flag = MASK_OUT_ABOVE_8(DX &= (DY | 0xffffff00)); + + m68k->n_flag = NFLAG_8(m68k->not_z_flag); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(and, 8, er, .) +{ + m68k->not_z_flag = MASK_OUT_ABOVE_8(DX &= (M68KMAKE_GET_OPER_AY_8 | 0xffffff00)); + + m68k->n_flag = NFLAG_8(m68k->not_z_flag); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(and, 16, er, d) +{ + m68k->not_z_flag = MASK_OUT_ABOVE_16(DX &= (DY | 0xffff0000)); + + m68k->n_flag = NFLAG_16(m68k->not_z_flag); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(and, 16, er, .) +{ + m68k->not_z_flag = MASK_OUT_ABOVE_16(DX &= (M68KMAKE_GET_OPER_AY_16 | 0xffff0000)); + + m68k->n_flag = NFLAG_16(m68k->not_z_flag); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(and, 32, er, d) +{ + m68k->not_z_flag = DX &= DY; + + m68k->n_flag = NFLAG_32(m68k->not_z_flag); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(and, 32, er, .) +{ + m68k->not_z_flag = DX &= M68KMAKE_GET_OPER_AY_32; + + m68k->n_flag = NFLAG_32(m68k->not_z_flag); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(and, 8, re, .) +{ + UINT32 ea = M68KMAKE_GET_EA_AY_8; + UINT32 res = DX & m68ki_read_8(m68k, ea); + + m68k->n_flag = NFLAG_8(res); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +M68KMAKE_OP(and, 16, re, .) +{ + UINT32 ea = M68KMAKE_GET_EA_AY_16; + UINT32 res = DX & m68ki_read_16(m68k, ea); + + m68k->n_flag = NFLAG_16(res); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +M68KMAKE_OP(and, 32, re, .) +{ + UINT32 ea = M68KMAKE_GET_EA_AY_32; + UINT32 res = DX & m68ki_read_32(m68k, ea); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + + m68ki_write_32(m68k, ea, res); +} + + +M68KMAKE_OP(andi, 8, ., d) +{ + m68k->not_z_flag = MASK_OUT_ABOVE_8(DY &= (OPER_I_8(m68k) | 0xffffff00)); + + m68k->n_flag = NFLAG_8(m68k->not_z_flag); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(andi, 8, ., .) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 ea = M68KMAKE_GET_EA_AY_8; + UINT32 res = src & m68ki_read_8(m68k, ea); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + + m68ki_write_8(m68k, ea, res); +} + + +M68KMAKE_OP(andi, 16, ., d) +{ + m68k->not_z_flag = MASK_OUT_ABOVE_16(DY &= (OPER_I_16(m68k) | 0xffff0000)); + + m68k->n_flag = NFLAG_16(m68k->not_z_flag); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(andi, 16, ., .) +{ + UINT32 src = OPER_I_16(m68k); + UINT32 ea = M68KMAKE_GET_EA_AY_16; + UINT32 res = src & m68ki_read_16(m68k, ea); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + + m68ki_write_16(m68k, ea, res); +} + + +M68KMAKE_OP(andi, 32, ., d) +{ + m68k->not_z_flag = DY &= (OPER_I_32(m68k)); + + m68k->n_flag = NFLAG_32(m68k->not_z_flag); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(andi, 32, ., .) +{ + UINT32 src = OPER_I_32(m68k); + UINT32 ea = M68KMAKE_GET_EA_AY_32; + UINT32 res = src & m68ki_read_32(m68k, ea); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + + m68ki_write_32(m68k, ea, res); +} + + +M68KMAKE_OP(andi, 16, toc, .) +{ + m68ki_set_ccr(m68k, m68ki_get_ccr(m68k) & OPER_I_16(m68k)); +} + + +M68KMAKE_OP(andi, 16, tos, .) +{ + if(m68k->s_flag) + { + UINT32 src = OPER_I_16(m68k); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_set_sr(m68k, m68ki_get_sr(m68k) & src); + return; + } + m68ki_exception_privilege_violation(m68k); +} + + +M68KMAKE_OP(asr, 8, s, .) +{ + UINT32* r_dst = &DY; + UINT32 shift = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 src = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = src >> shift; + + if(shift != 0) + m68k->remaining_cycles -= shift<cyc_shift; + + if(GET_MSB_8(src)) + res |= m68ki_shift_8_table[shift]; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->x_flag = m68k->c_flag = src << (9-shift); +} + + +M68KMAKE_OP(asr, 16, s, .) +{ + UINT32* r_dst = &DY; + UINT32 shift = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 src = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = src >> shift; + + if(shift != 0) + m68k->remaining_cycles -= shift<cyc_shift; + + if(GET_MSB_16(src)) + res |= m68ki_shift_16_table[shift]; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->x_flag = m68k->c_flag = src << (9-shift); +} + + +M68KMAKE_OP(asr, 32, s, .) +{ + UINT32* r_dst = &DY; + UINT32 shift = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 src = *r_dst; + UINT32 res = src >> shift; + + if(shift != 0) + m68k->remaining_cycles -= shift<cyc_shift; + + if(GET_MSB_32(src)) + res |= m68ki_shift_32_table[shift]; + + *r_dst = res; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->x_flag = m68k->c_flag = src << (9-shift); +} + + +M68KMAKE_OP(asr, 8, r, .) +{ + UINT32* r_dst = &DY; + UINT32 shift = DX & 0x3f; + UINT32 src = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = src >> shift; + + if(shift != 0) + { + m68k->remaining_cycles -= shift<cyc_shift; + + if(shift < 8) + { + if(GET_MSB_8(src)) + res |= m68ki_shift_8_table[shift]; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + m68k->x_flag = m68k->c_flag = src << (9-shift); + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + if(GET_MSB_8(src)) + { + *r_dst |= 0xff; + m68k->c_flag = CFLAG_SET; + m68k->x_flag = XFLAG_SET; + m68k->n_flag = NFLAG_SET; + m68k->not_z_flag = ZFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + *r_dst &= 0xffffff00; + m68k->c_flag = CFLAG_CLEAR; + m68k->x_flag = XFLAG_CLEAR; + m68k->n_flag = NFLAG_CLEAR; + m68k->not_z_flag = ZFLAG_SET; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + m68k->c_flag = CFLAG_CLEAR; + m68k->n_flag = NFLAG_8(src); + m68k->not_z_flag = src; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(asr, 16, r, .) +{ + UINT32* r_dst = &DY; + UINT32 shift = DX & 0x3f; + UINT32 src = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = src >> shift; + + if(shift != 0) + { + m68k->remaining_cycles -= shift<cyc_shift; + + if(shift < 16) + { + if(GET_MSB_16(src)) + res |= m68ki_shift_16_table[shift]; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + m68k->c_flag = m68k->x_flag = (src >> (shift - 1))<<8; + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + if(GET_MSB_16(src)) + { + *r_dst |= 0xffff; + m68k->c_flag = CFLAG_SET; + m68k->x_flag = XFLAG_SET; + m68k->n_flag = NFLAG_SET; + m68k->not_z_flag = ZFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + *r_dst &= 0xffff0000; + m68k->c_flag = CFLAG_CLEAR; + m68k->x_flag = XFLAG_CLEAR; + m68k->n_flag = NFLAG_CLEAR; + m68k->not_z_flag = ZFLAG_SET; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + m68k->c_flag = CFLAG_CLEAR; + m68k->n_flag = NFLAG_16(src); + m68k->not_z_flag = src; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(asr, 32, r, .) +{ + UINT32* r_dst = &DY; + UINT32 shift = DX & 0x3f; + UINT32 src = *r_dst; + UINT32 res = src >> shift; + + if(shift != 0) + { + m68k->remaining_cycles -= shift<cyc_shift; + + if(shift < 32) + { + if(GET_MSB_32(src)) + res |= m68ki_shift_32_table[shift]; + + *r_dst = res; + + m68k->c_flag = m68k->x_flag = (src >> (shift - 1))<<8; + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + if(GET_MSB_32(src)) + { + *r_dst = 0xffffffff; + m68k->c_flag = CFLAG_SET; + m68k->x_flag = XFLAG_SET; + m68k->n_flag = NFLAG_SET; + m68k->not_z_flag = ZFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + *r_dst = 0; + m68k->c_flag = CFLAG_CLEAR; + m68k->x_flag = XFLAG_CLEAR; + m68k->n_flag = NFLAG_CLEAR; + m68k->not_z_flag = ZFLAG_SET; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + m68k->c_flag = CFLAG_CLEAR; + m68k->n_flag = NFLAG_32(src); + m68k->not_z_flag = src; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(asr, 16, ., .) +{ + UINT32 ea = M68KMAKE_GET_EA_AY_16; + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = src >> 1; + + if(GET_MSB_16(src)) + res |= 0x8000; + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = m68k->x_flag = src << 8; +} + + +M68KMAKE_OP(asl, 8, s, .) +{ + UINT32* r_dst = &DY; + UINT32 shift = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 src = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = MASK_OUT_ABOVE_8(src << shift); + + if(shift != 0) + m68k->remaining_cycles -= shift<cyc_shift; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + m68k->x_flag = m68k->c_flag = src << shift; + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + src &= m68ki_shift_8_table[shift + 1]; + m68k->v_flag = (!(src == 0 || (src == m68ki_shift_8_table[shift + 1] && shift < 8)))<<7; +} + + +M68KMAKE_OP(asl, 16, s, .) +{ + UINT32* r_dst = &DY; + UINT32 shift = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 src = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = MASK_OUT_ABOVE_16(src << shift); + + if(shift != 0) + m68k->remaining_cycles -= shift<cyc_shift; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->x_flag = m68k->c_flag = src >> (8-shift); + src &= m68ki_shift_16_table[shift + 1]; + m68k->v_flag = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7; +} + + +M68KMAKE_OP(asl, 32, s, .) +{ + UINT32* r_dst = &DY; + UINT32 shift = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 src = *r_dst; + UINT32 res = MASK_OUT_ABOVE_32(src << shift); + + if(shift != 0) + m68k->remaining_cycles -= shift<cyc_shift; + + *r_dst = res; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->x_flag = m68k->c_flag = src >> (24-shift); + src &= m68ki_shift_32_table[shift + 1]; + m68k->v_flag = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7; +} + + +M68KMAKE_OP(asl, 8, r, .) +{ + UINT32* r_dst = &DY; + UINT32 shift = DX & 0x3f; + UINT32 src = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = MASK_OUT_ABOVE_8(src << shift); + + if(shift != 0) + { + m68k->remaining_cycles -= shift<cyc_shift; + + if(shift < 8) + { + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + m68k->x_flag = m68k->c_flag = src << shift; + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + src &= m68ki_shift_8_table[shift + 1]; + m68k->v_flag = (!(src == 0 || src == m68ki_shift_8_table[shift + 1]))<<7; + return; + } + + *r_dst &= 0xffffff00; + m68k->x_flag = m68k->c_flag = ((shift == 8 ? src & 1 : 0))<<8; + m68k->n_flag = NFLAG_CLEAR; + m68k->not_z_flag = ZFLAG_SET; + m68k->v_flag = (!(src == 0))<<7; + return; + } + + m68k->c_flag = CFLAG_CLEAR; + m68k->n_flag = NFLAG_8(src); + m68k->not_z_flag = src; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(asl, 16, r, .) +{ + UINT32* r_dst = &DY; + UINT32 shift = DX & 0x3f; + UINT32 src = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = MASK_OUT_ABOVE_16(src << shift); + + if(shift != 0) + { + m68k->remaining_cycles -= shift<cyc_shift; + + if(shift < 16) + { + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + m68k->x_flag = m68k->c_flag = (src << shift) >> 8; + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + src &= m68ki_shift_16_table[shift + 1]; + m68k->v_flag = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7; + return; + } + + *r_dst &= 0xffff0000; + m68k->x_flag = m68k->c_flag = ((shift == 16 ? src & 1 : 0))<<8; + m68k->n_flag = NFLAG_CLEAR; + m68k->not_z_flag = ZFLAG_SET; + m68k->v_flag = (!(src == 0))<<7; + return; + } + + m68k->c_flag = CFLAG_CLEAR; + m68k->n_flag = NFLAG_16(src); + m68k->not_z_flag = src; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(asl, 32, r, .) +{ + UINT32* r_dst = &DY; + UINT32 shift = DX & 0x3f; + UINT32 src = *r_dst; + UINT32 res = MASK_OUT_ABOVE_32(src << shift); + + if(shift != 0) + { + m68k->remaining_cycles -= shift<cyc_shift; + + if(shift < 32) + { + *r_dst = res; + m68k->x_flag = m68k->c_flag = (src >> (32 - shift)) << 8; + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + src &= m68ki_shift_32_table[shift + 1]; + m68k->v_flag = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7; + return; + } + + *r_dst = 0; + m68k->x_flag = m68k->c_flag = ((shift == 32 ? src & 1 : 0))<<8; + m68k->n_flag = NFLAG_CLEAR; + m68k->not_z_flag = ZFLAG_SET; + m68k->v_flag = (!(src == 0))<<7; + return; + } + + m68k->c_flag = CFLAG_CLEAR; + m68k->n_flag = NFLAG_32(src); + m68k->not_z_flag = src; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(asl, 16, ., .) +{ + UINT32 ea = M68KMAKE_GET_EA_AY_16; + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = MASK_OUT_ABOVE_16(src << 1); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->x_flag = m68k->c_flag = src >> 7; + src &= 0xc000; + m68k->v_flag = (!(src == 0 || src == 0xc000))<<7; +} + + +M68KMAKE_OP(bcc, 8, ., .) +{ + if(M68KMAKE_CC) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(m68k, MASK_OUT_ABOVE_8(m68k->ir)); + return; + } + m68k->remaining_cycles -= m68k->cyc_bcc_notake_b; +} + + +M68KMAKE_OP(bcc, 16, ., .) +{ + if(M68KMAKE_CC) + { + UINT32 offset = OPER_I_16(m68k); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(m68k, offset); + return; + } + REG_PC += 2; + m68k->remaining_cycles -= m68k->cyc_bcc_notake_w; +} + + +M68KMAKE_OP(bcc, 32, ., .) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(M68KMAKE_CC) + { + UINT32 offset = OPER_I_32(m68k); + REG_PC -= 4; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_32(m68k, offset); + return; + } + REG_PC += 4; + return; + } + else + { + if(M68KMAKE_CC) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(m68k, MASK_OUT_ABOVE_8(m68k->ir)); + return; + } + m68k->remaining_cycles -= m68k->cyc_bcc_notake_b; + } +} + + +M68KMAKE_OP(bchg, 32, r, d) +{ + UINT32* r_dst = &DY; + UINT32 mask = 1 << (DX & 0x1f); + + m68k->not_z_flag = *r_dst & mask; + *r_dst ^= mask; +} + + +M68KMAKE_OP(bchg, 8, r, .) +{ + UINT32 ea = M68KMAKE_GET_EA_AY_8; + UINT32 src = m68ki_read_8(m68k, ea); + UINT32 mask = 1 << (DX & 7); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src ^ mask); +} + + +M68KMAKE_OP(bchg, 32, s, d) +{ + UINT32* r_dst = &DY; + UINT32 mask = 1 << (OPER_I_8(m68k) & 0x1f); + + m68k->not_z_flag = *r_dst & mask; + *r_dst ^= mask; +} + + +M68KMAKE_OP(bchg, 8, s, .) +{ + UINT32 mask = 1 << (OPER_I_8(m68k) & 7); + UINT32 ea = M68KMAKE_GET_EA_AY_8; + UINT32 src = m68ki_read_8(m68k, ea); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src ^ mask); +} + + +M68KMAKE_OP(bclr, 32, r, d) +{ + UINT32* r_dst = &DY; + UINT32 mask = 1 << (DX & 0x1f); + + m68k->not_z_flag = *r_dst & mask; + *r_dst &= ~mask; +} + + +M68KMAKE_OP(bclr, 8, r, .) +{ + UINT32 ea = M68KMAKE_GET_EA_AY_8; + UINT32 src = m68ki_read_8(m68k, ea); + UINT32 mask = 1 << (DX & 7); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src & ~mask); +} + + +M68KMAKE_OP(bclr, 32, s, d) +{ + UINT32* r_dst = &DY; + UINT32 mask = 1 << (OPER_I_8(m68k) & 0x1f); + + m68k->not_z_flag = *r_dst & mask; + *r_dst &= ~mask; +} + + +M68KMAKE_OP(bclr, 8, s, .) +{ + UINT32 mask = 1 << (OPER_I_8(m68k) & 7); + UINT32 ea = M68KMAKE_GET_EA_AY_8; + UINT32 src = m68ki_read_8(m68k, ea); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src & ~mask); +} + + +M68KMAKE_OP(bfchg, 32, ., d) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32* data = &DY; + UINT64 mask; + + + if(BIT_B(word2)) + offset = REG_D[offset&7]; + if(BIT_5(word2)) + width = REG_D[width&7]; + + offset &= 31; + width = ((width-1) & 31) + 1; + + mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask = ROR_32(mask, offset); + + m68k->n_flag = NFLAG_32(*data<not_z_flag = *data & mask; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + *data ^= mask; + + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(bfchg, 32, ., .) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + INT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32 mask_base; + UINT32 data_long; + UINT32 mask_long; + UINT32 data_byte = 0; + UINT32 mask_byte = 0; + UINT32 ea = M68KMAKE_GET_EA_AY_8; + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(m68k, ea); + m68k->n_flag = NFLAG_32(data_long << offset); + m68k->not_z_flag = data_long & mask_long; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + m68ki_write_32(m68k, ea, data_long ^ mask_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(m68k, ea+4); + m68k->not_z_flag |= (data_byte & mask_byte); + m68ki_write_8(m68k, ea+4, data_byte ^ mask_byte); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(bfclr, 32, ., d) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32* data = &DY; + UINT64 mask; + + + if(BIT_B(word2)) + offset = REG_D[offset&7]; + if(BIT_5(word2)) + width = REG_D[width&7]; + + + offset &= 31; + width = ((width-1) & 31) + 1; + + + mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask = ROR_32(mask, offset); + + m68k->n_flag = NFLAG_32(*data<not_z_flag = *data & mask; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + *data &= ~mask; + + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(bfclr, 32, ., .) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + INT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32 mask_base; + UINT32 data_long; + UINT32 mask_long; + UINT32 data_byte = 0; + UINT32 mask_byte = 0; + UINT32 ea = M68KMAKE_GET_EA_AY_8; + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(m68k, ea); + m68k->n_flag = NFLAG_32(data_long << offset); + m68k->not_z_flag = data_long & mask_long; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + m68ki_write_32(m68k, ea, data_long & ~mask_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(m68k, ea+4); + m68k->not_z_flag |= (data_byte & mask_byte); + m68ki_write_8(m68k, ea+4, data_byte & ~mask_byte); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(bfexts, 32, ., d) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT64 data = DY; + + + if(BIT_B(word2)) + offset = REG_D[offset&7]; + if(BIT_5(word2)) + width = REG_D[width&7]; + + offset &= 31; + width = ((width-1) & 31) + 1; + + data = ROL_32(data, offset); + m68k->n_flag = NFLAG_32(data); + data = MAKE_INT_32(data) >> (32 - width); + + m68k->not_z_flag = data; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + REG_D[(word2>>12)&7] = data; + + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(bfexts, 32, ., .) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + INT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32 data; + UINT32 ea = M68KMAKE_GET_EA_AY_8; + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(m68k, ea); + + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(m68k, ea+4) << offset) >> 8; + + m68k->n_flag = NFLAG_32(data); + data = MAKE_INT_32(data) >> (32 - width); + + m68k->not_z_flag = data; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + REG_D[(word2 >> 12) & 7] = data; + + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(bfextu, 32, ., d) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT64 data = DY; + + + if(BIT_B(word2)) + offset = REG_D[offset&7]; + if(BIT_5(word2)) + width = REG_D[width&7]; + + offset &= 31; + width = ((width-1) & 31) + 1; + + data = ROL_32(data, offset); + m68k->n_flag = NFLAG_32(data); + data >>= 32 - width; + + m68k->not_z_flag = data; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + REG_D[(word2>>12)&7] = data; + + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(bfextu, 32, ., .) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + INT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32 data; + UINT32 ea = M68KMAKE_GET_EA_AY_8; + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(m68k, ea); + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(m68k, ea+4) << offset) >> 8; + + m68k->n_flag = NFLAG_32(data); + data >>= (32 - width); + + m68k->not_z_flag = data; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + REG_D[(word2 >> 12) & 7] = data; + + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(bfffo, 32, ., d) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT64 data = DY; + UINT32 bit; + + + if(BIT_B(word2)) + offset = REG_D[offset&7]; + if(BIT_5(word2)) + width = REG_D[width&7]; + + offset &= 31; + width = ((width-1) & 31) + 1; + + data = ROL_32(data, offset); + m68k->n_flag = NFLAG_32(data); + data >>= 32 - width; + + m68k->not_z_flag = data; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1) + offset++; + + REG_D[(word2>>12)&7] = offset; + + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(bfffo, 32, ., .) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + INT32 offset = (word2>>6)&31; + INT32 local_offset; + UINT32 width = word2; + UINT32 data; + UINT32 bit; + UINT32 ea = M68KMAKE_GET_EA_AY_8; + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + local_offset = offset % 8; + if(local_offset < 0) + { + local_offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(m68k, ea); + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(m68k, ea+4) << local_offset) >> 8; + + m68k->n_flag = NFLAG_32(data); + data >>= (32 - width); + + m68k->not_z_flag = data; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1) + offset++; + + REG_D[(word2>>12)&7] = offset; + + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(bfins, 32, ., d) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32* data = &DY; + UINT64 mask; + UINT64 insert = REG_D[(word2>>12)&7]; + + + if(BIT_B(word2)) + offset = REG_D[offset&7]; + if(BIT_5(word2)) + width = REG_D[width&7]; + + + offset &= 31; + width = ((width-1) & 31) + 1; + + + mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask = ROR_32(mask, offset); + + insert = MASK_OUT_ABOVE_32(insert << (32 - width)); + m68k->n_flag = NFLAG_32(insert); + m68k->not_z_flag = insert; + insert = ROR_32(insert, offset); + + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + *data &= ~mask; + *data |= insert; + + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(bfins, 32, ., .) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + INT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32 insert_base = REG_D[(word2>>12)&7]; + UINT32 insert_long; + UINT32 insert_byte; + UINT32 mask_base; + UINT32 data_long; + UINT32 mask_long; + UINT32 data_byte = 0; + UINT32 mask_byte = 0; + UINT32 ea = M68KMAKE_GET_EA_AY_8; + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + insert_base = MASK_OUT_ABOVE_32(insert_base << (32 - width)); + m68k->n_flag = NFLAG_32(insert_base); + m68k->not_z_flag = insert_base; + insert_long = insert_base >> offset; + + data_long = m68ki_read_32(m68k, ea); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + m68ki_write_32(m68k, ea, (data_long & ~mask_long) | insert_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + insert_byte = MASK_OUT_ABOVE_8(insert_base); + data_byte = m68ki_read_8(m68k, ea+4); + m68k->not_z_flag |= (data_byte & mask_byte); + m68ki_write_8(m68k, ea+4, (data_byte & ~mask_byte) | insert_byte); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(bfset, 32, ., d) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32* data = &DY; + UINT64 mask; + + + if(BIT_B(word2)) + offset = REG_D[offset&7]; + if(BIT_5(word2)) + width = REG_D[width&7]; + + + offset &= 31; + width = ((width-1) & 31) + 1; + + + mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask = ROR_32(mask, offset); + + m68k->n_flag = NFLAG_32(*data<not_z_flag = *data & mask; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + *data |= mask; + + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(bfset, 32, ., .) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + INT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32 mask_base; + UINT32 data_long; + UINT32 mask_long; + UINT32 data_byte = 0; + UINT32 mask_byte = 0; + UINT32 ea = M68KMAKE_GET_EA_AY_8; + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(m68k, ea); + m68k->n_flag = NFLAG_32(data_long << offset); + m68k->not_z_flag = data_long & mask_long; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + m68ki_write_32(m68k, ea, data_long | mask_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(m68k, ea+4); + m68k->not_z_flag |= (data_byte & mask_byte); + m68ki_write_8(m68k, ea+4, data_byte | mask_byte); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(bftst, 32, ., d) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32* data = &DY; + UINT64 mask; + + + if(BIT_B(word2)) + offset = REG_D[offset&7]; + if(BIT_5(word2)) + width = REG_D[width&7]; + + + offset &= 31; + width = ((width-1) & 31) + 1; + + + mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask = ROR_32(mask, offset); + + m68k->n_flag = NFLAG_32(*data<not_z_flag = *data & mask; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(bftst, 32, ., .) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + INT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32 mask_base; + UINT32 data_long; + UINT32 mask_long; + UINT32 data_byte = 0; + UINT32 mask_byte = 0; + UINT32 ea = M68KMAKE_GET_EA_AY_8; + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(m68k, ea); + m68k->n_flag = ((data_long & (0x80000000 >> offset))<>24; + m68k->not_z_flag = data_long & mask_long; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(m68k, ea+4); + m68k->not_z_flag |= (data_byte & mask_byte); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(bkpt, 0, ., .) +{ + if(CPU_TYPE_IS_010_PLUS(m68k->cpu_type)) + { + if (m68k->bkpt_ack_callback != NULL) + (*m68k->bkpt_ack_callback)(m68k->device, CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type) ? m68k->ir & 7 : 0); + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(bra, 8, ., .) +{ + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(m68k, MASK_OUT_ABOVE_8(m68k->ir)); + if(REG_PC == REG_PPC && m68k->remaining_cycles > 0) + m68k->remaining_cycles = 0; +} + + +M68KMAKE_OP(bra, 16, ., .) +{ + UINT32 offset = OPER_I_16(m68k); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(m68k, offset); + if(REG_PC == REG_PPC && m68k->remaining_cycles > 0) + m68k->remaining_cycles = 0; +} + + +M68KMAKE_OP(bra, 32, ., .) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 offset = OPER_I_32(m68k); + REG_PC -= 4; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_32(m68k, offset); + if(REG_PC == REG_PPC && m68k->remaining_cycles > 0) + m68k->remaining_cycles = 0; + return; + } + else + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(m68k, MASK_OUT_ABOVE_8(m68k->ir)); + if(REG_PC == REG_PPC && m68k->remaining_cycles > 0) + m68k->remaining_cycles = 0; + } +} + + +M68KMAKE_OP(bset, 32, r, d) +{ + UINT32* r_dst = &DY; + UINT32 mask = 1 << (DX & 0x1f); + + m68k->not_z_flag = *r_dst & mask; + *r_dst |= mask; +} + + +M68KMAKE_OP(bset, 8, r, .) +{ + UINT32 ea = M68KMAKE_GET_EA_AY_8; + UINT32 src = m68ki_read_8(m68k, ea); + UINT32 mask = 1 << (DX & 7); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src | mask); +} + + +M68KMAKE_OP(bset, 32, s, d) +{ + UINT32* r_dst = &DY; + UINT32 mask = 1 << (OPER_I_8(m68k) & 0x1f); + + m68k->not_z_flag = *r_dst & mask; + *r_dst |= mask; +} + + +M68KMAKE_OP(bset, 8, s, .) +{ + UINT32 mask = 1 << (OPER_I_8(m68k) & 7); + UINT32 ea = M68KMAKE_GET_EA_AY_8; + UINT32 src = m68ki_read_8(m68k, ea); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src | mask); +} + + +M68KMAKE_OP(bsr, 8, ., .) +{ + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_push_32(m68k, REG_PC); + m68ki_branch_8(m68k, MASK_OUT_ABOVE_8(m68k->ir)); +} + + +M68KMAKE_OP(bsr, 16, ., .) +{ + UINT32 offset = OPER_I_16(m68k); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_push_32(m68k, REG_PC); + REG_PC -= 2; + m68ki_branch_16(m68k, offset); +} + + +M68KMAKE_OP(bsr, 32, ., .) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 offset = OPER_I_32(m68k); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_push_32(m68k, REG_PC); + REG_PC -= 4; + m68ki_branch_32(m68k, offset); + return; + } + else + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_push_32(m68k, REG_PC); + m68ki_branch_8(m68k, MASK_OUT_ABOVE_8(m68k->ir)); + } +} + + +M68KMAKE_OP(btst, 32, r, d) +{ + m68k->not_z_flag = DY & (1 << (DX & 0x1f)); +} + + +M68KMAKE_OP(btst, 8, r, .) +{ + m68k->not_z_flag = M68KMAKE_GET_OPER_AY_8 & (1 << (DX & 7)); +} + + +M68KMAKE_OP(btst, 32, s, d) +{ + m68k->not_z_flag = DY & (1 << (OPER_I_8(m68k) & 0x1f)); +} + + +M68KMAKE_OP(btst, 8, s, .) +{ + UINT32 bit = OPER_I_8(m68k) & 7; + + m68k->not_z_flag = M68KMAKE_GET_OPER_AY_8 & (1 << bit); +} + + +M68KMAKE_OP(callm, 32, ., .) +{ + /* note: watch out for pcrelative modes */ + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + { + UINT32 ea = M68KMAKE_GET_EA_AY_32; + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + REG_PC += 2; +(void)ea; /* just to avoid an 'unused variable' warning */ + logerror("%s at %08x: called unimplemented instruction %04x (callm)\n", + m68k->device->tag, REG_PC - 2, m68k->ir); + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(cas, 8, ., .) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 ea = M68KMAKE_GET_EA_AY_8; + UINT32 dest = m68ki_read_8(m68k, ea); + UINT32* compare = ®_D[word2 & 7]; + UINT32 res = dest - MASK_OUT_ABOVE_8(*compare); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->v_flag = VFLAG_SUB_8(*compare, dest, res); + m68k->c_flag = CFLAG_8(res); + + if(COND_NE(m68k)) + *compare = MASK_OUT_BELOW_8(*compare) | dest; + else + { + m68k->remaining_cycles -= 3; + m68ki_write_8(m68k, ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7])); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(cas, 16, ., .) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 ea = M68KMAKE_GET_EA_AY_16; + UINT32 dest = m68ki_read_16(m68k, ea); + UINT32* compare = ®_D[word2 & 7]; + UINT32 res = dest - MASK_OUT_ABOVE_16(*compare); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->v_flag = VFLAG_SUB_16(*compare, dest, res); + m68k->c_flag = CFLAG_16(res); + + if(COND_NE(m68k)) + *compare = MASK_OUT_BELOW_16(*compare) | dest; + else + { + m68k->remaining_cycles -= 3; + m68ki_write_16(m68k, ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7])); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(cas, 32, ., .) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 ea = M68KMAKE_GET_EA_AY_32; + UINT32 dest = m68ki_read_32(m68k, ea); + UINT32* compare = ®_D[word2 & 7]; + UINT32 res = dest - *compare; + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(*compare, dest, res); + m68k->c_flag = CFLAG_SUB_32(*compare, dest, res); + + if(COND_NE(m68k)) + *compare = dest; + else + { + m68k->remaining_cycles -= 3; + m68ki_write_32(m68k, ea, REG_D[(word2 >> 6) & 7]); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(cas2, 16, ., .) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_32(m68k); + UINT32* compare1 = ®_D[(word2 >> 16) & 7]; + UINT32 ea1 = REG_DA[(word2 >> 28) & 15]; + UINT32 dest1 = m68ki_read_16(m68k, ea1); + UINT32 res1 = dest1 - MASK_OUT_ABOVE_16(*compare1); + UINT32* compare2 = ®_D[word2 & 7]; + UINT32 ea2 = REG_DA[(word2 >> 12) & 15]; + UINT32 dest2 = m68ki_read_16(m68k, ea2); + UINT32 res2; + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68k->n_flag = NFLAG_16(res1); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res1); + m68k->v_flag = VFLAG_SUB_16(*compare1, dest1, res1); + m68k->c_flag = CFLAG_16(res1); + + if(COND_EQ(m68k)) + { + res2 = dest2 - MASK_OUT_ABOVE_16(*compare2); + + m68k->n_flag = NFLAG_16(res2); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res2); + m68k->v_flag = VFLAG_SUB_16(*compare2, dest2, res2); + m68k->c_flag = CFLAG_16(res2); + + if(COND_EQ(m68k)) + { + m68k->remaining_cycles -= 3; + m68ki_write_16(m68k, ea1, REG_D[(word2 >> 22) & 7]); + m68ki_write_16(m68k, ea2, REG_D[(word2 >> 6) & 7]); + return; + } + } + *compare1 = BIT_1F(word2) ? MAKE_INT_16(dest1) : MASK_OUT_BELOW_16(*compare1) | dest1; + *compare2 = BIT_F(word2) ? MAKE_INT_16(dest2) : MASK_OUT_BELOW_16(*compare2) | dest2; + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(cas2, 32, ., .) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_32(m68k); + UINT32* compare1 = ®_D[(word2 >> 16) & 7]; + UINT32 ea1 = REG_DA[(word2 >> 28) & 15]; + UINT32 dest1 = m68ki_read_32(m68k, ea1); + UINT32 res1 = dest1 - *compare1; + UINT32* compare2 = ®_D[word2 & 7]; + UINT32 ea2 = REG_DA[(word2 >> 12) & 15]; + UINT32 dest2 = m68ki_read_32(m68k, ea2); + UINT32 res2; + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68k->n_flag = NFLAG_32(res1); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res1); + m68k->v_flag = VFLAG_SUB_32(*compare1, dest1, res1); + m68k->c_flag = CFLAG_SUB_32(*compare1, dest1, res1); + + if(COND_EQ(m68k)) + { + res2 = dest2 - *compare2; + + m68k->n_flag = NFLAG_32(res2); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res2); + m68k->v_flag = VFLAG_SUB_32(*compare2, dest2, res2); + m68k->c_flag = CFLAG_SUB_32(*compare2, dest2, res2); + + if(COND_EQ(m68k)) + { + m68k->remaining_cycles -= 3; + m68ki_write_32(m68k, ea1, REG_D[(word2 >> 22) & 7]); + m68ki_write_32(m68k, ea2, REG_D[(word2 >> 6) & 7]); + return; + } + } + *compare1 = dest1; + *compare2 = dest2; + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(chk, 16, ., d) +{ + INT32 src = MAKE_INT_16(DX); + INT32 bound = MAKE_INT_16(DY); + + m68k->not_z_flag = ZFLAG_16(src); /* Undocumented */ + m68k->v_flag = VFLAG_CLEAR; /* Undocumented */ + m68k->c_flag = CFLAG_CLEAR; /* Undocumented */ + + if(src >= 0 && src <= bound) + { + return; + } + m68k->n_flag = (src < 0)<<7; + m68ki_exception_trap(m68k, EXCEPTION_CHK); +} + + +M68KMAKE_OP(chk, 16, ., .) +{ + INT32 src = MAKE_INT_16(DX); + INT32 bound = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16); + + m68k->not_z_flag = ZFLAG_16(src); /* Undocumented */ + m68k->v_flag = VFLAG_CLEAR; /* Undocumented */ + m68k->c_flag = CFLAG_CLEAR; /* Undocumented */ + + if(src >= 0 && src <= bound) + { + return; + } + m68k->n_flag = (src < 0)<<7; + m68ki_exception_trap(m68k, EXCEPTION_CHK); +} + + +M68KMAKE_OP(chk, 32, ., d) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + INT32 src = MAKE_INT_32(DX); + INT32 bound = MAKE_INT_32(DY); + + m68k->not_z_flag = ZFLAG_32(src); /* Undocumented */ + m68k->v_flag = VFLAG_CLEAR; /* Undocumented */ + m68k->c_flag = CFLAG_CLEAR; /* Undocumented */ + + if(src >= 0 && src <= bound) + { + return; + } + m68k->n_flag = (src < 0)<<7; + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(chk, 32, ., .) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + INT32 src = MAKE_INT_32(DX); + INT32 bound = MAKE_INT_32(M68KMAKE_GET_OPER_AY_32); + + m68k->not_z_flag = ZFLAG_32(src); /* Undocumented */ + m68k->v_flag = VFLAG_CLEAR; /* Undocumented */ + m68k->c_flag = CFLAG_CLEAR; /* Undocumented */ + + if(src >= 0 && src <= bound) + { + return; + } + m68k->n_flag = (src < 0)<<7; + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(chk2cmp2, 8, ., pcdi) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 compare = REG_DA[(word2 >> 12) & 15]&0xff; + UINT32 ea = EA_PCDI_8(m68k); + UINT32 lower_bound = m68ki_read_pcrel_8(m68k, ea); + UINT32 upper_bound = m68ki_read_pcrel_8(m68k, ea + 1); + + if(!BIT_F(word2)) + m68k->c_flag = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound); + else + m68k->c_flag = compare - lower_bound; + m68k->not_z_flag = !((upper_bound==compare) | (lower_bound==compare)); + if(COND_CS(m68k)) + { + if(BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + + m68k->c_flag = upper_bound - compare; + if(COND_CS(m68k) && BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(chk2cmp2, 8, ., pcix) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 compare = REG_DA[(word2 >> 12) & 15]&0xff; + UINT32 ea = EA_PCIX_8(m68k); + UINT32 lower_bound = m68ki_read_pcrel_8(m68k, ea); + UINT32 upper_bound = m68ki_read_pcrel_8(m68k, ea + 1); + + if(!BIT_F(word2)) + m68k->c_flag = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound); + else + m68k->c_flag = compare - lower_bound; + m68k->not_z_flag = !((upper_bound==compare) | (lower_bound==compare)); + if(COND_CS(m68k)) + { + if(BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + + m68k->c_flag = upper_bound - compare; + if(COND_CS(m68k) && BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(chk2cmp2, 8, ., .) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 compare = REG_DA[(word2 >> 12) & 15]&0xff; + UINT32 ea = M68KMAKE_GET_EA_AY_8; + UINT32 lower_bound = m68ki_read_8(m68k, ea); + UINT32 upper_bound = m68ki_read_8(m68k, ea + 1); + + if(!BIT_F(word2)) + m68k->c_flag = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound); + else + m68k->c_flag = compare - lower_bound; + m68k->not_z_flag = !((upper_bound==compare) | (lower_bound==compare)); + if(COND_CS(m68k)) + { + if(BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + + m68k->c_flag = upper_bound - compare; + if(COND_CS(m68k) && BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(chk2cmp2, 16, ., pcdi) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 compare = REG_DA[(word2 >> 12) & 15]&0xffff; + UINT32 ea = EA_PCDI_16(m68k); + UINT32 lower_bound = m68ki_read_pcrel_16(m68k, ea); + UINT32 upper_bound = m68ki_read_pcrel_16(m68k, ea + 2); + + if(!BIT_F(word2)) + m68k->c_flag = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound); + else + m68k->c_flag = compare - lower_bound; + m68k->not_z_flag = !((upper_bound==compare) | (lower_bound==compare)); + m68k->c_flag = CFLAG_16(m68k->c_flag); + if(COND_CS(m68k)) + { + if(BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + + if(!BIT_F(word2)) + m68k->c_flag = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare); + else + m68k->c_flag = upper_bound - compare; + m68k->c_flag = CFLAG_16(m68k->c_flag); + if(COND_CS(m68k) && BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(chk2cmp2, 16, ., pcix) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 compare = REG_DA[(word2 >> 12) & 15]&0xffff; + UINT32 ea = EA_PCIX_16(m68k); + UINT32 lower_bound = m68ki_read_pcrel_16(m68k, ea); + UINT32 upper_bound = m68ki_read_pcrel_16(m68k, ea + 2); + + if(!BIT_F(word2)) + m68k->c_flag = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound); + else + m68k->c_flag = compare - lower_bound; + m68k->not_z_flag = !((upper_bound==compare) | (lower_bound==compare)); + m68k->c_flag = CFLAG_16(m68k->c_flag); + if(COND_CS(m68k)) + { + if(BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + + if(!BIT_F(word2)) + m68k->c_flag = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare); + else + m68k->c_flag = upper_bound - compare; + m68k->c_flag = CFLAG_16(m68k->c_flag); + if(COND_CS(m68k) && BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(chk2cmp2, 16, ., .) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 compare = REG_DA[(word2 >> 12) & 15]&0xffff; + UINT32 ea = M68KMAKE_GET_EA_AY_16; + UINT32 lower_bound = m68ki_read_16(m68k, ea); + UINT32 upper_bound = m68ki_read_16(m68k, ea + 2); + + if(!BIT_F(word2)) + m68k->c_flag = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound); + else + m68k->c_flag = compare - lower_bound; + + m68k->not_z_flag = !((upper_bound==compare) | (lower_bound==compare)); + m68k->c_flag = CFLAG_16(m68k->c_flag); + if(COND_CS(m68k)) + { + if(BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + if(!BIT_F(word2)) + m68k->c_flag = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare); + else + m68k->c_flag = upper_bound - compare; + + m68k->c_flag = CFLAG_16(m68k->c_flag); + if(COND_CS(m68k) && BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(chk2cmp2, 32, ., pcdi) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 compare = REG_DA[(word2 >> 12) & 15]; + UINT32 ea = EA_PCDI_32(m68k); + UINT32 lower_bound = m68ki_read_pcrel_32(m68k, ea); + UINT32 upper_bound = m68ki_read_pcrel_32(m68k, ea + 4); + + m68k->c_flag = compare - lower_bound; + m68k->not_z_flag = !((upper_bound==compare) | (lower_bound==compare)); + m68k->c_flag = CFLAG_SUB_32(lower_bound, compare, m68k->c_flag); + if(COND_CS(m68k)) + { + if(BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + + m68k->c_flag = upper_bound - compare; + m68k->c_flag = CFLAG_SUB_32(compare, upper_bound, m68k->c_flag); + if(COND_CS(m68k) && BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(chk2cmp2, 32, ., pcix) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 compare = REG_DA[(word2 >> 12) & 15]; + UINT32 ea = EA_PCIX_32(m68k); + UINT32 lower_bound = m68ki_read_pcrel_32(m68k, ea); + UINT32 upper_bound = m68ki_read_pcrel_32(m68k, ea + 4); + + m68k->c_flag = compare - lower_bound; + m68k->not_z_flag = !((upper_bound==compare) | (lower_bound==compare)); + m68k->c_flag = CFLAG_SUB_32(lower_bound, compare, m68k->c_flag); + if(COND_CS(m68k)) + { + if(BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + + m68k->c_flag = upper_bound - compare; + m68k->c_flag = CFLAG_SUB_32(compare, upper_bound, m68k->c_flag); + if(COND_CS(m68k) && BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(chk2cmp2, 32, ., .) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 compare = REG_DA[(word2 >> 12) & 15]; + UINT32 ea = M68KMAKE_GET_EA_AY_32; + UINT32 lower_bound = m68ki_read_32(m68k, ea); + UINT32 upper_bound = m68ki_read_32(m68k, ea + 4); + + m68k->c_flag = compare - lower_bound; + m68k->not_z_flag = !((upper_bound==compare) | (lower_bound==compare)); + m68k->c_flag = CFLAG_SUB_32(lower_bound, compare, m68k->c_flag); + if(COND_CS(m68k)) + { + if(BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + + m68k->c_flag = upper_bound - compare; + m68k->c_flag = CFLAG_SUB_32(compare, upper_bound, m68k->c_flag); + if(COND_CS(m68k) && BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(clr, 8, ., d) +{ + DY &= 0xffffff00; + + m68k->n_flag = NFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + m68k->not_z_flag = ZFLAG_SET; +} + + +M68KMAKE_OP(clr, 8, ., .) +{ + m68ki_write_8(m68k, M68KMAKE_GET_EA_AY_8, 0); + + m68k->n_flag = NFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + m68k->not_z_flag = ZFLAG_SET; +} + + +M68KMAKE_OP(clr, 16, ., d) +{ + DY &= 0xffff0000; + + m68k->n_flag = NFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + m68k->not_z_flag = ZFLAG_SET; +} + + +M68KMAKE_OP(clr, 16, ., .) +{ + m68ki_write_16(m68k, M68KMAKE_GET_EA_AY_16, 0); + + m68k->n_flag = NFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + m68k->not_z_flag = ZFLAG_SET; +} + + +M68KMAKE_OP(clr, 32, ., d) +{ + DY = 0; + + m68k->n_flag = NFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + m68k->not_z_flag = ZFLAG_SET; +} + + +M68KMAKE_OP(clr, 32, ., .) +{ + m68ki_write_32(m68k, M68KMAKE_GET_EA_AY_32, 0); + + m68k->n_flag = NFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + m68k->not_z_flag = ZFLAG_SET; +} + + +M68KMAKE_OP(cmp, 8, ., d) +{ + UINT32 src = MASK_OUT_ABOVE_8(DY); + UINT32 dst = MASK_OUT_ABOVE_8(DX); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + m68k->c_flag = CFLAG_8(res); +} + + +M68KMAKE_OP(cmp, 8, ., .) +{ + UINT32 src = M68KMAKE_GET_OPER_AY_8; + UINT32 dst = MASK_OUT_ABOVE_8(DX); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + m68k->c_flag = CFLAG_8(res); +} + + +M68KMAKE_OP(cmp, 16, ., d) +{ + UINT32 src = MASK_OUT_ABOVE_16(DY); + UINT32 dst = MASK_OUT_ABOVE_16(DX); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + m68k->c_flag = CFLAG_16(res); +} + + +M68KMAKE_OP(cmp, 16, ., a) +{ + UINT32 src = MASK_OUT_ABOVE_16(AY); + UINT32 dst = MASK_OUT_ABOVE_16(DX); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + m68k->c_flag = CFLAG_16(res); +} + + +M68KMAKE_OP(cmp, 16, ., .) +{ + UINT32 src = M68KMAKE_GET_OPER_AY_16; + UINT32 dst = MASK_OUT_ABOVE_16(DX); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + m68k->c_flag = CFLAG_16(res); +} + + +M68KMAKE_OP(cmp, 32, ., d) +{ + UINT32 src = DY; + UINT32 dst = DX; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); +} + + +M68KMAKE_OP(cmp, 32, ., a) +{ + UINT32 src = AY; + UINT32 dst = DX; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); +} + + +M68KMAKE_OP(cmp, 32, ., .) +{ + UINT32 src = M68KMAKE_GET_OPER_AY_32; + UINT32 dst = DX; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); +} + + +M68KMAKE_OP(cmpa, 16, ., d) +{ + UINT32 src = MAKE_INT_16(DY); + UINT32 dst = AX; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); +} + + +M68KMAKE_OP(cmpa, 16, ., a) +{ + UINT32 src = MAKE_INT_16(AY); + UINT32 dst = AX; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); +} + + +M68KMAKE_OP(cmpa, 16, ., .) +{ + UINT32 src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16); + UINT32 dst = AX; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); +} + + +M68KMAKE_OP(cmpa, 32, ., d) +{ + UINT32 src = DY; + UINT32 dst = AX; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); +} + + +M68KMAKE_OP(cmpa, 32, ., a) +{ + UINT32 src = AY; + UINT32 dst = AX; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); +} + + +M68KMAKE_OP(cmpa, 32, ., .) +{ + UINT32 src = M68KMAKE_GET_OPER_AY_32; + UINT32 dst = AX; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); +} + + +M68KMAKE_OP(cmpi, 8, ., d) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 dst = MASK_OUT_ABOVE_8(DY); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + m68k->c_flag = CFLAG_8(res); +} + + +M68KMAKE_OP(cmpi, 8, ., .) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 dst = M68KMAKE_GET_OPER_AY_8; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + m68k->c_flag = CFLAG_8(res); +} + + +M68KMAKE_OP(cmpi, 8, ., pcdi) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 src = OPER_I_8(m68k); + UINT32 dst = OPER_PCDI_8(m68k); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + m68k->c_flag = CFLAG_8(res); + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(cmpi, 8, ., pcix) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 src = OPER_I_8(m68k); + UINT32 dst = OPER_PCIX_8(m68k); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + m68k->c_flag = CFLAG_8(res); + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(cmpi, 16, ., d) +{ + UINT32 src = OPER_I_16(m68k); + UINT32 dst = MASK_OUT_ABOVE_16(DY); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + m68k->c_flag = CFLAG_16(res); +} + + +M68KMAKE_OP(cmpi, 16, ., .) +{ + UINT32 src = OPER_I_16(m68k); + UINT32 dst = M68KMAKE_GET_OPER_AY_16; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + m68k->c_flag = CFLAG_16(res); +} + + +M68KMAKE_OP(cmpi, 16, ., pcdi) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 src = OPER_I_16(m68k); + UINT32 dst = OPER_PCDI_16(m68k); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + m68k->c_flag = CFLAG_16(res); + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(cmpi, 16, ., pcix) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 src = OPER_I_16(m68k); + UINT32 dst = OPER_PCIX_16(m68k); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + m68k->c_flag = CFLAG_16(res); + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(cmpi, 32, ., d) +{ + UINT32 src = OPER_I_32(m68k); + UINT32 dst = DY; + UINT32 res = dst - src; + + if (m68k->cmpild_instr_callback != NULL) + (*m68k->cmpild_instr_callback)(m68k->device, src, m68k->ir & 7); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); +} + + +M68KMAKE_OP(cmpi, 32, ., .) +{ + UINT32 src = OPER_I_32(m68k); + UINT32 dst = M68KMAKE_GET_OPER_AY_32; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); +} + + +M68KMAKE_OP(cmpi, 32, ., pcdi) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 src = OPER_I_32(m68k); + UINT32 dst = OPER_PCDI_32(m68k); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(cmpi, 32, ., pcix) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 src = OPER_I_32(m68k); + UINT32 dst = OPER_PCIX_32(m68k); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(cmpm, 8, ., ax7) +{ + UINT32 src = OPER_AY_PI_8(m68k); + UINT32 dst = OPER_A7_PI_8(m68k); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + m68k->c_flag = CFLAG_8(res); +} + + +M68KMAKE_OP(cmpm, 8, ., ay7) +{ + UINT32 src = OPER_A7_PI_8(m68k); + UINT32 dst = OPER_AX_PI_8(m68k); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + m68k->c_flag = CFLAG_8(res); +} + + +M68KMAKE_OP(cmpm, 8, ., axy7) +{ + UINT32 src = OPER_A7_PI_8(m68k); + UINT32 dst = OPER_A7_PI_8(m68k); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + m68k->c_flag = CFLAG_8(res); +} + + +M68KMAKE_OP(cmpm, 8, ., .) +{ + UINT32 src = OPER_AY_PI_8(m68k); + UINT32 dst = OPER_AX_PI_8(m68k); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + m68k->c_flag = CFLAG_8(res); +} + + +M68KMAKE_OP(cmpm, 16, ., .) +{ + UINT32 src = OPER_AY_PI_16(m68k); + UINT32 dst = OPER_AX_PI_16(m68k); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + m68k->c_flag = CFLAG_16(res); +} + + +M68KMAKE_OP(cmpm, 32, ., .) +{ + UINT32 src = OPER_AY_PI_32(m68k); + UINT32 dst = OPER_AX_PI_32(m68k); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); +} + + +M68KMAKE_OP(cpbcc, 32, ., .) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + logerror( "%s at %08x: called unimplemented instruction %04x (cpbcc)\n", + m68k->device->tag, REG_PC - 2, m68k->ir); + return; + } + m68ki_exception_1111(m68k); +} + + +M68KMAKE_OP(cpdbcc, 32, ., .) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + logerror("%s at %08x: called unimplemented instruction %04x (cpdbcc)\n", + m68k->device->tag, REG_PC - 2, m68k->ir); + return; + } + m68ki_exception_1111(m68k); +} + + +M68KMAKE_OP(cpgen, 32, ., .) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + logerror("%s at %08x: called unimplemented instruction %04x (cpgen)\n", + m68k->device->tag, REG_PC - 2, m68k->ir); + return; + } + m68ki_exception_1111(m68k); +} + + +M68KMAKE_OP(cpscc, 32, ., .) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + logerror("%s at %08x: called unimplemented instruction %04x (cpscc)\n", + m68k->device->tag, REG_PC - 2, m68k->ir); + return; + } + m68ki_exception_1111(m68k); +} + + +M68KMAKE_OP(cptrapcc, 32, ., .) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + logerror("%s at %08x: called unimplemented instruction %04x (cptrapcc)\n", + m68k->device->tag, REG_PC - 2, m68k->ir); + return; + } + m68ki_exception_1111(m68k); +} + + +M68KMAKE_OP(dbt, 16, ., .) +{ + REG_PC += 2; +} + + +M68KMAKE_OP(dbf, 16, ., .) +{ + UINT32* r_dst = &DY; + UINT32 res = MASK_OUT_ABOVE_16(*r_dst - 1); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + if(res != 0xffff) + { + UINT32 offset = OPER_I_16(m68k); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(m68k, offset); + m68k->remaining_cycles -= m68k->cyc_dbcc_f_noexp; + return; + } + REG_PC += 2; + m68k->remaining_cycles -= m68k->cyc_dbcc_f_exp; +} + + +M68KMAKE_OP(dbcc, 16, ., .) +{ + if(M68KMAKE_NOT_CC) + { + UINT32* r_dst = &DY; + UINT32 res = MASK_OUT_ABOVE_16(*r_dst - 1); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + if(res != 0xffff) + { + UINT32 offset = OPER_I_16(m68k); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(m68k, offset); + m68k->remaining_cycles -= m68k->cyc_dbcc_f_noexp; + return; + } + REG_PC += 2; + m68k->remaining_cycles -= m68k->cyc_dbcc_f_exp; + return; + } + REG_PC += 2; +} + + +M68KMAKE_OP(divs, 16, ., d) +{ + UINT32* r_dst = &DX; + INT32 src = MAKE_INT_16(DY); + INT32 quotient; + INT32 remainder; + + if(src != 0) + { + if((UINT32)*r_dst == 0x80000000 && src == -1) + { + m68k->not_z_flag = 0; + m68k->n_flag = NFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + *r_dst = 0; + return; + } + + quotient = MAKE_INT_32(*r_dst) / src; + remainder = MAKE_INT_32(*r_dst) % src; + + if(quotient == MAKE_INT_16(quotient)) + { + m68k->not_z_flag = quotient; + m68k->n_flag = NFLAG_16(quotient); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + m68k->v_flag = VFLAG_SET; + return; + } + m68ki_exception_trap(m68k, EXCEPTION_ZERO_DIVIDE); +} + + +M68KMAKE_OP(divs, 16, ., .) +{ + UINT32* r_dst = &DX; + INT32 src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16); + INT32 quotient; + INT32 remainder; + + if(src != 0) + { + if((UINT32)*r_dst == 0x80000000 && src == -1) + { + m68k->not_z_flag = 0; + m68k->n_flag = NFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + *r_dst = 0; + return; + } + + quotient = MAKE_INT_32(*r_dst) / src; + remainder = MAKE_INT_32(*r_dst) % src; + + if(quotient == MAKE_INT_16(quotient)) + { + m68k->not_z_flag = quotient; + m68k->n_flag = NFLAG_16(quotient); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + m68k->v_flag = VFLAG_SET; + return; + } + m68ki_exception_trap(m68k, EXCEPTION_ZERO_DIVIDE); +} + + +M68KMAKE_OP(divu, 16, ., d) +{ + UINT32* r_dst = &DX; + UINT32 src = MASK_OUT_ABOVE_16(DY); + + if(src != 0) + { + UINT32 quotient = *r_dst / src; + UINT32 remainder = *r_dst % src; + + if(quotient < 0x10000) + { + m68k->not_z_flag = quotient; + m68k->n_flag = NFLAG_16(quotient); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + m68k->v_flag = VFLAG_SET; + return; + } + m68ki_exception_trap(m68k, EXCEPTION_ZERO_DIVIDE); +} + + +M68KMAKE_OP(divu, 16, ., .) +{ + UINT32* r_dst = &DX; + UINT32 src = M68KMAKE_GET_OPER_AY_16; + + if(src != 0) + { + UINT32 quotient = *r_dst / src; + UINT32 remainder = *r_dst % src; + + if(quotient < 0x10000) + { + m68k->not_z_flag = quotient; + m68k->n_flag = NFLAG_16(quotient); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + m68k->v_flag = VFLAG_SET; + return; + } + m68ki_exception_trap(m68k, EXCEPTION_ZERO_DIVIDE); +} + + +M68KMAKE_OP(divl, 32, ., d) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT64 divisor = DY; + UINT64 dividend = 0; + UINT64 quotient = 0; + UINT64 remainder = 0; + + if(divisor != 0) + { + if(BIT_A(word2)) /* 64 bit */ + { + dividend = REG_D[word2 & 7]; + dividend <<= 32; + dividend |= REG_D[(word2 >> 12) & 7]; + + if(BIT_B(word2)) /* signed */ + { + quotient = (UINT64)((INT64)dividend / (INT64)((INT32)divisor)); + remainder = (UINT64)((INT64)dividend % (INT64)((INT32)divisor)); + if((INT64)quotient != (INT64)((INT32)quotient)) + { + m68k->v_flag = VFLAG_SET; + return; + } + } + else /* unsigned */ + { + quotient = dividend / divisor; + if(quotient > 0xffffffff) + { + m68k->v_flag = VFLAG_SET; + return; + } + remainder = dividend % divisor; + } + } + else /* 32 bit */ + { + dividend = REG_D[(word2 >> 12) & 7]; + if(BIT_B(word2)) /* signed */ + { + quotient = (UINT64)((INT64)((INT32)dividend) / (INT64)((INT32)divisor)); + remainder = (UINT64)((INT64)((INT32)dividend) % (INT64)((INT32)divisor)); + } + else /* unsigned */ + { + quotient = dividend / divisor; + remainder = dividend % divisor; + } + } + + REG_D[word2 & 7] = remainder; + REG_D[(word2 >> 12) & 7] = quotient; + + m68k->n_flag = NFLAG_32(quotient); + m68k->not_z_flag = quotient; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + return; + } + m68ki_exception_trap(m68k, EXCEPTION_ZERO_DIVIDE); + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(divl, 32, ., .) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT64 divisor = M68KMAKE_GET_OPER_AY_32; + UINT64 dividend = 0; + UINT64 quotient = 0; + UINT64 remainder = 0; + + if(divisor != 0) + { + if(BIT_A(word2)) /* 64 bit */ + { + dividend = REG_D[word2 & 7]; + dividend <<= 32; + dividend |= REG_D[(word2 >> 12) & 7]; + + if(BIT_B(word2)) /* signed */ + { + quotient = (UINT64)((INT64)dividend / (INT64)((INT32)divisor)); + remainder = (UINT64)((INT64)dividend % (INT64)((INT32)divisor)); + if((INT64)quotient != (INT64)((INT32)quotient)) + { + m68k->v_flag = VFLAG_SET; + return; + } + } + else /* unsigned */ + { + quotient = dividend / divisor; + if(quotient > 0xffffffff) + { + m68k->v_flag = VFLAG_SET; + return; + } + remainder = dividend % divisor; + } + } + else /* 32 bit */ + { + dividend = REG_D[(word2 >> 12) & 7]; + if(BIT_B(word2)) /* signed */ + { + quotient = (UINT64)((INT64)((INT32)dividend) / (INT64)((INT32)divisor)); + remainder = (UINT64)((INT64)((INT32)dividend) % (INT64)((INT32)divisor)); + } + else /* unsigned */ + { + quotient = dividend / divisor; + remainder = dividend % divisor; + } + } + + REG_D[word2 & 7] = remainder; + REG_D[(word2 >> 12) & 7] = quotient; + + m68k->n_flag = NFLAG_32(quotient); + m68k->not_z_flag = quotient; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + return; + } + m68ki_exception_trap(m68k, EXCEPTION_ZERO_DIVIDE); + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(eor, 8, ., d) +{ + UINT32 res = MASK_OUT_ABOVE_8(DY ^= MASK_OUT_ABOVE_8(DX)); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(eor, 8, ., .) +{ + UINT32 ea = M68KMAKE_GET_EA_AY_8; + UINT32 res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(m68k, ea)); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(eor, 16, ., d) +{ + UINT32 res = MASK_OUT_ABOVE_16(DY ^= MASK_OUT_ABOVE_16(DX)); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(eor, 16, ., .) +{ + UINT32 ea = M68KMAKE_GET_EA_AY_16; + UINT32 res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(m68k, ea)); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(eor, 32, ., d) +{ + UINT32 res = DY ^= DX; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(eor, 32, ., .) +{ + UINT32 ea = M68KMAKE_GET_EA_AY_32; + UINT32 res = DX ^ m68ki_read_32(m68k, ea); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(eori, 8, ., d) +{ + UINT32 res = MASK_OUT_ABOVE_8(DY ^= OPER_I_8(m68k)); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(eori, 8, ., .) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 ea = M68KMAKE_GET_EA_AY_8; + UINT32 res = src ^ m68ki_read_8(m68k, ea); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(eori, 16, ., d) +{ + UINT32 res = MASK_OUT_ABOVE_16(DY ^= OPER_I_16(m68k)); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(eori, 16, ., .) +{ + UINT32 src = OPER_I_16(m68k); + UINT32 ea = M68KMAKE_GET_EA_AY_16; + UINT32 res = src ^ m68ki_read_16(m68k, ea); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(eori, 32, ., d) +{ + UINT32 res = DY ^= OPER_I_32(m68k); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(eori, 32, ., .) +{ + UINT32 src = OPER_I_32(m68k); + UINT32 ea = M68KMAKE_GET_EA_AY_32; + UINT32 res = src ^ m68ki_read_32(m68k, ea); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(eori, 16, toc, .) +{ + m68ki_set_ccr(m68k, m68ki_get_ccr(m68k) ^ OPER_I_16(m68k)); +} + + +M68KMAKE_OP(eori, 16, tos, .) +{ + if(m68k->s_flag) + { + UINT32 src = OPER_I_16(m68k); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_set_sr(m68k, m68ki_get_sr(m68k) ^ src); + return; + } + m68ki_exception_privilege_violation(m68k); +} + + +M68KMAKE_OP(exg, 32, dd, .) +{ + UINT32* reg_a = &DX; + UINT32* reg_b = &DY; + UINT32 tmp = *reg_a; + *reg_a = *reg_b; + *reg_b = tmp; +} + + +M68KMAKE_OP(exg, 32, aa, .) +{ + UINT32* reg_a = &AX; + UINT32* reg_b = &AY; + UINT32 tmp = *reg_a; + *reg_a = *reg_b; + *reg_b = tmp; +} + + +M68KMAKE_OP(exg, 32, da, .) +{ + UINT32* reg_a = &DX; + UINT32* reg_b = &AY; + UINT32 tmp = *reg_a; + *reg_a = *reg_b; + *reg_b = tmp; +} + + +M68KMAKE_OP(ext, 16, ., .) +{ + UINT32* r_dst = &DY; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xff00 : 0); + + m68k->n_flag = NFLAG_16(*r_dst); + m68k->not_z_flag = MASK_OUT_ABOVE_16(*r_dst); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(ext, 32, ., .) +{ + UINT32* r_dst = &DY; + + *r_dst = MASK_OUT_ABOVE_16(*r_dst) | (GET_MSB_16(*r_dst) ? 0xffff0000 : 0); + + m68k->n_flag = NFLAG_32(*r_dst); + m68k->not_z_flag = *r_dst; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(extb, 32, ., .) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32* r_dst = &DY; + + *r_dst = MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xffffff00 : 0); + + m68k->n_flag = NFLAG_32(*r_dst); + m68k->not_z_flag = *r_dst; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(illegal, 0, ., .) +{ + m68ki_exception_illegal(m68k); +} + +M68KMAKE_OP(jmp, 32, ., .) +{ + m68ki_jump(m68k, M68KMAKE_GET_EA_AY_32); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(REG_PC == REG_PPC && m68k->remaining_cycles > 0) + m68k->remaining_cycles = 0; +} + + +M68KMAKE_OP(jsr, 32, ., .) +{ + UINT32 ea = M68KMAKE_GET_EA_AY_32; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_push_32(m68k, REG_PC); + m68ki_jump(m68k, ea); +} + + +M68KMAKE_OP(lea, 32, ., .) +{ + AX = M68KMAKE_GET_EA_AY_32; +} + + +M68KMAKE_OP(link, 16, ., a7) +{ + REG_A[7] -= 4; + m68ki_write_32(m68k, REG_A[7], REG_A[7]); + REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16(m68k))); +} + + +M68KMAKE_OP(link, 16, ., .) +{ + UINT32* r_dst = &AY; + + m68ki_push_32(m68k, *r_dst); + *r_dst = REG_A[7]; + REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16(m68k))); +} + + +M68KMAKE_OP(link, 32, ., a7) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + REG_A[7] -= 4; + m68ki_write_32(m68k, REG_A[7], REG_A[7]); + REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32(m68k)); + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(link, 32, ., .) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32* r_dst = &AY; + + m68ki_push_32(m68k, *r_dst); + *r_dst = REG_A[7]; + REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32(m68k)); + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(lsr, 8, s, .) +{ + UINT32* r_dst = &DY; + UINT32 shift = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 src = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = src >> shift; + + if(shift != 0) + m68k->remaining_cycles -= shift<cyc_shift; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + m68k->n_flag = NFLAG_CLEAR; + m68k->not_z_flag = res; + m68k->x_flag = m68k->c_flag = src << (9-shift); + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(lsr, 16, s, .) +{ + UINT32* r_dst = &DY; + UINT32 shift = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 src = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = src >> shift; + + if(shift != 0) + m68k->remaining_cycles -= shift<cyc_shift; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + m68k->n_flag = NFLAG_CLEAR; + m68k->not_z_flag = res; + m68k->x_flag = m68k->c_flag = src << (9-shift); + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(lsr, 32, s, .) +{ + UINT32* r_dst = &DY; + UINT32 shift = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 src = *r_dst; + UINT32 res = src >> shift; + + if(shift != 0) + m68k->remaining_cycles -= shift<cyc_shift; + + *r_dst = res; + + m68k->n_flag = NFLAG_CLEAR; + m68k->not_z_flag = res; + m68k->x_flag = m68k->c_flag = src << (9-shift); + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(lsr, 8, r, .) +{ + UINT32* r_dst = &DY; + UINT32 shift = DX & 0x3f; + UINT32 src = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = src >> shift; + + if(shift != 0) + { + m68k->remaining_cycles -= shift<cyc_shift; + + if(shift <= 8) + { + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + m68k->x_flag = m68k->c_flag = src << (9-shift); + m68k->n_flag = NFLAG_CLEAR; + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + *r_dst &= 0xffffff00; + m68k->x_flag = XFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + m68k->n_flag = NFLAG_CLEAR; + m68k->not_z_flag = ZFLAG_SET; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + m68k->c_flag = CFLAG_CLEAR; + m68k->n_flag = NFLAG_8(src); + m68k->not_z_flag = src; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(lsr, 16, r, .) +{ + UINT32* r_dst = &DY; + UINT32 shift = DX & 0x3f; + UINT32 src = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = src >> shift; + + if(shift != 0) + { + m68k->remaining_cycles -= shift<cyc_shift; + + if(shift <= 16) + { + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + m68k->c_flag = m68k->x_flag = (src >> (shift - 1))<<8; + m68k->n_flag = NFLAG_CLEAR; + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + *r_dst &= 0xffff0000; + m68k->x_flag = XFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + m68k->n_flag = NFLAG_CLEAR; + m68k->not_z_flag = ZFLAG_SET; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + m68k->c_flag = CFLAG_CLEAR; + m68k->n_flag = NFLAG_16(src); + m68k->not_z_flag = src; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(lsr, 32, r, .) +{ + UINT32* r_dst = &DY; + UINT32 shift = DX & 0x3f; + UINT32 src = *r_dst; + UINT32 res = src >> shift; + + if(shift != 0) + { + m68k->remaining_cycles -= shift<cyc_shift; + + if(shift < 32) + { + *r_dst = res; + m68k->c_flag = m68k->x_flag = (src >> (shift - 1))<<8; + m68k->n_flag = NFLAG_CLEAR; + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + *r_dst = 0; + m68k->x_flag = m68k->c_flag = (shift == 32 ? GET_MSB_32(src)>>23 : 0); + m68k->n_flag = NFLAG_CLEAR; + m68k->not_z_flag = ZFLAG_SET; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + m68k->c_flag = CFLAG_CLEAR; + m68k->n_flag = NFLAG_32(src); + m68k->not_z_flag = src; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(lsr, 16, ., .) +{ + UINT32 ea = M68KMAKE_GET_EA_AY_16; + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = src >> 1; + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_CLEAR; + m68k->not_z_flag = res; + m68k->c_flag = m68k->x_flag = src << 8; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(lsl, 8, s, .) +{ + UINT32* r_dst = &DY; + UINT32 shift = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 src = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = MASK_OUT_ABOVE_8(src << shift); + + if(shift != 0) + m68k->remaining_cycles -= shift<cyc_shift; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->x_flag = m68k->c_flag = src << shift; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(lsl, 16, s, .) +{ + UINT32* r_dst = &DY; + UINT32 shift = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 src = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = MASK_OUT_ABOVE_16(src << shift); + + if(shift != 0) + m68k->remaining_cycles -= shift<cyc_shift; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->x_flag = m68k->c_flag = src >> (8-shift); + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(lsl, 32, s, .) +{ + UINT32* r_dst = &DY; + UINT32 shift = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 src = *r_dst; + UINT32 res = MASK_OUT_ABOVE_32(src << shift); + + if(shift != 0) + m68k->remaining_cycles -= shift<cyc_shift; + + *r_dst = res; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->x_flag = m68k->c_flag = src >> (24-shift); + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(lsl, 8, r, .) +{ + UINT32* r_dst = &DY; + UINT32 shift = DX & 0x3f; + UINT32 src = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = MASK_OUT_ABOVE_8(src << shift); + + if(shift != 0) + { + m68k->remaining_cycles -= shift<cyc_shift; + + if(shift <= 8) + { + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + m68k->x_flag = m68k->c_flag = src << shift; + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + *r_dst &= 0xffffff00; + m68k->x_flag = XFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + m68k->n_flag = NFLAG_CLEAR; + m68k->not_z_flag = ZFLAG_SET; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + m68k->c_flag = CFLAG_CLEAR; + m68k->n_flag = NFLAG_8(src); + m68k->not_z_flag = src; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(lsl, 16, r, .) +{ + UINT32* r_dst = &DY; + UINT32 shift = DX & 0x3f; + UINT32 src = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = MASK_OUT_ABOVE_16(src << shift); + + if(shift != 0) + { + m68k->remaining_cycles -= shift<cyc_shift; + + if(shift <= 16) + { + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + m68k->x_flag = m68k->c_flag = (src << shift) >> 8; + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + *r_dst &= 0xffff0000; + m68k->x_flag = XFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + m68k->n_flag = NFLAG_CLEAR; + m68k->not_z_flag = ZFLAG_SET; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + m68k->c_flag = CFLAG_CLEAR; + m68k->n_flag = NFLAG_16(src); + m68k->not_z_flag = src; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(lsl, 32, r, .) +{ + UINT32* r_dst = &DY; + UINT32 shift = DX & 0x3f; + UINT32 src = *r_dst; + UINT32 res = MASK_OUT_ABOVE_32(src << shift); + + if(shift != 0) + { + m68k->remaining_cycles -= shift<cyc_shift; + + if(shift < 32) + { + *r_dst = res; + m68k->x_flag = m68k->c_flag = (src >> (32 - shift)) << 8; + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + *r_dst = 0; + m68k->x_flag = m68k->c_flag = ((shift == 32 ? src & 1 : 0))<<8; + m68k->n_flag = NFLAG_CLEAR; + m68k->not_z_flag = ZFLAG_SET; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + m68k->c_flag = CFLAG_CLEAR; + m68k->n_flag = NFLAG_32(src); + m68k->not_z_flag = src; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(lsl, 16, ., .) +{ + UINT32 ea = M68KMAKE_GET_EA_AY_16; + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = MASK_OUT_ABOVE_16(src << 1); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->x_flag = m68k->c_flag = src >> 7; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 8, d, d) +{ + UINT32 res = MASK_OUT_ABOVE_8(DY); + UINT32* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 8, d, .) +{ + UINT32 res = M68KMAKE_GET_OPER_AY_8; + UINT32* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 8, ai, d) +{ + UINT32 res = MASK_OUT_ABOVE_8(DY); + UINT32 ea = EA_AX_AI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 8, ai, .) +{ + UINT32 res = M68KMAKE_GET_OPER_AY_8; + UINT32 ea = EA_AX_AI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 8, pi7, d) +{ + UINT32 res = MASK_OUT_ABOVE_8(DY); + UINT32 ea = EA_A7_PI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 8, pi, d) +{ + UINT32 res = MASK_OUT_ABOVE_8(DY); + UINT32 ea = EA_AX_PI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 8, pi7, .) +{ + UINT32 res = M68KMAKE_GET_OPER_AY_8; + UINT32 ea = EA_A7_PI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 8, pi, .) +{ + UINT32 res = M68KMAKE_GET_OPER_AY_8; + UINT32 ea = EA_AX_PI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 8, pd7, d) +{ + UINT32 res = MASK_OUT_ABOVE_8(DY); + UINT32 ea = EA_A7_PD_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 8, pd, d) +{ + UINT32 res = MASK_OUT_ABOVE_8(DY); + UINT32 ea = EA_AX_PD_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 8, pd7, .) +{ + UINT32 res = M68KMAKE_GET_OPER_AY_8; + UINT32 ea = EA_A7_PD_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 8, pd, .) +{ + UINT32 res = M68KMAKE_GET_OPER_AY_8; + UINT32 ea = EA_AX_PD_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 8, di, d) +{ + UINT32 res = MASK_OUT_ABOVE_8(DY); + UINT32 ea = EA_AX_DI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 8, di, .) +{ + UINT32 res = M68KMAKE_GET_OPER_AY_8; + UINT32 ea = EA_AX_DI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 8, ix, d) +{ + UINT32 res = MASK_OUT_ABOVE_8(DY); + UINT32 ea = EA_AX_IX_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 8, ix, .) +{ + UINT32 res = M68KMAKE_GET_OPER_AY_8; + UINT32 ea = EA_AX_IX_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 8, aw, d) +{ + UINT32 res = MASK_OUT_ABOVE_8(DY); + UINT32 ea = EA_AW_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 8, aw, .) +{ + UINT32 res = M68KMAKE_GET_OPER_AY_8; + UINT32 ea = EA_AW_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 8, al, d) +{ + UINT32 res = MASK_OUT_ABOVE_8(DY); + UINT32 ea = EA_AL_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 8, al, .) +{ + UINT32 res = M68KMAKE_GET_OPER_AY_8; + UINT32 ea = EA_AL_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 16, d, d) +{ + UINT32 res = MASK_OUT_ABOVE_16(DY); + UINT32* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 16, d, a) +{ + UINT32 res = MASK_OUT_ABOVE_16(AY); + UINT32* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 16, d, .) +{ + UINT32 res = M68KMAKE_GET_OPER_AY_16; + UINT32* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 16, ai, d) +{ + UINT32 res = MASK_OUT_ABOVE_16(DY); + UINT32 ea = EA_AX_AI_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 16, ai, a) +{ + UINT32 res = MASK_OUT_ABOVE_16(AY); + UINT32 ea = EA_AX_AI_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 16, ai, .) +{ + UINT32 res = M68KMAKE_GET_OPER_AY_16; + UINT32 ea = EA_AX_AI_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 16, pi, d) +{ + UINT32 res = MASK_OUT_ABOVE_16(DY); + UINT32 ea = EA_AX_PI_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 16, pi, a) +{ + UINT32 res = MASK_OUT_ABOVE_16(AY); + UINT32 ea = EA_AX_PI_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 16, pi, .) +{ + UINT32 res = M68KMAKE_GET_OPER_AY_16; + UINT32 ea = EA_AX_PI_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 16, pd, d) +{ + UINT32 res = MASK_OUT_ABOVE_16(DY); + UINT32 ea = EA_AX_PD_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 16, pd, a) +{ + UINT32 res = MASK_OUT_ABOVE_16(AY); + UINT32 ea = EA_AX_PD_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 16, pd, .) +{ + UINT32 res = M68KMAKE_GET_OPER_AY_16; + UINT32 ea = EA_AX_PD_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 16, di, d) +{ + UINT32 res = MASK_OUT_ABOVE_16(DY); + UINT32 ea = EA_AX_DI_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 16, di, a) +{ + UINT32 res = MASK_OUT_ABOVE_16(AY); + UINT32 ea = EA_AX_DI_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 16, di, .) +{ + UINT32 res = M68KMAKE_GET_OPER_AY_16; + UINT32 ea = EA_AX_DI_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 16, ix, d) +{ + UINT32 res = MASK_OUT_ABOVE_16(DY); + UINT32 ea = EA_AX_IX_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 16, ix, a) +{ + UINT32 res = MASK_OUT_ABOVE_16(AY); + UINT32 ea = EA_AX_IX_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 16, ix, .) +{ + UINT32 res = M68KMAKE_GET_OPER_AY_16; + UINT32 ea = EA_AX_IX_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 16, aw, d) +{ + UINT32 res = MASK_OUT_ABOVE_16(DY); + UINT32 ea = EA_AW_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 16, aw, a) +{ + UINT32 res = MASK_OUT_ABOVE_16(AY); + UINT32 ea = EA_AW_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 16, aw, .) +{ + UINT32 res = M68KMAKE_GET_OPER_AY_16; + UINT32 ea = EA_AW_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 16, al, d) +{ + UINT32 res = MASK_OUT_ABOVE_16(DY); + UINT32 ea = EA_AL_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 16, al, a) +{ + UINT32 res = MASK_OUT_ABOVE_16(AY); + UINT32 ea = EA_AL_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 16, al, .) +{ + UINT32 res = M68KMAKE_GET_OPER_AY_16; + UINT32 ea = EA_AL_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 32, d, d) +{ + UINT32 res = DY; + UINT32* r_dst = &DX; + + *r_dst = res; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 32, d, a) +{ + UINT32 res = AY; + UINT32* r_dst = &DX; + + *r_dst = res; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 32, d, .) +{ + UINT32 res = M68KMAKE_GET_OPER_AY_32; + UINT32* r_dst = &DX; + + *r_dst = res; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 32, ai, d) +{ + UINT32 res = DY; + UINT32 ea = EA_AX_AI_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 32, ai, a) +{ + UINT32 res = AY; + UINT32 ea = EA_AX_AI_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 32, ai, .) +{ + UINT32 res = M68KMAKE_GET_OPER_AY_32; + UINT32 ea = EA_AX_AI_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 32, pi, d) +{ + UINT32 res = DY; + UINT32 ea = EA_AX_PI_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 32, pi, a) +{ + UINT32 res = AY; + UINT32 ea = EA_AX_PI_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 32, pi, .) +{ + UINT32 res = M68KMAKE_GET_OPER_AY_32; + UINT32 ea = EA_AX_PI_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 32, pd, d) +{ + UINT32 res = DY; + UINT32 ea = EA_AX_PD_32(m68k); + + m68ki_write_16(m68k, ea+2, res & 0xFFFF ); + m68ki_write_16(m68k, ea, (res >> 16) & 0xFFFF ); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 32, pd, a) +{ + UINT32 res = AY; + UINT32 ea = EA_AX_PD_32(m68k); + + m68ki_write_16(m68k, ea+2, res & 0xFFFF ); + m68ki_write_16(m68k, ea, (res >> 16) & 0xFFFF ); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 32, pd, .) +{ + UINT32 res = M68KMAKE_GET_OPER_AY_32; + UINT32 ea = EA_AX_PD_32(m68k); + + m68ki_write_16(m68k, ea+2, res & 0xFFFF ); + m68ki_write_16(m68k, ea, (res >> 16) & 0xFFFF ); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 32, di, d) +{ + UINT32 res = DY; + UINT32 ea = EA_AX_DI_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 32, di, a) +{ + UINT32 res = AY; + UINT32 ea = EA_AX_DI_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 32, di, .) +{ + UINT32 res = M68KMAKE_GET_OPER_AY_32; + UINT32 ea = EA_AX_DI_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 32, ix, d) +{ + UINT32 res = DY; + UINT32 ea = EA_AX_IX_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 32, ix, a) +{ + UINT32 res = AY; + UINT32 ea = EA_AX_IX_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 32, ix, .) +{ + UINT32 res = M68KMAKE_GET_OPER_AY_32; + UINT32 ea = EA_AX_IX_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 32, aw, d) +{ + UINT32 res = DY; + UINT32 ea = EA_AW_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 32, aw, a) +{ + UINT32 res = AY; + UINT32 ea = EA_AW_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 32, aw, .) +{ + UINT32 res = M68KMAKE_GET_OPER_AY_32; + UINT32 ea = EA_AW_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 32, al, d) +{ + UINT32 res = DY; + UINT32 ea = EA_AL_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 32, al, a) +{ + UINT32 res = AY; + UINT32 ea = EA_AL_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move, 32, al, .) +{ + UINT32 res = M68KMAKE_GET_OPER_AY_32; + UINT32 ea = EA_AL_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(movea, 16, ., d) +{ + AX = MAKE_INT_16(DY); +} + + +M68KMAKE_OP(movea, 16, ., a) +{ + AX = MAKE_INT_16(AY); +} + + +M68KMAKE_OP(movea, 16, ., .) +{ + AX = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16); +} + + +M68KMAKE_OP(movea, 32, ., d) +{ + AX = DY; +} + + +M68KMAKE_OP(movea, 32, ., a) +{ + AX = AY; +} + + +M68KMAKE_OP(movea, 32, ., .) +{ + AX = M68KMAKE_GET_OPER_AY_32; +} + + +M68KMAKE_OP(move, 16, frc, d) +{ + if(CPU_TYPE_IS_010_PLUS(m68k->cpu_type)) + { + DY = MASK_OUT_BELOW_16(DY) | m68ki_get_ccr(m68k); + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(move, 16, frc, .) +{ + if(CPU_TYPE_IS_010_PLUS(m68k->cpu_type)) + { + m68ki_write_16(m68k, M68KMAKE_GET_EA_AY_16, m68ki_get_ccr(m68k)); + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(move, 16, toc, d) +{ + m68ki_set_ccr(m68k, DY); +} + + +M68KMAKE_OP(move, 16, toc, .) +{ + m68ki_set_ccr(m68k, M68KMAKE_GET_OPER_AY_16); +} + + +M68KMAKE_OP(move, 16, frs, d) +{ + if(CPU_TYPE_IS_000(m68k->cpu_type) || m68k->s_flag) /* NS990408 */ + { + DY = MASK_OUT_BELOW_16(DY) | m68ki_get_sr(m68k); + return; + } + m68ki_exception_privilege_violation(m68k); +} + + +M68KMAKE_OP(move, 16, frs, .) +{ + if(CPU_TYPE_IS_000(m68k->cpu_type) || m68k->s_flag) /* NS990408 */ + { + UINT32 ea = M68KMAKE_GET_EA_AY_16; + m68ki_write_16(m68k, ea, m68ki_get_sr(m68k)); + return; + } + m68ki_exception_privilege_violation(m68k); +} + + +M68KMAKE_OP(move, 16, tos, d) +{ + if(m68k->s_flag) + { + m68ki_set_sr(m68k, DY); + return; + } + m68ki_exception_privilege_violation(m68k); +} + + +M68KMAKE_OP(move, 16, tos, .) +{ + if(m68k->s_flag) + { + UINT32 new_sr = M68KMAKE_GET_OPER_AY_16; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_set_sr(m68k, new_sr); + return; + } + m68ki_exception_privilege_violation(m68k); +} + + +M68KMAKE_OP(move, 32, fru, .) +{ + if(m68k->s_flag) + { + AY = REG_USP; + return; + } + m68ki_exception_privilege_violation(m68k); +} + + +M68KMAKE_OP(move, 32, tou, .) +{ + if(m68k->s_flag) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + REG_USP = AY; + return; + } + m68ki_exception_privilege_violation(m68k); +} + + +M68KMAKE_OP(movec, 32, cr, .) +{ + if(CPU_TYPE_IS_010_PLUS(m68k->cpu_type)) + { + if(m68k->s_flag) + { + UINT32 word2 = OPER_I_16(m68k); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + switch (word2 & 0xfff) + { + case 0x000: /* SFC */ + REG_DA[(word2 >> 12) & 15] = m68k->sfc; + return; + case 0x001: /* DFC */ + REG_DA[(word2 >> 12) & 15] = m68k->dfc; + return; + case 0x002: /* CACR */ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + REG_DA[(word2 >> 12) & 15] = m68k->cacr; + return; + } + return; + case 0x800: /* USP */ + REG_DA[(word2 >> 12) & 15] = REG_USP; + return; + case 0x801: /* VBR */ + REG_DA[(word2 >> 12) & 15] = m68k->vbr; + return; + case 0x802: /* CAAR */ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + REG_DA[(word2 >> 12) & 15] = m68k->caar; + return; + } + m68ki_exception_illegal(m68k); + break; + case 0x803: /* MSP */ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + REG_DA[(word2 >> 12) & 15] = m68k->m_flag ? REG_SP : REG_MSP; + return; + } + m68ki_exception_illegal(m68k); + return; + case 0x804: /* ISP */ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + REG_DA[(word2 >> 12) & 15] = m68k->m_flag ? REG_ISP : REG_SP; + return; + } + m68ki_exception_illegal(m68k); + return; + case 0x003: /* TC */ + if(CPU_TYPE_IS_040_PLUS(m68k->cpu_type)) + { + /* TODO */ + return; + } + m68ki_exception_illegal(m68k); + return; + case 0x004: /* ITT0 */ + if(CPU_TYPE_IS_040_PLUS(m68k->cpu_type)) + { + /* TODO */ + return; + } + m68ki_exception_illegal(m68k); + return; + case 0x005: /* ITT1 */ + if(CPU_TYPE_IS_040_PLUS(m68k->cpu_type)) + { + /* TODO */ + return; + } + m68ki_exception_illegal(m68k); + return; + case 0x006: /* DTT0 */ + if(CPU_TYPE_IS_040_PLUS(m68k->cpu_type)) + { + /* TODO */ + return; + } + m68ki_exception_illegal(m68k); + return; + case 0x007: /* DTT1 */ + if(CPU_TYPE_IS_040_PLUS(m68k->cpu_type)) + { + /* TODO */ + return; + } + m68ki_exception_illegal(m68k); + return; + case 0x805: /* MMUSR */ + if(CPU_TYPE_IS_040_PLUS(m68k->cpu_type)) + { + /* TODO */ + return; + } + m68ki_exception_illegal(m68k); + return; + case 0x806: /* URP */ + if(CPU_TYPE_IS_040_PLUS(m68k->cpu_type)) + { + /* TODO */ + return; + } + m68ki_exception_illegal(m68k); + return; + case 0x807: /* SRP */ + if(CPU_TYPE_IS_040_PLUS(m68k->cpu_type)) + { + /* TODO */ + return; + } + m68ki_exception_illegal(m68k); + return; + default: + m68ki_exception_illegal(m68k); + return; + } + } + m68ki_exception_privilege_violation(m68k); + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(movec, 32, rc, .) +{ + if(CPU_TYPE_IS_010_PLUS(m68k->cpu_type)) + { + if(m68k->s_flag) + { + UINT32 word2 = OPER_I_16(m68k); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + switch (word2 & 0xfff) + { + case 0x000: /* SFC */ + m68k->sfc = REG_DA[(word2 >> 12) & 15] & 7; + return; + case 0x001: /* DFC */ + m68k->dfc = REG_DA[(word2 >> 12) & 15] & 7; + return; + case 0x002: /* CACR */ + /* Only EC020 and later have CACR */ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + /* 68030 can write all bits except 5-7, 040 can write all */ + if (CPU_TYPE_IS_040_PLUS(m68k->cpu_type)) + { + m68k->cacr = REG_DA[(word2 >> 12) & 15]; + } + else if (CPU_TYPE_IS_030_PLUS(m68k->cpu_type)) + { + m68k->cacr = REG_DA[(word2 >> 12) & 15] & 0xff1f; + } + else + { + m68k->cacr = REG_DA[(word2 >> 12) & 15] & 0x0f; + } + return; + } + m68ki_exception_illegal(m68k); + return; + case 0x800: /* USP */ + REG_USP = REG_DA[(word2 >> 12) & 15]; + return; + case 0x801: /* VBR */ + m68k->vbr = REG_DA[(word2 >> 12) & 15]; + return; + case 0x802: /* CAAR */ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + m68k->caar = REG_DA[(word2 >> 12) & 15]; + return; + } + m68ki_exception_illegal(m68k); + return; + case 0x803: /* MSP */ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + /* we are in supervisor mode so just check for M flag */ + if(!m68k->m_flag) + { + REG_MSP = REG_DA[(word2 >> 12) & 15]; + return; + } + REG_SP = REG_DA[(word2 >> 12) & 15]; + return; + } + m68ki_exception_illegal(m68k); + return; + case 0x804: /* ISP */ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(!m68k->m_flag) + { + REG_SP = REG_DA[(word2 >> 12) & 15]; + return; + } + REG_ISP = REG_DA[(word2 >> 12) & 15]; + return; + } + m68ki_exception_illegal(m68k); + return; + case 0x003: /* TC */ + if (CPU_TYPE_IS_040_PLUS(m68k->cpu_type)) + { + /* TODO */ + return; + } + m68ki_exception_illegal(m68k); + return; + case 0x004: /* ITT0 */ + if (CPU_TYPE_IS_040_PLUS(m68k->cpu_type)) + { + /* TODO */ + return; + } + m68ki_exception_illegal(m68k); + return; + case 0x005: /* ITT1 */ + if (CPU_TYPE_IS_040_PLUS(m68k->cpu_type)) + { + /* TODO */ + return; + } + m68ki_exception_illegal(m68k); + return; + case 0x006: /* DTT0 */ + if (CPU_TYPE_IS_040_PLUS(m68k->cpu_type)) + { + /* TODO */ + return; + } + m68ki_exception_illegal(m68k); + return; + case 0x007: /* DTT1 */ + if (CPU_TYPE_IS_040_PLUS(m68k->cpu_type)) + { + /* TODO */ + return; + } + m68ki_exception_illegal(m68k); + return; + case 0x805: /* MMUSR */ + if (CPU_TYPE_IS_040_PLUS(m68k->cpu_type)) + { + /* TODO */ + return; + } + m68ki_exception_illegal(m68k); + return; + case 0x806: /* URP */ + if (CPU_TYPE_IS_040_PLUS(m68k->cpu_type)) + { + /* TODO */ + return; + } + m68ki_exception_illegal(m68k); + return; + case 0x807: /* SRP */ + if (CPU_TYPE_IS_040_PLUS(m68k->cpu_type)) + { + /* TODO */ + return; + } + m68ki_exception_illegal(m68k); + return; + default: + m68ki_exception_illegal(m68k); + return; + } + } + m68ki_exception_privilege_violation(m68k); + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(movem, 16, re, pd) +{ + UINT32 i = 0; + UINT32 register_list = OPER_I_16(m68k); + UINT32 ea = AY; + UINT32 count = 0; + + for(; i < 16; i++) + if(register_list & (1 << i)) + { + ea -= 2; + m68ki_write_16(m68k, ea, MASK_OUT_ABOVE_16(REG_DA[15-i])); + count++; + } + AY = ea; + + m68k->remaining_cycles -= count<cyc_movem_w; +} + + +M68KMAKE_OP(movem, 16, re, .) +{ + UINT32 i = 0; + UINT32 register_list = OPER_I_16(m68k); + UINT32 ea = M68KMAKE_GET_EA_AY_16; + UINT32 count = 0; + + for(; i < 16; i++) + if(register_list & (1 << i)) + { + m68ki_write_16(m68k, ea, MASK_OUT_ABOVE_16(REG_DA[i])); + ea += 2; + count++; + } + + m68k->remaining_cycles -= count<cyc_movem_w; +} + + +M68KMAKE_OP(movem, 32, re, pd) +{ + UINT32 i = 0; + UINT32 register_list = OPER_I_16(m68k); + UINT32 ea = AY; + UINT32 count = 0; + + for(; i < 16; i++) + if(register_list & (1 << i)) + { + ea -= 4; + m68ki_write_16(m68k, ea+2, REG_DA[15-i] & 0xFFFF ); + m68ki_write_16(m68k, ea, (REG_DA[15-i] >> 16) & 0xFFFF ); + count++; + } + AY = ea; + + m68k->remaining_cycles -= count<cyc_movem_l; +} + + +M68KMAKE_OP(movem, 32, re, .) +{ + UINT32 i = 0; + UINT32 register_list = OPER_I_16(m68k); + UINT32 ea = M68KMAKE_GET_EA_AY_32; + UINT32 count = 0; + + for(; i < 16; i++) + if(register_list & (1 << i)) + { + m68ki_write_32(m68k, ea, REG_DA[i]); + ea += 4; + count++; + } + + m68k->remaining_cycles -= count<cyc_movem_l; +} + + +M68KMAKE_OP(movem, 16, er, pi) +{ + UINT32 i = 0; + UINT32 register_list = OPER_I_16(m68k); + UINT32 ea = AY; + UINT32 count = 0; + + for(; i < 16; i++) + if(register_list & (1 << i)) + { + REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(m68k, ea))); + ea += 2; + count++; + } + AY = ea; + + m68k->remaining_cycles -= count<cyc_movem_w; +} + + +M68KMAKE_OP(movem, 16, er, pcdi) +{ + UINT32 i = 0; + UINT32 register_list = OPER_I_16(m68k); + UINT32 ea = EA_PCDI_16(m68k); + UINT32 count = 0; + + for(; i < 16; i++) + if(register_list & (1 << i)) + { + REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_pcrel_16(m68k, ea))); + ea += 2; + count++; + } + + m68k->remaining_cycles -= count<cyc_movem_w; +} + + +M68KMAKE_OP(movem, 16, er, pcix) +{ + UINT32 i = 0; + UINT32 register_list = OPER_I_16(m68k); + UINT32 ea = EA_PCIX_16(m68k); + UINT32 count = 0; + + for(; i < 16; i++) + if(register_list & (1 << i)) + { + REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_pcrel_16(m68k, ea))); + ea += 2; + count++; + } + + m68k->remaining_cycles -= count<cyc_movem_w; +} + + +M68KMAKE_OP(movem, 16, er, .) +{ + UINT32 i = 0; + UINT32 register_list = OPER_I_16(m68k); + UINT32 ea = M68KMAKE_GET_EA_AY_16; + UINT32 count = 0; + + for(; i < 16; i++) + if(register_list & (1 << i)) + { + REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(m68k, ea))); + ea += 2; + count++; + } + + m68k->remaining_cycles -= count<cyc_movem_w; +} + + +M68KMAKE_OP(movem, 32, er, pi) +{ + UINT32 i = 0; + UINT32 register_list = OPER_I_16(m68k); + UINT32 ea = AY; + UINT32 count = 0; + + for(; i < 16; i++) + if(register_list & (1 << i)) + { + REG_DA[i] = m68ki_read_32(m68k, ea); + ea += 4; + count++; + } + AY = ea; + + m68k->remaining_cycles -= count<cyc_movem_l; +} + + +M68KMAKE_OP(movem, 32, er, pcdi) +{ + UINT32 i = 0; + UINT32 register_list = OPER_I_16(m68k); + UINT32 ea = EA_PCDI_32(m68k); + UINT32 count = 0; + + for(; i < 16; i++) + if(register_list & (1 << i)) + { + REG_DA[i] = m68ki_read_pcrel_32(m68k, ea); + ea += 4; + count++; + } + + m68k->remaining_cycles -= count<cyc_movem_l; +} + + +M68KMAKE_OP(movem, 32, er, pcix) +{ + UINT32 i = 0; + UINT32 register_list = OPER_I_16(m68k); + UINT32 ea = EA_PCIX_32(m68k); + UINT32 count = 0; + + for(; i < 16; i++) + if(register_list & (1 << i)) + { + REG_DA[i] = m68ki_read_pcrel_32(m68k, ea); + ea += 4; + count++; + } + + m68k->remaining_cycles -= count<cyc_movem_l; +} + + +M68KMAKE_OP(movem, 32, er, .) +{ + UINT32 i = 0; + UINT32 register_list = OPER_I_16(m68k); + UINT32 ea = M68KMAKE_GET_EA_AY_32; + UINT32 count = 0; + + for(; i < 16; i++) + if(register_list & (1 << i)) + { + REG_DA[i] = m68ki_read_32(m68k, ea); + ea += 4; + count++; + } + + m68k->remaining_cycles -= count<cyc_movem_l; +} + + +M68KMAKE_OP(movep, 16, re, .) +{ + UINT32 ea = EA_AY_DI_16(m68k); + UINT32 src = DX; + + m68ki_write_8(m68k, ea, MASK_OUT_ABOVE_8(src >> 8)); + m68ki_write_8(m68k, ea += 2, MASK_OUT_ABOVE_8(src)); +} + + +M68KMAKE_OP(movep, 32, re, .) +{ + UINT32 ea = EA_AY_DI_32(m68k); + UINT32 src = DX; + + m68ki_write_8(m68k, ea, MASK_OUT_ABOVE_8(src >> 24)); + m68ki_write_8(m68k, ea += 2, MASK_OUT_ABOVE_8(src >> 16)); + m68ki_write_8(m68k, ea += 2, MASK_OUT_ABOVE_8(src >> 8)); + m68ki_write_8(m68k, ea += 2, MASK_OUT_ABOVE_8(src)); +} + + +M68KMAKE_OP(movep, 16, er, .) +{ + UINT32 ea = EA_AY_DI_16(m68k); + UINT32* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | ((m68ki_read_8(m68k, ea) << 8) + m68ki_read_8(m68k, ea + 2)); +} + + +M68KMAKE_OP(movep, 32, er, .) +{ + UINT32 ea = EA_AY_DI_32(m68k); + + DX = (m68ki_read_8(m68k, ea) << 24) + (m68ki_read_8(m68k, ea + 2) << 16) + + (m68ki_read_8(m68k, ea + 4) << 8) + m68ki_read_8(m68k, ea + 6); +} + + +M68KMAKE_OP(moves, 8, ., .) +{ + if(CPU_TYPE_IS_010_PLUS(m68k->cpu_type)) + { + if(m68k->s_flag) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 ea = M68KMAKE_GET_EA_AY_8; + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_8_fc(m68k, ea, m68k->dfc, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15])); + return; + } + if(BIT_F(word2)) /* Memory to address register */ + { + REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(m68k, ea, m68k->sfc)); + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + m68k->remaining_cycles -= 2; + return; + } + /* Memory to data register */ + REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(m68k, ea, m68k->sfc); + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + m68k->remaining_cycles -= 2; + return; + } + m68ki_exception_privilege_violation(m68k); + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(moves, 16, ., .) +{ + if(CPU_TYPE_IS_010_PLUS(m68k->cpu_type)) + { + if(m68k->s_flag) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 ea = M68KMAKE_GET_EA_AY_16; + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_16_fc(m68k, ea, m68k->dfc, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15])); + return; + } + if(BIT_F(word2)) /* Memory to address register */ + { + REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(m68k, ea, m68k->sfc)); + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + m68k->remaining_cycles -= 2; + return; + } + /* Memory to data register */ + REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(m68k, ea, m68k->sfc); + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + m68k->remaining_cycles -= 2; + return; + } + m68ki_exception_privilege_violation(m68k); + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(moves, 32, ., .) +{ + if(CPU_TYPE_IS_010_PLUS(m68k->cpu_type)) + { + if(m68k->s_flag) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 ea = M68KMAKE_GET_EA_AY_32; + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_32_fc(m68k, ea, m68k->dfc, REG_DA[(word2 >> 12) & 15]); + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + m68k->remaining_cycles -= 2; + return; + } + /* Memory to register */ + REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(m68k, ea, m68k->sfc); + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + m68k->remaining_cycles -= 2; + return; + } + m68ki_exception_privilege_violation(m68k); + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(moveq, 32, ., .) +{ + UINT32 res = DX = MAKE_INT_8(MASK_OUT_ABOVE_8(m68k->ir)); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(move16, 32, ., .) +{ + UINT16 w2 = OPER_I_16(m68k); + int ax = m68k->ir & 7; + int ay = (w2 >> 12) & 7; + + m68ki_write_32(m68k, REG_A[ay], m68ki_read_32(m68k, REG_A[ax])); + m68ki_write_32(m68k, REG_A[ay]+4, m68ki_read_32(m68k, REG_A[ax]+4)); + m68ki_write_32(m68k, REG_A[ay]+8, m68ki_read_32(m68k, REG_A[ax]+8)); + m68ki_write_32(m68k, REG_A[ay]+12, m68ki_read_32(m68k, REG_A[ax]+12)); + + REG_A[ax] += 16; + REG_A[ay] += 16; +} + + +M68KMAKE_OP(muls, 16, ., d) +{ + UINT32* r_dst = &DX; + UINT32 res = MASK_OUT_ABOVE_32(MAKE_INT_16(DY) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst))); + + *r_dst = res; + + m68k->not_z_flag = res; + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(muls, 16, ., .) +{ + UINT32* r_dst = &DX; + UINT32 res = MASK_OUT_ABOVE_32(MAKE_INT_16(M68KMAKE_GET_OPER_AY_16) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst))); + + *r_dst = res; + + m68k->not_z_flag = res; + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(mulu, 16, ., d) +{ + UINT32* r_dst = &DX; + UINT32 res = MASK_OUT_ABOVE_16(DY) * MASK_OUT_ABOVE_16(*r_dst); + + *r_dst = res; + + m68k->not_z_flag = res; + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(mulu, 16, ., .) +{ + UINT32* r_dst = &DX; + UINT32 res = M68KMAKE_GET_OPER_AY_16 * MASK_OUT_ABOVE_16(*r_dst); + + *r_dst = res; + + m68k->not_z_flag = res; + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(mull, 32, ., d) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT64 src = DY; + UINT64 dst = REG_D[(word2 >> 12) & 7]; + UINT64 res; + + m68k->c_flag = CFLAG_CLEAR; + + if(BIT_B(word2)) /* signed */ + { + res = (INT64)((INT32)src) * (INT64)((INT32)dst); + if(!BIT_A(word2)) + { + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = ((INT64)res != (INT32)res)<<7; + REG_D[(word2 >> 12) & 7] = m68k->not_z_flag; + return; + } + m68k->not_z_flag = MASK_OUT_ABOVE_32(res) | (res>>32); + m68k->n_flag = NFLAG_64(res); + m68k->v_flag = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + + res = src * dst; + if(!BIT_A(word2)) + { + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = (res > 0xffffffff)<<7; + REG_D[(word2 >> 12) & 7] = m68k->not_z_flag; + return; + } + m68k->not_z_flag = MASK_OUT_ABOVE_32(res) | (res>>32); + m68k->n_flag = NFLAG_64(res); + m68k->v_flag = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(mull, 32, ., .) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT64 src = M68KMAKE_GET_OPER_AY_32; + UINT64 dst = REG_D[(word2 >> 12) & 7]; + UINT64 res; + + m68k->c_flag = CFLAG_CLEAR; + + if(BIT_B(word2)) /* signed */ + { + res = (INT64)((INT32)src) * (INT64)((INT32)dst); + if(!BIT_A(word2)) + { + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = ((INT64)res != (INT32)res)<<7; + REG_D[(word2 >> 12) & 7] = m68k->not_z_flag; + return; + } + m68k->not_z_flag = MASK_OUT_ABOVE_32(res) | (res>>32); + m68k->n_flag = NFLAG_64(res); + m68k->v_flag = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + + res = src * dst; + if(!BIT_A(word2)) + { + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = (res > 0xffffffff)<<7; + REG_D[(word2 >> 12) & 7] = m68k->not_z_flag; + return; + } + m68k->not_z_flag = MASK_OUT_ABOVE_32(res) | (res>>32); + m68k->n_flag = NFLAG_64(res); + m68k->v_flag = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(nbcd, 8, ., d) +{ + UINT32* r_dst = &DY; + UINT32 dst = *r_dst; + UINT32 res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1(m68k)); + + if(res != 0x9a) + { + m68k->v_flag = ~res; /* Undefined V behavior */ + + if((res & 0x0f) == 0xa) + res = (res & 0xf0) + 0x10; + + res = MASK_OUT_ABOVE_8(res); + + m68k->v_flag &= res; /* Undefined V behavior part II */ + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + m68k->not_z_flag |= res; + m68k->c_flag = CFLAG_SET; + m68k->x_flag = XFLAG_SET; + } + else + { + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + m68k->x_flag = XFLAG_CLEAR; + } + m68k->n_flag = NFLAG_8(res); /* Undefined N behavior */ +} + + +M68KMAKE_OP(nbcd, 8, ., .) +{ + UINT32 ea = M68KMAKE_GET_EA_AY_8; + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1(m68k)); + + if(res != 0x9a) + { + m68k->v_flag = ~res; /* Undefined V behavior */ + + if((res & 0x0f) == 0xa) + res = (res & 0xf0) + 0x10; + + res = MASK_OUT_ABOVE_8(res); + + m68k->v_flag &= res; /* Undefined V behavior part II */ + + m68ki_write_8(m68k, ea, MASK_OUT_ABOVE_8(res)); + + m68k->not_z_flag |= res; + m68k->c_flag = CFLAG_SET; + m68k->x_flag = XFLAG_SET; + } + else + { + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + m68k->x_flag = XFLAG_CLEAR; + } + m68k->n_flag = NFLAG_8(res); /* Undefined N behavior */ +} + + +M68KMAKE_OP(neg, 8, ., d) +{ + UINT32* r_dst = &DY; + UINT32 res = 0 - MASK_OUT_ABOVE_8(*r_dst); + + m68k->n_flag = NFLAG_8(res); + m68k->c_flag = m68k->x_flag = CFLAG_8(res); + m68k->v_flag = *r_dst & res; + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | m68k->not_z_flag; +} + + +M68KMAKE_OP(neg, 8, ., .) +{ + UINT32 ea = M68KMAKE_GET_EA_AY_8; + UINT32 src = m68ki_read_8(m68k, ea); + UINT32 res = 0 - src; + + m68k->n_flag = NFLAG_8(res); + m68k->c_flag = m68k->x_flag = CFLAG_8(res); + m68k->v_flag = src & res; + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +M68KMAKE_OP(neg, 16, ., d) +{ + UINT32* r_dst = &DY; + UINT32 res = 0 - MASK_OUT_ABOVE_16(*r_dst); + + m68k->n_flag = NFLAG_16(res); + m68k->c_flag = m68k->x_flag = CFLAG_16(res); + m68k->v_flag = (*r_dst & res)>>8; + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | m68k->not_z_flag; +} + + +M68KMAKE_OP(neg, 16, ., .) +{ + UINT32 ea = M68KMAKE_GET_EA_AY_16; + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = 0 - src; + + m68k->n_flag = NFLAG_16(res); + m68k->c_flag = m68k->x_flag = CFLAG_16(res); + m68k->v_flag = (src & res)>>8; + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +M68KMAKE_OP(neg, 32, ., d) +{ + UINT32* r_dst = &DY; + UINT32 res = 0 - *r_dst; + + m68k->n_flag = NFLAG_32(res); + m68k->c_flag = m68k->x_flag = CFLAG_SUB_32(*r_dst, 0, res); + m68k->v_flag = (*r_dst & res)>>24; + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + *r_dst = m68k->not_z_flag; +} + + +M68KMAKE_OP(neg, 32, ., .) +{ + UINT32 ea = M68KMAKE_GET_EA_AY_32; + UINT32 src = m68ki_read_32(m68k, ea); + UINT32 res = 0 - src; + + m68k->n_flag = NFLAG_32(res); + m68k->c_flag = m68k->x_flag = CFLAG_SUB_32(src, 0, res); + m68k->v_flag = (src & res)>>24; + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(m68k, ea, m68k->not_z_flag); +} + + +M68KMAKE_OP(negx, 8, ., d) +{ + UINT32* r_dst = &DY; + UINT32 res = 0 - MASK_OUT_ABOVE_8(*r_dst) - XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = *r_dst & res; + + res = MASK_OUT_ABOVE_8(res); + m68k->not_z_flag |= res; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; +} + + +M68KMAKE_OP(negx, 8, ., .) +{ + UINT32 ea = M68KMAKE_GET_EA_AY_8; + UINT32 src = m68ki_read_8(m68k, ea); + UINT32 res = 0 - src - XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = src & res; + + res = MASK_OUT_ABOVE_8(res); + m68k->not_z_flag |= res; + + m68ki_write_8(m68k, ea, res); +} + + +M68KMAKE_OP(negx, 16, ., d) +{ + UINT32* r_dst = &DY; + UINT32 res = 0 - MASK_OUT_ABOVE_16(*r_dst) - XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_16(res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->v_flag = (*r_dst & res)>>8; + + res = MASK_OUT_ABOVE_16(res); + m68k->not_z_flag |= res; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; +} + + +M68KMAKE_OP(negx, 16, ., .) +{ + UINT32 ea = M68KMAKE_GET_EA_AY_16; + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_16(res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->v_flag = (src & res)>>8; + + res = MASK_OUT_ABOVE_16(res); + m68k->not_z_flag |= res; + + m68ki_write_16(m68k, ea, res); +} + + +M68KMAKE_OP(negx, 32, ., d) +{ + UINT32* r_dst = &DY; + UINT32 res = 0 - MASK_OUT_ABOVE_32(*r_dst) - XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_32(res); + m68k->x_flag = m68k->c_flag = CFLAG_SUB_32(*r_dst, 0, res); + m68k->v_flag = (*r_dst & res)>>24; + + res = MASK_OUT_ABOVE_32(res); + m68k->not_z_flag |= res; + + *r_dst = res; +} + + +M68KMAKE_OP(negx, 32, ., .) +{ + UINT32 ea = M68KMAKE_GET_EA_AY_32; + UINT32 src = m68ki_read_32(m68k, ea); + UINT32 res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_32(res); + m68k->x_flag = m68k->c_flag = CFLAG_SUB_32(src, 0, res); + m68k->v_flag = (src & res)>>24; + + res = MASK_OUT_ABOVE_32(res); + m68k->not_z_flag |= res; + + m68ki_write_32(m68k, ea, res); +} + + +M68KMAKE_OP(nop, 0, ., .) +{ + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ +} + + +M68KMAKE_OP(not, 8, ., d) +{ + UINT32* r_dst = &DY; + UINT32 res = MASK_OUT_ABOVE_8(~*r_dst); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(not, 8, ., .) +{ + UINT32 ea = M68KMAKE_GET_EA_AY_8; + UINT32 res = MASK_OUT_ABOVE_8(~m68ki_read_8(m68k, ea)); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(not, 16, ., d) +{ + UINT32* r_dst = &DY; + UINT32 res = MASK_OUT_ABOVE_16(~*r_dst); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(not, 16, ., .) +{ + UINT32 ea = M68KMAKE_GET_EA_AY_16; + UINT32 res = MASK_OUT_ABOVE_16(~m68ki_read_16(m68k, ea)); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(not, 32, ., d) +{ + UINT32* r_dst = &DY; + UINT32 res = *r_dst = MASK_OUT_ABOVE_32(~*r_dst); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(not, 32, ., .) +{ + UINT32 ea = M68KMAKE_GET_EA_AY_32; + UINT32 res = MASK_OUT_ABOVE_32(~m68ki_read_32(m68k, ea)); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(or, 8, er, d) +{ + UINT32 res = MASK_OUT_ABOVE_8((DX |= MASK_OUT_ABOVE_8(DY))); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(or, 8, er, .) +{ + UINT32 res = MASK_OUT_ABOVE_8((DX |= M68KMAKE_GET_OPER_AY_8)); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(or, 16, er, d) +{ + UINT32 res = MASK_OUT_ABOVE_16((DX |= MASK_OUT_ABOVE_16(DY))); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(or, 16, er, .) +{ + UINT32 res = MASK_OUT_ABOVE_16((DX |= M68KMAKE_GET_OPER_AY_16)); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(or, 32, er, d) +{ + UINT32 res = DX |= DY; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(or, 32, er, .) +{ + UINT32 res = DX |= M68KMAKE_GET_OPER_AY_32; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(or, 8, re, .) +{ + UINT32 ea = M68KMAKE_GET_EA_AY_8; + UINT32 res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(m68k, ea)); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(or, 16, re, .) +{ + UINT32 ea = M68KMAKE_GET_EA_AY_16; + UINT32 res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(m68k, ea)); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(or, 32, re, .) +{ + UINT32 ea = M68KMAKE_GET_EA_AY_32; + UINT32 res = DX | m68ki_read_32(m68k, ea); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(ori, 8, ., d) +{ + UINT32 res = MASK_OUT_ABOVE_8((DY |= OPER_I_8(m68k))); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(ori, 8, ., .) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 ea = M68KMAKE_GET_EA_AY_8; + UINT32 res = MASK_OUT_ABOVE_8(src | m68ki_read_8(m68k, ea)); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(ori, 16, ., d) +{ + UINT32 res = MASK_OUT_ABOVE_16(DY |= OPER_I_16(m68k)); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(ori, 16, ., .) +{ + UINT32 src = OPER_I_16(m68k); + UINT32 ea = M68KMAKE_GET_EA_AY_16; + UINT32 res = MASK_OUT_ABOVE_16(src | m68ki_read_16(m68k, ea)); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(ori, 32, ., d) +{ + UINT32 res = DY |= OPER_I_32(m68k); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(ori, 32, ., .) +{ + UINT32 src = OPER_I_32(m68k); + UINT32 ea = M68KMAKE_GET_EA_AY_32; + UINT32 res = src | m68ki_read_32(m68k, ea); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(ori, 16, toc, .) +{ + m68ki_set_ccr(m68k, m68ki_get_ccr(m68k) | OPER_I_16(m68k)); +} + + +M68KMAKE_OP(ori, 16, tos, .) +{ + if(m68k->s_flag) + { + UINT32 src = OPER_I_16(m68k); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_set_sr(m68k, m68ki_get_sr(m68k) | src); + return; + } + m68ki_exception_privilege_violation(m68k); +} + + +M68KMAKE_OP(pack, 16, rr, .) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + /* Note: DX and DY are reversed in Motorola's docs */ + UINT32 src = DY + OPER_I_16(m68k); + UINT32* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | ((src >> 4) & 0x00f0) | (src & 0x000f); + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(pack, 16, mm, ax7) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + /* Note: AX and AY are reversed in Motorola's docs */ + UINT32 ea_src = EA_AY_PD_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea_src); + ea_src = EA_AY_PD_8(m68k); + src = ((src << 8) | m68ki_read_8(m68k, ea_src)) + OPER_I_16(m68k); + + m68ki_write_8(m68k, EA_A7_PD_8(m68k), ((src >> 4) & 0x00f0) | (src & 0x000f)); + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(pack, 16, mm, ay7) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + /* Note: AX and AY are reversed in Motorola's docs */ + UINT32 ea_src = EA_A7_PD_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea_src); + ea_src = EA_A7_PD_8(m68k); + src = ((src << 8) | m68ki_read_8(m68k, ea_src)) + OPER_I_16(m68k); + + m68ki_write_8(m68k, EA_AX_PD_8(m68k), ((src >> 4) & 0x00f0) | (src & 0x000f)); + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(pack, 16, mm, axy7) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 ea_src = EA_A7_PD_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea_src); + ea_src = EA_A7_PD_8(m68k); + src = ((src << 8) | m68ki_read_8(m68k, ea_src)) + OPER_I_16(m68k); + + m68ki_write_8(m68k, EA_A7_PD_8(m68k), ((src >> 4) & 0x00f0) | (src & 0x000f)); + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(pack, 16, mm, .) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + /* Note: AX and AY are reversed in Motorola's docs */ + UINT32 ea_src = EA_AY_PD_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea_src); + ea_src = EA_AY_PD_8(m68k); + src = ((src << 8) | m68ki_read_8(m68k, ea_src)) + OPER_I_16(m68k); + + m68ki_write_8(m68k, EA_AX_PD_8(m68k), ((src >> 4) & 0x00f0) | (src & 0x000f)); + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(pea, 32, ., .) +{ + UINT32 ea = M68KMAKE_GET_EA_AY_32; + + m68ki_push_32(m68k, ea); +} + +M68KMAKE_OP(pflush, 32, ., .) +{ + if ((CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) && (m68k->has_pmmu)) + { + logerror("68040: unhandled PFLUSH\n"); + return; + } + m68ki_exception_1111(m68k); +} + +M68KMAKE_OP(pmmu, 32, ., .) +{ + if ((CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) && (m68k->has_pmmu)) + { + m68881_mmu_ops(m68k); + } + else + { + m68ki_exception_1111(m68k); + } +} + +M68KMAKE_OP(reset, 0, ., .) +{ + if(m68k->s_flag) + { + if (m68k->reset_instr_callback != NULL) + (*m68k->reset_instr_callback)(m68k->device); + m68k->remaining_cycles -= m68k->cyc_reset; + return; + } + m68ki_exception_privilege_violation(m68k); +} + + +M68KMAKE_OP(ror, 8, s, .) +{ + UINT32* r_dst = &DY; + UINT32 orig_shift = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 shift = orig_shift & 7; + UINT32 src = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = ROR_8(src, shift); + + if(orig_shift != 0) + m68k->remaining_cycles -= orig_shift<cyc_shift; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = src << (9-orig_shift); + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(ror, 16, s, .) +{ + UINT32* r_dst = &DY; + UINT32 shift = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 src = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = ROR_16(src, shift); + + if(shift != 0) + m68k->remaining_cycles -= shift<cyc_shift; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = src << (9-shift); + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(ror, 32, s, .) +{ + UINT32* r_dst = &DY; + UINT32 shift = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT64 src = *r_dst; + UINT32 res = ROR_32(src, shift); + + if(shift != 0) + m68k->remaining_cycles -= shift<cyc_shift; + + *r_dst = res; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = src << (9-shift); + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(ror, 8, r, .) +{ + UINT32* r_dst = &DY; + UINT32 orig_shift = DX & 0x3f; + UINT32 shift = orig_shift & 7; + UINT32 src = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = ROR_8(src, shift); + + if(orig_shift != 0) + { + m68k->remaining_cycles -= orig_shift<cyc_shift; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + m68k->c_flag = src << (8-((shift-1)&7)); + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + m68k->c_flag = CFLAG_CLEAR; + m68k->n_flag = NFLAG_8(src); + m68k->not_z_flag = src; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(ror, 16, r, .) +{ + UINT32* r_dst = &DY; + UINT32 orig_shift = DX & 0x3f; + UINT32 shift = orig_shift & 15; + UINT32 src = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = ROR_16(src, shift); + + if(orig_shift != 0) + { + m68k->remaining_cycles -= orig_shift<cyc_shift; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + m68k->c_flag = (src >> ((shift - 1) & 15)) << 8; + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + m68k->c_flag = CFLAG_CLEAR; + m68k->n_flag = NFLAG_16(src); + m68k->not_z_flag = src; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(ror, 32, r, .) +{ + UINT32* r_dst = &DY; + UINT32 orig_shift = DX & 0x3f; + UINT32 shift = orig_shift & 31; + UINT64 src = *r_dst; + UINT32 res = ROR_32(src, shift); + + if(orig_shift != 0) + { + m68k->remaining_cycles -= orig_shift<cyc_shift; + + *r_dst = res; + m68k->c_flag = (src >> ((shift - 1) & 31)) << 8; + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + m68k->c_flag = CFLAG_CLEAR; + m68k->n_flag = NFLAG_32(src); + m68k->not_z_flag = src; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(ror, 16, ., .) +{ + UINT32 ea = M68KMAKE_GET_EA_AY_16; + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = ROR_16(src, 1); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = src << 8; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(rol, 8, s, .) +{ + UINT32* r_dst = &DY; + UINT32 orig_shift = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 shift = orig_shift & 7; + UINT32 src = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = ROL_8(src, shift); + + if(orig_shift != 0) + m68k->remaining_cycles -= orig_shift<cyc_shift; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = src << orig_shift; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(rol, 16, s, .) +{ + UINT32* r_dst = &DY; + UINT32 shift = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 src = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = ROL_16(src, shift); + + if(shift != 0) + m68k->remaining_cycles -= shift<cyc_shift; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = src >> (8-shift); + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(rol, 32, s, .) +{ + UINT32* r_dst = &DY; + UINT32 shift = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT64 src = *r_dst; + UINT32 res = ROL_32(src, shift); + + if(shift != 0) + m68k->remaining_cycles -= shift<cyc_shift; + + *r_dst = res; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = src >> (24-shift); + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(rol, 8, r, .) +{ + UINT32* r_dst = &DY; + UINT32 orig_shift = DX & 0x3f; + UINT32 shift = orig_shift & 7; + UINT32 src = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = ROL_8(src, shift); + + if(orig_shift != 0) + { + m68k->remaining_cycles -= orig_shift<cyc_shift; + + if(shift != 0) + { + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + m68k->c_flag = src << shift; + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + return; + } + m68k->c_flag = (src & 1)<<8; + m68k->n_flag = NFLAG_8(src); + m68k->not_z_flag = src; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + m68k->c_flag = CFLAG_CLEAR; + m68k->n_flag = NFLAG_8(src); + m68k->not_z_flag = src; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(rol, 16, r, .) +{ + UINT32* r_dst = &DY; + UINT32 orig_shift = DX & 0x3f; + UINT32 shift = orig_shift & 15; + UINT32 src = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = MASK_OUT_ABOVE_16(ROL_16(src, shift)); + + if(orig_shift != 0) + { + m68k->remaining_cycles -= orig_shift<cyc_shift; + + if(shift != 0) + { + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + m68k->c_flag = (src << shift) >> 8; + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + return; + } + m68k->c_flag = (src & 1)<<8; + m68k->n_flag = NFLAG_16(src); + m68k->not_z_flag = src; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + m68k->c_flag = CFLAG_CLEAR; + m68k->n_flag = NFLAG_16(src); + m68k->not_z_flag = src; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(rol, 32, r, .) +{ + UINT32* r_dst = &DY; + UINT32 orig_shift = DX & 0x3f; + UINT32 shift = orig_shift & 31; + UINT64 src = *r_dst; + UINT32 res = ROL_32(src, shift); + + if(orig_shift != 0) + { + m68k->remaining_cycles -= orig_shift<cyc_shift; + + *r_dst = res; + + m68k->c_flag = (src >> ((32 - shift) & 0x1f)) << 8; + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + m68k->c_flag = CFLAG_CLEAR; + m68k->n_flag = NFLAG_32(src); + m68k->not_z_flag = src; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(rol, 16, ., .) +{ + UINT32 ea = M68KMAKE_GET_EA_AY_16; + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = MASK_OUT_ABOVE_16(ROL_16(src, 1)); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = src >> 7; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(roxr, 8, s, .) +{ + UINT32* r_dst = &DY; + UINT32 shift = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 src = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = ROR_9(src | (XFLAG_AS_1(m68k) << 8), shift); + + if(shift != 0) + m68k->remaining_cycles -= shift<cyc_shift; + + m68k->c_flag = m68k->x_flag = res; + res = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(roxr, 16, s, .) +{ + UINT32* r_dst = &DY; + UINT32 shift = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 src = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = ROR_17(src | (XFLAG_AS_1(m68k) << 16), shift); + + if(shift != 0) + m68k->remaining_cycles -= shift<cyc_shift; + + m68k->c_flag = m68k->x_flag = res >> 8; + res = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(roxr, 32, s, .) +{ + UINT32* r_dst = &DY; + UINT32 shift = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT64 src = *r_dst; + UINT64 res = src | (((UINT64)XFLAG_AS_1(m68k)) << 32); + + if(shift != 0) + m68k->remaining_cycles -= shift<cyc_shift; + + res = ROR_33_64(res, shift); + + m68k->c_flag = m68k->x_flag = res >> 24; + res = MASK_OUT_ABOVE_32(res); + + *r_dst = res; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(roxr, 8, r, .) +{ + UINT32* r_dst = &DY; + UINT32 orig_shift = DX & 0x3f; + + if(orig_shift != 0) + { + UINT32 shift = orig_shift % 9; + UINT32 src = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = ROR_9(src | (XFLAG_AS_1(m68k) << 8), shift); + + m68k->remaining_cycles -= orig_shift<cyc_shift; + + m68k->c_flag = m68k->x_flag = res; + res = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + m68k->c_flag = m68k->x_flag; + m68k->n_flag = NFLAG_8(*r_dst); + m68k->not_z_flag = MASK_OUT_ABOVE_8(*r_dst); + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(roxr, 16, r, .) +{ + UINT32* r_dst = &DY; + UINT32 orig_shift = DX & 0x3f; + + if(orig_shift != 0) + { + UINT32 shift = orig_shift % 17; + UINT32 src = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = ROR_17(src | (XFLAG_AS_1(m68k) << 16), shift); + + m68k->remaining_cycles -= orig_shift<cyc_shift; + + m68k->c_flag = m68k->x_flag = res >> 8; + res = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + m68k->c_flag = m68k->x_flag; + m68k->n_flag = NFLAG_16(*r_dst); + m68k->not_z_flag = MASK_OUT_ABOVE_16(*r_dst); + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(roxr, 32, r, .) +{ + UINT32* r_dst = &DY; + UINT32 orig_shift = DX & 0x3f; + + if(orig_shift != 0) + { + UINT32 shift = orig_shift % 33; + UINT64 src = *r_dst; + UINT64 res = src | (((UINT64)XFLAG_AS_1(m68k)) << 32); + + res = ROR_33_64(res, shift); + + m68k->remaining_cycles -= orig_shift<cyc_shift; + + m68k->c_flag = m68k->x_flag = res >> 24; + res = MASK_OUT_ABOVE_32(res); + + *r_dst = res; + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + m68k->c_flag = m68k->x_flag; + m68k->n_flag = NFLAG_32(*r_dst); + m68k->not_z_flag = *r_dst; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(roxr, 16, ., .) +{ + UINT32 ea = M68KMAKE_GET_EA_AY_16; + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = ROR_17(src | (XFLAG_AS_1(m68k) << 16), 1); + + m68k->c_flag = m68k->x_flag = res >> 8; + res = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(roxl, 8, s, .) +{ + UINT32* r_dst = &DY; + UINT32 shift = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 src = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = ROL_9(src | (XFLAG_AS_1(m68k) << 8), shift); + + if(shift != 0) + m68k->remaining_cycles -= shift<cyc_shift; + + m68k->c_flag = m68k->x_flag = res; + res = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(roxl, 16, s, .) +{ + UINT32* r_dst = &DY; + UINT32 shift = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 src = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = ROL_17(src | (XFLAG_AS_1(m68k) << 16), shift); + + if(shift != 0) + m68k->remaining_cycles -= shift<cyc_shift; + + m68k->c_flag = m68k->x_flag = res >> 8; + res = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(roxl, 32, s, .) +{ + UINT32* r_dst = &DY; + UINT32 shift = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT64 src = *r_dst; + UINT64 res = src | (((UINT64)XFLAG_AS_1(m68k)) << 32); + + if(shift != 0) + m68k->remaining_cycles -= shift<cyc_shift; + + res = ROL_33_64(res, shift); + + m68k->c_flag = m68k->x_flag = res >> 24; + res = MASK_OUT_ABOVE_32(res); + + *r_dst = res; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(roxl, 8, r, .) +{ + UINT32* r_dst = &DY; + UINT32 orig_shift = DX & 0x3f; + + + if(orig_shift != 0) + { + UINT32 shift = orig_shift % 9; + UINT32 src = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = ROL_9(src | (XFLAG_AS_1(m68k) << 8), shift); + + m68k->remaining_cycles -= orig_shift<cyc_shift; + + m68k->c_flag = m68k->x_flag = res; + res = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + m68k->c_flag = m68k->x_flag; + m68k->n_flag = NFLAG_8(*r_dst); + m68k->not_z_flag = MASK_OUT_ABOVE_8(*r_dst); + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(roxl, 16, r, .) +{ + UINT32* r_dst = &DY; + UINT32 orig_shift = DX & 0x3f; + + if(orig_shift != 0) + { + UINT32 shift = orig_shift % 17; + UINT32 src = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = ROL_17(src | (XFLAG_AS_1(m68k) << 16), shift); + + m68k->remaining_cycles -= orig_shift<cyc_shift; + + m68k->c_flag = m68k->x_flag = res >> 8; + res = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + m68k->c_flag = m68k->x_flag; + m68k->n_flag = NFLAG_16(*r_dst); + m68k->not_z_flag = MASK_OUT_ABOVE_16(*r_dst); + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(roxl, 32, r, .) +{ + UINT32* r_dst = &DY; + UINT32 orig_shift = DX & 0x3f; + + if(orig_shift != 0) + { + UINT32 shift = orig_shift % 33; + UINT64 src = *r_dst; + UINT64 res = src | (((UINT64)XFLAG_AS_1(m68k)) << 32); + + res = ROL_33_64(res, shift); + + m68k->remaining_cycles -= orig_shift<cyc_shift; + + m68k->c_flag = m68k->x_flag = res >> 24; + res = MASK_OUT_ABOVE_32(res); + + *r_dst = res; + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + m68k->c_flag = m68k->x_flag; + m68k->n_flag = NFLAG_32(*r_dst); + m68k->not_z_flag = *r_dst; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(roxl, 16, ., .) +{ + UINT32 ea = M68KMAKE_GET_EA_AY_16; + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = ROL_17(src | (XFLAG_AS_1(m68k) << 16), 1); + + m68k->c_flag = m68k->x_flag = res >> 8; + res = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(rtd, 32, ., .) +{ + if(CPU_TYPE_IS_010_PLUS(m68k->cpu_type)) + { + UINT32 new_pc = m68ki_pull_32(m68k); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16(m68k))); + m68ki_jump(m68k, new_pc); + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(rte, 32, ., .) +{ + if(m68k->s_flag) + { + UINT32 new_sr; + UINT32 new_pc; + UINT32 format_word; + + if (m68k->rte_instr_callback != NULL) + (*m68k->rte_instr_callback)(m68k->device); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + + if(CPU_TYPE_IS_000(m68k->cpu_type)) + { + new_sr = m68ki_pull_16(m68k); + new_pc = m68ki_pull_32(m68k); + m68ki_jump(m68k, new_pc); + m68ki_set_sr(m68k, new_sr); + + m68k->instr_mode = INSTRUCTION_YES; + m68k->run_mode = RUN_MODE_NORMAL; + + return; + } + + if(CPU_TYPE_IS_010(m68k->cpu_type)) + { + format_word = m68ki_read_16(m68k, REG_A[7]+6) >> 12; + if(format_word == 0) + { + new_sr = m68ki_pull_16(m68k); + new_pc = m68ki_pull_32(m68k); + m68ki_fake_pull_16(m68k); /* format word */ + m68ki_jump(m68k, new_pc); + m68ki_set_sr(m68k, new_sr); + m68k->instr_mode = INSTRUCTION_YES; + m68k->run_mode = RUN_MODE_NORMAL; + return; + } + m68k->instr_mode = INSTRUCTION_YES; + m68k->run_mode = RUN_MODE_NORMAL; + /* Not handling bus fault (9) */ + m68ki_exception_format_error(m68k); + return; + } + + /* Otherwise it's 020 */ +rte_loop: + format_word = m68ki_read_16(m68k, REG_A[7]+6) >> 12; + switch(format_word) + { + case 0: /* Normal */ + new_sr = m68ki_pull_16(m68k); + new_pc = m68ki_pull_32(m68k); + m68ki_fake_pull_16(m68k); /* format word */ + m68ki_jump(m68k, new_pc); + m68ki_set_sr(m68k, new_sr); + m68k->instr_mode = INSTRUCTION_YES; + m68k->run_mode = RUN_MODE_NORMAL; + return; + case 1: /* Throwaway */ + new_sr = m68ki_pull_16(m68k); + m68ki_fake_pull_32(m68k); /* program counter */ + m68ki_fake_pull_16(m68k); /* format word */ + m68ki_set_sr_noint(m68k, new_sr); + goto rte_loop; + case 2: /* Trap */ + new_sr = m68ki_pull_16(m68k); + new_pc = m68ki_pull_32(m68k); + m68ki_fake_pull_16(m68k); /* format word */ + m68ki_fake_pull_32(m68k); /* address */ + m68ki_jump(m68k, new_pc); + m68ki_set_sr(m68k, new_sr); + m68k->instr_mode = INSTRUCTION_YES; + m68k->run_mode = RUN_MODE_NORMAL; + return; + } + /* Not handling long or short bus fault */ + m68k->instr_mode = INSTRUCTION_YES; + m68k->run_mode = RUN_MODE_NORMAL; + m68ki_exception_format_error(m68k); + return; + } + m68ki_exception_privilege_violation(m68k); +} + + +M68KMAKE_OP(rtm, 32, ., .) +{ + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + logerror("%s at %08x: called unimplemented instruction %04x (rtm)\n", + m68k->device->tag, REG_PC - 2, m68k->ir); + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(rtr, 32, ., .) +{ + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_set_ccr(m68k, m68ki_pull_16(m68k)); + m68ki_jump(m68k, m68ki_pull_32(m68k)); +} + + +M68KMAKE_OP(rts, 32, ., .) +{ + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_jump(m68k, m68ki_pull_32(m68k)); +} + + +M68KMAKE_OP(sbcd, 8, rr, .) +{ + UINT32* r_dst = &DX; + UINT32 src = DY; + UINT32 dst = *r_dst; + UINT32 res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1(m68k); + +// m68k->v_flag = ~res; /* Undefined V behavior */ + m68k->v_flag = VFLAG_CLEAR; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to assume cleared. */ + + if(res > 9) + res -= 6; + res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src); + if(res > 0x99) + { + res += 0xa0; + m68k->x_flag = m68k->c_flag = CFLAG_SET; + m68k->n_flag = NFLAG_SET; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to follow carry. */ + } + else + m68k->n_flag = m68k->x_flag = m68k->c_flag = 0; + + res = MASK_OUT_ABOVE_8(res); + +// m68k->v_flag &= res; /* Undefined V behavior part II */ +// m68k->n_flag = NFLAG_8(res); /* Undefined N behavior */ + m68k->not_z_flag |= res; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; +} + + +M68KMAKE_OP(sbcd, 8, mm, ax7) +{ + UINT32 src = OPER_AY_PD_8(m68k); + UINT32 ea = EA_A7_PD_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1(m68k); + +// m68k->v_flag = ~res; /* Undefined V behavior */ + m68k->v_flag = VFLAG_CLEAR; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to return zero. */ + + if(res > 9) + res -= 6; + res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src); + if(res > 0x99) + { + res += 0xa0; + m68k->x_flag = m68k->c_flag = CFLAG_SET; + m68k->n_flag = NFLAG_SET; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to follow carry. */ + } + else + m68k->n_flag = m68k->x_flag = m68k->c_flag = 0; + + res = MASK_OUT_ABOVE_8(res); + +// m68k->v_flag &= res; /* Undefined V behavior part II */ +// m68k->n_flag = NFLAG_8(res); /* Undefined N behavior */ + m68k->not_z_flag |= res; + + m68ki_write_8(m68k, ea, res); +} + + +M68KMAKE_OP(sbcd, 8, mm, ay7) +{ + UINT32 src = OPER_A7_PD_8(m68k); + UINT32 ea = EA_AX_PD_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1(m68k); + +// m68k->v_flag = ~res; /* Undefined V behavior */ + m68k->v_flag = VFLAG_CLEAR; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to return zero. */ + + if(res > 9) + res -= 6; + res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src); + if(res > 0x99) + { + res += 0xa0; + m68k->x_flag = m68k->c_flag = CFLAG_SET; + m68k->n_flag = NFLAG_SET; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to follow carry. */ + } + else + m68k->n_flag = m68k->x_flag = m68k->c_flag = 0; + + res = MASK_OUT_ABOVE_8(res); + +// m68k->v_flag &= res; /* Undefined V behavior part II */ +// m68k->n_flag = NFLAG_8(res); /* Undefined N behavior */ + m68k->not_z_flag |= res; + + m68ki_write_8(m68k, ea, res); +} + + +M68KMAKE_OP(sbcd, 8, mm, axy7) +{ + UINT32 src = OPER_A7_PD_8(m68k); + UINT32 ea = EA_A7_PD_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1(m68k); + +// m68k->v_flag = ~res; /* Undefined V behavior */ + m68k->v_flag = VFLAG_CLEAR; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to return zero. */ + + if(res > 9) + res -= 6; + res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src); + if(res > 0x99) + { + res += 0xa0; + m68k->x_flag = m68k->c_flag = CFLAG_SET; + m68k->n_flag = NFLAG_SET; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to follow carry. */ + } + else + m68k->n_flag = m68k->x_flag = m68k->c_flag = 0; + + res = MASK_OUT_ABOVE_8(res); + +// m68k->v_flag &= res; /* Undefined V behavior part II */ +// m68k->n_flag = NFLAG_8(res); /* Undefined N behavior */ + m68k->not_z_flag |= res; + + m68ki_write_8(m68k, ea, res); +} + + +M68KMAKE_OP(sbcd, 8, mm, .) +{ + UINT32 src = OPER_AY_PD_8(m68k); + UINT32 ea = EA_AX_PD_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1(m68k); + +// m68k->v_flag = ~res; /* Undefined V behavior */ + m68k->v_flag = VFLAG_CLEAR; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to return zero. */ + + if(res > 9) + res -= 6; + res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src); + if(res > 0x99) + { + res += 0xa0; + m68k->x_flag = m68k->c_flag = CFLAG_SET; + m68k->n_flag = NFLAG_SET; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to follow carry. */ + } + else + m68k->n_flag = m68k->x_flag = m68k->c_flag = 0; + + res = MASK_OUT_ABOVE_8(res); + +// m68k->v_flag &= res; /* Undefined V behavior part II */ +// m68k->n_flag = NFLAG_8(res); /* Undefined N behavior */ + m68k->not_z_flag |= res; + + m68ki_write_8(m68k, ea, res); +} + + +M68KMAKE_OP(st, 8, ., d) +{ + DY |= 0xff; +} + + +M68KMAKE_OP(st, 8, ., .) +{ + m68ki_write_8(m68k, M68KMAKE_GET_EA_AY_8, 0xff); +} + + +M68KMAKE_OP(sf, 8, ., d) +{ + DY &= 0xffffff00; +} + + +M68KMAKE_OP(sf, 8, ., .) +{ + m68ki_write_8(m68k, M68KMAKE_GET_EA_AY_8, 0); +} + + +M68KMAKE_OP(scc, 8, ., d) +{ + if(M68KMAKE_CC) + { + DY |= 0xff; + m68k->remaining_cycles -= m68k->cyc_scc_r_true; + return; + } + DY &= 0xffffff00; +} + + +M68KMAKE_OP(scc, 8, ., .) +{ + m68ki_write_8(m68k, M68KMAKE_GET_EA_AY_8, M68KMAKE_CC ? 0xff : 0); +} + + +M68KMAKE_OP(stop, 0, ., .) +{ + if(m68k->s_flag) + { + UINT32 new_sr = OPER_I_16(m68k); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68k->stopped |= STOP_LEVEL_STOP; + m68ki_set_sr(m68k, new_sr); + m68k->remaining_cycles = 0; + return; + } + m68ki_exception_privilege_violation(m68k); +} + + +M68KMAKE_OP(sub, 8, er, d) +{ + UINT32* r_dst = &DX; + UINT32 src = MASK_OUT_ABOVE_8(DY); + UINT32 dst = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | m68k->not_z_flag; +} + + +M68KMAKE_OP(sub, 8, er, .) +{ + UINT32* r_dst = &DX; + UINT32 src = M68KMAKE_GET_OPER_AY_8; + UINT32 dst = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | m68k->not_z_flag; +} + + +M68KMAKE_OP(sub, 16, er, d) +{ + UINT32* r_dst = &DX; + UINT32 src = MASK_OUT_ABOVE_16(DY); + UINT32 dst = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | m68k->not_z_flag; +} + + +M68KMAKE_OP(sub, 16, er, a) +{ + UINT32* r_dst = &DX; + UINT32 src = MASK_OUT_ABOVE_16(AY); + UINT32 dst = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | m68k->not_z_flag; +} + + +M68KMAKE_OP(sub, 16, er, .) +{ + UINT32* r_dst = &DX; + UINT32 src = M68KMAKE_GET_OPER_AY_16; + UINT32 dst = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | m68k->not_z_flag; +} + + +M68KMAKE_OP(sub, 32, er, d) +{ + UINT32* r_dst = &DX; + UINT32 src = DY; + UINT32 dst = *r_dst; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->x_flag = m68k->c_flag = CFLAG_SUB_32(src, dst, res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + *r_dst = m68k->not_z_flag; +} + + +M68KMAKE_OP(sub, 32, er, a) +{ + UINT32* r_dst = &DX; + UINT32 src = AY; + UINT32 dst = *r_dst; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->x_flag = m68k->c_flag = CFLAG_SUB_32(src, dst, res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + *r_dst = m68k->not_z_flag; +} + + +M68KMAKE_OP(sub, 32, er, .) +{ + UINT32* r_dst = &DX; + UINT32 src = M68KMAKE_GET_OPER_AY_32; + UINT32 dst = *r_dst; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->x_flag = m68k->c_flag = CFLAG_SUB_32(src, dst, res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + *r_dst = m68k->not_z_flag; +} + + +M68KMAKE_OP(sub, 8, re, .) +{ + UINT32 ea = M68KMAKE_GET_EA_AY_8; + UINT32 src = MASK_OUT_ABOVE_8(DX); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +M68KMAKE_OP(sub, 16, re, .) +{ + UINT32 ea = M68KMAKE_GET_EA_AY_16; + UINT32 src = MASK_OUT_ABOVE_16(DX); + UINT32 dst = m68ki_read_16(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +M68KMAKE_OP(sub, 32, re, .) +{ + UINT32 ea = M68KMAKE_GET_EA_AY_32; + UINT32 src = DX; + UINT32 dst = m68ki_read_32(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->x_flag = m68k->c_flag = CFLAG_SUB_32(src, dst, res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(m68k, ea, m68k->not_z_flag); +} + + +M68KMAKE_OP(suba, 16, ., d) +{ + UINT32* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(DY)); +} + + +M68KMAKE_OP(suba, 16, ., a) +{ + UINT32* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(AY)); +} + + +M68KMAKE_OP(suba, 16, ., .) +{ + UINT32* r_dst = &AX; + UINT32 src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16); + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - src); +} + + +M68KMAKE_OP(suba, 32, ., d) +{ + UINT32* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - DY); +} + + +M68KMAKE_OP(suba, 32, ., a) +{ + UINT32* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - AY); +} + + +M68KMAKE_OP(suba, 32, ., .) +{ + UINT32* r_dst = &AX; + UINT32 src = M68KMAKE_GET_OPER_AY_32; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - src); +} + + +M68KMAKE_OP(subi, 8, ., d) +{ + UINT32* r_dst = &DY; + UINT32 src = OPER_I_8(m68k); + UINT32 dst = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | m68k->not_z_flag; +} + + +M68KMAKE_OP(subi, 8, ., .) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 ea = M68KMAKE_GET_EA_AY_8; + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +M68KMAKE_OP(subi, 16, ., d) +{ + UINT32* r_dst = &DY; + UINT32 src = OPER_I_16(m68k); + UINT32 dst = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | m68k->not_z_flag; +} + + +M68KMAKE_OP(subi, 16, ., .) +{ + UINT32 src = OPER_I_16(m68k); + UINT32 ea = M68KMAKE_GET_EA_AY_16; + UINT32 dst = m68ki_read_16(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +M68KMAKE_OP(subi, 32, ., d) +{ + UINT32* r_dst = &DY; + UINT32 src = OPER_I_32(m68k); + UINT32 dst = *r_dst; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->x_flag = m68k->c_flag = CFLAG_SUB_32(src, dst, res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + + *r_dst = m68k->not_z_flag; +} + + +M68KMAKE_OP(subi, 32, ., .) +{ + UINT32 src = OPER_I_32(m68k); + UINT32 ea = M68KMAKE_GET_EA_AY_32; + UINT32 dst = m68ki_read_32(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->x_flag = m68k->c_flag = CFLAG_SUB_32(src, dst, res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(m68k, ea, m68k->not_z_flag); +} + + +M68KMAKE_OP(subq, 8, ., d) +{ + UINT32* r_dst = &DY; + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 dst = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | m68k->not_z_flag; +} + + +M68KMAKE_OP(subq, 8, ., .) +{ + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 ea = M68KMAKE_GET_EA_AY_8; + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +M68KMAKE_OP(subq, 16, ., d) +{ + UINT32* r_dst = &DY; + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 dst = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | m68k->not_z_flag; +} + + +M68KMAKE_OP(subq, 16, ., a) +{ + UINT32* r_dst = &AY; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((m68k->ir >> 9) - 1) & 7) + 1)); +} + + +M68KMAKE_OP(subq, 16, ., .) +{ + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 ea = M68KMAKE_GET_EA_AY_16; + UINT32 dst = m68ki_read_16(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +M68KMAKE_OP(subq, 32, ., d) +{ + UINT32* r_dst = &DY; + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 dst = *r_dst; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->x_flag = m68k->c_flag = CFLAG_SUB_32(src, dst, res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + + *r_dst = m68k->not_z_flag; +} + + +M68KMAKE_OP(subq, 32, ., a) +{ + UINT32* r_dst = &AY; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((m68k->ir >> 9) - 1) & 7) + 1)); +} + + +M68KMAKE_OP(subq, 32, ., .) +{ + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 ea = M68KMAKE_GET_EA_AY_32; + UINT32 dst = m68ki_read_32(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->x_flag = m68k->c_flag = CFLAG_SUB_32(src, dst, res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(m68k, ea, m68k->not_z_flag); +} + + +M68KMAKE_OP(subx, 8, rr, .) +{ + UINT32* r_dst = &DX; + UINT32 src = MASK_OUT_ABOVE_8(DY); + UINT32 dst = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = dst - src - XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + + res = MASK_OUT_ABOVE_8(res); + m68k->not_z_flag |= res; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; +} + + +M68KMAKE_OP(subx, 16, rr, .) +{ + UINT32* r_dst = &DX; + UINT32 src = MASK_OUT_ABOVE_16(DY); + UINT32 dst = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = dst - src - XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_16(res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + + res = MASK_OUT_ABOVE_16(res); + m68k->not_z_flag |= res; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; +} + + +M68KMAKE_OP(subx, 32, rr, .) +{ + UINT32* r_dst = &DX; + UINT32 src = DY; + UINT32 dst = *r_dst; + UINT32 res = dst - src - XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_32(res); + m68k->x_flag = m68k->c_flag = CFLAG_SUB_32(src, dst, res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + + res = MASK_OUT_ABOVE_32(res); + m68k->not_z_flag |= res; + + *r_dst = res; +} + + +M68KMAKE_OP(subx, 8, mm, ax7) +{ + UINT32 src = OPER_AY_PD_8(m68k); + UINT32 ea = EA_A7_PD_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = dst - src - XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + + res = MASK_OUT_ABOVE_8(res); + m68k->not_z_flag |= res; + + m68ki_write_8(m68k, ea, res); +} + + +M68KMAKE_OP(subx, 8, mm, ay7) +{ + UINT32 src = OPER_A7_PD_8(m68k); + UINT32 ea = EA_AX_PD_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = dst - src - XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + + res = MASK_OUT_ABOVE_8(res); + m68k->not_z_flag |= res; + + m68ki_write_8(m68k, ea, res); +} + + +M68KMAKE_OP(subx, 8, mm, axy7) +{ + UINT32 src = OPER_A7_PD_8(m68k); + UINT32 ea = EA_A7_PD_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = dst - src - XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + + res = MASK_OUT_ABOVE_8(res); + m68k->not_z_flag |= res; + + m68ki_write_8(m68k, ea, res); +} + + +M68KMAKE_OP(subx, 8, mm, .) +{ + UINT32 src = OPER_AY_PD_8(m68k); + UINT32 ea = EA_AX_PD_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = dst - src - XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + + res = MASK_OUT_ABOVE_8(res); + m68k->not_z_flag |= res; + + m68ki_write_8(m68k, ea, res); +} + + +M68KMAKE_OP(subx, 16, mm, .) +{ + UINT32 src = OPER_AY_PD_16(m68k); + UINT32 ea = EA_AX_PD_16(m68k); + UINT32 dst = m68ki_read_16(m68k, ea); + UINT32 res = dst - src - XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_16(res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + + res = MASK_OUT_ABOVE_16(res); + m68k->not_z_flag |= res; + + m68ki_write_16(m68k, ea, res); +} + + +M68KMAKE_OP(subx, 32, mm, .) +{ + UINT32 src = OPER_AY_PD_32(m68k); + UINT32 ea = EA_AX_PD_32(m68k); + UINT32 dst = m68ki_read_32(m68k, ea); + UINT32 res = dst - src - XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_32(res); + m68k->x_flag = m68k->c_flag = CFLAG_SUB_32(src, dst, res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + + res = MASK_OUT_ABOVE_32(res); + m68k->not_z_flag |= res; + + m68ki_write_32(m68k, ea, res); +} + + +M68KMAKE_OP(swap, 32, ., .) +{ + UINT32* r_dst = &DY; + + m68k->not_z_flag = MASK_OUT_ABOVE_32(*r_dst<<16); + *r_dst = (*r_dst>>16) | m68k->not_z_flag; + + m68k->not_z_flag = *r_dst; + m68k->n_flag = NFLAG_32(*r_dst); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +M68KMAKE_OP(tas, 8, ., d) +{ + UINT32* r_dst = &DY; + + m68k->not_z_flag = MASK_OUT_ABOVE_8(*r_dst); + m68k->n_flag = NFLAG_8(*r_dst); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + *r_dst |= 0x80; +} + + +M68KMAKE_OP(tas, 8, ., .) +{ + UINT32 ea = M68KMAKE_GET_EA_AY_8; + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 allow_writeback = TRUE; + + m68k->not_z_flag = dst; + m68k->n_flag = NFLAG_8(dst); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + /* The Genesis/Megadrive games Gargoyles and Ex-Mutants need the TAS writeback + disabled in order to function properly. Some Amiga software may also rely + on this, but only when accessing specific addresses so additional functionality + will be needed. */ + if (m68k->tas_instr_callback != NULL) + allow_writeback = (*m68k->tas_instr_callback)(m68k->device); + + if (allow_writeback) + m68ki_write_8(m68k, ea, dst | 0x80); +} + + +M68KMAKE_OP(trap, 0, ., .) +{ + /* Trap#n stacks exception frame type 0 */ + m68ki_exception_trapN(m68k, EXCEPTION_TRAP_BASE + (m68k->ir & 0xf)); /* HJB 990403 */ +} + + +M68KMAKE_OP(trapt, 0, ., .) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + m68ki_exception_trap(m68k, EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(trapt, 16, ., .) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + m68ki_exception_trap(m68k, EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(trapt, 32, ., .) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + m68ki_exception_trap(m68k, EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(trapf, 0, ., .) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(trapf, 16, ., .) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + REG_PC += 2; + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(trapf, 32, ., .) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + REG_PC += 4; + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(trapcc, 0, ., .) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(M68KMAKE_CC) + m68ki_exception_trap(m68k, EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(trapcc, 16, ., .) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(M68KMAKE_CC) + { + m68ki_exception_trap(m68k, EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 2; + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(trapcc, 32, ., .) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(M68KMAKE_CC) + { + m68ki_exception_trap(m68k, EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(trapv, 0, ., .) +{ + if(COND_VC(m68k)) + { + return; + } + m68ki_exception_trap(m68k, EXCEPTION_TRAPV); /* HJB 990403 */ +} + + +M68KMAKE_OP(tst, 8, ., d) +{ + UINT32 res = MASK_OUT_ABOVE_8(DY); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(tst, 8, ., .) +{ + UINT32 res = M68KMAKE_GET_OPER_AY_8; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(tst, 8, ., pcdi) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 res = OPER_PCDI_8(m68k); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(tst, 8, ., pcix) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 res = OPER_PCIX_8(m68k); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(tst, 8, ., i) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 res = OPER_I_8(m68k); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(tst, 16, ., d) +{ + UINT32 res = MASK_OUT_ABOVE_16(DY); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(tst, 16, ., a) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 res = MAKE_INT_16(AY); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(tst, 16, ., .) +{ + UINT32 res = M68KMAKE_GET_OPER_AY_16; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(tst, 16, ., pcdi) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 res = OPER_PCDI_16(m68k); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(tst, 16, ., pcix) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 res = OPER_PCIX_16(m68k); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(tst, 16, ., i) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 res = OPER_I_16(m68k); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(tst, 32, ., d) +{ + UINT32 res = DY; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(tst, 32, ., a) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 res = AY; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(tst, 32, ., .) +{ + UINT32 res = M68KMAKE_GET_OPER_AY_32; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +M68KMAKE_OP(tst, 32, ., pcdi) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 res = OPER_PCDI_32(m68k); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(tst, 32, ., pcix) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 res = OPER_PCIX_32(m68k); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(tst, 32, ., i) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 res = OPER_I_32(m68k); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(unlk, 32, ., a7) +{ + REG_A[7] = m68ki_read_32(m68k, REG_A[7]); +} + + +M68KMAKE_OP(unlk, 32, ., .) +{ + UINT32* r_dst = &AY; + + REG_A[7] = *r_dst; + *r_dst = m68ki_pull_32(m68k); +} + + +M68KMAKE_OP(unpk, 16, rr, .) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + /* Note: DX and DY are reversed in Motorola's docs */ + UINT32 src = DY; + UINT32* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | (((((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16(m68k)) & 0xffff); + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(unpk, 16, mm, ax7) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + /* Note: AX and AY are reversed in Motorola's docs */ + UINT32 src = OPER_AY_PD_8(m68k); + UINT32 ea_dst; + + src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16(m68k); + ea_dst = EA_A7_PD_8(m68k); + m68ki_write_8(m68k, ea_dst, (src >> 8) & 0xff); + ea_dst = EA_A7_PD_8(m68k); + m68ki_write_8(m68k, ea_dst, src & 0xff); + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(unpk, 16, mm, ay7) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + /* Note: AX and AY are reversed in Motorola's docs */ + UINT32 src = OPER_A7_PD_8(m68k); + UINT32 ea_dst; + + src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16(m68k); + ea_dst = EA_AX_PD_8(m68k); + m68ki_write_8(m68k, ea_dst, (src >> 8) & 0xff); + ea_dst = EA_AX_PD_8(m68k); + m68ki_write_8(m68k, ea_dst, src & 0xff); + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(unpk, 16, mm, axy7) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 src = OPER_A7_PD_8(m68k); + UINT32 ea_dst; + + src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16(m68k); + ea_dst = EA_A7_PD_8(m68k); + m68ki_write_8(m68k, ea_dst, (src >> 8) & 0xff); + ea_dst = EA_A7_PD_8(m68k); + m68ki_write_8(m68k, ea_dst, src & 0xff); + return; + } + m68ki_exception_illegal(m68k); +} + + +M68KMAKE_OP(unpk, 16, mm, .) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + /* Note: AX and AY are reversed in Motorola's docs */ + UINT32 src = OPER_AY_PD_8(m68k); + UINT32 ea_dst; + + src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16(m68k); + ea_dst = EA_AX_PD_8(m68k); + m68ki_write_8(m68k, ea_dst, (src >> 8) & 0xff); + ea_dst = EA_AX_PD_8(m68k); + m68ki_write_8(m68k, ea_dst, src & 0xff); + return; + } + m68ki_exception_illegal(m68k); +} + + + +XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +M68KMAKE_END diff --git a/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/m68k/m68kconf.h b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/m68k/m68kconf.h new file mode 100644 index 000000000..52cd366bd --- /dev/null +++ b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/m68k/m68kconf.h @@ -0,0 +1,98 @@ +#ifndef M68KCONF__HEADER +#define M68KCONF__HEADER + +/* ======================================================================== */ +/* ======================== MAIN 68K CONFIGURATION ======================== */ +/* ======================================================================== */ + +/* Configuration switches. + * Use OPT_SPECIFY_HANDLER for configuration options that allow callbacks. + * OPT_SPECIFY_HANDLER causes the core to link directly to the function + * or macro you specify, rather than using callback functions whose pointer + * must be passed in using m68k_set_xxx_callback(). + */ +#define OPT_OFF 0 +#define OPT_ON 1 +#define OPT_SPECIFY_HANDLER 2 + +/* If ON, the CPU will call m68k_write_32_pd() when it executes move.l with a + * predecrement destination EA mode instead of m68k_write_32(). + * To simulate real 68k behavior, m68k_write_32_pd() must first write the high + * word to [address+2], and then write the low word to [address]. + */ +#define M68K_SIMULATE_PD_WRITES OPT_OFF + +/* If ON, CPU will call the interrupt acknowledge callback when it services an + * interrupt. + * If off, all interrupts will be autovectored and all interrupt requests will + * auto-clear when the interrupt is serviced. + */ +#define M68K_EMULATE_INT_ACK OPT_OFF +#define M68K_INT_ACK_CALLBACK(A) vdp_68k_irq_ack(A) + +/* If ON, CPU will call the output reset callback when it encounters a reset + * instruction. + */ +#define M68K_EMULATE_RESET OPT_OFF +#define M68K_RESET_CALLBACK() your_reset_handler_function() + +/* If ON, CPU will call the callback when it encounters a tas + * instruction. + */ +#define M68K_TAS_HAS_CALLBACK OPT_OFF +#define M68K_TAS_CALLBACK() your_tas_handler_function() + +/* If ON, CPU will call the set fc callback on every memory access to + * differentiate between user/supervisor, program/data access like a real + * 68000 would. This should be enabled and the callback should be set if you + * want to properly emulate the m68010 or higher. (moves uses function codes + * to read/write data from different address spaces) + */ +#define M68K_EMULATE_FC OPT_OFF +#define M68K_SET_FC_CALLBACK(A) your_set_fc_handler_function(A) + +/* If ON, the CPU will monitor the trace flags and take trace exceptions + */ +#define M68K_EMULATE_TRACE OPT_OFF + +/* If ON, the CPU will emulate the 4-byte prefetch queue of a real 68000 */ +#define M68K_EMULATE_PREFETCH OPT_OFF + +/* If ON, the CPU will generate address error exceptions if it tries to + * access a word or longword at an odd address. + * NOTE: This is only emulated properly for 68000 mode. + */ +#define M68K_EMULATE_ADDRESS_ERROR OPT_OFF + +/* If ON and previous option is also ON, address error exceptions will + also be checked when fetching instructions. Disabling this can help + speeding up emulation while still emulating address error exceptions + on other memory access if needed. + * NOTE: This is only emulated properly for 68000 mode. + */ +#define M68K_CHECK_PC_ADDRESS_ERROR OPT_OFF + + +/* ----------------------------- COMPATIBILITY ---------------------------- */ + +/* The following options set optimizations that violate the current ANSI + * standard, but will be compliant under the forthcoming C9X standard. + */ + + +/* If ON, the enulation core will use 64-bit integers to speed up some + * operations. +*/ + +#if defined(_WIN64) || defined(__amd64__) +#define M68K_USE_64_BIT OPT_ON +#else +#define M68K_USE_64_BIT OPT_OFF +#endif + + +/* ======================================================================== */ +/* ============================== END OF FILE ============================= */ +/* ======================================================================== */ + +#endif /* M68KCONF__HEADER */ diff --git a/Frameworks/AudioOverload/aosdk/eng_ssf/m68kcpu.c b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/m68k/m68kcpu.c similarity index 55% rename from Frameworks/AudioOverload/aosdk/eng_ssf/m68kcpu.c rename to Frameworks/HighlyTheoretical/HighlyTheoretical/Core/m68k/m68kcpu.c index 94e3635fa..0ce3f683d 100644 --- a/Frameworks/AudioOverload/aosdk/eng_ssf/m68kcpu.c +++ b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/m68k/m68kcpu.c @@ -3,21 +3,21 @@ /* ======================================================================== */ #if 0 -static const char* copyright_notice = +static const char copyright_notice[] = "MUSASHI\n" -"Version 3.3 (2001-01-29)\n" +"Version 4.55 (2009-10-31)\n" "A portable Motorola M680x0 processor emulation engine.\n" -"Copyright 1998-2001 Karl Stenerud. All rights reserved.\n" +"Copyright Karl Stenerud. All rights reserved.\n" "\n" "This code may be freely used for non-commercial purpooses as long as this\n" "copyright notice remains unaltered in the source code and any binary files\n" "containing this code in compiled form.\n" "\n" -"All other lisencing terms must be negotiated with the author\n" +"All other licensing terms must be negotiated with the author\n" "(Karl Stenerud).\n" "\n" "The latest version of this code can be obtained at:\n" -"http://kstenerud.cjb.net\n" +"http://kstenerud.cjb.net or http://mamedev.org\n" ; #endif @@ -32,46 +32,17 @@ static const char* copyright_notice = /* ================================ INCLUDES ============================== */ /* ======================================================================== */ -#include "m68kops.h" +#include +#include "m68kconf.h" #include "m68kcpu.h" +#include "m68kops.h" /* ======================================================================== */ /* ================================= DATA ================================= */ /* ======================================================================== */ -int m68ki_initial_cycles; -int m68ki_remaining_cycles = 0; /* Number of clocks remaining */ -uint m68ki_tracing = 0; -uint m68ki_address_space; - -#ifdef M68K_LOG_ENABLE -char* m68ki_cpu_names[9] = -{ - "Invalid CPU", - "M68000", - "M68010", - "Invalid CPU", - "M68EC020" - "Invalid CPU", - "Invalid CPU", - "Invalid CPU", - "M68020" -}; -#endif /* M68K_LOG_ENABLE */ - -/* The CPU core */ -m68ki_cpu_core m68ki_cpu = {0}; - -#if M68K_EMULATE_ADDRESS_ERROR -jmp_buf m68ki_aerr_trap; -#endif /* M68K_EMULATE_ADDRESS_ERROR */ - -uint m68ki_aerr_address; -uint m68ki_aerr_write_mode; -uint m68ki_aerr_fc; - /* Used by shift & rotate instructions */ -uint8 m68ki_shift_8_table[65] = +const UINT8 m68ki_shift_8_table[65] = { 0x00, 0x80, 0xc0, 0xe0, 0xf0, 0xf8, 0xfc, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -80,7 +51,7 @@ uint8 m68ki_shift_8_table[65] = 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; -uint16 m68ki_shift_16_table[65] = +const UINT16 m68ki_shift_16_table[65] = { 0x0000, 0x8000, 0xc000, 0xe000, 0xf000, 0xf800, 0xfc00, 0xfe00, 0xff00, 0xff80, 0xffc0, 0xffe0, 0xfff0, 0xfff8, 0xfffc, 0xfffe, 0xffff, 0xffff, @@ -91,7 +62,7 @@ uint16 m68ki_shift_16_table[65] = 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff }; -uint m68ki_shift_32_table[65] = +const UINT32 m68ki_shift_32_table[65] = { 0x00000000, 0x80000000, 0xc0000000, 0xe0000000, 0xf0000000, 0xf8000000, 0xfc000000, 0xfe000000, 0xff000000, 0xff800000, 0xffc00000, 0xffe00000, @@ -110,16 +81,16 @@ uint m68ki_shift_32_table[65] = /* Number of clock cycles to use for exception processing. * I used 4 for any vectors that are undocumented for processing times. */ -uint8 m68ki_exception_cycle_table[3][256] = +const UINT8 m68ki_exception_cycle_table[5][256] = { { /* 000 */ - 4, /* 0: Reset - Initial Stack Pointer */ + 40, /* 0: Reset - Initial Stack Pointer */ 4, /* 1: Reset - Initial Program Counter */ 50, /* 2: Bus Error (unemulated) */ 50, /* 3: Address Error (unemulated) */ 34, /* 4: Illegal Instruction */ - 38, /* 5: Divide by Zero -- ASG: changed from 42 */ - 40, /* 6: CHK -- ASG: chanaged from 44 */ + 38, /* 5: Divide by Zero */ + 40, /* 6: CHK */ 34, /* 7: TRAPV */ 34, /* 8: Privilege Violation */ 34, /* 9: Trace */ @@ -145,7 +116,7 @@ uint8 m68ki_exception_cycle_table[3][256] = 44, /* 29: Level 5 Interrupt Autovector */ 44, /* 30: Level 6 Interrupt Autovector */ 44, /* 31: Level 7 Interrupt Autovector */ - 34, /* 32: TRAP #0 -- ASG: chanaged from 38 */ + 34, /* 32: TRAP #0 */ 34, /* 33: TRAP #1 */ 34, /* 34: TRAP #2 */ 34, /* 35: TRAP #3 */ @@ -186,7 +157,7 @@ uint8 m68ki_exception_cycle_table[3][256] = 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4 }, { /* 010 */ - 4, /* 0: Reset - Initial Stack Pointer */ + 40, /* 0: Reset - Initial Stack Pointer */ 4, /* 1: Reset - Initial Program Counter */ 126, /* 2: Bus Error (unemulated) */ 126, /* 3: Address Error (unemulated) */ @@ -330,10 +301,156 @@ uint8 m68ki_exception_cycle_table[3][256] = 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4, 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4, 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4 + }, + { /* 030 - not correct */ + 4, /* 0: Reset - Initial Stack Pointer */ + 4, /* 1: Reset - Initial Program Counter */ + 50, /* 2: Bus Error (unemulated) */ + 50, /* 3: Address Error (unemulated) */ + 20, /* 4: Illegal Instruction */ + 38, /* 5: Divide by Zero */ + 40, /* 6: CHK */ + 20, /* 7: TRAPV */ + 34, /* 8: Privilege Violation */ + 25, /* 9: Trace */ + 20, /* 10: 1010 */ + 20, /* 11: 1111 */ + 4, /* 12: RESERVED */ + 4, /* 13: Coprocessor Protocol Violation (unemulated) */ + 4, /* 14: Format Error */ + 30, /* 15: Uninitialized Interrupt */ + 4, /* 16: RESERVED */ + 4, /* 17: RESERVED */ + 4, /* 18: RESERVED */ + 4, /* 19: RESERVED */ + 4, /* 20: RESERVED */ + 4, /* 21: RESERVED */ + 4, /* 22: RESERVED */ + 4, /* 23: RESERVED */ + 30, /* 24: Spurious Interrupt */ + 30, /* 25: Level 1 Interrupt Autovector */ + 30, /* 26: Level 2 Interrupt Autovector */ + 30, /* 27: Level 3 Interrupt Autovector */ + 30, /* 28: Level 4 Interrupt Autovector */ + 30, /* 29: Level 5 Interrupt Autovector */ + 30, /* 30: Level 6 Interrupt Autovector */ + 30, /* 31: Level 7 Interrupt Autovector */ + 20, /* 32: TRAP #0 */ + 20, /* 33: TRAP #1 */ + 20, /* 34: TRAP #2 */ + 20, /* 35: TRAP #3 */ + 20, /* 36: TRAP #4 */ + 20, /* 37: TRAP #5 */ + 20, /* 38: TRAP #6 */ + 20, /* 39: TRAP #7 */ + 20, /* 40: TRAP #8 */ + 20, /* 41: TRAP #9 */ + 20, /* 42: TRAP #10 */ + 20, /* 43: TRAP #11 */ + 20, /* 44: TRAP #12 */ + 20, /* 45: TRAP #13 */ + 20, /* 46: TRAP #14 */ + 20, /* 47: TRAP #15 */ + 4, /* 48: FP Branch or Set on Unknown Condition (unemulated) */ + 4, /* 49: FP Inexact Result (unemulated) */ + 4, /* 50: FP Divide by Zero (unemulated) */ + 4, /* 51: FP Underflow (unemulated) */ + 4, /* 52: FP Operand Error (unemulated) */ + 4, /* 53: FP Overflow (unemulated) */ + 4, /* 54: FP Signaling NAN (unemulated) */ + 4, /* 55: FP Unimplemented Data Type (unemulated) */ + 4, /* 56: MMU Configuration Error (unemulated) */ + 4, /* 57: MMU Illegal Operation Error (unemulated) */ + 4, /* 58: MMU Access Level Violation Error (unemulated) */ + 4, /* 59: RESERVED */ + 4, /* 60: RESERVED */ + 4, /* 61: RESERVED */ + 4, /* 62: RESERVED */ + 4, /* 63: RESERVED */ + /* 64-255: User Defined */ + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4, + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4, + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4, + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4, + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4, + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4 + }, + { /* 040 */ // TODO: these values are not correct + 4, /* 0: Reset - Initial Stack Pointer */ + 4, /* 1: Reset - Initial Program Counter */ + 50, /* 2: Bus Error (unemulated) */ + 50, /* 3: Address Error (unemulated) */ + 20, /* 4: Illegal Instruction */ + 38, /* 5: Divide by Zero */ + 40, /* 6: CHK */ + 20, /* 7: TRAPV */ + 34, /* 8: Privilege Violation */ + 25, /* 9: Trace */ + 20, /* 10: 1010 */ + 20, /* 11: 1111 */ + 4, /* 12: RESERVED */ + 4, /* 13: Coprocessor Protocol Violation (unemulated) */ + 4, /* 14: Format Error */ + 30, /* 15: Uninitialized Interrupt */ + 4, /* 16: RESERVED */ + 4, /* 17: RESERVED */ + 4, /* 18: RESERVED */ + 4, /* 19: RESERVED */ + 4, /* 20: RESERVED */ + 4, /* 21: RESERVED */ + 4, /* 22: RESERVED */ + 4, /* 23: RESERVED */ + 30, /* 24: Spurious Interrupt */ + 30, /* 25: Level 1 Interrupt Autovector */ + 30, /* 26: Level 2 Interrupt Autovector */ + 30, /* 27: Level 3 Interrupt Autovector */ + 30, /* 28: Level 4 Interrupt Autovector */ + 30, /* 29: Level 5 Interrupt Autovector */ + 30, /* 30: Level 6 Interrupt Autovector */ + 30, /* 31: Level 7 Interrupt Autovector */ + 20, /* 32: TRAP #0 */ + 20, /* 33: TRAP #1 */ + 20, /* 34: TRAP #2 */ + 20, /* 35: TRAP #3 */ + 20, /* 36: TRAP #4 */ + 20, /* 37: TRAP #5 */ + 20, /* 38: TRAP #6 */ + 20, /* 39: TRAP #7 */ + 20, /* 40: TRAP #8 */ + 20, /* 41: TRAP #9 */ + 20, /* 42: TRAP #10 */ + 20, /* 43: TRAP #11 */ + 20, /* 44: TRAP #12 */ + 20, /* 45: TRAP #13 */ + 20, /* 46: TRAP #14 */ + 20, /* 47: TRAP #15 */ + 4, /* 48: FP Branch or Set on Unknown Condition (unemulated) */ + 4, /* 49: FP Inexact Result (unemulated) */ + 4, /* 50: FP Divide by Zero (unemulated) */ + 4, /* 51: FP Underflow (unemulated) */ + 4, /* 52: FP Operand Error (unemulated) */ + 4, /* 53: FP Overflow (unemulated) */ + 4, /* 54: FP Signaling NAN (unemulated) */ + 4, /* 55: FP Unimplemented Data Type (unemulated) */ + 4, /* 56: MMU Configuration Error (unemulated) */ + 4, /* 57: MMU Illegal Operation Error (unemulated) */ + 4, /* 58: MMU Access Level Violation Error (unemulated) */ + 4, /* 59: RESERVED */ + 4, /* 60: RESERVED */ + 4, /* 61: RESERVED */ + 4, /* 62: RESERVED */ + 4, /* 63: RESERVED */ + /* 64-255: User Defined */ + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4, + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4, + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4, + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4, + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4, + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4 } }; -uint8 m68ki_ea_idx_cycle_table[64] = +const UINT8 m68ki_ea_idx_cycle_table[64] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* ..01.000 no memory indirect, base NULL */ @@ -355,299 +472,66 @@ uint8 m68ki_ea_idx_cycle_table[64] = -/* ======================================================================== */ -/* =============================== CALLBACKS ============================== */ -/* ======================================================================== */ - -/* Default callbacks used if the callback hasn't been set yet, or if the - * callback is set to NULL - */ - -/* Interrupt acknowledge */ -static int default_int_ack_callback_data; -static int default_int_ack_callback(int int_level) -{ - default_int_ack_callback_data = int_level; - CPU_INT_LEVEL = 0; - return M68K_INT_ACK_AUTOVECTOR; -} - -/* Breakpoint acknowledge */ -static unsigned int default_bkpt_ack_callback_data; -static void default_bkpt_ack_callback(unsigned int data) -{ - default_bkpt_ack_callback_data = data; -} - -/* Called when a reset instruction is executed */ -static void default_reset_instr_callback(void) -{ -} - -/* Called when the program counter changed by a large value */ -static unsigned int default_pc_changed_callback_data; -static void default_pc_changed_callback(unsigned int new_pc) -{ - default_pc_changed_callback_data = new_pc; -} - -/* Called every time there's bus activity (read/write to/from memory */ -static unsigned int default_set_fc_callback_data; -static void default_set_fc_callback(unsigned int new_fc) -{ - default_set_fc_callback_data = new_fc; -} - -/* Called every instruction cycle prior to execution */ -static void default_instr_hook_callback(void) -{ -} - - -#if M68K_EMULATE_ADDRESS_ERROR - #include - jmp_buf m68ki_aerr_trap; -#endif /* M68K_EMULATE_ADDRESS_ERROR */ - - /* ======================================================================== */ /* ================================= API ================================== */ /* ======================================================================== */ -/* Access the internals of the CPU */ -unsigned int m68k_get_reg(void* context, m68k_register_t regnum) +void m68k_set_irq(m68ki_cpu_core *m68k, int irqline, int state) { - m68ki_cpu_core* cpu = context != NULL ?(m68ki_cpu_core*)context : &m68ki_cpu; + UINT32 old_level = m68k->int_level; + UINT32 vstate = m68k->virq_state; + UINT32 blevel; - switch(regnum) - { - case M68K_REG_D0: return cpu->dar[0]; - case M68K_REG_D1: return cpu->dar[1]; - case M68K_REG_D2: return cpu->dar[2]; - case M68K_REG_D3: return cpu->dar[3]; - case M68K_REG_D4: return cpu->dar[4]; - case M68K_REG_D5: return cpu->dar[5]; - case M68K_REG_D6: return cpu->dar[6]; - case M68K_REG_D7: return cpu->dar[7]; - case M68K_REG_A0: return cpu->dar[8]; - case M68K_REG_A1: return cpu->dar[9]; - case M68K_REG_A2: return cpu->dar[10]; - case M68K_REG_A3: return cpu->dar[11]; - case M68K_REG_A4: return cpu->dar[12]; - case M68K_REG_A5: return cpu->dar[13]; - case M68K_REG_A6: return cpu->dar[14]; - case M68K_REG_A7: return cpu->dar[15]; - case M68K_REG_PC: return MASK_OUT_ABOVE_32(cpu->pc); - case M68K_REG_SR: return cpu->t1_flag | - cpu->t0_flag | - (cpu->s_flag << 11) | - (cpu->m_flag << 11) | - cpu->int_mask | - ((cpu->x_flag & XFLAG_SET) >> 4) | - ((cpu->n_flag & NFLAG_SET) >> 4) | - ((!cpu->not_z_flag) << 2) | - ((cpu->v_flag & VFLAG_SET) >> 6) | - ((cpu->c_flag & CFLAG_SET) >> 8); - case M68K_REG_SP: return cpu->dar[15]; - case M68K_REG_USP: return cpu->s_flag ? cpu->sp[0] : cpu->dar[15]; - case M68K_REG_ISP: return cpu->s_flag && !cpu->m_flag ? cpu->dar[15] : cpu->sp[4]; - case M68K_REG_MSP: return cpu->s_flag && cpu->m_flag ? cpu->dar[15] : cpu->sp[6]; - case M68K_REG_SFC: return cpu->sfc; - case M68K_REG_DFC: return cpu->dfc; - case M68K_REG_VBR: return cpu->vbr; - case M68K_REG_CACR: return cpu->cacr; - case M68K_REG_CAAR: return cpu->caar; - case M68K_REG_PREF_ADDR: return cpu->pref_addr; - case M68K_REG_PREF_DATA: return cpu->pref_data; - case M68K_REG_PPC: return MASK_OUT_ABOVE_32(cpu->ppc); - case M68K_REG_IR: return cpu->ir; - case M68K_REG_CPU_TYPE: - switch(cpu->cpu_type) - { - case CPU_TYPE_000: return (unsigned int)M68K_CPU_TYPE_68000; - case CPU_TYPE_010: return (unsigned int)M68K_CPU_TYPE_68010; - case CPU_TYPE_EC020: return (unsigned int)M68K_CPU_TYPE_68EC020; - case CPU_TYPE_020: return (unsigned int)M68K_CPU_TYPE_68020; - } - return M68K_CPU_TYPE_INVALID; - default: return 0; + if(state == ASSERT_LINE) + vstate |= 1 << irqline; + else + vstate &= ~(1 << irqline); + m68k->virq_state = vstate; + + for(blevel = 7; blevel > 0; blevel--) + if(vstate & (1 << blevel)) + break; + + m68k->int_level = blevel << 8; + + /* A transition from < 7 to 7 always interrupts (NMI) */ + /* Note: Level 7 can also level trigger like a normal IRQ */ + if(old_level != 0x0700 && m68k->int_level == 0x0700) + m68k->nmi_pending = TRUE; +} + +/* translate logical to physical addresses */ +static int m68k_translate( m68ki_cpu_core *m68k, unsigned int *address ) +{ + /* only applies to the program address space and only does something if the MMU's enabled */ + return TRUE; +} + +/* Execute some instructions until we use up cycles clock cycles */ +int m68k_execute(m68ki_cpu_core *m68k, unsigned int cycles) +{ + m68k->initial_cycles = cycles; + + /* eat up any reset cycles */ + if (m68k->reset_cycles) { + int rc = m68k->reset_cycles; + m68k->reset_cycles = 0; + cycles -= rc; + + if (cycles <= 0) return rc; } - return 0; -} -void m68k_set_reg(m68k_register_t regnum, unsigned int value) -{ - switch(regnum) - { - case M68K_REG_D0: REG_D[0] = MASK_OUT_ABOVE_32(value); return; - case M68K_REG_D1: REG_D[1] = MASK_OUT_ABOVE_32(value); return; - case M68K_REG_D2: REG_D[2] = MASK_OUT_ABOVE_32(value); return; - case M68K_REG_D3: REG_D[3] = MASK_OUT_ABOVE_32(value); return; - case M68K_REG_D4: REG_D[4] = MASK_OUT_ABOVE_32(value); return; - case M68K_REG_D5: REG_D[5] = MASK_OUT_ABOVE_32(value); return; - case M68K_REG_D6: REG_D[6] = MASK_OUT_ABOVE_32(value); return; - case M68K_REG_D7: REG_D[7] = MASK_OUT_ABOVE_32(value); return; - case M68K_REG_A0: REG_A[0] = MASK_OUT_ABOVE_32(value); return; - case M68K_REG_A1: REG_A[1] = MASK_OUT_ABOVE_32(value); return; - case M68K_REG_A2: REG_A[2] = MASK_OUT_ABOVE_32(value); return; - case M68K_REG_A3: REG_A[3] = MASK_OUT_ABOVE_32(value); return; - case M68K_REG_A4: REG_A[4] = MASK_OUT_ABOVE_32(value); return; - case M68K_REG_A5: REG_A[5] = MASK_OUT_ABOVE_32(value); return; - case M68K_REG_A6: REG_A[6] = MASK_OUT_ABOVE_32(value); return; - case M68K_REG_A7: REG_A[7] = MASK_OUT_ABOVE_32(value); return; - case M68K_REG_PC: m68ki_jump(MASK_OUT_ABOVE_32(value)); return; - case M68K_REG_SR: m68ki_set_sr(value); return; - case M68K_REG_SP: REG_SP = MASK_OUT_ABOVE_32(value); return; - case M68K_REG_USP: if(FLAG_S) - REG_USP = MASK_OUT_ABOVE_32(value); - else - REG_SP = MASK_OUT_ABOVE_32(value); - return; - case M68K_REG_ISP: if(FLAG_S && !FLAG_M) - REG_SP = MASK_OUT_ABOVE_32(value); - else - REG_ISP = MASK_OUT_ABOVE_32(value); - return; - case M68K_REG_MSP: if(FLAG_S && FLAG_M) - REG_SP = MASK_OUT_ABOVE_32(value); - else - REG_MSP = MASK_OUT_ABOVE_32(value); - return; - case M68K_REG_VBR: REG_VBR = MASK_OUT_ABOVE_32(value); return; - case M68K_REG_SFC: REG_SFC = value & 7; return; - case M68K_REG_DFC: REG_DFC = value & 7; return; - case M68K_REG_CACR: REG_CACR = MASK_OUT_ABOVE_32(value); return; - case M68K_REG_CAAR: REG_CAAR = MASK_OUT_ABOVE_32(value); return; - case M68K_REG_PPC: REG_PPC = MASK_OUT_ABOVE_32(value); return; - case M68K_REG_IR: REG_IR = MASK_OUT_ABOVE_16(value); return; - case M68K_REG_CPU_TYPE: m68k_set_cpu_type(value); return; - default: return; - } -} + /* Set our pool of clock cycles available */ + m68k->remaining_cycles = cycles; -/* Set the callbacks */ -void m68k_set_int_ack_callback(int (*callback)(int int_level)) -{ - CALLBACK_INT_ACK = callback ? callback : default_int_ack_callback; -} + /* See if interrupts came in */ + m68ki_check_interrupts(m68k); -void m68k_set_bkpt_ack_callback(void (*callback)(unsigned int data)) -{ - CALLBACK_BKPT_ACK = callback ? callback : default_bkpt_ack_callback; -} - -void m68k_set_reset_instr_callback(void (*callback)(void)) -{ - CALLBACK_RESET_INSTR = callback ? callback : default_reset_instr_callback; -} - -void m68k_set_pc_changed_callback(void (*callback)(unsigned int new_pc)) -{ - CALLBACK_PC_CHANGED = callback ? callback : default_pc_changed_callback; -} - -void m68k_set_fc_callback(void (*callback)(unsigned int new_fc)) -{ - CALLBACK_SET_FC = callback ? callback : default_set_fc_callback; -} - -void m68k_set_instr_hook_callback(void (*callback)(void)) -{ - CALLBACK_INSTR_HOOK = callback ? callback : default_instr_hook_callback; -} - -#include -/* Set the CPU type. */ -void m68k_set_cpu_type(unsigned int cpu_type) -{ - switch(cpu_type) - { - case M68K_CPU_TYPE_68000: - CPU_TYPE = CPU_TYPE_000; - CPU_ADDRESS_MASK = 0x00ffffff; - CPU_SR_MASK = 0xa71f; /* T1 -- S -- -- I2 I1 I0 -- -- -- X N Z V C */ - CYC_INSTRUCTION = m68ki_cycles[0]; - CYC_EXCEPTION = m68ki_exception_cycle_table[0]; - CYC_BCC_NOTAKE_B = -2; - CYC_BCC_NOTAKE_W = 2; - CYC_DBCC_F_NOEXP = -2; - CYC_DBCC_F_EXP = 2; - CYC_SCC_R_FALSE = 2; - CYC_MOVEM_W = 2; - CYC_MOVEM_L = 3; - CYC_SHIFT = 1; - CYC_RESET = 132; - return; - case M68K_CPU_TYPE_68010: - CPU_TYPE = CPU_TYPE_010; - CPU_ADDRESS_MASK = 0x00ffffff; - CPU_SR_MASK = 0xa71f; /* T1 -- S -- -- I2 I1 I0 -- -- -- X N Z V C */ - CYC_INSTRUCTION = m68ki_cycles[1]; - CYC_EXCEPTION = m68ki_exception_cycle_table[1]; - CYC_BCC_NOTAKE_B = -4; - CYC_BCC_NOTAKE_W = 0; - CYC_DBCC_F_NOEXP = 0; - CYC_DBCC_F_EXP = 6; - CYC_SCC_R_FALSE = 0; - CYC_MOVEM_W = 2; - CYC_MOVEM_L = 3; - CYC_SHIFT = 1; - CYC_RESET = 130; - return; - case M68K_CPU_TYPE_68EC020: - CPU_TYPE = CPU_TYPE_EC020; - CPU_ADDRESS_MASK = 0x00ffffff; - CPU_SR_MASK = 0xf71f; /* T1 T0 S M -- I2 I1 I0 -- -- -- X N Z V C */ - CYC_INSTRUCTION = m68ki_cycles[2]; - CYC_EXCEPTION = m68ki_exception_cycle_table[2]; - CYC_BCC_NOTAKE_B = -2; - CYC_BCC_NOTAKE_W = 0; - CYC_DBCC_F_NOEXP = 0; - CYC_DBCC_F_EXP = 4; - CYC_SCC_R_FALSE = 0; - CYC_MOVEM_W = 2; - CYC_MOVEM_L = 2; - CYC_SHIFT = 0; - CYC_RESET = 518; - return; - case M68K_CPU_TYPE_68020: - CPU_TYPE = CPU_TYPE_020; - CPU_ADDRESS_MASK = 0xffffffff; - CPU_SR_MASK = 0xf71f; /* T1 T0 S M -- I2 I1 I0 -- -- -- X N Z V C */ - CYC_INSTRUCTION = m68ki_cycles[2]; - CYC_EXCEPTION = m68ki_exception_cycle_table[2]; - CYC_BCC_NOTAKE_B = -2; - CYC_BCC_NOTAKE_W = 0; - CYC_DBCC_F_NOEXP = 0; - CYC_DBCC_F_EXP = 4; - CYC_SCC_R_FALSE = 0; - CYC_MOVEM_W = 2; - CYC_MOVEM_L = 2; - CYC_SHIFT = 0; - CYC_RESET = 518; - return; - } -} - -int m68k_trap0; - -/* Execute some instructions until we use up num_cycles clock cycles */ -/* ASG: removed per-instruction interrupt checks */ -int m68k_execute(int num_cycles) -{ /* Make sure we're not stopped */ - if(!CPU_STOPPED) + if(!m68k->stopped) { - /* Set our pool of clock cycles available */ - SET_CYCLES(num_cycles); - m68ki_initial_cycles = num_cycles; - - /* ASG: update cycles */ - USE_CYCLES(CPU_INT_CYCLES); - CPU_INT_CYCLES = 0; - /* Return point if we had an address error */ - m68ki_set_address_error_trap(); /* auto-disable (see m68kcpu.h) */ + m68ki_set_address_error_trap(m68k); /* auto-disable (see m68kcpu.h) */ /* Main loop. Keep going until we run out of clock cycles */ do @@ -655,225 +539,103 @@ int m68k_execute(int num_cycles) /* Set tracing accodring to T1. (T0 is done inside instruction) */ m68ki_trace_t1(); /* auto-disable (see m68kcpu.h) */ - /* Set the address space for reads */ - m68ki_use_data_space(); /* auto-disable (see m68kcpu.h) */ - - /* Call external hook to peek at CPU */ - m68ki_instr_hook(); /* auto-disable (see m68kcpu.h) */ - -// if (REG_PC == m68k_trap0) printf("at trap0 (crash), prev_pc = %x\n", REG_PPC); - /* Record previous program counter */ REG_PPC = REG_PC; /* Read an instruction and call its handler */ - REG_IR = m68ki_read_imm_16(); - m68ki_instruction_jump_table[REG_IR](); - USE_CYCLES(CYC_INSTRUCTION[REG_IR]); + m68k->ir = m68ki_read_imm_16(m68k); + m68ki_instruction_jump_table[m68k->ir](m68k); + m68k->remaining_cycles -= m68k->cyc_instruction[m68k->ir]; /* Trace m68k_exception, if necessary */ m68ki_exception_if_trace(); /* auto-disable (see m68kcpu.h) */ - } while(GET_CYCLES() > 0); + } while (m68k->remaining_cycles > 0); /* set previous PC to current PC for the next entry into the loop */ REG_PPC = REG_PC; - - /* ASG: update cycles */ - USE_CYCLES(CPU_INT_CYCLES); - CPU_INT_CYCLES = 0; - - /* return how many clocks we used */ - return m68ki_initial_cycles - GET_CYCLES(); } + else if (m68k->remaining_cycles > 0) + m68k->remaining_cycles = 0; - /* We get here if the CPU is stopped or halted */ - SET_CYCLES(0); - CPU_INT_CYCLES = 0; - - return num_cycles; + /* return how many clocks we used */ + return m68k->initial_cycles - m68k->remaining_cycles; } - -int m68k_cycles_run(void) +static void m68k_init_internal(m68ki_cpu_core *m68k) { - return m68ki_initial_cycles - GET_CYCLES(); -} - -int m68k_cycles_remaining(void) -{ - return GET_CYCLES(); -} - -/* Change the timeslice */ -void m68k_modify_timeslice(int cycles) -{ - m68ki_initial_cycles += cycles; - ADD_CYCLES(cycles); -} - - -void m68k_end_timeslice(void) -{ - m68ki_initial_cycles = GET_CYCLES(); - SET_CYCLES(0); -} - - -/* ASG: rewrote so that the int_level is a mask of the IPL0/IPL1/IPL2 bits */ -/* KS: Modified so that IPL* bits match with mask positions in the SR - * and cleaned out remenants of the interrupt controller. - */ -void m68k_set_irq(unsigned int int_level) -{ - uint old_level = CPU_INT_LEVEL; - CPU_INT_LEVEL = int_level << 8; - - /* A transition from < 7 to 7 always interrupts (NMI) */ - /* Note: Level 7 can also level trigger like a normal IRQ */ - if(old_level != 0x0700 && CPU_INT_LEVEL == 0x0700) - m68ki_exception_interrupt(7); /* Edge triggered level 7 (NMI) */ - else - m68ki_check_interrupts(); /* Level triggered (IRQ) */ -} - -void m68k_init(void) -{ - static uint emulation_initialized = 0; + static UINT32 emulation_initialized = 0; /* The first call to this function initializes the opcode handler jump table */ if(!emulation_initialized) - { + { m68ki_build_opcode_table(); emulation_initialized = 1; } - - m68k_set_int_ack_callback(NULL); - m68k_set_bkpt_ack_callback(NULL); - m68k_set_reset_instr_callback(NULL); - m68k_set_pc_changed_callback(NULL); - m68k_set_fc_callback(NULL); - m68k_set_instr_hook_callback(NULL); } /* Pulse the RESET line on the CPU */ -void m68k_pulse_reset(void) +void m68k_pulse_reset(m68ki_cpu_core *m68k) { /* Clear all stop levels and eat up all remaining cycles */ - CPU_STOPPED = 0; - SET_CYCLES(0); + m68k->stopped = 0; + if (m68k->remaining_cycles > 0) + m68k->remaining_cycles = 0; - CPU_RUN_MODE = RUN_MODE_BERR_AERR_RESET; +#if M68K_EMULATE_ADDRESS_ERROR + m68k->run_mode = RUN_MODE_BERR_AERR_RESET; +#endif /* Turn off tracing */ - FLAG_T1 = FLAG_T0 = 0; + m68k->t1_flag = m68k->t0_flag = 0; m68ki_clear_trace(); /* Interrupt mask to level 7 */ - FLAG_INT_MASK = 0x0700; + m68k->int_mask = 0x0700; + m68k->int_level = 0; + m68k->virq_state = 0; /* Reset VBR */ - REG_VBR = 0; + m68k->vbr = 0; /* Go to supervisor mode */ - m68ki_set_sm_flag(SFLAG_SET | MFLAG_CLEAR); + m68ki_set_sm_flag(m68k, SFLAG_SET | MFLAG_CLEAR); /* Invalidate the prefetch queue */ -#if M68K_EMULATE_PREFETCH /* Set to arbitrary number since our first fetch is from 0 */ - CPU_PREF_ADDR = 0x1000; -#endif /* M68K_EMULATE_PREFETCH */ +#if M68K_EMULATE_PREFETCH + m68k->pref_addr = 0x1000; +#endif /* Read the initial stack pointer and program counter */ - m68ki_jump(0); - REG_SP = m68ki_read_imm_32(); - REG_PC = m68ki_read_imm_32(); - m68ki_jump(REG_PC); + m68ki_jump(m68k, 0); + REG_SP = m68ki_read_imm_32(m68k); + REG_PC = m68ki_read_imm_32(m68k); + m68ki_jump(m68k, REG_PC); - CPU_RUN_MODE = RUN_MODE_NORMAL; +#if M68K_EMULATE_ADDRESS_ERROR + m68k->run_mode = RUN_MODE_NORMAL; +#endif + + m68k->reset_cycles = m68k->cyc_exception[EXCEPTION_RESET]; } -/* Pulse the HALT line on the CPU */ -void m68k_pulse_halt(void) + + +/**************************************************************************** + * 68000 section + ****************************************************************************/ + +void m68k_init(m68ki_cpu_core *m68k) { - CPU_STOPPED |= STOP_LEVEL_HALT; + m68k_init_internal(m68k); + + m68k->sr_mask = 0xa71f; /* T1 -- S -- -- I2 I1 I0 -- -- -- X N Z V C */ + m68k->cyc_instruction = m68ki_cycles[0]; + m68k->cyc_exception = m68ki_exception_cycle_table[0]; + m68k->cyc_bcc_notake_b = -2; + m68k->cyc_bcc_notake_w = 2; + m68k->cyc_dbcc_f_noexp = -2; + m68k->cyc_dbcc_f_exp = 2; + m68k->cyc_scc_r_true = 2; + m68k->cyc_movem_w = 2; + m68k->cyc_movem_l = 3; + m68k->cyc_shift = 1; + m68k->cyc_reset = 132; } - - -/* Get and set the current CPU context */ -/* This is to allow for multiple CPUs */ -unsigned int m68k_context_size() -{ - return sizeof(m68ki_cpu_core); -} - -unsigned int m68k_get_context(void* dst) -{ - if(dst) *(m68ki_cpu_core*)dst = m68ki_cpu; - return sizeof(m68ki_cpu_core); -} - -void m68k_set_context(void* src) -{ - if(src) m68ki_cpu = *(m68ki_cpu_core*)src; -} - - - -/* ======================================================================== */ -/* ============================== MAME STUFF ============================== */ -/* ======================================================================== */ - -#if M68K_COMPILE_FOR_MAME == OPT_ON - -#include "state.h" - -static struct { - UINT16 sr; - int stopped; - int halted; -} m68k_substate; - -static void m68k_prepare_substate(void) -{ - m68k_substate.sr = m68ki_get_sr(); - m68k_substate.stopped = (CPU_STOPPED & STOP_LEVEL_STOP) != 0; - m68k_substate.halted = (CPU_STOPPED & STOP_LEVEL_HALT) != 0; -} - -static void m68k_post_load(void) -{ - m68ki_set_sr_noint_nosp(m68k_substate.sr); - CPU_STOPPED = m68k_substate.stopped ? STOP_LEVEL_STOP : 0 - | m68k_substate.halted ? STOP_LEVEL_HALT : 0; - m68ki_jump(REG_PC); -} - -void m68k_state_register(const char *type) -{ - int cpu = cpu_getactivecpu(); - - state_save_register_UINT32(type, cpu, "D" , REG_D, 8); - state_save_register_UINT32(type, cpu, "A" , REG_A, 8); - state_save_register_UINT32(type, cpu, "PPC" , ®_PPC, 1); - state_save_register_UINT32(type, cpu, "PC" , ®_PC, 1); - state_save_register_UINT32(type, cpu, "USP" , ®_USP, 1); - state_save_register_UINT32(type, cpu, "ISP" , ®_ISP, 1); - state_save_register_UINT32(type, cpu, "MSP" , ®_MSP, 1); - state_save_register_UINT32(type, cpu, "VBR" , ®_VBR, 1); - state_save_register_UINT32(type, cpu, "SFC" , ®_SFC, 1); - state_save_register_UINT32(type, cpu, "DFC" , ®_DFC, 1); - state_save_register_UINT32(type, cpu, "CACR" , ®_CACR, 1); - state_save_register_UINT32(type, cpu, "CAAR" , ®_CAAR, 1); - state_save_register_UINT16(type, cpu, "SR" , &m68k_substate.sr, 1); - state_save_register_UINT32(type, cpu, "INT_LEVEL" , &CPU_INT_LEVEL, 1); - state_save_register_UINT32(type, cpu, "INT_CYCLES", &CPU_INT_CYCLES, 1); - state_save_register_int (type, cpu, "STOPPED" , &m68k_substate.stopped); - state_save_register_int (type, cpu, "HALTED" , &m68k_substate.halted); - state_save_register_UINT32(type, cpu, "PREF_ADDR" , &CPU_PREF_ADDR, 1); - state_save_register_UINT32(type, cpu, "PREF_DATA" , &CPU_PREF_DATA, 1); - state_save_register_func_presave(m68k_prepare_substate); - state_save_register_func_postload(m68k_post_load); -} - -#endif /* M68K_COMPILE_FOR_MAME */ - -/* ======================================================================== */ -/* ============================== END OF FILE ============================= */ -/* ======================================================================== */ diff --git a/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/m68k/m68kcpu.h b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/m68k/m68kcpu.h new file mode 100644 index 000000000..5ab72afe1 --- /dev/null +++ b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/m68k/m68kcpu.h @@ -0,0 +1,1697 @@ +/* ======================================================================== */ +/* ========================= LICENSING & COPYRIGHT ======================== */ +/* ======================================================================== */ +/* + * MUSASHI + * Version 4.50 + * + * A portable Motorola M680x0 processor emulation engine. + * Copyright Karl Stenerud. All rights reserved. + * + * This code may be freely used for non-commercial purposes as long as this + * copyright notice remains unaltered in the source code and any binary files + * containing this code in compiled form. + * + * All other licensing terms must be negotiated with the author + * (Karl Stenerud). + * + * The latest version of this code can be obtained at: + * http://kstenerud.cjb.net + */ + + +#pragma once + +#ifndef __M68KCPU_H__ +#define __M68KCPU_H__ + +#include "m68k.h" + +#include +#include +#include +#define UINT8 uint8_t +#define UINT16 uint16_t +#define UINT32 uint32_t +#define UINT64 uint64_t +#define INT8 int8_t +#define INT16 int16_t +#define INT32 int32_t +#define INT64 int64_t + +#define U64 (uint64_t) + +/* ======================================================================== */ +/* ==================== ARCHITECTURE-DEPENDANT DEFINES ==================== */ +/* ======================================================================== */ + +/* Check for > 32bit sizes */ +#define MAKE_INT_8(A) (INT8)(A) +#define MAKE_INT_16(A) (INT16)(A) +#define MAKE_INT_32(A) (INT32)(A) + + +/* ======================================================================== */ +/* ============================ GENERAL DEFINES =========================== */ +/* ======================================================================== */ + +/* Exception Vectors handled by emulation */ +#define EXCEPTION_RESET 0 +#define EXCEPTION_BUS_ERROR 2 /* This one is not emulated! */ +#define EXCEPTION_ADDRESS_ERROR 3 /* This one is partially emulated (doesn't stack a proper frame yet) */ +#define EXCEPTION_ILLEGAL_INSTRUCTION 4 +#define EXCEPTION_ZERO_DIVIDE 5 +#define EXCEPTION_CHK 6 +#define EXCEPTION_TRAPV 7 +#define EXCEPTION_PRIVILEGE_VIOLATION 8 +#define EXCEPTION_TRACE 9 +#define EXCEPTION_1010 10 +#define EXCEPTION_1111 11 +#define EXCEPTION_FORMAT_ERROR 14 +#define EXCEPTION_UNINITIALIZED_INTERRUPT 15 +#define EXCEPTION_SPURIOUS_INTERRUPT 24 +#define EXCEPTION_INTERRUPT_AUTOVECTOR 24 +#define EXCEPTION_TRAP_BASE 32 + +/* Function codes set by CPU during data/address bus activity */ +#define FUNCTION_CODE_USER_DATA 1 +#define FUNCTION_CODE_USER_PROGRAM 2 +#define FUNCTION_CODE_SUPERVISOR_DATA 5 +#define FUNCTION_CODE_SUPERVISOR_PROGRAM 6 +#define FUNCTION_CODE_CPU_SPACE 7 + +/* CPU types for deciding what to emulate */ +#define CPU_TYPE_000 (0x00000001) +#define CPU_TYPE_008 (0x00000002) +#define CPU_TYPE_010 (0x00000004) +#define CPU_TYPE_EC020 (0x00000008) +#define CPU_TYPE_020 (0x00000010) +#define CPU_TYPE_EC030 (0x00000020) +#define CPU_TYPE_030 (0x00000040) +#define CPU_TYPE_EC040 (0x00000080) +#define CPU_TYPE_LC040 (0x00000100) +#define CPU_TYPE_040 (0x00000200) +#define CPU_TYPE_SCC070 (0x00000400) + +/* Different ways to stop the CPU */ +#define STOP_LEVEL_STOP 1 +#define STOP_LEVEL_HALT 2 + +/* Used for 68000 address error processing */ +#define INSTRUCTION_YES 0 +#define INSTRUCTION_NO 0x08 +#define MODE_READ 0x10 +#define MODE_WRITE 0 + +#define RUN_MODE_NORMAL 0 +#define RUN_MODE_BERR_AERR_RESET 1 + + +/* ======================================================================== */ +/* ================================ MACROS ================================ */ +/* ======================================================================== */ + + +/* ---------------------------- General Macros ---------------------------- */ + +/* Bit Isolation Macros */ +#define BIT_0(A) ((A) & 0x00000001) +#define BIT_1(A) ((A) & 0x00000002) +#define BIT_2(A) ((A) & 0x00000004) +#define BIT_3(A) ((A) & 0x00000008) +#define BIT_4(A) ((A) & 0x00000010) +#define BIT_5(A) ((A) & 0x00000020) +#define BIT_6(A) ((A) & 0x00000040) +#define BIT_7(A) ((A) & 0x00000080) +#define BIT_8(A) ((A) & 0x00000100) +#define BIT_9(A) ((A) & 0x00000200) +#define BIT_A(A) ((A) & 0x00000400) +#define BIT_B(A) ((A) & 0x00000800) +#define BIT_C(A) ((A) & 0x00001000) +#define BIT_D(A) ((A) & 0x00002000) +#define BIT_E(A) ((A) & 0x00004000) +#define BIT_F(A) ((A) & 0x00008000) +#define BIT_10(A) ((A) & 0x00010000) +#define BIT_11(A) ((A) & 0x00020000) +#define BIT_12(A) ((A) & 0x00040000) +#define BIT_13(A) ((A) & 0x00080000) +#define BIT_14(A) ((A) & 0x00100000) +#define BIT_15(A) ((A) & 0x00200000) +#define BIT_16(A) ((A) & 0x00400000) +#define BIT_17(A) ((A) & 0x00800000) +#define BIT_18(A) ((A) & 0x01000000) +#define BIT_19(A) ((A) & 0x02000000) +#define BIT_1A(A) ((A) & 0x04000000) +#define BIT_1B(A) ((A) & 0x08000000) +#define BIT_1C(A) ((A) & 0x10000000) +#define BIT_1D(A) ((A) & 0x20000000) +#define BIT_1E(A) ((A) & 0x40000000) +#define BIT_1F(A) ((A) & 0x80000000) + +/* Get the most significant bit for specific sizes */ +#define GET_MSB_8(A) ((A) & 0x80) +#define GET_MSB_9(A) ((A) & 0x100) +#define GET_MSB_16(A) ((A) & 0x8000) +#define GET_MSB_17(A) ((A) & 0x10000) +#define GET_MSB_32(A) ((A) & 0x80000000) +#define GET_MSB_33(A) ((A) & U64(0x100000000)) + +/* Isolate nibbles */ +#define LOW_NIBBLE(A) ((A) & 0x0f) +#define HIGH_NIBBLE(A) ((A) & 0xf0) + +/* These are used to isolate 8, 16, and 32 bit sizes */ +#define MASK_OUT_ABOVE_2(A) ((A) & 3) +#define MASK_OUT_ABOVE_8(A) ((A) & 0xff) +#define MASK_OUT_ABOVE_16(A) ((A) & 0xffff) +#define MASK_OUT_BELOW_2(A) ((A) & ~3) +#define MASK_OUT_BELOW_8(A) ((A) & ~0xff) +#define MASK_OUT_BELOW_16(A) ((A) & ~0xffff) + +/* No need to mask if we are 32 bit */ +#define MASK_OUT_ABOVE_32(A) ((A) & U64(0xffffffff)) +#define MASK_OUT_BELOW_32(A) ((A) & ~U64(0xffffffff)) + +/* Shift & Rotate Macros. */ +#define LSL(A, C) ((A) << (C)) +#define LSR(A, C) ((A) >> (C)) + +/* We have to do this because the morons at ANSI decided that shifts +* by >= data size are undefined. +*/ +#define LSR_32(A, C) ((C) < 32 ? (A) >> (C) : 0) +#define LSL_32(A, C) ((C) < 32 ? (A) << (C) : 0) + +#define LSL_32_64(A, C) ((A) << (C)) +#define LSR_32_64(A, C) ((A) >> (C)) +#define ROL_33_64(A, C) (LSL_32_64(A, C) | LSR_32_64(A, 33-(C))) +#define ROR_33_64(A, C) (LSR_32_64(A, C) | LSL_32_64(A, 33-(C))) + +#define ROL_8(A, C) MASK_OUT_ABOVE_8(LSL(A, C) | LSR(A, 8-(C))) +#define ROL_9(A, C) (LSL(A, C) | LSR(A, 9-(C))) +#define ROL_16(A, C) MASK_OUT_ABOVE_16(LSL(A, C) | LSR(A, 16-(C))) +#define ROL_17(A, C) (LSL(A, C) | LSR(A, 17-(C))) +#define ROL_32(A, C) MASK_OUT_ABOVE_32(LSL_32(A, C) | LSR_32(A, 32-(C))) +#define ROL_33(A, C) (LSL_32(A, C) | LSR_32(A, 33-(C))) + +#define ROR_8(A, C) MASK_OUT_ABOVE_8(LSR(A, C) | LSL(A, 8-(C))) +#define ROR_9(A, C) (LSR(A, C) | LSL(A, 9-(C))) +#define ROR_16(A, C) MASK_OUT_ABOVE_16(LSR(A, C) | LSL(A, 16-(C))) +#define ROR_17(A, C) (LSR(A, C) | LSL(A, 17-(C))) +#define ROR_32(A, C) MASK_OUT_ABOVE_32(LSR_32(A, C) | LSL_32(A, 32-(C))) +#define ROR_33(A, C) (LSR_32(A, C) | LSL_32(A, 33-(C))) + + + +/* ------------------------------ CPU Access ------------------------------ */ + +/* Access the CPU registers */ +#define REG_DA m68k->dar /* easy access to data and address regs */ +#define REG_D m68k->dar +#define REG_A (m68k->dar+8) +#define REG_PPC m68k->ppc +#define REG_PC m68k->pc +#define REG_SP_BASE m68k->sp +#define REG_USP m68k->sp[0] +#define REG_ISP m68k->sp[4] +#define REG_MSP m68k->sp[6] +#define REG_SP m68k->dar[15] + +#define REG_FP m68k->fpr +#define REG_FPCR m68k->fpcr +#define REG_FPSR m68k->fpsr +#define REG_FPIAR m68k->fpiar + +#define FLAG_T1 m68k->t1_flag +#define FLAG_S m68k->s_flag +#define FLAG_X m68k->x_flag +#define FLAG_N m68k->n_flag +#define FLAG_Z m68k->not_z_flag +#define FLAG_V m68k->v_flag +#define FLAG_C m68k->c_flag +#define FLAG_INT_MASK m68k->int_mask + + +/* ----------------------------- Configuration ---------------------------- */ + +/* These defines are dependant on the configuration defines in m68kconf.h */ + +/* Disable certain comparisons if we're not using all CPU types */ +#if 1 +#define CPU_TYPE_IS_040_PLUS(A) 0 +#define CPU_TYPE_IS_040_LESS(A) 1 + +#define CPU_TYPE_IS_030_PLUS(A) 0 +#define CPU_TYPE_IS_030_LESS(A) 1 + +#define CPU_TYPE_IS_020_PLUS(A) 0 +#define CPU_TYPE_IS_020_LESS(A) 1 + +#define CPU_TYPE_IS_020_VARIANT(A) 0 + +#define CPU_TYPE_IS_EC020_PLUS(A) 0 +#define CPU_TYPE_IS_EC020_LESS(A) 1 + +#define CPU_TYPE_IS_010(A) 0 +#define CPU_TYPE_IS_010_PLUS(A) 0 +#define CPU_TYPE_IS_010_LESS(A) 1 + +#define CPU_TYPE_IS_000(A) 1 +#else +#define CPU_TYPE_IS_040_PLUS(A) ((A) & (CPU_TYPE_040 | CPU_TYPE_EC040)) +#define CPU_TYPE_IS_040_LESS(A) 1 + +#define CPU_TYPE_IS_030_PLUS(A) ((A) & (CPU_TYPE_030 | CPU_TYPE_EC030 | CPU_TYPE_040 | CPU_TYPE_EC040)) +#define CPU_TYPE_IS_030_LESS(A) 1 + +#define CPU_TYPE_IS_020_PLUS(A) ((A) & (CPU_TYPE_020 | CPU_TYPE_030 | CPU_TYPE_EC030 | CPU_TYPE_040 | CPU_TYPE_EC040)) +#define CPU_TYPE_IS_020_LESS(A) 1 + +#define CPU_TYPE_IS_020_VARIANT(A) ((A) & (CPU_TYPE_EC020 | CPU_TYPE_020)) + +#define CPU_TYPE_IS_EC020_PLUS(A) ((A) & (CPU_TYPE_EC020 | CPU_TYPE_020 | CPU_TYPE_030 | CPU_TYPE_EC030 | CPU_TYPE_040 | CPU_TYPE_EC040)) +#define CPU_TYPE_IS_EC020_LESS(A) ((A) & (CPU_TYPE_000 | CPU_TYPE_008 | CPU_TYPE_010 | CPU_TYPE_EC020)) + +#define CPU_TYPE_IS_010(A) ((A) == CPU_TYPE_010) +#define CPU_TYPE_IS_010_PLUS(A) ((A) & (CPU_TYPE_010 | CPU_TYPE_EC020 | CPU_TYPE_020 | CPU_TYPE_EC030 | CPU_TYPE_030 | CPU_TYPE_040 | CPU_TYPE_EC040)) +#define CPU_TYPE_IS_010_LESS(A) ((A) & (CPU_TYPE_000 | CPU_TYPE_008 | CPU_TYPE_010)) + +#define CPU_TYPE_IS_000(A) ((A) == CPU_TYPE_000 || (A) == CPU_TYPE_008) +#endif + + +/* Configuration switches (see m68kconf.h for explanation) */ +#define M68K_EMULATE_TRACE 0 + +/* Enable or disable trace emulation */ +#if M68K_EMULATE_TRACE + /* Initiates trace checking before each instruction (t1) */ + #define m68ki_trace_t1() m68ki_tracing = m68k->t1_flag + /* adds t0 to trace checking if we encounter change of flow */ + #define m68ki_trace_t0() m68ki_tracing |= m68k->t0_flag + /* Clear all tracing */ + #define m68ki_clear_trace() m68ki_tracing = 0 + /* Cause a trace exception if we are tracing */ + #define m68ki_exception_if_trace() if(m68ki_tracing) m68ki_exception_trace(m68k) +#else + #define m68ki_trace_t1() + #define m68ki_trace_t0() + #define m68ki_clear_trace() + #define m68ki_exception_if_trace() +#endif /* M68K_EMULATE_TRACE */ + + + +/* Address error */ +/* sigjmp() on Mac OS X and *BSD in general saves signal contexts and is super-slow, use sigsetjmp() to tell it not to */ +#if M68K_EMULATE_ADDRESS_ERROR +#ifdef _BSD_SETJMP_H +#define m68ki_set_address_error_trap(m68k) \ + if(sigsetjmp(m68k->aerr_trap, 0) != 0) \ + { \ + m68ki_exception_address_error(m68k); \ + if(m68k->stopped) \ + { \ + if (m68k->remaining_cycles > 0) \ + m68k->remaining_cycles = 0; \ + return m68k->initial_cycles; \ + } \ + } + +#define m68ki_check_address_error(m68k, ADDR, WRITE_MODE, FC) \ + if((ADDR)&1) \ + { \ + m68k->aerr_address = ADDR; \ + m68k->aerr_write_mode = WRITE_MODE; \ + m68k->aerr_fc = FC; \ + siglongjmp(m68k->aerr_trap, 1); \ + } +#else +#define m68ki_set_address_error_trap(m68k) \ + if(setjmp(m68k->aerr_trap) != 0) \ + { \ + m68ki_exception_address_error(m68k); \ + if(m68k->stopped) \ + { \ + if (m68k->remaining_cycles > 0) \ + m68k->remaining_cycles = 0; \ + return m68k->initial_cycles; \ + } \ + } + +#define m68ki_check_address_error(m68k, ADDR, WRITE_MODE, FC) \ + if((ADDR)&1) \ + { \ + m68k->aerr_address = ADDR; \ + m68k->aerr_write_mode = WRITE_MODE; \ + m68k->aerr_fc = FC; \ + longjmp(m68k->aerr_trap, 1); \ + } +#endif +#else +#define m68ki_set_address_error_trap(m68k) +#define m68ki_check_address_error(m68k, ADDR, WRITE_MODE, FC) +#endif + + +/* -------------------------- EA / Operand Access ------------------------- */ + +/* + * The general instruction format follows this pattern: + * .... XXX. .... .YYY + * where XXX is register X and YYY is register Y + */ +/* Data Register Isolation */ +#define DX (REG_D[(m68k->ir >> 9) & 7]) +#define DY (REG_D[m68k->ir & 7]) +/* Address Register Isolation */ +#define AX (REG_A[(m68k->ir >> 9) & 7]) +#define AY (REG_A[m68k->ir & 7]) + + +/* Effective Address Calculations */ +#define EA_AY_AI_8(m68k) AY /* address register indirect */ +#define EA_AY_AI_16(m68k) EA_AY_AI_8(m68k) +#define EA_AY_AI_32(m68k) EA_AY_AI_8(m68k) +#define EA_AY_PI_8(m68k) (AY++) /* postincrement (size = byte) */ +#define EA_AY_PI_16(m68k) ((AY+=2)-2) /* postincrement (size = word) */ +#define EA_AY_PI_32(m68k) ((AY+=4)-4) /* postincrement (size = long) */ +#define EA_AY_PD_8(m68k) (--AY) /* predecrement (size = byte) */ +#define EA_AY_PD_16(m68k) (AY-=2) /* predecrement (size = word) */ +#define EA_AY_PD_32(m68k) (AY-=4) /* predecrement (size = long) */ +#define EA_AY_DI_8(m68k) (AY+MAKE_INT_16(m68ki_read_imm_16(m68k))) /* displacement */ +#define EA_AY_DI_16(m68k) EA_AY_DI_8(m68k) +#define EA_AY_DI_32(m68k) EA_AY_DI_8(m68k) +#define EA_AY_IX_8(m68k) m68ki_get_ea_ix(m68k, AY) /* indirect + index */ +#define EA_AY_IX_16(m68k) EA_AY_IX_8(m68k) +#define EA_AY_IX_32(m68k) EA_AY_IX_8(m68k) + +#define EA_AX_AI_8(m68k) AX +#define EA_AX_AI_16(m68k) EA_AX_AI_8(m68k) +#define EA_AX_AI_32(m68k) EA_AX_AI_8(m68k) +#define EA_AX_PI_8(m68k) (AX++) +#define EA_AX_PI_16(m68k) ((AX+=2)-2) +#define EA_AX_PI_32(m68k) ((AX+=4)-4) +#define EA_AX_PD_8(m68k) (--AX) +#define EA_AX_PD_16(m68k) (AX-=2) +#define EA_AX_PD_32(m68k) (AX-=4) +#define EA_AX_DI_8(m68k) (AX+MAKE_INT_16(m68ki_read_imm_16(m68k))) +#define EA_AX_DI_16(m68k) EA_AX_DI_8(m68k) +#define EA_AX_DI_32(m68k) EA_AX_DI_8(m68k) +#define EA_AX_IX_8(m68k) m68ki_get_ea_ix(m68k, AX) +#define EA_AX_IX_16(m68k) EA_AX_IX_8(m68k) +#define EA_AX_IX_32(m68k) EA_AX_IX_8(m68k) + +#define EA_A7_PI_8(m68k) ((REG_A[7]+=2)-2) +#define EA_A7_PD_8(m68k) (REG_A[7]-=2) + +#define EA_AW_8(m68k) MAKE_INT_16(m68ki_read_imm_16(m68k)) /* absolute word */ +#define EA_AW_16(m68k) EA_AW_8(m68k) +#define EA_AW_32(m68k) EA_AW_8(m68k) +#define EA_AL_8(m68k) m68ki_read_imm_32(m68k) /* absolute long */ +#define EA_AL_16(m68k) EA_AL_8(m68k) +#define EA_AL_32(m68k) EA_AL_8(m68k) +#define EA_PCDI_8(m68k) m68ki_get_ea_pcdi(m68k) /* pc indirect + displacement */ +#define EA_PCDI_16(m68k) EA_PCDI_8(m68k) +#define EA_PCDI_32(m68k) EA_PCDI_8(m68k) +#define EA_PCIX_8(m68k) m68ki_get_ea_pcix(m68k) /* pc indirect + index */ +#define EA_PCIX_16(m68k) EA_PCIX_8(m68k) +#define EA_PCIX_32(m68k) EA_PCIX_8(m68k) + + +#define OPER_I_8(m68k) m68ki_read_imm_8(m68k) +#define OPER_I_16(m68k) m68ki_read_imm_16(m68k) +#define OPER_I_32(m68k) m68ki_read_imm_32(m68k) + + + +/* --------------------------- Status Register ---------------------------- */ + +/* Flag Calculation Macros */ +#define CFLAG_8(A) (A) +#define CFLAG_16(A) ((A)>>8) + +#define CFLAG_ADD_32(S, D, R) (((S & D) | (~R & (S | D)))>>23) +#define CFLAG_SUB_32(S, D, R) (((S & R) | (~D & (S | R)))>>23) + +#define VFLAG_ADD_8(S, D, R) ((S^R) & (D^R)) +#define VFLAG_ADD_16(S, D, R) (((S^R) & (D^R))>>8) +#define VFLAG_ADD_32(S, D, R) (((S^R) & (D^R))>>24) + +#define VFLAG_SUB_8(S, D, R) ((S^D) & (R^D)) +#define VFLAG_SUB_16(S, D, R) (((S^D) & (R^D))>>8) +#define VFLAG_SUB_32(S, D, R) (((S^D) & (R^D))>>24) + +#define NFLAG_8(A) (A) +#define NFLAG_16(A) ((A)>>8) +#define NFLAG_32(A) ((A)>>24) +#define NFLAG_64(A) ((A)>>56) + +#define ZFLAG_8(A) MASK_OUT_ABOVE_8(A) +#define ZFLAG_16(A) MASK_OUT_ABOVE_16(A) +#define ZFLAG_32(A) MASK_OUT_ABOVE_32(A) + + +/* Flag values */ +#define NFLAG_SET 0x80 +#define NFLAG_CLEAR 0 +#define CFLAG_SET 0x100 +#define CFLAG_CLEAR 0 +#define XFLAG_SET 0x100 +#define XFLAG_CLEAR 0 +#define VFLAG_SET 0x80 +#define VFLAG_CLEAR 0 +#define ZFLAG_SET 0 +#define ZFLAG_CLEAR 0xffffffff + +#define SFLAG_SET 4 +#define SFLAG_CLEAR 0 +#define MFLAG_SET 2 +#define MFLAG_CLEAR 0 + +/* Turn flag values into 1 or 0 */ +#define XFLAG_AS_1(M) (((M)->x_flag>>8)&1) +#define NFLAG_AS_1(M) (((M)->n_flag>>7)&1) +#define VFLAG_AS_1(M) (((M)->v_flag>>7)&1) +#define ZFLAG_AS_1(M) (!(M)->not_z_flag) +#define CFLAG_AS_1(M) (((M)->c_flag>>8)&1) + + +/* Conditions */ +#define COND_CS(M) ((M)->c_flag&0x100) +#define COND_CC(M) (!COND_CS(M)) +#define COND_VS(M) ((M)->v_flag&0x80) +#define COND_VC(M) (!COND_VS(M)) +#define COND_NE(M) (M)->not_z_flag +#define COND_EQ(M) (!COND_NE(M)) +#define COND_MI(M) ((M)->n_flag&0x80) +#define COND_PL(M) (!COND_MI(M)) +#define COND_LT(M) (((M)->n_flag^(M)->v_flag)&0x80) +#define COND_GE(M) (!COND_LT(M)) +#define COND_HI(M) (COND_CC(M) && COND_NE(M)) +#define COND_LS(M) (COND_CS(M) || COND_EQ(M)) +#define COND_GT(M) (COND_GE(M) && COND_NE(M)) +#define COND_LE(M) (COND_LT(M) || COND_EQ(M)) + +/* Reversed conditions */ +#define COND_NOT_CS(M) COND_CC(M) +#define COND_NOT_CC(M) COND_CS(M) +#define COND_NOT_VS(M) COND_VC(M) +#define COND_NOT_VC(M) COND_VS(M) +#define COND_NOT_NE(M) COND_EQ(M) +#define COND_NOT_EQ(M) COND_NE(M) +#define COND_NOT_MI(M) COND_PL(M) +#define COND_NOT_PL(M) COND_MI(M) +#define COND_NOT_LT(M) COND_GE(M) +#define COND_NOT_GE(M) COND_LT(M) +#define COND_NOT_HI(M) COND_LS(M) +#define COND_NOT_LS(M) COND_HI(M) +#define COND_NOT_GT(M) COND_LE(M) +#define COND_NOT_LE(M) COND_GT(M) + +/* Not real conditions, but here for convenience */ +#define COND_XS(M) ((M)->x_flag&0x100) +#define COND_XC(M) (!COND_XS) + + +/* Get the condition code register */ +#define m68ki_get_ccr(M) ((COND_XS(M) >> 4) | \ + (COND_MI(M) >> 4) | \ + (COND_EQ(M) << 2) | \ + (COND_VS(M) >> 6) | \ + (COND_CS(M) >> 8)) + +/* Get the status register */ +#define m68ki_get_sr(M) ((M)->t1_flag | \ + (M)->t0_flag | \ + ((M)->s_flag << 11) | \ + ((M)->m_flag << 11) | \ + (M)->int_mask | \ + m68ki_get_ccr(M)) + + + +/* ----------------------------- Read / Write ----------------------------- */ + +/* Read from the current address space */ +#define m68ki_read_8(M, A) m68ki_read_8_fc (M, A, m68k->s_flag | FUNCTION_CODE_USER_DATA) +#define m68ki_read_16(M, A) m68ki_read_16_fc(M, A, m68k->s_flag | FUNCTION_CODE_USER_DATA) +#define m68ki_read_32(M, A) m68ki_read_32_fc(M, A, m68k->s_flag | FUNCTION_CODE_USER_DATA) + +/* Write to the current data space */ +#define m68ki_write_8(M, A, V) m68ki_write_8_fc (M, A, m68k->s_flag | FUNCTION_CODE_USER_DATA, V) +#define m68ki_write_16(M, A, V) m68ki_write_16_fc(M, A, m68k->s_flag | FUNCTION_CODE_USER_DATA, V) +#define m68ki_write_32(M, A, V) m68ki_write_32_fc(M, A, m68k->s_flag | FUNCTION_CODE_USER_DATA, V) +#define m68ki_write_32_pd(M, A, V) m68ki_write_32_pd_fc(M, A, m68k->s_flag | FUNCTION_CODE_USER_DATA, V) + +/* map read immediate 8 to read immediate 16 */ +#define m68ki_read_imm_8(M) MASK_OUT_ABOVE_8(m68ki_read_imm_16(M)) + +/* Map PC-relative reads */ +#define m68ki_read_pcrel_8(M, A) m68k_read_pcrelative_8(M, A) +#define m68ki_read_pcrel_16(M, A) m68k_read_pcrelative_16(M, A) +#define m68ki_read_pcrel_32(M, A) m68k_read_pcrelative_32(M, A) + +/* Read from the program space */ +#define m68ki_read_program_8(M, A) m68ki_read_8_fc(M, A, m68k->s_flag | FUNCTION_CODE_USER_PROGRAM) +#define m68ki_read_program_16(M, A) m68ki_read_16_fc(M, A, m68k->s_flag | FUNCTION_CODE_USER_PROGRAM) +#define m68ki_read_program_32(M, A) m68ki_read_32_fc(M, A, m68k->s_flag | FUNCTION_CODE_USER_PROGRAM) + +/* Read from the data space */ +#define m68ki_read_data_8(M, A) m68ki_read_8_fc(M, A, m68k->s_flag | FUNCTION_CODE_USER_DATA) +#define m68ki_read_data_16(M, A) m68ki_read_16_fc(M, A, m68k->s_flag | FUNCTION_CODE_USER_DATA) +#define m68ki_read_data_32(M, A) m68ki_read_32_fc(M, A, m68k->s_flag | FUNCTION_CODE_USER_DATA) + + + +/* ======================================================================== */ +/* =============================== PROTOTYPES ============================= */ +/* ======================================================================== */ + +/* Redirect memory calls */ + +extern const UINT8 m68ki_shift_8_table[]; +extern const UINT16 m68ki_shift_16_table[]; +extern const UINT32 m68ki_shift_32_table[]; +extern const UINT8 m68ki_exception_cycle_table[][256]; +extern const UINT8 m68ki_ea_idx_cycle_table[]; + +/* Read data immediately after the program counter */ +INLINE UINT32 m68ki_read_imm_16(m68ki_cpu_core *m68k); +INLINE UINT32 m68ki_read_imm_32(m68ki_cpu_core *m68k); + +/* Read data with specific function code */ +INLINE UINT32 m68ki_read_8_fc (m68ki_cpu_core *m68k, UINT32 address, UINT32 fc); +INLINE UINT32 m68ki_read_16_fc (m68ki_cpu_core *m68k, UINT32 address, UINT32 fc); +INLINE UINT32 m68ki_read_32_fc (m68ki_cpu_core *m68k, UINT32 address, UINT32 fc); + +/* Write data with specific function code */ +INLINE void m68ki_write_8_fc (m68ki_cpu_core *m68k, UINT32 address, UINT32 fc, UINT32 value); +INLINE void m68ki_write_16_fc(m68ki_cpu_core *m68k, UINT32 address, UINT32 fc, UINT32 value); +INLINE void m68ki_write_32_fc(m68ki_cpu_core *m68k, UINT32 address, UINT32 fc, UINT32 value); +INLINE void m68ki_write_32_pd_fc(m68ki_cpu_core *m68k, UINT32 address, UINT32 fc, UINT32 value); + +/* Indexed and PC-relative ea fetching */ +INLINE UINT32 m68ki_get_ea_pcdi(m68ki_cpu_core *m68k); +INLINE UINT32 m68ki_get_ea_pcix(m68ki_cpu_core *m68k); +INLINE UINT32 m68ki_get_ea_ix(m68ki_cpu_core *m68k, UINT32 An); + +/* Operand fetching */ +INLINE UINT32 OPER_AY_AI_8(m68ki_cpu_core *m68k); +INLINE UINT32 OPER_AY_AI_16(m68ki_cpu_core *m68k); +INLINE UINT32 OPER_AY_AI_32(m68ki_cpu_core *m68k); +INLINE UINT32 OPER_AY_PI_8(m68ki_cpu_core *m68k); +INLINE UINT32 OPER_AY_PI_16(m68ki_cpu_core *m68k); +INLINE UINT32 OPER_AY_PI_32(m68ki_cpu_core *m68k); +INLINE UINT32 OPER_AY_PD_8(m68ki_cpu_core *m68k); +INLINE UINT32 OPER_AY_PD_16(m68ki_cpu_core *m68k); +INLINE UINT32 OPER_AY_PD_32(m68ki_cpu_core *m68k); +INLINE UINT32 OPER_AY_DI_8(m68ki_cpu_core *m68k); +INLINE UINT32 OPER_AY_DI_16(m68ki_cpu_core *m68k); +INLINE UINT32 OPER_AY_DI_32(m68ki_cpu_core *m68k); +INLINE UINT32 OPER_AY_IX_8(m68ki_cpu_core *m68k); +INLINE UINT32 OPER_AY_IX_16(m68ki_cpu_core *m68k); +INLINE UINT32 OPER_AY_IX_32(m68ki_cpu_core *m68k); + +INLINE UINT32 OPER_AX_AI_8(m68ki_cpu_core *m68k); +INLINE UINT32 OPER_AX_AI_16(m68ki_cpu_core *m68k); +INLINE UINT32 OPER_AX_AI_32(m68ki_cpu_core *m68k); +INLINE UINT32 OPER_AX_PI_8(m68ki_cpu_core *m68k); +INLINE UINT32 OPER_AX_PI_16(m68ki_cpu_core *m68k); +INLINE UINT32 OPER_AX_PI_32(m68ki_cpu_core *m68k); +INLINE UINT32 OPER_AX_PD_8(m68ki_cpu_core *m68k); +INLINE UINT32 OPER_AX_PD_16(m68ki_cpu_core *m68k); +INLINE UINT32 OPER_AX_PD_32(m68ki_cpu_core *m68k); +INLINE UINT32 OPER_AX_DI_8(m68ki_cpu_core *m68k); +INLINE UINT32 OPER_AX_DI_16(m68ki_cpu_core *m68k); +INLINE UINT32 OPER_AX_DI_32(m68ki_cpu_core *m68k); +INLINE UINT32 OPER_AX_IX_8(m68ki_cpu_core *m68k); +INLINE UINT32 OPER_AX_IX_16(m68ki_cpu_core *m68k); +INLINE UINT32 OPER_AX_IX_32(m68ki_cpu_core *m68k); + +INLINE UINT32 OPER_A7_PI_8(m68ki_cpu_core *m68k); +INLINE UINT32 OPER_A7_PD_8(m68ki_cpu_core *m68k); + +INLINE UINT32 OPER_AW_8(m68ki_cpu_core *m68k); +INLINE UINT32 OPER_AW_16(m68ki_cpu_core *m68k); +INLINE UINT32 OPER_AW_32(m68ki_cpu_core *m68k); +INLINE UINT32 OPER_AL_8(m68ki_cpu_core *m68k); +INLINE UINT32 OPER_AL_16(m68ki_cpu_core *m68k); +INLINE UINT32 OPER_AL_32(m68ki_cpu_core *m68k); +INLINE UINT32 OPER_PCDI_8(m68ki_cpu_core *m68k); +INLINE UINT32 OPER_PCDI_16(m68ki_cpu_core *m68k); +INLINE UINT32 OPER_PCDI_32(m68ki_cpu_core *m68k); +INLINE UINT32 OPER_PCIX_8(m68ki_cpu_core *m68k); +INLINE UINT32 OPER_PCIX_16(m68ki_cpu_core *m68k); +INLINE UINT32 OPER_PCIX_32(m68ki_cpu_core *m68k); + +/* Stack operations */ +INLINE void m68ki_push_16(m68ki_cpu_core *m68k, UINT32 value); +INLINE void m68ki_push_32(m68ki_cpu_core *m68k, UINT32 value); +INLINE UINT32 m68ki_pull_16(m68ki_cpu_core *m68k); +INLINE UINT32 m68ki_pull_32(m68ki_cpu_core *m68k); + +/* Program flow operations */ +INLINE void m68ki_jump(m68ki_cpu_core *m68k, UINT32 new_pc); +INLINE void m68ki_jump_vector(m68ki_cpu_core *m68k, UINT32 vector); +INLINE void m68ki_branch_8(m68ki_cpu_core *m68k, UINT32 offset); +INLINE void m68ki_branch_16(m68ki_cpu_core *m68k, UINT32 offset); +INLINE void m68ki_branch_32(m68ki_cpu_core *m68k, UINT32 offset); + +/* Status register operations. */ +INLINE void m68ki_set_s_flag(m68ki_cpu_core *m68k, UINT32 value); /* Only bit 2 of value should be set (i.e. 4 or 0) */ +INLINE void m68ki_set_sm_flag(m68ki_cpu_core *m68k, UINT32 value); /* only bits 1 and 2 of value should be set */ +INLINE void m68ki_set_ccr(m68ki_cpu_core *m68k, UINT32 value); /* set the condition code register */ +INLINE void m68ki_set_sr(m68ki_cpu_core *m68k, UINT32 value); /* set the status register */ +INLINE void m68ki_set_sr_noint(m68ki_cpu_core *m68k, UINT32 value); /* set the status register */ + +/* Exception processing */ +INLINE UINT32 m68ki_init_exception(m68ki_cpu_core *m68k); /* Initial exception processing */ + +INLINE void m68ki_stack_frame_3word(m68ki_cpu_core *m68k, UINT32 pc, UINT32 sr); /* Stack various frame types */ +INLINE void m68ki_stack_frame_buserr(m68ki_cpu_core *m68k, UINT32 sr); + +INLINE void m68ki_stack_frame_0000(m68ki_cpu_core *m68k, UINT32 pc, UINT32 sr, UINT32 vector); +INLINE void m68ki_stack_frame_0001(m68ki_cpu_core *m68k, UINT32 pc, UINT32 sr, UINT32 vector); +INLINE void m68ki_stack_frame_0010(m68ki_cpu_core *m68k, UINT32 sr, UINT32 vector); +INLINE void m68ki_stack_frame_1000(m68ki_cpu_core *m68k, UINT32 pc, UINT32 sr, UINT32 vector); +INLINE void m68ki_stack_frame_1010(m68ki_cpu_core *m68k, UINT32 sr, UINT32 vector, UINT32 pc); +INLINE void m68ki_stack_frame_1011(m68ki_cpu_core *m68k, UINT32 sr, UINT32 vector, UINT32 pc); + +INLINE void m68ki_exception_trap(m68ki_cpu_core *m68k, UINT32 vector); +INLINE void m68ki_exception_trapN(m68ki_cpu_core *m68k, UINT32 vector); +INLINE void m68ki_exception_trace(m68ki_cpu_core *m68k); +INLINE void m68ki_exception_privilege_violation(m68ki_cpu_core *m68k); +INLINE void m68ki_exception_1010(m68ki_cpu_core *m68k); +INLINE void m68ki_exception_1111(m68ki_cpu_core *m68k); +INLINE void m68ki_exception_illegal(m68ki_cpu_core *m68k); +INLINE void m68ki_exception_format_error(m68ki_cpu_core *m68k); +INLINE void m68ki_exception_address_error(m68ki_cpu_core *m68k); +INLINE void m68ki_exception_interrupt(m68ki_cpu_core *m68k, UINT32 int_level); +INLINE void m68ki_check_interrupts(m68ki_cpu_core *m68k); /* ASG: check for interrupts */ + +/* quick disassembly (used for logging) */ +char* m68ki_disassemble_quick(unsigned int pc, unsigned int cpu_type); + + +/* ======================================================================== */ +/* =========================== UTILITY FUNCTIONS ========================== */ +/* ======================================================================== */ + + +#define m68k_read_immediate_16(M, address) *(uint16 *)((M)->memory_map[((address)>>16)&0xff].base + ((address) & 0xffff)) +#define m68k_read_immediate_32(M, address) (m68k_read_immediate_16(M, address) << 16) | (m68k_read_immediate_16(M, address+2)) + +/* Read data relative to the PC */ +#define m68k_read_pcrelative_8(M, address) READ_BYTE((M)->memory_map[((address)>>16)&0xff].base, (address) & 0xffff) +#define m68k_read_pcrelative_16(M, address) m68k_read_immediate_16(M, address) +#define m68k_read_pcrelative_32(M, address) m68k_read_immediate_32(M, address) + + +/* Special call to simulate undocumented 68k behavior when move.l with a + * predecrement destination mode is executed. + * A real 68k first writes the high word to [address+2], and then writes the + * low word to [address]. + */ +INLINE void m68kx_write_memory_32_pd(m68ki_cpu_core *m68k, unsigned int address, unsigned int value) +{ + m68ki_write_32_pd_fc(m68k, address, 0, value); +} + + +/* ---------------------------- Read Immediate ---------------------------- */ + +/* Handles all immediate reads, does address error check, function code setting, + * and prefetching if they are enabled in m68kconf.h + */ +INLINE UINT32 m68ki_read_imm_16(m68ki_cpu_core *m68k) +{ + UINT32 result; + uint pc; + + m68ki_check_address_error(m68k, REG_PC, MODE_READ, m68k->s_flag | FUNCTION_CODE_USER_PROGRAM); /* auto-disable (see m68kcpu.h) */ + +#if M68K_EMULATE_PREFETCH + if(REG_PC != m68k->pref_addr) + { + m68k->pref_addr = REG_PC; + m68k->pref_data = m68k_read_immediate_16(m68k->pref_addr); + } + result = MASK_OUT_ABOVE_16(m68k->pref_data); + REG_PC += 2; + m68k->pref_addr = REG_PC; + m68k->pref_data = m68k_read_immediate_16(m68k->pref_addr); + return result; +#else + pc = REG_PC; + REG_PC += 2; + return m68k_read_immediate_16(m68k, pc); +#endif +} + +INLINE UINT32 m68ki_read_imm_32(m68ki_cpu_core *m68k) +{ +#if M68K_EMULATE_PREFETCH + UINT32 temp_val; + + m68ki_check_address_error(m68k, REG_PC, MODE_READ, m68k->s_flag | FUNCTION_CODE_USER_PROGRAM); /* auto-disable (see m68kcpu.h) */ + + if(REG_PC != m68k->pref_addr) + { + m68k->pref_addr = REG_PC; + m68k->pref_data = m68k_read_immediate_16(m68k->pref_addr); + } + temp_val = MASK_OUT_ABOVE_16(m68k->pref_data); + REG_PC += 2; + m68k->pref_addr = REG_PC; + m68k->pref_data = m68k_read_immediate_16(m68k->pref_addr); + + temp_val = MASK_OUT_ABOVE_32((temp_val << 16) | MASK_OUT_ABOVE_16(m68k->pref_data)); + REG_PC += 2; + m68k->pref_addr = REG_PC; + m68k->pref_data = m68k_read_immediate_16(m68k->pref_addr); + + return temp_val; +#else +#if M68K_CHECK_PC_ADDRESS_ERROR + m68ki_check_address_error(REG_PC, MODE_READ, m68k->s_flag | FUNCTION_CODE_USER_PROGRAM) /* auto-disable (see m68kcpu.h) */ +#endif + uint pc = REG_PC; + REG_PC += 4; + return m68k_read_immediate_32(m68k, pc); +#endif +} + + + +/* ------------------------- Top level read/write ------------------------- */ + +/* Handles all memory accesses (except for immediate reads if they are + * configured to use separate functions in m68kconf.h). + * All memory accesses must go through these top level functions. + * These functions will also check for address error and set the function + * code if they are enabled in m68kconf.h. + */ +INLINE uint m68ki_read_8_fc(m68ki_cpu_core *m68k, uint address, uint fc) +{ + cpu_memory_map *temp = &m68k->memory_map[((address)>>16)&0xff];; + + if (temp->read8) return (*temp->read8)(temp->param, address & 0xFFFFFF); + else return READ_BYTE(temp->base, (address) & 0xffff); +} + +INLINE uint m68ki_read_16_fc(m68ki_cpu_core *m68k, uint address, uint fc) +{ + cpu_memory_map *temp; + + temp = &m68k->memory_map[((address)>>16)&0xff]; + if (temp->read16) return (*temp->read16)(temp->param, address & 0xFFFFFF); + else return *(uint16 *)(temp->base + ((address) & 0xffff)); +} + +INLINE uint m68ki_read_32_fc(m68ki_cpu_core *m68k, uint address, uint fc) +{ + cpu_memory_map *temp; + + temp = &m68k->memory_map[((address)>>16)&0xff]; + if (temp->read16) return ((*temp->read16)(temp->param, address & 0xFFFFFF) << 16) | ((*temp->read16)(temp->param, (address + 2) & 0xFFFFFF)); + else return m68k_read_immediate_32(m68k, address); +} + +INLINE void m68ki_write_8_fc(m68ki_cpu_core *m68k, uint address, uint fc, uint value) +{ + cpu_memory_map *temp; + + temp = &m68k->memory_map[((address)>>16)&0xff]; + if (temp->write8) (*temp->write8)(temp->param,address&0xFFFFFF,value); + else WRITE_BYTE(temp->base, (address) & 0xffff, value); +} + +INLINE void m68ki_write_16_fc(m68ki_cpu_core *m68k, uint address, uint fc, uint value) +{ + cpu_memory_map *temp; + + temp = &m68k->memory_map[((address)>>16)&0xff]; + if (temp->write16) (*temp->write16)(temp->param,address&0xFFFFFF,value); + else *(uint16 *)(temp->base + ((address) & 0xffff)) = value; +} + +INLINE void m68ki_write_32_fc(m68ki_cpu_core *m68k, uint address, uint fc, uint value) +{ + cpu_memory_map *temp; + + temp = &m68k->memory_map[((address)>>16)&0xff]; + if (temp->write16) (*temp->write16)(temp->param,address&0xFFFFFF,value>>16); + else *(uint16 *)(temp->base + ((address) & 0xffff)) = value >> 16; + + temp = &m68k->memory_map[((address + 2)>>16)&0xff]; + if (temp->write16) (*temp->write16)(temp->param,(address+2)&0xFFFFFF,value&0xffff); + else *(uint16 *)(temp->base + ((address + 2) & 0xffff)) = value; +} + +/* Special call to simulate undocumented 68k behavior when move.l with a + * predecrement destination mode is executed. + * A real 68k first writes the high word to [address+2], and then writes the + * low word to [address]. + */ +INLINE void m68ki_write_32_pd_fc(m68ki_cpu_core *m68k, UINT32 address, UINT32 fc, UINT32 value) +{ + cpu_memory_map *temp; + + temp = &m68k->memory_map[((address + 2)>>16)&0xff]; + if (temp->write16) (*temp->write16)(temp->param,(address+2)&0xFFFFFF,value&0xffff); + else *(uint16 *)(temp->base + ((address + 2) & 0xffff)) = value; + + temp = &m68k->memory_map[((address)>>16)&0xff]; + if (temp->write16) (*temp->write16)(temp->param,(address)&0xFFFFFF,value>>16); + else *(uint16 *)(temp->base + ((address) & 0xffff)) = value >> 16; +} + + +/* --------------------- Effective Address Calculation -------------------- */ + +/* The program counter relative addressing modes cause operands to be + * retrieved from program space, not data space. + */ +INLINE UINT32 m68ki_get_ea_pcdi(m68ki_cpu_core *m68k) +{ + UINT32 old_pc = REG_PC; + return old_pc + MAKE_INT_16(m68ki_read_imm_16(m68k)); +} + + +INLINE UINT32 m68ki_get_ea_pcix(m68ki_cpu_core *m68k) +{ + return m68ki_get_ea_ix(m68k, REG_PC); +} + +/* Indexed addressing modes are encoded as follows: + * + * Base instruction format: + * F E D C B A 9 8 7 6 | 5 4 3 | 2 1 0 + * x x x x x x x x x x | 1 1 0 | BASE REGISTER (An) + * + * Base instruction format for destination EA in move instructions: + * F E D C | B A 9 | 8 7 6 | 5 4 3 2 1 0 + * x x x x | BASE REG | 1 1 0 | X X X X X X (An) + * + * Brief extension format: + * F | E D C | B | A 9 | 8 | 7 6 5 4 3 2 1 0 + * D/A | REGISTER | W/L | SCALE | 0 | DISPLACEMENT + * + * Full extension format: + * F E D C B A 9 8 7 6 5 4 3 2 1 0 + * D/A | REGISTER | W/L | SCALE | 1 | BS | IS | BD SIZE | 0 | I/IS + * BASE DISPLACEMENT (0, 16, 32 bit) (bd) + * OUTER DISPLACEMENT (0, 16, 32 bit) (od) + * + * D/A: 0 = Dn, 1 = An (Xn) + * W/L: 0 = W (sign extend), 1 = L (.SIZE) + * SCALE: 00=1, 01=2, 10=4, 11=8 (*SCALE) + * BS: 0=add base reg, 1=suppress base reg (An suppressed) + * IS: 0=add index, 1=suppress index (Xn suppressed) + * BD SIZE: 00=reserved, 01=NULL, 10=Word, 11=Long (size of bd) + * + * IS I/IS Operation + * 0 000 No Memory Indirect + * 0 001 indir prex with null outer + * 0 010 indir prex with word outer + * 0 011 indir prex with long outer + * 0 100 reserved + * 0 101 indir postx with null outer + * 0 110 indir postx with word outer + * 0 111 indir postx with long outer + * 1 000 no memory indirect + * 1 001 mem indir with null outer + * 1 010 mem indir with word outer + * 1 011 mem indir with long outer + * 1 100-111 reserved + */ +INLINE UINT32 m68ki_get_ea_ix(m68ki_cpu_core *m68k, UINT32 An) +{ + /* An = base register */ + UINT32 extension = m68ki_read_imm_16(m68k); + UINT32 Xn = 0; /* Index register */ + UINT32 bd = 0; /* Base Displacement */ + UINT32 od = 0; /* Outer Displacement */ + + { + /* Calculate index */ + Xn = REG_DA[extension>>12]; /* Xn */ + if(!BIT_B(extension)) /* W/L */ + Xn = MAKE_INT_16(Xn); + + /* Add base register and displacement and return */ + return An + Xn + MAKE_INT_8(extension); + } + + /* Brief extension format */ + if(!BIT_8(extension)) + { + /* Calculate index */ + Xn = REG_DA[extension>>12]; /* Xn */ + if(!BIT_B(extension)) /* W/L */ + Xn = MAKE_INT_16(Xn); + + /* Add base register and displacement and return */ + return An + Xn + MAKE_INT_8(extension); + } + + /* Full extension format */ + + m68k->remaining_cycles -= m68ki_ea_idx_cycle_table[extension&0x3f]; + + /* Check if base register is present */ + if(BIT_7(extension)) /* BS */ + An = 0; /* An */ + + /* Check if index is present */ + if(!BIT_6(extension)) /* IS */ + { + Xn = REG_DA[extension>>12]; /* Xn */ + if(!BIT_B(extension)) /* W/L */ + Xn = MAKE_INT_16(Xn); + Xn <<= (extension>>9) & 3; /* SCALE */ + } + + /* Check if base displacement is present */ + if(BIT_5(extension)) /* BD SIZE */ + bd = BIT_4(extension) ? m68ki_read_imm_32(m68k) : MAKE_INT_16(m68ki_read_imm_16(m68k)); + + /* If no indirect action, we are done */ + if(!(extension&7)) /* No Memory Indirect */ + return An + bd + Xn; + + /* Check if outer displacement is present */ + if(BIT_1(extension)) /* I/IS: od */ + od = BIT_0(extension) ? m68ki_read_imm_32(m68k) : MAKE_INT_16(m68ki_read_imm_16(m68k)); + + /* Postindex */ + if(BIT_2(extension)) /* I/IS: 0 = preindex, 1 = postindex */ + return m68ki_read_32(m68k, An + bd) + Xn + od; + + /* Preindex */ + return m68ki_read_32(m68k, An + bd + Xn) + od; +} + + +/* Fetch operands */ +INLINE UINT32 OPER_AY_AI_8(m68ki_cpu_core *m68k) {UINT32 ea = EA_AY_AI_8(m68k); return m68ki_read_8(m68k, ea); } +INLINE UINT32 OPER_AY_AI_16(m68ki_cpu_core *m68k) {UINT32 ea = EA_AY_AI_16(m68k); return m68ki_read_16(m68k, ea);} +INLINE UINT32 OPER_AY_AI_32(m68ki_cpu_core *m68k) {UINT32 ea = EA_AY_AI_32(m68k); return m68ki_read_32(m68k, ea);} +INLINE UINT32 OPER_AY_PI_8(m68ki_cpu_core *m68k) {UINT32 ea = EA_AY_PI_8(m68k); return m68ki_read_8(m68k, ea); } +INLINE UINT32 OPER_AY_PI_16(m68ki_cpu_core *m68k) {UINT32 ea = EA_AY_PI_16(m68k); return m68ki_read_16(m68k, ea);} +INLINE UINT32 OPER_AY_PI_32(m68ki_cpu_core *m68k) {UINT32 ea = EA_AY_PI_32(m68k); return m68ki_read_32(m68k, ea);} +INLINE UINT32 OPER_AY_PD_8(m68ki_cpu_core *m68k) {UINT32 ea = EA_AY_PD_8(m68k); return m68ki_read_8(m68k, ea); } +INLINE UINT32 OPER_AY_PD_16(m68ki_cpu_core *m68k) {UINT32 ea = EA_AY_PD_16(m68k); return m68ki_read_16(m68k, ea);} +INLINE UINT32 OPER_AY_PD_32(m68ki_cpu_core *m68k) {UINT32 ea = EA_AY_PD_32(m68k); return m68ki_read_32(m68k, ea);} +INLINE UINT32 OPER_AY_DI_8(m68ki_cpu_core *m68k) {UINT32 ea = EA_AY_DI_8(m68k); return m68ki_read_8(m68k, ea); } +INLINE UINT32 OPER_AY_DI_16(m68ki_cpu_core *m68k) {UINT32 ea = EA_AY_DI_16(m68k); return m68ki_read_16(m68k, ea);} +INLINE UINT32 OPER_AY_DI_32(m68ki_cpu_core *m68k) {UINT32 ea = EA_AY_DI_32(m68k); return m68ki_read_32(m68k, ea);} +INLINE UINT32 OPER_AY_IX_8(m68ki_cpu_core *m68k) {UINT32 ea = EA_AY_IX_8(m68k); return m68ki_read_8(m68k, ea); } +INLINE UINT32 OPER_AY_IX_16(m68ki_cpu_core *m68k) {UINT32 ea = EA_AY_IX_16(m68k); return m68ki_read_16(m68k, ea);} +INLINE UINT32 OPER_AY_IX_32(m68ki_cpu_core *m68k) {UINT32 ea = EA_AY_IX_32(m68k); return m68ki_read_32(m68k, ea);} + +INLINE UINT32 OPER_AX_AI_8(m68ki_cpu_core *m68k) {UINT32 ea = EA_AX_AI_8(m68k); return m68ki_read_8(m68k, ea); } +INLINE UINT32 OPER_AX_AI_16(m68ki_cpu_core *m68k) {UINT32 ea = EA_AX_AI_16(m68k); return m68ki_read_16(m68k, ea);} +INLINE UINT32 OPER_AX_AI_32(m68ki_cpu_core *m68k) {UINT32 ea = EA_AX_AI_32(m68k); return m68ki_read_32(m68k, ea);} +INLINE UINT32 OPER_AX_PI_8(m68ki_cpu_core *m68k) {UINT32 ea = EA_AX_PI_8(m68k); return m68ki_read_8(m68k, ea); } +INLINE UINT32 OPER_AX_PI_16(m68ki_cpu_core *m68k) {UINT32 ea = EA_AX_PI_16(m68k); return m68ki_read_16(m68k, ea);} +INLINE UINT32 OPER_AX_PI_32(m68ki_cpu_core *m68k) {UINT32 ea = EA_AX_PI_32(m68k); return m68ki_read_32(m68k, ea);} +INLINE UINT32 OPER_AX_PD_8(m68ki_cpu_core *m68k) {UINT32 ea = EA_AX_PD_8(m68k); return m68ki_read_8(m68k, ea); } +INLINE UINT32 OPER_AX_PD_16(m68ki_cpu_core *m68k) {UINT32 ea = EA_AX_PD_16(m68k); return m68ki_read_16(m68k, ea);} +INLINE UINT32 OPER_AX_PD_32(m68ki_cpu_core *m68k) {UINT32 ea = EA_AX_PD_32(m68k); return m68ki_read_32(m68k, ea);} +INLINE UINT32 OPER_AX_DI_8(m68ki_cpu_core *m68k) {UINT32 ea = EA_AX_DI_8(m68k); return m68ki_read_8(m68k, ea); } +INLINE UINT32 OPER_AX_DI_16(m68ki_cpu_core *m68k) {UINT32 ea = EA_AX_DI_16(m68k); return m68ki_read_16(m68k, ea);} +INLINE UINT32 OPER_AX_DI_32(m68ki_cpu_core *m68k) {UINT32 ea = EA_AX_DI_32(m68k); return m68ki_read_32(m68k, ea);} +INLINE UINT32 OPER_AX_IX_8(m68ki_cpu_core *m68k) {UINT32 ea = EA_AX_IX_8(m68k); return m68ki_read_8(m68k, ea); } +INLINE UINT32 OPER_AX_IX_16(m68ki_cpu_core *m68k) {UINT32 ea = EA_AX_IX_16(m68k); return m68ki_read_16(m68k, ea);} +INLINE UINT32 OPER_AX_IX_32(m68ki_cpu_core *m68k) {UINT32 ea = EA_AX_IX_32(m68k); return m68ki_read_32(m68k, ea);} + +INLINE UINT32 OPER_A7_PI_8(m68ki_cpu_core *m68k) {UINT32 ea = EA_A7_PI_8(m68k); return m68ki_read_8(m68k, ea); } +INLINE UINT32 OPER_A7_PD_8(m68ki_cpu_core *m68k) {UINT32 ea = EA_A7_PD_8(m68k); return m68ki_read_8(m68k, ea); } + +INLINE UINT32 OPER_AW_8(m68ki_cpu_core *m68k) {UINT32 ea = EA_AW_8(m68k); return m68ki_read_8(m68k, ea); } +INLINE UINT32 OPER_AW_16(m68ki_cpu_core *m68k) {UINT32 ea = EA_AW_16(m68k); return m68ki_read_16(m68k, ea);} +INLINE UINT32 OPER_AW_32(m68ki_cpu_core *m68k) {UINT32 ea = EA_AW_32(m68k); return m68ki_read_32(m68k, ea);} +INLINE UINT32 OPER_AL_8(m68ki_cpu_core *m68k) {UINT32 ea = EA_AL_8(m68k); return m68ki_read_8(m68k, ea); } +INLINE UINT32 OPER_AL_16(m68ki_cpu_core *m68k) {UINT32 ea = EA_AL_16(m68k); return m68ki_read_16(m68k, ea);} +INLINE UINT32 OPER_AL_32(m68ki_cpu_core *m68k) {UINT32 ea = EA_AL_32(m68k); return m68ki_read_32(m68k, ea);} +INLINE UINT32 OPER_PCDI_8(m68ki_cpu_core *m68k) {UINT32 ea = EA_PCDI_8(m68k); return m68ki_read_pcrel_8(m68k, ea); } +INLINE UINT32 OPER_PCDI_16(m68ki_cpu_core *m68k) {UINT32 ea = EA_PCDI_16(m68k); return m68ki_read_pcrel_16(m68k, ea);} +INLINE UINT32 OPER_PCDI_32(m68ki_cpu_core *m68k) {UINT32 ea = EA_PCDI_32(m68k); return m68ki_read_pcrel_32(m68k, ea);} +INLINE UINT32 OPER_PCIX_8(m68ki_cpu_core *m68k) {UINT32 ea = EA_PCIX_8(m68k); return m68ki_read_pcrel_8(m68k, ea); } +INLINE UINT32 OPER_PCIX_16(m68ki_cpu_core *m68k) {UINT32 ea = EA_PCIX_16(m68k); return m68ki_read_pcrel_16(m68k, ea);} +INLINE UINT32 OPER_PCIX_32(m68ki_cpu_core *m68k) {UINT32 ea = EA_PCIX_32(m68k); return m68ki_read_pcrel_32(m68k, ea);} + + + +/* ---------------------------- Stack Functions --------------------------- */ + +/* Push/pull data from the stack */ +INLINE void m68ki_push_16(m68ki_cpu_core *m68k, UINT32 value) +{ + REG_SP = MASK_OUT_ABOVE_32(REG_SP - 2); + m68ki_write_16(m68k, REG_SP, value); +} + +INLINE void m68ki_push_32(m68ki_cpu_core *m68k, UINT32 value) +{ + REG_SP = MASK_OUT_ABOVE_32(REG_SP - 4); + m68ki_write_32(m68k, REG_SP, value); +} + +INLINE UINT32 m68ki_pull_16(m68ki_cpu_core *m68k) +{ + REG_SP = MASK_OUT_ABOVE_32(REG_SP + 2); + return m68ki_read_16(m68k, REG_SP-2); +} + +INLINE UINT32 m68ki_pull_32(m68ki_cpu_core *m68k) +{ + REG_SP = MASK_OUT_ABOVE_32(REG_SP + 4); + return m68ki_read_32(m68k, REG_SP-4); +} + + +/* Increment/decrement the stack as if doing a push/pull but + * don't do any memory access. + */ +INLINE void m68ki_fake_push_16(m68ki_cpu_core *m68k) +{ + REG_SP = MASK_OUT_ABOVE_32(REG_SP - 2); +} + +INLINE void m68ki_fake_push_32(m68ki_cpu_core *m68k) +{ + REG_SP = MASK_OUT_ABOVE_32(REG_SP - 4); +} + +INLINE void m68ki_fake_pull_16(m68ki_cpu_core *m68k) +{ + REG_SP = MASK_OUT_ABOVE_32(REG_SP + 2); +} + +INLINE void m68ki_fake_pull_32(m68ki_cpu_core *m68k) +{ + REG_SP = MASK_OUT_ABOVE_32(REG_SP + 4); +} + + +/* ----------------------------- Program Flow ----------------------------- */ + +/* Jump to a new program location or vector. + * These functions will also call the pc_changed callback if it was enabled + * in m68kconf.h. + */ +INLINE void m68ki_jump(m68ki_cpu_core *m68k, UINT32 new_pc) +{ + REG_PC = new_pc; +} + +INLINE void m68ki_jump_vector(m68ki_cpu_core *m68k, UINT32 vector) +{ + REG_PC = (vector<<2); + REG_PC = m68ki_read_data_32(m68k, REG_PC); +} + + +/* Branch to a new memory location. + * The 32-bit branch will call pc_changed if it was enabled in m68kconf.h. + * So far I've found no problems with not calling pc_changed for 8 or 16 + * bit branches. + */ +INLINE void m68ki_branch_8(m68ki_cpu_core *m68k, UINT32 offset) +{ + REG_PC += MAKE_INT_8(offset); +} + +INLINE void m68ki_branch_16(m68ki_cpu_core *m68k, UINT32 offset) +{ + REG_PC += MAKE_INT_16(offset); +} + +INLINE void m68ki_branch_32(m68ki_cpu_core *m68k, UINT32 offset) +{ + REG_PC += offset; +} + + + +/* ---------------------------- Status Register --------------------------- */ + +/* Set the S flag and change the active stack pointer. + * Note that value MUST be 4 or 0. + */ +INLINE void m68ki_set_s_flag(m68ki_cpu_core *m68k, UINT32 value) +{ + /* Backup the old stack pointer */ + REG_SP_BASE[m68k->s_flag | ((m68k->s_flag>>1) & m68k->m_flag)] = REG_SP; + /* Set the S flag */ + m68k->s_flag = value; + /* Set the new stack pointer */ + REG_SP = REG_SP_BASE[m68k->s_flag | ((m68k->s_flag>>1) & m68k->m_flag)]; +} + +/* Set the S and M flags and change the active stack pointer. + * Note that value MUST be 0, 2, 4, or 6 (bit2 = S, bit1 = M). + */ +INLINE void m68ki_set_sm_flag(m68ki_cpu_core *m68k, UINT32 value) +{ + /* Backup the old stack pointer */ + REG_SP_BASE[m68k->s_flag | ((m68k->s_flag>>1) & m68k->m_flag)] = REG_SP; + /* Set the S and M flags */ + m68k->s_flag = value & SFLAG_SET; + m68k->m_flag = value & MFLAG_SET; + /* Set the new stack pointer */ + REG_SP = REG_SP_BASE[m68k->s_flag | ((m68k->s_flag>>1) & m68k->m_flag)]; +} + +/* Set the S and M flags. Don't touch the stack pointer. */ +INLINE void m68ki_set_sm_flag_nosp(m68ki_cpu_core *m68k, UINT32 value) +{ + /* Set the S and M flags */ + m68k->s_flag = value & SFLAG_SET; + m68k->m_flag = value & MFLAG_SET; +} + + +/* Set the condition code register */ +INLINE void m68ki_set_ccr(m68ki_cpu_core *m68k, UINT32 value) +{ + m68k->x_flag = BIT_4(value) << 4; + m68k->n_flag = BIT_3(value) << 4; + m68k->not_z_flag = !BIT_2(value); + m68k->v_flag = BIT_1(value) << 6; + m68k->c_flag = BIT_0(value) << 8; +} + +/* Set the status register but don't check for interrupts */ +INLINE void m68ki_set_sr_noint(m68ki_cpu_core *m68k, UINT32 value) +{ + /* Mask out the "unimplemented" bits */ + value &= m68k->sr_mask; + + /* Now set the status register */ + m68k->t1_flag = BIT_F(value); + m68k->t0_flag = BIT_E(value); + m68k->int_mask = value & 0x0700; + m68ki_set_ccr(m68k, value); + m68ki_set_sm_flag(m68k, (value >> 11) & 6); +} + +/* Set the status register but don't check for interrupts nor + * change the stack pointer + */ +INLINE void m68ki_set_sr_noint_nosp(m68ki_cpu_core *m68k, UINT32 value) +{ + /* Mask out the "unimplemented" bits */ + value &= m68k->sr_mask; + + /* Now set the status register */ + m68k->t1_flag = BIT_F(value); + m68k->t0_flag = BIT_E(value); + m68k->int_mask = value & 0x0700; + m68ki_set_ccr(m68k, value); + m68ki_set_sm_flag_nosp(m68k, (value >> 11) & 6); +} + +/* Set the status register and check for interrupts */ +INLINE void m68ki_set_sr(m68ki_cpu_core *m68k, UINT32 value) +{ + m68ki_set_sr_noint(m68k, value); + m68ki_check_interrupts(m68k); +} + + +/* ------------------------- Exception Processing ------------------------- */ + +/* Initiate exception processing */ +INLINE UINT32 m68ki_init_exception(m68ki_cpu_core *m68k) +{ + /* Save the old status register */ + UINT32 sr = m68ki_get_sr(m68k); + + /* Turn off trace flag, clear pending traces */ + m68k->t1_flag = m68k->t0_flag = 0; + m68ki_clear_trace(); + /* Enter supervisor mode */ + m68ki_set_s_flag(m68k, SFLAG_SET); + + return sr; +} + +/* 3 word stack frame (68000 only) */ +INLINE void m68ki_stack_frame_3word(m68ki_cpu_core *m68k, UINT32 pc, UINT32 sr) +{ + m68ki_push_32(m68k, pc); + m68ki_push_16(m68k, sr); +} + +/* Format 0 stack frame. + * This is the standard stack frame for 68010+. + */ +INLINE void m68ki_stack_frame_0000(m68ki_cpu_core *m68k, UINT32 pc, UINT32 sr, UINT32 vector) +{ + /* Stack a 3-word frame if we are 68000 */ + { + m68ki_stack_frame_3word(m68k, pc, sr); + return; + } + m68ki_push_16(m68k, vector<<2); + m68ki_push_32(m68k, pc); + m68ki_push_16(m68k, sr); +} + +/* Format 1 stack frame (68020). + * For 68020, this is the 4 word throwaway frame. + */ +INLINE void m68ki_stack_frame_0001(m68ki_cpu_core *m68k, UINT32 pc, UINT32 sr, UINT32 vector) +{ + m68ki_push_16(m68k, 0x1000 | (vector<<2)); + m68ki_push_32(m68k, pc); + m68ki_push_16(m68k, sr); +} + +/* Format 2 stack frame. + * This is used only by 68020 for trap exceptions. + */ + + +/* Bus error stack frame (68000 only). + */ +#if M68K_EMULATE_ADDRESS_ERROR +INLINE void m68ki_stack_frame_buserr(m68ki_cpu_core *m68k, UINT32 sr) +{ + m68ki_push_32(m68k, REG_PC); + m68ki_push_16(m68k, sr); + m68ki_push_16(m68k, m68k->ir); + m68ki_push_32(m68k, m68k->aerr_address); /* access address */ + /* 0 0 0 0 0 0 0 0 0 0 0 R/W I/N FC + * R/W 0 = write, 1 = read + * I/N 0 = instruction, 1 = not + * FC 3-bit function code + */ + m68ki_push_16(m68k, m68k->aerr_write_mode | m68k->instr_mode | m68k->aerr_fc); +} +#endif + +/* Format 8 stack frame (68010). + * 68010 only. This is the 29 word bus/address error frame. + */ +void m68ki_stack_frame_1000(m68ki_cpu_core *m68k, UINT32 pc, UINT32 sr, UINT32 vector) +{ + /* VERSION + * NUMBER + * INTERNAL INFORMATION, 16 WORDS + */ + m68ki_fake_push_32(m68k); + m68ki_fake_push_32(m68k); + m68ki_fake_push_32(m68k); + m68ki_fake_push_32(m68k); + m68ki_fake_push_32(m68k); + m68ki_fake_push_32(m68k); + m68ki_fake_push_32(m68k); + m68ki_fake_push_32(m68k); + + /* INSTRUCTION INPUT BUFFER */ + m68ki_push_16(m68k, 0); + + /* UNUSED, RESERVED (not written) */ + m68ki_fake_push_16(m68k); + + /* DATA INPUT BUFFER */ + m68ki_push_16(m68k, 0); + + /* UNUSED, RESERVED (not written) */ + m68ki_fake_push_16(m68k); + + /* DATA OUTPUT BUFFER */ + m68ki_push_16(m68k, 0); + + /* UNUSED, RESERVED (not written) */ + m68ki_fake_push_16(m68k); + + /* FAULT ADDRESS */ + m68ki_push_32(m68k, 0); + + /* SPECIAL STATUS WORD */ + m68ki_push_16(m68k, 0); + + /* 1000, VECTOR OFFSET */ + m68ki_push_16(m68k, 0x8000 | (vector<<2)); + + /* PROGRAM COUNTER */ + m68ki_push_32(m68k, pc); + + /* STATUS REGISTER */ + m68ki_push_16(m68k, sr); +} + +/* Format A stack frame (short bus fault). + * This is used only by 68020 for bus fault and address error + * if the error happens at an instruction boundary. + * PC stacked is address of next instruction. + */ +void m68ki_stack_frame_1010(m68ki_cpu_core *m68k, UINT32 sr, UINT32 vector, UINT32 pc) +{ + /* INTERNAL REGISTER */ + m68ki_push_16(m68k, 0); + + /* INTERNAL REGISTER */ + m68ki_push_16(m68k, 0); + + /* DATA OUTPUT BUFFER (2 words) */ + m68ki_push_32(m68k, 0); + + /* INTERNAL REGISTER */ + m68ki_push_16(m68k, 0); + + /* INTERNAL REGISTER */ + m68ki_push_16(m68k, 0); + + /* DATA CYCLE FAULT ADDRESS (2 words) */ + m68ki_push_32(m68k, 0); + + /* INSTRUCTION PIPE STAGE B */ + m68ki_push_16(m68k, 0); + + /* INSTRUCTION PIPE STAGE C */ + m68ki_push_16(m68k, 0); + + /* SPECIAL STATUS REGISTER */ + m68ki_push_16(m68k, 0); + + /* INTERNAL REGISTER */ + m68ki_push_16(m68k, 0); + + /* 1010, VECTOR OFFSET */ + m68ki_push_16(m68k, 0xa000 | (vector<<2)); + + /* PROGRAM COUNTER */ + m68ki_push_32(m68k, pc); + + /* STATUS REGISTER */ + m68ki_push_16(m68k, sr); +} + +/* Format B stack frame (long bus fault). + * This is used only by 68020 for bus fault and address error + * if the error happens during instruction execution. + * PC stacked is address of instruction in progress. + */ +void m68ki_stack_frame_1011(m68ki_cpu_core *m68k, UINT32 sr, UINT32 vector, UINT32 pc) +{ + /* INTERNAL REGISTERS (18 words) */ + m68ki_push_32(m68k, 0); + m68ki_push_32(m68k, 0); + m68ki_push_32(m68k, 0); + m68ki_push_32(m68k, 0); + m68ki_push_32(m68k, 0); + m68ki_push_32(m68k, 0); + m68ki_push_32(m68k, 0); + m68ki_push_32(m68k, 0); + m68ki_push_32(m68k, 0); + + /* VERSION# (4 bits), INTERNAL INFORMATION */ + m68ki_push_16(m68k, 0); + + /* INTERNAL REGISTERS (3 words) */ + m68ki_push_32(m68k, 0); + m68ki_push_16(m68k, 0); + + /* DATA INTPUT BUFFER (2 words) */ + m68ki_push_32(m68k, 0); + + /* INTERNAL REGISTERS (2 words) */ + m68ki_push_32(m68k, 0); + + /* STAGE B ADDRESS (2 words) */ + m68ki_push_32(m68k, 0); + + /* INTERNAL REGISTER (4 words) */ + m68ki_push_32(m68k, 0); + m68ki_push_32(m68k, 0); + + /* DATA OUTPUT BUFFER (2 words) */ + m68ki_push_32(m68k, 0); + + /* INTERNAL REGISTER */ + m68ki_push_16(m68k, 0); + + /* INTERNAL REGISTER */ + m68ki_push_16(m68k, 0); + + /* DATA CYCLE FAULT ADDRESS (2 words) */ + m68ki_push_32(m68k, 0); + + /* INSTRUCTION PIPE STAGE B */ + m68ki_push_16(m68k, 0); + + /* INSTRUCTION PIPE STAGE C */ + m68ki_push_16(m68k, 0); + + /* SPECIAL STATUS REGISTER */ + m68ki_push_16(m68k, 0); + + /* INTERNAL REGISTER */ + m68ki_push_16(m68k, 0); + + /* 1011, VECTOR OFFSET */ + m68ki_push_16(m68k, 0xb000 | (vector<<2)); + + /* PROGRAM COUNTER */ + m68ki_push_32(m68k, pc); + + /* STATUS REGISTER */ + m68ki_push_16(m68k, sr); +} + + +/* Used for Group 2 exceptions. + * These stack a type 2 frame on the 020. + */ +INLINE void m68ki_exception_trap(m68ki_cpu_core *m68k, UINT32 vector) +{ + UINT32 sr = m68ki_init_exception(m68k); + + m68ki_stack_frame_0000(m68k, REG_PC, sr, vector); + + m68ki_jump_vector(m68k, vector); + + /* Use up some clock cycles */ + m68k->remaining_cycles -= m68k->cyc_exception[vector]; +} + +/* Trap#n stacks a 0 frame but behaves like group2 otherwise */ +INLINE void m68ki_exception_trapN(m68ki_cpu_core *m68k, UINT32 vector) +{ + UINT32 sr = m68ki_init_exception(m68k); + m68ki_stack_frame_0000(m68k, REG_PC, sr, vector); + m68ki_jump_vector(m68k, vector); + + /* Use up some clock cycles */ + m68k->remaining_cycles -= m68k->cyc_exception[vector]; +} + +/* Exception for trace mode */ +INLINE void m68ki_exception_trace(m68ki_cpu_core *m68k) +{ + UINT32 sr = m68ki_init_exception(m68k); + + { +#if M68K_EMULATE_ADDRESS_ERROR + { + m68k->instr_mode = INSTRUCTION_NO; + } +#endif + m68ki_stack_frame_0000(m68k, REG_PC, sr, EXCEPTION_TRACE); + } + + m68ki_jump_vector(m68k, EXCEPTION_TRACE); + + /* Trace nullifies a STOP instruction */ + m68k->stopped &= ~STOP_LEVEL_STOP; + + /* Use up some clock cycles */ + m68k->remaining_cycles -= m68k->cyc_exception[EXCEPTION_TRACE]; +} + +/* Exception for privilege violation */ +INLINE void m68ki_exception_privilege_violation(m68ki_cpu_core *m68k) +{ + UINT32 sr = m68ki_init_exception(m68k); + +#if M68K_EMULATE_ADDRESS_ERROR + { + m68k->instr_mode = INSTRUCTION_NO; + } +#endif + + m68ki_stack_frame_0000(m68k, REG_PPC, sr, EXCEPTION_PRIVILEGE_VIOLATION); + m68ki_jump_vector(m68k, EXCEPTION_PRIVILEGE_VIOLATION); + + /* Use up some clock cycles and undo the instruction's cycles */ + m68k->remaining_cycles -= m68k->cyc_exception[EXCEPTION_PRIVILEGE_VIOLATION] - m68k->cyc_instruction[m68k->ir]; +} + +/* Exception for A-Line instructions */ +INLINE void m68ki_exception_1010(m68ki_cpu_core *m68k) +{ + UINT32 sr; + + sr = m68ki_init_exception(m68k); + m68ki_stack_frame_0000(m68k, REG_PPC, sr, EXCEPTION_1010); + m68ki_jump_vector(m68k, EXCEPTION_1010); + + /* Use up some clock cycles and undo the instruction's cycles */ + m68k->remaining_cycles -= m68k->cyc_exception[EXCEPTION_1010] - m68k->cyc_instruction[m68k->ir]; +} + +/* Exception for F-Line instructions */ +INLINE void m68ki_exception_1111(m68ki_cpu_core *m68k) +{ + UINT32 sr; + + sr = m68ki_init_exception(m68k); + m68ki_stack_frame_0000(m68k, REG_PPC, sr, EXCEPTION_1111); + m68ki_jump_vector(m68k, EXCEPTION_1111); + + /* Use up some clock cycles and undo the instruction's cycles */ + m68k->remaining_cycles -= m68k->cyc_exception[EXCEPTION_1111] - m68k->cyc_instruction[m68k->ir]; +} + +/* Exception for illegal instructions */ +INLINE void m68ki_exception_illegal(m68ki_cpu_core *m68k) +{ + UINT32 sr; + + sr = m68ki_init_exception(m68k); + +#if M68K_EMULATE_ADDRESS_ERROR + { + m68k->instr_mode = INSTRUCTION_NO; + } +#endif + + m68ki_stack_frame_0000(m68k, REG_PPC, sr, EXCEPTION_ILLEGAL_INSTRUCTION); + m68ki_jump_vector(m68k, EXCEPTION_ILLEGAL_INSTRUCTION); + + /* Use up some clock cycles and undo the instruction's cycles */ + m68k->remaining_cycles -= m68k->cyc_exception[EXCEPTION_ILLEGAL_INSTRUCTION] - m68k->cyc_instruction[m68k->ir]; +} + +/* Exception for format errror in RTE */ +INLINE void m68ki_exception_format_error(m68ki_cpu_core *m68k) +{ + UINT32 sr = m68ki_init_exception(m68k); + m68ki_stack_frame_0000(m68k, REG_PC, sr, EXCEPTION_FORMAT_ERROR); + m68ki_jump_vector(m68k, EXCEPTION_FORMAT_ERROR); + + /* Use up some clock cycles and undo the instruction's cycles */ + m68k->remaining_cycles -= m68k->cyc_exception[EXCEPTION_FORMAT_ERROR] - m68k->cyc_instruction[m68k->ir]; +} + +/* Exception for address error */ +#if M68K_EMULATE_ADDRESS_ERROR +INLINE void m68ki_exception_address_error(m68ki_cpu_core *m68k) +{ + UINT32 sr = m68ki_init_exception(m68k); + + /* If we were processing a bus error, address error, or reset, + * this is a catastrophic failure. + * Halt the CPU + */ + if(m68k->run_mode == RUN_MODE_BERR_AERR_RESET) + { + (*m68k->memory.read8)(m68k->program, 0x00ffff01); + m68k->stopped = STOP_LEVEL_HALT; + return; + } + m68k->run_mode = RUN_MODE_BERR_AERR_RESET; + + /* Note: This is implemented for 68000 only! */ + m68ki_stack_frame_buserr(m68k, sr); + + m68ki_jump_vector(m68k, EXCEPTION_ADDRESS_ERROR); + + /* Use up some clock cycles and undo the instruction's cycles */ + m68k->remaining_cycles -= m68k->cyc_exception[EXCEPTION_ADDRESS_ERROR] - m68k->cyc_instruction[m68k->ir]; +} +#endif + + +/* Service an interrupt request and start exception processing */ +void m68ki_exception_interrupt(m68ki_cpu_core *m68k, UINT32 int_level) +{ + UINT32 vector; + UINT32 sr; + UINT32 new_pc; + +#if M68K_EMULATE_ADDRESS_ERROR + { + m68k->instr_mode = INSTRUCTION_NO; + } +#endif + + /* Turn off the stopped state */ + m68k->stopped &= ~STOP_LEVEL_STOP; + + /* If we are halted, don't do anything */ + if(m68k->stopped) + return; + + vector = M68K_INT_ACK_AUTOVECTOR; + + /* Get the interrupt vector */ + if(vector == M68K_INT_ACK_AUTOVECTOR) + /* Use the autovectors. This is the most commonly used implementation */ + vector = EXCEPTION_INTERRUPT_AUTOVECTOR+int_level; + else if(vector == M68K_INT_ACK_SPURIOUS) + /* Called if no devices respond to the interrupt acknowledge */ + vector = EXCEPTION_SPURIOUS_INTERRUPT; + else if(vector > 255) + return; + + /* Start exception processing */ + sr = m68ki_init_exception(m68k); + + /* Set the interrupt mask to the level of the one being serviced */ + m68k->int_mask = int_level<<8; + + /* Get the new PC */ + new_pc = m68ki_read_data_32(m68k, (vector<<2)); + + /* If vector is uninitialized, call the uninitialized interrupt vector */ + if(new_pc == 0) + new_pc = m68ki_read_data_32(m68k, (EXCEPTION_UNINITIALIZED_INTERRUPT<<2)); + + /* Generate a stack frame */ + m68ki_stack_frame_0000(m68k, REG_PC, sr, vector); + + m68ki_jump(m68k, new_pc); + + /* Defer cycle counting until later */ + m68k->remaining_cycles -= m68k->cyc_exception[vector]; +} + + +/* ASG: Check for interrupts */ +INLINE void m68ki_check_interrupts(m68ki_cpu_core *m68k) +{ + if(m68k->nmi_pending) + { + m68k->nmi_pending = FALSE; + m68ki_exception_interrupt(m68k, 7); + } + else if(m68k->int_level > m68k->int_mask) + m68ki_exception_interrupt(m68k, m68k->int_level>>8); +} + + + +/* ======================================================================== */ +/* ============================== END OF FILE ============================= */ +/* ======================================================================== */ + +#endif /* __M68KCPU_H__ */ diff --git a/Frameworks/AudioOverload/aosdk/eng_ssf/m68kmake.c b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/m68k/m68kmake.c similarity index 77% rename from Frameworks/AudioOverload/aosdk/eng_ssf/m68kmake.c rename to Frameworks/HighlyTheoretical/HighlyTheoretical/Core/m68k/m68kmake.c index 00e244b9e..067988f87 100644 --- a/Frameworks/AudioOverload/aosdk/eng_ssf/m68kmake.c +++ b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/m68k/m68kmake.c @@ -3,22 +3,29 @@ /* ======================================================================== */ /* * MUSASHI - * Version 3.3 + * Version 4.55 * * A portable Motorola M680x0 processor emulation engine. - * Copyright 1998-2001 Karl Stenerud. All rights reserved. + * Copyright Karl Stenerud. All rights reserved. * * This code may be freely used for non-commercial purposes as long as this * copyright notice remains unaltered in the source code and any binary files * containing this code in compiled form. * - * All other lisencing terms must be negotiated with the author + * All other licensing terms must be negotiated with the author * (Karl Stenerud). * * The latest version of this code can be obtained at: - * http://kstenerud.cjb.net + * http://kstenerud.cjb.net or http://mamedev.org/ */ +/* + * Modified For OpenVMS By: Robert Alan Byer + * byer@mail.ourservers.net + * + * 68030 and PMMU by R. Belmont + * 68040 and FPU by Ville Linde + */ /* ======================================================================== */ @@ -48,7 +55,7 @@ */ -char* g_version = "3.3"; +static const char g_version[] = "4.55"; /* ======================================================================== */ /* =============================== INCLUDES =============================== */ @@ -69,7 +76,6 @@ char* g_version = "3.3"; #define M68K_MAX_PATH 1024 #define M68K_MAX_DIR 1024 -#define NUM_CPUS 3 /* 000, 010, 020 */ #define MAX_LINE_LENGTH 200 /* length of 1 line */ #define MAX_BODY_LENGTH 300 /* Number of lines in 1 function */ #define MAX_REPLACE_LENGTH 30 /* Max number of replace strings */ @@ -85,9 +91,6 @@ char* g_version = "3.3"; #define FILENAME_INPUT "m68k_in.c" #define FILENAME_PROTOTYPE "m68kops.h" #define FILENAME_TABLE "m68kops.c" -#define FILENAME_OPS_AC "m68kopac.c" -#define FILENAME_OPS_DM "m68kopdm.c" -#define FILENAME_OPS_NZ "m68kopnz.c" /* Identifier sequences recognized by this program */ @@ -127,9 +130,15 @@ char* g_version = "3.3"; /* ============================== PROTOTYPES ============================== */ /* ======================================================================== */ -#define CPU_TYPE_000 0 -#define CPU_TYPE_010 1 -#define CPU_TYPE_020 2 +enum +{ + CPU_TYPE_000 = 0, + CPU_TYPE_010, + CPU_TYPE_020, + CPU_TYPE_030, + CPU_TYPE_040, + NUM_CPUS +}; #define UNSPECIFIED "." #define UNSPECIFIED_CH '.' @@ -177,15 +186,15 @@ typedef struct char ea_allowed[EA_ALLOWED_LENGTH]; /* Effective addressing modes allowed */ char cpu_mode[NUM_CPUS]; /* User or supervisor mode */ char cpus[NUM_CPUS+1]; /* Allowed CPUs */ - unsigned char cycles[NUM_CPUS]; /* cycles for 000, 010, 020 */ + unsigned char cycles[NUM_CPUS]; /* cycles for 000, 010, 020, 030, 040 */ } opcode_struct; /* All modifications necessary for a specific EA mode of an instruction */ typedef struct { - char* fname_add; - char* ea_add; + const char* fname_add; + const char* ea_add; unsigned int mask_add; unsigned int match_add; } ea_info_struct; @@ -208,34 +217,33 @@ typedef struct /* Function Prototypes */ -void error_exit(char* fmt, ...); -void perror_exit(char* fmt, ...); -int check_strsncpy(char* dst, char* src, int maxlength); -int check_atoi(char* str, int *result); -int skip_spaces(char* str); -int num_bits(int value); -int atoh(char* buff); -int fgetline(char* buff, int nchars, FILE* file); -int get_oper_cycles(opcode_struct* op, int ea_mode, int cpu_type); -opcode_struct* find_opcode(char* name, int size, char* spec_proc, char* spec_ea); -opcode_struct* find_illegal_opcode(void); -int extract_opcode_info(char* src, char* name, int* size, char* spec_proc, char* spec_ea); -void add_replace_string(replace_struct* replace, char* search_str, char* replace_str); -void write_body(FILE* filep, body_struct* body, replace_struct* replace); -void get_base_name(char* base_name, opcode_struct* op); -void write_prototype(FILE* filep, char* base_name); -void write_function_name(FILE* filep, char* base_name); -void add_opcode_output_table_entry(opcode_struct* op, char* name); +static void error_exit(const char* fmt, ...); +static void perror_exit(const char* fmt, ...); +static int check_strsncpy(char* dst, char* src, int maxlength); +static int check_atoi(char* str, int *result); +static int skip_spaces(char* str); +static int num_bits(int value); +//int atoh(char* buff); +static int fgetline(char* buff, int nchars, FILE* file); +static int get_oper_cycles(opcode_struct* op, int ea_mode, int cpu_type); +static opcode_struct* find_opcode(char* name, int size, char* spec_proc, char* spec_ea); +//opcode_struct* find_illegal_opcode(void); +static int extract_opcode_info(char* src, char* name, int* size, char* spec_proc, char* spec_ea); +static void add_replace_string(replace_struct* replace, const char* search_str, const char* replace_str); +static void write_body(FILE* filep, body_struct* body, replace_struct* replace); +static void get_base_name(char* base_name, opcode_struct* op); +static void write_function_name(FILE* filep, char* base_name); +static void add_opcode_output_table_entry(opcode_struct* op, char* name); static int DECL_SPEC compare_nof_true_bits(const void* aptr, const void* bptr); -void print_opcode_output_table(FILE* filep); -void write_table_entry(FILE* filep, opcode_struct* op); -void set_opcode_struct(opcode_struct* src, opcode_struct* dst, int ea_mode); -void generate_opcode_handler(FILE* filep, body_struct* body, replace_struct* replace, opcode_struct* opinfo, int ea_mode); -void generate_opcode_ea_variants(FILE* filep, body_struct* body, replace_struct* replace, opcode_struct* op); -void generate_opcode_cc_variants(FILE* filep, body_struct* body, replace_struct* replace, opcode_struct* op_in, int offset); -void process_opcode_handlers(void); -void populate_table(void); -void read_insert(char* insert); +static void print_opcode_output_table(FILE* filep); +static void write_table_entry(FILE* filep, opcode_struct* op); +static void set_opcode_struct(opcode_struct* src, opcode_struct* dst, int ea_mode); +static void generate_opcode_handler(FILE* filep, body_struct* body, replace_struct* replace, opcode_struct* opinfo, int ea_mode); +static void generate_opcode_ea_variants(FILE* filep, body_struct* body, replace_struct* replace, opcode_struct* op); +static void generate_opcode_cc_variants(FILE* filep, body_struct* body, replace_struct* replace, opcode_struct* op_in, int offset); +static void process_opcode_handlers(FILE* filep); +static void populate_table(void); +static void read_insert(char* insert); @@ -244,27 +252,24 @@ void read_insert(char* insert); /* ======================================================================== */ /* Name of the input file */ -char g_input_filename[M68K_MAX_PATH] = FILENAME_INPUT; +static char g_input_filename[M68K_MAX_PATH]; /* File handles */ -FILE* g_input_file = NULL; -FILE* g_prototype_file = NULL; -FILE* g_table_file = NULL; -FILE* g_ops_ac_file = NULL; -FILE* g_ops_dm_file = NULL; -FILE* g_ops_nz_file = NULL; +static FILE* g_input_file = NULL; +static FILE* g_prototype_file = NULL; +static FILE* g_table_file = NULL; -int g_num_functions = 0; /* Number of functions processed */ -int g_num_primitives = 0; /* Number of function primitives read */ -int g_line_number = 1; /* Current line number */ +static int g_num_functions = 0; /* Number of functions processed */ +static int g_num_primitives = 0; /* Number of function primitives read */ +static int g_line_number = 1; /* Current line number */ /* Opcode handler table */ -opcode_struct g_opcode_input_table[MAX_OPCODE_INPUT_TABLE_LENGTH]; +static opcode_struct g_opcode_input_table[MAX_OPCODE_INPUT_TABLE_LENGTH]; -opcode_struct g_opcode_output_table[MAX_OPCODE_OUTPUT_TABLE_LENGTH]; -int g_opcode_output_table_length = 0; +static opcode_struct g_opcode_output_table[MAX_OPCODE_OUTPUT_TABLE_LENGTH]; +static int g_opcode_output_table_length = 0; -ea_info_struct g_ea_info_table[13] = +static const ea_info_struct g_ea_info_table[13] = {/* fname ea mask match */ {"", "", 0x00, 0x00}, /* EA_MODE_NONE */ {"ai", "AY_AI", 0x38, 0x10}, /* EA_MODE_AI */ @@ -282,7 +287,7 @@ ea_info_struct g_ea_info_table[13] = }; -char* g_cc_table[16][2] = +static const char *const g_cc_table[16][2] = { { "t", "T"}, /* 0000 */ { "f", "F"}, /* 0001 */ @@ -303,7 +308,7 @@ char* g_cc_table[16][2] = }; /* size to index translator (0 -> 0, 8 and 16 -> 1, 32 -> 2) */ -int g_size_select_table[33] = +static const int g_size_select_table[33] = { 0, /* unsized */ 0, 0, 0, 0, 0, 0, 0, 1, /* 8 */ @@ -312,25 +317,26 @@ int g_size_select_table[33] = }; /* Extra cycles required for certain EA modes */ -int g_ea_cycle_table[13][NUM_CPUS][3] = -{/* 000 010 020 */ - {{ 0, 0, 0}, { 0, 0, 0}, { 0, 0, 0}}, /* EA_MODE_NONE */ - {{ 0, 4, 8}, { 0, 4, 8}, { 0, 4, 4}}, /* EA_MODE_AI */ - {{ 0, 4, 8}, { 0, 4, 8}, { 0, 4, 4}}, /* EA_MODE_PI */ - {{ 0, 4, 8}, { 0, 4, 8}, { 0, 4, 4}}, /* EA_MODE_PI7 */ - {{ 0, 6, 10}, { 0, 6, 10}, { 0, 5, 5}}, /* EA_MODE_PD */ - {{ 0, 6, 10}, { 0, 6, 10}, { 0, 5, 5}}, /* EA_MODE_PD7 */ - {{ 0, 8, 12}, { 0, 8, 12}, { 0, 5, 5}}, /* EA_MODE_DI */ - {{ 0, 10, 14}, { 0, 10, 14}, { 0, 7, 7}}, /* EA_MODE_IX */ - {{ 0, 8, 12}, { 0, 8, 12}, { 0, 4, 4}}, /* EA_MODE_AW */ - {{ 0, 12, 16}, { 0, 12, 16}, { 0, 4, 4}}, /* EA_MODE_AL */ - {{ 0, 8, 12}, { 0, 8, 12}, { 0, 5, 5}}, /* EA_MODE_PCDI */ - {{ 0, 10, 14}, { 0, 10, 14}, { 0, 7, 7}}, /* EA_MODE_PCIX */ - {{ 0, 4, 8}, { 0, 4, 8}, { 0, 2, 4}}, /* EA_MODE_I */ +/* TODO: correct timings for 030, 040 */ +static const int g_ea_cycle_table[13][NUM_CPUS][3] = +{/* 000 010 020 030 040 */ + {{ 0, 0, 0}, { 0, 0, 0}, { 0, 0, 0}, { 0, 0, 0}, { 0, 0, 0}}, /* EA_MODE_NONE */ + {{ 0, 4, 8}, { 0, 4, 8}, { 0, 4, 4}, { 0, 4, 4}, { 0, 4, 4}}, /* EA_MODE_AI */ + {{ 0, 4, 8}, { 0, 4, 8}, { 0, 4, 4}, { 0, 4, 4}, { 0, 4, 4}}, /* EA_MODE_PI */ + {{ 0, 4, 8}, { 0, 4, 8}, { 0, 4, 4}, { 0, 4, 4}, { 0, 4, 4}}, /* EA_MODE_PI7 */ + {{ 0, 6, 10}, { 0, 6, 10}, { 0, 5, 5}, { 0, 5, 5}, { 0, 5, 5}}, /* EA_MODE_PD */ + {{ 0, 6, 10}, { 0, 6, 10}, { 0, 5, 5}, { 0, 5, 5}, { 0, 5, 5}}, /* EA_MODE_PD7 */ + {{ 0, 8, 12}, { 0, 8, 12}, { 0, 5, 5}, { 0, 5, 5}, { 0, 5, 5}}, /* EA_MODE_DI */ + {{ 0, 10, 14}, { 0, 10, 14}, { 0, 7, 7}, { 0, 7, 7}, { 0, 7, 7}}, /* EA_MODE_IX */ + {{ 0, 8, 12}, { 0, 8, 12}, { 0, 4, 4}, { 0, 4, 4}, { 0, 4, 4}}, /* EA_MODE_AW */ + {{ 0, 12, 16}, { 0, 12, 16}, { 0, 4, 4}, { 0, 4, 4}, { 0, 4, 4}}, /* EA_MODE_AL */ + {{ 0, 8, 12}, { 0, 8, 12}, { 0, 5, 5}, { 0, 5, 5}, { 0, 5, 5}}, /* EA_MODE_PCDI */ + {{ 0, 10, 14}, { 0, 10, 14}, { 0, 7, 7}, { 0, 7, 7}, { 0, 7, 7}}, /* EA_MODE_PCIX */ + {{ 0, 4, 8}, { 0, 4, 8}, { 0, 2, 4}, { 0, 2, 4}, { 0, 2, 4}}, /* EA_MODE_I */ }; /* Extra cycles for JMP instruction (000, 010) */ -int g_jmp_cycle_table[13] = +static const int g_jmp_cycle_table[13] = { 0, /* EA_MODE_NONE */ 4, /* EA_MODE_AI */ @@ -339,7 +345,7 @@ int g_jmp_cycle_table[13] = 0, /* EA_MODE_PD */ 0, /* EA_MODE_PD7 */ 6, /* EA_MODE_DI */ - 8, /* EA_MODE_IX */ + 10, /* EA_MODE_IX */ 6, /* EA_MODE_AW */ 8, /* EA_MODE_AL */ 6, /* EA_MODE_PCDI */ @@ -348,7 +354,7 @@ int g_jmp_cycle_table[13] = }; /* Extra cycles for JSR instruction (000, 010) */ -int g_jsr_cycle_table[13] = +static const int g_jsr_cycle_table[13] = { 0, /* EA_MODE_NONE */ 4, /* EA_MODE_AI */ @@ -366,7 +372,7 @@ int g_jsr_cycle_table[13] = }; /* Extra cycles for LEA instruction (000, 010) */ -int g_lea_cycle_table[13] = +static const int g_lea_cycle_table[13] = { 0, /* EA_MODE_NONE */ 4, /* EA_MODE_AI */ @@ -384,10 +390,10 @@ int g_lea_cycle_table[13] = }; /* Extra cycles for PEA instruction (000, 010) */ -int g_pea_cycle_table[13] = +static const int g_pea_cycle_table[13] = { 0, /* EA_MODE_NONE */ - 4, /* EA_MODE_AI */ + 6, /* EA_MODE_AI */ 0, /* EA_MODE_PI */ 0, /* EA_MODE_PI7 */ 0, /* EA_MODE_PD */ @@ -401,8 +407,26 @@ int g_pea_cycle_table[13] = 0, /* EA_MODE_I */ }; +/* Extra cycles for MOVEM instruction (000, 010) */ +static const int g_movem_cycle_table[13] = +{ + 0, /* EA_MODE_NONE */ + 0, /* EA_MODE_AI */ + 0, /* EA_MODE_PI */ + 0, /* EA_MODE_PI7 */ + 0, /* EA_MODE_PD */ + 0, /* EA_MODE_PD7 */ + 4, /* EA_MODE_DI */ + 6, /* EA_MODE_IX */ + 4, /* EA_MODE_AW */ + 8, /* EA_MODE_AL */ + 0, /* EA_MODE_PCDI */ + 0, /* EA_MODE_PCIX */ + 0, /* EA_MODE_I */ +}; + /* Extra cycles for MOVES instruction (010) */ -int g_moves_cycle_table[13][3] = +static const int g_moves_cycle_table[13][3] = { { 0, 0, 0}, /* EA_MODE_NONE */ { 0, 4, 6}, /* EA_MODE_AI */ @@ -420,7 +444,7 @@ int g_moves_cycle_table[13][3] = }; /* Extra cycles for CLR instruction (010) */ -int g_clr_cycle_table[13][3] = +static const int g_clr_cycle_table[13][3] = { { 0, 0, 0}, /* EA_MODE_NONE */ { 0, 4, 6}, /* EA_MODE_AI */ @@ -444,7 +468,7 @@ int g_clr_cycle_table[13][3] = /* ======================================================================== */ /* Print an error message and exit with status error */ -void error_exit(char* fmt, ...) +static void error_exit(const char* fmt, ...) { va_list args; fprintf(stderr, "In %s, near or on line %d:\n\t", g_input_filename, g_line_number); @@ -455,16 +479,13 @@ void error_exit(char* fmt, ...) if(g_prototype_file) fclose(g_prototype_file); if(g_table_file) fclose(g_table_file); - if(g_ops_ac_file) fclose(g_ops_ac_file); - if(g_ops_dm_file) fclose(g_ops_dm_file); - if(g_ops_nz_file) fclose(g_ops_nz_file); if(g_input_file) fclose(g_input_file); exit(EXIT_FAILURE); } /* Print an error message, call perror(), and exit with status error */ -void perror_exit(char* fmt, ...) +static void perror_exit(const char* fmt, ...) { va_list args; va_start(args, fmt); @@ -474,9 +495,6 @@ void perror_exit(char* fmt, ...) if(g_prototype_file) fclose(g_prototype_file); if(g_table_file) fclose(g_table_file); - if(g_ops_ac_file) fclose(g_ops_ac_file); - if(g_ops_dm_file) fclose(g_ops_dm_file); - if(g_ops_nz_file) fclose(g_ops_nz_file); if(g_input_file) fclose(g_input_file); exit(EXIT_FAILURE); @@ -484,7 +502,7 @@ void perror_exit(char* fmt, ...) /* copy until 0 or space and exit with error if we read too far */ -int check_strsncpy(char* dst, char* src, int maxlength) +static int check_strsncpy(char* dst, char* src, int maxlength) { char* p = dst; while(*src && *src != ' ') @@ -498,7 +516,7 @@ int check_strsncpy(char* dst, char* src, int maxlength) } /* copy until 0 or specified character and exit with error if we read too far */ -int check_strcncpy(char* dst, char* src, char delim, int maxlength) +static int check_strcncpy(char* dst, char* src, char delim, int maxlength) { char* p = dst; while(*src && *src != delim) @@ -512,7 +530,7 @@ int check_strcncpy(char* dst, char* src, char delim, int maxlength) } /* convert ascii to integer and exit with error if we find invalid data */ -int check_atoi(char* str, int *result) +static int check_atoi(char* str, int *result) { int accum = 0; char* p = str; @@ -528,7 +546,7 @@ int check_atoi(char* str, int *result) } /* Skip past spaces in a string */ -int skip_spaces(char* str) +static int skip_spaces(char* str) { char* p = str; @@ -539,7 +557,7 @@ int skip_spaces(char* str) } /* Count the number of set bits in a value */ -int num_bits(int value) +static int num_bits(int value) { value = ((value & 0xaaaa) >> 1) + (value & 0x5555); value = ((value & 0xcccc) >> 2) + (value & 0x3333); @@ -548,6 +566,7 @@ int num_bits(int value) return value; } +#ifdef UNUSED_FUNCTION /* Convert a hex value written in ASCII */ int atoh(char* buff) { @@ -569,9 +588,10 @@ int atoh(char* buff) } return accum; } +#endif /* Get a line of text from a file, discarding any end-of-line characters */ -int fgetline(char* buff, int nchars, FILE* file) +static int fgetline(char* buff, int nchars, FILE* file) { int length; @@ -596,7 +616,7 @@ int fgetline(char* buff, int nchars, FILE* file) /* ======================================================================== */ /* Calculate the number of cycles an opcode requires */ -int get_oper_cycles(opcode_struct* op, int ea_mode, int cpu_type) +static int get_oper_cycles(opcode_struct* op, int ea_mode, int cpu_type) { int size = g_size_select_table[op->size]; @@ -614,7 +634,8 @@ int get_oper_cycles(opcode_struct* op, int ea_mode, int cpu_type) } /* ASG: added these cases -- immediate modes take 2 extra cycles here */ - if(cpu_type == CPU_TYPE_000 && ea_mode == EA_MODE_I && + /* SV: but only when operating on long, and also on register direct mode */ + if(cpu_type == CPU_TYPE_000 && (ea_mode == EA_MODE_I || ea_mode == EA_MODE_NONE) && op->size == 32 && ((strcmp(op->name, "add") == 0 && strcmp(op->spec_proc, "er") == 0) || strcmp(op->name, "adda") == 0 || (strcmp(op->name, "and") == 0 && strcmp(op->spec_proc, "er") == 0) || @@ -631,12 +652,14 @@ int get_oper_cycles(opcode_struct* op, int ea_mode, int cpu_type) return op->cycles[cpu_type] + g_lea_cycle_table[ea_mode]; if(strcmp(op->name, "pea") == 0) return op->cycles[cpu_type] + g_pea_cycle_table[ea_mode]; + if(strcmp(op->name, "movem") == 0) + return op->cycles[cpu_type] + g_movem_cycle_table[ea_mode]; } return op->cycles[cpu_type] + g_ea_cycle_table[ea_mode][cpu_type][size]; } /* Find an opcode in the opcode handler list */ -opcode_struct* find_opcode(char* name, int size, char* spec_proc, char* spec_ea) +static opcode_struct* find_opcode(char* name, int size, char* spec_proc, char* spec_ea) { opcode_struct* op; @@ -652,6 +675,7 @@ opcode_struct* find_opcode(char* name, int size, char* spec_proc, char* spec_ea) return NULL; } +#ifdef UNUSED_FUNCTION /* Specifically find the illegal opcode in the list */ opcode_struct* find_illegal_opcode(void) { @@ -664,9 +688,10 @@ opcode_struct* find_illegal_opcode(void) } return NULL; } +#endif /* Parse an opcode handler name */ -int extract_opcode_info(char* src, char* name, int* size, char* spec_proc, char* spec_ea) +static int extract_opcode_info(char* src, char* name, int* size, char* spec_proc, char* spec_ea) { char* ptr = strstr(src, ID_OPHANDLER_NAME); @@ -701,7 +726,7 @@ int extract_opcode_info(char* src, char* name, int* size, char* spec_proc, char* /* Add a search/replace pair to a replace structure */ -void add_replace_string(replace_struct* replace, char* search_str, char* replace_str) +static void add_replace_string(replace_struct* replace, const char* search_str, const char* replace_str) { if(replace->length >= MAX_REPLACE_LENGTH) error_exit("overflow in replace structure"); @@ -711,7 +736,7 @@ void add_replace_string(replace_struct* replace, char* search_str, char* replace } /* Write a function body while replacing any selected strings */ -void write_body(FILE* filep, body_struct* body, replace_struct* replace) +static void write_body(FILE* filep, body_struct* body, replace_struct* replace) { int i; int j; @@ -742,7 +767,7 @@ void write_body(FILE* filep, body_struct* body, replace_struct* replace) } /* Found a directive with no matching replace string */ if(!found) - error_exit("Unknown " ID_BASE " directive"); + error_exit("Unknown " ID_BASE " directive [%s]", output); } fprintf(filep, "%s\n", output); } @@ -750,7 +775,7 @@ void write_body(FILE* filep, body_struct* body, replace_struct* replace) } /* Generate a base function name from an opcode struct */ -void get_base_name(char* base_name, opcode_struct* op) +static void get_base_name(char* base_name, opcode_struct* op) { sprintf(base_name, "m68k_op_%s", op->name); if(op->size > 0) @@ -761,19 +786,13 @@ void get_base_name(char* base_name, opcode_struct* op) sprintf(base_name+strlen(base_name), "_%s", op->spec_ea); } -/* Write the prototype of an opcode handler function */ -void write_prototype(FILE* filep, char* base_name) -{ - fprintf(filep, "void %s(void);\n", base_name); -} - /* Write the name of an opcode handler function */ -void write_function_name(FILE* filep, char* base_name) +static void write_function_name(FILE* filep, char* base_name) { - fprintf(filep, "void %s(void)\n", base_name); + fprintf(filep, "static void %s(m68ki_cpu_core *m68k)\n", base_name); } -void add_opcode_output_table_entry(opcode_struct* op, char* name) +static void add_opcode_output_table_entry(opcode_struct* op, char* name) { opcode_struct* ptr; if(g_opcode_output_table_length > MAX_OPCODE_OUTPUT_TABLE_LENGTH) @@ -793,7 +812,7 @@ void add_opcode_output_table_entry(opcode_struct* op, char* name) */ static int DECL_SPEC compare_nof_true_bits(const void* aptr, const void* bptr) { - const opcode_struct *a = aptr, *b = bptr; + const opcode_struct *a = (const opcode_struct *)aptr, *b = (const opcode_struct *)bptr; if(a->bits != b->bits) return a->bits - b->bits; if(a->op_mask != b->op_mask) @@ -801,7 +820,7 @@ static int DECL_SPEC compare_nof_true_bits(const void* aptr, const void* bptr) return a->op_match - b->op_match; } -void print_opcode_output_table(FILE* filep) +static void print_opcode_output_table(FILE* filep) { int i; qsort((void *)g_opcode_output_table, g_opcode_output_table_length, sizeof(g_opcode_output_table[0]), compare_nof_true_bits); @@ -811,7 +830,7 @@ void print_opcode_output_table(FILE* filep) } /* Write an entry in the opcode handler table */ -void write_table_entry(FILE* filep, opcode_struct* op) +static void write_table_entry(FILE* filep, opcode_struct* op) { int i; @@ -829,7 +848,7 @@ void write_table_entry(FILE* filep, opcode_struct* op) } /* Fill out an opcode struct with a specific addressing mode of the source opcode struct */ -void set_opcode_struct(opcode_struct* src, opcode_struct* dst, int ea_mode) +static void set_opcode_struct(opcode_struct* src, opcode_struct* dst, int ea_mode) { int i; @@ -845,32 +864,31 @@ void set_opcode_struct(opcode_struct* src, opcode_struct* dst, int ea_mode) /* Generate a final opcode handler from the provided data */ -void generate_opcode_handler(FILE* filep, body_struct* body, replace_struct* replace, opcode_struct* opinfo, int ea_mode) +static void generate_opcode_handler(FILE* filep, body_struct* body, replace_struct* replace, opcode_struct* opinfo, int ea_mode) { char str[MAX_LINE_LENGTH+1]; - opcode_struct* op = malloc(sizeof(opcode_struct)); + opcode_struct* op = (opcode_struct *)malloc(sizeof(opcode_struct)); /* Set the opcode structure and write the tables, prototypes, etc */ set_opcode_struct(opinfo, op, ea_mode); get_base_name(str, op); - write_prototype(g_prototype_file, str); add_opcode_output_table_entry(op, str); write_function_name(filep, str); /* Add any replace strings needed */ if(ea_mode != EA_MODE_NONE) { - sprintf(str, "EA_%s_8()", g_ea_info_table[ea_mode].ea_add); + sprintf(str, "EA_%s_8(m68k)", g_ea_info_table[ea_mode].ea_add); add_replace_string(replace, ID_OPHANDLER_EA_AY_8, str); - sprintf(str, "EA_%s_16()", g_ea_info_table[ea_mode].ea_add); + sprintf(str, "EA_%s_16(m68k)", g_ea_info_table[ea_mode].ea_add); add_replace_string(replace, ID_OPHANDLER_EA_AY_16, str); - sprintf(str, "EA_%s_32()", g_ea_info_table[ea_mode].ea_add); + sprintf(str, "EA_%s_32(m68k)", g_ea_info_table[ea_mode].ea_add); add_replace_string(replace, ID_OPHANDLER_EA_AY_32, str); - sprintf(str, "OPER_%s_8()", g_ea_info_table[ea_mode].ea_add); + sprintf(str, "OPER_%s_8(m68k)", g_ea_info_table[ea_mode].ea_add); add_replace_string(replace, ID_OPHANDLER_OPER_AY_8, str); - sprintf(str, "OPER_%s_16()", g_ea_info_table[ea_mode].ea_add); + sprintf(str, "OPER_%s_16(m68k)", g_ea_info_table[ea_mode].ea_add); add_replace_string(replace, ID_OPHANDLER_OPER_AY_16, str); - sprintf(str, "OPER_%s_32()", g_ea_info_table[ea_mode].ea_add); + sprintf(str, "OPER_%s_32(m68k)", g_ea_info_table[ea_mode].ea_add); add_replace_string(replace, ID_OPHANDLER_OPER_AY_32, str); } @@ -881,7 +899,7 @@ void generate_opcode_handler(FILE* filep, body_struct* body, replace_struct* rep } /* Generate opcode variants based on available addressing modes */ -void generate_opcode_ea_variants(FILE* filep, body_struct* body, replace_struct* replace, opcode_struct* op) +static void generate_opcode_ea_variants(FILE* filep, body_struct* body, replace_struct* replace, opcode_struct* op) { int old_length = replace->length; @@ -936,13 +954,13 @@ void generate_opcode_ea_variants(FILE* filep, body_struct* body, replace_struct* } /* Generate variants of condition code opcodes */ -void generate_opcode_cc_variants(FILE* filep, body_struct* body, replace_struct* replace, opcode_struct* op_in, int offset) +static void generate_opcode_cc_variants(FILE* filep, body_struct* body, replace_struct* replace, opcode_struct* op_in, int offset) { char repl[20]; char replnot[20]; int i; int old_length = replace->length; - opcode_struct* op = malloc(sizeof(opcode_struct)); + opcode_struct* op = (opcode_struct *)malloc(sizeof(opcode_struct)); *op = *op_in; @@ -952,8 +970,8 @@ void generate_opcode_cc_variants(FILE* filep, body_struct* body, replace_struct* for(i=2;i<16;i++) { /* Add replace strings for this condition code */ - sprintf(repl, "COND_%s()", g_cc_table[i][1]); - sprintf(replnot, "COND_NOT_%s()", g_cc_table[i][1]); + sprintf(repl, "COND_%s(m68k)", g_cc_table[i][1]); + sprintf(replnot, "COND_NOT_%s(m68k)", g_cc_table[i][1]); add_replace_string(replace, ID_OPHANDLER_CC, repl); add_replace_string(replace, ID_OPHANDLER_NOT_CC, replnot); @@ -972,21 +990,17 @@ void generate_opcode_cc_variants(FILE* filep, body_struct* body, replace_struct* } /* Process the opcode handlers section of the input file */ -void process_opcode_handlers(void) +static void process_opcode_handlers(FILE* filep) { FILE* input_file = g_input_file; - FILE* output_file; char func_name[MAX_LINE_LENGTH+1]; char oper_name[MAX_LINE_LENGTH+1]; - int oper_size; + int oper_size = 0; char oper_spec_proc[MAX_LINE_LENGTH+1]; char oper_spec_ea[MAX_LINE_LENGTH+1]; opcode_struct* opinfo; - replace_struct* replace = malloc(sizeof(replace_struct)); - body_struct* body = malloc(sizeof(body_struct)); - - - output_file = g_ops_ac_file; + replace_struct* replace = (replace_struct*)malloc(sizeof(replace_struct)); + body_struct* body = (body_struct*)malloc(sizeof(body_struct)); for(;;) { @@ -1030,23 +1044,17 @@ void process_opcode_handlers(void) if(opinfo == NULL) error_exit("Unable to find matching table entry for %s", func_name); - /* Change output files if we pass 'c' or 'n' */ - if(output_file == g_ops_ac_file && oper_name[0] > 'c') - output_file = g_ops_dm_file; - else if(output_file == g_ops_dm_file && oper_name[0] > 'm') - output_file = g_ops_nz_file; - replace->length = 0; /* Generate opcode variants */ if(strcmp(opinfo->name, "bcc") == 0 || strcmp(opinfo->name, "scc") == 0) - generate_opcode_cc_variants(output_file, body, replace, opinfo, 1); + generate_opcode_cc_variants(filep, body, replace, opinfo, 1); else if(strcmp(opinfo->name, "dbcc") == 0) - generate_opcode_cc_variants(output_file, body, replace, opinfo, 2); + generate_opcode_cc_variants(filep, body, replace, opinfo, 2); else if(strcmp(opinfo->name, "trapcc") == 0) - generate_opcode_cc_variants(output_file, body, replace, opinfo, 4); + generate_opcode_cc_variants(filep, body, replace, opinfo, 4); else - generate_opcode_ea_variants(output_file, body, replace, opinfo); + generate_opcode_ea_variants(filep, body, replace, opinfo); } free(replace); @@ -1055,7 +1063,7 @@ void process_opcode_handlers(void) /* Populate the opcode handler table from the input file */ -void populate_table(void) +static void populate_table(void) { char* ptr; char bitpattern[17]; @@ -1069,13 +1077,13 @@ void populate_table(void) /* Find the start of the table */ while(strcmp(buff, ID_TABLE_START) != 0) if(fgetline(buff, MAX_LINE_LENGTH, g_input_file) < 0) - error_exit("Premature EOF while reading table"); + error_exit("(table_start) Premature EOF while reading table"); /* Process the entire table */ for(op = g_opcode_input_table;;op++) { if(fgetline(buff, MAX_LINE_LENGTH, g_input_file) < 0) - error_exit("Premature EOF while reading table"); + error_exit("(inline) Premature EOF while reading table"); if(strlen(buff) == 0) continue; /* We finish when we find an input separator */ @@ -1150,7 +1158,7 @@ void populate_table(void) } /* Read a header or footer insert from the input file */ -void read_insert(char* insert) +static void read_insert(char* insert) { char* ptr = insert; char* overflow = insert + MAX_INSERT_LENGTH - MAX_LINE_LENGTH; @@ -1209,7 +1217,7 @@ void read_insert(char* insert) /* ============================= MAIN FUNCTION ============================ */ /* ======================================================================== */ -int main(int argc, char **argv) +int main(int argc, char *argv[]) { /* File stuff */ char output_path[M68K_MAX_DIR] = ""; @@ -1219,7 +1227,9 @@ int main(int argc, char **argv) /* Inserts */ char temp_insert[MAX_INSERT_LENGTH+1]; char prototype_footer_insert[MAX_INSERT_LENGTH+1]; + char table_header_insert[MAX_INSERT_LENGTH+1]; char table_footer_insert[MAX_INSERT_LENGTH+1]; + char ophandler_header_insert[MAX_INSERT_LENGTH+1]; char ophandler_footer_insert[MAX_INSERT_LENGTH+1]; /* Flags if we've processed certain parts already */ int prototype_header_read = 0; @@ -1231,23 +1241,42 @@ int main(int argc, char **argv) int table_body_read = 0; int ophandler_body_read = 0; - printf("\n\t\tMusashi v%s 68000, 68010, 68EC020, 68020 emulator\n", g_version); - printf("\t\tCopyright 1998-2000 Karl Stenerud (karl@mame.net)\n\n"); + printf("\n\tMusashi v%s 68000, 68008, 68010, 68EC020, 68020, 68EC030, 68030, 68EC040, 68040 emulator\n", g_version); + printf("\tCopyright Karl Stenerud\n\n"); /* Check if output path and source for the input file are given */ - if(argc > 1) + if(argc > 1) { char *ptr; strcpy(output_path, argv[1]); for(ptr = strchr(output_path, '\\'); ptr; ptr = strchr(ptr, '\\')) *ptr = '/'; - if(output_path[strlen(output_path)-1] != '/') + +#if !(defined(__DECC) && defined(VMS)) + if(output_path[strlen(output_path)-1] != '/') strcat(output_path, "/"); - if(argc > 2) - strcpy(g_input_filename, argv[2]); +#endif } + strcpy(g_input_filename, (argc > 2) ? argv[2] : FILENAME_INPUT); + +#if defined(__DECC) && defined(VMS) + + /* Open the files we need */ + sprintf(filename, "%s%s", output_path, FILENAME_PROTOTYPE); + if((g_prototype_file = fopen(filename, "w")) == NULL) + perror_exit("Unable to create prototype file (%s)\n", filename); + + sprintf(filename, "%s%s", output_path, FILENAME_TABLE); + if((g_table_file = fopen(filename, "w")) == NULL) + perror_exit("Unable to create table file (%s)\n", filename); + + if((g_input_file=fopen(g_input_filename, "r")) == NULL) + perror_exit("can't open %s for input", g_input_filename); + +#else + /* Open the files we need */ sprintf(filename, "%s%s", output_path, FILENAME_PROTOTYPE); @@ -1258,21 +1287,10 @@ int main(int argc, char **argv) if((g_table_file = fopen(filename, "wt")) == NULL) perror_exit("Unable to create table file (%s)\n", filename); - sprintf(filename, "%s%s", output_path, FILENAME_OPS_AC); - if((g_ops_ac_file = fopen(filename, "wt")) == NULL) - perror_exit("Unable to create ops ac file (%s)\n", filename); - - sprintf(filename, "%s%s", output_path, FILENAME_OPS_DM); - if((g_ops_dm_file = fopen(filename, "wt")) == NULL) - perror_exit("Unable to create ops dm file (%s)\n", filename); - - sprintf(filename, "%s%s", output_path, FILENAME_OPS_NZ); - if((g_ops_nz_file = fopen(filename, "wt")) == NULL) - perror_exit("Unable to create ops nz file (%s)\n", filename); - if((g_input_file=fopen(g_input_filename, "rt")) == NULL) perror_exit("can't open %s for input", g_input_filename); +#endif /* Get to the first section of the input file */ section_id[0] = 0; @@ -1297,18 +1315,14 @@ int main(int argc, char **argv) { if(table_header_read) error_exit("Duplicate table header"); - read_insert(temp_insert); - fprintf(g_table_file, "%s", temp_insert); + read_insert(table_header_insert); table_header_read = 1; } else if(strcmp(section_id, ID_OPHANDLER_HEADER) == 0) { if(ophandler_header_read) error_exit("Duplicate opcode handler header"); - read_insert(temp_insert); - fprintf(g_ops_ac_file, "%s\n\n", temp_insert); - fprintf(g_ops_dm_file, "%s\n\n", temp_insert); - fprintf(g_ops_nz_file, "%s\n\n", temp_insert); + read_insert(ophandler_header_insert); ophandler_header_read = 1; } else if(strcmp(section_id, ID_PROTOTYPE_FOOTER) == 0) @@ -1361,7 +1375,9 @@ int main(int argc, char **argv) if(ophandler_body_read) error_exit("Duplicate opcode handler section"); - process_opcode_handlers(); + fprintf(g_table_file, "%s\n\n", ophandler_header_insert); + process_opcode_handlers(g_table_file); + fprintf(g_table_file, "%s\n\n", ophandler_footer_insert); ophandler_body_read = 1; } @@ -1385,13 +1401,11 @@ int main(int argc, char **argv) if(!ophandler_body_read) error_exit("Missing opcode handler body"); + fprintf(g_table_file, "%s\n\n", table_header_insert); print_opcode_output_table(g_table_file); + fprintf(g_table_file, "%s\n\n", table_footer_insert); fprintf(g_prototype_file, "%s\n\n", prototype_footer_insert); - fprintf(g_table_file, "%s\n\n", table_footer_insert); - fprintf(g_ops_ac_file, "%s\n\n", ophandler_footer_insert); - fprintf(g_ops_dm_file, "%s\n\n", ophandler_footer_insert); - fprintf(g_ops_nz_file, "%s\n\n", ophandler_footer_insert); break; } @@ -1404,9 +1418,6 @@ int main(int argc, char **argv) /* Close all files and exit */ fclose(g_prototype_file); fclose(g_table_file); - fclose(g_ops_ac_file); - fclose(g_ops_dm_file); - fclose(g_ops_nz_file); fclose(g_input_file); printf("Generated %d opcode handlers from %d primitives\n", g_num_functions, g_num_primitives); diff --git a/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/m68k/m68kops.c b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/m68k/m68kops.c new file mode 100644 index 000000000..4dc9ee365 --- /dev/null +++ b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/m68k/m68kops.c @@ -0,0 +1,34189 @@ +#include "m68kcpu.h" + +/* ======================================================================== */ +/* ========================= INSTRUCTION HANDLERS ========================= */ +/* ======================================================================== */ + + +static void m68k_op_1010(m68ki_cpu_core *m68k) +{ + m68ki_exception_1010(m68k); +} + + +static void m68k_op_1111(m68ki_cpu_core *m68k) +{ + m68ki_exception_1111(m68k); +} + + +static void m68k_op_040fpu0_32(m68ki_cpu_core *m68k) +{ + m68ki_exception_1111(m68k); +} + + +static void m68k_op_040fpu1_32(m68ki_cpu_core *m68k) +{ + m68ki_exception_1111(m68k); +} + + +static void m68k_op_abcd_8_rr(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = DY; + UINT32 dst = *r_dst; + UINT32 res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1(m68k); + + m68k->v_flag = ~res; /* Undefined V behavior */ + + if(res > 9) + res += 6; + res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst); + m68k->x_flag = m68k->c_flag = (res > 0x99) << 8; + if(m68k->c_flag) + res -= 0xa0; + + m68k->v_flag &= res; /* Undefined V behavior part II */ + m68k->n_flag = NFLAG_8(res); /* Undefined N behavior */ + + res = MASK_OUT_ABOVE_8(res); + m68k->not_z_flag |= res; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; +} + + +static void m68k_op_abcd_8_mm_ax7(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_AY_PD_8(m68k); + UINT32 ea = EA_A7_PD_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1(m68k); + + m68k->v_flag = ~res; /* Undefined V behavior */ + + if(res > 9) + res += 6; + res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst); + m68k->x_flag = m68k->c_flag = (res > 0x99) << 8; + if(m68k->c_flag) + res -= 0xa0; + + m68k->v_flag &= res; /* Undefined V behavior part II */ + m68k->n_flag = NFLAG_8(res); /* Undefined N behavior */ + + res = MASK_OUT_ABOVE_8(res); + m68k->not_z_flag |= res; + + m68ki_write_8(m68k, ea, res); +} + + +static void m68k_op_abcd_8_mm_ay7(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_A7_PD_8(m68k); + UINT32 ea = EA_AX_PD_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1(m68k); + + m68k->v_flag = ~res; /* Undefined V behavior */ + + if(res > 9) + res += 6; + res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst); + m68k->x_flag = m68k->c_flag = (res > 0x99) << 8; + if(m68k->c_flag) + res -= 0xa0; + + m68k->v_flag &= res; /* Undefined V behavior part II */ + m68k->n_flag = NFLAG_8(res); /* Undefined N behavior */ + + res = MASK_OUT_ABOVE_8(res); + m68k->not_z_flag |= res; + + m68ki_write_8(m68k, ea, res); +} + + +static void m68k_op_abcd_8_mm_axy7(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_A7_PD_8(m68k); + UINT32 ea = EA_A7_PD_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1(m68k); + + m68k->v_flag = ~res; /* Undefined V behavior */ + + if(res > 9) + res += 6; + res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst); + m68k->x_flag = m68k->c_flag = (res > 0x99) << 8; + if(m68k->c_flag) + res -= 0xa0; + + m68k->v_flag &= res; /* Undefined V behavior part II */ + m68k->n_flag = NFLAG_8(res); /* Undefined N behavior */ + + res = MASK_OUT_ABOVE_8(res); + m68k->not_z_flag |= res; + + m68ki_write_8(m68k, ea, res); +} + + +static void m68k_op_abcd_8_mm(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_AY_PD_8(m68k); + UINT32 ea = EA_AX_PD_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1(m68k); + + m68k->v_flag = ~res; /* Undefined V behavior */ + + if(res > 9) + res += 6; + res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst); + m68k->x_flag = m68k->c_flag = (res > 0x99) << 8; + if(m68k->c_flag) + res -= 0xa0; + + m68k->v_flag &= res; /* Undefined V behavior part II */ + m68k->n_flag = NFLAG_8(res); /* Undefined N behavior */ + + res = MASK_OUT_ABOVE_8(res); + m68k->not_z_flag |= res; + + m68ki_write_8(m68k, ea, res); +} + + +static void m68k_op_add_8_er_d(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = MASK_OUT_ABOVE_8(DY); + UINT32 dst = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_add_8_er_ai(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_AY_AI_8(m68k); + UINT32 dst = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_add_8_er_pi(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_AY_PI_8(m68k); + UINT32 dst = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_add_8_er_pi7(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_A7_PI_8(m68k); + UINT32 dst = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_add_8_er_pd(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_AY_PD_8(m68k); + UINT32 dst = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_add_8_er_pd7(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_A7_PD_8(m68k); + UINT32 dst = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_add_8_er_di(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_AY_DI_8(m68k); + UINT32 dst = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_add_8_er_ix(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_AY_IX_8(m68k); + UINT32 dst = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_add_8_er_aw(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_AW_8(m68k); + UINT32 dst = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_add_8_er_al(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_AL_8(m68k); + UINT32 dst = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_add_8_er_pcdi(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_PCDI_8(m68k); + UINT32 dst = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_add_8_er_pcix(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_PCIX_8(m68k); + UINT32 dst = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_add_8_er_i(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_I_8(m68k); + UINT32 dst = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_add_16_er_d(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = MASK_OUT_ABOVE_16(DY); + UINT32 dst = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_16(res); + m68k->v_flag = VFLAG_ADD_16(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_add_16_er_a(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = MASK_OUT_ABOVE_16(AY); + UINT32 dst = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_16(res); + m68k->v_flag = VFLAG_ADD_16(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_add_16_er_ai(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_AY_AI_16(m68k); + UINT32 dst = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_16(res); + m68k->v_flag = VFLAG_ADD_16(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_add_16_er_pi(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_AY_PI_16(m68k); + UINT32 dst = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_16(res); + m68k->v_flag = VFLAG_ADD_16(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_add_16_er_pd(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_AY_PD_16(m68k); + UINT32 dst = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_16(res); + m68k->v_flag = VFLAG_ADD_16(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_add_16_er_di(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_AY_DI_16(m68k); + UINT32 dst = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_16(res); + m68k->v_flag = VFLAG_ADD_16(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_add_16_er_ix(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_AY_IX_16(m68k); + UINT32 dst = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_16(res); + m68k->v_flag = VFLAG_ADD_16(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_add_16_er_aw(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_AW_16(m68k); + UINT32 dst = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_16(res); + m68k->v_flag = VFLAG_ADD_16(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_add_16_er_al(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_AL_16(m68k); + UINT32 dst = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_16(res); + m68k->v_flag = VFLAG_ADD_16(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_add_16_er_pcdi(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_PCDI_16(m68k); + UINT32 dst = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_16(res); + m68k->v_flag = VFLAG_ADD_16(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_add_16_er_pcix(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_PCIX_16(m68k); + UINT32 dst = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_16(res); + m68k->v_flag = VFLAG_ADD_16(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_add_16_er_i(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_I_16(m68k); + UINT32 dst = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_16(res); + m68k->v_flag = VFLAG_ADD_16(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_add_32_er_d(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = DY; + UINT32 dst = *r_dst; + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_ADD_32(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_ADD_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + *r_dst = m68k->not_z_flag; +} + + +static void m68k_op_add_32_er_a(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = AY; + UINT32 dst = *r_dst; + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_ADD_32(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_ADD_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + *r_dst = m68k->not_z_flag; +} + + +static void m68k_op_add_32_er_ai(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_AY_AI_32(m68k); + UINT32 dst = *r_dst; + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_ADD_32(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_ADD_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + *r_dst = m68k->not_z_flag; +} + + +static void m68k_op_add_32_er_pi(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_AY_PI_32(m68k); + UINT32 dst = *r_dst; + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_ADD_32(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_ADD_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + *r_dst = m68k->not_z_flag; +} + + +static void m68k_op_add_32_er_pd(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_AY_PD_32(m68k); + UINT32 dst = *r_dst; + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_ADD_32(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_ADD_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + *r_dst = m68k->not_z_flag; +} + + +static void m68k_op_add_32_er_di(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_AY_DI_32(m68k); + UINT32 dst = *r_dst; + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_ADD_32(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_ADD_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + *r_dst = m68k->not_z_flag; +} + + +static void m68k_op_add_32_er_ix(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_AY_IX_32(m68k); + UINT32 dst = *r_dst; + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_ADD_32(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_ADD_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + *r_dst = m68k->not_z_flag; +} + + +static void m68k_op_add_32_er_aw(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_AW_32(m68k); + UINT32 dst = *r_dst; + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_ADD_32(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_ADD_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + *r_dst = m68k->not_z_flag; +} + + +static void m68k_op_add_32_er_al(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_AL_32(m68k); + UINT32 dst = *r_dst; + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_ADD_32(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_ADD_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + *r_dst = m68k->not_z_flag; +} + + +static void m68k_op_add_32_er_pcdi(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_PCDI_32(m68k); + UINT32 dst = *r_dst; + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_ADD_32(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_ADD_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + *r_dst = m68k->not_z_flag; +} + + +static void m68k_op_add_32_er_pcix(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_PCIX_32(m68k); + UINT32 dst = *r_dst; + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_ADD_32(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_ADD_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + *r_dst = m68k->not_z_flag; +} + + +static void m68k_op_add_32_er_i(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_I_32(m68k); + UINT32 dst = *r_dst; + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_ADD_32(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_ADD_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + *r_dst = m68k->not_z_flag; +} + + +static void m68k_op_add_8_re_ai(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_AI_8(m68k); + UINT32 src = MASK_OUT_ABOVE_8(DX); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_add_8_re_pi(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PI_8(m68k); + UINT32 src = MASK_OUT_ABOVE_8(DX); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_add_8_re_pi7(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_A7_PI_8(m68k); + UINT32 src = MASK_OUT_ABOVE_8(DX); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_add_8_re_pd(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PD_8(m68k); + UINT32 src = MASK_OUT_ABOVE_8(DX); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_add_8_re_pd7(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_A7_PD_8(m68k); + UINT32 src = MASK_OUT_ABOVE_8(DX); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_add_8_re_di(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_DI_8(m68k); + UINT32 src = MASK_OUT_ABOVE_8(DX); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_add_8_re_ix(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_IX_8(m68k); + UINT32 src = MASK_OUT_ABOVE_8(DX); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_add_8_re_aw(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AW_8(m68k); + UINT32 src = MASK_OUT_ABOVE_8(DX); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_add_8_re_al(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AL_8(m68k); + UINT32 src = MASK_OUT_ABOVE_8(DX); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_add_16_re_ai(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_AI_16(m68k); + UINT32 src = MASK_OUT_ABOVE_16(DX); + UINT32 dst = m68ki_read_16(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_16(res); + m68k->v_flag = VFLAG_ADD_16(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_add_16_re_pi(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PI_16(m68k); + UINT32 src = MASK_OUT_ABOVE_16(DX); + UINT32 dst = m68ki_read_16(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_16(res); + m68k->v_flag = VFLAG_ADD_16(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_add_16_re_pd(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PD_16(m68k); + UINT32 src = MASK_OUT_ABOVE_16(DX); + UINT32 dst = m68ki_read_16(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_16(res); + m68k->v_flag = VFLAG_ADD_16(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_add_16_re_di(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_DI_16(m68k); + UINT32 src = MASK_OUT_ABOVE_16(DX); + UINT32 dst = m68ki_read_16(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_16(res); + m68k->v_flag = VFLAG_ADD_16(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_add_16_re_ix(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_IX_16(m68k); + UINT32 src = MASK_OUT_ABOVE_16(DX); + UINT32 dst = m68ki_read_16(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_16(res); + m68k->v_flag = VFLAG_ADD_16(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_add_16_re_aw(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AW_16(m68k); + UINT32 src = MASK_OUT_ABOVE_16(DX); + UINT32 dst = m68ki_read_16(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_16(res); + m68k->v_flag = VFLAG_ADD_16(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_add_16_re_al(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AL_16(m68k); + UINT32 src = MASK_OUT_ABOVE_16(DX); + UINT32 dst = m68ki_read_16(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_16(res); + m68k->v_flag = VFLAG_ADD_16(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_add_32_re_ai(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_AI_32(m68k); + UINT32 src = DX; + UINT32 dst = m68ki_read_32(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_ADD_32(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_ADD_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_add_32_re_pi(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PI_32(m68k); + UINT32 src = DX; + UINT32 dst = m68ki_read_32(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_ADD_32(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_ADD_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_add_32_re_pd(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PD_32(m68k); + UINT32 src = DX; + UINT32 dst = m68ki_read_32(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_ADD_32(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_ADD_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_add_32_re_di(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_DI_32(m68k); + UINT32 src = DX; + UINT32 dst = m68ki_read_32(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_ADD_32(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_ADD_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_add_32_re_ix(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_IX_32(m68k); + UINT32 src = DX; + UINT32 dst = m68ki_read_32(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_ADD_32(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_ADD_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_add_32_re_aw(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AW_32(m68k); + UINT32 src = DX; + UINT32 dst = m68ki_read_32(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_ADD_32(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_ADD_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_add_32_re_al(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AL_32(m68k); + UINT32 src = DX; + UINT32 dst = m68ki_read_32(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_ADD_32(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_ADD_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_adda_16_d(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(DY)); +} + + +static void m68k_op_adda_16_a(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(AY)); +} + + +static void m68k_op_adda_16_ai(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &AX; + UINT32 src = MAKE_INT_16(OPER_AY_AI_16(m68k)); + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + src); +} + + +static void m68k_op_adda_16_pi(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &AX; + UINT32 src = MAKE_INT_16(OPER_AY_PI_16(m68k)); + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + src); +} + + +static void m68k_op_adda_16_pd(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &AX; + UINT32 src = MAKE_INT_16(OPER_AY_PD_16(m68k)); + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + src); +} + + +static void m68k_op_adda_16_di(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &AX; + UINT32 src = MAKE_INT_16(OPER_AY_DI_16(m68k)); + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + src); +} + + +static void m68k_op_adda_16_ix(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &AX; + UINT32 src = MAKE_INT_16(OPER_AY_IX_16(m68k)); + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + src); +} + + +static void m68k_op_adda_16_aw(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &AX; + UINT32 src = MAKE_INT_16(OPER_AW_16(m68k)); + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + src); +} + + +static void m68k_op_adda_16_al(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &AX; + UINT32 src = MAKE_INT_16(OPER_AL_16(m68k)); + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + src); +} + + +static void m68k_op_adda_16_pcdi(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &AX; + UINT32 src = MAKE_INT_16(OPER_PCDI_16(m68k)); + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + src); +} + + +static void m68k_op_adda_16_pcix(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &AX; + UINT32 src = MAKE_INT_16(OPER_PCIX_16(m68k)); + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + src); +} + + +static void m68k_op_adda_16_i(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &AX; + UINT32 src = MAKE_INT_16(OPER_I_16(m68k)); + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + src); +} + + +static void m68k_op_adda_32_d(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + DY); +} + + +static void m68k_op_adda_32_a(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + AY); +} + + +static void m68k_op_adda_32_ai(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &AX; + UINT32 src = OPER_AY_AI_32(m68k); + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + src); +} + + +static void m68k_op_adda_32_pi(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &AX; + UINT32 src = OPER_AY_PI_32(m68k); + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + src); +} + + +static void m68k_op_adda_32_pd(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &AX; + UINT32 src = OPER_AY_PD_32(m68k); + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + src); +} + + +static void m68k_op_adda_32_di(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &AX; + UINT32 src = OPER_AY_DI_32(m68k); + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + src); +} + + +static void m68k_op_adda_32_ix(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &AX; + UINT32 src = OPER_AY_IX_32(m68k); + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + src); +} + + +static void m68k_op_adda_32_aw(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &AX; + UINT32 src = OPER_AW_32(m68k); + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + src); +} + + +static void m68k_op_adda_32_al(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &AX; + UINT32 src = OPER_AL_32(m68k); + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + src); +} + + +static void m68k_op_adda_32_pcdi(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &AX; + UINT32 src = OPER_PCDI_32(m68k); + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + src); +} + + +static void m68k_op_adda_32_pcix(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &AX; + UINT32 src = OPER_PCIX_32(m68k); + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + src); +} + + +static void m68k_op_adda_32_i(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &AX; + UINT32 src = OPER_I_32(m68k); + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + src); +} + + +static void m68k_op_addi_8_d(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 src = OPER_I_8(m68k); + UINT32 dst = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_addi_8_ai(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 ea = EA_AY_AI_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_addi_8_pi(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 ea = EA_AY_PI_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_addi_8_pi7(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 ea = EA_A7_PI_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_addi_8_pd(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 ea = EA_AY_PD_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_addi_8_pd7(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 ea = EA_A7_PD_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_addi_8_di(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 ea = EA_AY_DI_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_addi_8_ix(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 ea = EA_AY_IX_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_addi_8_aw(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 ea = EA_AW_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_addi_8_al(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 ea = EA_AL_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_addi_16_d(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 src = OPER_I_16(m68k); + UINT32 dst = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_16(res); + m68k->v_flag = VFLAG_ADD_16(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_addi_16_ai(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_16(m68k); + UINT32 ea = EA_AY_AI_16(m68k); + UINT32 dst = m68ki_read_16(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_16(res); + m68k->v_flag = VFLAG_ADD_16(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_addi_16_pi(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_16(m68k); + UINT32 ea = EA_AY_PI_16(m68k); + UINT32 dst = m68ki_read_16(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_16(res); + m68k->v_flag = VFLAG_ADD_16(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_addi_16_pd(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_16(m68k); + UINT32 ea = EA_AY_PD_16(m68k); + UINT32 dst = m68ki_read_16(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_16(res); + m68k->v_flag = VFLAG_ADD_16(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_addi_16_di(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_16(m68k); + UINT32 ea = EA_AY_DI_16(m68k); + UINT32 dst = m68ki_read_16(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_16(res); + m68k->v_flag = VFLAG_ADD_16(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_addi_16_ix(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_16(m68k); + UINT32 ea = EA_AY_IX_16(m68k); + UINT32 dst = m68ki_read_16(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_16(res); + m68k->v_flag = VFLAG_ADD_16(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_addi_16_aw(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_16(m68k); + UINT32 ea = EA_AW_16(m68k); + UINT32 dst = m68ki_read_16(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_16(res); + m68k->v_flag = VFLAG_ADD_16(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_addi_16_al(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_16(m68k); + UINT32 ea = EA_AL_16(m68k); + UINT32 dst = m68ki_read_16(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_16(res); + m68k->v_flag = VFLAG_ADD_16(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_addi_32_d(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 src = OPER_I_32(m68k); + UINT32 dst = *r_dst; + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_ADD_32(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_ADD_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + *r_dst = m68k->not_z_flag; +} + + +static void m68k_op_addi_32_ai(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_32(m68k); + UINT32 ea = EA_AY_AI_32(m68k); + UINT32 dst = m68ki_read_32(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_ADD_32(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_ADD_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_addi_32_pi(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_32(m68k); + UINT32 ea = EA_AY_PI_32(m68k); + UINT32 dst = m68ki_read_32(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_ADD_32(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_ADD_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_addi_32_pd(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_32(m68k); + UINT32 ea = EA_AY_PD_32(m68k); + UINT32 dst = m68ki_read_32(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_ADD_32(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_ADD_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_addi_32_di(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_32(m68k); + UINT32 ea = EA_AY_DI_32(m68k); + UINT32 dst = m68ki_read_32(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_ADD_32(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_ADD_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_addi_32_ix(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_32(m68k); + UINT32 ea = EA_AY_IX_32(m68k); + UINT32 dst = m68ki_read_32(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_ADD_32(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_ADD_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_addi_32_aw(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_32(m68k); + UINT32 ea = EA_AW_32(m68k); + UINT32 dst = m68ki_read_32(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_ADD_32(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_ADD_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_addi_32_al(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_32(m68k); + UINT32 ea = EA_AL_32(m68k); + UINT32 dst = m68ki_read_32(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_ADD_32(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_ADD_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_addq_8_d(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 dst = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_addq_8_ai(m68ki_cpu_core *m68k) +{ + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 ea = EA_AY_AI_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_addq_8_pi(m68ki_cpu_core *m68k) +{ + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 ea = EA_AY_PI_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_addq_8_pi7(m68ki_cpu_core *m68k) +{ + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 ea = EA_A7_PI_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_addq_8_pd(m68ki_cpu_core *m68k) +{ + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 ea = EA_AY_PD_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_addq_8_pd7(m68ki_cpu_core *m68k) +{ + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 ea = EA_A7_PD_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_addq_8_di(m68ki_cpu_core *m68k) +{ + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 ea = EA_AY_DI_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_addq_8_ix(m68ki_cpu_core *m68k) +{ + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 ea = EA_AY_IX_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_addq_8_aw(m68ki_cpu_core *m68k) +{ + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 ea = EA_AW_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_addq_8_al(m68ki_cpu_core *m68k) +{ + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 ea = EA_AL_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_addq_16_d(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 dst = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_16(res); + m68k->v_flag = VFLAG_ADD_16(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_addq_16_a(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &AY; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((m68k->ir >> 9) - 1) & 7) + 1); +} + + +static void m68k_op_addq_16_ai(m68ki_cpu_core *m68k) +{ + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 ea = EA_AY_AI_16(m68k); + UINT32 dst = m68ki_read_16(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_16(res); + m68k->v_flag = VFLAG_ADD_16(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_addq_16_pi(m68ki_cpu_core *m68k) +{ + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 ea = EA_AY_PI_16(m68k); + UINT32 dst = m68ki_read_16(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_16(res); + m68k->v_flag = VFLAG_ADD_16(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_addq_16_pd(m68ki_cpu_core *m68k) +{ + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 ea = EA_AY_PD_16(m68k); + UINT32 dst = m68ki_read_16(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_16(res); + m68k->v_flag = VFLAG_ADD_16(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_addq_16_di(m68ki_cpu_core *m68k) +{ + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 ea = EA_AY_DI_16(m68k); + UINT32 dst = m68ki_read_16(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_16(res); + m68k->v_flag = VFLAG_ADD_16(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_addq_16_ix(m68ki_cpu_core *m68k) +{ + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 ea = EA_AY_IX_16(m68k); + UINT32 dst = m68ki_read_16(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_16(res); + m68k->v_flag = VFLAG_ADD_16(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_addq_16_aw(m68ki_cpu_core *m68k) +{ + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 ea = EA_AW_16(m68k); + UINT32 dst = m68ki_read_16(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_16(res); + m68k->v_flag = VFLAG_ADD_16(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_addq_16_al(m68ki_cpu_core *m68k) +{ + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 ea = EA_AL_16(m68k); + UINT32 dst = m68ki_read_16(m68k, ea); + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_16(res); + m68k->v_flag = VFLAG_ADD_16(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_addq_32_d(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 dst = *r_dst; + UINT32 res = src + dst; + + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_ADD_32(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_ADD_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + *r_dst = m68k->not_z_flag; +} + + +static void m68k_op_addq_32_a(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &AY; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((m68k->ir >> 9) - 1) & 7) + 1); +} + + +static void m68k_op_addq_32_ai(m68ki_cpu_core *m68k) +{ + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 ea = EA_AY_AI_32(m68k); + UINT32 dst = m68ki_read_32(m68k, ea); + UINT32 res = src + dst; + + + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_ADD_32(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_ADD_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_addq_32_pi(m68ki_cpu_core *m68k) +{ + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 ea = EA_AY_PI_32(m68k); + UINT32 dst = m68ki_read_32(m68k, ea); + UINT32 res = src + dst; + + + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_ADD_32(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_ADD_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_addq_32_pd(m68ki_cpu_core *m68k) +{ + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 ea = EA_AY_PD_32(m68k); + UINT32 dst = m68ki_read_32(m68k, ea); + UINT32 res = src + dst; + + + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_ADD_32(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_ADD_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_addq_32_di(m68ki_cpu_core *m68k) +{ + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 ea = EA_AY_DI_32(m68k); + UINT32 dst = m68ki_read_32(m68k, ea); + UINT32 res = src + dst; + + + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_ADD_32(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_ADD_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_addq_32_ix(m68ki_cpu_core *m68k) +{ + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 ea = EA_AY_IX_32(m68k); + UINT32 dst = m68ki_read_32(m68k, ea); + UINT32 res = src + dst; + + + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_ADD_32(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_ADD_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_addq_32_aw(m68ki_cpu_core *m68k) +{ + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 ea = EA_AW_32(m68k); + UINT32 dst = m68ki_read_32(m68k, ea); + UINT32 res = src + dst; + + + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_ADD_32(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_ADD_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_addq_32_al(m68ki_cpu_core *m68k) +{ + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 ea = EA_AL_32(m68k); + UINT32 dst = m68ki_read_32(m68k, ea); + UINT32 res = src + dst; + + + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_ADD_32(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_ADD_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_addx_8_rr(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = MASK_OUT_ABOVE_8(DY); + UINT32 dst = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = src + dst + XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + + res = MASK_OUT_ABOVE_8(res); + m68k->not_z_flag |= res; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; +} + + +static void m68k_op_addx_16_rr(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = MASK_OUT_ABOVE_16(DY); + UINT32 dst = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = src + dst + XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_16(res); + m68k->v_flag = VFLAG_ADD_16(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + + res = MASK_OUT_ABOVE_16(res); + m68k->not_z_flag |= res; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; +} + + +static void m68k_op_addx_32_rr(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = DY; + UINT32 dst = *r_dst; + UINT32 res = src + dst + XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_ADD_32(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_ADD_32(src, dst, res); + + res = MASK_OUT_ABOVE_32(res); + m68k->not_z_flag |= res; + + *r_dst = res; +} + + +static void m68k_op_addx_8_mm_ax7(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_AY_PD_8(m68k); + UINT32 ea = EA_A7_PD_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = src + dst + XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + + res = MASK_OUT_ABOVE_8(res); + m68k->not_z_flag |= res; + + m68ki_write_8(m68k, ea, res); +} + + +static void m68k_op_addx_8_mm_ay7(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_A7_PD_8(m68k); + UINT32 ea = EA_AX_PD_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = src + dst + XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + + res = MASK_OUT_ABOVE_8(res); + m68k->not_z_flag |= res; + + m68ki_write_8(m68k, ea, res); +} + + +static void m68k_op_addx_8_mm_axy7(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_A7_PD_8(m68k); + UINT32 ea = EA_A7_PD_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = src + dst + XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + + res = MASK_OUT_ABOVE_8(res); + m68k->not_z_flag |= res; + + m68ki_write_8(m68k, ea, res); +} + + +static void m68k_op_addx_8_mm(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_AY_PD_8(m68k); + UINT32 ea = EA_AX_PD_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = src + dst + XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_8(res); + m68k->v_flag = VFLAG_ADD_8(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + + res = MASK_OUT_ABOVE_8(res); + m68k->not_z_flag |= res; + + m68ki_write_8(m68k, ea, res); +} + + +static void m68k_op_addx_16_mm(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_AY_PD_16(m68k); + UINT32 ea = EA_AX_PD_16(m68k); + UINT32 dst = m68ki_read_16(m68k, ea); + UINT32 res = src + dst + XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_16(res); + m68k->v_flag = VFLAG_ADD_16(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + + res = MASK_OUT_ABOVE_16(res); + m68k->not_z_flag |= res; + + m68ki_write_16(m68k, ea, res); +} + + +static void m68k_op_addx_32_mm(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_AY_PD_32(m68k); + UINT32 ea = EA_AX_PD_32(m68k); + UINT32 dst = m68ki_read_32(m68k, ea); + UINT32 res = src + dst + XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_ADD_32(src, dst, res); + m68k->x_flag = m68k->c_flag = CFLAG_ADD_32(src, dst, res); + + res = MASK_OUT_ABOVE_32(res); + m68k->not_z_flag |= res; + + m68ki_write_32(m68k, ea, res); +} + + +static void m68k_op_and_8_er_d(m68ki_cpu_core *m68k) +{ + m68k->not_z_flag = MASK_OUT_ABOVE_8(DX &= (DY | 0xffffff00)); + + m68k->n_flag = NFLAG_8(m68k->not_z_flag); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_and_8_er_ai(m68ki_cpu_core *m68k) +{ + m68k->not_z_flag = MASK_OUT_ABOVE_8(DX &= (OPER_AY_AI_8(m68k) | 0xffffff00)); + + m68k->n_flag = NFLAG_8(m68k->not_z_flag); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_and_8_er_pi(m68ki_cpu_core *m68k) +{ + m68k->not_z_flag = MASK_OUT_ABOVE_8(DX &= (OPER_AY_PI_8(m68k) | 0xffffff00)); + + m68k->n_flag = NFLAG_8(m68k->not_z_flag); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_and_8_er_pi7(m68ki_cpu_core *m68k) +{ + m68k->not_z_flag = MASK_OUT_ABOVE_8(DX &= (OPER_A7_PI_8(m68k) | 0xffffff00)); + + m68k->n_flag = NFLAG_8(m68k->not_z_flag); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_and_8_er_pd(m68ki_cpu_core *m68k) +{ + m68k->not_z_flag = MASK_OUT_ABOVE_8(DX &= (OPER_AY_PD_8(m68k) | 0xffffff00)); + + m68k->n_flag = NFLAG_8(m68k->not_z_flag); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_and_8_er_pd7(m68ki_cpu_core *m68k) +{ + m68k->not_z_flag = MASK_OUT_ABOVE_8(DX &= (OPER_A7_PD_8(m68k) | 0xffffff00)); + + m68k->n_flag = NFLAG_8(m68k->not_z_flag); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_and_8_er_di(m68ki_cpu_core *m68k) +{ + m68k->not_z_flag = MASK_OUT_ABOVE_8(DX &= (OPER_AY_DI_8(m68k) | 0xffffff00)); + + m68k->n_flag = NFLAG_8(m68k->not_z_flag); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_and_8_er_ix(m68ki_cpu_core *m68k) +{ + m68k->not_z_flag = MASK_OUT_ABOVE_8(DX &= (OPER_AY_IX_8(m68k) | 0xffffff00)); + + m68k->n_flag = NFLAG_8(m68k->not_z_flag); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_and_8_er_aw(m68ki_cpu_core *m68k) +{ + m68k->not_z_flag = MASK_OUT_ABOVE_8(DX &= (OPER_AW_8(m68k) | 0xffffff00)); + + m68k->n_flag = NFLAG_8(m68k->not_z_flag); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_and_8_er_al(m68ki_cpu_core *m68k) +{ + m68k->not_z_flag = MASK_OUT_ABOVE_8(DX &= (OPER_AL_8(m68k) | 0xffffff00)); + + m68k->n_flag = NFLAG_8(m68k->not_z_flag); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_and_8_er_pcdi(m68ki_cpu_core *m68k) +{ + m68k->not_z_flag = MASK_OUT_ABOVE_8(DX &= (OPER_PCDI_8(m68k) | 0xffffff00)); + + m68k->n_flag = NFLAG_8(m68k->not_z_flag); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_and_8_er_pcix(m68ki_cpu_core *m68k) +{ + m68k->not_z_flag = MASK_OUT_ABOVE_8(DX &= (OPER_PCIX_8(m68k) | 0xffffff00)); + + m68k->n_flag = NFLAG_8(m68k->not_z_flag); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_and_8_er_i(m68ki_cpu_core *m68k) +{ + m68k->not_z_flag = MASK_OUT_ABOVE_8(DX &= (OPER_I_8(m68k) | 0xffffff00)); + + m68k->n_flag = NFLAG_8(m68k->not_z_flag); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_and_16_er_d(m68ki_cpu_core *m68k) +{ + m68k->not_z_flag = MASK_OUT_ABOVE_16(DX &= (DY | 0xffff0000)); + + m68k->n_flag = NFLAG_16(m68k->not_z_flag); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_and_16_er_ai(m68ki_cpu_core *m68k) +{ + m68k->not_z_flag = MASK_OUT_ABOVE_16(DX &= (OPER_AY_AI_16(m68k) | 0xffff0000)); + + m68k->n_flag = NFLAG_16(m68k->not_z_flag); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_and_16_er_pi(m68ki_cpu_core *m68k) +{ + m68k->not_z_flag = MASK_OUT_ABOVE_16(DX &= (OPER_AY_PI_16(m68k) | 0xffff0000)); + + m68k->n_flag = NFLAG_16(m68k->not_z_flag); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_and_16_er_pd(m68ki_cpu_core *m68k) +{ + m68k->not_z_flag = MASK_OUT_ABOVE_16(DX &= (OPER_AY_PD_16(m68k) | 0xffff0000)); + + m68k->n_flag = NFLAG_16(m68k->not_z_flag); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_and_16_er_di(m68ki_cpu_core *m68k) +{ + m68k->not_z_flag = MASK_OUT_ABOVE_16(DX &= (OPER_AY_DI_16(m68k) | 0xffff0000)); + + m68k->n_flag = NFLAG_16(m68k->not_z_flag); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_and_16_er_ix(m68ki_cpu_core *m68k) +{ + m68k->not_z_flag = MASK_OUT_ABOVE_16(DX &= (OPER_AY_IX_16(m68k) | 0xffff0000)); + + m68k->n_flag = NFLAG_16(m68k->not_z_flag); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_and_16_er_aw(m68ki_cpu_core *m68k) +{ + m68k->not_z_flag = MASK_OUT_ABOVE_16(DX &= (OPER_AW_16(m68k) | 0xffff0000)); + + m68k->n_flag = NFLAG_16(m68k->not_z_flag); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_and_16_er_al(m68ki_cpu_core *m68k) +{ + m68k->not_z_flag = MASK_OUT_ABOVE_16(DX &= (OPER_AL_16(m68k) | 0xffff0000)); + + m68k->n_flag = NFLAG_16(m68k->not_z_flag); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_and_16_er_pcdi(m68ki_cpu_core *m68k) +{ + m68k->not_z_flag = MASK_OUT_ABOVE_16(DX &= (OPER_PCDI_16(m68k) | 0xffff0000)); + + m68k->n_flag = NFLAG_16(m68k->not_z_flag); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_and_16_er_pcix(m68ki_cpu_core *m68k) +{ + m68k->not_z_flag = MASK_OUT_ABOVE_16(DX &= (OPER_PCIX_16(m68k) | 0xffff0000)); + + m68k->n_flag = NFLAG_16(m68k->not_z_flag); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_and_16_er_i(m68ki_cpu_core *m68k) +{ + m68k->not_z_flag = MASK_OUT_ABOVE_16(DX &= (OPER_I_16(m68k) | 0xffff0000)); + + m68k->n_flag = NFLAG_16(m68k->not_z_flag); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_and_32_er_d(m68ki_cpu_core *m68k) +{ + m68k->not_z_flag = DX &= DY; + + m68k->n_flag = NFLAG_32(m68k->not_z_flag); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_and_32_er_ai(m68ki_cpu_core *m68k) +{ + m68k->not_z_flag = DX &= OPER_AY_AI_32(m68k); + + m68k->n_flag = NFLAG_32(m68k->not_z_flag); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_and_32_er_pi(m68ki_cpu_core *m68k) +{ + m68k->not_z_flag = DX &= OPER_AY_PI_32(m68k); + + m68k->n_flag = NFLAG_32(m68k->not_z_flag); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_and_32_er_pd(m68ki_cpu_core *m68k) +{ + m68k->not_z_flag = DX &= OPER_AY_PD_32(m68k); + + m68k->n_flag = NFLAG_32(m68k->not_z_flag); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_and_32_er_di(m68ki_cpu_core *m68k) +{ + m68k->not_z_flag = DX &= OPER_AY_DI_32(m68k); + + m68k->n_flag = NFLAG_32(m68k->not_z_flag); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_and_32_er_ix(m68ki_cpu_core *m68k) +{ + m68k->not_z_flag = DX &= OPER_AY_IX_32(m68k); + + m68k->n_flag = NFLAG_32(m68k->not_z_flag); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_and_32_er_aw(m68ki_cpu_core *m68k) +{ + m68k->not_z_flag = DX &= OPER_AW_32(m68k); + + m68k->n_flag = NFLAG_32(m68k->not_z_flag); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_and_32_er_al(m68ki_cpu_core *m68k) +{ + m68k->not_z_flag = DX &= OPER_AL_32(m68k); + + m68k->n_flag = NFLAG_32(m68k->not_z_flag); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_and_32_er_pcdi(m68ki_cpu_core *m68k) +{ + m68k->not_z_flag = DX &= OPER_PCDI_32(m68k); + + m68k->n_flag = NFLAG_32(m68k->not_z_flag); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_and_32_er_pcix(m68ki_cpu_core *m68k) +{ + m68k->not_z_flag = DX &= OPER_PCIX_32(m68k); + + m68k->n_flag = NFLAG_32(m68k->not_z_flag); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_and_32_er_i(m68ki_cpu_core *m68k) +{ + m68k->not_z_flag = DX &= OPER_I_32(m68k); + + m68k->n_flag = NFLAG_32(m68k->not_z_flag); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_and_8_re_ai(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_AI_8(m68k); + UINT32 res = DX & m68ki_read_8(m68k, ea); + + m68k->n_flag = NFLAG_8(res); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_and_8_re_pi(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PI_8(m68k); + UINT32 res = DX & m68ki_read_8(m68k, ea); + + m68k->n_flag = NFLAG_8(res); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_and_8_re_pi7(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_A7_PI_8(m68k); + UINT32 res = DX & m68ki_read_8(m68k, ea); + + m68k->n_flag = NFLAG_8(res); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_and_8_re_pd(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PD_8(m68k); + UINT32 res = DX & m68ki_read_8(m68k, ea); + + m68k->n_flag = NFLAG_8(res); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_and_8_re_pd7(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_A7_PD_8(m68k); + UINT32 res = DX & m68ki_read_8(m68k, ea); + + m68k->n_flag = NFLAG_8(res); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_and_8_re_di(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_DI_8(m68k); + UINT32 res = DX & m68ki_read_8(m68k, ea); + + m68k->n_flag = NFLAG_8(res); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_and_8_re_ix(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_IX_8(m68k); + UINT32 res = DX & m68ki_read_8(m68k, ea); + + m68k->n_flag = NFLAG_8(res); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_and_8_re_aw(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AW_8(m68k); + UINT32 res = DX & m68ki_read_8(m68k, ea); + + m68k->n_flag = NFLAG_8(res); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_and_8_re_al(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AL_8(m68k); + UINT32 res = DX & m68ki_read_8(m68k, ea); + + m68k->n_flag = NFLAG_8(res); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_and_16_re_ai(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_AI_16(m68k); + UINT32 res = DX & m68ki_read_16(m68k, ea); + + m68k->n_flag = NFLAG_16(res); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_and_16_re_pi(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PI_16(m68k); + UINT32 res = DX & m68ki_read_16(m68k, ea); + + m68k->n_flag = NFLAG_16(res); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_and_16_re_pd(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PD_16(m68k); + UINT32 res = DX & m68ki_read_16(m68k, ea); + + m68k->n_flag = NFLAG_16(res); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_and_16_re_di(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_DI_16(m68k); + UINT32 res = DX & m68ki_read_16(m68k, ea); + + m68k->n_flag = NFLAG_16(res); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_and_16_re_ix(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_IX_16(m68k); + UINT32 res = DX & m68ki_read_16(m68k, ea); + + m68k->n_flag = NFLAG_16(res); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_and_16_re_aw(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AW_16(m68k); + UINT32 res = DX & m68ki_read_16(m68k, ea); + + m68k->n_flag = NFLAG_16(res); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_and_16_re_al(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AL_16(m68k); + UINT32 res = DX & m68ki_read_16(m68k, ea); + + m68k->n_flag = NFLAG_16(res); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_and_32_re_ai(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_AI_32(m68k); + UINT32 res = DX & m68ki_read_32(m68k, ea); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + + m68ki_write_32(m68k, ea, res); +} + + +static void m68k_op_and_32_re_pi(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PI_32(m68k); + UINT32 res = DX & m68ki_read_32(m68k, ea); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + + m68ki_write_32(m68k, ea, res); +} + + +static void m68k_op_and_32_re_pd(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PD_32(m68k); + UINT32 res = DX & m68ki_read_32(m68k, ea); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + + m68ki_write_32(m68k, ea, res); +} + + +static void m68k_op_and_32_re_di(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_DI_32(m68k); + UINT32 res = DX & m68ki_read_32(m68k, ea); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + + m68ki_write_32(m68k, ea, res); +} + + +static void m68k_op_and_32_re_ix(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_IX_32(m68k); + UINT32 res = DX & m68ki_read_32(m68k, ea); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + + m68ki_write_32(m68k, ea, res); +} + + +static void m68k_op_and_32_re_aw(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AW_32(m68k); + UINT32 res = DX & m68ki_read_32(m68k, ea); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + + m68ki_write_32(m68k, ea, res); +} + + +static void m68k_op_and_32_re_al(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AL_32(m68k); + UINT32 res = DX & m68ki_read_32(m68k, ea); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + + m68ki_write_32(m68k, ea, res); +} + + +static void m68k_op_andi_8_d(m68ki_cpu_core *m68k) +{ + m68k->not_z_flag = MASK_OUT_ABOVE_8(DY &= (OPER_I_8(m68k) | 0xffffff00)); + + m68k->n_flag = NFLAG_8(m68k->not_z_flag); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_andi_8_ai(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 ea = EA_AY_AI_8(m68k); + UINT32 res = src & m68ki_read_8(m68k, ea); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + + m68ki_write_8(m68k, ea, res); +} + + +static void m68k_op_andi_8_pi(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 ea = EA_AY_PI_8(m68k); + UINT32 res = src & m68ki_read_8(m68k, ea); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + + m68ki_write_8(m68k, ea, res); +} + + +static void m68k_op_andi_8_pi7(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 ea = EA_A7_PI_8(m68k); + UINT32 res = src & m68ki_read_8(m68k, ea); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + + m68ki_write_8(m68k, ea, res); +} + + +static void m68k_op_andi_8_pd(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 ea = EA_AY_PD_8(m68k); + UINT32 res = src & m68ki_read_8(m68k, ea); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + + m68ki_write_8(m68k, ea, res); +} + + +static void m68k_op_andi_8_pd7(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 ea = EA_A7_PD_8(m68k); + UINT32 res = src & m68ki_read_8(m68k, ea); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + + m68ki_write_8(m68k, ea, res); +} + + +static void m68k_op_andi_8_di(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 ea = EA_AY_DI_8(m68k); + UINT32 res = src & m68ki_read_8(m68k, ea); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + + m68ki_write_8(m68k, ea, res); +} + + +static void m68k_op_andi_8_ix(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 ea = EA_AY_IX_8(m68k); + UINT32 res = src & m68ki_read_8(m68k, ea); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + + m68ki_write_8(m68k, ea, res); +} + + +static void m68k_op_andi_8_aw(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 ea = EA_AW_8(m68k); + UINT32 res = src & m68ki_read_8(m68k, ea); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + + m68ki_write_8(m68k, ea, res); +} + + +static void m68k_op_andi_8_al(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 ea = EA_AL_8(m68k); + UINT32 res = src & m68ki_read_8(m68k, ea); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + + m68ki_write_8(m68k, ea, res); +} + + +static void m68k_op_andi_16_d(m68ki_cpu_core *m68k) +{ + m68k->not_z_flag = MASK_OUT_ABOVE_16(DY &= (OPER_I_16(m68k) | 0xffff0000)); + + m68k->n_flag = NFLAG_16(m68k->not_z_flag); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_andi_16_ai(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_16(m68k); + UINT32 ea = EA_AY_AI_16(m68k); + UINT32 res = src & m68ki_read_16(m68k, ea); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + + m68ki_write_16(m68k, ea, res); +} + + +static void m68k_op_andi_16_pi(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_16(m68k); + UINT32 ea = EA_AY_PI_16(m68k); + UINT32 res = src & m68ki_read_16(m68k, ea); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + + m68ki_write_16(m68k, ea, res); +} + + +static void m68k_op_andi_16_pd(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_16(m68k); + UINT32 ea = EA_AY_PD_16(m68k); + UINT32 res = src & m68ki_read_16(m68k, ea); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + + m68ki_write_16(m68k, ea, res); +} + + +static void m68k_op_andi_16_di(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_16(m68k); + UINT32 ea = EA_AY_DI_16(m68k); + UINT32 res = src & m68ki_read_16(m68k, ea); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + + m68ki_write_16(m68k, ea, res); +} + + +static void m68k_op_andi_16_ix(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_16(m68k); + UINT32 ea = EA_AY_IX_16(m68k); + UINT32 res = src & m68ki_read_16(m68k, ea); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + + m68ki_write_16(m68k, ea, res); +} + + +static void m68k_op_andi_16_aw(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_16(m68k); + UINT32 ea = EA_AW_16(m68k); + UINT32 res = src & m68ki_read_16(m68k, ea); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + + m68ki_write_16(m68k, ea, res); +} + + +static void m68k_op_andi_16_al(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_16(m68k); + UINT32 ea = EA_AL_16(m68k); + UINT32 res = src & m68ki_read_16(m68k, ea); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + + m68ki_write_16(m68k, ea, res); +} + + +static void m68k_op_andi_32_d(m68ki_cpu_core *m68k) +{ + m68k->not_z_flag = DY &= (OPER_I_32(m68k)); + + m68k->n_flag = NFLAG_32(m68k->not_z_flag); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_andi_32_ai(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_32(m68k); + UINT32 ea = EA_AY_AI_32(m68k); + UINT32 res = src & m68ki_read_32(m68k, ea); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + + m68ki_write_32(m68k, ea, res); +} + + +static void m68k_op_andi_32_pi(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_32(m68k); + UINT32 ea = EA_AY_PI_32(m68k); + UINT32 res = src & m68ki_read_32(m68k, ea); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + + m68ki_write_32(m68k, ea, res); +} + + +static void m68k_op_andi_32_pd(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_32(m68k); + UINT32 ea = EA_AY_PD_32(m68k); + UINT32 res = src & m68ki_read_32(m68k, ea); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + + m68ki_write_32(m68k, ea, res); +} + + +static void m68k_op_andi_32_di(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_32(m68k); + UINT32 ea = EA_AY_DI_32(m68k); + UINT32 res = src & m68ki_read_32(m68k, ea); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + + m68ki_write_32(m68k, ea, res); +} + + +static void m68k_op_andi_32_ix(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_32(m68k); + UINT32 ea = EA_AY_IX_32(m68k); + UINT32 res = src & m68ki_read_32(m68k, ea); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + + m68ki_write_32(m68k, ea, res); +} + + +static void m68k_op_andi_32_aw(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_32(m68k); + UINT32 ea = EA_AW_32(m68k); + UINT32 res = src & m68ki_read_32(m68k, ea); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + + m68ki_write_32(m68k, ea, res); +} + + +static void m68k_op_andi_32_al(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_32(m68k); + UINT32 ea = EA_AL_32(m68k); + UINT32 res = src & m68ki_read_32(m68k, ea); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + + m68ki_write_32(m68k, ea, res); +} + + +static void m68k_op_andi_16_toc(m68ki_cpu_core *m68k) +{ + m68ki_set_ccr(m68k, m68ki_get_ccr(m68k) & OPER_I_16(m68k)); +} + + +static void m68k_op_andi_16_tos(m68ki_cpu_core *m68k) +{ + if(m68k->s_flag) + { + UINT32 src = OPER_I_16(m68k); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_set_sr(m68k, m68ki_get_sr(m68k) & src); + return; + } + m68ki_exception_privilege_violation(m68k); +} + + +static void m68k_op_asr_8_s(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 shift = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 src = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = src >> shift; + + if(shift != 0) + m68k->remaining_cycles -= shift<cyc_shift; + + if(GET_MSB_8(src)) + res |= m68ki_shift_8_table[shift]; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->x_flag = m68k->c_flag = src << (9-shift); +} + + +static void m68k_op_asr_16_s(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 shift = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 src = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = src >> shift; + + if(shift != 0) + m68k->remaining_cycles -= shift<cyc_shift; + + if(GET_MSB_16(src)) + res |= m68ki_shift_16_table[shift]; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->x_flag = m68k->c_flag = src << (9-shift); +} + + +static void m68k_op_asr_32_s(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 shift = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 src = *r_dst; + UINT32 res = src >> shift; + + if(shift != 0) + m68k->remaining_cycles -= shift<cyc_shift; + + if(GET_MSB_32(src)) + res |= m68ki_shift_32_table[shift]; + + *r_dst = res; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->x_flag = m68k->c_flag = src << (9-shift); +} + + +static void m68k_op_asr_8_r(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 shift = DX & 0x3f; + UINT32 src = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = src >> shift; + + if(shift != 0) + { + m68k->remaining_cycles -= shift<cyc_shift; + + if(shift < 8) + { + if(GET_MSB_8(src)) + res |= m68ki_shift_8_table[shift]; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + m68k->x_flag = m68k->c_flag = src << (9-shift); + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + if(GET_MSB_8(src)) + { + *r_dst |= 0xff; + m68k->c_flag = CFLAG_SET; + m68k->x_flag = XFLAG_SET; + m68k->n_flag = NFLAG_SET; + m68k->not_z_flag = ZFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + *r_dst &= 0xffffff00; + m68k->c_flag = CFLAG_CLEAR; + m68k->x_flag = XFLAG_CLEAR; + m68k->n_flag = NFLAG_CLEAR; + m68k->not_z_flag = ZFLAG_SET; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + m68k->c_flag = CFLAG_CLEAR; + m68k->n_flag = NFLAG_8(src); + m68k->not_z_flag = src; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_asr_16_r(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 shift = DX & 0x3f; + UINT32 src = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = src >> shift; + + if(shift != 0) + { + m68k->remaining_cycles -= shift<cyc_shift; + + if(shift < 16) + { + if(GET_MSB_16(src)) + res |= m68ki_shift_16_table[shift]; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + m68k->c_flag = m68k->x_flag = (src >> (shift - 1))<<8; + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + if(GET_MSB_16(src)) + { + *r_dst |= 0xffff; + m68k->c_flag = CFLAG_SET; + m68k->x_flag = XFLAG_SET; + m68k->n_flag = NFLAG_SET; + m68k->not_z_flag = ZFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + *r_dst &= 0xffff0000; + m68k->c_flag = CFLAG_CLEAR; + m68k->x_flag = XFLAG_CLEAR; + m68k->n_flag = NFLAG_CLEAR; + m68k->not_z_flag = ZFLAG_SET; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + m68k->c_flag = CFLAG_CLEAR; + m68k->n_flag = NFLAG_16(src); + m68k->not_z_flag = src; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_asr_32_r(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 shift = DX & 0x3f; + UINT32 src = *r_dst; + UINT32 res = src >> shift; + + if(shift != 0) + { + m68k->remaining_cycles -= shift<cyc_shift; + + if(shift < 32) + { + if(GET_MSB_32(src)) + res |= m68ki_shift_32_table[shift]; + + *r_dst = res; + + m68k->c_flag = m68k->x_flag = (src >> (shift - 1))<<8; + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + if(GET_MSB_32(src)) + { + *r_dst = 0xffffffff; + m68k->c_flag = CFLAG_SET; + m68k->x_flag = XFLAG_SET; + m68k->n_flag = NFLAG_SET; + m68k->not_z_flag = ZFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + *r_dst = 0; + m68k->c_flag = CFLAG_CLEAR; + m68k->x_flag = XFLAG_CLEAR; + m68k->n_flag = NFLAG_CLEAR; + m68k->not_z_flag = ZFLAG_SET; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + m68k->c_flag = CFLAG_CLEAR; + m68k->n_flag = NFLAG_32(src); + m68k->not_z_flag = src; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_asr_16_ai(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_AI_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = src >> 1; + + if(GET_MSB_16(src)) + res |= 0x8000; + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = m68k->x_flag = src << 8; +} + + +static void m68k_op_asr_16_pi(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PI_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = src >> 1; + + if(GET_MSB_16(src)) + res |= 0x8000; + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = m68k->x_flag = src << 8; +} + + +static void m68k_op_asr_16_pd(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PD_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = src >> 1; + + if(GET_MSB_16(src)) + res |= 0x8000; + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = m68k->x_flag = src << 8; +} + + +static void m68k_op_asr_16_di(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_DI_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = src >> 1; + + if(GET_MSB_16(src)) + res |= 0x8000; + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = m68k->x_flag = src << 8; +} + + +static void m68k_op_asr_16_ix(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_IX_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = src >> 1; + + if(GET_MSB_16(src)) + res |= 0x8000; + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = m68k->x_flag = src << 8; +} + + +static void m68k_op_asr_16_aw(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AW_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = src >> 1; + + if(GET_MSB_16(src)) + res |= 0x8000; + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = m68k->x_flag = src << 8; +} + + +static void m68k_op_asr_16_al(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AL_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = src >> 1; + + if(GET_MSB_16(src)) + res |= 0x8000; + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = m68k->x_flag = src << 8; +} + + +static void m68k_op_asl_8_s(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 shift = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 src = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = MASK_OUT_ABOVE_8(src << shift); + + if(shift != 0) + m68k->remaining_cycles -= shift<cyc_shift; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + m68k->x_flag = m68k->c_flag = src << shift; + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + src &= m68ki_shift_8_table[shift + 1]; + m68k->v_flag = (!(src == 0 || (src == m68ki_shift_8_table[shift + 1] && shift < 8)))<<7; +} + + +static void m68k_op_asl_16_s(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 shift = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 src = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = MASK_OUT_ABOVE_16(src << shift); + + if(shift != 0) + m68k->remaining_cycles -= shift<cyc_shift; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->x_flag = m68k->c_flag = src >> (8-shift); + src &= m68ki_shift_16_table[shift + 1]; + m68k->v_flag = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7; +} + + +static void m68k_op_asl_32_s(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 shift = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 src = *r_dst; + UINT32 res = MASK_OUT_ABOVE_32(src << shift); + + if(shift != 0) + m68k->remaining_cycles -= shift<cyc_shift; + + *r_dst = res; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->x_flag = m68k->c_flag = src >> (24-shift); + src &= m68ki_shift_32_table[shift + 1]; + m68k->v_flag = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7; +} + + +static void m68k_op_asl_8_r(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 shift = DX & 0x3f; + UINT32 src = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = MASK_OUT_ABOVE_8(src << shift); + + if(shift != 0) + { + m68k->remaining_cycles -= shift<cyc_shift; + + if(shift < 8) + { + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + m68k->x_flag = m68k->c_flag = src << shift; + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + src &= m68ki_shift_8_table[shift + 1]; + m68k->v_flag = (!(src == 0 || src == m68ki_shift_8_table[shift + 1]))<<7; + return; + } + + *r_dst &= 0xffffff00; + m68k->x_flag = m68k->c_flag = ((shift == 8 ? src & 1 : 0))<<8; + m68k->n_flag = NFLAG_CLEAR; + m68k->not_z_flag = ZFLAG_SET; + m68k->v_flag = (!(src == 0))<<7; + return; + } + + m68k->c_flag = CFLAG_CLEAR; + m68k->n_flag = NFLAG_8(src); + m68k->not_z_flag = src; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_asl_16_r(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 shift = DX & 0x3f; + UINT32 src = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = MASK_OUT_ABOVE_16(src << shift); + + if(shift != 0) + { + m68k->remaining_cycles -= shift<cyc_shift; + + if(shift < 16) + { + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + m68k->x_flag = m68k->c_flag = (src << shift) >> 8; + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + src &= m68ki_shift_16_table[shift + 1]; + m68k->v_flag = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7; + return; + } + + *r_dst &= 0xffff0000; + m68k->x_flag = m68k->c_flag = ((shift == 16 ? src & 1 : 0))<<8; + m68k->n_flag = NFLAG_CLEAR; + m68k->not_z_flag = ZFLAG_SET; + m68k->v_flag = (!(src == 0))<<7; + return; + } + + m68k->c_flag = CFLAG_CLEAR; + m68k->n_flag = NFLAG_16(src); + m68k->not_z_flag = src; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_asl_32_r(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 shift = DX & 0x3f; + UINT32 src = *r_dst; + UINT32 res = MASK_OUT_ABOVE_32(src << shift); + + if(shift != 0) + { + m68k->remaining_cycles -= shift<cyc_shift; + + if(shift < 32) + { + *r_dst = res; + m68k->x_flag = m68k->c_flag = (src >> (32 - shift)) << 8; + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + src &= m68ki_shift_32_table[shift + 1]; + m68k->v_flag = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7; + return; + } + + *r_dst = 0; + m68k->x_flag = m68k->c_flag = ((shift == 32 ? src & 1 : 0))<<8; + m68k->n_flag = NFLAG_CLEAR; + m68k->not_z_flag = ZFLAG_SET; + m68k->v_flag = (!(src == 0))<<7; + return; + } + + m68k->c_flag = CFLAG_CLEAR; + m68k->n_flag = NFLAG_32(src); + m68k->not_z_flag = src; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_asl_16_ai(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_AI_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = MASK_OUT_ABOVE_16(src << 1); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->x_flag = m68k->c_flag = src >> 7; + src &= 0xc000; + m68k->v_flag = (!(src == 0 || src == 0xc000))<<7; +} + + +static void m68k_op_asl_16_pi(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PI_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = MASK_OUT_ABOVE_16(src << 1); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->x_flag = m68k->c_flag = src >> 7; + src &= 0xc000; + m68k->v_flag = (!(src == 0 || src == 0xc000))<<7; +} + + +static void m68k_op_asl_16_pd(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PD_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = MASK_OUT_ABOVE_16(src << 1); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->x_flag = m68k->c_flag = src >> 7; + src &= 0xc000; + m68k->v_flag = (!(src == 0 || src == 0xc000))<<7; +} + + +static void m68k_op_asl_16_di(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_DI_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = MASK_OUT_ABOVE_16(src << 1); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->x_flag = m68k->c_flag = src >> 7; + src &= 0xc000; + m68k->v_flag = (!(src == 0 || src == 0xc000))<<7; +} + + +static void m68k_op_asl_16_ix(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_IX_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = MASK_OUT_ABOVE_16(src << 1); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->x_flag = m68k->c_flag = src >> 7; + src &= 0xc000; + m68k->v_flag = (!(src == 0 || src == 0xc000))<<7; +} + + +static void m68k_op_asl_16_aw(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AW_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = MASK_OUT_ABOVE_16(src << 1); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->x_flag = m68k->c_flag = src >> 7; + src &= 0xc000; + m68k->v_flag = (!(src == 0 || src == 0xc000))<<7; +} + + +static void m68k_op_asl_16_al(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AL_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = MASK_OUT_ABOVE_16(src << 1); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->x_flag = m68k->c_flag = src >> 7; + src &= 0xc000; + m68k->v_flag = (!(src == 0 || src == 0xc000))<<7; +} + + +static void m68k_op_bhi_8(m68ki_cpu_core *m68k) +{ + if(COND_HI(m68k)) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(m68k, MASK_OUT_ABOVE_8(m68k->ir)); + return; + } + m68k->remaining_cycles -= m68k->cyc_bcc_notake_b; +} + + +static void m68k_op_bls_8(m68ki_cpu_core *m68k) +{ + if(COND_LS(m68k)) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(m68k, MASK_OUT_ABOVE_8(m68k->ir)); + return; + } + m68k->remaining_cycles -= m68k->cyc_bcc_notake_b; +} + + +static void m68k_op_bcc_8(m68ki_cpu_core *m68k) +{ + if(COND_CC(m68k)) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(m68k, MASK_OUT_ABOVE_8(m68k->ir)); + return; + } + m68k->remaining_cycles -= m68k->cyc_bcc_notake_b; +} + + +static void m68k_op_bcs_8(m68ki_cpu_core *m68k) +{ + if(COND_CS(m68k)) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(m68k, MASK_OUT_ABOVE_8(m68k->ir)); + return; + } + m68k->remaining_cycles -= m68k->cyc_bcc_notake_b; +} + + +static void m68k_op_bne_8(m68ki_cpu_core *m68k) +{ + if(COND_NE(m68k)) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(m68k, MASK_OUT_ABOVE_8(m68k->ir)); + return; + } + m68k->remaining_cycles -= m68k->cyc_bcc_notake_b; +} + + +static void m68k_op_beq_8(m68ki_cpu_core *m68k) +{ + if(COND_EQ(m68k)) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(m68k, MASK_OUT_ABOVE_8(m68k->ir)); + return; + } + m68k->remaining_cycles -= m68k->cyc_bcc_notake_b; +} + + +static void m68k_op_bvc_8(m68ki_cpu_core *m68k) +{ + if(COND_VC(m68k)) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(m68k, MASK_OUT_ABOVE_8(m68k->ir)); + return; + } + m68k->remaining_cycles -= m68k->cyc_bcc_notake_b; +} + + +static void m68k_op_bvs_8(m68ki_cpu_core *m68k) +{ + if(COND_VS(m68k)) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(m68k, MASK_OUT_ABOVE_8(m68k->ir)); + return; + } + m68k->remaining_cycles -= m68k->cyc_bcc_notake_b; +} + + +static void m68k_op_bpl_8(m68ki_cpu_core *m68k) +{ + if(COND_PL(m68k)) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(m68k, MASK_OUT_ABOVE_8(m68k->ir)); + return; + } + m68k->remaining_cycles -= m68k->cyc_bcc_notake_b; +} + + +static void m68k_op_bmi_8(m68ki_cpu_core *m68k) +{ + if(COND_MI(m68k)) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(m68k, MASK_OUT_ABOVE_8(m68k->ir)); + return; + } + m68k->remaining_cycles -= m68k->cyc_bcc_notake_b; +} + + +static void m68k_op_bge_8(m68ki_cpu_core *m68k) +{ + if(COND_GE(m68k)) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(m68k, MASK_OUT_ABOVE_8(m68k->ir)); + return; + } + m68k->remaining_cycles -= m68k->cyc_bcc_notake_b; +} + + +static void m68k_op_blt_8(m68ki_cpu_core *m68k) +{ + if(COND_LT(m68k)) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(m68k, MASK_OUT_ABOVE_8(m68k->ir)); + return; + } + m68k->remaining_cycles -= m68k->cyc_bcc_notake_b; +} + + +static void m68k_op_bgt_8(m68ki_cpu_core *m68k) +{ + if(COND_GT(m68k)) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(m68k, MASK_OUT_ABOVE_8(m68k->ir)); + return; + } + m68k->remaining_cycles -= m68k->cyc_bcc_notake_b; +} + + +static void m68k_op_ble_8(m68ki_cpu_core *m68k) +{ + if(COND_LE(m68k)) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(m68k, MASK_OUT_ABOVE_8(m68k->ir)); + return; + } + m68k->remaining_cycles -= m68k->cyc_bcc_notake_b; +} + + +static void m68k_op_bhi_16(m68ki_cpu_core *m68k) +{ + if(COND_HI(m68k)) + { + UINT32 offset = OPER_I_16(m68k); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(m68k, offset); + return; + } + REG_PC += 2; + m68k->remaining_cycles -= m68k->cyc_bcc_notake_w; +} + + +static void m68k_op_bls_16(m68ki_cpu_core *m68k) +{ + if(COND_LS(m68k)) + { + UINT32 offset = OPER_I_16(m68k); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(m68k, offset); + return; + } + REG_PC += 2; + m68k->remaining_cycles -= m68k->cyc_bcc_notake_w; +} + + +static void m68k_op_bcc_16(m68ki_cpu_core *m68k) +{ + if(COND_CC(m68k)) + { + UINT32 offset = OPER_I_16(m68k); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(m68k, offset); + return; + } + REG_PC += 2; + m68k->remaining_cycles -= m68k->cyc_bcc_notake_w; +} + + +static void m68k_op_bcs_16(m68ki_cpu_core *m68k) +{ + if(COND_CS(m68k)) + { + UINT32 offset = OPER_I_16(m68k); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(m68k, offset); + return; + } + REG_PC += 2; + m68k->remaining_cycles -= m68k->cyc_bcc_notake_w; +} + + +static void m68k_op_bne_16(m68ki_cpu_core *m68k) +{ + if(COND_NE(m68k)) + { + UINT32 offset = OPER_I_16(m68k); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(m68k, offset); + return; + } + REG_PC += 2; + m68k->remaining_cycles -= m68k->cyc_bcc_notake_w; +} + + +static void m68k_op_beq_16(m68ki_cpu_core *m68k) +{ + if(COND_EQ(m68k)) + { + UINT32 offset = OPER_I_16(m68k); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(m68k, offset); + return; + } + REG_PC += 2; + m68k->remaining_cycles -= m68k->cyc_bcc_notake_w; +} + + +static void m68k_op_bvc_16(m68ki_cpu_core *m68k) +{ + if(COND_VC(m68k)) + { + UINT32 offset = OPER_I_16(m68k); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(m68k, offset); + return; + } + REG_PC += 2; + m68k->remaining_cycles -= m68k->cyc_bcc_notake_w; +} + + +static void m68k_op_bvs_16(m68ki_cpu_core *m68k) +{ + if(COND_VS(m68k)) + { + UINT32 offset = OPER_I_16(m68k); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(m68k, offset); + return; + } + REG_PC += 2; + m68k->remaining_cycles -= m68k->cyc_bcc_notake_w; +} + + +static void m68k_op_bpl_16(m68ki_cpu_core *m68k) +{ + if(COND_PL(m68k)) + { + UINT32 offset = OPER_I_16(m68k); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(m68k, offset); + return; + } + REG_PC += 2; + m68k->remaining_cycles -= m68k->cyc_bcc_notake_w; +} + + +static void m68k_op_bmi_16(m68ki_cpu_core *m68k) +{ + if(COND_MI(m68k)) + { + UINT32 offset = OPER_I_16(m68k); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(m68k, offset); + return; + } + REG_PC += 2; + m68k->remaining_cycles -= m68k->cyc_bcc_notake_w; +} + + +static void m68k_op_bge_16(m68ki_cpu_core *m68k) +{ + if(COND_GE(m68k)) + { + UINT32 offset = OPER_I_16(m68k); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(m68k, offset); + return; + } + REG_PC += 2; + m68k->remaining_cycles -= m68k->cyc_bcc_notake_w; +} + + +static void m68k_op_blt_16(m68ki_cpu_core *m68k) +{ + if(COND_LT(m68k)) + { + UINT32 offset = OPER_I_16(m68k); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(m68k, offset); + return; + } + REG_PC += 2; + m68k->remaining_cycles -= m68k->cyc_bcc_notake_w; +} + + +static void m68k_op_bgt_16(m68ki_cpu_core *m68k) +{ + if(COND_GT(m68k)) + { + UINT32 offset = OPER_I_16(m68k); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(m68k, offset); + return; + } + REG_PC += 2; + m68k->remaining_cycles -= m68k->cyc_bcc_notake_w; +} + + +static void m68k_op_ble_16(m68ki_cpu_core *m68k) +{ + if(COND_LE(m68k)) + { + UINT32 offset = OPER_I_16(m68k); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(m68k, offset); + return; + } + REG_PC += 2; + m68k->remaining_cycles -= m68k->cyc_bcc_notake_w; +} + + +static void m68k_op_bhi_32(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(COND_HI(m68k)) + { + UINT32 offset = OPER_I_32(m68k); + REG_PC -= 4; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_32(m68k, offset); + return; + } + REG_PC += 4; + return; + } + else + { + if(COND_HI(m68k)) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(m68k, MASK_OUT_ABOVE_8(m68k->ir)); + return; + } + m68k->remaining_cycles -= m68k->cyc_bcc_notake_b; + } +} + + +static void m68k_op_bls_32(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(COND_LS(m68k)) + { + UINT32 offset = OPER_I_32(m68k); + REG_PC -= 4; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_32(m68k, offset); + return; + } + REG_PC += 4; + return; + } + else + { + if(COND_LS(m68k)) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(m68k, MASK_OUT_ABOVE_8(m68k->ir)); + return; + } + m68k->remaining_cycles -= m68k->cyc_bcc_notake_b; + } +} + + +static void m68k_op_bcc_32(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(COND_CC(m68k)) + { + UINT32 offset = OPER_I_32(m68k); + REG_PC -= 4; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_32(m68k, offset); + return; + } + REG_PC += 4; + return; + } + else + { + if(COND_CC(m68k)) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(m68k, MASK_OUT_ABOVE_8(m68k->ir)); + return; + } + m68k->remaining_cycles -= m68k->cyc_bcc_notake_b; + } +} + + +static void m68k_op_bcs_32(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(COND_CS(m68k)) + { + UINT32 offset = OPER_I_32(m68k); + REG_PC -= 4; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_32(m68k, offset); + return; + } + REG_PC += 4; + return; + } + else + { + if(COND_CS(m68k)) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(m68k, MASK_OUT_ABOVE_8(m68k->ir)); + return; + } + m68k->remaining_cycles -= m68k->cyc_bcc_notake_b; + } +} + + +static void m68k_op_bne_32(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(COND_NE(m68k)) + { + UINT32 offset = OPER_I_32(m68k); + REG_PC -= 4; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_32(m68k, offset); + return; + } + REG_PC += 4; + return; + } + else + { + if(COND_NE(m68k)) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(m68k, MASK_OUT_ABOVE_8(m68k->ir)); + return; + } + m68k->remaining_cycles -= m68k->cyc_bcc_notake_b; + } +} + + +static void m68k_op_beq_32(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(COND_EQ(m68k)) + { + UINT32 offset = OPER_I_32(m68k); + REG_PC -= 4; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_32(m68k, offset); + return; + } + REG_PC += 4; + return; + } + else + { + if(COND_EQ(m68k)) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(m68k, MASK_OUT_ABOVE_8(m68k->ir)); + return; + } + m68k->remaining_cycles -= m68k->cyc_bcc_notake_b; + } +} + + +static void m68k_op_bvc_32(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(COND_VC(m68k)) + { + UINT32 offset = OPER_I_32(m68k); + REG_PC -= 4; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_32(m68k, offset); + return; + } + REG_PC += 4; + return; + } + else + { + if(COND_VC(m68k)) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(m68k, MASK_OUT_ABOVE_8(m68k->ir)); + return; + } + m68k->remaining_cycles -= m68k->cyc_bcc_notake_b; + } +} + + +static void m68k_op_bvs_32(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(COND_VS(m68k)) + { + UINT32 offset = OPER_I_32(m68k); + REG_PC -= 4; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_32(m68k, offset); + return; + } + REG_PC += 4; + return; + } + else + { + if(COND_VS(m68k)) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(m68k, MASK_OUT_ABOVE_8(m68k->ir)); + return; + } + m68k->remaining_cycles -= m68k->cyc_bcc_notake_b; + } +} + + +static void m68k_op_bpl_32(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(COND_PL(m68k)) + { + UINT32 offset = OPER_I_32(m68k); + REG_PC -= 4; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_32(m68k, offset); + return; + } + REG_PC += 4; + return; + } + else + { + if(COND_PL(m68k)) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(m68k, MASK_OUT_ABOVE_8(m68k->ir)); + return; + } + m68k->remaining_cycles -= m68k->cyc_bcc_notake_b; + } +} + + +static void m68k_op_bmi_32(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(COND_MI(m68k)) + { + UINT32 offset = OPER_I_32(m68k); + REG_PC -= 4; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_32(m68k, offset); + return; + } + REG_PC += 4; + return; + } + else + { + if(COND_MI(m68k)) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(m68k, MASK_OUT_ABOVE_8(m68k->ir)); + return; + } + m68k->remaining_cycles -= m68k->cyc_bcc_notake_b; + } +} + + +static void m68k_op_bge_32(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(COND_GE(m68k)) + { + UINT32 offset = OPER_I_32(m68k); + REG_PC -= 4; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_32(m68k, offset); + return; + } + REG_PC += 4; + return; + } + else + { + if(COND_GE(m68k)) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(m68k, MASK_OUT_ABOVE_8(m68k->ir)); + return; + } + m68k->remaining_cycles -= m68k->cyc_bcc_notake_b; + } +} + + +static void m68k_op_blt_32(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(COND_LT(m68k)) + { + UINT32 offset = OPER_I_32(m68k); + REG_PC -= 4; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_32(m68k, offset); + return; + } + REG_PC += 4; + return; + } + else + { + if(COND_LT(m68k)) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(m68k, MASK_OUT_ABOVE_8(m68k->ir)); + return; + } + m68k->remaining_cycles -= m68k->cyc_bcc_notake_b; + } +} + + +static void m68k_op_bgt_32(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(COND_GT(m68k)) + { + UINT32 offset = OPER_I_32(m68k); + REG_PC -= 4; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_32(m68k, offset); + return; + } + REG_PC += 4; + return; + } + else + { + if(COND_GT(m68k)) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(m68k, MASK_OUT_ABOVE_8(m68k->ir)); + return; + } + m68k->remaining_cycles -= m68k->cyc_bcc_notake_b; + } +} + + +static void m68k_op_ble_32(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(COND_LE(m68k)) + { + UINT32 offset = OPER_I_32(m68k); + REG_PC -= 4; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_32(m68k, offset); + return; + } + REG_PC += 4; + return; + } + else + { + if(COND_LE(m68k)) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(m68k, MASK_OUT_ABOVE_8(m68k->ir)); + return; + } + m68k->remaining_cycles -= m68k->cyc_bcc_notake_b; + } +} + + +static void m68k_op_bchg_32_r_d(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 mask = 1 << (DX & 0x1f); + + m68k->not_z_flag = *r_dst & mask; + *r_dst ^= mask; +} + + +static void m68k_op_bchg_8_r_ai(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_AI_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + UINT32 mask = 1 << (DX & 7); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src ^ mask); +} + + +static void m68k_op_bchg_8_r_pi(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PI_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + UINT32 mask = 1 << (DX & 7); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src ^ mask); +} + + +static void m68k_op_bchg_8_r_pi7(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_A7_PI_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + UINT32 mask = 1 << (DX & 7); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src ^ mask); +} + + +static void m68k_op_bchg_8_r_pd(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PD_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + UINT32 mask = 1 << (DX & 7); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src ^ mask); +} + + +static void m68k_op_bchg_8_r_pd7(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_A7_PD_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + UINT32 mask = 1 << (DX & 7); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src ^ mask); +} + + +static void m68k_op_bchg_8_r_di(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_DI_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + UINT32 mask = 1 << (DX & 7); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src ^ mask); +} + + +static void m68k_op_bchg_8_r_ix(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_IX_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + UINT32 mask = 1 << (DX & 7); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src ^ mask); +} + + +static void m68k_op_bchg_8_r_aw(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AW_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + UINT32 mask = 1 << (DX & 7); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src ^ mask); +} + + +static void m68k_op_bchg_8_r_al(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AL_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + UINT32 mask = 1 << (DX & 7); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src ^ mask); +} + + +static void m68k_op_bchg_32_s_d(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 mask = 1 << (OPER_I_8(m68k) & 0x1f); + + m68k->not_z_flag = *r_dst & mask; + *r_dst ^= mask; +} + + +static void m68k_op_bchg_8_s_ai(m68ki_cpu_core *m68k) +{ + UINT32 mask = 1 << (OPER_I_8(m68k) & 7); + UINT32 ea = EA_AY_AI_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src ^ mask); +} + + +static void m68k_op_bchg_8_s_pi(m68ki_cpu_core *m68k) +{ + UINT32 mask = 1 << (OPER_I_8(m68k) & 7); + UINT32 ea = EA_AY_PI_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src ^ mask); +} + + +static void m68k_op_bchg_8_s_pi7(m68ki_cpu_core *m68k) +{ + UINT32 mask = 1 << (OPER_I_8(m68k) & 7); + UINT32 ea = EA_A7_PI_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src ^ mask); +} + + +static void m68k_op_bchg_8_s_pd(m68ki_cpu_core *m68k) +{ + UINT32 mask = 1 << (OPER_I_8(m68k) & 7); + UINT32 ea = EA_AY_PD_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src ^ mask); +} + + +static void m68k_op_bchg_8_s_pd7(m68ki_cpu_core *m68k) +{ + UINT32 mask = 1 << (OPER_I_8(m68k) & 7); + UINT32 ea = EA_A7_PD_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src ^ mask); +} + + +static void m68k_op_bchg_8_s_di(m68ki_cpu_core *m68k) +{ + UINT32 mask = 1 << (OPER_I_8(m68k) & 7); + UINT32 ea = EA_AY_DI_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src ^ mask); +} + + +static void m68k_op_bchg_8_s_ix(m68ki_cpu_core *m68k) +{ + UINT32 mask = 1 << (OPER_I_8(m68k) & 7); + UINT32 ea = EA_AY_IX_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src ^ mask); +} + + +static void m68k_op_bchg_8_s_aw(m68ki_cpu_core *m68k) +{ + UINT32 mask = 1 << (OPER_I_8(m68k) & 7); + UINT32 ea = EA_AW_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src ^ mask); +} + + +static void m68k_op_bchg_8_s_al(m68ki_cpu_core *m68k) +{ + UINT32 mask = 1 << (OPER_I_8(m68k) & 7); + UINT32 ea = EA_AL_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src ^ mask); +} + + +static void m68k_op_bclr_32_r_d(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 mask = 1 << (DX & 0x1f); + + m68k->not_z_flag = *r_dst & mask; + *r_dst &= ~mask; +} + + +static void m68k_op_bclr_8_r_ai(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_AI_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + UINT32 mask = 1 << (DX & 7); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src & ~mask); +} + + +static void m68k_op_bclr_8_r_pi(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PI_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + UINT32 mask = 1 << (DX & 7); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src & ~mask); +} + + +static void m68k_op_bclr_8_r_pi7(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_A7_PI_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + UINT32 mask = 1 << (DX & 7); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src & ~mask); +} + + +static void m68k_op_bclr_8_r_pd(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PD_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + UINT32 mask = 1 << (DX & 7); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src & ~mask); +} + + +static void m68k_op_bclr_8_r_pd7(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_A7_PD_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + UINT32 mask = 1 << (DX & 7); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src & ~mask); +} + + +static void m68k_op_bclr_8_r_di(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_DI_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + UINT32 mask = 1 << (DX & 7); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src & ~mask); +} + + +static void m68k_op_bclr_8_r_ix(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_IX_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + UINT32 mask = 1 << (DX & 7); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src & ~mask); +} + + +static void m68k_op_bclr_8_r_aw(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AW_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + UINT32 mask = 1 << (DX & 7); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src & ~mask); +} + + +static void m68k_op_bclr_8_r_al(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AL_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + UINT32 mask = 1 << (DX & 7); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src & ~mask); +} + + +static void m68k_op_bclr_32_s_d(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 mask = 1 << (OPER_I_8(m68k) & 0x1f); + + m68k->not_z_flag = *r_dst & mask; + *r_dst &= ~mask; +} + + +static void m68k_op_bclr_8_s_ai(m68ki_cpu_core *m68k) +{ + UINT32 mask = 1 << (OPER_I_8(m68k) & 7); + UINT32 ea = EA_AY_AI_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src & ~mask); +} + + +static void m68k_op_bclr_8_s_pi(m68ki_cpu_core *m68k) +{ + UINT32 mask = 1 << (OPER_I_8(m68k) & 7); + UINT32 ea = EA_AY_PI_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src & ~mask); +} + + +static void m68k_op_bclr_8_s_pi7(m68ki_cpu_core *m68k) +{ + UINT32 mask = 1 << (OPER_I_8(m68k) & 7); + UINT32 ea = EA_A7_PI_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src & ~mask); +} + + +static void m68k_op_bclr_8_s_pd(m68ki_cpu_core *m68k) +{ + UINT32 mask = 1 << (OPER_I_8(m68k) & 7); + UINT32 ea = EA_AY_PD_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src & ~mask); +} + + +static void m68k_op_bclr_8_s_pd7(m68ki_cpu_core *m68k) +{ + UINT32 mask = 1 << (OPER_I_8(m68k) & 7); + UINT32 ea = EA_A7_PD_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src & ~mask); +} + + +static void m68k_op_bclr_8_s_di(m68ki_cpu_core *m68k) +{ + UINT32 mask = 1 << (OPER_I_8(m68k) & 7); + UINT32 ea = EA_AY_DI_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src & ~mask); +} + + +static void m68k_op_bclr_8_s_ix(m68ki_cpu_core *m68k) +{ + UINT32 mask = 1 << (OPER_I_8(m68k) & 7); + UINT32 ea = EA_AY_IX_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src & ~mask); +} + + +static void m68k_op_bclr_8_s_aw(m68ki_cpu_core *m68k) +{ + UINT32 mask = 1 << (OPER_I_8(m68k) & 7); + UINT32 ea = EA_AW_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src & ~mask); +} + + +static void m68k_op_bclr_8_s_al(m68ki_cpu_core *m68k) +{ + UINT32 mask = 1 << (OPER_I_8(m68k) & 7); + UINT32 ea = EA_AL_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src & ~mask); +} + + +static void m68k_op_bfchg_32_d(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32* data = &DY; + UINT64 mask; + + + if(BIT_B(word2)) + offset = REG_D[offset&7]; + if(BIT_5(word2)) + width = REG_D[width&7]; + + offset &= 31; + width = ((width-1) & 31) + 1; + + mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask = ROR_32(mask, offset); + + m68k->n_flag = NFLAG_32(*data<not_z_flag = *data & mask; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + *data ^= mask; + + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_bfchg_32_ai(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + INT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32 mask_base; + UINT32 data_long; + UINT32 mask_long; + UINT32 data_byte = 0; + UINT32 mask_byte = 0; + UINT32 ea = EA_AY_AI_8(m68k); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(m68k, ea); + m68k->n_flag = NFLAG_32(data_long << offset); + m68k->not_z_flag = data_long & mask_long; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + m68ki_write_32(m68k, ea, data_long ^ mask_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(m68k, ea+4); + m68k->not_z_flag |= (data_byte & mask_byte); + m68ki_write_8(m68k, ea+4, data_byte ^ mask_byte); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_bfchg_32_di(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + INT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32 mask_base; + UINT32 data_long; + UINT32 mask_long; + UINT32 data_byte = 0; + UINT32 mask_byte = 0; + UINT32 ea = EA_AY_DI_8(m68k); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(m68k, ea); + m68k->n_flag = NFLAG_32(data_long << offset); + m68k->not_z_flag = data_long & mask_long; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + m68ki_write_32(m68k, ea, data_long ^ mask_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(m68k, ea+4); + m68k->not_z_flag |= (data_byte & mask_byte); + m68ki_write_8(m68k, ea+4, data_byte ^ mask_byte); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_bfchg_32_ix(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + INT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32 mask_base; + UINT32 data_long; + UINT32 mask_long; + UINT32 data_byte = 0; + UINT32 mask_byte = 0; + UINT32 ea = EA_AY_IX_8(m68k); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(m68k, ea); + m68k->n_flag = NFLAG_32(data_long << offset); + m68k->not_z_flag = data_long & mask_long; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + m68ki_write_32(m68k, ea, data_long ^ mask_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(m68k, ea+4); + m68k->not_z_flag |= (data_byte & mask_byte); + m68ki_write_8(m68k, ea+4, data_byte ^ mask_byte); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_bfchg_32_aw(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + INT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32 mask_base; + UINT32 data_long; + UINT32 mask_long; + UINT32 data_byte = 0; + UINT32 mask_byte = 0; + UINT32 ea = EA_AW_8(m68k); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(m68k, ea); + m68k->n_flag = NFLAG_32(data_long << offset); + m68k->not_z_flag = data_long & mask_long; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + m68ki_write_32(m68k, ea, data_long ^ mask_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(m68k, ea+4); + m68k->not_z_flag |= (data_byte & mask_byte); + m68ki_write_8(m68k, ea+4, data_byte ^ mask_byte); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_bfchg_32_al(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + INT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32 mask_base; + UINT32 data_long; + UINT32 mask_long; + UINT32 data_byte = 0; + UINT32 mask_byte = 0; + UINT32 ea = EA_AL_8(m68k); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(m68k, ea); + m68k->n_flag = NFLAG_32(data_long << offset); + m68k->not_z_flag = data_long & mask_long; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + m68ki_write_32(m68k, ea, data_long ^ mask_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(m68k, ea+4); + m68k->not_z_flag |= (data_byte & mask_byte); + m68ki_write_8(m68k, ea+4, data_byte ^ mask_byte); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_bfclr_32_d(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32* data = &DY; + UINT64 mask; + + + if(BIT_B(word2)) + offset = REG_D[offset&7]; + if(BIT_5(word2)) + width = REG_D[width&7]; + + + offset &= 31; + width = ((width-1) & 31) + 1; + + + mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask = ROR_32(mask, offset); + + m68k->n_flag = NFLAG_32(*data<not_z_flag = *data & mask; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + *data &= ~mask; + + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_bfclr_32_ai(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + INT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32 mask_base; + UINT32 data_long; + UINT32 mask_long; + UINT32 data_byte = 0; + UINT32 mask_byte = 0; + UINT32 ea = EA_AY_AI_8(m68k); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(m68k, ea); + m68k->n_flag = NFLAG_32(data_long << offset); + m68k->not_z_flag = data_long & mask_long; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + m68ki_write_32(m68k, ea, data_long & ~mask_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(m68k, ea+4); + m68k->not_z_flag |= (data_byte & mask_byte); + m68ki_write_8(m68k, ea+4, data_byte & ~mask_byte); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_bfclr_32_di(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + INT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32 mask_base; + UINT32 data_long; + UINT32 mask_long; + UINT32 data_byte = 0; + UINT32 mask_byte = 0; + UINT32 ea = EA_AY_DI_8(m68k); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(m68k, ea); + m68k->n_flag = NFLAG_32(data_long << offset); + m68k->not_z_flag = data_long & mask_long; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + m68ki_write_32(m68k, ea, data_long & ~mask_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(m68k, ea+4); + m68k->not_z_flag |= (data_byte & mask_byte); + m68ki_write_8(m68k, ea+4, data_byte & ~mask_byte); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_bfclr_32_ix(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + INT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32 mask_base; + UINT32 data_long; + UINT32 mask_long; + UINT32 data_byte = 0; + UINT32 mask_byte = 0; + UINT32 ea = EA_AY_IX_8(m68k); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(m68k, ea); + m68k->n_flag = NFLAG_32(data_long << offset); + m68k->not_z_flag = data_long & mask_long; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + m68ki_write_32(m68k, ea, data_long & ~mask_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(m68k, ea+4); + m68k->not_z_flag |= (data_byte & mask_byte); + m68ki_write_8(m68k, ea+4, data_byte & ~mask_byte); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_bfclr_32_aw(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + INT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32 mask_base; + UINT32 data_long; + UINT32 mask_long; + UINT32 data_byte = 0; + UINT32 mask_byte = 0; + UINT32 ea = EA_AW_8(m68k); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(m68k, ea); + m68k->n_flag = NFLAG_32(data_long << offset); + m68k->not_z_flag = data_long & mask_long; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + m68ki_write_32(m68k, ea, data_long & ~mask_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(m68k, ea+4); + m68k->not_z_flag |= (data_byte & mask_byte); + m68ki_write_8(m68k, ea+4, data_byte & ~mask_byte); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_bfclr_32_al(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + INT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32 mask_base; + UINT32 data_long; + UINT32 mask_long; + UINT32 data_byte = 0; + UINT32 mask_byte = 0; + UINT32 ea = EA_AL_8(m68k); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(m68k, ea); + m68k->n_flag = NFLAG_32(data_long << offset); + m68k->not_z_flag = data_long & mask_long; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + m68ki_write_32(m68k, ea, data_long & ~mask_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(m68k, ea+4); + m68k->not_z_flag |= (data_byte & mask_byte); + m68ki_write_8(m68k, ea+4, data_byte & ~mask_byte); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_bfexts_32_d(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT64 data = DY; + + + if(BIT_B(word2)) + offset = REG_D[offset&7]; + if(BIT_5(word2)) + width = REG_D[width&7]; + + offset &= 31; + width = ((width-1) & 31) + 1; + + data = ROL_32(data, offset); + m68k->n_flag = NFLAG_32(data); + data = MAKE_INT_32(data) >> (32 - width); + + m68k->not_z_flag = data; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + REG_D[(word2>>12)&7] = data; + + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_bfexts_32_ai(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + INT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32 data; + UINT32 ea = EA_AY_AI_8(m68k); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(m68k, ea); + + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(m68k, ea+4) << offset) >> 8; + + m68k->n_flag = NFLAG_32(data); + data = MAKE_INT_32(data) >> (32 - width); + + m68k->not_z_flag = data; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + REG_D[(word2 >> 12) & 7] = data; + + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_bfexts_32_di(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + INT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32 data; + UINT32 ea = EA_AY_DI_8(m68k); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(m68k, ea); + + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(m68k, ea+4) << offset) >> 8; + + m68k->n_flag = NFLAG_32(data); + data = MAKE_INT_32(data) >> (32 - width); + + m68k->not_z_flag = data; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + REG_D[(word2 >> 12) & 7] = data; + + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_bfexts_32_ix(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + INT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32 data; + UINT32 ea = EA_AY_IX_8(m68k); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(m68k, ea); + + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(m68k, ea+4) << offset) >> 8; + + m68k->n_flag = NFLAG_32(data); + data = MAKE_INT_32(data) >> (32 - width); + + m68k->not_z_flag = data; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + REG_D[(word2 >> 12) & 7] = data; + + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_bfexts_32_aw(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + INT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32 data; + UINT32 ea = EA_AW_8(m68k); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(m68k, ea); + + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(m68k, ea+4) << offset) >> 8; + + m68k->n_flag = NFLAG_32(data); + data = MAKE_INT_32(data) >> (32 - width); + + m68k->not_z_flag = data; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + REG_D[(word2 >> 12) & 7] = data; + + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_bfexts_32_al(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + INT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32 data; + UINT32 ea = EA_AL_8(m68k); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(m68k, ea); + + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(m68k, ea+4) << offset) >> 8; + + m68k->n_flag = NFLAG_32(data); + data = MAKE_INT_32(data) >> (32 - width); + + m68k->not_z_flag = data; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + REG_D[(word2 >> 12) & 7] = data; + + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_bfexts_32_pcdi(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + INT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32 data; + UINT32 ea = EA_PCDI_8(m68k); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(m68k, ea); + + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(m68k, ea+4) << offset) >> 8; + + m68k->n_flag = NFLAG_32(data); + data = MAKE_INT_32(data) >> (32 - width); + + m68k->not_z_flag = data; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + REG_D[(word2 >> 12) & 7] = data; + + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_bfexts_32_pcix(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + INT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32 data; + UINT32 ea = EA_PCIX_8(m68k); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(m68k, ea); + + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(m68k, ea+4) << offset) >> 8; + + m68k->n_flag = NFLAG_32(data); + data = MAKE_INT_32(data) >> (32 - width); + + m68k->not_z_flag = data; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + REG_D[(word2 >> 12) & 7] = data; + + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_bfextu_32_d(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT64 data = DY; + + + if(BIT_B(word2)) + offset = REG_D[offset&7]; + if(BIT_5(word2)) + width = REG_D[width&7]; + + offset &= 31; + width = ((width-1) & 31) + 1; + + data = ROL_32(data, offset); + m68k->n_flag = NFLAG_32(data); + data >>= 32 - width; + + m68k->not_z_flag = data; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + REG_D[(word2>>12)&7] = data; + + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_bfextu_32_ai(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + INT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32 data; + UINT32 ea = EA_AY_AI_8(m68k); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(m68k, ea); + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(m68k, ea+4) << offset) >> 8; + + m68k->n_flag = NFLAG_32(data); + data >>= (32 - width); + + m68k->not_z_flag = data; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + REG_D[(word2 >> 12) & 7] = data; + + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_bfextu_32_di(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + INT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32 data; + UINT32 ea = EA_AY_DI_8(m68k); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(m68k, ea); + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(m68k, ea+4) << offset) >> 8; + + m68k->n_flag = NFLAG_32(data); + data >>= (32 - width); + + m68k->not_z_flag = data; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + REG_D[(word2 >> 12) & 7] = data; + + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_bfextu_32_ix(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + INT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32 data; + UINT32 ea = EA_AY_IX_8(m68k); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(m68k, ea); + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(m68k, ea+4) << offset) >> 8; + + m68k->n_flag = NFLAG_32(data); + data >>= (32 - width); + + m68k->not_z_flag = data; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + REG_D[(word2 >> 12) & 7] = data; + + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_bfextu_32_aw(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + INT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32 data; + UINT32 ea = EA_AW_8(m68k); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(m68k, ea); + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(m68k, ea+4) << offset) >> 8; + + m68k->n_flag = NFLAG_32(data); + data >>= (32 - width); + + m68k->not_z_flag = data; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + REG_D[(word2 >> 12) & 7] = data; + + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_bfextu_32_al(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + INT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32 data; + UINT32 ea = EA_AL_8(m68k); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(m68k, ea); + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(m68k, ea+4) << offset) >> 8; + + m68k->n_flag = NFLAG_32(data); + data >>= (32 - width); + + m68k->not_z_flag = data; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + REG_D[(word2 >> 12) & 7] = data; + + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_bfextu_32_pcdi(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + INT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32 data; + UINT32 ea = EA_PCDI_8(m68k); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(m68k, ea); + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(m68k, ea+4) << offset) >> 8; + + m68k->n_flag = NFLAG_32(data); + data >>= (32 - width); + + m68k->not_z_flag = data; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + REG_D[(word2 >> 12) & 7] = data; + + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_bfextu_32_pcix(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + INT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32 data; + UINT32 ea = EA_PCIX_8(m68k); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(m68k, ea); + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(m68k, ea+4) << offset) >> 8; + + m68k->n_flag = NFLAG_32(data); + data >>= (32 - width); + + m68k->not_z_flag = data; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + REG_D[(word2 >> 12) & 7] = data; + + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_bfffo_32_d(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT64 data = DY; + UINT32 bit; + + + if(BIT_B(word2)) + offset = REG_D[offset&7]; + if(BIT_5(word2)) + width = REG_D[width&7]; + + offset &= 31; + width = ((width-1) & 31) + 1; + + data = ROL_32(data, offset); + m68k->n_flag = NFLAG_32(data); + data >>= 32 - width; + + m68k->not_z_flag = data; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1) + offset++; + + REG_D[(word2>>12)&7] = offset; + + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_bfffo_32_ai(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + INT32 offset = (word2>>6)&31; + INT32 local_offset; + UINT32 width = word2; + UINT32 data; + UINT32 bit; + UINT32 ea = EA_AY_AI_8(m68k); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + local_offset = offset % 8; + if(local_offset < 0) + { + local_offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(m68k, ea); + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(m68k, ea+4) << local_offset) >> 8; + + m68k->n_flag = NFLAG_32(data); + data >>= (32 - width); + + m68k->not_z_flag = data; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1) + offset++; + + REG_D[(word2>>12)&7] = offset; + + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_bfffo_32_di(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + INT32 offset = (word2>>6)&31; + INT32 local_offset; + UINT32 width = word2; + UINT32 data; + UINT32 bit; + UINT32 ea = EA_AY_DI_8(m68k); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + local_offset = offset % 8; + if(local_offset < 0) + { + local_offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(m68k, ea); + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(m68k, ea+4) << local_offset) >> 8; + + m68k->n_flag = NFLAG_32(data); + data >>= (32 - width); + + m68k->not_z_flag = data; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1) + offset++; + + REG_D[(word2>>12)&7] = offset; + + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_bfffo_32_ix(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + INT32 offset = (word2>>6)&31; + INT32 local_offset; + UINT32 width = word2; + UINT32 data; + UINT32 bit; + UINT32 ea = EA_AY_IX_8(m68k); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + local_offset = offset % 8; + if(local_offset < 0) + { + local_offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(m68k, ea); + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(m68k, ea+4) << local_offset) >> 8; + + m68k->n_flag = NFLAG_32(data); + data >>= (32 - width); + + m68k->not_z_flag = data; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1) + offset++; + + REG_D[(word2>>12)&7] = offset; + + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_bfffo_32_aw(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + INT32 offset = (word2>>6)&31; + INT32 local_offset; + UINT32 width = word2; + UINT32 data; + UINT32 bit; + UINT32 ea = EA_AW_8(m68k); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + local_offset = offset % 8; + if(local_offset < 0) + { + local_offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(m68k, ea); + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(m68k, ea+4) << local_offset) >> 8; + + m68k->n_flag = NFLAG_32(data); + data >>= (32 - width); + + m68k->not_z_flag = data; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1) + offset++; + + REG_D[(word2>>12)&7] = offset; + + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_bfffo_32_al(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + INT32 offset = (word2>>6)&31; + INT32 local_offset; + UINT32 width = word2; + UINT32 data; + UINT32 bit; + UINT32 ea = EA_AL_8(m68k); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + local_offset = offset % 8; + if(local_offset < 0) + { + local_offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(m68k, ea); + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(m68k, ea+4) << local_offset) >> 8; + + m68k->n_flag = NFLAG_32(data); + data >>= (32 - width); + + m68k->not_z_flag = data; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1) + offset++; + + REG_D[(word2>>12)&7] = offset; + + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_bfffo_32_pcdi(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + INT32 offset = (word2>>6)&31; + INT32 local_offset; + UINT32 width = word2; + UINT32 data; + UINT32 bit; + UINT32 ea = EA_PCDI_8(m68k); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + local_offset = offset % 8; + if(local_offset < 0) + { + local_offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(m68k, ea); + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(m68k, ea+4) << local_offset) >> 8; + + m68k->n_flag = NFLAG_32(data); + data >>= (32 - width); + + m68k->not_z_flag = data; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1) + offset++; + + REG_D[(word2>>12)&7] = offset; + + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_bfffo_32_pcix(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + INT32 offset = (word2>>6)&31; + INT32 local_offset; + UINT32 width = word2; + UINT32 data; + UINT32 bit; + UINT32 ea = EA_PCIX_8(m68k); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + local_offset = offset % 8; + if(local_offset < 0) + { + local_offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(m68k, ea); + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(m68k, ea+4) << local_offset) >> 8; + + m68k->n_flag = NFLAG_32(data); + data >>= (32 - width); + + m68k->not_z_flag = data; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1) + offset++; + + REG_D[(word2>>12)&7] = offset; + + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_bfins_32_d(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32* data = &DY; + UINT64 mask; + UINT64 insert = REG_D[(word2>>12)&7]; + + + if(BIT_B(word2)) + offset = REG_D[offset&7]; + if(BIT_5(word2)) + width = REG_D[width&7]; + + + offset &= 31; + width = ((width-1) & 31) + 1; + + + mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask = ROR_32(mask, offset); + + insert = MASK_OUT_ABOVE_32(insert << (32 - width)); + m68k->n_flag = NFLAG_32(insert); + m68k->not_z_flag = insert; + insert = ROR_32(insert, offset); + + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + *data &= ~mask; + *data |= insert; + + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_bfins_32_ai(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + INT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32 insert_base = REG_D[(word2>>12)&7]; + UINT32 insert_long; + UINT32 insert_byte; + UINT32 mask_base; + UINT32 data_long; + UINT32 mask_long; + UINT32 data_byte = 0; + UINT32 mask_byte = 0; + UINT32 ea = EA_AY_AI_8(m68k); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + insert_base = MASK_OUT_ABOVE_32(insert_base << (32 - width)); + m68k->n_flag = NFLAG_32(insert_base); + m68k->not_z_flag = insert_base; + insert_long = insert_base >> offset; + + data_long = m68ki_read_32(m68k, ea); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + m68ki_write_32(m68k, ea, (data_long & ~mask_long) | insert_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + insert_byte = MASK_OUT_ABOVE_8(insert_base); + data_byte = m68ki_read_8(m68k, ea+4); + m68k->not_z_flag |= (data_byte & mask_byte); + m68ki_write_8(m68k, ea+4, (data_byte & ~mask_byte) | insert_byte); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_bfins_32_di(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + INT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32 insert_base = REG_D[(word2>>12)&7]; + UINT32 insert_long; + UINT32 insert_byte; + UINT32 mask_base; + UINT32 data_long; + UINT32 mask_long; + UINT32 data_byte = 0; + UINT32 mask_byte = 0; + UINT32 ea = EA_AY_DI_8(m68k); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + insert_base = MASK_OUT_ABOVE_32(insert_base << (32 - width)); + m68k->n_flag = NFLAG_32(insert_base); + m68k->not_z_flag = insert_base; + insert_long = insert_base >> offset; + + data_long = m68ki_read_32(m68k, ea); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + m68ki_write_32(m68k, ea, (data_long & ~mask_long) | insert_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + insert_byte = MASK_OUT_ABOVE_8(insert_base); + data_byte = m68ki_read_8(m68k, ea+4); + m68k->not_z_flag |= (data_byte & mask_byte); + m68ki_write_8(m68k, ea+4, (data_byte & ~mask_byte) | insert_byte); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_bfins_32_ix(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + INT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32 insert_base = REG_D[(word2>>12)&7]; + UINT32 insert_long; + UINT32 insert_byte; + UINT32 mask_base; + UINT32 data_long; + UINT32 mask_long; + UINT32 data_byte = 0; + UINT32 mask_byte = 0; + UINT32 ea = EA_AY_IX_8(m68k); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + insert_base = MASK_OUT_ABOVE_32(insert_base << (32 - width)); + m68k->n_flag = NFLAG_32(insert_base); + m68k->not_z_flag = insert_base; + insert_long = insert_base >> offset; + + data_long = m68ki_read_32(m68k, ea); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + m68ki_write_32(m68k, ea, (data_long & ~mask_long) | insert_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + insert_byte = MASK_OUT_ABOVE_8(insert_base); + data_byte = m68ki_read_8(m68k, ea+4); + m68k->not_z_flag |= (data_byte & mask_byte); + m68ki_write_8(m68k, ea+4, (data_byte & ~mask_byte) | insert_byte); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_bfins_32_aw(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + INT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32 insert_base = REG_D[(word2>>12)&7]; + UINT32 insert_long; + UINT32 insert_byte; + UINT32 mask_base; + UINT32 data_long; + UINT32 mask_long; + UINT32 data_byte = 0; + UINT32 mask_byte = 0; + UINT32 ea = EA_AW_8(m68k); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + insert_base = MASK_OUT_ABOVE_32(insert_base << (32 - width)); + m68k->n_flag = NFLAG_32(insert_base); + m68k->not_z_flag = insert_base; + insert_long = insert_base >> offset; + + data_long = m68ki_read_32(m68k, ea); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + m68ki_write_32(m68k, ea, (data_long & ~mask_long) | insert_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + insert_byte = MASK_OUT_ABOVE_8(insert_base); + data_byte = m68ki_read_8(m68k, ea+4); + m68k->not_z_flag |= (data_byte & mask_byte); + m68ki_write_8(m68k, ea+4, (data_byte & ~mask_byte) | insert_byte); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_bfins_32_al(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + INT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32 insert_base = REG_D[(word2>>12)&7]; + UINT32 insert_long; + UINT32 insert_byte; + UINT32 mask_base; + UINT32 data_long; + UINT32 mask_long; + UINT32 data_byte = 0; + UINT32 mask_byte = 0; + UINT32 ea = EA_AL_8(m68k); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + insert_base = MASK_OUT_ABOVE_32(insert_base << (32 - width)); + m68k->n_flag = NFLAG_32(insert_base); + m68k->not_z_flag = insert_base; + insert_long = insert_base >> offset; + + data_long = m68ki_read_32(m68k, ea); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + m68ki_write_32(m68k, ea, (data_long & ~mask_long) | insert_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + insert_byte = MASK_OUT_ABOVE_8(insert_base); + data_byte = m68ki_read_8(m68k, ea+4); + m68k->not_z_flag |= (data_byte & mask_byte); + m68ki_write_8(m68k, ea+4, (data_byte & ~mask_byte) | insert_byte); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_bfset_32_d(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32* data = &DY; + UINT64 mask; + + + if(BIT_B(word2)) + offset = REG_D[offset&7]; + if(BIT_5(word2)) + width = REG_D[width&7]; + + + offset &= 31; + width = ((width-1) & 31) + 1; + + + mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask = ROR_32(mask, offset); + + m68k->n_flag = NFLAG_32(*data<not_z_flag = *data & mask; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + *data |= mask; + + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_bfset_32_ai(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + INT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32 mask_base; + UINT32 data_long; + UINT32 mask_long; + UINT32 data_byte = 0; + UINT32 mask_byte = 0; + UINT32 ea = EA_AY_AI_8(m68k); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(m68k, ea); + m68k->n_flag = NFLAG_32(data_long << offset); + m68k->not_z_flag = data_long & mask_long; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + m68ki_write_32(m68k, ea, data_long | mask_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(m68k, ea+4); + m68k->not_z_flag |= (data_byte & mask_byte); + m68ki_write_8(m68k, ea+4, data_byte | mask_byte); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_bfset_32_di(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + INT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32 mask_base; + UINT32 data_long; + UINT32 mask_long; + UINT32 data_byte = 0; + UINT32 mask_byte = 0; + UINT32 ea = EA_AY_DI_8(m68k); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(m68k, ea); + m68k->n_flag = NFLAG_32(data_long << offset); + m68k->not_z_flag = data_long & mask_long; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + m68ki_write_32(m68k, ea, data_long | mask_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(m68k, ea+4); + m68k->not_z_flag |= (data_byte & mask_byte); + m68ki_write_8(m68k, ea+4, data_byte | mask_byte); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_bfset_32_ix(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + INT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32 mask_base; + UINT32 data_long; + UINT32 mask_long; + UINT32 data_byte = 0; + UINT32 mask_byte = 0; + UINT32 ea = EA_AY_IX_8(m68k); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(m68k, ea); + m68k->n_flag = NFLAG_32(data_long << offset); + m68k->not_z_flag = data_long & mask_long; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + m68ki_write_32(m68k, ea, data_long | mask_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(m68k, ea+4); + m68k->not_z_flag |= (data_byte & mask_byte); + m68ki_write_8(m68k, ea+4, data_byte | mask_byte); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_bfset_32_aw(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + INT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32 mask_base; + UINT32 data_long; + UINT32 mask_long; + UINT32 data_byte = 0; + UINT32 mask_byte = 0; + UINT32 ea = EA_AW_8(m68k); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(m68k, ea); + m68k->n_flag = NFLAG_32(data_long << offset); + m68k->not_z_flag = data_long & mask_long; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + m68ki_write_32(m68k, ea, data_long | mask_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(m68k, ea+4); + m68k->not_z_flag |= (data_byte & mask_byte); + m68ki_write_8(m68k, ea+4, data_byte | mask_byte); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_bfset_32_al(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + INT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32 mask_base; + UINT32 data_long; + UINT32 mask_long; + UINT32 data_byte = 0; + UINT32 mask_byte = 0; + UINT32 ea = EA_AL_8(m68k); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(m68k, ea); + m68k->n_flag = NFLAG_32(data_long << offset); + m68k->not_z_flag = data_long & mask_long; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + m68ki_write_32(m68k, ea, data_long | mask_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(m68k, ea+4); + m68k->not_z_flag |= (data_byte & mask_byte); + m68ki_write_8(m68k, ea+4, data_byte | mask_byte); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_bftst_32_d(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32* data = &DY; + UINT64 mask; + + + if(BIT_B(word2)) + offset = REG_D[offset&7]; + if(BIT_5(word2)) + width = REG_D[width&7]; + + + offset &= 31; + width = ((width-1) & 31) + 1; + + + mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask = ROR_32(mask, offset); + + m68k->n_flag = NFLAG_32(*data<not_z_flag = *data & mask; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_bftst_32_ai(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + INT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32 mask_base; + UINT32 data_long; + UINT32 mask_long; + UINT32 data_byte = 0; + UINT32 mask_byte = 0; + UINT32 ea = EA_AY_AI_8(m68k); + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(m68k, ea); + m68k->n_flag = ((data_long & (0x80000000 >> offset))<>24; + m68k->not_z_flag = data_long & mask_long; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(m68k, ea+4); + m68k->not_z_flag |= (data_byte & mask_byte); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_bftst_32_di(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + INT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32 mask_base; + UINT32 data_long; + UINT32 mask_long; + UINT32 data_byte = 0; + UINT32 mask_byte = 0; + UINT32 ea = EA_AY_DI_8(m68k); + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(m68k, ea); + m68k->n_flag = ((data_long & (0x80000000 >> offset))<>24; + m68k->not_z_flag = data_long & mask_long; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(m68k, ea+4); + m68k->not_z_flag |= (data_byte & mask_byte); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_bftst_32_ix(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + INT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32 mask_base; + UINT32 data_long; + UINT32 mask_long; + UINT32 data_byte = 0; + UINT32 mask_byte = 0; + UINT32 ea = EA_AY_IX_8(m68k); + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(m68k, ea); + m68k->n_flag = ((data_long & (0x80000000 >> offset))<>24; + m68k->not_z_flag = data_long & mask_long; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(m68k, ea+4); + m68k->not_z_flag |= (data_byte & mask_byte); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_bftst_32_aw(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + INT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32 mask_base; + UINT32 data_long; + UINT32 mask_long; + UINT32 data_byte = 0; + UINT32 mask_byte = 0; + UINT32 ea = EA_AW_8(m68k); + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(m68k, ea); + m68k->n_flag = ((data_long & (0x80000000 >> offset))<>24; + m68k->not_z_flag = data_long & mask_long; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(m68k, ea+4); + m68k->not_z_flag |= (data_byte & mask_byte); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_bftst_32_al(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + INT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32 mask_base; + UINT32 data_long; + UINT32 mask_long; + UINT32 data_byte = 0; + UINT32 mask_byte = 0; + UINT32 ea = EA_AL_8(m68k); + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(m68k, ea); + m68k->n_flag = ((data_long & (0x80000000 >> offset))<>24; + m68k->not_z_flag = data_long & mask_long; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(m68k, ea+4); + m68k->not_z_flag |= (data_byte & mask_byte); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_bftst_32_pcdi(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + INT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32 mask_base; + UINT32 data_long; + UINT32 mask_long; + UINT32 data_byte = 0; + UINT32 mask_byte = 0; + UINT32 ea = EA_PCDI_8(m68k); + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(m68k, ea); + m68k->n_flag = ((data_long & (0x80000000 >> offset))<>24; + m68k->not_z_flag = data_long & mask_long; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(m68k, ea+4); + m68k->not_z_flag |= (data_byte & mask_byte); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_bftst_32_pcix(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + INT32 offset = (word2>>6)&31; + UINT32 width = word2; + UINT32 mask_base; + UINT32 data_long; + UINT32 mask_long; + UINT32 data_byte = 0; + UINT32 mask_byte = 0; + UINT32 ea = EA_PCIX_8(m68k); + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(m68k, ea); + m68k->n_flag = ((data_long & (0x80000000 >> offset))<>24; + m68k->not_z_flag = data_long & mask_long; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(m68k, ea+4); + m68k->not_z_flag |= (data_byte & mask_byte); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_bkpt(m68ki_cpu_core *m68k) +{ + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_bra_8(m68ki_cpu_core *m68k) +{ + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(m68k, MASK_OUT_ABOVE_8(m68k->ir)); + if(REG_PC == REG_PPC && m68k->remaining_cycles > 0) + m68k->remaining_cycles = 0; +} + + +static void m68k_op_bra_16(m68ki_cpu_core *m68k) +{ + UINT32 offset = OPER_I_16(m68k); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(m68k, offset); + if(REG_PC == REG_PPC && m68k->remaining_cycles > 0) + m68k->remaining_cycles = 0; +} + + +static void m68k_op_bra_32(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 offset = OPER_I_32(m68k); + REG_PC -= 4; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_32(m68k, offset); + if(REG_PC == REG_PPC && m68k->remaining_cycles > 0) + m68k->remaining_cycles = 0; + return; + } + else + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(m68k, MASK_OUT_ABOVE_8(m68k->ir)); + if(REG_PC == REG_PPC && m68k->remaining_cycles > 0) + m68k->remaining_cycles = 0; + } +} + + +static void m68k_op_bset_32_r_d(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 mask = 1 << (DX & 0x1f); + + m68k->not_z_flag = *r_dst & mask; + *r_dst |= mask; +} + + +static void m68k_op_bset_8_r_ai(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_AI_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + UINT32 mask = 1 << (DX & 7); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src | mask); +} + + +static void m68k_op_bset_8_r_pi(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PI_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + UINT32 mask = 1 << (DX & 7); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src | mask); +} + + +static void m68k_op_bset_8_r_pi7(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_A7_PI_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + UINT32 mask = 1 << (DX & 7); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src | mask); +} + + +static void m68k_op_bset_8_r_pd(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PD_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + UINT32 mask = 1 << (DX & 7); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src | mask); +} + + +static void m68k_op_bset_8_r_pd7(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_A7_PD_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + UINT32 mask = 1 << (DX & 7); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src | mask); +} + + +static void m68k_op_bset_8_r_di(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_DI_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + UINT32 mask = 1 << (DX & 7); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src | mask); +} + + +static void m68k_op_bset_8_r_ix(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_IX_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + UINT32 mask = 1 << (DX & 7); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src | mask); +} + + +static void m68k_op_bset_8_r_aw(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AW_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + UINT32 mask = 1 << (DX & 7); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src | mask); +} + + +static void m68k_op_bset_8_r_al(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AL_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + UINT32 mask = 1 << (DX & 7); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src | mask); +} + + +static void m68k_op_bset_32_s_d(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 mask = 1 << (OPER_I_8(m68k) & 0x1f); + + m68k->not_z_flag = *r_dst & mask; + *r_dst |= mask; +} + + +static void m68k_op_bset_8_s_ai(m68ki_cpu_core *m68k) +{ + UINT32 mask = 1 << (OPER_I_8(m68k) & 7); + UINT32 ea = EA_AY_AI_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src | mask); +} + + +static void m68k_op_bset_8_s_pi(m68ki_cpu_core *m68k) +{ + UINT32 mask = 1 << (OPER_I_8(m68k) & 7); + UINT32 ea = EA_AY_PI_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src | mask); +} + + +static void m68k_op_bset_8_s_pi7(m68ki_cpu_core *m68k) +{ + UINT32 mask = 1 << (OPER_I_8(m68k) & 7); + UINT32 ea = EA_A7_PI_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src | mask); +} + + +static void m68k_op_bset_8_s_pd(m68ki_cpu_core *m68k) +{ + UINT32 mask = 1 << (OPER_I_8(m68k) & 7); + UINT32 ea = EA_AY_PD_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src | mask); +} + + +static void m68k_op_bset_8_s_pd7(m68ki_cpu_core *m68k) +{ + UINT32 mask = 1 << (OPER_I_8(m68k) & 7); + UINT32 ea = EA_A7_PD_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src | mask); +} + + +static void m68k_op_bset_8_s_di(m68ki_cpu_core *m68k) +{ + UINT32 mask = 1 << (OPER_I_8(m68k) & 7); + UINT32 ea = EA_AY_DI_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src | mask); +} + + +static void m68k_op_bset_8_s_ix(m68ki_cpu_core *m68k) +{ + UINT32 mask = 1 << (OPER_I_8(m68k) & 7); + UINT32 ea = EA_AY_IX_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src | mask); +} + + +static void m68k_op_bset_8_s_aw(m68ki_cpu_core *m68k) +{ + UINT32 mask = 1 << (OPER_I_8(m68k) & 7); + UINT32 ea = EA_AW_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src | mask); +} + + +static void m68k_op_bset_8_s_al(m68ki_cpu_core *m68k) +{ + UINT32 mask = 1 << (OPER_I_8(m68k) & 7); + UINT32 ea = EA_AL_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + + m68k->not_z_flag = src & mask; + m68ki_write_8(m68k, ea, src | mask); +} + + +static void m68k_op_bsr_8(m68ki_cpu_core *m68k) +{ + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_push_32(m68k, REG_PC); + m68ki_branch_8(m68k, MASK_OUT_ABOVE_8(m68k->ir)); +} + + +static void m68k_op_bsr_16(m68ki_cpu_core *m68k) +{ + UINT32 offset = OPER_I_16(m68k); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_push_32(m68k, REG_PC); + REG_PC -= 2; + m68ki_branch_16(m68k, offset); +} + + +static void m68k_op_bsr_32(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 offset = OPER_I_32(m68k); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_push_32(m68k, REG_PC); + REG_PC -= 4; + m68ki_branch_32(m68k, offset); + return; + } + else + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_push_32(m68k, REG_PC); + m68ki_branch_8(m68k, MASK_OUT_ABOVE_8(m68k->ir)); + } +} + + +static void m68k_op_btst_32_r_d(m68ki_cpu_core *m68k) +{ + m68k->not_z_flag = DY & (1 << (DX & 0x1f)); +} + + +static void m68k_op_btst_8_r_ai(m68ki_cpu_core *m68k) +{ + m68k->not_z_flag = OPER_AY_AI_8(m68k) & (1 << (DX & 7)); +} + + +static void m68k_op_btst_8_r_pi(m68ki_cpu_core *m68k) +{ + m68k->not_z_flag = OPER_AY_PI_8(m68k) & (1 << (DX & 7)); +} + + +static void m68k_op_btst_8_r_pi7(m68ki_cpu_core *m68k) +{ + m68k->not_z_flag = OPER_A7_PI_8(m68k) & (1 << (DX & 7)); +} + + +static void m68k_op_btst_8_r_pd(m68ki_cpu_core *m68k) +{ + m68k->not_z_flag = OPER_AY_PD_8(m68k) & (1 << (DX & 7)); +} + + +static void m68k_op_btst_8_r_pd7(m68ki_cpu_core *m68k) +{ + m68k->not_z_flag = OPER_A7_PD_8(m68k) & (1 << (DX & 7)); +} + + +static void m68k_op_btst_8_r_di(m68ki_cpu_core *m68k) +{ + m68k->not_z_flag = OPER_AY_DI_8(m68k) & (1 << (DX & 7)); +} + + +static void m68k_op_btst_8_r_ix(m68ki_cpu_core *m68k) +{ + m68k->not_z_flag = OPER_AY_IX_8(m68k) & (1 << (DX & 7)); +} + + +static void m68k_op_btst_8_r_aw(m68ki_cpu_core *m68k) +{ + m68k->not_z_flag = OPER_AW_8(m68k) & (1 << (DX & 7)); +} + + +static void m68k_op_btst_8_r_al(m68ki_cpu_core *m68k) +{ + m68k->not_z_flag = OPER_AL_8(m68k) & (1 << (DX & 7)); +} + + +static void m68k_op_btst_8_r_pcdi(m68ki_cpu_core *m68k) +{ + m68k->not_z_flag = OPER_PCDI_8(m68k) & (1 << (DX & 7)); +} + + +static void m68k_op_btst_8_r_pcix(m68ki_cpu_core *m68k) +{ + m68k->not_z_flag = OPER_PCIX_8(m68k) & (1 << (DX & 7)); +} + + +static void m68k_op_btst_8_r_i(m68ki_cpu_core *m68k) +{ + m68k->not_z_flag = OPER_I_8(m68k) & (1 << (DX & 7)); +} + + +static void m68k_op_btst_32_s_d(m68ki_cpu_core *m68k) +{ + m68k->not_z_flag = DY & (1 << (OPER_I_8(m68k) & 0x1f)); +} + + +static void m68k_op_btst_8_s_ai(m68ki_cpu_core *m68k) +{ + UINT32 bit = OPER_I_8(m68k) & 7; + + m68k->not_z_flag = OPER_AY_AI_8(m68k) & (1 << bit); +} + + +static void m68k_op_btst_8_s_pi(m68ki_cpu_core *m68k) +{ + UINT32 bit = OPER_I_8(m68k) & 7; + + m68k->not_z_flag = OPER_AY_PI_8(m68k) & (1 << bit); +} + + +static void m68k_op_btst_8_s_pi7(m68ki_cpu_core *m68k) +{ + UINT32 bit = OPER_I_8(m68k) & 7; + + m68k->not_z_flag = OPER_A7_PI_8(m68k) & (1 << bit); +} + + +static void m68k_op_btst_8_s_pd(m68ki_cpu_core *m68k) +{ + UINT32 bit = OPER_I_8(m68k) & 7; + + m68k->not_z_flag = OPER_AY_PD_8(m68k) & (1 << bit); +} + + +static void m68k_op_btst_8_s_pd7(m68ki_cpu_core *m68k) +{ + UINT32 bit = OPER_I_8(m68k) & 7; + + m68k->not_z_flag = OPER_A7_PD_8(m68k) & (1 << bit); +} + + +static void m68k_op_btst_8_s_di(m68ki_cpu_core *m68k) +{ + UINT32 bit = OPER_I_8(m68k) & 7; + + m68k->not_z_flag = OPER_AY_DI_8(m68k) & (1 << bit); +} + + +static void m68k_op_btst_8_s_ix(m68ki_cpu_core *m68k) +{ + UINT32 bit = OPER_I_8(m68k) & 7; + + m68k->not_z_flag = OPER_AY_IX_8(m68k) & (1 << bit); +} + + +static void m68k_op_btst_8_s_aw(m68ki_cpu_core *m68k) +{ + UINT32 bit = OPER_I_8(m68k) & 7; + + m68k->not_z_flag = OPER_AW_8(m68k) & (1 << bit); +} + + +static void m68k_op_btst_8_s_al(m68ki_cpu_core *m68k) +{ + UINT32 bit = OPER_I_8(m68k) & 7; + + m68k->not_z_flag = OPER_AL_8(m68k) & (1 << bit); +} + + +static void m68k_op_btst_8_s_pcdi(m68ki_cpu_core *m68k) +{ + UINT32 bit = OPER_I_8(m68k) & 7; + + m68k->not_z_flag = OPER_PCDI_8(m68k) & (1 << bit); +} + + +static void m68k_op_btst_8_s_pcix(m68ki_cpu_core *m68k) +{ + UINT32 bit = OPER_I_8(m68k) & 7; + + m68k->not_z_flag = OPER_PCIX_8(m68k) & (1 << bit); +} + + +static void m68k_op_callm_32_ai(m68ki_cpu_core *m68k) +{ + /* note: watch out for pcrelative modes */ + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + { + UINT32 ea = EA_AY_AI_32(m68k); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + REG_PC += 2; +(void)ea; /* just to avoid an 'unused variable' warning */ + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_callm_32_di(m68ki_cpu_core *m68k) +{ + /* note: watch out for pcrelative modes */ + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + { + UINT32 ea = EA_AY_DI_32(m68k); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + REG_PC += 2; +(void)ea; /* just to avoid an 'unused variable' warning */ + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_callm_32_ix(m68ki_cpu_core *m68k) +{ + /* note: watch out for pcrelative modes */ + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + { + UINT32 ea = EA_AY_IX_32(m68k); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + REG_PC += 2; +(void)ea; /* just to avoid an 'unused variable' warning */ + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_callm_32_aw(m68ki_cpu_core *m68k) +{ + /* note: watch out for pcrelative modes */ + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + { + UINT32 ea = EA_AW_32(m68k); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + REG_PC += 2; +(void)ea; /* just to avoid an 'unused variable' warning */ + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_callm_32_al(m68ki_cpu_core *m68k) +{ + /* note: watch out for pcrelative modes */ + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + { + UINT32 ea = EA_AL_32(m68k); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + REG_PC += 2; +(void)ea; /* just to avoid an 'unused variable' warning */ + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_callm_32_pcdi(m68ki_cpu_core *m68k) +{ + /* note: watch out for pcrelative modes */ + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + { + UINT32 ea = EA_PCDI_32(m68k); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + REG_PC += 2; +(void)ea; /* just to avoid an 'unused variable' warning */ + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_callm_32_pcix(m68ki_cpu_core *m68k) +{ + /* note: watch out for pcrelative modes */ + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + { + UINT32 ea = EA_PCIX_32(m68k); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + REG_PC += 2; +(void)ea; /* just to avoid an 'unused variable' warning */ + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_cas_8_ai(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 ea = EA_AY_AI_8(m68k); + UINT32 dest = m68ki_read_8(m68k, ea); + UINT32* compare = ®_D[word2 & 7]; + UINT32 res = dest - MASK_OUT_ABOVE_8(*compare); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->v_flag = VFLAG_SUB_8(*compare, dest, res); + m68k->c_flag = CFLAG_8(res); + + if(COND_NE(m68k)) + *compare = MASK_OUT_BELOW_8(*compare) | dest; + else + { + m68k->remaining_cycles -= 3; + m68ki_write_8(m68k, ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7])); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_cas_8_pi(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 ea = EA_AY_PI_8(m68k); + UINT32 dest = m68ki_read_8(m68k, ea); + UINT32* compare = ®_D[word2 & 7]; + UINT32 res = dest - MASK_OUT_ABOVE_8(*compare); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->v_flag = VFLAG_SUB_8(*compare, dest, res); + m68k->c_flag = CFLAG_8(res); + + if(COND_NE(m68k)) + *compare = MASK_OUT_BELOW_8(*compare) | dest; + else + { + m68k->remaining_cycles -= 3; + m68ki_write_8(m68k, ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7])); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_cas_8_pi7(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 ea = EA_A7_PI_8(m68k); + UINT32 dest = m68ki_read_8(m68k, ea); + UINT32* compare = ®_D[word2 & 7]; + UINT32 res = dest - MASK_OUT_ABOVE_8(*compare); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->v_flag = VFLAG_SUB_8(*compare, dest, res); + m68k->c_flag = CFLAG_8(res); + + if(COND_NE(m68k)) + *compare = MASK_OUT_BELOW_8(*compare) | dest; + else + { + m68k->remaining_cycles -= 3; + m68ki_write_8(m68k, ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7])); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_cas_8_pd(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 ea = EA_AY_PD_8(m68k); + UINT32 dest = m68ki_read_8(m68k, ea); + UINT32* compare = ®_D[word2 & 7]; + UINT32 res = dest - MASK_OUT_ABOVE_8(*compare); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->v_flag = VFLAG_SUB_8(*compare, dest, res); + m68k->c_flag = CFLAG_8(res); + + if(COND_NE(m68k)) + *compare = MASK_OUT_BELOW_8(*compare) | dest; + else + { + m68k->remaining_cycles -= 3; + m68ki_write_8(m68k, ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7])); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_cas_8_pd7(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 ea = EA_A7_PD_8(m68k); + UINT32 dest = m68ki_read_8(m68k, ea); + UINT32* compare = ®_D[word2 & 7]; + UINT32 res = dest - MASK_OUT_ABOVE_8(*compare); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->v_flag = VFLAG_SUB_8(*compare, dest, res); + m68k->c_flag = CFLAG_8(res); + + if(COND_NE(m68k)) + *compare = MASK_OUT_BELOW_8(*compare) | dest; + else + { + m68k->remaining_cycles -= 3; + m68ki_write_8(m68k, ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7])); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_cas_8_di(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 ea = EA_AY_DI_8(m68k); + UINT32 dest = m68ki_read_8(m68k, ea); + UINT32* compare = ®_D[word2 & 7]; + UINT32 res = dest - MASK_OUT_ABOVE_8(*compare); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->v_flag = VFLAG_SUB_8(*compare, dest, res); + m68k->c_flag = CFLAG_8(res); + + if(COND_NE(m68k)) + *compare = MASK_OUT_BELOW_8(*compare) | dest; + else + { + m68k->remaining_cycles -= 3; + m68ki_write_8(m68k, ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7])); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_cas_8_ix(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 ea = EA_AY_IX_8(m68k); + UINT32 dest = m68ki_read_8(m68k, ea); + UINT32* compare = ®_D[word2 & 7]; + UINT32 res = dest - MASK_OUT_ABOVE_8(*compare); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->v_flag = VFLAG_SUB_8(*compare, dest, res); + m68k->c_flag = CFLAG_8(res); + + if(COND_NE(m68k)) + *compare = MASK_OUT_BELOW_8(*compare) | dest; + else + { + m68k->remaining_cycles -= 3; + m68ki_write_8(m68k, ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7])); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_cas_8_aw(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 ea = EA_AW_8(m68k); + UINT32 dest = m68ki_read_8(m68k, ea); + UINT32* compare = ®_D[word2 & 7]; + UINT32 res = dest - MASK_OUT_ABOVE_8(*compare); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->v_flag = VFLAG_SUB_8(*compare, dest, res); + m68k->c_flag = CFLAG_8(res); + + if(COND_NE(m68k)) + *compare = MASK_OUT_BELOW_8(*compare) | dest; + else + { + m68k->remaining_cycles -= 3; + m68ki_write_8(m68k, ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7])); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_cas_8_al(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 ea = EA_AL_8(m68k); + UINT32 dest = m68ki_read_8(m68k, ea); + UINT32* compare = ®_D[word2 & 7]; + UINT32 res = dest - MASK_OUT_ABOVE_8(*compare); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->v_flag = VFLAG_SUB_8(*compare, dest, res); + m68k->c_flag = CFLAG_8(res); + + if(COND_NE(m68k)) + *compare = MASK_OUT_BELOW_8(*compare) | dest; + else + { + m68k->remaining_cycles -= 3; + m68ki_write_8(m68k, ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7])); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_cas_16_ai(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 ea = EA_AY_AI_16(m68k); + UINT32 dest = m68ki_read_16(m68k, ea); + UINT32* compare = ®_D[word2 & 7]; + UINT32 res = dest - MASK_OUT_ABOVE_16(*compare); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->v_flag = VFLAG_SUB_16(*compare, dest, res); + m68k->c_flag = CFLAG_16(res); + + if(COND_NE(m68k)) + *compare = MASK_OUT_BELOW_16(*compare) | dest; + else + { + m68k->remaining_cycles -= 3; + m68ki_write_16(m68k, ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7])); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_cas_16_pi(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 ea = EA_AY_PI_16(m68k); + UINT32 dest = m68ki_read_16(m68k, ea); + UINT32* compare = ®_D[word2 & 7]; + UINT32 res = dest - MASK_OUT_ABOVE_16(*compare); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->v_flag = VFLAG_SUB_16(*compare, dest, res); + m68k->c_flag = CFLAG_16(res); + + if(COND_NE(m68k)) + *compare = MASK_OUT_BELOW_16(*compare) | dest; + else + { + m68k->remaining_cycles -= 3; + m68ki_write_16(m68k, ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7])); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_cas_16_pd(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 ea = EA_AY_PD_16(m68k); + UINT32 dest = m68ki_read_16(m68k, ea); + UINT32* compare = ®_D[word2 & 7]; + UINT32 res = dest - MASK_OUT_ABOVE_16(*compare); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->v_flag = VFLAG_SUB_16(*compare, dest, res); + m68k->c_flag = CFLAG_16(res); + + if(COND_NE(m68k)) + *compare = MASK_OUT_BELOW_16(*compare) | dest; + else + { + m68k->remaining_cycles -= 3; + m68ki_write_16(m68k, ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7])); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_cas_16_di(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 ea = EA_AY_DI_16(m68k); + UINT32 dest = m68ki_read_16(m68k, ea); + UINT32* compare = ®_D[word2 & 7]; + UINT32 res = dest - MASK_OUT_ABOVE_16(*compare); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->v_flag = VFLAG_SUB_16(*compare, dest, res); + m68k->c_flag = CFLAG_16(res); + + if(COND_NE(m68k)) + *compare = MASK_OUT_BELOW_16(*compare) | dest; + else + { + m68k->remaining_cycles -= 3; + m68ki_write_16(m68k, ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7])); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_cas_16_ix(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 ea = EA_AY_IX_16(m68k); + UINT32 dest = m68ki_read_16(m68k, ea); + UINT32* compare = ®_D[word2 & 7]; + UINT32 res = dest - MASK_OUT_ABOVE_16(*compare); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->v_flag = VFLAG_SUB_16(*compare, dest, res); + m68k->c_flag = CFLAG_16(res); + + if(COND_NE(m68k)) + *compare = MASK_OUT_BELOW_16(*compare) | dest; + else + { + m68k->remaining_cycles -= 3; + m68ki_write_16(m68k, ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7])); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_cas_16_aw(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 ea = EA_AW_16(m68k); + UINT32 dest = m68ki_read_16(m68k, ea); + UINT32* compare = ®_D[word2 & 7]; + UINT32 res = dest - MASK_OUT_ABOVE_16(*compare); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->v_flag = VFLAG_SUB_16(*compare, dest, res); + m68k->c_flag = CFLAG_16(res); + + if(COND_NE(m68k)) + *compare = MASK_OUT_BELOW_16(*compare) | dest; + else + { + m68k->remaining_cycles -= 3; + m68ki_write_16(m68k, ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7])); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_cas_16_al(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 ea = EA_AL_16(m68k); + UINT32 dest = m68ki_read_16(m68k, ea); + UINT32* compare = ®_D[word2 & 7]; + UINT32 res = dest - MASK_OUT_ABOVE_16(*compare); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->v_flag = VFLAG_SUB_16(*compare, dest, res); + m68k->c_flag = CFLAG_16(res); + + if(COND_NE(m68k)) + *compare = MASK_OUT_BELOW_16(*compare) | dest; + else + { + m68k->remaining_cycles -= 3; + m68ki_write_16(m68k, ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7])); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_cas_32_ai(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 ea = EA_AY_AI_32(m68k); + UINT32 dest = m68ki_read_32(m68k, ea); + UINT32* compare = ®_D[word2 & 7]; + UINT32 res = dest - *compare; + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(*compare, dest, res); + m68k->c_flag = CFLAG_SUB_32(*compare, dest, res); + + if(COND_NE(m68k)) + *compare = dest; + else + { + m68k->remaining_cycles -= 3; + m68ki_write_32(m68k, ea, REG_D[(word2 >> 6) & 7]); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_cas_32_pi(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 ea = EA_AY_PI_32(m68k); + UINT32 dest = m68ki_read_32(m68k, ea); + UINT32* compare = ®_D[word2 & 7]; + UINT32 res = dest - *compare; + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(*compare, dest, res); + m68k->c_flag = CFLAG_SUB_32(*compare, dest, res); + + if(COND_NE(m68k)) + *compare = dest; + else + { + m68k->remaining_cycles -= 3; + m68ki_write_32(m68k, ea, REG_D[(word2 >> 6) & 7]); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_cas_32_pd(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 ea = EA_AY_PD_32(m68k); + UINT32 dest = m68ki_read_32(m68k, ea); + UINT32* compare = ®_D[word2 & 7]; + UINT32 res = dest - *compare; + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(*compare, dest, res); + m68k->c_flag = CFLAG_SUB_32(*compare, dest, res); + + if(COND_NE(m68k)) + *compare = dest; + else + { + m68k->remaining_cycles -= 3; + m68ki_write_32(m68k, ea, REG_D[(word2 >> 6) & 7]); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_cas_32_di(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 ea = EA_AY_DI_32(m68k); + UINT32 dest = m68ki_read_32(m68k, ea); + UINT32* compare = ®_D[word2 & 7]; + UINT32 res = dest - *compare; + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(*compare, dest, res); + m68k->c_flag = CFLAG_SUB_32(*compare, dest, res); + + if(COND_NE(m68k)) + *compare = dest; + else + { + m68k->remaining_cycles -= 3; + m68ki_write_32(m68k, ea, REG_D[(word2 >> 6) & 7]); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_cas_32_ix(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 ea = EA_AY_IX_32(m68k); + UINT32 dest = m68ki_read_32(m68k, ea); + UINT32* compare = ®_D[word2 & 7]; + UINT32 res = dest - *compare; + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(*compare, dest, res); + m68k->c_flag = CFLAG_SUB_32(*compare, dest, res); + + if(COND_NE(m68k)) + *compare = dest; + else + { + m68k->remaining_cycles -= 3; + m68ki_write_32(m68k, ea, REG_D[(word2 >> 6) & 7]); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_cas_32_aw(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 ea = EA_AW_32(m68k); + UINT32 dest = m68ki_read_32(m68k, ea); + UINT32* compare = ®_D[word2 & 7]; + UINT32 res = dest - *compare; + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(*compare, dest, res); + m68k->c_flag = CFLAG_SUB_32(*compare, dest, res); + + if(COND_NE(m68k)) + *compare = dest; + else + { + m68k->remaining_cycles -= 3; + m68ki_write_32(m68k, ea, REG_D[(word2 >> 6) & 7]); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_cas_32_al(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 ea = EA_AL_32(m68k); + UINT32 dest = m68ki_read_32(m68k, ea); + UINT32* compare = ®_D[word2 & 7]; + UINT32 res = dest - *compare; + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(*compare, dest, res); + m68k->c_flag = CFLAG_SUB_32(*compare, dest, res); + + if(COND_NE(m68k)) + *compare = dest; + else + { + m68k->remaining_cycles -= 3; + m68ki_write_32(m68k, ea, REG_D[(word2 >> 6) & 7]); + } + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_cas2_16(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_32(m68k); + UINT32* compare1 = ®_D[(word2 >> 16) & 7]; + UINT32 ea1 = REG_DA[(word2 >> 28) & 15]; + UINT32 dest1 = m68ki_read_16(m68k, ea1); + UINT32 res1 = dest1 - MASK_OUT_ABOVE_16(*compare1); + UINT32* compare2 = ®_D[word2 & 7]; + UINT32 ea2 = REG_DA[(word2 >> 12) & 15]; + UINT32 dest2 = m68ki_read_16(m68k, ea2); + UINT32 res2; + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68k->n_flag = NFLAG_16(res1); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res1); + m68k->v_flag = VFLAG_SUB_16(*compare1, dest1, res1); + m68k->c_flag = CFLAG_16(res1); + + if(COND_EQ(m68k)) + { + res2 = dest2 - MASK_OUT_ABOVE_16(*compare2); + + m68k->n_flag = NFLAG_16(res2); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res2); + m68k->v_flag = VFLAG_SUB_16(*compare2, dest2, res2); + m68k->c_flag = CFLAG_16(res2); + + if(COND_EQ(m68k)) + { + m68k->remaining_cycles -= 3; + m68ki_write_16(m68k, ea1, REG_D[(word2 >> 22) & 7]); + m68ki_write_16(m68k, ea2, REG_D[(word2 >> 6) & 7]); + return; + } + } + *compare1 = BIT_1F(word2) ? MAKE_INT_16(dest1) : MASK_OUT_BELOW_16(*compare1) | dest1; + *compare2 = BIT_F(word2) ? MAKE_INT_16(dest2) : MASK_OUT_BELOW_16(*compare2) | dest2; + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_cas2_32(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_32(m68k); + UINT32* compare1 = ®_D[(word2 >> 16) & 7]; + UINT32 ea1 = REG_DA[(word2 >> 28) & 15]; + UINT32 dest1 = m68ki_read_32(m68k, ea1); + UINT32 res1 = dest1 - *compare1; + UINT32* compare2 = ®_D[word2 & 7]; + UINT32 ea2 = REG_DA[(word2 >> 12) & 15]; + UINT32 dest2 = m68ki_read_32(m68k, ea2); + UINT32 res2; + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68k->n_flag = NFLAG_32(res1); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res1); + m68k->v_flag = VFLAG_SUB_32(*compare1, dest1, res1); + m68k->c_flag = CFLAG_SUB_32(*compare1, dest1, res1); + + if(COND_EQ(m68k)) + { + res2 = dest2 - *compare2; + + m68k->n_flag = NFLAG_32(res2); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res2); + m68k->v_flag = VFLAG_SUB_32(*compare2, dest2, res2); + m68k->c_flag = CFLAG_SUB_32(*compare2, dest2, res2); + + if(COND_EQ(m68k)) + { + m68k->remaining_cycles -= 3; + m68ki_write_32(m68k, ea1, REG_D[(word2 >> 22) & 7]); + m68ki_write_32(m68k, ea2, REG_D[(word2 >> 6) & 7]); + return; + } + } + *compare1 = dest1; + *compare2 = dest2; + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_chk_16_d(m68ki_cpu_core *m68k) +{ + INT32 src = MAKE_INT_16(DX); + INT32 bound = MAKE_INT_16(DY); + + m68k->not_z_flag = ZFLAG_16(src); /* Undocumented */ + m68k->v_flag = VFLAG_CLEAR; /* Undocumented */ + m68k->c_flag = CFLAG_CLEAR; /* Undocumented */ + + if(src >= 0 && src <= bound) + { + return; + } + m68k->n_flag = (src < 0)<<7; + m68ki_exception_trap(m68k, EXCEPTION_CHK); +} + + +static void m68k_op_chk_16_ai(m68ki_cpu_core *m68k) +{ + INT32 src = MAKE_INT_16(DX); + INT32 bound = MAKE_INT_16(OPER_AY_AI_16(m68k)); + + m68k->not_z_flag = ZFLAG_16(src); /* Undocumented */ + m68k->v_flag = VFLAG_CLEAR; /* Undocumented */ + m68k->c_flag = CFLAG_CLEAR; /* Undocumented */ + + if(src >= 0 && src <= bound) + { + return; + } + m68k->n_flag = (src < 0)<<7; + m68ki_exception_trap(m68k, EXCEPTION_CHK); +} + + +static void m68k_op_chk_16_pi(m68ki_cpu_core *m68k) +{ + INT32 src = MAKE_INT_16(DX); + INT32 bound = MAKE_INT_16(OPER_AY_PI_16(m68k)); + + m68k->not_z_flag = ZFLAG_16(src); /* Undocumented */ + m68k->v_flag = VFLAG_CLEAR; /* Undocumented */ + m68k->c_flag = CFLAG_CLEAR; /* Undocumented */ + + if(src >= 0 && src <= bound) + { + return; + } + m68k->n_flag = (src < 0)<<7; + m68ki_exception_trap(m68k, EXCEPTION_CHK); +} + + +static void m68k_op_chk_16_pd(m68ki_cpu_core *m68k) +{ + INT32 src = MAKE_INT_16(DX); + INT32 bound = MAKE_INT_16(OPER_AY_PD_16(m68k)); + + m68k->not_z_flag = ZFLAG_16(src); /* Undocumented */ + m68k->v_flag = VFLAG_CLEAR; /* Undocumented */ + m68k->c_flag = CFLAG_CLEAR; /* Undocumented */ + + if(src >= 0 && src <= bound) + { + return; + } + m68k->n_flag = (src < 0)<<7; + m68ki_exception_trap(m68k, EXCEPTION_CHK); +} + + +static void m68k_op_chk_16_di(m68ki_cpu_core *m68k) +{ + INT32 src = MAKE_INT_16(DX); + INT32 bound = MAKE_INT_16(OPER_AY_DI_16(m68k)); + + m68k->not_z_flag = ZFLAG_16(src); /* Undocumented */ + m68k->v_flag = VFLAG_CLEAR; /* Undocumented */ + m68k->c_flag = CFLAG_CLEAR; /* Undocumented */ + + if(src >= 0 && src <= bound) + { + return; + } + m68k->n_flag = (src < 0)<<7; + m68ki_exception_trap(m68k, EXCEPTION_CHK); +} + + +static void m68k_op_chk_16_ix(m68ki_cpu_core *m68k) +{ + INT32 src = MAKE_INT_16(DX); + INT32 bound = MAKE_INT_16(OPER_AY_IX_16(m68k)); + + m68k->not_z_flag = ZFLAG_16(src); /* Undocumented */ + m68k->v_flag = VFLAG_CLEAR; /* Undocumented */ + m68k->c_flag = CFLAG_CLEAR; /* Undocumented */ + + if(src >= 0 && src <= bound) + { + return; + } + m68k->n_flag = (src < 0)<<7; + m68ki_exception_trap(m68k, EXCEPTION_CHK); +} + + +static void m68k_op_chk_16_aw(m68ki_cpu_core *m68k) +{ + INT32 src = MAKE_INT_16(DX); + INT32 bound = MAKE_INT_16(OPER_AW_16(m68k)); + + m68k->not_z_flag = ZFLAG_16(src); /* Undocumented */ + m68k->v_flag = VFLAG_CLEAR; /* Undocumented */ + m68k->c_flag = CFLAG_CLEAR; /* Undocumented */ + + if(src >= 0 && src <= bound) + { + return; + } + m68k->n_flag = (src < 0)<<7; + m68ki_exception_trap(m68k, EXCEPTION_CHK); +} + + +static void m68k_op_chk_16_al(m68ki_cpu_core *m68k) +{ + INT32 src = MAKE_INT_16(DX); + INT32 bound = MAKE_INT_16(OPER_AL_16(m68k)); + + m68k->not_z_flag = ZFLAG_16(src); /* Undocumented */ + m68k->v_flag = VFLAG_CLEAR; /* Undocumented */ + m68k->c_flag = CFLAG_CLEAR; /* Undocumented */ + + if(src >= 0 && src <= bound) + { + return; + } + m68k->n_flag = (src < 0)<<7; + m68ki_exception_trap(m68k, EXCEPTION_CHK); +} + + +static void m68k_op_chk_16_pcdi(m68ki_cpu_core *m68k) +{ + INT32 src = MAKE_INT_16(DX); + INT32 bound = MAKE_INT_16(OPER_PCDI_16(m68k)); + + m68k->not_z_flag = ZFLAG_16(src); /* Undocumented */ + m68k->v_flag = VFLAG_CLEAR; /* Undocumented */ + m68k->c_flag = CFLAG_CLEAR; /* Undocumented */ + + if(src >= 0 && src <= bound) + { + return; + } + m68k->n_flag = (src < 0)<<7; + m68ki_exception_trap(m68k, EXCEPTION_CHK); +} + + +static void m68k_op_chk_16_pcix(m68ki_cpu_core *m68k) +{ + INT32 src = MAKE_INT_16(DX); + INT32 bound = MAKE_INT_16(OPER_PCIX_16(m68k)); + + m68k->not_z_flag = ZFLAG_16(src); /* Undocumented */ + m68k->v_flag = VFLAG_CLEAR; /* Undocumented */ + m68k->c_flag = CFLAG_CLEAR; /* Undocumented */ + + if(src >= 0 && src <= bound) + { + return; + } + m68k->n_flag = (src < 0)<<7; + m68ki_exception_trap(m68k, EXCEPTION_CHK); +} + + +static void m68k_op_chk_16_i(m68ki_cpu_core *m68k) +{ + INT32 src = MAKE_INT_16(DX); + INT32 bound = MAKE_INT_16(OPER_I_16(m68k)); + + m68k->not_z_flag = ZFLAG_16(src); /* Undocumented */ + m68k->v_flag = VFLAG_CLEAR; /* Undocumented */ + m68k->c_flag = CFLAG_CLEAR; /* Undocumented */ + + if(src >= 0 && src <= bound) + { + return; + } + m68k->n_flag = (src < 0)<<7; + m68ki_exception_trap(m68k, EXCEPTION_CHK); +} + + +static void m68k_op_chk_32_d(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + INT32 src = MAKE_INT_32(DX); + INT32 bound = MAKE_INT_32(DY); + + m68k->not_z_flag = ZFLAG_32(src); /* Undocumented */ + m68k->v_flag = VFLAG_CLEAR; /* Undocumented */ + m68k->c_flag = CFLAG_CLEAR; /* Undocumented */ + + if(src >= 0 && src <= bound) + { + return; + } + m68k->n_flag = (src < 0)<<7; + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_chk_32_ai(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + INT32 src = MAKE_INT_32(DX); + INT32 bound = MAKE_INT_32(OPER_AY_AI_32(m68k)); + + m68k->not_z_flag = ZFLAG_32(src); /* Undocumented */ + m68k->v_flag = VFLAG_CLEAR; /* Undocumented */ + m68k->c_flag = CFLAG_CLEAR; /* Undocumented */ + + if(src >= 0 && src <= bound) + { + return; + } + m68k->n_flag = (src < 0)<<7; + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_chk_32_pi(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + INT32 src = MAKE_INT_32(DX); + INT32 bound = MAKE_INT_32(OPER_AY_PI_32(m68k)); + + m68k->not_z_flag = ZFLAG_32(src); /* Undocumented */ + m68k->v_flag = VFLAG_CLEAR; /* Undocumented */ + m68k->c_flag = CFLAG_CLEAR; /* Undocumented */ + + if(src >= 0 && src <= bound) + { + return; + } + m68k->n_flag = (src < 0)<<7; + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_chk_32_pd(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + INT32 src = MAKE_INT_32(DX); + INT32 bound = MAKE_INT_32(OPER_AY_PD_32(m68k)); + + m68k->not_z_flag = ZFLAG_32(src); /* Undocumented */ + m68k->v_flag = VFLAG_CLEAR; /* Undocumented */ + m68k->c_flag = CFLAG_CLEAR; /* Undocumented */ + + if(src >= 0 && src <= bound) + { + return; + } + m68k->n_flag = (src < 0)<<7; + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_chk_32_di(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + INT32 src = MAKE_INT_32(DX); + INT32 bound = MAKE_INT_32(OPER_AY_DI_32(m68k)); + + m68k->not_z_flag = ZFLAG_32(src); /* Undocumented */ + m68k->v_flag = VFLAG_CLEAR; /* Undocumented */ + m68k->c_flag = CFLAG_CLEAR; /* Undocumented */ + + if(src >= 0 && src <= bound) + { + return; + } + m68k->n_flag = (src < 0)<<7; + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_chk_32_ix(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + INT32 src = MAKE_INT_32(DX); + INT32 bound = MAKE_INT_32(OPER_AY_IX_32(m68k)); + + m68k->not_z_flag = ZFLAG_32(src); /* Undocumented */ + m68k->v_flag = VFLAG_CLEAR; /* Undocumented */ + m68k->c_flag = CFLAG_CLEAR; /* Undocumented */ + + if(src >= 0 && src <= bound) + { + return; + } + m68k->n_flag = (src < 0)<<7; + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_chk_32_aw(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + INT32 src = MAKE_INT_32(DX); + INT32 bound = MAKE_INT_32(OPER_AW_32(m68k)); + + m68k->not_z_flag = ZFLAG_32(src); /* Undocumented */ + m68k->v_flag = VFLAG_CLEAR; /* Undocumented */ + m68k->c_flag = CFLAG_CLEAR; /* Undocumented */ + + if(src >= 0 && src <= bound) + { + return; + } + m68k->n_flag = (src < 0)<<7; + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_chk_32_al(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + INT32 src = MAKE_INT_32(DX); + INT32 bound = MAKE_INT_32(OPER_AL_32(m68k)); + + m68k->not_z_flag = ZFLAG_32(src); /* Undocumented */ + m68k->v_flag = VFLAG_CLEAR; /* Undocumented */ + m68k->c_flag = CFLAG_CLEAR; /* Undocumented */ + + if(src >= 0 && src <= bound) + { + return; + } + m68k->n_flag = (src < 0)<<7; + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_chk_32_pcdi(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + INT32 src = MAKE_INT_32(DX); + INT32 bound = MAKE_INT_32(OPER_PCDI_32(m68k)); + + m68k->not_z_flag = ZFLAG_32(src); /* Undocumented */ + m68k->v_flag = VFLAG_CLEAR; /* Undocumented */ + m68k->c_flag = CFLAG_CLEAR; /* Undocumented */ + + if(src >= 0 && src <= bound) + { + return; + } + m68k->n_flag = (src < 0)<<7; + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_chk_32_pcix(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + INT32 src = MAKE_INT_32(DX); + INT32 bound = MAKE_INT_32(OPER_PCIX_32(m68k)); + + m68k->not_z_flag = ZFLAG_32(src); /* Undocumented */ + m68k->v_flag = VFLAG_CLEAR; /* Undocumented */ + m68k->c_flag = CFLAG_CLEAR; /* Undocumented */ + + if(src >= 0 && src <= bound) + { + return; + } + m68k->n_flag = (src < 0)<<7; + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_chk_32_i(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + INT32 src = MAKE_INT_32(DX); + INT32 bound = MAKE_INT_32(OPER_I_32(m68k)); + + m68k->not_z_flag = ZFLAG_32(src); /* Undocumented */ + m68k->v_flag = VFLAG_CLEAR; /* Undocumented */ + m68k->c_flag = CFLAG_CLEAR; /* Undocumented */ + + if(src >= 0 && src <= bound) + { + return; + } + m68k->n_flag = (src < 0)<<7; + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_chk2cmp2_8_pcdi(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 compare = REG_DA[(word2 >> 12) & 15]&0xff; + UINT32 ea = EA_PCDI_8(m68k); + UINT32 lower_bound = m68ki_read_pcrel_8(m68k, ea); + UINT32 upper_bound = m68ki_read_pcrel_8(m68k, ea + 1); + + if(!BIT_F(word2)) + m68k->c_flag = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound); + else + m68k->c_flag = compare - lower_bound; + m68k->not_z_flag = !((upper_bound==compare) | (lower_bound==compare)); + if(COND_CS(m68k)) + { + if(BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + + m68k->c_flag = upper_bound - compare; + if(COND_CS(m68k) && BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_chk2cmp2_8_pcix(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 compare = REG_DA[(word2 >> 12) & 15]&0xff; + UINT32 ea = EA_PCIX_8(m68k); + UINT32 lower_bound = m68ki_read_pcrel_8(m68k, ea); + UINT32 upper_bound = m68ki_read_pcrel_8(m68k, ea + 1); + + if(!BIT_F(word2)) + m68k->c_flag = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound); + else + m68k->c_flag = compare - lower_bound; + m68k->not_z_flag = !((upper_bound==compare) | (lower_bound==compare)); + if(COND_CS(m68k)) + { + if(BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + + m68k->c_flag = upper_bound - compare; + if(COND_CS(m68k) && BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_chk2cmp2_8_ai(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 compare = REG_DA[(word2 >> 12) & 15]&0xff; + UINT32 ea = EA_AY_AI_8(m68k); + UINT32 lower_bound = m68ki_read_8(m68k, ea); + UINT32 upper_bound = m68ki_read_8(m68k, ea + 1); + + if(!BIT_F(word2)) + m68k->c_flag = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound); + else + m68k->c_flag = compare - lower_bound; + m68k->not_z_flag = !((upper_bound==compare) | (lower_bound==compare)); + if(COND_CS(m68k)) + { + if(BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + + m68k->c_flag = upper_bound - compare; + if(COND_CS(m68k) && BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_chk2cmp2_8_di(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 compare = REG_DA[(word2 >> 12) & 15]&0xff; + UINT32 ea = EA_AY_DI_8(m68k); + UINT32 lower_bound = m68ki_read_8(m68k, ea); + UINT32 upper_bound = m68ki_read_8(m68k, ea + 1); + + if(!BIT_F(word2)) + m68k->c_flag = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound); + else + m68k->c_flag = compare - lower_bound; + m68k->not_z_flag = !((upper_bound==compare) | (lower_bound==compare)); + if(COND_CS(m68k)) + { + if(BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + + m68k->c_flag = upper_bound - compare; + if(COND_CS(m68k) && BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_chk2cmp2_8_ix(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 compare = REG_DA[(word2 >> 12) & 15]&0xff; + UINT32 ea = EA_AY_IX_8(m68k); + UINT32 lower_bound = m68ki_read_8(m68k, ea); + UINT32 upper_bound = m68ki_read_8(m68k, ea + 1); + + if(!BIT_F(word2)) + m68k->c_flag = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound); + else + m68k->c_flag = compare - lower_bound; + m68k->not_z_flag = !((upper_bound==compare) | (lower_bound==compare)); + if(COND_CS(m68k)) + { + if(BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + + m68k->c_flag = upper_bound - compare; + if(COND_CS(m68k) && BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_chk2cmp2_8_aw(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 compare = REG_DA[(word2 >> 12) & 15]&0xff; + UINT32 ea = EA_AW_8(m68k); + UINT32 lower_bound = m68ki_read_8(m68k, ea); + UINT32 upper_bound = m68ki_read_8(m68k, ea + 1); + + if(!BIT_F(word2)) + m68k->c_flag = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound); + else + m68k->c_flag = compare - lower_bound; + m68k->not_z_flag = !((upper_bound==compare) | (lower_bound==compare)); + if(COND_CS(m68k)) + { + if(BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + + m68k->c_flag = upper_bound - compare; + if(COND_CS(m68k) && BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_chk2cmp2_8_al(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 compare = REG_DA[(word2 >> 12) & 15]&0xff; + UINT32 ea = EA_AL_8(m68k); + UINT32 lower_bound = m68ki_read_8(m68k, ea); + UINT32 upper_bound = m68ki_read_8(m68k, ea + 1); + + if(!BIT_F(word2)) + m68k->c_flag = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound); + else + m68k->c_flag = compare - lower_bound; + m68k->not_z_flag = !((upper_bound==compare) | (lower_bound==compare)); + if(COND_CS(m68k)) + { + if(BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + + m68k->c_flag = upper_bound - compare; + if(COND_CS(m68k) && BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_chk2cmp2_16_pcdi(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 compare = REG_DA[(word2 >> 12) & 15]&0xffff; + UINT32 ea = EA_PCDI_16(m68k); + UINT32 lower_bound = m68ki_read_pcrel_16(m68k, ea); + UINT32 upper_bound = m68ki_read_pcrel_16(m68k, ea + 2); + + if(!BIT_F(word2)) + m68k->c_flag = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound); + else + m68k->c_flag = compare - lower_bound; + m68k->not_z_flag = !((upper_bound==compare) | (lower_bound==compare)); + m68k->c_flag = CFLAG_16(m68k->c_flag); + if(COND_CS(m68k)) + { + if(BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + + if(!BIT_F(word2)) + m68k->c_flag = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare); + else + m68k->c_flag = upper_bound - compare; + m68k->c_flag = CFLAG_16(m68k->c_flag); + if(COND_CS(m68k) && BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_chk2cmp2_16_pcix(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 compare = REG_DA[(word2 >> 12) & 15]&0xffff; + UINT32 ea = EA_PCIX_16(m68k); + UINT32 lower_bound = m68ki_read_pcrel_16(m68k, ea); + UINT32 upper_bound = m68ki_read_pcrel_16(m68k, ea + 2); + + if(!BIT_F(word2)) + m68k->c_flag = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound); + else + m68k->c_flag = compare - lower_bound; + m68k->not_z_flag = !((upper_bound==compare) | (lower_bound==compare)); + m68k->c_flag = CFLAG_16(m68k->c_flag); + if(COND_CS(m68k)) + { + if(BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + + if(!BIT_F(word2)) + m68k->c_flag = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare); + else + m68k->c_flag = upper_bound - compare; + m68k->c_flag = CFLAG_16(m68k->c_flag); + if(COND_CS(m68k) && BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_chk2cmp2_16_ai(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 compare = REG_DA[(word2 >> 12) & 15]&0xffff; + UINT32 ea = EA_AY_AI_16(m68k); + UINT32 lower_bound = m68ki_read_16(m68k, ea); + UINT32 upper_bound = m68ki_read_16(m68k, ea + 2); + + if(!BIT_F(word2)) + m68k->c_flag = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound); + else + m68k->c_flag = compare - lower_bound; + + m68k->not_z_flag = !((upper_bound==compare) | (lower_bound==compare)); + m68k->c_flag = CFLAG_16(m68k->c_flag); + if(COND_CS(m68k)) + { + if(BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + if(!BIT_F(word2)) + m68k->c_flag = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare); + else + m68k->c_flag = upper_bound - compare; + + m68k->c_flag = CFLAG_16(m68k->c_flag); + if(COND_CS(m68k) && BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_chk2cmp2_16_di(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 compare = REG_DA[(word2 >> 12) & 15]&0xffff; + UINT32 ea = EA_AY_DI_16(m68k); + UINT32 lower_bound = m68ki_read_16(m68k, ea); + UINT32 upper_bound = m68ki_read_16(m68k, ea + 2); + + if(!BIT_F(word2)) + m68k->c_flag = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound); + else + m68k->c_flag = compare - lower_bound; + + m68k->not_z_flag = !((upper_bound==compare) | (lower_bound==compare)); + m68k->c_flag = CFLAG_16(m68k->c_flag); + if(COND_CS(m68k)) + { + if(BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + if(!BIT_F(word2)) + m68k->c_flag = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare); + else + m68k->c_flag = upper_bound - compare; + + m68k->c_flag = CFLAG_16(m68k->c_flag); + if(COND_CS(m68k) && BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_chk2cmp2_16_ix(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 compare = REG_DA[(word2 >> 12) & 15]&0xffff; + UINT32 ea = EA_AY_IX_16(m68k); + UINT32 lower_bound = m68ki_read_16(m68k, ea); + UINT32 upper_bound = m68ki_read_16(m68k, ea + 2); + + if(!BIT_F(word2)) + m68k->c_flag = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound); + else + m68k->c_flag = compare - lower_bound; + + m68k->not_z_flag = !((upper_bound==compare) | (lower_bound==compare)); + m68k->c_flag = CFLAG_16(m68k->c_flag); + if(COND_CS(m68k)) + { + if(BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + if(!BIT_F(word2)) + m68k->c_flag = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare); + else + m68k->c_flag = upper_bound - compare; + + m68k->c_flag = CFLAG_16(m68k->c_flag); + if(COND_CS(m68k) && BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_chk2cmp2_16_aw(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 compare = REG_DA[(word2 >> 12) & 15]&0xffff; + UINT32 ea = EA_AW_16(m68k); + UINT32 lower_bound = m68ki_read_16(m68k, ea); + UINT32 upper_bound = m68ki_read_16(m68k, ea + 2); + + if(!BIT_F(word2)) + m68k->c_flag = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound); + else + m68k->c_flag = compare - lower_bound; + + m68k->not_z_flag = !((upper_bound==compare) | (lower_bound==compare)); + m68k->c_flag = CFLAG_16(m68k->c_flag); + if(COND_CS(m68k)) + { + if(BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + if(!BIT_F(word2)) + m68k->c_flag = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare); + else + m68k->c_flag = upper_bound - compare; + + m68k->c_flag = CFLAG_16(m68k->c_flag); + if(COND_CS(m68k) && BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_chk2cmp2_16_al(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 compare = REG_DA[(word2 >> 12) & 15]&0xffff; + UINT32 ea = EA_AL_16(m68k); + UINT32 lower_bound = m68ki_read_16(m68k, ea); + UINT32 upper_bound = m68ki_read_16(m68k, ea + 2); + + if(!BIT_F(word2)) + m68k->c_flag = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound); + else + m68k->c_flag = compare - lower_bound; + + m68k->not_z_flag = !((upper_bound==compare) | (lower_bound==compare)); + m68k->c_flag = CFLAG_16(m68k->c_flag); + if(COND_CS(m68k)) + { + if(BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + if(!BIT_F(word2)) + m68k->c_flag = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare); + else + m68k->c_flag = upper_bound - compare; + + m68k->c_flag = CFLAG_16(m68k->c_flag); + if(COND_CS(m68k) && BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_chk2cmp2_32_pcdi(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 compare = REG_DA[(word2 >> 12) & 15]; + UINT32 ea = EA_PCDI_32(m68k); + UINT32 lower_bound = m68ki_read_pcrel_32(m68k, ea); + UINT32 upper_bound = m68ki_read_pcrel_32(m68k, ea + 4); + + m68k->c_flag = compare - lower_bound; + m68k->not_z_flag = !((upper_bound==compare) | (lower_bound==compare)); + m68k->c_flag = CFLAG_SUB_32(lower_bound, compare, m68k->c_flag); + if(COND_CS(m68k)) + { + if(BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + + m68k->c_flag = upper_bound - compare; + m68k->c_flag = CFLAG_SUB_32(compare, upper_bound, m68k->c_flag); + if(COND_CS(m68k) && BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_chk2cmp2_32_pcix(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 compare = REG_DA[(word2 >> 12) & 15]; + UINT32 ea = EA_PCIX_32(m68k); + UINT32 lower_bound = m68ki_read_pcrel_32(m68k, ea); + UINT32 upper_bound = m68ki_read_pcrel_32(m68k, ea + 4); + + m68k->c_flag = compare - lower_bound; + m68k->not_z_flag = !((upper_bound==compare) | (lower_bound==compare)); + m68k->c_flag = CFLAG_SUB_32(lower_bound, compare, m68k->c_flag); + if(COND_CS(m68k)) + { + if(BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + + m68k->c_flag = upper_bound - compare; + m68k->c_flag = CFLAG_SUB_32(compare, upper_bound, m68k->c_flag); + if(COND_CS(m68k) && BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_chk2cmp2_32_ai(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 compare = REG_DA[(word2 >> 12) & 15]; + UINT32 ea = EA_AY_AI_32(m68k); + UINT32 lower_bound = m68ki_read_32(m68k, ea); + UINT32 upper_bound = m68ki_read_32(m68k, ea + 4); + + m68k->c_flag = compare - lower_bound; + m68k->not_z_flag = !((upper_bound==compare) | (lower_bound==compare)); + m68k->c_flag = CFLAG_SUB_32(lower_bound, compare, m68k->c_flag); + if(COND_CS(m68k)) + { + if(BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + + m68k->c_flag = upper_bound - compare; + m68k->c_flag = CFLAG_SUB_32(compare, upper_bound, m68k->c_flag); + if(COND_CS(m68k) && BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_chk2cmp2_32_di(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 compare = REG_DA[(word2 >> 12) & 15]; + UINT32 ea = EA_AY_DI_32(m68k); + UINT32 lower_bound = m68ki_read_32(m68k, ea); + UINT32 upper_bound = m68ki_read_32(m68k, ea + 4); + + m68k->c_flag = compare - lower_bound; + m68k->not_z_flag = !((upper_bound==compare) | (lower_bound==compare)); + m68k->c_flag = CFLAG_SUB_32(lower_bound, compare, m68k->c_flag); + if(COND_CS(m68k)) + { + if(BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + + m68k->c_flag = upper_bound - compare; + m68k->c_flag = CFLAG_SUB_32(compare, upper_bound, m68k->c_flag); + if(COND_CS(m68k) && BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_chk2cmp2_32_ix(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 compare = REG_DA[(word2 >> 12) & 15]; + UINT32 ea = EA_AY_IX_32(m68k); + UINT32 lower_bound = m68ki_read_32(m68k, ea); + UINT32 upper_bound = m68ki_read_32(m68k, ea + 4); + + m68k->c_flag = compare - lower_bound; + m68k->not_z_flag = !((upper_bound==compare) | (lower_bound==compare)); + m68k->c_flag = CFLAG_SUB_32(lower_bound, compare, m68k->c_flag); + if(COND_CS(m68k)) + { + if(BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + + m68k->c_flag = upper_bound - compare; + m68k->c_flag = CFLAG_SUB_32(compare, upper_bound, m68k->c_flag); + if(COND_CS(m68k) && BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_chk2cmp2_32_aw(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 compare = REG_DA[(word2 >> 12) & 15]; + UINT32 ea = EA_AW_32(m68k); + UINT32 lower_bound = m68ki_read_32(m68k, ea); + UINT32 upper_bound = m68ki_read_32(m68k, ea + 4); + + m68k->c_flag = compare - lower_bound; + m68k->not_z_flag = !((upper_bound==compare) | (lower_bound==compare)); + m68k->c_flag = CFLAG_SUB_32(lower_bound, compare, m68k->c_flag); + if(COND_CS(m68k)) + { + if(BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + + m68k->c_flag = upper_bound - compare; + m68k->c_flag = CFLAG_SUB_32(compare, upper_bound, m68k->c_flag); + if(COND_CS(m68k) && BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_chk2cmp2_32_al(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 compare = REG_DA[(word2 >> 12) & 15]; + UINT32 ea = EA_AL_32(m68k); + UINT32 lower_bound = m68ki_read_32(m68k, ea); + UINT32 upper_bound = m68ki_read_32(m68k, ea + 4); + + m68k->c_flag = compare - lower_bound; + m68k->not_z_flag = !((upper_bound==compare) | (lower_bound==compare)); + m68k->c_flag = CFLAG_SUB_32(lower_bound, compare, m68k->c_flag); + if(COND_CS(m68k)) + { + if(BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + + m68k->c_flag = upper_bound - compare; + m68k->c_flag = CFLAG_SUB_32(compare, upper_bound, m68k->c_flag); + if(COND_CS(m68k) && BIT_B(word2)) + m68ki_exception_trap(m68k, EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_clr_8_d(m68ki_cpu_core *m68k) +{ + DY &= 0xffffff00; + + m68k->n_flag = NFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + m68k->not_z_flag = ZFLAG_SET; +} + + +static void m68k_op_clr_8_ai(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_AI_8(m68k), 0); + + m68k->n_flag = NFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + m68k->not_z_flag = ZFLAG_SET; +} + + +static void m68k_op_clr_8_pi(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_PI_8(m68k), 0); + + m68k->n_flag = NFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + m68k->not_z_flag = ZFLAG_SET; +} + + +static void m68k_op_clr_8_pi7(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_A7_PI_8(m68k), 0); + + m68k->n_flag = NFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + m68k->not_z_flag = ZFLAG_SET; +} + + +static void m68k_op_clr_8_pd(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_PD_8(m68k), 0); + + m68k->n_flag = NFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + m68k->not_z_flag = ZFLAG_SET; +} + + +static void m68k_op_clr_8_pd7(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_A7_PD_8(m68k), 0); + + m68k->n_flag = NFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + m68k->not_z_flag = ZFLAG_SET; +} + + +static void m68k_op_clr_8_di(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_DI_8(m68k), 0); + + m68k->n_flag = NFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + m68k->not_z_flag = ZFLAG_SET; +} + + +static void m68k_op_clr_8_ix(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_IX_8(m68k), 0); + + m68k->n_flag = NFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + m68k->not_z_flag = ZFLAG_SET; +} + + +static void m68k_op_clr_8_aw(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AW_8(m68k), 0); + + m68k->n_flag = NFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + m68k->not_z_flag = ZFLAG_SET; +} + + +static void m68k_op_clr_8_al(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AL_8(m68k), 0); + + m68k->n_flag = NFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + m68k->not_z_flag = ZFLAG_SET; +} + + +static void m68k_op_clr_16_d(m68ki_cpu_core *m68k) +{ + DY &= 0xffff0000; + + m68k->n_flag = NFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + m68k->not_z_flag = ZFLAG_SET; +} + + +static void m68k_op_clr_16_ai(m68ki_cpu_core *m68k) +{ + m68ki_write_16(m68k, EA_AY_AI_16(m68k), 0); + + m68k->n_flag = NFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + m68k->not_z_flag = ZFLAG_SET; +} + + +static void m68k_op_clr_16_pi(m68ki_cpu_core *m68k) +{ + m68ki_write_16(m68k, EA_AY_PI_16(m68k), 0); + + m68k->n_flag = NFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + m68k->not_z_flag = ZFLAG_SET; +} + + +static void m68k_op_clr_16_pd(m68ki_cpu_core *m68k) +{ + m68ki_write_16(m68k, EA_AY_PD_16(m68k), 0); + + m68k->n_flag = NFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + m68k->not_z_flag = ZFLAG_SET; +} + + +static void m68k_op_clr_16_di(m68ki_cpu_core *m68k) +{ + m68ki_write_16(m68k, EA_AY_DI_16(m68k), 0); + + m68k->n_flag = NFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + m68k->not_z_flag = ZFLAG_SET; +} + + +static void m68k_op_clr_16_ix(m68ki_cpu_core *m68k) +{ + m68ki_write_16(m68k, EA_AY_IX_16(m68k), 0); + + m68k->n_flag = NFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + m68k->not_z_flag = ZFLAG_SET; +} + + +static void m68k_op_clr_16_aw(m68ki_cpu_core *m68k) +{ + m68ki_write_16(m68k, EA_AW_16(m68k), 0); + + m68k->n_flag = NFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + m68k->not_z_flag = ZFLAG_SET; +} + + +static void m68k_op_clr_16_al(m68ki_cpu_core *m68k) +{ + m68ki_write_16(m68k, EA_AL_16(m68k), 0); + + m68k->n_flag = NFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + m68k->not_z_flag = ZFLAG_SET; +} + + +static void m68k_op_clr_32_d(m68ki_cpu_core *m68k) +{ + DY = 0; + + m68k->n_flag = NFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + m68k->not_z_flag = ZFLAG_SET; +} + + +static void m68k_op_clr_32_ai(m68ki_cpu_core *m68k) +{ + m68ki_write_32(m68k, EA_AY_AI_32(m68k), 0); + + m68k->n_flag = NFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + m68k->not_z_flag = ZFLAG_SET; +} + + +static void m68k_op_clr_32_pi(m68ki_cpu_core *m68k) +{ + m68ki_write_32(m68k, EA_AY_PI_32(m68k), 0); + + m68k->n_flag = NFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + m68k->not_z_flag = ZFLAG_SET; +} + + +static void m68k_op_clr_32_pd(m68ki_cpu_core *m68k) +{ + m68ki_write_32(m68k, EA_AY_PD_32(m68k), 0); + + m68k->n_flag = NFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + m68k->not_z_flag = ZFLAG_SET; +} + + +static void m68k_op_clr_32_di(m68ki_cpu_core *m68k) +{ + m68ki_write_32(m68k, EA_AY_DI_32(m68k), 0); + + m68k->n_flag = NFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + m68k->not_z_flag = ZFLAG_SET; +} + + +static void m68k_op_clr_32_ix(m68ki_cpu_core *m68k) +{ + m68ki_write_32(m68k, EA_AY_IX_32(m68k), 0); + + m68k->n_flag = NFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + m68k->not_z_flag = ZFLAG_SET; +} + + +static void m68k_op_clr_32_aw(m68ki_cpu_core *m68k) +{ + m68ki_write_32(m68k, EA_AW_32(m68k), 0); + + m68k->n_flag = NFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + m68k->not_z_flag = ZFLAG_SET; +} + + +static void m68k_op_clr_32_al(m68ki_cpu_core *m68k) +{ + m68ki_write_32(m68k, EA_AL_32(m68k), 0); + + m68k->n_flag = NFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + m68k->not_z_flag = ZFLAG_SET; +} + + +static void m68k_op_cmp_8_d(m68ki_cpu_core *m68k) +{ + UINT32 src = MASK_OUT_ABOVE_8(DY); + UINT32 dst = MASK_OUT_ABOVE_8(DX); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + m68k->c_flag = CFLAG_8(res); +} + + +static void m68k_op_cmp_8_ai(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_AY_AI_8(m68k); + UINT32 dst = MASK_OUT_ABOVE_8(DX); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + m68k->c_flag = CFLAG_8(res); +} + + +static void m68k_op_cmp_8_pi(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_AY_PI_8(m68k); + UINT32 dst = MASK_OUT_ABOVE_8(DX); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + m68k->c_flag = CFLAG_8(res); +} + + +static void m68k_op_cmp_8_pi7(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_A7_PI_8(m68k); + UINT32 dst = MASK_OUT_ABOVE_8(DX); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + m68k->c_flag = CFLAG_8(res); +} + + +static void m68k_op_cmp_8_pd(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_AY_PD_8(m68k); + UINT32 dst = MASK_OUT_ABOVE_8(DX); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + m68k->c_flag = CFLAG_8(res); +} + + +static void m68k_op_cmp_8_pd7(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_A7_PD_8(m68k); + UINT32 dst = MASK_OUT_ABOVE_8(DX); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + m68k->c_flag = CFLAG_8(res); +} + + +static void m68k_op_cmp_8_di(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_AY_DI_8(m68k); + UINT32 dst = MASK_OUT_ABOVE_8(DX); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + m68k->c_flag = CFLAG_8(res); +} + + +static void m68k_op_cmp_8_ix(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_AY_IX_8(m68k); + UINT32 dst = MASK_OUT_ABOVE_8(DX); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + m68k->c_flag = CFLAG_8(res); +} + + +static void m68k_op_cmp_8_aw(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_AW_8(m68k); + UINT32 dst = MASK_OUT_ABOVE_8(DX); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + m68k->c_flag = CFLAG_8(res); +} + + +static void m68k_op_cmp_8_al(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_AL_8(m68k); + UINT32 dst = MASK_OUT_ABOVE_8(DX); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + m68k->c_flag = CFLAG_8(res); +} + + +static void m68k_op_cmp_8_pcdi(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_PCDI_8(m68k); + UINT32 dst = MASK_OUT_ABOVE_8(DX); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + m68k->c_flag = CFLAG_8(res); +} + + +static void m68k_op_cmp_8_pcix(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_PCIX_8(m68k); + UINT32 dst = MASK_OUT_ABOVE_8(DX); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + m68k->c_flag = CFLAG_8(res); +} + + +static void m68k_op_cmp_8_i(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 dst = MASK_OUT_ABOVE_8(DX); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + m68k->c_flag = CFLAG_8(res); +} + + +static void m68k_op_cmp_16_d(m68ki_cpu_core *m68k) +{ + UINT32 src = MASK_OUT_ABOVE_16(DY); + UINT32 dst = MASK_OUT_ABOVE_16(DX); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + m68k->c_flag = CFLAG_16(res); +} + + +static void m68k_op_cmp_16_a(m68ki_cpu_core *m68k) +{ + UINT32 src = MASK_OUT_ABOVE_16(AY); + UINT32 dst = MASK_OUT_ABOVE_16(DX); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + m68k->c_flag = CFLAG_16(res); +} + + +static void m68k_op_cmp_16_ai(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_AY_AI_16(m68k); + UINT32 dst = MASK_OUT_ABOVE_16(DX); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + m68k->c_flag = CFLAG_16(res); +} + + +static void m68k_op_cmp_16_pi(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_AY_PI_16(m68k); + UINT32 dst = MASK_OUT_ABOVE_16(DX); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + m68k->c_flag = CFLAG_16(res); +} + + +static void m68k_op_cmp_16_pd(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_AY_PD_16(m68k); + UINT32 dst = MASK_OUT_ABOVE_16(DX); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + m68k->c_flag = CFLAG_16(res); +} + + +static void m68k_op_cmp_16_di(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_AY_DI_16(m68k); + UINT32 dst = MASK_OUT_ABOVE_16(DX); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + m68k->c_flag = CFLAG_16(res); +} + + +static void m68k_op_cmp_16_ix(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_AY_IX_16(m68k); + UINT32 dst = MASK_OUT_ABOVE_16(DX); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + m68k->c_flag = CFLAG_16(res); +} + + +static void m68k_op_cmp_16_aw(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_AW_16(m68k); + UINT32 dst = MASK_OUT_ABOVE_16(DX); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + m68k->c_flag = CFLAG_16(res); +} + + +static void m68k_op_cmp_16_al(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_AL_16(m68k); + UINT32 dst = MASK_OUT_ABOVE_16(DX); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + m68k->c_flag = CFLAG_16(res); +} + + +static void m68k_op_cmp_16_pcdi(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_PCDI_16(m68k); + UINT32 dst = MASK_OUT_ABOVE_16(DX); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + m68k->c_flag = CFLAG_16(res); +} + + +static void m68k_op_cmp_16_pcix(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_PCIX_16(m68k); + UINT32 dst = MASK_OUT_ABOVE_16(DX); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + m68k->c_flag = CFLAG_16(res); +} + + +static void m68k_op_cmp_16_i(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_16(m68k); + UINT32 dst = MASK_OUT_ABOVE_16(DX); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + m68k->c_flag = CFLAG_16(res); +} + + +static void m68k_op_cmp_32_d(m68ki_cpu_core *m68k) +{ + UINT32 src = DY; + UINT32 dst = DX; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); +} + + +static void m68k_op_cmp_32_a(m68ki_cpu_core *m68k) +{ + UINT32 src = AY; + UINT32 dst = DX; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); +} + + +static void m68k_op_cmp_32_ai(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_AY_AI_32(m68k); + UINT32 dst = DX; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); +} + + +static void m68k_op_cmp_32_pi(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_AY_PI_32(m68k); + UINT32 dst = DX; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); +} + + +static void m68k_op_cmp_32_pd(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_AY_PD_32(m68k); + UINT32 dst = DX; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); +} + + +static void m68k_op_cmp_32_di(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_AY_DI_32(m68k); + UINT32 dst = DX; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); +} + + +static void m68k_op_cmp_32_ix(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_AY_IX_32(m68k); + UINT32 dst = DX; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); +} + + +static void m68k_op_cmp_32_aw(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_AW_32(m68k); + UINT32 dst = DX; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); +} + + +static void m68k_op_cmp_32_al(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_AL_32(m68k); + UINT32 dst = DX; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); +} + + +static void m68k_op_cmp_32_pcdi(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_PCDI_32(m68k); + UINT32 dst = DX; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); +} + + +static void m68k_op_cmp_32_pcix(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_PCIX_32(m68k); + UINT32 dst = DX; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); +} + + +static void m68k_op_cmp_32_i(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_32(m68k); + UINT32 dst = DX; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); +} + + +static void m68k_op_cmpa_16_d(m68ki_cpu_core *m68k) +{ + UINT32 src = MAKE_INT_16(DY); + UINT32 dst = AX; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); +} + + +static void m68k_op_cmpa_16_a(m68ki_cpu_core *m68k) +{ + UINT32 src = MAKE_INT_16(AY); + UINT32 dst = AX; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); +} + + +static void m68k_op_cmpa_16_ai(m68ki_cpu_core *m68k) +{ + UINT32 src = MAKE_INT_16(OPER_AY_AI_16(m68k)); + UINT32 dst = AX; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); +} + + +static void m68k_op_cmpa_16_pi(m68ki_cpu_core *m68k) +{ + UINT32 src = MAKE_INT_16(OPER_AY_PI_16(m68k)); + UINT32 dst = AX; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); +} + + +static void m68k_op_cmpa_16_pd(m68ki_cpu_core *m68k) +{ + UINT32 src = MAKE_INT_16(OPER_AY_PD_16(m68k)); + UINT32 dst = AX; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); +} + + +static void m68k_op_cmpa_16_di(m68ki_cpu_core *m68k) +{ + UINT32 src = MAKE_INT_16(OPER_AY_DI_16(m68k)); + UINT32 dst = AX; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); +} + + +static void m68k_op_cmpa_16_ix(m68ki_cpu_core *m68k) +{ + UINT32 src = MAKE_INT_16(OPER_AY_IX_16(m68k)); + UINT32 dst = AX; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); +} + + +static void m68k_op_cmpa_16_aw(m68ki_cpu_core *m68k) +{ + UINT32 src = MAKE_INT_16(OPER_AW_16(m68k)); + UINT32 dst = AX; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); +} + + +static void m68k_op_cmpa_16_al(m68ki_cpu_core *m68k) +{ + UINT32 src = MAKE_INT_16(OPER_AL_16(m68k)); + UINT32 dst = AX; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); +} + + +static void m68k_op_cmpa_16_pcdi(m68ki_cpu_core *m68k) +{ + UINT32 src = MAKE_INT_16(OPER_PCDI_16(m68k)); + UINT32 dst = AX; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); +} + + +static void m68k_op_cmpa_16_pcix(m68ki_cpu_core *m68k) +{ + UINT32 src = MAKE_INT_16(OPER_PCIX_16(m68k)); + UINT32 dst = AX; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); +} + + +static void m68k_op_cmpa_16_i(m68ki_cpu_core *m68k) +{ + UINT32 src = MAKE_INT_16(OPER_I_16(m68k)); + UINT32 dst = AX; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); +} + + +static void m68k_op_cmpa_32_d(m68ki_cpu_core *m68k) +{ + UINT32 src = DY; + UINT32 dst = AX; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); +} + + +static void m68k_op_cmpa_32_a(m68ki_cpu_core *m68k) +{ + UINT32 src = AY; + UINT32 dst = AX; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); +} + + +static void m68k_op_cmpa_32_ai(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_AY_AI_32(m68k); + UINT32 dst = AX; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); +} + + +static void m68k_op_cmpa_32_pi(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_AY_PI_32(m68k); + UINT32 dst = AX; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); +} + + +static void m68k_op_cmpa_32_pd(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_AY_PD_32(m68k); + UINT32 dst = AX; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); +} + + +static void m68k_op_cmpa_32_di(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_AY_DI_32(m68k); + UINT32 dst = AX; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); +} + + +static void m68k_op_cmpa_32_ix(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_AY_IX_32(m68k); + UINT32 dst = AX; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); +} + + +static void m68k_op_cmpa_32_aw(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_AW_32(m68k); + UINT32 dst = AX; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); +} + + +static void m68k_op_cmpa_32_al(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_AL_32(m68k); + UINT32 dst = AX; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); +} + + +static void m68k_op_cmpa_32_pcdi(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_PCDI_32(m68k); + UINT32 dst = AX; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); +} + + +static void m68k_op_cmpa_32_pcix(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_PCIX_32(m68k); + UINT32 dst = AX; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); +} + + +static void m68k_op_cmpa_32_i(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_32(m68k); + UINT32 dst = AX; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); +} + + +static void m68k_op_cmpi_8_d(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 dst = MASK_OUT_ABOVE_8(DY); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + m68k->c_flag = CFLAG_8(res); +} + + +static void m68k_op_cmpi_8_ai(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 dst = OPER_AY_AI_8(m68k); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + m68k->c_flag = CFLAG_8(res); +} + + +static void m68k_op_cmpi_8_pi(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 dst = OPER_AY_PI_8(m68k); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + m68k->c_flag = CFLAG_8(res); +} + + +static void m68k_op_cmpi_8_pi7(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 dst = OPER_A7_PI_8(m68k); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + m68k->c_flag = CFLAG_8(res); +} + + +static void m68k_op_cmpi_8_pd(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 dst = OPER_AY_PD_8(m68k); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + m68k->c_flag = CFLAG_8(res); +} + + +static void m68k_op_cmpi_8_pd7(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 dst = OPER_A7_PD_8(m68k); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + m68k->c_flag = CFLAG_8(res); +} + + +static void m68k_op_cmpi_8_di(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 dst = OPER_AY_DI_8(m68k); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + m68k->c_flag = CFLAG_8(res); +} + + +static void m68k_op_cmpi_8_ix(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 dst = OPER_AY_IX_8(m68k); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + m68k->c_flag = CFLAG_8(res); +} + + +static void m68k_op_cmpi_8_aw(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 dst = OPER_AW_8(m68k); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + m68k->c_flag = CFLAG_8(res); +} + + +static void m68k_op_cmpi_8_al(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 dst = OPER_AL_8(m68k); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + m68k->c_flag = CFLAG_8(res); +} + + +static void m68k_op_cmpi_8_pcdi(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 src = OPER_I_8(m68k); + UINT32 dst = OPER_PCDI_8(m68k); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + m68k->c_flag = CFLAG_8(res); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_cmpi_8_pcix(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 src = OPER_I_8(m68k); + UINT32 dst = OPER_PCIX_8(m68k); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + m68k->c_flag = CFLAG_8(res); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_cmpi_16_d(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_16(m68k); + UINT32 dst = MASK_OUT_ABOVE_16(DY); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + m68k->c_flag = CFLAG_16(res); +} + + +static void m68k_op_cmpi_16_ai(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_16(m68k); + UINT32 dst = OPER_AY_AI_16(m68k); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + m68k->c_flag = CFLAG_16(res); +} + + +static void m68k_op_cmpi_16_pi(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_16(m68k); + UINT32 dst = OPER_AY_PI_16(m68k); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + m68k->c_flag = CFLAG_16(res); +} + + +static void m68k_op_cmpi_16_pd(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_16(m68k); + UINT32 dst = OPER_AY_PD_16(m68k); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + m68k->c_flag = CFLAG_16(res); +} + + +static void m68k_op_cmpi_16_di(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_16(m68k); + UINT32 dst = OPER_AY_DI_16(m68k); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + m68k->c_flag = CFLAG_16(res); +} + + +static void m68k_op_cmpi_16_ix(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_16(m68k); + UINT32 dst = OPER_AY_IX_16(m68k); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + m68k->c_flag = CFLAG_16(res); +} + + +static void m68k_op_cmpi_16_aw(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_16(m68k); + UINT32 dst = OPER_AW_16(m68k); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + m68k->c_flag = CFLAG_16(res); +} + + +static void m68k_op_cmpi_16_al(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_16(m68k); + UINT32 dst = OPER_AL_16(m68k); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + m68k->c_flag = CFLAG_16(res); +} + + +static void m68k_op_cmpi_16_pcdi(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 src = OPER_I_16(m68k); + UINT32 dst = OPER_PCDI_16(m68k); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + m68k->c_flag = CFLAG_16(res); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_cmpi_16_pcix(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 src = OPER_I_16(m68k); + UINT32 dst = OPER_PCIX_16(m68k); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + m68k->c_flag = CFLAG_16(res); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_cmpi_32_d(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_32(m68k); + UINT32 dst = DY; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); +} + + +static void m68k_op_cmpi_32_ai(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_32(m68k); + UINT32 dst = OPER_AY_AI_32(m68k); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); +} + + +static void m68k_op_cmpi_32_pi(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_32(m68k); + UINT32 dst = OPER_AY_PI_32(m68k); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); +} + + +static void m68k_op_cmpi_32_pd(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_32(m68k); + UINT32 dst = OPER_AY_PD_32(m68k); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); +} + + +static void m68k_op_cmpi_32_di(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_32(m68k); + UINT32 dst = OPER_AY_DI_32(m68k); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); +} + + +static void m68k_op_cmpi_32_ix(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_32(m68k); + UINT32 dst = OPER_AY_IX_32(m68k); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); +} + + +static void m68k_op_cmpi_32_aw(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_32(m68k); + UINT32 dst = OPER_AW_32(m68k); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); +} + + +static void m68k_op_cmpi_32_al(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_32(m68k); + UINT32 dst = OPER_AL_32(m68k); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); +} + + +static void m68k_op_cmpi_32_pcdi(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 src = OPER_I_32(m68k); + UINT32 dst = OPER_PCDI_32(m68k); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_cmpi_32_pcix(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 src = OPER_I_32(m68k); + UINT32 dst = OPER_PCIX_32(m68k); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_cmpm_8_ax7(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_AY_PI_8(m68k); + UINT32 dst = OPER_A7_PI_8(m68k); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + m68k->c_flag = CFLAG_8(res); +} + + +static void m68k_op_cmpm_8_ay7(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_A7_PI_8(m68k); + UINT32 dst = OPER_AX_PI_8(m68k); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + m68k->c_flag = CFLAG_8(res); +} + + +static void m68k_op_cmpm_8_axy7(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_A7_PI_8(m68k); + UINT32 dst = OPER_A7_PI_8(m68k); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + m68k->c_flag = CFLAG_8(res); +} + + +static void m68k_op_cmpm_8(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_AY_PI_8(m68k); + UINT32 dst = OPER_AX_PI_8(m68k); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + m68k->c_flag = CFLAG_8(res); +} + + +static void m68k_op_cmpm_16(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_AY_PI_16(m68k); + UINT32 dst = OPER_AX_PI_16(m68k); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + m68k->c_flag = CFLAG_16(res); +} + + +static void m68k_op_cmpm_32(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_AY_PI_32(m68k); + UINT32 dst = OPER_AX_PI_32(m68k); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->c_flag = CFLAG_SUB_32(src, dst, res); +} + + +static void m68k_op_cpbcc_32(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + return; + } + m68ki_exception_1111(m68k); +} + + +static void m68k_op_cpdbcc_32(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + return; + } + m68ki_exception_1111(m68k); +} + + +static void m68k_op_cpgen_32(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + return; + } + m68ki_exception_1111(m68k); +} + + +static void m68k_op_cpscc_32(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + return; + } + m68ki_exception_1111(m68k); +} + + +static void m68k_op_cptrapcc_32(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + return; + } + m68ki_exception_1111(m68k); +} + + +static void m68k_op_dbt_16(m68ki_cpu_core *m68k) +{ + REG_PC += 2; +} + + +static void m68k_op_dbf_16(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 res = MASK_OUT_ABOVE_16(*r_dst - 1); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + if(res != 0xffff) + { + UINT32 offset = OPER_I_16(m68k); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(m68k, offset); + m68k->remaining_cycles -= m68k->cyc_dbcc_f_noexp; + return; + } + REG_PC += 2; + m68k->remaining_cycles -= m68k->cyc_dbcc_f_exp; +} + + +static void m68k_op_dbhi_16(m68ki_cpu_core *m68k) +{ + if(COND_NOT_HI(m68k)) + { + UINT32* r_dst = &DY; + UINT32 res = MASK_OUT_ABOVE_16(*r_dst - 1); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + if(res != 0xffff) + { + UINT32 offset = OPER_I_16(m68k); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(m68k, offset); + m68k->remaining_cycles -= m68k->cyc_dbcc_f_noexp; + return; + } + REG_PC += 2; + m68k->remaining_cycles -= m68k->cyc_dbcc_f_exp; + return; + } + REG_PC += 2; +} + + +static void m68k_op_dbls_16(m68ki_cpu_core *m68k) +{ + if(COND_NOT_LS(m68k)) + { + UINT32* r_dst = &DY; + UINT32 res = MASK_OUT_ABOVE_16(*r_dst - 1); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + if(res != 0xffff) + { + UINT32 offset = OPER_I_16(m68k); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(m68k, offset); + m68k->remaining_cycles -= m68k->cyc_dbcc_f_noexp; + return; + } + REG_PC += 2; + m68k->remaining_cycles -= m68k->cyc_dbcc_f_exp; + return; + } + REG_PC += 2; +} + + +static void m68k_op_dbcc_16(m68ki_cpu_core *m68k) +{ + if(COND_NOT_CC(m68k)) + { + UINT32* r_dst = &DY; + UINT32 res = MASK_OUT_ABOVE_16(*r_dst - 1); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + if(res != 0xffff) + { + UINT32 offset = OPER_I_16(m68k); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(m68k, offset); + m68k->remaining_cycles -= m68k->cyc_dbcc_f_noexp; + return; + } + REG_PC += 2; + m68k->remaining_cycles -= m68k->cyc_dbcc_f_exp; + return; + } + REG_PC += 2; +} + + +static void m68k_op_dbcs_16(m68ki_cpu_core *m68k) +{ + if(COND_NOT_CS(m68k)) + { + UINT32* r_dst = &DY; + UINT32 res = MASK_OUT_ABOVE_16(*r_dst - 1); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + if(res != 0xffff) + { + UINT32 offset = OPER_I_16(m68k); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(m68k, offset); + m68k->remaining_cycles -= m68k->cyc_dbcc_f_noexp; + return; + } + REG_PC += 2; + m68k->remaining_cycles -= m68k->cyc_dbcc_f_exp; + return; + } + REG_PC += 2; +} + + +static void m68k_op_dbne_16(m68ki_cpu_core *m68k) +{ + if(COND_NOT_NE(m68k)) + { + UINT32* r_dst = &DY; + UINT32 res = MASK_OUT_ABOVE_16(*r_dst - 1); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + if(res != 0xffff) + { + UINT32 offset = OPER_I_16(m68k); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(m68k, offset); + m68k->remaining_cycles -= m68k->cyc_dbcc_f_noexp; + return; + } + REG_PC += 2; + m68k->remaining_cycles -= m68k->cyc_dbcc_f_exp; + return; + } + REG_PC += 2; +} + + +static void m68k_op_dbeq_16(m68ki_cpu_core *m68k) +{ + if(COND_NOT_EQ(m68k)) + { + UINT32* r_dst = &DY; + UINT32 res = MASK_OUT_ABOVE_16(*r_dst - 1); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + if(res != 0xffff) + { + UINT32 offset = OPER_I_16(m68k); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(m68k, offset); + m68k->remaining_cycles -= m68k->cyc_dbcc_f_noexp; + return; + } + REG_PC += 2; + m68k->remaining_cycles -= m68k->cyc_dbcc_f_exp; + return; + } + REG_PC += 2; +} + + +static void m68k_op_dbvc_16(m68ki_cpu_core *m68k) +{ + if(COND_NOT_VC(m68k)) + { + UINT32* r_dst = &DY; + UINT32 res = MASK_OUT_ABOVE_16(*r_dst - 1); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + if(res != 0xffff) + { + UINT32 offset = OPER_I_16(m68k); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(m68k, offset); + m68k->remaining_cycles -= m68k->cyc_dbcc_f_noexp; + return; + } + REG_PC += 2; + m68k->remaining_cycles -= m68k->cyc_dbcc_f_exp; + return; + } + REG_PC += 2; +} + + +static void m68k_op_dbvs_16(m68ki_cpu_core *m68k) +{ + if(COND_NOT_VS(m68k)) + { + UINT32* r_dst = &DY; + UINT32 res = MASK_OUT_ABOVE_16(*r_dst - 1); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + if(res != 0xffff) + { + UINT32 offset = OPER_I_16(m68k); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(m68k, offset); + m68k->remaining_cycles -= m68k->cyc_dbcc_f_noexp; + return; + } + REG_PC += 2; + m68k->remaining_cycles -= m68k->cyc_dbcc_f_exp; + return; + } + REG_PC += 2; +} + + +static void m68k_op_dbpl_16(m68ki_cpu_core *m68k) +{ + if(COND_NOT_PL(m68k)) + { + UINT32* r_dst = &DY; + UINT32 res = MASK_OUT_ABOVE_16(*r_dst - 1); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + if(res != 0xffff) + { + UINT32 offset = OPER_I_16(m68k); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(m68k, offset); + m68k->remaining_cycles -= m68k->cyc_dbcc_f_noexp; + return; + } + REG_PC += 2; + m68k->remaining_cycles -= m68k->cyc_dbcc_f_exp; + return; + } + REG_PC += 2; +} + + +static void m68k_op_dbmi_16(m68ki_cpu_core *m68k) +{ + if(COND_NOT_MI(m68k)) + { + UINT32* r_dst = &DY; + UINT32 res = MASK_OUT_ABOVE_16(*r_dst - 1); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + if(res != 0xffff) + { + UINT32 offset = OPER_I_16(m68k); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(m68k, offset); + m68k->remaining_cycles -= m68k->cyc_dbcc_f_noexp; + return; + } + REG_PC += 2; + m68k->remaining_cycles -= m68k->cyc_dbcc_f_exp; + return; + } + REG_PC += 2; +} + + +static void m68k_op_dbge_16(m68ki_cpu_core *m68k) +{ + if(COND_NOT_GE(m68k)) + { + UINT32* r_dst = &DY; + UINT32 res = MASK_OUT_ABOVE_16(*r_dst - 1); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + if(res != 0xffff) + { + UINT32 offset = OPER_I_16(m68k); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(m68k, offset); + m68k->remaining_cycles -= m68k->cyc_dbcc_f_noexp; + return; + } + REG_PC += 2; + m68k->remaining_cycles -= m68k->cyc_dbcc_f_exp; + return; + } + REG_PC += 2; +} + + +static void m68k_op_dblt_16(m68ki_cpu_core *m68k) +{ + if(COND_NOT_LT(m68k)) + { + UINT32* r_dst = &DY; + UINT32 res = MASK_OUT_ABOVE_16(*r_dst - 1); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + if(res != 0xffff) + { + UINT32 offset = OPER_I_16(m68k); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(m68k, offset); + m68k->remaining_cycles -= m68k->cyc_dbcc_f_noexp; + return; + } + REG_PC += 2; + m68k->remaining_cycles -= m68k->cyc_dbcc_f_exp; + return; + } + REG_PC += 2; +} + + +static void m68k_op_dbgt_16(m68ki_cpu_core *m68k) +{ + if(COND_NOT_GT(m68k)) + { + UINT32* r_dst = &DY; + UINT32 res = MASK_OUT_ABOVE_16(*r_dst - 1); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + if(res != 0xffff) + { + UINT32 offset = OPER_I_16(m68k); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(m68k, offset); + m68k->remaining_cycles -= m68k->cyc_dbcc_f_noexp; + return; + } + REG_PC += 2; + m68k->remaining_cycles -= m68k->cyc_dbcc_f_exp; + return; + } + REG_PC += 2; +} + + +static void m68k_op_dble_16(m68ki_cpu_core *m68k) +{ + if(COND_NOT_LE(m68k)) + { + UINT32* r_dst = &DY; + UINT32 res = MASK_OUT_ABOVE_16(*r_dst - 1); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + if(res != 0xffff) + { + UINT32 offset = OPER_I_16(m68k); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(m68k, offset); + m68k->remaining_cycles -= m68k->cyc_dbcc_f_noexp; + return; + } + REG_PC += 2; + m68k->remaining_cycles -= m68k->cyc_dbcc_f_exp; + return; + } + REG_PC += 2; +} + + +static void m68k_op_divs_16_d(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + INT32 src = MAKE_INT_16(DY); + INT32 quotient; + INT32 remainder; + + if(src != 0) + { + if((UINT32)*r_dst == 0x80000000 && src == -1) + { + m68k->not_z_flag = 0; + m68k->n_flag = NFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + *r_dst = 0; + return; + } + + quotient = MAKE_INT_32(*r_dst) / src; + remainder = MAKE_INT_32(*r_dst) % src; + + if(quotient == MAKE_INT_16(quotient)) + { + m68k->not_z_flag = quotient; + m68k->n_flag = NFLAG_16(quotient); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + m68k->v_flag = VFLAG_SET; + return; + } + m68ki_exception_trap(m68k, EXCEPTION_ZERO_DIVIDE); +} + + +static void m68k_op_divs_16_ai(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + INT32 src = MAKE_INT_16(OPER_AY_AI_16(m68k)); + INT32 quotient; + INT32 remainder; + + if(src != 0) + { + if((UINT32)*r_dst == 0x80000000 && src == -1) + { + m68k->not_z_flag = 0; + m68k->n_flag = NFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + *r_dst = 0; + return; + } + + quotient = MAKE_INT_32(*r_dst) / src; + remainder = MAKE_INT_32(*r_dst) % src; + + if(quotient == MAKE_INT_16(quotient)) + { + m68k->not_z_flag = quotient; + m68k->n_flag = NFLAG_16(quotient); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + m68k->v_flag = VFLAG_SET; + return; + } + m68ki_exception_trap(m68k, EXCEPTION_ZERO_DIVIDE); +} + + +static void m68k_op_divs_16_pi(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + INT32 src = MAKE_INT_16(OPER_AY_PI_16(m68k)); + INT32 quotient; + INT32 remainder; + + if(src != 0) + { + if((UINT32)*r_dst == 0x80000000 && src == -1) + { + m68k->not_z_flag = 0; + m68k->n_flag = NFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + *r_dst = 0; + return; + } + + quotient = MAKE_INT_32(*r_dst) / src; + remainder = MAKE_INT_32(*r_dst) % src; + + if(quotient == MAKE_INT_16(quotient)) + { + m68k->not_z_flag = quotient; + m68k->n_flag = NFLAG_16(quotient); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + m68k->v_flag = VFLAG_SET; + return; + } + m68ki_exception_trap(m68k, EXCEPTION_ZERO_DIVIDE); +} + + +static void m68k_op_divs_16_pd(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + INT32 src = MAKE_INT_16(OPER_AY_PD_16(m68k)); + INT32 quotient; + INT32 remainder; + + if(src != 0) + { + if((UINT32)*r_dst == 0x80000000 && src == -1) + { + m68k->not_z_flag = 0; + m68k->n_flag = NFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + *r_dst = 0; + return; + } + + quotient = MAKE_INT_32(*r_dst) / src; + remainder = MAKE_INT_32(*r_dst) % src; + + if(quotient == MAKE_INT_16(quotient)) + { + m68k->not_z_flag = quotient; + m68k->n_flag = NFLAG_16(quotient); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + m68k->v_flag = VFLAG_SET; + return; + } + m68ki_exception_trap(m68k, EXCEPTION_ZERO_DIVIDE); +} + + +static void m68k_op_divs_16_di(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + INT32 src = MAKE_INT_16(OPER_AY_DI_16(m68k)); + INT32 quotient; + INT32 remainder; + + if(src != 0) + { + if((UINT32)*r_dst == 0x80000000 && src == -1) + { + m68k->not_z_flag = 0; + m68k->n_flag = NFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + *r_dst = 0; + return; + } + + quotient = MAKE_INT_32(*r_dst) / src; + remainder = MAKE_INT_32(*r_dst) % src; + + if(quotient == MAKE_INT_16(quotient)) + { + m68k->not_z_flag = quotient; + m68k->n_flag = NFLAG_16(quotient); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + m68k->v_flag = VFLAG_SET; + return; + } + m68ki_exception_trap(m68k, EXCEPTION_ZERO_DIVIDE); +} + + +static void m68k_op_divs_16_ix(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + INT32 src = MAKE_INT_16(OPER_AY_IX_16(m68k)); + INT32 quotient; + INT32 remainder; + + if(src != 0) + { + if((UINT32)*r_dst == 0x80000000 && src == -1) + { + m68k->not_z_flag = 0; + m68k->n_flag = NFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + *r_dst = 0; + return; + } + + quotient = MAKE_INT_32(*r_dst) / src; + remainder = MAKE_INT_32(*r_dst) % src; + + if(quotient == MAKE_INT_16(quotient)) + { + m68k->not_z_flag = quotient; + m68k->n_flag = NFLAG_16(quotient); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + m68k->v_flag = VFLAG_SET; + return; + } + m68ki_exception_trap(m68k, EXCEPTION_ZERO_DIVIDE); +} + + +static void m68k_op_divs_16_aw(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + INT32 src = MAKE_INT_16(OPER_AW_16(m68k)); + INT32 quotient; + INT32 remainder; + + if(src != 0) + { + if((UINT32)*r_dst == 0x80000000 && src == -1) + { + m68k->not_z_flag = 0; + m68k->n_flag = NFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + *r_dst = 0; + return; + } + + quotient = MAKE_INT_32(*r_dst) / src; + remainder = MAKE_INT_32(*r_dst) % src; + + if(quotient == MAKE_INT_16(quotient)) + { + m68k->not_z_flag = quotient; + m68k->n_flag = NFLAG_16(quotient); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + m68k->v_flag = VFLAG_SET; + return; + } + m68ki_exception_trap(m68k, EXCEPTION_ZERO_DIVIDE); +} + + +static void m68k_op_divs_16_al(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + INT32 src = MAKE_INT_16(OPER_AL_16(m68k)); + INT32 quotient; + INT32 remainder; + + if(src != 0) + { + if((UINT32)*r_dst == 0x80000000 && src == -1) + { + m68k->not_z_flag = 0; + m68k->n_flag = NFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + *r_dst = 0; + return; + } + + quotient = MAKE_INT_32(*r_dst) / src; + remainder = MAKE_INT_32(*r_dst) % src; + + if(quotient == MAKE_INT_16(quotient)) + { + m68k->not_z_flag = quotient; + m68k->n_flag = NFLAG_16(quotient); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + m68k->v_flag = VFLAG_SET; + return; + } + m68ki_exception_trap(m68k, EXCEPTION_ZERO_DIVIDE); +} + + +static void m68k_op_divs_16_pcdi(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + INT32 src = MAKE_INT_16(OPER_PCDI_16(m68k)); + INT32 quotient; + INT32 remainder; + + if(src != 0) + { + if((UINT32)*r_dst == 0x80000000 && src == -1) + { + m68k->not_z_flag = 0; + m68k->n_flag = NFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + *r_dst = 0; + return; + } + + quotient = MAKE_INT_32(*r_dst) / src; + remainder = MAKE_INT_32(*r_dst) % src; + + if(quotient == MAKE_INT_16(quotient)) + { + m68k->not_z_flag = quotient; + m68k->n_flag = NFLAG_16(quotient); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + m68k->v_flag = VFLAG_SET; + return; + } + m68ki_exception_trap(m68k, EXCEPTION_ZERO_DIVIDE); +} + + +static void m68k_op_divs_16_pcix(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + INT32 src = MAKE_INT_16(OPER_PCIX_16(m68k)); + INT32 quotient; + INT32 remainder; + + if(src != 0) + { + if((UINT32)*r_dst == 0x80000000 && src == -1) + { + m68k->not_z_flag = 0; + m68k->n_flag = NFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + *r_dst = 0; + return; + } + + quotient = MAKE_INT_32(*r_dst) / src; + remainder = MAKE_INT_32(*r_dst) % src; + + if(quotient == MAKE_INT_16(quotient)) + { + m68k->not_z_flag = quotient; + m68k->n_flag = NFLAG_16(quotient); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + m68k->v_flag = VFLAG_SET; + return; + } + m68ki_exception_trap(m68k, EXCEPTION_ZERO_DIVIDE); +} + + +static void m68k_op_divs_16_i(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + INT32 src = MAKE_INT_16(OPER_I_16(m68k)); + INT32 quotient; + INT32 remainder; + + if(src != 0) + { + if((UINT32)*r_dst == 0x80000000 && src == -1) + { + m68k->not_z_flag = 0; + m68k->n_flag = NFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + *r_dst = 0; + return; + } + + quotient = MAKE_INT_32(*r_dst) / src; + remainder = MAKE_INT_32(*r_dst) % src; + + if(quotient == MAKE_INT_16(quotient)) + { + m68k->not_z_flag = quotient; + m68k->n_flag = NFLAG_16(quotient); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + m68k->v_flag = VFLAG_SET; + return; + } + m68ki_exception_trap(m68k, EXCEPTION_ZERO_DIVIDE); +} + + +static void m68k_op_divu_16_d(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = MASK_OUT_ABOVE_16(DY); + + if(src != 0) + { + UINT32 quotient = *r_dst / src; + UINT32 remainder = *r_dst % src; + + if(quotient < 0x10000) + { + m68k->not_z_flag = quotient; + m68k->n_flag = NFLAG_16(quotient); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + m68k->v_flag = VFLAG_SET; + return; + } + m68ki_exception_trap(m68k, EXCEPTION_ZERO_DIVIDE); +} + + +static void m68k_op_divu_16_ai(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_AY_AI_16(m68k); + + if(src != 0) + { + UINT32 quotient = *r_dst / src; + UINT32 remainder = *r_dst % src; + + if(quotient < 0x10000) + { + m68k->not_z_flag = quotient; + m68k->n_flag = NFLAG_16(quotient); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + m68k->v_flag = VFLAG_SET; + return; + } + m68ki_exception_trap(m68k, EXCEPTION_ZERO_DIVIDE); +} + + +static void m68k_op_divu_16_pi(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_AY_PI_16(m68k); + + if(src != 0) + { + UINT32 quotient = *r_dst / src; + UINT32 remainder = *r_dst % src; + + if(quotient < 0x10000) + { + m68k->not_z_flag = quotient; + m68k->n_flag = NFLAG_16(quotient); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + m68k->v_flag = VFLAG_SET; + return; + } + m68ki_exception_trap(m68k, EXCEPTION_ZERO_DIVIDE); +} + + +static void m68k_op_divu_16_pd(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_AY_PD_16(m68k); + + if(src != 0) + { + UINT32 quotient = *r_dst / src; + UINT32 remainder = *r_dst % src; + + if(quotient < 0x10000) + { + m68k->not_z_flag = quotient; + m68k->n_flag = NFLAG_16(quotient); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + m68k->v_flag = VFLAG_SET; + return; + } + m68ki_exception_trap(m68k, EXCEPTION_ZERO_DIVIDE); +} + + +static void m68k_op_divu_16_di(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_AY_DI_16(m68k); + + if(src != 0) + { + UINT32 quotient = *r_dst / src; + UINT32 remainder = *r_dst % src; + + if(quotient < 0x10000) + { + m68k->not_z_flag = quotient; + m68k->n_flag = NFLAG_16(quotient); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + m68k->v_flag = VFLAG_SET; + return; + } + m68ki_exception_trap(m68k, EXCEPTION_ZERO_DIVIDE); +} + + +static void m68k_op_divu_16_ix(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_AY_IX_16(m68k); + + if(src != 0) + { + UINT32 quotient = *r_dst / src; + UINT32 remainder = *r_dst % src; + + if(quotient < 0x10000) + { + m68k->not_z_flag = quotient; + m68k->n_flag = NFLAG_16(quotient); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + m68k->v_flag = VFLAG_SET; + return; + } + m68ki_exception_trap(m68k, EXCEPTION_ZERO_DIVIDE); +} + + +static void m68k_op_divu_16_aw(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_AW_16(m68k); + + if(src != 0) + { + UINT32 quotient = *r_dst / src; + UINT32 remainder = *r_dst % src; + + if(quotient < 0x10000) + { + m68k->not_z_flag = quotient; + m68k->n_flag = NFLAG_16(quotient); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + m68k->v_flag = VFLAG_SET; + return; + } + m68ki_exception_trap(m68k, EXCEPTION_ZERO_DIVIDE); +} + + +static void m68k_op_divu_16_al(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_AL_16(m68k); + + if(src != 0) + { + UINT32 quotient = *r_dst / src; + UINT32 remainder = *r_dst % src; + + if(quotient < 0x10000) + { + m68k->not_z_flag = quotient; + m68k->n_flag = NFLAG_16(quotient); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + m68k->v_flag = VFLAG_SET; + return; + } + m68ki_exception_trap(m68k, EXCEPTION_ZERO_DIVIDE); +} + + +static void m68k_op_divu_16_pcdi(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_PCDI_16(m68k); + + if(src != 0) + { + UINT32 quotient = *r_dst / src; + UINT32 remainder = *r_dst % src; + + if(quotient < 0x10000) + { + m68k->not_z_flag = quotient; + m68k->n_flag = NFLAG_16(quotient); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + m68k->v_flag = VFLAG_SET; + return; + } + m68ki_exception_trap(m68k, EXCEPTION_ZERO_DIVIDE); +} + + +static void m68k_op_divu_16_pcix(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_PCIX_16(m68k); + + if(src != 0) + { + UINT32 quotient = *r_dst / src; + UINT32 remainder = *r_dst % src; + + if(quotient < 0x10000) + { + m68k->not_z_flag = quotient; + m68k->n_flag = NFLAG_16(quotient); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + m68k->v_flag = VFLAG_SET; + return; + } + m68ki_exception_trap(m68k, EXCEPTION_ZERO_DIVIDE); +} + + +static void m68k_op_divu_16_i(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_I_16(m68k); + + if(src != 0) + { + UINT32 quotient = *r_dst / src; + UINT32 remainder = *r_dst % src; + + if(quotient < 0x10000) + { + m68k->not_z_flag = quotient; + m68k->n_flag = NFLAG_16(quotient); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + m68k->v_flag = VFLAG_SET; + return; + } + m68ki_exception_trap(m68k, EXCEPTION_ZERO_DIVIDE); +} + + +static void m68k_op_divl_32_d(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT64 divisor = DY; + UINT64 dividend = 0; + UINT64 quotient = 0; + UINT64 remainder = 0; + + if(divisor != 0) + { + if(BIT_A(word2)) /* 64 bit */ + { + dividend = REG_D[word2 & 7]; + dividend <<= 32; + dividend |= REG_D[(word2 >> 12) & 7]; + + if(BIT_B(word2)) /* signed */ + { + quotient = (UINT64)((INT64)dividend / (INT64)((INT32)divisor)); + remainder = (UINT64)((INT64)dividend % (INT64)((INT32)divisor)); + if((INT64)quotient != (INT64)((INT32)quotient)) + { + m68k->v_flag = VFLAG_SET; + return; + } + } + else /* unsigned */ + { + quotient = dividend / divisor; + if(quotient > 0xffffffff) + { + m68k->v_flag = VFLAG_SET; + return; + } + remainder = dividend % divisor; + } + } + else /* 32 bit */ + { + dividend = REG_D[(word2 >> 12) & 7]; + if(BIT_B(word2)) /* signed */ + { + quotient = (UINT64)((INT64)((INT32)dividend) / (INT64)((INT32)divisor)); + remainder = (UINT64)((INT64)((INT32)dividend) % (INT64)((INT32)divisor)); + } + else /* unsigned */ + { + quotient = dividend / divisor; + remainder = dividend % divisor; + } + } + + REG_D[word2 & 7] = remainder; + REG_D[(word2 >> 12) & 7] = quotient; + + m68k->n_flag = NFLAG_32(quotient); + m68k->not_z_flag = quotient; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + return; + } + m68ki_exception_trap(m68k, EXCEPTION_ZERO_DIVIDE); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_divl_32_ai(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT64 divisor = OPER_AY_AI_32(m68k); + UINT64 dividend = 0; + UINT64 quotient = 0; + UINT64 remainder = 0; + + if(divisor != 0) + { + if(BIT_A(word2)) /* 64 bit */ + { + dividend = REG_D[word2 & 7]; + dividend <<= 32; + dividend |= REG_D[(word2 >> 12) & 7]; + + if(BIT_B(word2)) /* signed */ + { + quotient = (UINT64)((INT64)dividend / (INT64)((INT32)divisor)); + remainder = (UINT64)((INT64)dividend % (INT64)((INT32)divisor)); + if((INT64)quotient != (INT64)((INT32)quotient)) + { + m68k->v_flag = VFLAG_SET; + return; + } + } + else /* unsigned */ + { + quotient = dividend / divisor; + if(quotient > 0xffffffff) + { + m68k->v_flag = VFLAG_SET; + return; + } + remainder = dividend % divisor; + } + } + else /* 32 bit */ + { + dividend = REG_D[(word2 >> 12) & 7]; + if(BIT_B(word2)) /* signed */ + { + quotient = (UINT64)((INT64)((INT32)dividend) / (INT64)((INT32)divisor)); + remainder = (UINT64)((INT64)((INT32)dividend) % (INT64)((INT32)divisor)); + } + else /* unsigned */ + { + quotient = dividend / divisor; + remainder = dividend % divisor; + } + } + + REG_D[word2 & 7] = remainder; + REG_D[(word2 >> 12) & 7] = quotient; + + m68k->n_flag = NFLAG_32(quotient); + m68k->not_z_flag = quotient; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + return; + } + m68ki_exception_trap(m68k, EXCEPTION_ZERO_DIVIDE); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_divl_32_pi(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT64 divisor = OPER_AY_PI_32(m68k); + UINT64 dividend = 0; + UINT64 quotient = 0; + UINT64 remainder = 0; + + if(divisor != 0) + { + if(BIT_A(word2)) /* 64 bit */ + { + dividend = REG_D[word2 & 7]; + dividend <<= 32; + dividend |= REG_D[(word2 >> 12) & 7]; + + if(BIT_B(word2)) /* signed */ + { + quotient = (UINT64)((INT64)dividend / (INT64)((INT32)divisor)); + remainder = (UINT64)((INT64)dividend % (INT64)((INT32)divisor)); + if((INT64)quotient != (INT64)((INT32)quotient)) + { + m68k->v_flag = VFLAG_SET; + return; + } + } + else /* unsigned */ + { + quotient = dividend / divisor; + if(quotient > 0xffffffff) + { + m68k->v_flag = VFLAG_SET; + return; + } + remainder = dividend % divisor; + } + } + else /* 32 bit */ + { + dividend = REG_D[(word2 >> 12) & 7]; + if(BIT_B(word2)) /* signed */ + { + quotient = (UINT64)((INT64)((INT32)dividend) / (INT64)((INT32)divisor)); + remainder = (UINT64)((INT64)((INT32)dividend) % (INT64)((INT32)divisor)); + } + else /* unsigned */ + { + quotient = dividend / divisor; + remainder = dividend % divisor; + } + } + + REG_D[word2 & 7] = remainder; + REG_D[(word2 >> 12) & 7] = quotient; + + m68k->n_flag = NFLAG_32(quotient); + m68k->not_z_flag = quotient; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + return; + } + m68ki_exception_trap(m68k, EXCEPTION_ZERO_DIVIDE); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_divl_32_pd(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT64 divisor = OPER_AY_PD_32(m68k); + UINT64 dividend = 0; + UINT64 quotient = 0; + UINT64 remainder = 0; + + if(divisor != 0) + { + if(BIT_A(word2)) /* 64 bit */ + { + dividend = REG_D[word2 & 7]; + dividend <<= 32; + dividend |= REG_D[(word2 >> 12) & 7]; + + if(BIT_B(word2)) /* signed */ + { + quotient = (UINT64)((INT64)dividend / (INT64)((INT32)divisor)); + remainder = (UINT64)((INT64)dividend % (INT64)((INT32)divisor)); + if((INT64)quotient != (INT64)((INT32)quotient)) + { + m68k->v_flag = VFLAG_SET; + return; + } + } + else /* unsigned */ + { + quotient = dividend / divisor; + if(quotient > 0xffffffff) + { + m68k->v_flag = VFLAG_SET; + return; + } + remainder = dividend % divisor; + } + } + else /* 32 bit */ + { + dividend = REG_D[(word2 >> 12) & 7]; + if(BIT_B(word2)) /* signed */ + { + quotient = (UINT64)((INT64)((INT32)dividend) / (INT64)((INT32)divisor)); + remainder = (UINT64)((INT64)((INT32)dividend) % (INT64)((INT32)divisor)); + } + else /* unsigned */ + { + quotient = dividend / divisor; + remainder = dividend % divisor; + } + } + + REG_D[word2 & 7] = remainder; + REG_D[(word2 >> 12) & 7] = quotient; + + m68k->n_flag = NFLAG_32(quotient); + m68k->not_z_flag = quotient; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + return; + } + m68ki_exception_trap(m68k, EXCEPTION_ZERO_DIVIDE); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_divl_32_di(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT64 divisor = OPER_AY_DI_32(m68k); + UINT64 dividend = 0; + UINT64 quotient = 0; + UINT64 remainder = 0; + + if(divisor != 0) + { + if(BIT_A(word2)) /* 64 bit */ + { + dividend = REG_D[word2 & 7]; + dividend <<= 32; + dividend |= REG_D[(word2 >> 12) & 7]; + + if(BIT_B(word2)) /* signed */ + { + quotient = (UINT64)((INT64)dividend / (INT64)((INT32)divisor)); + remainder = (UINT64)((INT64)dividend % (INT64)((INT32)divisor)); + if((INT64)quotient != (INT64)((INT32)quotient)) + { + m68k->v_flag = VFLAG_SET; + return; + } + } + else /* unsigned */ + { + quotient = dividend / divisor; + if(quotient > 0xffffffff) + { + m68k->v_flag = VFLAG_SET; + return; + } + remainder = dividend % divisor; + } + } + else /* 32 bit */ + { + dividend = REG_D[(word2 >> 12) & 7]; + if(BIT_B(word2)) /* signed */ + { + quotient = (UINT64)((INT64)((INT32)dividend) / (INT64)((INT32)divisor)); + remainder = (UINT64)((INT64)((INT32)dividend) % (INT64)((INT32)divisor)); + } + else /* unsigned */ + { + quotient = dividend / divisor; + remainder = dividend % divisor; + } + } + + REG_D[word2 & 7] = remainder; + REG_D[(word2 >> 12) & 7] = quotient; + + m68k->n_flag = NFLAG_32(quotient); + m68k->not_z_flag = quotient; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + return; + } + m68ki_exception_trap(m68k, EXCEPTION_ZERO_DIVIDE); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_divl_32_ix(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT64 divisor = OPER_AY_IX_32(m68k); + UINT64 dividend = 0; + UINT64 quotient = 0; + UINT64 remainder = 0; + + if(divisor != 0) + { + if(BIT_A(word2)) /* 64 bit */ + { + dividend = REG_D[word2 & 7]; + dividend <<= 32; + dividend |= REG_D[(word2 >> 12) & 7]; + + if(BIT_B(word2)) /* signed */ + { + quotient = (UINT64)((INT64)dividend / (INT64)((INT32)divisor)); + remainder = (UINT64)((INT64)dividend % (INT64)((INT32)divisor)); + if((INT64)quotient != (INT64)((INT32)quotient)) + { + m68k->v_flag = VFLAG_SET; + return; + } + } + else /* unsigned */ + { + quotient = dividend / divisor; + if(quotient > 0xffffffff) + { + m68k->v_flag = VFLAG_SET; + return; + } + remainder = dividend % divisor; + } + } + else /* 32 bit */ + { + dividend = REG_D[(word2 >> 12) & 7]; + if(BIT_B(word2)) /* signed */ + { + quotient = (UINT64)((INT64)((INT32)dividend) / (INT64)((INT32)divisor)); + remainder = (UINT64)((INT64)((INT32)dividend) % (INT64)((INT32)divisor)); + } + else /* unsigned */ + { + quotient = dividend / divisor; + remainder = dividend % divisor; + } + } + + REG_D[word2 & 7] = remainder; + REG_D[(word2 >> 12) & 7] = quotient; + + m68k->n_flag = NFLAG_32(quotient); + m68k->not_z_flag = quotient; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + return; + } + m68ki_exception_trap(m68k, EXCEPTION_ZERO_DIVIDE); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_divl_32_aw(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT64 divisor = OPER_AW_32(m68k); + UINT64 dividend = 0; + UINT64 quotient = 0; + UINT64 remainder = 0; + + if(divisor != 0) + { + if(BIT_A(word2)) /* 64 bit */ + { + dividend = REG_D[word2 & 7]; + dividend <<= 32; + dividend |= REG_D[(word2 >> 12) & 7]; + + if(BIT_B(word2)) /* signed */ + { + quotient = (UINT64)((INT64)dividend / (INT64)((INT32)divisor)); + remainder = (UINT64)((INT64)dividend % (INT64)((INT32)divisor)); + if((INT64)quotient != (INT64)((INT32)quotient)) + { + m68k->v_flag = VFLAG_SET; + return; + } + } + else /* unsigned */ + { + quotient = dividend / divisor; + if(quotient > 0xffffffff) + { + m68k->v_flag = VFLAG_SET; + return; + } + remainder = dividend % divisor; + } + } + else /* 32 bit */ + { + dividend = REG_D[(word2 >> 12) & 7]; + if(BIT_B(word2)) /* signed */ + { + quotient = (UINT64)((INT64)((INT32)dividend) / (INT64)((INT32)divisor)); + remainder = (UINT64)((INT64)((INT32)dividend) % (INT64)((INT32)divisor)); + } + else /* unsigned */ + { + quotient = dividend / divisor; + remainder = dividend % divisor; + } + } + + REG_D[word2 & 7] = remainder; + REG_D[(word2 >> 12) & 7] = quotient; + + m68k->n_flag = NFLAG_32(quotient); + m68k->not_z_flag = quotient; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + return; + } + m68ki_exception_trap(m68k, EXCEPTION_ZERO_DIVIDE); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_divl_32_al(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT64 divisor = OPER_AL_32(m68k); + UINT64 dividend = 0; + UINT64 quotient = 0; + UINT64 remainder = 0; + + if(divisor != 0) + { + if(BIT_A(word2)) /* 64 bit */ + { + dividend = REG_D[word2 & 7]; + dividend <<= 32; + dividend |= REG_D[(word2 >> 12) & 7]; + + if(BIT_B(word2)) /* signed */ + { + quotient = (UINT64)((INT64)dividend / (INT64)((INT32)divisor)); + remainder = (UINT64)((INT64)dividend % (INT64)((INT32)divisor)); + if((INT64)quotient != (INT64)((INT32)quotient)) + { + m68k->v_flag = VFLAG_SET; + return; + } + } + else /* unsigned */ + { + quotient = dividend / divisor; + if(quotient > 0xffffffff) + { + m68k->v_flag = VFLAG_SET; + return; + } + remainder = dividend % divisor; + } + } + else /* 32 bit */ + { + dividend = REG_D[(word2 >> 12) & 7]; + if(BIT_B(word2)) /* signed */ + { + quotient = (UINT64)((INT64)((INT32)dividend) / (INT64)((INT32)divisor)); + remainder = (UINT64)((INT64)((INT32)dividend) % (INT64)((INT32)divisor)); + } + else /* unsigned */ + { + quotient = dividend / divisor; + remainder = dividend % divisor; + } + } + + REG_D[word2 & 7] = remainder; + REG_D[(word2 >> 12) & 7] = quotient; + + m68k->n_flag = NFLAG_32(quotient); + m68k->not_z_flag = quotient; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + return; + } + m68ki_exception_trap(m68k, EXCEPTION_ZERO_DIVIDE); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_divl_32_pcdi(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT64 divisor = OPER_PCDI_32(m68k); + UINT64 dividend = 0; + UINT64 quotient = 0; + UINT64 remainder = 0; + + if(divisor != 0) + { + if(BIT_A(word2)) /* 64 bit */ + { + dividend = REG_D[word2 & 7]; + dividend <<= 32; + dividend |= REG_D[(word2 >> 12) & 7]; + + if(BIT_B(word2)) /* signed */ + { + quotient = (UINT64)((INT64)dividend / (INT64)((INT32)divisor)); + remainder = (UINT64)((INT64)dividend % (INT64)((INT32)divisor)); + if((INT64)quotient != (INT64)((INT32)quotient)) + { + m68k->v_flag = VFLAG_SET; + return; + } + } + else /* unsigned */ + { + quotient = dividend / divisor; + if(quotient > 0xffffffff) + { + m68k->v_flag = VFLAG_SET; + return; + } + remainder = dividend % divisor; + } + } + else /* 32 bit */ + { + dividend = REG_D[(word2 >> 12) & 7]; + if(BIT_B(word2)) /* signed */ + { + quotient = (UINT64)((INT64)((INT32)dividend) / (INT64)((INT32)divisor)); + remainder = (UINT64)((INT64)((INT32)dividend) % (INT64)((INT32)divisor)); + } + else /* unsigned */ + { + quotient = dividend / divisor; + remainder = dividend % divisor; + } + } + + REG_D[word2 & 7] = remainder; + REG_D[(word2 >> 12) & 7] = quotient; + + m68k->n_flag = NFLAG_32(quotient); + m68k->not_z_flag = quotient; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + return; + } + m68ki_exception_trap(m68k, EXCEPTION_ZERO_DIVIDE); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_divl_32_pcix(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT64 divisor = OPER_PCIX_32(m68k); + UINT64 dividend = 0; + UINT64 quotient = 0; + UINT64 remainder = 0; + + if(divisor != 0) + { + if(BIT_A(word2)) /* 64 bit */ + { + dividend = REG_D[word2 & 7]; + dividend <<= 32; + dividend |= REG_D[(word2 >> 12) & 7]; + + if(BIT_B(word2)) /* signed */ + { + quotient = (UINT64)((INT64)dividend / (INT64)((INT32)divisor)); + remainder = (UINT64)((INT64)dividend % (INT64)((INT32)divisor)); + if((INT64)quotient != (INT64)((INT32)quotient)) + { + m68k->v_flag = VFLAG_SET; + return; + } + } + else /* unsigned */ + { + quotient = dividend / divisor; + if(quotient > 0xffffffff) + { + m68k->v_flag = VFLAG_SET; + return; + } + remainder = dividend % divisor; + } + } + else /* 32 bit */ + { + dividend = REG_D[(word2 >> 12) & 7]; + if(BIT_B(word2)) /* signed */ + { + quotient = (UINT64)((INT64)((INT32)dividend) / (INT64)((INT32)divisor)); + remainder = (UINT64)((INT64)((INT32)dividend) % (INT64)((INT32)divisor)); + } + else /* unsigned */ + { + quotient = dividend / divisor; + remainder = dividend % divisor; + } + } + + REG_D[word2 & 7] = remainder; + REG_D[(word2 >> 12) & 7] = quotient; + + m68k->n_flag = NFLAG_32(quotient); + m68k->not_z_flag = quotient; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + return; + } + m68ki_exception_trap(m68k, EXCEPTION_ZERO_DIVIDE); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_divl_32_i(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT64 divisor = OPER_I_32(m68k); + UINT64 dividend = 0; + UINT64 quotient = 0; + UINT64 remainder = 0; + + if(divisor != 0) + { + if(BIT_A(word2)) /* 64 bit */ + { + dividend = REG_D[word2 & 7]; + dividend <<= 32; + dividend |= REG_D[(word2 >> 12) & 7]; + + if(BIT_B(word2)) /* signed */ + { + quotient = (UINT64)((INT64)dividend / (INT64)((INT32)divisor)); + remainder = (UINT64)((INT64)dividend % (INT64)((INT32)divisor)); + if((INT64)quotient != (INT64)((INT32)quotient)) + { + m68k->v_flag = VFLAG_SET; + return; + } + } + else /* unsigned */ + { + quotient = dividend / divisor; + if(quotient > 0xffffffff) + { + m68k->v_flag = VFLAG_SET; + return; + } + remainder = dividend % divisor; + } + } + else /* 32 bit */ + { + dividend = REG_D[(word2 >> 12) & 7]; + if(BIT_B(word2)) /* signed */ + { + quotient = (UINT64)((INT64)((INT32)dividend) / (INT64)((INT32)divisor)); + remainder = (UINT64)((INT64)((INT32)dividend) % (INT64)((INT32)divisor)); + } + else /* unsigned */ + { + quotient = dividend / divisor; + remainder = dividend % divisor; + } + } + + REG_D[word2 & 7] = remainder; + REG_D[(word2 >> 12) & 7] = quotient; + + m68k->n_flag = NFLAG_32(quotient); + m68k->not_z_flag = quotient; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + return; + } + m68ki_exception_trap(m68k, EXCEPTION_ZERO_DIVIDE); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_eor_8_d(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_8(DY ^= MASK_OUT_ABOVE_8(DX)); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_eor_8_ai(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_AI_8(m68k); + UINT32 res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(m68k, ea)); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_eor_8_pi(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PI_8(m68k); + UINT32 res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(m68k, ea)); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_eor_8_pi7(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_A7_PI_8(m68k); + UINT32 res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(m68k, ea)); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_eor_8_pd(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PD_8(m68k); + UINT32 res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(m68k, ea)); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_eor_8_pd7(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_A7_PD_8(m68k); + UINT32 res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(m68k, ea)); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_eor_8_di(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_DI_8(m68k); + UINT32 res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(m68k, ea)); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_eor_8_ix(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_IX_8(m68k); + UINT32 res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(m68k, ea)); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_eor_8_aw(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AW_8(m68k); + UINT32 res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(m68k, ea)); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_eor_8_al(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AL_8(m68k); + UINT32 res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(m68k, ea)); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_eor_16_d(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_16(DY ^= MASK_OUT_ABOVE_16(DX)); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_eor_16_ai(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_AI_16(m68k); + UINT32 res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(m68k, ea)); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_eor_16_pi(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PI_16(m68k); + UINT32 res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(m68k, ea)); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_eor_16_pd(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PD_16(m68k); + UINT32 res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(m68k, ea)); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_eor_16_di(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_DI_16(m68k); + UINT32 res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(m68k, ea)); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_eor_16_ix(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_IX_16(m68k); + UINT32 res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(m68k, ea)); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_eor_16_aw(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AW_16(m68k); + UINT32 res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(m68k, ea)); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_eor_16_al(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AL_16(m68k); + UINT32 res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(m68k, ea)); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_eor_32_d(m68ki_cpu_core *m68k) +{ + UINT32 res = DY ^= DX; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_eor_32_ai(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_AI_32(m68k); + UINT32 res = DX ^ m68ki_read_32(m68k, ea); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_eor_32_pi(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PI_32(m68k); + UINT32 res = DX ^ m68ki_read_32(m68k, ea); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_eor_32_pd(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PD_32(m68k); + UINT32 res = DX ^ m68ki_read_32(m68k, ea); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_eor_32_di(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_DI_32(m68k); + UINT32 res = DX ^ m68ki_read_32(m68k, ea); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_eor_32_ix(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_IX_32(m68k); + UINT32 res = DX ^ m68ki_read_32(m68k, ea); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_eor_32_aw(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AW_32(m68k); + UINT32 res = DX ^ m68ki_read_32(m68k, ea); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_eor_32_al(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AL_32(m68k); + UINT32 res = DX ^ m68ki_read_32(m68k, ea); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_eori_8_d(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_8(DY ^= OPER_I_8(m68k)); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_eori_8_ai(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 ea = EA_AY_AI_8(m68k); + UINT32 res = src ^ m68ki_read_8(m68k, ea); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_eori_8_pi(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 ea = EA_AY_PI_8(m68k); + UINT32 res = src ^ m68ki_read_8(m68k, ea); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_eori_8_pi7(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 ea = EA_A7_PI_8(m68k); + UINT32 res = src ^ m68ki_read_8(m68k, ea); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_eori_8_pd(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 ea = EA_AY_PD_8(m68k); + UINT32 res = src ^ m68ki_read_8(m68k, ea); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_eori_8_pd7(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 ea = EA_A7_PD_8(m68k); + UINT32 res = src ^ m68ki_read_8(m68k, ea); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_eori_8_di(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 ea = EA_AY_DI_8(m68k); + UINT32 res = src ^ m68ki_read_8(m68k, ea); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_eori_8_ix(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 ea = EA_AY_IX_8(m68k); + UINT32 res = src ^ m68ki_read_8(m68k, ea); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_eori_8_aw(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 ea = EA_AW_8(m68k); + UINT32 res = src ^ m68ki_read_8(m68k, ea); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_eori_8_al(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 ea = EA_AL_8(m68k); + UINT32 res = src ^ m68ki_read_8(m68k, ea); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_eori_16_d(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_16(DY ^= OPER_I_16(m68k)); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_eori_16_ai(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_16(m68k); + UINT32 ea = EA_AY_AI_16(m68k); + UINT32 res = src ^ m68ki_read_16(m68k, ea); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_eori_16_pi(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_16(m68k); + UINT32 ea = EA_AY_PI_16(m68k); + UINT32 res = src ^ m68ki_read_16(m68k, ea); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_eori_16_pd(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_16(m68k); + UINT32 ea = EA_AY_PD_16(m68k); + UINT32 res = src ^ m68ki_read_16(m68k, ea); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_eori_16_di(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_16(m68k); + UINT32 ea = EA_AY_DI_16(m68k); + UINT32 res = src ^ m68ki_read_16(m68k, ea); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_eori_16_ix(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_16(m68k); + UINT32 ea = EA_AY_IX_16(m68k); + UINT32 res = src ^ m68ki_read_16(m68k, ea); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_eori_16_aw(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_16(m68k); + UINT32 ea = EA_AW_16(m68k); + UINT32 res = src ^ m68ki_read_16(m68k, ea); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_eori_16_al(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_16(m68k); + UINT32 ea = EA_AL_16(m68k); + UINT32 res = src ^ m68ki_read_16(m68k, ea); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_eori_32_d(m68ki_cpu_core *m68k) +{ + UINT32 res = DY ^= OPER_I_32(m68k); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_eori_32_ai(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_32(m68k); + UINT32 ea = EA_AY_AI_32(m68k); + UINT32 res = src ^ m68ki_read_32(m68k, ea); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_eori_32_pi(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_32(m68k); + UINT32 ea = EA_AY_PI_32(m68k); + UINT32 res = src ^ m68ki_read_32(m68k, ea); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_eori_32_pd(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_32(m68k); + UINT32 ea = EA_AY_PD_32(m68k); + UINT32 res = src ^ m68ki_read_32(m68k, ea); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_eori_32_di(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_32(m68k); + UINT32 ea = EA_AY_DI_32(m68k); + UINT32 res = src ^ m68ki_read_32(m68k, ea); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_eori_32_ix(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_32(m68k); + UINT32 ea = EA_AY_IX_32(m68k); + UINT32 res = src ^ m68ki_read_32(m68k, ea); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_eori_32_aw(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_32(m68k); + UINT32 ea = EA_AW_32(m68k); + UINT32 res = src ^ m68ki_read_32(m68k, ea); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_eori_32_al(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_32(m68k); + UINT32 ea = EA_AL_32(m68k); + UINT32 res = src ^ m68ki_read_32(m68k, ea); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_eori_16_toc(m68ki_cpu_core *m68k) +{ + m68ki_set_ccr(m68k, m68ki_get_ccr(m68k) ^ OPER_I_16(m68k)); +} + + +static void m68k_op_eori_16_tos(m68ki_cpu_core *m68k) +{ + if(m68k->s_flag) + { + UINT32 src = OPER_I_16(m68k); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_set_sr(m68k, m68ki_get_sr(m68k) ^ src); + return; + } + m68ki_exception_privilege_violation(m68k); +} + + +static void m68k_op_exg_32_dd(m68ki_cpu_core *m68k) +{ + UINT32* reg_a = &DX; + UINT32* reg_b = &DY; + UINT32 tmp = *reg_a; + *reg_a = *reg_b; + *reg_b = tmp; +} + + +static void m68k_op_exg_32_aa(m68ki_cpu_core *m68k) +{ + UINT32* reg_a = &AX; + UINT32* reg_b = &AY; + UINT32 tmp = *reg_a; + *reg_a = *reg_b; + *reg_b = tmp; +} + + +static void m68k_op_exg_32_da(m68ki_cpu_core *m68k) +{ + UINT32* reg_a = &DX; + UINT32* reg_b = &AY; + UINT32 tmp = *reg_a; + *reg_a = *reg_b; + *reg_b = tmp; +} + + +static void m68k_op_ext_16(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xff00 : 0); + + m68k->n_flag = NFLAG_16(*r_dst); + m68k->not_z_flag = MASK_OUT_ABOVE_16(*r_dst); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_ext_32(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + + *r_dst = MASK_OUT_ABOVE_16(*r_dst) | (GET_MSB_16(*r_dst) ? 0xffff0000 : 0); + + m68k->n_flag = NFLAG_32(*r_dst); + m68k->not_z_flag = *r_dst; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_extb_32(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32* r_dst = &DY; + + *r_dst = MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xffffff00 : 0); + + m68k->n_flag = NFLAG_32(*r_dst); + m68k->not_z_flag = *r_dst; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_illegal(m68ki_cpu_core *m68k) +{ + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_jmp_32_ai(m68ki_cpu_core *m68k) +{ + m68ki_jump(m68k, EA_AY_AI_32(m68k)); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(REG_PC == REG_PPC && m68k->remaining_cycles > 0) + m68k->remaining_cycles = 0; +} + + +static void m68k_op_jmp_32_di(m68ki_cpu_core *m68k) +{ + m68ki_jump(m68k, EA_AY_DI_32(m68k)); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(REG_PC == REG_PPC && m68k->remaining_cycles > 0) + m68k->remaining_cycles = 0; +} + + +static void m68k_op_jmp_32_ix(m68ki_cpu_core *m68k) +{ + m68ki_jump(m68k, EA_AY_IX_32(m68k)); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(REG_PC == REG_PPC && m68k->remaining_cycles > 0) + m68k->remaining_cycles = 0; +} + + +static void m68k_op_jmp_32_aw(m68ki_cpu_core *m68k) +{ + m68ki_jump(m68k, EA_AW_32(m68k)); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(REG_PC == REG_PPC && m68k->remaining_cycles > 0) + m68k->remaining_cycles = 0; +} + + +static void m68k_op_jmp_32_al(m68ki_cpu_core *m68k) +{ + m68ki_jump(m68k, EA_AL_32(m68k)); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(REG_PC == REG_PPC && m68k->remaining_cycles > 0) + m68k->remaining_cycles = 0; +} + + +static void m68k_op_jmp_32_pcdi(m68ki_cpu_core *m68k) +{ + m68ki_jump(m68k, EA_PCDI_32(m68k)); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(REG_PC == REG_PPC && m68k->remaining_cycles > 0) + m68k->remaining_cycles = 0; +} + + +static void m68k_op_jmp_32_pcix(m68ki_cpu_core *m68k) +{ + m68ki_jump(m68k, EA_PCIX_32(m68k)); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(REG_PC == REG_PPC && m68k->remaining_cycles > 0) + m68k->remaining_cycles = 0; +} + + +static void m68k_op_jsr_32_ai(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_AI_32(m68k); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_push_32(m68k, REG_PC); + m68ki_jump(m68k, ea); +} + + +static void m68k_op_jsr_32_di(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_DI_32(m68k); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_push_32(m68k, REG_PC); + m68ki_jump(m68k, ea); +} + + +static void m68k_op_jsr_32_ix(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_IX_32(m68k); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_push_32(m68k, REG_PC); + m68ki_jump(m68k, ea); +} + + +static void m68k_op_jsr_32_aw(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AW_32(m68k); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_push_32(m68k, REG_PC); + m68ki_jump(m68k, ea); +} + + +static void m68k_op_jsr_32_al(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AL_32(m68k); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_push_32(m68k, REG_PC); + m68ki_jump(m68k, ea); +} + + +static void m68k_op_jsr_32_pcdi(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_PCDI_32(m68k); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_push_32(m68k, REG_PC); + m68ki_jump(m68k, ea); +} + + +static void m68k_op_jsr_32_pcix(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_PCIX_32(m68k); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_push_32(m68k, REG_PC); + m68ki_jump(m68k, ea); +} + + +static void m68k_op_lea_32_ai(m68ki_cpu_core *m68k) +{ + AX = EA_AY_AI_32(m68k); +} + + +static void m68k_op_lea_32_di(m68ki_cpu_core *m68k) +{ + AX = EA_AY_DI_32(m68k); +} + + +static void m68k_op_lea_32_ix(m68ki_cpu_core *m68k) +{ + AX = EA_AY_IX_32(m68k); +} + + +static void m68k_op_lea_32_aw(m68ki_cpu_core *m68k) +{ + AX = EA_AW_32(m68k); +} + + +static void m68k_op_lea_32_al(m68ki_cpu_core *m68k) +{ + AX = EA_AL_32(m68k); +} + + +static void m68k_op_lea_32_pcdi(m68ki_cpu_core *m68k) +{ + AX = EA_PCDI_32(m68k); +} + + +static void m68k_op_lea_32_pcix(m68ki_cpu_core *m68k) +{ + AX = EA_PCIX_32(m68k); +} + + +static void m68k_op_link_16_a7(m68ki_cpu_core *m68k) +{ + REG_A[7] -= 4; + m68ki_write_32(m68k, REG_A[7], REG_A[7]); + REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16(m68k))); +} + + +static void m68k_op_link_16(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &AY; + + m68ki_push_32(m68k, *r_dst); + *r_dst = REG_A[7]; + REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16(m68k))); +} + + +static void m68k_op_link_32_a7(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + REG_A[7] -= 4; + m68ki_write_32(m68k, REG_A[7], REG_A[7]); + REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32(m68k)); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_link_32(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32* r_dst = &AY; + + m68ki_push_32(m68k, *r_dst); + *r_dst = REG_A[7]; + REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32(m68k)); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_lsr_8_s(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 shift = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 src = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = src >> shift; + + if(shift != 0) + m68k->remaining_cycles -= shift<cyc_shift; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + m68k->n_flag = NFLAG_CLEAR; + m68k->not_z_flag = res; + m68k->x_flag = m68k->c_flag = src << (9-shift); + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_lsr_16_s(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 shift = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 src = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = src >> shift; + + if(shift != 0) + m68k->remaining_cycles -= shift<cyc_shift; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + m68k->n_flag = NFLAG_CLEAR; + m68k->not_z_flag = res; + m68k->x_flag = m68k->c_flag = src << (9-shift); + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_lsr_32_s(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 shift = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 src = *r_dst; + UINT32 res = src >> shift; + + if(shift != 0) + m68k->remaining_cycles -= shift<cyc_shift; + + *r_dst = res; + + m68k->n_flag = NFLAG_CLEAR; + m68k->not_z_flag = res; + m68k->x_flag = m68k->c_flag = src << (9-shift); + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_lsr_8_r(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 shift = DX & 0x3f; + UINT32 src = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = src >> shift; + + if(shift != 0) + { + m68k->remaining_cycles -= shift<cyc_shift; + + if(shift <= 8) + { + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + m68k->x_flag = m68k->c_flag = src << (9-shift); + m68k->n_flag = NFLAG_CLEAR; + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + *r_dst &= 0xffffff00; + m68k->x_flag = XFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + m68k->n_flag = NFLAG_CLEAR; + m68k->not_z_flag = ZFLAG_SET; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + m68k->c_flag = CFLAG_CLEAR; + m68k->n_flag = NFLAG_8(src); + m68k->not_z_flag = src; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_lsr_16_r(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 shift = DX & 0x3f; + UINT32 src = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = src >> shift; + + if(shift != 0) + { + m68k->remaining_cycles -= shift<cyc_shift; + + if(shift <= 16) + { + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + m68k->c_flag = m68k->x_flag = (src >> (shift - 1))<<8; + m68k->n_flag = NFLAG_CLEAR; + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + *r_dst &= 0xffff0000; + m68k->x_flag = XFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + m68k->n_flag = NFLAG_CLEAR; + m68k->not_z_flag = ZFLAG_SET; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + m68k->c_flag = CFLAG_CLEAR; + m68k->n_flag = NFLAG_16(src); + m68k->not_z_flag = src; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_lsr_32_r(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 shift = DX & 0x3f; + UINT32 src = *r_dst; + UINT32 res = src >> shift; + + if(shift != 0) + { + m68k->remaining_cycles -= shift<cyc_shift; + + if(shift < 32) + { + *r_dst = res; + m68k->c_flag = m68k->x_flag = (src >> (shift - 1))<<8; + m68k->n_flag = NFLAG_CLEAR; + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + *r_dst = 0; + m68k->x_flag = m68k->c_flag = (shift == 32 ? GET_MSB_32(src)>>23 : 0); + m68k->n_flag = NFLAG_CLEAR; + m68k->not_z_flag = ZFLAG_SET; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + m68k->c_flag = CFLAG_CLEAR; + m68k->n_flag = NFLAG_32(src); + m68k->not_z_flag = src; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_lsr_16_ai(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_AI_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = src >> 1; + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_CLEAR; + m68k->not_z_flag = res; + m68k->c_flag = m68k->x_flag = src << 8; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_lsr_16_pi(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PI_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = src >> 1; + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_CLEAR; + m68k->not_z_flag = res; + m68k->c_flag = m68k->x_flag = src << 8; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_lsr_16_pd(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PD_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = src >> 1; + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_CLEAR; + m68k->not_z_flag = res; + m68k->c_flag = m68k->x_flag = src << 8; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_lsr_16_di(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_DI_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = src >> 1; + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_CLEAR; + m68k->not_z_flag = res; + m68k->c_flag = m68k->x_flag = src << 8; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_lsr_16_ix(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_IX_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = src >> 1; + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_CLEAR; + m68k->not_z_flag = res; + m68k->c_flag = m68k->x_flag = src << 8; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_lsr_16_aw(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AW_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = src >> 1; + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_CLEAR; + m68k->not_z_flag = res; + m68k->c_flag = m68k->x_flag = src << 8; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_lsr_16_al(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AL_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = src >> 1; + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_CLEAR; + m68k->not_z_flag = res; + m68k->c_flag = m68k->x_flag = src << 8; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_lsl_8_s(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 shift = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 src = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = MASK_OUT_ABOVE_8(src << shift); + + if(shift != 0) + m68k->remaining_cycles -= shift<cyc_shift; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->x_flag = m68k->c_flag = src << shift; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_lsl_16_s(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 shift = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 src = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = MASK_OUT_ABOVE_16(src << shift); + + if(shift != 0) + m68k->remaining_cycles -= shift<cyc_shift; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->x_flag = m68k->c_flag = src >> (8-shift); + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_lsl_32_s(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 shift = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 src = *r_dst; + UINT32 res = MASK_OUT_ABOVE_32(src << shift); + + if(shift != 0) + m68k->remaining_cycles -= shift<cyc_shift; + + *r_dst = res; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->x_flag = m68k->c_flag = src >> (24-shift); + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_lsl_8_r(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 shift = DX & 0x3f; + UINT32 src = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = MASK_OUT_ABOVE_8(src << shift); + + if(shift != 0) + { + m68k->remaining_cycles -= shift<cyc_shift; + + if(shift <= 8) + { + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + m68k->x_flag = m68k->c_flag = src << shift; + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + *r_dst &= 0xffffff00; + m68k->x_flag = XFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + m68k->n_flag = NFLAG_CLEAR; + m68k->not_z_flag = ZFLAG_SET; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + m68k->c_flag = CFLAG_CLEAR; + m68k->n_flag = NFLAG_8(src); + m68k->not_z_flag = src; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_lsl_16_r(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 shift = DX & 0x3f; + UINT32 src = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = MASK_OUT_ABOVE_16(src << shift); + + if(shift != 0) + { + m68k->remaining_cycles -= shift<cyc_shift; + + if(shift <= 16) + { + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + m68k->x_flag = m68k->c_flag = (src << shift) >> 8; + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + *r_dst &= 0xffff0000; + m68k->x_flag = XFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + m68k->n_flag = NFLAG_CLEAR; + m68k->not_z_flag = ZFLAG_SET; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + m68k->c_flag = CFLAG_CLEAR; + m68k->n_flag = NFLAG_16(src); + m68k->not_z_flag = src; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_lsl_32_r(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 shift = DX & 0x3f; + UINT32 src = *r_dst; + UINT32 res = MASK_OUT_ABOVE_32(src << shift); + + if(shift != 0) + { + m68k->remaining_cycles -= shift<cyc_shift; + + if(shift < 32) + { + *r_dst = res; + m68k->x_flag = m68k->c_flag = (src >> (32 - shift)) << 8; + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + *r_dst = 0; + m68k->x_flag = m68k->c_flag = ((shift == 32 ? src & 1 : 0))<<8; + m68k->n_flag = NFLAG_CLEAR; + m68k->not_z_flag = ZFLAG_SET; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + m68k->c_flag = CFLAG_CLEAR; + m68k->n_flag = NFLAG_32(src); + m68k->not_z_flag = src; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_lsl_16_ai(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_AI_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = MASK_OUT_ABOVE_16(src << 1); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->x_flag = m68k->c_flag = src >> 7; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_lsl_16_pi(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PI_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = MASK_OUT_ABOVE_16(src << 1); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->x_flag = m68k->c_flag = src >> 7; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_lsl_16_pd(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PD_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = MASK_OUT_ABOVE_16(src << 1); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->x_flag = m68k->c_flag = src >> 7; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_lsl_16_di(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_DI_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = MASK_OUT_ABOVE_16(src << 1); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->x_flag = m68k->c_flag = src >> 7; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_lsl_16_ix(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_IX_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = MASK_OUT_ABOVE_16(src << 1); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->x_flag = m68k->c_flag = src >> 7; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_lsl_16_aw(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AW_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = MASK_OUT_ABOVE_16(src << 1); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->x_flag = m68k->c_flag = src >> 7; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_lsl_16_al(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AL_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = MASK_OUT_ABOVE_16(src << 1); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->x_flag = m68k->c_flag = src >> 7; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_move_8_d_d(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_8(DY); + UINT32* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_d_ai(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_AI_8(m68k); + UINT32* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_d_pi(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PI_8(m68k); + UINT32* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_d_pi7(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_A7_PI_8(m68k); + UINT32* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_d_pd(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PD_8(m68k); + UINT32* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_d_pd7(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_A7_PD_8(m68k); + UINT32* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_d_di(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_DI_8(m68k); + UINT32* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_d_ix(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_IX_8(m68k); + UINT32* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_d_aw(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AW_8(m68k); + UINT32* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_d_al(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AL_8(m68k); + UINT32* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_d_pcdi(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_PCDI_8(m68k); + UINT32* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_d_pcix(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_PCIX_8(m68k); + UINT32* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_d_i(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_I_8(m68k); + UINT32* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_ai_d(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_8(DY); + UINT32 ea = EA_AX_AI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_ai_ai(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_AI_8(m68k); + UINT32 ea = EA_AX_AI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_ai_pi(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PI_8(m68k); + UINT32 ea = EA_AX_AI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_ai_pi7(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_A7_PI_8(m68k); + UINT32 ea = EA_AX_AI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_ai_pd(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PD_8(m68k); + UINT32 ea = EA_AX_AI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_ai_pd7(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_A7_PD_8(m68k); + UINT32 ea = EA_AX_AI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_ai_di(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_DI_8(m68k); + UINT32 ea = EA_AX_AI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_ai_ix(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_IX_8(m68k); + UINT32 ea = EA_AX_AI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_ai_aw(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AW_8(m68k); + UINT32 ea = EA_AX_AI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_ai_al(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AL_8(m68k); + UINT32 ea = EA_AX_AI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_ai_pcdi(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_PCDI_8(m68k); + UINT32 ea = EA_AX_AI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_ai_pcix(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_PCIX_8(m68k); + UINT32 ea = EA_AX_AI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_ai_i(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_I_8(m68k); + UINT32 ea = EA_AX_AI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_pi7_d(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_8(DY); + UINT32 ea = EA_A7_PI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_pi_d(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_8(DY); + UINT32 ea = EA_AX_PI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_pi7_ai(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_AI_8(m68k); + UINT32 ea = EA_A7_PI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_pi7_pi(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PI_8(m68k); + UINT32 ea = EA_A7_PI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_pi7_pi7(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_A7_PI_8(m68k); + UINT32 ea = EA_A7_PI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_pi7_pd(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PD_8(m68k); + UINT32 ea = EA_A7_PI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_pi7_pd7(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_A7_PD_8(m68k); + UINT32 ea = EA_A7_PI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_pi7_di(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_DI_8(m68k); + UINT32 ea = EA_A7_PI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_pi7_ix(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_IX_8(m68k); + UINT32 ea = EA_A7_PI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_pi7_aw(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AW_8(m68k); + UINT32 ea = EA_A7_PI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_pi7_al(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AL_8(m68k); + UINT32 ea = EA_A7_PI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_pi7_pcdi(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_PCDI_8(m68k); + UINT32 ea = EA_A7_PI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_pi7_pcix(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_PCIX_8(m68k); + UINT32 ea = EA_A7_PI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_pi7_i(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_I_8(m68k); + UINT32 ea = EA_A7_PI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_pi_ai(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_AI_8(m68k); + UINT32 ea = EA_AX_PI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_pi_pi(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PI_8(m68k); + UINT32 ea = EA_AX_PI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_pi_pi7(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_A7_PI_8(m68k); + UINT32 ea = EA_AX_PI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_pi_pd(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PD_8(m68k); + UINT32 ea = EA_AX_PI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_pi_pd7(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_A7_PD_8(m68k); + UINT32 ea = EA_AX_PI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_pi_di(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_DI_8(m68k); + UINT32 ea = EA_AX_PI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_pi_ix(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_IX_8(m68k); + UINT32 ea = EA_AX_PI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_pi_aw(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AW_8(m68k); + UINT32 ea = EA_AX_PI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_pi_al(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AL_8(m68k); + UINT32 ea = EA_AX_PI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_pi_pcdi(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_PCDI_8(m68k); + UINT32 ea = EA_AX_PI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_pi_pcix(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_PCIX_8(m68k); + UINT32 ea = EA_AX_PI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_pi_i(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_I_8(m68k); + UINT32 ea = EA_AX_PI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_pd7_d(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_8(DY); + UINT32 ea = EA_A7_PD_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_pd_d(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_8(DY); + UINT32 ea = EA_AX_PD_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_pd7_ai(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_AI_8(m68k); + UINT32 ea = EA_A7_PD_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_pd7_pi(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PI_8(m68k); + UINT32 ea = EA_A7_PD_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_pd7_pi7(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_A7_PI_8(m68k); + UINT32 ea = EA_A7_PD_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_pd7_pd(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PD_8(m68k); + UINT32 ea = EA_A7_PD_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_pd7_pd7(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_A7_PD_8(m68k); + UINT32 ea = EA_A7_PD_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_pd7_di(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_DI_8(m68k); + UINT32 ea = EA_A7_PD_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_pd7_ix(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_IX_8(m68k); + UINT32 ea = EA_A7_PD_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_pd7_aw(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AW_8(m68k); + UINT32 ea = EA_A7_PD_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_pd7_al(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AL_8(m68k); + UINT32 ea = EA_A7_PD_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_pd7_pcdi(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_PCDI_8(m68k); + UINT32 ea = EA_A7_PD_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_pd7_pcix(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_PCIX_8(m68k); + UINT32 ea = EA_A7_PD_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_pd7_i(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_I_8(m68k); + UINT32 ea = EA_A7_PD_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_pd_ai(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_AI_8(m68k); + UINT32 ea = EA_AX_PD_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_pd_pi(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PI_8(m68k); + UINT32 ea = EA_AX_PD_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_pd_pi7(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_A7_PI_8(m68k); + UINT32 ea = EA_AX_PD_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_pd_pd(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PD_8(m68k); + UINT32 ea = EA_AX_PD_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_pd_pd7(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_A7_PD_8(m68k); + UINT32 ea = EA_AX_PD_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_pd_di(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_DI_8(m68k); + UINT32 ea = EA_AX_PD_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_pd_ix(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_IX_8(m68k); + UINT32 ea = EA_AX_PD_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_pd_aw(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AW_8(m68k); + UINT32 ea = EA_AX_PD_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_pd_al(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AL_8(m68k); + UINT32 ea = EA_AX_PD_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_pd_pcdi(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_PCDI_8(m68k); + UINT32 ea = EA_AX_PD_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_pd_pcix(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_PCIX_8(m68k); + UINT32 ea = EA_AX_PD_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_pd_i(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_I_8(m68k); + UINT32 ea = EA_AX_PD_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_di_d(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_8(DY); + UINT32 ea = EA_AX_DI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_di_ai(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_AI_8(m68k); + UINT32 ea = EA_AX_DI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_di_pi(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PI_8(m68k); + UINT32 ea = EA_AX_DI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_di_pi7(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_A7_PI_8(m68k); + UINT32 ea = EA_AX_DI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_di_pd(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PD_8(m68k); + UINT32 ea = EA_AX_DI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_di_pd7(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_A7_PD_8(m68k); + UINT32 ea = EA_AX_DI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_di_di(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_DI_8(m68k); + UINT32 ea = EA_AX_DI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_di_ix(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_IX_8(m68k); + UINT32 ea = EA_AX_DI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_di_aw(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AW_8(m68k); + UINT32 ea = EA_AX_DI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_di_al(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AL_8(m68k); + UINT32 ea = EA_AX_DI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_di_pcdi(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_PCDI_8(m68k); + UINT32 ea = EA_AX_DI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_di_pcix(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_PCIX_8(m68k); + UINT32 ea = EA_AX_DI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_di_i(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_I_8(m68k); + UINT32 ea = EA_AX_DI_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_ix_d(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_8(DY); + UINT32 ea = EA_AX_IX_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_ix_ai(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_AI_8(m68k); + UINT32 ea = EA_AX_IX_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_ix_pi(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PI_8(m68k); + UINT32 ea = EA_AX_IX_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_ix_pi7(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_A7_PI_8(m68k); + UINT32 ea = EA_AX_IX_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_ix_pd(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PD_8(m68k); + UINT32 ea = EA_AX_IX_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_ix_pd7(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_A7_PD_8(m68k); + UINT32 ea = EA_AX_IX_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_ix_di(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_DI_8(m68k); + UINT32 ea = EA_AX_IX_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_ix_ix(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_IX_8(m68k); + UINT32 ea = EA_AX_IX_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_ix_aw(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AW_8(m68k); + UINT32 ea = EA_AX_IX_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_ix_al(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AL_8(m68k); + UINT32 ea = EA_AX_IX_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_ix_pcdi(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_PCDI_8(m68k); + UINT32 ea = EA_AX_IX_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_ix_pcix(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_PCIX_8(m68k); + UINT32 ea = EA_AX_IX_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_ix_i(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_I_8(m68k); + UINT32 ea = EA_AX_IX_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_aw_d(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_8(DY); + UINT32 ea = EA_AW_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_aw_ai(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_AI_8(m68k); + UINT32 ea = EA_AW_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_aw_pi(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PI_8(m68k); + UINT32 ea = EA_AW_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_aw_pi7(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_A7_PI_8(m68k); + UINT32 ea = EA_AW_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_aw_pd(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PD_8(m68k); + UINT32 ea = EA_AW_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_aw_pd7(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_A7_PD_8(m68k); + UINT32 ea = EA_AW_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_aw_di(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_DI_8(m68k); + UINT32 ea = EA_AW_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_aw_ix(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_IX_8(m68k); + UINT32 ea = EA_AW_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_aw_aw(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AW_8(m68k); + UINT32 ea = EA_AW_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_aw_al(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AL_8(m68k); + UINT32 ea = EA_AW_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_aw_pcdi(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_PCDI_8(m68k); + UINT32 ea = EA_AW_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_aw_pcix(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_PCIX_8(m68k); + UINT32 ea = EA_AW_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_aw_i(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_I_8(m68k); + UINT32 ea = EA_AW_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_al_d(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_8(DY); + UINT32 ea = EA_AL_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_al_ai(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_AI_8(m68k); + UINT32 ea = EA_AL_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_al_pi(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PI_8(m68k); + UINT32 ea = EA_AL_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_al_pi7(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_A7_PI_8(m68k); + UINT32 ea = EA_AL_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_al_pd(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PD_8(m68k); + UINT32 ea = EA_AL_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_al_pd7(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_A7_PD_8(m68k); + UINT32 ea = EA_AL_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_al_di(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_DI_8(m68k); + UINT32 ea = EA_AL_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_al_ix(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_IX_8(m68k); + UINT32 ea = EA_AL_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_al_aw(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AW_8(m68k); + UINT32 ea = EA_AL_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_al_al(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AL_8(m68k); + UINT32 ea = EA_AL_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_al_pcdi(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_PCDI_8(m68k); + UINT32 ea = EA_AL_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_al_pcix(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_PCIX_8(m68k); + UINT32 ea = EA_AL_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_8_al_i(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_I_8(m68k); + UINT32 ea = EA_AL_8(m68k); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_d_d(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_16(DY); + UINT32* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_d_a(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_16(AY); + UINT32* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_d_ai(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_AI_16(m68k); + UINT32* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_d_pi(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PI_16(m68k); + UINT32* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_d_pd(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PD_16(m68k); + UINT32* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_d_di(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_DI_16(m68k); + UINT32* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_d_ix(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_IX_16(m68k); + UINT32* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_d_aw(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AW_16(m68k); + UINT32* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_d_al(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AL_16(m68k); + UINT32* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_d_pcdi(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_PCDI_16(m68k); + UINT32* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_d_pcix(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_PCIX_16(m68k); + UINT32* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_d_i(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_I_16(m68k); + UINT32* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_ai_d(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_16(DY); + UINT32 ea = EA_AX_AI_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_ai_a(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_16(AY); + UINT32 ea = EA_AX_AI_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_ai_ai(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_AI_16(m68k); + UINT32 ea = EA_AX_AI_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_ai_pi(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PI_16(m68k); + UINT32 ea = EA_AX_AI_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_ai_pd(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PD_16(m68k); + UINT32 ea = EA_AX_AI_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_ai_di(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_DI_16(m68k); + UINT32 ea = EA_AX_AI_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_ai_ix(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_IX_16(m68k); + UINT32 ea = EA_AX_AI_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_ai_aw(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AW_16(m68k); + UINT32 ea = EA_AX_AI_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_ai_al(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AL_16(m68k); + UINT32 ea = EA_AX_AI_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_ai_pcdi(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_PCDI_16(m68k); + UINT32 ea = EA_AX_AI_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_ai_pcix(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_PCIX_16(m68k); + UINT32 ea = EA_AX_AI_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_ai_i(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_I_16(m68k); + UINT32 ea = EA_AX_AI_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_pi_d(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_16(DY); + UINT32 ea = EA_AX_PI_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_pi_a(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_16(AY); + UINT32 ea = EA_AX_PI_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_pi_ai(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_AI_16(m68k); + UINT32 ea = EA_AX_PI_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_pi_pi(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PI_16(m68k); + UINT32 ea = EA_AX_PI_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_pi_pd(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PD_16(m68k); + UINT32 ea = EA_AX_PI_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_pi_di(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_DI_16(m68k); + UINT32 ea = EA_AX_PI_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_pi_ix(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_IX_16(m68k); + UINT32 ea = EA_AX_PI_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_pi_aw(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AW_16(m68k); + UINT32 ea = EA_AX_PI_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_pi_al(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AL_16(m68k); + UINT32 ea = EA_AX_PI_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_pi_pcdi(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_PCDI_16(m68k); + UINT32 ea = EA_AX_PI_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_pi_pcix(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_PCIX_16(m68k); + UINT32 ea = EA_AX_PI_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_pi_i(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_I_16(m68k); + UINT32 ea = EA_AX_PI_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_pd_d(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_16(DY); + UINT32 ea = EA_AX_PD_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_pd_a(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_16(AY); + UINT32 ea = EA_AX_PD_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_pd_ai(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_AI_16(m68k); + UINT32 ea = EA_AX_PD_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_pd_pi(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PI_16(m68k); + UINT32 ea = EA_AX_PD_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_pd_pd(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PD_16(m68k); + UINT32 ea = EA_AX_PD_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_pd_di(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_DI_16(m68k); + UINT32 ea = EA_AX_PD_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_pd_ix(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_IX_16(m68k); + UINT32 ea = EA_AX_PD_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_pd_aw(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AW_16(m68k); + UINT32 ea = EA_AX_PD_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_pd_al(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AL_16(m68k); + UINT32 ea = EA_AX_PD_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_pd_pcdi(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_PCDI_16(m68k); + UINT32 ea = EA_AX_PD_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_pd_pcix(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_PCIX_16(m68k); + UINT32 ea = EA_AX_PD_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_pd_i(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_I_16(m68k); + UINT32 ea = EA_AX_PD_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_di_d(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_16(DY); + UINT32 ea = EA_AX_DI_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_di_a(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_16(AY); + UINT32 ea = EA_AX_DI_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_di_ai(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_AI_16(m68k); + UINT32 ea = EA_AX_DI_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_di_pi(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PI_16(m68k); + UINT32 ea = EA_AX_DI_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_di_pd(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PD_16(m68k); + UINT32 ea = EA_AX_DI_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_di_di(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_DI_16(m68k); + UINT32 ea = EA_AX_DI_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_di_ix(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_IX_16(m68k); + UINT32 ea = EA_AX_DI_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_di_aw(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AW_16(m68k); + UINT32 ea = EA_AX_DI_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_di_al(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AL_16(m68k); + UINT32 ea = EA_AX_DI_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_di_pcdi(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_PCDI_16(m68k); + UINT32 ea = EA_AX_DI_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_di_pcix(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_PCIX_16(m68k); + UINT32 ea = EA_AX_DI_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_di_i(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_I_16(m68k); + UINT32 ea = EA_AX_DI_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_ix_d(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_16(DY); + UINT32 ea = EA_AX_IX_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_ix_a(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_16(AY); + UINT32 ea = EA_AX_IX_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_ix_ai(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_AI_16(m68k); + UINT32 ea = EA_AX_IX_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_ix_pi(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PI_16(m68k); + UINT32 ea = EA_AX_IX_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_ix_pd(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PD_16(m68k); + UINT32 ea = EA_AX_IX_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_ix_di(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_DI_16(m68k); + UINT32 ea = EA_AX_IX_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_ix_ix(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_IX_16(m68k); + UINT32 ea = EA_AX_IX_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_ix_aw(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AW_16(m68k); + UINT32 ea = EA_AX_IX_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_ix_al(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AL_16(m68k); + UINT32 ea = EA_AX_IX_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_ix_pcdi(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_PCDI_16(m68k); + UINT32 ea = EA_AX_IX_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_ix_pcix(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_PCIX_16(m68k); + UINT32 ea = EA_AX_IX_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_ix_i(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_I_16(m68k); + UINT32 ea = EA_AX_IX_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_aw_d(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_16(DY); + UINT32 ea = EA_AW_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_aw_a(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_16(AY); + UINT32 ea = EA_AW_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_aw_ai(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_AI_16(m68k); + UINT32 ea = EA_AW_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_aw_pi(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PI_16(m68k); + UINT32 ea = EA_AW_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_aw_pd(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PD_16(m68k); + UINT32 ea = EA_AW_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_aw_di(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_DI_16(m68k); + UINT32 ea = EA_AW_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_aw_ix(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_IX_16(m68k); + UINT32 ea = EA_AW_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_aw_aw(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AW_16(m68k); + UINT32 ea = EA_AW_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_aw_al(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AL_16(m68k); + UINT32 ea = EA_AW_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_aw_pcdi(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_PCDI_16(m68k); + UINT32 ea = EA_AW_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_aw_pcix(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_PCIX_16(m68k); + UINT32 ea = EA_AW_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_aw_i(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_I_16(m68k); + UINT32 ea = EA_AW_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_al_d(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_16(DY); + UINT32 ea = EA_AL_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_al_a(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_16(AY); + UINT32 ea = EA_AL_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_al_ai(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_AI_16(m68k); + UINT32 ea = EA_AL_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_al_pi(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PI_16(m68k); + UINT32 ea = EA_AL_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_al_pd(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PD_16(m68k); + UINT32 ea = EA_AL_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_al_di(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_DI_16(m68k); + UINT32 ea = EA_AL_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_al_ix(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_IX_16(m68k); + UINT32 ea = EA_AL_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_al_aw(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AW_16(m68k); + UINT32 ea = EA_AL_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_al_al(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AL_16(m68k); + UINT32 ea = EA_AL_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_al_pcdi(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_PCDI_16(m68k); + UINT32 ea = EA_AL_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_al_pcix(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_PCIX_16(m68k); + UINT32 ea = EA_AL_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_16_al_i(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_I_16(m68k); + UINT32 ea = EA_AL_16(m68k); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_d_d(m68ki_cpu_core *m68k) +{ + UINT32 res = DY; + UINT32* r_dst = &DX; + + *r_dst = res; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_d_a(m68ki_cpu_core *m68k) +{ + UINT32 res = AY; + UINT32* r_dst = &DX; + + *r_dst = res; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_d_ai(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_AI_32(m68k); + UINT32* r_dst = &DX; + + *r_dst = res; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_d_pi(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PI_32(m68k); + UINT32* r_dst = &DX; + + *r_dst = res; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_d_pd(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PD_32(m68k); + UINT32* r_dst = &DX; + + *r_dst = res; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_d_di(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_DI_32(m68k); + UINT32* r_dst = &DX; + + *r_dst = res; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_d_ix(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_IX_32(m68k); + UINT32* r_dst = &DX; + + *r_dst = res; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_d_aw(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AW_32(m68k); + UINT32* r_dst = &DX; + + *r_dst = res; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_d_al(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AL_32(m68k); + UINT32* r_dst = &DX; + + *r_dst = res; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_d_pcdi(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_PCDI_32(m68k); + UINT32* r_dst = &DX; + + *r_dst = res; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_d_pcix(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_PCIX_32(m68k); + UINT32* r_dst = &DX; + + *r_dst = res; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_d_i(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_I_32(m68k); + UINT32* r_dst = &DX; + + *r_dst = res; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_ai_d(m68ki_cpu_core *m68k) +{ + UINT32 res = DY; + UINT32 ea = EA_AX_AI_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_ai_a(m68ki_cpu_core *m68k) +{ + UINT32 res = AY; + UINT32 ea = EA_AX_AI_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_ai_ai(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_AI_32(m68k); + UINT32 ea = EA_AX_AI_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_ai_pi(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PI_32(m68k); + UINT32 ea = EA_AX_AI_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_ai_pd(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PD_32(m68k); + UINT32 ea = EA_AX_AI_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_ai_di(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_DI_32(m68k); + UINT32 ea = EA_AX_AI_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_ai_ix(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_IX_32(m68k); + UINT32 ea = EA_AX_AI_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_ai_aw(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AW_32(m68k); + UINT32 ea = EA_AX_AI_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_ai_al(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AL_32(m68k); + UINT32 ea = EA_AX_AI_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_ai_pcdi(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_PCDI_32(m68k); + UINT32 ea = EA_AX_AI_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_ai_pcix(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_PCIX_32(m68k); + UINT32 ea = EA_AX_AI_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_ai_i(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_I_32(m68k); + UINT32 ea = EA_AX_AI_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_pi_d(m68ki_cpu_core *m68k) +{ + UINT32 res = DY; + UINT32 ea = EA_AX_PI_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_pi_a(m68ki_cpu_core *m68k) +{ + UINT32 res = AY; + UINT32 ea = EA_AX_PI_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_pi_ai(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_AI_32(m68k); + UINT32 ea = EA_AX_PI_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_pi_pi(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PI_32(m68k); + UINT32 ea = EA_AX_PI_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_pi_pd(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PD_32(m68k); + UINT32 ea = EA_AX_PI_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_pi_di(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_DI_32(m68k); + UINT32 ea = EA_AX_PI_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_pi_ix(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_IX_32(m68k); + UINT32 ea = EA_AX_PI_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_pi_aw(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AW_32(m68k); + UINT32 ea = EA_AX_PI_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_pi_al(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AL_32(m68k); + UINT32 ea = EA_AX_PI_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_pi_pcdi(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_PCDI_32(m68k); + UINT32 ea = EA_AX_PI_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_pi_pcix(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_PCIX_32(m68k); + UINT32 ea = EA_AX_PI_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_pi_i(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_I_32(m68k); + UINT32 ea = EA_AX_PI_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_pd_d(m68ki_cpu_core *m68k) +{ + UINT32 res = DY; + UINT32 ea = EA_AX_PD_32(m68k); + + m68ki_write_16(m68k, ea+2, res & 0xFFFF ); + m68ki_write_16(m68k, ea, (res >> 16) & 0xFFFF ); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_pd_a(m68ki_cpu_core *m68k) +{ + UINT32 res = AY; + UINT32 ea = EA_AX_PD_32(m68k); + + m68ki_write_16(m68k, ea+2, res & 0xFFFF ); + m68ki_write_16(m68k, ea, (res >> 16) & 0xFFFF ); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_pd_ai(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_AI_32(m68k); + UINT32 ea = EA_AX_PD_32(m68k); + + m68ki_write_16(m68k, ea+2, res & 0xFFFF ); + m68ki_write_16(m68k, ea, (res >> 16) & 0xFFFF ); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_pd_pi(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PI_32(m68k); + UINT32 ea = EA_AX_PD_32(m68k); + + m68ki_write_16(m68k, ea+2, res & 0xFFFF ); + m68ki_write_16(m68k, ea, (res >> 16) & 0xFFFF ); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_pd_pd(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PD_32(m68k); + UINT32 ea = EA_AX_PD_32(m68k); + + m68ki_write_16(m68k, ea+2, res & 0xFFFF ); + m68ki_write_16(m68k, ea, (res >> 16) & 0xFFFF ); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_pd_di(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_DI_32(m68k); + UINT32 ea = EA_AX_PD_32(m68k); + + m68ki_write_16(m68k, ea+2, res & 0xFFFF ); + m68ki_write_16(m68k, ea, (res >> 16) & 0xFFFF ); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_pd_ix(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_IX_32(m68k); + UINT32 ea = EA_AX_PD_32(m68k); + + m68ki_write_16(m68k, ea+2, res & 0xFFFF ); + m68ki_write_16(m68k, ea, (res >> 16) & 0xFFFF ); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_pd_aw(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AW_32(m68k); + UINT32 ea = EA_AX_PD_32(m68k); + + m68ki_write_16(m68k, ea+2, res & 0xFFFF ); + m68ki_write_16(m68k, ea, (res >> 16) & 0xFFFF ); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_pd_al(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AL_32(m68k); + UINT32 ea = EA_AX_PD_32(m68k); + + m68ki_write_16(m68k, ea+2, res & 0xFFFF ); + m68ki_write_16(m68k, ea, (res >> 16) & 0xFFFF ); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_pd_pcdi(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_PCDI_32(m68k); + UINT32 ea = EA_AX_PD_32(m68k); + + m68ki_write_16(m68k, ea+2, res & 0xFFFF ); + m68ki_write_16(m68k, ea, (res >> 16) & 0xFFFF ); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_pd_pcix(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_PCIX_32(m68k); + UINT32 ea = EA_AX_PD_32(m68k); + + m68ki_write_16(m68k, ea+2, res & 0xFFFF ); + m68ki_write_16(m68k, ea, (res >> 16) & 0xFFFF ); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_pd_i(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_I_32(m68k); + UINT32 ea = EA_AX_PD_32(m68k); + + m68ki_write_16(m68k, ea+2, res & 0xFFFF ); + m68ki_write_16(m68k, ea, (res >> 16) & 0xFFFF ); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_di_d(m68ki_cpu_core *m68k) +{ + UINT32 res = DY; + UINT32 ea = EA_AX_DI_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_di_a(m68ki_cpu_core *m68k) +{ + UINT32 res = AY; + UINT32 ea = EA_AX_DI_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_di_ai(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_AI_32(m68k); + UINT32 ea = EA_AX_DI_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_di_pi(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PI_32(m68k); + UINT32 ea = EA_AX_DI_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_di_pd(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PD_32(m68k); + UINT32 ea = EA_AX_DI_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_di_di(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_DI_32(m68k); + UINT32 ea = EA_AX_DI_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_di_ix(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_IX_32(m68k); + UINT32 ea = EA_AX_DI_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_di_aw(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AW_32(m68k); + UINT32 ea = EA_AX_DI_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_di_al(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AL_32(m68k); + UINT32 ea = EA_AX_DI_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_di_pcdi(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_PCDI_32(m68k); + UINT32 ea = EA_AX_DI_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_di_pcix(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_PCIX_32(m68k); + UINT32 ea = EA_AX_DI_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_di_i(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_I_32(m68k); + UINT32 ea = EA_AX_DI_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_ix_d(m68ki_cpu_core *m68k) +{ + UINT32 res = DY; + UINT32 ea = EA_AX_IX_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_ix_a(m68ki_cpu_core *m68k) +{ + UINT32 res = AY; + UINT32 ea = EA_AX_IX_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_ix_ai(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_AI_32(m68k); + UINT32 ea = EA_AX_IX_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_ix_pi(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PI_32(m68k); + UINT32 ea = EA_AX_IX_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_ix_pd(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PD_32(m68k); + UINT32 ea = EA_AX_IX_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_ix_di(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_DI_32(m68k); + UINT32 ea = EA_AX_IX_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_ix_ix(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_IX_32(m68k); + UINT32 ea = EA_AX_IX_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_ix_aw(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AW_32(m68k); + UINT32 ea = EA_AX_IX_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_ix_al(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AL_32(m68k); + UINT32 ea = EA_AX_IX_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_ix_pcdi(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_PCDI_32(m68k); + UINT32 ea = EA_AX_IX_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_ix_pcix(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_PCIX_32(m68k); + UINT32 ea = EA_AX_IX_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_ix_i(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_I_32(m68k); + UINT32 ea = EA_AX_IX_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_aw_d(m68ki_cpu_core *m68k) +{ + UINT32 res = DY; + UINT32 ea = EA_AW_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_aw_a(m68ki_cpu_core *m68k) +{ + UINT32 res = AY; + UINT32 ea = EA_AW_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_aw_ai(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_AI_32(m68k); + UINT32 ea = EA_AW_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_aw_pi(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PI_32(m68k); + UINT32 ea = EA_AW_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_aw_pd(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PD_32(m68k); + UINT32 ea = EA_AW_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_aw_di(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_DI_32(m68k); + UINT32 ea = EA_AW_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_aw_ix(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_IX_32(m68k); + UINT32 ea = EA_AW_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_aw_aw(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AW_32(m68k); + UINT32 ea = EA_AW_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_aw_al(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AL_32(m68k); + UINT32 ea = EA_AW_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_aw_pcdi(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_PCDI_32(m68k); + UINT32 ea = EA_AW_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_aw_pcix(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_PCIX_32(m68k); + UINT32 ea = EA_AW_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_aw_i(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_I_32(m68k); + UINT32 ea = EA_AW_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_al_d(m68ki_cpu_core *m68k) +{ + UINT32 res = DY; + UINT32 ea = EA_AL_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_al_a(m68ki_cpu_core *m68k) +{ + UINT32 res = AY; + UINT32 ea = EA_AL_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_al_ai(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_AI_32(m68k); + UINT32 ea = EA_AL_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_al_pi(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PI_32(m68k); + UINT32 ea = EA_AL_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_al_pd(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PD_32(m68k); + UINT32 ea = EA_AL_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_al_di(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_DI_32(m68k); + UINT32 ea = EA_AL_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_al_ix(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_IX_32(m68k); + UINT32 ea = EA_AL_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_al_aw(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AW_32(m68k); + UINT32 ea = EA_AL_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_al_al(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AL_32(m68k); + UINT32 ea = EA_AL_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_al_pcdi(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_PCDI_32(m68k); + UINT32 ea = EA_AL_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_al_pcix(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_PCIX_32(m68k); + UINT32 ea = EA_AL_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move_32_al_i(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_I_32(m68k); + UINT32 ea = EA_AL_32(m68k); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_movea_16_d(m68ki_cpu_core *m68k) +{ + AX = MAKE_INT_16(DY); +} + + +static void m68k_op_movea_16_a(m68ki_cpu_core *m68k) +{ + AX = MAKE_INT_16(AY); +} + + +static void m68k_op_movea_16_ai(m68ki_cpu_core *m68k) +{ + AX = MAKE_INT_16(OPER_AY_AI_16(m68k)); +} + + +static void m68k_op_movea_16_pi(m68ki_cpu_core *m68k) +{ + AX = MAKE_INT_16(OPER_AY_PI_16(m68k)); +} + + +static void m68k_op_movea_16_pd(m68ki_cpu_core *m68k) +{ + AX = MAKE_INT_16(OPER_AY_PD_16(m68k)); +} + + +static void m68k_op_movea_16_di(m68ki_cpu_core *m68k) +{ + AX = MAKE_INT_16(OPER_AY_DI_16(m68k)); +} + + +static void m68k_op_movea_16_ix(m68ki_cpu_core *m68k) +{ + AX = MAKE_INT_16(OPER_AY_IX_16(m68k)); +} + + +static void m68k_op_movea_16_aw(m68ki_cpu_core *m68k) +{ + AX = MAKE_INT_16(OPER_AW_16(m68k)); +} + + +static void m68k_op_movea_16_al(m68ki_cpu_core *m68k) +{ + AX = MAKE_INT_16(OPER_AL_16(m68k)); +} + + +static void m68k_op_movea_16_pcdi(m68ki_cpu_core *m68k) +{ + AX = MAKE_INT_16(OPER_PCDI_16(m68k)); +} + + +static void m68k_op_movea_16_pcix(m68ki_cpu_core *m68k) +{ + AX = MAKE_INT_16(OPER_PCIX_16(m68k)); +} + + +static void m68k_op_movea_16_i(m68ki_cpu_core *m68k) +{ + AX = MAKE_INT_16(OPER_I_16(m68k)); +} + + +static void m68k_op_movea_32_d(m68ki_cpu_core *m68k) +{ + AX = DY; +} + + +static void m68k_op_movea_32_a(m68ki_cpu_core *m68k) +{ + AX = AY; +} + + +static void m68k_op_movea_32_ai(m68ki_cpu_core *m68k) +{ + AX = OPER_AY_AI_32(m68k); +} + + +static void m68k_op_movea_32_pi(m68ki_cpu_core *m68k) +{ + AX = OPER_AY_PI_32(m68k); +} + + +static void m68k_op_movea_32_pd(m68ki_cpu_core *m68k) +{ + AX = OPER_AY_PD_32(m68k); +} + + +static void m68k_op_movea_32_di(m68ki_cpu_core *m68k) +{ + AX = OPER_AY_DI_32(m68k); +} + + +static void m68k_op_movea_32_ix(m68ki_cpu_core *m68k) +{ + AX = OPER_AY_IX_32(m68k); +} + + +static void m68k_op_movea_32_aw(m68ki_cpu_core *m68k) +{ + AX = OPER_AW_32(m68k); +} + + +static void m68k_op_movea_32_al(m68ki_cpu_core *m68k) +{ + AX = OPER_AL_32(m68k); +} + + +static void m68k_op_movea_32_pcdi(m68ki_cpu_core *m68k) +{ + AX = OPER_PCDI_32(m68k); +} + + +static void m68k_op_movea_32_pcix(m68ki_cpu_core *m68k) +{ + AX = OPER_PCIX_32(m68k); +} + + +static void m68k_op_movea_32_i(m68ki_cpu_core *m68k) +{ + AX = OPER_I_32(m68k); +} + + +static void m68k_op_move_16_frc_d(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_010_PLUS(m68k->cpu_type)) + { + DY = MASK_OUT_BELOW_16(DY) | m68ki_get_ccr(m68k); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_move_16_frc_ai(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_010_PLUS(m68k->cpu_type)) + { + m68ki_write_16(m68k, EA_AY_AI_16(m68k), m68ki_get_ccr(m68k)); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_move_16_frc_pi(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_010_PLUS(m68k->cpu_type)) + { + m68ki_write_16(m68k, EA_AY_PI_16(m68k), m68ki_get_ccr(m68k)); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_move_16_frc_pd(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_010_PLUS(m68k->cpu_type)) + { + m68ki_write_16(m68k, EA_AY_PD_16(m68k), m68ki_get_ccr(m68k)); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_move_16_frc_di(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_010_PLUS(m68k->cpu_type)) + { + m68ki_write_16(m68k, EA_AY_DI_16(m68k), m68ki_get_ccr(m68k)); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_move_16_frc_ix(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_010_PLUS(m68k->cpu_type)) + { + m68ki_write_16(m68k, EA_AY_IX_16(m68k), m68ki_get_ccr(m68k)); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_move_16_frc_aw(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_010_PLUS(m68k->cpu_type)) + { + m68ki_write_16(m68k, EA_AW_16(m68k), m68ki_get_ccr(m68k)); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_move_16_frc_al(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_010_PLUS(m68k->cpu_type)) + { + m68ki_write_16(m68k, EA_AL_16(m68k), m68ki_get_ccr(m68k)); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_move_16_toc_d(m68ki_cpu_core *m68k) +{ + m68ki_set_ccr(m68k, DY); +} + + +static void m68k_op_move_16_toc_ai(m68ki_cpu_core *m68k) +{ + m68ki_set_ccr(m68k, OPER_AY_AI_16(m68k)); +} + + +static void m68k_op_move_16_toc_pi(m68ki_cpu_core *m68k) +{ + m68ki_set_ccr(m68k, OPER_AY_PI_16(m68k)); +} + + +static void m68k_op_move_16_toc_pd(m68ki_cpu_core *m68k) +{ + m68ki_set_ccr(m68k, OPER_AY_PD_16(m68k)); +} + + +static void m68k_op_move_16_toc_di(m68ki_cpu_core *m68k) +{ + m68ki_set_ccr(m68k, OPER_AY_DI_16(m68k)); +} + + +static void m68k_op_move_16_toc_ix(m68ki_cpu_core *m68k) +{ + m68ki_set_ccr(m68k, OPER_AY_IX_16(m68k)); +} + + +static void m68k_op_move_16_toc_aw(m68ki_cpu_core *m68k) +{ + m68ki_set_ccr(m68k, OPER_AW_16(m68k)); +} + + +static void m68k_op_move_16_toc_al(m68ki_cpu_core *m68k) +{ + m68ki_set_ccr(m68k, OPER_AL_16(m68k)); +} + + +static void m68k_op_move_16_toc_pcdi(m68ki_cpu_core *m68k) +{ + m68ki_set_ccr(m68k, OPER_PCDI_16(m68k)); +} + + +static void m68k_op_move_16_toc_pcix(m68ki_cpu_core *m68k) +{ + m68ki_set_ccr(m68k, OPER_PCIX_16(m68k)); +} + + +static void m68k_op_move_16_toc_i(m68ki_cpu_core *m68k) +{ + m68ki_set_ccr(m68k, OPER_I_16(m68k)); +} + + +static void m68k_op_move_16_frs_d(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_000(m68k->cpu_type) || m68k->s_flag) /* NS990408 */ + { + DY = MASK_OUT_BELOW_16(DY) | m68ki_get_sr(m68k); + return; + } + m68ki_exception_privilege_violation(m68k); +} + + +static void m68k_op_move_16_frs_ai(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_000(m68k->cpu_type) || m68k->s_flag) /* NS990408 */ + { + UINT32 ea = EA_AY_AI_16(m68k); + m68ki_write_16(m68k, ea, m68ki_get_sr(m68k)); + return; + } + m68ki_exception_privilege_violation(m68k); +} + + +static void m68k_op_move_16_frs_pi(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_000(m68k->cpu_type) || m68k->s_flag) /* NS990408 */ + { + UINT32 ea = EA_AY_PI_16(m68k); + m68ki_write_16(m68k, ea, m68ki_get_sr(m68k)); + return; + } + m68ki_exception_privilege_violation(m68k); +} + + +static void m68k_op_move_16_frs_pd(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_000(m68k->cpu_type) || m68k->s_flag) /* NS990408 */ + { + UINT32 ea = EA_AY_PD_16(m68k); + m68ki_write_16(m68k, ea, m68ki_get_sr(m68k)); + return; + } + m68ki_exception_privilege_violation(m68k); +} + + +static void m68k_op_move_16_frs_di(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_000(m68k->cpu_type) || m68k->s_flag) /* NS990408 */ + { + UINT32 ea = EA_AY_DI_16(m68k); + m68ki_write_16(m68k, ea, m68ki_get_sr(m68k)); + return; + } + m68ki_exception_privilege_violation(m68k); +} + + +static void m68k_op_move_16_frs_ix(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_000(m68k->cpu_type) || m68k->s_flag) /* NS990408 */ + { + UINT32 ea = EA_AY_IX_16(m68k); + m68ki_write_16(m68k, ea, m68ki_get_sr(m68k)); + return; + } + m68ki_exception_privilege_violation(m68k); +} + + +static void m68k_op_move_16_frs_aw(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_000(m68k->cpu_type) || m68k->s_flag) /* NS990408 */ + { + UINT32 ea = EA_AW_16(m68k); + m68ki_write_16(m68k, ea, m68ki_get_sr(m68k)); + return; + } + m68ki_exception_privilege_violation(m68k); +} + + +static void m68k_op_move_16_frs_al(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_000(m68k->cpu_type) || m68k->s_flag) /* NS990408 */ + { + UINT32 ea = EA_AL_16(m68k); + m68ki_write_16(m68k, ea, m68ki_get_sr(m68k)); + return; + } + m68ki_exception_privilege_violation(m68k); +} + + +static void m68k_op_move_16_tos_d(m68ki_cpu_core *m68k) +{ + if(m68k->s_flag) + { + m68ki_set_sr(m68k, DY); + return; + } + m68ki_exception_privilege_violation(m68k); +} + + +static void m68k_op_move_16_tos_ai(m68ki_cpu_core *m68k) +{ + if(m68k->s_flag) + { + UINT32 new_sr = OPER_AY_AI_16(m68k); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_set_sr(m68k, new_sr); + return; + } + m68ki_exception_privilege_violation(m68k); +} + + +static void m68k_op_move_16_tos_pi(m68ki_cpu_core *m68k) +{ + if(m68k->s_flag) + { + UINT32 new_sr = OPER_AY_PI_16(m68k); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_set_sr(m68k, new_sr); + return; + } + m68ki_exception_privilege_violation(m68k); +} + + +static void m68k_op_move_16_tos_pd(m68ki_cpu_core *m68k) +{ + if(m68k->s_flag) + { + UINT32 new_sr = OPER_AY_PD_16(m68k); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_set_sr(m68k, new_sr); + return; + } + m68ki_exception_privilege_violation(m68k); +} + + +static void m68k_op_move_16_tos_di(m68ki_cpu_core *m68k) +{ + if(m68k->s_flag) + { + UINT32 new_sr = OPER_AY_DI_16(m68k); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_set_sr(m68k, new_sr); + return; + } + m68ki_exception_privilege_violation(m68k); +} + + +static void m68k_op_move_16_tos_ix(m68ki_cpu_core *m68k) +{ + if(m68k->s_flag) + { + UINT32 new_sr = OPER_AY_IX_16(m68k); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_set_sr(m68k, new_sr); + return; + } + m68ki_exception_privilege_violation(m68k); +} + + +static void m68k_op_move_16_tos_aw(m68ki_cpu_core *m68k) +{ + if(m68k->s_flag) + { + UINT32 new_sr = OPER_AW_16(m68k); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_set_sr(m68k, new_sr); + return; + } + m68ki_exception_privilege_violation(m68k); +} + + +static void m68k_op_move_16_tos_al(m68ki_cpu_core *m68k) +{ + if(m68k->s_flag) + { + UINT32 new_sr = OPER_AL_16(m68k); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_set_sr(m68k, new_sr); + return; + } + m68ki_exception_privilege_violation(m68k); +} + + +static void m68k_op_move_16_tos_pcdi(m68ki_cpu_core *m68k) +{ + if(m68k->s_flag) + { + UINT32 new_sr = OPER_PCDI_16(m68k); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_set_sr(m68k, new_sr); + return; + } + m68ki_exception_privilege_violation(m68k); +} + + +static void m68k_op_move_16_tos_pcix(m68ki_cpu_core *m68k) +{ + if(m68k->s_flag) + { + UINT32 new_sr = OPER_PCIX_16(m68k); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_set_sr(m68k, new_sr); + return; + } + m68ki_exception_privilege_violation(m68k); +} + + +static void m68k_op_move_16_tos_i(m68ki_cpu_core *m68k) +{ + if(m68k->s_flag) + { + UINT32 new_sr = OPER_I_16(m68k); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_set_sr(m68k, new_sr); + return; + } + m68ki_exception_privilege_violation(m68k); +} + + +static void m68k_op_move_32_fru(m68ki_cpu_core *m68k) +{ + if(m68k->s_flag) + { + AY = REG_USP; + return; + } + m68ki_exception_privilege_violation(m68k); +} + + +static void m68k_op_move_32_tou(m68ki_cpu_core *m68k) +{ + if(m68k->s_flag) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + REG_USP = AY; + return; + } + m68ki_exception_privilege_violation(m68k); +} + + +static void m68k_op_movec_32_cr(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_010_PLUS(m68k->cpu_type)) + { + if(m68k->s_flag) + { + UINT32 word2 = OPER_I_16(m68k); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + switch (word2 & 0xfff) + { + case 0x000: /* SFC */ + REG_DA[(word2 >> 12) & 15] = m68k->sfc; + return; + case 0x001: /* DFC */ + REG_DA[(word2 >> 12) & 15] = m68k->dfc; + return; + case 0x002: /* CACR */ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + REG_DA[(word2 >> 12) & 15] = m68k->cacr; + return; + } + return; + case 0x800: /* USP */ + REG_DA[(word2 >> 12) & 15] = REG_USP; + return; + case 0x801: /* VBR */ + REG_DA[(word2 >> 12) & 15] = m68k->vbr; + return; + case 0x802: /* CAAR */ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + REG_DA[(word2 >> 12) & 15] = m68k->caar; + return; + } + m68ki_exception_illegal(m68k); + break; + case 0x803: /* MSP */ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + REG_DA[(word2 >> 12) & 15] = m68k->m_flag ? REG_SP : REG_MSP; + return; + } + m68ki_exception_illegal(m68k); + return; + case 0x804: /* ISP */ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + REG_DA[(word2 >> 12) & 15] = m68k->m_flag ? REG_ISP : REG_SP; + return; + } + m68ki_exception_illegal(m68k); + return; + case 0x003: /* TC */ + if(CPU_TYPE_IS_040_PLUS(m68k->cpu_type)) + { + /* TODO */ + return; + } + m68ki_exception_illegal(m68k); + return; + case 0x004: /* ITT0 */ + if(CPU_TYPE_IS_040_PLUS(m68k->cpu_type)) + { + /* TODO */ + return; + } + m68ki_exception_illegal(m68k); + return; + case 0x005: /* ITT1 */ + if(CPU_TYPE_IS_040_PLUS(m68k->cpu_type)) + { + /* TODO */ + return; + } + m68ki_exception_illegal(m68k); + return; + case 0x006: /* DTT0 */ + if(CPU_TYPE_IS_040_PLUS(m68k->cpu_type)) + { + /* TODO */ + return; + } + m68ki_exception_illegal(m68k); + return; + case 0x007: /* DTT1 */ + if(CPU_TYPE_IS_040_PLUS(m68k->cpu_type)) + { + /* TODO */ + return; + } + m68ki_exception_illegal(m68k); + return; + case 0x805: /* MMUSR */ + if(CPU_TYPE_IS_040_PLUS(m68k->cpu_type)) + { + /* TODO */ + return; + } + m68ki_exception_illegal(m68k); + return; + case 0x806: /* URP */ + if(CPU_TYPE_IS_040_PLUS(m68k->cpu_type)) + { + /* TODO */ + return; + } + m68ki_exception_illegal(m68k); + return; + case 0x807: /* SRP */ + if(CPU_TYPE_IS_040_PLUS(m68k->cpu_type)) + { + /* TODO */ + return; + } + m68ki_exception_illegal(m68k); + return; + default: + m68ki_exception_illegal(m68k); + return; + } + } + m68ki_exception_privilege_violation(m68k); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_movec_32_rc(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_010_PLUS(m68k->cpu_type)) + { + if(m68k->s_flag) + { + UINT32 word2 = OPER_I_16(m68k); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + switch (word2 & 0xfff) + { + case 0x000: /* SFC */ + m68k->sfc = REG_DA[(word2 >> 12) & 15] & 7; + return; + case 0x001: /* DFC */ + m68k->dfc = REG_DA[(word2 >> 12) & 15] & 7; + return; + case 0x002: /* CACR */ + /* Only EC020 and later have CACR */ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + /* 68030 can write all bits except 5-7, 040 can write all */ + if (CPU_TYPE_IS_040_PLUS(m68k->cpu_type)) + { + m68k->cacr = REG_DA[(word2 >> 12) & 15]; + } + else if (CPU_TYPE_IS_030_PLUS(m68k->cpu_type)) + { + m68k->cacr = REG_DA[(word2 >> 12) & 15] & 0xff1f; + } + else + { + m68k->cacr = REG_DA[(word2 >> 12) & 15] & 0x0f; + } + return; + } + m68ki_exception_illegal(m68k); + return; + case 0x800: /* USP */ + REG_USP = REG_DA[(word2 >> 12) & 15]; + return; + case 0x801: /* VBR */ + m68k->vbr = REG_DA[(word2 >> 12) & 15]; + return; + case 0x802: /* CAAR */ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + m68k->caar = REG_DA[(word2 >> 12) & 15]; + return; + } + m68ki_exception_illegal(m68k); + return; + case 0x803: /* MSP */ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + /* we are in supervisor mode so just check for M flag */ + if(!m68k->m_flag) + { + REG_MSP = REG_DA[(word2 >> 12) & 15]; + return; + } + REG_SP = REG_DA[(word2 >> 12) & 15]; + return; + } + m68ki_exception_illegal(m68k); + return; + case 0x804: /* ISP */ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(!m68k->m_flag) + { + REG_SP = REG_DA[(word2 >> 12) & 15]; + return; + } + REG_ISP = REG_DA[(word2 >> 12) & 15]; + return; + } + m68ki_exception_illegal(m68k); + return; + case 0x003: /* TC */ + if (CPU_TYPE_IS_040_PLUS(m68k->cpu_type)) + { + /* TODO */ + return; + } + m68ki_exception_illegal(m68k); + return; + case 0x004: /* ITT0 */ + if (CPU_TYPE_IS_040_PLUS(m68k->cpu_type)) + { + /* TODO */ + return; + } + m68ki_exception_illegal(m68k); + return; + case 0x005: /* ITT1 */ + if (CPU_TYPE_IS_040_PLUS(m68k->cpu_type)) + { + /* TODO */ + return; + } + m68ki_exception_illegal(m68k); + return; + case 0x006: /* DTT0 */ + if (CPU_TYPE_IS_040_PLUS(m68k->cpu_type)) + { + /* TODO */ + return; + } + m68ki_exception_illegal(m68k); + return; + case 0x007: /* DTT1 */ + if (CPU_TYPE_IS_040_PLUS(m68k->cpu_type)) + { + /* TODO */ + return; + } + m68ki_exception_illegal(m68k); + return; + case 0x805: /* MMUSR */ + if (CPU_TYPE_IS_040_PLUS(m68k->cpu_type)) + { + /* TODO */ + return; + } + m68ki_exception_illegal(m68k); + return; + case 0x806: /* URP */ + if (CPU_TYPE_IS_040_PLUS(m68k->cpu_type)) + { + /* TODO */ + return; + } + m68ki_exception_illegal(m68k); + return; + case 0x807: /* SRP */ + if (CPU_TYPE_IS_040_PLUS(m68k->cpu_type)) + { + /* TODO */ + return; + } + m68ki_exception_illegal(m68k); + return; + default: + m68ki_exception_illegal(m68k); + return; + } + } + m68ki_exception_privilege_violation(m68k); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_movem_16_re_pd(m68ki_cpu_core *m68k) +{ + UINT32 i = 0; + UINT32 register_list = OPER_I_16(m68k); + UINT32 ea = AY; + UINT32 count = 0; + + for(; i < 16; i++) + if(register_list & (1 << i)) + { + ea -= 2; + m68ki_write_16(m68k, ea, MASK_OUT_ABOVE_16(REG_DA[15-i])); + count++; + } + AY = ea; + + m68k->remaining_cycles -= count<cyc_movem_w; +} + + +static void m68k_op_movem_16_re_ai(m68ki_cpu_core *m68k) +{ + UINT32 i = 0; + UINT32 register_list = OPER_I_16(m68k); + UINT32 ea = EA_AY_AI_16(m68k); + UINT32 count = 0; + + for(; i < 16; i++) + if(register_list & (1 << i)) + { + m68ki_write_16(m68k, ea, MASK_OUT_ABOVE_16(REG_DA[i])); + ea += 2; + count++; + } + + m68k->remaining_cycles -= count<cyc_movem_w; +} + + +static void m68k_op_movem_16_re_di(m68ki_cpu_core *m68k) +{ + UINT32 i = 0; + UINT32 register_list = OPER_I_16(m68k); + UINT32 ea = EA_AY_DI_16(m68k); + UINT32 count = 0; + + for(; i < 16; i++) + if(register_list & (1 << i)) + { + m68ki_write_16(m68k, ea, MASK_OUT_ABOVE_16(REG_DA[i])); + ea += 2; + count++; + } + + m68k->remaining_cycles -= count<cyc_movem_w; +} + + +static void m68k_op_movem_16_re_ix(m68ki_cpu_core *m68k) +{ + UINT32 i = 0; + UINT32 register_list = OPER_I_16(m68k); + UINT32 ea = EA_AY_IX_16(m68k); + UINT32 count = 0; + + for(; i < 16; i++) + if(register_list & (1 << i)) + { + m68ki_write_16(m68k, ea, MASK_OUT_ABOVE_16(REG_DA[i])); + ea += 2; + count++; + } + + m68k->remaining_cycles -= count<cyc_movem_w; +} + + +static void m68k_op_movem_16_re_aw(m68ki_cpu_core *m68k) +{ + UINT32 i = 0; + UINT32 register_list = OPER_I_16(m68k); + UINT32 ea = EA_AW_16(m68k); + UINT32 count = 0; + + for(; i < 16; i++) + if(register_list & (1 << i)) + { + m68ki_write_16(m68k, ea, MASK_OUT_ABOVE_16(REG_DA[i])); + ea += 2; + count++; + } + + m68k->remaining_cycles -= count<cyc_movem_w; +} + + +static void m68k_op_movem_16_re_al(m68ki_cpu_core *m68k) +{ + UINT32 i = 0; + UINT32 register_list = OPER_I_16(m68k); + UINT32 ea = EA_AL_16(m68k); + UINT32 count = 0; + + for(; i < 16; i++) + if(register_list & (1 << i)) + { + m68ki_write_16(m68k, ea, MASK_OUT_ABOVE_16(REG_DA[i])); + ea += 2; + count++; + } + + m68k->remaining_cycles -= count<cyc_movem_w; +} + + +static void m68k_op_movem_32_re_pd(m68ki_cpu_core *m68k) +{ + UINT32 i = 0; + UINT32 register_list = OPER_I_16(m68k); + UINT32 ea = AY; + UINT32 count = 0; + + for(; i < 16; i++) + if(register_list & (1 << i)) + { + ea -= 4; + m68ki_write_16(m68k, ea+2, REG_DA[15-i] & 0xFFFF ); + m68ki_write_16(m68k, ea, (REG_DA[15-i] >> 16) & 0xFFFF ); + count++; + } + AY = ea; + + m68k->remaining_cycles -= count<cyc_movem_l; +} + + +static void m68k_op_movem_32_re_ai(m68ki_cpu_core *m68k) +{ + UINT32 i = 0; + UINT32 register_list = OPER_I_16(m68k); + UINT32 ea = EA_AY_AI_32(m68k); + UINT32 count = 0; + + for(; i < 16; i++) + if(register_list & (1 << i)) + { + m68ki_write_32(m68k, ea, REG_DA[i]); + ea += 4; + count++; + } + + m68k->remaining_cycles -= count<cyc_movem_l; +} + + +static void m68k_op_movem_32_re_di(m68ki_cpu_core *m68k) +{ + UINT32 i = 0; + UINT32 register_list = OPER_I_16(m68k); + UINT32 ea = EA_AY_DI_32(m68k); + UINT32 count = 0; + + for(; i < 16; i++) + if(register_list & (1 << i)) + { + m68ki_write_32(m68k, ea, REG_DA[i]); + ea += 4; + count++; + } + + m68k->remaining_cycles -= count<cyc_movem_l; +} + + +static void m68k_op_movem_32_re_ix(m68ki_cpu_core *m68k) +{ + UINT32 i = 0; + UINT32 register_list = OPER_I_16(m68k); + UINT32 ea = EA_AY_IX_32(m68k); + UINT32 count = 0; + + for(; i < 16; i++) + if(register_list & (1 << i)) + { + m68ki_write_32(m68k, ea, REG_DA[i]); + ea += 4; + count++; + } + + m68k->remaining_cycles -= count<cyc_movem_l; +} + + +static void m68k_op_movem_32_re_aw(m68ki_cpu_core *m68k) +{ + UINT32 i = 0; + UINT32 register_list = OPER_I_16(m68k); + UINT32 ea = EA_AW_32(m68k); + UINT32 count = 0; + + for(; i < 16; i++) + if(register_list & (1 << i)) + { + m68ki_write_32(m68k, ea, REG_DA[i]); + ea += 4; + count++; + } + + m68k->remaining_cycles -= count<cyc_movem_l; +} + + +static void m68k_op_movem_32_re_al(m68ki_cpu_core *m68k) +{ + UINT32 i = 0; + UINT32 register_list = OPER_I_16(m68k); + UINT32 ea = EA_AL_32(m68k); + UINT32 count = 0; + + for(; i < 16; i++) + if(register_list & (1 << i)) + { + m68ki_write_32(m68k, ea, REG_DA[i]); + ea += 4; + count++; + } + + m68k->remaining_cycles -= count<cyc_movem_l; +} + + +static void m68k_op_movem_16_er_pi(m68ki_cpu_core *m68k) +{ + UINT32 i = 0; + UINT32 register_list = OPER_I_16(m68k); + UINT32 ea = AY; + UINT32 count = 0; + + for(; i < 16; i++) + if(register_list & (1 << i)) + { + REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(m68k, ea))); + ea += 2; + count++; + } + AY = ea; + + m68k->remaining_cycles -= count<cyc_movem_w; +} + + +static void m68k_op_movem_16_er_pcdi(m68ki_cpu_core *m68k) +{ + UINT32 i = 0; + UINT32 register_list = OPER_I_16(m68k); + UINT32 ea = EA_PCDI_16(m68k); + UINT32 count = 0; + + for(; i < 16; i++) + if(register_list & (1 << i)) + { + REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_pcrel_16(m68k, ea))); + ea += 2; + count++; + } + + m68k->remaining_cycles -= count<cyc_movem_w; +} + + +static void m68k_op_movem_16_er_pcix(m68ki_cpu_core *m68k) +{ + UINT32 i = 0; + UINT32 register_list = OPER_I_16(m68k); + UINT32 ea = EA_PCIX_16(m68k); + UINT32 count = 0; + + for(; i < 16; i++) + if(register_list & (1 << i)) + { + REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_pcrel_16(m68k, ea))); + ea += 2; + count++; + } + + m68k->remaining_cycles -= count<cyc_movem_w; +} + + +static void m68k_op_movem_16_er_ai(m68ki_cpu_core *m68k) +{ + UINT32 i = 0; + UINT32 register_list = OPER_I_16(m68k); + UINT32 ea = EA_AY_AI_16(m68k); + UINT32 count = 0; + + for(; i < 16; i++) + if(register_list & (1 << i)) + { + REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(m68k, ea))); + ea += 2; + count++; + } + + m68k->remaining_cycles -= count<cyc_movem_w; +} + + +static void m68k_op_movem_16_er_di(m68ki_cpu_core *m68k) +{ + UINT32 i = 0; + UINT32 register_list = OPER_I_16(m68k); + UINT32 ea = EA_AY_DI_16(m68k); + UINT32 count = 0; + + for(; i < 16; i++) + if(register_list & (1 << i)) + { + REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(m68k, ea))); + ea += 2; + count++; + } + + m68k->remaining_cycles -= count<cyc_movem_w; +} + + +static void m68k_op_movem_16_er_ix(m68ki_cpu_core *m68k) +{ + UINT32 i = 0; + UINT32 register_list = OPER_I_16(m68k); + UINT32 ea = EA_AY_IX_16(m68k); + UINT32 count = 0; + + for(; i < 16; i++) + if(register_list & (1 << i)) + { + REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(m68k, ea))); + ea += 2; + count++; + } + + m68k->remaining_cycles -= count<cyc_movem_w; +} + + +static void m68k_op_movem_16_er_aw(m68ki_cpu_core *m68k) +{ + UINT32 i = 0; + UINT32 register_list = OPER_I_16(m68k); + UINT32 ea = EA_AW_16(m68k); + UINT32 count = 0; + + for(; i < 16; i++) + if(register_list & (1 << i)) + { + REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(m68k, ea))); + ea += 2; + count++; + } + + m68k->remaining_cycles -= count<cyc_movem_w; +} + + +static void m68k_op_movem_16_er_al(m68ki_cpu_core *m68k) +{ + UINT32 i = 0; + UINT32 register_list = OPER_I_16(m68k); + UINT32 ea = EA_AL_16(m68k); + UINT32 count = 0; + + for(; i < 16; i++) + if(register_list & (1 << i)) + { + REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(m68k, ea))); + ea += 2; + count++; + } + + m68k->remaining_cycles -= count<cyc_movem_w; +} + + +static void m68k_op_movem_32_er_pi(m68ki_cpu_core *m68k) +{ + UINT32 i = 0; + UINT32 register_list = OPER_I_16(m68k); + UINT32 ea = AY; + UINT32 count = 0; + + for(; i < 16; i++) + if(register_list & (1 << i)) + { + REG_DA[i] = m68ki_read_32(m68k, ea); + ea += 4; + count++; + } + AY = ea; + + m68k->remaining_cycles -= count<cyc_movem_l; +} + + +static void m68k_op_movem_32_er_pcdi(m68ki_cpu_core *m68k) +{ + UINT32 i = 0; + UINT32 register_list = OPER_I_16(m68k); + UINT32 ea = EA_PCDI_32(m68k); + UINT32 count = 0; + + for(; i < 16; i++) + if(register_list & (1 << i)) + { + REG_DA[i] = m68ki_read_pcrel_32(m68k, ea); + ea += 4; + count++; + } + + m68k->remaining_cycles -= count<cyc_movem_l; +} + + +static void m68k_op_movem_32_er_pcix(m68ki_cpu_core *m68k) +{ + UINT32 i = 0; + UINT32 register_list = OPER_I_16(m68k); + UINT32 ea = EA_PCIX_32(m68k); + UINT32 count = 0; + + for(; i < 16; i++) + if(register_list & (1 << i)) + { + REG_DA[i] = m68ki_read_pcrel_32(m68k, ea); + ea += 4; + count++; + } + + m68k->remaining_cycles -= count<cyc_movem_l; +} + + +static void m68k_op_movem_32_er_ai(m68ki_cpu_core *m68k) +{ + UINT32 i = 0; + UINT32 register_list = OPER_I_16(m68k); + UINT32 ea = EA_AY_AI_32(m68k); + UINT32 count = 0; + + for(; i < 16; i++) + if(register_list & (1 << i)) + { + REG_DA[i] = m68ki_read_32(m68k, ea); + ea += 4; + count++; + } + + m68k->remaining_cycles -= count<cyc_movem_l; +} + + +static void m68k_op_movem_32_er_di(m68ki_cpu_core *m68k) +{ + UINT32 i = 0; + UINT32 register_list = OPER_I_16(m68k); + UINT32 ea = EA_AY_DI_32(m68k); + UINT32 count = 0; + + for(; i < 16; i++) + if(register_list & (1 << i)) + { + REG_DA[i] = m68ki_read_32(m68k, ea); + ea += 4; + count++; + } + + m68k->remaining_cycles -= count<cyc_movem_l; +} + + +static void m68k_op_movem_32_er_ix(m68ki_cpu_core *m68k) +{ + UINT32 i = 0; + UINT32 register_list = OPER_I_16(m68k); + UINT32 ea = EA_AY_IX_32(m68k); + UINT32 count = 0; + + for(; i < 16; i++) + if(register_list & (1 << i)) + { + REG_DA[i] = m68ki_read_32(m68k, ea); + ea += 4; + count++; + } + + m68k->remaining_cycles -= count<cyc_movem_l; +} + + +static void m68k_op_movem_32_er_aw(m68ki_cpu_core *m68k) +{ + UINT32 i = 0; + UINT32 register_list = OPER_I_16(m68k); + UINT32 ea = EA_AW_32(m68k); + UINT32 count = 0; + + for(; i < 16; i++) + if(register_list & (1 << i)) + { + REG_DA[i] = m68ki_read_32(m68k, ea); + ea += 4; + count++; + } + + m68k->remaining_cycles -= count<cyc_movem_l; +} + + +static void m68k_op_movem_32_er_al(m68ki_cpu_core *m68k) +{ + UINT32 i = 0; + UINT32 register_list = OPER_I_16(m68k); + UINT32 ea = EA_AL_32(m68k); + UINT32 count = 0; + + for(; i < 16; i++) + if(register_list & (1 << i)) + { + REG_DA[i] = m68ki_read_32(m68k, ea); + ea += 4; + count++; + } + + m68k->remaining_cycles -= count<cyc_movem_l; +} + + +static void m68k_op_movep_16_re(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_DI_16(m68k); + UINT32 src = DX; + + m68ki_write_8(m68k, ea, MASK_OUT_ABOVE_8(src >> 8)); + m68ki_write_8(m68k, ea += 2, MASK_OUT_ABOVE_8(src)); +} + + +static void m68k_op_movep_32_re(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_DI_32(m68k); + UINT32 src = DX; + + m68ki_write_8(m68k, ea, MASK_OUT_ABOVE_8(src >> 24)); + m68ki_write_8(m68k, ea += 2, MASK_OUT_ABOVE_8(src >> 16)); + m68ki_write_8(m68k, ea += 2, MASK_OUT_ABOVE_8(src >> 8)); + m68ki_write_8(m68k, ea += 2, MASK_OUT_ABOVE_8(src)); +} + + +static void m68k_op_movep_16_er(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_DI_16(m68k); + UINT32* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | ((m68ki_read_8(m68k, ea) << 8) + m68ki_read_8(m68k, ea + 2)); +} + + +static void m68k_op_movep_32_er(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_DI_32(m68k); + + DX = (m68ki_read_8(m68k, ea) << 24) + (m68ki_read_8(m68k, ea + 2) << 16) + + (m68ki_read_8(m68k, ea + 4) << 8) + m68ki_read_8(m68k, ea + 6); +} + + +static void m68k_op_moves_8_ai(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_010_PLUS(m68k->cpu_type)) + { + if(m68k->s_flag) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 ea = EA_AY_AI_8(m68k); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_8_fc(m68k, ea, m68k->dfc, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15])); + return; + } + if(BIT_F(word2)) /* Memory to address register */ + { + REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(m68k, ea, m68k->sfc)); + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + m68k->remaining_cycles -= 2; + return; + } + /* Memory to data register */ + REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(m68k, ea, m68k->sfc); + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + m68k->remaining_cycles -= 2; + return; + } + m68ki_exception_privilege_violation(m68k); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_moves_8_pi(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_010_PLUS(m68k->cpu_type)) + { + if(m68k->s_flag) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 ea = EA_AY_PI_8(m68k); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_8_fc(m68k, ea, m68k->dfc, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15])); + return; + } + if(BIT_F(word2)) /* Memory to address register */ + { + REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(m68k, ea, m68k->sfc)); + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + m68k->remaining_cycles -= 2; + return; + } + /* Memory to data register */ + REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(m68k, ea, m68k->sfc); + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + m68k->remaining_cycles -= 2; + return; + } + m68ki_exception_privilege_violation(m68k); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_moves_8_pi7(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_010_PLUS(m68k->cpu_type)) + { + if(m68k->s_flag) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 ea = EA_A7_PI_8(m68k); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_8_fc(m68k, ea, m68k->dfc, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15])); + return; + } + if(BIT_F(word2)) /* Memory to address register */ + { + REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(m68k, ea, m68k->sfc)); + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + m68k->remaining_cycles -= 2; + return; + } + /* Memory to data register */ + REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(m68k, ea, m68k->sfc); + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + m68k->remaining_cycles -= 2; + return; + } + m68ki_exception_privilege_violation(m68k); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_moves_8_pd(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_010_PLUS(m68k->cpu_type)) + { + if(m68k->s_flag) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 ea = EA_AY_PD_8(m68k); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_8_fc(m68k, ea, m68k->dfc, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15])); + return; + } + if(BIT_F(word2)) /* Memory to address register */ + { + REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(m68k, ea, m68k->sfc)); + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + m68k->remaining_cycles -= 2; + return; + } + /* Memory to data register */ + REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(m68k, ea, m68k->sfc); + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + m68k->remaining_cycles -= 2; + return; + } + m68ki_exception_privilege_violation(m68k); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_moves_8_pd7(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_010_PLUS(m68k->cpu_type)) + { + if(m68k->s_flag) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 ea = EA_A7_PD_8(m68k); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_8_fc(m68k, ea, m68k->dfc, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15])); + return; + } + if(BIT_F(word2)) /* Memory to address register */ + { + REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(m68k, ea, m68k->sfc)); + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + m68k->remaining_cycles -= 2; + return; + } + /* Memory to data register */ + REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(m68k, ea, m68k->sfc); + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + m68k->remaining_cycles -= 2; + return; + } + m68ki_exception_privilege_violation(m68k); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_moves_8_di(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_010_PLUS(m68k->cpu_type)) + { + if(m68k->s_flag) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 ea = EA_AY_DI_8(m68k); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_8_fc(m68k, ea, m68k->dfc, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15])); + return; + } + if(BIT_F(word2)) /* Memory to address register */ + { + REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(m68k, ea, m68k->sfc)); + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + m68k->remaining_cycles -= 2; + return; + } + /* Memory to data register */ + REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(m68k, ea, m68k->sfc); + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + m68k->remaining_cycles -= 2; + return; + } + m68ki_exception_privilege_violation(m68k); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_moves_8_ix(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_010_PLUS(m68k->cpu_type)) + { + if(m68k->s_flag) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 ea = EA_AY_IX_8(m68k); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_8_fc(m68k, ea, m68k->dfc, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15])); + return; + } + if(BIT_F(word2)) /* Memory to address register */ + { + REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(m68k, ea, m68k->sfc)); + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + m68k->remaining_cycles -= 2; + return; + } + /* Memory to data register */ + REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(m68k, ea, m68k->sfc); + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + m68k->remaining_cycles -= 2; + return; + } + m68ki_exception_privilege_violation(m68k); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_moves_8_aw(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_010_PLUS(m68k->cpu_type)) + { + if(m68k->s_flag) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 ea = EA_AW_8(m68k); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_8_fc(m68k, ea, m68k->dfc, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15])); + return; + } + if(BIT_F(word2)) /* Memory to address register */ + { + REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(m68k, ea, m68k->sfc)); + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + m68k->remaining_cycles -= 2; + return; + } + /* Memory to data register */ + REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(m68k, ea, m68k->sfc); + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + m68k->remaining_cycles -= 2; + return; + } + m68ki_exception_privilege_violation(m68k); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_moves_8_al(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_010_PLUS(m68k->cpu_type)) + { + if(m68k->s_flag) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 ea = EA_AL_8(m68k); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_8_fc(m68k, ea, m68k->dfc, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15])); + return; + } + if(BIT_F(word2)) /* Memory to address register */ + { + REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(m68k, ea, m68k->sfc)); + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + m68k->remaining_cycles -= 2; + return; + } + /* Memory to data register */ + REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(m68k, ea, m68k->sfc); + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + m68k->remaining_cycles -= 2; + return; + } + m68ki_exception_privilege_violation(m68k); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_moves_16_ai(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_010_PLUS(m68k->cpu_type)) + { + if(m68k->s_flag) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 ea = EA_AY_AI_16(m68k); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_16_fc(m68k, ea, m68k->dfc, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15])); + return; + } + if(BIT_F(word2)) /* Memory to address register */ + { + REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(m68k, ea, m68k->sfc)); + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + m68k->remaining_cycles -= 2; + return; + } + /* Memory to data register */ + REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(m68k, ea, m68k->sfc); + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + m68k->remaining_cycles -= 2; + return; + } + m68ki_exception_privilege_violation(m68k); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_moves_16_pi(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_010_PLUS(m68k->cpu_type)) + { + if(m68k->s_flag) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 ea = EA_AY_PI_16(m68k); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_16_fc(m68k, ea, m68k->dfc, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15])); + return; + } + if(BIT_F(word2)) /* Memory to address register */ + { + REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(m68k, ea, m68k->sfc)); + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + m68k->remaining_cycles -= 2; + return; + } + /* Memory to data register */ + REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(m68k, ea, m68k->sfc); + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + m68k->remaining_cycles -= 2; + return; + } + m68ki_exception_privilege_violation(m68k); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_moves_16_pd(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_010_PLUS(m68k->cpu_type)) + { + if(m68k->s_flag) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 ea = EA_AY_PD_16(m68k); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_16_fc(m68k, ea, m68k->dfc, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15])); + return; + } + if(BIT_F(word2)) /* Memory to address register */ + { + REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(m68k, ea, m68k->sfc)); + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + m68k->remaining_cycles -= 2; + return; + } + /* Memory to data register */ + REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(m68k, ea, m68k->sfc); + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + m68k->remaining_cycles -= 2; + return; + } + m68ki_exception_privilege_violation(m68k); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_moves_16_di(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_010_PLUS(m68k->cpu_type)) + { + if(m68k->s_flag) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 ea = EA_AY_DI_16(m68k); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_16_fc(m68k, ea, m68k->dfc, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15])); + return; + } + if(BIT_F(word2)) /* Memory to address register */ + { + REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(m68k, ea, m68k->sfc)); + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + m68k->remaining_cycles -= 2; + return; + } + /* Memory to data register */ + REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(m68k, ea, m68k->sfc); + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + m68k->remaining_cycles -= 2; + return; + } + m68ki_exception_privilege_violation(m68k); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_moves_16_ix(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_010_PLUS(m68k->cpu_type)) + { + if(m68k->s_flag) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 ea = EA_AY_IX_16(m68k); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_16_fc(m68k, ea, m68k->dfc, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15])); + return; + } + if(BIT_F(word2)) /* Memory to address register */ + { + REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(m68k, ea, m68k->sfc)); + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + m68k->remaining_cycles -= 2; + return; + } + /* Memory to data register */ + REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(m68k, ea, m68k->sfc); + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + m68k->remaining_cycles -= 2; + return; + } + m68ki_exception_privilege_violation(m68k); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_moves_16_aw(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_010_PLUS(m68k->cpu_type)) + { + if(m68k->s_flag) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 ea = EA_AW_16(m68k); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_16_fc(m68k, ea, m68k->dfc, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15])); + return; + } + if(BIT_F(word2)) /* Memory to address register */ + { + REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(m68k, ea, m68k->sfc)); + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + m68k->remaining_cycles -= 2; + return; + } + /* Memory to data register */ + REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(m68k, ea, m68k->sfc); + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + m68k->remaining_cycles -= 2; + return; + } + m68ki_exception_privilege_violation(m68k); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_moves_16_al(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_010_PLUS(m68k->cpu_type)) + { + if(m68k->s_flag) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 ea = EA_AL_16(m68k); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_16_fc(m68k, ea, m68k->dfc, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15])); + return; + } + if(BIT_F(word2)) /* Memory to address register */ + { + REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(m68k, ea, m68k->sfc)); + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + m68k->remaining_cycles -= 2; + return; + } + /* Memory to data register */ + REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(m68k, ea, m68k->sfc); + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + m68k->remaining_cycles -= 2; + return; + } + m68ki_exception_privilege_violation(m68k); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_moves_32_ai(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_010_PLUS(m68k->cpu_type)) + { + if(m68k->s_flag) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 ea = EA_AY_AI_32(m68k); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_32_fc(m68k, ea, m68k->dfc, REG_DA[(word2 >> 12) & 15]); + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + m68k->remaining_cycles -= 2; + return; + } + /* Memory to register */ + REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(m68k, ea, m68k->sfc); + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + m68k->remaining_cycles -= 2; + return; + } + m68ki_exception_privilege_violation(m68k); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_moves_32_pi(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_010_PLUS(m68k->cpu_type)) + { + if(m68k->s_flag) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 ea = EA_AY_PI_32(m68k); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_32_fc(m68k, ea, m68k->dfc, REG_DA[(word2 >> 12) & 15]); + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + m68k->remaining_cycles -= 2; + return; + } + /* Memory to register */ + REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(m68k, ea, m68k->sfc); + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + m68k->remaining_cycles -= 2; + return; + } + m68ki_exception_privilege_violation(m68k); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_moves_32_pd(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_010_PLUS(m68k->cpu_type)) + { + if(m68k->s_flag) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 ea = EA_AY_PD_32(m68k); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_32_fc(m68k, ea, m68k->dfc, REG_DA[(word2 >> 12) & 15]); + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + m68k->remaining_cycles -= 2; + return; + } + /* Memory to register */ + REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(m68k, ea, m68k->sfc); + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + m68k->remaining_cycles -= 2; + return; + } + m68ki_exception_privilege_violation(m68k); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_moves_32_di(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_010_PLUS(m68k->cpu_type)) + { + if(m68k->s_flag) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 ea = EA_AY_DI_32(m68k); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_32_fc(m68k, ea, m68k->dfc, REG_DA[(word2 >> 12) & 15]); + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + m68k->remaining_cycles -= 2; + return; + } + /* Memory to register */ + REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(m68k, ea, m68k->sfc); + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + m68k->remaining_cycles -= 2; + return; + } + m68ki_exception_privilege_violation(m68k); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_moves_32_ix(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_010_PLUS(m68k->cpu_type)) + { + if(m68k->s_flag) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 ea = EA_AY_IX_32(m68k); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_32_fc(m68k, ea, m68k->dfc, REG_DA[(word2 >> 12) & 15]); + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + m68k->remaining_cycles -= 2; + return; + } + /* Memory to register */ + REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(m68k, ea, m68k->sfc); + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + m68k->remaining_cycles -= 2; + return; + } + m68ki_exception_privilege_violation(m68k); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_moves_32_aw(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_010_PLUS(m68k->cpu_type)) + { + if(m68k->s_flag) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 ea = EA_AW_32(m68k); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_32_fc(m68k, ea, m68k->dfc, REG_DA[(word2 >> 12) & 15]); + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + m68k->remaining_cycles -= 2; + return; + } + /* Memory to register */ + REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(m68k, ea, m68k->sfc); + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + m68k->remaining_cycles -= 2; + return; + } + m68ki_exception_privilege_violation(m68k); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_moves_32_al(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_010_PLUS(m68k->cpu_type)) + { + if(m68k->s_flag) + { + UINT32 word2 = OPER_I_16(m68k); + UINT32 ea = EA_AL_32(m68k); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_32_fc(m68k, ea, m68k->dfc, REG_DA[(word2 >> 12) & 15]); + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + m68k->remaining_cycles -= 2; + return; + } + /* Memory to register */ + REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(m68k, ea, m68k->sfc); + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + m68k->remaining_cycles -= 2; + return; + } + m68ki_exception_privilege_violation(m68k); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_moveq_32(m68ki_cpu_core *m68k) +{ + UINT32 res = DX = MAKE_INT_8(MASK_OUT_ABOVE_8(m68k->ir)); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_move16_32(m68ki_cpu_core *m68k) +{ + UINT16 w2 = OPER_I_16(m68k); + int ax = m68k->ir & 7; + int ay = (w2 >> 12) & 7; + + m68ki_write_32(m68k, REG_A[ay], m68ki_read_32(m68k, REG_A[ax])); + m68ki_write_32(m68k, REG_A[ay]+4, m68ki_read_32(m68k, REG_A[ax]+4)); + m68ki_write_32(m68k, REG_A[ay]+8, m68ki_read_32(m68k, REG_A[ax]+8)); + m68ki_write_32(m68k, REG_A[ay]+12, m68ki_read_32(m68k, REG_A[ax]+12)); + + REG_A[ax] += 16; + REG_A[ay] += 16; +} + + +static void m68k_op_muls_16_d(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 res = MASK_OUT_ABOVE_32(MAKE_INT_16(DY) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst))); + + *r_dst = res; + + m68k->not_z_flag = res; + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_muls_16_ai(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_AY_AI_16(m68k)) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst))); + + *r_dst = res; + + m68k->not_z_flag = res; + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_muls_16_pi(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_AY_PI_16(m68k)) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst))); + + *r_dst = res; + + m68k->not_z_flag = res; + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_muls_16_pd(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_AY_PD_16(m68k)) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst))); + + *r_dst = res; + + m68k->not_z_flag = res; + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_muls_16_di(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_AY_DI_16(m68k)) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst))); + + *r_dst = res; + + m68k->not_z_flag = res; + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_muls_16_ix(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_AY_IX_16(m68k)) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst))); + + *r_dst = res; + + m68k->not_z_flag = res; + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_muls_16_aw(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_AW_16(m68k)) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst))); + + *r_dst = res; + + m68k->not_z_flag = res; + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_muls_16_al(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_AL_16(m68k)) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst))); + + *r_dst = res; + + m68k->not_z_flag = res; + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_muls_16_pcdi(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_PCDI_16(m68k)) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst))); + + *r_dst = res; + + m68k->not_z_flag = res; + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_muls_16_pcix(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_PCIX_16(m68k)) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst))); + + *r_dst = res; + + m68k->not_z_flag = res; + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_muls_16_i(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_I_16(m68k)) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst))); + + *r_dst = res; + + m68k->not_z_flag = res; + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_mulu_16_d(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 res = MASK_OUT_ABOVE_16(DY) * MASK_OUT_ABOVE_16(*r_dst); + + *r_dst = res; + + m68k->not_z_flag = res; + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_mulu_16_ai(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 res = OPER_AY_AI_16(m68k) * MASK_OUT_ABOVE_16(*r_dst); + + *r_dst = res; + + m68k->not_z_flag = res; + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_mulu_16_pi(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 res = OPER_AY_PI_16(m68k) * MASK_OUT_ABOVE_16(*r_dst); + + *r_dst = res; + + m68k->not_z_flag = res; + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_mulu_16_pd(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 res = OPER_AY_PD_16(m68k) * MASK_OUT_ABOVE_16(*r_dst); + + *r_dst = res; + + m68k->not_z_flag = res; + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_mulu_16_di(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 res = OPER_AY_DI_16(m68k) * MASK_OUT_ABOVE_16(*r_dst); + + *r_dst = res; + + m68k->not_z_flag = res; + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_mulu_16_ix(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 res = OPER_AY_IX_16(m68k) * MASK_OUT_ABOVE_16(*r_dst); + + *r_dst = res; + + m68k->not_z_flag = res; + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_mulu_16_aw(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 res = OPER_AW_16(m68k) * MASK_OUT_ABOVE_16(*r_dst); + + *r_dst = res; + + m68k->not_z_flag = res; + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_mulu_16_al(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 res = OPER_AL_16(m68k) * MASK_OUT_ABOVE_16(*r_dst); + + *r_dst = res; + + m68k->not_z_flag = res; + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_mulu_16_pcdi(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 res = OPER_PCDI_16(m68k) * MASK_OUT_ABOVE_16(*r_dst); + + *r_dst = res; + + m68k->not_z_flag = res; + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_mulu_16_pcix(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 res = OPER_PCIX_16(m68k) * MASK_OUT_ABOVE_16(*r_dst); + + *r_dst = res; + + m68k->not_z_flag = res; + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_mulu_16_i(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 res = OPER_I_16(m68k) * MASK_OUT_ABOVE_16(*r_dst); + + *r_dst = res; + + m68k->not_z_flag = res; + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_mull_32_d(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT64 src = DY; + UINT64 dst = REG_D[(word2 >> 12) & 7]; + UINT64 res; + + m68k->c_flag = CFLAG_CLEAR; + + if(BIT_B(word2)) /* signed */ + { + res = (INT64)((INT32)src) * (INT64)((INT32)dst); + if(!BIT_A(word2)) + { + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = ((INT64)res != (INT32)res)<<7; + REG_D[(word2 >> 12) & 7] = m68k->not_z_flag; + return; + } + m68k->not_z_flag = MASK_OUT_ABOVE_32(res) | (res>>32); + m68k->n_flag = NFLAG_64(res); + m68k->v_flag = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + + res = src * dst; + if(!BIT_A(word2)) + { + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = (res > 0xffffffff)<<7; + REG_D[(word2 >> 12) & 7] = m68k->not_z_flag; + return; + } + m68k->not_z_flag = MASK_OUT_ABOVE_32(res) | (res>>32); + m68k->n_flag = NFLAG_64(res); + m68k->v_flag = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_mull_32_ai(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT64 src = OPER_AY_AI_32(m68k); + UINT64 dst = REG_D[(word2 >> 12) & 7]; + UINT64 res; + + m68k->c_flag = CFLAG_CLEAR; + + if(BIT_B(word2)) /* signed */ + { + res = (INT64)((INT32)src) * (INT64)((INT32)dst); + if(!BIT_A(word2)) + { + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = ((INT64)res != (INT32)res)<<7; + REG_D[(word2 >> 12) & 7] = m68k->not_z_flag; + return; + } + m68k->not_z_flag = MASK_OUT_ABOVE_32(res) | (res>>32); + m68k->n_flag = NFLAG_64(res); + m68k->v_flag = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + + res = src * dst; + if(!BIT_A(word2)) + { + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = (res > 0xffffffff)<<7; + REG_D[(word2 >> 12) & 7] = m68k->not_z_flag; + return; + } + m68k->not_z_flag = MASK_OUT_ABOVE_32(res) | (res>>32); + m68k->n_flag = NFLAG_64(res); + m68k->v_flag = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_mull_32_pi(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT64 src = OPER_AY_PI_32(m68k); + UINT64 dst = REG_D[(word2 >> 12) & 7]; + UINT64 res; + + m68k->c_flag = CFLAG_CLEAR; + + if(BIT_B(word2)) /* signed */ + { + res = (INT64)((INT32)src) * (INT64)((INT32)dst); + if(!BIT_A(word2)) + { + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = ((INT64)res != (INT32)res)<<7; + REG_D[(word2 >> 12) & 7] = m68k->not_z_flag; + return; + } + m68k->not_z_flag = MASK_OUT_ABOVE_32(res) | (res>>32); + m68k->n_flag = NFLAG_64(res); + m68k->v_flag = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + + res = src * dst; + if(!BIT_A(word2)) + { + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = (res > 0xffffffff)<<7; + REG_D[(word2 >> 12) & 7] = m68k->not_z_flag; + return; + } + m68k->not_z_flag = MASK_OUT_ABOVE_32(res) | (res>>32); + m68k->n_flag = NFLAG_64(res); + m68k->v_flag = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_mull_32_pd(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT64 src = OPER_AY_PD_32(m68k); + UINT64 dst = REG_D[(word2 >> 12) & 7]; + UINT64 res; + + m68k->c_flag = CFLAG_CLEAR; + + if(BIT_B(word2)) /* signed */ + { + res = (INT64)((INT32)src) * (INT64)((INT32)dst); + if(!BIT_A(word2)) + { + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = ((INT64)res != (INT32)res)<<7; + REG_D[(word2 >> 12) & 7] = m68k->not_z_flag; + return; + } + m68k->not_z_flag = MASK_OUT_ABOVE_32(res) | (res>>32); + m68k->n_flag = NFLAG_64(res); + m68k->v_flag = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + + res = src * dst; + if(!BIT_A(word2)) + { + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = (res > 0xffffffff)<<7; + REG_D[(word2 >> 12) & 7] = m68k->not_z_flag; + return; + } + m68k->not_z_flag = MASK_OUT_ABOVE_32(res) | (res>>32); + m68k->n_flag = NFLAG_64(res); + m68k->v_flag = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_mull_32_di(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT64 src = OPER_AY_DI_32(m68k); + UINT64 dst = REG_D[(word2 >> 12) & 7]; + UINT64 res; + + m68k->c_flag = CFLAG_CLEAR; + + if(BIT_B(word2)) /* signed */ + { + res = (INT64)((INT32)src) * (INT64)((INT32)dst); + if(!BIT_A(word2)) + { + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = ((INT64)res != (INT32)res)<<7; + REG_D[(word2 >> 12) & 7] = m68k->not_z_flag; + return; + } + m68k->not_z_flag = MASK_OUT_ABOVE_32(res) | (res>>32); + m68k->n_flag = NFLAG_64(res); + m68k->v_flag = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + + res = src * dst; + if(!BIT_A(word2)) + { + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = (res > 0xffffffff)<<7; + REG_D[(word2 >> 12) & 7] = m68k->not_z_flag; + return; + } + m68k->not_z_flag = MASK_OUT_ABOVE_32(res) | (res>>32); + m68k->n_flag = NFLAG_64(res); + m68k->v_flag = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_mull_32_ix(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT64 src = OPER_AY_IX_32(m68k); + UINT64 dst = REG_D[(word2 >> 12) & 7]; + UINT64 res; + + m68k->c_flag = CFLAG_CLEAR; + + if(BIT_B(word2)) /* signed */ + { + res = (INT64)((INT32)src) * (INT64)((INT32)dst); + if(!BIT_A(word2)) + { + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = ((INT64)res != (INT32)res)<<7; + REG_D[(word2 >> 12) & 7] = m68k->not_z_flag; + return; + } + m68k->not_z_flag = MASK_OUT_ABOVE_32(res) | (res>>32); + m68k->n_flag = NFLAG_64(res); + m68k->v_flag = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + + res = src * dst; + if(!BIT_A(word2)) + { + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = (res > 0xffffffff)<<7; + REG_D[(word2 >> 12) & 7] = m68k->not_z_flag; + return; + } + m68k->not_z_flag = MASK_OUT_ABOVE_32(res) | (res>>32); + m68k->n_flag = NFLAG_64(res); + m68k->v_flag = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_mull_32_aw(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT64 src = OPER_AW_32(m68k); + UINT64 dst = REG_D[(word2 >> 12) & 7]; + UINT64 res; + + m68k->c_flag = CFLAG_CLEAR; + + if(BIT_B(word2)) /* signed */ + { + res = (INT64)((INT32)src) * (INT64)((INT32)dst); + if(!BIT_A(word2)) + { + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = ((INT64)res != (INT32)res)<<7; + REG_D[(word2 >> 12) & 7] = m68k->not_z_flag; + return; + } + m68k->not_z_flag = MASK_OUT_ABOVE_32(res) | (res>>32); + m68k->n_flag = NFLAG_64(res); + m68k->v_flag = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + + res = src * dst; + if(!BIT_A(word2)) + { + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = (res > 0xffffffff)<<7; + REG_D[(word2 >> 12) & 7] = m68k->not_z_flag; + return; + } + m68k->not_z_flag = MASK_OUT_ABOVE_32(res) | (res>>32); + m68k->n_flag = NFLAG_64(res); + m68k->v_flag = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_mull_32_al(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT64 src = OPER_AL_32(m68k); + UINT64 dst = REG_D[(word2 >> 12) & 7]; + UINT64 res; + + m68k->c_flag = CFLAG_CLEAR; + + if(BIT_B(word2)) /* signed */ + { + res = (INT64)((INT32)src) * (INT64)((INT32)dst); + if(!BIT_A(word2)) + { + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = ((INT64)res != (INT32)res)<<7; + REG_D[(word2 >> 12) & 7] = m68k->not_z_flag; + return; + } + m68k->not_z_flag = MASK_OUT_ABOVE_32(res) | (res>>32); + m68k->n_flag = NFLAG_64(res); + m68k->v_flag = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + + res = src * dst; + if(!BIT_A(word2)) + { + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = (res > 0xffffffff)<<7; + REG_D[(word2 >> 12) & 7] = m68k->not_z_flag; + return; + } + m68k->not_z_flag = MASK_OUT_ABOVE_32(res) | (res>>32); + m68k->n_flag = NFLAG_64(res); + m68k->v_flag = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_mull_32_pcdi(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT64 src = OPER_PCDI_32(m68k); + UINT64 dst = REG_D[(word2 >> 12) & 7]; + UINT64 res; + + m68k->c_flag = CFLAG_CLEAR; + + if(BIT_B(word2)) /* signed */ + { + res = (INT64)((INT32)src) * (INT64)((INT32)dst); + if(!BIT_A(word2)) + { + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = ((INT64)res != (INT32)res)<<7; + REG_D[(word2 >> 12) & 7] = m68k->not_z_flag; + return; + } + m68k->not_z_flag = MASK_OUT_ABOVE_32(res) | (res>>32); + m68k->n_flag = NFLAG_64(res); + m68k->v_flag = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + + res = src * dst; + if(!BIT_A(word2)) + { + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = (res > 0xffffffff)<<7; + REG_D[(word2 >> 12) & 7] = m68k->not_z_flag; + return; + } + m68k->not_z_flag = MASK_OUT_ABOVE_32(res) | (res>>32); + m68k->n_flag = NFLAG_64(res); + m68k->v_flag = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_mull_32_pcix(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT64 src = OPER_PCIX_32(m68k); + UINT64 dst = REG_D[(word2 >> 12) & 7]; + UINT64 res; + + m68k->c_flag = CFLAG_CLEAR; + + if(BIT_B(word2)) /* signed */ + { + res = (INT64)((INT32)src) * (INT64)((INT32)dst); + if(!BIT_A(word2)) + { + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = ((INT64)res != (INT32)res)<<7; + REG_D[(word2 >> 12) & 7] = m68k->not_z_flag; + return; + } + m68k->not_z_flag = MASK_OUT_ABOVE_32(res) | (res>>32); + m68k->n_flag = NFLAG_64(res); + m68k->v_flag = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + + res = src * dst; + if(!BIT_A(word2)) + { + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = (res > 0xffffffff)<<7; + REG_D[(word2 >> 12) & 7] = m68k->not_z_flag; + return; + } + m68k->not_z_flag = MASK_OUT_ABOVE_32(res) | (res>>32); + m68k->n_flag = NFLAG_64(res); + m68k->v_flag = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_mull_32_i(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 word2 = OPER_I_16(m68k); + UINT64 src = OPER_I_32(m68k); + UINT64 dst = REG_D[(word2 >> 12) & 7]; + UINT64 res; + + m68k->c_flag = CFLAG_CLEAR; + + if(BIT_B(word2)) /* signed */ + { + res = (INT64)((INT32)src) * (INT64)((INT32)dst); + if(!BIT_A(word2)) + { + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = ((INT64)res != (INT32)res)<<7; + REG_D[(word2 >> 12) & 7] = m68k->not_z_flag; + return; + } + m68k->not_z_flag = MASK_OUT_ABOVE_32(res) | (res>>32); + m68k->n_flag = NFLAG_64(res); + m68k->v_flag = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + + res = src * dst; + if(!BIT_A(word2)) + { + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->n_flag = NFLAG_32(res); + m68k->v_flag = (res > 0xffffffff)<<7; + REG_D[(word2 >> 12) & 7] = m68k->not_z_flag; + return; + } + m68k->not_z_flag = MASK_OUT_ABOVE_32(res) | (res>>32); + m68k->n_flag = NFLAG_64(res); + m68k->v_flag = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_nbcd_8_d(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 dst = *r_dst; + UINT32 res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1(m68k)); + + if(res != 0x9a) + { + m68k->v_flag = ~res; /* Undefined V behavior */ + + if((res & 0x0f) == 0xa) + res = (res & 0xf0) + 0x10; + + res = MASK_OUT_ABOVE_8(res); + + m68k->v_flag &= res; /* Undefined V behavior part II */ + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + m68k->not_z_flag |= res; + m68k->c_flag = CFLAG_SET; + m68k->x_flag = XFLAG_SET; + } + else + { + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + m68k->x_flag = XFLAG_CLEAR; + } + m68k->n_flag = NFLAG_8(res); /* Undefined N behavior */ +} + + +static void m68k_op_nbcd_8_ai(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_AI_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1(m68k)); + + if(res != 0x9a) + { + m68k->v_flag = ~res; /* Undefined V behavior */ + + if((res & 0x0f) == 0xa) + res = (res & 0xf0) + 0x10; + + res = MASK_OUT_ABOVE_8(res); + + m68k->v_flag &= res; /* Undefined V behavior part II */ + + m68ki_write_8(m68k, ea, MASK_OUT_ABOVE_8(res)); + + m68k->not_z_flag |= res; + m68k->c_flag = CFLAG_SET; + m68k->x_flag = XFLAG_SET; + } + else + { + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + m68k->x_flag = XFLAG_CLEAR; + } + m68k->n_flag = NFLAG_8(res); /* Undefined N behavior */ +} + + +static void m68k_op_nbcd_8_pi(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PI_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1(m68k)); + + if(res != 0x9a) + { + m68k->v_flag = ~res; /* Undefined V behavior */ + + if((res & 0x0f) == 0xa) + res = (res & 0xf0) + 0x10; + + res = MASK_OUT_ABOVE_8(res); + + m68k->v_flag &= res; /* Undefined V behavior part II */ + + m68ki_write_8(m68k, ea, MASK_OUT_ABOVE_8(res)); + + m68k->not_z_flag |= res; + m68k->c_flag = CFLAG_SET; + m68k->x_flag = XFLAG_SET; + } + else + { + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + m68k->x_flag = XFLAG_CLEAR; + } + m68k->n_flag = NFLAG_8(res); /* Undefined N behavior */ +} + + +static void m68k_op_nbcd_8_pi7(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_A7_PI_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1(m68k)); + + if(res != 0x9a) + { + m68k->v_flag = ~res; /* Undefined V behavior */ + + if((res & 0x0f) == 0xa) + res = (res & 0xf0) + 0x10; + + res = MASK_OUT_ABOVE_8(res); + + m68k->v_flag &= res; /* Undefined V behavior part II */ + + m68ki_write_8(m68k, ea, MASK_OUT_ABOVE_8(res)); + + m68k->not_z_flag |= res; + m68k->c_flag = CFLAG_SET; + m68k->x_flag = XFLAG_SET; + } + else + { + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + m68k->x_flag = XFLAG_CLEAR; + } + m68k->n_flag = NFLAG_8(res); /* Undefined N behavior */ +} + + +static void m68k_op_nbcd_8_pd(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PD_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1(m68k)); + + if(res != 0x9a) + { + m68k->v_flag = ~res; /* Undefined V behavior */ + + if((res & 0x0f) == 0xa) + res = (res & 0xf0) + 0x10; + + res = MASK_OUT_ABOVE_8(res); + + m68k->v_flag &= res; /* Undefined V behavior part II */ + + m68ki_write_8(m68k, ea, MASK_OUT_ABOVE_8(res)); + + m68k->not_z_flag |= res; + m68k->c_flag = CFLAG_SET; + m68k->x_flag = XFLAG_SET; + } + else + { + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + m68k->x_flag = XFLAG_CLEAR; + } + m68k->n_flag = NFLAG_8(res); /* Undefined N behavior */ +} + + +static void m68k_op_nbcd_8_pd7(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_A7_PD_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1(m68k)); + + if(res != 0x9a) + { + m68k->v_flag = ~res; /* Undefined V behavior */ + + if((res & 0x0f) == 0xa) + res = (res & 0xf0) + 0x10; + + res = MASK_OUT_ABOVE_8(res); + + m68k->v_flag &= res; /* Undefined V behavior part II */ + + m68ki_write_8(m68k, ea, MASK_OUT_ABOVE_8(res)); + + m68k->not_z_flag |= res; + m68k->c_flag = CFLAG_SET; + m68k->x_flag = XFLAG_SET; + } + else + { + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + m68k->x_flag = XFLAG_CLEAR; + } + m68k->n_flag = NFLAG_8(res); /* Undefined N behavior */ +} + + +static void m68k_op_nbcd_8_di(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_DI_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1(m68k)); + + if(res != 0x9a) + { + m68k->v_flag = ~res; /* Undefined V behavior */ + + if((res & 0x0f) == 0xa) + res = (res & 0xf0) + 0x10; + + res = MASK_OUT_ABOVE_8(res); + + m68k->v_flag &= res; /* Undefined V behavior part II */ + + m68ki_write_8(m68k, ea, MASK_OUT_ABOVE_8(res)); + + m68k->not_z_flag |= res; + m68k->c_flag = CFLAG_SET; + m68k->x_flag = XFLAG_SET; + } + else + { + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + m68k->x_flag = XFLAG_CLEAR; + } + m68k->n_flag = NFLAG_8(res); /* Undefined N behavior */ +} + + +static void m68k_op_nbcd_8_ix(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_IX_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1(m68k)); + + if(res != 0x9a) + { + m68k->v_flag = ~res; /* Undefined V behavior */ + + if((res & 0x0f) == 0xa) + res = (res & 0xf0) + 0x10; + + res = MASK_OUT_ABOVE_8(res); + + m68k->v_flag &= res; /* Undefined V behavior part II */ + + m68ki_write_8(m68k, ea, MASK_OUT_ABOVE_8(res)); + + m68k->not_z_flag |= res; + m68k->c_flag = CFLAG_SET; + m68k->x_flag = XFLAG_SET; + } + else + { + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + m68k->x_flag = XFLAG_CLEAR; + } + m68k->n_flag = NFLAG_8(res); /* Undefined N behavior */ +} + + +static void m68k_op_nbcd_8_aw(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AW_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1(m68k)); + + if(res != 0x9a) + { + m68k->v_flag = ~res; /* Undefined V behavior */ + + if((res & 0x0f) == 0xa) + res = (res & 0xf0) + 0x10; + + res = MASK_OUT_ABOVE_8(res); + + m68k->v_flag &= res; /* Undefined V behavior part II */ + + m68ki_write_8(m68k, ea, MASK_OUT_ABOVE_8(res)); + + m68k->not_z_flag |= res; + m68k->c_flag = CFLAG_SET; + m68k->x_flag = XFLAG_SET; + } + else + { + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + m68k->x_flag = XFLAG_CLEAR; + } + m68k->n_flag = NFLAG_8(res); /* Undefined N behavior */ +} + + +static void m68k_op_nbcd_8_al(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AL_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1(m68k)); + + if(res != 0x9a) + { + m68k->v_flag = ~res; /* Undefined V behavior */ + + if((res & 0x0f) == 0xa) + res = (res & 0xf0) + 0x10; + + res = MASK_OUT_ABOVE_8(res); + + m68k->v_flag &= res; /* Undefined V behavior part II */ + + m68ki_write_8(m68k, ea, MASK_OUT_ABOVE_8(res)); + + m68k->not_z_flag |= res; + m68k->c_flag = CFLAG_SET; + m68k->x_flag = XFLAG_SET; + } + else + { + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + m68k->x_flag = XFLAG_CLEAR; + } + m68k->n_flag = NFLAG_8(res); /* Undefined N behavior */ +} + + +static void m68k_op_neg_8_d(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 res = 0 - MASK_OUT_ABOVE_8(*r_dst); + + m68k->n_flag = NFLAG_8(res); + m68k->c_flag = m68k->x_flag = CFLAG_8(res); + m68k->v_flag = *r_dst & res; + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_neg_8_ai(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_AI_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + UINT32 res = 0 - src; + + m68k->n_flag = NFLAG_8(res); + m68k->c_flag = m68k->x_flag = CFLAG_8(res); + m68k->v_flag = src & res; + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_neg_8_pi(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PI_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + UINT32 res = 0 - src; + + m68k->n_flag = NFLAG_8(res); + m68k->c_flag = m68k->x_flag = CFLAG_8(res); + m68k->v_flag = src & res; + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_neg_8_pi7(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_A7_PI_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + UINT32 res = 0 - src; + + m68k->n_flag = NFLAG_8(res); + m68k->c_flag = m68k->x_flag = CFLAG_8(res); + m68k->v_flag = src & res; + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_neg_8_pd(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PD_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + UINT32 res = 0 - src; + + m68k->n_flag = NFLAG_8(res); + m68k->c_flag = m68k->x_flag = CFLAG_8(res); + m68k->v_flag = src & res; + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_neg_8_pd7(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_A7_PD_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + UINT32 res = 0 - src; + + m68k->n_flag = NFLAG_8(res); + m68k->c_flag = m68k->x_flag = CFLAG_8(res); + m68k->v_flag = src & res; + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_neg_8_di(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_DI_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + UINT32 res = 0 - src; + + m68k->n_flag = NFLAG_8(res); + m68k->c_flag = m68k->x_flag = CFLAG_8(res); + m68k->v_flag = src & res; + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_neg_8_ix(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_IX_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + UINT32 res = 0 - src; + + m68k->n_flag = NFLAG_8(res); + m68k->c_flag = m68k->x_flag = CFLAG_8(res); + m68k->v_flag = src & res; + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_neg_8_aw(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AW_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + UINT32 res = 0 - src; + + m68k->n_flag = NFLAG_8(res); + m68k->c_flag = m68k->x_flag = CFLAG_8(res); + m68k->v_flag = src & res; + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_neg_8_al(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AL_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + UINT32 res = 0 - src; + + m68k->n_flag = NFLAG_8(res); + m68k->c_flag = m68k->x_flag = CFLAG_8(res); + m68k->v_flag = src & res; + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_neg_16_d(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 res = 0 - MASK_OUT_ABOVE_16(*r_dst); + + m68k->n_flag = NFLAG_16(res); + m68k->c_flag = m68k->x_flag = CFLAG_16(res); + m68k->v_flag = (*r_dst & res)>>8; + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_neg_16_ai(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_AI_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = 0 - src; + + m68k->n_flag = NFLAG_16(res); + m68k->c_flag = m68k->x_flag = CFLAG_16(res); + m68k->v_flag = (src & res)>>8; + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_neg_16_pi(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PI_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = 0 - src; + + m68k->n_flag = NFLAG_16(res); + m68k->c_flag = m68k->x_flag = CFLAG_16(res); + m68k->v_flag = (src & res)>>8; + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_neg_16_pd(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PD_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = 0 - src; + + m68k->n_flag = NFLAG_16(res); + m68k->c_flag = m68k->x_flag = CFLAG_16(res); + m68k->v_flag = (src & res)>>8; + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_neg_16_di(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_DI_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = 0 - src; + + m68k->n_flag = NFLAG_16(res); + m68k->c_flag = m68k->x_flag = CFLAG_16(res); + m68k->v_flag = (src & res)>>8; + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_neg_16_ix(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_IX_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = 0 - src; + + m68k->n_flag = NFLAG_16(res); + m68k->c_flag = m68k->x_flag = CFLAG_16(res); + m68k->v_flag = (src & res)>>8; + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_neg_16_aw(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AW_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = 0 - src; + + m68k->n_flag = NFLAG_16(res); + m68k->c_flag = m68k->x_flag = CFLAG_16(res); + m68k->v_flag = (src & res)>>8; + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_neg_16_al(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AL_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = 0 - src; + + m68k->n_flag = NFLAG_16(res); + m68k->c_flag = m68k->x_flag = CFLAG_16(res); + m68k->v_flag = (src & res)>>8; + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_neg_32_d(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 res = 0 - *r_dst; + + m68k->n_flag = NFLAG_32(res); + m68k->c_flag = m68k->x_flag = CFLAG_SUB_32(*r_dst, 0, res); + m68k->v_flag = (*r_dst & res)>>24; + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + *r_dst = m68k->not_z_flag; +} + + +static void m68k_op_neg_32_ai(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_AI_32(m68k); + UINT32 src = m68ki_read_32(m68k, ea); + UINT32 res = 0 - src; + + m68k->n_flag = NFLAG_32(res); + m68k->c_flag = m68k->x_flag = CFLAG_SUB_32(src, 0, res); + m68k->v_flag = (src & res)>>24; + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_neg_32_pi(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PI_32(m68k); + UINT32 src = m68ki_read_32(m68k, ea); + UINT32 res = 0 - src; + + m68k->n_flag = NFLAG_32(res); + m68k->c_flag = m68k->x_flag = CFLAG_SUB_32(src, 0, res); + m68k->v_flag = (src & res)>>24; + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_neg_32_pd(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PD_32(m68k); + UINT32 src = m68ki_read_32(m68k, ea); + UINT32 res = 0 - src; + + m68k->n_flag = NFLAG_32(res); + m68k->c_flag = m68k->x_flag = CFLAG_SUB_32(src, 0, res); + m68k->v_flag = (src & res)>>24; + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_neg_32_di(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_DI_32(m68k); + UINT32 src = m68ki_read_32(m68k, ea); + UINT32 res = 0 - src; + + m68k->n_flag = NFLAG_32(res); + m68k->c_flag = m68k->x_flag = CFLAG_SUB_32(src, 0, res); + m68k->v_flag = (src & res)>>24; + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_neg_32_ix(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_IX_32(m68k); + UINT32 src = m68ki_read_32(m68k, ea); + UINT32 res = 0 - src; + + m68k->n_flag = NFLAG_32(res); + m68k->c_flag = m68k->x_flag = CFLAG_SUB_32(src, 0, res); + m68k->v_flag = (src & res)>>24; + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_neg_32_aw(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AW_32(m68k); + UINT32 src = m68ki_read_32(m68k, ea); + UINT32 res = 0 - src; + + m68k->n_flag = NFLAG_32(res); + m68k->c_flag = m68k->x_flag = CFLAG_SUB_32(src, 0, res); + m68k->v_flag = (src & res)>>24; + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_neg_32_al(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AL_32(m68k); + UINT32 src = m68ki_read_32(m68k, ea); + UINT32 res = 0 - src; + + m68k->n_flag = NFLAG_32(res); + m68k->c_flag = m68k->x_flag = CFLAG_SUB_32(src, 0, res); + m68k->v_flag = (src & res)>>24; + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_negx_8_d(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 res = 0 - MASK_OUT_ABOVE_8(*r_dst) - XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = *r_dst & res; + + res = MASK_OUT_ABOVE_8(res); + m68k->not_z_flag |= res; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; +} + + +static void m68k_op_negx_8_ai(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_AI_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + UINT32 res = 0 - src - XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = src & res; + + res = MASK_OUT_ABOVE_8(res); + m68k->not_z_flag |= res; + + m68ki_write_8(m68k, ea, res); +} + + +static void m68k_op_negx_8_pi(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PI_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + UINT32 res = 0 - src - XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = src & res; + + res = MASK_OUT_ABOVE_8(res); + m68k->not_z_flag |= res; + + m68ki_write_8(m68k, ea, res); +} + + +static void m68k_op_negx_8_pi7(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_A7_PI_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + UINT32 res = 0 - src - XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = src & res; + + res = MASK_OUT_ABOVE_8(res); + m68k->not_z_flag |= res; + + m68ki_write_8(m68k, ea, res); +} + + +static void m68k_op_negx_8_pd(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PD_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + UINT32 res = 0 - src - XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = src & res; + + res = MASK_OUT_ABOVE_8(res); + m68k->not_z_flag |= res; + + m68ki_write_8(m68k, ea, res); +} + + +static void m68k_op_negx_8_pd7(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_A7_PD_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + UINT32 res = 0 - src - XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = src & res; + + res = MASK_OUT_ABOVE_8(res); + m68k->not_z_flag |= res; + + m68ki_write_8(m68k, ea, res); +} + + +static void m68k_op_negx_8_di(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_DI_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + UINT32 res = 0 - src - XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = src & res; + + res = MASK_OUT_ABOVE_8(res); + m68k->not_z_flag |= res; + + m68ki_write_8(m68k, ea, res); +} + + +static void m68k_op_negx_8_ix(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_IX_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + UINT32 res = 0 - src - XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = src & res; + + res = MASK_OUT_ABOVE_8(res); + m68k->not_z_flag |= res; + + m68ki_write_8(m68k, ea, res); +} + + +static void m68k_op_negx_8_aw(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AW_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + UINT32 res = 0 - src - XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = src & res; + + res = MASK_OUT_ABOVE_8(res); + m68k->not_z_flag |= res; + + m68ki_write_8(m68k, ea, res); +} + + +static void m68k_op_negx_8_al(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AL_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea); + UINT32 res = 0 - src - XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = src & res; + + res = MASK_OUT_ABOVE_8(res); + m68k->not_z_flag |= res; + + m68ki_write_8(m68k, ea, res); +} + + +static void m68k_op_negx_16_d(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 res = 0 - MASK_OUT_ABOVE_16(*r_dst) - XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_16(res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->v_flag = (*r_dst & res)>>8; + + res = MASK_OUT_ABOVE_16(res); + m68k->not_z_flag |= res; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; +} + + +static void m68k_op_negx_16_ai(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_AI_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_16(res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->v_flag = (src & res)>>8; + + res = MASK_OUT_ABOVE_16(res); + m68k->not_z_flag |= res; + + m68ki_write_16(m68k, ea, res); +} + + +static void m68k_op_negx_16_pi(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PI_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_16(res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->v_flag = (src & res)>>8; + + res = MASK_OUT_ABOVE_16(res); + m68k->not_z_flag |= res; + + m68ki_write_16(m68k, ea, res); +} + + +static void m68k_op_negx_16_pd(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PD_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_16(res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->v_flag = (src & res)>>8; + + res = MASK_OUT_ABOVE_16(res); + m68k->not_z_flag |= res; + + m68ki_write_16(m68k, ea, res); +} + + +static void m68k_op_negx_16_di(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_DI_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_16(res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->v_flag = (src & res)>>8; + + res = MASK_OUT_ABOVE_16(res); + m68k->not_z_flag |= res; + + m68ki_write_16(m68k, ea, res); +} + + +static void m68k_op_negx_16_ix(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_IX_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_16(res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->v_flag = (src & res)>>8; + + res = MASK_OUT_ABOVE_16(res); + m68k->not_z_flag |= res; + + m68ki_write_16(m68k, ea, res); +} + + +static void m68k_op_negx_16_aw(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AW_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_16(res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->v_flag = (src & res)>>8; + + res = MASK_OUT_ABOVE_16(res); + m68k->not_z_flag |= res; + + m68ki_write_16(m68k, ea, res); +} + + +static void m68k_op_negx_16_al(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AL_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_16(res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->v_flag = (src & res)>>8; + + res = MASK_OUT_ABOVE_16(res); + m68k->not_z_flag |= res; + + m68ki_write_16(m68k, ea, res); +} + + +static void m68k_op_negx_32_d(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 res = 0 - MASK_OUT_ABOVE_32(*r_dst) - XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_32(res); + m68k->x_flag = m68k->c_flag = CFLAG_SUB_32(*r_dst, 0, res); + m68k->v_flag = (*r_dst & res)>>24; + + res = MASK_OUT_ABOVE_32(res); + m68k->not_z_flag |= res; + + *r_dst = res; +} + + +static void m68k_op_negx_32_ai(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_AI_32(m68k); + UINT32 src = m68ki_read_32(m68k, ea); + UINT32 res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_32(res); + m68k->x_flag = m68k->c_flag = CFLAG_SUB_32(src, 0, res); + m68k->v_flag = (src & res)>>24; + + res = MASK_OUT_ABOVE_32(res); + m68k->not_z_flag |= res; + + m68ki_write_32(m68k, ea, res); +} + + +static void m68k_op_negx_32_pi(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PI_32(m68k); + UINT32 src = m68ki_read_32(m68k, ea); + UINT32 res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_32(res); + m68k->x_flag = m68k->c_flag = CFLAG_SUB_32(src, 0, res); + m68k->v_flag = (src & res)>>24; + + res = MASK_OUT_ABOVE_32(res); + m68k->not_z_flag |= res; + + m68ki_write_32(m68k, ea, res); +} + + +static void m68k_op_negx_32_pd(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PD_32(m68k); + UINT32 src = m68ki_read_32(m68k, ea); + UINT32 res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_32(res); + m68k->x_flag = m68k->c_flag = CFLAG_SUB_32(src, 0, res); + m68k->v_flag = (src & res)>>24; + + res = MASK_OUT_ABOVE_32(res); + m68k->not_z_flag |= res; + + m68ki_write_32(m68k, ea, res); +} + + +static void m68k_op_negx_32_di(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_DI_32(m68k); + UINT32 src = m68ki_read_32(m68k, ea); + UINT32 res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_32(res); + m68k->x_flag = m68k->c_flag = CFLAG_SUB_32(src, 0, res); + m68k->v_flag = (src & res)>>24; + + res = MASK_OUT_ABOVE_32(res); + m68k->not_z_flag |= res; + + m68ki_write_32(m68k, ea, res); +} + + +static void m68k_op_negx_32_ix(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_IX_32(m68k); + UINT32 src = m68ki_read_32(m68k, ea); + UINT32 res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_32(res); + m68k->x_flag = m68k->c_flag = CFLAG_SUB_32(src, 0, res); + m68k->v_flag = (src & res)>>24; + + res = MASK_OUT_ABOVE_32(res); + m68k->not_z_flag |= res; + + m68ki_write_32(m68k, ea, res); +} + + +static void m68k_op_negx_32_aw(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AW_32(m68k); + UINT32 src = m68ki_read_32(m68k, ea); + UINT32 res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_32(res); + m68k->x_flag = m68k->c_flag = CFLAG_SUB_32(src, 0, res); + m68k->v_flag = (src & res)>>24; + + res = MASK_OUT_ABOVE_32(res); + m68k->not_z_flag |= res; + + m68ki_write_32(m68k, ea, res); +} + + +static void m68k_op_negx_32_al(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AL_32(m68k); + UINT32 src = m68ki_read_32(m68k, ea); + UINT32 res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_32(res); + m68k->x_flag = m68k->c_flag = CFLAG_SUB_32(src, 0, res); + m68k->v_flag = (src & res)>>24; + + res = MASK_OUT_ABOVE_32(res); + m68k->not_z_flag |= res; + + m68ki_write_32(m68k, ea, res); +} + + +static void m68k_op_nop(m68ki_cpu_core *m68k) +{ + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ +} + + +static void m68k_op_not_8_d(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 res = MASK_OUT_ABOVE_8(~*r_dst); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_not_8_ai(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_AI_8(m68k); + UINT32 res = MASK_OUT_ABOVE_8(~m68ki_read_8(m68k, ea)); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_not_8_pi(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PI_8(m68k); + UINT32 res = MASK_OUT_ABOVE_8(~m68ki_read_8(m68k, ea)); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_not_8_pi7(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_A7_PI_8(m68k); + UINT32 res = MASK_OUT_ABOVE_8(~m68ki_read_8(m68k, ea)); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_not_8_pd(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PD_8(m68k); + UINT32 res = MASK_OUT_ABOVE_8(~m68ki_read_8(m68k, ea)); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_not_8_pd7(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_A7_PD_8(m68k); + UINT32 res = MASK_OUT_ABOVE_8(~m68ki_read_8(m68k, ea)); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_not_8_di(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_DI_8(m68k); + UINT32 res = MASK_OUT_ABOVE_8(~m68ki_read_8(m68k, ea)); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_not_8_ix(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_IX_8(m68k); + UINT32 res = MASK_OUT_ABOVE_8(~m68ki_read_8(m68k, ea)); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_not_8_aw(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AW_8(m68k); + UINT32 res = MASK_OUT_ABOVE_8(~m68ki_read_8(m68k, ea)); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_not_8_al(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AL_8(m68k); + UINT32 res = MASK_OUT_ABOVE_8(~m68ki_read_8(m68k, ea)); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_not_16_d(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 res = MASK_OUT_ABOVE_16(~*r_dst); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_not_16_ai(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_AI_16(m68k); + UINT32 res = MASK_OUT_ABOVE_16(~m68ki_read_16(m68k, ea)); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_not_16_pi(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PI_16(m68k); + UINT32 res = MASK_OUT_ABOVE_16(~m68ki_read_16(m68k, ea)); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_not_16_pd(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PD_16(m68k); + UINT32 res = MASK_OUT_ABOVE_16(~m68ki_read_16(m68k, ea)); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_not_16_di(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_DI_16(m68k); + UINT32 res = MASK_OUT_ABOVE_16(~m68ki_read_16(m68k, ea)); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_not_16_ix(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_IX_16(m68k); + UINT32 res = MASK_OUT_ABOVE_16(~m68ki_read_16(m68k, ea)); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_not_16_aw(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AW_16(m68k); + UINT32 res = MASK_OUT_ABOVE_16(~m68ki_read_16(m68k, ea)); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_not_16_al(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AL_16(m68k); + UINT32 res = MASK_OUT_ABOVE_16(~m68ki_read_16(m68k, ea)); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_not_32_d(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 res = *r_dst = MASK_OUT_ABOVE_32(~*r_dst); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_not_32_ai(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_AI_32(m68k); + UINT32 res = MASK_OUT_ABOVE_32(~m68ki_read_32(m68k, ea)); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_not_32_pi(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PI_32(m68k); + UINT32 res = MASK_OUT_ABOVE_32(~m68ki_read_32(m68k, ea)); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_not_32_pd(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PD_32(m68k); + UINT32 res = MASK_OUT_ABOVE_32(~m68ki_read_32(m68k, ea)); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_not_32_di(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_DI_32(m68k); + UINT32 res = MASK_OUT_ABOVE_32(~m68ki_read_32(m68k, ea)); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_not_32_ix(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_IX_32(m68k); + UINT32 res = MASK_OUT_ABOVE_32(~m68ki_read_32(m68k, ea)); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_not_32_aw(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AW_32(m68k); + UINT32 res = MASK_OUT_ABOVE_32(~m68ki_read_32(m68k, ea)); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_not_32_al(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AL_32(m68k); + UINT32 res = MASK_OUT_ABOVE_32(~m68ki_read_32(m68k, ea)); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_8_er_d(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_8((DX |= MASK_OUT_ABOVE_8(DY))); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_8_er_ai(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_8((DX |= OPER_AY_AI_8(m68k))); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_8_er_pi(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_8((DX |= OPER_AY_PI_8(m68k))); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_8_er_pi7(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_8((DX |= OPER_A7_PI_8(m68k))); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_8_er_pd(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_8((DX |= OPER_AY_PD_8(m68k))); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_8_er_pd7(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_8((DX |= OPER_A7_PD_8(m68k))); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_8_er_di(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_8((DX |= OPER_AY_DI_8(m68k))); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_8_er_ix(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_8((DX |= OPER_AY_IX_8(m68k))); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_8_er_aw(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_8((DX |= OPER_AW_8(m68k))); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_8_er_al(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_8((DX |= OPER_AL_8(m68k))); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_8_er_pcdi(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_8((DX |= OPER_PCDI_8(m68k))); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_8_er_pcix(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_8((DX |= OPER_PCIX_8(m68k))); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_8_er_i(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_8((DX |= OPER_I_8(m68k))); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_16_er_d(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_16((DX |= MASK_OUT_ABOVE_16(DY))); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_16_er_ai(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_16((DX |= OPER_AY_AI_16(m68k))); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_16_er_pi(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_16((DX |= OPER_AY_PI_16(m68k))); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_16_er_pd(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_16((DX |= OPER_AY_PD_16(m68k))); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_16_er_di(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_16((DX |= OPER_AY_DI_16(m68k))); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_16_er_ix(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_16((DX |= OPER_AY_IX_16(m68k))); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_16_er_aw(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_16((DX |= OPER_AW_16(m68k))); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_16_er_al(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_16((DX |= OPER_AL_16(m68k))); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_16_er_pcdi(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_16((DX |= OPER_PCDI_16(m68k))); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_16_er_pcix(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_16((DX |= OPER_PCIX_16(m68k))); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_16_er_i(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_16((DX |= OPER_I_16(m68k))); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_32_er_d(m68ki_cpu_core *m68k) +{ + UINT32 res = DX |= DY; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_32_er_ai(m68ki_cpu_core *m68k) +{ + UINT32 res = DX |= OPER_AY_AI_32(m68k); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_32_er_pi(m68ki_cpu_core *m68k) +{ + UINT32 res = DX |= OPER_AY_PI_32(m68k); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_32_er_pd(m68ki_cpu_core *m68k) +{ + UINT32 res = DX |= OPER_AY_PD_32(m68k); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_32_er_di(m68ki_cpu_core *m68k) +{ + UINT32 res = DX |= OPER_AY_DI_32(m68k); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_32_er_ix(m68ki_cpu_core *m68k) +{ + UINT32 res = DX |= OPER_AY_IX_32(m68k); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_32_er_aw(m68ki_cpu_core *m68k) +{ + UINT32 res = DX |= OPER_AW_32(m68k); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_32_er_al(m68ki_cpu_core *m68k) +{ + UINT32 res = DX |= OPER_AL_32(m68k); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_32_er_pcdi(m68ki_cpu_core *m68k) +{ + UINT32 res = DX |= OPER_PCDI_32(m68k); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_32_er_pcix(m68ki_cpu_core *m68k) +{ + UINT32 res = DX |= OPER_PCIX_32(m68k); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_32_er_i(m68ki_cpu_core *m68k) +{ + UINT32 res = DX |= OPER_I_32(m68k); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_8_re_ai(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_AI_8(m68k); + UINT32 res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(m68k, ea)); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_8_re_pi(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PI_8(m68k); + UINT32 res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(m68k, ea)); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_8_re_pi7(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_A7_PI_8(m68k); + UINT32 res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(m68k, ea)); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_8_re_pd(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PD_8(m68k); + UINT32 res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(m68k, ea)); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_8_re_pd7(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_A7_PD_8(m68k); + UINT32 res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(m68k, ea)); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_8_re_di(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_DI_8(m68k); + UINT32 res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(m68k, ea)); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_8_re_ix(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_IX_8(m68k); + UINT32 res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(m68k, ea)); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_8_re_aw(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AW_8(m68k); + UINT32 res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(m68k, ea)); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_8_re_al(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AL_8(m68k); + UINT32 res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(m68k, ea)); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_16_re_ai(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_AI_16(m68k); + UINT32 res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(m68k, ea)); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_16_re_pi(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PI_16(m68k); + UINT32 res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(m68k, ea)); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_16_re_pd(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PD_16(m68k); + UINT32 res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(m68k, ea)); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_16_re_di(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_DI_16(m68k); + UINT32 res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(m68k, ea)); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_16_re_ix(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_IX_16(m68k); + UINT32 res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(m68k, ea)); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_16_re_aw(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AW_16(m68k); + UINT32 res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(m68k, ea)); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_16_re_al(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AL_16(m68k); + UINT32 res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(m68k, ea)); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_32_re_ai(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_AI_32(m68k); + UINT32 res = DX | m68ki_read_32(m68k, ea); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_32_re_pi(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PI_32(m68k); + UINT32 res = DX | m68ki_read_32(m68k, ea); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_32_re_pd(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PD_32(m68k); + UINT32 res = DX | m68ki_read_32(m68k, ea); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_32_re_di(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_DI_32(m68k); + UINT32 res = DX | m68ki_read_32(m68k, ea); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_32_re_ix(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_IX_32(m68k); + UINT32 res = DX | m68ki_read_32(m68k, ea); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_32_re_aw(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AW_32(m68k); + UINT32 res = DX | m68ki_read_32(m68k, ea); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_or_32_re_al(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AL_32(m68k); + UINT32 res = DX | m68ki_read_32(m68k, ea); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_ori_8_d(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_8((DY |= OPER_I_8(m68k))); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_ori_8_ai(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 ea = EA_AY_AI_8(m68k); + UINT32 res = MASK_OUT_ABOVE_8(src | m68ki_read_8(m68k, ea)); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_ori_8_pi(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 ea = EA_AY_PI_8(m68k); + UINT32 res = MASK_OUT_ABOVE_8(src | m68ki_read_8(m68k, ea)); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_ori_8_pi7(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 ea = EA_A7_PI_8(m68k); + UINT32 res = MASK_OUT_ABOVE_8(src | m68ki_read_8(m68k, ea)); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_ori_8_pd(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 ea = EA_AY_PD_8(m68k); + UINT32 res = MASK_OUT_ABOVE_8(src | m68ki_read_8(m68k, ea)); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_ori_8_pd7(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 ea = EA_A7_PD_8(m68k); + UINT32 res = MASK_OUT_ABOVE_8(src | m68ki_read_8(m68k, ea)); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_ori_8_di(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 ea = EA_AY_DI_8(m68k); + UINT32 res = MASK_OUT_ABOVE_8(src | m68ki_read_8(m68k, ea)); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_ori_8_ix(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 ea = EA_AY_IX_8(m68k); + UINT32 res = MASK_OUT_ABOVE_8(src | m68ki_read_8(m68k, ea)); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_ori_8_aw(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 ea = EA_AW_8(m68k); + UINT32 res = MASK_OUT_ABOVE_8(src | m68ki_read_8(m68k, ea)); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_ori_8_al(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 ea = EA_AL_8(m68k); + UINT32 res = MASK_OUT_ABOVE_8(src | m68ki_read_8(m68k, ea)); + + m68ki_write_8(m68k, ea, res); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_ori_16_d(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_16(DY |= OPER_I_16(m68k)); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_ori_16_ai(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_16(m68k); + UINT32 ea = EA_AY_AI_16(m68k); + UINT32 res = MASK_OUT_ABOVE_16(src | m68ki_read_16(m68k, ea)); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_ori_16_pi(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_16(m68k); + UINT32 ea = EA_AY_PI_16(m68k); + UINT32 res = MASK_OUT_ABOVE_16(src | m68ki_read_16(m68k, ea)); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_ori_16_pd(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_16(m68k); + UINT32 ea = EA_AY_PD_16(m68k); + UINT32 res = MASK_OUT_ABOVE_16(src | m68ki_read_16(m68k, ea)); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_ori_16_di(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_16(m68k); + UINT32 ea = EA_AY_DI_16(m68k); + UINT32 res = MASK_OUT_ABOVE_16(src | m68ki_read_16(m68k, ea)); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_ori_16_ix(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_16(m68k); + UINT32 ea = EA_AY_IX_16(m68k); + UINT32 res = MASK_OUT_ABOVE_16(src | m68ki_read_16(m68k, ea)); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_ori_16_aw(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_16(m68k); + UINT32 ea = EA_AW_16(m68k); + UINT32 res = MASK_OUT_ABOVE_16(src | m68ki_read_16(m68k, ea)); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_ori_16_al(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_16(m68k); + UINT32 ea = EA_AL_16(m68k); + UINT32 res = MASK_OUT_ABOVE_16(src | m68ki_read_16(m68k, ea)); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_ori_32_d(m68ki_cpu_core *m68k) +{ + UINT32 res = DY |= OPER_I_32(m68k); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_ori_32_ai(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_32(m68k); + UINT32 ea = EA_AY_AI_32(m68k); + UINT32 res = src | m68ki_read_32(m68k, ea); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_ori_32_pi(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_32(m68k); + UINT32 ea = EA_AY_PI_32(m68k); + UINT32 res = src | m68ki_read_32(m68k, ea); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_ori_32_pd(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_32(m68k); + UINT32 ea = EA_AY_PD_32(m68k); + UINT32 res = src | m68ki_read_32(m68k, ea); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_ori_32_di(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_32(m68k); + UINT32 ea = EA_AY_DI_32(m68k); + UINT32 res = src | m68ki_read_32(m68k, ea); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_ori_32_ix(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_32(m68k); + UINT32 ea = EA_AY_IX_32(m68k); + UINT32 res = src | m68ki_read_32(m68k, ea); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_ori_32_aw(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_32(m68k); + UINT32 ea = EA_AW_32(m68k); + UINT32 res = src | m68ki_read_32(m68k, ea); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_ori_32_al(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_32(m68k); + UINT32 ea = EA_AL_32(m68k); + UINT32 res = src | m68ki_read_32(m68k, ea); + + m68ki_write_32(m68k, ea, res); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_ori_16_toc(m68ki_cpu_core *m68k) +{ + m68ki_set_ccr(m68k, m68ki_get_ccr(m68k) | OPER_I_16(m68k)); +} + + +static void m68k_op_ori_16_tos(m68ki_cpu_core *m68k) +{ + if(m68k->s_flag) + { + UINT32 src = OPER_I_16(m68k); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_set_sr(m68k, m68ki_get_sr(m68k) | src); + return; + } + m68ki_exception_privilege_violation(m68k); +} + + +static void m68k_op_pack_16_rr(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + /* Note: DX and DY are reversed in Motorola's docs */ + UINT32 src = DY + OPER_I_16(m68k); + UINT32* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | ((src >> 4) & 0x00f0) | (src & 0x000f); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_pack_16_mm_ax7(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + /* Note: AX and AY are reversed in Motorola's docs */ + UINT32 ea_src = EA_AY_PD_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea_src); + ea_src = EA_AY_PD_8(m68k); + src = ((src << 8) | m68ki_read_8(m68k, ea_src)) + OPER_I_16(m68k); + + m68ki_write_8(m68k, EA_A7_PD_8(m68k), ((src >> 4) & 0x00f0) | (src & 0x000f)); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_pack_16_mm_ay7(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + /* Note: AX and AY are reversed in Motorola's docs */ + UINT32 ea_src = EA_A7_PD_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea_src); + ea_src = EA_A7_PD_8(m68k); + src = ((src << 8) | m68ki_read_8(m68k, ea_src)) + OPER_I_16(m68k); + + m68ki_write_8(m68k, EA_AX_PD_8(m68k), ((src >> 4) & 0x00f0) | (src & 0x000f)); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_pack_16_mm_axy7(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 ea_src = EA_A7_PD_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea_src); + ea_src = EA_A7_PD_8(m68k); + src = ((src << 8) | m68ki_read_8(m68k, ea_src)) + OPER_I_16(m68k); + + m68ki_write_8(m68k, EA_A7_PD_8(m68k), ((src >> 4) & 0x00f0) | (src & 0x000f)); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_pack_16_mm(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + /* Note: AX and AY are reversed in Motorola's docs */ + UINT32 ea_src = EA_AY_PD_8(m68k); + UINT32 src = m68ki_read_8(m68k, ea_src); + ea_src = EA_AY_PD_8(m68k); + src = ((src << 8) | m68ki_read_8(m68k, ea_src)) + OPER_I_16(m68k); + + m68ki_write_8(m68k, EA_AX_PD_8(m68k), ((src >> 4) & 0x00f0) | (src & 0x000f)); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_pea_32_ai(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_AI_32(m68k); + + m68ki_push_32(m68k, ea); +} + + +static void m68k_op_pea_32_di(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_DI_32(m68k); + + m68ki_push_32(m68k, ea); +} + + +static void m68k_op_pea_32_ix(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_IX_32(m68k); + + m68ki_push_32(m68k, ea); +} + + +static void m68k_op_pea_32_aw(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AW_32(m68k); + + m68ki_push_32(m68k, ea); +} + + +static void m68k_op_pea_32_al(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AL_32(m68k); + + m68ki_push_32(m68k, ea); +} + + +static void m68k_op_pea_32_pcdi(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_PCDI_32(m68k); + + m68ki_push_32(m68k, ea); +} + + +static void m68k_op_pea_32_pcix(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_PCIX_32(m68k); + + m68ki_push_32(m68k, ea); +} + + +static void m68k_op_pflush_32(m68ki_cpu_core *m68k) +{ + m68ki_exception_1111(m68k); +} + + +static void m68k_op_pmmu_32(m68ki_cpu_core *m68k) +{ + { + m68ki_exception_1111(m68k); + } +} + + +static void m68k_op_reset(m68ki_cpu_core *m68k) +{ + if(m68k->s_flag) + { + m68k->remaining_cycles -= m68k->cyc_reset; + return; + } + m68ki_exception_privilege_violation(m68k); +} + + +static void m68k_op_ror_8_s(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 orig_shift = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 shift = orig_shift & 7; + UINT32 src = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = ROR_8(src, shift); + + if(orig_shift != 0) + m68k->remaining_cycles -= orig_shift<cyc_shift; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = src << (9-orig_shift); + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_ror_16_s(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 shift = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 src = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = ROR_16(src, shift); + + if(shift != 0) + m68k->remaining_cycles -= shift<cyc_shift; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = src << (9-shift); + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_ror_32_s(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 shift = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT64 src = *r_dst; + UINT32 res = ROR_32(src, shift); + + if(shift != 0) + m68k->remaining_cycles -= shift<cyc_shift; + + *r_dst = res; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = src << (9-shift); + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_ror_8_r(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 orig_shift = DX & 0x3f; + UINT32 shift = orig_shift & 7; + UINT32 src = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = ROR_8(src, shift); + + if(orig_shift != 0) + { + m68k->remaining_cycles -= orig_shift<cyc_shift; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + m68k->c_flag = src << (8-((shift-1)&7)); + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + m68k->c_flag = CFLAG_CLEAR; + m68k->n_flag = NFLAG_8(src); + m68k->not_z_flag = src; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_ror_16_r(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 orig_shift = DX & 0x3f; + UINT32 shift = orig_shift & 15; + UINT32 src = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = ROR_16(src, shift); + + if(orig_shift != 0) + { + m68k->remaining_cycles -= orig_shift<cyc_shift; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + m68k->c_flag = (src >> ((shift - 1) & 15)) << 8; + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + m68k->c_flag = CFLAG_CLEAR; + m68k->n_flag = NFLAG_16(src); + m68k->not_z_flag = src; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_ror_32_r(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 orig_shift = DX & 0x3f; + UINT32 shift = orig_shift & 31; + UINT64 src = *r_dst; + UINT32 res = ROR_32(src, shift); + + if(orig_shift != 0) + { + m68k->remaining_cycles -= orig_shift<cyc_shift; + + *r_dst = res; + m68k->c_flag = (src >> ((shift - 1) & 31)) << 8; + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + m68k->c_flag = CFLAG_CLEAR; + m68k->n_flag = NFLAG_32(src); + m68k->not_z_flag = src; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_ror_16_ai(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_AI_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = ROR_16(src, 1); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = src << 8; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_ror_16_pi(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PI_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = ROR_16(src, 1); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = src << 8; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_ror_16_pd(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PD_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = ROR_16(src, 1); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = src << 8; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_ror_16_di(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_DI_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = ROR_16(src, 1); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = src << 8; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_ror_16_ix(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_IX_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = ROR_16(src, 1); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = src << 8; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_ror_16_aw(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AW_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = ROR_16(src, 1); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = src << 8; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_ror_16_al(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AL_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = ROR_16(src, 1); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = src << 8; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_rol_8_s(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 orig_shift = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 shift = orig_shift & 7; + UINT32 src = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = ROL_8(src, shift); + + if(orig_shift != 0) + m68k->remaining_cycles -= orig_shift<cyc_shift; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->c_flag = src << orig_shift; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_rol_16_s(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 shift = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 src = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = ROL_16(src, shift); + + if(shift != 0) + m68k->remaining_cycles -= shift<cyc_shift; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = src >> (8-shift); + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_rol_32_s(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 shift = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT64 src = *r_dst; + UINT32 res = ROL_32(src, shift); + + if(shift != 0) + m68k->remaining_cycles -= shift<cyc_shift; + + *r_dst = res; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->c_flag = src >> (24-shift); + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_rol_8_r(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 orig_shift = DX & 0x3f; + UINT32 shift = orig_shift & 7; + UINT32 src = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = ROL_8(src, shift); + + if(orig_shift != 0) + { + m68k->remaining_cycles -= orig_shift<cyc_shift; + + if(shift != 0) + { + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + m68k->c_flag = src << shift; + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + return; + } + m68k->c_flag = (src & 1)<<8; + m68k->n_flag = NFLAG_8(src); + m68k->not_z_flag = src; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + m68k->c_flag = CFLAG_CLEAR; + m68k->n_flag = NFLAG_8(src); + m68k->not_z_flag = src; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_rol_16_r(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 orig_shift = DX & 0x3f; + UINT32 shift = orig_shift & 15; + UINT32 src = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = MASK_OUT_ABOVE_16(ROL_16(src, shift)); + + if(orig_shift != 0) + { + m68k->remaining_cycles -= orig_shift<cyc_shift; + + if(shift != 0) + { + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + m68k->c_flag = (src << shift) >> 8; + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + return; + } + m68k->c_flag = (src & 1)<<8; + m68k->n_flag = NFLAG_16(src); + m68k->not_z_flag = src; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + m68k->c_flag = CFLAG_CLEAR; + m68k->n_flag = NFLAG_16(src); + m68k->not_z_flag = src; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_rol_32_r(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 orig_shift = DX & 0x3f; + UINT32 shift = orig_shift & 31; + UINT64 src = *r_dst; + UINT32 res = ROL_32(src, shift); + + if(orig_shift != 0) + { + m68k->remaining_cycles -= orig_shift<cyc_shift; + + *r_dst = res; + + m68k->c_flag = (src >> ((32 - shift) & 0x1f)) << 8; + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + m68k->c_flag = CFLAG_CLEAR; + m68k->n_flag = NFLAG_32(src); + m68k->not_z_flag = src; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_rol_16_ai(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_AI_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = MASK_OUT_ABOVE_16(ROL_16(src, 1)); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = src >> 7; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_rol_16_pi(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PI_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = MASK_OUT_ABOVE_16(ROL_16(src, 1)); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = src >> 7; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_rol_16_pd(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PD_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = MASK_OUT_ABOVE_16(ROL_16(src, 1)); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = src >> 7; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_rol_16_di(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_DI_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = MASK_OUT_ABOVE_16(ROL_16(src, 1)); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = src >> 7; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_rol_16_ix(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_IX_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = MASK_OUT_ABOVE_16(ROL_16(src, 1)); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = src >> 7; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_rol_16_aw(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AW_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = MASK_OUT_ABOVE_16(ROL_16(src, 1)); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = src >> 7; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_rol_16_al(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AL_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = MASK_OUT_ABOVE_16(ROL_16(src, 1)); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->c_flag = src >> 7; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_roxr_8_s(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 shift = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 src = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = ROR_9(src | (XFLAG_AS_1(m68k) << 8), shift); + + if(shift != 0) + m68k->remaining_cycles -= shift<cyc_shift; + + m68k->c_flag = m68k->x_flag = res; + res = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_roxr_16_s(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 shift = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 src = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = ROR_17(src | (XFLAG_AS_1(m68k) << 16), shift); + + if(shift != 0) + m68k->remaining_cycles -= shift<cyc_shift; + + m68k->c_flag = m68k->x_flag = res >> 8; + res = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_roxr_32_s(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 shift = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT64 src = *r_dst; + UINT64 res = src | (((UINT64)XFLAG_AS_1(m68k)) << 32); + + if(shift != 0) + m68k->remaining_cycles -= shift<cyc_shift; + + res = ROR_33_64(res, shift); + + m68k->c_flag = m68k->x_flag = res >> 24; + res = MASK_OUT_ABOVE_32(res); + + *r_dst = res; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_roxr_8_r(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 orig_shift = DX & 0x3f; + + if(orig_shift != 0) + { + UINT32 shift = orig_shift % 9; + UINT32 src = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = ROR_9(src | (XFLAG_AS_1(m68k) << 8), shift); + + m68k->remaining_cycles -= orig_shift<cyc_shift; + + m68k->c_flag = m68k->x_flag = res; + res = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + m68k->c_flag = m68k->x_flag; + m68k->n_flag = NFLAG_8(*r_dst); + m68k->not_z_flag = MASK_OUT_ABOVE_8(*r_dst); + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_roxr_16_r(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 orig_shift = DX & 0x3f; + + if(orig_shift != 0) + { + UINT32 shift = orig_shift % 17; + UINT32 src = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = ROR_17(src | (XFLAG_AS_1(m68k) << 16), shift); + + m68k->remaining_cycles -= orig_shift<cyc_shift; + + m68k->c_flag = m68k->x_flag = res >> 8; + res = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + m68k->c_flag = m68k->x_flag; + m68k->n_flag = NFLAG_16(*r_dst); + m68k->not_z_flag = MASK_OUT_ABOVE_16(*r_dst); + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_roxr_32_r(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 orig_shift = DX & 0x3f; + + if(orig_shift != 0) + { + UINT32 shift = orig_shift % 33; + UINT64 src = *r_dst; + UINT64 res = src | (((UINT64)XFLAG_AS_1(m68k)) << 32); + + res = ROR_33_64(res, shift); + + m68k->remaining_cycles -= orig_shift<cyc_shift; + + m68k->c_flag = m68k->x_flag = res >> 24; + res = MASK_OUT_ABOVE_32(res); + + *r_dst = res; + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + m68k->c_flag = m68k->x_flag; + m68k->n_flag = NFLAG_32(*r_dst); + m68k->not_z_flag = *r_dst; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_roxr_16_ai(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_AI_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = ROR_17(src | (XFLAG_AS_1(m68k) << 16), 1); + + m68k->c_flag = m68k->x_flag = res >> 8; + res = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_roxr_16_pi(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PI_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = ROR_17(src | (XFLAG_AS_1(m68k) << 16), 1); + + m68k->c_flag = m68k->x_flag = res >> 8; + res = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_roxr_16_pd(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PD_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = ROR_17(src | (XFLAG_AS_1(m68k) << 16), 1); + + m68k->c_flag = m68k->x_flag = res >> 8; + res = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_roxr_16_di(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_DI_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = ROR_17(src | (XFLAG_AS_1(m68k) << 16), 1); + + m68k->c_flag = m68k->x_flag = res >> 8; + res = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_roxr_16_ix(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_IX_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = ROR_17(src | (XFLAG_AS_1(m68k) << 16), 1); + + m68k->c_flag = m68k->x_flag = res >> 8; + res = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_roxr_16_aw(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AW_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = ROR_17(src | (XFLAG_AS_1(m68k) << 16), 1); + + m68k->c_flag = m68k->x_flag = res >> 8; + res = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_roxr_16_al(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AL_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = ROR_17(src | (XFLAG_AS_1(m68k) << 16), 1); + + m68k->c_flag = m68k->x_flag = res >> 8; + res = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_roxl_8_s(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 shift = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 src = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = ROL_9(src | (XFLAG_AS_1(m68k) << 8), shift); + + if(shift != 0) + m68k->remaining_cycles -= shift<cyc_shift; + + m68k->c_flag = m68k->x_flag = res; + res = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_roxl_16_s(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 shift = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 src = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = ROL_17(src | (XFLAG_AS_1(m68k) << 16), shift); + + if(shift != 0) + m68k->remaining_cycles -= shift<cyc_shift; + + m68k->c_flag = m68k->x_flag = res >> 8; + res = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_roxl_32_s(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 shift = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT64 src = *r_dst; + UINT64 res = src | (((UINT64)XFLAG_AS_1(m68k)) << 32); + + if(shift != 0) + m68k->remaining_cycles -= shift<cyc_shift; + + res = ROL_33_64(res, shift); + + m68k->c_flag = m68k->x_flag = res >> 24; + res = MASK_OUT_ABOVE_32(res); + + *r_dst = res; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_roxl_8_r(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 orig_shift = DX & 0x3f; + + + if(orig_shift != 0) + { + UINT32 shift = orig_shift % 9; + UINT32 src = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = ROL_9(src | (XFLAG_AS_1(m68k) << 8), shift); + + m68k->remaining_cycles -= orig_shift<cyc_shift; + + m68k->c_flag = m68k->x_flag = res; + res = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + m68k->c_flag = m68k->x_flag; + m68k->n_flag = NFLAG_8(*r_dst); + m68k->not_z_flag = MASK_OUT_ABOVE_8(*r_dst); + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_roxl_16_r(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 orig_shift = DX & 0x3f; + + if(orig_shift != 0) + { + UINT32 shift = orig_shift % 17; + UINT32 src = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = ROL_17(src | (XFLAG_AS_1(m68k) << 16), shift); + + m68k->remaining_cycles -= orig_shift<cyc_shift; + + m68k->c_flag = m68k->x_flag = res >> 8; + res = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + m68k->c_flag = m68k->x_flag; + m68k->n_flag = NFLAG_16(*r_dst); + m68k->not_z_flag = MASK_OUT_ABOVE_16(*r_dst); + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_roxl_32_r(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 orig_shift = DX & 0x3f; + + if(orig_shift != 0) + { + UINT32 shift = orig_shift % 33; + UINT64 src = *r_dst; + UINT64 res = src | (((UINT64)XFLAG_AS_1(m68k)) << 32); + + res = ROL_33_64(res, shift); + + m68k->remaining_cycles -= orig_shift<cyc_shift; + + m68k->c_flag = m68k->x_flag = res >> 24; + res = MASK_OUT_ABOVE_32(res); + + *r_dst = res; + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + return; + } + + m68k->c_flag = m68k->x_flag; + m68k->n_flag = NFLAG_32(*r_dst); + m68k->not_z_flag = *r_dst; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_roxl_16_ai(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_AI_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = ROL_17(src | (XFLAG_AS_1(m68k) << 16), 1); + + m68k->c_flag = m68k->x_flag = res >> 8; + res = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_roxl_16_pi(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PI_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = ROL_17(src | (XFLAG_AS_1(m68k) << 16), 1); + + m68k->c_flag = m68k->x_flag = res >> 8; + res = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_roxl_16_pd(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PD_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = ROL_17(src | (XFLAG_AS_1(m68k) << 16), 1); + + m68k->c_flag = m68k->x_flag = res >> 8; + res = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_roxl_16_di(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_DI_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = ROL_17(src | (XFLAG_AS_1(m68k) << 16), 1); + + m68k->c_flag = m68k->x_flag = res >> 8; + res = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_roxl_16_ix(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_IX_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = ROL_17(src | (XFLAG_AS_1(m68k) << 16), 1); + + m68k->c_flag = m68k->x_flag = res >> 8; + res = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_roxl_16_aw(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AW_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = ROL_17(src | (XFLAG_AS_1(m68k) << 16), 1); + + m68k->c_flag = m68k->x_flag = res >> 8; + res = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_roxl_16_al(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AL_16(m68k); + UINT32 src = m68ki_read_16(m68k, ea); + UINT32 res = ROL_17(src | (XFLAG_AS_1(m68k) << 16), 1); + + m68k->c_flag = m68k->x_flag = res >> 8; + res = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(m68k, ea, res); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_rtd_32(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_010_PLUS(m68k->cpu_type)) + { + UINT32 new_pc = m68ki_pull_32(m68k); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16(m68k))); + m68ki_jump(m68k, new_pc); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_rte_32(m68ki_cpu_core *m68k) +{ + if(m68k->s_flag) + { + UINT32 new_sr; + UINT32 new_pc; + UINT32 format_word; + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + + if(CPU_TYPE_IS_000(m68k->cpu_type)) + { + new_sr = m68ki_pull_16(m68k); + new_pc = m68ki_pull_32(m68k); + m68ki_jump(m68k, new_pc); + m68ki_set_sr(m68k, new_sr); + +#if M68K_EMULATE_ADDRESS_ERROR + m68k->instr_mode = INSTRUCTION_YES; + m68k->run_mode = RUN_MODE_NORMAL; +#endif + + return; + } + + if(CPU_TYPE_IS_010(m68k->cpu_type)) + { + format_word = m68ki_read_16(m68k, REG_A[7]+6) >> 12; + if(format_word == 0) + { + new_sr = m68ki_pull_16(m68k); + new_pc = m68ki_pull_32(m68k); + m68ki_fake_pull_16(m68k); /* format word */ + m68ki_jump(m68k, new_pc); + m68ki_set_sr(m68k, new_sr); +#if M68K_EMULATE_ADDRESS_ERROR + m68k->instr_mode = INSTRUCTION_YES; + m68k->run_mode = RUN_MODE_NORMAL; +#endif + return; + } +#if M68K_EMULATE_ADDRESS_ERROR + m68k->instr_mode = INSTRUCTION_YES; + m68k->run_mode = RUN_MODE_NORMAL; +#endif + /* Not handling bus fault (9) */ + m68ki_exception_format_error(m68k); + return; + } + + /* Otherwise it's 020 */ +rte_loop: + format_word = m68ki_read_16(m68k, REG_A[7]+6) >> 12; + switch(format_word) + { + case 0: /* Normal */ + new_sr = m68ki_pull_16(m68k); + new_pc = m68ki_pull_32(m68k); + m68ki_fake_pull_16(m68k); /* format word */ + m68ki_jump(m68k, new_pc); + m68ki_set_sr(m68k, new_sr); +#if M68K_EMULATE_ADDRESS_ERROR + m68k->instr_mode = INSTRUCTION_YES; + m68k->run_mode = RUN_MODE_NORMAL; +#endif + return; + case 1: /* Throwaway */ + new_sr = m68ki_pull_16(m68k); + m68ki_fake_pull_32(m68k); /* program counter */ + m68ki_fake_pull_16(m68k); /* format word */ + m68ki_set_sr_noint(m68k, new_sr); + goto rte_loop; + case 2: /* Trap */ + new_sr = m68ki_pull_16(m68k); + new_pc = m68ki_pull_32(m68k); + m68ki_fake_pull_16(m68k); /* format word */ + m68ki_fake_pull_32(m68k); /* address */ + m68ki_jump(m68k, new_pc); + m68ki_set_sr(m68k, new_sr); +#if M68K_EMULATE_ADDRESS_ERROR + m68k->instr_mode = INSTRUCTION_YES; + m68k->run_mode = RUN_MODE_NORMAL; +#endif + return; + } + /* Not handling long or short bus fault */ +#if M68K_EMULATE_ADDRESS_ERROR + m68k->instr_mode = INSTRUCTION_YES; + m68k->run_mode = RUN_MODE_NORMAL; +#endif + m68ki_exception_format_error(m68k); + return; + } + m68ki_exception_privilege_violation(m68k); +} + + +static void m68k_op_rtm_32(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_020_VARIANT(m68k->cpu_type)) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_rtr_32(m68ki_cpu_core *m68k) +{ + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_set_ccr(m68k, m68ki_pull_16(m68k)); + m68ki_jump(m68k, m68ki_pull_32(m68k)); +} + + +static void m68k_op_rts_32(m68ki_cpu_core *m68k) +{ + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_jump(m68k, m68ki_pull_32(m68k)); +} + + +static void m68k_op_sbcd_8_rr(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = DY; + UINT32 dst = *r_dst; + UINT32 res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1(m68k); + +// m68k->v_flag = ~res; /* Undefined V behavior */ + m68k->v_flag = VFLAG_CLEAR; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to assume cleared. */ + + if(res > 9) + res -= 6; + res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src); + if(res > 0x99) + { + res += 0xa0; + m68k->x_flag = m68k->c_flag = CFLAG_SET; + m68k->n_flag = NFLAG_SET; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to follow carry. */ + } + else + m68k->n_flag = m68k->x_flag = m68k->c_flag = 0; + + res = MASK_OUT_ABOVE_8(res); + +// m68k->v_flag &= res; /* Undefined V behavior part II */ +// m68k->n_flag = NFLAG_8(res); /* Undefined N behavior */ + m68k->not_z_flag |= res; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; +} + + +static void m68k_op_sbcd_8_mm_ax7(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_AY_PD_8(m68k); + UINT32 ea = EA_A7_PD_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1(m68k); + +// m68k->v_flag = ~res; /* Undefined V behavior */ + m68k->v_flag = VFLAG_CLEAR; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to return zero. */ + + if(res > 9) + res -= 6; + res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src); + if(res > 0x99) + { + res += 0xa0; + m68k->x_flag = m68k->c_flag = CFLAG_SET; + m68k->n_flag = NFLAG_SET; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to follow carry. */ + } + else + m68k->n_flag = m68k->x_flag = m68k->c_flag = 0; + + res = MASK_OUT_ABOVE_8(res); + +// m68k->v_flag &= res; /* Undefined V behavior part II */ +// m68k->n_flag = NFLAG_8(res); /* Undefined N behavior */ + m68k->not_z_flag |= res; + + m68ki_write_8(m68k, ea, res); +} + + +static void m68k_op_sbcd_8_mm_ay7(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_A7_PD_8(m68k); + UINT32 ea = EA_AX_PD_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1(m68k); + +// m68k->v_flag = ~res; /* Undefined V behavior */ + m68k->v_flag = VFLAG_CLEAR; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to return zero. */ + + if(res > 9) + res -= 6; + res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src); + if(res > 0x99) + { + res += 0xa0; + m68k->x_flag = m68k->c_flag = CFLAG_SET; + m68k->n_flag = NFLAG_SET; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to follow carry. */ + } + else + m68k->n_flag = m68k->x_flag = m68k->c_flag = 0; + + res = MASK_OUT_ABOVE_8(res); + +// m68k->v_flag &= res; /* Undefined V behavior part II */ +// m68k->n_flag = NFLAG_8(res); /* Undefined N behavior */ + m68k->not_z_flag |= res; + + m68ki_write_8(m68k, ea, res); +} + + +static void m68k_op_sbcd_8_mm_axy7(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_A7_PD_8(m68k); + UINT32 ea = EA_A7_PD_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1(m68k); + +// m68k->v_flag = ~res; /* Undefined V behavior */ + m68k->v_flag = VFLAG_CLEAR; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to return zero. */ + + if(res > 9) + res -= 6; + res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src); + if(res > 0x99) + { + res += 0xa0; + m68k->x_flag = m68k->c_flag = CFLAG_SET; + m68k->n_flag = NFLAG_SET; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to follow carry. */ + } + else + m68k->n_flag = m68k->x_flag = m68k->c_flag = 0; + + res = MASK_OUT_ABOVE_8(res); + +// m68k->v_flag &= res; /* Undefined V behavior part II */ +// m68k->n_flag = NFLAG_8(res); /* Undefined N behavior */ + m68k->not_z_flag |= res; + + m68ki_write_8(m68k, ea, res); +} + + +static void m68k_op_sbcd_8_mm(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_AY_PD_8(m68k); + UINT32 ea = EA_AX_PD_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1(m68k); + +// m68k->v_flag = ~res; /* Undefined V behavior */ + m68k->v_flag = VFLAG_CLEAR; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to return zero. */ + + if(res > 9) + res -= 6; + res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src); + if(res > 0x99) + { + res += 0xa0; + m68k->x_flag = m68k->c_flag = CFLAG_SET; + m68k->n_flag = NFLAG_SET; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to follow carry. */ + } + else + m68k->n_flag = m68k->x_flag = m68k->c_flag = 0; + + res = MASK_OUT_ABOVE_8(res); + +// m68k->v_flag &= res; /* Undefined V behavior part II */ +// m68k->n_flag = NFLAG_8(res); /* Undefined N behavior */ + m68k->not_z_flag |= res; + + m68ki_write_8(m68k, ea, res); +} + + +static void m68k_op_st_8_d(m68ki_cpu_core *m68k) +{ + DY |= 0xff; +} + + +static void m68k_op_st_8_ai(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_AI_8(m68k), 0xff); +} + + +static void m68k_op_st_8_pi(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_PI_8(m68k), 0xff); +} + + +static void m68k_op_st_8_pi7(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_A7_PI_8(m68k), 0xff); +} + + +static void m68k_op_st_8_pd(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_PD_8(m68k), 0xff); +} + + +static void m68k_op_st_8_pd7(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_A7_PD_8(m68k), 0xff); +} + + +static void m68k_op_st_8_di(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_DI_8(m68k), 0xff); +} + + +static void m68k_op_st_8_ix(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_IX_8(m68k), 0xff); +} + + +static void m68k_op_st_8_aw(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AW_8(m68k), 0xff); +} + + +static void m68k_op_st_8_al(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AL_8(m68k), 0xff); +} + + +static void m68k_op_sf_8_d(m68ki_cpu_core *m68k) +{ + DY &= 0xffffff00; +} + + +static void m68k_op_sf_8_ai(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_AI_8(m68k), 0); +} + + +static void m68k_op_sf_8_pi(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_PI_8(m68k), 0); +} + + +static void m68k_op_sf_8_pi7(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_A7_PI_8(m68k), 0); +} + + +static void m68k_op_sf_8_pd(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_PD_8(m68k), 0); +} + + +static void m68k_op_sf_8_pd7(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_A7_PD_8(m68k), 0); +} + + +static void m68k_op_sf_8_di(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_DI_8(m68k), 0); +} + + +static void m68k_op_sf_8_ix(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_IX_8(m68k), 0); +} + + +static void m68k_op_sf_8_aw(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AW_8(m68k), 0); +} + + +static void m68k_op_sf_8_al(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AL_8(m68k), 0); +} + + +static void m68k_op_shi_8_d(m68ki_cpu_core *m68k) +{ + if(COND_HI(m68k)) + { + DY |= 0xff; + m68k->remaining_cycles -= m68k->cyc_scc_r_true; + return; + } + DY &= 0xffffff00; +} + + +static void m68k_op_sls_8_d(m68ki_cpu_core *m68k) +{ + if(COND_LS(m68k)) + { + DY |= 0xff; + m68k->remaining_cycles -= m68k->cyc_scc_r_true; + return; + } + DY &= 0xffffff00; +} + + +static void m68k_op_scc_8_d(m68ki_cpu_core *m68k) +{ + if(COND_CC(m68k)) + { + DY |= 0xff; + m68k->remaining_cycles -= m68k->cyc_scc_r_true; + return; + } + DY &= 0xffffff00; +} + + +static void m68k_op_scs_8_d(m68ki_cpu_core *m68k) +{ + if(COND_CS(m68k)) + { + DY |= 0xff; + m68k->remaining_cycles -= m68k->cyc_scc_r_true; + return; + } + DY &= 0xffffff00; +} + + +static void m68k_op_sne_8_d(m68ki_cpu_core *m68k) +{ + if(COND_NE(m68k)) + { + DY |= 0xff; + m68k->remaining_cycles -= m68k->cyc_scc_r_true; + return; + } + DY &= 0xffffff00; +} + + +static void m68k_op_seq_8_d(m68ki_cpu_core *m68k) +{ + if(COND_EQ(m68k)) + { + DY |= 0xff; + m68k->remaining_cycles -= m68k->cyc_scc_r_true; + return; + } + DY &= 0xffffff00; +} + + +static void m68k_op_svc_8_d(m68ki_cpu_core *m68k) +{ + if(COND_VC(m68k)) + { + DY |= 0xff; + m68k->remaining_cycles -= m68k->cyc_scc_r_true; + return; + } + DY &= 0xffffff00; +} + + +static void m68k_op_svs_8_d(m68ki_cpu_core *m68k) +{ + if(COND_VS(m68k)) + { + DY |= 0xff; + m68k->remaining_cycles -= m68k->cyc_scc_r_true; + return; + } + DY &= 0xffffff00; +} + + +static void m68k_op_spl_8_d(m68ki_cpu_core *m68k) +{ + if(COND_PL(m68k)) + { + DY |= 0xff; + m68k->remaining_cycles -= m68k->cyc_scc_r_true; + return; + } + DY &= 0xffffff00; +} + + +static void m68k_op_smi_8_d(m68ki_cpu_core *m68k) +{ + if(COND_MI(m68k)) + { + DY |= 0xff; + m68k->remaining_cycles -= m68k->cyc_scc_r_true; + return; + } + DY &= 0xffffff00; +} + + +static void m68k_op_sge_8_d(m68ki_cpu_core *m68k) +{ + if(COND_GE(m68k)) + { + DY |= 0xff; + m68k->remaining_cycles -= m68k->cyc_scc_r_true; + return; + } + DY &= 0xffffff00; +} + + +static void m68k_op_slt_8_d(m68ki_cpu_core *m68k) +{ + if(COND_LT(m68k)) + { + DY |= 0xff; + m68k->remaining_cycles -= m68k->cyc_scc_r_true; + return; + } + DY &= 0xffffff00; +} + + +static void m68k_op_sgt_8_d(m68ki_cpu_core *m68k) +{ + if(COND_GT(m68k)) + { + DY |= 0xff; + m68k->remaining_cycles -= m68k->cyc_scc_r_true; + return; + } + DY &= 0xffffff00; +} + + +static void m68k_op_sle_8_d(m68ki_cpu_core *m68k) +{ + if(COND_LE(m68k)) + { + DY |= 0xff; + m68k->remaining_cycles -= m68k->cyc_scc_r_true; + return; + } + DY &= 0xffffff00; +} + + +static void m68k_op_shi_8_ai(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_AI_8(m68k), COND_HI(m68k) ? 0xff : 0); +} + + +static void m68k_op_shi_8_pi(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_PI_8(m68k), COND_HI(m68k) ? 0xff : 0); +} + + +static void m68k_op_shi_8_pi7(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_A7_PI_8(m68k), COND_HI(m68k) ? 0xff : 0); +} + + +static void m68k_op_shi_8_pd(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_PD_8(m68k), COND_HI(m68k) ? 0xff : 0); +} + + +static void m68k_op_shi_8_pd7(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_A7_PD_8(m68k), COND_HI(m68k) ? 0xff : 0); +} + + +static void m68k_op_shi_8_di(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_DI_8(m68k), COND_HI(m68k) ? 0xff : 0); +} + + +static void m68k_op_shi_8_ix(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_IX_8(m68k), COND_HI(m68k) ? 0xff : 0); +} + + +static void m68k_op_shi_8_aw(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AW_8(m68k), COND_HI(m68k) ? 0xff : 0); +} + + +static void m68k_op_shi_8_al(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AL_8(m68k), COND_HI(m68k) ? 0xff : 0); +} + + +static void m68k_op_sls_8_ai(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_AI_8(m68k), COND_LS(m68k) ? 0xff : 0); +} + + +static void m68k_op_sls_8_pi(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_PI_8(m68k), COND_LS(m68k) ? 0xff : 0); +} + + +static void m68k_op_sls_8_pi7(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_A7_PI_8(m68k), COND_LS(m68k) ? 0xff : 0); +} + + +static void m68k_op_sls_8_pd(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_PD_8(m68k), COND_LS(m68k) ? 0xff : 0); +} + + +static void m68k_op_sls_8_pd7(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_A7_PD_8(m68k), COND_LS(m68k) ? 0xff : 0); +} + + +static void m68k_op_sls_8_di(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_DI_8(m68k), COND_LS(m68k) ? 0xff : 0); +} + + +static void m68k_op_sls_8_ix(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_IX_8(m68k), COND_LS(m68k) ? 0xff : 0); +} + + +static void m68k_op_sls_8_aw(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AW_8(m68k), COND_LS(m68k) ? 0xff : 0); +} + + +static void m68k_op_sls_8_al(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AL_8(m68k), COND_LS(m68k) ? 0xff : 0); +} + + +static void m68k_op_scc_8_ai(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_AI_8(m68k), COND_CC(m68k) ? 0xff : 0); +} + + +static void m68k_op_scc_8_pi(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_PI_8(m68k), COND_CC(m68k) ? 0xff : 0); +} + + +static void m68k_op_scc_8_pi7(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_A7_PI_8(m68k), COND_CC(m68k) ? 0xff : 0); +} + + +static void m68k_op_scc_8_pd(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_PD_8(m68k), COND_CC(m68k) ? 0xff : 0); +} + + +static void m68k_op_scc_8_pd7(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_A7_PD_8(m68k), COND_CC(m68k) ? 0xff : 0); +} + + +static void m68k_op_scc_8_di(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_DI_8(m68k), COND_CC(m68k) ? 0xff : 0); +} + + +static void m68k_op_scc_8_ix(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_IX_8(m68k), COND_CC(m68k) ? 0xff : 0); +} + + +static void m68k_op_scc_8_aw(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AW_8(m68k), COND_CC(m68k) ? 0xff : 0); +} + + +static void m68k_op_scc_8_al(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AL_8(m68k), COND_CC(m68k) ? 0xff : 0); +} + + +static void m68k_op_scs_8_ai(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_AI_8(m68k), COND_CS(m68k) ? 0xff : 0); +} + + +static void m68k_op_scs_8_pi(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_PI_8(m68k), COND_CS(m68k) ? 0xff : 0); +} + + +static void m68k_op_scs_8_pi7(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_A7_PI_8(m68k), COND_CS(m68k) ? 0xff : 0); +} + + +static void m68k_op_scs_8_pd(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_PD_8(m68k), COND_CS(m68k) ? 0xff : 0); +} + + +static void m68k_op_scs_8_pd7(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_A7_PD_8(m68k), COND_CS(m68k) ? 0xff : 0); +} + + +static void m68k_op_scs_8_di(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_DI_8(m68k), COND_CS(m68k) ? 0xff : 0); +} + + +static void m68k_op_scs_8_ix(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_IX_8(m68k), COND_CS(m68k) ? 0xff : 0); +} + + +static void m68k_op_scs_8_aw(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AW_8(m68k), COND_CS(m68k) ? 0xff : 0); +} + + +static void m68k_op_scs_8_al(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AL_8(m68k), COND_CS(m68k) ? 0xff : 0); +} + + +static void m68k_op_sne_8_ai(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_AI_8(m68k), COND_NE(m68k) ? 0xff : 0); +} + + +static void m68k_op_sne_8_pi(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_PI_8(m68k), COND_NE(m68k) ? 0xff : 0); +} + + +static void m68k_op_sne_8_pi7(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_A7_PI_8(m68k), COND_NE(m68k) ? 0xff : 0); +} + + +static void m68k_op_sne_8_pd(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_PD_8(m68k), COND_NE(m68k) ? 0xff : 0); +} + + +static void m68k_op_sne_8_pd7(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_A7_PD_8(m68k), COND_NE(m68k) ? 0xff : 0); +} + + +static void m68k_op_sne_8_di(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_DI_8(m68k), COND_NE(m68k) ? 0xff : 0); +} + + +static void m68k_op_sne_8_ix(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_IX_8(m68k), COND_NE(m68k) ? 0xff : 0); +} + + +static void m68k_op_sne_8_aw(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AW_8(m68k), COND_NE(m68k) ? 0xff : 0); +} + + +static void m68k_op_sne_8_al(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AL_8(m68k), COND_NE(m68k) ? 0xff : 0); +} + + +static void m68k_op_seq_8_ai(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_AI_8(m68k), COND_EQ(m68k) ? 0xff : 0); +} + + +static void m68k_op_seq_8_pi(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_PI_8(m68k), COND_EQ(m68k) ? 0xff : 0); +} + + +static void m68k_op_seq_8_pi7(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_A7_PI_8(m68k), COND_EQ(m68k) ? 0xff : 0); +} + + +static void m68k_op_seq_8_pd(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_PD_8(m68k), COND_EQ(m68k) ? 0xff : 0); +} + + +static void m68k_op_seq_8_pd7(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_A7_PD_8(m68k), COND_EQ(m68k) ? 0xff : 0); +} + + +static void m68k_op_seq_8_di(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_DI_8(m68k), COND_EQ(m68k) ? 0xff : 0); +} + + +static void m68k_op_seq_8_ix(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_IX_8(m68k), COND_EQ(m68k) ? 0xff : 0); +} + + +static void m68k_op_seq_8_aw(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AW_8(m68k), COND_EQ(m68k) ? 0xff : 0); +} + + +static void m68k_op_seq_8_al(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AL_8(m68k), COND_EQ(m68k) ? 0xff : 0); +} + + +static void m68k_op_svc_8_ai(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_AI_8(m68k), COND_VC(m68k) ? 0xff : 0); +} + + +static void m68k_op_svc_8_pi(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_PI_8(m68k), COND_VC(m68k) ? 0xff : 0); +} + + +static void m68k_op_svc_8_pi7(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_A7_PI_8(m68k), COND_VC(m68k) ? 0xff : 0); +} + + +static void m68k_op_svc_8_pd(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_PD_8(m68k), COND_VC(m68k) ? 0xff : 0); +} + + +static void m68k_op_svc_8_pd7(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_A7_PD_8(m68k), COND_VC(m68k) ? 0xff : 0); +} + + +static void m68k_op_svc_8_di(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_DI_8(m68k), COND_VC(m68k) ? 0xff : 0); +} + + +static void m68k_op_svc_8_ix(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_IX_8(m68k), COND_VC(m68k) ? 0xff : 0); +} + + +static void m68k_op_svc_8_aw(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AW_8(m68k), COND_VC(m68k) ? 0xff : 0); +} + + +static void m68k_op_svc_8_al(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AL_8(m68k), COND_VC(m68k) ? 0xff : 0); +} + + +static void m68k_op_svs_8_ai(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_AI_8(m68k), COND_VS(m68k) ? 0xff : 0); +} + + +static void m68k_op_svs_8_pi(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_PI_8(m68k), COND_VS(m68k) ? 0xff : 0); +} + + +static void m68k_op_svs_8_pi7(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_A7_PI_8(m68k), COND_VS(m68k) ? 0xff : 0); +} + + +static void m68k_op_svs_8_pd(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_PD_8(m68k), COND_VS(m68k) ? 0xff : 0); +} + + +static void m68k_op_svs_8_pd7(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_A7_PD_8(m68k), COND_VS(m68k) ? 0xff : 0); +} + + +static void m68k_op_svs_8_di(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_DI_8(m68k), COND_VS(m68k) ? 0xff : 0); +} + + +static void m68k_op_svs_8_ix(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_IX_8(m68k), COND_VS(m68k) ? 0xff : 0); +} + + +static void m68k_op_svs_8_aw(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AW_8(m68k), COND_VS(m68k) ? 0xff : 0); +} + + +static void m68k_op_svs_8_al(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AL_8(m68k), COND_VS(m68k) ? 0xff : 0); +} + + +static void m68k_op_spl_8_ai(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_AI_8(m68k), COND_PL(m68k) ? 0xff : 0); +} + + +static void m68k_op_spl_8_pi(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_PI_8(m68k), COND_PL(m68k) ? 0xff : 0); +} + + +static void m68k_op_spl_8_pi7(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_A7_PI_8(m68k), COND_PL(m68k) ? 0xff : 0); +} + + +static void m68k_op_spl_8_pd(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_PD_8(m68k), COND_PL(m68k) ? 0xff : 0); +} + + +static void m68k_op_spl_8_pd7(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_A7_PD_8(m68k), COND_PL(m68k) ? 0xff : 0); +} + + +static void m68k_op_spl_8_di(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_DI_8(m68k), COND_PL(m68k) ? 0xff : 0); +} + + +static void m68k_op_spl_8_ix(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_IX_8(m68k), COND_PL(m68k) ? 0xff : 0); +} + + +static void m68k_op_spl_8_aw(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AW_8(m68k), COND_PL(m68k) ? 0xff : 0); +} + + +static void m68k_op_spl_8_al(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AL_8(m68k), COND_PL(m68k) ? 0xff : 0); +} + + +static void m68k_op_smi_8_ai(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_AI_8(m68k), COND_MI(m68k) ? 0xff : 0); +} + + +static void m68k_op_smi_8_pi(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_PI_8(m68k), COND_MI(m68k) ? 0xff : 0); +} + + +static void m68k_op_smi_8_pi7(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_A7_PI_8(m68k), COND_MI(m68k) ? 0xff : 0); +} + + +static void m68k_op_smi_8_pd(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_PD_8(m68k), COND_MI(m68k) ? 0xff : 0); +} + + +static void m68k_op_smi_8_pd7(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_A7_PD_8(m68k), COND_MI(m68k) ? 0xff : 0); +} + + +static void m68k_op_smi_8_di(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_DI_8(m68k), COND_MI(m68k) ? 0xff : 0); +} + + +static void m68k_op_smi_8_ix(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_IX_8(m68k), COND_MI(m68k) ? 0xff : 0); +} + + +static void m68k_op_smi_8_aw(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AW_8(m68k), COND_MI(m68k) ? 0xff : 0); +} + + +static void m68k_op_smi_8_al(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AL_8(m68k), COND_MI(m68k) ? 0xff : 0); +} + + +static void m68k_op_sge_8_ai(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_AI_8(m68k), COND_GE(m68k) ? 0xff : 0); +} + + +static void m68k_op_sge_8_pi(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_PI_8(m68k), COND_GE(m68k) ? 0xff : 0); +} + + +static void m68k_op_sge_8_pi7(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_A7_PI_8(m68k), COND_GE(m68k) ? 0xff : 0); +} + + +static void m68k_op_sge_8_pd(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_PD_8(m68k), COND_GE(m68k) ? 0xff : 0); +} + + +static void m68k_op_sge_8_pd7(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_A7_PD_8(m68k), COND_GE(m68k) ? 0xff : 0); +} + + +static void m68k_op_sge_8_di(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_DI_8(m68k), COND_GE(m68k) ? 0xff : 0); +} + + +static void m68k_op_sge_8_ix(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_IX_8(m68k), COND_GE(m68k) ? 0xff : 0); +} + + +static void m68k_op_sge_8_aw(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AW_8(m68k), COND_GE(m68k) ? 0xff : 0); +} + + +static void m68k_op_sge_8_al(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AL_8(m68k), COND_GE(m68k) ? 0xff : 0); +} + + +static void m68k_op_slt_8_ai(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_AI_8(m68k), COND_LT(m68k) ? 0xff : 0); +} + + +static void m68k_op_slt_8_pi(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_PI_8(m68k), COND_LT(m68k) ? 0xff : 0); +} + + +static void m68k_op_slt_8_pi7(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_A7_PI_8(m68k), COND_LT(m68k) ? 0xff : 0); +} + + +static void m68k_op_slt_8_pd(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_PD_8(m68k), COND_LT(m68k) ? 0xff : 0); +} + + +static void m68k_op_slt_8_pd7(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_A7_PD_8(m68k), COND_LT(m68k) ? 0xff : 0); +} + + +static void m68k_op_slt_8_di(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_DI_8(m68k), COND_LT(m68k) ? 0xff : 0); +} + + +static void m68k_op_slt_8_ix(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_IX_8(m68k), COND_LT(m68k) ? 0xff : 0); +} + + +static void m68k_op_slt_8_aw(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AW_8(m68k), COND_LT(m68k) ? 0xff : 0); +} + + +static void m68k_op_slt_8_al(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AL_8(m68k), COND_LT(m68k) ? 0xff : 0); +} + + +static void m68k_op_sgt_8_ai(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_AI_8(m68k), COND_GT(m68k) ? 0xff : 0); +} + + +static void m68k_op_sgt_8_pi(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_PI_8(m68k), COND_GT(m68k) ? 0xff : 0); +} + + +static void m68k_op_sgt_8_pi7(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_A7_PI_8(m68k), COND_GT(m68k) ? 0xff : 0); +} + + +static void m68k_op_sgt_8_pd(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_PD_8(m68k), COND_GT(m68k) ? 0xff : 0); +} + + +static void m68k_op_sgt_8_pd7(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_A7_PD_8(m68k), COND_GT(m68k) ? 0xff : 0); +} + + +static void m68k_op_sgt_8_di(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_DI_8(m68k), COND_GT(m68k) ? 0xff : 0); +} + + +static void m68k_op_sgt_8_ix(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_IX_8(m68k), COND_GT(m68k) ? 0xff : 0); +} + + +static void m68k_op_sgt_8_aw(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AW_8(m68k), COND_GT(m68k) ? 0xff : 0); +} + + +static void m68k_op_sgt_8_al(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AL_8(m68k), COND_GT(m68k) ? 0xff : 0); +} + + +static void m68k_op_sle_8_ai(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_AI_8(m68k), COND_LE(m68k) ? 0xff : 0); +} + + +static void m68k_op_sle_8_pi(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_PI_8(m68k), COND_LE(m68k) ? 0xff : 0); +} + + +static void m68k_op_sle_8_pi7(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_A7_PI_8(m68k), COND_LE(m68k) ? 0xff : 0); +} + + +static void m68k_op_sle_8_pd(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_PD_8(m68k), COND_LE(m68k) ? 0xff : 0); +} + + +static void m68k_op_sle_8_pd7(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_A7_PD_8(m68k), COND_LE(m68k) ? 0xff : 0); +} + + +static void m68k_op_sle_8_di(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_DI_8(m68k), COND_LE(m68k) ? 0xff : 0); +} + + +static void m68k_op_sle_8_ix(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AY_IX_8(m68k), COND_LE(m68k) ? 0xff : 0); +} + + +static void m68k_op_sle_8_aw(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AW_8(m68k), COND_LE(m68k) ? 0xff : 0); +} + + +static void m68k_op_sle_8_al(m68ki_cpu_core *m68k) +{ + m68ki_write_8(m68k, EA_AL_8(m68k), COND_LE(m68k) ? 0xff : 0); +} + + +static void m68k_op_stop(m68ki_cpu_core *m68k) +{ + if(m68k->s_flag) + { + UINT32 new_sr = OPER_I_16(m68k); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68k->stopped |= STOP_LEVEL_STOP; + m68ki_set_sr(m68k, new_sr); + m68k->remaining_cycles = 0; + return; + } + m68ki_exception_privilege_violation(m68k); +} + + +static void m68k_op_sub_8_er_d(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = MASK_OUT_ABOVE_8(DY); + UINT32 dst = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_sub_8_er_ai(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_AY_AI_8(m68k); + UINT32 dst = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_sub_8_er_pi(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_AY_PI_8(m68k); + UINT32 dst = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_sub_8_er_pi7(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_A7_PI_8(m68k); + UINT32 dst = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_sub_8_er_pd(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_AY_PD_8(m68k); + UINT32 dst = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_sub_8_er_pd7(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_A7_PD_8(m68k); + UINT32 dst = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_sub_8_er_di(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_AY_DI_8(m68k); + UINT32 dst = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_sub_8_er_ix(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_AY_IX_8(m68k); + UINT32 dst = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_sub_8_er_aw(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_AW_8(m68k); + UINT32 dst = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_sub_8_er_al(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_AL_8(m68k); + UINT32 dst = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_sub_8_er_pcdi(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_PCDI_8(m68k); + UINT32 dst = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_sub_8_er_pcix(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_PCIX_8(m68k); + UINT32 dst = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_sub_8_er_i(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_I_8(m68k); + UINT32 dst = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_sub_16_er_d(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = MASK_OUT_ABOVE_16(DY); + UINT32 dst = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_sub_16_er_a(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = MASK_OUT_ABOVE_16(AY); + UINT32 dst = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_sub_16_er_ai(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_AY_AI_16(m68k); + UINT32 dst = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_sub_16_er_pi(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_AY_PI_16(m68k); + UINT32 dst = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_sub_16_er_pd(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_AY_PD_16(m68k); + UINT32 dst = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_sub_16_er_di(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_AY_DI_16(m68k); + UINT32 dst = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_sub_16_er_ix(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_AY_IX_16(m68k); + UINT32 dst = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_sub_16_er_aw(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_AW_16(m68k); + UINT32 dst = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_sub_16_er_al(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_AL_16(m68k); + UINT32 dst = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_sub_16_er_pcdi(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_PCDI_16(m68k); + UINT32 dst = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_sub_16_er_pcix(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_PCIX_16(m68k); + UINT32 dst = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_sub_16_er_i(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_I_16(m68k); + UINT32 dst = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_sub_32_er_d(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = DY; + UINT32 dst = *r_dst; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->x_flag = m68k->c_flag = CFLAG_SUB_32(src, dst, res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + *r_dst = m68k->not_z_flag; +} + + +static void m68k_op_sub_32_er_a(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = AY; + UINT32 dst = *r_dst; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->x_flag = m68k->c_flag = CFLAG_SUB_32(src, dst, res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + *r_dst = m68k->not_z_flag; +} + + +static void m68k_op_sub_32_er_ai(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_AY_AI_32(m68k); + UINT32 dst = *r_dst; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->x_flag = m68k->c_flag = CFLAG_SUB_32(src, dst, res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + *r_dst = m68k->not_z_flag; +} + + +static void m68k_op_sub_32_er_pi(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_AY_PI_32(m68k); + UINT32 dst = *r_dst; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->x_flag = m68k->c_flag = CFLAG_SUB_32(src, dst, res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + *r_dst = m68k->not_z_flag; +} + + +static void m68k_op_sub_32_er_pd(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_AY_PD_32(m68k); + UINT32 dst = *r_dst; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->x_flag = m68k->c_flag = CFLAG_SUB_32(src, dst, res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + *r_dst = m68k->not_z_flag; +} + + +static void m68k_op_sub_32_er_di(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_AY_DI_32(m68k); + UINT32 dst = *r_dst; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->x_flag = m68k->c_flag = CFLAG_SUB_32(src, dst, res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + *r_dst = m68k->not_z_flag; +} + + +static void m68k_op_sub_32_er_ix(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_AY_IX_32(m68k); + UINT32 dst = *r_dst; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->x_flag = m68k->c_flag = CFLAG_SUB_32(src, dst, res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + *r_dst = m68k->not_z_flag; +} + + +static void m68k_op_sub_32_er_aw(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_AW_32(m68k); + UINT32 dst = *r_dst; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->x_flag = m68k->c_flag = CFLAG_SUB_32(src, dst, res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + *r_dst = m68k->not_z_flag; +} + + +static void m68k_op_sub_32_er_al(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_AL_32(m68k); + UINT32 dst = *r_dst; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->x_flag = m68k->c_flag = CFLAG_SUB_32(src, dst, res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + *r_dst = m68k->not_z_flag; +} + + +static void m68k_op_sub_32_er_pcdi(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_PCDI_32(m68k); + UINT32 dst = *r_dst; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->x_flag = m68k->c_flag = CFLAG_SUB_32(src, dst, res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + *r_dst = m68k->not_z_flag; +} + + +static void m68k_op_sub_32_er_pcix(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_PCIX_32(m68k); + UINT32 dst = *r_dst; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->x_flag = m68k->c_flag = CFLAG_SUB_32(src, dst, res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + *r_dst = m68k->not_z_flag; +} + + +static void m68k_op_sub_32_er_i(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = OPER_I_32(m68k); + UINT32 dst = *r_dst; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->x_flag = m68k->c_flag = CFLAG_SUB_32(src, dst, res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + + *r_dst = m68k->not_z_flag; +} + + +static void m68k_op_sub_8_re_ai(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_AI_8(m68k); + UINT32 src = MASK_OUT_ABOVE_8(DX); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_sub_8_re_pi(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PI_8(m68k); + UINT32 src = MASK_OUT_ABOVE_8(DX); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_sub_8_re_pi7(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_A7_PI_8(m68k); + UINT32 src = MASK_OUT_ABOVE_8(DX); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_sub_8_re_pd(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PD_8(m68k); + UINT32 src = MASK_OUT_ABOVE_8(DX); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_sub_8_re_pd7(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_A7_PD_8(m68k); + UINT32 src = MASK_OUT_ABOVE_8(DX); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_sub_8_re_di(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_DI_8(m68k); + UINT32 src = MASK_OUT_ABOVE_8(DX); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_sub_8_re_ix(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_IX_8(m68k); + UINT32 src = MASK_OUT_ABOVE_8(DX); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_sub_8_re_aw(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AW_8(m68k); + UINT32 src = MASK_OUT_ABOVE_8(DX); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_sub_8_re_al(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AL_8(m68k); + UINT32 src = MASK_OUT_ABOVE_8(DX); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_sub_16_re_ai(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_AI_16(m68k); + UINT32 src = MASK_OUT_ABOVE_16(DX); + UINT32 dst = m68ki_read_16(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_sub_16_re_pi(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PI_16(m68k); + UINT32 src = MASK_OUT_ABOVE_16(DX); + UINT32 dst = m68ki_read_16(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_sub_16_re_pd(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PD_16(m68k); + UINT32 src = MASK_OUT_ABOVE_16(DX); + UINT32 dst = m68ki_read_16(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_sub_16_re_di(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_DI_16(m68k); + UINT32 src = MASK_OUT_ABOVE_16(DX); + UINT32 dst = m68ki_read_16(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_sub_16_re_ix(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_IX_16(m68k); + UINT32 src = MASK_OUT_ABOVE_16(DX); + UINT32 dst = m68ki_read_16(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_sub_16_re_aw(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AW_16(m68k); + UINT32 src = MASK_OUT_ABOVE_16(DX); + UINT32 dst = m68ki_read_16(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_sub_16_re_al(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AL_16(m68k); + UINT32 src = MASK_OUT_ABOVE_16(DX); + UINT32 dst = m68ki_read_16(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_sub_32_re_ai(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_AI_32(m68k); + UINT32 src = DX; + UINT32 dst = m68ki_read_32(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->x_flag = m68k->c_flag = CFLAG_SUB_32(src, dst, res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_sub_32_re_pi(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PI_32(m68k); + UINT32 src = DX; + UINT32 dst = m68ki_read_32(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->x_flag = m68k->c_flag = CFLAG_SUB_32(src, dst, res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_sub_32_re_pd(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PD_32(m68k); + UINT32 src = DX; + UINT32 dst = m68ki_read_32(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->x_flag = m68k->c_flag = CFLAG_SUB_32(src, dst, res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_sub_32_re_di(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_DI_32(m68k); + UINT32 src = DX; + UINT32 dst = m68ki_read_32(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->x_flag = m68k->c_flag = CFLAG_SUB_32(src, dst, res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_sub_32_re_ix(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_IX_32(m68k); + UINT32 src = DX; + UINT32 dst = m68ki_read_32(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->x_flag = m68k->c_flag = CFLAG_SUB_32(src, dst, res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_sub_32_re_aw(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AW_32(m68k); + UINT32 src = DX; + UINT32 dst = m68ki_read_32(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->x_flag = m68k->c_flag = CFLAG_SUB_32(src, dst, res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_sub_32_re_al(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AL_32(m68k); + UINT32 src = DX; + UINT32 dst = m68ki_read_32(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->x_flag = m68k->c_flag = CFLAG_SUB_32(src, dst, res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_suba_16_d(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(DY)); +} + + +static void m68k_op_suba_16_a(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(AY)); +} + + +static void m68k_op_suba_16_ai(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &AX; + UINT32 src = MAKE_INT_16(OPER_AY_AI_16(m68k)); + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - src); +} + + +static void m68k_op_suba_16_pi(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &AX; + UINT32 src = MAKE_INT_16(OPER_AY_PI_16(m68k)); + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - src); +} + + +static void m68k_op_suba_16_pd(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &AX; + UINT32 src = MAKE_INT_16(OPER_AY_PD_16(m68k)); + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - src); +} + + +static void m68k_op_suba_16_di(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &AX; + UINT32 src = MAKE_INT_16(OPER_AY_DI_16(m68k)); + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - src); +} + + +static void m68k_op_suba_16_ix(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &AX; + UINT32 src = MAKE_INT_16(OPER_AY_IX_16(m68k)); + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - src); +} + + +static void m68k_op_suba_16_aw(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &AX; + UINT32 src = MAKE_INT_16(OPER_AW_16(m68k)); + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - src); +} + + +static void m68k_op_suba_16_al(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &AX; + UINT32 src = MAKE_INT_16(OPER_AL_16(m68k)); + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - src); +} + + +static void m68k_op_suba_16_pcdi(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &AX; + UINT32 src = MAKE_INT_16(OPER_PCDI_16(m68k)); + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - src); +} + + +static void m68k_op_suba_16_pcix(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &AX; + UINT32 src = MAKE_INT_16(OPER_PCIX_16(m68k)); + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - src); +} + + +static void m68k_op_suba_16_i(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &AX; + UINT32 src = MAKE_INT_16(OPER_I_16(m68k)); + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - src); +} + + +static void m68k_op_suba_32_d(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - DY); +} + + +static void m68k_op_suba_32_a(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - AY); +} + + +static void m68k_op_suba_32_ai(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &AX; + UINT32 src = OPER_AY_AI_32(m68k); + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - src); +} + + +static void m68k_op_suba_32_pi(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &AX; + UINT32 src = OPER_AY_PI_32(m68k); + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - src); +} + + +static void m68k_op_suba_32_pd(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &AX; + UINT32 src = OPER_AY_PD_32(m68k); + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - src); +} + + +static void m68k_op_suba_32_di(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &AX; + UINT32 src = OPER_AY_DI_32(m68k); + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - src); +} + + +static void m68k_op_suba_32_ix(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &AX; + UINT32 src = OPER_AY_IX_32(m68k); + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - src); +} + + +static void m68k_op_suba_32_aw(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &AX; + UINT32 src = OPER_AW_32(m68k); + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - src); +} + + +static void m68k_op_suba_32_al(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &AX; + UINT32 src = OPER_AL_32(m68k); + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - src); +} + + +static void m68k_op_suba_32_pcdi(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &AX; + UINT32 src = OPER_PCDI_32(m68k); + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - src); +} + + +static void m68k_op_suba_32_pcix(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &AX; + UINT32 src = OPER_PCIX_32(m68k); + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - src); +} + + +static void m68k_op_suba_32_i(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &AX; + UINT32 src = OPER_I_32(m68k); + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - src); +} + + +static void m68k_op_subi_8_d(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 src = OPER_I_8(m68k); + UINT32 dst = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_subi_8_ai(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 ea = EA_AY_AI_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_subi_8_pi(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 ea = EA_AY_PI_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_subi_8_pi7(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 ea = EA_A7_PI_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_subi_8_pd(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 ea = EA_AY_PD_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_subi_8_pd7(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 ea = EA_A7_PD_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_subi_8_di(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 ea = EA_AY_DI_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_subi_8_ix(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 ea = EA_AY_IX_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_subi_8_aw(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 ea = EA_AW_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_subi_8_al(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_8(m68k); + UINT32 ea = EA_AL_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_subi_16_d(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 src = OPER_I_16(m68k); + UINT32 dst = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_subi_16_ai(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_16(m68k); + UINT32 ea = EA_AY_AI_16(m68k); + UINT32 dst = m68ki_read_16(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_subi_16_pi(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_16(m68k); + UINT32 ea = EA_AY_PI_16(m68k); + UINT32 dst = m68ki_read_16(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_subi_16_pd(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_16(m68k); + UINT32 ea = EA_AY_PD_16(m68k); + UINT32 dst = m68ki_read_16(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_subi_16_di(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_16(m68k); + UINT32 ea = EA_AY_DI_16(m68k); + UINT32 dst = m68ki_read_16(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_subi_16_ix(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_16(m68k); + UINT32 ea = EA_AY_IX_16(m68k); + UINT32 dst = m68ki_read_16(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_subi_16_aw(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_16(m68k); + UINT32 ea = EA_AW_16(m68k); + UINT32 dst = m68ki_read_16(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_subi_16_al(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_16(m68k); + UINT32 ea = EA_AL_16(m68k); + UINT32 dst = m68ki_read_16(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_subi_32_d(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 src = OPER_I_32(m68k); + UINT32 dst = *r_dst; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->x_flag = m68k->c_flag = CFLAG_SUB_32(src, dst, res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + + *r_dst = m68k->not_z_flag; +} + + +static void m68k_op_subi_32_ai(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_32(m68k); + UINT32 ea = EA_AY_AI_32(m68k); + UINT32 dst = m68ki_read_32(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->x_flag = m68k->c_flag = CFLAG_SUB_32(src, dst, res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_subi_32_pi(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_32(m68k); + UINT32 ea = EA_AY_PI_32(m68k); + UINT32 dst = m68ki_read_32(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->x_flag = m68k->c_flag = CFLAG_SUB_32(src, dst, res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_subi_32_pd(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_32(m68k); + UINT32 ea = EA_AY_PD_32(m68k); + UINT32 dst = m68ki_read_32(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->x_flag = m68k->c_flag = CFLAG_SUB_32(src, dst, res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_subi_32_di(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_32(m68k); + UINT32 ea = EA_AY_DI_32(m68k); + UINT32 dst = m68ki_read_32(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->x_flag = m68k->c_flag = CFLAG_SUB_32(src, dst, res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_subi_32_ix(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_32(m68k); + UINT32 ea = EA_AY_IX_32(m68k); + UINT32 dst = m68ki_read_32(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->x_flag = m68k->c_flag = CFLAG_SUB_32(src, dst, res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_subi_32_aw(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_32(m68k); + UINT32 ea = EA_AW_32(m68k); + UINT32 dst = m68ki_read_32(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->x_flag = m68k->c_flag = CFLAG_SUB_32(src, dst, res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_subi_32_al(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_I_32(m68k); + UINT32 ea = EA_AL_32(m68k); + UINT32 dst = m68ki_read_32(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->x_flag = m68k->c_flag = CFLAG_SUB_32(src, dst, res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_subq_8_d(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 dst = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_subq_8_ai(m68ki_cpu_core *m68k) +{ + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 ea = EA_AY_AI_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_subq_8_pi(m68ki_cpu_core *m68k) +{ + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 ea = EA_AY_PI_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_subq_8_pi7(m68ki_cpu_core *m68k) +{ + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 ea = EA_A7_PI_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_subq_8_pd(m68ki_cpu_core *m68k) +{ + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 ea = EA_AY_PD_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_subq_8_pd7(m68ki_cpu_core *m68k) +{ + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 ea = EA_A7_PD_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_subq_8_di(m68ki_cpu_core *m68k) +{ + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 ea = EA_AY_DI_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_subq_8_ix(m68ki_cpu_core *m68k) +{ + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 ea = EA_AY_IX_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_subq_8_aw(m68ki_cpu_core *m68k) +{ + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 ea = EA_AW_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_subq_8_al(m68ki_cpu_core *m68k) +{ + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 ea = EA_AL_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = MASK_OUT_ABOVE_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_subq_16_d(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 dst = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | m68k->not_z_flag; +} + + +static void m68k_op_subq_16_a(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &AY; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((m68k->ir >> 9) - 1) & 7) + 1)); +} + + +static void m68k_op_subq_16_ai(m68ki_cpu_core *m68k) +{ + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 ea = EA_AY_AI_16(m68k); + UINT32 dst = m68ki_read_16(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_subq_16_pi(m68ki_cpu_core *m68k) +{ + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 ea = EA_AY_PI_16(m68k); + UINT32 dst = m68ki_read_16(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_subq_16_pd(m68ki_cpu_core *m68k) +{ + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 ea = EA_AY_PD_16(m68k); + UINT32 dst = m68ki_read_16(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_subq_16_di(m68ki_cpu_core *m68k) +{ + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 ea = EA_AY_DI_16(m68k); + UINT32 dst = m68ki_read_16(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_subq_16_ix(m68ki_cpu_core *m68k) +{ + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 ea = EA_AY_IX_16(m68k); + UINT32 dst = m68ki_read_16(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_subq_16_aw(m68ki_cpu_core *m68k) +{ + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 ea = EA_AW_16(m68k); + UINT32 dst = m68ki_read_16(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_subq_16_al(m68ki_cpu_core *m68k) +{ + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 ea = EA_AL_16(m68k); + UINT32 dst = m68ki_read_16(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = MASK_OUT_ABOVE_16(res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_subq_32_d(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 dst = *r_dst; + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->x_flag = m68k->c_flag = CFLAG_SUB_32(src, dst, res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + + *r_dst = m68k->not_z_flag; +} + + +static void m68k_op_subq_32_a(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &AY; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((m68k->ir >> 9) - 1) & 7) + 1)); +} + + +static void m68k_op_subq_32_ai(m68ki_cpu_core *m68k) +{ + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 ea = EA_AY_AI_32(m68k); + UINT32 dst = m68ki_read_32(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->x_flag = m68k->c_flag = CFLAG_SUB_32(src, dst, res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_subq_32_pi(m68ki_cpu_core *m68k) +{ + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 ea = EA_AY_PI_32(m68k); + UINT32 dst = m68ki_read_32(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->x_flag = m68k->c_flag = CFLAG_SUB_32(src, dst, res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_subq_32_pd(m68ki_cpu_core *m68k) +{ + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 ea = EA_AY_PD_32(m68k); + UINT32 dst = m68ki_read_32(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->x_flag = m68k->c_flag = CFLAG_SUB_32(src, dst, res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_subq_32_di(m68ki_cpu_core *m68k) +{ + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 ea = EA_AY_DI_32(m68k); + UINT32 dst = m68ki_read_32(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->x_flag = m68k->c_flag = CFLAG_SUB_32(src, dst, res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_subq_32_ix(m68ki_cpu_core *m68k) +{ + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 ea = EA_AY_IX_32(m68k); + UINT32 dst = m68ki_read_32(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->x_flag = m68k->c_flag = CFLAG_SUB_32(src, dst, res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_subq_32_aw(m68ki_cpu_core *m68k) +{ + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 ea = EA_AW_32(m68k); + UINT32 dst = m68ki_read_32(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->x_flag = m68k->c_flag = CFLAG_SUB_32(src, dst, res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_subq_32_al(m68ki_cpu_core *m68k) +{ + UINT32 src = (((m68k->ir >> 9) - 1) & 7) + 1; + UINT32 ea = EA_AL_32(m68k); + UINT32 dst = m68ki_read_32(m68k, ea); + UINT32 res = dst - src; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = MASK_OUT_ABOVE_32(res); + m68k->x_flag = m68k->c_flag = CFLAG_SUB_32(src, dst, res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(m68k, ea, m68k->not_z_flag); +} + + +static void m68k_op_subx_8_rr(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = MASK_OUT_ABOVE_8(DY); + UINT32 dst = MASK_OUT_ABOVE_8(*r_dst); + UINT32 res = dst - src - XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + + res = MASK_OUT_ABOVE_8(res); + m68k->not_z_flag |= res; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; +} + + +static void m68k_op_subx_16_rr(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = MASK_OUT_ABOVE_16(DY); + UINT32 dst = MASK_OUT_ABOVE_16(*r_dst); + UINT32 res = dst - src - XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_16(res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + + res = MASK_OUT_ABOVE_16(res); + m68k->not_z_flag |= res; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; +} + + +static void m68k_op_subx_32_rr(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DX; + UINT32 src = DY; + UINT32 dst = *r_dst; + UINT32 res = dst - src - XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_32(res); + m68k->x_flag = m68k->c_flag = CFLAG_SUB_32(src, dst, res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + + res = MASK_OUT_ABOVE_32(res); + m68k->not_z_flag |= res; + + *r_dst = res; +} + + +static void m68k_op_subx_8_mm_ax7(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_AY_PD_8(m68k); + UINT32 ea = EA_A7_PD_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = dst - src - XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + + res = MASK_OUT_ABOVE_8(res); + m68k->not_z_flag |= res; + + m68ki_write_8(m68k, ea, res); +} + + +static void m68k_op_subx_8_mm_ay7(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_A7_PD_8(m68k); + UINT32 ea = EA_AX_PD_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = dst - src - XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + + res = MASK_OUT_ABOVE_8(res); + m68k->not_z_flag |= res; + + m68ki_write_8(m68k, ea, res); +} + + +static void m68k_op_subx_8_mm_axy7(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_A7_PD_8(m68k); + UINT32 ea = EA_A7_PD_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = dst - src - XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + + res = MASK_OUT_ABOVE_8(res); + m68k->not_z_flag |= res; + + m68ki_write_8(m68k, ea, res); +} + + +static void m68k_op_subx_8_mm(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_AY_PD_8(m68k); + UINT32 ea = EA_AX_PD_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 res = dst - src - XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_8(res); + m68k->x_flag = m68k->c_flag = CFLAG_8(res); + m68k->v_flag = VFLAG_SUB_8(src, dst, res); + + res = MASK_OUT_ABOVE_8(res); + m68k->not_z_flag |= res; + + m68ki_write_8(m68k, ea, res); +} + + +static void m68k_op_subx_16_mm(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_AY_PD_16(m68k); + UINT32 ea = EA_AX_PD_16(m68k); + UINT32 dst = m68ki_read_16(m68k, ea); + UINT32 res = dst - src - XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_16(res); + m68k->x_flag = m68k->c_flag = CFLAG_16(res); + m68k->v_flag = VFLAG_SUB_16(src, dst, res); + + res = MASK_OUT_ABOVE_16(res); + m68k->not_z_flag |= res; + + m68ki_write_16(m68k, ea, res); +} + + +static void m68k_op_subx_32_mm(m68ki_cpu_core *m68k) +{ + UINT32 src = OPER_AY_PD_32(m68k); + UINT32 ea = EA_AX_PD_32(m68k); + UINT32 dst = m68ki_read_32(m68k, ea); + UINT32 res = dst - src - XFLAG_AS_1(m68k); + + m68k->n_flag = NFLAG_32(res); + m68k->x_flag = m68k->c_flag = CFLAG_SUB_32(src, dst, res); + m68k->v_flag = VFLAG_SUB_32(src, dst, res); + + res = MASK_OUT_ABOVE_32(res); + m68k->not_z_flag |= res; + + m68ki_write_32(m68k, ea, res); +} + + +static void m68k_op_swap_32(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + + m68k->not_z_flag = MASK_OUT_ABOVE_32(*r_dst<<16); + *r_dst = (*r_dst>>16) | m68k->not_z_flag; + + m68k->not_z_flag = *r_dst; + m68k->n_flag = NFLAG_32(*r_dst); + m68k->c_flag = CFLAG_CLEAR; + m68k->v_flag = VFLAG_CLEAR; +} + + +static void m68k_op_tas_8_d(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &DY; + + m68k->not_z_flag = MASK_OUT_ABOVE_8(*r_dst); + m68k->n_flag = NFLAG_8(*r_dst); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + *r_dst |= 0x80; +} + + +static void m68k_op_tas_8_ai(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_AI_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 allow_writeback = TRUE; + + m68k->not_z_flag = dst; + m68k->n_flag = NFLAG_8(dst); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + /* The Genesis/Megadrive games Gargoyles and Ex-Mutants need the TAS writeback + disabled in order to function properly. Some Amiga software may also rely + on this, but only when accessing specific addresses so additional functionality + will be needed. */ + + if (allow_writeback) + m68ki_write_8(m68k, ea, dst | 0x80); +} + + +static void m68k_op_tas_8_pi(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PI_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 allow_writeback = TRUE; + + m68k->not_z_flag = dst; + m68k->n_flag = NFLAG_8(dst); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + /* The Genesis/Megadrive games Gargoyles and Ex-Mutants need the TAS writeback + disabled in order to function properly. Some Amiga software may also rely + on this, but only when accessing specific addresses so additional functionality + will be needed. */ + + if (allow_writeback) + m68ki_write_8(m68k, ea, dst | 0x80); +} + + +static void m68k_op_tas_8_pi7(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_A7_PI_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 allow_writeback = TRUE; + + m68k->not_z_flag = dst; + m68k->n_flag = NFLAG_8(dst); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + /* The Genesis/Megadrive games Gargoyles and Ex-Mutants need the TAS writeback + disabled in order to function properly. Some Amiga software may also rely + on this, but only when accessing specific addresses so additional functionality + will be needed. */ + + if (allow_writeback) + m68ki_write_8(m68k, ea, dst | 0x80); +} + + +static void m68k_op_tas_8_pd(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_PD_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 allow_writeback = TRUE; + + m68k->not_z_flag = dst; + m68k->n_flag = NFLAG_8(dst); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + /* The Genesis/Megadrive games Gargoyles and Ex-Mutants need the TAS writeback + disabled in order to function properly. Some Amiga software may also rely + on this, but only when accessing specific addresses so additional functionality + will be needed. */ + + if (allow_writeback) + m68ki_write_8(m68k, ea, dst | 0x80); +} + + +static void m68k_op_tas_8_pd7(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_A7_PD_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 allow_writeback = TRUE; + + m68k->not_z_flag = dst; + m68k->n_flag = NFLAG_8(dst); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + /* The Genesis/Megadrive games Gargoyles and Ex-Mutants need the TAS writeback + disabled in order to function properly. Some Amiga software may also rely + on this, but only when accessing specific addresses so additional functionality + will be needed. */ + + if (allow_writeback) + m68ki_write_8(m68k, ea, dst | 0x80); +} + + +static void m68k_op_tas_8_di(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_DI_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 allow_writeback = TRUE; + + m68k->not_z_flag = dst; + m68k->n_flag = NFLAG_8(dst); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + /* The Genesis/Megadrive games Gargoyles and Ex-Mutants need the TAS writeback + disabled in order to function properly. Some Amiga software may also rely + on this, but only when accessing specific addresses so additional functionality + will be needed. */ + + if (allow_writeback) + m68ki_write_8(m68k, ea, dst | 0x80); +} + + +static void m68k_op_tas_8_ix(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AY_IX_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 allow_writeback = TRUE; + + m68k->not_z_flag = dst; + m68k->n_flag = NFLAG_8(dst); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + /* The Genesis/Megadrive games Gargoyles and Ex-Mutants need the TAS writeback + disabled in order to function properly. Some Amiga software may also rely + on this, but only when accessing specific addresses so additional functionality + will be needed. */ + + if (allow_writeback) + m68ki_write_8(m68k, ea, dst | 0x80); +} + + +static void m68k_op_tas_8_aw(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AW_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 allow_writeback = TRUE; + + m68k->not_z_flag = dst; + m68k->n_flag = NFLAG_8(dst); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + /* The Genesis/Megadrive games Gargoyles and Ex-Mutants need the TAS writeback + disabled in order to function properly. Some Amiga software may also rely + on this, but only when accessing specific addresses so additional functionality + will be needed. */ + + if (allow_writeback) + m68ki_write_8(m68k, ea, dst | 0x80); +} + + +static void m68k_op_tas_8_al(m68ki_cpu_core *m68k) +{ + UINT32 ea = EA_AL_8(m68k); + UINT32 dst = m68ki_read_8(m68k, ea); + UINT32 allow_writeback = TRUE; + + m68k->not_z_flag = dst; + m68k->n_flag = NFLAG_8(dst); + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + + /* The Genesis/Megadrive games Gargoyles and Ex-Mutants need the TAS writeback + disabled in order to function properly. Some Amiga software may also rely + on this, but only when accessing specific addresses so additional functionality + will be needed. */ + + if (allow_writeback) + m68ki_write_8(m68k, ea, dst | 0x80); +} + + +static void m68k_op_trap(m68ki_cpu_core *m68k) +{ + /* Trap#n stacks exception frame type 0 */ + m68ki_exception_trapN(m68k, EXCEPTION_TRAP_BASE + (m68k->ir & 0xf)); /* HJB 990403 */ +} + + +static void m68k_op_trapt(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + m68ki_exception_trap(m68k, EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_trapt_16(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + m68ki_exception_trap(m68k, EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_trapt_32(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + m68ki_exception_trap(m68k, EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_trapf(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_trapf_16(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + REG_PC += 2; + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_trapf_32(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + REG_PC += 4; + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_traphi(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(COND_HI(m68k)) + m68ki_exception_trap(m68k, EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_trapls(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(COND_LS(m68k)) + m68ki_exception_trap(m68k, EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_trapcc(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(COND_CC(m68k)) + m68ki_exception_trap(m68k, EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_trapcs(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(COND_CS(m68k)) + m68ki_exception_trap(m68k, EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_trapne(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(COND_NE(m68k)) + m68ki_exception_trap(m68k, EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_trapeq(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(COND_EQ(m68k)) + m68ki_exception_trap(m68k, EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_trapvc(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(COND_VC(m68k)) + m68ki_exception_trap(m68k, EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_trapvs(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(COND_VS(m68k)) + m68ki_exception_trap(m68k, EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_trappl(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(COND_PL(m68k)) + m68ki_exception_trap(m68k, EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_trapmi(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(COND_MI(m68k)) + m68ki_exception_trap(m68k, EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_trapge(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(COND_GE(m68k)) + m68ki_exception_trap(m68k, EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_traplt(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(COND_LT(m68k)) + m68ki_exception_trap(m68k, EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_trapgt(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(COND_GT(m68k)) + m68ki_exception_trap(m68k, EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_traple(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(COND_LE(m68k)) + m68ki_exception_trap(m68k, EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_traphi_16(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(COND_HI(m68k)) + { + m68ki_exception_trap(m68k, EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 2; + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_trapls_16(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(COND_LS(m68k)) + { + m68ki_exception_trap(m68k, EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 2; + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_trapcc_16(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(COND_CC(m68k)) + { + m68ki_exception_trap(m68k, EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 2; + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_trapcs_16(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(COND_CS(m68k)) + { + m68ki_exception_trap(m68k, EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 2; + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_trapne_16(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(COND_NE(m68k)) + { + m68ki_exception_trap(m68k, EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 2; + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_trapeq_16(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(COND_EQ(m68k)) + { + m68ki_exception_trap(m68k, EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 2; + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_trapvc_16(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(COND_VC(m68k)) + { + m68ki_exception_trap(m68k, EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 2; + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_trapvs_16(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(COND_VS(m68k)) + { + m68ki_exception_trap(m68k, EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 2; + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_trappl_16(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(COND_PL(m68k)) + { + m68ki_exception_trap(m68k, EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 2; + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_trapmi_16(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(COND_MI(m68k)) + { + m68ki_exception_trap(m68k, EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 2; + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_trapge_16(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(COND_GE(m68k)) + { + m68ki_exception_trap(m68k, EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 2; + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_traplt_16(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(COND_LT(m68k)) + { + m68ki_exception_trap(m68k, EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 2; + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_trapgt_16(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(COND_GT(m68k)) + { + m68ki_exception_trap(m68k, EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 2; + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_traple_16(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(COND_LE(m68k)) + { + m68ki_exception_trap(m68k, EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 2; + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_traphi_32(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(COND_HI(m68k)) + { + m68ki_exception_trap(m68k, EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_trapls_32(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(COND_LS(m68k)) + { + m68ki_exception_trap(m68k, EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_trapcc_32(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(COND_CC(m68k)) + { + m68ki_exception_trap(m68k, EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_trapcs_32(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(COND_CS(m68k)) + { + m68ki_exception_trap(m68k, EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_trapne_32(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(COND_NE(m68k)) + { + m68ki_exception_trap(m68k, EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_trapeq_32(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(COND_EQ(m68k)) + { + m68ki_exception_trap(m68k, EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_trapvc_32(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(COND_VC(m68k)) + { + m68ki_exception_trap(m68k, EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_trapvs_32(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(COND_VS(m68k)) + { + m68ki_exception_trap(m68k, EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_trappl_32(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(COND_PL(m68k)) + { + m68ki_exception_trap(m68k, EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_trapmi_32(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(COND_MI(m68k)) + { + m68ki_exception_trap(m68k, EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_trapge_32(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(COND_GE(m68k)) + { + m68ki_exception_trap(m68k, EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_traplt_32(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(COND_LT(m68k)) + { + m68ki_exception_trap(m68k, EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_trapgt_32(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(COND_GT(m68k)) + { + m68ki_exception_trap(m68k, EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_traple_32(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + if(COND_LE(m68k)) + { + m68ki_exception_trap(m68k, EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_trapv(m68ki_cpu_core *m68k) +{ + if(COND_VC(m68k)) + { + return; + } + m68ki_exception_trap(m68k, EXCEPTION_TRAPV); /* HJB 990403 */ +} + + +static void m68k_op_tst_8_d(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_8(DY); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_tst_8_ai(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_AI_8(m68k); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_tst_8_pi(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PI_8(m68k); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_tst_8_pi7(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_A7_PI_8(m68k); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_tst_8_pd(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PD_8(m68k); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_tst_8_pd7(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_A7_PD_8(m68k); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_tst_8_di(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_DI_8(m68k); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_tst_8_ix(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_IX_8(m68k); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_tst_8_aw(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AW_8(m68k); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_tst_8_al(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AL_8(m68k); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_tst_8_pcdi(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 res = OPER_PCDI_8(m68k); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_tst_8_pcix(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 res = OPER_PCIX_8(m68k); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_tst_8_i(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 res = OPER_I_8(m68k); + + m68k->n_flag = NFLAG_8(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_tst_16_d(m68ki_cpu_core *m68k) +{ + UINT32 res = MASK_OUT_ABOVE_16(DY); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_tst_16_a(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 res = MAKE_INT_16(AY); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_tst_16_ai(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_AI_16(m68k); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_tst_16_pi(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PI_16(m68k); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_tst_16_pd(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PD_16(m68k); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_tst_16_di(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_DI_16(m68k); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_tst_16_ix(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_IX_16(m68k); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_tst_16_aw(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AW_16(m68k); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_tst_16_al(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AL_16(m68k); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_tst_16_pcdi(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 res = OPER_PCDI_16(m68k); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_tst_16_pcix(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 res = OPER_PCIX_16(m68k); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_tst_16_i(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 res = OPER_I_16(m68k); + + m68k->n_flag = NFLAG_16(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_tst_32_d(m68ki_cpu_core *m68k) +{ + UINT32 res = DY; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_tst_32_a(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 res = AY; + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_tst_32_ai(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_AI_32(m68k); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_tst_32_pi(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PI_32(m68k); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_tst_32_pd(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_PD_32(m68k); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_tst_32_di(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_DI_32(m68k); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_tst_32_ix(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AY_IX_32(m68k); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_tst_32_aw(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AW_32(m68k); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_tst_32_al(m68ki_cpu_core *m68k) +{ + UINT32 res = OPER_AL_32(m68k); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; +} + + +static void m68k_op_tst_32_pcdi(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 res = OPER_PCDI_32(m68k); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_tst_32_pcix(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 res = OPER_PCIX_32(m68k); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_tst_32_i(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 res = OPER_I_32(m68k); + + m68k->n_flag = NFLAG_32(res); + m68k->not_z_flag = res; + m68k->v_flag = VFLAG_CLEAR; + m68k->c_flag = CFLAG_CLEAR; + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_unlk_32_a7(m68ki_cpu_core *m68k) +{ + REG_A[7] = m68ki_read_32(m68k, REG_A[7]); +} + + +static void m68k_op_unlk_32(m68ki_cpu_core *m68k) +{ + UINT32* r_dst = &AY; + + REG_A[7] = *r_dst; + *r_dst = m68ki_pull_32(m68k); +} + + +static void m68k_op_unpk_16_rr(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + /* Note: DX and DY are reversed in Motorola's docs */ + UINT32 src = DY; + UINT32* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | (((((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16(m68k)) & 0xffff); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_unpk_16_mm_ax7(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + /* Note: AX and AY are reversed in Motorola's docs */ + UINT32 src = OPER_AY_PD_8(m68k); + UINT32 ea_dst; + + src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16(m68k); + ea_dst = EA_A7_PD_8(m68k); + m68ki_write_8(m68k, ea_dst, (src >> 8) & 0xff); + ea_dst = EA_A7_PD_8(m68k); + m68ki_write_8(m68k, ea_dst, src & 0xff); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_unpk_16_mm_ay7(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + /* Note: AX and AY are reversed in Motorola's docs */ + UINT32 src = OPER_A7_PD_8(m68k); + UINT32 ea_dst; + + src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16(m68k); + ea_dst = EA_AX_PD_8(m68k); + m68ki_write_8(m68k, ea_dst, (src >> 8) & 0xff); + ea_dst = EA_AX_PD_8(m68k); + m68ki_write_8(m68k, ea_dst, src & 0xff); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_unpk_16_mm_axy7(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + UINT32 src = OPER_A7_PD_8(m68k); + UINT32 ea_dst; + + src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16(m68k); + ea_dst = EA_A7_PD_8(m68k); + m68ki_write_8(m68k, ea_dst, (src >> 8) & 0xff); + ea_dst = EA_A7_PD_8(m68k); + m68ki_write_8(m68k, ea_dst, src & 0xff); + return; + } + m68ki_exception_illegal(m68k); +} + + +static void m68k_op_unpk_16_mm(m68ki_cpu_core *m68k) +{ + if(CPU_TYPE_IS_EC020_PLUS(m68k->cpu_type)) + { + /* Note: AX and AY are reversed in Motorola's docs */ + UINT32 src = OPER_AY_PD_8(m68k); + UINT32 ea_dst; + + src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16(m68k); + ea_dst = EA_AX_PD_8(m68k); + m68ki_write_8(m68k, ea_dst, (src >> 8) & 0xff); + ea_dst = EA_AX_PD_8(m68k); + m68ki_write_8(m68k, ea_dst, src & 0xff); + return; + } + m68ki_exception_illegal(m68k); +} + + +/* ======================================================================== */ +/* ============================== END OF FILE ============================= */ +/* ======================================================================== */ + + +/* ======================================================================== */ +/* ========================= OPCODE TABLE BUILDER ========================= */ +/* ======================================================================== */ + +#include "m68kops.h" + +#define NUM_CPU_TYPES 5 + +void (*m68ki_instruction_jump_table[0x10000])(m68ki_cpu_core *m68k); /* opcode handler jump table */ +unsigned char m68ki_cycles[NUM_CPU_TYPES][0x10000]; /* Cycles used by CPU type */ + +/* This is used to generate the opcode handler jump table */ +typedef struct +{ + void (*opcode_handler)(m68ki_cpu_core *m68k); /* handler function */ + unsigned int mask; /* mask on opcode */ + unsigned int match; /* what to match after masking */ + unsigned char cycles[NUM_CPU_TYPES]; /* cycles each cpu type takes */ +} opcode_handler_struct; + + +/* Opcode handler table */ +static const opcode_handler_struct m68k_opcode_handler_table[] = +{ +/* function mask match 000 010 020 040 */ + + + {m68k_op_1010 , 0xf000, 0xa000, { 4, 4, 4, 4, 4}}, + {m68k_op_1111 , 0xf000, 0xf000, { 4, 4, 4, 4, 4}}, + {m68k_op_moveq_32 , 0xf100, 0x7000, { 4, 4, 2, 2, 2}}, + {m68k_op_cpbcc_32 , 0xf180, 0xf080, { 0, 0, 4, 4, 0}}, + {m68k_op_cpgen_32 , 0xf1c0, 0xf000, { 0, 0, 4, 4, 0}}, + {m68k_op_cpscc_32 , 0xf1c0, 0xf040, { 0, 0, 4, 4, 0}}, + {m68k_op_pmmu_32 , 0xfe00, 0xf000, { 0, 0, 8, 8, 8}}, + {m68k_op_bra_8 , 0xff00, 0x6000, { 10, 10, 10, 10, 10}}, + {m68k_op_bsr_8 , 0xff00, 0x6100, { 18, 18, 7, 7, 7}}, + {m68k_op_bhi_8 , 0xff00, 0x6200, { 10, 10, 6, 6, 6}}, + {m68k_op_bls_8 , 0xff00, 0x6300, { 10, 10, 6, 6, 6}}, + {m68k_op_bcc_8 , 0xff00, 0x6400, { 10, 10, 6, 6, 6}}, + {m68k_op_bcs_8 , 0xff00, 0x6500, { 10, 10, 6, 6, 6}}, + {m68k_op_bne_8 , 0xff00, 0x6600, { 10, 10, 6, 6, 6}}, + {m68k_op_beq_8 , 0xff00, 0x6700, { 10, 10, 6, 6, 6}}, + {m68k_op_bvc_8 , 0xff00, 0x6800, { 10, 10, 6, 6, 6}}, + {m68k_op_bvs_8 , 0xff00, 0x6900, { 10, 10, 6, 6, 6}}, + {m68k_op_bpl_8 , 0xff00, 0x6a00, { 10, 10, 6, 6, 6}}, + {m68k_op_bmi_8 , 0xff00, 0x6b00, { 10, 10, 6, 6, 6}}, + {m68k_op_bge_8 , 0xff00, 0x6c00, { 10, 10, 6, 6, 6}}, + {m68k_op_blt_8 , 0xff00, 0x6d00, { 10, 10, 6, 6, 6}}, + {m68k_op_bgt_8 , 0xff00, 0x6e00, { 10, 10, 6, 6, 6}}, + {m68k_op_ble_8 , 0xff00, 0x6f00, { 10, 10, 6, 6, 6}}, + {m68k_op_040fpu0_32 , 0xff00, 0xf200, { 0, 0, 0, 0, 0}}, + {m68k_op_040fpu1_32 , 0xff00, 0xf300, { 0, 0, 0, 0, 0}}, + {m68k_op_btst_32_r_d , 0xf1f8, 0x0100, { 6, 6, 4, 4, 4}}, + {m68k_op_movep_16_er , 0xf1f8, 0x0108, { 16, 16, 12, 12, 12}}, + {m68k_op_btst_8_r_ai , 0xf1f8, 0x0110, { 8, 8, 8, 8, 8}}, + {m68k_op_btst_8_r_pi , 0xf1f8, 0x0118, { 8, 8, 8, 8, 8}}, + {m68k_op_btst_8_r_pd , 0xf1f8, 0x0120, { 10, 10, 9, 9, 9}}, + {m68k_op_btst_8_r_di , 0xf1f8, 0x0128, { 12, 12, 9, 9, 9}}, + {m68k_op_btst_8_r_ix , 0xf1f8, 0x0130, { 14, 14, 11, 11, 11}}, + {m68k_op_bchg_32_r_d , 0xf1f8, 0x0140, { 8, 8, 4, 4, 4}}, + {m68k_op_movep_32_er , 0xf1f8, 0x0148, { 24, 24, 18, 18, 18}}, + {m68k_op_bchg_8_r_ai , 0xf1f8, 0x0150, { 12, 12, 8, 8, 8}}, + {m68k_op_bchg_8_r_pi , 0xf1f8, 0x0158, { 12, 12, 8, 8, 8}}, + {m68k_op_bchg_8_r_pd , 0xf1f8, 0x0160, { 14, 14, 9, 9, 9}}, + {m68k_op_bchg_8_r_di , 0xf1f8, 0x0168, { 16, 16, 9, 9, 9}}, + {m68k_op_bchg_8_r_ix , 0xf1f8, 0x0170, { 18, 18, 11, 11, 11}}, + {m68k_op_bclr_32_r_d , 0xf1f8, 0x0180, { 10, 10, 4, 4, 4}}, + {m68k_op_movep_16_re , 0xf1f8, 0x0188, { 16, 16, 11, 11, 11}}, + {m68k_op_bclr_8_r_ai , 0xf1f8, 0x0190, { 12, 14, 8, 8, 8}}, + {m68k_op_bclr_8_r_pi , 0xf1f8, 0x0198, { 12, 14, 8, 8, 8}}, + {m68k_op_bclr_8_r_pd , 0xf1f8, 0x01a0, { 14, 16, 9, 9, 9}}, + {m68k_op_bclr_8_r_di , 0xf1f8, 0x01a8, { 16, 18, 9, 9, 9}}, + {m68k_op_bclr_8_r_ix , 0xf1f8, 0x01b0, { 18, 20, 11, 11, 11}}, + {m68k_op_bset_32_r_d , 0xf1f8, 0x01c0, { 8, 8, 4, 4, 4}}, + {m68k_op_movep_32_re , 0xf1f8, 0x01c8, { 24, 24, 17, 17, 17}}, + {m68k_op_bset_8_r_ai , 0xf1f8, 0x01d0, { 12, 12, 8, 8, 8}}, + {m68k_op_bset_8_r_pi , 0xf1f8, 0x01d8, { 12, 12, 8, 8, 8}}, + {m68k_op_bset_8_r_pd , 0xf1f8, 0x01e0, { 14, 14, 9, 9, 9}}, + {m68k_op_bset_8_r_di , 0xf1f8, 0x01e8, { 16, 16, 9, 9, 9}}, + {m68k_op_bset_8_r_ix , 0xf1f8, 0x01f0, { 18, 18, 11, 11, 11}}, + {m68k_op_move_8_d_d , 0xf1f8, 0x1000, { 4, 4, 2, 2, 2}}, + {m68k_op_move_8_d_ai , 0xf1f8, 0x1010, { 8, 8, 6, 6, 6}}, + {m68k_op_move_8_d_pi , 0xf1f8, 0x1018, { 8, 8, 6, 6, 6}}, + {m68k_op_move_8_d_pd , 0xf1f8, 0x1020, { 10, 10, 7, 7, 7}}, + {m68k_op_move_8_d_di , 0xf1f8, 0x1028, { 12, 12, 7, 7, 7}}, + {m68k_op_move_8_d_ix , 0xf1f8, 0x1030, { 14, 14, 9, 9, 9}}, + {m68k_op_move_8_ai_d , 0xf1f8, 0x1080, { 8, 8, 4, 4, 4}}, + {m68k_op_move_8_ai_ai , 0xf1f8, 0x1090, { 12, 12, 8, 8, 8}}, + {m68k_op_move_8_ai_pi , 0xf1f8, 0x1098, { 12, 12, 8, 8, 8}}, + {m68k_op_move_8_ai_pd , 0xf1f8, 0x10a0, { 14, 14, 9, 9, 9}}, + {m68k_op_move_8_ai_di , 0xf1f8, 0x10a8, { 16, 16, 9, 9, 9}}, + {m68k_op_move_8_ai_ix , 0xf1f8, 0x10b0, { 18, 18, 11, 11, 11}}, + {m68k_op_move_8_pi_d , 0xf1f8, 0x10c0, { 8, 8, 4, 4, 4}}, + {m68k_op_move_8_pi_ai , 0xf1f8, 0x10d0, { 12, 12, 8, 8, 8}}, + {m68k_op_move_8_pi_pi , 0xf1f8, 0x10d8, { 12, 12, 8, 8, 8}}, + {m68k_op_move_8_pi_pd , 0xf1f8, 0x10e0, { 14, 14, 9, 9, 9}}, + {m68k_op_move_8_pi_di , 0xf1f8, 0x10e8, { 16, 16, 9, 9, 9}}, + {m68k_op_move_8_pi_ix , 0xf1f8, 0x10f0, { 18, 18, 11, 11, 11}}, + {m68k_op_move_8_pd_d , 0xf1f8, 0x1100, { 8, 8, 5, 5, 5}}, + {m68k_op_move_8_pd_ai , 0xf1f8, 0x1110, { 12, 12, 9, 9, 9}}, + {m68k_op_move_8_pd_pi , 0xf1f8, 0x1118, { 12, 12, 9, 9, 9}}, + {m68k_op_move_8_pd_pd , 0xf1f8, 0x1120, { 14, 14, 10, 10, 10}}, + {m68k_op_move_8_pd_di , 0xf1f8, 0x1128, { 16, 16, 10, 10, 10}}, + {m68k_op_move_8_pd_ix , 0xf1f8, 0x1130, { 18, 18, 12, 12, 12}}, + {m68k_op_move_8_di_d , 0xf1f8, 0x1140, { 12, 12, 5, 5, 5}}, + {m68k_op_move_8_di_ai , 0xf1f8, 0x1150, { 16, 16, 9, 9, 9}}, + {m68k_op_move_8_di_pi , 0xf1f8, 0x1158, { 16, 16, 9, 9, 9}}, + {m68k_op_move_8_di_pd , 0xf1f8, 0x1160, { 18, 18, 10, 10, 10}}, + {m68k_op_move_8_di_di , 0xf1f8, 0x1168, { 20, 20, 10, 10, 10}}, + {m68k_op_move_8_di_ix , 0xf1f8, 0x1170, { 22, 22, 12, 12, 12}}, + {m68k_op_move_8_ix_d , 0xf1f8, 0x1180, { 14, 14, 7, 7, 7}}, + {m68k_op_move_8_ix_ai , 0xf1f8, 0x1190, { 18, 18, 11, 11, 11}}, + {m68k_op_move_8_ix_pi , 0xf1f8, 0x1198, { 18, 18, 11, 11, 11}}, + {m68k_op_move_8_ix_pd , 0xf1f8, 0x11a0, { 20, 20, 12, 12, 12}}, + {m68k_op_move_8_ix_di , 0xf1f8, 0x11a8, { 22, 22, 12, 12, 12}}, + {m68k_op_move_8_ix_ix , 0xf1f8, 0x11b0, { 24, 24, 14, 14, 14}}, + {m68k_op_move_32_d_d , 0xf1f8, 0x2000, { 4, 4, 2, 2, 2}}, + {m68k_op_move_32_d_a , 0xf1f8, 0x2008, { 4, 4, 2, 2, 2}}, + {m68k_op_move_32_d_ai , 0xf1f8, 0x2010, { 12, 12, 6, 6, 6}}, + {m68k_op_move_32_d_pi , 0xf1f8, 0x2018, { 12, 12, 6, 6, 6}}, + {m68k_op_move_32_d_pd , 0xf1f8, 0x2020, { 14, 14, 7, 7, 7}}, + {m68k_op_move_32_d_di , 0xf1f8, 0x2028, { 16, 16, 7, 7, 7}}, + {m68k_op_move_32_d_ix , 0xf1f8, 0x2030, { 18, 18, 9, 9, 9}}, + {m68k_op_movea_32_d , 0xf1f8, 0x2040, { 4, 4, 2, 2, 2}}, + {m68k_op_movea_32_a , 0xf1f8, 0x2048, { 4, 4, 2, 2, 2}}, + {m68k_op_movea_32_ai , 0xf1f8, 0x2050, { 12, 12, 6, 6, 6}}, + {m68k_op_movea_32_pi , 0xf1f8, 0x2058, { 12, 12, 6, 6, 6}}, + {m68k_op_movea_32_pd , 0xf1f8, 0x2060, { 14, 14, 7, 7, 7}}, + {m68k_op_movea_32_di , 0xf1f8, 0x2068, { 16, 16, 7, 7, 7}}, + {m68k_op_movea_32_ix , 0xf1f8, 0x2070, { 18, 18, 9, 9, 9}}, + {m68k_op_move_32_ai_d , 0xf1f8, 0x2080, { 12, 12, 4, 4, 4}}, + {m68k_op_move_32_ai_a , 0xf1f8, 0x2088, { 12, 12, 4, 4, 4}}, + {m68k_op_move_32_ai_ai , 0xf1f8, 0x2090, { 20, 20, 8, 8, 8}}, + {m68k_op_move_32_ai_pi , 0xf1f8, 0x2098, { 20, 20, 8, 8, 8}}, + {m68k_op_move_32_ai_pd , 0xf1f8, 0x20a0, { 22, 22, 9, 9, 9}}, + {m68k_op_move_32_ai_di , 0xf1f8, 0x20a8, { 24, 24, 9, 9, 9}}, + {m68k_op_move_32_ai_ix , 0xf1f8, 0x20b0, { 26, 26, 11, 11, 11}}, + {m68k_op_move_32_pi_d , 0xf1f8, 0x20c0, { 12, 12, 4, 4, 4}}, + {m68k_op_move_32_pi_a , 0xf1f8, 0x20c8, { 12, 12, 4, 4, 4}}, + {m68k_op_move_32_pi_ai , 0xf1f8, 0x20d0, { 20, 20, 8, 8, 8}}, + {m68k_op_move_32_pi_pi , 0xf1f8, 0x20d8, { 20, 20, 8, 8, 8}}, + {m68k_op_move_32_pi_pd , 0xf1f8, 0x20e0, { 22, 22, 9, 9, 9}}, + {m68k_op_move_32_pi_di , 0xf1f8, 0x20e8, { 24, 24, 9, 9, 9}}, + {m68k_op_move_32_pi_ix , 0xf1f8, 0x20f0, { 26, 26, 11, 11, 11}}, + {m68k_op_move_32_pd_d , 0xf1f8, 0x2100, { 12, 14, 5, 5, 5}}, + {m68k_op_move_32_pd_a , 0xf1f8, 0x2108, { 12, 14, 5, 5, 5}}, + {m68k_op_move_32_pd_ai , 0xf1f8, 0x2110, { 20, 22, 9, 9, 9}}, + {m68k_op_move_32_pd_pi , 0xf1f8, 0x2118, { 20, 22, 9, 9, 9}}, + {m68k_op_move_32_pd_pd , 0xf1f8, 0x2120, { 22, 24, 10, 10, 10}}, + {m68k_op_move_32_pd_di , 0xf1f8, 0x2128, { 24, 26, 10, 10, 10}}, + {m68k_op_move_32_pd_ix , 0xf1f8, 0x2130, { 26, 28, 12, 12, 12}}, + {m68k_op_move_32_di_d , 0xf1f8, 0x2140, { 16, 16, 5, 5, 5}}, + {m68k_op_move_32_di_a , 0xf1f8, 0x2148, { 16, 16, 5, 5, 5}}, + {m68k_op_move_32_di_ai , 0xf1f8, 0x2150, { 24, 24, 9, 9, 9}}, + {m68k_op_move_32_di_pi , 0xf1f8, 0x2158, { 24, 24, 9, 9, 9}}, + {m68k_op_move_32_di_pd , 0xf1f8, 0x2160, { 26, 26, 10, 10, 10}}, + {m68k_op_move_32_di_di , 0xf1f8, 0x2168, { 28, 28, 10, 10, 10}}, + {m68k_op_move_32_di_ix , 0xf1f8, 0x2170, { 30, 30, 12, 12, 12}}, + {m68k_op_move_32_ix_d , 0xf1f8, 0x2180, { 18, 18, 7, 7, 7}}, + {m68k_op_move_32_ix_a , 0xf1f8, 0x2188, { 18, 18, 7, 7, 7}}, + {m68k_op_move_32_ix_ai , 0xf1f8, 0x2190, { 26, 26, 11, 11, 11}}, + {m68k_op_move_32_ix_pi , 0xf1f8, 0x2198, { 26, 26, 11, 11, 11}}, + {m68k_op_move_32_ix_pd , 0xf1f8, 0x21a0, { 28, 28, 12, 12, 12}}, + {m68k_op_move_32_ix_di , 0xf1f8, 0x21a8, { 30, 30, 12, 12, 12}}, + {m68k_op_move_32_ix_ix , 0xf1f8, 0x21b0, { 32, 32, 14, 14, 14}}, + {m68k_op_move_16_d_d , 0xf1f8, 0x3000, { 4, 4, 2, 2, 2}}, + {m68k_op_move_16_d_a , 0xf1f8, 0x3008, { 4, 4, 2, 2, 2}}, + {m68k_op_move_16_d_ai , 0xf1f8, 0x3010, { 8, 8, 6, 6, 6}}, + {m68k_op_move_16_d_pi , 0xf1f8, 0x3018, { 8, 8, 6, 6, 6}}, + {m68k_op_move_16_d_pd , 0xf1f8, 0x3020, { 10, 10, 7, 7, 7}}, + {m68k_op_move_16_d_di , 0xf1f8, 0x3028, { 12, 12, 7, 7, 7}}, + {m68k_op_move_16_d_ix , 0xf1f8, 0x3030, { 14, 14, 9, 9, 9}}, + {m68k_op_movea_16_d , 0xf1f8, 0x3040, { 4, 4, 2, 2, 2}}, + {m68k_op_movea_16_a , 0xf1f8, 0x3048, { 4, 4, 2, 2, 2}}, + {m68k_op_movea_16_ai , 0xf1f8, 0x3050, { 8, 8, 6, 6, 6}}, + {m68k_op_movea_16_pi , 0xf1f8, 0x3058, { 8, 8, 6, 6, 6}}, + {m68k_op_movea_16_pd , 0xf1f8, 0x3060, { 10, 10, 7, 7, 7}}, + {m68k_op_movea_16_di , 0xf1f8, 0x3068, { 12, 12, 7, 7, 7}}, + {m68k_op_movea_16_ix , 0xf1f8, 0x3070, { 14, 14, 9, 9, 9}}, + {m68k_op_move_16_ai_d , 0xf1f8, 0x3080, { 8, 8, 4, 4, 4}}, + {m68k_op_move_16_ai_a , 0xf1f8, 0x3088, { 8, 8, 4, 4, 4}}, + {m68k_op_move_16_ai_ai , 0xf1f8, 0x3090, { 12, 12, 8, 8, 8}}, + {m68k_op_move_16_ai_pi , 0xf1f8, 0x3098, { 12, 12, 8, 8, 8}}, + {m68k_op_move_16_ai_pd , 0xf1f8, 0x30a0, { 14, 14, 9, 9, 9}}, + {m68k_op_move_16_ai_di , 0xf1f8, 0x30a8, { 16, 16, 9, 9, 9}}, + {m68k_op_move_16_ai_ix , 0xf1f8, 0x30b0, { 18, 18, 11, 11, 11}}, + {m68k_op_move_16_pi_d , 0xf1f8, 0x30c0, { 8, 8, 4, 4, 4}}, + {m68k_op_move_16_pi_a , 0xf1f8, 0x30c8, { 8, 8, 4, 4, 4}}, + {m68k_op_move_16_pi_ai , 0xf1f8, 0x30d0, { 12, 12, 8, 8, 8}}, + {m68k_op_move_16_pi_pi , 0xf1f8, 0x30d8, { 12, 12, 8, 8, 8}}, + {m68k_op_move_16_pi_pd , 0xf1f8, 0x30e0, { 14, 14, 9, 9, 9}}, + {m68k_op_move_16_pi_di , 0xf1f8, 0x30e8, { 16, 16, 9, 9, 9}}, + {m68k_op_move_16_pi_ix , 0xf1f8, 0x30f0, { 18, 18, 11, 11, 11}}, + {m68k_op_move_16_pd_d , 0xf1f8, 0x3100, { 8, 8, 5, 5, 5}}, + {m68k_op_move_16_pd_a , 0xf1f8, 0x3108, { 8, 8, 5, 5, 5}}, + {m68k_op_move_16_pd_ai , 0xf1f8, 0x3110, { 12, 12, 9, 9, 9}}, + {m68k_op_move_16_pd_pi , 0xf1f8, 0x3118, { 12, 12, 9, 9, 9}}, + {m68k_op_move_16_pd_pd , 0xf1f8, 0x3120, { 14, 14, 10, 10, 10}}, + {m68k_op_move_16_pd_di , 0xf1f8, 0x3128, { 16, 16, 10, 10, 10}}, + {m68k_op_move_16_pd_ix , 0xf1f8, 0x3130, { 18, 18, 12, 12, 12}}, + {m68k_op_move_16_di_d , 0xf1f8, 0x3140, { 12, 12, 5, 5, 5}}, + {m68k_op_move_16_di_a , 0xf1f8, 0x3148, { 12, 12, 5, 5, 5}}, + {m68k_op_move_16_di_ai , 0xf1f8, 0x3150, { 16, 16, 9, 9, 9}}, + {m68k_op_move_16_di_pi , 0xf1f8, 0x3158, { 16, 16, 9, 9, 9}}, + {m68k_op_move_16_di_pd , 0xf1f8, 0x3160, { 18, 18, 10, 10, 10}}, + {m68k_op_move_16_di_di , 0xf1f8, 0x3168, { 20, 20, 10, 10, 10}}, + {m68k_op_move_16_di_ix , 0xf1f8, 0x3170, { 22, 22, 12, 12, 12}}, + {m68k_op_move_16_ix_d , 0xf1f8, 0x3180, { 14, 14, 7, 7, 7}}, + {m68k_op_move_16_ix_a , 0xf1f8, 0x3188, { 14, 14, 7, 7, 7}}, + {m68k_op_move_16_ix_ai , 0xf1f8, 0x3190, { 18, 18, 11, 11, 11}}, + {m68k_op_move_16_ix_pi , 0xf1f8, 0x3198, { 18, 18, 11, 11, 11}}, + {m68k_op_move_16_ix_pd , 0xf1f8, 0x31a0, { 20, 20, 12, 12, 12}}, + {m68k_op_move_16_ix_di , 0xf1f8, 0x31a8, { 22, 22, 12, 12, 12}}, + {m68k_op_move_16_ix_ix , 0xf1f8, 0x31b0, { 24, 24, 14, 14, 14}}, + {m68k_op_chk_32_d , 0xf1f8, 0x4100, { 0, 0, 8, 8, 8}}, + {m68k_op_chk_32_ai , 0xf1f8, 0x4110, { 0, 0, 12, 12, 12}}, + {m68k_op_chk_32_pi , 0xf1f8, 0x4118, { 0, 0, 12, 12, 12}}, + {m68k_op_chk_32_pd , 0xf1f8, 0x4120, { 0, 0, 13, 13, 13}}, + {m68k_op_chk_32_di , 0xf1f8, 0x4128, { 0, 0, 13, 13, 13}}, + {m68k_op_chk_32_ix , 0xf1f8, 0x4130, { 0, 0, 15, 15, 15}}, + {m68k_op_chk_16_d , 0xf1f8, 0x4180, { 10, 8, 8, 8, 8}}, + {m68k_op_chk_16_ai , 0xf1f8, 0x4190, { 14, 12, 12, 12, 12}}, + {m68k_op_chk_16_pi , 0xf1f8, 0x4198, { 14, 12, 12, 12, 12}}, + {m68k_op_chk_16_pd , 0xf1f8, 0x41a0, { 16, 14, 13, 13, 13}}, + {m68k_op_chk_16_di , 0xf1f8, 0x41a8, { 18, 16, 13, 13, 13}}, + {m68k_op_chk_16_ix , 0xf1f8, 0x41b0, { 20, 18, 15, 15, 15}}, + {m68k_op_lea_32_ai , 0xf1f8, 0x41d0, { 4, 4, 6, 6, 6}}, + {m68k_op_lea_32_di , 0xf1f8, 0x41e8, { 8, 8, 7, 7, 7}}, + {m68k_op_lea_32_ix , 0xf1f8, 0x41f0, { 12, 12, 9, 9, 9}}, + {m68k_op_addq_8_d , 0xf1f8, 0x5000, { 4, 4, 2, 2, 2}}, + {m68k_op_addq_8_ai , 0xf1f8, 0x5010, { 12, 12, 8, 8, 8}}, + {m68k_op_addq_8_pi , 0xf1f8, 0x5018, { 12, 12, 8, 8, 8}}, + {m68k_op_addq_8_pd , 0xf1f8, 0x5020, { 14, 14, 9, 9, 9}}, + {m68k_op_addq_8_di , 0xf1f8, 0x5028, { 16, 16, 9, 9, 9}}, + {m68k_op_addq_8_ix , 0xf1f8, 0x5030, { 18, 18, 11, 11, 11}}, + {m68k_op_addq_16_d , 0xf1f8, 0x5040, { 4, 4, 2, 2, 2}}, + {m68k_op_addq_16_a , 0xf1f8, 0x5048, { 4, 4, 2, 2, 2}}, + {m68k_op_addq_16_ai , 0xf1f8, 0x5050, { 12, 12, 8, 8, 8}}, + {m68k_op_addq_16_pi , 0xf1f8, 0x5058, { 12, 12, 8, 8, 8}}, + {m68k_op_addq_16_pd , 0xf1f8, 0x5060, { 14, 14, 9, 9, 9}}, + {m68k_op_addq_16_di , 0xf1f8, 0x5068, { 16, 16, 9, 9, 9}}, + {m68k_op_addq_16_ix , 0xf1f8, 0x5070, { 18, 18, 11, 11, 11}}, + {m68k_op_addq_32_d , 0xf1f8, 0x5080, { 8, 8, 2, 2, 2}}, + {m68k_op_addq_32_a , 0xf1f8, 0x5088, { 8, 8, 2, 2, 2}}, + {m68k_op_addq_32_ai , 0xf1f8, 0x5090, { 20, 20, 8, 8, 8}}, + {m68k_op_addq_32_pi , 0xf1f8, 0x5098, { 20, 20, 8, 8, 8}}, + {m68k_op_addq_32_pd , 0xf1f8, 0x50a0, { 22, 22, 9, 9, 9}}, + {m68k_op_addq_32_di , 0xf1f8, 0x50a8, { 24, 24, 9, 9, 9}}, + {m68k_op_addq_32_ix , 0xf1f8, 0x50b0, { 26, 26, 11, 11, 11}}, + {m68k_op_subq_8_d , 0xf1f8, 0x5100, { 4, 4, 2, 2, 2}}, + {m68k_op_subq_8_ai , 0xf1f8, 0x5110, { 12, 12, 8, 8, 8}}, + {m68k_op_subq_8_pi , 0xf1f8, 0x5118, { 12, 12, 8, 8, 8}}, + {m68k_op_subq_8_pd , 0xf1f8, 0x5120, { 14, 14, 9, 9, 9}}, + {m68k_op_subq_8_di , 0xf1f8, 0x5128, { 16, 16, 9, 9, 9}}, + {m68k_op_subq_8_ix , 0xf1f8, 0x5130, { 18, 18, 11, 11, 11}}, + {m68k_op_subq_16_d , 0xf1f8, 0x5140, { 4, 4, 2, 2, 2}}, + {m68k_op_subq_16_a , 0xf1f8, 0x5148, { 8, 4, 2, 2, 2}}, + {m68k_op_subq_16_ai , 0xf1f8, 0x5150, { 12, 12, 8, 8, 8}}, + {m68k_op_subq_16_pi , 0xf1f8, 0x5158, { 12, 12, 8, 8, 8}}, + {m68k_op_subq_16_pd , 0xf1f8, 0x5160, { 14, 14, 9, 9, 9}}, + {m68k_op_subq_16_di , 0xf1f8, 0x5168, { 16, 16, 9, 9, 9}}, + {m68k_op_subq_16_ix , 0xf1f8, 0x5170, { 18, 18, 11, 11, 11}}, + {m68k_op_subq_32_d , 0xf1f8, 0x5180, { 8, 8, 2, 2, 2}}, + {m68k_op_subq_32_a , 0xf1f8, 0x5188, { 8, 8, 2, 2, 2}}, + {m68k_op_subq_32_ai , 0xf1f8, 0x5190, { 20, 20, 8, 8, 8}}, + {m68k_op_subq_32_pi , 0xf1f8, 0x5198, { 20, 20, 8, 8, 8}}, + {m68k_op_subq_32_pd , 0xf1f8, 0x51a0, { 22, 22, 9, 9, 9}}, + {m68k_op_subq_32_di , 0xf1f8, 0x51a8, { 24, 24, 9, 9, 9}}, + {m68k_op_subq_32_ix , 0xf1f8, 0x51b0, { 26, 26, 11, 11, 11}}, + {m68k_op_or_8_er_d , 0xf1f8, 0x8000, { 4, 4, 2, 2, 2}}, + {m68k_op_or_8_er_ai , 0xf1f8, 0x8010, { 8, 8, 6, 6, 6}}, + {m68k_op_or_8_er_pi , 0xf1f8, 0x8018, { 8, 8, 6, 6, 6}}, + {m68k_op_or_8_er_pd , 0xf1f8, 0x8020, { 10, 10, 7, 7, 7}}, + {m68k_op_or_8_er_di , 0xf1f8, 0x8028, { 12, 12, 7, 7, 7}}, + {m68k_op_or_8_er_ix , 0xf1f8, 0x8030, { 14, 14, 9, 9, 9}}, + {m68k_op_or_16_er_d , 0xf1f8, 0x8040, { 4, 4, 2, 2, 2}}, + {m68k_op_or_16_er_ai , 0xf1f8, 0x8050, { 8, 8, 6, 6, 6}}, + {m68k_op_or_16_er_pi , 0xf1f8, 0x8058, { 8, 8, 6, 6, 6}}, + {m68k_op_or_16_er_pd , 0xf1f8, 0x8060, { 10, 10, 7, 7, 7}}, + {m68k_op_or_16_er_di , 0xf1f8, 0x8068, { 12, 12, 7, 7, 7}}, + {m68k_op_or_16_er_ix , 0xf1f8, 0x8070, { 14, 14, 9, 9, 9}}, + {m68k_op_or_32_er_d , 0xf1f8, 0x8080, { 8, 6, 2, 2, 2}}, + {m68k_op_or_32_er_ai , 0xf1f8, 0x8090, { 14, 14, 6, 6, 6}}, + {m68k_op_or_32_er_pi , 0xf1f8, 0x8098, { 14, 14, 6, 6, 6}}, + {m68k_op_or_32_er_pd , 0xf1f8, 0x80a0, { 16, 16, 7, 7, 7}}, + {m68k_op_or_32_er_di , 0xf1f8, 0x80a8, { 18, 18, 7, 7, 7}}, + {m68k_op_or_32_er_ix , 0xf1f8, 0x80b0, { 20, 20, 9, 9, 9}}, + {m68k_op_divu_16_d , 0xf1f8, 0x80c0, {140, 108, 44, 44, 44}}, + {m68k_op_divu_16_ai , 0xf1f8, 0x80d0, {144, 112, 48, 48, 48}}, + {m68k_op_divu_16_pi , 0xf1f8, 0x80d8, {144, 112, 48, 48, 48}}, + {m68k_op_divu_16_pd , 0xf1f8, 0x80e0, {146, 114, 49, 49, 49}}, + {m68k_op_divu_16_di , 0xf1f8, 0x80e8, {148, 116, 49, 49, 49}}, + {m68k_op_divu_16_ix , 0xf1f8, 0x80f0, {150, 118, 51, 51, 51}}, + {m68k_op_sbcd_8_rr , 0xf1f8, 0x8100, { 6, 6, 4, 4, 4}}, + {m68k_op_sbcd_8_mm , 0xf1f8, 0x8108, { 18, 18, 16, 16, 16}}, + {m68k_op_or_8_re_ai , 0xf1f8, 0x8110, { 12, 12, 8, 8, 8}}, + {m68k_op_or_8_re_pi , 0xf1f8, 0x8118, { 12, 12, 8, 8, 8}}, + {m68k_op_or_8_re_pd , 0xf1f8, 0x8120, { 14, 14, 9, 9, 9}}, + {m68k_op_or_8_re_di , 0xf1f8, 0x8128, { 16, 16, 9, 9, 9}}, + {m68k_op_or_8_re_ix , 0xf1f8, 0x8130, { 18, 18, 11, 11, 11}}, + {m68k_op_pack_16_rr , 0xf1f8, 0x8140, { 0, 0, 6, 6, 6}}, + {m68k_op_pack_16_mm , 0xf1f8, 0x8148, { 0, 0, 13, 13, 13}}, + {m68k_op_or_16_re_ai , 0xf1f8, 0x8150, { 12, 12, 8, 8, 8}}, + {m68k_op_or_16_re_pi , 0xf1f8, 0x8158, { 12, 12, 8, 8, 8}}, + {m68k_op_or_16_re_pd , 0xf1f8, 0x8160, { 14, 14, 9, 9, 9}}, + {m68k_op_or_16_re_di , 0xf1f8, 0x8168, { 16, 16, 9, 9, 9}}, + {m68k_op_or_16_re_ix , 0xf1f8, 0x8170, { 18, 18, 11, 11, 11}}, + {m68k_op_unpk_16_rr , 0xf1f8, 0x8180, { 0, 0, 8, 8, 8}}, + {m68k_op_unpk_16_mm , 0xf1f8, 0x8188, { 0, 0, 13, 13, 13}}, + {m68k_op_or_32_re_ai , 0xf1f8, 0x8190, { 20, 20, 8, 8, 8}}, + {m68k_op_or_32_re_pi , 0xf1f8, 0x8198, { 20, 20, 8, 8, 8}}, + {m68k_op_or_32_re_pd , 0xf1f8, 0x81a0, { 22, 22, 9, 9, 9}}, + {m68k_op_or_32_re_di , 0xf1f8, 0x81a8, { 24, 24, 9, 9, 9}}, + {m68k_op_or_32_re_ix , 0xf1f8, 0x81b0, { 26, 26, 11, 11, 11}}, + {m68k_op_divs_16_d , 0xf1f8, 0x81c0, {158, 122, 56, 56, 56}}, + {m68k_op_divs_16_ai , 0xf1f8, 0x81d0, {162, 126, 60, 60, 60}}, + {m68k_op_divs_16_pi , 0xf1f8, 0x81d8, {162, 126, 60, 60, 60}}, + {m68k_op_divs_16_pd , 0xf1f8, 0x81e0, {164, 128, 61, 61, 61}}, + {m68k_op_divs_16_di , 0xf1f8, 0x81e8, {166, 130, 61, 61, 61}}, + {m68k_op_divs_16_ix , 0xf1f8, 0x81f0, {168, 132, 63, 63, 63}}, + {m68k_op_sub_8_er_d , 0xf1f8, 0x9000, { 4, 4, 2, 2, 2}}, + {m68k_op_sub_8_er_ai , 0xf1f8, 0x9010, { 8, 8, 6, 6, 6}}, + {m68k_op_sub_8_er_pi , 0xf1f8, 0x9018, { 8, 8, 6, 6, 6}}, + {m68k_op_sub_8_er_pd , 0xf1f8, 0x9020, { 10, 10, 7, 7, 7}}, + {m68k_op_sub_8_er_di , 0xf1f8, 0x9028, { 12, 12, 7, 7, 7}}, + {m68k_op_sub_8_er_ix , 0xf1f8, 0x9030, { 14, 14, 9, 9, 9}}, + {m68k_op_sub_16_er_d , 0xf1f8, 0x9040, { 4, 4, 2, 2, 2}}, + {m68k_op_sub_16_er_a , 0xf1f8, 0x9048, { 4, 4, 2, 2, 2}}, + {m68k_op_sub_16_er_ai , 0xf1f8, 0x9050, { 8, 8, 6, 6, 6}}, + {m68k_op_sub_16_er_pi , 0xf1f8, 0x9058, { 8, 8, 6, 6, 6}}, + {m68k_op_sub_16_er_pd , 0xf1f8, 0x9060, { 10, 10, 7, 7, 7}}, + {m68k_op_sub_16_er_di , 0xf1f8, 0x9068, { 12, 12, 7, 7, 7}}, + {m68k_op_sub_16_er_ix , 0xf1f8, 0x9070, { 14, 14, 9, 9, 9}}, + {m68k_op_sub_32_er_d , 0xf1f8, 0x9080, { 8, 6, 2, 2, 2}}, + {m68k_op_sub_32_er_a , 0xf1f8, 0x9088, { 8, 6, 2, 2, 2}}, + {m68k_op_sub_32_er_ai , 0xf1f8, 0x9090, { 14, 14, 6, 6, 6}}, + {m68k_op_sub_32_er_pi , 0xf1f8, 0x9098, { 14, 14, 6, 6, 6}}, + {m68k_op_sub_32_er_pd , 0xf1f8, 0x90a0, { 16, 16, 7, 7, 7}}, + {m68k_op_sub_32_er_di , 0xf1f8, 0x90a8, { 18, 18, 7, 7, 7}}, + {m68k_op_sub_32_er_ix , 0xf1f8, 0x90b0, { 20, 20, 9, 9, 9}}, + {m68k_op_suba_16_d , 0xf1f8, 0x90c0, { 8, 8, 2, 2, 2}}, + {m68k_op_suba_16_a , 0xf1f8, 0x90c8, { 8, 8, 2, 2, 2}}, + {m68k_op_suba_16_ai , 0xf1f8, 0x90d0, { 12, 12, 6, 6, 6}}, + {m68k_op_suba_16_pi , 0xf1f8, 0x90d8, { 12, 12, 6, 6, 6}}, + {m68k_op_suba_16_pd , 0xf1f8, 0x90e0, { 14, 14, 7, 7, 7}}, + {m68k_op_suba_16_di , 0xf1f8, 0x90e8, { 16, 16, 7, 7, 7}}, + {m68k_op_suba_16_ix , 0xf1f8, 0x90f0, { 18, 18, 9, 9, 9}}, + {m68k_op_subx_8_rr , 0xf1f8, 0x9100, { 4, 4, 2, 2, 2}}, + {m68k_op_subx_8_mm , 0xf1f8, 0x9108, { 18, 18, 12, 12, 12}}, + {m68k_op_sub_8_re_ai , 0xf1f8, 0x9110, { 12, 12, 8, 8, 8}}, + {m68k_op_sub_8_re_pi , 0xf1f8, 0x9118, { 12, 12, 8, 8, 8}}, + {m68k_op_sub_8_re_pd , 0xf1f8, 0x9120, { 14, 14, 9, 9, 9}}, + {m68k_op_sub_8_re_di , 0xf1f8, 0x9128, { 16, 16, 9, 9, 9}}, + {m68k_op_sub_8_re_ix , 0xf1f8, 0x9130, { 18, 18, 11, 11, 11}}, + {m68k_op_subx_16_rr , 0xf1f8, 0x9140, { 4, 4, 2, 2, 2}}, + {m68k_op_subx_16_mm , 0xf1f8, 0x9148, { 18, 18, 12, 12, 12}}, + {m68k_op_sub_16_re_ai , 0xf1f8, 0x9150, { 12, 12, 8, 8, 8}}, + {m68k_op_sub_16_re_pi , 0xf1f8, 0x9158, { 12, 12, 8, 8, 8}}, + {m68k_op_sub_16_re_pd , 0xf1f8, 0x9160, { 14, 14, 9, 9, 9}}, + {m68k_op_sub_16_re_di , 0xf1f8, 0x9168, { 16, 16, 9, 9, 9}}, + {m68k_op_sub_16_re_ix , 0xf1f8, 0x9170, { 18, 18, 11, 11, 11}}, + {m68k_op_subx_32_rr , 0xf1f8, 0x9180, { 8, 6, 2, 2, 2}}, + {m68k_op_subx_32_mm , 0xf1f8, 0x9188, { 30, 30, 12, 12, 12}}, + {m68k_op_sub_32_re_ai , 0xf1f8, 0x9190, { 20, 20, 8, 8, 8}}, + {m68k_op_sub_32_re_pi , 0xf1f8, 0x9198, { 20, 20, 8, 8, 8}}, + {m68k_op_sub_32_re_pd , 0xf1f8, 0x91a0, { 22, 22, 9, 9, 9}}, + {m68k_op_sub_32_re_di , 0xf1f8, 0x91a8, { 24, 24, 9, 9, 9}}, + {m68k_op_sub_32_re_ix , 0xf1f8, 0x91b0, { 26, 26, 11, 11, 11}}, + {m68k_op_suba_32_d , 0xf1f8, 0x91c0, { 8, 6, 2, 2, 2}}, + {m68k_op_suba_32_a , 0xf1f8, 0x91c8, { 8, 6, 2, 2, 2}}, + {m68k_op_suba_32_ai , 0xf1f8, 0x91d0, { 14, 14, 6, 6, 6}}, + {m68k_op_suba_32_pi , 0xf1f8, 0x91d8, { 14, 14, 6, 6, 6}}, + {m68k_op_suba_32_pd , 0xf1f8, 0x91e0, { 16, 16, 7, 7, 7}}, + {m68k_op_suba_32_di , 0xf1f8, 0x91e8, { 18, 18, 7, 7, 7}}, + {m68k_op_suba_32_ix , 0xf1f8, 0x91f0, { 20, 20, 9, 9, 9}}, + {m68k_op_cmp_8_d , 0xf1f8, 0xb000, { 4, 4, 2, 2, 2}}, + {m68k_op_cmp_8_ai , 0xf1f8, 0xb010, { 8, 8, 6, 6, 6}}, + {m68k_op_cmp_8_pi , 0xf1f8, 0xb018, { 8, 8, 6, 6, 6}}, + {m68k_op_cmp_8_pd , 0xf1f8, 0xb020, { 10, 10, 7, 7, 7}}, + {m68k_op_cmp_8_di , 0xf1f8, 0xb028, { 12, 12, 7, 7, 7}}, + {m68k_op_cmp_8_ix , 0xf1f8, 0xb030, { 14, 14, 9, 9, 9}}, + {m68k_op_cmp_16_d , 0xf1f8, 0xb040, { 4, 4, 2, 2, 2}}, + {m68k_op_cmp_16_a , 0xf1f8, 0xb048, { 4, 4, 2, 2, 2}}, + {m68k_op_cmp_16_ai , 0xf1f8, 0xb050, { 8, 8, 6, 6, 6}}, + {m68k_op_cmp_16_pi , 0xf1f8, 0xb058, { 8, 8, 6, 6, 6}}, + {m68k_op_cmp_16_pd , 0xf1f8, 0xb060, { 10, 10, 7, 7, 7}}, + {m68k_op_cmp_16_di , 0xf1f8, 0xb068, { 12, 12, 7, 7, 7}}, + {m68k_op_cmp_16_ix , 0xf1f8, 0xb070, { 14, 14, 9, 9, 9}}, + {m68k_op_cmp_32_d , 0xf1f8, 0xb080, { 6, 6, 2, 2, 2}}, + {m68k_op_cmp_32_a , 0xf1f8, 0xb088, { 6, 6, 2, 2, 2}}, + {m68k_op_cmp_32_ai , 0xf1f8, 0xb090, { 14, 14, 6, 6, 6}}, + {m68k_op_cmp_32_pi , 0xf1f8, 0xb098, { 14, 14, 6, 6, 6}}, + {m68k_op_cmp_32_pd , 0xf1f8, 0xb0a0, { 16, 16, 7, 7, 7}}, + {m68k_op_cmp_32_di , 0xf1f8, 0xb0a8, { 18, 18, 7, 7, 7}}, + {m68k_op_cmp_32_ix , 0xf1f8, 0xb0b0, { 20, 20, 9, 9, 9}}, + {m68k_op_cmpa_16_d , 0xf1f8, 0xb0c0, { 6, 6, 4, 4, 4}}, + {m68k_op_cmpa_16_a , 0xf1f8, 0xb0c8, { 6, 6, 4, 4, 4}}, + {m68k_op_cmpa_16_ai , 0xf1f8, 0xb0d0, { 10, 10, 8, 8, 8}}, + {m68k_op_cmpa_16_pi , 0xf1f8, 0xb0d8, { 10, 10, 8, 8, 8}}, + {m68k_op_cmpa_16_pd , 0xf1f8, 0xb0e0, { 12, 12, 9, 9, 9}}, + {m68k_op_cmpa_16_di , 0xf1f8, 0xb0e8, { 14, 14, 9, 9, 9}}, + {m68k_op_cmpa_16_ix , 0xf1f8, 0xb0f0, { 16, 16, 11, 11, 11}}, + {m68k_op_eor_8_d , 0xf1f8, 0xb100, { 4, 4, 2, 2, 2}}, + {m68k_op_cmpm_8 , 0xf1f8, 0xb108, { 12, 12, 9, 9, 9}}, + {m68k_op_eor_8_ai , 0xf1f8, 0xb110, { 12, 12, 8, 8, 8}}, + {m68k_op_eor_8_pi , 0xf1f8, 0xb118, { 12, 12, 8, 8, 8}}, + {m68k_op_eor_8_pd , 0xf1f8, 0xb120, { 14, 14, 9, 9, 9}}, + {m68k_op_eor_8_di , 0xf1f8, 0xb128, { 16, 16, 9, 9, 9}}, + {m68k_op_eor_8_ix , 0xf1f8, 0xb130, { 18, 18, 11, 11, 11}}, + {m68k_op_eor_16_d , 0xf1f8, 0xb140, { 4, 4, 2, 2, 2}}, + {m68k_op_cmpm_16 , 0xf1f8, 0xb148, { 12, 12, 9, 9, 9}}, + {m68k_op_eor_16_ai , 0xf1f8, 0xb150, { 12, 12, 8, 8, 8}}, + {m68k_op_eor_16_pi , 0xf1f8, 0xb158, { 12, 12, 8, 8, 8}}, + {m68k_op_eor_16_pd , 0xf1f8, 0xb160, { 14, 14, 9, 9, 9}}, + {m68k_op_eor_16_di , 0xf1f8, 0xb168, { 16, 16, 9, 9, 9}}, + {m68k_op_eor_16_ix , 0xf1f8, 0xb170, { 18, 18, 11, 11, 11}}, + {m68k_op_eor_32_d , 0xf1f8, 0xb180, { 8, 6, 2, 2, 2}}, + {m68k_op_cmpm_32 , 0xf1f8, 0xb188, { 20, 20, 9, 9, 9}}, + {m68k_op_eor_32_ai , 0xf1f8, 0xb190, { 20, 20, 8, 8, 8}}, + {m68k_op_eor_32_pi , 0xf1f8, 0xb198, { 20, 20, 8, 8, 8}}, + {m68k_op_eor_32_pd , 0xf1f8, 0xb1a0, { 22, 22, 9, 9, 9}}, + {m68k_op_eor_32_di , 0xf1f8, 0xb1a8, { 24, 24, 9, 9, 9}}, + {m68k_op_eor_32_ix , 0xf1f8, 0xb1b0, { 26, 26, 11, 11, 11}}, + {m68k_op_cmpa_32_d , 0xf1f8, 0xb1c0, { 6, 6, 4, 4, 4}}, + {m68k_op_cmpa_32_a , 0xf1f8, 0xb1c8, { 6, 6, 4, 4, 4}}, + {m68k_op_cmpa_32_ai , 0xf1f8, 0xb1d0, { 14, 14, 8, 8, 8}}, + {m68k_op_cmpa_32_pi , 0xf1f8, 0xb1d8, { 14, 14, 8, 8, 8}}, + {m68k_op_cmpa_32_pd , 0xf1f8, 0xb1e0, { 16, 16, 9, 9, 9}}, + {m68k_op_cmpa_32_di , 0xf1f8, 0xb1e8, { 18, 18, 9, 9, 9}}, + {m68k_op_cmpa_32_ix , 0xf1f8, 0xb1f0, { 20, 20, 11, 11, 11}}, + {m68k_op_and_8_er_d , 0xf1f8, 0xc000, { 4, 4, 2, 2, 2}}, + {m68k_op_and_8_er_ai , 0xf1f8, 0xc010, { 8, 8, 6, 6, 6}}, + {m68k_op_and_8_er_pi , 0xf1f8, 0xc018, { 8, 8, 6, 6, 6}}, + {m68k_op_and_8_er_pd , 0xf1f8, 0xc020, { 10, 10, 7, 7, 7}}, + {m68k_op_and_8_er_di , 0xf1f8, 0xc028, { 12, 12, 7, 7, 7}}, + {m68k_op_and_8_er_ix , 0xf1f8, 0xc030, { 14, 14, 9, 9, 9}}, + {m68k_op_and_16_er_d , 0xf1f8, 0xc040, { 4, 4, 2, 2, 2}}, + {m68k_op_and_16_er_ai , 0xf1f8, 0xc050, { 8, 8, 6, 6, 6}}, + {m68k_op_and_16_er_pi , 0xf1f8, 0xc058, { 8, 8, 6, 6, 6}}, + {m68k_op_and_16_er_pd , 0xf1f8, 0xc060, { 10, 10, 7, 7, 7}}, + {m68k_op_and_16_er_di , 0xf1f8, 0xc068, { 12, 12, 7, 7, 7}}, + {m68k_op_and_16_er_ix , 0xf1f8, 0xc070, { 14, 14, 9, 9, 9}}, + {m68k_op_and_32_er_d , 0xf1f8, 0xc080, { 8, 6, 2, 2, 2}}, + {m68k_op_and_32_er_ai , 0xf1f8, 0xc090, { 14, 14, 6, 6, 6}}, + {m68k_op_and_32_er_pi , 0xf1f8, 0xc098, { 14, 14, 6, 6, 6}}, + {m68k_op_and_32_er_pd , 0xf1f8, 0xc0a0, { 16, 16, 7, 7, 7}}, + {m68k_op_and_32_er_di , 0xf1f8, 0xc0a8, { 18, 18, 7, 7, 7}}, + {m68k_op_and_32_er_ix , 0xf1f8, 0xc0b0, { 20, 20, 9, 9, 9}}, + {m68k_op_mulu_16_d , 0xf1f8, 0xc0c0, { 54, 30, 27, 27, 27}}, + {m68k_op_mulu_16_ai , 0xf1f8, 0xc0d0, { 58, 34, 31, 31, 31}}, + {m68k_op_mulu_16_pi , 0xf1f8, 0xc0d8, { 58, 34, 31, 31, 31}}, + {m68k_op_mulu_16_pd , 0xf1f8, 0xc0e0, { 60, 36, 32, 32, 32}}, + {m68k_op_mulu_16_di , 0xf1f8, 0xc0e8, { 62, 38, 32, 32, 32}}, + {m68k_op_mulu_16_ix , 0xf1f8, 0xc0f0, { 64, 40, 34, 34, 34}}, + {m68k_op_abcd_8_rr , 0xf1f8, 0xc100, { 6, 6, 4, 4, 4}}, + {m68k_op_abcd_8_mm , 0xf1f8, 0xc108, { 18, 18, 16, 16, 16}}, + {m68k_op_and_8_re_ai , 0xf1f8, 0xc110, { 12, 12, 8, 8, 8}}, + {m68k_op_and_8_re_pi , 0xf1f8, 0xc118, { 12, 12, 8, 8, 8}}, + {m68k_op_and_8_re_pd , 0xf1f8, 0xc120, { 14, 14, 9, 9, 9}}, + {m68k_op_and_8_re_di , 0xf1f8, 0xc128, { 16, 16, 9, 9, 9}}, + {m68k_op_and_8_re_ix , 0xf1f8, 0xc130, { 18, 18, 11, 11, 11}}, + {m68k_op_exg_32_dd , 0xf1f8, 0xc140, { 6, 6, 2, 2, 2}}, + {m68k_op_exg_32_aa , 0xf1f8, 0xc148, { 6, 6, 2, 2, 2}}, + {m68k_op_and_16_re_ai , 0xf1f8, 0xc150, { 12, 12, 8, 8, 8}}, + {m68k_op_and_16_re_pi , 0xf1f8, 0xc158, { 12, 12, 8, 8, 8}}, + {m68k_op_and_16_re_pd , 0xf1f8, 0xc160, { 14, 14, 9, 9, 9}}, + {m68k_op_and_16_re_di , 0xf1f8, 0xc168, { 16, 16, 9, 9, 9}}, + {m68k_op_and_16_re_ix , 0xf1f8, 0xc170, { 18, 18, 11, 11, 11}}, + {m68k_op_exg_32_da , 0xf1f8, 0xc188, { 6, 6, 2, 2, 2}}, + {m68k_op_and_32_re_ai , 0xf1f8, 0xc190, { 20, 20, 8, 8, 8}}, + {m68k_op_and_32_re_pi , 0xf1f8, 0xc198, { 20, 20, 8, 8, 8}}, + {m68k_op_and_32_re_pd , 0xf1f8, 0xc1a0, { 22, 22, 9, 9, 9}}, + {m68k_op_and_32_re_di , 0xf1f8, 0xc1a8, { 24, 24, 9, 9, 9}}, + {m68k_op_and_32_re_ix , 0xf1f8, 0xc1b0, { 26, 26, 11, 11, 11}}, + {m68k_op_muls_16_d , 0xf1f8, 0xc1c0, { 54, 32, 27, 27, 27}}, + {m68k_op_muls_16_ai , 0xf1f8, 0xc1d0, { 58, 36, 31, 31, 31}}, + {m68k_op_muls_16_pi , 0xf1f8, 0xc1d8, { 58, 36, 31, 31, 31}}, + {m68k_op_muls_16_pd , 0xf1f8, 0xc1e0, { 60, 38, 32, 32, 32}}, + {m68k_op_muls_16_di , 0xf1f8, 0xc1e8, { 62, 40, 32, 32, 32}}, + {m68k_op_muls_16_ix , 0xf1f8, 0xc1f0, { 64, 42, 34, 34, 34}}, + {m68k_op_add_8_er_d , 0xf1f8, 0xd000, { 4, 4, 2, 2, 2}}, + {m68k_op_add_8_er_ai , 0xf1f8, 0xd010, { 8, 8, 6, 6, 6}}, + {m68k_op_add_8_er_pi , 0xf1f8, 0xd018, { 8, 8, 6, 6, 6}}, + {m68k_op_add_8_er_pd , 0xf1f8, 0xd020, { 10, 10, 7, 7, 7}}, + {m68k_op_add_8_er_di , 0xf1f8, 0xd028, { 12, 12, 7, 7, 7}}, + {m68k_op_add_8_er_ix , 0xf1f8, 0xd030, { 14, 14, 9, 9, 9}}, + {m68k_op_add_16_er_d , 0xf1f8, 0xd040, { 4, 4, 2, 2, 2}}, + {m68k_op_add_16_er_a , 0xf1f8, 0xd048, { 4, 4, 2, 2, 2}}, + {m68k_op_add_16_er_ai , 0xf1f8, 0xd050, { 8, 8, 6, 6, 6}}, + {m68k_op_add_16_er_pi , 0xf1f8, 0xd058, { 8, 8, 6, 6, 6}}, + {m68k_op_add_16_er_pd , 0xf1f8, 0xd060, { 10, 10, 7, 7, 7}}, + {m68k_op_add_16_er_di , 0xf1f8, 0xd068, { 12, 12, 7, 7, 7}}, + {m68k_op_add_16_er_ix , 0xf1f8, 0xd070, { 14, 14, 9, 9, 9}}, + {m68k_op_add_32_er_d , 0xf1f8, 0xd080, { 8, 6, 2, 2, 2}}, + {m68k_op_add_32_er_a , 0xf1f8, 0xd088, { 8, 6, 2, 2, 2}}, + {m68k_op_add_32_er_ai , 0xf1f8, 0xd090, { 14, 14, 6, 6, 6}}, + {m68k_op_add_32_er_pi , 0xf1f8, 0xd098, { 14, 14, 6, 6, 6}}, + {m68k_op_add_32_er_pd , 0xf1f8, 0xd0a0, { 16, 16, 7, 7, 7}}, + {m68k_op_add_32_er_di , 0xf1f8, 0xd0a8, { 18, 18, 7, 7, 7}}, + {m68k_op_add_32_er_ix , 0xf1f8, 0xd0b0, { 20, 20, 9, 9, 9}}, + {m68k_op_adda_16_d , 0xf1f8, 0xd0c0, { 8, 8, 2, 2, 2}}, + {m68k_op_adda_16_a , 0xf1f8, 0xd0c8, { 8, 8, 2, 2, 2}}, + {m68k_op_adda_16_ai , 0xf1f8, 0xd0d0, { 12, 12, 6, 6, 6}}, + {m68k_op_adda_16_pi , 0xf1f8, 0xd0d8, { 12, 12, 6, 6, 6}}, + {m68k_op_adda_16_pd , 0xf1f8, 0xd0e0, { 14, 14, 7, 7, 7}}, + {m68k_op_adda_16_di , 0xf1f8, 0xd0e8, { 16, 16, 7, 7, 7}}, + {m68k_op_adda_16_ix , 0xf1f8, 0xd0f0, { 18, 18, 9, 9, 9}}, + {m68k_op_addx_8_rr , 0xf1f8, 0xd100, { 4, 4, 2, 2, 2}}, + {m68k_op_addx_8_mm , 0xf1f8, 0xd108, { 18, 18, 12, 12, 12}}, + {m68k_op_add_8_re_ai , 0xf1f8, 0xd110, { 12, 12, 8, 8, 8}}, + {m68k_op_add_8_re_pi , 0xf1f8, 0xd118, { 12, 12, 8, 8, 8}}, + {m68k_op_add_8_re_pd , 0xf1f8, 0xd120, { 14, 14, 9, 9, 9}}, + {m68k_op_add_8_re_di , 0xf1f8, 0xd128, { 16, 16, 9, 9, 9}}, + {m68k_op_add_8_re_ix , 0xf1f8, 0xd130, { 18, 18, 11, 11, 11}}, + {m68k_op_addx_16_rr , 0xf1f8, 0xd140, { 4, 4, 2, 2, 2}}, + {m68k_op_addx_16_mm , 0xf1f8, 0xd148, { 18, 18, 12, 12, 12}}, + {m68k_op_add_16_re_ai , 0xf1f8, 0xd150, { 12, 12, 8, 8, 8}}, + {m68k_op_add_16_re_pi , 0xf1f8, 0xd158, { 12, 12, 8, 8, 8}}, + {m68k_op_add_16_re_pd , 0xf1f8, 0xd160, { 14, 14, 9, 9, 9}}, + {m68k_op_add_16_re_di , 0xf1f8, 0xd168, { 16, 16, 9, 9, 9}}, + {m68k_op_add_16_re_ix , 0xf1f8, 0xd170, { 18, 18, 11, 11, 11}}, + {m68k_op_addx_32_rr , 0xf1f8, 0xd180, { 8, 6, 2, 2, 2}}, + {m68k_op_addx_32_mm , 0xf1f8, 0xd188, { 30, 30, 12, 12, 12}}, + {m68k_op_add_32_re_ai , 0xf1f8, 0xd190, { 20, 20, 8, 8, 8}}, + {m68k_op_add_32_re_pi , 0xf1f8, 0xd198, { 20, 20, 8, 8, 8}}, + {m68k_op_add_32_re_pd , 0xf1f8, 0xd1a0, { 22, 22, 9, 9, 9}}, + {m68k_op_add_32_re_di , 0xf1f8, 0xd1a8, { 24, 24, 9, 9, 9}}, + {m68k_op_add_32_re_ix , 0xf1f8, 0xd1b0, { 26, 26, 11, 11, 11}}, + {m68k_op_adda_32_d , 0xf1f8, 0xd1c0, { 8, 6, 2, 2, 2}}, + {m68k_op_adda_32_a , 0xf1f8, 0xd1c8, { 8, 6, 2, 2, 2}}, + {m68k_op_adda_32_ai , 0xf1f8, 0xd1d0, { 14, 14, 6, 6, 6}}, + {m68k_op_adda_32_pi , 0xf1f8, 0xd1d8, { 14, 14, 6, 6, 6}}, + {m68k_op_adda_32_pd , 0xf1f8, 0xd1e0, { 16, 16, 7, 7, 7}}, + {m68k_op_adda_32_di , 0xf1f8, 0xd1e8, { 18, 18, 7, 7, 7}}, + {m68k_op_adda_32_ix , 0xf1f8, 0xd1f0, { 20, 20, 9, 9, 9}}, + {m68k_op_asr_8_s , 0xf1f8, 0xe000, { 6, 6, 6, 6, 6}}, + {m68k_op_lsr_8_s , 0xf1f8, 0xe008, { 6, 6, 4, 4, 4}}, + {m68k_op_roxr_8_s , 0xf1f8, 0xe010, { 6, 6, 12, 12, 12}}, + {m68k_op_ror_8_s , 0xf1f8, 0xe018, { 6, 6, 8, 8, 8}}, + {m68k_op_asr_8_r , 0xf1f8, 0xe020, { 6, 6, 6, 6, 6}}, + {m68k_op_lsr_8_r , 0xf1f8, 0xe028, { 6, 6, 6, 6, 6}}, + {m68k_op_roxr_8_r , 0xf1f8, 0xe030, { 6, 6, 12, 12, 12}}, + {m68k_op_ror_8_r , 0xf1f8, 0xe038, { 6, 6, 8, 8, 8}}, + {m68k_op_asr_16_s , 0xf1f8, 0xe040, { 6, 6, 6, 6, 6}}, + {m68k_op_lsr_16_s , 0xf1f8, 0xe048, { 6, 6, 4, 4, 4}}, + {m68k_op_roxr_16_s , 0xf1f8, 0xe050, { 6, 6, 12, 12, 12}}, + {m68k_op_ror_16_s , 0xf1f8, 0xe058, { 6, 6, 8, 8, 8}}, + {m68k_op_asr_16_r , 0xf1f8, 0xe060, { 6, 6, 6, 6, 6}}, + {m68k_op_lsr_16_r , 0xf1f8, 0xe068, { 6, 6, 6, 6, 6}}, + {m68k_op_roxr_16_r , 0xf1f8, 0xe070, { 6, 6, 12, 12, 12}}, + {m68k_op_ror_16_r , 0xf1f8, 0xe078, { 6, 6, 8, 8, 8}}, + {m68k_op_asr_32_s , 0xf1f8, 0xe080, { 8, 8, 6, 6, 6}}, + {m68k_op_lsr_32_s , 0xf1f8, 0xe088, { 8, 8, 4, 4, 4}}, + {m68k_op_roxr_32_s , 0xf1f8, 0xe090, { 8, 8, 12, 12, 12}}, + {m68k_op_ror_32_s , 0xf1f8, 0xe098, { 8, 8, 8, 8, 8}}, + {m68k_op_asr_32_r , 0xf1f8, 0xe0a0, { 8, 8, 6, 6, 6}}, + {m68k_op_lsr_32_r , 0xf1f8, 0xe0a8, { 8, 8, 6, 6, 6}}, + {m68k_op_roxr_32_r , 0xf1f8, 0xe0b0, { 8, 8, 12, 12, 12}}, + {m68k_op_ror_32_r , 0xf1f8, 0xe0b8, { 8, 8, 8, 8, 8}}, + {m68k_op_asl_8_s , 0xf1f8, 0xe100, { 6, 6, 8, 8, 8}}, + {m68k_op_lsl_8_s , 0xf1f8, 0xe108, { 6, 6, 4, 4, 4}}, + {m68k_op_roxl_8_s , 0xf1f8, 0xe110, { 6, 6, 12, 12, 12}}, + {m68k_op_rol_8_s , 0xf1f8, 0xe118, { 6, 6, 8, 8, 8}}, + {m68k_op_asl_8_r , 0xf1f8, 0xe120, { 6, 6, 8, 8, 8}}, + {m68k_op_lsl_8_r , 0xf1f8, 0xe128, { 6, 6, 6, 6, 6}}, + {m68k_op_roxl_8_r , 0xf1f8, 0xe130, { 6, 6, 12, 12, 12}}, + {m68k_op_rol_8_r , 0xf1f8, 0xe138, { 6, 6, 8, 8, 8}}, + {m68k_op_asl_16_s , 0xf1f8, 0xe140, { 6, 6, 8, 8, 8}}, + {m68k_op_lsl_16_s , 0xf1f8, 0xe148, { 6, 6, 4, 4, 4}}, + {m68k_op_roxl_16_s , 0xf1f8, 0xe150, { 6, 6, 12, 12, 12}}, + {m68k_op_rol_16_s , 0xf1f8, 0xe158, { 6, 6, 8, 8, 8}}, + {m68k_op_asl_16_r , 0xf1f8, 0xe160, { 6, 6, 8, 8, 8}}, + {m68k_op_lsl_16_r , 0xf1f8, 0xe168, { 6, 6, 6, 6, 6}}, + {m68k_op_roxl_16_r , 0xf1f8, 0xe170, { 6, 6, 12, 12, 12}}, + {m68k_op_rol_16_r , 0xf1f8, 0xe178, { 6, 6, 8, 8, 8}}, + {m68k_op_asl_32_s , 0xf1f8, 0xe180, { 8, 8, 8, 8, 8}}, + {m68k_op_lsl_32_s , 0xf1f8, 0xe188, { 8, 8, 4, 4, 4}}, + {m68k_op_roxl_32_s , 0xf1f8, 0xe190, { 8, 8, 12, 12, 12}}, + {m68k_op_rol_32_s , 0xf1f8, 0xe198, { 8, 8, 8, 8, 8}}, + {m68k_op_asl_32_r , 0xf1f8, 0xe1a0, { 8, 8, 8, 8, 8}}, + {m68k_op_lsl_32_r , 0xf1f8, 0xe1a8, { 8, 8, 6, 6, 6}}, + {m68k_op_roxl_32_r , 0xf1f8, 0xe1b0, { 8, 8, 12, 12, 12}}, + {m68k_op_rol_32_r , 0xf1f8, 0xe1b8, { 8, 8, 8, 8, 8}}, + {m68k_op_cpdbcc_32 , 0xf1f8, 0xf048, { 0, 0, 4, 4, 0}}, + {m68k_op_cptrapcc_32 , 0xf1f8, 0xf078, { 0, 0, 4, 4, 0}}, + {m68k_op_rtm_32 , 0xfff0, 0x06c0, { 0, 0, 19, 19, 19}}, + {m68k_op_trap , 0xfff0, 0x4e40, { 4, 4, 4, 4, 4}}, + {m68k_op_btst_8_r_pi7 , 0xf1ff, 0x011f, { 8, 8, 8, 8, 8}}, + {m68k_op_btst_8_r_pd7 , 0xf1ff, 0x0127, { 10, 10, 9, 9, 9}}, + {m68k_op_btst_8_r_aw , 0xf1ff, 0x0138, { 12, 12, 8, 8, 8}}, + {m68k_op_btst_8_r_al , 0xf1ff, 0x0139, { 16, 16, 8, 8, 8}}, + {m68k_op_btst_8_r_pcdi , 0xf1ff, 0x013a, { 12, 12, 9, 9, 9}}, + {m68k_op_btst_8_r_pcix , 0xf1ff, 0x013b, { 14, 14, 11, 11, 11}}, + {m68k_op_btst_8_r_i , 0xf1ff, 0x013c, { 8, 8, 6, 6, 6}}, + {m68k_op_bchg_8_r_pi7 , 0xf1ff, 0x015f, { 12, 12, 8, 8, 8}}, + {m68k_op_bchg_8_r_pd7 , 0xf1ff, 0x0167, { 14, 14, 9, 9, 9}}, + {m68k_op_bchg_8_r_aw , 0xf1ff, 0x0178, { 16, 16, 8, 8, 8}}, + {m68k_op_bchg_8_r_al , 0xf1ff, 0x0179, { 20, 20, 8, 8, 8}}, + {m68k_op_bclr_8_r_pi7 , 0xf1ff, 0x019f, { 12, 14, 8, 8, 8}}, + {m68k_op_bclr_8_r_pd7 , 0xf1ff, 0x01a7, { 14, 16, 9, 9, 9}}, + {m68k_op_bclr_8_r_aw , 0xf1ff, 0x01b8, { 16, 18, 8, 8, 8}}, + {m68k_op_bclr_8_r_al , 0xf1ff, 0x01b9, { 20, 22, 8, 8, 8}}, + {m68k_op_bset_8_r_pi7 , 0xf1ff, 0x01df, { 12, 12, 8, 8, 8}}, + {m68k_op_bset_8_r_pd7 , 0xf1ff, 0x01e7, { 14, 14, 9, 9, 9}}, + {m68k_op_bset_8_r_aw , 0xf1ff, 0x01f8, { 16, 16, 8, 8, 8}}, + {m68k_op_bset_8_r_al , 0xf1ff, 0x01f9, { 20, 20, 8, 8, 8}}, + {m68k_op_move_8_d_pi7 , 0xf1ff, 0x101f, { 8, 8, 6, 6, 6}}, + {m68k_op_move_8_d_pd7 , 0xf1ff, 0x1027, { 10, 10, 7, 7, 7}}, + {m68k_op_move_8_d_aw , 0xf1ff, 0x1038, { 12, 12, 6, 6, 6}}, + {m68k_op_move_8_d_al , 0xf1ff, 0x1039, { 16, 16, 6, 6, 6}}, + {m68k_op_move_8_d_pcdi , 0xf1ff, 0x103a, { 12, 12, 7, 7, 7}}, + {m68k_op_move_8_d_pcix , 0xf1ff, 0x103b, { 14, 14, 9, 9, 9}}, + {m68k_op_move_8_d_i , 0xf1ff, 0x103c, { 8, 8, 4, 4, 4}}, + {m68k_op_move_8_ai_pi7 , 0xf1ff, 0x109f, { 12, 12, 8, 8, 8}}, + {m68k_op_move_8_ai_pd7 , 0xf1ff, 0x10a7, { 14, 14, 9, 9, 9}}, + {m68k_op_move_8_ai_aw , 0xf1ff, 0x10b8, { 16, 16, 8, 8, 8}}, + {m68k_op_move_8_ai_al , 0xf1ff, 0x10b9, { 20, 20, 8, 8, 8}}, + {m68k_op_move_8_ai_pcdi , 0xf1ff, 0x10ba, { 16, 16, 9, 9, 9}}, + {m68k_op_move_8_ai_pcix , 0xf1ff, 0x10bb, { 18, 18, 11, 11, 11}}, + {m68k_op_move_8_ai_i , 0xf1ff, 0x10bc, { 12, 12, 6, 6, 6}}, + {m68k_op_move_8_pi_pi7 , 0xf1ff, 0x10df, { 12, 12, 8, 8, 8}}, + {m68k_op_move_8_pi_pd7 , 0xf1ff, 0x10e7, { 14, 14, 9, 9, 9}}, + {m68k_op_move_8_pi_aw , 0xf1ff, 0x10f8, { 16, 16, 8, 8, 8}}, + {m68k_op_move_8_pi_al , 0xf1ff, 0x10f9, { 20, 20, 8, 8, 8}}, + {m68k_op_move_8_pi_pcdi , 0xf1ff, 0x10fa, { 16, 16, 9, 9, 9}}, + {m68k_op_move_8_pi_pcix , 0xf1ff, 0x10fb, { 18, 18, 11, 11, 11}}, + {m68k_op_move_8_pi_i , 0xf1ff, 0x10fc, { 12, 12, 6, 6, 6}}, + {m68k_op_move_8_pd_pi7 , 0xf1ff, 0x111f, { 12, 12, 9, 9, 9}}, + {m68k_op_move_8_pd_pd7 , 0xf1ff, 0x1127, { 14, 14, 10, 10, 10}}, + {m68k_op_move_8_pd_aw , 0xf1ff, 0x1138, { 16, 16, 9, 9, 9}}, + {m68k_op_move_8_pd_al , 0xf1ff, 0x1139, { 20, 20, 9, 9, 9}}, + {m68k_op_move_8_pd_pcdi , 0xf1ff, 0x113a, { 16, 16, 10, 10, 10}}, + {m68k_op_move_8_pd_pcix , 0xf1ff, 0x113b, { 18, 18, 12, 12, 12}}, + {m68k_op_move_8_pd_i , 0xf1ff, 0x113c, { 12, 12, 7, 7, 7}}, + {m68k_op_move_8_di_pi7 , 0xf1ff, 0x115f, { 16, 16, 9, 9, 9}}, + {m68k_op_move_8_di_pd7 , 0xf1ff, 0x1167, { 18, 18, 10, 10, 10}}, + {m68k_op_move_8_di_aw , 0xf1ff, 0x1178, { 20, 20, 9, 9, 9}}, + {m68k_op_move_8_di_al , 0xf1ff, 0x1179, { 24, 24, 9, 9, 9}}, + {m68k_op_move_8_di_pcdi , 0xf1ff, 0x117a, { 20, 20, 10, 10, 10}}, + {m68k_op_move_8_di_pcix , 0xf1ff, 0x117b, { 22, 22, 12, 12, 12}}, + {m68k_op_move_8_di_i , 0xf1ff, 0x117c, { 16, 16, 7, 7, 7}}, + {m68k_op_move_8_ix_pi7 , 0xf1ff, 0x119f, { 18, 18, 11, 11, 11}}, + {m68k_op_move_8_ix_pd7 , 0xf1ff, 0x11a7, { 20, 20, 12, 12, 12}}, + {m68k_op_move_8_ix_aw , 0xf1ff, 0x11b8, { 22, 22, 11, 11, 11}}, + {m68k_op_move_8_ix_al , 0xf1ff, 0x11b9, { 26, 26, 11, 11, 11}}, + {m68k_op_move_8_ix_pcdi , 0xf1ff, 0x11ba, { 22, 22, 12, 12, 12}}, + {m68k_op_move_8_ix_pcix , 0xf1ff, 0x11bb, { 24, 24, 14, 14, 14}}, + {m68k_op_move_8_ix_i , 0xf1ff, 0x11bc, { 18, 18, 9, 9, 9}}, + {m68k_op_move_32_d_aw , 0xf1ff, 0x2038, { 16, 16, 6, 6, 6}}, + {m68k_op_move_32_d_al , 0xf1ff, 0x2039, { 20, 20, 6, 6, 6}}, + {m68k_op_move_32_d_pcdi , 0xf1ff, 0x203a, { 16, 16, 7, 7, 7}}, + {m68k_op_move_32_d_pcix , 0xf1ff, 0x203b, { 18, 18, 9, 9, 9}}, + {m68k_op_move_32_d_i , 0xf1ff, 0x203c, { 12, 12, 6, 6, 6}}, + {m68k_op_movea_32_aw , 0xf1ff, 0x2078, { 16, 16, 6, 6, 6}}, + {m68k_op_movea_32_al , 0xf1ff, 0x2079, { 20, 20, 6, 6, 6}}, + {m68k_op_movea_32_pcdi , 0xf1ff, 0x207a, { 16, 16, 7, 7, 7}}, + {m68k_op_movea_32_pcix , 0xf1ff, 0x207b, { 18, 18, 9, 9, 9}}, + {m68k_op_movea_32_i , 0xf1ff, 0x207c, { 12, 12, 6, 6, 6}}, + {m68k_op_move_32_ai_aw , 0xf1ff, 0x20b8, { 24, 24, 8, 8, 8}}, + {m68k_op_move_32_ai_al , 0xf1ff, 0x20b9, { 28, 28, 8, 8, 8}}, + {m68k_op_move_32_ai_pcdi , 0xf1ff, 0x20ba, { 24, 24, 9, 9, 9}}, + {m68k_op_move_32_ai_pcix , 0xf1ff, 0x20bb, { 26, 26, 11, 11, 11}}, + {m68k_op_move_32_ai_i , 0xf1ff, 0x20bc, { 20, 20, 8, 8, 8}}, + {m68k_op_move_32_pi_aw , 0xf1ff, 0x20f8, { 24, 24, 8, 8, 8}}, + {m68k_op_move_32_pi_al , 0xf1ff, 0x20f9, { 28, 28, 8, 8, 8}}, + {m68k_op_move_32_pi_pcdi , 0xf1ff, 0x20fa, { 24, 24, 9, 9, 9}}, + {m68k_op_move_32_pi_pcix , 0xf1ff, 0x20fb, { 26, 26, 11, 11, 11}}, + {m68k_op_move_32_pi_i , 0xf1ff, 0x20fc, { 20, 20, 8, 8, 8}}, + {m68k_op_move_32_pd_aw , 0xf1ff, 0x2138, { 24, 26, 9, 9, 9}}, + {m68k_op_move_32_pd_al , 0xf1ff, 0x2139, { 28, 30, 9, 9, 9}}, + {m68k_op_move_32_pd_pcdi , 0xf1ff, 0x213a, { 24, 26, 10, 10, 10}}, + {m68k_op_move_32_pd_pcix , 0xf1ff, 0x213b, { 26, 28, 12, 12, 12}}, + {m68k_op_move_32_pd_i , 0xf1ff, 0x213c, { 20, 22, 9, 9, 9}}, + {m68k_op_move_32_di_aw , 0xf1ff, 0x2178, { 28, 28, 9, 9, 9}}, + {m68k_op_move_32_di_al , 0xf1ff, 0x2179, { 32, 32, 9, 9, 9}}, + {m68k_op_move_32_di_pcdi , 0xf1ff, 0x217a, { 28, 28, 10, 10, 10}}, + {m68k_op_move_32_di_pcix , 0xf1ff, 0x217b, { 30, 30, 12, 12, 12}}, + {m68k_op_move_32_di_i , 0xf1ff, 0x217c, { 24, 24, 9, 9, 9}}, + {m68k_op_move_32_ix_aw , 0xf1ff, 0x21b8, { 30, 30, 11, 11, 11}}, + {m68k_op_move_32_ix_al , 0xf1ff, 0x21b9, { 34, 34, 11, 11, 11}}, + {m68k_op_move_32_ix_pcdi , 0xf1ff, 0x21ba, { 30, 30, 12, 12, 12}}, + {m68k_op_move_32_ix_pcix , 0xf1ff, 0x21bb, { 32, 32, 14, 14, 14}}, + {m68k_op_move_32_ix_i , 0xf1ff, 0x21bc, { 26, 26, 11, 11, 11}}, + {m68k_op_move_16_d_aw , 0xf1ff, 0x3038, { 12, 12, 6, 6, 6}}, + {m68k_op_move_16_d_al , 0xf1ff, 0x3039, { 16, 16, 6, 6, 6}}, + {m68k_op_move_16_d_pcdi , 0xf1ff, 0x303a, { 12, 12, 7, 7, 7}}, + {m68k_op_move_16_d_pcix , 0xf1ff, 0x303b, { 14, 14, 9, 9, 9}}, + {m68k_op_move_16_d_i , 0xf1ff, 0x303c, { 8, 8, 4, 4, 4}}, + {m68k_op_movea_16_aw , 0xf1ff, 0x3078, { 12, 12, 6, 6, 6}}, + {m68k_op_movea_16_al , 0xf1ff, 0x3079, { 16, 16, 6, 6, 6}}, + {m68k_op_movea_16_pcdi , 0xf1ff, 0x307a, { 12, 12, 7, 7, 7}}, + {m68k_op_movea_16_pcix , 0xf1ff, 0x307b, { 14, 14, 9, 9, 9}}, + {m68k_op_movea_16_i , 0xf1ff, 0x307c, { 8, 8, 4, 4, 4}}, + {m68k_op_move_16_ai_aw , 0xf1ff, 0x30b8, { 16, 16, 8, 8, 8}}, + {m68k_op_move_16_ai_al , 0xf1ff, 0x30b9, { 20, 20, 8, 8, 8}}, + {m68k_op_move_16_ai_pcdi , 0xf1ff, 0x30ba, { 16, 16, 9, 9, 9}}, + {m68k_op_move_16_ai_pcix , 0xf1ff, 0x30bb, { 18, 18, 11, 11, 11}}, + {m68k_op_move_16_ai_i , 0xf1ff, 0x30bc, { 12, 12, 6, 6, 6}}, + {m68k_op_move_16_pi_aw , 0xf1ff, 0x30f8, { 16, 16, 8, 8, 8}}, + {m68k_op_move_16_pi_al , 0xf1ff, 0x30f9, { 20, 20, 8, 8, 8}}, + {m68k_op_move_16_pi_pcdi , 0xf1ff, 0x30fa, { 16, 16, 9, 9, 9}}, + {m68k_op_move_16_pi_pcix , 0xf1ff, 0x30fb, { 18, 18, 11, 11, 11}}, + {m68k_op_move_16_pi_i , 0xf1ff, 0x30fc, { 12, 12, 6, 6, 6}}, + {m68k_op_move_16_pd_aw , 0xf1ff, 0x3138, { 16, 16, 9, 9, 9}}, + {m68k_op_move_16_pd_al , 0xf1ff, 0x3139, { 20, 20, 9, 9, 9}}, + {m68k_op_move_16_pd_pcdi , 0xf1ff, 0x313a, { 16, 16, 10, 10, 10}}, + {m68k_op_move_16_pd_pcix , 0xf1ff, 0x313b, { 18, 18, 12, 12, 12}}, + {m68k_op_move_16_pd_i , 0xf1ff, 0x313c, { 12, 12, 7, 7, 7}}, + {m68k_op_move_16_di_aw , 0xf1ff, 0x3178, { 20, 20, 9, 9, 9}}, + {m68k_op_move_16_di_al , 0xf1ff, 0x3179, { 24, 24, 9, 9, 9}}, + {m68k_op_move_16_di_pcdi , 0xf1ff, 0x317a, { 20, 20, 10, 10, 10}}, + {m68k_op_move_16_di_pcix , 0xf1ff, 0x317b, { 22, 22, 12, 12, 12}}, + {m68k_op_move_16_di_i , 0xf1ff, 0x317c, { 16, 16, 7, 7, 7}}, + {m68k_op_move_16_ix_aw , 0xf1ff, 0x31b8, { 22, 22, 11, 11, 11}}, + {m68k_op_move_16_ix_al , 0xf1ff, 0x31b9, { 26, 26, 11, 11, 11}}, + {m68k_op_move_16_ix_pcdi , 0xf1ff, 0x31ba, { 22, 22, 12, 12, 12}}, + {m68k_op_move_16_ix_pcix , 0xf1ff, 0x31bb, { 24, 24, 14, 14, 14}}, + {m68k_op_move_16_ix_i , 0xf1ff, 0x31bc, { 18, 18, 9, 9, 9}}, + {m68k_op_chk_32_aw , 0xf1ff, 0x4138, { 0, 0, 12, 12, 12}}, + {m68k_op_chk_32_al , 0xf1ff, 0x4139, { 0, 0, 12, 12, 12}}, + {m68k_op_chk_32_pcdi , 0xf1ff, 0x413a, { 0, 0, 13, 13, 13}}, + {m68k_op_chk_32_pcix , 0xf1ff, 0x413b, { 0, 0, 15, 15, 15}}, + {m68k_op_chk_32_i , 0xf1ff, 0x413c, { 0, 0, 12, 12, 12}}, + {m68k_op_chk_16_aw , 0xf1ff, 0x41b8, { 18, 16, 12, 12, 12}}, + {m68k_op_chk_16_al , 0xf1ff, 0x41b9, { 22, 20, 12, 12, 12}}, + {m68k_op_chk_16_pcdi , 0xf1ff, 0x41ba, { 18, 16, 13, 13, 13}}, + {m68k_op_chk_16_pcix , 0xf1ff, 0x41bb, { 20, 18, 15, 15, 15}}, + {m68k_op_chk_16_i , 0xf1ff, 0x41bc, { 14, 12, 10, 10, 10}}, + {m68k_op_lea_32_aw , 0xf1ff, 0x41f8, { 8, 8, 6, 6, 6}}, + {m68k_op_lea_32_al , 0xf1ff, 0x41f9, { 12, 12, 6, 6, 6}}, + {m68k_op_lea_32_pcdi , 0xf1ff, 0x41fa, { 8, 8, 7, 7, 7}}, + {m68k_op_lea_32_pcix , 0xf1ff, 0x41fb, { 12, 12, 9, 9, 9}}, + {m68k_op_addq_8_pi7 , 0xf1ff, 0x501f, { 12, 12, 8, 8, 8}}, + {m68k_op_addq_8_pd7 , 0xf1ff, 0x5027, { 14, 14, 9, 9, 9}}, + {m68k_op_addq_8_aw , 0xf1ff, 0x5038, { 16, 16, 8, 8, 8}}, + {m68k_op_addq_8_al , 0xf1ff, 0x5039, { 20, 20, 8, 8, 8}}, + {m68k_op_addq_16_aw , 0xf1ff, 0x5078, { 16, 16, 8, 8, 8}}, + {m68k_op_addq_16_al , 0xf1ff, 0x5079, { 20, 20, 8, 8, 8}}, + {m68k_op_addq_32_aw , 0xf1ff, 0x50b8, { 24, 24, 8, 8, 8}}, + {m68k_op_addq_32_al , 0xf1ff, 0x50b9, { 28, 28, 8, 8, 8}}, + {m68k_op_subq_8_pi7 , 0xf1ff, 0x511f, { 12, 12, 8, 8, 8}}, + {m68k_op_subq_8_pd7 , 0xf1ff, 0x5127, { 14, 14, 9, 9, 9}}, + {m68k_op_subq_8_aw , 0xf1ff, 0x5138, { 16, 16, 8, 8, 8}}, + {m68k_op_subq_8_al , 0xf1ff, 0x5139, { 20, 20, 8, 8, 8}}, + {m68k_op_subq_16_aw , 0xf1ff, 0x5178, { 16, 16, 8, 8, 8}}, + {m68k_op_subq_16_al , 0xf1ff, 0x5179, { 20, 20, 8, 8, 8}}, + {m68k_op_subq_32_aw , 0xf1ff, 0x51b8, { 24, 24, 8, 8, 8}}, + {m68k_op_subq_32_al , 0xf1ff, 0x51b9, { 28, 28, 8, 8, 8}}, + {m68k_op_or_8_er_pi7 , 0xf1ff, 0x801f, { 8, 8, 6, 6, 6}}, + {m68k_op_or_8_er_pd7 , 0xf1ff, 0x8027, { 10, 10, 7, 7, 7}}, + {m68k_op_or_8_er_aw , 0xf1ff, 0x8038, { 12, 12, 6, 6, 6}}, + {m68k_op_or_8_er_al , 0xf1ff, 0x8039, { 16, 16, 6, 6, 6}}, + {m68k_op_or_8_er_pcdi , 0xf1ff, 0x803a, { 12, 12, 7, 7, 7}}, + {m68k_op_or_8_er_pcix , 0xf1ff, 0x803b, { 14, 14, 9, 9, 9}}, + {m68k_op_or_8_er_i , 0xf1ff, 0x803c, { 8, 8, 4, 4, 4}}, + {m68k_op_or_16_er_aw , 0xf1ff, 0x8078, { 12, 12, 6, 6, 6}}, + {m68k_op_or_16_er_al , 0xf1ff, 0x8079, { 16, 16, 6, 6, 6}}, + {m68k_op_or_16_er_pcdi , 0xf1ff, 0x807a, { 12, 12, 7, 7, 7}}, + {m68k_op_or_16_er_pcix , 0xf1ff, 0x807b, { 14, 14, 9, 9, 9}}, + {m68k_op_or_16_er_i , 0xf1ff, 0x807c, { 8, 8, 4, 4, 4}}, + {m68k_op_or_32_er_aw , 0xf1ff, 0x80b8, { 18, 18, 6, 6, 6}}, + {m68k_op_or_32_er_al , 0xf1ff, 0x80b9, { 22, 22, 6, 6, 6}}, + {m68k_op_or_32_er_pcdi , 0xf1ff, 0x80ba, { 18, 18, 7, 7, 7}}, + {m68k_op_or_32_er_pcix , 0xf1ff, 0x80bb, { 20, 20, 9, 9, 9}}, + {m68k_op_or_32_er_i , 0xf1ff, 0x80bc, { 16, 14, 6, 6, 6}}, + {m68k_op_divu_16_aw , 0xf1ff, 0x80f8, {148, 116, 48, 48, 48}}, + {m68k_op_divu_16_al , 0xf1ff, 0x80f9, {152, 120, 48, 48, 48}}, + {m68k_op_divu_16_pcdi , 0xf1ff, 0x80fa, {148, 116, 49, 49, 49}}, + {m68k_op_divu_16_pcix , 0xf1ff, 0x80fb, {150, 118, 51, 51, 51}}, + {m68k_op_divu_16_i , 0xf1ff, 0x80fc, {144, 112, 46, 46, 46}}, + {m68k_op_sbcd_8_mm_ay7 , 0xf1ff, 0x810f, { 18, 18, 16, 16, 16}}, + {m68k_op_or_8_re_pi7 , 0xf1ff, 0x811f, { 12, 12, 8, 8, 8}}, + {m68k_op_or_8_re_pd7 , 0xf1ff, 0x8127, { 14, 14, 9, 9, 9}}, + {m68k_op_or_8_re_aw , 0xf1ff, 0x8138, { 16, 16, 8, 8, 8}}, + {m68k_op_or_8_re_al , 0xf1ff, 0x8139, { 20, 20, 8, 8, 8}}, + {m68k_op_pack_16_mm_ay7 , 0xf1ff, 0x814f, { 0, 0, 13, 13, 13}}, + {m68k_op_or_16_re_aw , 0xf1ff, 0x8178, { 16, 16, 8, 8, 8}}, + {m68k_op_or_16_re_al , 0xf1ff, 0x8179, { 20, 20, 8, 8, 8}}, + {m68k_op_unpk_16_mm_ay7 , 0xf1ff, 0x818f, { 0, 0, 13, 13, 13}}, + {m68k_op_or_32_re_aw , 0xf1ff, 0x81b8, { 24, 24, 8, 8, 8}}, + {m68k_op_or_32_re_al , 0xf1ff, 0x81b9, { 28, 28, 8, 8, 8}}, + {m68k_op_divs_16_aw , 0xf1ff, 0x81f8, {166, 130, 60, 60, 60}}, + {m68k_op_divs_16_al , 0xf1ff, 0x81f9, {170, 134, 60, 60, 60}}, + {m68k_op_divs_16_pcdi , 0xf1ff, 0x81fa, {166, 130, 61, 61, 61}}, + {m68k_op_divs_16_pcix , 0xf1ff, 0x81fb, {168, 132, 63, 63, 63}}, + {m68k_op_divs_16_i , 0xf1ff, 0x81fc, {162, 126, 58, 58, 58}}, + {m68k_op_sub_8_er_pi7 , 0xf1ff, 0x901f, { 8, 8, 6, 6, 6}}, + {m68k_op_sub_8_er_pd7 , 0xf1ff, 0x9027, { 10, 10, 7, 7, 7}}, + {m68k_op_sub_8_er_aw , 0xf1ff, 0x9038, { 12, 12, 6, 6, 6}}, + {m68k_op_sub_8_er_al , 0xf1ff, 0x9039, { 16, 16, 6, 6, 6}}, + {m68k_op_sub_8_er_pcdi , 0xf1ff, 0x903a, { 12, 12, 7, 7, 7}}, + {m68k_op_sub_8_er_pcix , 0xf1ff, 0x903b, { 14, 14, 9, 9, 9}}, + {m68k_op_sub_8_er_i , 0xf1ff, 0x903c, { 8, 8, 4, 4, 4}}, + {m68k_op_sub_16_er_aw , 0xf1ff, 0x9078, { 12, 12, 6, 6, 6}}, + {m68k_op_sub_16_er_al , 0xf1ff, 0x9079, { 16, 16, 6, 6, 6}}, + {m68k_op_sub_16_er_pcdi , 0xf1ff, 0x907a, { 12, 12, 7, 7, 7}}, + {m68k_op_sub_16_er_pcix , 0xf1ff, 0x907b, { 14, 14, 9, 9, 9}}, + {m68k_op_sub_16_er_i , 0xf1ff, 0x907c, { 8, 8, 4, 4, 4}}, + {m68k_op_sub_32_er_aw , 0xf1ff, 0x90b8, { 18, 18, 6, 6, 6}}, + {m68k_op_sub_32_er_al , 0xf1ff, 0x90b9, { 22, 22, 6, 6, 6}}, + {m68k_op_sub_32_er_pcdi , 0xf1ff, 0x90ba, { 18, 18, 7, 7, 7}}, + {m68k_op_sub_32_er_pcix , 0xf1ff, 0x90bb, { 20, 20, 9, 9, 9}}, + {m68k_op_sub_32_er_i , 0xf1ff, 0x90bc, { 16, 14, 6, 6, 6}}, + {m68k_op_suba_16_aw , 0xf1ff, 0x90f8, { 16, 16, 6, 6, 6}}, + {m68k_op_suba_16_al , 0xf1ff, 0x90f9, { 20, 20, 6, 6, 6}}, + {m68k_op_suba_16_pcdi , 0xf1ff, 0x90fa, { 16, 16, 7, 7, 7}}, + {m68k_op_suba_16_pcix , 0xf1ff, 0x90fb, { 18, 18, 9, 9, 9}}, + {m68k_op_suba_16_i , 0xf1ff, 0x90fc, { 12, 12, 4, 4, 4}}, + {m68k_op_subx_8_mm_ay7 , 0xf1ff, 0x910f, { 18, 18, 12, 12, 12}}, + {m68k_op_sub_8_re_pi7 , 0xf1ff, 0x911f, { 12, 12, 8, 8, 8}}, + {m68k_op_sub_8_re_pd7 , 0xf1ff, 0x9127, { 14, 14, 9, 9, 9}}, + {m68k_op_sub_8_re_aw , 0xf1ff, 0x9138, { 16, 16, 8, 8, 8}}, + {m68k_op_sub_8_re_al , 0xf1ff, 0x9139, { 20, 20, 8, 8, 8}}, + {m68k_op_sub_16_re_aw , 0xf1ff, 0x9178, { 16, 16, 8, 8, 8}}, + {m68k_op_sub_16_re_al , 0xf1ff, 0x9179, { 20, 20, 8, 8, 8}}, + {m68k_op_sub_32_re_aw , 0xf1ff, 0x91b8, { 24, 24, 8, 8, 8}}, + {m68k_op_sub_32_re_al , 0xf1ff, 0x91b9, { 28, 28, 8, 8, 8}}, + {m68k_op_suba_32_aw , 0xf1ff, 0x91f8, { 18, 18, 6, 6, 6}}, + {m68k_op_suba_32_al , 0xf1ff, 0x91f9, { 22, 22, 6, 6, 6}}, + {m68k_op_suba_32_pcdi , 0xf1ff, 0x91fa, { 18, 18, 7, 7, 7}}, + {m68k_op_suba_32_pcix , 0xf1ff, 0x91fb, { 20, 20, 9, 9, 9}}, + {m68k_op_suba_32_i , 0xf1ff, 0x91fc, { 16, 14, 6, 6, 6}}, + {m68k_op_cmp_8_pi7 , 0xf1ff, 0xb01f, { 8, 8, 6, 6, 6}}, + {m68k_op_cmp_8_pd7 , 0xf1ff, 0xb027, { 10, 10, 7, 7, 7}}, + {m68k_op_cmp_8_aw , 0xf1ff, 0xb038, { 12, 12, 6, 6, 6}}, + {m68k_op_cmp_8_al , 0xf1ff, 0xb039, { 16, 16, 6, 6, 6}}, + {m68k_op_cmp_8_pcdi , 0xf1ff, 0xb03a, { 12, 12, 7, 7, 7}}, + {m68k_op_cmp_8_pcix , 0xf1ff, 0xb03b, { 14, 14, 9, 9, 9}}, + {m68k_op_cmp_8_i , 0xf1ff, 0xb03c, { 8, 8, 4, 4, 4}}, + {m68k_op_cmp_16_aw , 0xf1ff, 0xb078, { 12, 12, 6, 6, 6}}, + {m68k_op_cmp_16_al , 0xf1ff, 0xb079, { 16, 16, 6, 6, 6}}, + {m68k_op_cmp_16_pcdi , 0xf1ff, 0xb07a, { 12, 12, 7, 7, 7}}, + {m68k_op_cmp_16_pcix , 0xf1ff, 0xb07b, { 14, 14, 9, 9, 9}}, + {m68k_op_cmp_16_i , 0xf1ff, 0xb07c, { 8, 8, 4, 4, 4}}, + {m68k_op_cmp_32_aw , 0xf1ff, 0xb0b8, { 18, 18, 6, 6, 6}}, + {m68k_op_cmp_32_al , 0xf1ff, 0xb0b9, { 22, 22, 6, 6, 6}}, + {m68k_op_cmp_32_pcdi , 0xf1ff, 0xb0ba, { 18, 18, 7, 7, 7}}, + {m68k_op_cmp_32_pcix , 0xf1ff, 0xb0bb, { 20, 20, 9, 9, 9}}, + {m68k_op_cmp_32_i , 0xf1ff, 0xb0bc, { 14, 14, 6, 6, 6}}, + {m68k_op_cmpa_16_aw , 0xf1ff, 0xb0f8, { 14, 14, 8, 8, 8}}, + {m68k_op_cmpa_16_al , 0xf1ff, 0xb0f9, { 18, 18, 8, 8, 8}}, + {m68k_op_cmpa_16_pcdi , 0xf1ff, 0xb0fa, { 14, 14, 9, 9, 9}}, + {m68k_op_cmpa_16_pcix , 0xf1ff, 0xb0fb, { 16, 16, 11, 11, 11}}, + {m68k_op_cmpa_16_i , 0xf1ff, 0xb0fc, { 10, 10, 6, 6, 6}}, + {m68k_op_cmpm_8_ay7 , 0xf1ff, 0xb10f, { 12, 12, 9, 9, 9}}, + {m68k_op_eor_8_pi7 , 0xf1ff, 0xb11f, { 12, 12, 8, 8, 8}}, + {m68k_op_eor_8_pd7 , 0xf1ff, 0xb127, { 14, 14, 9, 9, 9}}, + {m68k_op_eor_8_aw , 0xf1ff, 0xb138, { 16, 16, 8, 8, 8}}, + {m68k_op_eor_8_al , 0xf1ff, 0xb139, { 20, 20, 8, 8, 8}}, + {m68k_op_eor_16_aw , 0xf1ff, 0xb178, { 16, 16, 8, 8, 8}}, + {m68k_op_eor_16_al , 0xf1ff, 0xb179, { 20, 20, 8, 8, 8}}, + {m68k_op_eor_32_aw , 0xf1ff, 0xb1b8, { 24, 24, 8, 8, 8}}, + {m68k_op_eor_32_al , 0xf1ff, 0xb1b9, { 28, 28, 8, 8, 8}}, + {m68k_op_cmpa_32_aw , 0xf1ff, 0xb1f8, { 18, 18, 8, 8, 8}}, + {m68k_op_cmpa_32_al , 0xf1ff, 0xb1f9, { 22, 22, 8, 8, 8}}, + {m68k_op_cmpa_32_pcdi , 0xf1ff, 0xb1fa, { 18, 18, 9, 9, 9}}, + {m68k_op_cmpa_32_pcix , 0xf1ff, 0xb1fb, { 20, 20, 11, 11, 11}}, + {m68k_op_cmpa_32_i , 0xf1ff, 0xb1fc, { 14, 14, 8, 8, 8}}, + {m68k_op_and_8_er_pi7 , 0xf1ff, 0xc01f, { 8, 8, 6, 6, 6}}, + {m68k_op_and_8_er_pd7 , 0xf1ff, 0xc027, { 10, 10, 7, 7, 7}}, + {m68k_op_and_8_er_aw , 0xf1ff, 0xc038, { 12, 12, 6, 6, 6}}, + {m68k_op_and_8_er_al , 0xf1ff, 0xc039, { 16, 16, 6, 6, 6}}, + {m68k_op_and_8_er_pcdi , 0xf1ff, 0xc03a, { 12, 12, 7, 7, 7}}, + {m68k_op_and_8_er_pcix , 0xf1ff, 0xc03b, { 14, 14, 9, 9, 9}}, + {m68k_op_and_8_er_i , 0xf1ff, 0xc03c, { 8, 8, 4, 4, 4}}, + {m68k_op_and_16_er_aw , 0xf1ff, 0xc078, { 12, 12, 6, 6, 6}}, + {m68k_op_and_16_er_al , 0xf1ff, 0xc079, { 16, 16, 6, 6, 6}}, + {m68k_op_and_16_er_pcdi , 0xf1ff, 0xc07a, { 12, 12, 7, 7, 7}}, + {m68k_op_and_16_er_pcix , 0xf1ff, 0xc07b, { 14, 14, 9, 9, 9}}, + {m68k_op_and_16_er_i , 0xf1ff, 0xc07c, { 8, 8, 4, 4, 4}}, + {m68k_op_and_32_er_aw , 0xf1ff, 0xc0b8, { 18, 18, 6, 6, 6}}, + {m68k_op_and_32_er_al , 0xf1ff, 0xc0b9, { 22, 22, 6, 6, 6}}, + {m68k_op_and_32_er_pcdi , 0xf1ff, 0xc0ba, { 18, 18, 7, 7, 7}}, + {m68k_op_and_32_er_pcix , 0xf1ff, 0xc0bb, { 20, 20, 9, 9, 9}}, + {m68k_op_and_32_er_i , 0xf1ff, 0xc0bc, { 16, 14, 6, 6, 6}}, + {m68k_op_mulu_16_aw , 0xf1ff, 0xc0f8, { 62, 38, 31, 31, 31}}, + {m68k_op_mulu_16_al , 0xf1ff, 0xc0f9, { 66, 42, 31, 31, 31}}, + {m68k_op_mulu_16_pcdi , 0xf1ff, 0xc0fa, { 62, 38, 32, 32, 32}}, + {m68k_op_mulu_16_pcix , 0xf1ff, 0xc0fb, { 64, 40, 34, 34, 34}}, + {m68k_op_mulu_16_i , 0xf1ff, 0xc0fc, { 58, 34, 29, 29, 29}}, + {m68k_op_abcd_8_mm_ay7 , 0xf1ff, 0xc10f, { 18, 18, 16, 16, 16}}, + {m68k_op_and_8_re_pi7 , 0xf1ff, 0xc11f, { 12, 12, 8, 8, 8}}, + {m68k_op_and_8_re_pd7 , 0xf1ff, 0xc127, { 14, 14, 9, 9, 9}}, + {m68k_op_and_8_re_aw , 0xf1ff, 0xc138, { 16, 16, 8, 8, 8}}, + {m68k_op_and_8_re_al , 0xf1ff, 0xc139, { 20, 20, 8, 8, 8}}, + {m68k_op_and_16_re_aw , 0xf1ff, 0xc178, { 16, 16, 8, 8, 8}}, + {m68k_op_and_16_re_al , 0xf1ff, 0xc179, { 20, 20, 8, 8, 8}}, + {m68k_op_and_32_re_aw , 0xf1ff, 0xc1b8, { 24, 24, 8, 8, 8}}, + {m68k_op_and_32_re_al , 0xf1ff, 0xc1b9, { 28, 28, 8, 8, 8}}, + {m68k_op_muls_16_aw , 0xf1ff, 0xc1f8, { 62, 40, 31, 31, 31}}, + {m68k_op_muls_16_al , 0xf1ff, 0xc1f9, { 66, 44, 31, 31, 31}}, + {m68k_op_muls_16_pcdi , 0xf1ff, 0xc1fa, { 62, 40, 32, 32, 32}}, + {m68k_op_muls_16_pcix , 0xf1ff, 0xc1fb, { 64, 42, 34, 34, 34}}, + {m68k_op_muls_16_i , 0xf1ff, 0xc1fc, { 58, 36, 29, 29, 29}}, + {m68k_op_add_8_er_pi7 , 0xf1ff, 0xd01f, { 8, 8, 6, 6, 6}}, + {m68k_op_add_8_er_pd7 , 0xf1ff, 0xd027, { 10, 10, 7, 7, 7}}, + {m68k_op_add_8_er_aw , 0xf1ff, 0xd038, { 12, 12, 6, 6, 6}}, + {m68k_op_add_8_er_al , 0xf1ff, 0xd039, { 16, 16, 6, 6, 6}}, + {m68k_op_add_8_er_pcdi , 0xf1ff, 0xd03a, { 12, 12, 7, 7, 7}}, + {m68k_op_add_8_er_pcix , 0xf1ff, 0xd03b, { 14, 14, 9, 9, 9}}, + {m68k_op_add_8_er_i , 0xf1ff, 0xd03c, { 8, 8, 4, 4, 4}}, + {m68k_op_add_16_er_aw , 0xf1ff, 0xd078, { 12, 12, 6, 6, 6}}, + {m68k_op_add_16_er_al , 0xf1ff, 0xd079, { 16, 16, 6, 6, 6}}, + {m68k_op_add_16_er_pcdi , 0xf1ff, 0xd07a, { 12, 12, 7, 7, 7}}, + {m68k_op_add_16_er_pcix , 0xf1ff, 0xd07b, { 14, 14, 9, 9, 9}}, + {m68k_op_add_16_er_i , 0xf1ff, 0xd07c, { 8, 8, 4, 4, 4}}, + {m68k_op_add_32_er_aw , 0xf1ff, 0xd0b8, { 18, 18, 6, 6, 6}}, + {m68k_op_add_32_er_al , 0xf1ff, 0xd0b9, { 22, 22, 6, 6, 6}}, + {m68k_op_add_32_er_pcdi , 0xf1ff, 0xd0ba, { 18, 18, 7, 7, 7}}, + {m68k_op_add_32_er_pcix , 0xf1ff, 0xd0bb, { 20, 20, 9, 9, 9}}, + {m68k_op_add_32_er_i , 0xf1ff, 0xd0bc, { 16, 14, 6, 6, 6}}, + {m68k_op_adda_16_aw , 0xf1ff, 0xd0f8, { 16, 16, 6, 6, 6}}, + {m68k_op_adda_16_al , 0xf1ff, 0xd0f9, { 20, 20, 6, 6, 6}}, + {m68k_op_adda_16_pcdi , 0xf1ff, 0xd0fa, { 16, 16, 7, 7, 7}}, + {m68k_op_adda_16_pcix , 0xf1ff, 0xd0fb, { 18, 18, 9, 9, 9}}, + {m68k_op_adda_16_i , 0xf1ff, 0xd0fc, { 12, 12, 4, 4, 4}}, + {m68k_op_addx_8_mm_ay7 , 0xf1ff, 0xd10f, { 18, 18, 12, 12, 12}}, + {m68k_op_add_8_re_pi7 , 0xf1ff, 0xd11f, { 12, 12, 8, 8, 8}}, + {m68k_op_add_8_re_pd7 , 0xf1ff, 0xd127, { 14, 14, 9, 9, 9}}, + {m68k_op_add_8_re_aw , 0xf1ff, 0xd138, { 16, 16, 8, 8, 8}}, + {m68k_op_add_8_re_al , 0xf1ff, 0xd139, { 20, 20, 8, 8, 8}}, + {m68k_op_add_16_re_aw , 0xf1ff, 0xd178, { 16, 16, 8, 8, 8}}, + {m68k_op_add_16_re_al , 0xf1ff, 0xd179, { 20, 20, 8, 8, 8}}, + {m68k_op_add_32_re_aw , 0xf1ff, 0xd1b8, { 24, 24, 8, 8, 8}}, + {m68k_op_add_32_re_al , 0xf1ff, 0xd1b9, { 28, 28, 8, 8, 8}}, + {m68k_op_adda_32_aw , 0xf1ff, 0xd1f8, { 18, 18, 6, 6, 6}}, + {m68k_op_adda_32_al , 0xf1ff, 0xd1f9, { 22, 22, 6, 6, 6}}, + {m68k_op_adda_32_pcdi , 0xf1ff, 0xd1fa, { 18, 18, 7, 7, 7}}, + {m68k_op_adda_32_pcix , 0xf1ff, 0xd1fb, { 20, 20, 9, 9, 9}}, + {m68k_op_adda_32_i , 0xf1ff, 0xd1fc, { 16, 14, 6, 6, 6}}, + {m68k_op_ori_8_d , 0xfff8, 0x0000, { 8, 8, 2, 2, 2}}, + {m68k_op_ori_8_ai , 0xfff8, 0x0010, { 16, 16, 8, 8, 8}}, + {m68k_op_ori_8_pi , 0xfff8, 0x0018, { 16, 16, 8, 8, 8}}, + {m68k_op_ori_8_pd , 0xfff8, 0x0020, { 18, 18, 9, 9, 9}}, + {m68k_op_ori_8_di , 0xfff8, 0x0028, { 20, 20, 9, 9, 9}}, + {m68k_op_ori_8_ix , 0xfff8, 0x0030, { 22, 22, 11, 11, 11}}, + {m68k_op_ori_16_d , 0xfff8, 0x0040, { 8, 8, 2, 2, 2}}, + {m68k_op_ori_16_ai , 0xfff8, 0x0050, { 16, 16, 8, 8, 8}}, + {m68k_op_ori_16_pi , 0xfff8, 0x0058, { 16, 16, 8, 8, 8}}, + {m68k_op_ori_16_pd , 0xfff8, 0x0060, { 18, 18, 9, 9, 9}}, + {m68k_op_ori_16_di , 0xfff8, 0x0068, { 20, 20, 9, 9, 9}}, + {m68k_op_ori_16_ix , 0xfff8, 0x0070, { 22, 22, 11, 11, 11}}, + {m68k_op_ori_32_d , 0xfff8, 0x0080, { 16, 14, 2, 2, 2}}, + {m68k_op_ori_32_ai , 0xfff8, 0x0090, { 28, 28, 8, 8, 8}}, + {m68k_op_ori_32_pi , 0xfff8, 0x0098, { 28, 28, 8, 8, 8}}, + {m68k_op_ori_32_pd , 0xfff8, 0x00a0, { 30, 30, 9, 9, 9}}, + {m68k_op_ori_32_di , 0xfff8, 0x00a8, { 32, 32, 9, 9, 9}}, + {m68k_op_ori_32_ix , 0xfff8, 0x00b0, { 34, 34, 11, 11, 11}}, + {m68k_op_chk2cmp2_8_ai , 0xfff8, 0x00d0, { 0, 0, 22, 22, 22}}, + {m68k_op_chk2cmp2_8_di , 0xfff8, 0x00e8, { 0, 0, 23, 23, 23}}, + {m68k_op_chk2cmp2_8_ix , 0xfff8, 0x00f0, { 0, 0, 25, 25, 25}}, + {m68k_op_andi_8_d , 0xfff8, 0x0200, { 8, 8, 2, 2, 2}}, + {m68k_op_andi_8_ai , 0xfff8, 0x0210, { 16, 16, 8, 8, 8}}, + {m68k_op_andi_8_pi , 0xfff8, 0x0218, { 16, 16, 8, 8, 8}}, + {m68k_op_andi_8_pd , 0xfff8, 0x0220, { 18, 18, 9, 9, 9}}, + {m68k_op_andi_8_di , 0xfff8, 0x0228, { 20, 20, 9, 9, 9}}, + {m68k_op_andi_8_ix , 0xfff8, 0x0230, { 22, 22, 11, 11, 11}}, + {m68k_op_andi_16_d , 0xfff8, 0x0240, { 8, 8, 2, 2, 2}}, + {m68k_op_andi_16_ai , 0xfff8, 0x0250, { 16, 16, 8, 8, 8}}, + {m68k_op_andi_16_pi , 0xfff8, 0x0258, { 16, 16, 8, 8, 8}}, + {m68k_op_andi_16_pd , 0xfff8, 0x0260, { 18, 18, 9, 9, 9}}, + {m68k_op_andi_16_di , 0xfff8, 0x0268, { 20, 20, 9, 9, 9}}, + {m68k_op_andi_16_ix , 0xfff8, 0x0270, { 22, 22, 11, 11, 11}}, + {m68k_op_andi_32_d , 0xfff8, 0x0280, { 14, 14, 2, 2, 2}}, + {m68k_op_andi_32_ai , 0xfff8, 0x0290, { 28, 28, 8, 8, 8}}, + {m68k_op_andi_32_pi , 0xfff8, 0x0298, { 28, 28, 8, 8, 8}}, + {m68k_op_andi_32_pd , 0xfff8, 0x02a0, { 30, 30, 9, 9, 9}}, + {m68k_op_andi_32_di , 0xfff8, 0x02a8, { 32, 32, 9, 9, 9}}, + {m68k_op_andi_32_ix , 0xfff8, 0x02b0, { 34, 34, 11, 11, 11}}, + {m68k_op_chk2cmp2_16_ai , 0xfff8, 0x02d0, { 0, 0, 22, 22, 22}}, + {m68k_op_chk2cmp2_16_di , 0xfff8, 0x02e8, { 0, 0, 23, 23, 23}}, + {m68k_op_chk2cmp2_16_ix , 0xfff8, 0x02f0, { 0, 0, 25, 25, 25}}, + {m68k_op_subi_8_d , 0xfff8, 0x0400, { 8, 8, 2, 2, 2}}, + {m68k_op_subi_8_ai , 0xfff8, 0x0410, { 16, 16, 8, 8, 8}}, + {m68k_op_subi_8_pi , 0xfff8, 0x0418, { 16, 16, 8, 8, 8}}, + {m68k_op_subi_8_pd , 0xfff8, 0x0420, { 18, 18, 9, 9, 9}}, + {m68k_op_subi_8_di , 0xfff8, 0x0428, { 20, 20, 9, 9, 9}}, + {m68k_op_subi_8_ix , 0xfff8, 0x0430, { 22, 22, 11, 11, 11}}, + {m68k_op_subi_16_d , 0xfff8, 0x0440, { 8, 8, 2, 2, 2}}, + {m68k_op_subi_16_ai , 0xfff8, 0x0450, { 16, 16, 8, 8, 8}}, + {m68k_op_subi_16_pi , 0xfff8, 0x0458, { 16, 16, 8, 8, 8}}, + {m68k_op_subi_16_pd , 0xfff8, 0x0460, { 18, 18, 9, 9, 9}}, + {m68k_op_subi_16_di , 0xfff8, 0x0468, { 20, 20, 9, 9, 9}}, + {m68k_op_subi_16_ix , 0xfff8, 0x0470, { 22, 22, 11, 11, 11}}, + {m68k_op_subi_32_d , 0xfff8, 0x0480, { 16, 14, 2, 2, 2}}, + {m68k_op_subi_32_ai , 0xfff8, 0x0490, { 28, 28, 8, 8, 8}}, + {m68k_op_subi_32_pi , 0xfff8, 0x0498, { 28, 28, 8, 8, 8}}, + {m68k_op_subi_32_pd , 0xfff8, 0x04a0, { 30, 30, 9, 9, 9}}, + {m68k_op_subi_32_di , 0xfff8, 0x04a8, { 32, 32, 9, 9, 9}}, + {m68k_op_subi_32_ix , 0xfff8, 0x04b0, { 34, 34, 11, 11, 11}}, + {m68k_op_chk2cmp2_32_ai , 0xfff8, 0x04d0, { 0, 0, 22, 22, 22}}, + {m68k_op_chk2cmp2_32_di , 0xfff8, 0x04e8, { 0, 0, 23, 23, 23}}, + {m68k_op_chk2cmp2_32_ix , 0xfff8, 0x04f0, { 0, 0, 25, 25, 25}}, + {m68k_op_addi_8_d , 0xfff8, 0x0600, { 8, 8, 2, 2, 2}}, + {m68k_op_addi_8_ai , 0xfff8, 0x0610, { 16, 16, 8, 8, 8}}, + {m68k_op_addi_8_pi , 0xfff8, 0x0618, { 16, 16, 8, 8, 8}}, + {m68k_op_addi_8_pd , 0xfff8, 0x0620, { 18, 18, 9, 9, 9}}, + {m68k_op_addi_8_di , 0xfff8, 0x0628, { 20, 20, 9, 9, 9}}, + {m68k_op_addi_8_ix , 0xfff8, 0x0630, { 22, 22, 11, 11, 11}}, + {m68k_op_addi_16_d , 0xfff8, 0x0640, { 8, 8, 2, 2, 2}}, + {m68k_op_addi_16_ai , 0xfff8, 0x0650, { 16, 16, 8, 8, 8}}, + {m68k_op_addi_16_pi , 0xfff8, 0x0658, { 16, 16, 8, 8, 8}}, + {m68k_op_addi_16_pd , 0xfff8, 0x0660, { 18, 18, 9, 9, 9}}, + {m68k_op_addi_16_di , 0xfff8, 0x0668, { 20, 20, 9, 9, 9}}, + {m68k_op_addi_16_ix , 0xfff8, 0x0670, { 22, 22, 11, 11, 11}}, + {m68k_op_addi_32_d , 0xfff8, 0x0680, { 16, 14, 2, 2, 2}}, + {m68k_op_addi_32_ai , 0xfff8, 0x0690, { 28, 28, 8, 8, 8}}, + {m68k_op_addi_32_pi , 0xfff8, 0x0698, { 28, 28, 8, 8, 8}}, + {m68k_op_addi_32_pd , 0xfff8, 0x06a0, { 30, 30, 9, 9, 9}}, + {m68k_op_addi_32_di , 0xfff8, 0x06a8, { 32, 32, 9, 9, 9}}, + {m68k_op_addi_32_ix , 0xfff8, 0x06b0, { 34, 34, 11, 11, 11}}, + {m68k_op_callm_32_ai , 0xfff8, 0x06d0, { 0, 0, 64, 64, 64}}, + {m68k_op_callm_32_di , 0xfff8, 0x06e8, { 0, 0, 65, 65, 65}}, + {m68k_op_callm_32_ix , 0xfff8, 0x06f0, { 0, 0, 67, 67, 67}}, + {m68k_op_btst_32_s_d , 0xfff8, 0x0800, { 10, 10, 4, 4, 4}}, + {m68k_op_btst_8_s_ai , 0xfff8, 0x0810, { 12, 12, 8, 8, 8}}, + {m68k_op_btst_8_s_pi , 0xfff8, 0x0818, { 12, 12, 8, 8, 8}}, + {m68k_op_btst_8_s_pd , 0xfff8, 0x0820, { 14, 14, 9, 9, 9}}, + {m68k_op_btst_8_s_di , 0xfff8, 0x0828, { 16, 16, 9, 9, 9}}, + {m68k_op_btst_8_s_ix , 0xfff8, 0x0830, { 18, 18, 11, 11, 11}}, + {m68k_op_bchg_32_s_d , 0xfff8, 0x0840, { 12, 12, 4, 4, 4}}, + {m68k_op_bchg_8_s_ai , 0xfff8, 0x0850, { 16, 16, 8, 8, 8}}, + {m68k_op_bchg_8_s_pi , 0xfff8, 0x0858, { 16, 16, 8, 8, 8}}, + {m68k_op_bchg_8_s_pd , 0xfff8, 0x0860, { 18, 18, 9, 9, 9}}, + {m68k_op_bchg_8_s_di , 0xfff8, 0x0868, { 20, 20, 9, 9, 9}}, + {m68k_op_bchg_8_s_ix , 0xfff8, 0x0870, { 22, 22, 11, 11, 11}}, + {m68k_op_bclr_32_s_d , 0xfff8, 0x0880, { 14, 14, 4, 4, 4}}, + {m68k_op_bclr_8_s_ai , 0xfff8, 0x0890, { 16, 16, 8, 8, 8}}, + {m68k_op_bclr_8_s_pi , 0xfff8, 0x0898, { 16, 16, 8, 8, 8}}, + {m68k_op_bclr_8_s_pd , 0xfff8, 0x08a0, { 18, 18, 9, 9, 9}}, + {m68k_op_bclr_8_s_di , 0xfff8, 0x08a8, { 20, 20, 9, 9, 9}}, + {m68k_op_bclr_8_s_ix , 0xfff8, 0x08b0, { 22, 22, 11, 11, 11}}, + {m68k_op_bset_32_s_d , 0xfff8, 0x08c0, { 12, 12, 4, 4, 4}}, + {m68k_op_bset_8_s_ai , 0xfff8, 0x08d0, { 16, 16, 8, 8, 8}}, + {m68k_op_bset_8_s_pi , 0xfff8, 0x08d8, { 16, 16, 8, 8, 8}}, + {m68k_op_bset_8_s_pd , 0xfff8, 0x08e0, { 18, 18, 9, 9, 9}}, + {m68k_op_bset_8_s_di , 0xfff8, 0x08e8, { 20, 20, 9, 9, 9}}, + {m68k_op_bset_8_s_ix , 0xfff8, 0x08f0, { 22, 22, 11, 11, 11}}, + {m68k_op_eori_8_d , 0xfff8, 0x0a00, { 8, 8, 2, 2, 2}}, + {m68k_op_eori_8_ai , 0xfff8, 0x0a10, { 16, 16, 8, 8, 8}}, + {m68k_op_eori_8_pi , 0xfff8, 0x0a18, { 16, 16, 8, 8, 8}}, + {m68k_op_eori_8_pd , 0xfff8, 0x0a20, { 18, 18, 9, 9, 9}}, + {m68k_op_eori_8_di , 0xfff8, 0x0a28, { 20, 20, 9, 9, 9}}, + {m68k_op_eori_8_ix , 0xfff8, 0x0a30, { 22, 22, 11, 11, 11}}, + {m68k_op_eori_16_d , 0xfff8, 0x0a40, { 8, 8, 2, 2, 2}}, + {m68k_op_eori_16_ai , 0xfff8, 0x0a50, { 16, 16, 8, 8, 8}}, + {m68k_op_eori_16_pi , 0xfff8, 0x0a58, { 16, 16, 8, 8, 8}}, + {m68k_op_eori_16_pd , 0xfff8, 0x0a60, { 18, 18, 9, 9, 9}}, + {m68k_op_eori_16_di , 0xfff8, 0x0a68, { 20, 20, 9, 9, 9}}, + {m68k_op_eori_16_ix , 0xfff8, 0x0a70, { 22, 22, 11, 11, 11}}, + {m68k_op_eori_32_d , 0xfff8, 0x0a80, { 16, 14, 2, 2, 2}}, + {m68k_op_eori_32_ai , 0xfff8, 0x0a90, { 28, 28, 8, 8, 8}}, + {m68k_op_eori_32_pi , 0xfff8, 0x0a98, { 28, 28, 8, 8, 8}}, + {m68k_op_eori_32_pd , 0xfff8, 0x0aa0, { 30, 30, 9, 9, 9}}, + {m68k_op_eori_32_di , 0xfff8, 0x0aa8, { 32, 32, 9, 9, 9}}, + {m68k_op_eori_32_ix , 0xfff8, 0x0ab0, { 34, 34, 11, 11, 11}}, + {m68k_op_cas_8_ai , 0xfff8, 0x0ad0, { 0, 0, 16, 16, 16}}, + {m68k_op_cas_8_pi , 0xfff8, 0x0ad8, { 0, 0, 16, 16, 16}}, + {m68k_op_cas_8_pd , 0xfff8, 0x0ae0, { 0, 0, 17, 17, 17}}, + {m68k_op_cas_8_di , 0xfff8, 0x0ae8, { 0, 0, 17, 17, 17}}, + {m68k_op_cas_8_ix , 0xfff8, 0x0af0, { 0, 0, 19, 19, 19}}, + {m68k_op_cmpi_8_d , 0xfff8, 0x0c00, { 8, 8, 2, 2, 2}}, + {m68k_op_cmpi_8_ai , 0xfff8, 0x0c10, { 12, 12, 6, 6, 6}}, + {m68k_op_cmpi_8_pi , 0xfff8, 0x0c18, { 12, 12, 6, 6, 6}}, + {m68k_op_cmpi_8_pd , 0xfff8, 0x0c20, { 14, 14, 7, 7, 7}}, + {m68k_op_cmpi_8_di , 0xfff8, 0x0c28, { 16, 16, 7, 7, 7}}, + {m68k_op_cmpi_8_ix , 0xfff8, 0x0c30, { 18, 18, 9, 9, 9}}, + {m68k_op_cmpi_16_d , 0xfff8, 0x0c40, { 8, 8, 2, 2, 2}}, + {m68k_op_cmpi_16_ai , 0xfff8, 0x0c50, { 12, 12, 6, 6, 6}}, + {m68k_op_cmpi_16_pi , 0xfff8, 0x0c58, { 12, 12, 6, 6, 6}}, + {m68k_op_cmpi_16_pd , 0xfff8, 0x0c60, { 14, 14, 7, 7, 7}}, + {m68k_op_cmpi_16_di , 0xfff8, 0x0c68, { 16, 16, 7, 7, 7}}, + {m68k_op_cmpi_16_ix , 0xfff8, 0x0c70, { 18, 18, 9, 9, 9}}, + {m68k_op_cmpi_32_d , 0xfff8, 0x0c80, { 14, 12, 2, 2, 2}}, + {m68k_op_cmpi_32_ai , 0xfff8, 0x0c90, { 20, 20, 6, 6, 6}}, + {m68k_op_cmpi_32_pi , 0xfff8, 0x0c98, { 20, 20, 6, 6, 6}}, + {m68k_op_cmpi_32_pd , 0xfff8, 0x0ca0, { 22, 22, 7, 7, 7}}, + {m68k_op_cmpi_32_di , 0xfff8, 0x0ca8, { 24, 24, 7, 7, 7}}, + {m68k_op_cmpi_32_ix , 0xfff8, 0x0cb0, { 26, 26, 9, 9, 9}}, + {m68k_op_cas_16_ai , 0xfff8, 0x0cd0, { 0, 0, 16, 16, 16}}, + {m68k_op_cas_16_pi , 0xfff8, 0x0cd8, { 0, 0, 16, 16, 16}}, + {m68k_op_cas_16_pd , 0xfff8, 0x0ce0, { 0, 0, 17, 17, 17}}, + {m68k_op_cas_16_di , 0xfff8, 0x0ce8, { 0, 0, 17, 17, 17}}, + {m68k_op_cas_16_ix , 0xfff8, 0x0cf0, { 0, 0, 19, 19, 19}}, + {m68k_op_moves_8_ai , 0xfff8, 0x0e10, { 0, 18, 9, 9, 9}}, + {m68k_op_moves_8_pi , 0xfff8, 0x0e18, { 0, 18, 9, 9, 9}}, + {m68k_op_moves_8_pd , 0xfff8, 0x0e20, { 0, 20, 10, 10, 10}}, + {m68k_op_moves_8_di , 0xfff8, 0x0e28, { 0, 26, 10, 10, 10}}, + {m68k_op_moves_8_ix , 0xfff8, 0x0e30, { 0, 30, 12, 12, 12}}, + {m68k_op_moves_16_ai , 0xfff8, 0x0e50, { 0, 18, 9, 9, 9}}, + {m68k_op_moves_16_pi , 0xfff8, 0x0e58, { 0, 18, 9, 9, 9}}, + {m68k_op_moves_16_pd , 0xfff8, 0x0e60, { 0, 20, 10, 10, 10}}, + {m68k_op_moves_16_di , 0xfff8, 0x0e68, { 0, 26, 10, 10, 10}}, + {m68k_op_moves_16_ix , 0xfff8, 0x0e70, { 0, 30, 12, 12, 12}}, + {m68k_op_moves_32_ai , 0xfff8, 0x0e90, { 0, 22, 9, 9, 9}}, + {m68k_op_moves_32_pi , 0xfff8, 0x0e98, { 0, 22, 9, 9, 9}}, + {m68k_op_moves_32_pd , 0xfff8, 0x0ea0, { 0, 28, 10, 10, 10}}, + {m68k_op_moves_32_di , 0xfff8, 0x0ea8, { 0, 32, 10, 10, 10}}, + {m68k_op_moves_32_ix , 0xfff8, 0x0eb0, { 0, 36, 12, 12, 12}}, + {m68k_op_cas_32_ai , 0xfff8, 0x0ed0, { 0, 0, 16, 16, 16}}, + {m68k_op_cas_32_pi , 0xfff8, 0x0ed8, { 0, 0, 16, 16, 16}}, + {m68k_op_cas_32_pd , 0xfff8, 0x0ee0, { 0, 0, 17, 17, 17}}, + {m68k_op_cas_32_di , 0xfff8, 0x0ee8, { 0, 0, 17, 17, 17}}, + {m68k_op_cas_32_ix , 0xfff8, 0x0ef0, { 0, 0, 19, 19, 19}}, + {m68k_op_move_8_aw_d , 0xfff8, 0x11c0, { 12, 12, 4, 4, 4}}, + {m68k_op_move_8_aw_ai , 0xfff8, 0x11d0, { 16, 16, 8, 8, 8}}, + {m68k_op_move_8_aw_pi , 0xfff8, 0x11d8, { 16, 16, 8, 8, 8}}, + {m68k_op_move_8_aw_pd , 0xfff8, 0x11e0, { 18, 18, 9, 9, 9}}, + {m68k_op_move_8_aw_di , 0xfff8, 0x11e8, { 20, 20, 9, 9, 9}}, + {m68k_op_move_8_aw_ix , 0xfff8, 0x11f0, { 22, 22, 11, 11, 11}}, + {m68k_op_move_8_al_d , 0xfff8, 0x13c0, { 16, 16, 6, 6, 6}}, + {m68k_op_move_8_al_ai , 0xfff8, 0x13d0, { 20, 20, 10, 10, 10}}, + {m68k_op_move_8_al_pi , 0xfff8, 0x13d8, { 20, 20, 10, 10, 10}}, + {m68k_op_move_8_al_pd , 0xfff8, 0x13e0, { 22, 22, 11, 11, 11}}, + {m68k_op_move_8_al_di , 0xfff8, 0x13e8, { 24, 24, 11, 11, 11}}, + {m68k_op_move_8_al_ix , 0xfff8, 0x13f0, { 26, 26, 13, 13, 13}}, + {m68k_op_move_8_pi7_d , 0xfff8, 0x1ec0, { 8, 8, 4, 4, 4}}, + {m68k_op_move_8_pi7_ai , 0xfff8, 0x1ed0, { 12, 12, 8, 8, 8}}, + {m68k_op_move_8_pi7_pi , 0xfff8, 0x1ed8, { 12, 12, 8, 8, 8}}, + {m68k_op_move_8_pi7_pd , 0xfff8, 0x1ee0, { 14, 14, 9, 9, 9}}, + {m68k_op_move_8_pi7_di , 0xfff8, 0x1ee8, { 16, 16, 9, 9, 9}}, + {m68k_op_move_8_pi7_ix , 0xfff8, 0x1ef0, { 18, 18, 11, 11, 11}}, + {m68k_op_move_8_pd7_d , 0xfff8, 0x1f00, { 8, 8, 5, 5, 5}}, + {m68k_op_move_8_pd7_ai , 0xfff8, 0x1f10, { 12, 12, 9, 9, 9}}, + {m68k_op_move_8_pd7_pi , 0xfff8, 0x1f18, { 12, 12, 9, 9, 9}}, + {m68k_op_move_8_pd7_pd , 0xfff8, 0x1f20, { 14, 14, 10, 10, 10}}, + {m68k_op_move_8_pd7_di , 0xfff8, 0x1f28, { 16, 16, 10, 10, 10}}, + {m68k_op_move_8_pd7_ix , 0xfff8, 0x1f30, { 18, 18, 12, 12, 12}}, + {m68k_op_move_32_aw_d , 0xfff8, 0x21c0, { 16, 16, 4, 4, 4}}, + {m68k_op_move_32_aw_a , 0xfff8, 0x21c8, { 16, 16, 4, 4, 4}}, + {m68k_op_move_32_aw_ai , 0xfff8, 0x21d0, { 24, 24, 8, 8, 8}}, + {m68k_op_move_32_aw_pi , 0xfff8, 0x21d8, { 24, 24, 8, 8, 8}}, + {m68k_op_move_32_aw_pd , 0xfff8, 0x21e0, { 26, 26, 9, 9, 9}}, + {m68k_op_move_32_aw_di , 0xfff8, 0x21e8, { 28, 28, 9, 9, 9}}, + {m68k_op_move_32_aw_ix , 0xfff8, 0x21f0, { 30, 30, 11, 11, 11}}, + {m68k_op_move_32_al_d , 0xfff8, 0x23c0, { 20, 20, 6, 6, 6}}, + {m68k_op_move_32_al_a , 0xfff8, 0x23c8, { 20, 20, 6, 6, 6}}, + {m68k_op_move_32_al_ai , 0xfff8, 0x23d0, { 28, 28, 10, 10, 10}}, + {m68k_op_move_32_al_pi , 0xfff8, 0x23d8, { 28, 28, 10, 10, 10}}, + {m68k_op_move_32_al_pd , 0xfff8, 0x23e0, { 30, 30, 11, 11, 11}}, + {m68k_op_move_32_al_di , 0xfff8, 0x23e8, { 32, 32, 11, 11, 11}}, + {m68k_op_move_32_al_ix , 0xfff8, 0x23f0, { 34, 34, 13, 13, 13}}, + {m68k_op_move_16_aw_d , 0xfff8, 0x31c0, { 12, 12, 4, 4, 4}}, + {m68k_op_move_16_aw_a , 0xfff8, 0x31c8, { 12, 12, 4, 4, 4}}, + {m68k_op_move_16_aw_ai , 0xfff8, 0x31d0, { 16, 16, 8, 8, 8}}, + {m68k_op_move_16_aw_pi , 0xfff8, 0x31d8, { 16, 16, 8, 8, 8}}, + {m68k_op_move_16_aw_pd , 0xfff8, 0x31e0, { 18, 18, 9, 9, 9}}, + {m68k_op_move_16_aw_di , 0xfff8, 0x31e8, { 20, 20, 9, 9, 9}}, + {m68k_op_move_16_aw_ix , 0xfff8, 0x31f0, { 22, 22, 11, 11, 11}}, + {m68k_op_move_16_al_d , 0xfff8, 0x33c0, { 16, 16, 6, 6, 6}}, + {m68k_op_move_16_al_a , 0xfff8, 0x33c8, { 16, 16, 6, 6, 6}}, + {m68k_op_move_16_al_ai , 0xfff8, 0x33d0, { 20, 20, 10, 10, 10}}, + {m68k_op_move_16_al_pi , 0xfff8, 0x33d8, { 20, 20, 10, 10, 10}}, + {m68k_op_move_16_al_pd , 0xfff8, 0x33e0, { 22, 22, 11, 11, 11}}, + {m68k_op_move_16_al_di , 0xfff8, 0x33e8, { 24, 24, 11, 11, 11}}, + {m68k_op_move_16_al_ix , 0xfff8, 0x33f0, { 26, 26, 13, 13, 13}}, + {m68k_op_negx_8_d , 0xfff8, 0x4000, { 4, 4, 2, 2, 2}}, + {m68k_op_negx_8_ai , 0xfff8, 0x4010, { 12, 12, 8, 8, 8}}, + {m68k_op_negx_8_pi , 0xfff8, 0x4018, { 12, 12, 8, 8, 8}}, + {m68k_op_negx_8_pd , 0xfff8, 0x4020, { 14, 14, 9, 9, 9}}, + {m68k_op_negx_8_di , 0xfff8, 0x4028, { 16, 16, 9, 9, 9}}, + {m68k_op_negx_8_ix , 0xfff8, 0x4030, { 18, 18, 11, 11, 11}}, + {m68k_op_negx_16_d , 0xfff8, 0x4040, { 4, 4, 2, 2, 2}}, + {m68k_op_negx_16_ai , 0xfff8, 0x4050, { 12, 12, 8, 8, 8}}, + {m68k_op_negx_16_pi , 0xfff8, 0x4058, { 12, 12, 8, 8, 8}}, + {m68k_op_negx_16_pd , 0xfff8, 0x4060, { 14, 14, 9, 9, 9}}, + {m68k_op_negx_16_di , 0xfff8, 0x4068, { 16, 16, 9, 9, 9}}, + {m68k_op_negx_16_ix , 0xfff8, 0x4070, { 18, 18, 11, 11, 11}}, + {m68k_op_negx_32_d , 0xfff8, 0x4080, { 6, 6, 2, 2, 2}}, + {m68k_op_negx_32_ai , 0xfff8, 0x4090, { 20, 20, 8, 8, 8}}, + {m68k_op_negx_32_pi , 0xfff8, 0x4098, { 20, 20, 8, 8, 8}}, + {m68k_op_negx_32_pd , 0xfff8, 0x40a0, { 22, 22, 9, 9, 9}}, + {m68k_op_negx_32_di , 0xfff8, 0x40a8, { 24, 24, 9, 9, 9}}, + {m68k_op_negx_32_ix , 0xfff8, 0x40b0, { 26, 26, 11, 11, 11}}, + {m68k_op_move_16_frs_d , 0xfff8, 0x40c0, { 6, 4, 8, 8, 8}}, + {m68k_op_move_16_frs_ai , 0xfff8, 0x40d0, { 12, 12, 12, 12, 12}}, + {m68k_op_move_16_frs_pi , 0xfff8, 0x40d8, { 12, 12, 12, 12, 12}}, + {m68k_op_move_16_frs_pd , 0xfff8, 0x40e0, { 14, 14, 13, 13, 13}}, + {m68k_op_move_16_frs_di , 0xfff8, 0x40e8, { 16, 16, 13, 13, 13}}, + {m68k_op_move_16_frs_ix , 0xfff8, 0x40f0, { 18, 18, 15, 15, 15}}, + {m68k_op_clr_8_d , 0xfff8, 0x4200, { 4, 4, 2, 2, 2}}, + {m68k_op_clr_8_ai , 0xfff8, 0x4210, { 12, 8, 8, 8, 8}}, + {m68k_op_clr_8_pi , 0xfff8, 0x4218, { 12, 8, 8, 8, 8}}, + {m68k_op_clr_8_pd , 0xfff8, 0x4220, { 14, 10, 9, 9, 9}}, + {m68k_op_clr_8_di , 0xfff8, 0x4228, { 16, 12, 9, 9, 9}}, + {m68k_op_clr_8_ix , 0xfff8, 0x4230, { 18, 14, 11, 11, 11}}, + {m68k_op_clr_16_d , 0xfff8, 0x4240, { 4, 4, 2, 2, 2}}, + {m68k_op_clr_16_ai , 0xfff8, 0x4250, { 12, 8, 8, 8, 8}}, + {m68k_op_clr_16_pi , 0xfff8, 0x4258, { 12, 8, 8, 8, 8}}, + {m68k_op_clr_16_pd , 0xfff8, 0x4260, { 14, 10, 9, 9, 9}}, + {m68k_op_clr_16_di , 0xfff8, 0x4268, { 16, 12, 9, 9, 9}}, + {m68k_op_clr_16_ix , 0xfff8, 0x4270, { 18, 14, 11, 11, 11}}, + {m68k_op_clr_32_d , 0xfff8, 0x4280, { 6, 6, 2, 2, 2}}, + {m68k_op_clr_32_ai , 0xfff8, 0x4290, { 20, 12, 8, 8, 8}}, + {m68k_op_clr_32_pi , 0xfff8, 0x4298, { 20, 12, 8, 8, 8}}, + {m68k_op_clr_32_pd , 0xfff8, 0x42a0, { 22, 14, 9, 9, 9}}, + {m68k_op_clr_32_di , 0xfff8, 0x42a8, { 24, 16, 9, 9, 9}}, + {m68k_op_clr_32_ix , 0xfff8, 0x42b0, { 26, 20, 11, 11, 11}}, + {m68k_op_move_16_frc_d , 0xfff8, 0x42c0, { 0, 4, 4, 4, 4}}, + {m68k_op_move_16_frc_ai , 0xfff8, 0x42d0, { 0, 12, 8, 8, 8}}, + {m68k_op_move_16_frc_pi , 0xfff8, 0x42d8, { 0, 12, 8, 8, 8}}, + {m68k_op_move_16_frc_pd , 0xfff8, 0x42e0, { 0, 14, 9, 9, 9}}, + {m68k_op_move_16_frc_di , 0xfff8, 0x42e8, { 0, 16, 9, 9, 9}}, + {m68k_op_move_16_frc_ix , 0xfff8, 0x42f0, { 0, 18, 11, 11, 11}}, + {m68k_op_neg_8_d , 0xfff8, 0x4400, { 4, 4, 2, 2, 2}}, + {m68k_op_neg_8_ai , 0xfff8, 0x4410, { 12, 12, 8, 8, 8}}, + {m68k_op_neg_8_pi , 0xfff8, 0x4418, { 12, 12, 8, 8, 8}}, + {m68k_op_neg_8_pd , 0xfff8, 0x4420, { 14, 14, 9, 9, 9}}, + {m68k_op_neg_8_di , 0xfff8, 0x4428, { 16, 16, 9, 9, 9}}, + {m68k_op_neg_8_ix , 0xfff8, 0x4430, { 18, 18, 11, 11, 11}}, + {m68k_op_neg_16_d , 0xfff8, 0x4440, { 4, 4, 2, 2, 2}}, + {m68k_op_neg_16_ai , 0xfff8, 0x4450, { 12, 12, 8, 8, 8}}, + {m68k_op_neg_16_pi , 0xfff8, 0x4458, { 12, 12, 8, 8, 8}}, + {m68k_op_neg_16_pd , 0xfff8, 0x4460, { 14, 14, 9, 9, 9}}, + {m68k_op_neg_16_di , 0xfff8, 0x4468, { 16, 16, 9, 9, 9}}, + {m68k_op_neg_16_ix , 0xfff8, 0x4470, { 18, 18, 11, 11, 11}}, + {m68k_op_neg_32_d , 0xfff8, 0x4480, { 6, 6, 2, 2, 2}}, + {m68k_op_neg_32_ai , 0xfff8, 0x4490, { 20, 20, 8, 8, 8}}, + {m68k_op_neg_32_pi , 0xfff8, 0x4498, { 20, 20, 8, 8, 8}}, + {m68k_op_neg_32_pd , 0xfff8, 0x44a0, { 22, 22, 9, 9, 9}}, + {m68k_op_neg_32_di , 0xfff8, 0x44a8, { 24, 24, 9, 9, 9}}, + {m68k_op_neg_32_ix , 0xfff8, 0x44b0, { 26, 26, 11, 11, 11}}, + {m68k_op_move_16_toc_d , 0xfff8, 0x44c0, { 12, 12, 4, 4, 4}}, + {m68k_op_move_16_toc_ai , 0xfff8, 0x44d0, { 16, 16, 8, 8, 8}}, + {m68k_op_move_16_toc_pi , 0xfff8, 0x44d8, { 16, 16, 8, 8, 8}}, + {m68k_op_move_16_toc_pd , 0xfff8, 0x44e0, { 18, 18, 9, 9, 9}}, + {m68k_op_move_16_toc_di , 0xfff8, 0x44e8, { 20, 20, 9, 9, 9}}, + {m68k_op_move_16_toc_ix , 0xfff8, 0x44f0, { 22, 22, 11, 11, 11}}, + {m68k_op_not_8_d , 0xfff8, 0x4600, { 4, 4, 2, 2, 2}}, + {m68k_op_not_8_ai , 0xfff8, 0x4610, { 12, 12, 8, 8, 8}}, + {m68k_op_not_8_pi , 0xfff8, 0x4618, { 12, 12, 8, 8, 8}}, + {m68k_op_not_8_pd , 0xfff8, 0x4620, { 14, 14, 9, 9, 9}}, + {m68k_op_not_8_di , 0xfff8, 0x4628, { 16, 16, 9, 9, 9}}, + {m68k_op_not_8_ix , 0xfff8, 0x4630, { 18, 18, 11, 11, 11}}, + {m68k_op_not_16_d , 0xfff8, 0x4640, { 4, 4, 2, 2, 2}}, + {m68k_op_not_16_ai , 0xfff8, 0x4650, { 12, 12, 8, 8, 8}}, + {m68k_op_not_16_pi , 0xfff8, 0x4658, { 12, 12, 8, 8, 8}}, + {m68k_op_not_16_pd , 0xfff8, 0x4660, { 14, 14, 9, 9, 9}}, + {m68k_op_not_16_di , 0xfff8, 0x4668, { 16, 16, 9, 9, 9}}, + {m68k_op_not_16_ix , 0xfff8, 0x4670, { 18, 18, 11, 11, 11}}, + {m68k_op_not_32_d , 0xfff8, 0x4680, { 6, 6, 2, 2, 2}}, + {m68k_op_not_32_ai , 0xfff8, 0x4690, { 20, 20, 8, 8, 8}}, + {m68k_op_not_32_pi , 0xfff8, 0x4698, { 20, 20, 8, 8, 8}}, + {m68k_op_not_32_pd , 0xfff8, 0x46a0, { 22, 22, 9, 9, 9}}, + {m68k_op_not_32_di , 0xfff8, 0x46a8, { 24, 24, 9, 9, 9}}, + {m68k_op_not_32_ix , 0xfff8, 0x46b0, { 26, 26, 11, 11, 11}}, + {m68k_op_move_16_tos_d , 0xfff8, 0x46c0, { 12, 12, 8, 8, 8}}, + {m68k_op_move_16_tos_ai , 0xfff8, 0x46d0, { 16, 16, 12, 12, 12}}, + {m68k_op_move_16_tos_pi , 0xfff8, 0x46d8, { 16, 16, 12, 12, 12}}, + {m68k_op_move_16_tos_pd , 0xfff8, 0x46e0, { 18, 18, 13, 13, 13}}, + {m68k_op_move_16_tos_di , 0xfff8, 0x46e8, { 20, 20, 13, 13, 13}}, + {m68k_op_move_16_tos_ix , 0xfff8, 0x46f0, { 22, 22, 15, 15, 15}}, + {m68k_op_nbcd_8_d , 0xfff8, 0x4800, { 6, 6, 6, 6, 6}}, + {m68k_op_link_32 , 0xfff8, 0x4808, { 0, 0, 6, 6, 6}}, + {m68k_op_nbcd_8_ai , 0xfff8, 0x4810, { 12, 12, 10, 10, 10}}, + {m68k_op_nbcd_8_pi , 0xfff8, 0x4818, { 12, 12, 10, 10, 10}}, + {m68k_op_nbcd_8_pd , 0xfff8, 0x4820, { 14, 14, 11, 11, 11}}, + {m68k_op_nbcd_8_di , 0xfff8, 0x4828, { 16, 16, 11, 11, 11}}, + {m68k_op_nbcd_8_ix , 0xfff8, 0x4830, { 18, 18, 13, 13, 13}}, + {m68k_op_swap_32 , 0xfff8, 0x4840, { 4, 4, 4, 4, 4}}, + {m68k_op_bkpt , 0xfff8, 0x4848, { 0, 10, 10, 10, 10}}, + {m68k_op_pea_32_ai , 0xfff8, 0x4850, { 12, 12, 9, 9, 9}}, + {m68k_op_pea_32_di , 0xfff8, 0x4868, { 16, 16, 10, 10, 10}}, + {m68k_op_pea_32_ix , 0xfff8, 0x4870, { 20, 20, 12, 12, 12}}, + {m68k_op_ext_16 , 0xfff8, 0x4880, { 4, 4, 4, 4, 4}}, + {m68k_op_movem_16_re_ai , 0xfff8, 0x4890, { 8, 8, 8, 8, 8}}, + {m68k_op_movem_16_re_pd , 0xfff8, 0x48a0, { 8, 8, 4, 4, 4}}, + {m68k_op_movem_16_re_di , 0xfff8, 0x48a8, { 12, 12, 9, 9, 9}}, + {m68k_op_movem_16_re_ix , 0xfff8, 0x48b0, { 14, 14, 11, 11, 11}}, + {m68k_op_ext_32 , 0xfff8, 0x48c0, { 4, 4, 4, 4, 4}}, + {m68k_op_movem_32_re_ai , 0xfff8, 0x48d0, { 8, 8, 8, 8, 8}}, + {m68k_op_movem_32_re_pd , 0xfff8, 0x48e0, { 8, 8, 4, 4, 4}}, + {m68k_op_movem_32_re_di , 0xfff8, 0x48e8, { 12, 12, 9, 9, 9}}, + {m68k_op_movem_32_re_ix , 0xfff8, 0x48f0, { 14, 14, 11, 11, 11}}, + {m68k_op_extb_32 , 0xfff8, 0x49c0, { 0, 0, 4, 4, 4}}, + {m68k_op_tst_8_d , 0xfff8, 0x4a00, { 4, 4, 2, 2, 2}}, + {m68k_op_tst_8_ai , 0xfff8, 0x4a10, { 8, 8, 6, 6, 6}}, + {m68k_op_tst_8_pi , 0xfff8, 0x4a18, { 8, 8, 6, 6, 6}}, + {m68k_op_tst_8_pd , 0xfff8, 0x4a20, { 10, 10, 7, 7, 7}}, + {m68k_op_tst_8_di , 0xfff8, 0x4a28, { 12, 12, 7, 7, 7}}, + {m68k_op_tst_8_ix , 0xfff8, 0x4a30, { 14, 14, 9, 9, 9}}, + {m68k_op_tst_16_d , 0xfff8, 0x4a40, { 4, 4, 2, 2, 2}}, + {m68k_op_tst_16_a , 0xfff8, 0x4a48, { 0, 0, 2, 2, 2}}, + {m68k_op_tst_16_ai , 0xfff8, 0x4a50, { 8, 8, 6, 6, 6}}, + {m68k_op_tst_16_pi , 0xfff8, 0x4a58, { 8, 8, 6, 6, 6}}, + {m68k_op_tst_16_pd , 0xfff8, 0x4a60, { 10, 10, 7, 7, 7}}, + {m68k_op_tst_16_di , 0xfff8, 0x4a68, { 12, 12, 7, 7, 7}}, + {m68k_op_tst_16_ix , 0xfff8, 0x4a70, { 14, 14, 9, 9, 9}}, + {m68k_op_tst_32_d , 0xfff8, 0x4a80, { 4, 4, 2, 2, 2}}, + {m68k_op_tst_32_a , 0xfff8, 0x4a88, { 0, 0, 2, 2, 2}}, + {m68k_op_tst_32_ai , 0xfff8, 0x4a90, { 12, 12, 6, 6, 6}}, + {m68k_op_tst_32_pi , 0xfff8, 0x4a98, { 12, 12, 6, 6, 6}}, + {m68k_op_tst_32_pd , 0xfff8, 0x4aa0, { 14, 14, 7, 7, 7}}, + {m68k_op_tst_32_di , 0xfff8, 0x4aa8, { 16, 16, 7, 7, 7}}, + {m68k_op_tst_32_ix , 0xfff8, 0x4ab0, { 18, 18, 9, 9, 9}}, + {m68k_op_tas_8_d , 0xfff8, 0x4ac0, { 4, 4, 4, 4, 4}}, + {m68k_op_tas_8_ai , 0xfff8, 0x4ad0, { 18, 18, 16, 16, 16}}, + {m68k_op_tas_8_pi , 0xfff8, 0x4ad8, { 18, 18, 16, 16, 16}}, + {m68k_op_tas_8_pd , 0xfff8, 0x4ae0, { 20, 20, 17, 17, 17}}, + {m68k_op_tas_8_di , 0xfff8, 0x4ae8, { 22, 22, 17, 17, 17}}, + {m68k_op_tas_8_ix , 0xfff8, 0x4af0, { 24, 24, 19, 19, 19}}, + {m68k_op_mull_32_d , 0xfff8, 0x4c00, { 0, 0, 43, 43, 43}}, + {m68k_op_mull_32_ai , 0xfff8, 0x4c10, { 0, 0, 47, 47, 47}}, + {m68k_op_mull_32_pi , 0xfff8, 0x4c18, { 0, 0, 47, 47, 47}}, + {m68k_op_mull_32_pd , 0xfff8, 0x4c20, { 0, 0, 48, 48, 48}}, + {m68k_op_mull_32_di , 0xfff8, 0x4c28, { 0, 0, 48, 48, 48}}, + {m68k_op_mull_32_ix , 0xfff8, 0x4c30, { 0, 0, 50, 50, 50}}, + {m68k_op_divl_32_d , 0xfff8, 0x4c40, { 0, 0, 84, 84, 84}}, + {m68k_op_divl_32_ai , 0xfff8, 0x4c50, { 0, 0, 88, 88, 88}}, + {m68k_op_divl_32_pi , 0xfff8, 0x4c58, { 0, 0, 88, 88, 88}}, + {m68k_op_divl_32_pd , 0xfff8, 0x4c60, { 0, 0, 89, 89, 89}}, + {m68k_op_divl_32_di , 0xfff8, 0x4c68, { 0, 0, 89, 89, 89}}, + {m68k_op_divl_32_ix , 0xfff8, 0x4c70, { 0, 0, 91, 91, 91}}, + {m68k_op_movem_16_er_ai , 0xfff8, 0x4c90, { 12, 12, 12, 12, 12}}, + {m68k_op_movem_16_er_pi , 0xfff8, 0x4c98, { 12, 12, 8, 8, 8}}, + {m68k_op_movem_16_er_di , 0xfff8, 0x4ca8, { 16, 16, 13, 13, 13}}, + {m68k_op_movem_16_er_ix , 0xfff8, 0x4cb0, { 18, 18, 15, 15, 15}}, + {m68k_op_movem_32_er_ai , 0xfff8, 0x4cd0, { 12, 12, 12, 12, 12}}, + {m68k_op_movem_32_er_pi , 0xfff8, 0x4cd8, { 12, 12, 8, 8, 8}}, + {m68k_op_movem_32_er_di , 0xfff8, 0x4ce8, { 16, 16, 13, 13, 13}}, + {m68k_op_movem_32_er_ix , 0xfff8, 0x4cf0, { 18, 18, 15, 15, 15}}, + {m68k_op_link_16 , 0xfff8, 0x4e50, { 16, 16, 5, 5, 5}}, + {m68k_op_unlk_32 , 0xfff8, 0x4e58, { 12, 12, 6, 6, 6}}, + {m68k_op_move_32_tou , 0xfff8, 0x4e60, { 4, 6, 2, 2, 2}}, + {m68k_op_move_32_fru , 0xfff8, 0x4e68, { 4, 6, 2, 2, 2}}, + {m68k_op_jsr_32_ai , 0xfff8, 0x4e90, { 16, 16, 4, 4, 4}}, + {m68k_op_jsr_32_di , 0xfff8, 0x4ea8, { 18, 18, 5, 5, 5}}, + {m68k_op_jsr_32_ix , 0xfff8, 0x4eb0, { 22, 22, 7, 7, 7}}, + {m68k_op_jmp_32_ai , 0xfff8, 0x4ed0, { 8, 8, 4, 4, 4}}, + {m68k_op_jmp_32_di , 0xfff8, 0x4ee8, { 10, 10, 5, 5, 5}}, + {m68k_op_jmp_32_ix , 0xfff8, 0x4ef0, { 14, 14, 7, 7, 7}}, + {m68k_op_st_8_d , 0xfff8, 0x50c0, { 6, 4, 4, 4, 4}}, + {m68k_op_dbt_16 , 0xfff8, 0x50c8, { 12, 12, 6, 6, 6}}, + {m68k_op_st_8_ai , 0xfff8, 0x50d0, { 12, 12, 10, 10, 10}}, + {m68k_op_st_8_pi , 0xfff8, 0x50d8, { 12, 12, 10, 10, 10}}, + {m68k_op_st_8_pd , 0xfff8, 0x50e0, { 14, 14, 11, 11, 11}}, + {m68k_op_st_8_di , 0xfff8, 0x50e8, { 16, 16, 11, 11, 11}}, + {m68k_op_st_8_ix , 0xfff8, 0x50f0, { 18, 18, 13, 13, 13}}, + {m68k_op_sf_8_d , 0xfff8, 0x51c0, { 4, 4, 4, 4, 4}}, + {m68k_op_dbf_16 , 0xfff8, 0x51c8, { 12, 12, 6, 6, 6}}, + {m68k_op_sf_8_ai , 0xfff8, 0x51d0, { 12, 12, 10, 10, 10}}, + {m68k_op_sf_8_pi , 0xfff8, 0x51d8, { 12, 12, 10, 10, 10}}, + {m68k_op_sf_8_pd , 0xfff8, 0x51e0, { 14, 14, 11, 11, 11}}, + {m68k_op_sf_8_di , 0xfff8, 0x51e8, { 16, 16, 11, 11, 11}}, + {m68k_op_sf_8_ix , 0xfff8, 0x51f0, { 18, 18, 13, 13, 13}}, + {m68k_op_shi_8_d , 0xfff8, 0x52c0, { 4, 4, 4, 4, 4}}, + {m68k_op_dbhi_16 , 0xfff8, 0x52c8, { 12, 12, 6, 6, 6}}, + {m68k_op_shi_8_ai , 0xfff8, 0x52d0, { 12, 12, 10, 10, 10}}, + {m68k_op_shi_8_pi , 0xfff8, 0x52d8, { 12, 12, 10, 10, 10}}, + {m68k_op_shi_8_pd , 0xfff8, 0x52e0, { 14, 14, 11, 11, 11}}, + {m68k_op_shi_8_di , 0xfff8, 0x52e8, { 16, 16, 11, 11, 11}}, + {m68k_op_shi_8_ix , 0xfff8, 0x52f0, { 18, 18, 13, 13, 13}}, + {m68k_op_sls_8_d , 0xfff8, 0x53c0, { 4, 4, 4, 4, 4}}, + {m68k_op_dbls_16 , 0xfff8, 0x53c8, { 12, 12, 6, 6, 6}}, + {m68k_op_sls_8_ai , 0xfff8, 0x53d0, { 12, 12, 10, 10, 10}}, + {m68k_op_sls_8_pi , 0xfff8, 0x53d8, { 12, 12, 10, 10, 10}}, + {m68k_op_sls_8_pd , 0xfff8, 0x53e0, { 14, 14, 11, 11, 11}}, + {m68k_op_sls_8_di , 0xfff8, 0x53e8, { 16, 16, 11, 11, 11}}, + {m68k_op_sls_8_ix , 0xfff8, 0x53f0, { 18, 18, 13, 13, 13}}, + {m68k_op_scc_8_d , 0xfff8, 0x54c0, { 4, 4, 4, 4, 4}}, + {m68k_op_dbcc_16 , 0xfff8, 0x54c8, { 12, 12, 6, 6, 6}}, + {m68k_op_scc_8_ai , 0xfff8, 0x54d0, { 12, 12, 10, 10, 10}}, + {m68k_op_scc_8_pi , 0xfff8, 0x54d8, { 12, 12, 10, 10, 10}}, + {m68k_op_scc_8_pd , 0xfff8, 0x54e0, { 14, 14, 11, 11, 11}}, + {m68k_op_scc_8_di , 0xfff8, 0x54e8, { 16, 16, 11, 11, 11}}, + {m68k_op_scc_8_ix , 0xfff8, 0x54f0, { 18, 18, 13, 13, 13}}, + {m68k_op_scs_8_d , 0xfff8, 0x55c0, { 4, 4, 4, 4, 4}}, + {m68k_op_dbcs_16 , 0xfff8, 0x55c8, { 12, 12, 6, 6, 6}}, + {m68k_op_scs_8_ai , 0xfff8, 0x55d0, { 12, 12, 10, 10, 10}}, + {m68k_op_scs_8_pi , 0xfff8, 0x55d8, { 12, 12, 10, 10, 10}}, + {m68k_op_scs_8_pd , 0xfff8, 0x55e0, { 14, 14, 11, 11, 11}}, + {m68k_op_scs_8_di , 0xfff8, 0x55e8, { 16, 16, 11, 11, 11}}, + {m68k_op_scs_8_ix , 0xfff8, 0x55f0, { 18, 18, 13, 13, 13}}, + {m68k_op_sne_8_d , 0xfff8, 0x56c0, { 4, 4, 4, 4, 4}}, + {m68k_op_dbne_16 , 0xfff8, 0x56c8, { 12, 12, 6, 6, 6}}, + {m68k_op_sne_8_ai , 0xfff8, 0x56d0, { 12, 12, 10, 10, 10}}, + {m68k_op_sne_8_pi , 0xfff8, 0x56d8, { 12, 12, 10, 10, 10}}, + {m68k_op_sne_8_pd , 0xfff8, 0x56e0, { 14, 14, 11, 11, 11}}, + {m68k_op_sne_8_di , 0xfff8, 0x56e8, { 16, 16, 11, 11, 11}}, + {m68k_op_sne_8_ix , 0xfff8, 0x56f0, { 18, 18, 13, 13, 13}}, + {m68k_op_seq_8_d , 0xfff8, 0x57c0, { 4, 4, 4, 4, 4}}, + {m68k_op_dbeq_16 , 0xfff8, 0x57c8, { 12, 12, 6, 6, 6}}, + {m68k_op_seq_8_ai , 0xfff8, 0x57d0, { 12, 12, 10, 10, 10}}, + {m68k_op_seq_8_pi , 0xfff8, 0x57d8, { 12, 12, 10, 10, 10}}, + {m68k_op_seq_8_pd , 0xfff8, 0x57e0, { 14, 14, 11, 11, 11}}, + {m68k_op_seq_8_di , 0xfff8, 0x57e8, { 16, 16, 11, 11, 11}}, + {m68k_op_seq_8_ix , 0xfff8, 0x57f0, { 18, 18, 13, 13, 13}}, + {m68k_op_svc_8_d , 0xfff8, 0x58c0, { 4, 4, 4, 4, 4}}, + {m68k_op_dbvc_16 , 0xfff8, 0x58c8, { 12, 12, 6, 6, 6}}, + {m68k_op_svc_8_ai , 0xfff8, 0x58d0, { 12, 12, 10, 10, 10}}, + {m68k_op_svc_8_pi , 0xfff8, 0x58d8, { 12, 12, 10, 10, 10}}, + {m68k_op_svc_8_pd , 0xfff8, 0x58e0, { 14, 14, 11, 11, 11}}, + {m68k_op_svc_8_di , 0xfff8, 0x58e8, { 16, 16, 11, 11, 11}}, + {m68k_op_svc_8_ix , 0xfff8, 0x58f0, { 18, 18, 13, 13, 13}}, + {m68k_op_svs_8_d , 0xfff8, 0x59c0, { 4, 4, 4, 4, 4}}, + {m68k_op_dbvs_16 , 0xfff8, 0x59c8, { 12, 12, 6, 6, 6}}, + {m68k_op_svs_8_ai , 0xfff8, 0x59d0, { 12, 12, 10, 10, 10}}, + {m68k_op_svs_8_pi , 0xfff8, 0x59d8, { 12, 12, 10, 10, 10}}, + {m68k_op_svs_8_pd , 0xfff8, 0x59e0, { 14, 14, 11, 11, 11}}, + {m68k_op_svs_8_di , 0xfff8, 0x59e8, { 16, 16, 11, 11, 11}}, + {m68k_op_svs_8_ix , 0xfff8, 0x59f0, { 18, 18, 13, 13, 13}}, + {m68k_op_spl_8_d , 0xfff8, 0x5ac0, { 4, 4, 4, 4, 4}}, + {m68k_op_dbpl_16 , 0xfff8, 0x5ac8, { 12, 12, 6, 6, 6}}, + {m68k_op_spl_8_ai , 0xfff8, 0x5ad0, { 12, 12, 10, 10, 10}}, + {m68k_op_spl_8_pi , 0xfff8, 0x5ad8, { 12, 12, 10, 10, 10}}, + {m68k_op_spl_8_pd , 0xfff8, 0x5ae0, { 14, 14, 11, 11, 11}}, + {m68k_op_spl_8_di , 0xfff8, 0x5ae8, { 16, 16, 11, 11, 11}}, + {m68k_op_spl_8_ix , 0xfff8, 0x5af0, { 18, 18, 13, 13, 13}}, + {m68k_op_smi_8_d , 0xfff8, 0x5bc0, { 4, 4, 4, 4, 4}}, + {m68k_op_dbmi_16 , 0xfff8, 0x5bc8, { 12, 12, 6, 6, 6}}, + {m68k_op_smi_8_ai , 0xfff8, 0x5bd0, { 12, 12, 10, 10, 10}}, + {m68k_op_smi_8_pi , 0xfff8, 0x5bd8, { 12, 12, 10, 10, 10}}, + {m68k_op_smi_8_pd , 0xfff8, 0x5be0, { 14, 14, 11, 11, 11}}, + {m68k_op_smi_8_di , 0xfff8, 0x5be8, { 16, 16, 11, 11, 11}}, + {m68k_op_smi_8_ix , 0xfff8, 0x5bf0, { 18, 18, 13, 13, 13}}, + {m68k_op_sge_8_d , 0xfff8, 0x5cc0, { 4, 4, 4, 4, 4}}, + {m68k_op_dbge_16 , 0xfff8, 0x5cc8, { 12, 12, 6, 6, 6}}, + {m68k_op_sge_8_ai , 0xfff8, 0x5cd0, { 12, 12, 10, 10, 10}}, + {m68k_op_sge_8_pi , 0xfff8, 0x5cd8, { 12, 12, 10, 10, 10}}, + {m68k_op_sge_8_pd , 0xfff8, 0x5ce0, { 14, 14, 11, 11, 11}}, + {m68k_op_sge_8_di , 0xfff8, 0x5ce8, { 16, 16, 11, 11, 11}}, + {m68k_op_sge_8_ix , 0xfff8, 0x5cf0, { 18, 18, 13, 13, 13}}, + {m68k_op_slt_8_d , 0xfff8, 0x5dc0, { 4, 4, 4, 4, 4}}, + {m68k_op_dblt_16 , 0xfff8, 0x5dc8, { 12, 12, 6, 6, 6}}, + {m68k_op_slt_8_ai , 0xfff8, 0x5dd0, { 12, 12, 10, 10, 10}}, + {m68k_op_slt_8_pi , 0xfff8, 0x5dd8, { 12, 12, 10, 10, 10}}, + {m68k_op_slt_8_pd , 0xfff8, 0x5de0, { 14, 14, 11, 11, 11}}, + {m68k_op_slt_8_di , 0xfff8, 0x5de8, { 16, 16, 11, 11, 11}}, + {m68k_op_slt_8_ix , 0xfff8, 0x5df0, { 18, 18, 13, 13, 13}}, + {m68k_op_sgt_8_d , 0xfff8, 0x5ec0, { 4, 4, 4, 4, 4}}, + {m68k_op_dbgt_16 , 0xfff8, 0x5ec8, { 12, 12, 6, 6, 6}}, + {m68k_op_sgt_8_ai , 0xfff8, 0x5ed0, { 12, 12, 10, 10, 10}}, + {m68k_op_sgt_8_pi , 0xfff8, 0x5ed8, { 12, 12, 10, 10, 10}}, + {m68k_op_sgt_8_pd , 0xfff8, 0x5ee0, { 14, 14, 11, 11, 11}}, + {m68k_op_sgt_8_di , 0xfff8, 0x5ee8, { 16, 16, 11, 11, 11}}, + {m68k_op_sgt_8_ix , 0xfff8, 0x5ef0, { 18, 18, 13, 13, 13}}, + {m68k_op_sle_8_d , 0xfff8, 0x5fc0, { 4, 4, 4, 4, 4}}, + {m68k_op_dble_16 , 0xfff8, 0x5fc8, { 12, 12, 6, 6, 6}}, + {m68k_op_sle_8_ai , 0xfff8, 0x5fd0, { 12, 12, 10, 10, 10}}, + {m68k_op_sle_8_pi , 0xfff8, 0x5fd8, { 12, 12, 10, 10, 10}}, + {m68k_op_sle_8_pd , 0xfff8, 0x5fe0, { 14, 14, 11, 11, 11}}, + {m68k_op_sle_8_di , 0xfff8, 0x5fe8, { 16, 16, 11, 11, 11}}, + {m68k_op_sle_8_ix , 0xfff8, 0x5ff0, { 18, 18, 13, 13, 13}}, + {m68k_op_sbcd_8_mm_ax7 , 0xfff8, 0x8f08, { 18, 18, 16, 16, 16}}, + {m68k_op_pack_16_mm_ax7 , 0xfff8, 0x8f48, { 0, 0, 13, 13, 13}}, + {m68k_op_unpk_16_mm_ax7 , 0xfff8, 0x8f88, { 0, 0, 13, 13, 13}}, + {m68k_op_subx_8_mm_ax7 , 0xfff8, 0x9f08, { 18, 18, 12, 12, 12}}, + {m68k_op_cmpm_8_ax7 , 0xfff8, 0xbf08, { 12, 12, 9, 9, 9}}, + {m68k_op_abcd_8_mm_ax7 , 0xfff8, 0xcf08, { 18, 18, 16, 16, 16}}, + {m68k_op_addx_8_mm_ax7 , 0xfff8, 0xdf08, { 18, 18, 12, 12, 12}}, + {m68k_op_asr_16_ai , 0xfff8, 0xe0d0, { 12, 12, 9, 9, 9}}, + {m68k_op_asr_16_pi , 0xfff8, 0xe0d8, { 12, 12, 9, 9, 9}}, + {m68k_op_asr_16_pd , 0xfff8, 0xe0e0, { 14, 14, 10, 10, 10}}, + {m68k_op_asr_16_di , 0xfff8, 0xe0e8, { 16, 16, 10, 10, 10}}, + {m68k_op_asr_16_ix , 0xfff8, 0xe0f0, { 18, 18, 12, 12, 12}}, + {m68k_op_asl_16_ai , 0xfff8, 0xe1d0, { 12, 12, 10, 10, 10}}, + {m68k_op_asl_16_pi , 0xfff8, 0xe1d8, { 12, 12, 10, 10, 10}}, + {m68k_op_asl_16_pd , 0xfff8, 0xe1e0, { 14, 14, 11, 11, 11}}, + {m68k_op_asl_16_di , 0xfff8, 0xe1e8, { 16, 16, 11, 11, 11}}, + {m68k_op_asl_16_ix , 0xfff8, 0xe1f0, { 18, 18, 13, 13, 13}}, + {m68k_op_lsr_16_ai , 0xfff8, 0xe2d0, { 12, 12, 9, 9, 9}}, + {m68k_op_lsr_16_pi , 0xfff8, 0xe2d8, { 12, 12, 9, 9, 9}}, + {m68k_op_lsr_16_pd , 0xfff8, 0xe2e0, { 14, 14, 10, 10, 10}}, + {m68k_op_lsr_16_di , 0xfff8, 0xe2e8, { 16, 16, 10, 10, 10}}, + {m68k_op_lsr_16_ix , 0xfff8, 0xe2f0, { 18, 18, 12, 12, 12}}, + {m68k_op_lsl_16_ai , 0xfff8, 0xe3d0, { 12, 12, 9, 9, 9}}, + {m68k_op_lsl_16_pi , 0xfff8, 0xe3d8, { 12, 12, 9, 9, 9}}, + {m68k_op_lsl_16_pd , 0xfff8, 0xe3e0, { 14, 14, 10, 10, 10}}, + {m68k_op_lsl_16_di , 0xfff8, 0xe3e8, { 16, 16, 10, 10, 10}}, + {m68k_op_lsl_16_ix , 0xfff8, 0xe3f0, { 18, 18, 12, 12, 12}}, + {m68k_op_roxr_16_ai , 0xfff8, 0xe4d0, { 12, 12, 9, 9, 9}}, + {m68k_op_roxr_16_pi , 0xfff8, 0xe4d8, { 12, 12, 9, 9, 9}}, + {m68k_op_roxr_16_pd , 0xfff8, 0xe4e0, { 14, 14, 10, 10, 10}}, + {m68k_op_roxr_16_di , 0xfff8, 0xe4e8, { 16, 16, 10, 10, 10}}, + {m68k_op_roxr_16_ix , 0xfff8, 0xe4f0, { 18, 18, 12, 12, 12}}, + {m68k_op_roxl_16_ai , 0xfff8, 0xe5d0, { 12, 12, 9, 9, 9}}, + {m68k_op_roxl_16_pi , 0xfff8, 0xe5d8, { 12, 12, 9, 9, 9}}, + {m68k_op_roxl_16_pd , 0xfff8, 0xe5e0, { 14, 14, 10, 10, 10}}, + {m68k_op_roxl_16_di , 0xfff8, 0xe5e8, { 16, 16, 10, 10, 10}}, + {m68k_op_roxl_16_ix , 0xfff8, 0xe5f0, { 18, 18, 12, 12, 12}}, + {m68k_op_ror_16_ai , 0xfff8, 0xe6d0, { 12, 12, 11, 11, 11}}, + {m68k_op_ror_16_pi , 0xfff8, 0xe6d8, { 12, 12, 11, 11, 11}}, + {m68k_op_ror_16_pd , 0xfff8, 0xe6e0, { 14, 14, 12, 12, 12}}, + {m68k_op_ror_16_di , 0xfff8, 0xe6e8, { 16, 16, 12, 12, 12}}, + {m68k_op_ror_16_ix , 0xfff8, 0xe6f0, { 18, 18, 14, 14, 14}}, + {m68k_op_rol_16_ai , 0xfff8, 0xe7d0, { 12, 12, 11, 11, 11}}, + {m68k_op_rol_16_pi , 0xfff8, 0xe7d8, { 12, 12, 11, 11, 11}}, + {m68k_op_rol_16_pd , 0xfff8, 0xe7e0, { 14, 14, 12, 12, 12}}, + {m68k_op_rol_16_di , 0xfff8, 0xe7e8, { 16, 16, 12, 12, 12}}, + {m68k_op_rol_16_ix , 0xfff8, 0xe7f0, { 18, 18, 14, 14, 14}}, + {m68k_op_bftst_32_d , 0xfff8, 0xe8c0, { 0, 0, 6, 6, 6}}, + {m68k_op_bftst_32_ai , 0xfff8, 0xe8d0, { 0, 0, 17, 17, 17}}, + {m68k_op_bftst_32_di , 0xfff8, 0xe8e8, { 0, 0, 18, 18, 18}}, + {m68k_op_bftst_32_ix , 0xfff8, 0xe8f0, { 0, 0, 20, 20, 20}}, + {m68k_op_bfextu_32_d , 0xfff8, 0xe9c0, { 0, 0, 8, 8, 8}}, + {m68k_op_bfextu_32_ai , 0xfff8, 0xe9d0, { 0, 0, 19, 19, 19}}, + {m68k_op_bfextu_32_di , 0xfff8, 0xe9e8, { 0, 0, 20, 20, 20}}, + {m68k_op_bfextu_32_ix , 0xfff8, 0xe9f0, { 0, 0, 22, 22, 22}}, + {m68k_op_bfchg_32_d , 0xfff8, 0xeac0, { 0, 0, 12, 12, 12}}, + {m68k_op_bfchg_32_ai , 0xfff8, 0xead0, { 0, 0, 24, 24, 24}}, + {m68k_op_bfchg_32_di , 0xfff8, 0xeae8, { 0, 0, 25, 25, 25}}, + {m68k_op_bfchg_32_ix , 0xfff8, 0xeaf0, { 0, 0, 27, 27, 27}}, + {m68k_op_bfexts_32_d , 0xfff8, 0xebc0, { 0, 0, 8, 8, 8}}, + {m68k_op_bfexts_32_ai , 0xfff8, 0xebd0, { 0, 0, 19, 19, 19}}, + {m68k_op_bfexts_32_di , 0xfff8, 0xebe8, { 0, 0, 20, 20, 20}}, + {m68k_op_bfexts_32_ix , 0xfff8, 0xebf0, { 0, 0, 22, 22, 22}}, + {m68k_op_bfclr_32_d , 0xfff8, 0xecc0, { 0, 0, 12, 12, 12}}, + {m68k_op_bfclr_32_ai , 0xfff8, 0xecd0, { 0, 0, 24, 24, 24}}, + {m68k_op_bfclr_32_di , 0xfff8, 0xece8, { 0, 0, 25, 25, 25}}, + {m68k_op_bfclr_32_ix , 0xfff8, 0xecf0, { 0, 0, 27, 27, 27}}, + {m68k_op_bfffo_32_d , 0xfff8, 0xedc0, { 0, 0, 18, 18, 18}}, + {m68k_op_bfffo_32_ai , 0xfff8, 0xedd0, { 0, 0, 32, 32, 32}}, + {m68k_op_bfffo_32_di , 0xfff8, 0xede8, { 0, 0, 33, 33, 33}}, + {m68k_op_bfffo_32_ix , 0xfff8, 0xedf0, { 0, 0, 35, 35, 35}}, + {m68k_op_bfset_32_d , 0xfff8, 0xeec0, { 0, 0, 12, 12, 12}}, + {m68k_op_bfset_32_ai , 0xfff8, 0xeed0, { 0, 0, 24, 24, 24}}, + {m68k_op_bfset_32_di , 0xfff8, 0xeee8, { 0, 0, 25, 25, 25}}, + {m68k_op_bfset_32_ix , 0xfff8, 0xeef0, { 0, 0, 27, 27, 27}}, + {m68k_op_bfins_32_d , 0xfff8, 0xefc0, { 0, 0, 10, 10, 10}}, + {m68k_op_bfins_32_ai , 0xfff8, 0xefd0, { 0, 0, 21, 21, 21}}, + {m68k_op_bfins_32_di , 0xfff8, 0xefe8, { 0, 0, 22, 22, 22}}, + {m68k_op_bfins_32_ix , 0xfff8, 0xeff0, { 0, 0, 24, 24, 24}}, + {m68k_op_move16_32 , 0xfff8, 0xf620, { 0, 0, 0, 0, 4}}, + {m68k_op_ori_8_pi7 , 0xffff, 0x001f, { 16, 16, 8, 8, 8}}, + {m68k_op_ori_8_pd7 , 0xffff, 0x0027, { 18, 18, 9, 9, 9}}, + {m68k_op_ori_8_aw , 0xffff, 0x0038, { 20, 20, 8, 8, 8}}, + {m68k_op_ori_8_al , 0xffff, 0x0039, { 24, 24, 8, 8, 8}}, + {m68k_op_ori_16_toc , 0xffff, 0x003c, { 20, 16, 12, 12, 12}}, + {m68k_op_ori_16_aw , 0xffff, 0x0078, { 20, 20, 8, 8, 8}}, + {m68k_op_ori_16_al , 0xffff, 0x0079, { 24, 24, 8, 8, 8}}, + {m68k_op_ori_16_tos , 0xffff, 0x007c, { 20, 16, 12, 12, 12}}, + {m68k_op_ori_32_aw , 0xffff, 0x00b8, { 32, 32, 8, 8, 8}}, + {m68k_op_ori_32_al , 0xffff, 0x00b9, { 36, 36, 8, 8, 8}}, + {m68k_op_chk2cmp2_8_aw , 0xffff, 0x00f8, { 0, 0, 22, 22, 22}}, + {m68k_op_chk2cmp2_8_al , 0xffff, 0x00f9, { 0, 0, 22, 22, 22}}, + {m68k_op_chk2cmp2_8_pcdi , 0xffff, 0x00fa, { 0, 0, 23, 23, 23}}, + {m68k_op_chk2cmp2_8_pcix , 0xffff, 0x00fb, { 0, 0, 23, 23, 23}}, + {m68k_op_andi_8_pi7 , 0xffff, 0x021f, { 16, 16, 8, 8, 8}}, + {m68k_op_andi_8_pd7 , 0xffff, 0x0227, { 18, 18, 9, 9, 9}}, + {m68k_op_andi_8_aw , 0xffff, 0x0238, { 20, 20, 8, 8, 8}}, + {m68k_op_andi_8_al , 0xffff, 0x0239, { 24, 24, 8, 8, 8}}, + {m68k_op_andi_16_toc , 0xffff, 0x023c, { 20, 16, 12, 12, 12}}, + {m68k_op_andi_16_aw , 0xffff, 0x0278, { 20, 20, 8, 8, 8}}, + {m68k_op_andi_16_al , 0xffff, 0x0279, { 24, 24, 8, 8, 8}}, + {m68k_op_andi_16_tos , 0xffff, 0x027c, { 20, 16, 12, 12, 12}}, + {m68k_op_andi_32_aw , 0xffff, 0x02b8, { 32, 32, 8, 8, 8}}, + {m68k_op_andi_32_al , 0xffff, 0x02b9, { 36, 36, 8, 8, 8}}, + {m68k_op_chk2cmp2_16_aw , 0xffff, 0x02f8, { 0, 0, 22, 22, 22}}, + {m68k_op_chk2cmp2_16_al , 0xffff, 0x02f9, { 0, 0, 22, 22, 22}}, + {m68k_op_chk2cmp2_16_pcdi , 0xffff, 0x02fa, { 0, 0, 23, 23, 23}}, + {m68k_op_chk2cmp2_16_pcix , 0xffff, 0x02fb, { 0, 0, 23, 23, 23}}, + {m68k_op_subi_8_pi7 , 0xffff, 0x041f, { 16, 16, 8, 8, 8}}, + {m68k_op_subi_8_pd7 , 0xffff, 0x0427, { 18, 18, 9, 9, 9}}, + {m68k_op_subi_8_aw , 0xffff, 0x0438, { 20, 20, 8, 8, 8}}, + {m68k_op_subi_8_al , 0xffff, 0x0439, { 24, 24, 8, 8, 8}}, + {m68k_op_subi_16_aw , 0xffff, 0x0478, { 20, 20, 8, 8, 8}}, + {m68k_op_subi_16_al , 0xffff, 0x0479, { 24, 24, 8, 8, 8}}, + {m68k_op_subi_32_aw , 0xffff, 0x04b8, { 32, 32, 8, 8, 8}}, + {m68k_op_subi_32_al , 0xffff, 0x04b9, { 36, 36, 8, 8, 8}}, + {m68k_op_chk2cmp2_32_aw , 0xffff, 0x04f8, { 0, 0, 22, 22, 22}}, + {m68k_op_chk2cmp2_32_al , 0xffff, 0x04f9, { 0, 0, 22, 22, 22}}, + {m68k_op_chk2cmp2_32_pcdi , 0xffff, 0x04fa, { 0, 0, 23, 23, 23}}, + {m68k_op_chk2cmp2_32_pcix , 0xffff, 0x04fb, { 0, 0, 23, 23, 23}}, + {m68k_op_addi_8_pi7 , 0xffff, 0x061f, { 16, 16, 8, 8, 8}}, + {m68k_op_addi_8_pd7 , 0xffff, 0x0627, { 18, 18, 9, 9, 9}}, + {m68k_op_addi_8_aw , 0xffff, 0x0638, { 20, 20, 8, 8, 8}}, + {m68k_op_addi_8_al , 0xffff, 0x0639, { 24, 24, 8, 8, 8}}, + {m68k_op_addi_16_aw , 0xffff, 0x0678, { 20, 20, 8, 8, 8}}, + {m68k_op_addi_16_al , 0xffff, 0x0679, { 24, 24, 8, 8, 8}}, + {m68k_op_addi_32_aw , 0xffff, 0x06b8, { 32, 32, 8, 8, 8}}, + {m68k_op_addi_32_al , 0xffff, 0x06b9, { 36, 36, 8, 8, 8}}, + {m68k_op_callm_32_aw , 0xffff, 0x06f8, { 0, 0, 64, 64, 64}}, + {m68k_op_callm_32_al , 0xffff, 0x06f9, { 0, 0, 64, 64, 64}}, + {m68k_op_callm_32_pcdi , 0xffff, 0x06fa, { 0, 0, 65, 65, 65}}, + {m68k_op_callm_32_pcix , 0xffff, 0x06fb, { 0, 0, 67, 67, 67}}, + {m68k_op_btst_8_s_pi7 , 0xffff, 0x081f, { 12, 12, 8, 8, 8}}, + {m68k_op_btst_8_s_pd7 , 0xffff, 0x0827, { 14, 14, 9, 9, 9}}, + {m68k_op_btst_8_s_aw , 0xffff, 0x0838, { 16, 16, 8, 8, 8}}, + {m68k_op_btst_8_s_al , 0xffff, 0x0839, { 20, 20, 8, 8, 8}}, + {m68k_op_btst_8_s_pcdi , 0xffff, 0x083a, { 16, 16, 9, 9, 9}}, + {m68k_op_btst_8_s_pcix , 0xffff, 0x083b, { 18, 18, 11, 11, 11}}, + {m68k_op_bchg_8_s_pi7 , 0xffff, 0x085f, { 16, 16, 8, 8, 8}}, + {m68k_op_bchg_8_s_pd7 , 0xffff, 0x0867, { 18, 18, 9, 9, 9}}, + {m68k_op_bchg_8_s_aw , 0xffff, 0x0878, { 20, 20, 8, 8, 8}}, + {m68k_op_bchg_8_s_al , 0xffff, 0x0879, { 24, 24, 8, 8, 8}}, + {m68k_op_bclr_8_s_pi7 , 0xffff, 0x089f, { 16, 16, 8, 8, 8}}, + {m68k_op_bclr_8_s_pd7 , 0xffff, 0x08a7, { 18, 18, 9, 9, 9}}, + {m68k_op_bclr_8_s_aw , 0xffff, 0x08b8, { 20, 20, 8, 8, 8}}, + {m68k_op_bclr_8_s_al , 0xffff, 0x08b9, { 24, 24, 8, 8, 8}}, + {m68k_op_bset_8_s_pi7 , 0xffff, 0x08df, { 16, 16, 8, 8, 8}}, + {m68k_op_bset_8_s_pd7 , 0xffff, 0x08e7, { 18, 18, 9, 9, 9}}, + {m68k_op_bset_8_s_aw , 0xffff, 0x08f8, { 20, 20, 8, 8, 8}}, + {m68k_op_bset_8_s_al , 0xffff, 0x08f9, { 24, 24, 8, 8, 8}}, + {m68k_op_eori_8_pi7 , 0xffff, 0x0a1f, { 16, 16, 8, 8, 8}}, + {m68k_op_eori_8_pd7 , 0xffff, 0x0a27, { 18, 18, 9, 9, 9}}, + {m68k_op_eori_8_aw , 0xffff, 0x0a38, { 20, 20, 8, 8, 8}}, + {m68k_op_eori_8_al , 0xffff, 0x0a39, { 24, 24, 8, 8, 8}}, + {m68k_op_eori_16_toc , 0xffff, 0x0a3c, { 20, 16, 12, 12, 12}}, + {m68k_op_eori_16_aw , 0xffff, 0x0a78, { 20, 20, 8, 8, 8}}, + {m68k_op_eori_16_al , 0xffff, 0x0a79, { 24, 24, 8, 8, 8}}, + {m68k_op_eori_16_tos , 0xffff, 0x0a7c, { 20, 16, 12, 12, 12}}, + {m68k_op_eori_32_aw , 0xffff, 0x0ab8, { 32, 32, 8, 8, 8}}, + {m68k_op_eori_32_al , 0xffff, 0x0ab9, { 36, 36, 8, 8, 8}}, + {m68k_op_cas_8_pi7 , 0xffff, 0x0adf, { 0, 0, 16, 16, 16}}, + {m68k_op_cas_8_pd7 , 0xffff, 0x0ae7, { 0, 0, 17, 17, 17}}, + {m68k_op_cas_8_aw , 0xffff, 0x0af8, { 0, 0, 16, 16, 16}}, + {m68k_op_cas_8_al , 0xffff, 0x0af9, { 0, 0, 16, 16, 16}}, + {m68k_op_cmpi_8_pi7 , 0xffff, 0x0c1f, { 12, 12, 6, 6, 6}}, + {m68k_op_cmpi_8_pd7 , 0xffff, 0x0c27, { 14, 14, 7, 7, 7}}, + {m68k_op_cmpi_8_aw , 0xffff, 0x0c38, { 16, 16, 6, 6, 6}}, + {m68k_op_cmpi_8_al , 0xffff, 0x0c39, { 20, 20, 6, 6, 6}}, + {m68k_op_cmpi_8_pcdi , 0xffff, 0x0c3a, { 0, 0, 7, 7, 7}}, + {m68k_op_cmpi_8_pcix , 0xffff, 0x0c3b, { 0, 0, 9, 9, 9}}, + {m68k_op_cmpi_16_aw , 0xffff, 0x0c78, { 16, 16, 6, 6, 6}}, + {m68k_op_cmpi_16_al , 0xffff, 0x0c79, { 20, 20, 6, 6, 6}}, + {m68k_op_cmpi_16_pcdi , 0xffff, 0x0c7a, { 0, 0, 7, 7, 7}}, + {m68k_op_cmpi_16_pcix , 0xffff, 0x0c7b, { 0, 0, 9, 9, 9}}, + {m68k_op_cmpi_32_aw , 0xffff, 0x0cb8, { 24, 24, 6, 6, 6}}, + {m68k_op_cmpi_32_al , 0xffff, 0x0cb9, { 28, 28, 6, 6, 6}}, + {m68k_op_cmpi_32_pcdi , 0xffff, 0x0cba, { 0, 0, 7, 7, 7}}, + {m68k_op_cmpi_32_pcix , 0xffff, 0x0cbb, { 0, 0, 9, 9, 9}}, + {m68k_op_cas_16_aw , 0xffff, 0x0cf8, { 0, 0, 16, 16, 16}}, + {m68k_op_cas_16_al , 0xffff, 0x0cf9, { 0, 0, 16, 16, 16}}, + {m68k_op_cas2_16 , 0xffff, 0x0cfc, { 0, 0, 12, 12, 12}}, + {m68k_op_moves_8_pi7 , 0xffff, 0x0e1f, { 0, 18, 9, 9, 9}}, + {m68k_op_moves_8_pd7 , 0xffff, 0x0e27, { 0, 20, 10, 10, 10}}, + {m68k_op_moves_8_aw , 0xffff, 0x0e38, { 0, 26, 9, 9, 9}}, + {m68k_op_moves_8_al , 0xffff, 0x0e39, { 0, 30, 9, 9, 9}}, + {m68k_op_moves_16_aw , 0xffff, 0x0e78, { 0, 26, 9, 9, 9}}, + {m68k_op_moves_16_al , 0xffff, 0x0e79, { 0, 30, 9, 9, 9}}, + {m68k_op_moves_32_aw , 0xffff, 0x0eb8, { 0, 32, 9, 9, 9}}, + {m68k_op_moves_32_al , 0xffff, 0x0eb9, { 0, 36, 9, 9, 9}}, + {m68k_op_cas_32_aw , 0xffff, 0x0ef8, { 0, 0, 16, 16, 16}}, + {m68k_op_cas_32_al , 0xffff, 0x0ef9, { 0, 0, 16, 16, 16}}, + {m68k_op_cas2_32 , 0xffff, 0x0efc, { 0, 0, 12, 12, 12}}, + {m68k_op_move_8_aw_pi7 , 0xffff, 0x11df, { 16, 16, 8, 8, 8}}, + {m68k_op_move_8_aw_pd7 , 0xffff, 0x11e7, { 18, 18, 9, 9, 9}}, + {m68k_op_move_8_aw_aw , 0xffff, 0x11f8, { 20, 20, 8, 8, 8}}, + {m68k_op_move_8_aw_al , 0xffff, 0x11f9, { 24, 24, 8, 8, 8}}, + {m68k_op_move_8_aw_pcdi , 0xffff, 0x11fa, { 20, 20, 9, 9, 9}}, + {m68k_op_move_8_aw_pcix , 0xffff, 0x11fb, { 22, 22, 11, 11, 11}}, + {m68k_op_move_8_aw_i , 0xffff, 0x11fc, { 16, 16, 6, 6, 6}}, + {m68k_op_move_8_al_pi7 , 0xffff, 0x13df, { 20, 20, 10, 10, 10}}, + {m68k_op_move_8_al_pd7 , 0xffff, 0x13e7, { 22, 22, 11, 11, 11}}, + {m68k_op_move_8_al_aw , 0xffff, 0x13f8, { 24, 24, 10, 10, 10}}, + {m68k_op_move_8_al_al , 0xffff, 0x13f9, { 28, 28, 10, 10, 10}}, + {m68k_op_move_8_al_pcdi , 0xffff, 0x13fa, { 24, 24, 11, 11, 11}}, + {m68k_op_move_8_al_pcix , 0xffff, 0x13fb, { 26, 26, 13, 13, 13}}, + {m68k_op_move_8_al_i , 0xffff, 0x13fc, { 20, 20, 8, 8, 8}}, + {m68k_op_move_8_pi7_pi7 , 0xffff, 0x1edf, { 12, 12, 8, 8, 8}}, + {m68k_op_move_8_pi7_pd7 , 0xffff, 0x1ee7, { 14, 14, 9, 9, 9}}, + {m68k_op_move_8_pi7_aw , 0xffff, 0x1ef8, { 16, 16, 8, 8, 8}}, + {m68k_op_move_8_pi7_al , 0xffff, 0x1ef9, { 20, 20, 8, 8, 8}}, + {m68k_op_move_8_pi7_pcdi , 0xffff, 0x1efa, { 16, 16, 9, 9, 9}}, + {m68k_op_move_8_pi7_pcix , 0xffff, 0x1efb, { 18, 18, 11, 11, 11}}, + {m68k_op_move_8_pi7_i , 0xffff, 0x1efc, { 12, 12, 6, 6, 6}}, + {m68k_op_move_8_pd7_pi7 , 0xffff, 0x1f1f, { 12, 12, 9, 9, 9}}, + {m68k_op_move_8_pd7_pd7 , 0xffff, 0x1f27, { 14, 14, 10, 10, 10}}, + {m68k_op_move_8_pd7_aw , 0xffff, 0x1f38, { 16, 16, 9, 9, 9}}, + {m68k_op_move_8_pd7_al , 0xffff, 0x1f39, { 20, 20, 9, 9, 9}}, + {m68k_op_move_8_pd7_pcdi , 0xffff, 0x1f3a, { 16, 16, 10, 10, 10}}, + {m68k_op_move_8_pd7_pcix , 0xffff, 0x1f3b, { 18, 18, 12, 12, 12}}, + {m68k_op_move_8_pd7_i , 0xffff, 0x1f3c, { 12, 12, 7, 7, 7}}, + {m68k_op_move_32_aw_aw , 0xffff, 0x21f8, { 28, 28, 8, 8, 8}}, + {m68k_op_move_32_aw_al , 0xffff, 0x21f9, { 32, 32, 8, 8, 8}}, + {m68k_op_move_32_aw_pcdi , 0xffff, 0x21fa, { 28, 28, 9, 9, 9}}, + {m68k_op_move_32_aw_pcix , 0xffff, 0x21fb, { 30, 30, 11, 11, 11}}, + {m68k_op_move_32_aw_i , 0xffff, 0x21fc, { 24, 24, 8, 8, 8}}, + {m68k_op_move_32_al_aw , 0xffff, 0x23f8, { 32, 32, 10, 10, 10}}, + {m68k_op_move_32_al_al , 0xffff, 0x23f9, { 36, 36, 10, 10, 10}}, + {m68k_op_move_32_al_pcdi , 0xffff, 0x23fa, { 32, 32, 11, 11, 11}}, + {m68k_op_move_32_al_pcix , 0xffff, 0x23fb, { 34, 34, 13, 13, 13}}, + {m68k_op_move_32_al_i , 0xffff, 0x23fc, { 28, 28, 10, 10, 10}}, + {m68k_op_move_16_aw_aw , 0xffff, 0x31f8, { 20, 20, 8, 8, 8}}, + {m68k_op_move_16_aw_al , 0xffff, 0x31f9, { 24, 24, 8, 8, 8}}, + {m68k_op_move_16_aw_pcdi , 0xffff, 0x31fa, { 20, 20, 9, 9, 9}}, + {m68k_op_move_16_aw_pcix , 0xffff, 0x31fb, { 22, 22, 11, 11, 11}}, + {m68k_op_move_16_aw_i , 0xffff, 0x31fc, { 16, 16, 6, 6, 6}}, + {m68k_op_move_16_al_aw , 0xffff, 0x33f8, { 24, 24, 10, 10, 10}}, + {m68k_op_move_16_al_al , 0xffff, 0x33f9, { 28, 28, 10, 10, 10}}, + {m68k_op_move_16_al_pcdi , 0xffff, 0x33fa, { 24, 24, 11, 11, 11}}, + {m68k_op_move_16_al_pcix , 0xffff, 0x33fb, { 26, 26, 13, 13, 13}}, + {m68k_op_move_16_al_i , 0xffff, 0x33fc, { 20, 20, 8, 8, 8}}, + {m68k_op_negx_8_pi7 , 0xffff, 0x401f, { 12, 12, 8, 8, 8}}, + {m68k_op_negx_8_pd7 , 0xffff, 0x4027, { 14, 14, 9, 9, 9}}, + {m68k_op_negx_8_aw , 0xffff, 0x4038, { 16, 16, 8, 8, 8}}, + {m68k_op_negx_8_al , 0xffff, 0x4039, { 20, 20, 8, 8, 8}}, + {m68k_op_negx_16_aw , 0xffff, 0x4078, { 16, 16, 8, 8, 8}}, + {m68k_op_negx_16_al , 0xffff, 0x4079, { 20, 20, 8, 8, 8}}, + {m68k_op_negx_32_aw , 0xffff, 0x40b8, { 24, 24, 8, 8, 8}}, + {m68k_op_negx_32_al , 0xffff, 0x40b9, { 28, 28, 8, 8, 8}}, + {m68k_op_move_16_frs_aw , 0xffff, 0x40f8, { 16, 16, 12, 12, 12}}, + {m68k_op_move_16_frs_al , 0xffff, 0x40f9, { 20, 20, 12, 12, 12}}, + {m68k_op_clr_8_pi7 , 0xffff, 0x421f, { 12, 8, 8, 8, 8}}, + {m68k_op_clr_8_pd7 , 0xffff, 0x4227, { 14, 10, 9, 9, 9}}, + {m68k_op_clr_8_aw , 0xffff, 0x4238, { 16, 12, 8, 8, 8}}, + {m68k_op_clr_8_al , 0xffff, 0x4239, { 20, 14, 8, 8, 8}}, + {m68k_op_clr_16_aw , 0xffff, 0x4278, { 16, 12, 8, 8, 8}}, + {m68k_op_clr_16_al , 0xffff, 0x4279, { 20, 14, 8, 8, 8}}, + {m68k_op_clr_32_aw , 0xffff, 0x42b8, { 24, 16, 8, 8, 8}}, + {m68k_op_clr_32_al , 0xffff, 0x42b9, { 28, 20, 8, 8, 8}}, + {m68k_op_move_16_frc_aw , 0xffff, 0x42f8, { 0, 16, 8, 8, 8}}, + {m68k_op_move_16_frc_al , 0xffff, 0x42f9, { 0, 20, 8, 8, 8}}, + {m68k_op_neg_8_pi7 , 0xffff, 0x441f, { 12, 12, 8, 8, 8}}, + {m68k_op_neg_8_pd7 , 0xffff, 0x4427, { 14, 14, 9, 9, 9}}, + {m68k_op_neg_8_aw , 0xffff, 0x4438, { 16, 16, 8, 8, 8}}, + {m68k_op_neg_8_al , 0xffff, 0x4439, { 20, 20, 8, 8, 8}}, + {m68k_op_neg_16_aw , 0xffff, 0x4478, { 16, 16, 8, 8, 8}}, + {m68k_op_neg_16_al , 0xffff, 0x4479, { 20, 20, 8, 8, 8}}, + {m68k_op_neg_32_aw , 0xffff, 0x44b8, { 24, 24, 8, 8, 8}}, + {m68k_op_neg_32_al , 0xffff, 0x44b9, { 28, 28, 8, 8, 8}}, + {m68k_op_move_16_toc_aw , 0xffff, 0x44f8, { 20, 20, 8, 8, 8}}, + {m68k_op_move_16_toc_al , 0xffff, 0x44f9, { 24, 24, 8, 8, 8}}, + {m68k_op_move_16_toc_pcdi , 0xffff, 0x44fa, { 20, 20, 9, 9, 9}}, + {m68k_op_move_16_toc_pcix , 0xffff, 0x44fb, { 22, 22, 11, 11, 11}}, + {m68k_op_move_16_toc_i , 0xffff, 0x44fc, { 16, 16, 6, 6, 6}}, + {m68k_op_not_8_pi7 , 0xffff, 0x461f, { 12, 12, 8, 8, 8}}, + {m68k_op_not_8_pd7 , 0xffff, 0x4627, { 14, 14, 9, 9, 9}}, + {m68k_op_not_8_aw , 0xffff, 0x4638, { 16, 16, 8, 8, 8}}, + {m68k_op_not_8_al , 0xffff, 0x4639, { 20, 20, 8, 8, 8}}, + {m68k_op_not_16_aw , 0xffff, 0x4678, { 16, 16, 8, 8, 8}}, + {m68k_op_not_16_al , 0xffff, 0x4679, { 20, 20, 8, 8, 8}}, + {m68k_op_not_32_aw , 0xffff, 0x46b8, { 24, 24, 8, 8, 8}}, + {m68k_op_not_32_al , 0xffff, 0x46b9, { 28, 28, 8, 8, 8}}, + {m68k_op_move_16_tos_aw , 0xffff, 0x46f8, { 20, 20, 12, 12, 12}}, + {m68k_op_move_16_tos_al , 0xffff, 0x46f9, { 24, 24, 12, 12, 12}}, + {m68k_op_move_16_tos_pcdi , 0xffff, 0x46fa, { 20, 20, 13, 13, 13}}, + {m68k_op_move_16_tos_pcix , 0xffff, 0x46fb, { 22, 22, 15, 15, 15}}, + {m68k_op_move_16_tos_i , 0xffff, 0x46fc, { 16, 16, 10, 10, 10}}, + {m68k_op_link_32_a7 , 0xffff, 0x480f, { 0, 0, 6, 6, 6}}, + {m68k_op_nbcd_8_pi7 , 0xffff, 0x481f, { 12, 12, 10, 10, 10}}, + {m68k_op_nbcd_8_pd7 , 0xffff, 0x4827, { 14, 14, 11, 11, 11}}, + {m68k_op_nbcd_8_aw , 0xffff, 0x4838, { 16, 16, 10, 10, 10}}, + {m68k_op_nbcd_8_al , 0xffff, 0x4839, { 20, 20, 10, 10, 10}}, + {m68k_op_pea_32_aw , 0xffff, 0x4878, { 16, 16, 9, 9, 9}}, + {m68k_op_pea_32_al , 0xffff, 0x4879, { 20, 20, 9, 9, 9}}, + {m68k_op_pea_32_pcdi , 0xffff, 0x487a, { 16, 16, 10, 10, 10}}, + {m68k_op_pea_32_pcix , 0xffff, 0x487b, { 20, 20, 12, 12, 12}}, + {m68k_op_movem_16_re_aw , 0xffff, 0x48b8, { 12, 12, 8, 8, 8}}, + {m68k_op_movem_16_re_al , 0xffff, 0x48b9, { 16, 16, 8, 8, 8}}, + {m68k_op_movem_32_re_aw , 0xffff, 0x48f8, { 12, 12, 8, 8, 8}}, + {m68k_op_movem_32_re_al , 0xffff, 0x48f9, { 16, 16, 8, 8, 8}}, + {m68k_op_tst_8_pi7 , 0xffff, 0x4a1f, { 8, 8, 6, 6, 6}}, + {m68k_op_tst_8_pd7 , 0xffff, 0x4a27, { 10, 10, 7, 7, 7}}, + {m68k_op_tst_8_aw , 0xffff, 0x4a38, { 12, 12, 6, 6, 6}}, + {m68k_op_tst_8_al , 0xffff, 0x4a39, { 16, 16, 6, 6, 6}}, + {m68k_op_tst_8_pcdi , 0xffff, 0x4a3a, { 0, 0, 7, 7, 7}}, + {m68k_op_tst_8_pcix , 0xffff, 0x4a3b, { 0, 0, 9, 9, 9}}, + {m68k_op_tst_8_i , 0xffff, 0x4a3c, { 0, 0, 6, 6, 6}}, + {m68k_op_tst_16_aw , 0xffff, 0x4a78, { 12, 12, 6, 6, 6}}, + {m68k_op_tst_16_al , 0xffff, 0x4a79, { 16, 16, 6, 6, 6}}, + {m68k_op_tst_16_pcdi , 0xffff, 0x4a7a, { 0, 0, 7, 7, 7}}, + {m68k_op_tst_16_pcix , 0xffff, 0x4a7b, { 0, 0, 9, 9, 9}}, + {m68k_op_tst_16_i , 0xffff, 0x4a7c, { 0, 0, 6, 6, 6}}, + {m68k_op_tst_32_aw , 0xffff, 0x4ab8, { 16, 16, 6, 6, 6}}, + {m68k_op_tst_32_al , 0xffff, 0x4ab9, { 20, 20, 6, 6, 6}}, + {m68k_op_tst_32_pcdi , 0xffff, 0x4aba, { 0, 0, 7, 7, 7}}, + {m68k_op_tst_32_pcix , 0xffff, 0x4abb, { 0, 0, 9, 9, 9}}, + {m68k_op_tst_32_i , 0xffff, 0x4abc, { 0, 0, 6, 6, 6}}, + {m68k_op_tas_8_pi7 , 0xffff, 0x4adf, { 18, 18, 16, 16, 16}}, + {m68k_op_tas_8_pd7 , 0xffff, 0x4ae7, { 20, 20, 17, 17, 17}}, + {m68k_op_tas_8_aw , 0xffff, 0x4af8, { 22, 22, 16, 16, 16}}, + {m68k_op_tas_8_al , 0xffff, 0x4af9, { 26, 26, 16, 16, 16}}, + {m68k_op_illegal , 0xffff, 0x4afc, { 4, 4, 4, 4, 4}}, + {m68k_op_mull_32_aw , 0xffff, 0x4c38, { 0, 0, 47, 47, 47}}, + {m68k_op_mull_32_al , 0xffff, 0x4c39, { 0, 0, 47, 47, 47}}, + {m68k_op_mull_32_pcdi , 0xffff, 0x4c3a, { 0, 0, 48, 48, 48}}, + {m68k_op_mull_32_pcix , 0xffff, 0x4c3b, { 0, 0, 50, 50, 50}}, + {m68k_op_mull_32_i , 0xffff, 0x4c3c, { 0, 0, 47, 47, 47}}, + {m68k_op_divl_32_aw , 0xffff, 0x4c78, { 0, 0, 88, 88, 88}}, + {m68k_op_divl_32_al , 0xffff, 0x4c79, { 0, 0, 88, 88, 88}}, + {m68k_op_divl_32_pcdi , 0xffff, 0x4c7a, { 0, 0, 89, 89, 89}}, + {m68k_op_divl_32_pcix , 0xffff, 0x4c7b, { 0, 0, 91, 91, 91}}, + {m68k_op_divl_32_i , 0xffff, 0x4c7c, { 0, 0, 88, 88, 88}}, + {m68k_op_movem_16_er_aw , 0xffff, 0x4cb8, { 16, 16, 12, 12, 12}}, + {m68k_op_movem_16_er_al , 0xffff, 0x4cb9, { 20, 20, 12, 12, 12}}, + {m68k_op_movem_16_er_pcdi , 0xffff, 0x4cba, { 16, 16, 9, 9, 9}}, + {m68k_op_movem_16_er_pcix , 0xffff, 0x4cbb, { 18, 18, 11, 11, 11}}, + {m68k_op_movem_32_er_aw , 0xffff, 0x4cf8, { 16, 16, 12, 12, 12}}, + {m68k_op_movem_32_er_al , 0xffff, 0x4cf9, { 20, 20, 12, 12, 12}}, + {m68k_op_movem_32_er_pcdi , 0xffff, 0x4cfa, { 16, 16, 9, 9, 9}}, + {m68k_op_movem_32_er_pcix , 0xffff, 0x4cfb, { 18, 18, 11, 11, 11}}, + {m68k_op_link_16_a7 , 0xffff, 0x4e57, { 16, 16, 5, 5, 5}}, + {m68k_op_unlk_32_a7 , 0xffff, 0x4e5f, { 12, 12, 6, 6, 6}}, + {m68k_op_reset , 0xffff, 0x4e70, { 0, 0, 0, 0, 0}}, + {m68k_op_nop , 0xffff, 0x4e71, { 4, 4, 2, 2, 2}}, + {m68k_op_stop , 0xffff, 0x4e72, { 4, 4, 8, 8, 8}}, + {m68k_op_rte_32 , 0xffff, 0x4e73, { 20, 24, 20, 20, 20}}, + {m68k_op_rtd_32 , 0xffff, 0x4e74, { 0, 16, 10, 10, 10}}, + {m68k_op_rts_32 , 0xffff, 0x4e75, { 16, 16, 10, 10, 10}}, + {m68k_op_trapv , 0xffff, 0x4e76, { 4, 4, 4, 4, 4}}, + {m68k_op_rtr_32 , 0xffff, 0x4e77, { 20, 20, 14, 14, 14}}, + {m68k_op_movec_32_cr , 0xffff, 0x4e7a, { 0, 12, 6, 6, 6}}, + {m68k_op_movec_32_rc , 0xffff, 0x4e7b, { 0, 10, 12, 12, 12}}, + {m68k_op_jsr_32_aw , 0xffff, 0x4eb8, { 18, 18, 4, 4, 4}}, + {m68k_op_jsr_32_al , 0xffff, 0x4eb9, { 20, 20, 4, 4, 4}}, + {m68k_op_jsr_32_pcdi , 0xffff, 0x4eba, { 18, 18, 5, 5, 5}}, + {m68k_op_jsr_32_pcix , 0xffff, 0x4ebb, { 22, 22, 7, 7, 7}}, + {m68k_op_jmp_32_aw , 0xffff, 0x4ef8, { 10, 10, 4, 4, 4}}, + {m68k_op_jmp_32_al , 0xffff, 0x4ef9, { 12, 12, 4, 4, 4}}, + {m68k_op_jmp_32_pcdi , 0xffff, 0x4efa, { 10, 10, 5, 5, 5}}, + {m68k_op_jmp_32_pcix , 0xffff, 0x4efb, { 14, 14, 7, 7, 7}}, + {m68k_op_st_8_pi7 , 0xffff, 0x50df, { 12, 12, 10, 10, 10}}, + {m68k_op_st_8_pd7 , 0xffff, 0x50e7, { 14, 14, 11, 11, 11}}, + {m68k_op_st_8_aw , 0xffff, 0x50f8, { 16, 16, 10, 10, 10}}, + {m68k_op_st_8_al , 0xffff, 0x50f9, { 20, 20, 10, 10, 10}}, + {m68k_op_trapt_16 , 0xffff, 0x50fa, { 0, 0, 6, 6, 6}}, + {m68k_op_trapt_32 , 0xffff, 0x50fb, { 0, 0, 8, 8, 8}}, + {m68k_op_trapt , 0xffff, 0x50fc, { 0, 0, 4, 4, 4}}, + {m68k_op_sf_8_pi7 , 0xffff, 0x51df, { 12, 12, 10, 10, 10}}, + {m68k_op_sf_8_pd7 , 0xffff, 0x51e7, { 14, 14, 11, 11, 11}}, + {m68k_op_sf_8_aw , 0xffff, 0x51f8, { 16, 16, 10, 10, 10}}, + {m68k_op_sf_8_al , 0xffff, 0x51f9, { 20, 20, 10, 10, 10}}, + {m68k_op_trapf_16 , 0xffff, 0x51fa, { 0, 0, 6, 6, 6}}, + {m68k_op_trapf_32 , 0xffff, 0x51fb, { 0, 0, 8, 8, 8}}, + {m68k_op_trapf , 0xffff, 0x51fc, { 0, 0, 4, 4, 4}}, + {m68k_op_shi_8_pi7 , 0xffff, 0x52df, { 12, 12, 10, 10, 10}}, + {m68k_op_shi_8_pd7 , 0xffff, 0x52e7, { 14, 14, 11, 11, 11}}, + {m68k_op_shi_8_aw , 0xffff, 0x52f8, { 16, 16, 10, 10, 10}}, + {m68k_op_shi_8_al , 0xffff, 0x52f9, { 20, 20, 10, 10, 10}}, + {m68k_op_traphi_16 , 0xffff, 0x52fa, { 0, 0, 6, 6, 6}}, + {m68k_op_traphi_32 , 0xffff, 0x52fb, { 0, 0, 8, 8, 8}}, + {m68k_op_traphi , 0xffff, 0x52fc, { 0, 0, 4, 4, 4}}, + {m68k_op_sls_8_pi7 , 0xffff, 0x53df, { 12, 12, 10, 10, 10}}, + {m68k_op_sls_8_pd7 , 0xffff, 0x53e7, { 14, 14, 11, 11, 11}}, + {m68k_op_sls_8_aw , 0xffff, 0x53f8, { 16, 16, 10, 10, 10}}, + {m68k_op_sls_8_al , 0xffff, 0x53f9, { 20, 20, 10, 10, 10}}, + {m68k_op_trapls_16 , 0xffff, 0x53fa, { 0, 0, 6, 6, 6}}, + {m68k_op_trapls_32 , 0xffff, 0x53fb, { 0, 0, 8, 8, 8}}, + {m68k_op_trapls , 0xffff, 0x53fc, { 0, 0, 4, 4, 4}}, + {m68k_op_scc_8_pi7 , 0xffff, 0x54df, { 12, 12, 10, 10, 10}}, + {m68k_op_scc_8_pd7 , 0xffff, 0x54e7, { 14, 14, 11, 11, 11}}, + {m68k_op_scc_8_aw , 0xffff, 0x54f8, { 16, 16, 10, 10, 10}}, + {m68k_op_scc_8_al , 0xffff, 0x54f9, { 20, 20, 10, 10, 10}}, + {m68k_op_trapcc_16 , 0xffff, 0x54fa, { 0, 0, 6, 6, 6}}, + {m68k_op_trapcc_32 , 0xffff, 0x54fb, { 0, 0, 8, 8, 8}}, + {m68k_op_trapcc , 0xffff, 0x54fc, { 0, 0, 4, 4, 4}}, + {m68k_op_scs_8_pi7 , 0xffff, 0x55df, { 12, 12, 10, 10, 10}}, + {m68k_op_scs_8_pd7 , 0xffff, 0x55e7, { 14, 14, 11, 11, 11}}, + {m68k_op_scs_8_aw , 0xffff, 0x55f8, { 16, 16, 10, 10, 10}}, + {m68k_op_scs_8_al , 0xffff, 0x55f9, { 20, 20, 10, 10, 10}}, + {m68k_op_trapcs_16 , 0xffff, 0x55fa, { 0, 0, 6, 6, 6}}, + {m68k_op_trapcs_32 , 0xffff, 0x55fb, { 0, 0, 8, 8, 8}}, + {m68k_op_trapcs , 0xffff, 0x55fc, { 0, 0, 4, 4, 4}}, + {m68k_op_sne_8_pi7 , 0xffff, 0x56df, { 12, 12, 10, 10, 10}}, + {m68k_op_sne_8_pd7 , 0xffff, 0x56e7, { 14, 14, 11, 11, 11}}, + {m68k_op_sne_8_aw , 0xffff, 0x56f8, { 16, 16, 10, 10, 10}}, + {m68k_op_sne_8_al , 0xffff, 0x56f9, { 20, 20, 10, 10, 10}}, + {m68k_op_trapne_16 , 0xffff, 0x56fa, { 0, 0, 6, 6, 6}}, + {m68k_op_trapne_32 , 0xffff, 0x56fb, { 0, 0, 8, 8, 8}}, + {m68k_op_trapne , 0xffff, 0x56fc, { 0, 0, 4, 4, 4}}, + {m68k_op_seq_8_pi7 , 0xffff, 0x57df, { 12, 12, 10, 10, 10}}, + {m68k_op_seq_8_pd7 , 0xffff, 0x57e7, { 14, 14, 11, 11, 11}}, + {m68k_op_seq_8_aw , 0xffff, 0x57f8, { 16, 16, 10, 10, 10}}, + {m68k_op_seq_8_al , 0xffff, 0x57f9, { 20, 20, 10, 10, 10}}, + {m68k_op_trapeq_16 , 0xffff, 0x57fa, { 0, 0, 6, 6, 6}}, + {m68k_op_trapeq_32 , 0xffff, 0x57fb, { 0, 0, 8, 8, 8}}, + {m68k_op_trapeq , 0xffff, 0x57fc, { 0, 0, 4, 4, 4}}, + {m68k_op_svc_8_pi7 , 0xffff, 0x58df, { 12, 12, 10, 10, 10}}, + {m68k_op_svc_8_pd7 , 0xffff, 0x58e7, { 14, 14, 11, 11, 11}}, + {m68k_op_svc_8_aw , 0xffff, 0x58f8, { 16, 16, 10, 10, 10}}, + {m68k_op_svc_8_al , 0xffff, 0x58f9, { 20, 20, 10, 10, 10}}, + {m68k_op_trapvc_16 , 0xffff, 0x58fa, { 0, 0, 6, 6, 6}}, + {m68k_op_trapvc_32 , 0xffff, 0x58fb, { 0, 0, 8, 8, 8}}, + {m68k_op_trapvc , 0xffff, 0x58fc, { 0, 0, 4, 4, 4}}, + {m68k_op_svs_8_pi7 , 0xffff, 0x59df, { 12, 12, 10, 10, 10}}, + {m68k_op_svs_8_pd7 , 0xffff, 0x59e7, { 14, 14, 11, 11, 11}}, + {m68k_op_svs_8_aw , 0xffff, 0x59f8, { 16, 16, 10, 10, 10}}, + {m68k_op_svs_8_al , 0xffff, 0x59f9, { 20, 20, 10, 10, 10}}, + {m68k_op_trapvs_16 , 0xffff, 0x59fa, { 0, 0, 6, 6, 6}}, + {m68k_op_trapvs_32 , 0xffff, 0x59fb, { 0, 0, 8, 8, 8}}, + {m68k_op_trapvs , 0xffff, 0x59fc, { 0, 0, 4, 4, 4}}, + {m68k_op_spl_8_pi7 , 0xffff, 0x5adf, { 12, 12, 10, 10, 10}}, + {m68k_op_spl_8_pd7 , 0xffff, 0x5ae7, { 14, 14, 11, 11, 11}}, + {m68k_op_spl_8_aw , 0xffff, 0x5af8, { 16, 16, 10, 10, 10}}, + {m68k_op_spl_8_al , 0xffff, 0x5af9, { 20, 20, 10, 10, 10}}, + {m68k_op_trappl_16 , 0xffff, 0x5afa, { 0, 0, 6, 6, 6}}, + {m68k_op_trappl_32 , 0xffff, 0x5afb, { 0, 0, 8, 8, 8}}, + {m68k_op_trappl , 0xffff, 0x5afc, { 0, 0, 4, 4, 4}}, + {m68k_op_smi_8_pi7 , 0xffff, 0x5bdf, { 12, 12, 10, 10, 10}}, + {m68k_op_smi_8_pd7 , 0xffff, 0x5be7, { 14, 14, 11, 11, 11}}, + {m68k_op_smi_8_aw , 0xffff, 0x5bf8, { 16, 16, 10, 10, 10}}, + {m68k_op_smi_8_al , 0xffff, 0x5bf9, { 20, 20, 10, 10, 10}}, + {m68k_op_trapmi_16 , 0xffff, 0x5bfa, { 0, 0, 6, 6, 6}}, + {m68k_op_trapmi_32 , 0xffff, 0x5bfb, { 0, 0, 8, 8, 8}}, + {m68k_op_trapmi , 0xffff, 0x5bfc, { 0, 0, 4, 4, 4}}, + {m68k_op_sge_8_pi7 , 0xffff, 0x5cdf, { 12, 12, 10, 10, 10}}, + {m68k_op_sge_8_pd7 , 0xffff, 0x5ce7, { 14, 14, 11, 11, 11}}, + {m68k_op_sge_8_aw , 0xffff, 0x5cf8, { 16, 16, 10, 10, 10}}, + {m68k_op_sge_8_al , 0xffff, 0x5cf9, { 20, 20, 10, 10, 10}}, + {m68k_op_trapge_16 , 0xffff, 0x5cfa, { 0, 0, 6, 6, 6}}, + {m68k_op_trapge_32 , 0xffff, 0x5cfb, { 0, 0, 8, 8, 8}}, + {m68k_op_trapge , 0xffff, 0x5cfc, { 0, 0, 4, 4, 4}}, + {m68k_op_slt_8_pi7 , 0xffff, 0x5ddf, { 12, 12, 10, 10, 10}}, + {m68k_op_slt_8_pd7 , 0xffff, 0x5de7, { 14, 14, 11, 11, 11}}, + {m68k_op_slt_8_aw , 0xffff, 0x5df8, { 16, 16, 10, 10, 10}}, + {m68k_op_slt_8_al , 0xffff, 0x5df9, { 20, 20, 10, 10, 10}}, + {m68k_op_traplt_16 , 0xffff, 0x5dfa, { 0, 0, 6, 6, 6}}, + {m68k_op_traplt_32 , 0xffff, 0x5dfb, { 0, 0, 8, 8, 8}}, + {m68k_op_traplt , 0xffff, 0x5dfc, { 0, 0, 4, 4, 4}}, + {m68k_op_sgt_8_pi7 , 0xffff, 0x5edf, { 12, 12, 10, 10, 10}}, + {m68k_op_sgt_8_pd7 , 0xffff, 0x5ee7, { 14, 14, 11, 11, 11}}, + {m68k_op_sgt_8_aw , 0xffff, 0x5ef8, { 16, 16, 10, 10, 10}}, + {m68k_op_sgt_8_al , 0xffff, 0x5ef9, { 20, 20, 10, 10, 10}}, + {m68k_op_trapgt_16 , 0xffff, 0x5efa, { 0, 0, 6, 6, 6}}, + {m68k_op_trapgt_32 , 0xffff, 0x5efb, { 0, 0, 8, 8, 8}}, + {m68k_op_trapgt , 0xffff, 0x5efc, { 0, 0, 4, 4, 4}}, + {m68k_op_sle_8_pi7 , 0xffff, 0x5fdf, { 12, 12, 10, 10, 10}}, + {m68k_op_sle_8_pd7 , 0xffff, 0x5fe7, { 14, 14, 11, 11, 11}}, + {m68k_op_sle_8_aw , 0xffff, 0x5ff8, { 16, 16, 10, 10, 10}}, + {m68k_op_sle_8_al , 0xffff, 0x5ff9, { 20, 20, 10, 10, 10}}, + {m68k_op_traple_16 , 0xffff, 0x5ffa, { 0, 0, 6, 6, 6}}, + {m68k_op_traple_32 , 0xffff, 0x5ffb, { 0, 0, 8, 8, 8}}, + {m68k_op_traple , 0xffff, 0x5ffc, { 0, 0, 4, 4, 4}}, + {m68k_op_bra_16 , 0xffff, 0x6000, { 10, 10, 10, 10, 10}}, + {m68k_op_bra_32 , 0xffff, 0x60ff, { 10, 10, 10, 10, 10}}, + {m68k_op_bsr_16 , 0xffff, 0x6100, { 18, 18, 7, 7, 7}}, + {m68k_op_bsr_32 , 0xffff, 0x61ff, { 18, 18, 7, 7, 7}}, + {m68k_op_bhi_16 , 0xffff, 0x6200, { 10, 10, 6, 6, 6}}, + {m68k_op_bhi_32 , 0xffff, 0x62ff, { 10, 10, 6, 6, 6}}, + {m68k_op_bls_16 , 0xffff, 0x6300, { 10, 10, 6, 6, 6}}, + {m68k_op_bls_32 , 0xffff, 0x63ff, { 10, 10, 6, 6, 6}}, + {m68k_op_bcc_16 , 0xffff, 0x6400, { 10, 10, 6, 6, 6}}, + {m68k_op_bcc_32 , 0xffff, 0x64ff, { 10, 10, 6, 6, 6}}, + {m68k_op_bcs_16 , 0xffff, 0x6500, { 10, 10, 6, 6, 6}}, + {m68k_op_bcs_32 , 0xffff, 0x65ff, { 10, 10, 6, 6, 6}}, + {m68k_op_bne_16 , 0xffff, 0x6600, { 10, 10, 6, 6, 6}}, + {m68k_op_bne_32 , 0xffff, 0x66ff, { 10, 10, 6, 6, 6}}, + {m68k_op_beq_16 , 0xffff, 0x6700, { 10, 10, 6, 6, 6}}, + {m68k_op_beq_32 , 0xffff, 0x67ff, { 10, 10, 6, 6, 6}}, + {m68k_op_bvc_16 , 0xffff, 0x6800, { 10, 10, 6, 6, 6}}, + {m68k_op_bvc_32 , 0xffff, 0x68ff, { 10, 10, 6, 6, 6}}, + {m68k_op_bvs_16 , 0xffff, 0x6900, { 10, 10, 6, 6, 6}}, + {m68k_op_bvs_32 , 0xffff, 0x69ff, { 10, 10, 6, 6, 6}}, + {m68k_op_bpl_16 , 0xffff, 0x6a00, { 10, 10, 6, 6, 6}}, + {m68k_op_bpl_32 , 0xffff, 0x6aff, { 10, 10, 6, 6, 6}}, + {m68k_op_bmi_16 , 0xffff, 0x6b00, { 10, 10, 6, 6, 6}}, + {m68k_op_bmi_32 , 0xffff, 0x6bff, { 10, 10, 6, 6, 6}}, + {m68k_op_bge_16 , 0xffff, 0x6c00, { 10, 10, 6, 6, 6}}, + {m68k_op_bge_32 , 0xffff, 0x6cff, { 10, 10, 6, 6, 6}}, + {m68k_op_blt_16 , 0xffff, 0x6d00, { 10, 10, 6, 6, 6}}, + {m68k_op_blt_32 , 0xffff, 0x6dff, { 10, 10, 6, 6, 6}}, + {m68k_op_bgt_16 , 0xffff, 0x6e00, { 10, 10, 6, 6, 6}}, + {m68k_op_bgt_32 , 0xffff, 0x6eff, { 10, 10, 6, 6, 6}}, + {m68k_op_ble_16 , 0xffff, 0x6f00, { 10, 10, 6, 6, 6}}, + {m68k_op_ble_32 , 0xffff, 0x6fff, { 10, 10, 6, 6, 6}}, + {m68k_op_sbcd_8_mm_axy7 , 0xffff, 0x8f0f, { 18, 18, 16, 16, 16}}, + {m68k_op_pack_16_mm_axy7 , 0xffff, 0x8f4f, { 0, 0, 13, 13, 13}}, + {m68k_op_unpk_16_mm_axy7 , 0xffff, 0x8f8f, { 0, 0, 13, 13, 13}}, + {m68k_op_subx_8_mm_axy7 , 0xffff, 0x9f0f, { 18, 18, 12, 12, 12}}, + {m68k_op_cmpm_8_axy7 , 0xffff, 0xbf0f, { 12, 12, 9, 9, 9}}, + {m68k_op_abcd_8_mm_axy7 , 0xffff, 0xcf0f, { 18, 18, 16, 16, 16}}, + {m68k_op_addx_8_mm_axy7 , 0xffff, 0xdf0f, { 18, 18, 12, 12, 12}}, + {m68k_op_asr_16_aw , 0xffff, 0xe0f8, { 16, 16, 9, 9, 9}}, + {m68k_op_asr_16_al , 0xffff, 0xe0f9, { 20, 20, 9, 9, 9}}, + {m68k_op_asl_16_aw , 0xffff, 0xe1f8, { 16, 16, 10, 10, 10}}, + {m68k_op_asl_16_al , 0xffff, 0xe1f9, { 20, 20, 10, 10, 10}}, + {m68k_op_lsr_16_aw , 0xffff, 0xe2f8, { 16, 16, 9, 9, 9}}, + {m68k_op_lsr_16_al , 0xffff, 0xe2f9, { 20, 20, 9, 9, 9}}, + {m68k_op_lsl_16_aw , 0xffff, 0xe3f8, { 16, 16, 9, 9, 9}}, + {m68k_op_lsl_16_al , 0xffff, 0xe3f9, { 20, 20, 9, 9, 9}}, + {m68k_op_roxr_16_aw , 0xffff, 0xe4f8, { 16, 16, 9, 9, 9}}, + {m68k_op_roxr_16_al , 0xffff, 0xe4f9, { 20, 20, 9, 9, 9}}, + {m68k_op_roxl_16_aw , 0xffff, 0xe5f8, { 16, 16, 9, 9, 9}}, + {m68k_op_roxl_16_al , 0xffff, 0xe5f9, { 20, 20, 9, 9, 9}}, + {m68k_op_ror_16_aw , 0xffff, 0xe6f8, { 16, 16, 11, 11, 11}}, + {m68k_op_ror_16_al , 0xffff, 0xe6f9, { 20, 20, 11, 11, 11}}, + {m68k_op_rol_16_aw , 0xffff, 0xe7f8, { 16, 16, 11, 11, 11}}, + {m68k_op_rol_16_al , 0xffff, 0xe7f9, { 20, 20, 11, 11, 11}}, + {m68k_op_bftst_32_aw , 0xffff, 0xe8f8, { 0, 0, 17, 17, 17}}, + {m68k_op_bftst_32_al , 0xffff, 0xe8f9, { 0, 0, 17, 17, 17}}, + {m68k_op_bftst_32_pcdi , 0xffff, 0xe8fa, { 0, 0, 18, 18, 18}}, + {m68k_op_bftst_32_pcix , 0xffff, 0xe8fb, { 0, 0, 20, 20, 20}}, + {m68k_op_bfextu_32_aw , 0xffff, 0xe9f8, { 0, 0, 19, 19, 19}}, + {m68k_op_bfextu_32_al , 0xffff, 0xe9f9, { 0, 0, 19, 19, 19}}, + {m68k_op_bfextu_32_pcdi , 0xffff, 0xe9fa, { 0, 0, 20, 20, 20}}, + {m68k_op_bfextu_32_pcix , 0xffff, 0xe9fb, { 0, 0, 22, 22, 22}}, + {m68k_op_bfchg_32_aw , 0xffff, 0xeaf8, { 0, 0, 24, 24, 24}}, + {m68k_op_bfchg_32_al , 0xffff, 0xeaf9, { 0, 0, 24, 24, 24}}, + {m68k_op_bfexts_32_aw , 0xffff, 0xebf8, { 0, 0, 19, 19, 19}}, + {m68k_op_bfexts_32_al , 0xffff, 0xebf9, { 0, 0, 19, 19, 19}}, + {m68k_op_bfexts_32_pcdi , 0xffff, 0xebfa, { 0, 0, 20, 20, 20}}, + {m68k_op_bfexts_32_pcix , 0xffff, 0xebfb, { 0, 0, 22, 22, 22}}, + {m68k_op_bfclr_32_aw , 0xffff, 0xecf8, { 0, 0, 24, 24, 24}}, + {m68k_op_bfclr_32_al , 0xffff, 0xecf9, { 0, 0, 24, 24, 24}}, + {m68k_op_bfffo_32_aw , 0xffff, 0xedf8, { 0, 0, 32, 32, 32}}, + {m68k_op_bfffo_32_al , 0xffff, 0xedf9, { 0, 0, 32, 32, 32}}, + {m68k_op_bfffo_32_pcdi , 0xffff, 0xedfa, { 0, 0, 33, 33, 33}}, + {m68k_op_bfffo_32_pcix , 0xffff, 0xedfb, { 0, 0, 35, 35, 35}}, + {m68k_op_bfset_32_aw , 0xffff, 0xeef8, { 0, 0, 24, 24, 24}}, + {m68k_op_bfset_32_al , 0xffff, 0xeef9, { 0, 0, 24, 24, 24}}, + {m68k_op_bfins_32_aw , 0xffff, 0xeff8, { 0, 0, 21, 21, 21}}, + {m68k_op_bfins_32_al , 0xffff, 0xeff9, { 0, 0, 21, 21, 21}}, + {m68k_op_pflush_32 , 0xffff, 0xf518, { 0, 0, 0, 0, 4}}, + {0, 0, 0, {0, 0, 0, 0, 0}} +}; + + +/* Build the opcode handler jump table */ +void m68ki_build_opcode_table(void) +{ + const opcode_handler_struct *ostruct; + int instr; + int i; + int j; + int k; + + for(i = 0; i < 0x10000; i++) + { + /* default to illegal */ + m68ki_instruction_jump_table[i] = m68k_op_illegal; + for(k=0;kmask != 0xff00) + { + for(i = 0;i < 0x10000;i++) + { + if((i & ostruct->mask) == ostruct->match) + { + m68ki_instruction_jump_table[i] = ostruct->opcode_handler; + for(k=0;kcycles[k]; + } + } + ostruct++; + } + while(ostruct->mask == 0xff00) + { + for(i = 0;i <= 0xff;i++) + { + m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler; + for(k=0;kmatch | i] = ostruct->cycles[k]; + } + ostruct++; + } + while(ostruct->mask == 0xf1f8) + { + for(i = 0;i < 8;i++) + { + for(j = 0;j < 8;j++) + { + instr = ostruct->match | (i << 9) | j; + m68ki_instruction_jump_table[instr] = ostruct->opcode_handler; + for(k=0;kcycles[k]; + } + } + ostruct++; + } + while(ostruct->mask == 0xfff0) + { + for(i = 0;i <= 0x0f;i++) + { + m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler; + for(k=0;kmatch | i] = ostruct->cycles[k]; + } + ostruct++; + } + while(ostruct->mask == 0xf1ff) + { + for(i = 0;i <= 0x07;i++) + { + m68ki_instruction_jump_table[ostruct->match | (i << 9)] = ostruct->opcode_handler; + for(k=0;kmatch | (i << 9)] = ostruct->cycles[k]; + } + ostruct++; + } + while(ostruct->mask == 0xfff8) + { + for(i = 0;i <= 0x07;i++) + { + m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler; + for(k=0;kmatch | i] = ostruct->cycles[k]; + } + ostruct++; + } + while(ostruct->mask == 0xffff) + { + m68ki_instruction_jump_table[ostruct->match] = ostruct->opcode_handler; + for(k=0;kmatch] = ostruct->cycles[k]; + ostruct++; + } +} + + +/* ======================================================================== */ +/* ============================== END OF FILE ============================= */ +/* ======================================================================== */ + + diff --git a/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/m68k/m68kops.h b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/m68k/m68kops.h new file mode 100644 index 000000000..3fa317dd2 --- /dev/null +++ b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/m68k/m68kops.h @@ -0,0 +1,22 @@ +#ifndef M68KOPS__HEADER +#define M68KOPS__HEADER + +/* ======================================================================== */ +/* ============================ OPCODE HANDLERS =========================== */ +/* ======================================================================== */ + + +/* Build the opcode handler table */ +void m68ki_build_opcode_table(void); + +extern void (*m68ki_instruction_jump_table[0x10000])(m68ki_cpu_core *m68k); /* opcode handler jump table */ +extern unsigned char m68ki_cycles[][0x10000]; + + +/* ======================================================================== */ +/* ============================== END OF FILE ============================= */ +/* ======================================================================== */ + +#endif /* M68KOPS__HEADER */ + + diff --git a/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/m68k/macros.h b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/m68k/macros.h new file mode 100644 index 000000000..70fb1814a --- /dev/null +++ b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/m68k/macros.h @@ -0,0 +1,57 @@ +#ifndef _MACROS_H_ +#define _MACROS_H_ + +#ifdef LSB_FIRST + +#define READ_BYTE(BASE, ADDR) (BASE)[(ADDR)^1] + +#define READ_WORD(BASE, ADDR) (((BASE)[ADDR]<<8) | (BASE)[(ADDR)+1]) + +#define READ_WORD_LONG(BASE, ADDR) (((BASE)[(ADDR)+1]<<24) | \ + ((BASE)[(ADDR)]<<16) | \ + ((BASE)[(ADDR)+3]<<8) | \ + (BASE)[(ADDR)+2]) + +#define WRITE_BYTE(BASE, ADDR, VAL) (BASE)[(ADDR)^1] = (VAL)&0xff + +#define WRITE_WORD(BASE, ADDR, VAL) (BASE)[ADDR] = ((VAL)>>8) & 0xff; \ + (BASE)[(ADDR)+1] = (VAL)&0xff + +#define WRITE_WORD_LONG(BASE, ADDR, VAL) (BASE)[(ADDR+1)] = ((VAL)>>24) & 0xff; \ + (BASE)[(ADDR)] = ((VAL)>>16)&0xff; \ + (BASE)[(ADDR+3)] = ((VAL)>>8)&0xff; \ + (BASE)[(ADDR+2)] = (VAL)&0xff + +#else + +#define READ_BYTE(BASE, ADDR) (BASE)[ADDR] +#define READ_WORD(BASE, ADDR) *(uint16 *)((BASE) + (ADDR)) +#define READ_WORD_LONG(BASE, ADDR) *(uint32 *)((BASE) + (ADDR)) +#define WRITE_BYTE(BASE, ADDR, VAL) (BASE)[ADDR] = VAL & 0xff +#define WRITE_WORD(BASE, ADDR, VAL) *(uint16 *)((BASE) + (ADDR)) = VAL & 0xffff +#define WRITE_WORD_LONG(BASE, ADDR, VAL) *(uint32 *)((BASE) + (ADDR)) = VAL & 0xffffffff +#endif + +/* C89 compatibility */ +#ifndef M_PI +#define M_PI 3.14159265358979323846264338327f +#endif /* M_PI */ + +/* Set to your compiler's static inline keyword to enable it, or + * set it to blank to disable it. + * If you define INLINE in the makefile, it will override this value. + * NOTE: not enabling inline functions will SEVERELY slow down emulation. + */ +#ifndef INLINE +#ifndef _DEBUG +#define INLINE static __inline +#else +#define INLINE static +#endif +#endif /* INLINE */ + +#define BOOL unsigned char +#define FALSE 0 +#define TRUE 1 + +#endif /* _MACROS_H_ */ diff --git a/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/m68k/readme.txt b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/m68k/readme.txt new file mode 100644 index 000000000..91549011e --- /dev/null +++ b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/m68k/readme.txt @@ -0,0 +1,315 @@ + MUSASHI + ======= + + Version 3.3 + + A portable Motorola M680x0 processor emulation engine. + Copyright 1998-2001 Karl Stenerud. All rights reserved. + + + +INTRODUCTION: +------------ + +Musashi is a Motorola 68000, 68010, 68EC020, and 68020 emulator written in C. +This emulator was written with two goals in mind: portability and speed. + +The emulator is written to ANSI C specifications with the exception that I use +inline functions. This is not compliant to the ANSI spec, but will be +compliant to the ANSI C9X spec. + +It has been successfully running in the MAME project (www.mame.net) for over 2 +years and so has had time to mature. + + + +LICENSE AND COPYRIGHT: +--------------------- + +The Musashi M680x0 emulator is copyright 1998-2001 Karl Stenerud. + +The source code included in this archive is provided AS-IS, free for any +non-commercial purpose. + +If you build a program using this core, please give credit to the author. + +If you wish to use this core in a commercial environment, please contact +the author to discuss commercial licensing. + + + +AVAILABILITY: +------------ +The latest version of this code can be obtained at: +http://kstenerud.cjb.net + + + +CONTACTING THE AUTHOR: +--------------------- +I can be reached at kstenerud@mame.net + + + +BASIC CONFIGURATION: +------------------- +The basic configuration will give you a standard 68000 that has sufficient +functionality to work in a primitive environment. + +This setup assumes that you only have 1 device interrupting it, that the +device will always request an autovectored interrupt, and it will always clear +the interrupt before the interrupt service routine finishes (but could +possibly re-assert the interrupt). +You will have only one address space, no tracing, and no instruction prefetch. + +To implement the basic configuration: + +- Open m68kconf.h and verify that the settings for INLINE and DECL_SPEC will + work with your compiler. (They are set for gcc) + +- In your host program, implement the following functions: + unsigned int m68k_read_memory_8(unsigned int address); + unsigned int m68k_read_memory_16(unsigned int address); + unsigned int m68k_read_memory_32(unsigned int address); + void m68k_write_memory_8(unsigned int address, unsigned int value); + void m68k_write_memory_16(unsigned int address, unsigned int value); + void m68k_write_memory_32(unsigned int address, unsigned int value); + +- In your host program, be sure to call m68k_pulse_reset() once before calling + any of the other functions as this initializes the core. + +- Use m68k_execute() to execute instructions and m68k_set_irq() to cause an + interrupt. + + + +ADDING PROPER INTERRUPT HANDLING: +-------------------------------- +The interrupt handling in the basic configuration doesn't emulate the +interrupt acknowledge phase of the CPU and automatically clears an interrupt +request during interrupt processing. +While this works for most systems, you may need more accurate interrupt +handling. + +To add proper interrupt handling: + +- In m68kconf.h, set M68K_EMULATE_INT_ACK to OPT_SPECIFY_HANDLER + +- In m68kconf.h, set M68K_INT_ACK_CALLBACK(A) to your interrupt acknowledge + routine + +- Your interrupt acknowledge routine must return an interrupt vector, + M68K_INT_ACK_AUTOVECTOR, or M68K_INT_ACK_SPURIOUS. most m68k + implementations just use autovectored interrupts. + +- When the interrupting device is satisfied, you must call m68k_set_irq(0) to + remove the interrupt request. + + + +MULTIPLE INTERRUPTS: +------------------- +The above system will work if you have only one device interrupting the CPU, +but if you have more than one device, you must do a bit more. + +To add multiple interrupts: + +- You must make an interrupt arbitration device that will take the highest + priority interrupt and encode it onto the IRQ pins on the CPU. + +- The interrupt arbitration device should use m68k_set_irq() to set the + highest pending interrupt, or 0 for no interrupts pending. + + + +SEPARATE IMMEDIATE AND PC-RELATIVE READS: +---------------------------------------- +You can write faster memory access functions if you know whether you are +fetching from ROM or RAM. Immediate reads are always from the program space +(Always in ROM unless it is running self-modifying code). +This will also separate the pc-relative reads, since some systems treat +PROGRAM mode reads and DATA mode reads differently (for program encryption, +for instance). See the section below (ADDRESS SPACE) for an explanation of +PROGRAM and DATA mode. + +To enable separate reads: + +- In m68kconf.h, turn on M68K_SEPARATE_READS. + +- In your host program, implement the following functions: + unsigned int m68k_read_immediate_16(unsigned int address); + unsigned int m68k_read_immediate_32(unsigned int address); + + unsigned int m68k_read_pcrelative_8(unsigned int address); + unsigned int m68k_read_pcrelative_16(unsigned int address); + unsigned int m68k_read_pcrelative_32(unsigned int address); + +- If you need to know the current PC (for banking and such), set + M68K_MONITOR_PC to OPT_SPECIFY_HANDLER, and set M68K_SET_PC_CALLBACK(A) to + your routine. + + + +ADDRESS SPACES: +-------------- +Most systems will only implement one address space, placing ROM at the lower +addresses and RAM at the higher. However, there is the possibility that a +system will implement ROM and RAM in the same address range, but in different +address spaces, or will have different mamory types that require different +handling for the program and the data. + +The 68k accomodates this by allowing different program spaces, the most +important to us being PROGRAM and DATA space. Here is a breakdown of +how information is fetched: + +- All immediate reads are fetched from PROGRAM space. + +- All PC-relative reads are fetched from PROGRAM space. + +- The initial stack pointer and program counter are fetched from PROGRAM space. + +- All other reads (except for those from the moves instruction for 68020) + are fetched from DATA space. + +The m68k deals with this by encoding the requested address space on the +function code pins: + + FC + Address Space 210 + ------------------ --- + USER DATA 001 + USER PROGRAM 010 + SUPERVISOR DATA 101 + SUPERVISOR PROGRAM 110 + CPU SPACE 111 <-- not emulated in this core since we emulate + interrupt acknowledge in another way. + +Problems arise here if you need to emulate this distinction (if, for example, +your ROM and RAM are at the same address range, with RAM and ROM enable +wired to the function code pins). + +There are 2 ways to deal with this situation using Musashi: + +1. If you only need the distinction between PROGRAM and DATA (the most common), + you can just separate the reads (see the preceeding section). This is the + faster solution. + +2. You can emulate the function code pins entirely. + +To emulate the function code pins: + +- In m68kconf.h, set M68K_EMULATE_FC to OPT_SPECIFY_HANDLER and set + M68K_SET_FC_CALLBACK(A) to your function code handler function. + +- Your function code handler should select the proper address space for + subsequent calls to m68k_read_xx (and m68k_write_xx for 68010+). + +Note: immediate reads are always done from program space, so technically you + don't need to implement the separate immediate reads, although you could + gain more speed improvements leaving them in and doing some clever + programming. + + + +USING DIFFERENT CPU TYPES: +------------------------- +The default is to enable only the 68000 cpu type. To change this, change the +settings for M68K_EMULATE_010 etc in m68kconf.h. + +To set the CPU type you want to use: + +- Make sure it is enabled in m68kconf.h. Current switches are: + M68K_EMULATE_010 + M68K_EMULATE_EC020 + M68K_EMULATE_020 + +- In your host program, call m68k_set_cpu_type() and then call + m68k_pulse_reset(). Valid CPU types are: + M68K_CPU_TYPE_68000, + M68K_CPU_TYPE_68010, + M68K_CPU_TYPE_68EC020, + M68K_CPU_TYPE_68020 + + + +CLOCK FREQUENCY: +--------------- +In order to emulate the correct clock frequency, you will have to calculate +how long it takes the emulation to execute a certain number of "cycles" and +vary your calls to m68k_execute() accordingly. +As well, it is a good idea to take away the CPU's timeslice when it writes to +a memory-mapped port in order to give the device it wrote to a chance to +react. + +You can use the functions m68k_cycles_run(), m68k_cycles_remaining(), +m68k_modify_timeslice(), and m68k_end_timeslice() to do this. +Try to use large cycle values in your calls to m68k_execute() since it will +increase throughput. You can always take away the timeslice later. + + + +MORE CORRECT EMULATION: +---------------------- +You may need to enable these in order to properly emulate some of the more +obscure functions of the m68k: + +- M68K_EMULATE_BKPT_ACK causes the CPU to call a breakpoint handler on a BKPT + instruction + +- M68K_EMULATE_TRACE causes the CPU to generate trace exceptions when the + trace bits are set + +- M68K_EMULATE_RESET causes the CPU to call a reset handler on a RESET + instruction. + +- M68K_EMULATE_PREFETCH emulates the 4-word instruction prefetch that is part + of the 68000/68010 (needed for Amiga emulation). + +- call m68k_pulse_halt() to emulate the HALT pin. + + + +CONVENIENCE FUNCTIONS: +--------------------- +These are in here for programmer convenience: + +- M68K_INSTRUCTION_HOOK lets you call a handler before each instruction. + +- M68K_LOG_ENABLE and M68K_LOG_1010_1111 lets you log illegal and A/F-line + instructions. + + + +MULTIPLE CPU EMULATION: +---------------------- +The default is to use only one CPU. To use more than one CPU in this core, +there are some things to keep in mind: + +- To have different cpus call different functions, use OPT_ON instead of + OPT_SPECIFY_HANDLER, and use the m68k_set_xxx_callback() functions to set + your callback handlers on a per-cpu basis. + +- Be sure to call set_cpu_type() for each CPU you use. + +- Use m68k_set_context() and m68k_get_context() to switch to another CPU. + + + +LOAD AND SAVE CPU CONTEXTS FROM DISK: +------------------------------------ +You can use them68k_load_context() and m68k_save_context() functions to load +and save the CPU state to disk. + + + +GET/SET INFORMATION FROM THE CPU: +-------------------------------- +You can use m68k_get_reg() and m68k_set_reg() to gain access to the internals +of the CPU. + + + +EXAMPLE: +------- + +I have included a file example.zip that contains a full example. diff --git a/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/satsound.c b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/satsound.c new file mode 100644 index 000000000..13f6cac65 --- /dev/null +++ b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/satsound.c @@ -0,0 +1,818 @@ +///////////////////////////////////////////////////////////////////////////// +// +// satsound - Saturn sound system emulation +// +///////////////////////////////////////////////////////////////////////////// + +#ifndef EMU_COMPILE +#error "Hi I forgot to set EMU_COMPILE" +#endif + +#include "satsound.h" + +// #define USE_STARSCREAM +#ifdef USE_STARSCREAM +#include "Starscream/starcpu.h" +#elif defined(USE_M68K) +#include +#include "m68k/m68kconf.h" +#include "m68k/m68k.h" +#else +#include "c68k/c68k.h" +#endif + +#include "yam.h" + +///////////////////////////////////////////////////////////////////////////// +// +// Static information +// +sint32 EMU_CALL satsound_init(void) { return 0; } + +#define CYCLES_PER_SAMPLE (256) + +///////////////////////////////////////////////////////////////////////////// +// +// State information +// +struct SATSOUND_STATE { + struct SATSOUND_STATE *myself; // Pointer used to check location invariance + + uint32 offset_to_maps; + uint32 offset_to_scpu; + uint32 offset_to_yam; + uint32 offset_to_ram; + + uint8 yam_prev_int; +// uint8 scpu_is_executing; + + uint32 scpu_odometer_checkpoint; +#ifndef USE_STARSCREAM + uint32 scpu_odometer_save; +#endif + uint32 sound_samples_remaining; + uint32 cycles_ahead_of_sound; + sint32 cycles_executed; +}; + +// bytes to either side of RAM to prevent branch overflow problems +#define RAMSLOP (0x9000) + +#define SATSOUNDSTATE ((struct SATSOUND_STATE*)(state)) +#define MAPS ((void*)(((char*)(SATSOUNDSTATE))+(SATSOUNDSTATE->offset_to_maps))) +#ifdef USE_STARSCREAM +#define SCPUSTATE ((void*)(((char*)(SATSOUNDSTATE))+(SATSOUNDSTATE->offset_to_scpu))) +#elif defined(USE_M68K) +#define SCPUSTATE ((m68ki_cpu_core*)(((char*)(SATSOUNDSTATE))+(SATSOUNDSTATE->offset_to_scpu))) +#else +#define SCPUSTATE ((c68k_struc*)(((char*)(SATSOUNDSTATE))+(SATSOUNDSTATE->offset_to_scpu))) +#endif +#define YAMSTATE ((void*)(((char*)(SATSOUNDSTATE))+(SATSOUNDSTATE->offset_to_yam))) +#define RAMBYTEPTR (((uint8*)(((char*)(SATSOUNDSTATE))+(SATSOUNDSTATE->offset_to_ram)))+RAMSLOP) + +#ifdef USE_STARSCREAM +extern const uint32 satsound_total_maps_size; +#endif + +uint32 EMU_CALL satsound_get_state_size(void) { + uint32 offset = 0; + offset += sizeof(struct SATSOUND_STATE); +#ifdef USE_STARSCREAM + offset += satsound_total_maps_size; + offset += s68000_get_state_size(); +#elif defined(USE_M68K) + offset += sizeof(m68ki_cpu_core); +#else + offset += sizeof(c68k_struc); +#endif + offset += yam_get_state_size(1); + offset += 0x80000 + 2*RAMSLOP; + return offset; +} + +#if defined(USE_STARSCREAM) || defined(USE_M68K) +static void recompute_and_set_memory_maps(struct SATSOUND_STATE *state); +#endif + +///////////////////////////////////////////////////////////////////////////// +// +// Check to see if this structure has moved, and if so, recompute +// +static void location_check(struct SATSOUND_STATE *state) { + if(state->myself != state) { +#if defined(USE_STARSCREAM) || defined(USE_M68K) + recompute_and_set_memory_maps(SATSOUNDSTATE); +#else + C68k_Set_Fetch(SCPUSTATE, 0x00000, 0x7FFFF, RAMBYTEPTR); +#endif + yam_setram(YAMSTATE, (uint32*)(RAMBYTEPTR), 0x80000, EMU_ENDIAN_XOR(1) ^ 1, 0); + state->myself = state; + } +} + +#if !defined(USE_STARSCREAM) && !defined(USE_M68K) +///////////////////////////////////////////////////////////////////////////// +// +// CPU access callbacks +// +static void satsound_advancesync(struct SATSOUND_STATE *state); + +u32 FASTCALL satsound_cb_readb(void *state, const u32 address) +{ + if (address < (512*1024)) return RAMBYTEPTR[address^EMU_ENDIAN_XOR(1)^1]; + + if (address >= 0x100000 && address < 0x100c00) { + int shift = ((address & 1) ^ 1) * 8; + satsound_advancesync(SATSOUNDSTATE); + return (yam_scsp_load_reg(YAMSTATE, address & 0xFFE, 0xFF << shift) >> shift) & 0xFF; + } + + return 0; +} + +u32 FASTCALL satsound_cb_readw(void *state, const u32 address) +{ + if (address < (512*1024)) return ((uint16*)(RAMBYTEPTR))[address/2]; + + if (address >= 0x100000 && address < 0x100c00) { + satsound_advancesync(SATSOUNDSTATE); + return yam_scsp_load_reg(YAMSTATE, address & 0xFFE, 0xFFFF); + } + + return 0; +} + +void FASTCALL satsound_cb_writeb(void *state, const u32 address, u32 data) +{ + if (address < (512*1024)) { + RAMBYTEPTR[address^EMU_ENDIAN_XOR(1)^1] = data; + return; + } + + if (address >= 0x100000 && address < 0x100c00) { + uint8 breakcpu = 0; + int shift = ((address & 1) ^ 1) * 8; + satsound_advancesync(SATSOUNDSTATE); + //printf("satsound_yam_writebyte(%08X,%08X)\n",address,data); + yam_scsp_store_reg( + YAMSTATE, + address & 0xFFE, + (data & 0xFF) << shift, + 0xFF << shift, + &breakcpu + ); + if(breakcpu) C68k_Release_Cycle(SCPUSTATE); + return; + } +} + +void FASTCALL satsound_cb_writew(void *state, const u32 address, u32 data) +{ + if (address < (512*1024)) { + ((uint16*)(RAMBYTEPTR))[address/2] = data; + return; + } + + if (address >= 0x100000 && address < 0x100c00) { + uint8 breakcpu = 0; + satsound_advancesync(SATSOUNDSTATE); + //printf("satsound_yam_writeword(%08X,%08X)\n",address,data); + yam_scsp_store_reg( + YAMSTATE, + address & 0xFFE, + data & 0xFFFF, + 0xFFFF, + &breakcpu + ); + if(breakcpu) C68k_Release_Cycle(SCPUSTATE); + return; + } +} +#endif + +///////////////////////////////////////////////////////////////////////////// +// +// Clear state +// +void EMU_CALL satsound_clear_state(void *state) { + uint32 offset; + + // Clear local struct + memset(state, 0, sizeof(struct SATSOUND_STATE)); + + // Set up offsets + offset = sizeof(struct SATSOUND_STATE); +#ifdef USE_STARSCREAM + SATSOUNDSTATE->offset_to_maps = offset; offset += satsound_total_maps_size; + SATSOUNDSTATE->offset_to_scpu = offset; offset += s68000_get_state_size(); +#elif defined(USE_M68K) + SATSOUNDSTATE->offset_to_maps = offset; + SATSOUNDSTATE->offset_to_scpu = offset; offset += sizeof(m68ki_cpu_core); +#else + SATSOUNDSTATE->offset_to_maps = offset; + SATSOUNDSTATE->offset_to_scpu = offset; offset += sizeof(c68k_struc); +#endif + SATSOUNDSTATE->offset_to_yam = offset; offset += yam_get_state_size(1); + SATSOUNDSTATE->offset_to_ram = offset; offset += 0x80000 + 2*RAMSLOP; + + // + // Take care of substructures + // + memset(RAMBYTEPTR-RAMSLOP, 0xFF, RAMSLOP); + memset(RAMBYTEPTR , 0x00, 0x80000); + memset(RAMBYTEPTR+0x80000, 0xFF, RAMSLOP); +#ifdef USE_STARSCREAM + s68000_clear_state(SCPUSTATE); +#elif defined(USE_M68K) + memset(SCPUSTATE, 0, sizeof(m68ki_cpu_core)); + m68k_init(SCPUSTATE); +#else + C68k_Init(SCPUSTATE, NULL); + + C68k_Set_Callback_Param(SCPUSTATE, state); + C68k_Set_Fetch(SCPUSTATE, 0x00000, 0x7FFFF, RAMBYTEPTR); + C68k_Set_ReadB(SCPUSTATE, satsound_cb_readb); + C68k_Set_ReadW(SCPUSTATE, satsound_cb_readw); + C68k_Set_WriteB(SCPUSTATE, satsound_cb_writeb); + C68k_Set_WriteW(SCPUSTATE, satsound_cb_writew); +#endif + yam_clear_state(YAMSTATE, 1); + // No idea what to initialize the interrupt system to, so leave it alone + + // + // Compute all location-dependent pointers + // + location_check(SATSOUNDSTATE); + + // Done +} + +///////////////////////////////////////////////////////////////////////////// +// +// Obtain substates +// +void* EMU_CALL satsound_get_scpu_state(void *state) { return (void*)SCPUSTATE; } +void* EMU_CALL satsound_get_yam_state(void *state) { return YAMSTATE; } + +///////////////////////////////////////////////////////////////////////////// +// +// Upload data to RAM, no side effects +// +void EMU_CALL satsound_upload_to_ram( + void *state, + uint32 address, + void *src, + uint32 len +) { + uint32 i; + for(i = 0; i < len; i++) { + (RAMBYTEPTR)[((address+i)^(EMU_ENDIAN_XOR(1)^1))&0x7FFFF] = + ((uint8*)src)[i]; + } + +#ifdef USE_STARSCREAM + s68000_reset(SCPUSTATE); +#elif defined(USE_M68K) + m68k_pulse_reset(SCPUSTATE); +#else + C68k_Reset(SCPUSTATE); +#endif +} + +///////////////////////////////////////////////////////////////////////////// +// +// Sync Yamaha emulation with satsound +// +static void sync_sound(struct SATSOUND_STATE *state) { + if(state->cycles_ahead_of_sound >= CYCLES_PER_SAMPLE) { + uint32 samples = (state->cycles_ahead_of_sound) / CYCLES_PER_SAMPLE; + // + // Avoid overflowing the number of samples remaining + // + if(samples > state->sound_samples_remaining) { + samples = state->sound_samples_remaining; + } + if(samples > 0) { + yam_advance(YAMSTATE, samples); + state->cycles_ahead_of_sound -= CYCLES_PER_SAMPLE * samples; + state->sound_samples_remaining -= samples; + } + } +} + +///////////////////////////////////////////////////////////////////////////// +// +// Advance hardware activity to match progress by SCPU +// +static void satsound_advancesync(struct SATSOUND_STATE *state) { + uint32 odometer, elapse; + // + // Get the number of elapsed cycles + // +#ifdef USE_STARSCREAM + odometer = s68000_read_odometer(SCPUSTATE); +#elif defined(USE_M68K) + odometer = SCPUSTATE->initial_cycles - SCPUSTATE->remaining_cycles; +#else + odometer = C68k_Get_CycleDone(SCPUSTATE); + if(odometer == ~0) odometer = state->scpu_odometer_save; +#endif + elapse = odometer - (state->scpu_odometer_checkpoint); + state->scpu_odometer_checkpoint = odometer; + // + // Update cycles executed + // + state->cycles_executed += elapse; + state->cycles_ahead_of_sound += elapse; + // + // Synchronize the sound part + // + sync_sound(SATSOUNDSTATE); +} + +#ifdef USE_STARSCREAM +///////////////////////////////////////////////////////////////////////////// +// +// Starscream I/O callbacks +// +static unsigned STARSCREAM_CALL satsound_yam_readbyte( + void *state, + unsigned address +) { + int shift = ((address & 1) ^ 1) * 8; + satsound_advancesync(SATSOUNDSTATE); + return (yam_scsp_load_reg(YAMSTATE, address & 0xFFE, 0xFF << shift) >> shift) & 0xFF; +} + +static unsigned STARSCREAM_CALL satsound_yam_readword( + void *state, + unsigned address +) { + satsound_advancesync(SATSOUNDSTATE); + return yam_scsp_load_reg(YAMSTATE, address & 0xFFE, 0xFFFF) & 0xFFFF; +} + +static void STARSCREAM_CALL satsound_yam_writebyte( + void *state, + unsigned address, + unsigned data +) { + uint8 breakcpu = 0; + int shift = ((address & 1) ^ 1) * 8; + satsound_advancesync(SATSOUNDSTATE); +//printf("satsound_yam_writebyte(%08X,%08X)\n",address,data); + yam_scsp_store_reg( + YAMSTATE, + address & 0xFFE, + (data & 0xFF) << shift, + 0xFF << shift, + &breakcpu + ); + if(breakcpu) s68000_break(SCPUSTATE); +} + +static void STARSCREAM_CALL satsound_yam_writeword( + void *state, + unsigned address, + unsigned data +) { + uint8 breakcpu = 0; + satsound_advancesync(SATSOUNDSTATE); +//printf("satsound_yam_writeword(%08X,%08X)\n",address,data); + yam_scsp_store_reg( + YAMSTATE, + address & 0xFFE, + data & 0xFFFF, + 0xFFFF, + &breakcpu + ); + if(breakcpu) s68000_break(SCPUSTATE); +} + +///////////////////////////////////////////////////////////////////////////// +// +// Static memory map structures +// + +static const struct STARSCREAM_PROGRAMREGION satsound_map_fetch[] = { + { 0x000000, 0x07FFFF, 0 }, + { -1, -1, NULL } +}; + +static const struct STARSCREAM_DATAREGION satsound_map_readbyte[] = { + { 0x000000, 0x07FFFF, NULL, NULL }, + { 0x100000, 0x100FFF, satsound_yam_readbyte, NULL }, + { -1, -1, NULL, NULL } +}; + +static const struct STARSCREAM_DATAREGION satsound_map_readword[] = { + { 0x000000, 0x07FFFF, NULL, NULL }, + { 0x100000, 0x100FFF, satsound_yam_readword, NULL }, + { -1, -1, NULL, NULL } +}; + +static const struct STARSCREAM_DATAREGION satsound_map_writebyte[] = { + { 0x000000, 0x07FFFF, NULL, NULL }, + { 0x100000, 0x100FFF, satsound_yam_writebyte, NULL }, + { -1, -1, NULL, NULL } +}; + +static const struct STARSCREAM_DATAREGION satsound_map_writeword[] = { + { 0x000000, 0x07FFFF, NULL, NULL }, + { 0x100000, 0x100FFF, satsound_yam_writeword, NULL }, + { -1, -1, NULL, NULL } +}; + +static void *computemap_program( + struct SATSOUND_STATE *state, + struct STARSCREAM_PROGRAMREGION *dst, + const struct STARSCREAM_PROGRAMREGION *src +) { + int i; + for(i = 0;; i++) { + memcpy(dst + i, src + i, sizeof(struct STARSCREAM_PROGRAMREGION)); + if(dst[i].lowaddr == ((uint32)(-1))) { i++; break; } + } + dst[0].offset = RAMBYTEPTR; + return dst + i; +} + +static void *computemap_data( + struct SATSOUND_STATE *state, + struct STARSCREAM_DATAREGION *dst, + const struct STARSCREAM_DATAREGION *src +) { + int i; + for(i = 0;; i++) { + memcpy(dst + i, src + i, sizeof(struct STARSCREAM_DATAREGION)); + if(dst[i].lowaddr == ((uint32)(-1))) { i++; break; } + } + dst[0].userdata = RAMBYTEPTR; + dst[1].userdata = state; + return dst + i; +} + +const uint32 satsound_total_maps_size = + sizeof(satsound_map_fetch) + + sizeof(satsound_map_readbyte) + + sizeof(satsound_map_readword) + + sizeof(satsound_map_writebyte) + + sizeof(satsound_map_writeword); + +///////////////////////////////////////////////////////////////////////////// +// +// Recompute the memory maps AND REGISTER with the SCPU state. +// +static void recompute_and_set_memory_maps( + struct SATSOUND_STATE *state +) { + void *mapinfo[10]; + // + // Create mapinfo for registering with s68000_set_memory_maps + // + mapinfo[0] = MAPS; + mapinfo[1] = computemap_program(state, mapinfo[0], satsound_map_fetch); + mapinfo[2] = computemap_data (state, mapinfo[1], satsound_map_readbyte); + mapinfo[3] = computemap_data (state, mapinfo[2], satsound_map_readword); + mapinfo[4] = computemap_data (state, mapinfo[3], satsound_map_writebyte); + computemap_data (state, mapinfo[4], satsound_map_writeword); + mapinfo[5] = mapinfo[0]; + mapinfo[6] = mapinfo[1]; + mapinfo[7] = mapinfo[2]; + mapinfo[8] = mapinfo[3]; + mapinfo[9] = mapinfo[4]; + // + // Register memory maps + // + s68000_set_memory_maps(SCPUSTATE, mapinfo); +} +#endif + +#ifdef USE_M68K + +static unsigned int satsound_read_dummy(void *param, unsigned int address) +{ + return 0; +} + +static void satsound_write_dummy(void *param, unsigned int address, unsigned int data) +{ +} + +static unsigned int satsound_apu_read8(void *state, unsigned int address) +{ + if (address >= 0x100000 && address < 0x100c00) { + int shift = ((address & 1) ^ 1) * 8; + satsound_advancesync(SATSOUNDSTATE); + return (yam_scsp_load_reg(YAMSTATE, address & 0xFFE, 0xFF << shift) >> shift) & 0xFF; + } + + return 0; +} + +static unsigned int satsound_apu_read16(void *state, unsigned int address) +{ + if (address >= 0x100000 && address < 0x100c00) { + satsound_advancesync(SATSOUNDSTATE); + return yam_scsp_load_reg(YAMSTATE, address & 0xFFE, 0xFFFF) & 0xFFFF; + } + + return 0; +} + +static void satsound_apu_write8(void *state, unsigned int address, unsigned int data) +{ + if (address >= 0x100000 && address < 0x100c00) { + uint8 breakcpu = 0; + int shift = ((address & 1) ^ 1) * 8; + satsound_advancesync(SATSOUNDSTATE); + //printf("satsound_yam_writebyte(%08X,%08X)\n",address,data); + yam_scsp_store_reg( + YAMSTATE, + address & 0xFFE, + (data & 0xFF) << shift, + 0xFF << shift, + &breakcpu + ); + if(breakcpu) { + SATSOUNDSTATE->scpu_odometer_save = SCPUSTATE->remaining_cycles; + SCPUSTATE->remaining_cycles = 0; + } + } +} + +static void satsound_apu_write16(void *state, unsigned int address, unsigned int data) +{ + if (address >= 0x100000 && address < 0x100c00) { + uint8 breakcpu = 0; + satsound_advancesync(SATSOUNDSTATE); + //printf("satsound_yam_writebyte(%08X,%08X)\n",address,data); + yam_scsp_store_reg( + YAMSTATE, + address & 0xFFE, + data, + 0xFFFF, + &breakcpu + ); + if(breakcpu) { + SATSOUNDSTATE->scpu_odometer_save = SCPUSTATE->remaining_cycles; + SCPUSTATE->remaining_cycles = 0; + } + } +} + +static void recompute_and_set_memory_maps( + struct SATSOUND_STATE *state +) { + uint32 i; + cpu_memory_map * map; + for(i = 0; i < 8; i++) { + map = SCPUSTATE->memory_map + i; + map->param = NULL; + map->base = RAMBYTEPTR + (i << 16); + map->read8 = NULL; + map->read16 = NULL; + map->write8 = NULL; + map->write16 = NULL; + } + for(; i < 0x10; i++) { + map = SCPUSTATE->memory_map + i; + map->param = NULL; + map->base = NULL; + map->read8 = satsound_read_dummy; + map->read16 = satsound_read_dummy; + map->write8 = satsound_write_dummy; + map->write16 = satsound_write_dummy; + } + map = SCPUSTATE->memory_map + 0x10; + map->param = state; + map->base = NULL; + map->read8 = satsound_apu_read8; + map->read16 = satsound_apu_read16; + map->write8 = satsound_apu_write8; + map->write16 = satsound_apu_write16; + for(i = 0x11; i < 0x100; i++) { + map = SCPUSTATE->memory_map + i; + map->param = NULL; + map->base = NULL; + map->read8 = satsound_read_dummy; + map->read16 = satsound_read_dummy; + map->write8 = satsound_write_dummy; + map->write16 = satsound_write_dummy; + } +} +#endif + +///////////////////////////////////////////////////////////////////////////// +// +// Determine how many cycles until the next interrupt +// +// This is then used as an upper bound for how many cycles can be executed +// before checking for futher interrupts +// +static uint32 cycles_until_next_interrupt(struct SATSOUND_STATE *state) { + uint32 yamsamples; + uint32 yamcycles; + yamsamples = yam_get_min_samples_until_interrupt(YAMSTATE); + if(yamsamples > 0x10000) { yamsamples = 0x10000; } + yamcycles = yamsamples * CYCLES_PER_SAMPLE; + if(yamcycles <= state->cycles_ahead_of_sound) return 1; + return yamcycles - state->cycles_ahead_of_sound; +} + +///////////////////////////////////////////////////////////////////////////// +// +// Executes the given number of cycles or the given number of samples +// (whichever is less) +// +// Sets *sound_samples to the number of samples actually generated, +// which may be ZERO or LESS than the number requested, but never more. +// +// Return value: +// >= 0 The number of cycles actually executed, which may be ZERO, MORE, +// or LESS than the number requested +// <= -1 Unrecoverable error +// +#if defined(SCSP_LOG) && !defined(USE_STARSCREAM) +unsigned char ** scsp_pc; +unsigned char ** scsp_basepc; +#endif + +sint32 EMU_CALL satsound_execute( + void *state, + sint32 cycles, + sint16 *sound_buf, + uint32 *sound_samples +) { + sint32 error = 0; + uint8 *yamintptr; + // + // If we have a bogus cycle count, return error + // + if(cycles < 0) { return -1; } + // + // Ensure location invariance + // + location_check(SATSOUNDSTATE); + // + // Cap to sane values to avoid overflow problems + // + if(cycles > 0x1000000) { cycles = 0x1000000; } + if((*sound_samples) > 0x10000) { (*sound_samples) = 0x10000; } + // + // Set up the buffer + // + yam_beginbuffer(YAMSTATE, sound_buf); + SATSOUNDSTATE->sound_samples_remaining = *sound_samples; + // + // Get the interrupt pending pointer + // + yamintptr = yam_get_interrupt_pending_ptr(YAMSTATE); + // + // Zero out these counters + // + SATSOUNDSTATE->cycles_executed = 0; +#ifdef USE_STARSCREAM + SATSOUNDSTATE->scpu_odometer_checkpoint = s68000_read_odometer(SCPUSTATE); +#elif defined(USE_M68K) + SATSOUNDSTATE->scpu_odometer_checkpoint = 0; +#else + SATSOUNDSTATE->scpu_odometer_checkpoint = 0; +#endif + // + // Sync any pending samples from last time + // + sync_sound(SATSOUNDSTATE); + // + // Cap cycles depending on how many samples we have left to generate + // + { sint32 cap = CYCLES_PER_SAMPLE * SATSOUNDSTATE->sound_samples_remaining; + cap -= SATSOUNDSTATE->cycles_ahead_of_sound; + if(cap < 0) cap = 0; + if(cycles > cap) cycles = cap; + } + // + // Reset the 68K if necessary + // +// if(!(SATSOUNDSTATE->scpu_is_executing)) { +// s68000_reset(SCPUSTATE); +// SATSOUNDSTATE->scpu_is_executing = 1; +// } + +#if defined(SCSP_LOG) && !defined(USE_STARSCREAM) + scsp_pc = &(SCPUSTATE->PC); + scsp_basepc = &(SCPUSTATE->BasePC); +#endif + + // + // Execution loop + // + while(SATSOUNDSTATE->cycles_executed < cycles) { +#ifdef USE_STARSCREAM + uint32 r; +#else + sint32 r; +#endif + uint32 remain = cycles - SATSOUNDSTATE->cycles_executed; + uint32 ci = cycles_until_next_interrupt(SATSOUNDSTATE); + if(remain > ci) { remain = ci; } + if(remain > 0x1000000) { remain = 0x1000000; } + + if((SATSOUNDSTATE->yam_prev_int) != (*yamintptr)) { +//printf("interrupt %d\n",(int)(*yamintptr)); +#ifdef USE_STARSCREAM + SATSOUNDSTATE->yam_prev_int = (*yamintptr); + if(*yamintptr) { + s68000_interrupt( + SCPUSTATE, + ((-1)*256) + ((SATSOUNDSTATE->yam_prev_int)&7) + ); + } +#elif defined(USE_M68K) + unsigned line = ((*yamintptr) ? *yamintptr : SATSOUNDSTATE->yam_prev_int) & 7; + unsigned line_state = *yamintptr ? ASSERT_LINE : RESET_LINE; + m68k_set_irq( + SCPUSTATE, + line, + line_state + ); + SATSOUNDSTATE->yam_prev_int = (*yamintptr); +#else + SATSOUNDSTATE->yam_prev_int = (*yamintptr); + if(*yamintptr) { + C68k_Set_IRQ( + SCPUSTATE, + (SATSOUNDSTATE->yam_prev_int)&7 + ); + } +#endif + } +//printf("executing remain=%d\n",remain); +#ifdef USE_STARSCREAM + r = s68000_execute(SCPUSTATE, remain); + if(r != 0x80000000) { +#elif defined(USE_M68K) + SATSOUNDSTATE->scpu_odometer_save = ~0; + r = m68k_execute(SCPUSTATE, remain); + if (0) { +#else + r = C68k_Exec(SCPUSTATE, remain); + if(r < 0) { +#endif + error = -1; break; + } +#if !defined(USE_STARSCREAM) && !defined(USE_M68K) + SATSOUNDSTATE->scpu_odometer_save = r; +#endif +#ifdef USE_M68K + if(SATSOUNDSTATE->scpu_odometer_save != ~0) { + SCPUSTATE->remaining_cycles += SATSOUNDSTATE->scpu_odometer_save; + } +#endif + satsound_advancesync(SATSOUNDSTATE); +#if !defined(USE_STARSCREAM) + SATSOUNDSTATE->scpu_odometer_checkpoint = 0; +#endif + } + // + // Flush out actual sound rendering + // + yam_flush(YAMSTATE); + // + // Adjust outgoing sample count + // + (*sound_samples) -= SATSOUNDSTATE->sound_samples_remaining; + // + // Done + // + if(error) return error; + return SATSOUNDSTATE->cycles_executed; +} + +///////////////////////////////////////////////////////////////////////////// +// +// Get / set memory words with no side effects +// +uint16 EMU_CALL satsound_getword(void *state, uint32 a) { + return *((uint16*)(RAMBYTEPTR+(a&0x7FFFE))); +} + +void EMU_CALL satsound_setword(void *state, uint32 a, uint16 d) { + *((uint16*)(RAMBYTEPTR+(a&0x7FFFE))) = d; +} + +///////////////////////////////////////////////////////////////////////////// +// +// Get the current program counter +// +uint32 EMU_CALL satsound_get_pc(void *state) { +#ifdef USE_STARSCREAM + return s68000_getreg(SCPUSTATE, STARSCREAM_REG_PC); +#elif defined(USE_M68K) + return SCPUSTATE->pc; +#else + return C68k_Get_PC(SCPUSTATE); +#endif +} + +///////////////////////////////////////////////////////////////////////////// diff --git a/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/satsound.h b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/satsound.h new file mode 100644 index 000000000..879066a09 --- /dev/null +++ b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/satsound.h @@ -0,0 +1,75 @@ +///////////////////////////////////////////////////////////////////////////// +// +// satsound - Saturn sound system emulation +// +///////////////////////////////////////////////////////////////////////////// + +#ifndef __SEGA_SATSOUND_H__ +#define __SEGA_SATSOUND_H__ + +#include "emuconfig.h" + +///////////////////////////////////////////////////////////////////////////// + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Init / state +// +sint32 EMU_CALL satsound_init(void); +uint32 EMU_CALL satsound_get_state_size(void); +void EMU_CALL satsound_clear_state(void *state); + +// +// Obtain substates +// +void* EMU_CALL satsound_get_scpu_state(void *state); +void* EMU_CALL satsound_get_yam_state(void *state); + +// +// Get / set memory words with no side effects +// +uint16 EMU_CALL satsound_getword(void *state, uint32 a); +void EMU_CALL satsound_setword(void *state, uint32 a, uint16 d); + +// +// Uploads a section of data; only affects RAM +// +void EMU_CALL satsound_upload_to_ram(void *state, uint32 address, void *src, uint32 len); + +// +// Executes the given number of cycles or the given number of samples +// (whichever is less) +// +// Sets *sound_samples to the number of samples actually generated, +// which may be ZERO or LESS than the number requested, but never more. +// +// Return value: +// >= 0 The number of cycles actually executed, which may be ZERO, MORE, +// or LESS than the number requested +// <= -1 Unrecoverable error +// +sint32 EMU_CALL satsound_execute( + void *state, + sint32 cycles, + sint16 *sound_buf, + uint32 *sound_samples +); + +///////////////////////////////////////////////////////////////////////////// +// +// Get the current program counter +// +uint32 EMU_CALL satsound_get_pc(void *state); + +///////////////////////////////////////////////////////////////////////////// + +#ifdef __cplusplus +} +#endif + +///////////////////////////////////////////////////////////////////////////// + +#endif diff --git a/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/sega.c b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/sega.c new file mode 100644 index 000000000..cdbd3b5b5 --- /dev/null +++ b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/sega.c @@ -0,0 +1,303 @@ +///////////////////////////////////////////////////////////////////////////// +// +// sega - Top-level emulation for Saturn and DC +// +///////////////////////////////////////////////////////////////////////////// + +#ifndef EMU_COMPILE +#error "Hi I forgot to set EMU_COMPILE" +#endif + +#include "sega.h" + +#include "satsound.h" +#include "dcsound.h" +#include "arm.h" +#include "yam.h" +#ifdef USE_STARSCREAM +#include "Starscream/starcpu.h" +#endif + +///////////////////////////////////////////////////////////////////////////// +// +// Static init for the whole library +// +static uint8 library_was_initialized = 0; + +// +// Deliberately create a NULL dereference +// Useful for calling attention to show-stopper problems like forgetting to +// call sega_init() or compiling with the wrong byte order +// +static void sega_hang(const char *message) { + for(;;) { *((volatile char*)0) = *message; } +} + +// +// Endian check +// +static void sega_endian_check(void) { + uint32 num = 0x61626364; + // Big + if(!memcmp(&num, "abcd", 4)) { +#ifdef SEGA_BIG_ENDIAN + return; +#endif + sega_hang("endian check"); + } + // Little + if(!memcmp(&num, "dcba", 4)) { +#ifndef SEGA_BIG_ENDIAN + return; +#endif + sega_hang("endian check"); + } + // Don't know what! + sega_hang("endian check"); +} + +// +// Data type size check +// +static void sega_size_check(void) { + if(sizeof(uint8 ) != 1) sega_hang("size check"); + if(sizeof(uint16) != 2) sega_hang("size check"); + if(sizeof(uint32) != 4) sega_hang("size check"); + if(sizeof(uint64) != 8) sega_hang("size check"); + if(sizeof(sint8 ) != 1) sega_hang("size check"); + if(sizeof(sint16) != 2) sega_hang("size check"); + if(sizeof(sint32) != 4) sega_hang("size check"); + if(sizeof(sint64) != 8) sega_hang("size check"); +} + +sint32 EMU_CALL sega_init(void) { + sint32 r; + sega_endian_check(); + sega_size_check(); + + if(library_was_initialized) return 0; + +#ifndef DISABLE_SSF + r = satsound_init(); if(r) return r; +#endif + r = dcsound_init(); if(r) return r; + r = arm_init(); if(r) return r; + r = yam_init(); if(r) return r; +#ifndef DISABLE_SSF +#ifdef USE_STARSCREAM + r = s68000_init(); if(r) return r; +#endif +#endif + + library_was_initialized = 1; + return 0; +} + +///////////////////////////////////////////////////////////////////////////// +// +// Version information +// +const char* EMU_CALL sega_getversion(void) { + static const char s[] = "SegaCore0001 (built " __DATE__ ")"; + static char rv[500]; + int sl = strlen(s); + memcpy(rv, s, sl); +#ifndef DISABLE_SSF + rv[sl] = '\n'; +#ifdef USE_STARSCREAM + strcpy(rv+sl+1, s68000_get_version()); +#else + strcpy(rv+sl+1, "C68K"); +#endif +#endif + + return rv; +} + +///////////////////////////////////////////////////////////////////////////// +// +// State information +// + +struct SEGA_STATE { + uint32 offset_to_dcsound; + uint32 offset_to_satsound; +}; + +#define SEGASTATE ((struct SEGA_STATE*)(state)) +#define DCSOUNDSTATE ((void*)(((char*)(state))+(SEGASTATE->offset_to_dcsound))) +#define SATSOUNDSTATE ((void*)(((char*)(state))+(SEGASTATE->offset_to_satsound))) + +#define HAVE_DCSOUND (SEGASTATE->offset_to_dcsound!=0) +#define HAVE_SATSOUND (SEGASTATE->offset_to_satsound!=0) + +uint32 EMU_CALL sega_get_state_size(uint8 version) { + uint32 size = 0; + if(version != 2) version = 1; + size += sizeof(struct SEGA_STATE); +#ifndef DISABLE_SSF + if(version == 1) size += satsound_get_state_size(); +#endif + if(version == 2) size += dcsound_get_state_size(); + return size; +} + +void EMU_CALL sega_clear_state(void *state, uint8 version) { + uint32 offset; + + if(version != 2) version = 1; + // + // If we haven't initialized, we really SHOULD have. + // + if(!library_was_initialized) sega_hang("library not initialized"); + + // Clear local struct + memset(state, 0, sizeof(struct SEGA_STATE)); + // Set up offsets + offset = sizeof(struct SEGA_STATE); +#ifndef DISABLE_SSF + if(version == 1) { SEGASTATE->offset_to_satsound = offset; offset += satsound_get_state_size(); } +#endif + if(version == 2) { SEGASTATE->offset_to_dcsound = offset; offset += dcsound_get_state_size(); } + // + // Take care of substructures + // +#ifndef DISABLE_SSF + if(HAVE_SATSOUND) satsound_clear_state(SATSOUNDSTATE); +#endif + if(HAVE_DCSOUND) dcsound_clear_state(DCSOUNDSTATE); + // Done +} + +///////////////////////////////////////////////////////////////////////////// +// +// Obtain substates +// +void* EMU_CALL sega_get_satsound_state(void *state) { +#ifdef DISABLE_SSF + return NULL; +#else + if(!(HAVE_SATSOUND)) return NULL; + return SATSOUNDSTATE; +#endif +} + +void* EMU_CALL sega_get_dcsound_state(void *state) { + if(!(HAVE_DCSOUND)) return NULL; + return DCSOUNDSTATE; +} + +///////////////////////////////////////////////////////////////////////////// +// +// Executes the given number of cycles or the given number of samples +// (whichever is less) +// +// Sets *sound_samples to the number of samples actually generated, +// which may be ZERO or LESS than the number requested, but never more. +// +// Return value: +// >= 0 The number of cycles actually executed, which may be ZERO, MORE, +// or LESS than the number requested +// <= -1 Unrecoverable error +// +sint32 EMU_CALL sega_execute( + void *state, + sint32 cycles, + sint16 *sound_buf, + uint32 *sound_samples +) { +#ifndef DISABLE_SSF + if(HAVE_SATSOUND) { + return satsound_execute(SATSOUNDSTATE, cycles, sound_buf, sound_samples); + } else +#endif + if(HAVE_DCSOUND) { + return dcsound_execute(DCSOUNDSTATE, cycles, sound_buf, sound_samples); + } else { + return -1; + } +} + +///////////////////////////////////////////////////////////////////////////// + +static uint32 get32lsb(uint8 *src) { + return + ((((uint32)(src[0])) & 0xFF) << 0) | + ((((uint32)(src[1])) & 0xFF) << 8) | + ((((uint32)(src[2])) & 0xFF) << 16) | + ((((uint32)(src[3])) & 0xFF) << 24); +} + +static uint32 get32msb(uint8 *src) { + return + ((((uint32)(src[3])) & 0xFF) << 0) | + ((((uint32)(src[2])) & 0xFF) << 8) | + ((((uint32)(src[1])) & 0xFF) << 16) | + ((((uint32)(src[0])) & 0xFF) << 24); +} + +///////////////////////////////////////////////////////////////////////////// +// +// Upload program - must INCLUDE the 4-byte header. +// Returns nonzero on error. +// +sint32 EMU_CALL sega_upload_program(void *state, void *program, uint32 size) { + uint32 start; + if(size < 5) return -1; + start = get32lsb((uint8*)program); +#ifndef DISABLE_SSF + if(HAVE_SATSOUND) { + satsound_upload_to_ram(SATSOUNDSTATE, start, ((uint8*)program) + 4, size - 4); + } else +#endif + if(HAVE_DCSOUND) { + dcsound_upload_to_ram(DCSOUNDSTATE, start, ((uint8*)program) + 4, size - 4); + } else { + return -1; + } + return 0; +} + +///////////////////////////////////////////////////////////////////////////// +// +// Get the current program counter +// +uint32 EMU_CALL sega_get_pc(void *state) { +#ifndef DISABLE_SSF + if(HAVE_SATSOUND) return satsound_get_pc(SATSOUNDSTATE); +#endif + if(HAVE_DCSOUND) return dcsound_get_pc(DCSOUNDSTATE); + return 0; +} + +///////////////////////////////////////////////////////////////////////////// + +static void *getyamstate(struct SEGA_STATE *state) { + void *yamstate = NULL; +#ifndef DISABLE_SSF + if(HAVE_SATSOUND) { yamstate = satsound_get_yam_state(SATSOUNDSTATE); } +#endif + if(HAVE_DCSOUND) { yamstate = dcsound_get_yam_state(DCSOUNDSTATE); } + return yamstate; +} + +///////////////////////////////////////////////////////////////////////////// +// +// Enable or disable various things +// +void EMU_CALL sega_enable_dry(void *state, uint8 enable) { + void *yamstate = getyamstate(SEGASTATE); + if(yamstate) yam_enable_dry(yamstate, enable); +} + +void EMU_CALL sega_enable_dsp(void *state, uint8 enable) { + void *yamstate = getyamstate(SEGASTATE); + if(yamstate) yam_enable_dsp(yamstate, enable); +} + +void EMU_CALL sega_enable_dsp_dynarec(void *state, uint8 enable) { + void *yamstate = getyamstate(SEGASTATE); + if(yamstate) yam_enable_dsp_dynarec(yamstate, enable); +} + +///////////////////////////////////////////////////////////////////////////// diff --git a/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/sega.h b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/sega.h new file mode 100644 index 000000000..65658e712 --- /dev/null +++ b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/sega.h @@ -0,0 +1,106 @@ +///////////////////////////////////////////////////////////////////////////// +// +// sega - Top-level emulation for DC and Saturn +// +///////////////////////////////////////////////////////////////////////////// + +#ifndef __SEGA_SEGA_H__ +#define __SEGA_SEGA_H__ + +#include "emuconfig.h" + +///////////////////////////////////////////////////////////////////////////// + +#ifdef __cplusplus +extern "C" { +#endif + +///////////////////////////////////////////////////////////////////////////// +// +// Static init for the whole library +// Returns nonzero on error +// +// May generate a null dereference if the library was compiled wrong, but +// that's for me to worry about. +// +sint32 EMU_CALL sega_init(void); + +///////////////////////////////////////////////////////////////////////////// +// +// Version information +// +const char* EMU_CALL sega_getversion(void); + +///////////////////////////////////////////////////////////////////////////// +// +// State init +// Version = 1 for Saturn, 2 for Dreamcast +// +// Example of usage: +// +// void *my_sega_state = malloc(sega_get_state_size(version)); +// sega_clear_state(my_sega_state, version); +// ... +// [subsequent sega calls] +// ... +// +uint32 EMU_CALL sega_get_state_size(uint8 version); +void EMU_CALL sega_clear_state(void *state, uint8 version); + +///////////////////////////////////////////////////////////////////////////// +// +// Obtain substates +// +void* EMU_CALL sega_get_satsound_state(void *state); +void* EMU_CALL sega_get_dcsound_state(void *state); + +///////////////////////////////////////////////////////////////////////////// +// +// Upload program - must INCLUDE the 4-byte header. +// Returns nonzero on error. +// +sint32 EMU_CALL sega_upload_program(void *state, void *program, uint32 size); + +///////////////////////////////////////////////////////////////////////////// +// +// Executes the given number of cycles or the given number of samples +// (whichever is less) +// +// Sets *sound_samples to the number of samples actually generated, +// which may be ZERO or LESS than the number requested, but never more. +// +// Return value: +// >= 0 The number of cycles actually executed, which may be ZERO, MORE, +// or LESS than the number requested +// <= -1 Unrecoverable error +// +sint32 EMU_CALL sega_execute( + void *state, + sint32 cycles, + sint16 *sound_buf, + uint32 *sound_samples +); + +///////////////////////////////////////////////////////////////////////////// +// +// Get the current program counter +// +uint32 EMU_CALL sega_get_pc(void *state); + +///////////////////////////////////////////////////////////////////////////// +// +// Enable or disable various things +// +void EMU_CALL sega_enable_dry(void *state, uint8 enable); +void EMU_CALL sega_enable_dsp(void *state, uint8 enable); +void EMU_CALL sega_enable_dsp_dynarec(void *state, uint8 enable); + +///////////////////////////////////////////////////////////////////////////// + +#ifdef __cplusplus +} +#endif + +///////////////////////////////////////////////////////////////////////////// + +#endif diff --git a/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/yam.c b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/yam.c new file mode 100644 index 000000000..5c579d641 --- /dev/null +++ b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/yam.c @@ -0,0 +1,3477 @@ +///////////////////////////////////////////////////////////////////////////// +// +// yam - Emulates Yamaha SCSP and AICA +// +///////////////////////////////////////////////////////////////////////////// + +#ifndef EMU_COMPILE +#error "Hi I forgot to set EMU_COMPILE" +#endif + +#include "yam.h" + +#ifdef _WIN32 +#define WIN32_LEAN_AND_MEAN +#include +#elif defined(HAVE_MPROTECT) +#include +#include +#include +#endif + +#include + +#ifndef _WIN32 +#define __cdecl +#define __fastcall __attribute__((regparm(3))) +#endif + +/* No dynarec for x86_64 yet */ +#if defined(_WIN32) || defined(__i386__) +#define ENABLE_DYNAREC +#endif +#if defined(_WIN64) || defined(__amd64__) +#undef ENABLE_DYNAREC +#endif + +// no 'conversion from _blah_ possible loss of data' warnings +#pragma warning (disable: 4244) + +///////////////////////////////////////////////////////////////////////////// + +// meh, these don't like to work higher than 1 and 2 +#define RENDERMAX (200) +#define RINGMAX (256) // should be nearest power of two that's at least one greater than RENDERMAX + +///////////////////////////////////////////////////////////////////////////// + +#define INT_ONE_SAMPLE (10) +#define INT_MIDI_OUTPUT (9) +#define INT_TIMER_C (8) +#define INT_TIMER_B (7) +#define INT_TIMER_A (6) +#define INT_CPU (5) +#define INT_DMA_END (4) +#define INT_MIDI_INPUT (3) +#define INT_RESERVED_2 (2) +#define INT_RESERVED_1 (1) +#define INT_EXTERNAL (0) + +///////////////////////////////////////////////////////////////////////////// +// +// Static information +// + +#define MAKELFOPHASEINC(x) (((uint64)(0x100000000)) / ((uint64)(x))) + +static uint32 lfophaseinctable[0x20] = { +MAKELFOPHASEINC(0x3FC00),MAKELFOPHASEINC(0x37C00),MAKELFOPHASEINC(0x2FC00),MAKELFOPHASEINC(0x27C00), +MAKELFOPHASEINC(0x1FC00),MAKELFOPHASEINC(0x1BC00),MAKELFOPHASEINC(0x17C00),MAKELFOPHASEINC(0x13C00), +MAKELFOPHASEINC(0x0FC00),MAKELFOPHASEINC(0x0BC00),MAKELFOPHASEINC(0x0DC00),MAKELFOPHASEINC(0x09C00), +MAKELFOPHASEINC(0x07C00),MAKELFOPHASEINC(0x06C00),MAKELFOPHASEINC(0x05C00),MAKELFOPHASEINC(0x04C00), +MAKELFOPHASEINC(0x03C00),MAKELFOPHASEINC(0x03400),MAKELFOPHASEINC(0x02C00),MAKELFOPHASEINC(0x02400), +MAKELFOPHASEINC(0x01C00),MAKELFOPHASEINC(0x01800),MAKELFOPHASEINC(0x01400),MAKELFOPHASEINC(0x01000), +MAKELFOPHASEINC(0x00C00),MAKELFOPHASEINC(0x00A00),MAKELFOPHASEINC(0x00800),MAKELFOPHASEINC(0x00600), +MAKELFOPHASEINC(0x00400),MAKELFOPHASEINC(0x00300),MAKELFOPHASEINC(0x00200),MAKELFOPHASEINC(0x00100) +}; + +static uint8 envattackshift[0x3D][4] = { +/* 00-07 */ {4,4,4,4},{4,4,4,4},{4,4,4,4},{4,4,4,4},{4,4,4,4},{4,4,4,4},{4,4,4,4},{4,4,4,4}, +/* 08-0F */ {4,4,4,4},{4,4,4,4},{4,4,4,4},{4,4,4,4},{4,4,4,4},{4,4,4,4},{4,4,4,4},{4,4,4,4}, +/* 10-17 */ {4,4,4,4},{4,4,4,4},{4,4,4,4},{4,4,4,4},{4,4,4,4},{4,4,4,4},{4,4,4,4},{4,4,4,4}, +/* 18-1F */ {4,4,4,4},{4,4,4,4},{4,4,4,4},{4,4,4,4},{4,4,4,4},{4,4,4,4},{4,4,4,4},{4,4,4,4}, +/* 20-27 */ {4,4,4,4},{4,4,4,4},{4,4,4,4},{4,4,4,4},{4,4,4,4},{4,4,4,4},{4,4,4,4},{4,4,4,4}, +/* 28-2F */ {4,4,4,4},{4,4,4,4},{4,4,4,4},{4,4,4,4},{4,4,4,4},{4,4,4,4},{4,4,4,4},{4,4,4,4}, +/* 30-37 */ {4,4,4,4},{3,4,4,4},{3,4,3,4},{3,3,3,4},{3,3,3,3},{2,3,3,3},{2,3,2,3},{2,2,2,3}, +/* 38-3C */ {2,2,2,2},{1,2,2,2},{1,2,1,2},{1,1,1,2},{1,1,1,1} +}; + +static uint8 envdecayvalue[0x3D][4] = { +/* 00-07 */ {1,1,1,1},{1,1,1,1},{1,1,1,1},{1,1,1,1},{1,1,1,1},{1,1,1,1},{1,1,1,1},{1,1,1,1}, +/* 08-0F */ {1,1,1,1},{1,1,1,1},{1,1,1,1},{1,1,1,1},{1,1,1,1},{1,1,1,1},{1,1,1,1},{1,1,1,1}, +/* 10-17 */ {1,1,1,1},{1,1,1,1},{1,1,1,1},{1,1,1,1},{1,1,1,1},{1,1,1,1},{1,1,1,1},{1,1,1,1}, +/* 18-1F */ {1,1,1,1},{1,1,1,1},{1,1,1,1},{1,1,1,1},{1,1,1,1},{1,1,1,1},{1,1,1,1},{1,1,1,1}, +/* 20-27 */ {1,1,1,1},{1,1,1,1},{1,1,1,1},{1,1,1,1},{1,1,1,1},{1,1,1,1},{1,1,1,1},{1,1,1,1}, +/* 28-2F */ {1,1,1,1},{1,1,1,1},{1,1,1,1},{1,1,1,1},{1,1,1,1},{1,1,1,1},{1,1,1,1},{1,1,1,1}, +/* 30-37 */ {1,1,1,1},{2,1,1,1},{2,1,2,1},{2,2,2,1},{2,2,2,2},{4,2,2,2},{4,2,4,2},{4,4,4,2}, +/* 38-3C */ {4,4,4,4},{8,4,4,4},{8,4,8,4},{8,8,8,4},{8,8,8,8} +}; + +static sint32 adpcmscale[8] = { + 0x0E6, 0x0E6, 0x0E6, 0x0E6, 0x133, 0x199, 0x200, 0x266 +}; + +static sint32 adpcmdiff[16] = { + 1, 3, 5, 7, 9, 11, 13, 15, +-1,-3,-5,-7,-9,-11,-13,-15 +}; + +static sint32 qtable[32] = { +0x0E00,0x0E80,0x0F00,0x0F80, +0x1000,0x1080,0x1100,0x1180, +0x1200,0x1280,0x1300,0x1280, +0x1400,0x1480,0x1500,0x1580, +0x1600,0x1680,0x1700,0x1780, +0x1800,0x1880,0x1900,0x1980, +0x1A00,0x1A80,0x1B00,0x1B80, +0x1C00,0x1D00,0x1E00,0x1F00 +}; + +// Lifted from MAME/etc cores by kode54, in an attempt to fix some stuff +//Envelope times in ms +#define LFO_SHIFT 8 + +struct _LFO +{ + unsigned short phase; + uint32 phase_step; + int *table; + int *scale; +}; + +#define LFIX(v) ((unsigned int) ((float) (1<>0x0)&0xff; + int iPAN=(i>>0x8)&0x1f; + int iSDL=(i>>0xD)&0x07; + float TL=1.0; + float SegaDB=0; + float fSDL=1.0; + float PAN=1.0; + float LPAN,RPAN; + + if(iTL&0x01) SegaDB-=0.4; + if(iTL&0x02) SegaDB-=0.8; + if(iTL&0x04) SegaDB-=1.5; + if(iTL&0x08) SegaDB-=3; + if(iTL&0x10) SegaDB-=6; + if(iTL&0x20) SegaDB-=12; + if(iTL&0x40) SegaDB-=24; + if(iTL&0x80) SegaDB-=48; + + TL=pow(10.0,SegaDB/20.0); + + SegaDB=0; + if(iPAN&0x1) SegaDB-=3; + if(iPAN&0x2) SegaDB-=6; + if(iPAN&0x4) SegaDB-=12; + if(iPAN&0x8) SegaDB-=24; + + if((iPAN&0xf)==0xf) PAN=0.0; + else PAN=pow(10.0,SegaDB/20.0); + + if(iPAN<0x10) + { + LPAN=PAN; + RPAN=1.0; + } + else + { + RPAN=PAN; + LPAN=1.0; + } + + if(iSDL) + fSDL=pow(10.0,(SDLT_SCSP[iSDL])/20.0); + else + fSDL=0.0; + + LPANTABLE_SCSP[i]=FIX((4.0*LPAN*TL*fSDL)); + RPANTABLE_SCSP[i]=FIX((4.0*RPAN*TL*fSDL)); + } + + for(i=0;i<0x20000;++i) { + int iTL =(i>>0x0)&0xff; + int iPAN=(i>>0x8)&0x1f; + int iSDL=(i>>0xD)&0x0F; + float TL=1.0; + float SegaDB=0; + float fSDL=1.0; + float PAN=1.0; + float LPAN,RPAN; + + if(iTL&0x01) SegaDB-=0.4; + if(iTL&0x02) SegaDB-=0.8; + if(iTL&0x04) SegaDB-=1.5; + if(iTL&0x08) SegaDB-=3; + if(iTL&0x10) SegaDB-=6; + if(iTL&0x20) SegaDB-=12; + if(iTL&0x40) SegaDB-=24; + if(iTL&0x80) SegaDB-=48; + + TL=pow(10.0,SegaDB/20.0); + + SegaDB=0; + if(iPAN&0x1) SegaDB-=3; + if(iPAN&0x2) SegaDB-=6; + if(iPAN&0x4) SegaDB-=12; + if(iPAN&0x8) SegaDB-=24; + + if((iPAN&0xf)==0xf) PAN=0.0; + else PAN=pow(10.0,SegaDB/20.0); + + if(iPAN<0x10) + { + LPAN=PAN; + RPAN=1.0; + } + else + { + RPAN=PAN; + LPAN=1.0; + } + + if(iSDL) + fSDL=pow(10.0,(SDLT_AICA[iSDL])/20.0); + else + fSDL=0.0; + + LPANTABLE_AICA[i]=FIX((4.0*LPAN*TL*fSDL)); + RPANTABLE_AICA[i]=FIX((4.0*RPAN*TL*fSDL)); + } + + ARTABLE[0]=DRTABLE[0]=0; //Infinite time + ARTABLE[1]=DRTABLE[1]=0; //Infinite time + for(i=2;i<64;++i) { + double t,step,scale; + t=ARTimes[i]; //In ms + if(t!=0.0) { + step=(1023*1000.0)/((float) 44100.0f*t); + scale=(double) (1<t_0rrrrrrr )) << 56; // TRA + value |= ((uint64)(mpro->t_Twwwwwww ^ 0x80)) << 48; // !TWT, TWA + value |= ((uint64)(mpro->tablemask & 1)) << 31; // TABLE + value |= ((uint64)(mpro->adrmask & 1)) << 1; // ADREB + value |= ((uint64)(mpro->negb & 1)) << 18; // NEGB + { uint64 sh = mpro->m_wrAFyyYh & 1; + if((mpro->__kisxzbon & 0x20) == 0) { sh ^= 3; } + value |= (sh << 20); // SHFT + } + value |= ((uint64)(mpro->__kisxzbon & 0x10)) << 43; // XSEL + value |= ((uint64)(mpro->__kisxzbon & 0x0C)) << 14; // ZERO, BSEL + value |= ((uint64)(mpro->__kisxzbon & 0x02)) << 6; // NOFL *** THIS IS JUST A GUESS *** + value |= ((uint64)(mpro->__kisxzbon & 0x01)) << 0; // NXADR + value |= ((uint64)(mpro->m_wrAFyyYh & 0xC0)) << 23; // MWT, MRD + value |= ((uint64)(mpro->m_wrAFyyYh & 0x32)) << 18; // ADRL, FRCL, YRL + value |= ((uint64)(mpro->m_wrAFyyYh & 0x0C)) << 43; // YSEL + value |= ((uint64)(mpro->i_00rrrrrr & 0x3F)) << 38; // IRA + value |= ((uint64)(mpro->i_0T0wwwww & 0x1F)) << 32; // IWA + value |= ((uint64)((mpro->i_0T0wwwww & 0x40) ^ 0x40)) << 31; // !IWT + value |= ((uint64)((mpro->e_000Twwww & 0x1F) ^ 0x10)) << 24; // !EWT, EWA + value |= ((uint64)(mpro->m_00aaaaaa & 0x1F)) << 2; // MASA (fewer bits on SCSP) + value |= ((uint64)(mpro->c_0rrrrrrr & 0x3F)) << 9; // CRA (SCSP exclusive) + + return value; +} + +static void mpro_scsp_write(struct MPRO *mpro, uint64 value) { + mpro->t_0rrrrrrr = ((value >> 56) & 0x7F); // TRA + mpro->t_Twwwwwww = ((value >> 48) ^ 0x80); // !TWT, TWA + mpro->tablemask = ((value >> 31) & 1) ? (-1) : (0); // TABLE + mpro->adrmask = ((value >> 1) & 1) ? (-1) : (0); // ADREB + mpro->negb = ((value >> 18) & 1) ? (-1) : (0); // NEGB + mpro->__kisxzbon = 0; + if(!value) { mpro->__kisxzbon |= 0x80; } // skip + if(((value >> 20) & 3) == 3) { mpro->__kisxzbon |= 0x40; } // interpolate + if(((value >> 21) & 1) == 0) { mpro->__kisxzbon |= 0x20; } // saturate + mpro->__kisxzbon |= (value >> 43) & 0x10; // XSEL + mpro->__kisxzbon |= (value >> 14) & 0x0C; // ZERO, BSEL + mpro->__kisxzbon |= (value >> 6) & 0x02; // NOFL *** THIS IS JUST A GUESS *** + mpro->__kisxzbon |= (value >> 0) & 1; // NXADR + mpro->m_wrAFyyYh = (value >> 23) & 0xC0; // MWT, MRD + mpro->m_wrAFyyYh |= (value >> 18) & 0x32; // ADRL, FRCL, YRL + mpro->m_wrAFyyYh |= (value >> 43) & 0x0C; // YSEL + mpro->m_wrAFyyYh |= ((value >> 20) & 1) ^ ((value >> 21) & 1); // shift left by + mpro->i_00rrrrrr = (value >> 38) & 0x3F; // IRA + mpro->i_0T0wwwww = (value >> 32) & 0x1F; // IWA + mpro->i_0T0wwwww |= ((value >> 31) & 0x40) ^ 0x40; // !IWT + mpro->e_000Twwww = ((value >> 24) & 0x1F) ^ 0x10; // !EWT, EWA + mpro->m_00aaaaaa = (value >> 2) & 0x1F; // MASA (fewer bits on SCSP) + mpro->c_0rrrrrrr = (value >> 9) & 0x3F; // CRA (SCSP exclusive) +} + +static void mpro_aica_write(struct MPRO *mpro, uint64 value) { + mpro->t_0rrrrrrr = ((value >> 57) & 0x7F); // TRA + mpro->t_Twwwwwww = ((value >> 49) ^ 0x80); // !TWT, TWA + mpro->tablemask = ((value >> 31) & 1) ? (-1) : (0); // TABLE + mpro->adrmask = ((value >> 8) & 1) ? (-1) : (0); // ADREB + mpro->negb = ((value >> 18) & 1) ? (-1) : (0); // NEGB + mpro->__kisxzbon = 0; + if(!value) { mpro->__kisxzbon |= 0x80; } // skip + if(((value >> 20) & 3) == 3) { mpro->__kisxzbon |= 0x40; } // interpolate + if(((value >> 21) & 1) == 0) { mpro->__kisxzbon |= 0x20; } // saturate + mpro->__kisxzbon |= (value >> 43) & 0x10; // XSEL + mpro->__kisxzbon |= (value >> 14) & 0x0E; // ZERO, BSEL, NOFL + mpro->__kisxzbon |= (value >> 7) & 1; // NXADR + mpro->m_wrAFyyYh = (value >> 23) & 0xC0; // MWT, MRD + mpro->m_wrAFyyYh |= (value >> 18) & 0x32; // ADRL, FRCL, YRL + mpro->m_wrAFyyYh |= (value >> 43) & 0x0C; // YSEL + mpro->m_wrAFyyYh |= ((value >> 20) & 1) ^ ((value >> 21) & 1); // shift left by + mpro->i_00rrrrrr = (value >> 39) & 0x3F; // IRA + mpro->i_0T0wwwww = (value >> 33) & 0x1F; // IWA + mpro->i_0T0wwwww |= ((value >> 32) & 0x40) ^ 0x40; // !IWT + mpro->e_000Twwww = ((value >> 24) & 0x1F) ^ 0x10; // !EWT, EWA + mpro->m_00aaaaaa = (value >> 9) & 0x3F; // MASA +} + +static uint64 mpro_aica_read(struct MPRO *mpro) { + uint64 value = 0; + value |= ((uint64)(mpro->t_0rrrrrrr )) << 57; // TRA + value |= ((uint64)(mpro->t_Twwwwwww ^ 0x80)) << 49; // !TWT, TWA + value |= ((uint64)(mpro->tablemask & 1)) << 31; // TABLE + value |= ((uint64)(mpro->adrmask & 1)) << 8; // ADREB + value |= ((uint64)(mpro->negb & 1)) << 18; // NEGB + { uint64 sh = mpro->m_wrAFyyYh & 1; + if((mpro->__kisxzbon & 0x20) == 0) { sh ^= 3; } + value |= (sh << 20); // SHFT + } + value |= ((uint64)(mpro->__kisxzbon & 0x10)) << 43; // XSEL + value |= ((uint64)(mpro->__kisxzbon & 0x0E)) << 14; // ZERO, BSEL, NOFL + value |= ((uint64)(mpro->__kisxzbon & 0x01)) << 7; // NXADR + value |= ((uint64)(mpro->m_wrAFyyYh & 0xC0)) << 23; // MWT, MRD + value |= ((uint64)(mpro->m_wrAFyyYh & 0x32)) << 18; // ADRL, FRCL, YRL + value |= ((uint64)(mpro->m_wrAFyyYh & 0x0C)) << 43; // YSEL + value |= ((uint64)(mpro->i_00rrrrrr & 0x3F)) << 39; // IRA + value |= ((uint64)(mpro->i_0T0wwwww & 0x1F)) << 33; // IWA + value |= ((uint64)((mpro->i_0T0wwwww & 0x40) ^ 0x40)) << 32; // !IWT + value |= ((uint64)((mpro->e_000Twwww & 0x1F) ^ 0x10)) << 24; // !EWT, EWA + value |= ((uint64)(mpro->m_00aaaaaa & 0x3F)) << 9; // MASA + return value; +} + +#define DYNACODE_MAX_SIZE (0x6000) +#define DYNACODE_SLOP_SIZE (0x80) + +struct YAM_STATE { + // + // Misc. + // + uint32 version; + void *ram_ptr; // EXTERNALLY-REGISTERED pointer + uint32 ram_mask; + sint16 *out_buf; // EXTERNALLY-REGISTERED pointer + uint32 out_pending; + uint32 odometer; + uint8 dry_out_enabled; + uint8 dsp_emulation_enabled; +#ifdef ENABLE_DYNAREC + uint8 dsp_dyna_enabled; + uint8 dsp_dyna_valid; +#endif + uint32 randseed; + uint32 mem_word_address_xor; + uint32 mem_byte_address_xor; + // + // Common regs + // + uint8 efsdl[18]; + uint8 efpan[18]; + uint8 mono; + uint8 mvol; + uint32 rbp; + uint8 rbl; + uint8 afsel; + uint8 mslc; + uint8 mrwinh; + uint8 tctl[3], tim[3]; + uint16 mcieb, mcipd; + uint16 scieb, scipd; + uint8 scilv0, scilv1, scilv2; + uint8 inton, intreq; + uint32 rtc; + // + // DSP regs + // + sint16 coef[128]; // stored as 13-bit + uint16 madrs[64]; + struct MPRO mpro[128]; + sint32 temp[128]; + // INPUTS all pre-promoted to 24-bit + // 0x00-0x1F: MEMS + // 0x20-0x2F: MIXS + // 0x30-0x31: EXTS + // 0x32-0x3F: always zero + // 0x40-0x5F: slop area to handle IWTA + sint32 inputs[0x60]; + // EFREG + // 0x00-0x0F: EFREG + // 0x10-0x1F: slop area to handle EWTA + sint16 efreg[0x20]; + uint32 mdec_ct; + uint32 adrs_reg; + + sint32 xzbchoice[5]; +#define XZBCHOICE_TEMP (0) +#define XZBCHOICE_ACC (1) +#define XZBCHOICE_ZERO (2) +#define XZBCHOICE_ZERO_ACC (3) +#define XZBCHOICE_INPUTS (4) + + sint32 yychoice[4]; +#define YYCHOICE_FRC_REG (0) +#define YYCHOICE_COEF (1) +#define YYCHOICE_Y_REG_H (2) +#define YYCHOICE_Y_REG_L (3) + + sint32 mem_in_data[4]; + + // SCSP modulation data + sint16 ringbuf[32*RINGMAX]; + uint32 bufptr; + // DMA registers + uint32 dmea; + uint16 drga; + uint16 dtlg; + // + // Channel regs + // + struct YAM_CHAN chan[64]; + // + // Buffer for dynarec code + // +#ifdef ENABLE_DYNAREC + uint8 dynacode[DYNACODE_MAX_SIZE]; +#endif +}; + +// +// Get size +// +uint32 EMU_CALL yam_get_state_size(uint8 version) { + return sizeof(struct YAM_STATE); +} + +// +// Initialize DSP state +// +void EMU_CALL yam_clear_state(void *state, uint8 version) { + int i; + if(version != 2) { version = 1; } + // Clear to zero + memset(state, 0, sizeof(struct YAM_STATE)); + // Set version + YAMSTATE->version = version; + // Clear channel regs + for(i = 0; i < 64; i++) { + YAMSTATE->chan[i].EG.state = RELEASE; + YAMSTATE->chan[i].lpfstate = 3; + YAMSTATE->chan[i].eghold = 0; + YAMSTATE->chan[i].lpflevel = 0x1FFF; + // no lowpass on the SCSP + if(version == 1) { YAMSTATE->chan[i].lpoff = 1; } + } + // Initialize MPRO + for(i = 0; i < 128; i++) { + switch(version) { + case 1: + mpro_scsp_write((YAMSTATE->mpro) + i, 0); + break; + case 2: + YAMSTATE->mpro[i].c_0rrrrrrr = i; + mpro_aica_write((YAMSTATE->mpro) + i, 0); + break; + } + } + // Enable dry output + YAMSTATE->dry_out_enabled = 1; + + // Enable DSP emulation by default + YAMSTATE->dsp_emulation_enabled = 1; + + // Enable DSP dynarec +#ifdef ENABLE_DYNAREC + YAMSTATE->dsp_dyna_enabled = 1; +#endif +} + +///////////////////////////////////////////////////////////////////////////// +// +// Ugly hack to log debug output +// +/* +FILE *logfile = NULL; + +static void logf(const char *fmt, ...) { + va_list a; + va_start(a, fmt); + if(!logfile) { + logfile=fopen("C:\\Corlett\\yam.log","wb"); + } + if(logfile) { vfprintf(logfile, fmt, a); fflush(logfile); } +} + +static void logupdate(struct YAM_STATE *state) { + int i; + logf("log update\n"); +// for(i=0;i<10;i++) { +// logf("mpro %d: %08X %08X\n",i,state->mpro32[2*i+0],state->mpro32[2*i+1]); +// } + for(i = 0; i < 64; i++) { + logf("chan %d: dsp %X level %X\n",i,state->chan[i].dspchan,state->chan[i].dsplevel); + } + for(i = 0; i < 16; i++) { + logf("efsdl %d: %X pan %X\n",i,state->efsdl[i],state->efpan[i]); + } +} + +static void logstep(struct YAM_STATE *state, uint32 odometer) { + static uint32 lastodometer = 0; + if((odometer/50000) > (lastodometer/50000)) { + lastodometer = odometer; + logupdate(state); + } +} + +static int st = 0; + +static void dumpch(struct YAM_STATE *state, struct YAM_CHAN *chan) { + logf("st=%u (%us) envstate=%X level=%X\n",st,st/44100,chan->envstate,chan->envlevel); + logf(" playpos=%X ls=%X le=%X\n",chan->playpos,chan->loopstart,chan->loopend); + logf(" sample=%X tl=%X oct=%X fns=%X\n",chan->sampleaddr, chan->tl,chan->oct,chan->fns); + logf(" rbp=%X rbl=%X\n",state->rbp,state->rbl); +} +*/ +///////////////////////////////////////////////////////////////////////////// +// +// Set RAM pointer and size (must be a power of 2) +// +void EMU_CALL yam_setram(void *state, uint32 *ram, uint32 size, uint8 mbx, uint8 mwx) { + YAMSTATE->ram_ptr = ram; + if((size & (size-1)) == 0) { + YAMSTATE->ram_mask = size-1; + } else { + YAMSTATE->ram_mask = 0; + } + YAMSTATE->mem_byte_address_xor = mbx; + YAMSTATE->mem_word_address_xor = mwx; + // + // Invalidate dynarec code + // +#ifdef ENABLE_DYNAREC + YAMSTATE->dsp_dyna_valid = 0; +#endif +} + +///////////////////////////////////////////////////////////////////////////// +// +// Set output buffer pointer and begin new execution run +// +void EMU_CALL yam_beginbuffer(void *state, sint16 *buf) { + YAMSTATE->out_buf = buf; + YAMSTATE->out_pending = 0; +} + +///////////////////////////////////////////////////////////////////////////// +// +// Enable or disable various things +// +void EMU_CALL yam_enable_dry(void *state, uint8 enable) { + YAMSTATE->dry_out_enabled = (enable != 0); +} + +void EMU_CALL yam_enable_dsp(void *state, uint8 enable) { + YAMSTATE->dsp_emulation_enabled = (enable != 0); +#ifdef ENABLE_DYNAREC + if(enable == 0) { YAMSTATE->dsp_dyna_valid = 0; } +#endif +} + +void EMU_CALL yam_enable_dsp_dynarec(void *state, uint8 enable) { +#ifdef ENABLE_DYNAREC + YAMSTATE->dsp_dyna_enabled = (enable != 0); + if(enable == 0) { YAMSTATE->dsp_dyna_valid = 0; } +#endif +} + +///////////////////////////////////////////////////////////////////////////// +// +// Timers / interrupts +// + +// +// Recompute intreq +// +static void sci_recompute(struct YAM_STATE *state) { + int i; + uint16 scipd = (state->scipd) & (state->scieb); + state->inton = 0; + for(i = 10; i >= 0; i--) { + if(((scipd) >> i) & 1) { + if(i > 7) i = 7; + state->intreq = + ((((state->scilv0) >> i) & 1) << 0) | + ((((state->scilv1) >> i) & 1) << 1) | + ((((state->scilv2) >> i) & 1) << 2); + state->inton = state->intreq; + return; + } + } +} + +// +// Signal an interrupt +// +static void sci_signal(struct YAM_STATE *state, int n) { + state->scipd |= (1 << n); + if(!(state->inton)) { + sci_recompute(state); + } +} + +uint8* EMU_CALL yam_get_interrupt_pending_ptr(void *state) { + return &(YAMSTATE->inton); +} + +// +// Determine how many samples until the next interrupt +// +uint32 EMU_CALL yam_get_min_samples_until_interrupt(void *state) { + uint32 min = 0xFFFFFFFF; + uint32 t, samples; + +//return 1; + + for(t = 0; t < 3; t++) { + if(YAMSTATE->scieb & (1 << (INT_TIMER_A + t))) { + samples = 0x100-((uint32)(YAMSTATE->tim[t])); + samples <<= YAMSTATE->tctl[t]; + samples -= (YAMSTATE->odometer) & ((1<tctl[t])-1); + if(samples < min) { min = samples; } + } + } +//printf("yam min: ta=%X %02X tb=%X %02X tc=%X %02X min=%u\n",YAMSTATE->tctl[0],YAMSTATE->tim[0],YAMSTATE->tctl[1],YAMSTATE->tim[1],YAMSTATE->tctl[2],YAMSTATE->tim[2],min); +// min should never be 1 if the above is correct +// if(min < 1) { min = 1; } + return min; +} + +///////////////////////////////////////////////////////////////////////////// +// +// Advance timers and interrupts +// +void EMU_CALL yam_advance(void *state, uint32 samples) { + uint32 t; +//printf("yam_advance(%u)",samples); + for(t = 0; t < 3; t++) { + uint8 scale = YAMSTATE->tctl[t]; + uint32 whole = YAMSTATE->tim[t]; + uint32 frac = (YAMSTATE->odometer) & ((1<= remain) { sci_signal(state, INT_TIMER_A + t); } + YAMSTATE->tim[t] = ((frac + samples + (whole << scale)) >> scale) & 0xFF; + } + YAMSTATE->out_pending += samples; + YAMSTATE->odometer += samples; +} + +///////////////////////////////////////////////////////////////////////////// +// +// Envelope calculation +// +static int Get_AR(int base,int R) +{ + int Rate=base+(R<<1); + if(Rate>63) Rate=63; + if(Rate<0) Rate=0; + return ARTABLE[Rate]; +} + +static int Get_DR(int base,int R) +{ + int Rate=base+(R<<1); + if(Rate>63) Rate=63; + if(Rate<0) Rate=0; + return DRTABLE[Rate]; +} + +static int Get_RR(int base,int R) +{ + int Rate=base+(R<<1); + if(Rate>63) Rate=63; + if(Rate<0) Rate=0; + return DRTABLE[Rate]; +} + +static void Compute_EG(struct YAM_CHAN *chan) +{ + int octave=chan->oct; + int rate; + if(octave&8) octave=octave-16; + if(chan->krs!=0xf) + rate=octave+2*chan->krs+((chan->fns>>9)&1); + else + rate=0; //rate=((FNS(slot)>>9)&1); + + chan->EG.volume=0x17F<EG.AR=Get_AR(rate,chan->ar[0]); + chan->EG.D1R=Get_DR(rate,chan->ar[1]); + chan->EG.D2R=Get_DR(rate,chan->ar[2]); + chan->EG.RR=Get_RR(rate,chan->ar[3]); + chan->EG.DL=0x1f-chan->dl; + chan->EG.EGHOLD=chan->eghold; +} + +static void keyoff(struct YAM_CHAN *chan, int keyoff); + +static int EG_Update(struct YAM_CHAN *chan) +{ + switch(chan->EG.state) { + case ATTACK: + chan->EG.volume+=chan->EG.AR; + if(chan->EG.volume>=(0x3ff<link) { + chan->EG.state=DECAY1; + if(chan->EG.D1R>=(1024<EG.state=DECAY2; + } + chan->EG.volume=0x3ff<EG.EGHOLD) +#if SHIFT >= 10 + return 0x3ff<<(SHIFT-10); +#else + return 0x3ff>>(10-SHIFT); +#endif + break; + case DECAY1: + chan->EG.volume-=chan->EG.D1R; + if(chan->EG.volume<=0) + chan->EG.volume=0; + if(chan->EG.volume>>(EG_SHIFT+5)<=chan->EG.DL) + chan->EG.state=DECAY2; + break; + case DECAY2: + if(chan->ar[2]==0) +#if SHIFT >= 10 + return (chan->EG.volume>>EG_SHIFT)<<(SHIFT-10); +#else + return (chan->EG.volume>>EG_SHIFT)>>(10-SHIFT); +#endif + chan->EG.volume-=chan->EG.D2R; + if(chan->EG.volume<=0) + chan->EG.volume=0; + break; + case RELEASE: + chan->EG.volume-=chan->EG.RR; + if(chan->EG.volume<=0) { + chan->EG.volume=0; + keyoff(chan, 0); + } + break; + default: + return 1<= 10 + return (chan->EG.volume>>EG_SHIFT)<<(SHIFT-10); +#else + return (chan->EG.volume>>EG_SHIFT)>>(10-SHIFT); +#endif +} + +static uint32 AICA_Step(struct YAM_CHAN *chan) +{ + int octave=chan->oct; + uint32 Fn; + + Fn=(FNS_Table[chan->fns]); //24.8 + if(octave&8) + Fn>>=(16-octave); + else + Fn<<=octave; + + return Fn/(44100); +} + +static signed int PLFO_Step(struct _LFO *LFO) +{ + int p; + LFO->phase+=LFO->phase_step; +#if LFO_SHIFT!=8 + LFO->phase&=(1<<(LFO_SHIFT+8))-1; +#endif + p=LFO->table[LFO->phase>>LFO_SHIFT]; + p=LFO->scale[p+128]; + return p<<(SHIFT-LFO_SHIFT); +} + +static signed int ALFO_Step(struct _LFO *LFO) +{ + int p; + LFO->phase+=LFO->phase_step; +#if LFO_SHIFT!=8 + LFO->phase&=(1<<(LFO_SHIFT+8))-1; +#endif + p=LFO->table[LFO->phase>>LFO_SHIFT]; + p=LFO->scale[p]; + return p<<(SHIFT-LFO_SHIFT); +} + +static void LFO_ComputeStep(struct _LFO *LFO,sint32 LFOF,sint32 LFOWS,sint32 LFOS,int ALFO) +{ + float step=(float) LFOFreq[LFOF]*256.0/(float)44100.0; + LFO->phase_step=(unsigned int) ((float) (1<table=ALFO_SAW; break; + case 1: LFO->table=ALFO_SQR; break; + case 2: LFO->table=ALFO_TRI; break; + case 3: LFO->table=ALFO_NOI; break; + } + LFO->scale=ASCALES[LFOS]; + } + else { + switch(LFOWS) + { + case 0: LFO->table=PLFO_SAW; break; + case 1: LFO->table=PLFO_SQR; break; + case 2: LFO->table=PLFO_TRI; break; + case 3: LFO->table=PLFO_NOI; break; + } + LFO->scale=PSCALES[LFOS]; + } +} + +static void Compute_LFO(struct YAM_CHAN *chan) +{ + if(chan->plfos!=0) + LFO_ComputeStep(&(chan->PLFO),chan->lfof,chan->plfows,chan->plfos,0); + if(chan->alfos!=0) + LFO_ComputeStep(&(chan->ALFO),chan->lfof,chan->alfows,chan->alfos,1); +} + +#define ADPCMSHIFT 8 +#define ADFIX(f) (int) ((float) f*(float) (1<>31)^0x7FFF):(x)) + +static signed short DecodeADPCM(int *PrevSignal, unsigned char Delta, int *PrevQuant) +{ + int x = *PrevQuant * quant_mul [Delta & 15]; + x = *PrevSignal + ((int)(x + ((uint32)x >> 29)) >> 3); + *PrevSignal=ICLIP16(x); + *PrevQuant=(*PrevQuant*TableQuant[Delta&7])>>ADPCMSHIFT; + *PrevQuant=(*PrevQuant<0x7f)?0x7f:((*PrevQuant>0x6000)?0x6000:*PrevQuant); + return *PrevSignal; +} + +///////////////////////////////////////////////////////////////////////////// +// +// Key on/off +// +static void keyon(struct YAM_STATE *state, struct YAM_CHAN *chan) { +//printf("keyon %08X\n",chan); + // Ignore redundant key-ons + if(chan->EG.state != RELEASE) return; + chan->cur_addr = 0; + chan->nxt_addr = 1 << SHIFT; + chan->Backwards=0; + chan->step=AICA_Step(chan); + chan->lpflevel = chan->flv[0]; + chan->lpfstate = 0; + chan->samplebufcur = 0; + chan->samplebufnext = 0; + Compute_EG(chan); + chan->EG.state=ATTACK; + chan->EG.volume=0x17F<pcms >= 2) + { + uint8 *base; + uint32 adbase; + uint32 curstep, steps_to_go; + + chan->curstep = 0; + chan->adbase = chan->sampleaddr & state->ram_mask; + InitADPCM(&(chan->cur_sample), &(chan->cur_quant)); + InitADPCM(&(chan->cur_lpsample), &(chan->cur_lpquant)); + + // walk to the ADPCM state at LSA + curstep = 0; + base = ((uint8*)state->ram_ptr); + adbase = chan->adbase; + steps_to_go = chan->loopstart; + + while (curstep < steps_to_go) { + int shift1, delta1; + shift1 = 4*((curstep&1)); + delta1 = (base[adbase]>>shift1)&0xf; + DecodeADPCM(&(chan->cur_lpsample),delta1,&(chan->cur_lpquant)); + curstep++; + if (!(curstep & 1)) { + adbase = (adbase + 1) & state->ram_mask; + } + } + + chan->cur_lpstep = curstep; + chan->adlpbase = adbase; + + // on real hardware this creates undefined behavior. + if (chan->loopstart > chan->loopend) { + chan->loopend = 0xFFFF; + } + } +} + +static void keyoff(struct YAM_CHAN *chan,int keyoff) { + chan->EG.state = RELEASE; + chan->lpfstate = 3; + if(!keyoff) chan->EG.volume = 0; + chan->kyonb = 0; +} + +///////////////////////////////////////////////////////////////////////////// +// +// Channel registers +// +static uint32 chan_scsp_load_reg(struct YAM_STATE *state, uint8 ch, uint8 a) { + struct YAM_CHAN *chan = state->chan + (((uint32)ch) & 0x1F); + uint16 d = 0; + // don't really need a flush for loading chan regs + switch(a & 0x1E) { + case 0x00: // PlayControl + d = (((uint32)(chan->kyonb )) & 0x0001) << 11; + d |= (((uint32)(chan->sampler_invert )) & 0xC000) >> 5; + d |= (((uint32)(chan->ssctl )) & 0x0003) << 7; + d |= (((uint32)(chan->sampler_looptype)) & 0x0003) << 5; + d |= (((uint32)(chan->pcms )) & 0x0001) << 4; + d |= ((chan->sampleaddr) >> 16) & 0xF; + break; + case 0x02: // SampleAddrLow + d = chan->sampleaddr; + break; + case 0x04: // LoopStart + d = chan->loopstart; + break; + case 0x06: // LoopEnd + d = chan->loopend; + break; + case 0x08: // AmpEnv1 + d = (((uint32)(chan->ar[2] )) & 0x001F) << 11; + d |= (((uint32)(chan->ar[1] )) & 0x001F) << 6; + d |= (((uint32)(chan->eghold )) & 1) << 5; + d |= (((uint32)(chan->ar[0] )) & 0x001F) << 0; + break; + case 0x0A: // AmpEnv2 + d = (((uint32)(chan->link )) & 0x0001) << 14; + d |= (((uint32)(chan->krs )) & 0x000F) << 10; + d |= (((uint32)(chan->dl )) & 0x001F) << 5; + d |= (((uint32)(chan->ar[3] )) & 0x001F) << 0; + break; + case 0x0C: // TotalLevel + d = (((uint32)(chan->stwinh )) & 0x0001) << 9; + d |= (((uint32)(chan->voff )) & 0x0001) << 8; + d |= (((uint32)(chan->tl )) & 0x00FF) << 0; + break; + case 0x0E: // Modulation + d = (((uint32)(chan->mdl )) & 0x000F) << 12; + d |= (((uint32)(chan->mdxsl )) & 0x003F) << 6; + d |= (((uint32)(chan->mdysl )) & 0x003F) << 0; + break; + case 0x10: // SampleRatePitch + d = (((uint32)(chan->oct )) & 0x000F) << 11; + d |= (((uint32)(chan->fns )) & 0x07FF) << 0; + break; + case 0x12: // LFOControl + d = (((uint32)(chan->lfore )) & 0x0001) << 15; + d |= (((uint32)(chan->lfof )) & 0x001F) << 10; + d |= (((uint32)(chan->plfows )) & 0x0003) << 8; + d |= (((uint32)(chan->plfos )) & 0x0007) << 5; + d |= (((uint32)(chan->alfows )) & 0x0003) << 3; + d |= (((uint32)(chan->alfos )) & 0x0007) << 0; + break; + case 0x14: // DSPInputSelect + d = (((uint32)(chan->dspchan )) & 0x000F) << 3; + d |= (((uint32)(chan->dsplevel )) & 0x0007) >> 0; + break; + case 0x16: // SendLevels + d = (((uint32)(chan->disdl )) & 0x0007) << 13; + d |= (((uint32)(chan->dipan )) & 0x001F) << 8; + if(ch < 18) { + d |= (((uint32)(state->efsdl[ch])) & 0x07) << 5; + d |= (((uint32)(state->efpan[ch])) & 0x1F) << 0; + } + break; + } + return d; +} + +static void chan_scsp_store_reg(struct YAM_STATE *state, uint8 ch, uint8 a, uint32 d, uint32 mask) { + struct YAM_CHAN *chan; + a &= 0x1E; + if(a >= 0x18) return; + yam_flush(YAMSTATE); + chan = state->chan + (((uint32)ch) & 0x1F); + switch(a & 0x1E) { + case 0x00: // PlayControl + if(mask & 0x00FF) { + chan->sampleaddr &= 0xFFFF; + chan->sampleaddr |= (((uint32)d) & 0xF) << 16; + chan->pcms = (d >> 4) & 1; + chan->sampler_looptype = (d >> 5) & 3; + chan->ssctl &= 2; + chan->ssctl |= (d >> 7) & 1; + } + if(mask & 0xFF00) { + chan->ssctl &= 1; + chan->ssctl |= (d >> 7) & 2; + chan->sampler_invert = 0; + if(d & (1<< 9)) chan->sampler_invert |= 0x00007FFF; + if(d & (1<<10)) chan->sampler_invert |= 0xFFFF8000; + chan->kyonb = (d >> 11) & 1; + if(d & 0x1000) { // kyonex + int ch; +//for(ch=0;ch<32;ch++){printf("%d",state->chan[ch].envstate);}printf("\n"); + for(ch = 0; ch < 32; ch++) { + if(state->chan[ch].kyonb) { +//printf("*"); + keyon(state, state->chan + ch); + } else { +//printf("."); + keyoff(state->chan + ch, 1); + } + } +//printf("\n"); +//for(ch=0;ch<32;ch++){printf("%d",state->chan[ch].envstate);}printf("\n"); + } + } + break; + case 0x02: // SampleAddrLow + chan->sampleaddr &= (0xFFFFF ^ mask); + chan->sampleaddr |= (d & mask); + break; + case 0x04: // LoopStart + chan->loopstart &= (0xFFFF ^ mask); + chan->loopstart |= (d & mask); + break; + case 0x06: // LoopEnd + chan->loopend &= (0xFFFF ^ mask); + chan->loopend |= (d & mask); + break; + case 0x08: // AmpEnv1 + if(mask & 0x00FF) { + chan->ar[0] = d & 0x1F; + chan->eghold = !!(d & (1<<5)); +// chan->envlevelmask[0] = 0x1FFF; + chan->ar[1] &= 0x1C; + chan->ar[1] |= (d >> 6) & 0x03; + } + if(mask & 0xFF00) { + chan->ar[1] &= 0x03; + chan->ar[1] |= (d >> 6) & 0x1C; + chan->ar[2] = (d >> 11) & 0x1F; + } + break; + case 0x0A: // AmpEnv2 + if(mask & 0x00FF) { + chan->ar[3] = d & 0x1F; + chan->dl &= 0x18; + chan->dl |= (d >> 5) & 0x07; + } + if(mask & 0xFF00) { + chan->dl &= 0x07; + chan->dl |= (d >> 5) & 0x18; + chan->krs = (d >> 10) & 0xF; + chan->link = (d >> 14) & 1; + } + break; + case 0x0C: // TotalLevel + if(mask & 0x00FF) { + chan->tl = d & 0xFF; + } + if(mask & 0xFF00) { + chan->voff = (d >> 8) & 1; + chan->stwinh = (d >> 9) & 1; + } + break; + case 0x0E: // Modulation + if(mask & 0x00FF) { + chan->mdysl = d & 0x3F; + chan->mdxsl &= 0x3C; + chan->mdxsl |= (d >> 6) & 0x03; + } + if(mask & 0xFF00) { + chan->mdxsl &= 0x03; + chan->mdxsl |= (d >> 6) & 0x3C; + chan->mdl = (d >> 12) & 0xF; + } + break; + case 0x10: // SampleRatePitch + if(mask & 0x00FF) { + chan->fns &= 0x700; + chan->fns |= d & 0x0FF; + } + if(mask & 0xFF00) { + chan->fns &= 0x0FF; + chan->fns |= d & 0x700; + chan->oct = (d >> 11) & 0xF; + } + chan->step = AICA_Step(chan); + break; + case 0x12: // LFOControl + if(mask & 0x00FF) { + chan->alfos = d & 7; + chan->alfows = (d >> 3) & 3; + chan->plfos = (d >> 5) & 7; + } + if(mask & 0xFF00) { + chan->plfows = (d >> 8) & 3; + chan->lfof = (d >> 10) & 0x1F; + chan->lfore = (d >> 15) & 1; + } + Compute_LFO(chan); + break; + case 0x14: // DSPInputSelect + if(mask & 0x00FF) { + chan->dsplevel = d & 0x7; + chan->dspchan = (d >> 3) & 0xF; + } + break; + case 0x16: // SendLevels + if(mask & 0x00FF) { + if(ch < 18) { + state->efpan[ch] = d & 0x1F; + state->efsdl[ch] = (d >> 5) & 0x7; + } + } + if(mask & 0xFF00) { + chan->dipan = (d >> 8) & 0x1F; + chan->disdl = (d >> 13) & 0x7; + } + break; + } +} + +static uint32 chan_aica_load_reg(struct YAM_STATE *state, uint8 ch, uint8 a) { + struct YAM_CHAN *chan = state->chan + (((uint32)ch) & 0x3F); + uint16 d = 0; + // don't really need a flush for loading chan regs + switch(a & 0x7C) { + case 0x00: // PlayControl + d = (((uint32)(chan->kyonb )) & 0x0001) << 14; + d |= (((uint32)(chan->ssctl )) & 0x0001) << 10; + d |= (((uint32)(chan->sampler_looptype)) & 0x0001) << 9; + d |= (((uint32)(chan->pcms )) & 0x0003) << 7; + d |= ((chan->sampleaddr) >> 16) & 0x7F; + break; + case 0x04: // SampleAddrLow + d = chan->sampleaddr; + break; + case 0x08: // LoopStart + d = chan->loopstart; + break; + case 0x0C: // LoopEnd + d = chan->loopend; + break; + case 0x10: // AmpEnv1 + d = (((uint32)(chan->ar[2] )) & 0x001F) << 11; + d |= (((uint32)(chan->ar[1] )) & 0x001F) << 6; + d |= (((uint32)(chan->ar[0] )) & 0x001F) << 0; + break; + case 0x14: // AmpEnv2 + d = (((uint32)(chan->link )) & 0x0001) << 14; + d |= (((uint32)(chan->krs )) & 0x000F) << 10; + d |= (((uint32)(chan->dl )) & 0x001F) << 5; + d |= (((uint32)(chan->ar[3] )) & 0x001F) << 0; + break; + case 0x18: // SampleRatePitch + d = (((uint32)(chan->oct )) & 0x000F) << 11; + d |= (((uint32)(chan->fns )) & 0x07FF) << 0; + break; + case 0x1C: // LFOControl + d = (((uint32)(chan->lfore )) & 0x0001) << 15; + d |= (((uint32)(chan->lfof )) & 0x001F) << 10; + d |= (((uint32)(chan->plfows )) & 0x0003) << 8; + d |= (((uint32)(chan->plfos )) & 0x0007) << 5; + d |= (((uint32)(chan->alfows )) & 0x0003) << 3; + d |= (((uint32)(chan->alfos )) & 0x0007) << 0; + break; + case 0x20: // DSPChannelSend + d = (((uint32)(chan->dsplevel )) & 0x000F) << 4; + d |= (((uint32)(chan->dspchan )) & 0x000F) << 0; + break; + case 0x24: // DirectPanVolSend + d = (((uint32)(chan->disdl )) & 0x000F) << 8; + d |= (((uint32)(chan->dipan )) & 0x001F) << 0; + break; + case 0x28: // LPF1Volume + d = (((uint32)(chan->tl )) & 0x00FF) << 8; + d |= (((uint32)(chan->voff )) & 0x0001) << 6; + d |= (((uint32)(chan->lpoff )) & 0x0001) << 5; + d |= (((uint32)(chan->q )) & 0x001F) << 0; + break; + case 0x2C: // LPF2 + d = (chan->flv[0]) & 0x1FFF; + break; + case 0x30: // LPF3 + d = (chan->flv[1]) & 0x1FFF; + break; + case 0x34: // LPF4 + d = (chan->flv[2]) & 0x1FFF; + break; + case 0x38: // LPF5 + d = (chan->flv[3]) & 0x1FFF; + break; + case 0x3C: // LPF6 + d = (chan->flv[4]) & 0x1FFF; + break; + case 0x40: // LPF7 + d = (((uint32)(chan->fr[0] )) & 0x001F) << 8; + d |= (((uint32)(chan->fr[1] )) & 0x001F) << 0; + break; + case 0x44: // LPF8 + d = (((uint32)(chan->fr[2] )) & 0x001F) << 8; + d |= (((uint32)(chan->fr[3] )) & 0x001F) << 0; + break; + } + return d; +} + +static void chan_aica_store_reg(struct YAM_STATE *state, uint8 ch, uint8 a, uint32 d, uint32 mask) { + struct YAM_CHAN *chan; + a &= 0x7C; + if(a >= 0x48) return; + yam_flush(YAMSTATE); + chan = state->chan + (((uint32)ch) & 0x3F); + switch(a) { + case 0x00: // PlayControl + if(mask & 0x00FF) { + chan->sampleaddr &= 0xFFFF; + chan->sampleaddr |= (((uint32)d) & 0x7F) << 16; + chan->pcms &= 2; + chan->pcms |= (d >> 7) & 1; + } + if(mask & 0xFF00) { + chan->pcms &= 1; + chan->pcms |= (d >> 7) & 2; + chan->sampler_looptype = (d >> 9) & 1; + chan->ssctl = (d >> 10) & 1; + chan->kyonb = (d >> 14) & 1; + if(d & 0x8000) { // kyonex + int ch; + for(ch = 0; ch < 64; ch++) { + if(state->chan[ch].kyonb) { keyon(state, state->chan + ch); } + else { keyoff(state->chan + ch, 1); } + } + } + } + break; + case 0x04: // SampleAddrLow + chan->sampleaddr &= (0x7FFFFF ^ mask); + chan->sampleaddr |= (d & mask); + break; + case 0x08: // LoopStart + chan->loopstart &= (0xFFFF ^ mask); + chan->loopstart |= (d & mask); + break; + case 0x0C: // LoopEnd + chan->loopend &= (0xFFFF ^ mask); + chan->loopend |= (d & mask); + break; + case 0x10: // AmpEnv1 + if(mask & 0x00FF) { + chan->ar[0] = d & 0x1F; + chan->ar[1] &= 0x1C; + chan->ar[1] |= (d >> 6) & 0x03; + } + if(mask & 0xFF00) { + chan->ar[1] &= 0x03; + chan->ar[1] |= (d >> 6) & 0x1C; + chan->ar[2] = (d >> 11) & 0x1F; + } + break; + case 0x14: // AmpEnv2 + if(mask & 0x00FF) { + chan->ar[3] = d & 0x1F; + chan->dl &= 0x18; + chan->dl |= (d >> 5) & 0x07; + } + if(mask & 0xFF00) { + chan->dl &= 0x07; + chan->dl |= (d >> 5) & 0x18; + chan->krs = (d >> 10) & 0xF; + chan->link = (d >> 14) & 1; + } + break; + case 0x18: // SampleRatePitch + if(mask & 0x00FF) { + chan->fns &= 0x700; + chan->fns |= d & 0x0FF; + } + if(mask & 0xFF00) { + chan->fns &= 0x0FF; + chan->fns |= d & 0x700; + chan->oct = (d >> 11) & 0xF; + } + chan->step = AICA_Step(chan); + break; + case 0x1C: // LFOControl + if(mask & 0x00FF) { + chan->alfos = d & 7; + chan->alfows = (d >> 3) & 3; + chan->plfos = (d >> 5) & 7; + } + if(mask & 0xFF00) { + chan->plfows = (d >> 8) & 3; + chan->lfof = (d >> 10) & 0x1F; + chan->lfore = (d >> 15) & 1; + } + Compute_LFO(chan); + break; + case 0x20: // DSPChannelSend + if(mask & 0x00FF) { + chan->dspchan = d & 0xF; + chan->dsplevel = (d >> 4) & 0xF; + } + break; + case 0x24: // DirectPanVolSend + if(mask & 0x00FF) { chan->dipan = d & 0x1F; } + if(mask & 0xFF00) { chan->disdl = (d >> 8) & 0xF; } + break; + case 0x28: // LPF1Volume + if(mask & 0x00FF) { + chan->q = d & 0x1F; + chan->lpoff = (d >> 5) & 1; + chan->voff = (d >> 6) & 1; + } + if(mask & 0xFF00) { + chan->tl = (d >> 8) & 0xFF; + } + break; + case 0x2C: // LPF2 + chan->flv[0] = (((chan->flv[0]) & (0xFFFF ^ mask)) | (d & mask)) & 0x1FFF; + break; + case 0x30: // LPF3 + chan->flv[1] = (((chan->flv[1]) & (0xFFFF ^ mask)) | (d & mask)) & 0x1FFF; + break; + case 0x34: // LPF4 + chan->flv[2] = (((chan->flv[2]) & (0xFFFF ^ mask)) | (d & mask)) & 0x1FFF; + break; + case 0x38: // LPF5 + chan->flv[3] = (((chan->flv[3]) & (0xFFFF ^ mask)) | (d & mask)) & 0x1FFF; + break; + case 0x3C: // LPF6 + chan->flv[4] = (((chan->flv[4]) & (0xFFFF ^ mask)) | (d & mask)) & 0x1FFF; + break; + case 0x40: // LPF7 + if(mask & 0x00FF) { chan->fr[1] = (d >> 0) & 0x1F; } + if(mask & 0xFF00) { chan->fr[0] = (d >> 8) & 0x1F; } + break; + case 0x44: // LPF8 + if(mask & 0x00FF) { chan->fr[3] = (d >> 0) & 0x1F; } + if(mask & 0xFF00) { chan->fr[2] = (d >> 8) & 0x1F; } + break; + } +} + +///////////////////////////////////////////////////////////////////////////// +// +// DSP registers +// +static void coef_write(struct YAM_STATE *state, uint32 n, uint32 d, uint32 mask) { + sint16 old = state->coef[n]; + yam_flush(state); + n &= 0x7F; + state->coef[n] <<= 3; + state->coef[n] &= ~mask; + state->coef[n] |= d & mask; + state->coef[n] = ((sint16)(state->coef[n])) >> 3; +#ifdef ENABLE_DYNAREC + if(old != state->coef[n]) { state->dsp_dyna_valid = 0; } +#endif +} + +static void madrs_write(struct YAM_STATE *state, uint32 n, uint32 d, uint32 mask) { + uint16 old = state->madrs[n]; + yam_flush(state); + n &= 0x3F; + state->madrs[n] &= ~mask; + state->madrs[n] |= d & mask; +#ifdef ENABLE_DYNAREC + if(old != state->madrs[n]) { state->dsp_dyna_valid = 0; } +#endif +} + +static uint32 temp_read(struct YAM_STATE *state, uint32 n) { + yam_flush(state); + if((n & 1) == 0) { return ((state->temp[(n/2)&0x7F]) >> 0) & 0x00FF; } + else { return ((state->temp[(n/2)&0x7F]) >> 8) & 0xFFFF; } +} + +static void temp_write(struct YAM_STATE *state, uint32 n, uint32 d, uint32 mask) { + yam_flush(state); + switch(n & 1) { + case 0: mask &= 0x00FF; break; + case 1: mask &= 0xFFFF; mask <<= 8; d <<= 8; break; + } + n /= 2; n &= 0x1F; + state->temp[n] &= ~mask; + state->temp[n] |= d & mask; + // redo sign extension + state->temp[n] <<= 8; + state->temp[n] >>= 8; +} + +static uint32 mems_read(struct YAM_STATE *state, uint32 n) { + yam_flush(state); + if((n & 1) == 0) { return ((state->inputs[(n/2)&0x1F]) >> 0) & 0x00FF; } + else { return ((state->inputs[(n/2)&0x1F]) >> 8) & 0xFFFF; } +} + +static void mems_write(struct YAM_STATE *state, uint32 n, uint32 d, uint32 mask) { + yam_flush(state); + switch(n & 1) { + case 0: mask &= 0x00FF; break; + case 1: mask &= 0xFFFF; mask <<= 8; d <<= 8; break; + } + n /= 2; n &= 0x1F; + state->inputs[n] &= ~mask; + state->inputs[n] |= d & mask; + // redo sign extension + state->inputs[n] <<= 8; + state->inputs[n] >>= 8; +} + +static uint32 mixs_read(struct YAM_STATE *state, uint32 n) { + yam_flush(state); + // MIXS is pre-promoted to 24-bit here, so shift it right by 4 + if((n & 1) == 0) { return ((state->inputs[0x20+((n/2)&0xF)]) >> 4) & 0x000F; } + else { return ((state->inputs[0x20+((n/2)&0xF)]) >> 8) & 0xFFFF; } +} + +static uint32 efreg_read(struct YAM_STATE *state, uint32 n) { + yam_flush(state); + return ((uint32)(state->efreg[n & 0xF])) & 0xFFFF; +} + +static void efreg_write(struct YAM_STATE *state, uint32 n, uint32 d, uint32 mask) { + yam_flush(state); + state->efreg[n & 0xF] &= ~mask; + state->efreg[n & 0xF] |= d & mask; +} + +static uint32 exts_read(struct YAM_STATE *state, uint32 n) { + yam_flush(state); + return (state->inputs[0x30 + (n & 1)] >> 8) & 0xFFFF; +} + +static void exts_write(struct YAM_STATE *state, uint32 n, uint32 d, uint32 mask) { + yam_flush(state); + state->inputs[0x30 + (n & 1)] >>= 8; + state->inputs[0x30 + (n & 1)] &= ~mask; + state->inputs[0x30 + (n & 1)] |= d & mask; + state->inputs[0x30 + (n & 1)] <<= 16; + state->inputs[0x30 + (n & 1)] >>= 8; +} + +static uint32 dsp_scsp_load_reg(struct YAM_STATE *state, uint32 a) { + a &= 0xFFE; + if(a < 0x700) return 0; + if(a < 0x780) return state->coef[(a/2) & 0x3F] << 3; + if(a < 0x7C0) return state->madrs[(a/2) & 0x1F]; + if(a < 0x800) return 0; + if(a < 0xC00) { + uint8 shift = ((a&6)^6) * 8; + uint32 index = ((a-0x800)/8)&0x7F; + return (mpro_scsp_read(state->mpro + index) >> shift) & 0xFFFF; + } + if(a < 0xE00) return temp_read(state, (a/2) & 0xFF); + if(a < 0xE80) return mems_read(state, (a/2) & 0x3F); + if(a < 0xEC0) return mixs_read(state, (a/2) & 0x1F); + if(a < 0xEE0) return efreg_read(state, (a/2) & 0xF); + if(a < 0xEE4) return exts_read(state, (a/2) & 1); + return 0; +} + +static void dsp_scsp_store_reg( + struct YAM_STATE *state, + uint32 a, uint32 d, uint32 mask +) { + a &= 0xFFE; + if(a < 0x700) { return; } + if(a < 0x780) { coef_write(state, (a/2) & 0x3F, d, mask); return; } + if(a < 0x7C0) { madrs_write(state, (a/2) & 0x1F, d, mask); return; } + if(a < 0x800) { return; } + if(a < 0xC00) { + uint8 shift64 = ((a&6)^6) * 8; + uint32 index64 = ((a-0x800)/8)&0x7F; + uint64 mask64sh = ((uint64)(mask & 0xFFFF)) << shift64; + uint64 dm64sh = ((uint64)(d & mask & 0xFFFF)) << shift64; + uint64 oldvalue = mpro_scsp_read(state->mpro + index64); + uint64 newvalue = (oldvalue & (~mask64sh)) | dm64sh; + if(newvalue != oldvalue) { + yam_flush(state); + mpro_scsp_write(state->mpro + index64, newvalue); +#ifdef ENABLE_DYNAREC + state->dsp_dyna_valid = 0; +#endif + } + return; + } + if(a < 0xE00) { temp_write(state, (a/2) & 0xFF, d, mask); return; } + if(a < 0xE80) { mems_write(state, (a/2) & 0x3F, d, mask); return; } + // you can't write to MIXS, at least not meaningfully + if(a < 0xEC0) { return; } + if(a < 0xEE0) { efreg_write(state, (a/2) & 0xF, d, mask); return; } + if(a < 0xEE4) { exts_write(state, (a/2) & 1, d, mask); return; } +} + +static uint32 dsp_aica_load_reg(struct YAM_STATE *state, uint32 a) { + a &= 0xFFFC; + if(a < 0x3000) return 0; + if(a < 0x3200) return state->coef[(a/4) & 0x7F] << 3; + if(a < 0x3300) return state->madrs[(a/4) & 0x3F]; + if(a < 0x3400) return 0; + if(a < 0x3C00) { + uint8 shift64 = ((a&0xC)^0xC) * 4; + uint32 index64 = ((a-0x3400)/16)&0x7F; + return (mpro_aica_read(state->mpro + index64) >> shift64) & 0xFFFF; + } + if(a < 0x4000) return 0; + if(a < 0x4400) return temp_read(state, (a/4) & 0xFF); + if(a < 0x4500) return mems_read(state, (a/4) & 0x3F); + if(a < 0x4580) return mixs_read(state, (a/4) & 0x1F); + if(a < 0x45C0) return efreg_read(state, (a/4) & 0xF); + if(a < 0x45C8) return exts_read(state, (a/4) & 1); + return 0; +} + +static void dsp_aica_store_reg( + struct YAM_STATE *state, + uint32 a, uint32 d, uint32 mask +) { + a &= 0xFFFC; + if(a < 0x3000) { return; } + if(a < 0x3200) { coef_write(state, (a/4) & 0x7F, d, mask); return; } + if(a < 0x3300) { madrs_write(state, (a/4) & 0x3F, d, mask); return; } + if(a < 0x3400) { return; } + if(a < 0x3C00) { + uint8 shift64 = ((a&0xC)^0xC) * 4; + uint32 index64 = ((a-0x3400)/16)&0x7F; + uint64 mask64sh = ((uint64)(mask & 0xFFFF)) << shift64; + uint64 dm64sh = ((uint64)(d & mask & 0xFFFF)) << shift64; + uint64 oldvalue = mpro_aica_read(state->mpro + index64); + uint64 newvalue = (oldvalue & (~mask64sh)) | dm64sh; + if(newvalue != oldvalue) { + yam_flush(state); + mpro_aica_write(state->mpro + index64, newvalue); +#ifdef ENABLE_DYNAREC + state->dsp_dyna_valid = 0; +#endif + } + return; + } + if(a < 0x4000) { return; } + if(a < 0x4400) { temp_write(state, (a/4) & 0xFF, d, mask); return; } + if(a < 0x4500) { mems_write(state, (a/4) & 0x3F, d, mask); return; } + // you can't write to MIXS, at least not meaningfully + if(a < 0x4580) { return; } + if(a < 0x45C0) { efreg_write(state, (a/4) & 0xF, d, mask); return; } + if(a < 0x45C8) { exts_write(state, (a/4) & 1, d, mask); return; } +} + +///////////////////////////////////////////////////////////////////////////// +// +// Externally-accessible load/store register +// + +#if defined(SCSP_LOG) && !defined(USE_STARSCREAM) +#include + extern FILE * scsp_log; + extern unsigned char ** scsp_pc, ** scsp_basepc; +#endif + +uint32 EMU_CALL yam_scsp_load_reg(void *state, uint32 a, uint32 mask) { + uint32 d = 0; + a &= 0xFFE; + if(a < 0x400) return chan_scsp_load_reg(YAMSTATE, a>>5, a&0x1E) & mask; + if(a >= 0x700) return dsp_scsp_load_reg(YAMSTATE, a) & mask; + if(a >= 0x600) return YAMSTATE->ringbuf[(YAMSTATE->bufptr-64+(a-0x600)/2)&(32*RINGMAX-1)] & mask; + switch(a) { + case 0x400: d = 0x0010; break; // MasterVolume (actually returns the LSI version) + case 0x402: // RingBufferAddress + d = (((uint32)(YAMSTATE->rbl)) & 3) << 7; + d |= ((YAMSTATE->rbp >> 13) & 0x7F); + break; + case 0x404: d = (1<<11) | (1 << 8); break; // MIDIInput, unimplemented + case 0x406: d = 0; break; // MIDI output, unimplemented + case 0x408: // CallAddress (playpos in increments of 4K) + { int c = (YAMSTATE->mslc) & 0x1F; + int sgc, ca, eg; + struct YAM_CHAN * chan; + + if(YAMSTATE->out_pending > 0) yam_flush(YAMSTATE); + + chan = YAMSTATE->chan + c; + + sgc = chan->EG.state & 3; + ca = ( chan->cur_addr >> (SHIFT + 12) ) & 0xf; + eg = ( 0x1f - ( chan->EG.volume >> (EG_SHIFT + 5) ) ) & 0x1f; + + d = (c << 11) | (ca << 7) | (sgc << 5) | eg; + +// +// might only be checking when envstate is release anyway? +// + +// d |= (YAMSTATE->chan[c].envstate != 3) << 4; +//d |= 1<<3; + +// d |= (YAMSTATE->chan[c].lp & 1) << 4; +// YAMSTATE->chan[c].lp = 0; + + + +// +// here bit 3 seems to be set to 1 to indicate idle. +// what idle means, I haven't determined +// + +//d|=1<<3; + + //d|=(YAMSTATE->chan[c].sampler_dir!=0)<<4; +// d|=(YAMSTATE->chan[c].envlevel>=0x80)<<4; + +// d|=((YAMSTATE->chan[c].envlevel)&0x3FF)>>5; + + //if(YAMSTATE->chan[c].envstate >= 1) { + // d |= 1<<4; + // d|=(YAMSTATE->chan[c].envlevel>=0x100)<<3; + //} +// //d |= 1<<3; +// d |= (YAMSTATE->chan[c].envlevel >= 0x80) << 3; +// +// d |= (YAMSTATE->chan[c].sampler_dir!=0) << 3; +//d|=1<<3; + + // if 1<<3 always set: missing notes + // if 1<<3 never set: notes get cut off early, but most are there + // if it's >=0x300: missing notes + // if it's >=0x3C0: missing notes + // if it's <0x300: notes get cut off early + +// close but missing notes +// d |= (YAMSTATE->chan[c].envstate == 3) << 4; +// d |= (YAMSTATE->chan[c].envlevel >= 0x281) << 3; + + +// d |= 1<<4; + +// d |= (YAMSTATE->chan[c].envlevel >= 0x281) << 3; +// d |= (YAMSTATE->chan[c].envstate != 3) << 3; + +// d |= (YAMSTATE->chan[c].sampler_dir == 0) << 4; + + //d |= ((YAMSTATE->chan[c].envlevel) & 0x1FFF) >> 3; + +//d ^= 0x00; // few +//d ^= 0x67; // few (these bits have no effect) +//d ^= 0x7F; // many missing notes +//d ^= 1<<4; // few +//d ^= 1<<3; // few +//d ^= 3<<3; // many missing notes + +// only updates when hardware bit 1<<4 is 1 +// hardware bit 1<<3 means idle? + + + +// ok but wrong +// d |= (((uint32)(YAMSTATE->chan[c].envstate)) & 3) << 5; +// d |= ((YAMSTATE->chan[c].envlevel) & 0x3FF) >> 5; +// d ^= 0x7F; + + +// { uint32 l = (YAMSTATE->chan[c].envlevel) & (YAMSTATE->chan[c].envlevelmask[YAMSTATE->chan[c].envstate & 3]); +// if(l>0x3BF)l=0x1FFF; +// if(YAMSTATE->chan[c].sampler_dir == 0) l=0x1FFF; +//d|=(l>=0x3C0)<<3; +//d|=(l>=0x3C0)<<4; +// d |= l >> 8; +// if(l>=0x3BF) d|=0<<3; +//d|=l>>5; +// } + + +//d^=0x1C; +// d |= ((YAMSTATE->chan[c].envlevel) & 0x1FFF) >> 8; + +//{ uint32 es = ((uint32)(YAMSTATE->chan[c].envstate)) & 3; +// es = 0; +// if(YAMSTATE->chan[c].sampler_dir == 0) es = 3; +// d |= es << 3; +//} + +//d ^= 0x18; +//d |= 0x00; + + } + + break; + case 0x412: + d = YAMSTATE->dmea & 0xFFFF; + break; + case 0x414: + d = (((uint32)(YAMSTATE->dmea)) & 0xF0000) >> 4; + d |= (((uint32)(YAMSTATE->drga)) & 0xFFE) << 0; + break; + case 0x416: + d = (((uint32)(YAMSTATE->dtlg)) & 0xFFE) << 0; + break; + case 0x418: + d = (((uint32)(YAMSTATE->tctl[0])) & 0x7) << 8; + d |= (((uint32)(YAMSTATE->tim[0])) & 0xFF) << 0; + break; + case 0x41A: + d = (((uint32)(YAMSTATE->tctl[1])) & 0x7) << 8; + d |= (((uint32)(YAMSTATE->tim[1])) & 0xFF) << 0; + break; + case 0x41C: + d = (((uint32)(YAMSTATE->tctl[2])) & 0x7) << 8; + d |= (((uint32)(YAMSTATE->tim[2])) & 0xFF) << 0; + break; + case 0x41E: d = YAMSTATE->scieb & 0x07FF; break; + case 0x420: d = YAMSTATE->scipd & 0x07FF; break; + case 0x424: d = YAMSTATE->scilv0 & 0xFF; break; + case 0x426: d = YAMSTATE->scilv1 & 0xFF; break; + case 0x428: d = YAMSTATE->scilv2 & 0xFF; break; + case 0x42A: d = YAMSTATE->mcieb & 0x07FF; break; + case 0x42C: d = YAMSTATE->mcipd & 0x07FF; break; + } +#if defined(SCSP_LOG) && !defined(USE_STARSCREAM) + fprintf(scsp_log, "%u - %08x r: %04x, %04x\n", YAMSTATE->odometer, (int)(*scsp_pc - *scsp_basepc), a, d); +#endif + return d & mask; +} + +void EMU_CALL yam_scsp_store_reg(void *state, uint32 a, uint32 d, uint32 mask, uint8 *breakcpu) { + a &= 0xFFE; + d &= 0xFFFF & mask; +#if defined(SCSP_LOG) && !defined(USE_STARSCREAM) + fprintf(scsp_log, "%u - %08x w: %04x, %04x\n", YAMSTATE->odometer, (int)(*scsp_pc - *scsp_basepc), a, d); +#endif + mask &= 0xFFFF; + if(a < 0x400) { chan_scsp_store_reg(YAMSTATE, a>>5, a&0x1E, d, mask); return; } + if(a >= 0x700) { dsp_scsp_store_reg(YAMSTATE, a, d, mask); return; } + if(a >= 0x600) { uint32 offset = (YAMSTATE->bufptr-64+(a-0x600)/2)&(32*RINGMAX-1); YAMSTATE->ringbuf[offset] = (d & mask) | (YAMSTATE->ringbuf[offset] & ~mask); return; } + switch(a) { + case 0x400: // MasterVolume + yam_flush(YAMSTATE); + if(mask & 0x00FF) { + YAMSTATE->mvol = d & 0xF; + } + break; + case 0x402: // RingBufferAddress + { uint32 oldrbp = YAMSTATE->rbp; + uint8 oldrbl = YAMSTATE->rbl; + if(mask & 0x00FF) { + YAMSTATE->rbp = (((uint32)d) & 0x7F) << 13; + YAMSTATE->rbl &= 2; + YAMSTATE->rbl |= (d >> 7) & 1; + } + if(mask & 0xFF00) { + YAMSTATE->rbl &= 1; + YAMSTATE->rbl |= (d >> 7) & 2; + } + if((oldrbp != YAMSTATE->rbp) || (oldrbl != YAMSTATE->rbl)) { + uint32 newrbp = YAMSTATE->rbp; + uint8 newrbl = YAMSTATE->rbl; + YAMSTATE->rbp = oldrbp; + YAMSTATE->rbl = oldrbl; + yam_flush(YAMSTATE); +#ifdef ENABLE_DYNAREC + YAMSTATE->dsp_dyna_valid = 0; +#endif + YAMSTATE->rbp = newrbp; + YAMSTATE->rbl = newrbl; + } + } + break; + case 0x408: // ChnInfoReq + if(mask & 0xFF00) { + YAMSTATE->mslc = (d >> 11) & 0x1F; + } + break; + case 0x412: // DMA + if(mask & 0x00FF) { YAMSTATE->dmea = (YAMSTATE->dmea & 0xFFF00) | (d & 0xFF); } + if(mask & 0xFF00) { YAMSTATE->dmea = (YAMSTATE->dmea & 0xF00FF) | (d & 0xFF00); } + break; + case 0x414: + if(mask & 0xFF) { YAMSTATE->drga = (YAMSTATE->drga & 0xF00) | (d & 0xFE); } + if(mask & 0xFF00) { YAMSTATE->drga = (YAMSTATE->drga & 0x0FF) | (d & 0xF00); YAMSTATE->dmea = (YAMSTATE->dmea & 0xFFFF) | ((d & 0xF000) << 4); } + break; + case 0x416: + if(mask & 0xFF) { YAMSTATE->dtlg = (YAMSTATE->dtlg & 0xF00) | (d & 0xFE); } + if(mask & 0xFF00) { YAMSTATE->dtlg = (YAMSTATE->dtlg & 0xFF) | (d & 0xF00); } + break; + case 0x418: // TimerAControl + if(mask & 0x00FF) { YAMSTATE->tim[0] = d & 0xFF; } + if(mask & 0xFF00) { YAMSTATE->tctl[0] = (d >> 8) & 7; } + if(breakcpu) *breakcpu = 1; + break; + case 0x41A: // TimerBControl + if(mask & 0x00FF) { YAMSTATE->tim[1] = d & 0xFF; } + if(mask & 0xFF00) { YAMSTATE->tctl[1] = (d >> 8) & 7; } + if(breakcpu) *breakcpu = 1; + break; + case 0x41C: // TimerCControl + if(mask & 0x00FF) { YAMSTATE->tim[2] = d & 0xFF; } + if(mask & 0xFF00) { YAMSTATE->tctl[2] = (d >> 8) & 7; } + if(breakcpu) *breakcpu = 1; + break; + case 0x41E: // SCIEB + YAMSTATE->scieb = (((YAMSTATE->scieb) & (~mask)) | (d & mask)) & 0x7FF; + if(breakcpu) *breakcpu = 1; + break; + case 0x420: // SCIPD + YAMSTATE->scipd = (((YAMSTATE->scipd) & (~mask)) | (d & mask)) & 0x7FF; + if(breakcpu) *breakcpu = 1; + break; + case 0x422: // SCIRE + YAMSTATE->scipd &= ~(d & mask); + // I guess this is how we acknowledge interrupts now + sci_recompute(YAMSTATE); + if(breakcpu) *breakcpu = 1; + break; + case 0x424: // SCILV0 + if(mask & 0x00FF) { YAMSTATE->scilv0 = d; } + break; + case 0x426: // SCILV1 + if(mask & 0x00FF) { YAMSTATE->scilv1 = d; } + break; + case 0x428: // SCILV2 + if(mask & 0x00FF) { YAMSTATE->scilv2 = d; } + break; + case 0x42A: // MCIEB + YAMSTATE->mcieb = (((YAMSTATE->mcieb) & (~mask)) | (d & mask)) & 0x7FF; + break; + case 0x42C: // MCIPD + YAMSTATE->mcipd = (((YAMSTATE->mcipd) & (~mask)) | (d & mask)) & 0x7FF; + break; + case 0x42E: // MCIRE + YAMSTATE->mcipd &= ~(d & mask); + break; + } +} + +uint32 EMU_CALL yam_aica_load_reg(void *state, uint32 a, uint32 mask) { + uint32 d = 0; + a &= 0xFFFC; + if(a < 0x2000) return chan_aica_load_reg(YAMSTATE, a>>7, a&0x7C) & mask; + if(a >= 0x3000) return dsp_aica_load_reg(YAMSTATE, a) & mask; + if(a < 0x2048) { + d = + ((((uint32)(YAMSTATE->efsdl[(a - 0x2000) / 4])) & 0x0F) << 8) | + ((((uint32)(YAMSTATE->efpan[(a - 0x2000) / 4])) & 0x1F) << 0); + return d & mask; + } + switch(a) { + case 0x2800: d = 0x0010; break; // MasterVolume (actually returns the LSI version) + case 0x2804: // RingBufferAddress + d = (((uint32)(YAMSTATE->rbl)) & 3) << 13; + d |= ((YAMSTATE->rbp >> 11) & 0xFFF); + break; + case 0x2808: d = (1<<11) | (1 << 8); break; // MIDIInput, unimplemented + case 0x280C: d = 0; break; // ChnInfoReq, always seems to return 0 when read + case 0x2810: // PlayStatus +// if(YAMSTATE->out_pending > 100) yam_flush(YAMSTATE); + if(YAMSTATE->out_pending > 0) yam_flush(YAMSTATE); + { int c = (YAMSTATE->mslc) & 0x3F; + d = (((uint32)(YAMSTATE->chan[c].lp )) & 1) << 15; + if(YAMSTATE->afsel == 0) { + d |= (((uint32)(YAMSTATE->chan[c].EG.state)) & 3) << 13; + d |= (~YAMSTATE->chan[c].EG.volume >> (EG_SHIFT-3)) & 0x1FFF; + } else { + d |= (((uint32)(YAMSTATE->chan[c].lpfstate)) & 3) << 13; + d |= (YAMSTATE->chan[c].lpflevel) & 0x1FFF; + } + } + break; + case 0x2814: d = (YAMSTATE->chan[YAMSTATE->mslc].cur_addr)>>(SHIFT+12); break; + case 0x2880: d = YAMSTATE->mrwinh & 0xF; break; + case 0x2884: d = 0; break; + case 0x2888: d = 0; break; + case 0x288C: d = 0; break; + case 0x2890: + d = (((uint32)(YAMSTATE->tctl[0])) & 0x7) << 8; + d |= (((uint32)(YAMSTATE->tim[0])) & 0xFF) << 0; + break; + case 0x2894: + d = (((uint32)(YAMSTATE->tctl[1])) & 0x7) << 8; + d |= (((uint32)(YAMSTATE->tim[1])) & 0xFF) << 0; + break; + case 0x2898: + d = (((uint32)(YAMSTATE->tctl[2])) & 0x7) << 8; + d |= (((uint32)(YAMSTATE->tim[2])) & 0xFF) << 0; + break; + case 0x289C: d = YAMSTATE->scieb & 0x07FF; break; + case 0x28A0: d = YAMSTATE->scipd & 0x07FF; break; + case 0x28A4: d = 0; break; + case 0x28A8: d = YAMSTATE->scilv0 & 0xFF; break; + case 0x28AC: d = YAMSTATE->scilv1 & 0xFF; break; + case 0x28B0: d = YAMSTATE->scilv2 & 0xFF; break; + case 0x28B4: d = YAMSTATE->mcieb & 0x07FF; break; + case 0x28B8: d = YAMSTATE->mcipd & 0x07FF; break; + case 0x28BC: d = 0; break; + case 0x2C00: d = 0; break; + case 0x2D00: d = YAMSTATE->intreq & 7; break; + case 0x2D04: d = 0; break; + case 0x2E00: d = YAMSTATE->rtc >> 16; break; + case 0x2E04: d = YAMSTATE->rtc; break; + } + return d & mask; +} + +void EMU_CALL yam_aica_store_reg(void *state, uint32 a, uint32 d, uint32 mask, uint8 *breakcpu) { + a &= 0xFFFC; + d &= 0xFFFF & mask; + if(a < 0x2000) { chan_aica_store_reg(YAMSTATE, a>>7, a&0x7C, d, mask); return; } + if(a >= 0x3000) { dsp_aica_store_reg(YAMSTATE, a, d, mask); return; } + if(a < 0x2048) { + if(mask & 0x00FF) { YAMSTATE->efpan[(a - 0x2000) / 4] = d & 0x1F; } + if(mask & 0xFF00) { YAMSTATE->efsdl[(a - 0x2000) / 4] = (d >> 8) & 0x0F; } + return; + } + switch(a) { + case 0x2800: // MasterVolume + yam_flush(YAMSTATE); + if(mask & 0x00FF) { + YAMSTATE->mvol = d & 0xF; + } + if(mask & 0xFF00) { + YAMSTATE->mono = (d >> 15) & 1; + } + break; + case 0x2804: // RingBufferAddress + { uint32 oldrbp = YAMSTATE->rbp; + uint8 oldrbl = YAMSTATE->rbl; + if(mask & 0x00FF) { + YAMSTATE->rbp >>= 11; + YAMSTATE->rbp &= 0xF00; + YAMSTATE->rbp |= d & 0x0FF; + YAMSTATE->rbp <<= 11; + } + if(mask & 0xFF00) { + YAMSTATE->rbp >>= 11; + YAMSTATE->rbp &= 0x0FF; + YAMSTATE->rbp |= d & 0xF00; + YAMSTATE->rbp <<= 11; + YAMSTATE->rbl = (d >> 13) & 3; + } + if((oldrbp != YAMSTATE->rbp) || (oldrbl != YAMSTATE->rbl)) { + uint32 newrbp = YAMSTATE->rbp; + uint8 newrbl = YAMSTATE->rbl; + YAMSTATE->rbp = oldrbp; + YAMSTATE->rbl = oldrbl; + yam_flush(YAMSTATE); +#ifdef ENABLE_DYNAREC + YAMSTATE->dsp_dyna_valid = 0; +#endif + YAMSTATE->rbp = newrbp; + YAMSTATE->rbl = newrbl; + } + } + break; + case 0x2808: // MIDIInput, unimplemented + break; + case 0x280C: // ChnInfoReq + if(mask & 0x00FF) { + // MIDI output buffer, unimplemented + } + if(mask & 0xFF00) { + YAMSTATE->mslc = (d >> 8) & 0x3F; + YAMSTATE->afsel = (d >> 14) & 1; + } + break; + case 0x2810: break; // PlayStatus - writing probably has no effect. + case 0x2814: break; // PlayPos - writing probably has no effect. + case 0x2880: // misc. + if(mask & 0x00FF) { + YAMSTATE->mrwinh = d & 0xF; + } + break; + case 0x2884: break; // misc. + case 0x2888: break; // misc. + case 0x288C: break; // misc. + case 0x2890: // TimerAControl + if(mask & 0x00FF) { YAMSTATE->tim[0] = d & 0xFF; } + if(mask & 0xFF00) { YAMSTATE->tctl[0] = (d >> 8) & 7; } + if(breakcpu) *breakcpu = 1; + break; + case 0x2894: // TimerBControl + if(mask & 0x00FF) { YAMSTATE->tim[1] = d & 0xFF; } + if(mask & 0xFF00) { YAMSTATE->tctl[1] = (d >> 8) & 7; } + if(breakcpu) *breakcpu = 1; + break; + case 0x2898: // TimerCControl + if(mask & 0x00FF) { YAMSTATE->tim[2] = d & 0xFF; } + if(mask & 0xFF00) { YAMSTATE->tctl[2] = (d >> 8) & 7; } + if(breakcpu) *breakcpu = 1; + break; + case 0x289C: // SCIEB + YAMSTATE->scieb = (((YAMSTATE->scieb) & (~mask)) | (d & mask)) & 0x7FF; + if(breakcpu) *breakcpu = 1; + break; + case 0x28A0: // SCIPD + YAMSTATE->scipd = (((YAMSTATE->scipd) & (~mask)) | (d & mask)) & 0x7FF; + if(breakcpu) *breakcpu = 1; + break; + case 0x28A4: // SCIRE + YAMSTATE->scipd &= ~(d & mask); + if(breakcpu) *breakcpu = 1; + break; + case 0x28A8: // SCILV0 + if(mask & 0x00FF) { YAMSTATE->scilv0 = d; } + break; + case 0x28AC: // SCILV1 + if(mask & 0x00FF) { YAMSTATE->scilv1 = d; } + break; + case 0x28B0: // SCILV2 + if(mask & 0x00FF) { YAMSTATE->scilv2 = d; } + break; + case 0x28B4: // MCIEB + YAMSTATE->mcieb = (((YAMSTATE->mcieb) & (~mask)) | (d & mask)) & 0x7FF; + break; + case 0x28B8: // MCIPD + YAMSTATE->mcipd = (((YAMSTATE->mcipd) & (~mask)) | (d & mask)) & 0x7FF; + break; + case 0x28BC: // MCIRE + YAMSTATE->mcipd &= ~(d & mask); + break; + case 0x2C00: // ARMReset + break; + case 0x2D00: // INTRequest + break; + case 0x2D04: // INTClear + // running through the recompute will clear the previous interrupt + // as well as enabling the next one, if there is a next one + sci_recompute(YAMSTATE); + if(breakcpu) *breakcpu = 1; + break; + case 0x2E00: // RTCHi + break; + case 0x2E04: // RTCLo + break; + } +} + +///////////////////////////////////////////////////////////////////////////// +// +// Generate random data +// +static uint32 yamrand16(struct YAM_STATE *state) { + state->randseed = 1103515245 * state->randseed + 12345; + return state->randseed >> 16; +} + +///////////////////////////////////////////////////////////////////////////// +// +// (original) Envelope-related calculations +// + +// +// Adjust actual rate to get effective rate +// +static uint32 env_adjustrate(struct YAM_CHAN *chan, uint32 rate) { + sint32 effrate = rate * 2; + if(chan->krs < 0xF) { + effrate += (chan->fns >> 9) & 1; + effrate += chan->krs * 2; + effrate = (effrate - 8) + (chan->oct ^ 8); + } + // Clipping is important because of the table lookups + if(effrate <= 0) return 0; + if(effrate >= 0x3C) return 0x3C; + return effrate; +} + +// +// Determine whether a step is going to occur here +// +static int env_needstep(uint32 effrate, uint32 odometer) { + uint32 shift; + uint32 pattern; + uint32 bitplace; + if(effrate <= 0x01) return 0; + if(effrate >= 0x30) return ((odometer & 1) == 0); + shift = 12 - ((effrate - 1) >> 2); + pattern = (effrate - 1) & 3; + if(odometer & ((1<> shift) & 7; + return (0xFFFDDDD5 >> (pattern * 8 + bitplace)) & 1; + // 11010101 0x01 each bit is 4096 samples + // 11011101 0x02 + // 11111101 0x03 + // 11111111 0x04 +} + +///////////////////////////////////////////////////////////////////////////// +// +// Read next sample +// +static sint32 AICA_UpdateSlot(struct YAM_STATE *state, struct YAM_CHAN *chan) +{ + sint32 sample, fpart; + int cur_sample; //current sample + int nxt_sample; //next sample + int step=chan->step; + uint32 addr1,addr2,addr_select; // current and next sample addresses + uint32 *addr[2] = {&addr1, &addr2}; // used for linear interpolation + uint32 *slot_addr[2] = {&(chan->cur_addr), &(chan->nxt_addr)}; // + + if(chan->ssctl!=0) //no FM or noise yet + return 0; + + if(chan->plfos!=0) { + step=step*PLFO_Step(&(chan->PLFO)); + step>>=SHIFT; + } + + if(chan->pcms == 0) { + addr1=(chan->cur_addr>>(SHIFT-1))&state->ram_mask&~1; + addr2=(chan->nxt_addr>>(SHIFT-1))&state->ram_mask&~1; + } + else { + addr1=chan->cur_addr>>SHIFT; + addr2=chan->nxt_addr>>SHIFT; + } + + if(state->version == 1 && (chan->mdl!=0 || chan->mdxsl!=0 || chan->mdysl!=0)) + { + sint32 smp=(state->ringbuf[(state->bufptr-64+chan->mdxsl)&(32*RINGMAX-1)]+state->ringbuf[(state->bufptr-64+chan->mdysl)&(32*RINGMAX-1)])/2; + + smp<<=0xA; // associate cycle with 1024 + smp>>=0x1A-chan->mdl; // ex. for MDL=0xF, sample range corresponds to +/- 64 pi (32=2^5 cycles) so shift by 11 (16-5 == 0x1A-0xF) + if(chan->pcms == 0) smp<<=1; + + addr1+=smp; addr2+=smp; + } + + if(chan->pcms == 1) // 8-bit signed + { + sint8 *p1=(signed char *) (((uint8*)state->ram_ptr)+(((chan->sampleaddr+addr1)^state->mem_byte_address_xor)&state->ram_mask)); + sint8 *p2=(signed char *) (((uint8*)state->ram_ptr)+(((chan->sampleaddr+addr2)^state->mem_byte_address_xor)&state->ram_mask)); + cur_sample = (p1[0] << 8) ^ chan->sampler_invert; + nxt_sample = (p2[0] << 8) ^ chan->sampler_invert; + } + else if (chan->pcms == 0) //16 bit signed + { + sint16 *p1=(signed short *) (((uint8*)state->ram_ptr)+(((chan->sampleaddr+addr1)^state->mem_word_address_xor)&state->ram_mask&~1)); + sint16 *p2=(signed short *) (((uint8*)state->ram_ptr)+(((chan->sampleaddr+addr2)^state->mem_word_address_xor)&state->ram_mask&~1)); + cur_sample = p1[0] ^ chan->sampler_invert; + nxt_sample = p2[0] ^ chan->sampler_invert; + } + else // 4-bit ADPCM + { + uint32 adbase = chan->adbase; + uint8 *base; + uint32 steps_to_go = addr2, curstep = chan->curstep; + + if(adbase) { + base = ((uint8*)state->ram_ptr); + cur_sample = chan->cur_sample; // may already contains current decoded sample + + // seek to the interpolation sample + while (curstep < steps_to_go) { + int shift1, delta1; + shift1 = 4*((curstep&1)); + delta1 = (base[adbase]>>shift1)&0xf; + DecodeADPCM(&(chan->cur_sample),delta1,&(chan->cur_quant)); + curstep++; + if (!(curstep & 1)) { + adbase = (adbase + 1) & state->ram_mask; + } + if (curstep == addr1) + cur_sample = chan->cur_sample; + } + nxt_sample = chan->cur_sample; + + chan->adbase = adbase; + chan->curstep = curstep; + } + else { + cur_sample = nxt_sample = 0; + } + } + + fpart = chan->cur_addr & ((1<>=SHIFT; + + chan->prv_addr=chan->cur_addr; + if(chan->Backwards) + chan->cur_addr-=step; + else + chan->cur_addr+=step; + chan->nxt_addr=chan->cur_addr+(1<cur_addr>>SHIFT; + addr2=chan->nxt_addr>>SHIFT; + + if(addr1>=chan->loopstart && !(chan->Backwards)) { + if(chan->link && chan->EG.state==ATTACK) + chan->EG.state = DECAY1; + } + + for (addr_select=0;addr_select<2;addr_select++) + { + sint32 rem_addr; + switch(chan->sampler_looptype) + { + case 0: //no loop + if(*addr[addr_select]>=chan->loopstart && *addr[addr_select]>=chan->loopend) { + keyoff(chan, 0); + } + break; + case 1: //normal loop + if(*addr[addr_select]>=chan->loopend) { + rem_addr = *slot_addr[addr_select] - (chan->loopend<loopstart<pcms>=2) { + // restore the state @ LSA - the sampler will naturally walk to (LSA + remainder) + chan->adbase = (chan->sampleaddr+(chan->loopstart/2))&state->ram_mask; + chan->curstep = chan->loopstart; + if (chan->pcms == 2) { + chan->cur_sample = chan->cur_lpsample; + chan->cur_quant = chan->cur_lpquant; + } + //printf("Looping: slot_addr %x LSA %x LEA %x step %x base %x\n", slot->cur_addr>>SHIFT, LSA(slot), LEA(slot), slot->curstep, slot->adbase); + } + } + break; + case 2: //reverse loop + if((*addr[addr_select]>=chan->loopstart) && !(chan->Backwards)) { + rem_addr = *slot_addr[addr_select] - (chan->loopstart<loopend<Backwards = 1; + } + else if((*addr[addr_select]loopstart || (*slot_addr[addr_select]&0x80000000)) && chan->Backwards) { + rem_addr = (chan->loopstart<loopend<=chan->loopend) //reached end, reverse till start + { + rem_addr = *slot_addr[addr_select] - (chan->loopend<loopend<Backwards = 1; + } + else if((*addr[addr_select]loopstart || (*slot_addr[addr_select]&0x80000000)) && chan->Backwards)//reached start or negative + { + rem_addr = (chan->loopstart<loopstart<Backwards = 0; + } + break; + } + } + + if(chan->alfos!=0) { + sample=sample*ALFO_Step(&(chan->ALFO)); + sample>>=SHIFT; + } + + if(chan->EG.state==ATTACK) + sample=(sample*EG_Update(chan))>>SHIFT; + else + sample=(sample*EG_TABLE[EG_Update(chan)>>(SHIFT-10)])>>SHIFT; + + if(state->version == 1 && !chan->stwinh) + { + unsigned short Enc = ((chan->tl)<<0x0)|(0x7<<0xd); + state->ringbuf[state->bufptr] = (sample * LPANTABLE_SCSP[Enc])>>(SHIFT+1); + } + + /*if(chan->mslc) { + AICA->udata.data[0x14/2] = addr1; + if (!(AFSEL(AICA))) { + UINT16 res; + + AICA->udata.data[0x10/2] |= slot->EG.state<<13; + + res = 0x3FF - (slot->EG.volume>>EG_SHIFT); + + res *= 959; + res /= 1024; + + if (res > 959) res = 959; + + AICA->udata.data[0x10/2] = res; + + //AICA->udata.data[0x10/2] |= 0x3FF - (slot->EG.volume>>EG_SHIFT); + } + }*/ + + return sample; +} + +///////////////////////////////////////////////////////////////////////////// +// +// Generate samples +// Samples are returned in 20-bit format +// Returns the number of samples actually generated +// +static uint32 generate_samples( + struct YAM_STATE *state, + struct YAM_CHAN *chan, + sint32 *buf, + uint32 odometer, + uint32 samples +) { + uint32 g; + uint32 bufptrsave = state->bufptr; + +//gfreq[samples]++; + +//printf("generate_samples(%08X,%08X,%u)\n",chan,buf,samples); + + for(g = 0; g < samples; g++) { +//buf[g]=g*100;continue; + // + // If the amp envelope is inactive, quit + // + if(chan->EG.volume <= 0) { + break; + } + // + // If we must generate a sample, generate it + // + if(buf) { + // Apply filter, if we want it + sint32 s = AICA_UpdateSlot(state, chan); + if(!(chan->lpoff)) { + uint32 fv = chan->lpflevel; + uint32 qv = chan->q & 0x1F; + sint32 f = (((fv & 0xFF) | 0x100) << 4) >> ((fv >> 8) ^ 0x1F); + sint32 q = qtable[qv]; + s = f * s + (0x2000 - f + q) * (chan->lpp1) - q * (chan->lpp2); + s >>= 13; + chan->lpp2 = chan->lpp1; + chan->lpp1 = s; + } + // Write output + buf[g] = s; + } + state->bufptr = (state->bufptr + 32) & (32*RINGMAX-1); + // + // Now we need to advance the channel state machine, regardless of + // whether we're generating output or not + // + // + // Advance filter envelope + // + { uint32 effectiverate = env_adjustrate(chan, chan->fr[chan->lpfstate]); + if(env_needstep(effectiverate, odometer)) { + uint32 d = envdecayvalue[effectiverate][odometer&3]; + uint32 target = chan->flv[chan->lpfstate+1]; + if(chan->lpflevel < target) { + uint32 maxd = target - chan->lpflevel; + if(d > maxd) { d = maxd; } + chan->lpflevel += d; + } else if(chan->lpflevel > target) { + uint32 maxd = chan->lpflevel - target; + if(d > maxd) { d = maxd; } + chan->lpflevel -= d; + } else { + if(chan->lpfstate < 3) { chan->lpfstate++; } + } + } + } + // Advance our temporary odometer copy + odometer++; + // Done with this sample! + } + state->bufptr = bufptrsave; + return g; +} + +///////////////////////////////////////////////////////////////////////////// +// +// Render a single channel and add it to the given outputs +// +// directout or fxout may be NULL +// +static void render_and_add_channel( + struct YAM_STATE *state, + struct YAM_CHAN *chan, + sint32 *directout, + sint32 *fxout, + uint32 odometer, + uint32 samples +) { + uint32 i; + sint32 localbuf[RENDERMAX]; + uint32 rendersamples; + + // Channel does nothing if attenuation >= 0x3C0 + if(chan->EG.volume <= 0) { return; } + + if(!chan->disdl) { directout = NULL; } + if(!chan->dsplevel) { fxout = NULL; } + + // Generate samples + rendersamples = generate_samples( + state, + chan, + (directout || fxout || (state->version == 1 && !chan->stwinh)) ? localbuf : NULL, + odometer, + samples + ); + + // Add to output + if(directout) { + sint32 vol_l, vol_r; + convert_stereo_send_level( + chan->tl, + chan->disdl, + (state->mono) ? 0 : (chan->dipan), + &vol_l, &vol_r, + state->version + ); + for(i = 0; i < rendersamples; i++) { + directout[0] += (localbuf[i]*vol_l) >> SHIFT; + directout[1] += (localbuf[i]*vol_r) >> SHIFT; + directout += 2; + } + } + if(fxout) { + sint32 vol_l, vol_r; + convert_stereo_send_level( + chan->tl, + chan->dsplevel, + 0, + &vol_l, &vol_r, + state->version + ); + for(i = 0; i < rendersamples; i++) { + fxout[0] += (localbuf[i]*vol_l) >> (SHIFT-2); + fxout += 16; + } + } + +} + +///////////////////////////////////////////////////////////////////////////// +// +// Floating-point conversion +// +static uint32 __fastcall float16_to_int24(uint32 f) { + uint32 exponent = (f >> 11) & 0xF; + sint32 result; + result = (f & 0x8000) << 16; // take the sign in bit 31 + result >>= 1; // duplicate the sign in bit 30 + if(exponent >= 12) { exponent = 11; } // cap exponent to 11 for denormals + else { result ^= 0x40000000; } // reverse bit 30 for normals + result |= (f & 0x7FF) << 19; // set bits 29-0 to the mantissa + result >>= exponent + 8; // shift right by the exponent + 8 + return result; +} + +static uint32 __fastcall int24_to_float16(uint32 i) { + uint32 exponent = 0; + uint32 sign = i & 0x00800000; + if(sign) { i = ~i; } + i &= 0x7FFFFF; + if(i < 0x020000) { exponent += (6<<11); i <<= 6; } + if(i < 0x100000) { exponent += (3<<11); i <<= 3; } + if(i < 0x400000) { exponent += (1<<11); i <<= 1; } + if(i < 0x400000) { exponent += (1<<11); i <<= 1; } + if(i < 0x400000) { exponent += (1<<11); } + i >>= 11; + i &= 0x7FF; + i |= exponent; + if(sign) { i ^= 0x87FF; } + return i; +} + +///////////////////////////////////////////////////////////////////////////// + +#define SINT32ATOFFSET(a,b) (*((sint32*)(((uint8*)(a))+(b)))) + +///////////////////////////////////////////////////////////////////////////// +// +// Execute one sample on the effects DSP +// +static void __fastcall dsp_sample_interpret(struct YAM_STATE *state) { + const struct MPRO *mpro = state->mpro; + uint32 i; + // Pre-compute ringbuffer size mask + uint32 rbmask = (1 << ((state->rbl)+13)) - 1; + // + // For 128 steps: + // + for(i = 0; i < 128; i++, mpro++) { + sint32 b, x, y, shifted; + // + // Proper skip for "empty" instructions + // + if((mpro->__kisxzbon) & 0x80) { + x = state->temp[(state->mdec_ct)&0x7F]; + state->xzbchoice[XZBCHOICE_ACC] = + ((((sint64)x) * ((sint64)(state->yychoice[YYCHOICE_FRC_REG]))) >> 12) + x; + continue; + } + state->xzbchoice[XZBCHOICE_TEMP] = state->temp[((mpro->t_0rrrrrrr)+(state->mdec_ct))&0x7F]; + state->yychoice[YYCHOICE_COEF] = state->coef[mpro->c_0rrrrrrr]; + // + // Input read + // + state->xzbchoice[XZBCHOICE_INPUTS] = state->inputs[mpro->i_00rrrrrr]; + // + // Input write + // + state->inputs[mpro->i_0T0wwwww] = state->mem_in_data[i & 3]; + // + // B selection + // + b = SINT32ATOFFSET(state->xzbchoice, (mpro->__kisxzbon) & 0x0C); + b ^= ((sint32)(mpro->negb)); + b -= ((sint32)(mpro->negb)); + // + // X selection + // + x = SINT32ATOFFSET(state->xzbchoice, (mpro->__kisxzbon) & 0x10); + // + // Y selection + // + y = SINT32ATOFFSET(state->yychoice, (mpro->m_wrAFyyYh) & 0x0C); + // + // Y latch + // + if(mpro->m_wrAFyyYh & 2) { + sint32 inputs = state->xzbchoice[XZBCHOICE_INPUTS]; + state->yychoice[YYCHOICE_Y_REG_H] = inputs >> 11; + state->yychoice[YYCHOICE_Y_REG_L] = (inputs >> 4) & 0xFFF; + } + // + // Shift of previous accumulator + // + shifted = state->xzbchoice[XZBCHOICE_ACC] << ((mpro->m_wrAFyyYh) & 1); + if((mpro->__kisxzbon) & 0x20) { + if(shifted > ( 0x7FFFFF)) { shifted = ( 0x7FFFFF); } + if(shifted < (-0x800000)) { shifted = (-0x800000); } + } + // + // Multiply and accumulate + // + state->xzbchoice[XZBCHOICE_ACC] = ((((sint64)x) * ((sint64)y)) >> 12) + b; + // + // Temp write + // + if(mpro->t_Twwwwwww < 0x80) { + state->temp[((mpro->t_Twwwwwww)+(state->mdec_ct))&0x7F] = shifted; + } + // + // Fractional address latch + // + if((mpro->m_wrAFyyYh) & 0x10) { + if((mpro->__kisxzbon) & 0x40) { + state->yychoice[YYCHOICE_FRC_REG] = shifted & 0xFFF; + } else { + state->yychoice[YYCHOICE_FRC_REG] = shifted >> 11; + } + } + // + // Memory operations + // + if((mpro->m_wrAFyyYh) & 0xC0) { + sint32 tm = ((sint32)(mpro->tablemask)); + uint32 a = state->madrs[mpro->m_00aaaaaa]; + a += (state->adrs_reg) & ((sint32)(mpro->adrmask)); + a += (mpro->__kisxzbon) & 1; + a += (state->mdec_ct) & (~tm); + a &= (rbmask | tm) & 0xFFFF; + a <<= 1; + a += state->rbp; + a &= (state->ram_mask); + a ^= state->mem_word_address_xor; + if(mpro->m_wrAFyyYh & 0x40) { // MRD + sint32 memdata = *((sint16*)(((sint8*)(state->ram_ptr))+a)); + if(!(mpro->__kisxzbon & 2)) { memdata = float16_to_int24(memdata); } + else { memdata <<= 8; } + state->mem_in_data[(i+2)&3] = memdata; + } + if(mpro->m_wrAFyyYh & 0x80) { // MWT + sint32 memdata = shifted; + if(!(mpro->__kisxzbon & 2)) { memdata = int24_to_float16(memdata); } + else { memdata >>= 8; } + *((sint16*)(((sint8*)(state->ram_ptr))+a)) = memdata; + } + } + // + // Address latch + // + if((mpro->m_wrAFyyYh) & 0x20) { + if((mpro->__kisxzbon) & 0x40) { + state->adrs_reg = shifted >> 12; + } else { + state->adrs_reg = state->xzbchoice[XZBCHOICE_INPUTS] >> 16; + } + state->adrs_reg &= 0xFFF; + } + // + // Effect output write + // + state->efreg[mpro->e_000Twwww] = shifted >> 8; + // End of step + } +} + +///////////////////////////////////////////////////////////////////////////// +// +// +// + +#define C(N) { *outp++ = ((uint8)(N)); } +#define C32(N) { *((uint32*)outp) = ((uint32)(N)); outp += 4; } +#define C32CALL(N) { *((uint32*)outp) = ((uint32)(N)) - (((uint32)(outp))+4); outp += 4; } + +#define STRUCTOFS(thetype,thefield) ((uint32)(&(((struct thetype*)0)->thefield))) +#define STATEOFS(thefield) STRUCTOFS(YAM_STATE,thefield) + +static int instruction_uses_shifted(struct MPRO *mpro) { + // uses SHIFTED if: + // - ADRL and INTERP + if((mpro->m_wrAFyyYh & 0x20) != 0) { + if((mpro->__kisxzbon & 0x40) != 0) return 1; + } + // - FRCL + if((mpro->m_wrAFyyYh & 0x10) != 0) return 1; + // - EWT + if((mpro->e_000Twwww & 0x10) == 0) return 1; + // - TWT + if((mpro->t_Twwwwwww & 0x80) == 0) return 1; + // - MWT + if((mpro->m_wrAFyyYh & 0x80) != 0) return 1; + // otherwise not + return 0; +} + +// +// Compile x86 code out of the current DSP program/coef/address set +// Also uses the current ringbuffer pointer and size, and ram pointer/mask/memwordxor +// So if any of those change, the compiled dynacode must be invalidated +// +#ifdef ENABLE_DYNAREC +static void dynacompile(struct YAM_STATE *state) { + // Pre-compute ringbuffer size mask + uint32 rbmask = (1 << ((state->rbl)+13)) - 1; + + uint8 *outp = state->dynacode; + int i; + char ins_uses_acc[129]; + char ins_uses_shifted[129]; + // + // Put some slop here to avoid cache problems? + // + outp += DYNACODE_SLOP_SIZE; + // + // Figure out which instructions need what things + // + memset(ins_uses_acc, 0, sizeof(ins_uses_acc)); + memset(ins_uses_shifted, 0, sizeof(ins_uses_shifted)); + ins_uses_acc[128] = 1; + ins_uses_shifted[128] = 1; + for(i = 0; i < 128; i++) { + struct MPRO *mpro = state->mpro + i; + ins_uses_shifted[i] = instruction_uses_shifted(mpro); + ins_uses_acc[i] = + (ins_uses_shifted[i]) || + ((mpro->__kisxzbon & 0x0C) == 0x04); + } + + // + // Prefix + // + C(0x60) // pusha + C(0x89) C(0xCF) // mov edi, ecx + C(0x8B) C(0xAF) C32(STATEOFS(mdec_ct)) // mov ebp,[edi+] + C(0x8B) C(0xB7) C32(STATEOFS(xzbchoice[XZBCHOICE_ACC])) // mov esi,[edi+] + // 16 bytes + // + // Each instruction + // + for(i = 0; i < 128; i++) { + struct MPRO *mpro = state->mpro + i; + // + // If we need to compute the new accumulator, do so (to EAX) + // + if(ins_uses_acc[i + 1]) { + int need_tra = + ((mpro->__kisxzbon & 0x10) == 0x00) || + ((mpro->__kisxzbon & 0x0C) == 0x00); + // + // If we will need TRA in the future, compute it in ECX + // + if(need_tra) { + C(0x8D) C(0x4D) C(mpro->t_0rrrrrrr) // lea ecx,[ebp+] + C(0x83) C(0xE1) C(0x7F) // and ecx,7Fh + } + // 6 bytes max + // + // Load EAX with the Y value + // + switch(mpro->m_wrAFyyYh & 0x0C) { + case 0x00: // FRC_REG + C(0x8B) C(0x87) C32(STATEOFS(yychoice[YYCHOICE_FRC_REG])) // mov eax,[edi+yychoice0] + break; + case 0x04: // COEF + { sint32 coef = state->coef[mpro->c_0rrrrrrr]; + C(0xB8) C32(coef) // mov eax, + } + break; + case 0x08: // Y_REG_H + C(0x8B) C(0x87) C32(STATEOFS(yychoice[YYCHOICE_Y_REG_H])) // mov eax,[edi+yychoice2] + break; + case 0x0C: // Y_REG_L + C(0x8B) C(0x87) C32(STATEOFS(yychoice[YYCHOICE_Y_REG_L])) // mov eax,[edi+yychoice3] + break; + } + // 6 bytes max + // + // Multiply by the X value + // + if((mpro->__kisxzbon & 0x10) == 0) { + C(0xF7) C(0xAC) C(0x8F) C32(STATEOFS(temp)) // imul dword ptr [edi+ecx*4+temp] + } else { + C(0xF7) C(0xAF) C32(STATEOFS(inputs[mpro->i_00rrrrrr])) // imul dword ptr [edi+] + } + C(0x0F) C(0xAC) C(0xD0) C(0x0C) // shrd eax,edx,12 + // 11 bytes max + // + // Add B if necessary + // + if((mpro->__kisxzbon & 0x08) == 0) { + if(mpro->negb == 0) { + if((mpro->__kisxzbon & 0x04) == 0) { + C(0x03) C(0x84) C(0x8F) C32(STATEOFS(temp)) // add eax,[edi+ecx*4+] + } else { + C(0x01) C(0xF0) // add eax,esi + } + } else { + if((mpro->__kisxzbon & 0x04) == 0) { + C(0x2B) C(0x84) C(0x8F) C32(STATEOFS(temp)) // sub eax,[edi+ecx*4+] + } else { + C(0x29) C(0xF0) // sub eax,esi + } + } + } + // 7 bytes max + } + // 30 bytes max + // + // If YRL is on, latch Y register + // + if(mpro->m_wrAFyyYh & 2) { + C(0x8B) C(0x97) C32(STATEOFS(inputs[mpro->i_00rrrrrr])) // mov edx, [edi+] + C(0xC1) C(0xFA) C(0x0B) // sar edx,11 + C(0x89) C(0x97) C32(STATEOFS(yychoice[YYCHOICE_Y_REG_H])) // mov [edi+],edx + C(0x8B) C(0x97) C32(STATEOFS(inputs[mpro->i_00rrrrrr])) // mov edx, [edi+] + C(0xC1) C(0xFA) C(0x04) // sar edx,4 + C(0x81) C(0xE2) C32(0x00000FFF) // and edx,0FFFh + C(0x89) C(0x97) C32(STATEOFS(yychoice[YYCHOICE_Y_REG_L])) // mov [edi+],edx + } + // 36 bytes max + // + // If we will be needing SHIFTED this instruction, edx will become SHIFTED: + // + if(ins_uses_shifted[i]) { + if((mpro->__kisxzbon & 0x20) == 0) { // no saturate + C(0x89) C(0xF2) // mov edx,esi + C(0xC1) C(0xE2) C(8+(mpro->m_wrAFyyYh & 1)) // shl edx, + C(0xC1) C(0xFA) C(0x08) // sar edx,8 + // 8 bytes max + } else { // saturate + if((mpro->m_wrAFyyYh & 1) == 0) { // NOT shifting left + C(0x8D) C(0x96) C32(0x00800000) // lea edx,[esi+800000h] + C(0xF7) C(0xC2) C32(0xFF000000) // test edx,0FF000000h + C(0x89) C(0xF2) // mov edx,esi + // 14 bytes max + } else { // shifting left + C(0x8D) C(0x94) C(0x36) C32(0x00800000) // lea edx,[esi+esi+800000h] + C(0xF7) C(0xC2) C32(0xFF000000) // test edx,0FF000000h + C(0x8D) C(0x14) C(0x36) // lea edx,[esi+esi] + // 16 bytes max + } + C(0x74) C(0x09) // je +9bytes + C(0xC1) C(0xFA) C(0x1F) // sar edx,1Fh + C(0x81) C(0xF2) C32(0x007FFFFF) // xor edx,7FFFFFh + // 27 bytes max + } + } + // 27 bytes max + // + // If we need the accumulator next instruction, save it + // + if(ins_uses_acc[i + 1]) { + C(0x89) C(0xC6) // mov esi,eax + } + // 2 bytes max + // + // If FRCL is set, latch it + // + if(mpro->m_wrAFyyYh & 0x10) { + C(0x89) C(0xD0) //mov eax,edx + if(mpro->__kisxzbon & 0x40) { // interpolate mode + C(0x25) C32(0x00000FFF) // and eax,0FFFh + } else { // non-interpolate mode + C(0xC1) C(0xF8) C(0x0B) // sar eax,11 + } + C(0x89) C(0x87) C32(STATEOFS(yychoice[YYCHOICE_FRC_REG])) // mov [edi+],eax + } + // 13 bytes max + // + // If TWT is on, perform the temp write of SHIFTED + // + if((mpro->t_Twwwwwww & 0x80) == 0) { + C(0x8D) C(0x4D) C(mpro->t_Twwwwwww) // lea ecx,[ebp+] + C(0x83) C(0xE1) C(0x7F) // and ecx,7Fh + C(0x89) C(0x94) C(0x8F) C32(STATEOFS(temp)) // mov [edi+ecx*4+],edx + } + // 13 bytes max + // + // If EWT is on, perform write of EFREG + // + if((mpro->e_000Twwww & 0x10) == 0) { + C(0x89) C(0xD0) // mov eax,edx + C(0xC1) C(0xF8) C(0x08) // sar eax,8 + C(0x89) C(0x87) C32(STATEOFS(efreg[mpro->e_000Twwww])) // mov [edi+],eax + } + // 11 bytes max + // + // If we'll be needing an address, compute it in EBX (a word address) + // ODD LINES ONLY + // + if((i & 1) && (mpro->m_wrAFyyYh & 0xC0)) { + uint32 madrsnx = state->madrs[mpro->m_00aaaaaa]; + if(mpro->__kisxzbon & 1) { madrsnx++; } + madrsnx &= 0xFFFF; + if(mpro->tablemask == 0) { + C(0x8D) C(0x9D) C32(madrsnx) // lea ebx,[ebp+] + if(mpro->adrmask != 0) { + C(0x03) C(0x9F) C32(STATEOFS(adrs_reg)) // add ebx,[edi+] + } + C(0x81) C(0xE3) C32(rbmask) // and ebx, + // 18 bytes max + } else { + C(0xBB) C32(madrsnx) // mov ebx, + if(mpro->adrmask != 0) { + C(0x03) C(0x9F) C32(STATEOFS(adrs_reg)) // add ebx,[edi+] + C(0x81) C(0xE3) C32(0x0000FFFF) // and ebx,0FFFFh + } + // 17 bytes max + } + C(0x81) C(0xC3) C32(state->rbp / 2) // add ebx, + C(0x81) C(0xE3) C32(state->ram_mask / 2) // and ebx, + if((state->mem_word_address_xor / 2) != 0) { + C(0x83) C(0xF3) C(state->mem_word_address_xor / 2) // xor ebx, + } + } + // 33 bytes max ODD LINES ONLY + // + // If ADRL is set, latch address reg + // + if(mpro->m_wrAFyyYh & 0x20) { + if(mpro->__kisxzbon & 0x40) { // interpolate mode + C(0x89) C(0xD0) // mov eax,edx + C(0xC1) C(0xF8) C(0x0C) // sar eax,12 + } else { + C(0x8B) C(0x87) C32(STATEOFS(inputs[mpro->i_00rrrrrr])) // mov eax,[edi+] + C(0xC1) C(0xF8) C(0x10) // sar eax,16 + } + C(0x25) C32(0x00000FFF) // and eax,0FFFh + C(0x89) C(0x87) C32(STATEOFS(adrs_reg)) // mov [edi+],eax + } + // 20 bytes max + // + // If MRD is set, read from ebx*2: + // ODD LINES ONLY + // + if((i & 1) && (mpro->m_wrAFyyYh & 0x40)) { + if((mpro->__kisxzbon & 0x02) == 0) { // NOFL=0 + C(0x0F) C(0xBF) C(0x8C) C(0x1B) C32(state->ram_ptr) // movsx ecx, word ptr [ebx+ebx+] + C(0xE8) C32CALL(float16_to_int24) // call float16_to_int24 + // 13 bytes max + } else { // NOFL=1: + C(0x0F) C(0xBF) C(0x84) C(0x1B) C32(state->ram_ptr) // movsx eax, word ptr [ebx+ebx+] + C(0xC1) C(0xE0) C(0x08) // shl eax,8 + // 11 bytes max + } + C(0x89) C(0x87) C32(STATEOFS(mem_in_data[(i+2)&3])) // mov [edi+],eax + // 19 bytes max + // + // Or, if MWT is set, write edx to ebx*2: + // ODD LINES ONLY + // + } else if((i & 1) && (mpro->m_wrAFyyYh & 0x80)) { + if((mpro->__kisxzbon & 0x02) == 0) { // NOFL=0 + C(0x89) C(0xD1) // mov ecx,edx + C(0xE8) C32CALL(int24_to_float16) // call int24_to_float16 + C(0x66) C(0x89) C(0x84) C(0x1B) C32(state->ram_ptr) // mov [ebx+ebx+],ax + // 15 bytes max + } else { // NOFL=1: + C(0xC1) C(0xFA) C(0x08) // sar edx,8 + C(0x66) C(0x89) C(0x94) C(0x1B) C32(state->ram_ptr) // mov [ebx+ebx+],dx + // 11 bytes max + } + // 15 bytes max + } + // 19 bytes max ODD LINES ONLY + // + // If IWT is on, perform input write + // ODD LINES ONLY + // + if((i&1) && ((mpro->i_0T0wwwww & 0x40) == 0)) { + C(0x8B) C(0x97) C32(STATEOFS(mem_in_data[i&3])) // mov edx, [edi+] + C(0x89) C(0x97) C32(STATEOFS(inputs[mpro->i_0T0wwwww])) // mov [edi+],edx + } + // 12 bytes max ODD LINES ONLY + } + // + // Suffix + // + C(0x89) C(0xB7) C32(STATEOFS(xzbchoice[XZBCHOICE_ACC])) // mov [edi+],esi + C(0x61) // popa + C(0xC3) // retn + // 8 bytes + // + // Set valid flag + // + state->dsp_dyna_valid = 1; + +//{FILE*f=fopen("C:\\Corlett\\yamdyna.bin","wb");if(f){fwrite(state->dynacode,1,0x6000,f);fclose(f);}} + +} +#endif + +///////////////////////////////////////////////////////////////////////////// + +typedef void (__fastcall *dsp_sample_t)(struct YAM_STATE *state); + +///////////////////////////////////////////////////////////////////////////// +// +// Render effects by emulating the DSP +// +static void render_effects( + struct YAM_STATE *state, + sint32 *fxbus, + sint32 *out, + uint32 samples +) { + dsp_sample_t samplefunc; + uint32 i, j; + sint32 efvol_l[16]; + sint32 efvol_r[16]; + +#ifdef ENABLE_DYNAREC + if(state->dsp_dyna_enabled) { + if(!(state->dsp_dyna_valid)) { + dynacompile(state); + } + samplefunc = (dsp_sample_t)(((uint8*)(state->dynacode)) + DYNACODE_SLOP_SIZE); +#else + if (0) { +#endif + } else { + samplefunc = dsp_sample_interpret; + } + + // + // Determine what the effect out levels are, for left and right + // + for(j = 0; j < 16; j++) { + convert_stereo_send_level( + 0x00, + state->efsdl[j], + (state->mono) ? 0 : state->efpan[j], + efvol_l + j, efvol_r + j, + state->version + ); + } + // + // For every sample: + // + for(i = 0; i < samples; i++, fxbus += 16, out += 2) { + // + // Clip and copy fxbus inputs (20-bit, pre-promote to 24-bit) + // + for(j = 0; j < 16; j++) { + sint32 t = fxbus[j]; + if(t < (-0x80000)) t = (-0x80000); + if(t > ( 0x7FFFF)) t = ( 0x7FFFF); + state->inputs[0x20 + j] = t << 4; + } + // + // Execute one DSP sample + // + samplefunc(state); + // Advance MDEC_CT + state->mdec_ct--; + // + // Copy outputs out of EFREG, scale accordingly, and add to output + // + for(j = 0; j < 16; j++) if(state->efsdl[j]) { + sint32 ef = (sint32)((sint16)(state->efreg[j])); + out[0] += (ef*efvol_l[j]) >> SHIFT; + out[1] += (ef*efvol_r[j]) >> SHIFT; + } + } + +} + +///////////////////////////////////////////////////////////////////////////// +// +// Must not render more than RENDERMAX samples at a time +// +struct render_priority +{ + sint32 channel_number; + sint32 priority_level; +}; +int __cdecl render_priority_compare(void * a, void * b) { + struct render_priority *_a = (struct render_priority *) a; + struct render_priority *_b = (struct render_priority *) b; + return _b->priority_level - _a->priority_level; +} +static void render(struct YAM_STATE *state, uint32 odometer, uint32 samples) { + uint32 i, j; + struct render_priority priority_list[64]; + sint32 outbuf[2*RENDERMAX]; + sint32 fxbus[16*RENDERMAX]; + sint32 *directout; +// sint32 *fxout; + sint16 *buf; + uint32 nchannels; + uint32 bufptr_base; + int wantreverb = 0; + if(!samples) return; + buf = YAMSTATE->out_buf; + directout = (buf && (state->dry_out_enabled)) ? outbuf : NULL; + nchannels = ((YAMSTATE->version) == 1) ? 32 : 64; + +// st=odometer; +//if(odometer>=11*44100)dumpch(YAMSTATE,YAMSTATE->chan+11); +/* +if(odometer >= 11*44100) { +static int dumped=0; +if(!dumped) { +dumped=1; +{FILE*f=fopen("C:\\Corlett\\yamdump.ram","wb"); +if(f){ +fwrite(YAMSTATE->ram_ptr,0x200000,1,f); +fclose(f); +} +} +} +} +*/ + +//logstep(state,odometer); + + // figure out if we want reverb or not + if(buf && (state->dsp_emulation_enabled)) { + for(i = 0; i < 16; i++) { if(state->efsdl[i] != 0) break; } + wantreverb = (i < 16); + } else { + wantreverb = 0; + } + if(buf) { + memset(outbuf, 0, 4*2*samples); + if(wantreverb) memset(fxbus, 0, 4*16*samples); + } + // + // Figure out if any channels need to be rendered before others + // + for(i = 0; i < nchannels; i++) { + priority_list[i].channel_number = i; + priority_list[i].priority_level = 0; + } + if (state->version == 1) { + for(i = 0; i < nchannels; i++) { + struct YAM_CHAN *chan = state->chan + i; + sint32 priority_level = priority_list[i].priority_level + 1; + if (chan->mdxsl) priority_list[(i+chan->mdxsl)&31].priority_level = priority_level; + if (chan->mdysl) priority_list[(i+chan->mdysl)&31].priority_level = priority_level; + } + qsort(&priority_list, nchannels, sizeof(*priority_list), render_priority_compare); + } + bufptr_base = state->bufptr; + // + // Render each channel + // + for(i = 0; i < nchannels; i++) { + struct YAM_CHAN *chan; + j = priority_list[i].channel_number; + chan = state->chan + j; + state->bufptr = bufptr_base + j; +// is 11 + render_and_add_channel(state, chan, directout, + wantreverb ? (fxbus + chan->dspchan) : NULL, + odometer, samples + ); + } + state->bufptr = (bufptr_base + (32*samples)) & (32*RINGMAX-1); + // + // Emulate DSP effects if desired + // + if(wantreverb) { render_effects(state, fxbus, outbuf, samples); } + // + // Scale, clip and copy output + // + if(buf) { + sint32 vol_l, vol_r; + const sint32 shift = SHIFT + 3 + state->version; + convert_stereo_send_level(0x00, state->mvol, 0x00, &vol_l, &vol_r, 2); + for(i = 0; i < samples; i++) { + sint32 l = outbuf[2 * i + 0]; + sint32 r = outbuf[2 * i + 1]; + l *= vol_l; l >>= shift; + r *= vol_l; r >>= shift; + l = ICLIP16(l); + r = ICLIP16(r); + buf[2 * i + 0] = l; + buf[2 * i + 1] = r; + } + } +} + +///////////////////////////////////////////////////////////////////////////// +// +// Flush all pending samples into the output buffer +// +void EMU_CALL yam_flush(void *state) { +// return; +//printf("yam_flush(%up)",YAMSTATE->out_pending); + + for(;;) { + uint32 n = YAMSTATE->out_pending; + if(n < 1) { break; } + if(n > RENDERMAX) { n = RENDERMAX; } + render(YAMSTATE, YAMSTATE->odometer - YAMSTATE->out_pending, n); + YAMSTATE->out_pending -= n; + if(YAMSTATE->out_buf) { YAMSTATE->out_buf += 2 * n; } + } +} + +///////////////////////////////////////////////////////////////////////////// +// +// Prepare or unprepare dynacode buffer for execution +// +void EMU_CALL yam_prepare_dynacode(void *state) { +#ifdef ENABLE_DYNAREC +#ifdef _WIN32 + DWORD i; + VirtualProtect( &YAMSTATE->dynacode, sizeof(YAMSTATE->dynacode), PAGE_EXECUTE_READWRITE, &i ); +#elif defined(HAVE_MPROTECT) + unsigned long startaddr = &YAMSTATE->dynacode; + unsigned long length = sizeof(YAMSTATE->dynacode); + int psize = getpagesize(); + unsigned long addr = ( startaddr & ~(psize - 1) ); + mprotect( (char *) addr, length + startaddr - addr + psize, PROT_READ | PROT_WRITE | PROT_EXEC ); +#endif +#endif +} + +void EMU_CALL yam_unprepare_dynacode(void *state) { +#ifdef ENABLE_DYNAREC +#ifdef _WIN32 + DWORD i; + VirtualProtect( &YAMSTATE->dynacode, sizeof(YAMSTATE->dynacode), PAGE_READWRITE, &i ); +#elif defined(HAVE_MPROTECT) + unsigned long startaddr = &YAMSTATE->dynacode; + unsigned long length = sizeof(YAMSTATE->dynacode); + int psize = getpagesize(); + unsigned long addr = ( startaddr & ~(psize - 1) ); + mprotect( (char *) addr, length + startaddr - addr + psize, PROT_READ | PROT_WRITE ); +#endif +#endif +} + +///////////////////////////////////////////////////////////////////////////// diff --git a/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/yam.h b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/yam.h new file mode 100644 index 000000000..272d6fb1c --- /dev/null +++ b/Frameworks/HighlyTheoretical/HighlyTheoretical/Core/yam.h @@ -0,0 +1,52 @@ +///////////////////////////////////////////////////////////////////////////// +// +// yam - Emulates Yamaha SCSP and AICA +// +///////////////////////////////////////////////////////////////////////////// + +#ifndef __SEGA_YAM_H__ +#define __SEGA_YAM_H__ + +#include "emuconfig.h" + +#ifdef __cplusplus +extern "C" { +#endif + +///////////////////////////////////////////////////////////////////////////// + +// version = 1 for SCSP, 2 for AICA +// ramsize must be a power of 2 + +sint32 EMU_CALL yam_init(void); +uint32 EMU_CALL yam_get_state_size(uint8 version); +void EMU_CALL yam_clear_state(void *state, uint8 version); + +void EMU_CALL yam_enable_dry(void *state, uint8 enable); +void EMU_CALL yam_enable_dsp(void *state, uint8 enable); +void EMU_CALL yam_enable_dsp_dynarec(void *state, uint8 enable); + +void EMU_CALL yam_setram(void *state, uint32 *ram, uint32 size, uint8 mbx, uint8 mwx); +void EMU_CALL yam_beginbuffer(void *state, sint16 *buf); +void EMU_CALL yam_advance(void *state, uint32 samples); +void EMU_CALL yam_flush(void *state); + +uint32 EMU_CALL yam_aica_load_reg(void *state, uint32 a, uint32 mask); +void EMU_CALL yam_aica_store_reg(void *state, uint32 a, uint32 d, uint32 mask, uint8 *breakcpu); + +uint32 EMU_CALL yam_scsp_load_reg(void *state, uint32 a, uint32 mask); +void EMU_CALL yam_scsp_store_reg(void *state, uint32 a, uint32 d, uint32 mask, uint8 *breakcpu); + +uint8* EMU_CALL yam_get_interrupt_pending_ptr(void *state); +uint32 EMU_CALL yam_get_min_samples_until_interrupt(void *state); + +void EMU_CALL yam_prepare_dynacode(void *state); +void EMU_CALL yam_unprepare_dynacode(void *state); + +///////////////////////////////////////////////////////////////////////////// + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Frameworks/HighlyTheoretical/HighlyTheoretical/HighlyTheoretical-Info.plist b/Frameworks/HighlyTheoretical/HighlyTheoretical/HighlyTheoretical-Info.plist new file mode 100644 index 000000000..02c2a8310 --- /dev/null +++ b/Frameworks/HighlyTheoretical/HighlyTheoretical/HighlyTheoretical-Info.plist @@ -0,0 +1,30 @@ + + + + + CFBundleDevelopmentRegion + English + CFBundleExecutable + ${EXECUTABLE_NAME} + CFBundleIconFile + + CFBundleIdentifier + NoWork-Inc.${PRODUCT_NAME:rfc1034identifier} + CFBundleInfoDictionaryVersion + 6.0 + CFBundleName + ${PRODUCT_NAME} + CFBundlePackageType + FMWK + CFBundleShortVersionString + 1.0 + CFBundleSignature + ???? + CFBundleVersion + 1 + NSHumanReadableCopyright + Copyright © 2013 Christopher Snowhill. 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+ int reserved_size; + struct SOURCE_FILE *next; +}; + +struct DIR_ENTRY { + char name[37]; + struct DIR_ENTRY *subdir; + int length; + int block_size; + struct SOURCE_FILE *source; + int *offset_table; + struct DIR_ENTRY *next; +}; + +struct CACHEBLOCK { + struct SOURCE_FILE *from_source; + int from_offset; + char *uncompressed_data; + int uncompressed_size; +}; + +struct PSF2FS { + struct SOURCE_FILE *sources; + struct DIR_ENTRY *dir; + struct CACHEBLOCK cacheblock; + + int adderror; +}; + +///////////////////////////////////////////////////////////////////////////// + +static void source_cleanup_free(struct SOURCE_FILE *source) { + while(source) { + struct SOURCE_FILE *next = source->next; + if(source->reserved_data) free( source->reserved_data ); + free( source ); + source = next; + } +} + +static void dir_cleanup_free(struct DIR_ENTRY *dir) { + while(dir) { + struct DIR_ENTRY *next = dir->next; + if(dir->subdir) dir_cleanup_free(dir->subdir); + free( dir ); + dir = next; + } +} + +static void cache_cleanup(struct CACHEBLOCK *cacheblock) { + if(!cacheblock) return; + if(cacheblock->uncompressed_data) free( cacheblock->uncompressed_data ); +} + +///////////////////////////////////////////////////////////////////////////// + +void *psf2fs_create(void) { + struct PSF2FS *fs; + fs = ( struct PSF2FS * ) malloc( sizeof( struct PSF2FS ) ); + if(!fs) return NULL; + memset(fs, 0, sizeof(struct PSF2FS)); + return fs; +} + +///////////////////////////////////////////////////////////////////////////// + +void psf2fs_delete(void *psf2fs) { + struct PSF2FS *fs = (struct PSF2FS*)psf2fs; + if(fs->sources) source_cleanup_free(fs->sources); + if(fs->dir) dir_cleanup_free(fs->dir); + cache_cleanup(&(fs->cacheblock)); + free( fs ); +} + +///////////////////////////////////////////////////////////////////////////// + +static int isdirsep(char c) { return (c == '/' || c == '\\' || c == '|' || c == ':'); } + +static void makelibpath(const char *path, const char *libpath, char *finalpath, int finalpath_length) { + int l; + int p_l = 0; + for(l = 0; path[l]; l++) { if(isdirsep(path[l])) { p_l = l + 1; } } + while(isdirsep(*libpath)) libpath++; + if(!finalpath_length) return; + *finalpath = 0; + if(p_l > (finalpath_length - 1)) p_l = (finalpath_length - 1); + if(p_l) { + memcpy(finalpath, path, p_l); + finalpath[p_l] = 0; + finalpath += p_l; + finalpath_length -= p_l; + } + if(!finalpath_length) return; + strncpy(finalpath, libpath, finalpath_length); + finalpath[finalpath_length - 1] = 0; +} + +///////////////////////////////////////////////////////////////////////////// + +static unsigned read32lsb(const uint8_t * foo) { + return ( + ((foo[0] & 0xFF) << 0) | + ((foo[1] & 0xFF) << 8) | + ((foo[2] & 0xFF) << 16) | + ((foo[3] & 0xFF) << 24) + ); +} + +///////////////////////////////////////////////////////////////////////////// + +static int __memicmp(const char * a, const char * b, int length) +{ + int o, p; + for (o = 0; o < length; o++) { + p = tolower(a[o]) - tolower(b[o]); + if (p) return p; + } + return 0; +} + +///////////////////////////////////////////////////////////////////////////// + +static struct DIR_ENTRY *finddirentry( + struct DIR_ENTRY *dir, + const char *name, + int name_l +) { + if(name_l > 36) return NULL; + while(dir) { + if(!__memicmp(dir->name, name, name_l) && dir->name[name_l] == 0) return dir; + dir = dir->next; + } + return NULL; +} + +///////////////////////////////////////////////////////////////////////////// +// +// Make a DIR_ENTRY list for a given file and Reserved offset. +// Recurses subdirectories also. +// All entries are set to point to the given SOURCE_FILE. +// +static struct DIR_ENTRY *makearchivedir( + struct PSF2FS *fs, + int offset, + struct SOURCE_FILE *source +) { + struct DIR_ENTRY *dir = NULL; + const uint8_t *file = source->reserved_data; + int n, num; + if(offset < 0) goto corrupt; + if(offset >= source->reserved_size) { goto corrupt; } + if((offset + 4) > source->reserved_size) { goto corrupt; } + num = read32lsb(file + offset); + offset += 4; + if(num < 0) goto corrupt; + for(n = 0; n < num; n++) { + int o, u, b; + if((offset + 48) > source->reserved_size) { goto corrupt; } + { struct DIR_ENTRY *entry = ( struct DIR_ENTRY * ) malloc( sizeof( struct DIR_ENTRY ) ); + if(!entry) goto outofmemory; + memset(entry, 0, sizeof(struct DIR_ENTRY)); + entry->next = dir; + dir = entry; + } + memcpy(dir->name, file + offset, 36); + o = read32lsb(file + offset + 36); + u = read32lsb(file + offset + 40); + b = read32lsb(file + offset + 44); + offset += 48; + if(o < 0) goto corrupt; + if(u < 0) goto corrupt; + if(b < 0) goto corrupt; + if(o && o < offset) { +// char s[100]; +// sprintf(s,"q[o=%08X offset=%08X]",o,offset); +// errormessageadd(fs, s); + goto corrupt; + } + // if this new entry describes a subdirectory: + if(u == 0 && b == 0 && o != 0) { + dir->subdir = makearchivedir(fs, o, source); + if(fs->adderror) goto error; +// if(!dir->subdir) goto error; + // if this new entry describes a zero-length file: + } else if(u == 0 || b == 0 || o == 0) { + // fields were zero anyway + // if this new entry describes a real source file: + } else { + int i; + int blocks = (u + (b-1)) / b; + int dataofs = o + 4 * blocks; + if(dataofs >= source->reserved_size) { goto corrupt; } + // record the info + dir->length = u; + dir->block_size = b; + dir->source = source; + dir->offset_table = (int *) malloc( ( blocks + 1 ) * sizeof( int ) ); + if(!dir->offset_table) goto outofmemory; + for(i = 0; i < blocks; i++) { + int cbs; + if((o + 4) > source->reserved_size) { goto corrupt; } + cbs = read32lsb(file + o); + o += 4; + dir->offset_table[i] = dataofs; + dataofs += cbs; + } + dir->offset_table[i] = dataofs; + } + } +success: + return dir; + +corrupt: + goto error; +outofmemory: + goto error; +error: + dir_cleanup_free(dir); + fs->adderror = 1; + return NULL; +} + +///////////////////////////////////////////////////////////////////////////// +// +// Merge two SOURCE_FILE lists. +// Guaranteed to succeed and not to free anything. +// +static struct SOURCE_FILE *mergesource( + struct SOURCE_FILE *to, + struct SOURCE_FILE *from +) { + struct SOURCE_FILE *to_tail; + if(!to && !from) return NULL; + if(!to) { + struct SOURCE_FILE *t; + t = to; to = from; from = t; + } + to_tail = to; + while(to_tail->next) { to_tail = to_tail->next; } + to_tail->next = from; + return to; +} + +///////////////////////////////////////////////////////////////////////////// +// +// Merge two DIR_ENTRY lists. +// Guaranteed to succeed. May free some structures. +// +static struct DIR_ENTRY *mergedir( + struct DIR_ENTRY *to, + struct DIR_ENTRY *from +) { + // will traverse "from", and add to "to". + while(from) { + struct DIR_ENTRY *entry_to; + struct DIR_ENTRY *entry_from; + entry_from = from; + from = from->next; + // delink entry_from + entry_from->next = NULL; + // look for a duplicate entry in "to" + entry_to = finddirentry(to, entry_from->name, strlen(entry_from->name)); + // if there is one, do something fancy and then free entry_from. + if(entry_to) { + // if both are subdirs, merge the subdirs + if((entry_to->subdir) && (entry_from->subdir)) { + entry_to->subdir = mergedir(entry_to->subdir, entry_from->subdir); + entry_from->subdir = NULL; + // if both are files, copy over the info + } else if((!(entry_to->subdir)) && (!(entry_from->subdir))) { + entry_to->length = entry_from->length; + entry_to->block_size = entry_from->block_size; + entry_to->source = entry_from->source; + if(entry_to->offset_table) free( entry_to->offset_table ); + entry_to->offset_table = entry_from->offset_table; + entry_from->offset_table = NULL; + // if one's a subdir but the other's not, we lose "from". this is fine. + } + dir_cleanup_free(entry_from); + entry_from = NULL; + // otherwise, just relink to the top of "to" + } else { + entry_from->next = to; + to = entry_from; + } + } + return to; +} + +///////////////////////////////////////////////////////////////////////////// +// +// only modifies *psource and *pdir on success +// +static int addarchive( + struct PSF2FS *fs, + const uint8_t *reserved_data, + int reserved_size, + struct SOURCE_FILE **psource, + struct DIR_ENTRY **pdir +) { + struct SOURCE_FILE *source = *psource; + struct DIR_ENTRY *dir = *pdir; + // these relate to the current file + struct SOURCE_FILE *this_source = NULL; + struct DIR_ENTRY *this_dir = NULL; + + // default to no error + fs->adderror = 0; + + // create a source entry for this psf2 + this_source = ( struct SOURCE_FILE * ) malloc( sizeof( struct SOURCE_FILE ) ); + if(!this_source) goto outofmemory; + this_source->reserved_data = ( uint8_t * ) malloc( reserved_size ); + if(!this_source->reserved_data) goto outofmemory; + memcpy(this_source->reserved_data, reserved_data, reserved_size); + this_source->reserved_size = reserved_size; + this_source->next = NULL; + this_dir = makearchivedir(fs, 0, this_source); + if(fs->adderror) goto error; + + // success + // now merge everything + *psource = mergesource(source, this_source); + *pdir = mergedir(dir, this_dir); +success: + return 0; + +outofmemory: + goto error; +error: + if(dir) dir_cleanup_free(dir); + if(source) source_cleanup_free(source); + if(this_dir) dir_cleanup_free(this_dir); + if(this_source) source_cleanup_free(this_source); + return -1; +} + +///////////////////////////////////////////////////////////////////////////// +// +// +// +int psf2fs_load_callback(void * psf2fs, const uint8_t * exe, size_t exe_size, + const uint8_t * reserved, size_t reserved_size) { + struct PSF2FS *fs = (struct PSF2FS*)psf2fs; + (void)exe; + (void)exe_size; + return addarchive(fs, reserved, reserved_size, &(fs->sources), &(fs->dir)); +} + +///////////////////////////////////////////////////////////////////////////// +// +// +// +static int virtual_read(struct PSF2FS *fs, struct DIR_ENTRY *entry, int offset, char *buffer, int length) { + int length_read = 0; + int r; + unsigned long destlen; + if(offset >= entry->length) return 0; + if((offset + length) > entry->length) length = entry->length - offset; + while(length_read < length) { + // get info on the current block + int blocknum = offset / entry->block_size; + int ofs_within_block = offset % entry->block_size; + int canread; + int block_zofs = entry->offset_table[blocknum]; + int block_zsize = entry->offset_table[blocknum+1] - block_zofs; + int block_usize; + if(block_zofs <= 0 || block_zofs >= entry->source->reserved_size) goto bounds; + if((block_zofs+block_zsize) > entry->source->reserved_size) goto bounds; + + // get the actual uncompressed size of this block + block_usize = entry->length - (blocknum * entry->block_size); + if(block_usize > entry->block_size) block_usize = entry->block_size; + + // if it's not already in the cache block, read it + if( + (fs->cacheblock.from_offset != block_zofs) || + (fs->cacheblock.from_source != entry->source) + ) { + // invalidate cache without freeing buffer + fs->cacheblock.from_source = NULL; + + // make sure there's a buffer allocated + // but only reallocate if the size is different + if(fs->cacheblock.uncompressed_size != block_usize) { + fs->cacheblock.uncompressed_size = 0; + if(fs->cacheblock.uncompressed_data) { + free( fs->cacheblock.uncompressed_data ); + fs->cacheblock.uncompressed_data = NULL; + } + fs->cacheblock.uncompressed_data = ( char * ) malloc( block_usize ); + if(!fs->cacheblock.uncompressed_data) goto outofmemory; + fs->cacheblock.uncompressed_size = block_usize; + } + destlen = block_usize; + // attempt decompress + r = uncompress((unsigned char *) fs->cacheblock.uncompressed_data, &destlen, (const unsigned char *) entry->source->reserved_data + block_zofs, block_zsize); + if(r != Z_OK || destlen != block_usize) { +// char s[999]; +// sprintf(s,"zdata=%02X %02X %02X blockz=%d blocku=%d destlenout=%d", zdata[0], zdata[1], zdata[2], block_zsize, block_usize, destlen); +// errormessageadd(fs, s); + goto error; + } + } + + // at this point, we can read whatever we want out of the cacheblock + canread = fs->cacheblock.uncompressed_size - ofs_within_block; + if(canread > (length - length_read)) canread = length - length_read; + + // copy + memcpy(buffer, fs->cacheblock.uncompressed_data + ofs_within_block, canread); + + // advance pointers/counters + offset += canread; + length_read += canread; + buffer += canread; + } + +success: + return length_read; + +bounds: + goto error; +outofmemory: + goto error; +error: + // if cacheblock was invalidated, we can free it + if(!fs->cacheblock.from_source) { + fs->cacheblock.uncompressed_size = 0; + if(fs->cacheblock.uncompressed_data) { + free( fs->cacheblock.uncompressed_data ); + fs->cacheblock.uncompressed_data = NULL; + } + } + return -1; +} + +///////////////////////////////////////////////////////////////////////////// +// +// +// +int psf2fs_virtual_readfile(void *psf2fs, const char *path, int offset, char *buffer, int length) { + struct PSF2FS *fs = (struct PSF2FS*)psf2fs; + struct DIR_ENTRY *entry = fs->dir; + + + if(!path) goto invalidarg; + if(offset < 0) goto invalidarg; + if(!buffer) goto invalidarg; + if(length < 0) goto invalidarg; + + for(;;) { + int l; + int need_dir; + if(!entry) goto pathnotfound; + while(isdirsep(*path)) path++; + for(l = 0;; l++) { + if(!path[l]) { need_dir = 0; break; } + if(isdirsep(path[l])) { need_dir = 1; break; } + } + entry = finddirentry(entry, path, l); + if(!entry) goto pathnotfound; + if(!need_dir) break; + entry = entry->subdir; + path += l; + } + + // if we "found" a file but it's a directory, then we didn't find it + if(entry->subdir) goto pathnotfound; + + // special case: if requested length is 0, return the total file length + if(!length) return entry->length; + + // otherwise, read from source + return virtual_read(fs, entry, offset, buffer, length); + +pathnotfound: + goto error; +invalidarg: + goto error; +error: + return -1; +} + +///////////////////////////////////////////////////////////////////////////// diff --git a/Frameworks/psflib/psflib/psf2fs.h b/Frameworks/psflib/psflib/psf2fs.h new file mode 100644 index 000000000..f76d01afb --- /dev/null +++ b/Frameworks/psflib/psflib/psf2fs.h @@ -0,0 +1,23 @@ +#ifndef PSF2FS_H +#define PSF2FS_H + +#include "psflib.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void * psf2fs_create(); + +void psf2fs_delete( void * ); + +int psf2fs_load_callback(void * psf2vfs, const uint8_t * exe, size_t exe_size, + const uint8_t * reserved, size_t reserved_size); + +int psf2fs_virtual_readfile(void *psf2vfs, const char *path, int offset, char *buffer, int length); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Frameworks/psflib/psflib/psflib-Info.plist b/Frameworks/psflib/psflib/psflib-Info.plist new file mode 100644 index 000000000..02c2a8310 --- /dev/null +++ b/Frameworks/psflib/psflib/psflib-Info.plist @@ -0,0 +1,30 @@ + + + + + CFBundleDevelopmentRegion + English + CFBundleExecutable + ${EXECUTABLE_NAME} + CFBundleIconFile + + CFBundleIdentifier + NoWork-Inc.${PRODUCT_NAME:rfc1034identifier} + CFBundleInfoDictionaryVersion + 6.0 + CFBundleName + ${PRODUCT_NAME} + CFBundlePackageType + FMWK + CFBundleShortVersionString + 1.0 + CFBundleSignature + ???? + CFBundleVersion + 1 + NSHumanReadableCopyright + Copyright © 2013 Christopher Snowhill. All rights reserved. + NSPrincipalClass + + + diff --git a/Frameworks/psflib/psflib/psflib.c b/Frameworks/psflib/psflib/psflib.c new file mode 100644 index 000000000..aaf5f41e8 --- /dev/null +++ b/Frameworks/psflib/psflib/psflib.c @@ -0,0 +1,518 @@ +#include "psflib.h" + +#include +#include + +#include + +#ifdef _MSC_VER +#define snprintf sprintf_s +#define strcasecmp _stricmp +#else +#include +#endif + +#define strdup(s) my_strdup(s) + +static char * my_strdup(const char * s) +{ + size_t l; + char * r; + if (!s) return NULL; + l = strlen(s) + 1; + r = (char *) malloc(l); + if (!r) return NULL; + memcpy(r, s, l); + return r; +} + +const char * strrpbrk( const char * s, const char * accept) +{ + const char * start; + + if ( !s || !*s || !accept || !*accept ) return NULL; + + start = s; + s += strlen( s ) - 1; + + while (s >= start) + { + const char *a = accept; + while (*a != '\0') + if (*a++ == *s) + return s; + --s; + } + + return NULL; +} + +enum { max_recursion_depth = 10 }; + +typedef struct psf_load_state +{ + int depth; + + unsigned char allowed_version; + + char * base_path; + const psf_file_callbacks * file_callbacks; + + psf_load_callback load_target; + void * load_context; + + psf_info_callback info_target; + void * info_context; + + char lib_name_temp[32]; +} psf_load_state; + +static int psf_load_internal( psf_load_state * state, const char * file_name ); + +int psf_load( const char * uri, const psf_file_callbacks * file_callbacks, uint8_t allowed_version, + psf_load_callback load_target, void * load_context, psf_info_callback info_target, void * info_context ) +{ + int rval; + + psf_load_state state; + + const char * file_name; + + if ( !uri || !*uri || !file_callbacks || !file_callbacks->path_separators || !*file_callbacks->path_separators || !file_callbacks->fopen || + !file_callbacks->fread || !file_callbacks->fseek || !file_callbacks->fclose || !file_callbacks->ftell ) return -1; + + state.depth = 0; + state.allowed_version = allowed_version; + state.file_callbacks = file_callbacks; + state.load_target = load_target; + state.load_context = load_context; + state.info_target = info_target; + state.info_context = info_context; + + state.base_path = strdup( uri ); + if ( !state.base_path ) return -1; + + file_name = strrpbrk( uri, file_callbacks->path_separators ); + + if ( file_name ) + { + ++file_name; + state.base_path[ file_name - uri ] = '\0'; + } + else + { + state.base_path[ 0 ] = '\0'; + file_name = uri; + } + + rval = psf_load_internal( &state, file_name ); + + free( state.base_path ); + + return rval; +} + +typedef struct psf_tag psf_tag; + +struct psf_tag { + char * name; + char * value; + psf_tag * next, *prev; +}; + +#define FIELDS_SPLIT 6 +static const char * fields_to_split[FIELDS_SPLIT] = {"ARTIST", "ALBUM ARTIST", "PRODUCER", "COMPOSER", "PERFORMER", "GENRE"}; + +static int check_split_value( const char * name ) +{ + unsigned i; + for ( i = 0; i < FIELDS_SPLIT; i++ ) + { + if ( !strcasecmp( name, fields_to_split[ i ] ) ) return 1; + } + return 0; +} + +static psf_tag * find_tag( psf_tag * tags, const char * name ) +{ + if ( tags && name && *name ) + { + while ( tags ) + { + if ( !strcasecmp( tags->name, name ) ) return tags; + tags = tags->next; + } + } + + return NULL; +} + +static void free_tags( psf_tag * tags ) +{ + psf_tag * tag = tags, * next; + while ( tag ) + { + next = tag->next; + if ( tag->name ) free( tag->name ); + if ( tag->value ) free( tag->value ); + free( tag ); + tag = next; + } +} + +static psf_tag * add_tag_multi( psf_tag * tags, const char * name, const char ** values, int values_count ) +{ + psf_tag * footer; + psf_tag * tag; + + int i; + + if ( !name || !*name || !values || !values_count || !*values ) return NULL; + + footer = tags; + + tag = find_tag( tags, name ); + if ( !tag ) + { + tag = calloc(1, sizeof(psf_tag)); + if (!tag) return footer; + tag->name = strdup( name ); + if ( !tag->name ) + { + free( tag ); + return footer; + } + tag->next = tags; + if ( tags ) tags->prev = tag; + footer = tag; + } + if ( tag->value ) + { + size_t old_length = strlen(tag->value); + char * new_value = (char *) realloc( tag->value, old_length + strlen( values[ 0 ] ) + 2 ); + if (!new_value) return footer; + tag->value = new_value; + new_value[ old_length ] = '\n'; + strcpy( new_value + old_length + 1, values[ 0 ] ); + } + else + { + tag->value = strdup( values[ 0 ] ); + if ( !tag->value ) return footer; + } + + for (i = 1; i < values_count; i++) + { + tag = calloc(1, sizeof(psf_tag)); + if ( !tag ) return footer; + tag->name = strdup( name ); + if ( !tag->name ) + { + free( tag ); + return footer; + } + tag->value = strdup( values[ i ] ); + if ( !tag->value ) + { + free( tag->name ); + free( tag ); + return footer; + } + tag->next = footer; + if ( footer ) footer->prev = tag; + footer = tag; + } + + return footer; +} + +static psf_tag * add_tag( psf_tag * tags, const char * name, const char * value ) +{ + int values_count; + const char ** values; + char * value_split; + + if ( !name || !*name || !value || !*value ) return tags; + + if ( check_split_value( name ) ) + { + char * split_point, * remain; + const char ** new_values; + values_count = 0; + values = NULL; + value_split = strdup( value ); + if ( !value_split ) return tags; + remain = value_split; + split_point = strstr( value_split, "; " ); + while ( split_point ) + { + values_count++; + new_values = realloc( values, sizeof(const char*) * ((values_count + 3) & ~3) ); + if ( !new_values ) + { + if ( values ) free( values ); + free( value_split ); + return tags; + } + values = new_values; + *split_point = '\0'; + values[ values_count - 1 ] = remain; + remain = split_point + 2; + split_point = strstr( remain, "; " ); + } + if ( *remain ) + { + values_count++; + new_values = realloc( values, sizeof(char*) * ((values_count + 3) & ~3) ); + if ( !new_values ) + { + if ( values ) free( values ); + free( value_split ); + return tags; + } + values = new_values; + values[ values_count - 1 ] = remain; + } + } + else + { + values_count = 1; + value_split = NULL; + values = (const char **) malloc(sizeof(const char *)); + if ( !values ) return tags; + values[ 0 ] = value; + } + + tags = add_tag_multi( tags, name, values, values_count ); + + if ( value_split ) free( value_split ); + free( values ); + + return tags; +} + +/* Split line on first equals sign, and remove any whitespace surrounding the name and value fields */ + +static psf_tag * process_tag_line( psf_tag * tags, char * line ) +{ + char * name, * value, * end; + char * equals = strchr( line, '=' ); + if ( !equals ) return tags; + + name = line; + value = equals + 1; + end = line + strlen( line ); + + while ( name < equals && *name > 0 && *name <= ' ' ) name++; + if ( name == equals ) return tags; + + --equals; + while ( equals > name && *equals > 0 && *equals <= ' ' ) --equals; + equals[1] = '\0'; + + while ( value < end && *value > 0 && *value <= ' ' ) value++; + if ( value == end ) return tags; + + --end; + while ( end > value && *value > 0 && *value <= ' ' ) --end; + end[1] = '\0'; + + if ( *name == '_' ) + { + psf_tag * tag = find_tag( tags, name ); + if ( tag ) return tags; + } + + return add_tag( tags, name, value ); +} + +static psf_tag * process_tags( char * buffer ) +{ + psf_tag * tags = NULL; + char * line_end; + if ( !buffer || !*buffer ) return NULL; + + line_end = strpbrk( buffer, "\n\r" ); + while ( line_end ) + { + *line_end++ = '\0'; + tags = process_tag_line( tags, buffer ); + while ( *line_end && ( *line_end == '\n' || *line_end == '\r' ) ) line_end++; + buffer = line_end; + line_end = strpbrk( buffer, "\n\r" ); + } + if ( *buffer ) tags = process_tag_line( tags, buffer ); + + return tags; +} + +static int psf_load_internal( psf_load_state * state, const char * file_name ) +{ + psf_tag * tags = NULL; + psf_tag * tag; + + char * full_path; + + void * file; + + long file_size, tag_size; + + int n; + + uint8_t header_buffer[16]; + + uint8_t * exe_compressed_buffer = NULL; + uint8_t * exe_decompressed_buffer = NULL; + uint8_t * reserved_buffer = NULL; + char * tag_buffer = NULL; + + uint32_t exe_compressed_size, exe_crc32, reserved_size; + uLong exe_decompressed_size, try_exe_decompressed_size; + + int zerr; + + if ( ++state->depth > max_recursion_depth ) return -1; + + full_path = (char *) malloc( strlen(state->base_path) + strlen(file_name) + 1 ); + if ( !full_path ) return -1; + + strcpy( full_path, state->base_path ); + strcat( full_path, file_name ); + + file = state->file_callbacks->fopen( full_path ); + + free( full_path ); + + if ( !file ) return -1; + + if ( state->file_callbacks->fread( header_buffer, 1, 16, file ) < 16 ) goto error_close_file; + + if ( memcmp( header_buffer, "PSF", 3 ) ) goto error_close_file; + + if ( state->allowed_version && ( header_buffer[ 3 ] != state->allowed_version ) ) goto error_close_file; + + reserved_size = header_buffer[ 4 ] | ( header_buffer[ 5 ] << 8 ) | ( header_buffer[ 6 ] << 16 ) | ( header_buffer[ 7 ] << 24 ); + exe_compressed_size = header_buffer[ 8 ] | ( header_buffer[ 9 ] << 8 ) | ( header_buffer[ 10 ] << 16 ) | ( header_buffer[ 11 ] << 24 ); + exe_crc32 = header_buffer[ 12 ] | ( header_buffer[ 13 ] << 8 ) | ( header_buffer[ 14 ] << 16 ) | ( header_buffer[ 15 ] << 24 ); + + if ( state->file_callbacks->fseek( file, 0, SEEK_END ) ) goto error_close_file; + + file_size = state->file_callbacks->ftell( file ); + + if ( file_size >= 16 + reserved_size + exe_compressed_size + 5 ) + { + tag_size = file_size - ( 16 + reserved_size + exe_compressed_size ); + if ( state->file_callbacks->fseek( file, -tag_size, SEEK_CUR ) ) goto error_close_file; + tag_buffer = (char *) malloc( tag_size + 1 ); + if ( !tag_buffer ) goto error_close_file; + if ( state->file_callbacks->fread( tag_buffer, 1, tag_size, file ) < (size_t)tag_size ) goto error_free_buffers; + tag_buffer[ tag_size ] = 0; + if ( !memcmp( tag_buffer, "[TAG]", 5 ) ) tags = process_tags( tag_buffer + 5 ); + free( tag_buffer ); + tag_buffer = NULL; + + if ( tags && state->info_target && state->depth == 1 ) + { + tag = tags; + while ( tag->next ) tag = tag->next; + while ( tag ) + { + state->info_target( state->info_context, tag->name, tag->value ); + tag = tag->prev; + } + } + } + + if ( !state->load_target ) goto done; + + tag = find_tag( tags, "_lib" ); + if ( tag ) + { + if ( psf_load_internal( state, tag->value ) < 0 ) goto error_free_tags; + } + + reserved_buffer = (uint8_t *) malloc( reserved_size ); + if ( !reserved_buffer ) goto error_free_tags; + exe_compressed_buffer = (uint8_t *) malloc( exe_compressed_size ); + if ( !exe_compressed_buffer ) goto error_free_tags; + + if ( state->file_callbacks->fseek( file, 16, SEEK_SET ) ) goto error_free_tags; + if ( reserved_size && state->file_callbacks->fread( reserved_buffer, 1, reserved_size, file ) < reserved_size ) goto error_free_tags; + if ( exe_compressed_size && state->file_callbacks->fread( exe_compressed_buffer, 1, exe_compressed_size, file ) < exe_compressed_size ) goto error_free_tags; + state->file_callbacks->fclose( file ); + file = NULL; + + if ( exe_compressed_size ) + { + if ( exe_crc32 != crc32(crc32(0L, Z_NULL, 0), exe_compressed_buffer, exe_compressed_size) ) goto error_free_tags; + + exe_decompressed_size = try_exe_decompressed_size = exe_compressed_size * 3; + exe_decompressed_buffer = (uint8_t *) malloc( exe_decompressed_size ); + if ( !exe_decompressed_buffer ) goto error_free_tags; + + while ( Z_OK != ( zerr = uncompress( exe_decompressed_buffer, &exe_decompressed_size, exe_compressed_buffer, exe_compressed_size ) ) ) + { + void * try_exe_decompressed_buffer; + + if ( Z_MEM_ERROR != zerr && Z_BUF_ERROR != zerr ) goto error_free_tags; + + try_exe_decompressed_size += 1 * 1024 * 1024; + exe_decompressed_size = try_exe_decompressed_size; + + try_exe_decompressed_buffer = realloc( exe_decompressed_buffer, exe_decompressed_size ); + if ( !try_exe_decompressed_buffer ) goto error_free_tags; + + exe_decompressed_buffer = (uint8_t *) try_exe_decompressed_buffer; + } + } + else + { + exe_decompressed_size = 0; + exe_decompressed_buffer = (uint8_t *) malloc( exe_decompressed_size ); + if ( !exe_decompressed_buffer ) goto error_free_tags; + } + + free( exe_compressed_buffer ); + exe_compressed_buffer = NULL; + + if ( state->load_target( state->load_context, exe_decompressed_buffer, exe_decompressed_size, reserved_buffer, reserved_size ) ) goto error_free_tags; + + free( reserved_buffer ); + reserved_buffer = NULL; + + free( exe_decompressed_buffer ); + exe_decompressed_buffer = NULL; + + n = 2; + snprintf( state->lib_name_temp, 31, "_lib%u", n ); + state->lib_name_temp[ 31 ] = '\0'; + tag = find_tag( tags, state->lib_name_temp ); + while ( tag ) + { + if ( psf_load_internal( state, tag->value ) < 0 ) goto error_free_tags; + ++n; + snprintf( state->lib_name_temp, 31, "_lib%u", n ); + state->lib_name_temp[ 31 ] = '\0'; + tag = find_tag( tags, state->lib_name_temp ); + } + +done: + if ( file ) state->file_callbacks->fclose( file ); + + free_tags( tags ); + + --state->depth; + + return header_buffer[ 3 ]; + +error_free_tags: + free_tags( tags ); +error_free_buffers: + if ( exe_compressed_buffer ) free( exe_compressed_buffer ); + if ( exe_decompressed_buffer ) free( exe_decompressed_buffer ); + if ( reserved_buffer ) free( reserved_buffer ); + if ( tag_buffer ) free( tag_buffer ); +error_close_file: + if ( file ) state->file_callbacks->fclose( file ); + return -1; +} diff --git a/Frameworks/psflib/psflib/psflib.h b/Frameworks/psflib/psflib/psflib.h new file mode 100644 index 000000000..308596e32 --- /dev/null +++ b/Frameworks/psflib/psflib/psflib.h @@ -0,0 +1,71 @@ +#ifndef PSFLIB_H +#define PSFLIB_H + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct psf_file_callbacks +{ + /* list of characters which act as path separators, null terminated */ + const char * path_separators; + + /* accepts UTF-8 encoding, returns file handle */ + void * (* fopen )(const char *); + + /* reads to specified buffer, returns count of size bytes read */ + size_t (* fread )(void *, size_t size, size_t count, void * handle); + + /* returns zero on success, -1 on error */ + int (* fseek )(void * handle, int64_t, int); + + /* returns zero on success, -1 on error */ + int (* fclose)(void * handle); + + /* returns current file offset */ + long (* ftell )(void * handle); +} psf_file_callbacks; + +/* Receives exe and reserved bodies, with deepest _lib->_lib->_lib etc head first, followed + * by the specified file itself, then followed by numbered library chains. + * + * Example: + * + * outermost file, a.psf, has _lib=b.psf and _lib2=c.psf tags; b.psf has _lib=d.psf: + * + * the callback will be passed the contents of d.psf, then b.psf, then a.psf, then c.psf + * + * Returning non-zero indicates an error. + */ +typedef int (* psf_load_callback)(void * context, const uint8_t * exe, size_t exe_size, + const uint8_t * reserved, size_t reserved_size); + +/* Receives the name/value pairs from the outermost file, one at a time. + * + * Returning non-zero indicates an error. + */ +typedef int (* psf_info_callback)(void * context, const char * name, const char * value); + +/* Loads the PSF chain starting with uri, opened using file_callbacks, passes the tags, + * if any, to the optional info_target callback, then passes all loaded data to load_target + * with the highest priority file first. + * + * allowed_version may be set to zero to probe the file version, but is not recommended when + * actually loading files into an emulator state. + * + * Both load_target and info_target are optional. + * + * Returns negative on error, PSF version on success. + */ +int psf_load( const char * uri, const psf_file_callbacks * file_callbacks, uint8_t allowed_version, + psf_load_callback load_target, void * load_context, psf_info_callback info_target, void * info_context ); + +#ifdef __cplusplus +} +#endif + +#endif // PSFLIB_H diff --git a/Plugins/AudioOverload/AODecoder.h b/Plugins/AudioOverload/AODecoder.h deleted file mode 100644 index d1f4f2e36..000000000 --- a/Plugins/AudioOverload/AODecoder.h +++ /dev/null @@ -1,24 +0,0 @@ -// -// AODecoder.h -// AudioOverload -// -// Created by Vincent Spader on 2/28/09. -// Copyright 2009 __MyCompanyName__. All rights reserved. -// - -#import -#import "Plugin.h" - -@interface AODecoder : NSObject { - uint8_t *fileBuffer; - uint8_t *sampleBuffer; - int samplesInBuffer; - - int type; - - BOOL closed; - long long totalFrames; - long long framesRead; -} - -@end diff --git a/Plugins/AudioOverload/AODecoder.m b/Plugins/AudioOverload/AODecoder.m deleted file mode 100644 index fe4c7b1db..000000000 --- a/Plugins/AudioOverload/AODecoder.m +++ /dev/null @@ -1,368 +0,0 @@ -// -// AODecoder.m -// AudioOverload -// -// Created by Vincent Spader on 2/28/09. -// Copyright 2009 __MyCompanyName__. All rights reserved. -// - -#import "AODecoder.h" - -#import -#import -#import "GlobalLock.h" - -// WARNING: THIS IS IN NO WAY THREAD SAFE. WE SHOULD PROBABLY TAKE A GLOBAL LOCK AROUND THIS PLUGIN. This may cause all kinds of nastyness, but we'll see. -static GlobalLock *globalLock; - -@implementation AODecoder - -// The AO SDK requires you ask for 1 frame at a time. -#define SAMPLES_PER_FRAME 44100/60 - -static struct -{ - uint32_t sig; - char *name; - int32_t (*start)(uint8_t *, uint32_t); - int32_t (*gen)(int16_t *, uint32_t); - int32_t (*stop)(void); - int32_t (*command)(int32_t, int32_t); - uint32_t rate; - int32_t (*fillinfo)(ao_display_info *); -} types[] = { -{ 0x50534641, "Capcom QSound (.qsf)", qsf_start, qsf_gen, qsf_stop, qsf_command, 60, qsf_fill_info }, -{ 0x50534611, "Sega Saturn (.ssf)", ssf_start, ssf_gen, ssf_stop, ssf_command, 60, ssf_fill_info }, -{ 0x50534601, "Sony PlayStation (.psf)", psf_start, psf_gen, psf_stop, psf_command, 60, psf_fill_info }, -{ 0x53505500, "Sony PlayStation (.spu)", spu_start, spu_gen, spu_stop, spu_command, 60, spu_fill_info }, -{ 0x50534602, "Sony PlayStation 2 (.psf2)", psf2_start, psf2_gen, psf2_stop, psf2_command, 60, psf2_fill_info }, -{ 0x50534612, "Sega Dreamcast (.dsf)", dsf_start, dsf_gen, dsf_stop, dsf_command, 60, dsf_fill_info }, - -{ 0xffffffff, "", NULL, NULL, NULL, NULL, 0, NULL } -}; - -static id currentSource; - -int ao_get_lib(char *fn, uint8 **buf, uint64 *length) -{ - NSString *fileName = [NSString stringWithUTF8String:fn]; - NSString *path = [[[[currentSource url] path] stringByDeletingLastPathComponent] stringByAppendingPathComponent:fileName]; - NSURL *url = [NSURL fileURLWithPath:path]; - - id audioSourceClass = NSClassFromString(@"AudioSource"); - id source = [audioSourceClass audioSourceForURL:url]; - - NSLog(@"Loading auxiliary file %s, at %@", fn, url); - - if (![source open:url]) { - NSLog(@"Error: Could not open file: %@", url); - return AO_FAIL; - } - - if (![source seekable]) { - NSLog(@"Error source not seekable or not a file url"); - return AO_FAIL; - } - - [source seek:0 whence:SEEK_END]; - long size = [source tell]; - [source seek:0 whence:SEEK_SET]; - - uint8_t *filebuf = malloc(size); - if (!filebuf) { - [source close]; - NSLog(@"ERROR: could not allocate %d bytes of memory\n", size); - return AO_FAIL; - } - - long amountRead = 0; - while (amountRead < size) { - int read = [source read:filebuf+amountRead amount:size - amountRead]; - amountRead += read; - } - [source close]; - - *buf = filebuf; - *length = (uint64)size; - - NSLog(@"Aux file successfully loaded!"); - return AO_SUCCESS; -} - - -+ (void)initialize -{ - if ([self class] == [AODecoder class]) { - globalLock = [[GlobalLock alloc] init]; - - ao_set_get_lib_callback(ao_get_lib); - } -} - -- (NSDictionary *)metadata -{ - ao_display_info info; - if ((*types[type].fillinfo)(&info) == AO_SUCCESS) - { - NSMutableDictionary *dict = [NSMutableDictionary dictionary]; - - for (int i = 1 ; i < 9; i++) { - NSString *key = [[NSString alloc] initWithUTF8String:info.title[i]]; - NSString *value = [[NSString alloc] initWithUTF8String:info.info[i]]; - - if (nil == key || nil == value) { - [key release]; - [value release]; - continue; - } - - if ([key hasPrefix:@"Name"]) { - [dict setObject:value forKey:@"title"]; - } - else if ([key hasPrefix:@"Artist"]) { - [dict setObject:value forKey:@"artist"]; - } - else if ([key hasPrefix:@"Game"]) { - [dict setObject:value forKey:@"album"]; - } - else if ([key hasPrefix:@"Year"]) { - [dict setObject:value forKey:@"year"]; - } - - [key release]; - [value release]; - } - - return dict; - } - - return nil; -} - -- (long long)retrieveTotalFrames -{ - long long frames = 0; - - ao_display_info info; - if ((*types[type].fillinfo)(&info) == AO_SUCCESS) - { - for (int i = 1 ; i < 9; i++) { - NSString *key = [[NSString alloc] initWithUTF8String:info.title[i]]; - NSString *value = [[NSString alloc] initWithUTF8String:info.info[i]]; - - if ([key hasPrefix:@"Length"]) { - NSArray *components = [value componentsSeparatedByString:@":"]; - - long totalSeconds = 0; - long multiplier = 1; - for (id component in [components reverseObjectEnumerator]) { - totalSeconds += [component integerValue] * multiplier; - multiplier *=60; - } - - frames = (totalSeconds * 44100); - } - - [key release]; - [value release]; - } - } - - return frames; -} - - -- (BOOL)openUnderLock:(id)source -{ - if (![source seekable] || ![[source url] isFileURL]) { - return NO; - } - - currentSource = [source retain]; - - [source seek:0 whence:SEEK_END]; - long size = [source tell]; - [source seek:0 whence:SEEK_SET]; - - fileBuffer = malloc(size); - if (!fileBuffer) { - return NO; - } - - long amountRead = 0; - while (amountRead < size) { - int read = [source read:fileBuffer+amountRead amount:size - amountRead]; - amountRead += read; - } - - [source close]; - - type = 0; - int filesig = fileBuffer[0]<<24 | fileBuffer[1]<<16 | fileBuffer[2]<<8 | fileBuffer[3]; - while (types[type].sig != 0xffffffff) - { - if (filesig == types[type].sig) - { - break; - } - else - { - type++; - } - } - - // now did we identify it above or just fall through? - if (types[type].sig != 0xffffffff) { - NSLog(@"File identified as %s\n", types[type].name); - } - else - { - NSLog(@"ERROR: File is unknown, signature bytes are %02x %02x %02x %02x\n", fileBuffer[0], fileBuffer[1], fileBuffer[2], fileBuffer[3]); - - return NO; - } - - - if ((*types[type].start)(fileBuffer, size) != AO_SUCCESS) - { - NSLog(@"ERROR: Engine rejected file!\n"); - - return NO; - } - - totalFrames = [self retrieveTotalFrames]; - - sampleBuffer = malloc(SAMPLES_PER_FRAME * 4); // 4 == bytes per sample * channels - samplesInBuffer = 0; - - [self willChangeValueForKey:@"properties"]; - [self didChangeValueForKey:@"properties"]; - - return YES; -} - -- (BOOL)open:(id)source -{ - [globalLock lock]; - - BOOL ret = [self openUnderLock:source]; - if (!ret) { - [self close]; - } - return ret; -} - - -- (int)readAudio:(void *)buf frames:(UInt32)frames -{ - if (totalFrames > 0 && framesRead > totalFrames) { - [self close]; - return 0; - } - - int amountRead = 0; - while (amountRead < frames) { - if (samplesInBuffer == 0) { - // Fill them up! - (*types[type].gen)((int16_t *)sampleBuffer, SAMPLES_PER_FRAME); - samplesInBuffer = SAMPLES_PER_FRAME; - } - - int requestAmount = frames - amountRead; - if (requestAmount > samplesInBuffer) { - requestAmount = samplesInBuffer; - } - - memcpy(((uint8_t *)buf) + amountRead*4, sampleBuffer, requestAmount*4); - memmove(sampleBuffer, sampleBuffer + (requestAmount*4), (samplesInBuffer - requestAmount)*4); - samplesInBuffer -= requestAmount; - - amountRead += requestAmount; - } - - framesRead += frames; - - return frames; -} - -- (void)closeUnderLock -{ - (*types[type ].stop)(); - if (NULL != fileBuffer) { - free(fileBuffer); - fileBuffer = NULL; - - free(sampleBuffer); - sampleBuffer = NULL; - } - - [currentSource release]; - currentSource = nil; -} - -- (void)close -{ - if (!closed) { - closed = YES; - - [self closeUnderLock]; - - [globalLock unlock]; - } -} - -- (long)seek:(long)frame -{ - return frame; -} - -- (NSDictionary *)properties -{ - return [NSDictionary dictionaryWithObjectsAndKeys: - [NSNumber numberWithInt:2], @"channels", - [NSNumber numberWithInt:16], @"bitsPerSample", - [NSNumber numberWithFloat:44100], @"sampleRate", - [NSNumber numberWithInteger:totalFrames], @"totalFrames", - [NSNumber numberWithInt:0], @"bitrate", - [NSNumber numberWithBool:NO], @"seekable", - @"host", @"endian", - nil]; -} - -+ (NSDictionary *)metadataForURL:(NSURL *)url -{ - [globalLock lock]; - id audioSourceClass = NSClassFromString(@"AudioSource"); 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+ buildConfigurations = ( + 8360EEF417F92AC8005208A4 /* Debug */, + 8360EEF517F92AC8005208A4 /* Release */, + ); + defaultConfigurationIsVisible = 0; + defaultConfigurationName = Release; + }; + 8360EEF617F92AC8005208A4 /* Build configuration list for PBXNativeTarget "HighlyComplete" */ = { + isa = XCConfigurationList; + buildConfigurations = ( + 8360EEF717F92AC8005208A4 /* Debug */, + 8360EEF817F92AC8005208A4 /* Release */, + ); + defaultConfigurationIsVisible = 0; + defaultConfigurationName = Release; + }; +/* End XCConfigurationList section */ + }; + rootObject = 8360EEDC17F92AC8005208A4 /* Project object */; +} diff --git a/Plugins/HighlyComplete/HighlyComplete.xcodeproj/xcuserdata/Chris.xcuserdatad/xcschemes/HighlyComplete.xcscheme b/Plugins/HighlyComplete/HighlyComplete.xcodeproj/xcuserdata/Chris.xcuserdatad/xcschemes/HighlyComplete.xcscheme new file mode 100644 index 000000000..d87df9e0a --- /dev/null +++ b/Plugins/HighlyComplete/HighlyComplete.xcodeproj/xcuserdata/Chris.xcuserdatad/xcschemes/HighlyComplete.xcscheme @@ -0,0 +1,59 @@ + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Plugins/HighlyComplete/HighlyComplete.xcodeproj/xcuserdata/Chris.xcuserdatad/xcschemes/xcschememanagement.plist b/Plugins/HighlyComplete/HighlyComplete.xcodeproj/xcuserdata/Chris.xcuserdatad/xcschemes/xcschememanagement.plist new file mode 100644 index 000000000..1960417bc --- /dev/null +++ b/Plugins/HighlyComplete/HighlyComplete.xcodeproj/xcuserdata/Chris.xcuserdatad/xcschemes/xcschememanagement.plist @@ -0,0 +1,22 @@ + + + + + SchemeUserState + + HighlyComplete.xcscheme + + orderHint + 33 + + + SuppressBuildableAutocreation + + 8360EEE317F92AC8005208A4 + + primary + + + + + diff --git a/Plugins/HighlyComplete/HighlyComplete/HCDecoder.h b/Plugins/HighlyComplete/HighlyComplete/HCDecoder.h new file mode 100644 index 000000000..d69019f91 --- /dev/null +++ b/Plugins/HighlyComplete/HighlyComplete/HCDecoder.h @@ -0,0 +1,32 @@ +// +// HCDecoder.h +// HighlyComplete +// +// Created by Christopher Snowhill on 9/30/13. +// Copyright 2013 __NoWork, Inc__. All rights reserved. +// + +#import +#import "Plugin.h" + +@interface HCDecoder : NSObject { + id currentSource; + uint8_t *emulatorCore; + void *emulatorExtra; + + NSDictionary *metadataList; + + int tagLengthMs; + int tagFadeMs; + + int volumeScale; + + int type; + + int sampleRate; + + long totalFrames; + long framesRead; +} + +@end diff --git a/Plugins/HighlyComplete/HighlyComplete/HCDecoder.mm b/Plugins/HighlyComplete/HighlyComplete/HCDecoder.mm new file mode 100644 index 000000000..3a2640e92 --- /dev/null +++ b/Plugins/HighlyComplete/HighlyComplete/HCDecoder.mm @@ -0,0 +1,907 @@ +// +// HCDecoder.m +// HighlyComplete +// +// Created by Christopher Snowhill on 9/30/13. +// Copyright 2013 __NoWork, Inc__. All rights reserved. +// + +#import "HCDecoder.h" + +#import "hebios.h" + +#import +#import + +#import +#import +#import +#import + +#import + +#import + +#import + + +@implementation HCDecoder + ++ (void)initialize +{ + bios_set_image(hebios, HEBIOS_SIZE); + psx_init(); + sega_init(); + qsound_init(); +} + +- (NSDictionary *)metadata +{ + return metadataList; +} + +- (long)retrieveTotalFrames +{ + return (tagLengthMs + tagFadeMs) * (sampleRate / 100) / 10; +} + +void * source_fopen(const char * path) +{ + NSString * urlString = [NSString stringWithUTF8String:path]; + NSURL * url = [NSURL URLWithString:[urlString stringByAddingPercentEscapesUsingEncoding:NSUTF8StringEncoding]]; + + id audioSourceClass = NSClassFromString(@"AudioSource"); + id source = [audioSourceClass audioSourceForURL:url]; + + if (![source open:url]) + return 0; + + if (![source seekable]) + return 0; + + return [source retain]; +} + +size_t source_fread(void * buffer, size_t size, size_t count, void * handle) +{ + id source = (id)handle; + + return [source read:buffer amount:(size * count)] / size; +} + +int source_fseek(void * handle, int64_t offset, int whence) +{ + id source = (id)handle; + + return [source seek:(long)offset whence:whence] ? 0 : -1; +} + +int source_fclose(void * handle) +{ + id source = (id)handle; + + [source release]; + + return 0; +} + +long source_ftell(void * handle) +{ + id source = (id)handle; + + return [source tell]; +} + +static psf_file_callbacks source_callbacks = +{ + "/|\\", + source_fopen, + source_fread, + source_fseek, + source_fclose, + source_ftell +}; + +struct psf_info_meta_state +{ + NSMutableDictionary * info; + + bool utf8; + + int tag_length_ms; + int tag_fade_ms; + + int volume_scale; +}; + +static int parse_time_crap(NSString * value) +{ + NSArray *components = [value componentsSeparatedByString:@":"]; + + float totalSeconds = 0; + float multiplier = 1000; + bool first = YES; + for (id component in [components reverseObjectEnumerator]) { + if (first) { + first = NO; + totalSeconds += [component floatValue] * multiplier; + } else { + totalSeconds += [component integerValue] * multiplier; + } + multiplier *= 60; + } + + return totalSeconds; +} + +static int db_to_int(NSString * value) +{ + return pow(10.0, [value floatValue] / 20) * 4096; +} + +static int scale_to_int(NSString * value) +{ + return [value floatValue] * 4096; +} + +static int psf_info_meta(void * context, const char * name, const char * value) +{ + struct psf_info_meta_state * state = ( struct psf_info_meta_state * ) context; + + NSString * tag = [NSString stringWithUTF8String:name]; + NSString * taglc = [tag lowercaseString]; + NSString * svalue = [NSString stringWithUTF8String:value]; + + if ([taglc isEqualToString:@"game"]) + { + taglc = @"album"; + } + else if ([taglc isEqualToString:@"date"]) + { + taglc = @"year"; + } + + if ([taglc hasPrefix:@"replaygain_"]) + { + if ([taglc isEqualToString:@"replaygain_album_gain"]) + { + state->volume_scale = db_to_int(svalue); + } + else if (!state->volume_scale && [taglc isEqualToString:@"replaygain_track_gain"]) + { + state->volume_scale = db_to_int(svalue); + } + } + else if ([taglc isEqualToString:@"volume"]) + { + if (!state->volume_scale) + state->volume_scale = scale_to_int(svalue); + } + else if ([taglc isEqualToString:@"length"]) + { + state->tag_length_ms = parse_time_crap(svalue); + } + else if ([taglc isEqualToString:@"fade"]) + { + state->tag_fade_ms = parse_time_crap(svalue); + } + else if ([taglc isEqualToString:@"utf8"]) + { + state->utf8 = true; + } + else if ([taglc hasPrefix:@"_lib"]) + { + } + else if ([taglc isEqualToString:@"_refresh"]) + { + } + else if ([taglc hasPrefix:@"_"]) + { + return -1; + } + else if ([taglc isEqualToString:@"title"] || + [taglc isEqualToString:@"artist"] || + [taglc isEqualToString:@"album"] || + [taglc isEqualToString:@"year"] || + [taglc isEqualToString:@"genre"] || + [taglc isEqualToString:@"track"]) + { + [state->info setObject:svalue forKey:taglc]; + } + + return 0; +} + +struct psf1_load_state +{ + void * emu; + bool first; + unsigned refresh; +}; + +typedef struct { + uint32_t pc0; + uint32_t gp0; + uint32_t t_addr; + uint32_t t_size; + uint32_t d_addr; + uint32_t d_size; + uint32_t b_addr; + uint32_t b_size; + uint32_t s_ptr; + uint32_t s_size; + uint32_t sp,fp,gp,ret,base; +} exec_header_t; + +typedef struct { + char key[8]; + uint32_t text; + uint32_t data; + exec_header_t exec; + char title[60]; +} psxexe_hdr_t; + +static int psf1_info(void * context, const char * name, const char * value) +{ + struct psf1_load_state * state = ( struct psf1_load_state * ) context; + + NSString * sname = [[NSString stringWithUTF8String:name] lowercaseString]; + NSString * svalue = [NSString stringWithUTF8String:value]; + + if ( !state->refresh && [sname isEqualToString:@"_refresh"] ) + { + state->refresh = [svalue integerValue]; + } + + return 0; +} + +unsigned get_be16( void const* p ) +{ + return (unsigned) ((unsigned char const*) p) [0] << 8 | + (unsigned) ((unsigned char const*) p) [1]; +} + +unsigned get_le32( void const* p ) +{ + return (unsigned) ((unsigned char const*) p) [3] << 24 | + (unsigned) ((unsigned char const*) p) [2] << 16 | + (unsigned) ((unsigned char const*) p) [1] << 8 | + (unsigned) ((unsigned char const*) p) [0]; +} + +unsigned get_be32( void const* p ) +{ + return (unsigned) ((unsigned char const*) p) [0] << 24 | + (unsigned) ((unsigned char const*) p) [1] << 16 | + (unsigned) ((unsigned char const*) p) [2] << 8 | + (unsigned) ((unsigned char const*) p) [3]; +} + +void set_le32( void* p, unsigned n ) +{ + ((unsigned char*) p) [0] = (unsigned char) n; + ((unsigned char*) p) [1] = (unsigned char) (n >> 8); + ((unsigned char*) p) [2] = (unsigned char) (n >> 16); + ((unsigned char*) p) [3] = (unsigned char) (n >> 24); +} + +int psf1_loader(void * context, const uint8_t * exe, size_t exe_size, + const uint8_t * reserved, size_t reserved_size) +{ + struct psf1_load_state * state = ( struct psf1_load_state * ) context; + + psxexe_hdr_t *psx = (psxexe_hdr_t *) exe; + + if ( exe_size < 0x800 ) return -1; + + uint32_t addr = get_le32( &psx->exec.t_addr ); + uint32_t size = exe_size - 0x800; + + addr &= 0x1fffff; + if ( ( addr < 0x10000 ) || ( size > 0x1f0000 ) || ( addr + size > 0x200000 ) ) return -1; + + void * pIOP = psx_get_iop_state( state->emu ); + iop_upload_to_ram( pIOP, addr, exe + 0x800, size ); + + if ( !state->refresh ) + { + if (!strncasecmp((const char *) exe + 113, "Japan", 5)) state->refresh = 60; + else if (!strncasecmp((const char *) exe + 113, "Europe", 6)) state->refresh = 50; + else if (!strncasecmp((const char *) exe + 113, "North America", 13)) state->refresh = 60; + } + + if ( state->first ) + { + void * pR3000 = iop_get_r3000_state( pIOP ); + r3000_setreg(pR3000, R3000_REG_PC, get_le32( &psx->exec.pc0 ) ); + r3000_setreg(pR3000, R3000_REG_GEN+29, get_le32( &psx->exec.s_ptr ) ); + state->first = false; + } + + return 0; +} + +static int EMU_CALL virtual_readfile(void *context, const char *path, int offset, char *buffer, int length) +{ + return psf2fs_virtual_readfile(context, path, offset, buffer, length); +} + +struct sdsf_loader_state +{ + uint8_t * data; + size_t data_size; +}; + +int sdsf_loader(void * context, const uint8_t * exe, size_t exe_size, + const uint8_t * reserved, size_t reserved_size) +{ + if ( exe_size < 4 ) return -1; + + struct sdsf_loader_state * state = ( struct sdsf_loader_state * ) context; + + uint8_t * dst = state->data; + + if ( state->data_size < 4 ) { + state->data = dst = ( uint8_t * ) malloc( exe_size ); + state->data_size = exe_size; + memcpy( dst, exe, exe_size ); + return 0; + } + + uint32_t dst_start = get_le32( dst ); + uint32_t src_start = get_le32( exe ); + dst_start &= 0x7fffff; + src_start &= 0x7fffff; + uint32_t dst_len = state->data_size - 4; + uint32_t src_len = exe_size - 4; + if ( dst_len > 0x800000 ) dst_len = 0x800000; + if ( src_len > 0x800000 ) src_len = 0x800000; + + if ( src_start < dst_start ) + { + uint32_t diff = dst_start - src_start; + state->data_size = dst_len + 4 + diff; + state->data = dst = ( uint8_t * ) realloc( dst, state->data_size ); + memmove( dst + 4 + diff, dst + 4, dst_len ); + memset( dst + 4, 0, diff ); + dst_len += diff; + dst_start = src_start; + set_le32( dst, dst_start ); + } + if ( ( src_start + src_len ) > ( dst_start + dst_len ) ) + { + uint32_t diff = ( src_start + src_len ) - ( dst_start + dst_len ); + state->data_size = dst_len + 4 + diff; + state->data = dst = ( uint8_t * ) realloc( dst, state->data_size ); + memset( dst + 4 + dst_len, 0, diff ); + } + + memcpy( dst + 4 + ( src_start - dst_start ), exe + 4, src_len ); + + return 0; +} + +struct qsf_loader_state +{ + uint8_t * key; + uint32_t key_size; + + uint8_t * z80_rom; + uint32_t z80_size; + + uint8_t * sample_rom; + uint32_t sample_size; +}; + +static int upload_section( struct qsf_loader_state * state, const char * section, uint32_t start, + const uint8_t * data, uint32_t size ) +{ + uint8_t ** array = NULL; + uint32_t * array_size = NULL; + uint32_t max_size = 0x7fffffff; + + if ( !strcmp( section, "KEY" ) ) { array = &state->key; array_size = &state->key_size; max_size = 11; } + else if ( !strcmp( section, "Z80" ) ) { array = &state->z80_rom; array_size = &state->z80_size; } + else if ( !strcmp( section, "SMP" ) ) { array = &state->sample_rom; array_size = &state->sample_size; } + else return -1; + + if ( ( start + size ) < start ) return -1; + + uint32_t new_size = start + size; + uint32_t old_size = *array_size; + if ( new_size > max_size ) return -1; + + if ( new_size > old_size ) { + *array = ( uint8_t * ) realloc( *array, new_size ); + *array_size = new_size; + memset( (*array) + old_size, 0, new_size - old_size ); + } + + memcpy( (*array) + start, data, size ); + + return 0; +} + +static int qsf_loader(void * context, const uint8_t * exe, size_t exe_size, + const uint8_t * reserved, size_t reserved_size) +{ + struct qsf_loader_state * state = ( struct qsf_loader_state * ) context; + + for (;;) { + char s[4]; + if ( exe_size < 11 ) break; + memcpy( s, exe, 3 ); exe += 3; exe_size -= 3; + s [3] = 0; + uint32_t dataofs = get_le32( exe ); exe += 4; exe_size -= 4; + uint32_t datasize = get_le32( exe ); exe += 4; exe_size -= 4; + if ( datasize > exe_size ) + return -1; + + if ( upload_section( state, s, dataofs, exe, datasize ) < 0 ) + return -1; + + exe += datasize; + exe_size -= datasize; + } + + return 0; +} + +struct gsf_loader_state +{ + int entry_set; + uint32_t entry; + uint8_t * data; + size_t data_size; +}; + +int gsf_loader(void * context, const uint8_t * exe, size_t exe_size, + const uint8_t * reserved, size_t reserved_size) +{ + if ( exe_size < 12 ) return -1; + + struct gsf_loader_state * state = ( struct gsf_loader_state * ) context; + + unsigned char *iptr; + unsigned isize; + unsigned char *xptr; + unsigned xentry = get_le32(exe + 0); + unsigned xsize = get_le32(exe + 8); + unsigned xofs = get_le32(exe + 4) & 0x1ffffff; + if ( xsize < exe_size - 12 ) return -1; + if (!state->entry_set) + { + state->entry = xentry; + state->entry_set = 1; + } + { + iptr = state->data; + isize = state->data_size; + state->data = 0; + state->data_size = 0; + } + if (!iptr) + { + unsigned rsize = xofs + xsize; + { + rsize -= 1; + rsize |= rsize >> 1; + rsize |= rsize >> 2; + rsize |= rsize >> 4; + rsize |= rsize >> 8; + rsize |= rsize >> 16; + rsize += 1; + } + iptr = (unsigned char *) malloc(rsize + 10); + if (!iptr) + return -1; + memset(iptr, 0, rsize + 10); + isize = rsize; + } + else if (isize < xofs + xsize) + { + unsigned rsize = xofs + xsize; + { + rsize -= 1; + rsize |= rsize >> 1; + rsize |= rsize >> 2; + rsize |= rsize >> 4; + rsize |= rsize >> 8; + rsize |= rsize >> 16; + rsize += 1; + } + xptr = (unsigned char *) realloc(iptr, xofs + rsize + 10); + if (!xptr) + { + free(iptr); + return -1; + } + iptr = xptr; + isize = rsize; + } + memcpy(iptr + xofs, exe + 12, xsize); + { + state->data = iptr; + state->data_size = isize; + } + return 0; +} + +struct gsf_sound_out : public GBASoundOut +{ + uint8_t * buffer; + size_t samples_written; + size_t buffer_size; + gsf_sound_out() : buffer( nil ), samples_written( 0 ), buffer_size( 0 ) { } + virtual ~gsf_sound_out() { if ( buffer ) free( buffer ); } + // Receives signed 16-bit stereo audio and a byte count + virtual void write(const void * samples, unsigned bytes) + { + if ( bytes + samples_written > buffer_size ) + { + size_t new_buffer_size = ( buffer_size + bytes + 2047 ) & ~2047; + buffer = ( uint8_t * ) realloc( buffer, new_buffer_size ); + buffer_size = new_buffer_size; + } + memcpy( buffer + samples_written, samples, bytes ); + samples_written += bytes; + } +}; + +- (BOOL)open:(id)source +{ + if (![source seekable]) { + return NO; + } + + currentSource = [source retain]; + + struct psf_info_meta_state info; + + info.info = [NSMutableDictionary dictionary]; + info.utf8 = false; + info.tag_length_ms = 0; + info.tag_fade_ms = 0; + info.volume_scale = 0; + + NSString * decodedUrl = [[[source url] absoluteString] stringByReplacingPercentEscapesUsingEncoding:NSUTF8StringEncoding]; + + type = psf_load( [decodedUrl UTF8String], &source_callbacks, 0, 0, 0, psf_info_meta, &info ); + + if (type <= 0) + return NO; + + emulatorCore = nil; + emulatorExtra = nil; + + sampleRate = 44100; + + if ( type == 1 ) + { + emulatorCore = ( uint8_t * ) malloc( psx_get_state_size( 1 ) ); + + psx_clear_state( emulatorCore, 1 ); + + struct psf1_load_state state; + + state.emu = emulatorCore; + state.first = true; + state.refresh = 0; + + if ( psf_load( [decodedUrl UTF8String], &source_callbacks, 1, psf1_loader, &state, psf1_info, &state ) <= 0 ) + return NO; + + if ( state.refresh ) + psx_set_refresh( emulatorCore, state.refresh ); + } + else if ( type == 2 ) + { + emulatorExtra = psf2fs_create(); + + struct psf1_load_state state; + + state.refresh = 0; + + if ( psf_load( [decodedUrl UTF8String], &source_callbacks, 2, psf2fs_load_callback, emulatorExtra, psf1_info, &state ) <= 0 ) + return NO; + + emulatorCore = ( uint8_t * ) malloc( psx_get_state_size( 2 ) ); + + psx_clear_state( emulatorCore, 2 ); + + if ( state.refresh ) + psx_set_refresh( emulatorCore, state.refresh ); + + psx_set_readfile( emulatorCore, virtual_readfile, emulatorExtra ); + + sampleRate = 48000; + } + else if ( type == 0x11 || type == 0x12 ) + { + struct sdsf_loader_state state; + memset( &state, 0, sizeof(state) ); + + if ( psf_load( [decodedUrl UTF8String], &source_callbacks, type, sdsf_loader, &state, 0, 0) <= 0 ) + return NO; + + emulatorCore = ( uint8_t * ) malloc( sega_get_state_size( type - 0x10 ) ); + + sega_clear_state( emulatorCore, type - 0x10 ); + + sega_enable_dry( emulatorCore, 1 ); + sega_enable_dsp( emulatorCore, 1 ); + + sega_enable_dsp_dynarec( emulatorCore, 0 ); + + uint32_t start = *(uint32_t*) state.data; + uint32_t length = state.data_size; + const uint32_t max_length = ( type == 0x12 ) ? 0x800000 : 0x80000; + if ( ( start + ( length - 4 ) ) > max_length ) { + length = max_length - start + 4; + } + sega_upload_program( emulatorCore, state.data, length ); + + free( state.data ); + } + else if ( type == 0x22 ) + { + struct gsf_loader_state state; + memset( &state, 0, sizeof(state) ); + + if ( psf_load( [decodedUrl UTF8String], &source_callbacks, 0x22, gsf_loader, &state, 0, 0 ) <= 0 ) + return NO; + + GBASystem * system = new GBASystem; + + emulatorCore = ( uint8_t * ) system; + + system->cpuIsMultiBoot = ((state.entry >> 24) == 2); + + CPULoadRom( system, state.data, state.data_size ); + + free( state.data ); + + struct gsf_sound_out * sound_out = new gsf_sound_out; + + emulatorExtra = sound_out; + + soundInit( system, sound_out ); + soundReset( system ); + + CPUInit( system ); + CPUReset( system ); + } + else if ( type == 0x41 ) + { + struct qsf_loader_state * state = ( struct qsf_loader_state * ) calloc( 1, sizeof( *state ) ); + + emulatorExtra = state; + + if ( psf_load( [decodedUrl UTF8String], &source_callbacks, 0x41, qsf_loader, state, 0, 0) <= 0 ) + return NO; + + emulatorCore = ( uint8_t * ) malloc( qsound_get_state_size() ); + + qsound_clear_state( emulatorCore ); + + if(state->key_size == 11) { + uint8_t * ptr = state->key; + uint32_t swap_key1 = get_be32( ptr + 0 ); + uint32_t swap_key2 = get_be32( ptr + 4 ); + uint32_t addr_key = get_be16( ptr + 8 ); + uint8_t xor_key = *( ptr + 10 ); + qsound_set_kabuki_key( emulatorCore, swap_key1, swap_key2, addr_key, xor_key ); + } else { + qsound_set_kabuki_key( emulatorCore, 0, 0, 0, 0 ); + } + qsound_set_z80_rom( emulatorCore, state->z80_rom, state->z80_size ); + qsound_set_sample_rom( emulatorCore, state->sample_rom, state->sample_size ); + } + else return NO; + + tagLengthMs = info.tag_length_ms; + tagFadeMs = info.tag_fade_ms; + volumeScale = info.volume_scale; + + metadataList = info.info; + + framesRead = 0; + totalFrames = [self retrieveTotalFrames]; + + [self willChangeValueForKey:@"properties"]; + [self didChangeValueForKey:@"properties"]; + + return YES; +} + + +- (int)readAudio:(void *)buf frames:(UInt32)frames +{ + if ( type == 1 || type == 2 ) + { + uint32_t howmany = frames; + psx_execute( emulatorCore, 0x7fffffff, ( int16_t * ) buf, &howmany, 0 ); + frames = howmany; + } + else if ( type == 0x11 || type == 0x12 ) + { + uint32_t howmany = frames; + sega_execute( emulatorCore, 0x7fffffff, ( int16_t * ) buf, &howmany ); + frames = howmany; + } + else if ( type == 0x22 ) + { + GBASystem * system = ( GBASystem * ) emulatorCore; + struct gsf_sound_out * sound_out = ( struct gsf_sound_out * ) emulatorExtra; + + CPULoop( system, 250000 ); + + UInt32 frames_rendered = sound_out->samples_written / 4; + + if ( frames_rendered >= frames ) + { + memcpy( buf, sound_out->buffer, frames * 4 ); + frames_rendered -= frames; + memcpy( sound_out->buffer, sound_out->buffer + frames * 4, frames_rendered * 4 ); + } + else + { + memcpy( buf, sound_out->buffer, frames_rendered * 4 ); + frames = frames_rendered; + frames_rendered = 0; + } + sound_out->samples_written = frames_rendered; + } + else if ( type == 0x41 ) + { + uint32_t howmany = frames; + qsound_execute( emulatorCore, 0x7fffffff, ( int16_t * ) buf, &howmany); + frames = howmany; + } + + if ( volumeScale ) + { + int16_t * samples = ( int16_t * ) buf; + + for ( UInt32 i = 0, j = frames * 2; i < j; ++i ) + { + int sample = ( samples[ i ] * volumeScale ) >> 12; + if ( (uint32_t)(sample + 0x8000) & 0xffff0000 ) sample = ( sample >> 31 ) ^ 0x7fff; + samples[ i ] = ( int16_t ) sample; + } + } + + framesRead += frames; + + return frames; +} + +- (void)close +{ + if ( emulatorCore ) { + if ( type == 0x22 ) { + GBASystem * system = ( GBASystem * ) emulatorCore; + CPUCleanUp( system ); + soundShutdown( system ); + delete system; + } else { + free( emulatorCore ); + } + emulatorCore = nil; + } + + if ( type == 2 && emulatorExtra ) { + psf2fs_delete( emulatorExtra ); + emulatorExtra = nil; + } else if ( type == 0x22 && emulatorExtra ) { + delete ( gsf_sound_out * ) emulatorExtra; + emulatorExtra = nil; + } else if ( type == 0x41 && emulatorExtra ) { + struct qsf_loader_state * state = ( struct qsf_loader_state * ) emulatorExtra; + free( state->key ); + free( state->z80_rom ); + free( state->sample_rom ); + free( state ); + emulatorExtra = nil; + } +} + +- (long)seek:(long)frame +{ + if (frame < framesRead) { + [self close]; + [self open:currentSource]; + } + + if ( type == 1 || type == 2 ) + { + uint32_t howmany = (uint32_t)(frame - framesRead); + psx_execute( emulatorCore, 0x7fffffff, 0, &howmany, 0 ); + frame = (long)(howmany + framesRead); + } + else if ( type == 0x11 || type == 0x12 ) + { + uint32_t howmany = (uint32_t)(frame - framesRead); + sega_execute( emulatorCore, 0x7fffffff, 0, &howmany ); + frame = (long)(howmany + framesRead); + } + else if ( type == 0x22 ) + { + GBASystem * system = ( GBASystem * ) emulatorCore; + struct gsf_sound_out * sound_out = ( struct gsf_sound_out * ) emulatorExtra; + + long frames_to_run = frame - framesRead; + + do + { + if ( frames_to_run * 4 >= sound_out->samples_written ) + { + frames_to_run -= sound_out->samples_written / 4; + sound_out->samples_written = 0; + } + else + { + sound_out->samples_written -= frames_to_run * 4; + memcpy( sound_out->buffer, sound_out->buffer + frames_to_run * 4, sound_out->samples_written ); + frames_to_run = 0; + } + + if ( frames_to_run ) + CPULoop( system, 250000 ); + } while ( frames_to_run ); + } + else if ( type == 0x41 ) + { + uint32_t howmany = (uint32_t)(frame - framesRead); + qsound_execute( emulatorCore, 0x7fffffff, 0, &howmany ); + frame = (long)(howmany + framesRead); + } + + return frame; +} + +- (NSDictionary *)properties +{ + return [NSDictionary dictionaryWithObjectsAndKeys: + [NSNumber numberWithInt:2], @"channels", + [NSNumber numberWithInt:16], @"bitsPerSample", + [NSNumber numberWithFloat:sampleRate], @"sampleRate", + [NSNumber numberWithInteger:totalFrames], @"totalFrames", + [NSNumber numberWithInt:0], @"bitrate", + [NSNumber numberWithBool:YES], @"seekable", + @"host", @"endian", + nil]; +} + ++ (NSDictionary *)metadataForURL:(NSURL *)url +{ + struct psf_info_meta_state info; + + info.info = [NSMutableDictionary dictionary]; + info.utf8 = false; + info.tag_length_ms = 0; + info.tag_fade_ms = 0; + info.volume_scale = 0; + + NSString * decodedUrl = [[url absoluteString] stringByReplacingPercentEscapesUsingEncoding:NSUTF8StringEncoding]; + + if ( psf_load( [decodedUrl UTF8String], &source_callbacks, 0, 0, 0, psf_info_meta, &info ) <= 0) + return NO; + + return info.info; +} + ++ (NSArray *)fileTypes +{ + return [NSArray arrayWithObjects:@"psf",@"minipsf",@"psf2", @"minipsf2", @"ssf", @"minissf", @"dsf", @"minidsf", @"qsf", @"miniqsf", @"gsf", @"minigsf", nil]; +} + ++ (NSArray *)mimeTypes +{ + return [NSArray arrayWithObjects:@"audio/x-psf", nil]; +} + + + +@end diff --git a/Plugins/AudioOverload/Info.plist b/Plugins/HighlyComplete/HighlyComplete/HighlyComplete-Info.plist similarity index 75% rename from Plugins/AudioOverload/Info.plist rename to Plugins/HighlyComplete/HighlyComplete/HighlyComplete-Info.plist index 9399ace6b..9d8051c76 100644 --- a/Plugins/AudioOverload/Info.plist +++ b/Plugins/HighlyComplete/HighlyComplete/HighlyComplete-Info.plist @@ -6,20 +6,24 @@ English CFBundleExecutable ${EXECUTABLE_NAME} - CFBundleName - ${PRODUCT_NAME} CFBundleIconFile CFBundleIdentifier - com.yourcompany.${PRODUCT_NAME:identifier} + NoWork-Inc.${PRODUCT_NAME:rfc1034identifier} CFBundleInfoDictionaryVersion 6.0 + CFBundleName + ${PRODUCT_NAME} CFBundlePackageType BNDL + CFBundleShortVersionString + 1.0 CFBundleSignature ???? CFBundleVersion - 1.0 + 1 + NSHumanReadableCopyright + Copyright © 2013 Christopher Snowhill. All rights reserved. NSPrincipalClass diff --git a/Plugins/HighlyComplete/HighlyComplete/HighlyComplete-Prefix.pch b/Plugins/HighlyComplete/HighlyComplete/HighlyComplete-Prefix.pch new file mode 100644 index 000000000..35d76409f --- /dev/null +++ b/Plugins/HighlyComplete/HighlyComplete/HighlyComplete-Prefix.pch @@ -0,0 +1,9 @@ +// +// Prefix header +// +// The contents of this file are implicitly included at the beginning of every source file. +// + +#ifdef __OBJC__ + #import +#endif diff --git a/Plugins/HighlyComplete/HighlyComplete/en.lproj/InfoPlist.strings b/Plugins/HighlyComplete/HighlyComplete/en.lproj/InfoPlist.strings new file mode 100644 index 000000000..477b28ff8 --- /dev/null +++ b/Plugins/HighlyComplete/HighlyComplete/en.lproj/InfoPlist.strings @@ -0,0 +1,2 @@ +/* Localized versions of Info.plist keys */ + diff --git a/Plugins/HighlyComplete/HighlyComplete/hebios.bin b/Plugins/HighlyComplete/HighlyComplete/hebios.bin new file mode 100644 index 000000000..3aaa05582 Binary files /dev/null and b/Plugins/HighlyComplete/HighlyComplete/hebios.bin differ diff --git a/Plugins/HighlyComplete/HighlyComplete/hebios.h b/Plugins/HighlyComplete/HighlyComplete/hebios.h new file mode 100644 index 000000000..0ed962252 --- /dev/null +++ b/Plugins/HighlyComplete/HighlyComplete/hebios.h @@ -0,0 +1,43701 @@ +#ifndef __HEBIOS_H +#define __HEBIOS_H + +#define HEBIOS_SIZE 524288 + +static uint8_t hebios[524288] = +{ + 0x00, 0x78, 0x1A, 0x40, 0x00, 0x00, 0x00, 0x00, 0x59, 0x00, 0x41, 0x2B, + 0x05, 0x00, 0x20, 0x14, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xBF, 0x1A, 0x3C, + 0x00, 0x08, 0x5A, 0x37, 0x08, 0x00, 0x40, 0x03, 0x00, 0x00, 0x00, 0x00, + 0xC0, 0xBF, 0x1A, 0x3C, 0x00, 0x20, 0x5A, 0x37, 0x08, 0x00, 0x40, 0x03, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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e35663f63..000000000 --- a/ThirdParty/Frameworks/Growl.framework/Versions/A/Headers/GrowlApplicationBridge-Carbon.h +++ /dev/null @@ -1,780 +0,0 @@ -// -// GrowlApplicationBridge-Carbon.h -// Growl -// -// Created by Mac-arena the Bored Zo on Wed Jun 18 2004. -// Based on GrowlApplicationBridge.h by Evan Schoenberg. -// This source code is in the public domain. You may freely link it into any -// program. -// - -#ifndef _GROWLAPPLICATIONBRIDGE_CARBON_H_ -#define _GROWLAPPLICATIONBRIDGE_CARBON_H_ - -#include -#include - -#ifndef GROWL_EXPORT -#define GROWL_EXPORT __attribute__((visibility("default"))) -#endif - -/*! @header GrowlApplicationBridge-Carbon.h - * @abstract Declares an API that Carbon applications can use to interact with Growl. - * @discussion GrowlApplicationBridge uses a delegate to provide information //XXX - * to Growl (such as your application's name and what notifications it may - * post) and to provide information to your application (such as that Growl - * is listening for notifications or that a notification has been clicked). - * - * You can set the Growldelegate with Growl_SetDelegate and find out the - * current delegate with Growl_GetDelegate. See struct Growl_Delegate for more - * information about the delegate. - */ - -__BEGIN_DECLS - -/*! @struct Growl_Delegate - * @abstract Delegate to supply GrowlApplicationBridge with information and respond to events. - * @discussion The Growl delegate provides your interface to - * GrowlApplicationBridge. When GrowlApplicationBridge needs information about - * your application, it looks for it in the delegate; when Growl or the user - * does something that you might be interested in, GrowlApplicationBridge - * looks for a callback in the delegate and calls it if present - * (meaning, if it is not NULL). - * XXX on all of that - * @field size The size of the delegate structure. - * @field applicationName The name of your application. - * @field registrationDictionary A dictionary describing your application and the notifications it can send out. - * @field applicationIconData Your application's icon. - * @field growlInstallationWindowTitle The title of the installation window. - * @field growlInstallationInformation Text to display in the installation window. - * @field growlUpdateWindowTitle The title of the update window. - * @field growlUpdateInformation Text to display in the update window. - * @field referenceCount A count of owners of the delegate. - * @field retain Called when GrowlApplicationBridge receives this delegate. - * @field release Called when GrowlApplicationBridge no longer needs this delegate. - * @field growlIsReady Called when GrowlHelperApp is listening for notifications. - * @field growlNotificationWasClicked Called when a Growl notification is clicked. - * @field growlNotificationTimedOut Called when a Growl notification timed out. - */ -struct Growl_Delegate { - /* @discussion This should be sizeof(struct Growl_Delegate). - */ - size_t size; - - /*All of these attributes are optional. - *Optional attributes can be NULL; required attributes that - * are NULL cause setting the Growl delegate to fail. - *XXX - move optional/required status into the discussion for each field - */ - - /* This name is used both internally and in the Growl preferences. - * - * This should remain stable between different versions and incarnations of - * your application. - * For example, "SurfWriter" is a good app name, whereas "SurfWriter 2.0" and - * "SurfWriter Lite" are not. - * - * This can be NULL if it is provided elsewhere, namely in an - * auto-discoverable plist file in your app bundle - * (XXX refer to more information on that) or in registrationDictionary. - */ - CFStringRef applicationName; - - /* - * Must contain at least these keys: - * GROWL_NOTIFICATIONS_ALL (CFArray): - * Contains the names of all notifications your application may post. - * - * Can also contain these keys: - * GROWL_NOTIFICATIONS_DEFAULT (CFArray): - * Names of notifications that should be enabled by default. - * If omitted, GROWL_NOTIFICATIONS_ALL will be used. - * GROWL_APP_NAME (CFString): - * Same as the applicationName member of this structure. - * If both are present, the applicationName member shall prevail. - * If this key is present, you may omit applicationName (set it to NULL). - * GROWL_APP_ICON (CFData): - * Same as the iconData member of this structure. - * If both are present, the iconData member shall prevail. - * If this key is present, you may omit iconData (set it to NULL). - * - * If you change the contents of this dictionary after setting the delegate, - * be sure to call Growl_Reregister. - * - * This can be NULL if you have an auto-discoverable plist file in your app - * bundle. (XXX refer to more information on that) - */ - CFDictionaryRef registrationDictionary; - - /* The data can be in any format supported by NSImage. As of - * Mac OS X 10.3, this includes the .icns, TIFF, JPEG, GIF, PNG, PDF, and - * PICT formats. - * - * If this is not supplied, Growl will look up your application's icon by - * its application name. - */ - CFDataRef applicationIconData; - - /* Installer display attributes - * - * These four attributes are used by the Growl installer, if this framework - * supports it. - * For any of these being NULL, a localised default will be - * supplied. - */ - - /* If this is NULL, Growl will use a default, - * localized title. - * - * Only used if you're using Growl-WithInstaller.framework. Otherwise, - * this member is ignored. - */ - CFStringRef growlInstallationWindowTitle; - /* This information may be as long or short as desired (the - * window will be sized to fit it). If Growl is not installed, it will - * be displayed to the user as an explanation of what Growl is and what - * it can do in your application. - * It should probably note that no download is required to install. - * - * If this is NULL, Growl will use a default, localized - * explanation. - * - * Only used if you're using Growl-WithInstaller.framework. Otherwise, - * this member is ignored. - */ - CFStringRef growlInstallationInformation; - /* If this is NULL, Growl will use a default, - * localized title. - * - * Only used if you're using Growl-WithInstaller.framework. Otherwise, - * this member is ignored. - */ - CFStringRef growlUpdateWindowTitle; - /* This information may be as long or short as desired (the - * window will be sized to fit it). If an older version of Growl is - * installed, it will be displayed to the user as an explanation that an - * updated version of Growl is included in your application and - * no download is required. - * - * If this is NULL, Growl will use a default, localized - * explanation. - * - * Only used if you're using Growl-WithInstaller.framework. Otherwise, - * this member is ignored. - */ - CFStringRef growlUpdateInformation; - - /* This member is provided for use by your retain and release - * callbacks (see below). - * - * GrowlApplicationBridge never directly uses this member. Instead, it - * calls your retain callback (if non-NULL) and your release - * callback (if non-NULL). - */ - unsigned referenceCount; - - //Functions. Currently all of these are optional (any of them can be NULL). - - /* When you call Growl_SetDelegate(newDelegate), it will call - * oldDelegate->release(oldDelegate), and then it will call - * newDelegate->retain(newDelegate), and the return value from retain - * is what will be set as the delegate. - * (This means that this member works like CFRetain and -[NSObject retain].) - * This member is optional (it can be NULL). - * For a delegate allocated with malloc, this member would be - * NULL. - * @result A delegate to which GrowlApplicationBridge holds a reference. - */ - void *(*retain)(void *); - /* When you call Growl_SetDelegate(newDelegate), it will call - * oldDelegate->release(oldDelegate), and then it will call - * newDelegate->retain(newDelegate), and the return value from retain - * is what will be set as the delegate. - * (This means that this member works like CFRelease and - * -[NSObject release].) - * This member is optional (it can be NULL). - * For a delegate allocated with malloc, this member might be - * free(3). - */ - void (*release)(void *); - - /* Informs the delegate that Growl (specifically, the GrowlHelperApp) was - * launched successfully (or was already running). The application can - * take actions with the knowledge that Growl is installed and functional. - */ - void (*growlIsReady)(void); - - /* Informs the delegate that a Growl notification was clicked. It is only - * sent for notifications sent with a non-NULL clickContext, - * so if you want to receive a message when a notification is clicked, - * clickContext must not be NULL when calling - * Growl_PostNotification or - * Growl_NotifyWithTitleDescriptionNameIconPriorityStickyClickContext. - */ - void (*growlNotificationWasClicked)(CFPropertyListRef clickContext); - - /* Informs the delegate that a Growl notification timed out. It is only - * sent for notifications sent with a non-NULL clickContext, - * so if you want to receive a message when a notification is clicked, - * clickContext must not be NULL when calling - * Growl_PostNotification or - * Growl_NotifyWithTitleDescriptionNameIconPriorityStickyClickContext. - */ - void (*growlNotificationTimedOut)(CFPropertyListRef clickContext); -}; - -/*! @struct Growl_Notification - * @abstract Structure describing a Growl notification. - * @discussion XXX - * @field size The size of the notification structure. - * @field name Identifies the notification. - * @field title Short synopsis of the notification. - * @field description Additional text. - * @field iconData An icon for the notification. - * @field priority An indicator of the notification's importance. - * @field reserved Bits reserved for future usage. - * @field isSticky Requests that a notification stay on-screen until dismissed explicitly. - * @field clickContext An identifier to be passed to your click callback when a notification is clicked. - * @field clickCallback A callback to call when the notification is clicked. - */ -struct Growl_Notification { - /* This should be sizeof(struct Growl_Notification). - */ - size_t size; - - /* The notification name distinguishes one type of - * notification from another. The name should be human-readable, as it - * will be displayed in the Growl preference pane. - * - * The name is used in the GROWL_NOTIFICATIONS_ALL and - * GROWL_NOTIFICATIONS_DEFAULT arrays in the registration dictionary, and - * in this member of the Growl_Notification structure. - */ - CFStringRef name; - - /* A notification's title describes the notification briefly. - * It should be easy to read quickly by the user. - */ - CFStringRef title; - - /* The description supplements the title with more - * information. It is usually longer and sometimes involves a list of - * subjects. For example, for a 'Download complete' notification, the - * description might have one filename per line. GrowlMail in Growl 0.6 - * uses a description of '%d new mail(s)' (formatted with the number of - * messages). - */ - CFStringRef description; - - /* The notification icon usually indicates either what - * happened (it may have the same icon as e.g. a toolbar item that - * started the process that led to the notification), or what it happened - * to (e.g. a document icon). - * - * The icon data is optional, so it can be NULL. In that - * case, the application icon is used alone. Not all displays support - * icons. - * - * The data can be in any format supported by NSImage. As of Mac OS X - * 10.3, this includes the .icns, TIFF, JPEG, GIF, PNG, PDF, and PICT form - * ats. - */ - CFDataRef iconData; - - /* Priority is new in Growl 0.6, and is represented as a - * signed integer from -2 to +2. 0 is Normal priority, -2 is Very Low - * priority, and +2 is Very High priority. - * - * Not all displays support priority. If you do not wish to assign a - * priority to your notification, assign 0. - */ - signed int priority; - - /* These bits are not used in Growl 0.6. Set them to 0. - */ - unsigned reserved: 31; - - /* When the sticky bit is clear, in most displays, - * notifications disappear after a certain amount of time. Sticky - * notifications, however, remain on-screen until the user dismisses them - * explicitly, usually by clicking them. - * - * Sticky notifications were introduced in Growl 0.6. Most notifications - * should not be sticky. Not all displays support sticky notifications, - * and the user may choose in Growl's preference pane to force the - * notification to be sticky or non-sticky, in which case the sticky bit - * in the notification will be ignored. - */ - unsigned isSticky: 1; - - /* If this is not NULL, and your click callback - * is not NULL either, this will be passed to the callback - * when your notification is clicked by the user. - * - * Click feedback was introduced in Growl 0.6, and it is optional. Not - * all displays support click feedback. - */ - CFPropertyListRef clickContext; - - /* If this is not NULL, it will be called instead - * of the Growl delegate's click callback when clickContext is - * non-NULL and the notification is clicked on by the user. - * - * Click feedback was introduced in Growl 0.6, and it is optional. Not - * all displays support click feedback. - * - * The per-notification click callback is not yet supported as of Growl - * 0.7. - */ - void (*clickCallback)(CFPropertyListRef clickContext); - - CFStringRef identifier; -}; - -#pragma mark - -#pragma mark Easy initialisers - -/*! @defined InitGrowlDelegate - * @abstract Callable macro. Initializes a Growl delegate structure to defaults. - * @discussion Call with a pointer to a struct Growl_Delegate. All of the - * members of the structure will be set to 0 or NULL, except for - * size (which will be set to sizeof(struct Growl_Delegate)) and - * referenceCount (which will be set to 1). - */ -#define InitGrowlDelegate(delegate) \ - do { \ - if (delegate) { \ - (delegate)->size = sizeof(struct Growl_Delegate); \ - (delegate)->applicationName = NULL; \ - (delegate)->registrationDictionary = NULL; \ - (delegate)->applicationIconData = NULL; \ - (delegate)->growlInstallationWindowTitle = NULL; \ - (delegate)->growlInstallationInformation = NULL; \ - (delegate)->growlUpdateWindowTitle = NULL; \ - (delegate)->growlUpdateInformation = NULL; \ - (delegate)->referenceCount = 1U; \ - (delegate)->retain = NULL; \ - (delegate)->release = NULL; \ - (delegate)->growlIsReady = NULL; \ - (delegate)->growlNotificationWasClicked = NULL; \ - (delegate)->growlNotificationTimedOut = NULL; \ - } \ - } while(0) - -/*! @defined InitGrowlNotification - * @abstract Callable macro. Initializes a Growl notification structure to defaults. - * @discussion Call with a pointer to a struct Growl_Notification. All of - * the members of the structure will be set to 0 or NULL, except - * for size (which will be set to - * sizeof(struct Growl_Notification)). - */ -#define InitGrowlNotification(notification) \ - do { \ - if (notification) { \ - (notification)->size = sizeof(struct Growl_Notification); \ - (notification)->name = NULL; \ - (notification)->title = NULL; \ - (notification)->description = NULL; \ - (notification)->iconData = NULL; \ - (notification)->priority = 0; \ - (notification)->reserved = 0U; \ - (notification)->isSticky = false; \ - (notification)->clickContext = NULL; \ - (notification)->clickCallback = NULL; \ - (notification)->identifier = NULL; \ - } \ - } while(0) - -#pragma mark - -#pragma mark Public API - -// @functiongroup Managing the Growl delegate - -/*! @function Growl_SetDelegate - * @abstract Replaces the current Growl delegate with a new one, or removes - * the Growl delegate. - * @param newDelegate - * @result Returns false and does nothing else if a pointer that was passed in - * is unsatisfactory (because it is non-NULL, but at least one - * required member of it is NULL). Otherwise, sets or unsets the - * delegate and returns true. - * @discussion When newDelegate is non-NULL, sets - * the delegate to newDelegate. When it is NULL, - * the current delegate will be unset, and no delegate will be in place. - * - * It is legal for newDelegate to be the current delegate; - * nothing will happen, and Growl_SetDelegate will return true. It is also - * legal for it to be NULL, as described above; again, it will - * return true. - * - * If there was a delegate in place before the call, Growl_SetDelegate will - * call the old delegate's release member if it was non-NULL. If - * newDelegate is non-NULL, Growl_SetDelegate will - * call newDelegate->retain, and set the delegate to its return - * value. - * - * If you are using Growl-WithInstaller.framework, and an older version of - * Growl is installed on the user's system, the user will automatically be - * prompted to update. - * - * GrowlApplicationBridge currently does not copy this structure, nor does it - * retain any of the CF objects in the structure (it regards the structure as - * a container that retains the objects when they are added and releases them - * when they are removed or the structure is destroyed). Also, - * GrowlApplicationBridge currently does not modify any member of the - * structure, except possibly the referenceCount by calling the retain and - * release members. - */ -GROWL_EXPORT Boolean Growl_SetDelegate(struct Growl_Delegate *newDelegate); - -/*! @function Growl_GetDelegate - * @abstract Returns the current Growl delegate, if any. - * @result The current Growl delegate. - * @discussion Returns the last pointer passed into Growl_SetDelegate, or - * NULL if no such call has been made. - * - * This function follows standard Core Foundation reference-counting rules. - * Because it is a Get function, not a Copy function, it will not retain the - * delegate on your behalf. You are responsible for retaining and releasing - * the delegate as needed. - */ -GROWL_EXPORT struct Growl_Delegate *Growl_GetDelegate(void); - -#pragma mark - - -// @functiongroup Posting Growl notifications - -/*! @function Growl_PostNotification - * @abstract Posts a Growl notification. - * @param notification The notification to post. - * @discussion This is the preferred means for sending a Growl notification. - * The notification name and at least one of the title and description are - * required (all three are preferred). All other parameters may be - * NULL (or 0 or false as appropriate) to accept default values. - * - * If using the Growl-WithInstaller framework, if Growl is not installed the - * user will be prompted to install Growl. - * If the user cancels, this function will have no effect until the next - * application session, at which time when it is called the user will be - * prompted again. The user is also given the option to not be prompted again. - * If the user does choose to install Growl, the requested notification will - * be displayed once Growl is installed and running. - */ -GROWL_EXPORT void Growl_PostNotification(const struct Growl_Notification *notification); - -/*! @function Growl_PostNotificationWithDictionary -* @abstract Notifies using a userInfo dictionary suitable for passing to -* CFDistributedNotificationCenter. -* @param userInfo The dictionary to notify with. -* @discussion Before Growl 0.6, your application would have posted -* notifications using CFDistributedNotificationCenter by creating a userInfo -* dictionary with the notification data. This had the advantage of allowing -* you to add other data to the dictionary for programs besides Growl that -* might be listening. -* -* This function allows you to use such dictionaries without being restricted -* to using CFDistributedNotificationCenter. The keys for this dictionary - * can be found in GrowlDefines.h. -*/ -GROWL_EXPORT void Growl_PostNotificationWithDictionary(CFDictionaryRef userInfo); - -/*! @function Growl_NotifyWithTitleDescriptionNameIconPriorityStickyClickContext - * @abstract Posts a Growl notification using parameter values. - * @param title The title of the notification. - * @param description The description of the notification. - * @param notificationName The name of the notification as listed in the - * registration dictionary. - * @param iconData Data representing a notification icon. Can be NULL. - * @param priority The priority of the notification (-2 to +2, with -2 - * being Very Low and +2 being Very High). - * @param isSticky If true, requests that this notification wait for a - * response from the user. - * @param clickContext An object to pass to the clickCallback, if any. Can - * be NULL, in which case the clickCallback is not called. - * @discussion Creates a temporary Growl_Notification, fills it out with the - * supplied information, and calls Growl_PostNotification on it. - * See struct Growl_Notification and Growl_PostNotification for more - * information. - * - * The icon data can be in any format supported by NSImage. As of Mac OS X - * 10.3, this includes the .icns, TIFF, JPEG, GIF, PNG, PDF, and PICT formats. - */ -GROWL_EXPORT void Growl_NotifyWithTitleDescriptionNameIconPriorityStickyClickContext( - /*inhale*/ - CFStringRef title, - CFStringRef description, - CFStringRef notificationName, - CFDataRef iconData, - signed int priority, - Boolean isSticky, - CFPropertyListRef clickContext); - -#pragma mark - - -// @functiongroup Registering - -/*! @function Growl_RegisterWithDictionary - * @abstract Register your application with Growl without setting a delegate. - * @discussion When you call this function with a dictionary, - * GrowlApplicationBridge registers your application using that dictionary. - * If you pass NULL, GrowlApplicationBridge will ask the delegate - * (if there is one) for a dictionary, and if that doesn't work, it will look - * in your application's bundle for an auto-discoverable plist. - * (XXX refer to more information on that) - * - * If you pass a dictionary to this function, it must include the - * GROWL_APP_NAME key, unless a delegate is set. - * - * This function is mainly an alternative to the delegate system introduced - * with Growl 0.6. Without a delegate, you cannot receive callbacks such as - * growlIsReady (since they are sent to the delegate). You can, - * however, set a delegate after registering without one. - * - * This function was introduced in Growl.framework 0.7. - * @result false if registration failed (e.g. if Growl isn't installed). - */ -GROWL_EXPORT Boolean Growl_RegisterWithDictionary(CFDictionaryRef regDict); - -/*! @function Growl_Reregister - * @abstract Updates your registration with Growl. - * @discussion If your application changes the contents of the - * GROWL_NOTIFICATIONS_ALL key in the registrationDictionary member of the - * Growl delegate, or if it changes the value of that member, or if it - * changes the contents of its auto-discoverable plist, call this function - * to have Growl update its registration information for your application. - * - * Otherwise, this function does not normally need to be called. If you're - * using a delegate, your application will be registered when you set the - * delegate if both the delegate and its registrationDictionary member are - * non-NULL. - * - * This function is now implemented using - * Growl_RegisterWithDictionary. - */ -GROWL_EXPORT void Growl_Reregister(void); - -#pragma mark - - -/*! @function Growl_SetWillRegisterWhenGrowlIsReady - * @abstract Tells GrowlApplicationBridge to register with Growl when Growl - * launches (or not). - * @discussion When Growl has started listening for notifications, it posts a - * GROWL_IS_READY notification on the Distributed Notification - * Center. GrowlApplicationBridge listens for this notification, using it to - * perform various tasks (such as calling your delegate's - * growlIsReady callback, if it has one). If this function is - * called with true, one of those tasks will be to reregister - * with Growl (in the manner of Growl_Reregister). - * - * This attribute is automatically set back to false - * (the default) after every GROWL_IS_READY notification. - * @param flag true if you want GrowlApplicationBridge to register with - * Growl when next it is ready; false if not. - */ -GROWL_EXPORT void Growl_SetWillRegisterWhenGrowlIsReady(Boolean flag); -/*! @function Growl_WillRegisterWhenGrowlIsReady - * @abstract Reports whether GrowlApplicationBridge will register with Growl - * when Growl next launches. - * @result true if GrowlApplicationBridge will register with - * Growl when next it posts GROWL_IS_READY; false if not. - */ -GROWL_EXPORT Boolean Growl_WillRegisterWhenGrowlIsReady(void); - -#pragma mark - - -// @functiongroup Obtaining registration dictionaries - -/*! @function Growl_CopyRegistrationDictionaryFromDelegate - * @abstract Asks the delegate for a registration dictionary. - * @discussion If no delegate is set, or if the delegate's - * registrationDictionary member is NULL, this - * function returns NULL. - * - * This function does not attempt to clean up the dictionary in any way - for - * example, if it is missing the GROWL_APP_NAME key, the result - * will be missing it too. Use - * Growl_CreateRegistrationDictionaryByFillingInDictionary or - * Growl_CreateRegistrationDictionaryByFillingInDictionaryRestrictedToKeys - * to try to fill in missing keys. - * - * This function was introduced in Growl.framework 0.7. - * @result A registration dictionary. - */ -GROWL_EXPORT CFDictionaryRef Growl_CopyRegistrationDictionaryFromDelegate(void); - -/*! @function Growl_CopyRegistrationDictionaryFromBundle - * @abstract Looks in a bundle for a registration dictionary. - * @discussion This function looks in a bundle for an auto-discoverable - * registration dictionary file using CFBundleCopyResourceURL. - * If it finds one, it loads the file using CFPropertyList and - * returns the result. - * - * If you pass NULL as the bundle, the main bundle is examined. - * - * This function does not attempt to clean up the dictionary in any way - for - * example, if it is missing the GROWL_APP_NAME key, the result - * will be missing it too. Use - * Growl_CreateRegistrationDictionaryByFillingInDictionary: or - * Growl_CreateRegistrationDictionaryByFillingInDictionaryRestrictedToKeys - * to try to fill in missing keys. - * - * This function was introduced in Growl.framework 0.7. - * @result A registration dictionary. - */ -GROWL_EXPORT CFDictionaryRef Growl_CopyRegistrationDictionaryFromBundle(CFBundleRef bundle); - -/*! @function Growl_CreateBestRegistrationDictionary - * @abstract Obtains a registration dictionary, filled out to the best of - * GrowlApplicationBridge's knowledge. - * @discussion This function creates a registration dictionary as best - * GrowlApplicationBridge knows how. - * - * First, GrowlApplicationBridge examines the Growl delegate (if there is - * one) and gets the registration dictionary from that. If no such dictionary - * was obtained, GrowlApplicationBridge looks in your application's main - * bundle for an auto-discoverable registration dictionary file. If that - * doesn't exist either, this function returns NULL. - * - * Second, GrowlApplicationBridge calls - * Growl_CreateRegistrationDictionaryByFillingInDictionary with - * whatever dictionary was obtained. The result of that function is the - * result of this function. - * - * GrowlApplicationBridge uses this function when you call - * Growl_SetDelegate, or when you call - * Growl_RegisterWithDictionary with NULL. - * - * This function was introduced in Growl.framework 0.7. - * @result A registration dictionary. - */ -GROWL_EXPORT CFDictionaryRef Growl_CreateBestRegistrationDictionary(void); - -#pragma mark - - -// @functiongroup Filling in registration dictionaries - -/*! @function Growl_CreateRegistrationDictionaryByFillingInDictionary - * @abstract Tries to fill in missing keys in a registration dictionary. - * @param regDict The dictionary to fill in. - * @result The dictionary with the keys filled in. - * @discussion This function examines the passed-in dictionary for missing keys, - * and tries to work out correct values for them. As of 0.7, it uses: - * - * Key Value - * --- ----- - * GROWL_APP_NAME CFBundleExecutableName - * GROWL_APP_ICON The icon of the application. - * GROWL_APP_LOCATION The location of the application. - * GROWL_NOTIFICATIONS_DEFAULT GROWL_NOTIFICATIONS_ALL - * - * Keys are only filled in if missing; if a key is present in the dictionary, - * its value will not be changed. - * - * This function was introduced in Growl.framework 0.7. - */ -GROWL_EXPORT CFDictionaryRef Growl_CreateRegistrationDictionaryByFillingInDictionary(CFDictionaryRef regDict); -/*! @function Growl_CreateRegistrationDictionaryByFillingInDictionaryRestrictedToKeys - * @abstract Tries to fill in missing keys in a registration dictionary. - * @param regDict The dictionary to fill in. - * @param keys The keys to fill in. If NULL, any missing keys are filled in. - * @result The dictionary with the keys filled in. - * @discussion This function examines the passed-in dictionary for missing keys, - * and tries to work out correct values for them. As of 0.7, it uses: - * - * Key Value - * --- ----- - * GROWL_APP_NAME CFBundleExecutableName - * GROWL_APP_ICON The icon of the application. - * GROWL_APP_LOCATION The location of the application. - * GROWL_NOTIFICATIONS_DEFAULT GROWL_NOTIFICATIONS_ALL - * - * Only those keys that are listed in keys will be filled in. - * Other missing keys are ignored. Also, keys are only filled in if missing; - * if a key is present in the dictionary, its value will not be changed. - * - * This function was introduced in Growl.framework 0.7. - */ -GROWL_EXPORT CFDictionaryRef Growl_CreateRegistrationDictionaryByFillingInDictionaryRestrictedToKeys(CFDictionaryRef regDict, CFSetRef keys); - -/*! @brief Tries to fill in missing keys in a notification dictionary. - * @param notifDict The dictionary to fill in. - * @return The dictionary with the keys filled in. This will be a separate instance from \a notifDict. - * @discussion This function examines the \a notifDict for missing keys, and - * tries to get them from the last known registration dictionary. As of 1.1, - * the keys that it will look for are: - * - * \li GROWL_APP_NAME - * \li GROWL_APP_ICON - * - * @since Growl.framework 1.1 - */ -GROWL_EXPORT CFDictionaryRef Growl_CreateNotificationDictionaryByFillingInDictionary(CFDictionaryRef notifDict); - -#pragma mark - - -// @functiongroup Querying Growl's status - -/*! @function Growl_IsInstalled - * @abstract Determines whether the Growl prefpane and its helper app are - * installed. - * @result Returns true if Growl is installed, false otherwise. - */ -GROWL_EXPORT Boolean Growl_IsInstalled(void); - -/*! @function Growl_IsRunning - * @abstract Cycles through the process list to find whether GrowlHelperApp - * is running. - * @result Returns true if Growl is running, false otherwise. - */ -GROWL_EXPORT Boolean Growl_IsRunning(void); - -#pragma mark - - -// @functiongroup Launching Growl - -/*! @typedef GrowlLaunchCallback - * @abstract Callback to notify you that Growl is running. - * @param context The context pointer passed to Growl_LaunchIfInstalled. - * @discussion Growl_LaunchIfInstalled calls this callback function if Growl - * was already running or if it launched Growl successfully. - */ -typedef void (*GrowlLaunchCallback)(void *context); - -/*! @function Growl_LaunchIfInstalled - * @abstract Launches GrowlHelperApp if it is not already running. - * @param callback A callback function which will be called if Growl was successfully - * launched or was already running. Can be NULL. - * @param context The context pointer to pass to the callback. Can be NULL. - * @result Returns true if Growl was successfully launched or was already - * running; returns false and does not call the callback otherwise. - * @discussion Returns true and calls the callback (if the callback is not - * NULL) if the Growl helper app began launching or was already - * running. Returns false and performs no other action if Growl could not be - * launched (e.g. because the Growl preference pane is not properly installed). - * - * If Growl_CreateBestRegistrationDictionary returns - * non-NULL, this function will register with Growl atomically. - * - * The callback should take a single argument; this is to allow applications - * to have context-relevant information passed back. It is perfectly - * acceptable for context to be NULL. The callback itself can be - * NULL if you don't want one. - */ -GROWL_EXPORT Boolean Growl_LaunchIfInstalled(GrowlLaunchCallback callback, void *context); - -#pragma mark - -#pragma mark Constants - -/*! @defined GROWL_PREFPANE_BUNDLE_IDENTIFIER - * @abstract The CFBundleIdentifier of the Growl preference pane bundle. - * @discussion GrowlApplicationBridge uses this to determine whether Growl is - * currently installed, by searching for the Growl preference pane. Your - * application probably does not need to use this macro itself. - */ -#ifndef GROWL_PREFPANE_BUNDLE_IDENTIFIER -#define GROWL_PREFPANE_BUNDLE_IDENTIFIER CFSTR("com.growl.prefpanel") -#endif - -__END_DECLS - -#endif /* _GROWLAPPLICATIONBRIDGE_CARBON_H_ */