165 lines
4.5 KiB
C
165 lines
4.5 KiB
C
//
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// ARM7 processor emulator
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// version 1.6 / 2008-02-16
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// (c) Radoslaw Balcewicz
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//
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#ifndef _ARM7_h_
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#define _ARM7_h_
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#include "cpuintrf.h"
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//--------------------------------------------------------------------------
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// definitions and macros
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/** If defined, will turn on specific behavior emulation, as well as some
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optimizations that are valid only for Dreamcast AICA. */
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#define ARM7_DREAMCAST
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/** Define to enable Thumb support for ARM7. */
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//#define ARM7_THUMB
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// sanity tests
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#ifdef ARM7_DREAMCAST
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#ifdef ARM7_THUMB
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#warning "Dreamcast ARM7 is a -DI type, it doesn't support Thumb mode."
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#endif
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#else
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// #warning "Instructions cycle counts might not be correct."
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#endif
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//--------------------------------------------------------------------------
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//--------------------------------------------------------------------------
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// CPU definitions
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/** Status flags in CPSR register. */
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#define ARM7_CPSR_N (1 << 31)
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#define ARM7_CPSR_Z (1 << 30)
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#define ARM7_CPSR_C (1 << 29)
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#define ARM7_CPSR_V (1 << 28)
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#define ARM7_CPSR_I (1 << 7)
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#define ARM7_CPSR_F (1 << 6)
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#define ARM7_CPSR_T (1 << 5)
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/** CPSR bit mask for current operating mode. */
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#define ARM7_CPSR_M(x) ((x) & 0x1f)
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#define ARM7_CPSR_MX(sr,x) (((sr) & ~0x1f) | ((x) & 0x1f))
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/** Bit combinations for each operating mode. */
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#define ARM7_CPSR_M_usr 0x10
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#define ARM7_CPSR_M_fiq 0x11
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#define ARM7_CPSR_M_irq 0x12
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#define ARM7_CPSR_M_svc 0x13
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#define ARM7_CPSR_M_abt 0x17
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#define ARM7_CPSR_M_und 0x11
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#define ARM7_CPSR_M_sys 0x1f
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/** Control flags for ARM7 core. */
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#define ARM7_FL_FIQ (1 << 0)
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#define ARM7_FL_IRQ (1 << 1)
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/** Operating modes. */
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#define ARM7_MODE_usr 0
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#define ARM7_MODE_fiq 1
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#define ARM7_MODE_irq 2
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#define ARM7_MODE_svc 3
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#define ARM7_MODE_abt 4
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#define ARM7_MODE_und 5
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#define ARM7_MODE_sys 0
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//--------------------------------------------------------------------------
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//--------------------------------------------------------------------------
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// register definitions
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/** ARM7 register type (all are 32-bit). */
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typedef INT32 ARM7_REG;
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enum
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{
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ARM7_R0 = 0, ARM7_R1, ARM7_R2, ARM7_R3, ARM7_R4, ARM7_R5, ARM7_R6, ARM7_R7,
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ARM7_R8, ARM7_R9, ARM7_R10, ARM7_R11, ARM7_R12, ARM7_R13, ARM7_R14, ARM7_R15
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};
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/** R13 is stack pointer. */
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#define ARM7_SP 13
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/** R14 is link/return address. */
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#define ARM7_LR 14
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/** R15 is program counter. */
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#define ARM7_PC 15
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/** CPSR control register. */
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#define ARM7_CPSR 16
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/** SPSR control register. */
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#define ARM7_SPSR 17
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//--------------------------------------------------------------------------
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//--------------------------------------------------------------------------
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/** ARM7 CPU state structure. */
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struct sARM7
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{
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/** All-purpose and control registers (for current mode). */
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ARM7_REG Rx [18];
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/** Banked registers for all operating modes. */
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ARM7_REG Rx_bank [6][10];
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/** FIQ and IRQ interrupt requests. */
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int fiq, irq;
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/** Carry flag for barrel shifter and ALU operations. */
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int carry;
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/** Overflow flag for arithmetic instructions. */
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int overflow;
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/** Emulation control flags. */
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int flagi;
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/** Instruction code. */
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UINT32 kod;
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/** Cycle counter. */
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int cykle;
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};
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//--------------------------------------------------------------------------
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//--------------------------------------------------------------------------
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/** ARM7 state. */
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extern struct sARM7 ARM7;
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//--------------------------------------------------------------------------
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//--------------------------------------------------------------------------
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// public procedures
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/** ARM7 emulator init. */
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void ARM7_Init (void);
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/** Power-ON reset. */
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void ARM7_HardReset (void);
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/** Hardware reset via /RESET line. */
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void ARM7_SoftReset (void);
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/** CPSR update, possibly changing operating mode. */
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void ARM7_SetCPSR (ARM7_REG sr);
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/** Sets FIQ line state. */
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void ARM7_SetFIQ (int stan);
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/** Sets IRQ line state. */
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void ARM7_SetIRQ (int stan);
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/** Tests for pending interrupts, switches to one if possible. */
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void ARM7_CheckIRQ (void);
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/** Single step. */
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void ARM7_Step (void);
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/** Runs emulation for at least n cycles, returns actual amount of cycles
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burned - normal interpreter. */
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int ARM7_Execute (int n);
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//--------------------------------------------------------------------------
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enum
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{
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ARM7_IRQ_LINE=0, ARM7_FIRQ_LINE,
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ARM7_NUM_LINES
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};
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#ifdef ENABLE_DEBUGGER
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extern UINT32 arm7_disasm( char *pBuf, UINT32 pc, UINT32 opcode );
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extern UINT32 thumb_disasm( char *pBuf, UINT32 pc, UINT16 opcode );
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#endif
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#endif
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