110 lines
4.6 KiB
C
110 lines
4.6 KiB
C
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
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* Mupen64plus - cp1.c *
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* Mupen64Plus homepage: http://code.google.com/p/mupen64plus/ *
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* Copyright (C) 2002 Hacktarux *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
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* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
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#include "usf/usf.h"
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#include "new_dynarec/new_dynarec.h"
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#include "usf/usf_internal.h"
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/* Refer to Figure 6-2 on page 155 and explanation on page B-11
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of MIPS R4000 Microprocessor User's Manual (Second Edition)
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by Joe Heinrich.
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*/
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void shuffle_fpr_data(usf_state_t * state, int oldStatus, int newStatus)
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{
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#if defined(M64P_BIG_ENDIAN)
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const int isBigEndian = 1;
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#else
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const int isBigEndian = 0;
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#endif
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if ((newStatus & 0x04000000) != (oldStatus & 0x04000000))
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{
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int i;
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int temp_fgr_32[32];
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// pack or unpack the FGR register data
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if (newStatus & 0x04000000)
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{ // switching into 64-bit mode
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// retrieve 32 FPR values from packed 32-bit FGR registers
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for (i = 0; i < 32; i++)
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{
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temp_fgr_32[i] = *((int *) &state->reg_cop1_fgr_64[i>>1] + ((i & 1) ^ isBigEndian));
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}
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// unpack them into 32 64-bit registers, taking the high 32-bits from their temporary place in the upper 16 FGRs
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for (i = 0; i < 32; i++)
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{
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int high32 = *((int *) &state->reg_cop1_fgr_64[(i>>1)+16] + (i & 1));
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*((int *) &state->reg_cop1_fgr_64[i] + isBigEndian) = temp_fgr_32[i];
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*((int *) &state->reg_cop1_fgr_64[i] + (isBigEndian^1)) = high32;
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}
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}
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else
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{ // switching into 32-bit mode
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// retrieve the high 32 bits from each 64-bit FGR register and store in temp array
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for (i = 0; i < 32; i++)
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{
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temp_fgr_32[i] = *((int *) &state->reg_cop1_fgr_64[i] + (isBigEndian^1));
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}
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// take the low 32 bits from each register and pack them together into 64-bit pairs
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for (i = 0; i < 16; i++)
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{
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unsigned int least32 = *((unsigned int *) &state->reg_cop1_fgr_64[i*2] + isBigEndian);
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unsigned int most32 = *((unsigned int *) &state->reg_cop1_fgr_64[i*2+1] + isBigEndian);
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state->reg_cop1_fgr_64[i] = ((unsigned long long) most32 << 32) | (unsigned long long) least32;
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}
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// store the high bits in the upper 16 FGRs, which wont be accessible in 32-bit mode
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for (i = 0; i < 32; i++)
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{
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*((int *) &state->reg_cop1_fgr_64[(i>>1)+16] + (i & 1)) = temp_fgr_32[i];
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}
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}
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}
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}
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void set_fpr_pointers(usf_state_t * state, int newStatus)
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{
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int i;
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#if defined(M64P_BIG_ENDIAN)
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const int isBigEndian = 1;
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#else
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const int isBigEndian = 0;
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#endif
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// update the FPR register pointers
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if (newStatus & 0x04000000)
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{
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for (i = 0; i < 32; i++)
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{
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state->reg_cop1_double[i] = (double*) &state->reg_cop1_fgr_64[i];
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state->reg_cop1_simple[i] = ((float*) &state->reg_cop1_fgr_64[i]) + isBigEndian;
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}
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}
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else
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{
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for (i = 0; i < 32; i++)
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{
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state->reg_cop1_double[i] = (double*) &state->reg_cop1_fgr_64[i>>1];
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state->reg_cop1_simple[i] = ((float*) &state->reg_cop1_fgr_64[i>>1]) + ((i & 1) ^ isBigEndian);
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}
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}
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}
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