485 lines
20 KiB
Text
485 lines
20 KiB
Text
/*
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* This file is part of libsidplayfp, a SID player engine.
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*
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* Copyright 2011-2013 Leandro Nini <drfiemost@users.sourceforge.net>
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* Copyright 2007-2010 Antti Lankila
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* Copyright 2000 Simon White
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#include "mos6510debug.h"
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#ifdef DEBUG
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#include <cstdio>
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#include <cstdlib>
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#include "mos6510.h"
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#include "sidendian.h"
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#include "opcodes.h"
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namespace libsidplayfp
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{
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void MOS6510Debug::DumpState (event_clock_t time, MOS6510 &cpu)
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{
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fprintf(cpu.m_fdbg, " PC I A X Y SP DR PR NV-BDIZC Instruction (%d)\n", static_cast<int>(time));
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fprintf(cpu.m_fdbg, "%04x ", cpu.instrStartPC);
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fprintf(cpu.m_fdbg, cpu.irqAssertedOnPin ? "t " : "f ");
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fprintf(cpu.m_fdbg, "%02x ", cpu.Register_Accumulator);
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fprintf(cpu.m_fdbg, "%02x ", cpu.Register_X);
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fprintf(cpu.m_fdbg, "%02x ", cpu.Register_Y);
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fprintf(cpu.m_fdbg, "01%02x ", endian_16lo8 (cpu.Register_StackPointer));
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fprintf(cpu.m_fdbg, "%02x ", cpu.cpuRead (0));
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fprintf(cpu.m_fdbg, "%02x ", cpu.cpuRead (1));
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fprintf(cpu.m_fdbg, cpu.flags.N ? "1" : "0");
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fprintf(cpu.m_fdbg, cpu.flags.V ? "1" : "0");
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fprintf(cpu.m_fdbg, "1");
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fprintf(cpu.m_fdbg, cpu.flags.B ? "1" : "0");
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fprintf(cpu.m_fdbg, cpu.flags.D ? "1" : "0");
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fprintf(cpu.m_fdbg, cpu.flags.I ? "1" : "0");
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fprintf(cpu.m_fdbg, cpu.flags.Z ? "1" : "0");
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fprintf(cpu.m_fdbg, cpu.flags.C ? "1" : "0");
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const int opcode = cpu.cpuRead(cpu.instrStartPC);
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fprintf(cpu.m_fdbg, " %02x ", opcode);
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switch(opcode)
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{
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//Accumulator or Implied cpu.Cycle_EffectiveAddressing
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case ASLn: case LSRn: case ROLn: case RORn:
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fprintf(cpu.m_fdbg, " ");
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break;
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//Zero Page Addressing Mode Handler
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case ADCz: case ANDz: case ASLz: case BITz: case CMPz: case CPXz:
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case CPYz: case DCPz: case DECz: case EORz: case INCz: case ISBz:
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case LAXz: case LDAz: case LDXz: case LDYz: case LSRz: case NOPz_:
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case ORAz: case ROLz: case RORz: case SAXz: case SBCz: case SREz:
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case STAz: case STXz: case STYz: case SLOz: case RLAz: case RRAz:
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//ASOz AXSz DCMz INSz LSEz - Optional Opcode Names
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fprintf(cpu.m_fdbg, "%02x ", endian_16lo8 (cpu.instrOperand));
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break;
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//Zero Page with X Offset Addressing Mode Handler
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case ADCzx: case ANDzx: case ASLzx: case CMPzx: case DCPzx: case DECzx:
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case EORzx: case INCzx: case ISBzx: case LDAzx: case LDYzx: case LSRzx:
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case NOPzx_: case ORAzx: case RLAzx: case ROLzx: case RORzx: case RRAzx:
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case SBCzx: case SLOzx: case SREzx: case STAzx: case STYzx:
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//ASOzx DCMzx INSzx LSEzx - Optional Opcode Names
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fprintf(cpu.m_fdbg, "%02x ", endian_16lo8 (cpu.instrOperand));
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break;
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//Zero Page with Y Offset Addressing Mode Handler
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case LDXzy: case STXzy: case SAXzy: case LAXzy:
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//AXSzx - Optional Opcode Names
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fprintf(cpu.m_fdbg, "%02x ", endian_16lo8 (cpu.instrOperand));
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break;
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//Absolute Addressing Mode Handler
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case ADCa: case ANDa: case ASLa: case BITa: case CMPa: case CPXa:
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case CPYa: case DCPa: case DECa: case EORa: case INCa: case ISBa:
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case JMPw: case JSRw: case LAXa: case LDAa: case LDXa: case LDYa:
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case LSRa: case NOPa: case ORAa: case ROLa: case RORa: case SAXa:
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case SBCa: case SLOa: case SREa: case STAa: case STXa: case STYa:
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case RLAa: case RRAa:
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//ASOa AXSa DCMa INSa LSEa - Optional Opcode Names
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fprintf(cpu.m_fdbg, "%02x %02x ", endian_16lo8 (cpu.instrOperand), endian_16hi8 (cpu.instrOperand));
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break;
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//Absolute With X Offset Addresing Mode Handler
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case ADCax: case ANDax: case ASLax: case CMPax: case DCPax: case DECax:
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case EORax: case INCax: case ISBax: case LDAax: case LDYax: case LSRax:
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case NOPax_: case ORAax: case RLAax: case ROLax: case RORax: case RRAax:
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case SBCax: case SHYax: case SLOax: case SREax: case STAax:
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//ASOax DCMax INSax LSEax SAYax - Optional Opcode Names
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fprintf(cpu.m_fdbg, "%02x %02x ", endian_16lo8 (cpu.instrOperand), endian_16hi8 (cpu.instrOperand));
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break;
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//Absolute With Y Offset Addresing Mode Handler
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case ADCay: case ANDay: case CMPay: case DCPay: case EORay: case ISBay:
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case LASay: case LAXay: case LDAay: case LDXay: case ORAay: case RLAay:
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case RRAay: case SBCay: case SHAay: case SHSay: case SHXay: case SLOay:
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case SREay: case STAay:
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//ASOay AXAay DCMay INSax LSEay TASay XASay - Optional Opcode Names
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fprintf(cpu.m_fdbg, "%02x %02x ", endian_16lo8 (cpu.instrOperand), endian_16hi8 (cpu.instrOperand));
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break;
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//Immediate and Relative Addressing Mode Handler
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case ADCb: case ANDb: case ANCb_: case ANEb: case ASRb: case ARRb:
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case BCCr: case BCSr: case BEQr: case BMIr: case BNEr: case BPLr:
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case BVCr: case BVSr:
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case CMPb: case CPXb: case CPYb: case EORb: case LDAb: case LDXb:
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case LDYb: case LXAb: case NOPb_: case ORAb: case SBCb_: case SBXb:
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//OALb ALRb XAAb - Optional Opcode Names
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fprintf(cpu.m_fdbg, "%02x ", endian_16lo8 (cpu.Cycle_Data));
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break;
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//Indirect Addressing Mode Handler
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case JMPi:
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fprintf(cpu.m_fdbg, "%02x %02x ", endian_16lo8 (cpu.instrOperand), endian_16hi8 (cpu.instrOperand));
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break;
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//Indexed with X Preinc Addressing Mode Handler
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case ADCix: case ANDix: case CMPix: case DCPix: case EORix: case ISBix:
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case LAXix: case LDAix: case ORAix: case SAXix: case SBCix: case SLOix:
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case SREix: case STAix: case RLAix: case RRAix:
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//ASOix AXSix DCMix INSix LSEix - Optional Opcode Names
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fprintf(cpu.m_fdbg, "%02x ", endian_16lo8 (cpu.instrOperand));
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break;
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//Indexed with Y Postinc Addressing Mode Handler
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case ADCiy: case ANDiy: case CMPiy: case DCPiy: case EORiy: case ISBiy:
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case LAXiy: case LDAiy: case ORAiy: case RLAiy: case RRAiy: case SBCiy:
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case SHAiy: case SLOiy: case SREiy: case STAiy:
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//AXAiy ASOiy LSEiy DCMiy INSiy - Optional Opcode Names
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fprintf(cpu.m_fdbg, "%02x ", endian_16lo8 (cpu.instrOperand));
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break;
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default:
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fprintf(cpu.m_fdbg, " ");
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break;
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}
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switch(opcode)
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{
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case ADCb: case ADCz: case ADCzx: case ADCa: case ADCax: case ADCay:
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case ADCix: case ADCiy:
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fprintf(cpu.m_fdbg, " ADC"); break;
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case ANCb_:
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fprintf(cpu.m_fdbg, "*ANC"); break;
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case ANDb: case ANDz: case ANDzx: case ANDa: case ANDax: case ANDay:
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case ANDix: case ANDiy:
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fprintf(cpu.m_fdbg, " AND"); break;
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case ANEb: //Also known as XAA
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fprintf(cpu.m_fdbg, "*ANE"); break;
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case ARRb:
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fprintf(cpu.m_fdbg, "*ARR"); break;
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case ASLn: case ASLz: case ASLzx: case ASLa: case ASLax:
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fprintf(cpu.m_fdbg, " ASL"); break;
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case ASRb: //Also known as ALR
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fprintf(cpu.m_fdbg, "*ASR"); break;
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case BCCr:
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fprintf(cpu.m_fdbg, " BCC"); break;
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case BCSr:
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fprintf(cpu.m_fdbg, " BCS"); break;
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case BEQr:
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fprintf(cpu.m_fdbg, " BEQ"); break;
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case BITz: case BITa:
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fprintf(cpu.m_fdbg, " BIT"); break;
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case BMIr:
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fprintf(cpu.m_fdbg, " BMI"); break;
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case BNEr:
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fprintf(cpu.m_fdbg, " BNE"); break;
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case BPLr:
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fprintf(cpu.m_fdbg, " BPL"); break;
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case BRKn:
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fprintf(cpu.m_fdbg, " BRK"); break;
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case BVCr:
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fprintf(cpu.m_fdbg, " BVC"); break;
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case BVSr:
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fprintf(cpu.m_fdbg, " BVS"); break;
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case CLCn:
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fprintf(cpu.m_fdbg, " CLC"); break;
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case CLDn:
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fprintf(cpu.m_fdbg, " CLD"); break;
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case CLIn:
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fprintf(cpu.m_fdbg, " CLI"); break;
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case CLVn:
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fprintf(cpu.m_fdbg, " CLV"); break;
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case CMPb: case CMPz: case CMPzx: case CMPa: case CMPax: case CMPay:
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case CMPix: case CMPiy:
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fprintf(cpu.m_fdbg, " CMP"); break;
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case CPXb: case CPXz: case CPXa:
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fprintf(cpu.m_fdbg, " CPX"); break;
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case CPYb: case CPYz: case CPYa:
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fprintf(cpu.m_fdbg, " CPY"); break;
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case DCPz: case DCPzx: case DCPa: case DCPax: case DCPay: case DCPix:
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case DCPiy: //Also known as DCM
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fprintf(cpu.m_fdbg, "*DCP"); break;
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case DECz: case DECzx: case DECa: case DECax:
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fprintf(cpu.m_fdbg, " DEC"); break;
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case DEXn:
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fprintf(cpu.m_fdbg, " DEX"); break;
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case DEYn:
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fprintf(cpu.m_fdbg, " DEY"); break;
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case EORb: case EORz: case EORzx: case EORa: case EORax: case EORay:
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case EORix: case EORiy:
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fprintf(cpu.m_fdbg, " EOR"); break;
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case INCz: case INCzx: case INCa: case INCax:
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fprintf(cpu.m_fdbg, " INC"); break;
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case INXn:
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fprintf(cpu.m_fdbg, " INX"); break;
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case INYn:
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fprintf(cpu.m_fdbg, " INY"); break;
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case ISBz: case ISBzx: case ISBa: case ISBax: case ISBay: case ISBix:
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case ISBiy: //Also known as INS
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fprintf(cpu.m_fdbg, "*ISB"); break;
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case JMPw: case JMPi:
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fprintf(cpu.m_fdbg, " JMP"); break;
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case JSRw:
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fprintf(cpu.m_fdbg, " JSR"); break;
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case LASay:
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fprintf(cpu.m_fdbg, "*LAS"); break;
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case LAXz: case LAXzy: case LAXa: case LAXay: case LAXix: case LAXiy:
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fprintf(cpu.m_fdbg, "*LAX"); break;
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case LDAb: case LDAz: case LDAzx: case LDAa: case LDAax: case LDAay:
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case LDAix: case LDAiy:
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fprintf(cpu.m_fdbg, " LDA"); break;
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case LDXb: case LDXz: case LDXzy: case LDXa: case LDXay:
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fprintf(cpu.m_fdbg, " LDX"); break;
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case LDYb: case LDYz: case LDYzx: case LDYa: case LDYax:
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fprintf(cpu.m_fdbg, " LDY"); break;
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case LSRz: case LSRzx: case LSRa: case LSRax: case LSRn:
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fprintf(cpu.m_fdbg, " LSR"); break;
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case NOPn_: case NOPb_: case NOPz_: case NOPzx_: case NOPa: case NOPax_:
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if(opcode != NOPn) fprintf(cpu.m_fdbg, "*");
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else fprintf(cpu.m_fdbg, " ");
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fprintf(cpu.m_fdbg, "NOP"); break;
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case LXAb: //Also known as OAL
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fprintf(cpu.m_fdbg, "*LXA"); break;
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case ORAb: case ORAz: case ORAzx: case ORAa: case ORAax: case ORAay:
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case ORAix: case ORAiy:
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fprintf(cpu.m_fdbg, " ORA"); break;
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case PHAn:
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fprintf(cpu.m_fdbg, " PHA"); break;
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case PHPn:
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fprintf(cpu.m_fdbg, " PHP"); break;
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case PLAn:
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fprintf(cpu.m_fdbg, " PLA"); break;
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case PLPn:
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fprintf(cpu.m_fdbg, " PLP"); break;
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case RLAz: case RLAzx: case RLAix: case RLAa: case RLAax: case RLAay:
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case RLAiy:
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fprintf(cpu.m_fdbg, "*RLA"); break;
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case ROLz: case ROLzx: case ROLa: case ROLax: case ROLn:
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fprintf(cpu.m_fdbg, " ROL"); break;
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case RORz: case RORzx: case RORa: case RORax: case RORn:
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fprintf(cpu.m_fdbg, " ROR"); break;
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case RRAa: case RRAax: case RRAay: case RRAz: case RRAzx: case RRAix:
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case RRAiy:
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fprintf(cpu.m_fdbg, "*RRA"); break;
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case RTIn:
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fprintf(cpu.m_fdbg, " RTI"); break;
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case RTSn:
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fprintf(cpu.m_fdbg, " RTS"); break;
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case SAXz: case SAXzy: case SAXa: case SAXix: //Also known as AXS
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fprintf(cpu.m_fdbg, "*SAX"); break;
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case SBCb_:
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if(opcode != SBCb) fprintf(cpu.m_fdbg, "*");
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else fprintf(cpu.m_fdbg, " ");
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fprintf(cpu.m_fdbg, "SBC"); break;
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case SBCz: case SBCzx: case SBCa: case SBCax: case SBCay: case SBCix:
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case SBCiy:
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fprintf(cpu.m_fdbg, " SBC"); break;
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case SBXb:
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fprintf(cpu.m_fdbg, "*SBX"); break;
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case SECn:
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fprintf(cpu.m_fdbg, " SEC"); break;
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case SEDn:
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fprintf(cpu.m_fdbg, " SED"); break;
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case SEIn:
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fprintf(cpu.m_fdbg, " SEI"); break;
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case SHAay: case SHAiy: //Also known as AXA
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fprintf(cpu.m_fdbg, "*SHA"); break;
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case SHSay: //Also known as TAS
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fprintf(cpu.m_fdbg, "*SHS"); break;
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case SHXay: //Also known as XAS
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fprintf(cpu.m_fdbg, "*SHX"); break;
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case SHYax: //Also known as SAY
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fprintf(cpu.m_fdbg, "*SHY"); break;
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case SLOz: case SLOzx: case SLOa: case SLOax: case SLOay: case SLOix:
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case SLOiy: //Also known as ASO
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fprintf(cpu.m_fdbg, "*SLO"); break;
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case SREz: case SREzx: case SREa: case SREax: case SREay: case SREix:
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case SREiy: //Also known as LSE
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fprintf(cpu.m_fdbg, "*SRE"); break;
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case STAz: case STAzx: case STAa: case STAax: case STAay: case STAix:
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case STAiy:
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fprintf(cpu.m_fdbg, " STA"); break;
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case STXz: case STXzy: case STXa:
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fprintf(cpu.m_fdbg, " STX"); break;
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case STYz: case STYzx: case STYa:
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fprintf(cpu.m_fdbg, " STY"); break;
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case TAXn:
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fprintf(cpu.m_fdbg, " TAX"); break;
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case TAYn:
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fprintf(cpu.m_fdbg, " TAY"); break;
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case TSXn:
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fprintf(cpu.m_fdbg, " TSX"); break;
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case TXAn:
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fprintf(cpu.m_fdbg, " TXA"); break;
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case TXSn:
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fprintf(cpu.m_fdbg, " TXS"); break;
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case TYAn:
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fprintf(cpu.m_fdbg, " TYA"); break;
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default:
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fprintf(cpu.m_fdbg, "*HLT"); break;
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}
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switch(opcode)
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{
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//Accumulator or Implied cpu.Cycle_EffectiveAddressing
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case ASLn: case LSRn: case ROLn: case RORn:
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fprintf(cpu.m_fdbg, "n A");
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break;
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//Zero Page Addressing Mode Handler
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case ADCz: case ANDz: case ASLz: case BITz: case CMPz: case CPXz:
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case CPYz: case DCPz: case DECz: case EORz: case INCz: case ISBz:
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case LAXz: case LDAz: case LDXz: case LDYz: case LSRz: case ORAz:
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case ROLz: case RORz: case SBCz: case SREz: case SLOz: case RLAz:
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case RRAz:
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//ASOz AXSz DCMz INSz LSEz - Optional Opcode Names
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fprintf(cpu.m_fdbg, "z %02x {%02x}", endian_16lo8 (cpu.instrOperand), cpu.Cycle_Data);
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break;
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case SAXz: case STAz: case STXz: case STYz:
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#ifdef DEBUG
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case NOPz_:
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#endif
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fprintf(cpu.m_fdbg, "z %02x", endian_16lo8 (cpu.instrOperand));
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break;
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//Zero Page with X Offset Addressing Mode Handler
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case ADCzx: case ANDzx: case ASLzx: case CMPzx: case DCPzx: case DECzx:
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case EORzx: case INCzx: case ISBzx: case LDAzx: case LDYzx: case LSRzx:
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case ORAzx: case RLAzx: case ROLzx: case RORzx: case RRAzx: case SBCzx:
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case SLOzx: case SREzx:
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//ASOzx DCMzx INSzx LSEzx - Optional Opcode Names
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fprintf(cpu.m_fdbg, "zx %02x,X", endian_16lo8 (cpu.instrOperand));
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fprintf(cpu.m_fdbg, " [%04x]{%02x}", cpu.Cycle_EffectiveAddress, cpu.Cycle_Data);
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break;
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case STAzx: case STYzx:
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#ifdef DEBUG
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case NOPzx_:
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#endif
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fprintf(cpu.m_fdbg, "zx %02x,X", endian_16lo8 (cpu.instrOperand));
|
|
fprintf(cpu.m_fdbg, " [%04x]", cpu.Cycle_EffectiveAddress);
|
|
break;
|
|
|
|
//Zero Page with Y Offset Addressing Mode Handler
|
|
case LAXzy: case LDXzy:
|
|
//AXSzx - Optional Opcode Names
|
|
fprintf(cpu.m_fdbg, "zy %02x,Y", endian_16lo8 (cpu.instrOperand));
|
|
fprintf(cpu.m_fdbg, " [%04x]{%02x}", cpu.Cycle_EffectiveAddress, cpu.Cycle_Data);
|
|
break;
|
|
case STXzy: case SAXzy:
|
|
fprintf(cpu.m_fdbg, "zy %02x,Y", endian_16lo8 (cpu.instrOperand));
|
|
fprintf(cpu.m_fdbg, " [%04x]", cpu.Cycle_EffectiveAddress);
|
|
break;
|
|
|
|
//Absolute Addressing Mode Handler
|
|
case ADCa: case ANDa: case ASLa: case BITa: case CMPa: case CPXa:
|
|
case CPYa: case DCPa: case DECa: case EORa: case INCa: case ISBa:
|
|
case LAXa: case LDAa: case LDXa: case LDYa: case LSRa: case ORAa:
|
|
case ROLa: case RORa: case SBCa: case SLOa: case SREa: case RLAa:
|
|
case RRAa:
|
|
//ASOa AXSa DCMa INSa LSEa - Optional Opcode Names
|
|
fprintf(cpu.m_fdbg, "a %04x {%02x}", cpu.instrOperand, cpu.Cycle_Data);
|
|
break;
|
|
case SAXa: case STAa: case STXa: case STYa:
|
|
#ifdef DEBUG
|
|
case NOPa:
|
|
#endif
|
|
fprintf(cpu.m_fdbg, "a %04x", cpu.instrOperand);
|
|
break;
|
|
case JMPw: case JSRw:
|
|
fprintf(cpu.m_fdbg, "w %04x", cpu.instrOperand);
|
|
break;
|
|
|
|
//Absolute With X Offset Addresing Mode Handler
|
|
case ADCax: case ANDax: case ASLax: case CMPax: case DCPax: case DECax:
|
|
case EORax: case INCax: case ISBax: case LDAax: case LDYax: case LSRax:
|
|
case ORAax: case RLAax: case ROLax: case RORax: case RRAax: case SBCax:
|
|
case SLOax: case SREax:
|
|
//ASOax DCMax INSax LSEax SAYax - Optional Opcode Names
|
|
fprintf(cpu.m_fdbg, "ax %04x,X", cpu.instrOperand);
|
|
fprintf(cpu.m_fdbg, " [%04x]{%02x}", cpu.Cycle_EffectiveAddress, cpu.Cycle_Data);
|
|
break;
|
|
case SHYax: case STAax:
|
|
#ifdef DEBUG
|
|
case NOPax_:
|
|
#endif
|
|
fprintf(cpu.m_fdbg, "ax %04x,X", cpu.instrOperand);
|
|
fprintf(cpu.m_fdbg, " [%04x]", cpu.Cycle_EffectiveAddress);
|
|
break;
|
|
|
|
//Absolute With Y Offset Addresing Mode Handler
|
|
case ADCay: case ANDay: case CMPay: case DCPay: case EORay: case ISBay:
|
|
case LASay: case LAXay: case LDAay: case LDXay: case ORAay: case RLAay:
|
|
case RRAay: case SBCay: case SHSay: case SLOay: case SREay:
|
|
//ASOay AXAay DCMay INSax LSEay TASay XASay - Optional Opcode Names
|
|
fprintf(cpu.m_fdbg, "ay %04x,Y", cpu.instrOperand);
|
|
fprintf(cpu.m_fdbg, " [%04x]{%02x}", cpu.Cycle_EffectiveAddress, cpu.Cycle_Data);
|
|
break;
|
|
case SHAay: case SHXay: case STAay:
|
|
fprintf(cpu.m_fdbg, "ay %04x,Y", cpu.instrOperand);
|
|
fprintf(cpu.m_fdbg, " [%04x]", cpu.Cycle_EffectiveAddress);
|
|
break;
|
|
|
|
//Immediate Addressing Mode Handler
|
|
case ADCb: case ANDb: case ANCb_: case ANEb: case ASRb: case ARRb:
|
|
case CMPb: case CPXb: case CPYb: case EORb: case LDAb: case LDXb:
|
|
case LDYb: case LXAb: case ORAb: case SBCb_: case SBXb:
|
|
//OALb ALRb XAAb - Optional Opcode Names
|
|
#ifdef DEBUG
|
|
case NOPb_:
|
|
#endif
|
|
fprintf(cpu.m_fdbg, "b #%02x", endian_16lo8 (cpu.instrOperand));
|
|
break;
|
|
|
|
//Relative Addressing Mode Handler
|
|
case BCCr: case BCSr: case BEQr: case BMIr: case BNEr: case BPLr:
|
|
case BVCr: case BVSr:
|
|
fprintf(cpu.m_fdbg, "r #%02x", endian_16lo8 (cpu.instrOperand));
|
|
fprintf(cpu.m_fdbg, " [%04x]", cpu.Cycle_EffectiveAddress);
|
|
break;
|
|
|
|
//Indirect Addressing Mode Handler
|
|
case JMPi:
|
|
fprintf(cpu.m_fdbg, "i (%04x)", cpu.instrOperand);
|
|
fprintf(cpu.m_fdbg, " [%04x]", cpu.Cycle_EffectiveAddress);
|
|
break;
|
|
|
|
//Indexed with X Preinc Addressing Mode Handler
|
|
case ADCix: case ANDix: case CMPix: case DCPix: case EORix: case ISBix:
|
|
case LAXix: case LDAix: case ORAix: case SBCix: case SLOix: case SREix:
|
|
case RLAix: case RRAix:
|
|
//ASOix AXSix DCMix INSix LSEix - Optional Opcode Names
|
|
fprintf(cpu.m_fdbg, "ix (%02x,X)", endian_16lo8 (cpu.instrOperand));
|
|
fprintf(cpu.m_fdbg, " [%04x]{%02x}", cpu.Cycle_EffectiveAddress, cpu.Cycle_Data);
|
|
break;
|
|
case SAXix: case STAix:
|
|
fprintf(cpu.m_fdbg, "ix (%02x,X)", endian_16lo8 (cpu.instrOperand));
|
|
fprintf(cpu.m_fdbg, " [%04x]", cpu.Cycle_EffectiveAddress);
|
|
break;
|
|
|
|
//Indexed with Y Postinc Addressing Mode Handler
|
|
case ADCiy: case ANDiy: case CMPiy: case DCPiy: case EORiy: case ISBiy:
|
|
case LAXiy: case LDAiy: case ORAiy: case RLAiy: case RRAiy: case SBCiy:
|
|
case SLOiy: case SREiy:
|
|
//AXAiy ASOiy LSEiy DCMiy INSiy - Optional Opcode Names
|
|
fprintf(cpu.m_fdbg, "iy (%02x),Y", endian_16lo8 (cpu.instrOperand));
|
|
fprintf(cpu.m_fdbg, " [%04x]{%02x}", cpu.Cycle_EffectiveAddress, cpu.Cycle_Data);
|
|
break;
|
|
case SHAiy: case STAiy:
|
|
fprintf(cpu.m_fdbg, "iy (%02x),Y", endian_16lo8 (cpu.instrOperand));
|
|
fprintf(cpu.m_fdbg, " [%04x]", cpu.Cycle_EffectiveAddress);
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
fprintf(cpu.m_fdbg, "\n\n");
|
|
fflush(cpu.m_fdbg);
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|