8abbf267e1
The code now requires a variable to be set if Display Lists are to be skipped by setting display processor interrupt as the bypass code is supposed to. Also handle unsupported Ucode by calling the low level RSP emulator instead. Signed-off-by: Christopher Snowhill <kode54@gmail.com>
497 lines
21 KiB
C
497 lines
21 KiB
C
/******************************************************************************\
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* Authors: Iconoclast *
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* Release: 2013.12.11 *
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* License: CC0 Public Domain Dedication *
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* *
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* To the extent possible under law, the author(s) have dedicated all copyright *
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* and related and neighboring rights to this software to the public domain *
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* worldwide. This software is distributed without any warranty. *
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* *
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* You should have received a copy of the CC0 Public Domain Dedication along *
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* with this software. *
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* If not, see <http://creativecommons.org/publicdomain/zero/1.0/>. *
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\******************************************************************************/
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#include "rsp.h"
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#include "su.h"
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#include "vu/vu.h"
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#include "r4300/interupt.h"
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#define FIT_IMEM(PC) (PC & 0xFFF & 0xFFC)
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NOINLINE void run_task(usf_state_t * state)
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{
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register int PC;
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int wrap_count = 0;
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#ifdef SP_EXECUTE_LOG
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int last_PC;
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#endif
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if (CFG_WAIT_FOR_CPU_HOST != 0)
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{
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register int i;
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for (i = 0; i < 32; i++)
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state->MFC0_count[i] = 0;
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}
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PC = FIT_IMEM(state->g_sp.regs2[SP_PC_REG]);
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while ((state->g_sp.regs[SP_STATUS_REG] & 0x00000001) == 0x00000000)
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{
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register uint32_t inst;
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inst = *(uint32_t *)(state->IMEM + FIT_IMEM(PC));
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#ifdef SP_EXECUTE_LOG
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last_PC = PC;
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#endif
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#ifdef EMULATE_STATIC_PC
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PC = (PC + 0x004);
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if ( FIT_IMEM(PC) == 0 && ++wrap_count == 32 )
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{
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message( state, "RSP execution presumably caught in an infinite loop", 3 );
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break;
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}
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EX:
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#endif
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#ifdef SP_EXECUTE_LOG
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step_SP_commands(state, last_PC, inst);
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#endif
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if (inst >> 25 == 0x25) /* is a VU instruction */
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{
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const int opcode = inst % 64; /* inst.R.func */
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const int vd = (inst & 0x000007FF) >> 6; /* inst.R.sa */
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const int vs = (unsigned short)(inst) >> 11; /* inst.R.rd */
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const int vt = (inst >> 16) & 31; /* inst.R.rt */
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const int e = (inst >> 21) & 0xF; /* rs & 0xF */
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COP2_C2[opcode](state, vd, vs, vt, e);
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}
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else
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{
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const int op = inst >> 26;
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const int rs = inst >> 21; /* &= 31 */
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const int rt = (inst >> 16) & 31;
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const int rd = (unsigned short)(inst) >> 11;
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const int element = (inst & 0x000007FF) >> 7;
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const int base = (inst >> 21) & 31;
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#if (0)
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state->SR[0] = 0x00000000; /* already handled on per-instruction basis */
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#endif
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switch (op)
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{
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signed int offset;
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register uint32_t addr;
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case 000: /* SPECIAL */
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switch (inst % 64)
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{
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case 000: /* SLL */
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state->SR[rd] = state->SR[rt] << MASK_SA(inst >> 6);
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state->SR[0] = 0x00000000;
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CONTINUE
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case 002: /* SRL */
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state->SR[rd] = (unsigned)(state->SR[rt]) >> MASK_SA(inst >> 6);
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state->SR[0] = 0x00000000;
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CONTINUE
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case 003: /* SRA */
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state->SR[rd] = (signed)(state->SR[rt]) >> MASK_SA(inst >> 6);
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state->SR[0] = 0x00000000;
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CONTINUE
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case 004: /* SLLV */
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state->SR[rd] = state->SR[rt] << MASK_SA(state->SR[rs]);
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state->SR[0] = 0x00000000;
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CONTINUE
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case 006: /* SRLV */
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state->SR[rd] = (unsigned)(state->SR[rt]) >> MASK_SA(state->SR[rs]);
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state->SR[0] = 0x00000000;
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CONTINUE
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case 007: /* SRAV */
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state->SR[rd] = (signed)(state->SR[rt]) >> MASK_SA(state->SR[rs]);
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state->SR[0] = 0x00000000;
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CONTINUE
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case 011: /* JALR */
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state->SR[rd] = (PC + LINK_OFF) & 0x00000FFC;
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state->SR[0] = 0x00000000;
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case 010: /* JR */
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set_PC(state, state->SR[rs]);
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JUMP
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case 015: /* BREAK */
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state->g_sp.regs[SP_STATUS_REG] |= 0x00000003; /* BROKE | HALT */
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if (state->g_sp.regs[SP_STATUS_REG] & 0x00000040)
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{ /* SP_STATUS_INTR_BREAK */
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state->g_r4300.mi.regs[MI_INTR_REG] |= 0x00000001;
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check_interupt(state);
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}
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CONTINUE
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case 040: /* ADD */
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case 041: /* ADDU */
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state->SR[rd] = state->SR[rs] + state->SR[rt];
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state->SR[0] = 0x00000000; /* needed for Rareware ucodes */
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CONTINUE
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case 042: /* SUB */
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case 043: /* SUBU */
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state->SR[rd] = state->SR[rs] - state->SR[rt];
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state->SR[0] = 0x00000000;
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CONTINUE
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case 044: /* AND */
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state->SR[rd] = state->SR[rs] & state->SR[rt];
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state->SR[0] = 0x00000000; /* needed for Rareware ucodes */
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CONTINUE
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case 045: /* OR */
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state->SR[rd] = state->SR[rs] | state->SR[rt];
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state->SR[0] = 0x00000000;
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CONTINUE
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case 046: /* XOR */
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state->SR[rd] = state->SR[rs] ^ state->SR[rt];
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state->SR[0] = 0x00000000;
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CONTINUE
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case 047: /* NOR */
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state->SR[rd] = ~(state->SR[rs] | state->SR[rt]);
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state->SR[0] = 0x00000000;
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CONTINUE
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case 052: /* SLT */
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state->SR[rd] = ((signed)(state->SR[rs]) < (signed)(state->SR[rt]));
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state->SR[0] = 0x00000000;
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CONTINUE
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case 053: /* SLTU */
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state->SR[rd] = ((unsigned)(state->SR[rs]) < (unsigned)(state->SR[rt]));
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state->SR[0] = 0x00000000;
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CONTINUE
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default:
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res_S(state);
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CONTINUE
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}
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CONTINUE
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case 001: /* REGIMM */
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switch (rt)
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{
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case 020: /* BLTZAL */
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state->SR[31] = (PC + LINK_OFF) & 0x00000FFC;
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case 000: /* BLTZ */
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if (!(state->SR[base] < 0))
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CONTINUE
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set_PC(state, PC + 4*inst + SLOT_OFF);
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JUMP
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case 021: /* BGEZAL */
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state->SR[31] = (PC + LINK_OFF) & 0x00000FFC;
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case 001: /* BGEZ */
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if (!(state->SR[base] >= 0))
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CONTINUE
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set_PC(state, PC + 4*inst + SLOT_OFF);
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JUMP
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default:
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res_S(state);
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CONTINUE
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}
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CONTINUE
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case 003: /* JAL */
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state->SR[31] = (PC + LINK_OFF) & 0x00000FFC;
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case 002: /* J */
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set_PC(state, 4*inst);
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JUMP
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case 004: /* BEQ */
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if (!(state->SR[base] == state->SR[rt]))
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CONTINUE
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set_PC(state, PC + 4*inst + SLOT_OFF);
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JUMP
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case 005: /* BNE */
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if (!(state->SR[base] != state->SR[rt]))
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CONTINUE
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set_PC(state, PC + 4*inst + SLOT_OFF);
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JUMP
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case 006: /* BLEZ */
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if (!((signed)state->SR[base] <= 0x00000000))
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CONTINUE
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set_PC(state, PC + 4*inst + SLOT_OFF);
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JUMP
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case 007: /* BGTZ */
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if (!((signed)state->SR[base] > 0x00000000))
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CONTINUE
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set_PC(state, PC + 4*inst + SLOT_OFF);
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JUMP
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case 010: /* ADDI */
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case 011: /* ADDIU */
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state->SR[rt] = state->SR[base] + (signed short)(inst);
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state->SR[0] = 0x00000000;
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CONTINUE
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case 012: /* SLTI */
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state->SR[rt] = ((signed)(state->SR[base]) < (signed short)(inst));
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state->SR[0] = 0x00000000;
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CONTINUE
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case 013: /* SLTIU */
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state->SR[rt] = ((unsigned)(state->SR[base]) < (unsigned short)(inst));
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state->SR[0] = 0x00000000;
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CONTINUE
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case 014: /* ANDI */
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state->SR[rt] = state->SR[base] & (unsigned short)(inst);
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state->SR[0] = 0x00000000;
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CONTINUE
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case 015: /* ORI */
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state->SR[rt] = state->SR[base] | (unsigned short)(inst);
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state->SR[0] = 0x00000000;
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CONTINUE
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case 016: /* XORI */
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state->SR[rt] = state->SR[base] ^ (unsigned short)(inst);
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state->SR[0] = 0x00000000;
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CONTINUE
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case 017: /* LUI */
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state->SR[rt] = inst << 16;
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state->SR[0] = 0x00000000;
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CONTINUE
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case 020: /* COP0 */
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switch (base)
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{
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case 000: /* MFC0 */
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MFC0(state, rt, rd & 0xF);
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CONTINUE
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case 004: /* MTC0 */
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MTC0[rd & 0xF](state, rt);
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CONTINUE
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default:
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res_S(state);
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CONTINUE
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}
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CONTINUE
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case 022: /* COP2 */
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switch (base)
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{
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case 000: /* MFC2 */
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MFC2(state, rt, rd, element);
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CONTINUE
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case 002: /* CFC2 */
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CFC2(state, rt, rd);
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CONTINUE
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case 004: /* MTC2 */
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MTC2(state, rt, rd, element);
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CONTINUE
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case 006: /* CTC2 */
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CTC2(state, rt, rd);
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CONTINUE
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default:
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res_S(state);
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CONTINUE
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}
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CONTINUE
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case 040: /* LB */
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offset = (signed short)(inst);
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addr = (state->SR[base] + offset) & 0x00000FFF;
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state->SR[rt] = state->DMEM[BES(addr)];
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state->SR[rt] = (signed char)(state->SR[rt]);
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state->SR[0] = 0x00000000;
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CONTINUE
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case 041: /* LH */
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offset = (signed short)(inst);
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addr = (state->SR[base] + offset) & 0x00000FFF;
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if (addr%0x004 == 0x003)
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{
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SR_B(rt, 2) = state->DMEM[addr - BES(0x000)];
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addr = (addr + 0x00000001) & 0x00000FFF;
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SR_B(rt, 3) = state->DMEM[addr + BES(0x000)];
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state->SR[rt] = (signed short)(state->SR[rt]);
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}
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else
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{
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addr -= HES(0x000)*(addr%0x004 - 1);
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state->SR[rt] = *(signed short *)(state->DMEM + addr);
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}
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state->SR[0] = 0x00000000;
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CONTINUE
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case 043: /* LW */
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offset = (signed short)(inst);
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addr = (state->SR[base] + offset) & 0x00000FFF;
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if (addr%0x004 != 0x000)
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ULW(state, rt, addr);
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else
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state->SR[rt] = *(int32_t *)(state->DMEM + addr);
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state->SR[0] = 0x00000000;
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CONTINUE
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case 044: /* LBU */
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offset = (signed short)(inst);
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addr = (state->SR[base] + offset) & 0x00000FFF;
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state->SR[rt] = state->DMEM[BES(addr)];
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state->SR[rt] = (unsigned char)(state->SR[rt]);
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state->SR[0] = 0x00000000;
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CONTINUE
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case 045: /* LHU */
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offset = (signed short)(inst);
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addr = (state->SR[base] + offset) & 0x00000FFF;
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if (addr%0x004 == 0x003)
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{
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SR_B(rt, 2) = state->DMEM[addr - BES(0x000)];
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addr = (addr + 0x00000001) & 0x00000FFF;
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SR_B(rt, 3) = state->DMEM[addr + BES(0x000)];
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state->SR[rt] = (unsigned short)(state->SR[rt]);
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}
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else
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{
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addr -= HES(0x000)*(addr%0x004 - 1);
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state->SR[rt] = *(unsigned short *)(state->DMEM + addr);
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}
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state->SR[0] = 0x00000000;
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CONTINUE
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case 050: /* SB */
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offset = (signed short)(inst);
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addr = (state->SR[base] + offset) & 0x00000FFF;
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state->DMEM[BES(addr)] = (unsigned char)(state->SR[rt]);
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CONTINUE
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case 051: /* SH */
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offset = (signed short)(inst);
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addr = (state->SR[base] + offset) & 0x00000FFF;
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if (addr%0x004 == 0x003)
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{
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state->DMEM[addr - BES(0x000)] = SR_B(rt, 2);
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addr = (addr + 0x00000001) & 0x00000FFF;
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state->DMEM[addr + BES(0x000)] = SR_B(rt, 3);
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CONTINUE
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}
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addr -= HES(0x000)*(addr%0x004 - 1);
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*(short *)(state->DMEM + addr) = (short)(state->SR[rt]);
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CONTINUE
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case 053: /* SW */
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offset = (signed short)(inst);
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addr = (state->SR[base] + offset) & 0x00000FFF;
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if (addr%0x004 != 0x000)
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USW(state, rt, addr);
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else
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*(int32_t *)(state->DMEM + addr) = state->SR[rt];
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CONTINUE
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case 062: /* LWC2 */
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offset = SE(inst, 6);
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switch (rd)
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{
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case 000: /* LBV */
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LBV(state, rt, element, offset, base);
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CONTINUE
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case 001: /* LSV */
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LSV(state, rt, element, offset, base);
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CONTINUE
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case 002: /* LLV */
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LLV(state, rt, element, offset, base);
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CONTINUE
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case 003: /* LDV */
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LDV(state, rt, element, offset, base);
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CONTINUE
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case 004: /* LQV */
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LQV(state, rt, element, offset, base);
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CONTINUE
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case 005: /* LRV */
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LRV(state, rt, element, offset, base);
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CONTINUE
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case 006: /* LPV */
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LPV(state, rt, element, offset, base);
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CONTINUE
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case 007: /* LUV */
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LUV(state, rt, element, offset, base);
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CONTINUE
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case 010: /* LHV */
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LHV(state, rt, element, offset, base);
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CONTINUE
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case 011: /* LFV */
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LFV(state, rt, element, offset, base);
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CONTINUE
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case 013: /* LTV */
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LTV(state, rt, element, offset, base);
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CONTINUE
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default:
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res_S(state);
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CONTINUE
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}
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CONTINUE
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case 072: /* SWC2 */
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offset = SE(inst, 6);
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switch (rd)
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{
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case 000: /* SBV */
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SBV(state, rt, element, offset, base);
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CONTINUE
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case 001: /* SSV */
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SSV(state, rt, element, offset, base);
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CONTINUE
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case 002: /* SLV */
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SLV(state, rt, element, offset, base);
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CONTINUE
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case 003: /* SDV */
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SDV(state, rt, element, offset, base);
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CONTINUE
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case 004: /* SQV */
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SQV(state, rt, element, offset, base);
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CONTINUE
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case 005: /* SRV */
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SRV(state, rt, element, offset, base);
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CONTINUE
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case 006: /* SPV */
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SPV(state, rt, element, offset, base);
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CONTINUE
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case 007: /* SUV */
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SUV(state, rt, element, offset, base);
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CONTINUE
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case 010: /* SHV */
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SHV(state, rt, element, offset, base);
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CONTINUE
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case 011: /* SFV */
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SFV(state, rt, element, offset, base);
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CONTINUE
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case 012: /* SWV */
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SWV(state, rt, element, offset, base);
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CONTINUE
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case 013: /* STV */
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STV(state, rt, element, offset, base);
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CONTINUE
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default:
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res_S(state);
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CONTINUE
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}
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CONTINUE
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default:
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res_S(state);
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CONTINUE
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}
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}
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#ifndef EMULATE_STATIC_PC
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if (state->stage == 2) /* branch phase of scheduler */
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{
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state->stage = 0*stage;
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PC = state->temp_PC & 0x00000FFC;
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state->g_sp.regs2[SP_PC_REG] = state->temp_PC;
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}
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else
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{
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state->stage = 2*state->stage; /* next IW in branch delay slot? */
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PC = (PC + 0x004) & 0xFFC;
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if ( FIT_IMEM(PC) == 0 && ++wrap_count == 32 )
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{
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message( state, "RSP execution presumably caught in an infinite loop", 3 );
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break;
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}
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state->g_sp.regs2[SP_PC_REG] = PC;
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}
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continue;
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#else
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continue;
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BRANCH:
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inst = *(uint32_t *)(state->IMEM + FIT_IMEM(PC));
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#ifdef SP_EXECUTE_LOG
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last_PC = PC;
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#endif
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PC = state->temp_PC & 0x00000FFC;
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goto EX;
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#endif
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}
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state->g_sp.regs2[SP_PC_REG] = FIT_IMEM(PC);
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if (state->g_sp.regs[SP_STATUS_REG] & 0x00000002) /* normal exit, from executing BREAK */
|
|
return;
|
|
else if (state->g_r4300.mi.regs[MI_INTR_REG] & 0x00000001) /* interrupt set by MTC0 to break */
|
|
check_interupt(state);
|
|
else if (CFG_WAIT_FOR_CPU_HOST != 0) /* plugin system hack to re-sync */
|
|
{}
|
|
else if (state->g_sp.regs[SP_SEMAPHORE_REG] != 0x00000000) /* semaphore lock fixes */
|
|
{}
|
|
else /* ??? unknown, possibly external intervention from CPU memory map */
|
|
{
|
|
message(state, "SP_SET_HALT", 3);
|
|
return;
|
|
}
|
|
state->g_sp.regs[SP_STATUS_REG] &= ~0x00000001; /* CPU restarts with the correct SIGs. */
|
|
return;
|
|
}
|