410 lines
8.1 KiB
Modula-2
410 lines
8.1 KiB
Modula-2
/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
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* Mupen64plus - interpreter_special.def *
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* Mupen64Plus homepage: http://code.google.com/p/mupen64plus/ *
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* Copyright (C) 2002 Hacktarux *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
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* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
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DECLARE_INSTRUCTION(NOP)
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{
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ADD_TO_PC(1);
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}
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DECLARE_INSTRUCTION(SLL)
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{
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rrd32 = (unsigned int)(rrt32) << rsa;
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sign_extended(rrd);
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ADD_TO_PC(1);
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}
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DECLARE_INSTRUCTION(SRL)
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{
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rrd32 = (unsigned int)rrt32 >> rsa;
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sign_extended(rrd);
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ADD_TO_PC(1);
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}
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DECLARE_INSTRUCTION(SRA)
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{
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rrd32 = (signed int)rrt32 >> rsa;
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sign_extended(rrd);
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ADD_TO_PC(1);
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}
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DECLARE_INSTRUCTION(SLLV)
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{
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rrd32 = (unsigned int)(rrt32) << (rrs32&0x1F);
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sign_extended(rrd);
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ADD_TO_PC(1);
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}
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DECLARE_INSTRUCTION(SRLV)
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{
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rrd32 = (unsigned int)rrt32 >> (rrs32 & 0x1F);
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sign_extended(rrd);
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ADD_TO_PC(1);
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}
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DECLARE_INSTRUCTION(SRAV)
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{
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rrd32 = (signed int)rrt32 >> (rrs32 & 0x1F);
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sign_extended(rrd);
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ADD_TO_PC(1);
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}
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DECLARE_JUMP(JR, irs32, 1, &state->reg[0], 0, 0)
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DECLARE_JUMP(JALR, irs32, 1, &rrd, 0, 0)
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DECLARE_INSTRUCTION(SYSCALL)
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{
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state->g_cp0_regs[CP0_CAUSE_REG] = 8 << 2;
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exception_general(state);
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}
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DECLARE_INSTRUCTION(SYNC)
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{
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ADD_TO_PC(1);
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}
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DECLARE_INSTRUCTION(MFHI)
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{
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rrd = state->hi;
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ADD_TO_PC(1);
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}
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DECLARE_INSTRUCTION(MTHI)
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{
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state->hi = rrs;
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ADD_TO_PC(1);
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}
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DECLARE_INSTRUCTION(MFLO)
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{
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rrd = state->lo;
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ADD_TO_PC(1);
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}
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DECLARE_INSTRUCTION(MTLO)
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{
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state->lo = rrs;
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ADD_TO_PC(1);
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}
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DECLARE_INSTRUCTION(DSLLV)
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{
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rrd = rrt << (rrs32&0x3F);
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ADD_TO_PC(1);
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}
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DECLARE_INSTRUCTION(DSRLV)
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{
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rrd = (unsigned long long)rrt >> (rrs32 & 0x3F);
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ADD_TO_PC(1);
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}
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DECLARE_INSTRUCTION(DSRAV)
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{
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rrd = (long long)rrt >> (rrs32 & 0x3F);
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ADD_TO_PC(1);
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}
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DECLARE_INSTRUCTION(MULT)
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{
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long long int temp;
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temp = rrs * rrt;
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state->hi = temp >> 32;
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state->lo = temp;
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sign_extended(state->lo);
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ADD_TO_PC(1);
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}
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DECLARE_INSTRUCTION(MULTU)
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{
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unsigned long long int temp;
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temp = (unsigned int)rrs * (unsigned long long)((unsigned int)rrt);
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state->hi = (long long)temp >> 32;
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state->lo = temp;
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sign_extended(state->lo);
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ADD_TO_PC(1);
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}
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DECLARE_INSTRUCTION(DIV)
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{
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if (rrt32)
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{
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state->lo = rrs32 / rrt32;
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state->hi = rrs32 % rrt32;
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sign_extended(state->lo);
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sign_extended(state->hi);
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}
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else DebugMessage(state, M64MSG_ERROR, "DIV: divide by 0");
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ADD_TO_PC(1);
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}
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DECLARE_INSTRUCTION(DIVU)
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{
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if (rrt32)
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{
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state->lo = (unsigned int)rrs32 / (unsigned int)rrt32;
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state->hi = (unsigned int)rrs32 % (unsigned int)rrt32;
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sign_extended(state->lo);
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sign_extended(state->hi);
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}
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else DebugMessage(state, M64MSG_ERROR, "DIVU: divide by 0");
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ADD_TO_PC(1);
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}
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DECLARE_INSTRUCTION(DMULT)
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{
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unsigned long long int op1, op2, op3, op4;
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unsigned long long int result1, result2, result3, result4;
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unsigned long long int temp1, temp2, temp3, temp4;
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int sign = 0;
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if (rrs < 0)
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{
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op2 = -rrs;
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sign = 1 - sign;
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}
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else op2 = rrs;
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if (rrt < 0)
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{
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op4 = -rrt;
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sign = 1 - sign;
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}
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else op4 = rrt;
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op1 = op2 & 0xFFFFFFFF;
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op2 = (op2 >> 32) & 0xFFFFFFFF;
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op3 = op4 & 0xFFFFFFFF;
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op4 = (op4 >> 32) & 0xFFFFFFFF;
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temp1 = op1 * op3;
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temp2 = (temp1 >> 32) + op1 * op4;
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temp3 = op2 * op3;
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temp4 = (temp3 >> 32) + op2 * op4;
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result1 = temp1 & 0xFFFFFFFF;
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result2 = temp2 + (temp3 & 0xFFFFFFFF);
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result3 = (result2 >> 32) + temp4;
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result4 = (result3 >> 32);
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state->lo = result1 | (result2 << 32);
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state->hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
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if (sign)
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{
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state->hi = ~state->hi;
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if (!state->lo) state->hi++;
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else state->lo = ~state->lo + 1;
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}
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ADD_TO_PC(1);
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}
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DECLARE_INSTRUCTION(DMULTU)
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{
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unsigned long long int op1, op2, op3, op4;
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unsigned long long int result1, result2, result3, result4;
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unsigned long long int temp1, temp2, temp3, temp4;
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op1 = rrs & 0xFFFFFFFF;
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op2 = (rrs >> 32) & 0xFFFFFFFF;
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op3 = rrt & 0xFFFFFFFF;
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op4 = (rrt >> 32) & 0xFFFFFFFF;
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temp1 = op1 * op3;
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temp2 = (temp1 >> 32) + op1 * op4;
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temp3 = op2 * op3;
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temp4 = (temp3 >> 32) + op2 * op4;
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result1 = temp1 & 0xFFFFFFFF;
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result2 = temp2 + (temp3 & 0xFFFFFFFF);
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result3 = (result2 >> 32) + temp4;
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result4 = (result3 >> 32);
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state->lo = result1 | (result2 << 32);
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state->hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
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ADD_TO_PC(1);
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}
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DECLARE_INSTRUCTION(DDIV)
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{
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if (rrt)
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{
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state->lo = (long long int)rrs / (long long int)rrt;
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state->hi = (long long int)rrs % (long long int)rrt;
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}
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else DebugMessage(state, M64MSG_ERROR, "DDIV: divide by 0");
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ADD_TO_PC(1);
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}
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DECLARE_INSTRUCTION(DDIVU)
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{
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if (rrt)
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{
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state->lo = (unsigned long long int)rrs / (unsigned long long int)rrt;
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state->hi = (unsigned long long int)rrs % (unsigned long long int)rrt;
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}
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else DebugMessage(state, M64MSG_ERROR, "DDIVU: divide by 0");
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ADD_TO_PC(1);
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}
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DECLARE_INSTRUCTION(ADD)
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{
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rrd32 = rrs32 + rrt32;
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sign_extended(rrd);
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ADD_TO_PC(1);
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}
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DECLARE_INSTRUCTION(ADDU)
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{
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rrd32 = rrs32 + rrt32;
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sign_extended(rrd);
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ADD_TO_PC(1);
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}
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DECLARE_INSTRUCTION(SUB)
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{
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rrd32 = rrs32 - rrt32;
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sign_extended(rrd);
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ADD_TO_PC(1);
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}
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DECLARE_INSTRUCTION(SUBU)
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{
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rrd32 = rrs32 - rrt32;
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sign_extended(rrd);
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ADD_TO_PC(1);
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}
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DECLARE_INSTRUCTION(AND)
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{
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rrd = rrs & rrt;
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ADD_TO_PC(1);
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}
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DECLARE_INSTRUCTION(OR)
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{
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rrd = rrs | rrt;
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ADD_TO_PC(1);
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}
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DECLARE_INSTRUCTION(XOR)
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{
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rrd = rrs ^ rrt;
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ADD_TO_PC(1);
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}
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DECLARE_INSTRUCTION(NOR)
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{
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rrd = ~(rrs | rrt);
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ADD_TO_PC(1);
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}
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DECLARE_INSTRUCTION(SLT)
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{
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if (rrs < rrt) rrd = 1;
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else rrd = 0;
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ADD_TO_PC(1);
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}
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DECLARE_INSTRUCTION(SLTU)
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{
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if ((unsigned long long)rrs < (unsigned long long)rrt)
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rrd = 1;
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else rrd = 0;
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ADD_TO_PC(1);
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}
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DECLARE_INSTRUCTION(DADD)
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{
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rrd = rrs + rrt;
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ADD_TO_PC(1);
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}
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DECLARE_INSTRUCTION(DADDU)
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{
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rrd = rrs + rrt;
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ADD_TO_PC(1);
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}
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DECLARE_INSTRUCTION(DSUB)
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{
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rrd = rrs - rrt;
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ADD_TO_PC(1);
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}
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DECLARE_INSTRUCTION(DSUBU)
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{
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rrd = rrs - rrt;
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ADD_TO_PC(1);
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}
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DECLARE_INSTRUCTION(TEQ)
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{
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if (rrs == rrt)
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{
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DebugMessage(state, M64MSG_ERROR, "trap exception in TEQ");
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state->stop=1;
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}
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ADD_TO_PC(1);
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}
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DECLARE_INSTRUCTION(DSLL)
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{
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rrd = rrt << rsa;
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ADD_TO_PC(1);
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}
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DECLARE_INSTRUCTION(DSRL)
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{
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rrd = (unsigned long long)rrt >> rsa;
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ADD_TO_PC(1);
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}
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DECLARE_INSTRUCTION(DSRA)
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{
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rrd = rrt >> rsa;
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ADD_TO_PC(1);
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}
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DECLARE_INSTRUCTION(DSLL32)
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{
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rrd = rrt << (32+rsa);
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ADD_TO_PC(1);
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}
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DECLARE_INSTRUCTION(DSRL32)
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{
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rrd = (unsigned long long int)rrt >> (32+rsa);
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ADD_TO_PC(1);
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}
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DECLARE_INSTRUCTION(DSRA32)
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{
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rrd = (signed long long int)rrt >> (32+rsa);
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ADD_TO_PC(1);
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}
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/* Idle loop hack from 64th Note */
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DECLARE_INSTRUCTION(BREAK)
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{
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state->g_cp0_regs[CP0_COUNT_REG] = state->next_interupt;
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state->cycle_count = 0;
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ADD_TO_PC(1);
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}
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