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Yes, the SPC control register is supposed to clear its read ports, but SPC files aren't supposed to trigger that with their initial control register

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Chris Moeller 2013-10-26 15:25:06 -07:00
parent fb07d985ea
commit 2b40e87fee
2 changed files with 10 additions and 1 deletions
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2
Frameworks/GME/gme/Spc_Emu.cpp
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@ -376,10 +376,10 @@ blargg_err_t Spc_Emu::start_track_( int track )
smp.regs.s = header.sp; smp.regs.s = header.sp;
memcpy( smp.apuram, ptr, 0x10000 ); memcpy( smp.apuram, ptr, 0x10000 );
memcpy( smp.sfm_last, ptr + 0xF4, 4 );
static const uint8_t regs_to_copy[] = { 0xF1, 0xF2, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC }; static const uint8_t regs_to_copy[] = { 0xF1, 0xF2, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC };
for (auto n : regs_to_copy) smp.op_buswrite( n, ptr[ n ] ); for (auto n : regs_to_copy) smp.op_buswrite( n, ptr[ n ] );
memcpy( smp.sfm_last, ptr + 0xF4, 4 );
ptr += 0x10000; ptr += 0x10000;
smp.dsp.spc_dsp.load( ptr ); smp.dsp.spc_dsp.load( ptr );

9
Frameworks/GME/gme/higan/smp/memory.cpp
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@ -97,6 +97,15 @@ void SMP::op_buswrite(uint16_t addr, uint8_t data) {
case 0xf1: //CONTROL case 0xf1: //CONTROL
status.iplrom_enable = data & 0x80; status.iplrom_enable = data & 0x80;
if (data & 0x10) {
sfm_last[ 0 ] = 0;
sfm_last[ 1 ] = 0;
}
if (data & 0x20) {
sfm_last[ 2 ] = 0;
sfm_last[ 3 ] = 0;
}
//0->1 transistion resets timers //0->1 transistion resets timers
if(timer2.enable == false && (data & 0x04)) { if(timer2.enable == false && (data & 0x04)) {